Re: [U-Boot] [PATCH] sf: set the Uniform Sector to CR3NV instead of CR3V
Hi
On Jun 30, 2016 08:47, "Gong Qianyu" wrote:
>
> From: Mingkai Hu
>
> Set the flash to Uniform Sector Architecture in the non-volatile
> register. After the power cycle, it's also Uniform Sector Architecture.
>
> Signed-off-by: Mingkai Hu
> Signed-off-by: Gong Qianyu
>
> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
> index 64d4e0f..366c362 100644
> --- a/drivers/mtd/spi/spi_flash.c
> +++ b/drivers/mtd/spi/spi_flash.c
> @@ -975,7 +975,7 @@ int spi_flash_decode_fdt(const void *blob, struct
spi_flash *flash)
> static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
> {
> u8 cmd[4];
> - u32 offset = 0x84; /* CR3V register offset */
> + u32 offset = 0x4; /* CR3NV register offset */
> u8 cr3v;
> int ret;
>
I have already tested it and I have in my tree. I don't think that should
be mandatory in general
Michael
> --
> 2.1.0.27.g96db324
>
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[U-Boot] [PATCH] sf: set the Uniform Sector to CR3NV instead of CR3V
From: Mingkai Hu
Set the flash to Uniform Sector Architecture in the non-volatile
register. After the power cycle, it's also Uniform Sector Architecture.
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 64d4e0f..366c362 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -975,7 +975,7 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash
*flash)
static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
{
u8 cmd[4];
- u32 offset = 0x84; /* CR3V register offset */
+ u32 offset = 0x4; /* CR3NV register offset */
u8 cr3v;
int ret;
--
2.1.0.27.g96db324
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[U-Boot] [PATCH] phylib: add support for aquantia AQR106/107 PHY
From: Mingkai Hu
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index f90c2ae..ad12f6d 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -147,6 +147,32 @@ struct phy_driver aqr105_driver = {
.shutdown = &gen10g_shutdown,
};
+struct phy_driver aqr106_driver = {
+ .name = "Aquantia AQR106",
+ .uid = 0x3a1b4d0,
+ .mask = 0xfff0,
+ .features = PHY_10G_FEATURES,
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+ MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
+ .config = &aquantia_config,
+ .startup = &aquantia_startup,
+ .shutdown = &gen10g_shutdown,
+};
+
+struct phy_driver aqr107_driver = {
+ .name = "Aquantia AQR107",
+ .uid = 0x3a1b4e0,
+ .mask = 0xfff0,
+ .features = PHY_10G_FEATURES,
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+ MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
+ .config = &aquantia_config,
+ .startup = &aquantia_startup,
+ .shutdown = &gen10g_shutdown,
+};
+
struct phy_driver aqr405_driver = {
.name = "Aquantia AQR405",
.uid = 0x3a1b4b2,
@@ -165,6 +191,8 @@ int phy_aquantia_init(void)
phy_register(&aq1202_driver);
phy_register(&aq2104_driver);
phy_register(&aqr105_driver);
+ phy_register(&aqr106_driver);
+ phy_register(&aqr107_driver);
phy_register(&aqr405_driver);
return 0;
--
2.1.0.27.g96db324
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Re: [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support
On Fri, Jun 24, 2016 at 11:26 PM, york sun wrote: > On 06/15/2016 12:16 AM, Chen-Yu Tsai wrote: >> Hi, >> >> On Tue, Jun 14, 2016 at 3:01 PM, wrote: >>> From: Hongbo Zhang >>> >>> v5 changes: >>> - Give up fixing the potential bug of PSCI stack overlap with secure text >>> end >>> when there is more CPUs in system. Because I just want to keep this series >>> as >>> simple as it could be: adding basic PSCI v1.0 support and adding more PSCI >>> v1.0 implements of our platform. >>> While too compplicated patches in assembly language won't call for effective >>> reviews, even I think there is potential bug of PSCI stack, let's fix it in >>> sepetated patch later. >> >> I've done some patches fixing the stack allocation issue: >> >> https://github.com/wens/u-boot-sunxi/commits/c-psci-part2 >> >> These patches are ready, but I want to add a secure data section still. >> The data section will be for variables such as target PC, core/cluster >> power status, context ID, etc.. IMHO this is better than putting stuff >> at the top or bottom of the stack, and can also be referenced directly. >> > > > Chenyu, > > I see you have been working on PSCI for ARMv7. Can you review Hongbo's > patch set and give your comment or ack? > > York > > Thank Chenyu for valuable review comments, thank you York. Will send another version soon. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 10/12] libfdt: Add overlay application function
On Wed, Jun 29, 2016 at 07:34:54PM -0700, Frank Rowand wrote:
> On 06/27/16 20:12, David Gibson wrote:
> > On Mon, Jun 27, 2016 at 01:40:00PM +0200, Maxime Ripard wrote:
> >> Hi David,
> >>
> >> On Mon, Jun 27, 2016 at 03:26:07PM +1000, David Gibson wrote:
> +static uint32_t overlay_get_target_phandle(const void *fdto, int
> fragment)
> +{
> +const uint32_t *val;
> +int len;
> +
> +val = fdt_getprop(fdto, fragment, "target", &len);
> +if (!val || (*val == 0x) || (len != sizeof(*val)))
> +return 0;
> >>>
> >>> This doesn't distinguish between a missing property (which may
> >>> indicate a valid overlay using a target-path or some other method)
> >>> and a badly formatted 'target' property, which is definitely an error
> >>> in the overlay.
> >>>
> >>> I think those should be treated differently.
> >>
> >> AFAIK, phandles can have any 32 bits values but 0x. In order
> >> to cover the two cases, we would need to have some error code, but
> >> that doesn't really work with returning a uint32_t.
> >
> > Actually phandles can have any value except 0x *or* 0. So you
> > can use 0 for "couldn't find" and -1 for "badly formatted".
>
> < snip >
>
> Hi David,
>
> I would like to capture this for the specification.
>
> It seems like I could say that a value of 0 in the FDT is not allowed.
>
> Then thinking of what Pantelis is doing with overlays, it seems like a
> value of 0x is allowed in the FDT, but it means not a valid
> phandle, so do not try to de-reference it.
>
> Does that sound good?
That should be ok. Basically both 0 and -1 are invalid phandle
values, so it's up to us if we want to assign them specific "error"
meanings.
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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Re: [U-Boot] [PATCH v5 6/8] ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON
On Tue, Jun 28, 2016 at 12:30 PM, Chen-Yu Tsai wrote: > On Tue, Jun 14, 2016 at 3:01 PM, wrote: >> From: Hongbo Zhang >> >> For the robustness of codes, while powering on a CPU, it is better to check >> if the target CPU is already on or in the process of power on, if yes the >> power on routine shouldn't be executed further and should return with the >> corresponding status immediately. >> >> Signed-off-by: Hongbo Zhang >> --- >> arch/arm/cpu/armv7/ls102xa/psci.S | 29 + >> arch/arm/include/asm/psci.h | 5 + >> 2 files changed, 34 insertions(+) >> >> diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S >> b/arch/arm/cpu/armv7/ls102xa/psci.S >> index a4482e4..0188ade 100644 >> --- a/arch/arm/cpu/armv7/ls102xa/psci.S >> +++ b/arch/arm/cpu/armv7/ls102xa/psci.S >> @@ -66,6 +66,22 @@ psci_cpu_on: >> beq out_psci_cpu_on >> mov r1, r0 >> >> + bl psci_get_cpu_stack_top >> + sub r0, r0, #PSCI_CPU_STATUS_OFFSET >> + ldr r5, [r0] >> + >> + cmp r5, #PSCI_CPU_STATUS_ON >> + moveq r0, #ARM_PSCI_RET_ALREADY_ON >> + beq out_psci_cpu_on >> + >> + cmp r5, #PSCI_CPU_STATUS_ON_PENDING >> + moveq r0, #ARM_PSCI_RET_ON_PENDING >> + beq out_psci_cpu_on >> + >> + mov r5, #PSCI_CPU_STATUS_ON_PENDING >> + str r5, [r0] >> + dsb >> + >> bl psci_cpu_on_common >> >> @ Get DCFG base address >> @@ -123,6 +139,12 @@ holdoff_release: >> rev r6, r6 >> str r6, [r4, #DCFG_CCSR_SCRATCHRW1] >> >> + mov r0, r1 >> + bl psci_get_cpu_stack_top >> + sub r0, r0, #PSCI_CPU_STATUS_OFFSET >> + mov r5, #PSCI_CPU_STATUS_ON >> + str r5, [r0] >> + >> isb >> dsb >> >> @@ -137,6 +159,13 @@ out_psci_cpu_on: >> psci_cpu_off: >> bl psci_cpu_off_common >> >> + bl psci_get_cpu_id >> + bl psci_get_cpu_stack_top >> + sub r0, r0, #PSCI_CPU_STATUS_OFFSET >> + mov r5, #PSCI_CPU_STATUS_OFF >> + str r5, [r0] >> + dsb > > psci_cpu_off_common flushes and disables caches, and turns off SMP. > So the code you're adding might not work as expected? ARM folks > might know more. > Moving this code ahead of psci_cpu_off_common seems better? I just though such a code should be placed as later as it can. > The rest looks good, though I expect them to be pulled out into > common helpers and rewritten in C. :) > > Regards > ChenYu > >> + >> 1: wfi >> b 1b >> >> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h >> index bedcd30..89a1ba5 100644 >> --- a/arch/arm/include/asm/psci.h >> +++ b/arch/arm/include/asm/psci.h >> @@ -67,6 +67,11 @@ >> #define PSCI_PERCPU_STACK_SIZE 0x400 >> #define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4) >> #define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8) >> +#define PSCI_CPU_STATUS_OFFSET (PSCI_PERCPU_STACK_SIZE - 12) >> + >> +#define PSCI_CPU_STATUS_OFF0 >> +#define PSCI_CPU_STATUS_ON 1 >> +#define PSCI_CPU_STATUS_ON_PENDING 2 >> >> #ifndef __ASSEMBLY__ >> int psci_update_dt(void *fdt); >> -- >> 2.1.4 >> ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 10/12] libfdt: Add overlay application function
On 06/27/16 20:12, David Gibson wrote:
> On Mon, Jun 27, 2016 at 01:40:00PM +0200, Maxime Ripard wrote:
>> Hi David,
>>
>> On Mon, Jun 27, 2016 at 03:26:07PM +1000, David Gibson wrote:
+static uint32_t overlay_get_target_phandle(const void *fdto, int fragment)
+{
+ const uint32_t *val;
+ int len;
+
+ val = fdt_getprop(fdto, fragment, "target", &len);
+ if (!val || (*val == 0x) || (len != sizeof(*val)))
+ return 0;
>>>
>>> This doesn't distinguish between a missing property (which may
>>> indicate a valid overlay using a target-path or some other method)
>>> and a badly formatted 'target' property, which is definitely an error
>>> in the overlay.
>>>
>>> I think those should be treated differently.
>>
>> AFAIK, phandles can have any 32 bits values but 0x. In order
>> to cover the two cases, we would need to have some error code, but
>> that doesn't really work with returning a uint32_t.
>
> Actually phandles can have any value except 0x *or* 0. So you
> can use 0 for "couldn't find" and -1 for "badly formatted".
< snip >
Hi David,
I would like to capture this for the specification.
It seems like I could say that a value of 0 in the FDT is not allowed.
Then thinking of what Pantelis is doing with overlays, it seems like a
value of 0x is allowed in the FDT, but it means not a valid
phandle, so do not try to de-reference it.
Does that sound good?
-Frank
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Re: [U-Boot] [PATCH] SPL: sunxi: don't force .BSS into DRAM
On 06/30/2016 02:29 AM, Andre Przywara wrote:
> Probably due to some (ill-founded) fear of a large BSS all sunxi boards
> forced their SPL BSS section into DRAM.
> This only works if there is no usage of a .BSS variable before the DRAM
> is initialised.
> The recent inclusion of tiny-printf breaks this assumption (it has two
> variables in .BSS), so any early printf (printing a number) hangs a board.
I believe you should fix tiny-printf instead, try this patch:
diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 451f4f7..5b9b0dc 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -17,7 +17,7 @@ static char *bf;
static char zs;
/* Current position in sprintf() output string */
-static char *outstr;
+static char *outstr __section(".data");
static void out(char c)
{
> This in particular breaks the (WIP) Pine64 SPL, which at the moment links
> Allwinner's libdram library, trying to print debug information:
> DRAM:DRAM driver version: V1.0
> DRAM Type =
>
> As it turns out the normal BSS size for sunxi is about 256 Bytes, so we
> can happily remove the symbols and the linker script part that was
> forcing the section into DRAM and let the linker naturally put it into
> SRAM.
Except SRAM is limited, which is why bss was in DRAM.
> Tested on BananaPi M1 and Pine64(-SPL), also buildman sunxi was happy.
>
> Thanks to Siarhei for providing helpful hints!
>
> Signed-off-by: Andre Przywara
> ---
>
> (and now with the list in CC: as well) ...
>
> arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 4 +---
> include/configs/sunxi-common.h | 4
> 2 files changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
> b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
> index 53f0cbd..a90404f 100644
> --- a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
> +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
> @@ -16,8 +16,6 @@
> */
> MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
> LENGTH = CONFIG_SPL_MAX_SIZE }
> -MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
> - LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
>
> OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
> OUTPUT_ARCH(arm)
> @@ -54,5 +52,5 @@ SECTIONS
> *(.bss*)
> . = ALIGN(4);
> __bss_end = .;
> - } > .sdram
> + } > .sram
> }
> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
> index 94275a7..e3fe965 100644
> --- a/include/configs/sunxi-common.h
> +++ b/include/configs/sunxi-common.h
> @@ -75,7 +75,6 @@
> * since it needs to fit in with the other values. By also #defining it
> * we get warnings if the Kconfig value mismatches. */
> #define CONFIG_SPL_STACK_R_ADDR 0x2fe0
> -#define CONFIG_SPL_BSS_START_ADDR0x2ff8
> #else
> #define SDRAM_OFFSET(x) 0x4##x
> #define CONFIG_SYS_SDRAM_BASE0x4000
> @@ -86,11 +85,8 @@
> * since it needs to fit in with the other values. By also #defining it
> * we get warnings if the Kconfig value mismatches. */
> #define CONFIG_SPL_STACK_R_ADDR 0x4fe0
> -#define CONFIG_SPL_BSS_START_ADDR0x4ff8
> #endif
>
> -#define CONFIG_SPL_BSS_MAX_SIZE 0x0008 /* 512 KiB */
> -
> #if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
> /*
> * The A80's A1 sram starts at 0x0001 rather then at 0x and is
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2] mmc: increase MMC SDHCI read status timeout
2016-06-30 5:42 GMT+09:00 Steve Rae : > Otherwise, ocassionally see errors like this: > Flashing sparse image at offset 2078720 > Flashing Sparse Image > sdhci_send_command: Timeout for status update! > mmc fail to send stop cmd > write_sparse_image: Write failed, block #2181088 [0] > > This does not affect the actual writing speed, which is controlled by > the default value: > CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT > > It only increases the retries when reading: > SDHCI_INT_STATUS > to avoid the timeout error. > > Signed-off-by: Steve Rae > Reviewed-by: Stefan Roese > Tested-by: Masahiro Yamada Looks good to me. Thanks! -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6] mmc: atmel_sdhci: Convert to the driver model support
Convert the driver to the driver model while retaining the existing
legacy code. This allows the driver to support boards that have
converted to driver model as well as those that have not.
Signed-off-by: Wenyou Yang
Reviewed-by: Simon Glass
---
Changes in v6:
- Remove unnecessary white space.
- Use sdhci_read(), instead of readl().
- Remove the local variables min_clk.
Changes in v5:
- Add Reviewed-by tag.
Changes in v4:
- Update the clk API based on [PATCH] clk: convert API to match
reset/mailbox fstyle (http://patchwork.ozlabs.org/patch/625342/).
- Remove check on dev_get_parent() return.
- Fixed the return value, such as -ENODEV->-EINVAL.
Changes in v3:
- Remove the redundant log print.
Changes in v2:
- Add clock support, include enabling peripheral clock and
generated clock.
- Retain the existing legacy code to support boards which have not
converted to driver model.
drivers/mmc/Kconfig | 10 +
drivers/mmc/atmel_sdhci.c | 97 +++
2 files changed, 107 insertions(+)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index c80efc3..518c624 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -25,6 +25,16 @@ config MSM_SDHCI
SD 3.0 specifications. Both SD and eMMC devices are supported.
Card-detect gpios are not supported.
+config ATMEL_SDHCI
+ bool "Atmel SDHCI controller support"
+ depends on DM_MMC && ARCH_AT91
+ help
+ This enables support for the Atmel SDHCI controller, which supports
+ the embedded MultiMedia Card (e.MMC) Specification V4.51, the SD
+ Memory Card Specification V3.0, and the SDIO V3.0 specification.
+ It is compliant with the SD Host Controller Standard V3.0
+ specification.
+
config ROCKCHIP_DWMMC
bool "Rockchip SD/MMC controller support"
depends on DM_MMC && OF_CONTROL
diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
index 24b68b6..bd33dff 100644
--- a/drivers/mmc/atmel_sdhci.c
+++ b/drivers/mmc/atmel_sdhci.c
@@ -6,12 +6,15 @@
*/
#include
+#include
+#include
#include
#include
#include
#define ATMEL_SDHC_MIN_FREQ40
+#ifndef CONFIG_DM_MMC
int atmel_sdhci_init(void *regbase, u32 id)
{
struct sdhci_host *host;
@@ -38,3 +41,97 @@ int atmel_sdhci_init(void *regbase, u32 id)
return 0;
}
+
+#else
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int atmel_sdhci_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ u32 max_clk;
+ u32 val;
+ u32 clk_base, clk_mul;
+ u32 gck_rate;
+ struct udevice *dev_clk;
+ struct clk clk;
+ int periph, ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return ret;
+
+ periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1);
+ if (periph < 0)
+ return -EINVAL;
+
+ dev_clk = dev_get_parent(clk.dev);
+ ret = clk_request(dev_clk, &clk);
+ if (ret)
+ return ret;
+
+ clk.id = periph;
+ ret = clk_enable(&clk);
+ if (ret)
+ return ret;
+
+ host->name = (char *)dev->name;
+ host->ioaddr = (void *)dev_get_addr(dev);
+
+ host->quirks = 0;
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+ host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+"bus-width", 4);
+
+ val = sdhci_readl(host, SDHCI_CAPABILITIES);
+ clk_base = (val & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+ val = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ clk_mul = (val & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
+ gck_rate = clk_base * 100 * (clk_mul + 1);
+
+ ret = clk_get_by_index(dev, 1, &clk);
+ if (ret)
+ return ret;
+
+ periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1);
+ if (periph < 0)
+ return -EINVAL;
+
+ dev_clk = dev_get_parent(clk.dev);
+ ret = clk_request(dev_clk, &clk);
+ if (ret)
+ return ret;
+
+ clk.id = periph;
+ ret = clk_set_rate(&clk, gck_rate);
+ if (ret)
+ return ret;
+
+ max_clk = clk_get_rate(&clk);
+ if (!max_clk)
+ return -EINVAL;
+
+ add_sdhci(host, max_clk, ATMEL_SDHC_MIN_FREQ);
+
+ upriv->mmc = host->mmc;
+
+ clk_free(&clk);
+
+ return 0;
+}
+
+static const struct udevice_id atmel_sdhci_ids[] = {
+ { .compatible = "atmel,sama5d2-sdhci" },
+ { }
+};
+
+U_BOOT_DRIVER(atmel_sdhci_drv) = {
+ .name = "atmel_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = atmel_sdhci_ids,
+ .probe = atmel_sdhci_probe,
+ .priv_auto_alloc_size = sizeof(struct sdhci_host),
+};
+#endif
--
2
[U-Boot] [PATCH] SPL: sunxi: don't force .BSS into DRAM
Probably due to some (ill-founded) fear of a large BSS all sunxi boards
forced their SPL BSS section into DRAM.
This only works if there is no usage of a .BSS variable before the DRAM
is initialised.
The recent inclusion of tiny-printf breaks this assumption (it has two
variables in .BSS), so any early printf (printing a number) hangs a board.
This in particular breaks the (WIP) Pine64 SPL, which at the moment links
Allwinner's libdram library, trying to print debug information:
DRAM:DRAM driver version: V1.0
DRAM Type =
As it turns out the normal BSS size for sunxi is about 256 Bytes, so we
can happily remove the symbols and the linker script part that was
forcing the section into DRAM and let the linker naturally put it into
SRAM.
Tested on BananaPi M1 and Pine64(-SPL), also buildman sunxi was happy.
Thanks to Siarhei for providing helpful hints!
Signed-off-by: Andre Przywara
---
(and now with the list in CC: as well) ...
arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 4 +---
include/configs/sunxi-common.h | 4
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
index 53f0cbd..a90404f 100644
--- a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
@@ -16,8 +16,6 @@
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
-MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
- LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
@@ -54,5 +52,5 @@ SECTIONS
*(.bss*)
. = ALIGN(4);
__bss_end = .;
- } > .sdram
+ } > .sram
}
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 94275a7..e3fe965 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -75,7 +75,6 @@
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
#define CONFIG_SPL_STACK_R_ADDR0x2fe0
-#define CONFIG_SPL_BSS_START_ADDR 0x2ff8
#else
#define SDRAM_OFFSET(x) 0x4##x
#define CONFIG_SYS_SDRAM_BASE 0x4000
@@ -86,11 +85,8 @@
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
#define CONFIG_SPL_STACK_R_ADDR0x4fe0
-#define CONFIG_SPL_BSS_START_ADDR 0x4ff8
#endif
-#define CONFIG_SPL_BSS_MAX_SIZE0x0008 /* 512 KiB */
-
#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
/*
* The A80's A1 sram starts at 0x0001 rather then at 0x and is
--
2.9.0
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[U-Boot] [PATCH v2] powerpc: MPC8544DS: revert typo in I2C offset value
From: Benjamin Kamath
I2C offset was changed by commit 00f792e0 (added multibus support)
from 0x3100 to 0x3000. This typo leads to error when reading SPD
from DDR DIMMs.
Signed-off-by: Benjamin Kamath
Signed-off-by: York Sun
---
Changes in v2:
Add short summary of commit 00f792e0.
include/configs/MPC8544DS.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index b9d97c1..321f71e 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -209,7 +209,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 40
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES{ {0, 0x69} }
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
--
2.7.4
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Re: [U-Boot] [PATCH] powerpc: MPC8544DS: revert typo in I2C offset value
Hi York,
On Wed, Jun 29, 2016 at 6:27 PM, York Sun wrote:
> From: Benjamin Kamath
>
> I2C offset was changed by commit 00f792e0 from 0x3100 to 0x3000.
Please provide the summary of commit 00f792e0 in parenthesis.
> This typo leads to error when reading SPD from DDR DIMMs.
>
> Signed-off-by: Benjamin Kamath
> Signed-off-by: York Sun
>
> ---
>
> include/configs/MPC8544DS.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
> index b9d97c1..321f71e 100644
> --- a/include/configs/MPC8544DS.h
> +++ b/include/configs/MPC8544DS.h
> @@ -209,7 +209,7 @@ extern unsigned long get_board_sys_clk(unsigned long
> dummy);
> #define CONFIG_SYS_I2C_FSL
> #define CONFIG_SYS_FSL_I2C_SPEED 40
> #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
> +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
> #define CONFIG_SYS_I2C_NOPROBES{ {0, 0x69} }
> #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
>
> --
> 2.7.4
>
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[U-Boot] [PATCH] powerpc: MPC8544DS: revert typo in I2C offset value
From: Benjamin Kamath
I2C offset was changed by commit 00f792e0 from 0x3100 to 0x3000.
This typo leads to error when reading SPD from DDR DIMMs.
Signed-off-by: Benjamin Kamath
Signed-off-by: York Sun
---
include/configs/MPC8544DS.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index b9d97c1..321f71e 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -209,7 +209,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 40
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES{ {0, 0x69} }
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
--
2.7.4
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Re: [U-Boot] U-boot support for FIT image with 64 bit Linux Kernel
Hi,
On 27 June 2016 at 00:07, vinoth eswaran wrote:
> On Sun, Jun 26, 2016 at 4:53 AM, Simon Glass wrote:
>>
>> +Bin
>>
>> Hi,
>>
>> On 23 June 2016 at 08:45, vinoth eswaran wrote:
>> > Hello,
>> >
>> > I am working on an embedded project with the u-boot and Minnowboard
>> > max. With compressed kernel (bzImage) everything works fine, I want to
>> > check the performance with
>> > uncompressed kernel (vmlinux).
>> >
>> > So for creating the image.fit file I followed the instructions as per
>> > the file x86-fit-boot.txt except that I have changed the compression
>> > to none in the image.its file since I want to check the uncompressed
>> > Kernel
>> >
>> > data = /incbin/("./vmlinux.bin");
>> > type = "kernel";
>> > arch = "x86";
>> > os = "linux";
>> > compression = "none";
>>
>> Do you have a load address?
>>
>> >
>> > The bootcmd is "bootcmd=fatload mmc 1:1 0x0200 image.fit ; bootm
>> > 0x0200". Now I am seeing that the
>> > start up hangs after printing the commands starting kernel ... and the
>> > time summary. Do you have any idea why it is happening?
>> >
>> > reading imagefit
>> > 14566018 bytes read in 317 ms (43.8 MiB/s)
>> > ## Loading kernel from FIT Image at 0200 ...
>> >Using 'config@1' configuration
>> >Verifying Hash Integrity ... OK
>> >Trying 'kernel@1' kernel subimage
>> > Description: Vanilla Linux kernel
>> > Created: 2016-06-23 14:22:21 UTC
>> > Type: Kernel Image
>> > Compression: uncompressed
>> > Data Start: 0x02e8
>> > Data Size:14548992 Bytes = 13.9 MiB
>> > Architecture: Intel x86
>> > OS: Linux
>> > Load Address: 0x0100
>> > Entry Point: 0x
>> > Hash algo:sha1
>> > Hash value: 5a0bddcbf1f54ac989fff662fc43fb5fc801ebbc
>> >Verifying Hash Integrity ... sha1+ OK
>> > ## Loading setup from FIT Image at 0200 ...
>> >Using 'config@1' configuration
>> >Trying 'setup@1' setup subimage
>> > Description: Linux setup.bin
>> > Created: 2016-06-23 14:22:21 UTC
>> > Type: x86 setup.bin
>> > Compression: uncompressed
>> > Data Start: 0x02de01d0
>> > Data Size:15708 Bytes = 15.3 KiB
>> > Hash algo:sha1
>> > Hash value: 08ffa163d054b9b0f5b11d4b3db2a16247cee395
>> >Verifying Hash Integrity ... sha1+ OK
>> >Loading setup from 0x02de01d0 to 0x0009
>> >Loading Kernel Image ... OK
>> > Setup at 0x09
>> > Magic signature found
>> > Kernel command line: "quiet"
>> >
>> > Starting kernel ...
>> >
>> >
>> > I have seen in the document that it doesn't support for 64 bit kernel
>> > and the document link given is now not accessible.
>> > http://wiki.osdev.org/64-bit_Higher_Half_Kernel_with_GRUB_2
>>
>> Actually this comment is incorrect:
>>
>> "Note: these instructions assume a 32-bit kernel. U-Boot does not currently
>> support booting a 64-bit kernel as it has no way of going into 64-bit mode on
>> x86."
>>
>> U-Boot supports this. But you need to use x86_64 as the image type
>> instead of x86.
>>
>> Are you booting with a 32- or 64-bit kernel?
>>
>> Perhaps try without the 'qiuet'?
>>
>
> Thanks for reply, your information helped me. But I would like to
> request to sort this message when using x86_64 as architecture type in
> the mkimage. The following debug message when creating the FIT image
> guided me in the wrong path for the past few days, as I thought x86_64
> is not supported and I need to use x86. With arch=x86_64 while
> creating FIT/uImage,
>
>Invalid CPU Type - valid names are: alpha, arm, x86, ia64, m68k,
> microblaze, mips, mips64, nios2, powerpc, ppc, s390, sh, sparc,
> sparc64, blackfin, avr32
> Architecture: Unknown Architecture
>
> Also the image type used for setup.bin. With image type= x86_setup
>
> Invalid Image Type - valid names are: filesystem, firmware,
> flat_dt, imximage, kernel, kwbimage, multi, omapimage, ramdisk,
> script, standalone, flat_dt, kwbimage, imximage, ublimage
>
> Many Thanks:)
>
> Now with x86_64 as arch type I could run the system again. I should
> have ignored the message and tested initially, but also confusions
> with Load and entry addresses let me to stay blank.
I've found various infidelities with mkimage errors - I'll send a
series to improve things.
Regards,
Simon
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Re: [U-Boot] [PATCH 3/5] mmc: exynos_dw_mmc: add the error control for checking index
On 29 June 2016 at 03:46, Jaehoon Chung wrote: > PERIPH_ID_SDMMC4(131) is not continous value with PERIPH_ID_SDMMC0(75). > If there is no 'index' property in fdt, then dev_index should be > assigned to dev_id(Peripheral ID). > At this time, dev_index should be "56". It means Exynos SoC has "56" > numbers of DWMMC IP. To prevent this behavior, it needs to check the > maximum device index. > > Signed-off-by: Jaehoon Chung > --- > drivers/mmc/exynos_dw_mmc.c | 5 + > 1 file changed, 5 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] mmc: exynos_dw_mmc: use the 4bit bus-width by default
On 29 June 2016 at 03:46, Jaehoon Chung wrote: > If there is not "samsung,bus-width" property, use the 4bit buswidth by > default. > Almost all Exnyos SoCs support at least 4bit buswidth. > > Signed-off-by: Jaehoon Chung > --- > drivers/mmc/exynos_dw_mmc.c | 8 ++-- > 1 file changed, 2 insertions(+), 6 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/5] mmc: exynos_dw_mmc: clean the unused and unnecessary codes
On 29 June 2016 at 03:46, Jaehoon Chung wrote: > Clean the unused and unnecessary codse. > This patch is one of them for preparing to use DM. > Because it's easy to maintain and combine DM after cleaning codes. > > Signed-off-by: Jaehoon Chung > --- > drivers/mmc/exynos_dw_mmc.c | 31 +-- > 1 file changed, 9 insertions(+), 22 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/5] mmc: exynos_dw_mmc: remove #ifdef for OF_CONTROL
On 29 June 2016 at 03:46, Jaehoon Chung wrote: > Removed #ifdef for OF_CONTROL. > It might use 'OF_CONTROL' by default. > > Signed-off-by: Jaehoon Chung > --- > drivers/mmc/exynos_dw_mmc.c | 2 -- > 1 file changed, 2 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] mmc: exynos_dw_mmc: remove the unused function
On 29 June 2016 at 03:46, Jaehoon Chung wrote: > This function have maintained for supporting Non-FDT. > Now, Almost all SoC are changed to fdt style. > So there are no that this function is called anywhere. > > Signed-off-by: Jaehoon Chung > --- > arch/arm/mach-exynos/include/mach/dwmmc.h | 1 - > drivers/mmc/exynos_dw_mmc.c | 36 > --- > 2 files changed, 37 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1] dm: usb: Prevent NULL hub in usb_device_info()
Hi Bernhard,
On 29 June 2016 at 01:43, Bernhard Nortmann wrote:
> This patch modifies the usb_device_info() function to enumerate
> active USB hubs by iterating UCLASS_USB_HUB directly.
>
> The previous code used UCLASS_USB nodes instead and retrieved
> their first child node, expecting it to be a hub. However, it
> did not protect against retrieving (and dereferencing) a NULL
> pointer this way.
>
> Depending on the available USB hardware, this might happen easily.
> For example the USB controller on sun7i-a20 has top-level OHCI
> nodes that won't have any children as long as no USB1-only
> peripheral is attached. ("usb tree" will only show EHCI nodes.)
>
> The failure can also be demonstrated with U-Boot's sandbox
> architecture, by simply enabling the inactive "usb_2" node in
> test.dts. This creates a similar situation, where the existing
> usb_device_info() implementation would crash (segfault) when
> issuing a "usb info" command.
>
> Signed-off-by: Bernhard Nortmann
>
> ---
>
> cmd/usb.c | 15 +--
> 1 file changed, 5 insertions(+), 10 deletions(-)
Reviewed-by: Simon Glass
My only concern is whether this changes the ordering (since the
devices' devnum is printed out). But the existing ordering may not be
any better anyway, and if we had a problem we could sort it before
outputting the info, so it seems OK to me.
Thanks for fixing the bug.
- Simon
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[U-Boot] [PATCH v4] mtd: fix compiler warnings
- add missing declaration
- update debug output format specifiers
Signed-off-by: Steve Rae
---
the checkpatch warning:
warning: cmd/mtdparts.c,1494: quoted string split across lines
is for the existing code; it is not introduced with this change...
Changes in v4:
pulled this change out of the "iproc" series, as it had nothing to do with
"iproc"
Changes in v3:
none
Changes in v2:
none
cmd/mtdparts.c | 4 ++--
include/linux/mtd/mtd.h | 5 +
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index 44b2c3a..ea97415 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -1491,7 +1491,7 @@ static int spread_partitions(void)
part = list_entry(pentry, struct part_info, link);
debug("spread_partitions: device = %s%d, partition %d ="
- " (%s) 0x%08x@0x%08x\n",
+ " (%s) 0x%08llx@0x%08llx\n",
MTD_DEV_TYPE(dev->id->type), dev->id->num,
part_num, part->name, part->size,
part->offset);
@@ -2009,7 +2009,7 @@ static int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int
argc,
if (!strcmp(&argv[1][3], ".spread")) {
spread_partition(mtd, p, &next_offset);
- debug("increased %s to %d bytes\n", p->name, p->size);
+ debug("increased %s to %llu bytes\n", p->name, p->size);
}
#endif
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index cf20674..779eea0 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -500,5 +500,10 @@ int mtd_arg_off(const char *arg, int *idx, loff_t *off,
loff_t *size,
int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off,
loff_t *size, loff_t *maxsize, int devtype,
uint64_t chipsize);
+
+/* drivers/mtd/mtdcore.c */
+void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset,
+ const uint64_t length, uint64_t *len_incl_bad,
+ int *truncated);
#endif
#endif /* __MTD_MTD_H__ */
--
1.8.5
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Re: [U-Boot] [RFC PATCH v3 2/4] mtd: fix compiler warnings
Hi Scott, On Tue, Jun 28, 2016 at 6:17 PM, Scott Wood wrote: > On Sat, 2016-03-12 at 14:48 -0800, Steve Rae wrote: >> - add missing declaration >> - update debug output format specifiers >> >> Signed-off-by: Steve Rae >> --- >> the checkpatch warning: >> warning: cmd/mtdparts.c,1494: quoted string split across lines >> is for the existing code; it is not introduced with this change... >> >> Changes in v3: None >> Changes in v2: None > > Why is this an RFC patch? It seems like an attempt to fix straightforward > problems, unrelated to the iproc driver. > True - I'll pull it out of this series and send a new patch. >> >> diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h >> index 9da77ec..9c36f02 100644 >> --- a/include/linux/mtd/mtd.h >> +++ b/include/linux/mtd/mtd.h >> @@ -495,5 +495,13 @@ int mtd_arg_off(const char *arg, int *idx, loff_t *off, >> loff_t *size, >> int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, >>loff_t *size, loff_t *maxsize, int devtype, >>uint64_t chipsize); >> + >> +#ifdef CONFIG_CMD_MTDPARTS_SPREAD >> +/* drivers/mtd/mtdcore.c */ >> +void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset, >> + const uint64_t length, uint64_t *len_incl_bad, >> + int *truncated); >> +#endif /* CONFIG_CMD_MTDPARTS_SPREAD */ > > Don't ifdef prototypes. OK - thanks > > -Scott > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] mmc: increase MMC SDHCI read status timeout
Otherwise, ocassionally see errors like this:
Flashing sparse image at offset 2078720
Flashing Sparse Image
sdhci_send_command: Timeout for status update!
mmc fail to send stop cmd
write_sparse_image: Write failed, block #2181088 [0]
This does not affect the actual writing speed, which is controlled by
the default value:
CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT
It only increases the retries when reading:
SDHCI_INT_STATUS
to avoid the timeout error.
Signed-off-by: Steve Rae
Reviewed-by: Stefan Roese
Tested-by: Masahiro Yamada
---
as per the discussion in:
http://lists.denx.de/pipermail/u-boot/2016-June/258966.html
this supercedes:
http://patchwork.ozlabs.org/patch/615994/
Changes in v2:
dropped "CONFIG_" from the #define
dropped "arm:" in the commit message
drivers/mmc/sdhci.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 5c71ab8..604f18d 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -127,6 +127,7 @@ static int sdhci_transfer_data(struct sdhci_host *host,
struct mmc_data *data,
#define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200
#endif
#define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100
+#define SDHCI_READ_STATUS_TIMEOUT 1000
static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
@@ -243,9 +244,9 @@ static int sdhci_send_command(struct mmc *mmc, struct
mmc_cmd *cmd,
if (stat & SDHCI_INT_ERROR)
break;
} while (((stat & mask) != mask) &&
-(get_timer(start) < CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT));
+(get_timer(start) < SDHCI_READ_STATUS_TIMEOUT));
- if (get_timer(start) >= CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT) {
+ if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
return 0;
else {
--
1.8.5
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Re: [U-Boot] [PATCH] arm: mmc: increase MMC SDHCI read status timeout
Hi Masahiro, On Wed, Jun 29, 2016 at 4:52 AM, Masahiro Yamada wrote: > Hi Steve, > > >> @@ -127,6 +127,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, >> struct mmc_data *data, >> #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200 >> #endif >> #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100 >> +#define CONFIG_SDHCI_READ_STATUS_TIMEOUT 1000 >> >> static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, >>struct mmc_data *data) > > > When I see CONFIG_ prefix, I imagine this parameter can be configurable > via Kconfig or board header, > but this is not actually overridden. > that makes sense > Nor do I believe it should be moved to Kconfig, > because I doubt it is a CONFIG. > correct! so maybe the define should be ? : SDHCI_READ_STATUS_TIMEOUT > > Setting such things aside, one important thing is, > this patch fixes my problem. > > > > BTW, why did you add "arm: " to the git subject? > Is this patch related to ARM? > no (sorry) , I don't think so > > > Otherwise, > > Tested-by: Masahiro Yamada > > > -- > Best Regards > Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] imx: ventana: re-enable late board info display
3b1f681131149b5f62602f582a7e60b0185a2a49 caused a regression that removes board info dispaly for Gateworks Ventana boards because it made the invalid assumption that CONFIG_DISPLAY_BOARDINFO_LATE was the same thing as CONFIG_DISPLAY_BOARDINFO. Ventana needs to call show_board_info in late init because we need to have the i2c eeprom based model info. Re-define CONFIG_DISPLAY_BOARDINFO_LATE to allow that to happen. Cc: Peter Robinson Signed-off-by: Tim Harvey --- include/configs/gw_ventana.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 4acfca6..343f3c5 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -33,6 +33,8 @@ #include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h" #undef CONFIG_SPL_EXT_SUPPORT +#undef CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 6/9] spl: fit: add support for post-processing of images
Hi Simon, please see below... On Tue, Jun 28, 2016 at 08:28:07PM -0700, Simon Glass wrote: > On 27 June 2016 at 07:19, Andreas Dannenberg wrote: > > diff --git a/include/image.h b/include/image.h > > index d788c26..93d39e1 100644 > > --- a/include/image.h > > +++ b/include/image.h > > @@ -1173,4 +1173,21 @@ void android_print_contents(const struct > > andr_img_hdr *hdr); > > */ > > int board_fit_config_name_match(const char *name); > > > > +#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS > > +/** > > + * board_fit_image_post_process() - Do any post-process on FIT binary data > > + * > > + * This is used to do any sort of image manipulation, verification, > > decryption > > + * etc. in a platform or board specific way. Obviously, anything done here > > would > > + * need to be comprehended in how the images were prepared before being > > injected > > + * into the FIT creation (i.e. the binary blobs would have been > > pre-processed > > + * before being added to the FIT image). > > + * > > + * @image: pointer to the image start pointer > > + * @size: pointer to the image size > > + * @return no return value (failure should be handled internally) > > + */ > > +void board_fit_image_post_process(void **p_image, size_t *p_size); > > +#endif /* CONFIG_SPL_FIT_IMAGE_POST_PROCESS */ > > We don't need #ifdef in header files - it just makes the code harder > to read, and we'll still get a build error (with correct line number > info) if someone uses it when they should not. You are right that's technically not needed, but rather I was following how other prototypes are defined in that header file (like the ones that get declared when CONFIG_ANDROID_BOOT_IMAGE is defined). For now I'm not planning to re-spin the patch series, but if there is additional feedback I can take care of this one as well. Thanks and Regards, -- Andreas Dannenberg Texas Instruments Inc ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] u-boot on NAND sunxi
Hi, I've been playing a bit with a pcduino3 board (A20), I know mainline u-boot has no R/W support on NAND for these boards and that's not what I'm asking for :-) I've noticed that when I use an sdcard, u-boot+spl initializes the framebuffer and the screen goes on, whereas when I put u-boot.bin (without spl then) on the NAND the screen stays blank. Is there some magic done in the uboot's SPL that the defaut Allwinner's boot0/1 does not do ? The environment variables and uboot's output are identical in both boot processes: U-Boot 2016.03-dirty (Jun 28 2016 - 10:59:14 +0200) Allwinner Technology [...] HDMI connected: Setting up a 1280x1024 hdmi console (overscan 0x0) In:serial Out: vga Err: vga [...] The only difference is that the screen stays blank when uboot is read from the NAND by boot1. In this configuration booting linux (zImage+dtb read from a sdcard) afterwards does not bring the screen on either. Any idea on what's going on ? Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/5] fdt: Drop unused exynos compatible strings
Hi Simon,
On 06/20/2016 08:33 AM, Simon Glass wrote:
> A few drivers have moved to driver model, so we can drop these strings.
>
> Signed-off-by: Simon Glass
CC'd Minkyu.
Acked-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
>
> Changes in v3:
> - Add new patch to drop unused exynos compatible strings
>
> include/fdtdec.h | 3 ---
> lib/fdtdec.c | 3 ---
> 2 files changed, 6 deletions(-)
>
> diff --git a/include/fdtdec.h b/include/fdtdec.h
> index ae30b8a..8ce98a3 100644
> --- a/include/fdtdec.h
> +++ b/include/fdtdec.h
> @@ -141,12 +141,9 @@ enum fdt_compat_id {
> COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */
> COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */
> COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */
> - COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */
> COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */
> - COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
> COMPAT_SAMSUNG_EXYNOS_DWMMC,/* Exynos DWMMC controller */
> COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */
> - COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */
> COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
> COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */
> COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */
> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index 2f54d71..59b75f0 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -46,12 +46,9 @@ static const char * const compat_names[COMPAT_COUNT] = {
> COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
> COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),
> COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
> - COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
> COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
> - COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
> COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"),
> COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
> - COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
> COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686"),
> COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
> COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),
>
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Re: [U-Boot] [PATCH v5] mmc: atmel_sdhci: Convert to the driver model support
Hi Wenyou,
On 06/29/2016 03:45 PM, Wenyou Yang wrote:
> Convert the driver to the driver model while retaining the existing
> legacy code. This allows the driver to support boards that have
> converted to driver model as well as those that have not.
>
> Signed-off-by: Wenyou Yang
> Reviewed-by: Simon Glass
> ---
>
> Changes in v5:
> - Add Reviewed-by tag.
>
> Changes in v4:
> - Update the clk API based on [PATCH] clk: convert API to match
>reset/mailbox fstyle (http://patchwork.ozlabs.org/patch/625342/).
> - Remove check on dev_get_parent() return.
> - Fixed the return value, such as -ENODEV->-EINVAL.
>
> Changes in v3:
> - Remove the redundant log print.
>
> Changes in v2:
> - Add clock support, include enabling peripheral clock and
>generated clock.
> - Retain the existing legacy code to support boards which have not
>converted to driver model.
>
> drivers/mmc/Kconfig | 10 +
> drivers/mmc/atmel_sdhci.c | 99
> +++
> 2 files changed, 109 insertions(+)
>
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index c80efc3..518c624 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -25,6 +25,16 @@ config MSM_SDHCI
>SD 3.0 specifications. Both SD and eMMC devices are supported.
> Card-detect gpios are not supported.
>
> +config ATMEL_SDHCI
> + bool "Atmel SDHCI controller support"
> + depends on DM_MMC && ARCH_AT91
> + help
> + This enables support for the Atmel SDHCI controller, which supports
> + the embedded MultiMedia Card (e.MMC) Specification V4.51, the SD
> + Memory Card Specification V3.0, and the SDIO V3.0 specification.
> + It is compliant with the SD Host Controller Standard V3.0
> + specification.
> +
> config ROCKCHIP_DWMMC
> bool "Rockchip SD/MMC controller support"
> depends on DM_MMC && OF_CONTROL
> diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
> index 24b68b6..a68d192 100644
> --- a/drivers/mmc/atmel_sdhci.c
> +++ b/drivers/mmc/atmel_sdhci.c
> @@ -6,12 +6,16 @@
> */
>
> #include
> +#include
> +#include
> #include
> #include
> #include
>
> #define ATMEL_SDHC_MIN_FREQ 40
>
> +#ifndef CONFIG_DM_MMC
> +
Unnecessary white space.
> int atmel_sdhci_init(void *regbase, u32 id)
> {
> struct sdhci_host *host;
> @@ -38,3 +42,98 @@ int atmel_sdhci_init(void *regbase, u32 id)
>
> return 0;
> }
> +
> +#else
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static int atmel_sdhci_probe(struct udevice *dev)
> +{
> + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
> + struct sdhci_host *host = dev_get_priv(dev);
> + u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ;
> + u32 caps0, caps1;
> + u32 clk_base, clk_mul;
> + u32 gck_rate;
> + struct udevice *dev_clk;
> + struct clk clk;
> + int periph, ret;
> +
> + ret = clk_get_by_index(dev, 0, &clk);
> + if (ret)
> + return ret;
> +
> + periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1);
> + if (periph < 0)
> + return -EINVAL;
> +
> + dev_clk = dev_get_parent(clk.dev);
> + ret = clk_request(dev_clk, &clk);
> + if (ret)
> + return ret;
> +
> + clk.id = periph;
> + ret = clk_enable(&clk);
> + if (ret)
> + return ret;
> +
> + host->name = (char *)dev->name;
> + host->ioaddr = (void *)dev_get_addr(dev);
> +
> + host->quirks = 0;
> + host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
> +
> + host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
> + "bus-width", 4);
> +
> + caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
> + caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
Why don't use sdhci_readl()? There is no reason that use caps0 and caps1
variables.
val = sdhci_readl(host, SDHCI_CAPBILITES);
clk_base = (val & SDHCI_CLOCK_V3_BASE_MASK)
val = sdhci_readl(host, SDHCI_CAPBILITES_1);
clk_mul = (val & SDHCI_CLOCK_MUL...)
gck_rate = clk_base *
Then you can remove one of them. (caps0 or caps1)
> + clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
> + clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
> + gck_rate = clk_base * 100 * (clk_mul + 1);
> +
> + ret = clk_get_by_index(dev, 1, &clk);
> + if (ret)
> + return ret;
> +
> + periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1);
> + if (periph < 0)
> + return -EINVAL;
> +
> + dev_clk = dev_get_parent(clk.dev);
> + ret = clk_request(dev_clk, &clk);
> + if (ret)
> + return ret;
> +
> + clk.id = periph;
> + ret = clk_set_rate(&clk, gck_rate);
> + if (ret)
> + return ret;
> +
> + max_clk = clk_get_rate(&clk);
> + if (!max_clk)
> + return -EINVAL;
> +
> + add_sdhci(h
Re: [U-Boot] [PATCH] arm: mmc: increase MMC SDHCI read status timeout
Hi Steve, > @@ -127,6 +127,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, > struct mmc_data *data, > #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200 > #endif > #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100 > +#define CONFIG_SDHCI_READ_STATUS_TIMEOUT 1000 > > static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, >struct mmc_data *data) When I see CONFIG_ prefix, I imagine this parameter can be configurable via Kconfig or board header, but this is not actually overridden. Nor do I believe it should be moved to Kconfig, because I doubt it is a CONFIG. Setting such things aside, one important thing is, this patch fixes my problem. BTW, why did you add "arm: " to the git subject? Is this patch related to ARM? Otherwise, Tested-by: Masahiro Yamada -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] imximage: differentiate IVT offset for IMX_FIXED_IVT_OFFSET
When IMX_FIXED_IVT_OFFSET defined, use FLASH_OFFSET_STANDARD for different boot medias. This is needed for i.MX7. Signed-off-by: Peng Fan Cc: Stefano Babic --- tools/imximage.h | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tools/imximage.h b/tools/imximage.h index c7b9b5c..531dc7b 100644 --- a/tools/imximage.h +++ b/tools/imximage.h @@ -26,10 +26,17 @@ #define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD #define FLASH_OFFSET_SDFLASH_OFFSET_STANDARD #define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD + +#ifdef CONFIG_IMX_FIXED_IVT_OFFSET +#define FLASH_OFFSET_ONENAND FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_NOR FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_QSPI FLASH_OFFSET_STANDARD +#else #define FLASH_OFFSET_ONENAND 0x100 #define FLASH_OFFSET_NOR 0x1000 -#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD #define FLASH_OFFSET_QSPI 0x1000 +#endif /* Initial Load Region Size */ #define FLASH_LOADSIZE_UNDEFINED 0x -- 2.6.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] imx: kconfig: introduce IMX_FIXED_IVT_OFFSET
Introduce IMX_FIXED_IVT_OFFSET, which means different boot medias use the same IVT offset. To i.MX7, different boot medias' IVT offset is fixed at 0x400. So select IMX_FIXED_IVT_OFFSET for i.MX7D. Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/cpu/armv7/mx7/Kconfig | 1 + arch/arm/imx-common/Kconfig| 7 +++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig index ecfa4a2..6e70394 100644 --- a/arch/arm/cpu/armv7/mx7/Kconfig +++ b/arch/arm/cpu/armv7/mx7/Kconfig @@ -7,6 +7,7 @@ config MX7 config MX7D select ROM_UNIFIED_SECTIONS + select IMX_FIXED_IVT_OFFSET bool choice diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig index 1b7da5a..b248ef3 100644 --- a/arch/arm/imx-common/Kconfig +++ b/arch/arm/imx-common/Kconfig @@ -4,6 +4,13 @@ config IMX_CONFIG config ROM_UNIFIED_SECTIONS bool +config IMX_FIXED_IVT_OFFSET + bool "The IVT offset for different medias fixed or not" + help + The IVT offset for different boot medias are fixed or not. + To i.MX7, the IVT offset for different boot medias are + fixed. + config IMX_RDC bool "i.MX Resource domain controller driver" depends on ARCH_MX6 || ARCH_MX7 -- 2.6.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH v1] usb: spl: fix USB errata for FSL SPL targets
On 06/29/2016 06:12 AM, york sun wrote: > On 06/28/2016 08:53 PM, Sriram Dash wrote: >>> From: york sun >>> On 06/28/2016 12:02 AM, Sriram Dash wrote: > From: Marek Vasut [mailto:ma...@denx.de] On 06/28/2016 01:02 AM, York > Sun wrote: >> Commit 9262367 moved USB errata workaround to a C file but didn't >> build it for SPL targets. >> >> Signed-off-by: York Sun >> CC: Sriram Dash >> CC: Rajesh Bhagat >> >> --- >> Please review this patch. It fixed the compiling errors introduced >> by 9262367. Not sure if this is the way USB errata should be handled. >> >>drivers/Makefile| 7 +++ >>drivers/usb/common/Makefile | 8 ++-- >>include/configs/km/kmp204x-common.h | 1 + >>3 files changed, 14 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/Makefile b/drivers/Makefile index >> 1723958..88774ba 100644 >> --- a/drivers/Makefile >> +++ b/drivers/Makefile >> @@ -39,6 +39,13 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ >>obj-$(CONFIG_SPL_SATA_SUPPORT) += block/ >>obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/ >>obj-$(CONFIG_SPL_MMC_SUPPORT) += block/ >> +ifdef CONFIG_USB_EHCI_FSL >> +CONFIG_SPL_USB_ERRATA = y >> +endif >> +ifdef CONFIG_USB_XHCI_FSL >> +CONFIG_SPL_USB_ERRATA = y >> +endif >> +obj-$(CONFIG_SPL_USB_ERRATA) += usb/common/ > > I really dislike the naming here, I'd say just do > > obj-$(CONFIG_USB_EHCI_FSL) += usb/common/ > obj-$(CONFIG_USB_XHCI_FSL) += usb/common/ >>> >>> Better. >>> > Hello York/Marek, IMO, the build for SPL is failing in PPC as the cmd_errata is not getting the definition of the has_erratum_aNN functions. So, instead of EHCI or XHCI flags, i think we can use CONFIG_CMD_ERRATA for SPL build for the errata applicability. +obj-$(CONFIG_CMD_ERRATA) += usb/common/fsl-errata.o What is your opinion? >>> >>> Sriram, >>> >>> I think it is not a good idea. CONFIG_CMD_ERRATA has nothing to do with USB >>> errata specifically. It means to enable the command "errata", and nothing >>> more. >>> >>> What's broken here is the mechanism to detect if an erratum applies to a >>> particular >>> SoC version. Before your change, the functions were included from the >>> header file. >>> You moved those functions into a C file. That's fine. We need to build this >>> file for >>> both normal image and SPL. I don't think the workarounds are optional, >>> unless USB >>> is not used at all for SPL. >>> >>> I think Marek's comments make sense. >>> 1) obj-$(CONFIG_USB_EHCI_FSL) += usb/common/ >>> obj-$(CONFIG_USB_XHCI_FSL) += usb/common/ >> >> OK. This looks generic also. > > If an SoC has the errata, it should implement the workaround, regardless > if the U-Boot uses USB. Kernel may use it later. So we should treat it > that way. > >> >>> For this to work, we need to fix >>> kmp204x-common.h, which I noticed CONFIG_USB_EHCI_FSL is not defined. Please >>> examine if this macro should be defined at SoC level, instead of board >>> level. >> >> The kmp204x-common does not need to define CONFIG_USB_EHCI_FSL. >> Currently, the board is not using the USB. But, they are using >> CONFIG_CMD_ERRATA. So, instead of having a flag of CONFIG_USB_EHCI_FSL >> in the board specific file, drivers/usb/common/Makefile should include >> fsl-errata.o for the config CONFIG_CMD_ERRATA. What is your opinion? > > I don't agree. CMD_ERRATA is to enable the command to show which erratum > workaround has been implemented. It shouldn't gate if the actual > workaround code runs. Even kmp204x boards doesn't use USB, the > workaround still needs to be implemented, in case kernel uses USB later. > I was suggesting to put a macro in SoC config file if that fits the purpose. > >> >>> 2) Use a proper macro for fsl-dt-fixup.o The entry point is >>> fdt_fixup_dr_usb(), which >>> is only called by >>> ft_board_setup() when CONFIG_OF_BOARD_SETUP is defined. >>> >> >> Yes. You are correct. fdt_fixup_dr_usb is only called when >> CONFIG_OF_BOARD_SETUP >> is defined. So, I guess it will be fine for drivers/usb/common/Makefile >> >> obj-$(CONFIG_USB_EHCI_FSL) += fsl-errata.o >> obj-$(CONFIG_USB_XHCI_FSL) += fsl-errata.o >> obj-$( CONFIG_CMD_ERRATA) += fsl-errata.o This is a NAK >> obj-$(CONFIG_OF_BOARD_SETUP) += fsl-dt-fixup.o This is also a NAK, how the heck can this depend on OF_BOARD_SETUP? >> What is your opinion? > > That looks reasonable. Please test some targets with and without SPL, > powerpc and ARM. > > York > -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/5] mmc: exynos_dw_mmc: use the 4bit bus-width by default
If there is not "samsung,bus-width" property, use the 4bit buswidth by
default.
Almost all Exnyos SoCs support at least 4bit buswidth.
Signed-off-by: Jaehoon Chung
---
drivers/mmc/exynos_dw_mmc.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index cfbe135..ab0df46 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -154,12 +154,8 @@ static int exynos_dwmci_get_config(const void *blob, int
node,
return -EINVAL;
}
- /* Get the bus width from the device node */
- host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
- if (host->buswidth <= 0) {
- printf("DWMMC%d: Can't get bus-width\n", host->dev_index);
- return -EINVAL;
- }
+ /* Get the bus width from the device node (Default is 4bit buswidth) */
+ host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4);
/* Set the base address from the device node */
base = fdtdec_get_addr(blob, node, "reg");
--
1.9.1
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[U-Boot] [PATCH 4/5] mmc: exynos_dw_mmc: clean the unused and unnecessary codes
Clean the unused and unnecessary codse.
This patch is one of them for preparing to use DM.
Because it's easy to maintain and combine DM after cleaning codes.
Signed-off-by: Jaehoon Chung
---
drivers/mmc/exynos_dw_mmc.c | 31 +--
1 file changed, 9 insertions(+), 22 deletions(-)
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 5860023..cfbe135 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -80,11 +80,10 @@ static void exynos_dwmci_board_init(struct dwmci_host *host)
exynos_dwmci_clksel(host);
}
-static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
+static int exynos_dwmci_core_init(struct dwmci_host *host)
{
unsigned int div;
unsigned long freq, sclk;
- struct dwmci_exynos_priv_data *priv = host->priv;
if (host->bus_hz)
freq = host->bus_hz;
@@ -92,10 +91,10 @@ static int exynos_dwmci_core_init(struct dwmci_host *host,
int index)
freq = DWMMC_MAX_FREQ;
/* request mmc clock vlaue of 52MHz. */
- sclk = get_mmc_clk(index);
+ sclk = get_mmc_clk(host->dev_index);
div = DIV_ROUND_UP(sclk, freq);
/* set the clock divisor for mmc */
- set_mmc_clk(index, div);
+ set_mmc_clk(host->dev_index, div);
host->name = "EXYNOS DWMMC";
#ifdef CONFIG_EXYNOS5420
@@ -103,20 +102,12 @@ static int exynos_dwmci_core_init(struct dwmci_host
*host, int index)
#endif
host->board_init = exynos_dwmci_board_init;
- if (!priv->sdr_timing) {
- if (index == 0)
- priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
- else if (index == 2)
- priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
- }
-
host->caps = MMC_MODE_DDR_52MHz;
host->clksel = exynos_dwmci_clksel;
- host->dev_index = index;
host->get_mmc_clk = exynos_dwmci_get_clk;
/* Add the mmc channel to be registered with mmc core */
if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
- printf("DWMMC%d registration failed\n", index);
+ printf("DWMMC%d registration failed\n", host->dev_index);
return -1;
}
return 0;
@@ -126,18 +117,16 @@ static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
static int do_dwmci_init(struct dwmci_host *host)
{
- int index, flag, err;
-
- index = host->dev_index;
+ int flag, err;
flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
err = exynos_pinmux_config(host->dev_id, flag);
if (err) {
- printf("DWMMC%d not configure\n", index);
+ printf("DWMMC%d not configure\n", host->dev_index);
return err;
}
- return exynos_dwmci_core_init(host, index);
+ return exynos_dwmci_core_init(host);
}
static int exynos_dwmci_get_config(const void *blob, int node,
@@ -233,15 +222,13 @@ static int exynos_dwmci_process_node(const void *blob,
int exynos_dwmmc_init(const void *blob)
{
- int compat_id;
int node_list[DWMMC_MAX_CH_NUM];
int boot_dev_node;
int err = 0, count;
- compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC;
-
count = fdtdec_find_aliases_for_id(blob, "mmc",
- compat_id, node_list, DWMMC_MAX_CH_NUM);
+ COMPAT_SAMSUNG_EXYNOS_DWMMC, node_list,
+ DWMMC_MAX_CH_NUM);
/* For DWMMC always set boot device as mmc 0 */
if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) {
--
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[U-Boot] [PATCH 0/5] mmc: exynos_dw_mmc: clean the unnecessary codes
This patch-set is for maintaining more easier than now. Now, exynos_dw_mmc codes are too huge. Some codes can be reused and removed. Basic goal is the using DM. Before applied DM, it needs to clean more. In future, exynos_dw_mmc controller should support DM. Jaehoon Chung (5): mmc: exynos_dw_mmc: remove the unused function mmc: exynos_dw_mmc: remove #ifdef for OF_CONTROL mmc: exynos_dw_mmc: add the error control for checking index mmc: exynos_dw_mmc: clean the unused and unnecessary codes mmc: exynos_dw_mmc: use the 4bit bus-width by default arch/arm/mach-exynos/include/mach/dwmmc.h | 1 - drivers/mmc/exynos_dw_mmc.c | 78 ++- 2 files changed, 14 insertions(+), 65 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5] mmc: exynos_dw_mmc: add the error control for checking index
PERIPH_ID_SDMMC4(131) is not continous value with PERIPH_ID_SDMMC0(75).
If there is no 'index' property in fdt, then dev_index should be
assigned to dev_id(Peripheral ID).
At this time, dev_index should be "56". It means Exynos SoC has "56"
numbers of DWMMC IP. To prevent this behavior, it needs to check the
maximum device index.
Signed-off-by: Jaehoon Chung
---
drivers/mmc/exynos_dw_mmc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 80d17ad..5860023 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -160,6 +160,11 @@ static int exynos_dwmci_get_config(const void *blob, int
node,
if (host->dev_index == host->dev_id)
host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
+ if (host->dev_index > 4) {
+ printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
+ return -EINVAL;
+ }
+
/* Get the bus width from the device node */
host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
if (host->buswidth <= 0) {
--
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[U-Boot] [PATCH 2/5] mmc: exynos_dw_mmc: remove #ifdef for OF_CONTROL
Removed #ifdef for OF_CONTROL. It might use 'OF_CONTROL' by default. Signed-off-by: Jaehoon Chung --- drivers/mmc/exynos_dw_mmc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 2b9b3aa..80d17ad 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -122,7 +122,6 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index) return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM]; static int do_dwmci_init(struct dwmci_host *host) @@ -250,4 +249,3 @@ int exynos_dwmmc_init(const void *blob) return err; } -#endif -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/5] mmc: exynos_dw_mmc: remove the unused function
This function have maintained for supporting Non-FDT.
Now, Almost all SoC are changed to fdt style.
So there are no that this function is called anywhere.
Signed-off-by: Jaehoon Chung
---
arch/arm/mach-exynos/include/mach/dwmmc.h | 1 -
drivers/mmc/exynos_dw_mmc.c | 36 ---
2 files changed, 37 deletions(-)
diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h
b/arch/arm/mach-exynos/include/mach/dwmmc.h
index bd997ad..ab8361f 100644
--- a/arch/arm/mach-exynos/include/mach/dwmmc.h
+++ b/arch/arm/mach-exynos/include/mach/dwmmc.h
@@ -28,4 +28,3 @@
#define DWMCI_DIVRATIO_MASK0x7
int exynos_dwmmc_init(const void *blob);
-int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel);
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 863bbb3..2b9b3aa 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -122,42 +122,6 @@ static int exynos_dwmci_core_init(struct dwmci_host *host,
int index)
return 0;
}
-/*
- * This function adds the mmc channel to be registered with mmc core.
- * index - mmc channel number.
- * regbase - register base address of mmc channel specified in 'index'.
- * bus_width - operating bus width of mmc channel specified in 'index'.
- * clksel -value to be written into CLKSEL register in case of FDT.
- * NULL in case od non-FDT.
- */
-int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
-{
- struct dwmci_host *host = NULL;
- struct dwmci_exynos_priv_data *priv;
-
- host = malloc(sizeof(struct dwmci_host));
- if (!host) {
- error("dwmci_host malloc fail!\n");
- return -ENOMEM;
- }
-
- priv = malloc(sizeof(struct dwmci_exynos_priv_data));
- if (!priv) {
- error("dwmci_exynos_priv_data malloc fail!\n");
- return -ENOMEM;
- }
-
- host->ioaddr = (void *)regbase;
- host->buswidth = bus_width;
-
- if (clksel)
- priv->sdr_timing = clksel;
-
- host->priv = priv;
-
- return exynos_dwmci_core_init(host, index);
-}
-
#if CONFIG_IS_ENABLED(OF_CONTROL)
static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
--
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[U-Boot] [PATCH 03/11] pinctrl: uniphier: remove unneeded pin group nand_cs1
This SoC does not support NAND CS1. This place-holder is no longer
necessary.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index 4ddaddc..7bc0b28 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -25,8 +25,6 @@ static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10,
11, 12, 13, 14,
15, 16, 17};
static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0};
-static const unsigned nand_cs1_pins[] = {};
-static const unsigned nand_cs1_muxvals[] = {};
static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17};
static const unsigned sd_muxvals[] = {3, 3, 3, 3, 3, 3, 3, 3}; /* No SDVOLC */
static const unsigned uart0_pins[] = {54, 55};
@@ -54,7 +52,6 @@ static const struct uniphier_pinctrl_group
uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP(i2c3),
UNIPHIER_PINCTRL_GROUP(i2c4),
UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd), /* SD does not exist for LD11 */
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart1),
--
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[U-Boot] [PATCH 00/11] ARM: uniphier: pinctrl and DT fixes/updates
Masahiro Yamada (11): pinctrl: uniphier: remove wrong pin-mux functions for ProXstream2 pinctrl: uniphier: fix NAND pin-mux setting for PH1-LD11/LD20 pinctrl: uniphier: remove unneeded pin group nand_cs1 ARM: dts: uniphier: sync Device Trees with upstream Linux pinctrl: uniphier: allow to have pinctrl node under syscon node pinctrl: uniphier: split pinctrl driver for PH1-LD11 and PH1-LD20 pinctrl: uniphier: support pin configuration for dedicated pins pinctrl: uniphier: avoid building unneeded pin-mux tables for SPL pinctrl: uniphier: add ethernet pin-mux settings ARM: dts: uniphier: add AIDET nodes ARM: uniphier: add external IRQ settings arch/arm/dts/uniphier-common32.dtsi | 22 - arch/arm/dts/uniphier-ph1-ld11-ref.dts | 13 +-- arch/arm/dts/uniphier-ph1-ld11.dtsi | 50 -- arch/arm/dts/uniphier-ph1-ld20-ref.dts | 10 -- arch/arm/dts/uniphier-ph1-ld20.dtsi | 35 +-- arch/arm/dts/uniphier-ph1-ld4-ref.dts| 10 -- arch/arm/dts/uniphier-ph1-ld4.dtsi | 7 +- arch/arm/dts/uniphier-ph1-ld6b-ref.dts | 10 -- arch/arm/dts/uniphier-ph1-ld6b.dtsi | 4 +- arch/arm/dts/uniphier-ph1-pro4-ace.dts | 10 -- arch/arm/dts/uniphier-ph1-pro4-ref.dts | 10 -- arch/arm/dts/uniphier-ph1-pro4-sanji.dts | 10 -- arch/arm/dts/uniphier-ph1-pro4.dtsi | 7 +- arch/arm/dts/uniphier-ph1-pro5-4kbox.dts | 10 -- arch/arm/dts/uniphier-ph1-pro5.dtsi | 7 +- arch/arm/dts/uniphier-ph1-sld3.dtsi | 5 + arch/arm/dts/uniphier-ph1-sld8-ref.dts | 10 -- arch/arm/dts/uniphier-ph1-sld8.dtsi | 7 +- arch/arm/dts/uniphier-pinctrl.dtsi | 10 ++ arch/arm/dts/uniphier-proxstream2-gentil.dts | 10 -- arch/arm/dts/uniphier-proxstream2-vodka.dts | 10 -- arch/arm/dts/uniphier-proxstream2.dtsi | 7 +- arch/arm/dts/uniphier-ref-daughter.dtsi | 2 +- arch/arm/mach-uniphier/board_early_init_f.c | 39 arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c| 5 + drivers/pinctrl/uniphier/Kconfig | 10 +- drivers/pinctrl/uniphier/Makefile| 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 15 ++- drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 107 + drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 95 ++- drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 93 ++ drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 97 ++- drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 110 - drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 91 +- drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 116 +-- drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 87 + drivers/pinctrl/uniphier/pinctrl-uniphier.h | 23 - 37 files changed, 712 insertions(+), 453 deletions(-) create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 07/11] pinctrl: uniphier: support pin configuration for dedicated pins
PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration
(pin biasing, drive strength control), but not pin-muxing.
Allow to fill the mux value table with -1 for those pins; pins with
mux value -1 will be skipped in the pin-mux set function. The mux
value type should be changed from "unsigned" to "int" in order to
accommodate -1 as a special case.
[ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ]
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 5 ++-
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 29
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 33 +-
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 37 ++--
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 39 +++--
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 39 +++--
drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 43
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 43
drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 33 +-
drivers/pinctrl/uniphier/pinctrl-uniphier.h | 2 +-
10 files changed, 149 insertions(+), 154 deletions(-)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index fc8bbd2..0ad15ab 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -91,7 +91,7 @@ static void uniphier_pinconf_input_enable(struct udevice
*dev, unsigned pin)
}
static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
- unsigned muxval)
+ int muxval)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
unsigned mux_bits, reg_stride, reg, reg_end, shift, mask;
@@ -101,6 +101,9 @@ static void uniphier_pinmux_set_one(struct udevice *dev,
unsigned pin,
/* some pins need input-enabling */
uniphier_pinconf_input_enable(dev, pin);
+ if (muxval < 0)
+ return; /* dedicated pin; nothing to do for pin-mux */
+
if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
/*
* Mode offsetbit
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index bf8c693..e7147fc 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -11,35 +11,34 @@
#include "pinctrl-uniphier.h"
static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25};
-static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
+static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
-static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
static const unsigned i2c0_pins[] = {63, 64};
-static const unsigned i2c0_muxvals[] = {0, 0};
+static const int i2c0_muxvals[] = {0, 0};
static const unsigned i2c1_pins[] = {65, 66};
-static const unsigned i2c1_muxvals[] = {0, 0};
+static const int i2c1_muxvals[] = {0, 0};
static const unsigned i2c3_pins[] = {67, 68};
-static const unsigned i2c3_muxvals[] = {1, 1};
+static const int i2c3_muxvals[] = {1, 1};
static const unsigned i2c4_pins[] = {61, 62};
-static const unsigned i2c4_muxvals[] = {1, 1};
+static const int i2c4_muxvals[] = {1, 1};
static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
15, 16, 17};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0};
static const unsigned uart0_pins[] = {54, 55};
-static const unsigned uart0_muxvals[] = {0, 0};
+static const int uart0_muxvals[] = {0, 0};
static const unsigned uart1_pins[] = {58, 59};
-static const unsigned uart1_muxvals[] = {1, 1};
+static const int uart1_muxvals[] = {1, 1};
static const unsigned uart2_pins[] = {90, 91};
-static const unsigned uart2_muxvals[] = {1, 1};
+static const int uart2_muxvals[] = {1, 1};
static const unsigned uart3_pins[] = {94, 95};
-static const unsigned uart3_muxvals[] = {1, 1};
+static const int uart3_muxvals[] = {1, 1};
static const unsigned usb0_pins[] = {46, 47};
-static const unsigned usb0_muxvals[] = {0, 0};
+static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {48, 49};
-static const unsigned usb1_muxvals[] = {0, 0};
+static const int usb1_muxvals[] = {0, 0};
static const unsigned usb2_pins[] = {50, 51};
-static const unsigned usb2_muxvals[] = {0, 0};
+static const int usb2_muxvals[] = {0, 0};
static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP(emmc),
di
[U-Boot] [PATCH 02/11] pinctrl: uniphier: fix NAND pin-mux setting for PH1-LD11/LD20
My mistake in the initial support patch.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index fe154b7..4ddaddc 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -23,8 +23,8 @@ static const unsigned i2c4_pins[] = {61, 62};
static const unsigned i2c4_muxvals[] = {1, 1};
static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
15, 16, 17};
-static const unsigned nand_muxvals[] = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
- 2, 2, 2};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0};
static const unsigned nand_cs1_pins[] = {};
static const unsigned nand_cs1_muxvals[] = {};
static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17};
--
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[U-Boot] [PATCH 05/11] pinctrl: uniphier: allow to have pinctrl node under syscon node
Currently, the UniPhier pinctrl driver itself is a syscon, but it
turned out much more reasonable to make it a child node of a syscon
because our syscon node consists of a bunch of system configuration
registers, not only pinctrl, but also phy, and misc registers.
It is difficult to split the node. This commit allows to migrate to
the new DT structure.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 2 +-
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 4 ++--
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 2 +-
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 2 +-
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 2 +-
drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 2 +-
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 2 +-
drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 2 +-
drivers/pinctrl/uniphier/pinctrl-uniphier.h | 6 +++---
9 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index b8e26d9..fc8bbd2 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -173,7 +173,7 @@ int uniphier_pinctrl_probe(struct udevice *dev,
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
- addr = dev_get_addr(dev);
+ addr = dev_get_addr(dev->parent);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index 7bc0b28..a394081 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -95,8 +95,8 @@ static int uniphier_ld20_pinctrl_probe(struct udevice *dev)
}
static const struct udevice_id uniphier_ld20_pinctrl_match[] = {
- { .compatible = "socionext,ph1-ld11-pinctrl" },
- { .compatible = "socionext,ph1-ld20-pinctrl" },
+ { .compatible = "socionext,uniphier-ld11-pinctrl" },
+ { .compatible = "socionext,uniphier-ld20-pinctrl" },
{ /* sentinel */ }
};
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index ca66dee..79bc540 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -115,7 +115,7 @@ static int uniphier_ld4_pinctrl_probe(struct udevice *dev)
}
static const struct udevice_id uniphier_ld4_pinctrl_match[] = {
- { .compatible = "socionext,ph1-ld4-pinctrl" },
+ { .compatible = "socionext,uniphier-ld4-pinctrl" },
{ /* sentinel */ }
};
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
index 0fd4dc4..861e741 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
@@ -115,7 +115,7 @@ static int uniphier_ld6b_pinctrl_probe(struct udevice *dev)
}
static const struct udevice_id uniphier_ld6b_pinctrl_match[] = {
- { .compatible = "socionext,ph1-ld6b-pinctrl" },
+ { .compatible = "socionext,uniphier-ld6b-pinctrl" },
{ /* sentinel */ }
};
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
index 9ed7c74..f5194b6 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
@@ -112,7 +112,7 @@ static int uniphier_pro4_pinctrl_probe(struct udevice *dev)
}
static const struct udevice_id uniphier_pro4_pinctrl_match[] = {
- { .compatible = "socionext,ph1-pro4-pinctrl" },
+ { .compatible = "socionext,uniphier-pro4-pinctrl" },
{ /* sentinel */ }
};
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
index 6597f1c..72b9b39 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
@@ -126,7 +126,7 @@ static int uniphier_pro5_pinctrl_probe(struct udevice *dev)
}
static const struct udevice_id uniphier_pro5_pinctrl_match[] = {
- { .compatible = "socionext,ph1-pro5-pinctrl" },
+ { .compatible = "socionext,uniphier-pro5-pinctrl" },
{ /* sentinel */ }
};
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index 0dbfdc7..a1c4240 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -120,7 +120,7 @@ static int uniphier_pxs2_pinctrl_probe(struct udevice *dev)
}
static const struct udevice_id uniphier_pxs2_pinctrl_match[] = {
- { .compatible = "socionext,proxstream2-pinctrl" },
+ { .compatible = "socionext,uniphier-pxs2-pinctrl" },
{ /* sentinel */ }
};
diff --git a/drivers/pinctrl/unip
[U-Boot] [PATCH 08/11] pinctrl: uniphier: avoid building unneeded pin-mux tables for SPL
SPL does not use all of the devices, so we can save some memory
footprint.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 8
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 34
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 38 +-
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 42 ++--
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 44 ++---
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 46 +++---
drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 46 +++---
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 50
drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 40 +--
drivers/pinctrl/uniphier/pinctrl-uniphier.h | 15 ++-
10 files changed, 192 insertions(+), 171 deletions(-)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index 0ad15ab..225a05c 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -14,6 +14,8 @@
#include "pinctrl-uniphier.h"
+static const char *uniphier_pinctrl_dummy_name = "_dummy";
+
static int uniphier_pinctrl_get_groups_count(struct udevice *dev)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
@@ -26,6 +28,9 @@ static const char *uniphier_pinctrl_get_group_name(struct
udevice *dev,
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+ if (!priv->socdata->groups[selector].name)
+ return uniphier_pinctrl_dummy_name;
+
return priv->socdata->groups[selector].name;
}
@@ -41,6 +46,9 @@ static const char *uniphier_pinmux_get_function_name(struct
udevice *dev,
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+ if (!priv->socdata->functions[selector])
+ return uniphier_pinctrl_dummy_name;
+
return priv->socdata->functions[selector];
}
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index e7147fc..e2bd9ae 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -48,29 +48,29 @@ static const struct uniphier_pinctrl_group
uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP(i2c3),
UNIPHIER_PINCTRL_GROUP(i2c4),
UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+ UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+ UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+ UNIPHIER_PINCTRL_GROUP_SPL(uart3),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
};
static const char * const uniphier_ld11_functions[] = {
- "emmc",
- "i2c0",
- "i2c1",
- "i2c3",
- "i2c4",
- "nand",
- "uart0",
- "uart1",
- "uart2",
- "uart3",
- "usb0",
- "usb1",
- "usb2",
+ UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(i2c0),
+ UNIPHIER_PINMUX_FUNCTION(i2c1),
+ UNIPHIER_PINMUX_FUNCTION(i2c3),
+ UNIPHIER_PINMUX_FUNCTION(i2c4),
+ UNIPHIER_PINMUX_FUNCTION(nand),
+ UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+ UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+ UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+ UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+ UNIPHIER_PINMUX_FUNCTION(usb0),
+ UNIPHIER_PINMUX_FUNCTION(usb1),
+ UNIPHIER_PINMUX_FUNCTION(usb2),
};
static struct uniphier_pinctrl_socdata uniphier_ld11_pinctrl_socdata = {
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index b662ae7..15ee469 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -53,10 +53,10 @@ static const struct uniphier_pinctrl_group
uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP(i2c4),
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+ UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+ UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+ UNIPHIER_PINCTRL_GROUP_SPL(uart3),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
@@ -64,21 +64,21 @@ static const struct uniphier_pinctrl_group
uniphier_ld20_groups[] = {
};
static const char * const uniphier_ld20_functions[] = {
- "emmc",
- "i2c0",
- "i2c1",
- "i2c3",
- "i2c4",
- "nand",
-
[U-Boot] [PATCH 09/11] pinctrl: uniphier: add ethernet pin-mux settings
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 5 +
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 11 +++
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 12
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 12
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 23 +++
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 19 +++
drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 12
7 files changed, 94 insertions(+)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index e2bd9ae..e95870f 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -14,6 +14,9 @@ static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23,
24, 25};
static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17};
+static const int ether_rmii_muxvals[] = {4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4};
static const unsigned i2c0_pins[] = {63, 64};
static const int i2c0_muxvals[] = {0, 0};
static const unsigned i2c1_pins[] = {65, 66};
@@ -43,6 +46,7 @@ static const int usb2_muxvals[] = {0, 0};
static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(ether_rmii),
UNIPHIER_PINCTRL_GROUP(i2c0),
UNIPHIER_PINCTRL_GROUP(i2c1),
UNIPHIER_PINCTRL_GROUP(i2c3),
@@ -59,6 +63,7 @@ static const struct uniphier_pinctrl_group
uniphier_ld11_groups[] = {
static const char * const uniphier_ld11_functions[] = {
UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(ether_rmii),
UNIPHIER_PINMUX_FUNCTION(i2c0),
UNIPHIER_PINMUX_FUNCTION(i2c1),
UNIPHIER_PINMUX_FUNCTION(i2c3),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index 15ee469..e903196 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -14,6 +14,13 @@ static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23,
24, 25};
static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned ether_rgmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 38,
+ 39, 40, 41, 42, 43, 44, 45};
+static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 39,
+ 41, 42, 45};
+static const int ether_rmii_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
static const unsigned i2c0_pins[] = {63, 64};
static const int i2c0_muxvals[] = {0, 0};
static const unsigned i2c1_pins[] = {65, 66};
@@ -47,6 +54,8 @@ static const int usb3_muxvals[] = {0, 0};
static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+ UNIPHIER_PINCTRL_GROUP(ether_rmii),
UNIPHIER_PINCTRL_GROUP(i2c0),
UNIPHIER_PINCTRL_GROUP(i2c1),
UNIPHIER_PINCTRL_GROUP(i2c3),
@@ -65,6 +74,8 @@ static const struct uniphier_pinctrl_group
uniphier_ld20_groups[] = {
static const char * const uniphier_ld20_functions[] = {
UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+ UNIPHIER_PINMUX_FUNCTION(ether_rmii),
UNIPHIER_PINMUX_FUNCTION(i2c0),
UNIPHIER_PINMUX_FUNCTION(i2c1),
UNIPHIER_PINMUX_FUNCTION(i2c3),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index 56d9d5b..dbb9499 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -27,6 +27,14 @@ static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26,
27};
static const int emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned ether_mii_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40,
+ 41, 42, 43, 136, 137, 138, 139, 140,
+ 141, 142};
+static const int ether_mii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 4, 4, 4, 4, 4, 4, 4};
+static const uns
[U-Boot] [PATCH 06/11] pinctrl: uniphier: split pinctrl driver for PH1-LD11 and PH1-LD20
PH1-LD11 and PH1-LD20 have much pin controlling in common, so I
added a single driver shared between them in the initial commit.
However, the Ethernet pin-mux settings I am going to add are
different with each other, and they may diverge more as the
progress of development. Split it into two dedicated drivers.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/Kconfig | 10 ++-
drivers/pinctrl/uniphier/Makefile| 1 +
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 103 +++
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 12 +--
4 files changed, 118 insertions(+), 8 deletions(-)
create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index 1856ff0..7febea2 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -39,9 +39,15 @@ config PINCTRL_UNIPHIER_LD6B
default y
select PINCTRL_UNIPHIER
+config PINCTRL_UNIPHIER_LD11
+ bool "UniPhier PH1-LD11 SoC pinctrl driver"
+ depends on ARCH_UNIPHIER_LD11
+ default y
+ select PINCTRL_UNIPHIER
+
config PINCTRL_UNIPHIER_LD20
- bool "UniPhier PH1-LD11/PH1-LD20 SoC pinctrl driver"
- depends on ARCH_UNIPHIER_LD11 || ARCH_UNIPHIER_LD20
+ bool "UniPhier PH1-LD20 SoC pinctrl driver"
+ depends on ARCH_UNIPHIER_LD20
default y
select PINCTRL_UNIPHIER
diff --git a/drivers/pinctrl/uniphier/Makefile
b/drivers/pinctrl/uniphier/Makefile
index bea4dd8..4de251b 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -10,4 +10,5 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8) +=
pinctrl-uniphier-sld8.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PRO5)+= pinctrl-uniphier-pro5.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PXS2)+= pinctrl-uniphier-pxs2.o
obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B)+= pinctrl-uniphier-ld6b.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD11)+= pinctrl-uniphier-ld11.o
obj-$(CONFIG_PINCTRL_UNIPHIER_LD20)+= pinctrl-uniphier-ld20.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
new file mode 100644
index 000..bf8c693
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25};
+static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
+static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned i2c0_pins[] = {63, 64};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {65, 66};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {67, 68};
+static const unsigned i2c3_muxvals[] = {1, 1};
+static const unsigned i2c4_pins[] = {61, 62};
+static const unsigned i2c4_muxvals[] = {1, 1};
+static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
+15, 16, 17};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0};
+static const unsigned uart0_pins[] = {54, 55};
+static const unsigned uart0_muxvals[] = {0, 0};
+static const unsigned uart1_pins[] = {58, 59};
+static const unsigned uart1_muxvals[] = {1, 1};
+static const unsigned uart2_pins[] = {90, 91};
+static const unsigned uart2_muxvals[] = {1, 1};
+static const unsigned uart3_pins[] = {94, 95};
+static const unsigned uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {46, 47};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {48, 49};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {50, 51};
+static const unsigned usb2_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c4),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+};
+
+static const char * const uniphier_ld11_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c3",
+ "i2c4",
+ "nand",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "usb0",
+ "usb1",
+ "usb2",
+};
+
+static struc
[U-Boot] [PATCH 04/11] ARM: dts: uniphier: sync Device Trees with upstream Linux
I periodically sync Device Trees for better maintainability.
Signed-off-by: Masahiro Yamada
---
arch/arm/dts/uniphier-common32.dtsi | 22 +++---
arch/arm/dts/uniphier-ph1-ld11-ref.dts | 13 ++--
arch/arm/dts/uniphier-ph1-ld11.dtsi | 45 +++-
arch/arm/dts/uniphier-ph1-ld20-ref.dts | 10 ---
arch/arm/dts/uniphier-ph1-ld20.dtsi | 30 ++-
arch/arm/dts/uniphier-ph1-ld4-ref.dts| 10 ---
arch/arm/dts/uniphier-ph1-ld4.dtsi | 2 +-
arch/arm/dts/uniphier-ph1-ld6b-ref.dts | 10 ---
arch/arm/dts/uniphier-ph1-ld6b.dtsi | 4 +--
arch/arm/dts/uniphier-ph1-pro4-ace.dts | 10 ---
arch/arm/dts/uniphier-ph1-pro4-ref.dts | 10 ---
arch/arm/dts/uniphier-ph1-pro4-sanji.dts | 10 ---
arch/arm/dts/uniphier-ph1-pro4.dtsi | 2 +-
arch/arm/dts/uniphier-ph1-pro5-4kbox.dts | 10 ---
arch/arm/dts/uniphier-ph1-pro5.dtsi | 2 +-
arch/arm/dts/uniphier-ph1-sld8-ref.dts | 10 ---
arch/arm/dts/uniphier-ph1-sld8.dtsi | 2 +-
arch/arm/dts/uniphier-pinctrl.dtsi | 10 +++
arch/arm/dts/uniphier-proxstream2-gentil.dts | 10 ---
arch/arm/dts/uniphier-proxstream2-vodka.dts | 10 ---
arch/arm/dts/uniphier-proxstream2.dtsi | 2 +-
arch/arm/dts/uniphier-ref-daughter.dtsi | 2 +-
22 files changed, 98 insertions(+), 138 deletions(-)
diff --git a/arch/arm/dts/uniphier-common32.dtsi
b/arch/arm/dts/uniphier-common32.dtsi
index 7d59112..b0b2b57 100644
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ b/arch/arm/dts/uniphier-common32.dtsi
@@ -22,6 +22,7 @@
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
+ u-boot,dm-pre-reloc;
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
@@ -65,9 +66,12 @@
system_bus: system-bus@58c0 {
compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
reg = <0x58c0 0x400>;
#address-cells = <2>;
#size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@5980 {
@@ -109,9 +113,15 @@
interrupt-controller;
};
- pinctrl: pinctrl@5f801000 {
- /* specify compatible in each SoC DTSI */
- reg = <0x5f801000 0xe00>;
+ soc-glue@5f80 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5f80 0x2000>;
+ u-boot,dm-pre-reloc;
+
+ pinctrl: pinctrl {
+ /* specify compatible in each SoC DTSI */
+ u-boot,dm-pre-reloc;
+ };
};
sysctrl: sysctrl@6184 {
@@ -124,8 +134,12 @@
nand: nand@6800 {
compatible = "denali,denali-nand-dt";
- reg = <0x6800 0x20>, <0x6810 0x1000>;
+ status = "disabled";
reg-names = "nand_data", "denali_reg";
+ reg = <0x6800 0x20>, <0x6810 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
};
};
};
diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts
b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
index b148e9f..4eb7664 100644
--- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
@@ -1,7 +1,8 @@
/*
* Device Tree Source for UniPhier PH1-LD11 Reference Board
*
- * Copyright (C) 2016 Masahiro Yamada
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada
*
* SPDX-License-Identifier:GPL-2.0+X11
*/
@@ -62,20 +63,10 @@
};
/* for U-Boot only */
-/ {
- soc {
- u-boot,dm-pre-reloc;
- };
-};
-
&serial0 {
u-boot,dm-pre-reloc;
};
-&pinctrl {
- u-boot,dm-pre-reloc;
-};
-
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi
b/arch/arm/dts/uniphier-ph1-ld11.dtsi
index e485f90..8901a79 100644
--- a/arch/arm/dts/uniphier-ph1-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld11.dtsi
@@ -1,11 +1,14 @@
/*
* Device Tree Source for UniPhier PH1-LD11 SoC
*
- * Copyright (C) 2016 Masahiro Yamada
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada
*
* SPDX-License-Identifier:GPL-2.0+X11
*/
+/memreserve/ 0x8000 0x0008;/* cpu-release-addr */
+
/ {
compatible = "socionext,ph1-ld11";
#address-cell
[U-Boot] [PATCH 01/11] pinctrl: uniphier: remove wrong pin-mux functions for ProXstream2
These are pin group names, not function names.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index cfec877..0dbfdc7 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -96,11 +96,9 @@ static const char * const uniphier_pxs2_functions[] = {
"nand",
"sd",
"uart0",
- "uart0b",
"uart1",
"uart2",
"uart3",
- "uart3b",
"usb0",
"usb1",
"usb2",
--
1.9.1
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[U-Boot] [PATCH 10/11] ARM: dts: uniphier: add AIDET nodes
The AIDET (ARM Interrupt Detector Add-on Circuit) is a kind of
syscon block related with the interrupt controller.
Signed-off-by: Masahiro Yamada
---
arch/arm/dts/uniphier-ph1-ld11.dtsi| 5 +
arch/arm/dts/uniphier-ph1-ld20.dtsi| 5 +
arch/arm/dts/uniphier-ph1-ld4.dtsi | 5 +
arch/arm/dts/uniphier-ph1-pro4.dtsi| 5 +
arch/arm/dts/uniphier-ph1-pro5.dtsi| 5 +
arch/arm/dts/uniphier-ph1-sld3.dtsi| 5 +
arch/arm/dts/uniphier-ph1-sld8.dtsi| 5 +
arch/arm/dts/uniphier-proxstream2.dtsi | 5 +
8 files changed, 40 insertions(+)
diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi
b/arch/arm/dts/uniphier-ph1-ld11.dtsi
index 8901a79..ffe04f5 100644
--- a/arch/arm/dts/uniphier-ph1-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld11.dtsi
@@ -260,6 +260,11 @@
};
};
+ aidet@5fc2 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc2 0x200>;
+ };
+
gic: interrupt-controller@5fe0 {
compatible = "arm,gic-v3";
reg = <0x5fe0 0x1>, /* GICD */
diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi
b/arch/arm/dts/uniphier-ph1-ld20.dtsi
index 434890d..3d36a26 100644
--- a/arch/arm/dts/uniphier-ph1-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld20.dtsi
@@ -264,6 +264,11 @@
};
};
+ aidet@5fc2 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc2 0x200>;
+ };
+
gic: interrupt-controller@5fe0 {
compatible = "arm,gic-v3";
reg = <0x5fe0 0x1>, /* GICD */
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi
b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 5629b7d..07f315a 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -274,6 +274,11 @@
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&mio 5>, <&mio 6>;
};
+
+ aidet@6183 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x6183 0x200>;
+ };
};
&refclk {
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi
b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 080fced..e0b28b8 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -400,6 +400,11 @@
clocks = <&mio 4>, <&mio 6>;
};
+ aidet@5fc2 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc2 0x200>;
+ };
+
usb0: usb@65a0 {
compatible = "socionext,uniphier-xhci", "generic-xhci";
status = "disabled";
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi
b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index 5b7f6e8..05f961f 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -355,6 +355,11 @@
clock-frequency = <40>;
};
+ aidet@5fc2 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc2 0x200>;
+ };
+
emmc: sdhc@6840 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi
b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index 789713d..c3adaf1 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -349,6 +349,11 @@
clocks = <&mio 7>, <&mio 6>;
};
+ aidet@f183 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0xf183 0x200>;
+ };
+
sysctrl: sysctrl@f184 {
compatible = "socionext,ph1-sld3-sysctrl";
reg = <0xf184 0x4000>;
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi
b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index f07a1d1..e0376a1 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -274,6 +274,11 @@
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&mio 5>, <&mio 6>;
};
+
+ aidet@6183 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x6183 0x200>;
+ };
};
&refclk {
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi
b/arch/arm/dts/uniphier-proxstream2.dtsi
index 0a8c049..23a6bfa 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -383,6 +383,11 @@
bus-width = <4>;
};
+ aidet@5fc2 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc2 0x200>;
+ };
+
usb0: usb@65a0 {
compatible = "socionext,uniphier-xhci", "generic-xhci";
status =
[U-Boot] [PATCH 11/11] ARM: uniphier: add external IRQ setup code
I will carry this work-around until it is cared in the kernel.
This looks up the AIDET node and sets up a register to handle
active low interrupt signals.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/board_early_init_f.c | 39 +++
arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | 5
2 files changed, 44 insertions(+)
diff --git a/arch/arm/mach-uniphier/board_early_init_f.c
b/arch/arm/mach-uniphier/board_early_init_f.c
index f853701..d35d38d 100644
--- a/arch/arm/mach-uniphier/board_early_init_f.c
+++ b/arch/arm/mach-uniphier/board_early_init_f.c
@@ -4,10 +4,47 @@
* SPDX-License-Identifier:GPL-2.0+
*/
+#include
+#include
+#include
+
#include "init.h"
#include "micro-support-card.h"
#include "soc-info.h"
+DECLARE_GLOBAL_DATA_PTR;
+
+static void uniphier_setup_xirq(void)
+{
+ const void *fdt = gd->fdt_blob;
+ int soc_node, aidet_node;
+ const u32 *val;
+ unsigned long aidet_base;
+ u32 tmp;
+
+ soc_node = fdt_path_offset(fdt, "/soc");
+ if (soc_node < 0)
+ return;
+
+ aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5);
+ if (aidet_node < 0)
+ return;
+
+ val = fdt_getprop(fdt, aidet_node, "reg", NULL);
+ if (!val)
+ return;
+
+ aidet_base = fdt32_to_cpu(*val);
+
+ tmp = readl(aidet_base + 8);/* AIDET DETCONFR2 */
+ tmp |= 0x00ff; /* Set XIRQ0-7 low active */
+ writel(tmp, aidet_base + 8);
+
+ tmp = readl(0x5590);/* IRQCTL */
+ tmp |= 0x00ff;
+ writel(tmp, 0x5590);
+}
+
int board_early_init_f(void)
{
led_puts("U0");
@@ -81,6 +118,8 @@ int board_early_init_f(void)
break;
}
+ uniphier_setup_xirq();
+
led_puts("U2");
return 0;
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
index 6066b16..645b901 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
@@ -43,4 +43,9 @@ void uniphier_ld20_pin_init(void)
sg_set_pinsel(53, 0, 8, 4); /* USB3OD -> USB3OD */
sg_set_iectrl_range(46, 53);
#endif
+
+ sg_set_pinsel(149, 14, 8, 4); /* XIRQ0-> XIRQ0 */
+ sg_set_iectrl(149);
+ sg_set_pinsel(153, 14, 8, 4); /* XIRQ4-> XIRQ4 */
+ sg_set_iectrl(153);
}
--
1.9.1
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Re: [U-Boot] Problem loading boot script from ext4 mmc on sunxi H3
Hello, On 29 June 2016 at 10:45, Karsten Merker wrote: > On Wed, Jun 29, 2016 at 09:30:33AM +0200, Michal Suchanek wrote: > >> I tried loading system with recent u-boot but it does not work. >> >> Trying some ext4ls shows there is some problem accessing the filesystem. >> >> Not sure if this should be attributed to the ext driver or to the mmc >> driver or something else entirely. > > I haven't tested that myself, but I have seen reports on other > platforms that the u-boot ext4 driver has problems with ext4 > filesystems which use the "flex_bg" filesystem feature, as that > causes certain changes to the on-disk layout compared to ext4 > without this feature. From what people have reported, it appears > that "flex_bg" is enabled by default on ext4 filesystems created > with a recent mkfs.ext4 version. > Reformatting without flex_bg does not seem to have any effect. However, ls seems to give some random stuff for directories other than / so some similar remapping feature could cause this. Thanks Michal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ti_omap5_common: Find right dtb file for DRA72-RevC Evm
DRA72-Evm revC uses dra72-evm-revc.dtb. Update the same in env vatiables.
Signed-off-by: Lokesh Vutla
---
board/ti/dra7xx/evm.c | 10 +++---
include/configs/ti_omap5_common.h | 2 ++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 0394e4e..6a4d027 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -413,10 +413,14 @@ int board_late_init(void)
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
char *name = "unknown";
- if (is_dra72x())
- name = "dra72x";
- else
+ if (is_dra72x()) {
+ if (board_is_dra72x_revc_or_later())
+ name = "dra72x-revc";
+ else
+ name = "dra72x";
+ } else {
name = "dra7xx";
+ }
set_board_info_env(name);
diff --git a/include/configs/ti_omap5_common.h
b/include/configs/ti_omap5_common.h
index 2e4c8e9..3589cdc 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -100,6 +100,8 @@
"setenv fdtfile omap5-uevm.dtb; fi; " \
"if test $board_name = dra7xx; then " \
"setenv fdtfile dra7-evm.dtb; fi;" \
+ "if test $board_name = dra72x-revc; then " \
+ "setenv fdtfile dra72-evm-revc.dtb; fi;" \
"if test $board_name = dra72x; then " \
"setenv fdtfile dra72-evm.dtb; fi;" \
"if test $board_name = beagle_x15; then " \
--
2.9.0
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Re: [U-Boot] [PATCH 2/2] usbarmory: Add board_run_command() function
Hi Simon, On 28/06/2016 20:43, Simon Glass wrote: > Hi, > > On 27 June 2016 at 03:38, Stefano Babic wrote: >> Hi Andrej, >> >> On 20/06/2016 18:18, Andrej Rosano wrote: >> I ten to NACK this. You can do exactly the same with a U-Boot script, and if you want to have this as default, you can change your default environment. This is just a wrapper around the hush shell. >>> >>> The intention of the patch is to boot the kernel while having the CLI >>> disabled >>> (CONFIG_CMDLINE=n). The U-Boot script needs the CLI to be enabled AFAIK. >>> >>> It is better having the CLI disabled when using the Verified Boot, otherwise >>> there are chances to bypass the FIT image verification (e.g. using md/mw >>> commands in case are available): >> >> Why is it not enough to disable the CONSOLE ? I mean, if there is no >> user interface (and this is done in a lot of ways, for example setting >> stdin / stdout), there is no ways to bypass it because the interface is >> not availabel. Or is there some other security issues I am not aware of ? > > It is an extra level of security - providing a very simple command > execution instead of the general CLI. That is actually the original > purpose of board_run_command(). E.g. for Chrome OS we had an option to > either run the normal CLI or a simple (secure) one. Also see > cli_process_fdt() which provides for a 'bootsecure' mode, controlled > from the FDT. I see, thanks for explanation. My fear is that the process diverges and boards start to embed U-Boot scripts inside the code, letting them not very maintainable. But I have understood the issue and I put this patch for merging in my queue. Best regards, Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1] dm: usb: Prevent NULL hub in usb_device_info()
This patch modifies the usb_device_info() function to enumerate
active USB hubs by iterating UCLASS_USB_HUB directly.
The previous code used UCLASS_USB nodes instead and retrieved
their first child node, expecting it to be a hub. However, it
did not protect against retrieving (and dereferencing) a NULL
pointer this way.
Depending on the available USB hardware, this might happen easily.
For example the USB controller on sun7i-a20 has top-level OHCI
nodes that won't have any children as long as no USB1-only
peripheral is attached. ("usb tree" will only show EHCI nodes.)
The failure can also be demonstrated with U-Boot's sandbox
architecture, by simply enabling the inactive "usb_2" node in
test.dts. This creates a similar situation, where the existing
usb_device_info() implementation would crash (segfault) when
issuing a "usb info" command.
Signed-off-by: Bernhard Nortmann
---
cmd/usb.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/cmd/usb.c b/cmd/usb.c
index 58d9db2..3146f54 100644
--- a/cmd/usb.c
+++ b/cmd/usb.c
@@ -602,18 +602,13 @@ static void show_info(struct udevice *dev)
static int usb_device_info(void)
{
- struct udevice *bus;
-
- for (uclass_first_device(UCLASS_USB, &bus);
-bus;
-uclass_next_device(&bus)) {
- struct udevice *hub;
+ struct udevice *hub;
- device_find_first_child(bus, &hub);
- if (device_get_uclass_id(hub) == UCLASS_USB_HUB &&
- device_active(hub)) {
+ for (uclass_first_device(UCLASS_USB_HUB, &hub);
+hub;
+uclass_next_device(&hub)) {
+ if (device_active(hub))
show_info(hub);
- }
}
return 0;
--
2.7.3
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[U-Boot] Problem loading boot script from ext4 mmc on sunxi H3
Hello, I tried loading system with recent u-boot but it does not work. Trying some ext4ls shows there is some problem accessing the filesystem. Not sure if this should be attributed to the ext driver or to the mmc driver or something else entirely. Does this work for anybody? Any debug option to turn on? Thanks Michal U-Boot SPL 2016.07-rc2-00071-gc4ba89e (Jun 28 2016 - 16:53:32) DRAM: u MiB Trying to boot from MMC1 U-Boot 2016.07-rc2-00071-gc4ba89e (Jun 28 2016 - 16:53:32 +0200) Allwinner Technology CPU: Allwinner H3 (SUN8I 1680) Model: Xunlong Orange Pi One DRAM: 512 MiB MMC: SUNXI SD/MMC: 0 In:serial Out: serial Err: serial Net: No ethernet found. starting USB... USB0: USB EHCI 1.00 USB1: USB OHCI 1.0 scanning bus 0 for devices... 1 USB Device(s) found Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device Scanning mmc 0:1... USB device 0: unknown device No ethernet found. missing environment variable: pxeuuid missing environment variable: bootfile Retrieving file: pxelinux.cfg/ No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/00 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/0 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/ No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/00 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/0 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/default-arm-sunxi No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/default-arm No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/default No ethernet found. Config file not found No ethernet found. No ethernet found. => ext4ls mmc 0:1 boot => ext4ls mmc 0:1 opt < ? > 0 nux/drivers/mmc/core/sdio_cis.h * * Author:Nicolas Pitre * Created:June 11, 2007 * Copyright:MontaVis => ext4ls mmc 0:1 var => ext4ls mmc 0:1 4096 . 4096 .. 16384 lost+found 4096 scripts 4096 tmp 4096 scratch 4842 debug 18704 lib 0 run 0 etc 0 Makefile 0 home 0 media 0 config-4.4.0-rc5-00131-gce3f5ce-dirty 0 boot 0 srv 0 dev 0 proc 0 bin 0 mnt 0 sys 0 include 98629 source 0 var 0 sbin 0 root 0 usr 647 opt ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/2] i2c: atmel: DT binding for i2c driver
Hello Songjun Wu,
Am 20.06.2016 um 07:22 schrieb Songjun Wu:
DT binding documentation for atmel i2c driver.
Signed-off-by: Songjun Wu
---
Changes in v3: None
Changes in v2:
- Add phandles to input clocks
doc/device-tree-bindings/i2c/i2c-at91.txt | 26 ++
1 file changed, 26 insertions(+)
create mode 100644 doc/device-tree-bindings/i2c/i2c-at91.txt
Thanks!
Reviewed-by: Heiko Schocher
Acked-by: Heiko Schocher
bye,
Heiko
diff --git a/doc/device-tree-bindings/i2c/i2c-at91.txt
b/doc/device-tree-bindings/i2c/i2c-at91.txt
new file mode 100644
index 000..2065b73
--- /dev/null
+++ b/doc/device-tree-bindings/i2c/i2c-at91.txt
@@ -0,0 +1,26 @@
+I2C for Atmel platforms
+
+Required properties :
+- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
+ "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
+ "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c".
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks: phandles to input clocks.
+
+Optional properties:
+- clock-frequency: Desired I2C bus frequency in Hz, default value is 10.
+- Child nodes conforming to i2c bus binding.
+
+Examples :
+
+i2c0: i2c@f8028000 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0xf8028000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi0_clk>;
+ clock-frequency = <10>;
+};
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] [PATCH v3 1/2] i2c: atmel: add i2c driver
Hello Songjun Wu,
Am 20.06.2016 um 07:22 schrieb Songjun Wu:
Add i2c driver.
Signed-off-by: Songjun Wu
---
Changes in v3:
- Update the clk API.
Changes in v2:
- Add code to get and enable clock.
drivers/i2c/Kconfig| 10 ++
drivers/i2c/Makefile | 1 +
drivers/i2c/at91_i2c.c | 338 +
drivers/i2c/at91_i2c.h | 77 +++
4 files changed, 426 insertions(+)
create mode 100644 drivers/i2c/at91_i2c.c
create mode 100644 drivers/i2c/at91_i2c.h
Thanks!
Reviewed-by: Heiko Schocher
Acked-by: Heiko Schocher
bye,
Heiko
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 6e22bba..f6a613c 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -58,6 +58,16 @@ config DM_I2C_GPIO
bindings are supported.
Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
+config SYS_I2C_AT91
+ bool "Atmel I2C driver"
+ depends on DM_I2C && ARCH_AT91
+ help
+ Add support for the Atmel I2C driver. A serious problem is that there
+ is no documented way to issue repeated START conditions for more than
+ two messages, as needed to support combined I2C messages. Use the
+ i2c-gpio driver unless your system can cope with this limitation.
+ Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
+
config SYS_I2C_FSL
bool "Freescale I2C bus driver"
depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 167424d..c5362a5 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
+obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
diff --git a/drivers/i2c/at91_i2c.c b/drivers/i2c/at91_i2c.c
new file mode 100644
index 000..8e9c3ad
--- /dev/null
+++ b/drivers/i2c/at91_i2c.c
@@ -0,0 +1,338 @@
+/*
+ * Atmel I2C driver.
+ *
+ * (C) Copyright 2016 Songjun Wu
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "at91_i2c.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_TIMEOUT_MS 100
+
+static int at91_wait_for_xfer(struct at91_i2c_bus *bus, u32 status)
+{
+ struct at91_i2c_regs *reg = bus->regs;
+ ulong start_time = get_timer(0);
+ u32 sr;
+
+ bus->status = 0;
+
+ do {
+ sr = readl(®->sr);
+ bus->status |= sr;
+
+ if (sr & TWI_SR_NACK)
+ return -EREMOTEIO;
+ else if (sr & status)
+ return 0;
+ } while (get_timer(start_time) < I2C_TIMEOUT_MS);
+
+ return -ETIMEDOUT;
+}
+
+static int at91_i2c_xfer_msg(struct at91_i2c_bus *bus, struct i2c_msg *msg)
+{
+ struct at91_i2c_regs *reg = bus->regs;
+ bool is_read = msg->flags & I2C_M_RD;
+ u32 i;
+ int ret = 0;
+
+ readl(®->sr);
+ if (is_read) {
+ writel(TWI_CR_START, ®->cr);
+
+ for (i = 0; !ret && i < (msg->len - 1); i++) {
+ ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY);
+ msg->buf[i] = readl(®->rhr);
+ }
+
+ if (ret)
+ goto error;
+
+ writel(TWI_CR_STOP, ®->cr);
+
+ ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY);
+ if (ret)
+ goto error;
+
+ msg->buf[i] = readl(®->rhr);
+
+ } else {
+ writel(msg->buf[0], ®->thr);
+ for (i = 1; !ret && (i < msg->len); i++) {
+ writel(msg->buf[i], ®->thr);
+ ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY);
+ }
+
+ if (ret)
+ goto error;
+
+ writel(TWI_CR_STOP, ®->cr);
+ }
+
+ if (!ret)
+ ret = at91_wait_for_xfer(bus, TWI_SR_TXCOMP);
+
+ if (ret)
+ goto error;
+
+ if (bus->status & (TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_LOCK)) {
+ ret = -EIO;
+ goto error;
+ }
+
+ return 0;
+
+error:
+ if (bus->status & TWI_SR_LOCK)
+ writel(TWI_CR_LOCKCLR, ®->cr);
+
+ return ret;
+}
+
+static int at91_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
+{
+ struct at91_i2c_bus *bus = dev_get_priv(dev);
+ struct at91_i2c_regs *reg = bus->regs;
+ struct i2c_msg *m_start = msg;
+ bool is_read;
+ u32 int_addr_flag = 0;
+ int ret = 0;
+
+ if (nmsgs == 2) {
+ int internal_address = 0;
+ int i;
+
+ /* 1st msg is put into the internal address, s
[U-Boot] mkimage can't read .tmp
Hello all I have been trying to create a FIT image using mkimage using the command: mkimage -D "-I dts -O dtb -p 2000" -f name.its name.fit The output is: DTC: dts->dtb on file "name.its" mkimage: Can't read name.fit.tmp: Invalid argument mkimage Can't add hashes to FIT blob No matter what I try, which arguments I add or remove or which modifications I make to the its file, I keep getting this output. Unfortunately I can't find much on Google for this exact issue. I found someone who solved the issue by installing DTC, but that is not the issue in my case. Uboot development tools, DTC and mkimage are all at the latest version. Does anyone have any idea what other issues might be causing this behavior? Kind regards Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] i2c_eeprom: Add reading support
Hello Mario,
Am 22.06.2016 um 15:14 schrieb Mario Six:
From: "mario@gdsys.cc"
This patch implements the reading functionality for the generic I2C
EEPROM driver, which was just a non-functional stub until now.
Since the page size will be of importance for the writing support, we
add suitable members to the private data structure to keep track of it.
Compatibility strings for a range of at24c* chips are added.
Signed-off-by: Mario Six
---
Changes in v2:
- Simplified and documented the i2c_eeprom struct
- Simplified the read function
- Corrected Kconfig dependency (from DM to MISC)
---
drivers/misc/Kconfig | 5 +
drivers/misc/i2c_eeprom.c | 39 +++
include/i2c_eeprom.h | 4
3 files changed, 40 insertions(+), 8 deletions(-)
Thanks!
Reviewed-by: Heiko Schocher
bye,
Heiko
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 2373037..b84e351 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -144,4 +144,9 @@ config QFW
Hidden option to enable QEMU fw_cfg interface. This will be selected
by
either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
+config I2C_EEPROM
+ bool "Enable driver for generic I2C-attached EEPROMs"
+ depends on MISC
+ help
+ Enable a generic driver for EEPROMs attached via I2C.
endmenu
diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c
index 814134a..c9f4174 100644
--- a/drivers/misc/i2c_eeprom.c
+++ b/drivers/misc/i2c_eeprom.c
@@ -13,7 +13,7 @@
static int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf,
int size)
{
- return -ENODEV;
+ return dm_i2c_read(dev, offset, buf, size);
}
static int i2c_eeprom_write(struct udevice *dev, int offset,
@@ -27,23 +27,46 @@ struct i2c_eeprom_ops i2c_eeprom_std_ops = {
.write = i2c_eeprom_write,
};
+static int i2c_eeprom_std_ofdata_to_platdata(struct udevice *dev)
+{
+ struct i2c_eeprom *priv = dev_get_priv(dev);
+ u64 data = dev_get_driver_data(dev);
+
+ /* 6 bit -> page size of up to 2^63 (should be sufficient) */
+ priv->pagewidth = data & 0x3F;
+ priv->pagesize = (1 << priv->pagewidth);
+
+ return 0;
+}
+
int i2c_eeprom_std_probe(struct udevice *dev)
{
return 0;
}
static const struct udevice_id i2c_eeprom_std_ids[] = {
- { .compatible = "i2c-eeprom" },
+ { .compatible = "i2c-eeprom", .data = 0 },
+ { .compatible = "atmel,24c01a", .data = 3 },
+ { .compatible = "atmel,24c02", .data = 3 },
+ { .compatible = "atmel,24c04", .data = 4 },
+ { .compatible = "atmel,24c08a", .data = 4 },
+ { .compatible = "atmel,24c16a", .data = 4 },
+ { .compatible = "atmel,24c32", .data = 5 },
+ { .compatible = "atmel,24c64", .data = 5 },
+ { .compatible = "atmel,24c128", .data = 6 },
+ { .compatible = "atmel,24c256", .data = 6 },
+ { .compatible = "atmel,24c512", .data = 6 },
{ }
};
U_BOOT_DRIVER(i2c_eeprom_std) = {
- .name = "i2c_eeprom",
- .id = UCLASS_I2C_EEPROM,
- .of_match = i2c_eeprom_std_ids,
- .probe = i2c_eeprom_std_probe,
- .priv_auto_alloc_size = sizeof(struct i2c_eeprom),
- .ops= &i2c_eeprom_std_ops,
+ .name = "i2c_eeprom",
+ .id = UCLASS_I2C_EEPROM,
+ .of_match = i2c_eeprom_std_ids,
+ .probe = i2c_eeprom_std_probe,
+ .ofdata_to_platdata = i2c_eeprom_std_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct i2c_eeprom),
+ .ops= &i2c_eeprom_std_ops,
};
UCLASS_DRIVER(i2c_eeprom) = {
diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h
index ea6c962..0452892 100644
--- a/include/i2c_eeprom.h
+++ b/include/i2c_eeprom.h
@@ -14,6 +14,10 @@ struct i2c_eeprom_ops {
};
struct i2c_eeprom {
+ /* The EEPROM's page size in byte */
+ unsigned long pagesize;
+ /* The EEPROM's page width in bits (pagesize = 2^pagewidth) */
+ unsigned pagewidth;
};
#endif
--
2.7.0.GIT
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[U-Boot] Radxa Rock2 square bug report (kernel won't load)
Hi, I am attempting to use U-Boot on a radxa rock2 board, and noticed that the latest release of u-boot doesn't allow the kernel to boot. I am including a boot log below. I was able to get a working u-boot which boots my kernel by compiling v2016.03. (git://git.denx.de/u-boot.git) I traced a bit and found two commits which seem to break things, but I stopped there. 1) ed980b8c62fbe17052ec6151a68b5b0be3809485 after this commit I am able to get a working uboot with this patch: diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index fd32fb5..c2780c4 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -67,3 +67,4 @@ CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y +CONFIG_EFI_LOADER=n 2) c09d29057ab0b04db0857d319c6bff74de31b9c3 I wasn't able to find a solution here. I am using this toolchain: android-platform-prebuilts-gcc-linux-x86-arm-arm-eabi-4.6 Is there a better option for u-boot in general? I'm able to test and do some limited troubleshooting, but I don't think I can delve into dram init assembly code. I believe that v2016.03 is sufficient for our purposes, so this isn't critical for us. Just a friendly bug report. Good luck, Sandy Patterson U-Boot SPL 2016.05 (Jun 28 2016 - 09:57:30) Trying to boot from MMC1 I see a similar log in master: U-Boot 2016.05 (Jun 28 2016 - 09:57:30 -0400) Model: Radxa Rock 2 Square DRAM: 2 GiB MMC: dwmmc@ff0f: 0, dwmmc@ff0c: 1 ** First descriptor is NOT a primary desc on 0:1 ** stdio_add_devices: Video device failed (ret=-19) In:serial Out: serial Err: serial Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 5244128 bytes read in 390 ms (12.8 MiB/s) 41982 bytes read in 14 ms (2.9 MiB/s) 10534400 bytes read in 775 ms (13 MiB/s) Kernel image @ 0x200 [ 0x00 - 0x5004e0 ] ## Flattened Device Tree blob at 01f0 Booting using the fdt blob at 0x1f0 Loading Ramdisk to 1f5f4000, end 1e00 ... OK Loading Device Tree to 1f5e6000, end 1f5f33fd ... OK Starting kernel ... Reset not supported on this platform ### ERROR ### Please RESET the board ### ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] nitrogen6x : Use generic distro configuration
In order to simplify the use of various images on various media for nitrogen6x, the configuration of the board must follow the generic distro configuration (doc/README.distro). In order to boot your old rootfs, move your kernel and your device tree in /boot/. Then create /boot/extlinux/extlinux.conf with for example: default Buildroot label Buildroot kernel /boot/zImage append console=ttymxc1,115200 root=/dev/mmcblk0p1 rootwait rw fdtdir /boot Signed-off-by: Fabien Lahoudere --- Changes for V2: - reintegration of deleted env - changes are applied only if CONFIG_DISTRO_DEFAULTS=y Changes for V3: - remove undefined device tree configs/mx6qsabrelite_defconfig | 1 + configs/nitrogen6dl2g_defconfig | 1 + configs/nitrogen6dl_defconfig | 1 + configs/nitrogen6q2g_defconfig | 1 + configs/nitrogen6q_defconfig| 1 + configs/nitrogen6s1g_defconfig | 1 + configs/nitrogen6s_defconfig| 1 + doc/README.imx6 | 47 + include/configs/mx6_common.h| 24 + include/configs/nitrogen6x.h| 36 +-- 10 files changed, 108 insertions(+), 6 deletions(-) diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index fa6139a..27b64c4 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -36,3 +36,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_OF_LIBFDT=y +CONFIG_DISTRO_DEFAULTS=y \ No newline at end of file diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 02b2462..b1344c6 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -34,3 +34,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_OF_LIBFDT=y +CONFIG_DISTRO_DEFAULTS=y \ No newline at end of file diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 52553f6..f794c08 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -34,3 +34,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_OF_LIBFDT=y +CONFIG_DISTRO_DEFAULTS=y \ No newline at end of file diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 11188b7..56cebe0 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -34,3 +34,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_OF_LIBFDT=y +CONFIG_DISTRO_DEFAULTS=y \ No newline at end of file diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index 05bf140..c150b97 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -34,3 +34,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_OF_LIBFDT=y +CONFIG_DISTRO_DEFAULTS=y \ No newline at end of file diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index bb081a2..dfd096d 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -34,3 +34,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_OF_LIBFDT=y +CONFIG_DISTRO_DEFAULTS=y \ No newline at end of file diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index 08e91c9..5e2e693 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -34,3 +34,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_OF_LIBFDT=y +CONFIG_DISTRO_DEFAULTS=y \ No newline at end of file diff --git a/doc/README.imx6 b/doc/README.imx6 index 1823fb2..36452f6 100644 --- a/doc/README.imx6 +++ b/doc/README.imx6 @@ -138,3 +138,50 @@ c The last "c" command tells kermit (from ckermit package in most distros) to switch from command line mode to communication mode, and when the script is finished, the U-Boot prompt is shown in the same shell. + +3. Using generic distro configuration +- + +In order to simplify the use of various images on various media +for imx6 boards, the configuration of the board must follow the +generic distro configuration (doc/README.distro). + +3.1. Setup uboot configuration for your board +- + +First, you have to set 'CONFIG_DISTRO_DEFAULTS=y' in your board defconfig + +Some mandatory variable are set in mx6_common.h but can be overwritten like: + - fdtfile with CONFIG_FDTFILE + - fdt_addr_r and fdt_addr with CONFIG_FDTADDR + - ramdisk_addr_r, ramdiskaddr CONFIG_RAMDISKADDR + +You also have to define BOOT_TARGET_DEVICES with available media. +For example added in include/configs/nitrogen6x.h: +#define
Re: [U-Boot] socfpga 2016.05, CV socdk Rev E1, SPL and u-boot fail when booting from QSPI
Hi!
> > We don't support quad mode in U-Boot . You mean not entering Quad mode
> > in Linux ?
> >
>
> Nope, there seems to be quad support in u-boot, from spi_flash.c (my patched
> version):
>
> #ifndef CONFIG_SPL_BUILD
> /* Look for the fastest read cmd */
> cmd = fls(params->e_rd_cmd & spi->mode_rx);
> if (cmd) {
> cmd = spi_read_cmds_array[cmd - 1];
> flash->read_cmd = cmd;
> } else {
> #endif
> /* Go for default supported read cmd */
> flash->read_cmd = CMD_READ_ARRAY_FAST;
> #ifndef CONFIG_SPL_BUILD
> }
>
> /* Not require to look for fastest only two write cmds yet */
> if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
> flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
> else
> #endif
> /* Go for default supported write cmd */
> flash->write_cmd = CMD_PAGE_PROGRAM;
>
> /* Set the quad enable bit - only for quad commands */
> if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
> (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
> (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
> ret = set_quad_mode(flash, idcode[0]);
> if (ret) {
> debug("SF: Fail to set QEB for %02x\n", idcode[0]);
> return -EINVAL;
> }
> }
>
> So there is a call to set_quad_mode that prevented the SPL to work
> in vanilla 2016.05.
Just for the record, I seen similar problems on is1 board, and they
also somehow magically went away.
One possibility was that SPL was too big, and the quad spi probing
pushed it over the limits.
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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