[U-Boot] BeagleboneBlack vboot from SPI flash difficulties

[Joe Desbonnet]

I've been trying to implement vboot from SPI flash on the BeagleBone Black
with only limited success. I'm working with u-boot 2016.07 and using the
instructions in beaglebone_vboot.txt (in doc directory).

So far: I've had no problem booting regular u-boot from SPI flash. I build
with  am335x_boneblack_defconfig with minor modifications: added SPI_BOOT
to the list of items on CONFIG_SYS_EXTRA_OPTIONS and added
CONFIG_SPI_FLASH_STMICRO=y to enable support for my SPI flash chip
(M25P16). The I use the following command sequence from the u-boot command
line to program the flash:

sf probe 0
sf erase 0 +8
mmc rescan
fatload mmc 0 ${loadaddr} MLO.byteswap
sf write ${loadaddr} 0 ${filesize}
fatload mmc 0 ${loadaddr} u-boot.img
sf write ${loadaddr} 0x2 ${filesize}

And this works nicely.

I also have had success with vboot enabled u-boot using
the beaglebone_vboot.txt instructions and booting from SD card.

*BUT*

when I copy MLO(.byteswap) and u-boot.img that works successfully on SD
card to SPI flash it fails to get past the Second Phase Loader:

U-Boot SPL 2016.07 (Aug 10 2016 - 16:06:39)
Trying to boot from SPI

U-Boot SPL 2016.07 (Aug 10 2016 - 16:06:39)
Trying to boot from SPI

... etc for ever

On an oscilloscope I can see what I'm sure is the SPL trying to loading
u-boot.img on the SPI bus. But it never gets as far as executing it.

So in summary, I've got SPI boot working and vboot working but I cannot
seem to combine both.

Any ideas what I'm doing wrong?

Thanks,
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[U-Boot] Older u-boot mangles UBI from ubinize 1.5.2

[J Mo]

Greetings

I am attempting to port LEDE/OpenWRT to a new device; the TRENDnet 
TEW-827DRU, which is a IPQ806X-based (AP148) system. It has a NAND flash 
for storage with a UBI (kernel + squashfs + ubifs).


When my system attempts to attach the UBI, I see the following error 
from linux:



[3.781181] ubi0: attaching mtd11
[3.835224] UBI: EOF marker found, PEBs from 40 will be erased
[3.835384] ubi0: scanning is finished
[3.840040] ubi0 error: ubi_read_volume_table: the layout volume was 
not found
[3.844072] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd11, 
error -22

[3.850897] UBI error: cannot attach mtd11



I took this to google and it turns out that Ram Chandra Jangir here had 
noted the same issue a few months back, and then I got lucky and saw his 
patches yesterday:


https://patchwork.ozlabs.org/patch/657285/
https://patchwork.ozlabs.org/patch/624733/



I emailed Ram and he sent me his boot log and it looks identical to 
mine, so I think it's the same issue. (thx again Ram!)


I tried re-flashing my UBI and tftpbooting my kernel before u-boot could 
ever get a chance to mangle it, and now I get much further, though I'm 
still not able to mount my rootfs for unknown reasons:


[3.772502] ubi0: attaching mtd11
[3.826477] UBI: EOF marker found, PEBs from 40 will be erased
[3.826638] ubi0: scanning is finished
[3.872936] ubi0: volume 2 ("rootfs_data") re-sized from 9 to 
430 LEBs

[3.873734] ubi0: attached mtd11 (name "rootfs", size 64 MiB)
[3.878347] ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 
126976 bytes
[3.884234] ubi0: min./max. I/O unit sizes: 2048/2048, sub-page 
size 2048
[3.890936] ubi0: VID header offset: 2048 (aligned 2048), data 
offset: 4096

[3.897849] ubi0: good PEBs: 512, bad PEBs: 0, corrupted PEBs: 0
[3.904627] ubi0: user volume: 3, internal volumes: 1, max. 
volumes count: 128
[3.910815] ubi0: max/mean erase counter: 1/0, WL threshold: 
4096, image sequence number: 2142265782
[3.917902] ubi0: available PEBs: 0, total reserved PEBs: 512, 
PEBs reserved for bad PEB handling: 40

[3.927275] ubi0: background thread "ubi_bgt0d" started, PID 54
[3.937007] block ubiblock0_1: created from ubi0:1(rootfs)
[3.942096] hctosys: unable to open rtc device (rtc0)
[3.956528] VFS: Cannot open root device "ubi0:rootfs" or 
unknown-block(31,11): error -2
[3.956556] Please append a correct "root=" boot option; here 
are the available partitions:




Any advice on this? Any background information that I can read up on? My 
google searches have not come up with much. Ram knew about this, but I 
don't know if it's otherwise a known issue.


The process works fine on the OEM system, so I assume this is some 
ubinize format change which is incompatible with the older u-boot. Or, 
the newer kernel code doesn't know how to deal with the UBI once the 
older u-boot has mangled/attached it.


Seems like a backwards incompatibility issue.

Just to be clear, my kernel is inside the UBI, so u-boot must attach the 
UBI and read the volume to boot.


Rebuilding and replacing my u-boot is probably not possible for now, 
though I do have the OEM source. My device has a jtag, but I have not 
tested it and that's out of my league.




Additional info below:

--

My u-boot version: U-Boot 2012.07 [Standard IPQ806X.LN,r40331]

The old OEM ubinize is 1.2 from mtd-utils-1.4.5.

The old OEM kernel is 3.4.103. New kernel is 4.4.15.

LEDE built from commit 21f460a5dbef5e3ec59e2032b5b113fe045b475f

The new LEDE ubinize version is 1.5.2. The ubinize command (via LEDE's 
ubinize-image.sh script) to build my image was (paths truncated for 
readability):


ubinize-image.sh  --kernel .../TEW827DRU-uImage .../root.squashfs 
.../lede-ipq806x-TEW827DRU-squashfs-factory.bin.tmp -p 128KiB -m 2048   -E 5


Notably the new LEDE ubinize command uses "-E 5" whereas the old OEM 
does not, but I don't think that's related.


The ubinize.ini file looked like:

[kernel]
mode=ubi
vol_id=0
vol_type=dynamic
vol_name=kernel
image=/.../TEW827DRU-uImage
[rootfs]
mode=ubi
vol_id=1
vol_type=dynamic
vol_name=rootfs
image=/.../root.squashfs
[rootfs_data]
mode=ubi
vol_id=2
vol_type=dynamic
vol_name=rootfs_data
vol_size=1MiB
vol_flags=autoresize


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[U-Boot] [PATCH v3 02/27] sf: Remove e_rd_cmd from param table

[Jagan Teki]

e_rd_cmd is maintained separately for fastest read command code,
since the read commands are computed normally this e_rd_cmd
is not required in spi_flash_params table.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Cc: Vignesh R 
Cc: Mugunthan V N 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h |  18 +---
 drivers/mtd/spi/sf_params.c   | 200 +-
 2 files changed, 101 insertions(+), 117 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index c5cb791..71ba1a6 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -20,21 +20,6 @@ enum spi_dual_flash {
SF_DUAL_PARALLEL_FLASH  = BIT(1),
 };
 
-/* Enum list - Full read commands */
-enum spi_read_cmds {
-   ARRAY_SLOW  = BIT(0),
-   ARRAY_FAST  = BIT(1),
-   DUAL_OUTPUT_FAST= BIT(2),
-   QUAD_OUTPUT_FAST= BIT(3),
-   DUAL_IO_FAST= BIT(4),
-   QUAD_IO_FAST= BIT(5),
-};
-
-/* Normal - Extended - Full command set */
-#define RD_NORM(ARRAY_SLOW | ARRAY_FAST)
-#define RD_EXTN(RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
-#define RD_FULL(RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
-
 /* sf param flags */
 enum {
 #ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS
@@ -51,6 +36,7 @@ enum {
RD_QUADIO   = BIT(7),
RD_DUALIO   = BIT(8),
 };
+#define RD_FULLRD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO
 
 enum spi_nor_option_flags {
SNOR_F_SST_WR   = BIT(0),
@@ -145,7 +131,6 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
  * @sector_size:   Isn't necessarily a sector size from vendor,
  * the size listed here is what works with CMD_ERASE_64K
  * @nr_sectors:No.of sectors on this device
- * @e_rd_cmd:  Enum list for read commands
  * @flags: Important param, for flash specific behaviour
  */
 struct spi_flash_params {
@@ -154,7 +139,6 @@ struct spi_flash_params {
u16 ext_jedec;
u32 sector_size;
u32 nr_sectors;
-   u8 e_rd_cmd;
u16 flags;
 };
 
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 70ca236..5b50114 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -15,122 +15,122 @@
 /* SPI/QSPI flash device params structure */
 const struct spi_flash_params spi_flash_params_table[] = {
 #ifdef CONFIG_SPI_FLASH_ATMEL  /* ATMEL */
-   {"AT45DB011D", 0x1f2200, 0x0,   64 * 1024, 4, RD_NORM,  
SECT_4K},
-   {"AT45DB021D", 0x1f2300, 0x0,   64 * 1024, 8, RD_NORM,  
SECT_4K},
-   {"AT45DB041D", 0x1f2400, 0x0,   64 * 1024, 8, RD_NORM,  
SECT_4K},
-   {"AT45DB081D", 0x1f2500, 0x0,   64 * 1024,16, RD_NORM,  
SECT_4K},
-   {"AT45DB161D", 0x1f2600, 0x0,   64 * 1024,32, RD_NORM,  
SECT_4K},
-   {"AT45DB321D", 0x1f2700, 0x0,   64 * 1024,64, RD_NORM,  
SECT_4K},
-   {"AT45DB641D", 0x1f2800, 0x0,   64 * 1024,   128, RD_NORM,  
SECT_4K},
-   {"AT25DF321A", 0x1f4701, 0x0,   64 * 1024,64, RD_NORM,  
SECT_4K},
-   {"AT25DF321",  0x1f4700, 0x0,   64 * 1024,64, RD_NORM,  
SECT_4K},
-   {"AT26DF081A", 0x1f4501, 0x0,   64 * 1024,16, RD_NORM,  
SECT_4K},
+   {"AT45DB011D", 0x1f2200, 0x0,   64 * 1024, 4, SECT_4K},
+   {"AT45DB021D", 0x1f2300, 0x0,   64 * 1024, 8, SECT_4K},
+   {"AT45DB041D", 0x1f2400, 0x0,   64 * 1024, 8, SECT_4K},
+   {"AT45DB081D", 0x1f2500, 0x0,   64 * 1024,16, SECT_4K},
+   {"AT45DB161D", 0x1f2600, 0x0,   64 * 1024,32, SECT_4K},
+   {"AT45DB321D", 0x1f2700, 0x0,   64 * 1024,64, SECT_4K},
+   {"AT45DB641D", 0x1f2800, 0x0,   64 * 1024,   128, SECT_4K},
+   {"AT25DF321A", 0x1f4701, 0x0,   64 * 1024,64, SECT_4K},
+   {"AT25DF321",  0x1f4700, 0x0,   64 * 1024,64, SECT_4K},
+   {"AT26DF081A", 0x1f4501, 0x0,   64 * 1024,16, SECT_4K},
 #endif
 #ifdef CONFIG_SPI_FLASH_EON/* EON */
-   {"EN25Q32B",   0x1c3016, 0x0,   64 * 1024,64, RD_NORM,  
  0},
-   {"EN25Q64",0x1c3017, 0x0,   64 * 1024,   128, RD_NORM,  
SECT_4K},
-   {"EN25Q128B",  0x1c3018, 0x0,   64 * 1024,   256, RD_NORM,  
  0},
-   {"EN25S64",0x1c3817, 0x0,   64 * 1024,   128, RD_NORM,  
  0},
+   {"EN25Q32B",   0x1c3016, 0x0,   64 * 1024,64, 0},
+   {"EN25Q64",0x1c3017, 0x0,   64 * 1024,  

[U-Boot] [PATCH v3 10/27] sf: Rename spi_flash_params => spi_flash_info

[Jagan Teki]

Renamed for more readability
- spi_flash_params => spi_flash_info
- params => info

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sandbox.c |  6 +++---
 drivers/mtd/spi/sf_internal.h | 10 +-
 drivers/mtd/spi/sf_params.c   |  2 +-
 drivers/mtd/spi/spi_flash.c   | 46 +--
 4 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index f59134f..cecebb0 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -88,7 +88,7 @@ struct sandbox_spi_flash {
/* The current flash status (see STAT_XXX defines above) */
u16 status;
/* Data describing the flash we're emulating */
-   const struct spi_flash_params *data;
+   const struct spi_flash_info *data;
/* The file on disk to serv up data from */
int fd;
 };
@@ -112,7 +112,7 @@ static int sandbox_sf_probe(struct udevice *dev)
struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
const char *file;
size_t len, idname_len;
-   const struct spi_flash_params *data;
+   const struct spi_flash_info *data;
struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
struct sandbox_state *state = state_get_current();
struct udevice *bus = dev->parent;
@@ -168,7 +168,7 @@ static int sandbox_sf_probe(struct udevice *dev)
}
debug("%s: device='%s'\n", __func__, spec);
 
-   for (data = spi_flash_params_table; data->name; data++) {
+   for (data = spi_flash_ids; data->name; data++) {
len = strlen(data->name);
if (idname_len != len)
continue;
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 966fd21..bb5251d 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -104,11 +104,11 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
 #define CMD_SPANSION_WRAR  0x71 /* Write any device register */
 #endif
 
-#define JEDEC_ID(params)   (((params)->id[1]) << 8 | ((params)->id[2]))
-#define JEDEC_EXT(params)  (((params)->id[3]) << 8 | ((params)->id[4]))
+#define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
+#define JEDEC_EXT(info)(((info)->id[3]) << 8 | ((info)->id[4]))
 
 /**
- * struct spi_flash_params - SPI/QSPI flash device params structure
+ * struct spi_flash_info - SPI/QSPI flash device params structure
  *
  * @name:  Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
  * @sector_size:   Isn't necessarily a sector size from vendor,
@@ -116,7 +116,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
  * @nr_sectors:No.of sectors on this device
  * @flags: Important param, for flash specific behaviour
  */
-struct spi_flash_params {
+struct spi_flash_info {
const char *name;
 
/*
@@ -144,7 +144,7 @@ struct spi_flash_params {
 #define RD_FULL(RD_QUAD | RD_DUAL | RD_QUADIO | 
RD_DUALIO)
 };
 
-extern const struct spi_flash_params spi_flash_params_table[];
+extern const struct spi_flash_info spi_flash_ids[];
 
 /* Send a single-byte command to the device and read the response */
 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 70d9e18..7fcc3bc 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -28,7 +28,7 @@
.flags = (_flags),
 
 /* SPI/QSPI flash device params structure */
-const struct spi_flash_params spi_flash_params_table[] = {
+const struct spi_flash_info spi_flash_ids[] = {
 #ifdef CONFIG_SPI_FLASH_ATMEL  /* ATMEL */
{"AT45DB011D", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
{"AT45DB021D", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) },
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index e979b8e..099714e 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -924,11 +924,11 @@ static int micron_quad_enable(struct spi_flash *flash)
 }
 #endif
 
-static const struct spi_flash_params *spi_flash_read_id(struct spi_flash 
*flash)
+static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
 {
int tmp;
u8  id[5];
-   const struct spi_flash_params   *params;
+   const struct spi_flash_info *info;
 
tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, 5);
if (tmp < 0) {
@@ -936,11 +936,11 @@ static const struct spi_flash_params 
*spi_flash_read_id(struct spi_flash *flash)
return ERR_PTR(tmp);
}
 
-   params = spi_flash_params_table;
-   for (

[U-Boot] [PATCH v3 12/27] sf: Simplify lock ops detection code

[Jagan Teki]

Simplify the flash_lock ops detection code and added
meaningful comment.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/spi_flash.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index daa9014..b92b0bf 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1117,19 +1117,15 @@ int spi_flash_scan(struct spi_flash *flash)
flash->read = spi_flash_cmd_read_ops;
 #endif
 
-   /* lock hooks are flash specific - assign them based on idcode0 */
-   switch (JEDEC_MFR(info)) {
 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
-   case SPI_FLASH_CFI_MFR_STMICRO:
-   case SPI_FLASH_CFI_MFR_SST:
+   /* NOR protection support for STmicro/Micron chips and similar */
+   if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO ||
+   JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) {
flash->flash_lock = stm_lock;
flash->flash_unlock = stm_unlock;
flash->flash_is_locked = stm_is_locked;
-#endif
-   break;
-   default:
-   debug("SF: Lock ops not supported for %02x flash\n", 
JEDEC_MFR(info));
}
+#endif
 
/* Compute the flash size */
flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
-- 
2.7.4

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[U-Boot] [PATCH v3 19/27] sf: Add INFO6 flash_info macro

[Jagan Teki]

INFO6 is for tabulating 6 byte flash parts, Ex: S25FS256S_64K

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_params.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 8a2a6b2..344d9c9 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -23,6 +23,21 @@
.page_size = 256,   \
.flags = (_flags),
 
+#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
+   .id = { \
+   ((_jedec_id) >> 16) & 0xff, \
+   ((_jedec_id) >> 8) & 0xff,  \
+   (_jedec_id) & 0xff, \
+   ((_ext_id) >> 16) & 0xff,   \
+   ((_ext_id) >> 8) & 0xff,\
+   (_ext_id) & 0xff,   \
+   },  \
+   .id_len = 6,\
+   .sector_size = (_sector_size),  \
+   .n_sectors = (_n_sectors),  \
+   .page_size = 256,   \
+   .flags = (_flags),
+
 const struct spi_flash_info spi_flash_ids[] = {
 #ifdef CONFIG_SPI_FLASH_ATMEL  /* ATMEL */
{"AT45DB011D", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
-- 
2.7.4

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[U-Boot] [PATCH v3 16/27] sf: nr_sectors -> n_sectors

[Jagan Teki]

Rename nr_sectors as n_sectors to sync with Linux.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sandbox.c | 2 +-
 drivers/mtd/spi/sf_internal.h | 2 +-
 drivers/mtd/spi/sf_params.c   | 2 +-
 drivers/mtd/spi/spi_flash.c   | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 09ce783..4944059 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -289,7 +289,7 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash 
*sbsf, const u8 *rx,
/* we only support erase here */
if (sbsf->cmd == CMD_ERASE_CHIP) {
sbsf->erase_size = sbsf->data->sector_size *
-   sbsf->data->nr_sectors;
+   sbsf->data->n_sectors;
} else if (sbsf->cmd == CMD_ERASE_4K && (flags & SECT_4K)) {
sbsf->erase_size = 4 << 10;
} else if (sbsf->cmd == CMD_ERASE_64K && !(flags & SECT_4K)) {
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 4a88cf7..527c252 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -124,7 +124,7 @@ struct spi_flash_info {
 * necessarily called a "sector" by the vendor.
 */
u32 sector_size;
-   u32 nr_sectors;
+   u32 n_sectors;
 
u16 page_size;
 
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 7314455..8a2a6b2 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -19,7 +19,7 @@
},  \
.id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),   
\
.sector_size = (_sector_size),  \
-   .nr_sectors = (_n_sectors), \
+   .n_sectors = (_n_sectors),  \
.page_size = 256,   \
.flags = (_flags),
 
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index b92b0bf..0777bb5 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1143,7 +1143,7 @@ int spi_flash_scan(struct spi_flash *flash)
}
flash->page_size <<= flash->shift;
flash->sector_size = info->sector_size << flash->shift;
-   flash->size = flash->sector_size * info->nr_sectors << flash->shift;
+   flash->size = flash->sector_size * info->n_sectors << flash->shift;
 #ifdef CONFIG_SF_DUAL_FLASH
if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
flash->size <<= 1;
-- 
2.7.4

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[U-Boot] [PATCH v3 17/27] sf: Add SPI_FLASH_MAX_ID_LEN

[Jagan Teki]

Add id length of 5 bytes numerical value to macro.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h | 3 ++-
 drivers/mtd/spi/spi_flash.c   | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 527c252..437ac8a 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -108,6 +108,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
 #define JEDEC_MFR(info)((info)->id[0])
 #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
 #define JEDEC_EXT(info)(((info)->id[3]) << 8 | ((info)->id[4]))
+#define SPI_FLASH_MAX_ID_LEN   5
 
 struct spi_flash_info {
const char  *name;
@@ -117,7 +118,7 @@ struct spi_flash_info {
 * The first three bytes are the JEDIC ID.
 * JEDEC ID zero means "no ID" (mostly older chips).
 */
-   u8  id[5];
+   u8  id[SPI_FLASH_MAX_ID_LEN];
u8  id_len;
 
/* The size listed here is what works with SPINOR_OP_SE, which isn't
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 0777bb5..ba884d7 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -928,10 +928,10 @@ static int micron_quad_enable(struct spi_flash *flash)
 static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
 {
int tmp;
-   u8  id[5];
+   u8  id[SPI_FLASH_MAX_ID_LEN];
const struct spi_flash_info *info;
 
-   tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, 5);
+   tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN);
if (tmp < 0) {
printf("SF: error %d reading JEDEC ID\n", tmp);
return ERR_PTR(tmp);
-- 
2.7.4

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[U-Boot] [PATCH v3 13/27] sf: sandbox: Fix ID exctract from spi_flash_info

[Jagan Teki]

This patch fix the id exctract from spi_flash_info ids.

Cc: Simon Glass 
Cc: Bin Meng 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sandbox.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index cecebb0..09ce783 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -359,7 +359,8 @@ static int sandbox_sf_xfer(struct udevice *dev, unsigned 
int bitlen,
debug(" id: off:%u tx:", sbsf->off);
if (sbsf->off < IDCODE_LEN) {
/* Extract correct byte from ID 0x00aabbcc */
-   id = sbsf->data->jedec >>
+   id = ((JEDEC_MFR(sbsf->data) << 16) |
+   JEDEC_ID(sbsf->data)) >>
(8 * (IDCODE_LEN - 1 - sbsf->off));
} else {
id = 0;
-- 
2.7.4

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Re: [U-Boot] [PATCH 06/21] imx: timer: update gpt driver for i.MX6ULL

[Stefano Babic]

On 11/08/2016 08:02, Peng Fan wrote:
> The i.MX6ULL's GPT supportting taking OSC as clock source.
> Add i.MX6ULL support.
> 
> Signed-off-by: Peng Fan 
> Signed-off-by: Ye Li 
> Cc: Stefano Babic 
> ---
>  arch/arm/imx-common/timer.c | 7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
> index a01590c..fb1b693 100644
> --- a/arch/arm/imx-common/timer.c
> +++ b/arch/arm/imx-common/timer.c
> @@ -44,7 +44,8 @@ static inline int gpt_has_clk_source_osc(void)
>  {
>  #if defined(CONFIG_MX6)
>   if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
> - is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul())
> + is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
> + is_mx6ull())
>   return 1;
>  
>   return 0;
> @@ -83,8 +84,8 @@ int timer_init(void)
>   if (gpt_has_clk_source_osc()) {
>   i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
>  
> - /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
> - if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) {
> + /* For DL/S, SX, UL, ULL set 24Mhz OSC Enable bit and prescaler 
> */
> + if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull()) {
>   i |= GPTCR_24MEN;
>  
>   /* Produce 3Mhz clock */
> 
Reviewed-by: Stefano Babic 

Best regards,
Stefano Babic


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[U-Boot] [PATCH] defconfig: am43xx_evm: enable eth driver model

[Mugunthan V N]

Enable eth driver model for am43xx_evm as cpsw supports
driver model.

This was already added with the commit bc705ea1cf12 but with
commit 4c4e3b37750f to add fit support CONFIG_DM_ETH was missed.

Signed-off-by: Mugunthan V N 
Cc: Lokesh Vutla 
---
 configs/am43xx_evm_defconfig| 1 +
 configs/am43xx_hs_evm_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index b3fe269..56782f1 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -56,3 +56,4 @@ CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_DM_I2C=y
+CONFIG_DM_ETH=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index c8ce723..1553196 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -59,3 +59,4 @@ CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_DM_I2C=y
+CONFIG_DM_ETH=y
-- 
2.9.2.664.ga0a1831

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Re: [U-Boot] [PATCH 07/21] imx: mx6ull: skip setting ahb clock

[Stefano Babic]

On 11/08/2016 08:02, Peng Fan wrote:
> Rom already initialized clock at 396M and 132M for arm core and ahb,
> so skip setting them again in U-Boot.
> 
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> ---
>  arch/arm/cpu/armv7/mx6/soc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index 88fcfdc..af7fca5 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -343,7 +343,7 @@ int arch_cpu_init(void)
>*/
>   init_bandgap();
>  
> - if (!IS_ENABLED(CONFIG_MX6UL)) {
> + if (!is_mx6ul() && !is_mx6ull()) {
>   /*
>* When low freq boot is enabled, ROM will not set AHB
>* freq, so we need to ensure AHB freq is 132MHz in such
> 
Reviewed-by: Stefano Babic 

Best regards,
Stefano Babic


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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [U-Boot] [PULL] u-boot-usb/master

[Marek Vasut]

The following changes since commit 2863a9bfc29092be37f8beee230883367b057065:

  Merge git://git.denx.de/u-boot-rockchip (2016-08-06 11:38:14 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-usb.git master

for you to fetch changes up to 76b2fad775ee3cb58788b11454655ba5a244ac56:

  eth: asix88179: Add support for the driver model (2016-08-09 12:52:05
+0200)


Alban Bedel (4):
  eth: asix88179: Add VID:DID for Cypress GX3 USB Ethernet Adapter
  eth: asix88179: Fix receiving on big endian system
  eth: asix88179: Prepare supporting the driver model
  eth: asix88179: Add support for the driver model

Masahiro Yamada (3):
  usb: add CONFIG_USB_OHCI_HCD in Kconfig
  usb: add CONFIG_USB_UHCI_HCD in Kconfig
  usb: add (move) CONFIG_USB_HOST to Kconfig

Peng Fan (1):
  dm: ehci-mx6: support driver model

Rajesh Bhagat (5):
  drivers: usb: fsl: Make function for initialization to use in
CONFIG_DM_USB
  usb: ehci: fsl: Add code to use CONFIG_DM_USB
  usb: xhci: fsl: Add code to use CONFIG_DM_USB
  dm: ls1021a: dts: Update USB 3.0 node to support DM USB
  arm: ls1021a: Enable CONFIG_DM_USB in defconfigs

Stefan Roese (1):
  net: usb: r8152: Add DM support

 arch/arm/dts/ls1021a.dtsi|   2 +-

 configs/axs103_defconfig |   1 +

 configs/ls1021aqds_ddr4_nor_defconfig|   1 +

 configs/ls1021aqds_ddr4_nor_lpuart_defconfig |   1 +

 configs/ls1021aqds_nor_defconfig |   1 +

 configs/ls1021aqds_nor_lpuart_defconfig  |   1 +

 drivers/usb/eth/asix88179.c  | 263
+---
 drivers/usb/eth/r8152.c  | 237
+++
 drivers/usb/eth/r8152.h  |   4 ++
 drivers/usb/eth/r8152_fw.c   |   2 +
 drivers/usb/host/Kconfig |  59 +
 drivers/usb/host/ehci-fsl.c  | 194
+---
 drivers/usb/host/ehci-mx6.c  | 144
+-
 drivers/usb/host/xhci-fsl.c  |  83
-
 include/configs/am43xx_evm.h |   1 -
 include/configs/am57xx_evm.h |   1 -
 include/configs/cm_t43.h |   1 -
 include/configs/cm_t54.h |   1 -
 include/configs/dra7xx_evm.h |   1 -
 include/configs/duovero.h|   1 -
 include/configs/omap4_panda.h|   1 -
 include/configs/omap5_uevm.h |   1 -
 22 files changed, 885 insertions(+), 116 deletions(-)
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Re: [U-Boot] [PATCH] configs: dra7xx_evm: enable eth driver model

[Lokesh Vutla]

On Wednesday 10 August 2016 10:05 PM, Mugunthan V N wrote:
> Enable eth driver model for dra7xx_evm as cpsw supports
> driver model.
> 
> This was already added with the commit 641b936fa5ba but with
> commit bd7245849f7c to add fit support CONFIG_DM_ETH was missed.
> 
> Signed-off-by: Mugunthan V N 
> Cc: Lokesh Vutla 

Acked-by: Lokesh Vutla 

Thanks and regards,
Lokesh

> ---
>  configs/dra7xx_evm_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
> index 81d2a0e..e5f813d 100644
> --- a/configs/dra7xx_evm_defconfig
> +++ b/configs/dra7xx_evm_defconfig
> @@ -59,3 +59,4 @@ CONFIG_SPL_LOAD_FIT=y
>  CONFIG_OF_LIST="dra7-evm dra72-evm"
>  CONFIG_DM_I2C=y
>  CONFIG_PCF8575_GPIO=y
> +CONFIG_DM_ETH=y
> 
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[U-Boot] [PATCH v2 5/7] smbios: Expose in efi_loader as table

[Alexander Graf]

We can pass SMBIOS easily as EFI configuration table to an EFI payload. This
patch adds enablement for that case.

While at it, we also enable SMBIOS generation for ARM systems, since they 
support
EFI_LOADER.

Signed-off-by: Alexander Graf 

---

v1 -> v2:

  - fix whitespace
---
 cmd/bootefi.c|  3 +++
 include/efi_api.h|  4 
 include/efi_loader.h |  2 ++
 include/smbios.h |  1 +
 lib/Kconfig  |  4 ++--
 lib/smbios.c | 36 
 6 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 53a6ee3..e241b7d 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -205,6 +205,9 @@ static unsigned long do_bootefi_exec(void *efi, void *fdt)
if (!memcmp(bootefi_device_path[0].str, "N\0e\0t", 6))
loaded_image_info.device_handle = nethandle;
 #endif
+#ifdef CONFIG_GENERATE_SMBIOS_TABLE
+   efi_smbios_register();
+#endif
 
/* Initialize EFI runtime services */
efi_reset_system_init();
diff --git a/include/efi_api.h b/include/efi_api.h
index f572b88..bdb600e 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -201,6 +201,10 @@ struct efi_runtime_services {
EFI_GUID(0xb1b621d5, 0xf19c, 0x41a5, \
 0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0)
 
+#define SMBIOS_TABLE_GUID \
+   EFI_GUID(0xeb9d2d31, 0x2d88, 0x11d3,  \
+0x9a, 0x16, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+
 struct efi_configuration_table
 {
efi_guid_t guid;
diff --git a/include/efi_loader.h b/include/efi_loader.h
index ac8b77a..b0e8a7f 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -85,6 +85,8 @@ int efi_disk_register(void);
 int efi_gop_register(void);
 /* Called by bootefi to make the network interface available */
 int efi_net_register(void **handle);
+/* Called by bootefi to make SMBIOS tables available */
+void efi_smbios_register(void);
 
 /* Called by networking code to memorize the dhcp ack package */
 void efi_net_set_dhcp_ack(void *pkt, int len);
diff --git a/include/smbios.h b/include/smbios.h
index 5962d4c..fb6396a 100644
--- a/include/smbios.h
+++ b/include/smbios.h
@@ -55,6 +55,7 @@ struct __packed smbios_entry {
 #define BIOS_CHARACTERISTICS_SELECTABLE_BOOT   (1 << 16)
 
 #define BIOS_CHARACTERISTICS_EXT1_ACPI (1 << 0)
+#define BIOS_CHARACTERISTICS_EXT1_UEFI (1 << 3)
 #define BIOS_CHARACTERISTICS_EXT2_TARGET   (1 << 2)
 
 struct __packed smbios_type0 {
diff --git a/lib/Kconfig b/lib/Kconfig
index 5a14530..d7f75fe 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -150,12 +150,12 @@ config SPL_OF_LIBFDT
  version of the device tree.
 
 menu "System tables"
-   depends on !EFI && !SYS_COREBOOT
+   depends on (!EFI && !SYS_COREBOOT) || (ARM && EFI_LOADER)
 
 config GENERATE_SMBIOS_TABLE
bool "Generate an SMBIOS (System Management BIOS) table"
default y
-   depends on X86
+   depends on X86 || EFI_LOADER
help
  The System Management BIOS (SMBIOS) specification addresses how
  motherboard and system vendors present management information about
diff --git a/lib/smbios.c b/lib/smbios.c
index 8dfd486..4d85155 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -7,10 +7,13 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
+#ifdef CONFIG_X86
 #include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -79,14 +82,20 @@ static int smbios_write_type0(uintptr_t *current, int 
handle)
t->vendor = smbios_add_string(t->eos, "U-Boot");
t->bios_ver = smbios_add_string(t->eos, PLAIN_VERSION);
t->bios_release_date = smbios_add_string(t->eos, U_BOOT_DMI_DATE);
+#ifdef CONFIG_ROM_SIZE
t->bios_rom_size = (CONFIG_ROM_SIZE / 65536) - 1;
+#endif
t->bios_characteristics = BIOS_CHARACTERISTICS_PCI_SUPPORTED |
  BIOS_CHARACTERISTICS_SELECTABLE_BOOT |
  BIOS_CHARACTERISTICS_UPGRADEABLE;
 #ifdef CONFIG_GENERATE_ACPI_TABLE
t->bios_characteristics_ext1 = BIOS_CHARACTERISTICS_EXT1_ACPI;
 #endif
+#ifdef CONFIG_EFI_LOADER
+   t->bios_characteristics_ext1 |= BIOS_CHARACTERISTICS_EXT1_UEFI;
+#endif
t->bios_characteristics_ext2 = BIOS_CHARACTERISTICS_EXT2_TARGET;
+
t->bios_major_release = 0xff;
t->bios_minor_release = 0xff;
t->ec_major_release = 0xff;
@@ -152,6 +161,7 @@ static int smbios_write_type3(uintptr_t *current, int 
handle)
return len;
 }
 
+#ifdef CONFIG_X86
 static int smbios_write_type4(uintptr_t *current, int handle)
 {
struct smbios_type4 *t = (struct smbios_type4 *)*current;
@@ -184,6 +194,7 @@ static int smbios_write_type4(uintptr_t *current, int 
handle)
 
return len;
 }
+#endif
 
 static int smbios_write_type32(uintptr_t *current, int handle)
 {
@@ -216,7 +227,9 @@ static smbios_write_type smbios_write_funcs[] = {
smbios_write_type1,
smbios_write_type2,
smbios_write_type3,
+#i

[U-Boot] [PATCH] getting ubifs to run

[Marco]

Signed-off-by: Marco 
---
 arch/microblaze/include/asm/atomic.h | 114 +++
 arch/microblaze/include/asm/bitops.h |   8 +--
 fs/ubifs/io.c|   2 +-
 fs/ubifs/log.c   |  99 ++
 fs/ubifs/lpt_commit.c|  21 +++
 5 files changed, 239 insertions(+), 5 deletions(-)
 create mode 100644 arch/microblaze/include/asm/atomic.h

diff --git a/arch/microblaze/include/asm/atomic.h 
b/arch/microblaze/include/asm/atomic.h
new file mode 100644
index 000..2872149
--- /dev/null
+++ b/arch/microblaze/include/asm/atomic.h
@@ -0,0 +1,114 @@
+/*
+ *  linux/include/asm-arm/atomic.h
+ *
+ *  Copyright (c) 1996 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996RMK Created
+ *   13-04-1997RMK Made functions atomic!
+ *   07-12-1997RMK Upgraded for v2.1.
+ *   26-08-1998PJB Added #ifdef __KERNEL__
+ */
+#ifndef __ASM_ARM_ATOMIC_H
+#define __ASM_ARM_ATOMIC_H
+
+#ifdef CONFIG_SMP
+#error SMP not supported
+#endif
+
+typedef struct { volatile int counter; } atomic_t;
+
+#define ATOMIC_INIT(i) { (i) }
+
+#ifdef __KERNEL__
+#include 
+
+#define atomic_read(v) ((v)->counter)
+#define atomic_set(v,i)(((v)->counter) = (i))
+
+
+
+
+static inline void atomic_add(int i, volatile atomic_t *v)
+{
+   unsigned long flags = 0;
+
+   local_irq_save(flags);
+   v->counter += i;
+   local_irq_restore(flags);
+}
+
+static inline void atomic_sub(int i, volatile atomic_t *v)
+{
+   unsigned long flags = 0;
+
+   local_irq_save(flags);
+   v->counter -= i;
+   local_irq_restore(flags);
+}
+
+static inline void atomic_inc(volatile atomic_t *v)
+{
+   unsigned long flags = 0;
+
+   local_irq_save(flags);
+   v->counter += 1;
+   local_irq_restore(flags);
+}
+
+static inline void atomic_dec(volatile atomic_t *v)
+{
+   unsigned long flags = 0;
+
+   local_irq_save(flags);
+   v->counter -= 1;
+   local_irq_restore(flags);
+}
+
+static inline int atomic_dec_and_test(volatile atomic_t *v)
+{
+   unsigned long flags = 0;
+   int val;
+
+   local_irq_save(flags);
+   val = v->counter;
+   v->counter = val -= 1;
+   local_irq_restore(flags);
+
+   return val == 0;
+}
+
+static inline int atomic_add_negative(int i, volatile atomic_t *v)
+{
+   unsigned long flags = 0;
+   int val;
+
+   local_irq_save(flags);
+   val = v->counter;
+   v->counter = val += i;
+   local_irq_restore(flags);
+
+   return val < 0;
+}
+
+static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
+{
+   unsigned long flags = 0;
+
+   local_irq_save(flags);
+   *addr &= ~mask;
+   local_irq_restore(flags);
+}
+
+/* Atomic operations are already serializing on ARM */
+#define smp_mb__before_atomic_dec()barrier()
+#define smp_mb__after_atomic_dec() barrier()
+#define smp_mb__before_atomic_inc()barrier()
+#define smp_mb__after_atomic_inc() barrier()
+
+#endif
+#endif
diff --git a/arch/microblaze/include/asm/bitops.h 
b/arch/microblaze/include/asm/bitops.h
index 2cab2ac..b3b17b9 100644
--- a/arch/microblaze/include/asm/bitops.h
+++ b/arch/microblaze/include/asm/bitops.h
@@ -204,10 +204,10 @@ static inline int __test_bit(int nr, volatile void *addr)
return ((mask & *a) != 0);
 }
 
-#define test_bit(nr,addr) \
-(__builtin_constant_p(nr) ? \
- __constant_test_bit((nr),(addr)) : \
- __test_bit((nr),(addr)))
+static inline int test_bit(int nr, const void * addr)
+{
+   return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
 
 #define find_first_zero_bit(addr, size) \
find_next_zero_bit((addr), (size), 0)
diff --git a/fs/ubifs/io.c b/fs/ubifs/io.c
index 51a95bb..685713e 100644
--- a/fs/ubifs/io.c
+++ b/fs/ubifs/io.c
@@ -847,6 +847,7 @@ out:
ubifs_dump_leb(c, wbuf->lnum);
return err;
 }
+#endif
 
 /**
  * ubifs_write_node - write node to the media.
@@ -885,7 +886,6 @@ int ubifs_write_node(struct ubifs_info *c, void *buf, int 
len, int lnum,
 
return err;
 }
-#endif
 
 /**
  * ubifs_read_node_wbuf - read node from the media or write-buffer.
diff --git a/fs/ubifs/log.c b/fs/ubifs/log.c
index a07fdef..10302b9 100644
--- a/fs/ubifs/log.c
+++ b/fs/ubifs/log.c
@@ -743,3 +743,102 @@ static int dbg_check_bud_bytes(struct ubifs_info *c)
 
return err;
 }
+
+
+/**
+ * ubifs_commit_required - set commit state to "required".
+ * @c: UBIFS file-system description object
+ *
+ * This function is called if a commit is required but cannot be done from the
+ * calling function, so it is just flagged instead.
+ */
+void ubifs_commit_required(struct ubifs_info *c)
+{
+   spin_lock(&c->cs_lock);
+   switch (c->cmt_state

Re: [U-Boot] [PATCH] net: asix: Fix ASIX 88772B with driver model

[Alban Bedel]

On Thu, 11 Aug 2016 11:26:23 +0200
Marek Vasut  wrote:

> On 08/11/2016 10:52 AM, Alban Bedel wrote:
> > On Tue, 9 Aug 2016 14:32:14 +0200
> > Marek Vasut  wrote:
> > 
> >> On 08/09/2016 02:14 PM, Marcel Ziswiler wrote:
> >>> On Thu, 2016-08-04 at 11:12 +0200, Marek Vasut wrote:
>  On 08/04/2016 11:07 AM, Alban Bedel wrote:
> >
> > On Wed, 3 Aug 2016 15:23:30 +
> > Marcel Ziswiler  wrote:
> >
> >>
> >> On Wed, 2016-08-03 at 15:51 +0200, Marek Vasut wrote:
> >>>
> >>> On 08/03/2016 11:46 AM, Alban Bedel wrote:
> 
> 
>  On Wed, 3 Aug 2016 09:00:42 +0200
>  Marek Vasut  wrote:
> 
> >
> >
> > On 08/03/2016 07:32 AM, Alban Bedel wrote:
> >>
> >>
> >> Commit 147271209a9d ("net: asix: fix operation without
> >> eeprom")
> >> added a special handling for ASIX 88772B that enable
> >> another
> >> type of header. This break the driver in DM mode as the
> >> extra
> >> handling
> >> needed in the receive path is missing.
> > So add the extra handling ?
>  I can do that too, but I though u-boot preferred to avoid
>  useless
>  code.
> >>> Yes, if it is useless.
> >>>
> 
> 
> >
> >
> >>
> >>
> >> However this new header mode is not required and only
> >> seems to
> >> increase the code complexity, so this patch revert this
> >> part of
> >> commit 147271209a9d.
> > Why is it not required ?
>  It works fine without, since 2012. In fact this change is not
>  even
>  mentioned in the log of commit 147271209a9d, so I really
>  don't know
>  why
>  it was added in the first place. As can be seen in the revert
>  all
>  it
>  does is adding 2 bytes to the USB packets that are then just
>  skipped.
>  Seems pretty useless to me.
> >>> I would like to get some feedback on this from Marcel, since he
> >>> added
> >>> this stuff.
> >> Yes, sorry. I just came back from vacation and started looking
> >> into it
> >> now. As far as I remember on our hardware without this Ethernet
> >> did not
> >> quite work reliably. This also means that with driver model so
> >> far it
> >> does not work for us which I fed back to Simon once but so far
> >> this has
> >> not been resolved. That fix came from some early U-Boot work done
> >> by
> >> Antmicro way back and I am missing some of the history.
> > Then I'll do a new patch that just fix the driver model receive
> > path.
>  Hold on. Marcel, can you maybe test if removing this code has any
>  impact
>  on the behavior now ?
> >>>
> >>> Sorry for the delay. I tested Alban's patch now both on Toradex Colibri
> >>> T20 as well as T30 and its on-module ASIX USB-to-Ethernet chip actually
> >>> works perfectly aside from the occasional EHCI timed out on TD -
> >>> token=0x88008d80 Rx: failed to receive: -5 message which last I checked
> >>> with Simon is still unresolved but was already there long before any of
> >>> the driver model work started.
> >>>
> >>> Tested-by: Marcel Ziswiler 
> >>> Tested-on: Colibri T20/T30 on Colibri Evaluation Board
> >>>
> > 
> > Will this be applied for the upcoming release?
> 
> Yeah. Why the hurry though ?

I was just wondering because all the other patches I submitted have
been applied but this one still seems to be on hold.

Alban


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Re: [U-Boot] [PATCH] defconfig: am43xx_evm: enable eth driver model

[Tom Rini]

On Thu, Aug 11, 2016 at 02:27:04PM +0530, Mugunthan V N wrote:

> Enable eth driver model for am43xx_evm as cpsw supports
> driver model.
> 
> This was already added with the commit bc705ea1cf12 but with
> commit 4c4e3b37750f to add fit support CONFIG_DM_ETH was missed.
> 
> Signed-off-by: Mugunthan V N 
> Cc: Lokesh Vutla 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH v3] drivers: net: cpsw: always flush cache of size aligned to PKTALIGN

[Tom Rini]

On Thu, Aug 11, 2016 at 01:00:59PM +0530, Lokesh Vutla wrote:

> cpsw tries to flush dcache which is not in the range of PKTALIGN.
> Because of this the following warning comes while flushing:
> 
> CACHE: Misaligned operation at range [dffecec0, dffed016]
> 
> Fix it by flushing cache of size aligned to PKTALIGN.
> 
> Signed-off-by: Lokesh Vutla 

Reviewed-by: Tom Rini 

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Re: [U-Boot] disabling mmc in spl when booting using bootrom

[Ziyuan Xu]

On 2016年08月11日 19:39, Sandy Patterson wrote:


On Thu, Aug 11, 2016 at 7:35 AM, Ziyuan Xu > wrote:




On 2016年08月11日 19:31, Sandy Patterson wrote:

Simon,

I am trying to format a patch to disable MMC in the SPL if
booting main u-boot using BOOTROM, therefore the SPL MMC isn't
needed.

Is the best solution to wrap every header file (rock2.h
firefly-rk3288.h, etc) with ifdefs on the BACK_TO_BROM define?
Or would it be better to move the SPL MMC define into
rk3288-common.h and just have chromebook_jerry undef it like
it does the SPL GPIO code.

With that change, enabling BOOT_TO_BROM shrinks the spl from
32K to 23K.

Note that, firefly-rk3288 use OF_PLATDATA, we will use
u-boot-spl-no-dtb.bin instead of u-boot-spl-dtb.bin, and the size
of u-boot-spl-no-dtb.bin is almost 23K.


The patch would apply if OF_PLATDATA is used too (Although I haven't 
tested it). It would just shrink the SPL more right because you don't 
need the MMC driver. I wasn't planning to change any of the defconfigs.

Okay, I'll have no objection to your doing it.



@Simon, I think we will update doc/README.rockchip if you insist
on OF_PLATDATA for firefly-rk3288. we no longer use
u-boot-spl-dtb.bin.:-)


Sandy







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Re: [U-Boot] [PATCH 0/2] efi_loader: Implement reset on RPi

[Alexander Graf]

On 08.08.16 23:44, Simon Glass wrote:
> Hi,
> 
> On 7 August 2016 at 10:59, Andreas Färber  wrote:
>> Am 14.07.2016 um 08:18 schrieb Alexander Graf:
 Am 14.07.2016 um 06:48 schrieb Andreas Färber :

 Hi Alex,

> Am 05.06.2016 um 23:17 schrieb Alexander Graf:
> If Linux finds an EFI implementation it always uses the EFI reset handler 
> to
> reboot or power down the system.

 Hm, I thought my powerdown issues on the Jetson TK1 were for lack of
 CONFIG_AS3277_RESET - sounds like it could be due to EFI instead?
>>>
>>> It depends. IIRC the TK1 is 32bit, where you're probably using grub2 which 
>>> is not efi Linux aware, but instead boots over the zImage protocol. In that 
>>> case Linux doesn't know about efi runtime services.
>>
>> We've confirmed in the meantime that the Jetson TK1 issues were
>> unrelated to EFI and could be worked around by enabling some as3722
>> kernel option.
>>
> Unfortunately we haven't implemented that one yet. In fact, while we 
> prepared
> for RTS handling, we never actually implemented a single user.
>
> This is going to change today. This simple patch set enables RTS reset 
> support
> for the RPi systems, allowing you to reboot and shut down the rpi if 
> booted
> via EFI.
>
> It also lays the groundwork to show how to implement that functionality 
> at all,
> so I expect more boards to follow.
>
> Alexander Graf (2):
>  efi_loader: Allow boards to implement get_time and reset_system
>  ARM: bcm283x: Implement EFI RTS reset_system
>
> arch/arm/mach-bcm283x/include/mach/wdog.h |   2 +-
> arch/arm/mach-bcm283x/reset.c |  59 +++--
> cmd/bootefi.c |   4 ++
> include/efi_loader.h  |  18 ++
> lib/efi_loader/efi_runtime.c  | 101 
> ++
> 5 files changed, 166 insertions(+), 18 deletions(-)

 This all looks very non-generic and would mean that every board will
 need to be patched individually, which is unrealistic to be tested by
 just the two of us.

 Can't you patch the reset_cpu() declaration (common.h/sysreset.h)
 instead of all its implementations? We might still need to patch
 individual implementations but I don't see why any reset_cpu()
 implementation should be in a different section than others.
>>>
>>> Hmm. There are 2 minor problems:
>>>
>>>   1) Efi also supports power off on top of reset
>>>   2) We would have to convert all boards at once, rather than one by one, 
>>> as we couldn't distinguish between efi aware and unaware ones
>>
>> I don't see why we would need to convert everything at once either way.
>>
>>>
>>> And one major issue:
>>>
>>> All device memory pointers used by the reset functions need to be marked as 
>>> such in the efi memory map and live relocated when entering runtime mode. 
>>> So we need to manually touch every function either way.
> 
> I'm worried about this. It means that any code used from this run-time
> needs to be so marked. This could be large tracts of U-Boot. In

We only need to mark the few bits that are actually executed and used
within RTS. That's usually just 2 or 3 functions.

Also, moving forward, we'll see more and more systems implement PSCI
which means we can implement a generic PSCI RTS for reset/shutdown.

> particular, as I have mentioned a few times, I think the UEFI tables
> should be 'live' and not just created before booting, which means that
> much of driver/core needs to be in the UEFI section.

I don't fully understand what you're aiming for here. The tables are
always static in a uEFI world. I don't see how they could get more
"live" than creating them right before boot.

> Should we just adjust it so that the whole of U-Boot is in there? How
> big is the UEFI run-time normally?

It's really not a problem of putting things in one section or another.
It's that if anything within a run time .text section tries to access
any memory, be it MMIO or .data memory, it will need to get relocated if
we want to be able to run it as RTS.

But really, the RTS interface is very very very slim. Take a look at
lib/efi_loader/efi_runtime.c. The only thing that could remotely pull in
more code is RTC/variable support. But I'm sure we can find a way to
solve that without pulling in all internal abstraction layers.

> 
>>>
>>> That mesns we could either make a generic, broken version. Or we just 
>>> convert one by one for systems that we can verify it on :). I hope that I 
>>> designed the APIs easily enough that people who are not us enable RTS 
>>> support on other platforms too :)
>>
>>
>> Ping! Anyone any comments on the two open questions of uppercase vs.
>> lowercase and placement of attribute?
> 
> I prefer lower case :-)

I agree that lower case makes it look less aggressive, but should that
hold up this patch?

How about we shove every

Re: [U-Boot] [PATCH v3] drivers: net: cpsw: always flush cache of size aligned to PKTALIGN

[Mugunthan V N]

On Thursday 11 August 2016 01:00 PM, Lokesh Vutla wrote:
> cpsw tries to flush dcache which is not in the range of PKTALIGN.
> Because of this the following warning comes while flushing:
> 
> CACHE: Misaligned operation at range [dffecec0, dffed016]
> 
> Fix it by flushing cache of size aligned to PKTALIGN.
> 
> Signed-off-by: Lokesh Vutla 
> ---

Reviewed-by: Mugunthan V N 

Regards
Mugunthan V N

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[U-Boot] [PATCH 0/5] ARM: Enable CMD_TIME on all TI platforms

[Lokesh Vutla]

This series enables CMD_TIME on all TI platforms.

Lokesh Vutla (5):
  configs: am335x: Enable CMD_TIME
  configs: am43xx: Enable CMD_TIME
  configs: am57xx: Enable CMD_TIME
  configs: dra7xx: Enable CMD_TIME
  configs: ks2: Enable CMD_TIME

 configs/am335x_boneblack_defconfig| 1 +
 configs/am335x_evm_defconfig  | 1 +
 configs/am335x_evm_nor_defconfig  | 1 +
 configs/am335x_evm_norboot_defconfig  | 1 +
 configs/am335x_evm_spiboot_defconfig  | 1 +
 configs/am335x_evm_usbspl_defconfig   | 1 +
 configs/am43xx_evm_defconfig  | 1 +
 configs/am43xx_evm_ethboot_defconfig  | 1 +
 configs/am43xx_evm_qspiboot_defconfig | 1 +
 configs/am43xx_evm_usbhost_boot_defconfig | 1 +
 configs/am43xx_hs_evm_defconfig   | 1 +
 configs/am57xx_evm_defconfig  | 1 +
 configs/am57xx_hs_evm_defconfig   | 1 +
 configs/dra7xx_evm_defconfig  | 1 +
 configs/dra7xx_hs_evm_defconfig   | 1 +
 configs/k2e_evm_defconfig | 1 +
 configs/k2g_evm_defconfig | 1 +
 configs/k2hk_evm_defconfig| 1 +
 configs/k2l_evm_defconfig | 1 +
 19 files changed, 19 insertions(+)

-- 
2.9.2

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[U-Boot] [PATCH 1/5] configs: am335x: Enable CMD_TIME

[Lokesh Vutla]

Enable CONFIG_CMD_TIME for all am335x platforms

Signed-off-by: Lokesh Vutla 
---
 configs/am335x_boneblack_defconfig   | 1 +
 configs/am335x_evm_defconfig | 1 +
 configs/am335x_evm_nor_defconfig | 1 +
 configs/am335x_evm_norboot_defconfig | 1 +
 configs/am335x_evm_spiboot_defconfig | 1 +
 configs/am335x_evm_usbspl_defconfig  | 1 +
 6 files changed, 6 insertions(+)

diff --git a/configs/am335x_boneblack_defconfig 
b/configs/am335x_boneblack_defconfig
index d310e0b..5eebd2a 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -43,3 +43,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_CMD_TIME=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 6885230..2e11ac4 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -50,3 +50,4 @@ CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk 
am335x-bonegreen am335x-icev2"
 CONFIG_DM_I2C=y
+CONFIG_CMD_TIME=y
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index 76a004e..f2e1bf9 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -39,3 +39,4 @@ CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
 CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
+CONFIG_CMD_TIME=y
diff --git a/configs/am335x_evm_norboot_defconfig 
b/configs/am335x_evm_norboot_defconfig
index 99fc555..70a3167 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -36,3 +36,4 @@ CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
 CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
+CONFIG_CMD_TIME=y
diff --git a/configs/am335x_evm_spiboot_defconfig 
b/configs/am335x_evm_spiboot_defconfig
index 2fe1a25..11637c0 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -39,3 +39,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_CMD_TIME=y
diff --git a/configs/am335x_evm_usbspl_defconfig 
b/configs/am335x_evm_usbspl_defconfig
index cba5e84..5269484 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -39,3 +39,4 @@ CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
 CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
+CONFIG_CMD_TIME=y
-- 
2.9.2

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Re: [U-Boot] A command to discard saved environments?

[Masahiro Yamada]

2016-08-04 14:40 GMT+09:00 Wolfgang Denk :
> Dear James,
>
> In message  you wrote:
>>
>> > In your case, you could save the "erase" by overwriting the first 4
>> > bytes (where the CRC32 checksum is stored) with 0x.
>
> Wrong.  I meant writing 0x - as you can always write that,
> setting any remaining 1 bits to 0 which does not require an erase of
> the sector.
>
>> In the case of my NOR flash storage, telling erase to do one byte
>> actually causes the erasure of an entire flash sector, which we've
>> reserved for the NV environment.  You are of course correct that
>> overwriting the CRC will have the same operational effect.
>
> ...and as the next "saveenv" will start with an erase, writing 0 to
> the CRC 32 field saves you one erase cycle on that sector.
>
> I know, this is nitpicking. Soryy.
>
>> It's a rare occurrence that we need to do this, we don't use this sort
>> of operation as a normal part of doing business.
>
> Agreed. This should never be part of regular operation.
>
> Best regards,
>
> Wolfgang Denk
>


Sorry for my late reply.


I was in the conflict between my coworkers from different schools.

One always wants to save his preference in the environments in a
non-volatile device.

Another wants to load "uEnv.txt" to adjust environments, so the
environments from a non-volatile device
are just annoying for him.  He just want to clean the saved
environments away, and makes the
sectors for environments to the initial state.


I was searching a way to make everyone happy.
As Tom pointed out, the latter can use CONFIG_ENV_IS_NOWHERE.
Thanks!

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Re: [U-Boot] [PATCH] net: asix: Fix ASIX 88772B with driver model

[Marek Vasut]

On 08/11/2016 12:28 PM, Alban Bedel wrote:
> On Thu, 11 Aug 2016 11:26:23 +0200
> Marek Vasut  wrote:
> 
>> On 08/11/2016 10:52 AM, Alban Bedel wrote:
>>> On Tue, 9 Aug 2016 14:32:14 +0200
>>> Marek Vasut  wrote:
>>>
 On 08/09/2016 02:14 PM, Marcel Ziswiler wrote:
> On Thu, 2016-08-04 at 11:12 +0200, Marek Vasut wrote:
>> On 08/04/2016 11:07 AM, Alban Bedel wrote:
>>>
>>> On Wed, 3 Aug 2016 15:23:30 +
>>> Marcel Ziswiler  wrote:
>>>

 On Wed, 2016-08-03 at 15:51 +0200, Marek Vasut wrote:
>
> On 08/03/2016 11:46 AM, Alban Bedel wrote:
>>
>>
>> On Wed, 3 Aug 2016 09:00:42 +0200
>> Marek Vasut  wrote:
>>
>>>
>>>
>>> On 08/03/2016 07:32 AM, Alban Bedel wrote:


 Commit 147271209a9d ("net: asix: fix operation without
 eeprom")
 added a special handling for ASIX 88772B that enable
 another
 type of header. This break the driver in DM mode as the
 extra
 handling
 needed in the receive path is missing.
>>> So add the extra handling ?
>> I can do that too, but I though u-boot preferred to avoid
>> useless
>> code.
> Yes, if it is useless.
>
>>
>>
>>>
>>>


 However this new header mode is not required and only
 seems to
 increase the code complexity, so this patch revert this
 part of
 commit 147271209a9d.
>>> Why is it not required ?
>> It works fine without, since 2012. In fact this change is not
>> even
>> mentioned in the log of commit 147271209a9d, so I really
>> don't know
>> why
>> it was added in the first place. As can be seen in the revert
>> all
>> it
>> does is adding 2 bytes to the USB packets that are then just
>> skipped.
>> Seems pretty useless to me.
> I would like to get some feedback on this from Marcel, since he
> added
> this stuff.
 Yes, sorry. I just came back from vacation and started looking
 into it
 now. As far as I remember on our hardware without this Ethernet
 did not
 quite work reliably. This also means that with driver model so
 far it
 does not work for us which I fed back to Simon once but so far
 this has
 not been resolved. That fix came from some early U-Boot work done
 by
 Antmicro way back and I am missing some of the history.
>>> Then I'll do a new patch that just fix the driver model receive
>>> path.
>> Hold on. Marcel, can you maybe test if removing this code has any
>> impact
>> on the behavior now ?
>
> Sorry for the delay. I tested Alban's patch now both on Toradex Colibri
> T20 as well as T30 and its on-module ASIX USB-to-Ethernet chip actually
> works perfectly aside from the occasional EHCI timed out on TD -
> token=0x88008d80 Rx: failed to receive: -5 message which last I checked
> with Simon is still unresolved but was already there long before any of
> the driver model work started.
>
> Tested-by: Marcel Ziswiler 
> Tested-on: Colibri T20/T30 on Colibri Evaluation Board
>
>>>
>>> Will this be applied for the upcoming release?
>>
>> Yeah. Why the hurry though ?
> 
> I was just wondering because all the other patches I submitted have
> been applied but this one still seems to be on hold.

Well because this one was broken, so I had to throw it away. Please do
make sure next time that the stuff builds using buildman.


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[U-Boot] [PATCH] drivers: net: keystone_net: add rgmii link type support when parsing dt

[Mugunthan V N]

Add support to detect RGMII link interface from link-interface
device tree entry. Also rename the existing link type enums so
that it provides meaningful interface like SGMII.

Signed-off-by: Mugunthan V N 
---

Tested this patch on Keystone K2G evm, logs [1]

[1] - http://pastebin.ubuntu.com/23026361/

---
 drivers/net/keystone_net.c | 23 +++
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index e41b7d1..0da3325 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -56,13 +56,16 @@ struct rx_buff_desc net_rx_buffs = {
 #ifdef CONFIG_DM_ETH
 
 enum link_type {
-   LINK_TYPE_MAC_TO_MAC_AUTO = 0,
-   LINK_TYPE_MAC_TO_PHY_MODE = 1,
-   LINK_TYPE_MAC_TO_MAC_FORCED_MODE = 2,
-   LINK_TYPE_MAC_TO_FIBRE_MODE = 3,
-   LINK_TYPE_MAC_TO_PHY_NO_MDIO_MODE = 4,
-   LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
-   LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
+   LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0,
+   LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1,
+   LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE  = 2,
+   LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE   = 3,
+   LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4,
+   LINK_TYPE_RGMII_LINK_MAC_PHY= 5,
+   LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6,
+   LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO= 7,
+   LINK_TYPE_10G_MAC_TO_PHY_MODE   = 10,
+   LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE= 11,
 };
 
 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) |\
@@ -1077,11 +1080,15 @@ static int ks2_eth_parse_slave_interface(int netcp, int 
slave,
priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
}
 
-   if (priv->link_type == LINK_TYPE_MAC_TO_PHY_MODE) {
+   if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
priv->phy_if = PHY_INTERFACE_MODE_SGMII;
pdata->phy_interface = priv->phy_if;
priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
priv->has_mdio = true;
+   } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
+   priv->phy_if = PHY_INTERFACE_MODE_RGMII;
+   pdata->phy_interface = priv->phy_if;
+   priv->has_mdio = true;
}
 
return 0;
-- 
2.9.2.664.ga0a1831

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Re: [U-Boot] A command to discard saved environments?

[Wolfgang Denk]

Dear Masahiro,

In message  
you wrote:
>
> Another wants to load "uEnv.txt" to adjust environments, so the
> environments from a non-volatile device
> are just annoying for him.

This is largely a matter of taste, but I consider it as a perfectly
valid wish.

> He just want to clean the saved
> environments away, and makes the
> sectors for environments to the initial state.

This, on the other hand, is not reasonable.

If he does not like the saved environment, he is free to use the
regular "env" commands to define one he likes: "env default -f -a"
or "env default -f var ..." or "env delete -f var ..." followed by a
"env save" provide a lot of options.

There should be no need for manipulating stored data structures in
obscure ways.

One could discuss if an expension as "env delete -f -a" makes sense...

> As Tom pointed out, the latter can use CONFIG_ENV_IS_NOWHERE.

Of course. TIMTOWTDI...

Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Harrisberger's Fourth Law of the Lab:
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amount of equipment ruined.
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Re: [U-Boot] [PATCH v3 00/27] spi/sf: Updates on flash detection

[york sun]

On 08/11/2016 01:15 AM, Jagan Teki wrote:
>
> Tested on microzed and sandbox
>
> Tested-by: Jagan Teki 
>
> I've some host issues while running buildman, can anyone please run buildman?
>

I can compile for power and (limited) arm for you.

York

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Re: [U-Boot] [PATCH v3 00/27] spi/sf: Updates on flash detection

[Jagan Teki]

On 11 August 2016 at 20:47, york sun  wrote:
> On 08/11/2016 08:12 AM, york@nxp.com wrote:
>> On 08/11/2016 01:15 AM, Jagan Teki wrote:
>>>
>>> Tested on microzed and sandbox
>>>
>>> Tested-by: Jagan Teki 
>>>
>>> I've some host issues while running buildman, can anyone please run
>>> buildman?
>>>
>>
>> I can compile for power and (limited) arm for you.
>>
>
> I can't compile test your v3 patch. They are not in mailing list, or
> patchwork. I only got some of them.

Ohh..look like these are not in patchwork, Tom any idea?

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Re: [U-Boot] [PATCH] rockchip: Fix SPL console output when ROCKCHIP_SPL_BACK_TO_BROM is enabled

[Sandy Patterson]

On Wed, Aug 10, 2016 at 11:01 PM, Ziyuan Xu  wrote:

>
>
> On 2016年08月10日 22:21, Sandy Patterson wrote:
>
>> Move back_to_bootrom() call later in SPL init so that the console is
>> initialized and printouts happen.
>>
>> Currently when ROCKCHIP_SPL_BACK_TO_BROM is enabled there is no console
>> output from the SPL init stages.
>>
>> I wasn't sure exactly where this should happen, so if we are set to do
>> run spl_board_init, then go back to bootrom there after
>> preloader_console_init(). Otherwise fall back to old behavior of doing
>> it in board_init_f.
>>
> In fact, ROCKCHIP_SPL_BACK_TO_BROM's aim is to reduce SPL's size, and we
> can undef CONFIG_SPL_MMC_SUPPORT and other thing.
> The SPL only in charge of DDR initialization, so that boot rom could load
> u-boot to RAM.
> If you really need something output, you can enable EARYLY_UART in
> rk3288-board-spl.c:board_init_f().
> But the above is my own understanding.


EARLY_UART is a good tool, but this patch just fixes printouts. It's not
enabling or disabling any code compilation. The console init and version
information code is there. I just move the back_to_bootrom call later in
the SPL if that later point exits. You can still
disable CONFIG_SPL_BOARD_INIT and it will fall back to calling the bootrom
earlier.

We don't actually need that much space. We chose to use BOOT_TO_BROM
instead of disabling the console in SPL.

We disable CONFIG_SPL_MMC_SUPPORT in our production system within the
rock2.h file if CONFIG_SPL_MMC_SUPPORT. I'll submit another patch for that.
I think if boootrom is used then the mmc should be removed from spl. I'm
not really sure how the config system is supposed to work in this case.


>
>> Signed-off-by: Sandy Patterson 
>> ---
>>
>>   arch/arm/mach-rockchip/rk3288-board-spl.c | 5 -
>>   1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c
>> b/arch/arm/mach-rockchip/rk3288-board-spl.c
>> index e0d92a6..0c2d525 100644
>> --- a/arch/arm/mach-rockchip/rk3288-board-spl.c
>> +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
>> @@ -206,7 +206,7 @@ void board_init_f(ulong dummy)
>> debug("DRAM init failed: %d\n", ret);
>> return;
>> }
>> -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
>> +#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) &&
>> !defined(CONFIG_SPL_BOARD_INIT)
>> back_to_bootrom();
>>   #endif
>>   }
>> @@ -273,6 +273,9 @@ void spl_board_init(void)
>> }
>> preloader_console_init();
>> +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
>> +   back_to_bootrom();
>> +#endif
>> return;
>>   err:
>> printf("spl_board_init: Error %d\n", ret);
>>
>
>
>
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Re: [U-Boot] [PATCH v3 00/27] spi/sf: Updates on flash detection

[york sun]

On 08/11/2016 09:17 AM, Jagan Teki wrote:
> On 11 August 2016 at 20:47, york sun  wrote:
>> On 08/11/2016 08:12 AM, york@nxp.com wrote:
>>> On 08/11/2016 01:15 AM, Jagan Teki wrote:

 Tested on microzed and sandbox

 Tested-by: Jagan Teki 

 I've some host issues while running buildman, can anyone please run
 buildman?

>>>
>>> I can compile for power and (limited) arm for you.
>>>
>>
>> I can't compile test your v3 patch. They are not in mailing list, or
>> patchwork. I only got some of them.
>
> Ohh..look like these are not in patchwork, Tom any idea?
>

Jagan,

Maybe it takes time to show up in mailing list. It happened to me many 
times. Please send me the patches, or point me to your repository.

York

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Re: [U-Boot] [PATCH v3 00/27] spi/sf: Updates on flash detection

[Jagan Teki]

On 11 August 2016 at 21:50, york sun  wrote:
> On 08/11/2016 09:17 AM, Jagan Teki wrote:
>> On 11 August 2016 at 20:47, york sun  wrote:
>>> On 08/11/2016 08:12 AM, york@nxp.com wrote:
 On 08/11/2016 01:15 AM, Jagan Teki wrote:
>
> Tested on microzed and sandbox
>
> Tested-by: Jagan Teki 
>
> I've some host issues while running buildman, can anyone please run
> buildman?
>

 I can compile for power and (limited) arm for you.

>>>
>>> I can't compile test your v3 patch. They are not in mailing list, or
>>> patchwork. I only got some of them.
>>
>> Ohh..look like these are not in patchwork, Tom any idea?
>>
>
> Jagan,
>
> Maybe it takes time to show up in mailing list. It happened to me many
> times. Please send me the patches, or point me to your repository.

Please take the u-boot-spi/next [1]

[1] http://git.denx.de/?p=u-boot-spi.git;a=shortlog;h=refs/heads/next

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[U-Boot] [RFC: v2] tools/env: ensure environment starts at erase block boundary

[Andreas Fenkart]

56086921 added support for unaligned environments access.
U-boot itself does not support this:
- env_nand.c fails when using an unaligned offset. It produces an
  error in nand_erase_opts{drivers/mtd/nand/nand_util.c}
- in env_sf/env_flash the unused space at the end is preserved, but
  not in the beginning. block alignment is assumed
- env_sata/env_mmc aligns offset/length to the block size of the
  underlying device. data is silently redirected to the beginning of
  a block

There is seems no use case for unaligned environment. If there is
some useful data at the beginning of the the block (e.g. end of u-boot)
that would be very unsafe. If the redundant environments are hosted by
the same erase block then that invalidates the idea of double buffering.
It might be that unaligned access was allowed in the past, and that
people with legacy u-boot are trapped. But at the time of 56086921
it wasn't supported and due to reasons above I guess it was never
introduced.
I prefer to remove that (unused) feature in favor of simplicity

Signed-off-by: Andreas Fenkart 
---
 tools/env/fw_env.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 6b0dcaa..d2b167d 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -1294,6 +1294,18 @@ static int check_device_config(int dev)
struct stat st;
int fd, rc = 0;
 
+   if (DEVOFFSET(dev) % DEVESIZE(dev) != 0) {
+   fprintf(stderr, "Environment does not start on erase block 
boundary\n");
+   errno = EINVAL;
+   return -1;
+   }
+
+   if (ENVSIZE(dev) > ENVSECTORS(dev) * DEVESIZE(dev)) {
+   fprintf(stderr, "Environment does not fit into available 
sectors\n");
+   errno = EINVAL;
+   return -1;
+   }
+
fd = open(DEVNAME(dev), O_RDONLY);
if (fd < 0) {
fprintf(stderr,
-- 
2.8.1

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Re: [U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver

[york sun]

On 08/10/2016 09:55 PM, Shengzhou Liu wrote:
> This patch adds basic support for Freescale MMDC(Multi Mode DDR Controller).
> Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a
> update to this driver to support more flexible configuration if new features
> (DDR4, multiple controllers/chip selections, etc) are implimented in future.
>
> Signed-off-by: Shengzhou Liu 
> ---
>  Makefile  |   1 +
>  arch/arm/include/asm/arch-fsl-layerscape/config.h |   2 +
>  drivers/ddr/fsl/Makefile  |   1 +
>  drivers/ddr/fsl/fsl_mmdc.c| 152 
> ++
>  include/fsl_mmdc.h|  83 +---
>  5 files changed, 192 insertions(+), 47 deletions(-)
>  create mode 100644 drivers/ddr/fsl/fsl_mmdc.c
>
> diff --git a/Makefile b/Makefile
> index 99cc8cf..1bf6c6a 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -647,6 +647,7 @@ libs-y += drivers/power/ \
>  libs-y += drivers/spi/
>  libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
>  libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
> +libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
>  libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
>  libs-y += drivers/serial/
>  libs-y += drivers/usb/dwc3/
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
> b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> index b0ad4b4..478b7ab 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> @@ -18,6 +18,8 @@
>  #ifndef CONFIG_LS1012A
>  #define CONFIG_SYS_FSL_DDR   /* Freescale DDR driver */
>  #define CONFIG_SYS_FSL_DDR_VER   FSL_DDR_VER_5_0
> +#else
> +#define CONFIG_SYS_FSL_MMDC  /* Freescale MMDC driver */
>  #endif

Let's revert this logic, shall we?

>
>  /*
> diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
> index 01ea862..00dea42 100644
> --- a/drivers/ddr/fsl/Makefile
> +++ b/drivers/ddr/fsl/Makefile
> @@ -33,3 +33,4 @@ obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
>  obj-$(CONFIG_SYS_FSL_DDR_86XX)   += mpc86xx_ddr.o
>  obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3)  += arm_ddr_gen3.o
>  obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
> +obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
> diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c
> new file mode 100644
> index 000..eb36cea
> --- /dev/null
> +++ b/drivers/ddr/fsl/fsl_mmdc.c
> @@ -0,0 +1,152 @@
> +/*
> + * Copyright 2016 Freescale Semiconductor, Inc.

I think we should use NXP now.

> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +/*
> + * Generic driver for Freescale MMDC(Multi Mode DDR Controller).
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
> +{
> + int timeout = 1000;
> +
> + out_be32(ptr, value);
> +
> + while (in_be32(ptr) & bits) {
> + udelay(100);
> + timeout--;
> + }
> + if (timeout <= 0)
> + printf("Error: %p wait for clear timeout.\n", ptr);
> +}
> +
> +void mmdc_init(void)
> +{
> + struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
> + unsigned int tmp;
> +
> + /* 1. set configuration request */
> + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
> +
> + /* 2. configure the desired timing parameters */
> + out_be32(&mmdc->mdotc,  CONFIG_MMDC_MDOTC);
> + out_be32(&mmdc->mdcfg0, CONFIG_MMDC_MDCFG0);
> + out_be32(&mmdc->mdcfg1, CONFIG_MMDC_MDCFG1);
> + out_be32(&mmdc->mdcfg2, CONFIG_MMDC_MDCFG2);
> +
> + /* 3. configure DDR type and other miscellaneous parameters */
> + out_be32(&mmdc->mdmisc, CONFIG_MMDC_MDMISC);
> + out_be32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR);
> + out_be32(&mmdc->mdrwd,  CONFIG_MMDC_MDRWD);
> + out_be32(&mmdc->mpodtctrl, CONFIG_MMDC_MPODTCTRL);
> +
> + /* 4. configure the required delay while leaving reset */
> + out_be32(&mmdc->mdor,  CONFIG_MMDC_MDOR);
> +
> + /* 5. configure DDR physical parameters */
> + /* set row/column address width, burst length, data bus width */
> + tmp = CONFIG_MMDC_MDCTL & ~(MDCTL_SDE0 | MDCTL_SDE1);
> + out_be32(&mmdc->mdctl, tmp);
> + /* configure address space partition */
> + out_be32(&mmdc->mdasp, CONFIG_MMDC_MDASP);
> +
> + /* 6. perform a ZQ calibration - not needed here, doing in #8b */
> +
> + /* 7. enable MMDC with the desired chip select */
> +#if (CONFIG_CHIP_SELECTS_PER_CTRL == 1)
> + out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0);
> +#elif (CONFIG_CHIP_SELECTS_PER_CTRL == 2)
> + out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);
> +#endif
> +
> + /* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */
> + out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ |
> + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2);
> +
> + out_be

[U-Boot] [PATCH 0/3 v2] Some additions for sandbox and fs tests

[Stefan Brüns]

Add some documentation for the sandbox block device emulation and
fix some issues for the fs test script.

v2: added Acked-by: Simon Glass  on patch 1 and 2
added missing commit messages
dropped test/fs: replace deprecated "sb" command with "host"
 - will be replaced by pytest based implementation later

Stefan Brüns (4):
  Sandbox: document support of block device emulation
  sandbox: Add "host size" hostfs command for fs test
  test/fs: strip carriage-return from sandbox output

 board/sandbox/README.sandbox | 19 +++
 cmd/host.c   |  8 
 test/fs/fs-test.sh   |  2 +-
 3 files changed, 28 insertions(+), 1 deletion(-)

-- 
2.9.2

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[U-Boot] [PATCH 1/3 v2] Sandbox: document support of block device emulation

[Stefan Brüns]

Signed-off-by: Stefan Brüns 
Acked-by: Simon Glass 
---
 board/sandbox/README.sandbox | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox
index ed820d3..02d8ab3 100644
--- a/board/sandbox/README.sandbox
+++ b/board/sandbox/README.sandbox
@@ -320,6 +320,25 @@ CONFIG_SPI_IDLE_VAL
The idle value on the SPI bus
 
 
+Block Device Emulation
+--
+
+U-Boot can use raw disk images for block device emulation. To e.g. list
+the contents of the root directory on the second partion of the image
+"disk.raw", you can use the following commands:
+
+=>host bind 0 ./disk.raw
+=>ls host 0:2
+
+A disk image can be created using the following commands:
+
+$> truncate -s 1200M ./disk.raw
+$> echo -e "label: gpt\n,64M,U\n,,L" | /usr/sbin/sfdisk  ./disk.raw
+$> lodev=`sudo losetup -P -f --show ./disk.raw`
+$> sudo mkfs.vfat -n EFI -v ${lodev}p1
+$> sudo mkfs.ext4 -L ROOT -v ${lodev}p2
+
+
 Writing Sandbox Drivers
 ---
 
-- 
2.9.2

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[U-Boot] [PATCH 2/3 v2] sandbox: Add "host size" hostfs command for fs test

[Stefan Brüns]

This complements the size/fatsize/ext4size commands added in
commit cf6598193aed5de8855eaf70c1994f2bc437255a
load, save and ls are already implemented for hostfs, now tests can
cover the same operations on hostfs and emulated block devices.

Signed-off-by: Stefan Brüns 
Acked-by: Simon Glass 
---
 cmd/host.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/cmd/host.c b/cmd/host.c
index 8d84415..b427e54 100644
--- a/cmd/host.c
+++ b/cmd/host.c
@@ -25,6 +25,12 @@ static int do_host_ls(cmd_tbl_t *cmdtp, int flag, int argc,
return do_ls(cmdtp, flag, argc, argv, FS_TYPE_SANDBOX);
 }
 
+static int do_host_size(cmd_tbl_t *cmdtp, int flag, int argc,
+  char * const argv[])
+{
+   return do_size(cmdtp, flag, argc, argv, FS_TYPE_SANDBOX);
+}
+
 static int do_host_save(cmd_tbl_t *cmdtp, int flag, int argc,
   char * const argv[])
 {
@@ -138,6 +144,7 @@ static cmd_tbl_t cmd_host_sub[] = {
U_BOOT_CMD_MKENT(load, 7, 0, do_host_load, "", ""),
U_BOOT_CMD_MKENT(ls, 3, 0, do_host_ls, "", ""),
U_BOOT_CMD_MKENT(save, 6, 0, do_host_save, "", ""),
+   U_BOOT_CMD_MKENT(size, 3, 0, do_host_size, "", ""),
U_BOOT_CMD_MKENT(bind, 3, 0, do_host_bind, "", ""),
U_BOOT_CMD_MKENT(info, 3, 0, do_host_info, "", ""),
U_BOOT_CMD_MKENT(dev, 0, 1, do_host_dev, "", ""),
@@ -174,6 +181,7 @@ U_BOOT_CMD(
"host ls hostfs - - list files on host\n"
"host save hostfs -[] - "
"save a file to host\n"
+   "host size hostfs -  - determine size of file on host"
"host bind  [] - bind \"host\" device to file\n"
"host info []- show device binding & info\n"
"host dev [] - Set or retrieve the current host device\n"
-- 
2.9.2

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[U-Boot] [PATCH 3/3 v2] test/fs: strip carriage-return from sandbox output

[Stefan Brüns]

DM added carriage-returns to every newline. Strip everything after the
32 character long mdsum.

Signed-off-by: Stefan Brüns 
---
 test/fs/fs-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh
index 043e5d0..171b1de 100755
--- a/test/fs/fs-test.sh
+++ b/test/fs/fs-test.sh
@@ -402,7 +402,7 @@ check_md5() {
# the 7th field is the actual md5
md5_src=`grep -A3 "$1" "$2" | grep "md5 for"`
md5_src=($md5_src)
-   md5_src=${md5_src[6]}
+   md5_src=${md5_src[6]:0:32}
 
# The md5 list, each line is of the form:
# - 
-- 
2.9.2

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[U-Boot] [PATCH 2/2] armv8:ls1012a: Use common MMDC driver for ls1012a

[Shengzhou Liu]

Let's use common MMDC driver for DDR initialization on
LS1012ARDB, LS1012AQDS, LS1012AFRDM boards.

Signed-off-by: Shengzhou Liu 
---
 board/freescale/ls1012afrdm/ls1012afrdm.c | 116 --
 board/freescale/ls1012aqds/ls1012aqds.c   | 116 --
 board/freescale/ls1012ardb/ls1012ardb.c   | 116 --
 include/configs/ls1012afrdm.h |  23 --
 include/configs/ls1012aqds.h  |  24 ++-
 include/configs/ls1012ardb.h  |  22 --
 6 files changed, 57 insertions(+), 360 deletions(-)

diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c 
b/board/freescale/ls1012afrdm/ls1012afrdm.c
index a94a458..0bbb558 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -18,20 +18,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-{
-   int timeout = 1000;
-
-   out_be32(ptr, value);
-
-   while (in_be32(ptr) & bits) {
-   udelay(100);
-   timeout--;
-   }
-   if (timeout <= 0)
-   puts("Error: wait for clear timeout.\n");
-}
-
 int checkboard(void)
 {
puts("Board: LS1012AFRDM ");
@@ -39,108 +25,6 @@ int checkboard(void)
return 0;
 }
 
-void mmdc_init(void)
-{
-   struct mmdc_p_regs *mmdc =
-   (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
-
-   out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
-   /* configure timing parms */
-   out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
-   out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
-   out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
-   out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
-
-   /* other parms  */
-   out_be32(&mmdc->mdmisc,CONFIG_SYS_MMDC_CORE_MISC);
-   out_be32(&mmdc->mpmur0,CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
-   out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
-   out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
-
-   /* out of reset delays */
-   out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
-
-   /* physical parms */
-   out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
-   out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
-
-   /* Enable MMDC */
-   out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
-
-   /* dram init sequence: update MRs */
-   out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
-   CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
-   out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-   CMD_BANK_ADDR_3));
-   out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-   CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
-   out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
-   CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
-   CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
-
-   /* dram init sequence: ZQCL */
-   out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
-   CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
-   set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
-   CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
-   FORCE_ZQ_AUTO_CALIBRATION);
-
-   /* Calibrations now: wr lvl */
-   out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
-   CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-   CMD_BANK_ADDR_1));
-   out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
-   set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
-
-   mdelay(1);
-
-   out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-   CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
-   out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
-   mdelay(1);
-
-   /* Calibrations now: Read DQS gating calibration */
-   out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
-   CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
-   out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-   CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
-   out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
-   out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
-   set_wait_for_bits_clear(&mmdc->mpdgctrl0,
-   AUTO_RD_DQS_GATING_CALIBRATION_EN,
-   AUTO_RD_DQS_GATING_CALIBRATION_EN);
-
-   out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-   CMD_BANK_ADDR_3));
-
-   /* Calibrations now: Read calibration 

[U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver

[Shengzhou Liu]

This patch adds basic support for Freescale MMDC(Multi Mode DDR Controller).
Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a
update to this driver to support more flexible configuration if new features
(DDR4, multiple controllers/chip selections, etc) are implimented in future.

Signed-off-by: Shengzhou Liu 
---
 Makefile  |   1 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h |   2 +
 drivers/ddr/fsl/Makefile  |   1 +
 drivers/ddr/fsl/fsl_mmdc.c| 152 ++
 include/fsl_mmdc.h|  83 +---
 5 files changed, 192 insertions(+), 47 deletions(-)
 create mode 100644 drivers/ddr/fsl/fsl_mmdc.c

diff --git a/Makefile b/Makefile
index 99cc8cf..1bf6c6a 100644
--- a/Makefile
+++ b/Makefile
@@ -647,6 +647,7 @@ libs-y += drivers/power/ \
 libs-y += drivers/spi/
 libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
 libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
+libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
 libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
 libs-y += drivers/serial/
 libs-y += drivers/usb/dwc3/
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b0ad4b4..478b7ab 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -18,6 +18,8 @@
 #ifndef CONFIG_LS1012A
 #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
+#else
+#define CONFIG_SYS_FSL_MMDC/* Freescale MMDC driver */
 #endif
 
 /*
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
index 01ea862..00dea42 100644
--- a/drivers/ddr/fsl/Makefile
+++ b/drivers/ddr/fsl/Makefile
@@ -33,3 +33,4 @@ obj-$(CONFIG_SYS_FSL_DDRC_GEN3)   += mpc85xx_ddr_gen3.o
 obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
 obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3)+= arm_ddr_gen3.o
 obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
+obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c
new file mode 100644
index 000..eb36cea
--- /dev/null
+++ b/drivers/ddr/fsl/fsl_mmdc.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Generic driver for Freescale MMDC(Multi Mode DDR Controller).
+ */
+
+#include 
+#include 
+#include 
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+   int timeout = 1000;
+
+   out_be32(ptr, value);
+
+   while (in_be32(ptr) & bits) {
+   udelay(100);
+   timeout--;
+   }
+   if (timeout <= 0)
+   printf("Error: %p wait for clear timeout.\n", ptr);
+}
+
+void mmdc_init(void)
+{
+   struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+   unsigned int tmp;
+
+   /* 1. set configuration request */
+   out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
+
+   /* 2. configure the desired timing parameters */
+   out_be32(&mmdc->mdotc,  CONFIG_MMDC_MDOTC);
+   out_be32(&mmdc->mdcfg0, CONFIG_MMDC_MDCFG0);
+   out_be32(&mmdc->mdcfg1, CONFIG_MMDC_MDCFG1);
+   out_be32(&mmdc->mdcfg2, CONFIG_MMDC_MDCFG2);
+
+   /* 3. configure DDR type and other miscellaneous parameters */
+   out_be32(&mmdc->mdmisc, CONFIG_MMDC_MDMISC);
+   out_be32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR);
+   out_be32(&mmdc->mdrwd,  CONFIG_MMDC_MDRWD);
+   out_be32(&mmdc->mpodtctrl, CONFIG_MMDC_MPODTCTRL);
+
+   /* 4. configure the required delay while leaving reset */
+   out_be32(&mmdc->mdor,  CONFIG_MMDC_MDOR);
+
+   /* 5. configure DDR physical parameters */
+   /* set row/column address width, burst length, data bus width */
+   tmp = CONFIG_MMDC_MDCTL & ~(MDCTL_SDE0 | MDCTL_SDE1);
+   out_be32(&mmdc->mdctl, tmp);
+   /* configure address space partition */
+   out_be32(&mmdc->mdasp, CONFIG_MMDC_MDASP);
+
+   /* 6. perform a ZQ calibration - not needed here, doing in #8b */
+
+   /* 7. enable MMDC with the desired chip select */
+#if (CONFIG_CHIP_SELECTS_PER_CTRL == 1)
+   out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0);
+#elif (CONFIG_CHIP_SELECTS_PER_CTRL == 2)
+   out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);
+#endif
+
+   /* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */
+   out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ |
+   CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2);
+
+   out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(0) | MDSCR_ENABLE_CON_REQ |
+   CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+
+   out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+   CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+
+ 

Re: [U-Boot] [PATCH v2] drivers: net: cpsw: always flush cache of size PKTSIZE_ALIGN

[Lokesh Vutla]

On Thursday 11 August 2016 03:11 AM, Joe Hershberger wrote:
> Hi Lokesh,
> 
> On Wed, Aug 10, 2016 at 7:02 AM, Lokesh Vutla  wrote:
>>
>>
>> On Wednesday 10 August 2016 08:43 AM, Joe Hershberger wrote:
>>> Hi Lokesh
>>>
>>> On Tue, Aug 9, 2016 at 12:47 AM, Lokesh Vutla  wrote:
 cpsw tries to flush dcache which is not in the range of PKTSIZE.
 Because of this the following warning comes while flushing:

 CACHE: Misaligned operation at range [dffecec0, dffed016]

 Fix it by flushing cache of size PKTSIZE_ALIGN as similar to what is
 being done in _cpsw_recv.

 Signed-off-by: Lokesh Vutla 
 ---
 Changes since v1:
 - Use PKTALIGN instead of cache line size
 - Need not align start of packet buffer from the network subsystem.

  drivers/net/cpsw.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
 index 2ce4ec6..8ce5716 100644
 --- a/drivers/net/cpsw.c
 +++ b/drivers/net/cpsw.c
 @@ -907,7 +907,7 @@ static int _cpsw_send(struct cpsw_priv *priv, void 
 *packet, int length)
 int timeout = CPDMA_TIMEOUT;

 flush_dcache_range((unsigned long)packet,
 -  (unsigned long)packet + length);
 +  (unsigned long)packet + PKTSIZE_ALIGN);
>>>
>>> Technically you are flushing more than needed since you just need to
>>> be aligned to the cacheline beyond the size being sent, but you are
>>> flushing the maximum packet size every time. That said, it's still
>>> going to work and the code is readable. I'm fine with this, but wanted
>>> to make sure you knew this is more flushing than needed.
>>
>> Initially that was my idea as well and aligned length to cache line
>> size. As you suggested to use PKTSIZE_ALIGN and also _cpsw_recv uses the
>> same. So, I used PKTSIZE_ALIGN.
> 
> I actually recommended PKTALIGN, not PKTSIZE_ALIGN. For recv, the size

Oops my bad. I totally misunderstood your previous comment. Ill resend
this patch.

Thanks and regards,
Lokesh

> for invalidate is unknown until it's received (unless you can check a
> descriptor after it's received but before you read it), so it's more
> appropriate to use PKTSIZE_ALIGN. For send, you certainly know the
> size before flushing.
> 
> Cheers,
> -Joe
> 
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[U-Boot] [PATCH v3 04/27] spi: Remove SPI_RX_FAST

[Jagan Teki]

Removed SPI_RX_FAST since default read for spi slaves
are always 1-wire fast read.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Cc: Vignesh R 
Cc: Mugunthan V N 
Signed-off-by: Jagan Teki 
---
 include/spi.h | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/include/spi.h b/include/spi.h
index b262e06..4c17983 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -27,9 +27,8 @@
 #define SPI_TX_DUALBIT(9)  /* transmit with 2 wires */
 #define SPI_TX_QUADBIT(10) /* transmit with 4 wires */
 #define SPI_RX_SLOWBIT(11) /* receive with 1 wire slow */
-#define SPI_RX_FASTBIT(12) /* receive with 1 wire fast */
-#define SPI_RX_DUALBIT(13) /* receive with 2 wires */
-#define SPI_RX_QUADBIT(14) /* receive with 4 wires */
+#define SPI_RX_DUALBIT(12) /* receive with 2 wires */
+#define SPI_RX_QUADBIT(13) /* receive with 4 wires */
 
 /* SPI bus connection options - see enum spi_dual_flash */
 #define SPI_CONN_DUAL_SHARED   (1 << 0)
-- 
2.7.4

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[U-Boot] [PATCH v3 01/27] sf: Simplify fastest read cmd code

[Jagan Teki]

Fastest read command code look for fastest read command
taking inputs from spi->mode_rx and flags from param table
and controller mode_rx is always been a priority.

Since mode_rx is always set from controller side this optimized
code doesn't require much and this code required exctra overhead like
1) Maintain e_rx_cmd in param table
2) Maintain mode_rx in spi_slave {}

Hence removed this code, and look for read command from normal
spi->mode from spi_slave{} and params->flags

Cc: Simon Glass 
Cc: Bin Meng 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Cc: Vignesh R 
Cc: Mugunthan V N 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h |  4 
 drivers/mtd/spi/spi_flash.c   | 28 ++--
 2 files changed, 14 insertions(+), 18 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index da2bb7b..c5cb791 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -46,6 +46,10 @@ enum {
E_FSR   = BIT(2),
SST_WR  = BIT(3),
WR_QPP  = BIT(4),
+   RD_QUAD = BIT(5),
+   RD_DUAL = BIT(6),
+   RD_QUADIO   = BIT(7),
+   RD_DUALIO   = BIT(8),
 };
 
 enum spi_nor_option_flags {
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 64d4e0f..5fd408c 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1013,15 +1013,8 @@ int spi_flash_scan(struct spi_flash *flash)
struct spi_slave *spi = flash->spi;
const struct spi_flash_params *params;
u16 jedec, ext_jedec;
-   u8 cmd, idcode[5];
+   u8 idcode[5];
int ret;
-   static u8 spi_read_cmds_array[] = {
-   CMD_READ_ARRAY_SLOW,
-   CMD_READ_ARRAY_FAST,
-   CMD_READ_DUAL_OUTPUT_FAST,
-   CMD_READ_QUAD_OUTPUT_FAST,
-   CMD_READ_DUAL_IO_FAST,
-   CMD_READ_QUAD_IO_FAST };
 
/* Read the ID codes */
ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
@@ -1177,17 +1170,16 @@ int spi_flash_scan(struct spi_flash *flash)
/* Now erase size becomes valid sector size */
flash->sector_size = flash->erase_size;
 
-   /* Look for the fastest read cmd */
-   cmd = fls(params->e_rd_cmd & spi->mode_rx);
-   if (cmd) {
-   cmd = spi_read_cmds_array[cmd - 1];
-   flash->read_cmd = cmd;
-   } else {
-   /* Go for default supported read cmd */
-   flash->read_cmd = CMD_READ_ARRAY_FAST;
-   }
+   /* Look for read commands */
+   flash->read_cmd = CMD_READ_ARRAY_FAST;
+   if (spi->mode_rx & SPI_RX_SLOW)
+   flash->read_cmd = CMD_READ_ARRAY_SLOW;
+   else if (spi->mode_rx & SPI_RX_QUAD && params->flags & RD_QUAD)
+   flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST;
+   else if (spi->mode_rx & SPI_RX_DUAL && params->flags & RD_DUAL)
+   flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST;
 
-   /* Not require to look for fastest only two write cmds yet */
+   /* Look for write commands */
if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
else
-- 
2.7.4

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[U-Boot] [PATCH v3 06/27] sf: Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flash

[Jagan Teki]

Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flash code from header file.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Cc: Vignesh R 
Cc: Mugunthan V N 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h | 4 
 drivers/mtd/spi/spi_flash.c   | 5 -
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 9eb0b84..1301e48 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -22,11 +22,7 @@ enum spi_dual_flash {
 
 /* sf param flags */
 enum {
-#ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS
-   SECT_4K = 0,
-#else
SECT_4K = BIT(0),
-#endif
E_FSR   = BIT(1),
SST_WR  = BIT(2),
WR_QPP  = BIT(3),
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 2b2a409..7f6e9ae 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1155,11 +1155,14 @@ int spi_flash_scan(struct spi_flash *flash)
flash->size <<= 1;
 #endif
 
+#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
/* Compute erase sector and command */
if (params->flags & SECT_4K) {
flash->erase_cmd = CMD_ERASE_4K;
flash->erase_size = 4096 << flash->shift;
-   } else {
+   } else
+#endif
+   {
flash->erase_cmd = CMD_ERASE_64K;
flash->erase_size = flash->sector_size;
}
-- 
2.7.4

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[U-Boot] [PATCH v3 07/27] sf: Move flags macro's to spi_flash_params{} members

[Jagan Teki]

This patch moves flags macro's to respective member position on
spi_flash_params{}, for better readabilty and finding the
respective member macro's easily.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Cc: Vignesh R 
Cc: Mugunthan V N 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h | 23 ++-
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 1301e48..cde4cfb 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -20,19 +20,6 @@ enum spi_dual_flash {
SF_DUAL_PARALLEL_FLASH  = BIT(1),
 };
 
-/* sf param flags */
-enum {
-   SECT_4K = BIT(0),
-   E_FSR   = BIT(1),
-   SST_WR  = BIT(2),
-   WR_QPP  = BIT(3),
-   RD_QUAD = BIT(4),
-   RD_DUAL = BIT(5),
-   RD_QUADIO   = BIT(6),
-   RD_DUALIO   = BIT(7),
-};
-#define RD_FULLRD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO
-
 enum spi_nor_option_flags {
SNOR_F_SST_WR   = BIT(0),
SNOR_F_USE_FSR  = BIT(1),
@@ -133,7 +120,17 @@ struct spi_flash_params {
u16 ext_jedec;
u32 sector_size;
u32 nr_sectors;
+
u16 flags;
+#define SECT_4KBIT(0)
+#define E_FSR  BIT(1)
+#define SST_WR BIT(2)
+#define WR_QPP BIT(3)
+#define RD_QUADBIT(4)
+#define RD_DUALBIT(5)
+#define RD_QUADIO  BIT(6)
+#define RD_DUALIO  BIT(7)
+#define RD_FULL(RD_QUAD | RD_DUAL | RD_QUADIO | 
RD_DUALIO)
 };
 
 extern const struct spi_flash_params spi_flash_params_table[];
-- 
2.7.4

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[U-Boot] [PATCH v3 11/27] sf: Add JEDEC_MFR

[Jagan Teki]

Instead using idcode[0] for detecting manufacture id
add JEDEC_MFR macro for code simplicity and undesirability.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h |  1 +
 drivers/mtd/spi/spi_flash.c   | 30 +-
 2 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index bb5251d..a9455ac 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -104,6 +104,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
 #define CMD_SPANSION_WRAR  0x71 /* Write any device register */
 #endif
 
+#define JEDEC_MFR(info)((info)->id[0])
 #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
 #define JEDEC_EXT(info)(((info)->id[3]) << 8 | ((info)->id[4]))
 
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 099714e..daa9014 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -165,7 +165,8 @@ bar_end:
return flash->bank_curr;
 }
 
-static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0)
+static int spi_flash_read_bar(struct spi_flash *flash,
+ const struct spi_flash_info *info)
 {
u8 curr_bank = 0;
int ret;
@@ -173,7 +174,7 @@ static int spi_flash_read_bar(struct spi_flash *flash, u8 
idcode0)
if (flash->size <= SPI_FLASH_16MB_BOUN)
goto bar_end;
 
-   switch (idcode0) {
+   switch (JEDEC_MFR(info)) {
case SPI_FLASH_CFI_MFR_SPANSION:
flash->bank_read_cmd = CMD_BANKADDR_BRRD;
flash->bank_write_cmd = CMD_BANKADDR_BRWR;
@@ -949,9 +950,10 @@ static const struct spi_flash_info 
*spi_flash_read_id(struct spi_flash *flash)
return ERR_PTR(-ENODEV);
 }
 
-static int set_quad_mode(struct spi_flash *flash, u8 idcode0)
+static int set_quad_mode(struct spi_flash *flash,
+const struct spi_flash_info *info)
 {
-   switch (idcode0) {
+   switch (JEDEC_MFR(info)) {
 #ifdef CONFIG_SPI_FLASH_MACRONIX
case SPI_FLASH_CFI_MFR_MACRONIX:
return macronix_quad_enable(flash);
@@ -966,7 +968,8 @@ static int set_quad_mode(struct spi_flash *flash, u8 
idcode0)
return micron_quad_enable(flash);
 #endif
default:
-   printf("SF: Need set QEB func for %02x flash\n", idcode0);
+   printf("SF: Need set QEB func for %02x flash\n",
+  JEDEC_MFR(info));
return -1;
}
 }
@@ -1085,9 +1088,9 @@ int spi_flash_scan(struct spi_flash *flash)
}
 #endif
/* Flash powers up read-only, so clear BP# bits */
-   if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL ||
-   idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX ||
-   idcode[0] == SPI_FLASH_CFI_MFR_SST)
+   if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
+   JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX ||
+   JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST)
write_sr(flash, 0);
 
/* Assign spi data */
@@ -1115,7 +1118,7 @@ int spi_flash_scan(struct spi_flash *flash)
 #endif
 
/* lock hooks are flash specific - assign them based on idcode0 */
-   switch (idcode[0]) {
+   switch (JEDEC_MFR(info)) {
 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
case SPI_FLASH_CFI_MFR_STMICRO:
case SPI_FLASH_CFI_MFR_SST:
@@ -1125,7 +1128,7 @@ int spi_flash_scan(struct spi_flash *flash)
 #endif
break;
default:
-   debug("SF: Lock ops not supported for %02x flash\n", idcode[0]);
+   debug("SF: Lock ops not supported for %02x flash\n", 
JEDEC_MFR(info));
}
 
/* Compute the flash size */
@@ -1185,9 +1188,10 @@ int spi_flash_scan(struct spi_flash *flash)
if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
(flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
(flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
-   ret = set_quad_mode(flash, idcode[0]);
+   ret = set_quad_mode(flash, info);
if (ret) {
-   debug("SF: Fail to set QEB for %02x\n", idcode[0]);
+   debug("SF: Fail to set QEB for %02x\n",
+ JEDEC_MFR(info));
return -EINVAL;
}
}
@@ -1218,7 +1222,7 @@ int spi_flash_scan(struct spi_flash *flash)
 
/* Configure the BAR - discover bank cmds and read current bank */
 #ifdef CONFIG_SPI_FLASH_BAR
-   ret = spi_flash_read_bar(flash, idcode[0]);
+   ret = spi_flash_read_bar(flash, info);
if (ret < 0)
return ret;
 #endif
-- 
2.7.4

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[U-Boot] [PATCH v3 09/27] sf: Add JEDEC_ID and JEDEC_EXT macro

[Jagan Teki]

Few of the flash families with different ext_jedec
have changes in page_size so these macros check these
ext_jedec and assign page_size accordingly

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h |  4 
 drivers/mtd/spi/spi_flash.c   | 10 --
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index e6cd6da..966fd21 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -103,6 +103,10 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
 #define CMD_SPANSION_RDAR  0x65 /* Read any device register */
 #define CMD_SPANSION_WRAR  0x71 /* Write any device register */
 #endif
+
+#define JEDEC_ID(params)   (((params)->id[1]) << 8 | ((params)->id[2]))
+#define JEDEC_EXT(params)  (((params)->id[3]) << 8 | ((params)->id[4]))
+
 /**
  * struct spi_flash_params - SPI/QSPI flash device params structure
  *
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 680d1dc..e979b8e 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1130,19 +1130,17 @@ int spi_flash_scan(struct spi_flash *flash)
 
/* Compute the flash size */
flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
+   flash->page_size = params->page_size;
/*
 * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the
 * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with
 * the 0x4d00 Extended JEDEC code have 512b pages. All of the others
 * have 256b pages.
 */
-   if (ext_jedec == 0x4d00) {
-   if ((jedec == 0x0215) || (jedec == 0x216) || (jedec == 0x220))
-   flash->page_size = 256;
-   else
+   if (JEDEC_EXT(params) == 0x4d00) {
+   if ((JEDEC_ID(params) != 0x0215) &&
+   (JEDEC_ID(params) != 0x0216))
flash->page_size = 512;
-   } else {
-   flash->page_size = 256;
}
flash->page_size <<= flash->shift;
flash->sector_size = params->sector_size << flash->shift;
-- 
2.7.4

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[U-Boot] [PATCH v3 14/27] sf: Cleanup spi_flash_info{}

[Jagan Teki]

- Proper tabs spaces
- Removed unnecessary
- Added meaningful comments 

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h | 22 --
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index a9455ac..71feba9 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -108,17 +108,8 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
 #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
 #define JEDEC_EXT(info)(((info)->id[3]) << 8 | ((info)->id[4]))
 
-/**
- * struct spi_flash_info - SPI/QSPI flash device params structure
- *
- * @name:  Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
- * @sector_size:   Isn't necessarily a sector size from vendor,
- * the size listed here is what works with CMD_ERASE_64K
- * @nr_sectors:No.of sectors on this device
- * @flags: Important param, for flash specific behaviour
- */
 struct spi_flash_info {
-   const char *name;
+   const char  *name;
 
/*
 * This array stores the ID bytes.
@@ -128,12 +119,15 @@ struct spi_flash_info {
u8  id[5];
u8  id_len;
 
-   u32 sector_size;
-   u32 nr_sectors;
+   /* The size listed here is what works with SPINOR_OP_SE, which isn't
+* necessarily called a "sector" by the vendor.
+*/
+   u32 sector_size;
+   u32 nr_sectors;
 
-   u16 page_size;
+   u16 page_size;
 
-   u16 flags;
+   u16 flags;
 #define SECT_4KBIT(0)
 #define E_FSR  BIT(1)
 #define SST_WR BIT(2)
-- 
2.7.4

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[U-Boot] [PATCH v3 18/27] sf: Increase max id length by 1 byte

[Jagan Teki]

So, now SPI_FLASH_ID_MAX_LEN is 6 bytes useful for
few spansion flash families S25FS-S

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 437ac8a..f2ea368 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -108,7 +108,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
 #define JEDEC_MFR(info)((info)->id[0])
 #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
 #define JEDEC_EXT(info)(((info)->id[3]) << 8 | ((info)->id[4]))
-#define SPI_FLASH_MAX_ID_LEN   5
+#define SPI_FLASH_MAX_ID_LEN   6
 
 struct spi_flash_info {
const char  *name;
-- 
2.7.4

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[U-Boot] [PATCH v3 20/27] sf: params: Add S25FS256S_64K spi flash support

[Jagan Teki]

Add Spansion S25FS256S_64K spi flash to the list of spi_flash_ids.

In spansion S25FS-S family the physical sectors are grouped as
normal and parameter sectors. Parameter sectors are 4kB in size
with 8 set located at the bottom or top address of a device.
Normal sectors are similar to other flash family with sizes of
64kB or 32 kB.

To erase whole flash using sector erase(D8h or DCh) won't effect
the parameter sectors, so in order to erase these we must use 4K
sector erase commands (20h or 21h) separately.

So better to erase the whole flash using 4K sector erase instead
of detecting these family parts again and do two different erase
operations.

Cc: Yunhui Cui 
Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Michael Trimarchi 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_params.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 344d9c9..b029c76 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -93,6 +93,7 @@ const struct spi_flash_info spi_flash_ids[] = {
{"S25FL128S_64K",  INFO(0x012018, 0x4d01,  64 * 1024,   256, RD_FULL | 
WR_QPP) },
{"S25FL256S_256K", INFO(0x010219, 0x4d00, 256 * 1024,   128, RD_FULL | 
WR_QPP) },
{"S25FL256S_64K",  INFO(0x010219, 0x4d01,  64 * 1024,   512, RD_FULL | 
WR_QPP) },
+   {"S25FS256S_64K",  INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | 
WR_QPP | SECT_4K) },
{"S25FS512S",  INFO(0x010220, 0x4D00, 128 * 1024,   512, RD_FULL | 
WR_QPP) },
{"S25FL512S_256K", INFO(0x010220, 0x4d00, 256 * 1024,   256, RD_FULL | 
WR_QPP) },
{"S25FL512S_64K",  INFO(0x010220, 0x4d01,  64 * 1024,  1024, RD_FULL | 
WR_QPP) },
-- 
2.7.4

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[U-Boot] [PATCH v3 15/27] sf: Cleanup sf_params

[Jagan Teki]

- Move headers froms sf_params to common header file
- Removed unnecessary comment

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h | 5 +++--
 drivers/mtd/spi/sf_params.c   | 5 -
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 71feba9..4a88cf7 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -10,8 +10,9 @@
 #ifndef _SF_INTERNAL_H_
 #define _SF_INTERNAL_H_
 
-#include 
-#include 
+#include 
+#include 
+#include 
 
 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */
 enum spi_dual_flash {
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 7fcc3bc..7314455 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -6,10 +6,6 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#include 
-#include 
-#include 
-
 #include "sf_internal.h"
 
 /* Used when the "_ext_id" is two bytes at most */
@@ -27,7 +23,6 @@
.page_size = 256,   \
.flags = (_flags),
 
-/* SPI/QSPI flash device params structure */
 const struct spi_flash_info spi_flash_ids[] = {
 #ifdef CONFIG_SPI_FLASH_ATMEL  /* ATMEL */
{"AT45DB011D", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
-- 
2.7.4

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[U-Boot] [PATCH v3 22/27] sf: Remove non-meaningful comments

[Jagan Teki]

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/spi_flash.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 27b85ba..c1025c9 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1015,16 +1015,13 @@ int spi_flash_scan(struct spi_flash *flash)
JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST)
write_sr(flash, 0);
 
-   /* Assign spi data */
flash->name = info->name;
flash->memory_map = spi->memory_map;
flash->dual_flash = spi->option;
 
-   /* Assign spi flash flags */
if (info->flags & SST_WR)
flash->flags |= SNOR_F_SST_WR;
 
-   /* Assign spi_flash ops */
 #ifndef CONFIG_DM_SPI_FLASH
flash->write = spi_flash_cmd_write_ops;
 #if defined(CONFIG_SPI_FLASH_SST)
-- 
2.7.4

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[U-Boot] [PATCH v3 23/27] sf: Rename sf_params.c to spi_flash_ids

[Jagan Teki]

spi_flash_ids.c is more meaningful name as the flash_info
table structure spi_flash_info has spi_flash_ids instance.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/Makefile|   2 +-
 drivers/mtd/spi/spi_flash_ids.c | 176 
 2 files changed, 177 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mtd/spi/spi_flash_ids.c

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 6f47a66..6379b4b 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_SPL_SPI_BOOT)+= fsl_espi_spl.o
 obj-$(CONFIG_SPL_SPI_SUNXI)+= sunxi_spi_spl.o
 endif
 
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o sf_params.o sf.o
+obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o spi_flash_ids.o sf.o
 obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
 obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
 obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
new file mode 100644
index 000..61cac59
--- /dev/null
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -0,0 +1,176 @@
+/*
+ * SPI Flash ID's.
+ *
+ * Copyright (C) 2016 Jagan Teki 
+ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include "sf_internal.h"
+
+/* Used when the "_ext_id" is two bytes at most */
+#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
+   .id = { \
+   ((_jedec_id) >> 16) & 0xff, \
+   ((_jedec_id) >> 8) & 0xff,  \
+   (_jedec_id) & 0xff, \
+   ((_ext_id) >> 8) & 0xff,\
+   (_ext_id) & 0xff,   \
+   },  \
+   .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),   
\
+   .sector_size = (_sector_size),  \
+   .n_sectors = (_n_sectors),  \
+   .page_size = 256,   \
+   .flags = (_flags),
+
+#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
+   .id = { \
+   ((_jedec_id) >> 16) & 0xff, \
+   ((_jedec_id) >> 8) & 0xff,  \
+   (_jedec_id) & 0xff, \
+   ((_ext_id) >> 16) & 0xff,   \
+   ((_ext_id) >> 8) & 0xff,\
+   (_ext_id) & 0xff,   \
+   },  \
+   .id_len = 6,\
+   .sector_size = (_sector_size),  \
+   .n_sectors = (_n_sectors),  \
+   .page_size = 256,   \
+   .flags = (_flags),
+
+const struct spi_flash_info spi_flash_ids[] = {
+#ifdef CONFIG_SPI_FLASH_ATMEL  /* ATMEL */
+   {"AT45DB011D", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
+   {"AT45DB021D", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) },
+   {"AT45DB041D", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) },
+   {"AT45DB081D", INFO(0x1f2500, 0x0, 64 * 1024,16, SECT_4K) },
+   {"AT45DB161D", INFO(0x1f2600, 0x0, 64 * 1024,32, SECT_4K) },
+   {"AT45DB321D", INFO(0x1f2700, 0x0, 64 * 1024,64, SECT_4K) },
+   {"AT45DB641D", INFO(0x1f2800, 0x0, 64 * 1024,   128, SECT_4K) },
+   {"AT25DF321A", INFO(0x1f4701, 0x0, 64 * 1024,64, SECT_4K) },
+   {"AT25DF321",  INFO(0x1f4700, 0x0, 64 * 1024,64, SECT_4K) },
+   {"AT26DF081A", INFO(0x1f4501, 0x0, 64 * 1024,16, SECT_4K) },
+#endif
+#ifdef CONFIG_SPI_FLASH_EON/* EON */
+   {"EN25Q32B",   INFO(0x1c3016, 0x0, 64 * 1024,64, 0) },
+   {"EN25Q64",INFO(0x1c3017, 0x0, 64 * 1024,   128, SECT_4K) },
+   {"EN25Q128B",  INFO(0x1c3018, 0x0, 64 * 1024,   256, 0) },
+   {"EN25S64",INFO(0x1c3817, 0x0, 64 * 1024,   128, 0) },
+#endif
+#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
+   {"GD25Q64B",   INFO(0xc84017, 0x0, 64 * 1024,   128, SECT_4K) },
+   {"GD25LQ32",   INFO(0xc86016, 0x0, 64 * 1024,64, SECT_4K) },
+#endif
+#ifdef CONFIG_SPI_FLASH_ISSI   /* ISSI */
+   {"IS25LP032",  INFO(0x9d6016, 0x0, 64

[U-Boot] [PATCH v3 26/27] sf: Rename few local functions

[Jagan Teki]

spi_flash_write_bar-> write_bar
spi_flash_write_bar -> read_bar
spi_flash_cmd_wait_ready -> spi_flash_wait_till_ready

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h |  2 +-
 drivers/mtd/spi/spi_flash.c   | 23 +++
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index d50fb9a..2feb3b8 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -184,7 +184,7 @@ static inline int spi_flash_cmd_write_disable(struct 
spi_flash *flash)
  * - SPI claim
  * - spi_flash_cmd_write_enable
  * - spi_flash_cmd_write
- * - spi_flash_cmd_wait_ready
+ * - spi_flash_wait_till_ready
  * - SPI release
  */
 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index c1025c9..b4001a5 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -144,7 +144,7 @@ static int write_evcr(struct spi_flash *flash, u8 evcr)
 #endif
 
 #ifdef CONFIG_SPI_FLASH_BAR
-static int spi_flash_write_bar(struct spi_flash *flash, u32 offset)
+static int write_bar(struct spi_flash *flash, u32 offset)
 {
u8 cmd, bank_sel;
int ret;
@@ -165,8 +165,7 @@ bar_end:
return flash->bank_curr;
 }
 
-static int spi_flash_read_bar(struct spi_flash *flash,
- const struct spi_flash_info *info)
+static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
 {
u8 curr_bank = 0;
int ret;
@@ -263,8 +262,8 @@ static int spi_flash_ready(struct spi_flash *flash)
return sr && fsr;
 }
 
-static int spi_flash_cmd_wait_ready(struct spi_flash *flash,
-   unsigned long timeout)
+static int spi_flash_wait_till_ready(struct spi_flash *flash,
+unsigned long timeout)
 {
unsigned long timebase;
int ret;
@@ -312,7 +311,7 @@ int spi_flash_write_common(struct spi_flash *flash, const 
u8 *cmd,
return ret;
}
 
-   ret = spi_flash_cmd_wait_ready(flash, timeout);
+   ret = spi_flash_wait_till_ready(flash, timeout);
if (ret < 0) {
debug("SF: write %s timed out\n",
  timeout == SPI_FLASH_PROG_TIMEOUT ?
@@ -354,7 +353,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 
offset, size_t len)
spi_flash_dual(flash, &erase_addr);
 #endif
 #ifdef CONFIG_SPI_FLASH_BAR
-   ret = spi_flash_write_bar(flash, erase_addr);
+   ret = write_bar(flash, erase_addr);
if (ret < 0)
return ret;
 #endif
@@ -405,7 +404,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 
offset,
spi_flash_dual(flash, &write_addr);
 #endif
 #ifdef CONFIG_SPI_FLASH_BAR
-   ret = spi_flash_write_bar(flash, write_addr);
+   ret = write_bar(flash, write_addr);
if (ret < 0)
return ret;
 #endif
@@ -509,7 +508,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 
offset,
spi_flash_dual(flash, &read_addr);
 #endif
 #ifdef CONFIG_SPI_FLASH_BAR
-   ret = spi_flash_write_bar(flash, read_addr);
+   ret = write_bar(flash, read_addr);
if (ret < 0)
return ret;
bank_sel = flash->bank_curr;
@@ -561,7 +560,7 @@ static int sst_byte_write(struct spi_flash *flash, u32 
offset, const void *buf)
if (ret)
return ret;
 
-   return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+   return spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
 }
 
 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
@@ -609,7 +608,7 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, 
size_t len,
break;
}
 
-   ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+   ret = spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
if (ret)
break;
 
@@ -1137,7 +1136,7 @@ int spi_flash_scan(struct spi_flash *flash)
 
/* Configure the BAR - discover bank cmds and read current bank */
 #ifdef CONFIG_SPI_FLASH_BAR
-   ret = spi_flash_read_bar(flash, info);
+   ret = read_bar(flash, info);
if (ret < 0)
return ret;
 #endif
-- 
2.7.4

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[U-Boot] [PATCH v3 27/27] spi: Remove dual flash code

[Jagan Teki]

Dual flash code in spi are usually take the spi controller
to work with dual connected flash devices. Usually these
dual connection operation's are referred to flash controller
protocol rather with spi controller protocol, these are still
present in flash side for the usage of spi-nor controllers.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf.c| 4 
 drivers/mtd/spi/spi_flash.c | 1 -
 include/spi.h   | 6 --
 3 files changed, 11 deletions(-)

diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c
index 664e860..d5e175c 100644
--- a/drivers/mtd/spi/sf.c
+++ b/drivers/mtd/spi/sf.c
@@ -18,10 +18,6 @@ static int spi_flash_read_write(struct spi_slave *spi,
unsigned long flags = SPI_XFER_BEGIN;
int ret;
 
-#ifdef CONFIG_SF_DUAL_FLASH
-   if (spi->flags & SPI_XFER_U_PAGE)
-   flags |= SPI_XFER_U_PAGE;
-#endif
if (data_len == 0)
flags |= SPI_XFER_END;
 
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index b4001a5..708991c 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1016,7 +1016,6 @@ int spi_flash_scan(struct spi_flash *flash)
 
flash->name = info->name;
flash->memory_map = spi->memory_map;
-   flash->dual_flash = spi->option;
 
if (info->flags & SST_WR)
flash->flags |= SNOR_F_SST_WR;
diff --git a/include/spi.h b/include/spi.h
index 4c17983..deb65ef 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -30,10 +30,6 @@
 #define SPI_RX_DUALBIT(12) /* receive with 2 wires */
 #define SPI_RX_QUADBIT(13) /* receive with 4 wires */
 
-/* SPI bus connection options - see enum spi_dual_flash */
-#define SPI_CONN_DUAL_SHARED   (1 << 0)
-#define SPI_CONN_DUAL_SEPARATED(1 << 1)
-
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE  0xec
 
@@ -93,7 +89,6 @@ struct dm_spi_slave_platdata {
  * @max_write_size:If non-zero, the maximum number of bytes which can
  * be written at once, excluding command bytes.
  * @memory_map:Address of read-only SPI flash access.
- * @option:Varies SPI bus options - separate, shared bus.
  * @flags: Indication of SPI flags.
  */
 struct spi_slave {
@@ -117,7 +112,6 @@ struct spi_slave {
 #define SPI_XFER_ONCE  (SPI_XFER_BEGIN | SPI_XFER_END)
 #define SPI_XFER_MMAP  BIT(2)  /* Memory Mapped start */
 #define SPI_XFER_MMAP_END  BIT(3)  /* Memory Mapped End */
-#define SPI_XFER_U_PAGEBIT(4)
 };
 
 /**
-- 
2.7.4

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[U-Boot] [PATCH v3 25/27] sf: ids: Use small letter in ext_jedec

[Jagan Teki]

Use small 'd' in s25s512s ext_jedec

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/spi_flash_ids.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index f3c5e3f..9c3a450 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -95,7 +95,7 @@ const struct spi_flash_info spi_flash_ids[] = {
{"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024,   128, RD_FULL | 
WR_QPP) },
{"s25fl256s_64k",  INFO(0x010219, 0x4d01,  64 * 1024,   512, RD_FULL | 
WR_QPP) },
{"s25s256s_64k",   INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | 
WR_QPP | SECT_4K) },
-   {"s25s512s",   INFO(0x010220, 0x4D00, 128 * 1024,   512, RD_FULL | 
WR_QPP) },
+   {"s25s512s",   INFO(0x010220, 0x4d00, 128 * 1024,   512, RD_FULL | 
WR_QPP) },
{"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024,   256, RD_FULL | 
WR_QPP) },
{"s25fl512s_64k",  INFO(0x010220, 0x4d01,  64 * 1024,  1024, RD_FULL | 
WR_QPP) },
{"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024,   256, RD_FULL | 
WR_QPP) },
-- 
2.7.4

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Re: [U-Boot] [PATCH 02/21] imx: mx6ull: add mx6ull major cpu type

[Stefano Babic]

On 11/08/2016 08:02, Peng Fan wrote:
> Add i.MX6ULL major cpu type.
> 
> Signed-off-by: Peng Fan 
> Signed-off-by: Ye Li 
> Cc: Stefano Babic 
> ---
>  arch/arm/imx-common/cpu.c   | 2 ++
>  arch/arm/include/asm/arch-imx/cpu.h | 3 ++-
>  2 files changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
> index 4223187..ddedb08 100644
> --- a/arch/arm/imx-common/cpu.c
> +++ b/arch/arm/imx-common/cpu.c
> @@ -159,6 +159,8 @@ const char *get_imx_type(u32 imxtype)
>   return "6SX";   /* SoloX version of the mx6 */
>   case MXC_CPU_MX6UL:
>   return "6UL";   /* Ultra-Lite version of the mx6 */
> + case MXC_CPU_MX6ULL:
> + return "6ULL";  /* ULL version of the mx6 */
>   case MXC_CPU_MX51:
>   return "51";
>   case MXC_CPU_MX53:
> diff --git a/arch/arm/include/asm/arch-imx/cpu.h 
> b/arch/arm/include/asm/arch-imx/cpu.h
> index 7c63c13..667115b0 100644
> --- a/arch/arm/include/asm/arch-imx/cpu.h
> +++ b/arch/arm/include/asm/arch-imx/cpu.h
> @@ -17,7 +17,8 @@
>  #define MXC_CPU_MX6SX0x62
>  #define MXC_CPU_MX6Q 0x63
>  #define MXC_CPU_MX6UL0x64
> -#define MXC_CPU_MX6SOLO  0x65 /* dummy ID */
> +#define MXC_CPU_MX6ULL   0x65
> +#define MXC_CPU_MX6SOLO  0x66 /* dummy */
>  #define MXC_CPU_MX6D 0x67
>  #define MXC_CPU_MX6DP0x68
>  #define MXC_CPU_MX6QP0x69
> 

Reviewed-by: Stefano Babic 

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 08/21] imx: mx6ul: using runtime check when configuring PMIC_STBY_REQ

[Stefano Babic]

On 11/08/2016 08:02, Peng Fan wrote:
> Since MX6ULL select MX6UL, we can not use IS_ENABLED(CONFIG_MX6UL) here,
> because this piece code is only for i.MX6UL.
> 
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> ---
>  arch/arm/cpu/armv7/mx6/soc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index af7fca5..4083ba5 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -356,7 +356,7 @@ int arch_cpu_init(void)
>   set_ahb_rate(13200);
>   }
>  
> - if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) {
> + if (is_mx6ul() && is_soc_rev(CHIP_REV_1_0) == 0) {
>   /*
>* According to the design team's requirement on i.MX6UL,
>* the PMIC_STBY_REQ PAD should be configured as open
> 
Reviewed-by: Stefano Babic 

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH] net: asix: Fix ASIX 88772B with driver model

[Alban Bedel]

On Tue, 9 Aug 2016 14:32:14 +0200
Marek Vasut  wrote:

> On 08/09/2016 02:14 PM, Marcel Ziswiler wrote:
> > On Thu, 2016-08-04 at 11:12 +0200, Marek Vasut wrote:
> >> On 08/04/2016 11:07 AM, Alban Bedel wrote:
> >>>
> >>> On Wed, 3 Aug 2016 15:23:30 +
> >>> Marcel Ziswiler  wrote:
> >>>
> 
>  On Wed, 2016-08-03 at 15:51 +0200, Marek Vasut wrote:
> >
> > On 08/03/2016 11:46 AM, Alban Bedel wrote:
> >>
> >>
> >> On Wed, 3 Aug 2016 09:00:42 +0200
> >> Marek Vasut  wrote:
> >>
> >>>
> >>>
> >>> On 08/03/2016 07:32 AM, Alban Bedel wrote:
> 
> 
>  Commit 147271209a9d ("net: asix: fix operation without
>  eeprom")
>  added a special handling for ASIX 88772B that enable
>  another
>  type of header. This break the driver in DM mode as the
>  extra
>  handling
>  needed in the receive path is missing.
> >>> So add the extra handling ?
> >> I can do that too, but I though u-boot preferred to avoid
> >> useless
> >> code.
> > Yes, if it is useless.
> >
> >>
> >>
> >>>
> >>>
> 
> 
>  However this new header mode is not required and only
>  seems to
>  increase the code complexity, so this patch revert this
>  part of
>  commit 147271209a9d.
> >>> Why is it not required ?
> >> It works fine without, since 2012. In fact this change is not
> >> even
> >> mentioned in the log of commit 147271209a9d, so I really
> >> don't know
> >> why
> >> it was added in the first place. As can be seen in the revert
> >> all
> >> it
> >> does is adding 2 bytes to the USB packets that are then just
> >> skipped.
> >> Seems pretty useless to me.
> > I would like to get some feedback on this from Marcel, since he
> > added
> > this stuff.
>  Yes, sorry. I just came back from vacation and started looking
>  into it
>  now. As far as I remember on our hardware without this Ethernet
>  did not
>  quite work reliably. This also means that with driver model so
>  far it
>  does not work for us which I fed back to Simon once but so far
>  this has
>  not been resolved. That fix came from some early U-Boot work done
>  by
>  Antmicro way back and I am missing some of the history.
> >>> Then I'll do a new patch that just fix the driver model receive
> >>> path.
> >> Hold on. Marcel, can you maybe test if removing this code has any
> >> impact
> >> on the behavior now ?
> > 
> > Sorry for the delay. I tested Alban's patch now both on Toradex Colibri
> > T20 as well as T30 and its on-module ASIX USB-to-Ethernet chip actually
> > works perfectly aside from the occasional EHCI timed out on TD -
> > token=0x88008d80 Rx: failed to receive: -5 message which last I checked
> > with Simon is still unresolved but was already there long before any of
> > the driver model work started.
> > 
> > Tested-by: Marcel Ziswiler 
> > Tested-on: Colibri T20/T30 on Colibri Evaluation Board
> > 

Will this be applied for the upcoming release?

Alban


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Re: [U-Boot] [PATCH] net: asix: Fix ASIX 88772B with driver model

[Marek Vasut]

On 08/11/2016 10:52 AM, Alban Bedel wrote:
> On Tue, 9 Aug 2016 14:32:14 +0200
> Marek Vasut  wrote:
> 
>> On 08/09/2016 02:14 PM, Marcel Ziswiler wrote:
>>> On Thu, 2016-08-04 at 11:12 +0200, Marek Vasut wrote:
 On 08/04/2016 11:07 AM, Alban Bedel wrote:
>
> On Wed, 3 Aug 2016 15:23:30 +
> Marcel Ziswiler  wrote:
>
>>
>> On Wed, 2016-08-03 at 15:51 +0200, Marek Vasut wrote:
>>>
>>> On 08/03/2016 11:46 AM, Alban Bedel wrote:


 On Wed, 3 Aug 2016 09:00:42 +0200
 Marek Vasut  wrote:

>
>
> On 08/03/2016 07:32 AM, Alban Bedel wrote:
>>
>>
>> Commit 147271209a9d ("net: asix: fix operation without
>> eeprom")
>> added a special handling for ASIX 88772B that enable
>> another
>> type of header. This break the driver in DM mode as the
>> extra
>> handling
>> needed in the receive path is missing.
> So add the extra handling ?
 I can do that too, but I though u-boot preferred to avoid
 useless
 code.
>>> Yes, if it is useless.
>>>


>
>
>>
>>
>> However this new header mode is not required and only
>> seems to
>> increase the code complexity, so this patch revert this
>> part of
>> commit 147271209a9d.
> Why is it not required ?
 It works fine without, since 2012. In fact this change is not
 even
 mentioned in the log of commit 147271209a9d, so I really
 don't know
 why
 it was added in the first place. As can be seen in the revert
 all
 it
 does is adding 2 bytes to the USB packets that are then just
 skipped.
 Seems pretty useless to me.
>>> I would like to get some feedback on this from Marcel, since he
>>> added
>>> this stuff.
>> Yes, sorry. I just came back from vacation and started looking
>> into it
>> now. As far as I remember on our hardware without this Ethernet
>> did not
>> quite work reliably. This also means that with driver model so
>> far it
>> does not work for us which I fed back to Simon once but so far
>> this has
>> not been resolved. That fix came from some early U-Boot work done
>> by
>> Antmicro way back and I am missing some of the history.
> Then I'll do a new patch that just fix the driver model receive
> path.
 Hold on. Marcel, can you maybe test if removing this code has any
 impact
 on the behavior now ?
>>>
>>> Sorry for the delay. I tested Alban's patch now both on Toradex Colibri
>>> T20 as well as T30 and its on-module ASIX USB-to-Ethernet chip actually
>>> works perfectly aside from the occasional EHCI timed out on TD -
>>> token=0x88008d80 Rx: failed to receive: -5 message which last I checked
>>> with Simon is still unresolved but was already there long before any of
>>> the driver model work started.
>>>
>>> Tested-by: Marcel Ziswiler 
>>> Tested-on: Colibri T20/T30 on Colibri Evaluation Board
>>>
> 
> Will this be applied for the upcoming release?

Yeah. Why the hurry though ?


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[U-Boot] [PATCH 1/5] mmc: sd: extracting erase timeout information from sd status

[Peng Fan]

Add function to read SD_STATUS information.
According to the information, get erase_timeout/erase_size/erase_offset.
Add a structure sd_ssr to include the erase related information.

Signed-off-by: Peng Fan 
Cc: Jaehoon Chung 
Cc: Simon Glass 
Cc: Bin Meng 
Cc: Stefan Wahren 
Cc: Clemens Gruber 
Cc: Kever Yang 
Cc: Eric Nelson 
Cc: Stephen Warren 
---
 drivers/mmc/mmc.c | 70 +++
 include/mmc.h |  8 +++
 2 files changed, 78 insertions(+)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 3daa748..efe517a 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -21,6 +21,13 @@
 #include 
 #include "mmc_private.h"
 
+static const unsigned int sd_au_size[] = {
+   0,  SZ_16K / 512,   SZ_32K / 512,   SZ_64K / 512,
+   SZ_128K / 512,  SZ_256K / 512,  SZ_512K / 512,  SZ_1M / 512,
+   SZ_2M / 512,SZ_4M / 512,SZ_8M / 512,(SZ_8M + SZ_4M) 
/ 512,
+   SZ_16M / 512,   (SZ_16M + SZ_8M) / 512, SZ_32M / 512,   SZ_64M / 512,
+};
+
 #ifndef CONFIG_DM_MMC_OPS
 __weak int board_mmc_getwp(struct mmc *mmc)
 {
@@ -942,6 +949,65 @@ retry_scr:
return 0;
 }
 
+static int sd_read_ssr(struct mmc *mmc)
+{
+   int err, i;
+   struct mmc_cmd cmd;
+   ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
+   struct mmc_data data;
+   int timeout;
+   unsigned int au, eo, et, es;
+
+   cmd.cmdidx = MMC_CMD_APP_CMD;
+   cmd.resp_type = MMC_RSP_R1;
+   cmd.cmdarg = mmc->rca << 16;
+
+   err = mmc_send_cmd(mmc, &cmd, NULL);
+   if (err)
+   return err;
+
+   cmd.cmdidx = SD_CMD_APP_SD_STATUS;
+   cmd.resp_type = MMC_RSP_R1;
+   cmd.cmdarg = 0;
+
+   timeout = 3;
+
+retry_ssr:
+   data.dest = (char *)ssr;
+   data.blocksize = 64;
+   data.blocks = 1;
+   data.flags = MMC_DATA_READ;
+
+   err = mmc_send_cmd(mmc, &cmd, &data);
+   if (err) {
+   if (timeout--)
+   goto retry_ssr;
+
+   return err;
+   }
+
+   for (i = 0; i < 16; i++)
+   ssr[i] = be32_to_cpu(ssr[i]);
+
+   au = (ssr[2] >> 12) & 0xF;
+   if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
+   mmc->ssr.au = sd_au_size[au];
+   es = (ssr[3] >> 24) & 0xFF;
+   es |= (ssr[2] & 0xFF) << 8;
+   et = (ssr[3] >> 18) & 0x3F;
+   if (es && et) {
+   eo = (ssr[3] >> 16) & 0x3;
+   mmc->ssr.erase_timeout = (et * 1000) / es;
+   mmc->ssr.erase_offset = eo * 1000;
+   }
+   } else {
+   printf("Invalid Allocation Unit Size.\n");
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
 /* frequency bases */
 /* divided by 10 to be nice to platforms without floating point */
 static const int fbase[] = {
@@ -1347,6 +1413,10 @@ static int mmc_startup(struct mmc *mmc)
mmc_set_bus_width(mmc, 4);
}
 
+   err = sd_read_ssr(mmc);
+   if (err)
+   return err;
+
if (mmc->card_caps & MMC_MODE_HS)
mmc->tran_speed = 5000;
else
diff --git a/include/mmc.h b/include/mmc.h
index aa6d5d1..f09c36f 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -102,6 +102,7 @@
 #define SD_CMD_SWITCH_UHS18V   11
 
 #define SD_CMD_APP_SET_BUS_WIDTH   6
+#define SD_CMD_APP_SD_STATUS   13
 #define SD_CMD_ERASE_WR_BLK_START  32
 #define SD_CMD_ERASE_WR_BLK_END33
 #define SD_CMD_APP_SEND_OP_COND41
@@ -392,6 +393,12 @@ struct mmc_config {
unsigned char part_type;
 };
 
+struct sd_ssr {
+   unsigned int au;/* In sectors */
+   unsigned int erase_timeout; /* In milliseconds */
+   unsigned int erase_offset;  /* In milliseconds */
+};
+
 /*
  * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
  * with mmc_get_mmc_dev().
@@ -426,6 +433,7 @@ struct mmc {
uint write_bl_len;
uint erase_grp_size;/* in 512-byte sectors */
uint hc_wp_grp_size;/* in 512-byte sectors */
+   struct sd_ssr   ssr;
u64 capacity;
u64 capacity_user;
u64 capacity_boot;
-- 
2.6.2

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Re: [U-Boot] [PATCH v2] serial: bcm283x_mu: Detect disabled serial device

[Alexander Graf]

On 09.08.16 06:28, Stephen Warren wrote:
> On 08/04/2016 05:15 PM, Alexander Graf wrote:
>>
>>> On 04 Aug 2016, at 20:11, Stephen Warren  wrote:
>>>
>>> On 08/04/2016 01:11 AM, Alexander Graf wrote:
 On the raspberry pi, you can disable the serial port to gain dynamic
 frequency
 scaling which can get handy at times.

 However, in such a configuration the serial controller gets its rx
 queue filled
 up with zero bytes which then happily get transmitted on to whoever
 calls
 getc() today.

 This patch adds detection logic for that case by checking whether
 the RX pin is
 mapped to GPIO15 and disables the mini uart if it is not mapped
 properly.

 That way we can leave the driver enabled in the tree and can
 determine during
 runtime whether serial is usable or not, having a single binary that
 allows for
 uart and non-uart operation.
>>>
 diff --git a/drivers/serial/serial_bcm283x_mu.c
 b/drivers/serial/serial_bcm283x_mu.c
>>>
 @@ -72,9 +87,18 @@ static int bcm283x_mu_serial_probe(struct udevice
 *dev)
 {
 struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
 struct bcm283x_mu_priv *priv = dev_get_priv(dev);
 +struct bcm283x_gpio_regs *gpio = (struct bcm283x_gpio_regs
 *)plat->gpio;

 priv->regs = (struct bcm283x_mu_regs *)plat->base;

 +/*
 + * The RPi3 disables the mini uart by default. The easiest way
 to find
 + * out whether it is available is to check if the pin is muxed.
 + */
 +if (((readl(&gpio->gpfsel1) >> BCM283X_GPIO_GPFSEL1_F15_SHIFT) &
 +BCM283X_GPIO_ALTFUNC_MASK) != BCM283X_GPIO_ALTFUNC_5)
 +priv->disabled = true;
 +
 return 0;
>>>
>>> Comment on the current implementation: Can't probe() return an error
>>> if the device should be disabled? That would avoid the need to check
>>> priv->disabled in all the other functions.
>>
>> I guess I should’ve put that in a comment somewhere. Unfortunately we
>> can’t. If I just return an error on probe, U-Boot will panic because
>> we tell it in a CONFIG define that we require a serial port (grep for
>> CONFIG_REQUIRE_SERIAL_CONSOLE).
>>
>> We could maybe try to unset that define instead?
> 
> Yes, assuming that U-Boot runs just fine with HDMI console only, I think
> it's fine to unset CONFIG_REQUIRE_SERIAL_CONSOLE.
> 
>>> Overall comment: I'd rather not put this logic into the UART driver
>>> itself; it is system-specific rather than device-specific. I'd also
>>> rather not have the UART driver touching GPIO registers; that's not
>>> very modular, and could cause problems if the Pi is converted to use
>>> DT to instantiate devices.
>>>
>>> Instead, can we put the logic into board/raspberrypi/rpi/rpi.c? I.e.
>>> have some early function come along and enable/disable the
>>> bcm2837_serials device object as appropriate? That way it isolates
>>> the code to the Pi specifically, and not any other bcm283x board.
>>> We'd want to wrap that code in #ifdef CONFIG_PL01X_SERIAL.
>>
>> We can do that if we can fail at probe time. If we absolutely must
>> have a serial driver to work in the first place, that doesn’t work. I
>> can try to poke at it, but it’ll be a few days I think :).

So I couldn't find a sane way to fail probing based on something defined
in the board file, reusing the existing gpio device.

However, there's an easy alternative. We can make the console code just
ignore our serial device if we set its pointer to NULL. That way we
still have the device, but can contain all logic to disable usage of the
mini uart to the board file.


Alex
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Re: [U-Boot] disabling mmc in spl when booting using bootrom

[Ziyuan Xu]

On 2016年08月11日 19:31, Sandy Patterson wrote:

Simon,

I am trying to format a patch to disable MMC in the SPL if booting 
main u-boot using BOOTROM, therefore the SPL MMC isn't needed.


Is the best solution to wrap every header file (rock2.h 
firefly-rk3288.h, etc) with ifdefs on the BACK_TO_BROM define? Or 
would it be better to move the SPL MMC define into rk3288-common.h and 
just have chromebook_jerry undef it like it does the SPL GPIO code.


With that change, enabling BOOT_TO_BROM shrinks the spl from 32K to 23K.
Note that, firefly-rk3288 use OF_PLATDATA, we will use 
u-boot-spl-no-dtb.bin instead of u-boot-spl-dtb.bin, and the size of 
u-boot-spl-no-dtb.bin is almost 23K.


@Simon, I think we will update doc/README.rockchip if you insist on 
OF_PLATDATA for firefly-rk3288. we no longer use u-boot-spl-dtb.bin.:-)


Sandy



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Re: [U-Boot] disabling mmc in spl when booting using bootrom

[Sandy Patterson]

On Thu, Aug 11, 2016 at 7:35 AM, Ziyuan Xu  wrote:

>
>
> On 2016年08月11日 19:31, Sandy Patterson wrote:
>
>> Simon,
>>
>> I am trying to format a patch to disable MMC in the SPL if booting main
>> u-boot using BOOTROM, therefore the SPL MMC isn't needed.
>>
>> Is the best solution to wrap every header file (rock2.h firefly-rk3288.h,
>> etc) with ifdefs on the BACK_TO_BROM define? Or would it be better to move
>> the SPL MMC define into rk3288-common.h and just have chromebook_jerry
>> undef it like it does the SPL GPIO code.
>>
>> With that change, enabling BOOT_TO_BROM shrinks the spl from 32K to 23K.
>>
> Note that, firefly-rk3288 use OF_PLATDATA, we will use
> u-boot-spl-no-dtb.bin instead of u-boot-spl-dtb.bin, and the size of
> u-boot-spl-no-dtb.bin is almost 23K.
>

The patch would apply if OF_PLATDATA is used too (Although I haven't tested
it). It would just shrink the SPL more right because you don't need the MMC
driver. I wasn't planning to change any of the defconfigs.


>
> @Simon, I think we will update doc/README.rockchip if you insist on
> OF_PLATDATA for firefly-rk3288. we no longer use u-boot-spl-dtb.bin.:-)
>
>>
>> Sandy
>>
>
>
>
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[U-Boot] [PATCH 2/5] configs: am43xx: Enable CMD_TIME

[Lokesh Vutla]

Enable CONFIG_CMD_TIME for all am43xx platforms

Signed-off-by: Lokesh Vutla 
---
 configs/am43xx_evm_defconfig  | 1 +
 configs/am43xx_evm_ethboot_defconfig  | 1 +
 configs/am43xx_evm_qspiboot_defconfig | 1 +
 configs/am43xx_evm_usbhost_boot_defconfig | 1 +
 configs/am43xx_hs_evm_defconfig   | 1 +
 5 files changed, 5 insertions(+)

diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index b3fe269..9cb06aa 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -56,3 +56,4 @@ CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_DM_I2C=y
+CONFIG_CMD_TIME=y
diff --git a/configs/am43xx_evm_ethboot_defconfig 
b/configs/am43xx_evm_ethboot_defconfig
index 3b958d7..aef1144 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -42,3 +42,4 @@ CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
 CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
+CONFIG_CMD_TIME=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig 
b/configs/am43xx_evm_qspiboot_defconfig
index c6bc8e4..e4b65c6 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -42,3 +42,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
+CONFIG_CMD_TIME=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig 
b/configs/am43xx_evm_usbhost_boot_defconfig
index 34c875e..d993a13 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -57,3 +57,4 @@ CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
+CONFIG_CMD_TIME=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index c8ce723..388bb1b 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -59,3 +59,4 @@ CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_DM_I2C=y
+CONFIG_CMD_TIME=y
-- 
2.9.2

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[U-Boot] [PATCH 3/5] configs: am57xx: Enable CMD_TIME

[Lokesh Vutla]

Enable CONFIG_CMD_TIME for all am57x platforms

Signed-off-by: Lokesh Vutla 
---
 configs/am57xx_evm_defconfig| 1 +
 configs/am57xx_hs_evm_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index c95f45a..1649466 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -46,3 +46,4 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_TI_QSPI=y
 CONFIG_CMD_SF=y
+CONFIG_CMD_TIME=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index a4bfdd5..2ef92ce 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -48,3 +48,4 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_TI_QSPI=y
 CONFIG_CMD_SF=y
+CONFIG_CMD_TIME=y
-- 
2.9.2

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[U-Boot] [PATCH 5/5] configs: ks2: Enable CMD_TIME

[Lokesh Vutla]

Enable CMD_TIME on all keystone2 platforms

Signed-off-by: Lokesh Vutla 
---
 configs/k2e_evm_defconfig  | 1 +
 configs/k2g_evm_defconfig  | 1 +
 configs/k2hk_evm_defconfig | 1 +
 configs/k2l_evm_defconfig  | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 04c52f0..155e567 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -39,3 +39,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_LIB_RAND=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CMD_TIME=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 5d44e8d..d412f52 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -39,3 +39,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_CMD_TIME=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index c050f07..bc41392 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -39,3 +39,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_LIB_RAND=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CMD_TIME=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index e1386f7..6eb0141 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -39,3 +39,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_LIB_RAND=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CMD_TIME=y
-- 
2.9.2

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Re: [U-Boot] [PATCH 00/14] ARM: uniphier: updates for v2016.09-rc2

[Masahiro Yamada]

2016-08-10 16:08 GMT+09:00 Masahiro Yamada :
>
> Cleanups, Fixes, and PSCI support.
>
>
>
> Masahiro Yamada (14):
>   ARM: uniphier: refactor outer cache code
>   ARM: uniphier: support prefetch and touch operations for outer cache
>   ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabled
>   ARM: uniphier: refactor L2 zero-touching code in lowlevel_init
>   ARM: uniphier: fix ROM boot mode for PH1-sLD3
>   ARM: uniphier: move lowlevel debug init code after page table switch
>   ARM: uniphier: export uniphier_cache_enable/disable functions
>   ARM: uniphier: reuse uniphier_cache_disable() for lowlevel_init
>   ARM: uniphier: move outer cache register macros to .c file
>   ARM: uniphier: move (and rename) CONFIG_UNIPHIER_L2CACHE_ON to Kconfig
>   ARM: uniphier: fix CONFIG_SYS_CACHELINE_SIZE when outer cache is on
>   ARM: uniphier: add uniphier_cache_inv_way() to support way
> invalidation
>   ARM: uniphier: add uniphier_cache_set_active_ways()
>   ARM: uniphier: add PSCI support for UniPhier ARMv7 SoCs

Series, applied to u-boot-uniphier/master.



-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH 0/5] ARM: Enable CMD_TIME on all TI platforms

[Tom Rini]

On Thu, Aug 11, 2016 at 06:39:12PM +0530, Lokesh Vutla wrote:

> This series enables CMD_TIME on all TI platforms.
> 
> Lokesh Vutla (5):
>   configs: am335x: Enable CMD_TIME
>   configs: am43xx: Enable CMD_TIME
>   configs: am57xx: Enable CMD_TIME
>   configs: dra7xx: Enable CMD_TIME
>   configs: ks2: Enable CMD_TIME
> 
>  configs/am335x_boneblack_defconfig| 1 +
>  configs/am335x_evm_defconfig  | 1 +
>  configs/am335x_evm_nor_defconfig  | 1 +
>  configs/am335x_evm_norboot_defconfig  | 1 +
>  configs/am335x_evm_spiboot_defconfig  | 1 +
>  configs/am335x_evm_usbspl_defconfig   | 1 +
>  configs/am43xx_evm_defconfig  | 1 +
>  configs/am43xx_evm_ethboot_defconfig  | 1 +
>  configs/am43xx_evm_qspiboot_defconfig | 1 +
>  configs/am43xx_evm_usbhost_boot_defconfig | 1 +
>  configs/am43xx_hs_evm_defconfig   | 1 +
>  configs/am57xx_evm_defconfig  | 1 +
>  configs/am57xx_hs_evm_defconfig   | 1 +
>  configs/dra7xx_evm_defconfig  | 1 +
>  configs/dra7xx_hs_evm_defconfig   | 1 +
>  configs/k2e_evm_defconfig | 1 +
>  configs/k2g_evm_defconfig | 1 +
>  configs/k2hk_evm_defconfig| 1 +
>  configs/k2l_evm_defconfig | 1 +
>  19 files changed, 19 insertions(+)

This would have been a 1 line change to
include/configs/ti_armv7_common.h and is now 19 files and 19 lines, so a
step backwards.  Further, this isn't a SoC thing, it's a TI eval
platform consistency (and I imagine testing) thing.  I think it's time
to look at adding in board/ti/Kconfig (and other vendors too given the
existing include/configs/*common* files) for style things that don't
belong in arch/arm/cpu/armv7/omap-common/Kconfig (which needs to get
moved to arch/arm/mach-omap to match other platforms, yes) in this case.

The first patch to introduce board/ti/Kconfig will be "big" as the
board/ti/*/Kconfig will need to bring it in but follow up migration of
stuff out of include/configs/ti_*common.h will be smaller.

Thanks!

-- 
Tom


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[U-Boot] [PATCH 4/5] configs: dra7xx: Enable CMD_TIME

[Lokesh Vutla]

Enable CONFIG_CMD_TIME for all dra7xx platforms

Signed-off-by: Lokesh Vutla 
---
 configs/dra7xx_evm_defconfig| 1 +
 configs/dra7xx_hs_evm_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 81d2a0e..b6df7ae 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -59,3 +59,4 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_LIST="dra7-evm dra72-evm"
 CONFIG_DM_I2C=y
 CONFIG_PCF8575_GPIO=y
+CONFIG_CMD_TIME=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index ab68b1c..2848094 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -62,3 +62,4 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 CONFIG_OF_LIST="dra7-evm dra72-evm"
 CONFIG_DM_I2C=y
 CONFIG_PCF8575_GPIO=y
+CONFIG_CMD_TIME=y
-- 
2.9.2

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[U-Boot] [PATCH] ARM: make ARMV7_LPAE select PHYS_64BIT

[Masahiro Yamada]

As you see in arch/arm/include/asm/types.h, CONFIG_PHYS_64BIT
determines the size of phys_addr_t.  The ARM Large Physical Address
Extension allows CPUs to access a physical address space larger than
4GB, so the physical address may not fit in 32bit long phys_addr_t.

Signed-off-by: Masahiro Yamada 
---

I did Buildman test, but not run-time test.

Looks like bcm283x (RPI) is the only arch that selects ARMV7_LPAE,
so I hope Stephen will check this patch.


 arch/arm/cpu/armv7/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index 0560178..1697e61 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -45,6 +45,7 @@ config ARMV7_PSCI_NR_CPUS
 config ARMV7_LPAE
boolean "Use LPAE page table format" if EXPERT
depends on CPU_V7
+   select PHYS_64BIT
default n
---help---
Say Y here to use the long descriptor page table format. This is
-- 
1.9.1

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Re: [U-Boot] [PATCH v2 0/5] Enable caches for the RPi2

[Alexander Graf]

On 25.03.16 05:13, Stephen Warren wrote:
> On 03/16/2016 08:41 AM, Alexander Graf wrote:
>> This patch set converts the Raspberry Pi 2 system to properly make use of
>> the caches available in it.
>>
>> Because we're running in HYP mode, we first need to teach U-Boot how to
>> make use of HYP registers and the LPAE page layout which is mandated by
>> hardware when running in HYP mode.
>>
>> Then while we're at it, also mark the frame buffer cached to speed up
>> screen updates.
>>
>> With this patch set, my Raspberry Pi 3 running in AArch32 mode is a *lot*
>> faster than without.
>>
>> Please verify that the code works on a RPi2 as well and doesn't break the
>> original Pi. In theory it should work, but I only have a 3 to test on
>> available here.
> 
> I did find one quirk with this series (as tested in my rpi_dev branch on
> github): HDMI console scrolling is now extremely fast for 32-bit builds.
> However, it's noticeably slower on the 64-bit RPi 3 build. I wonder if
> the DCACHE_* constants aren't optimal for AArch64? Perhaps this can all
> be explained instead by RPi 3 needing a slower core clock to support a
> fixed mini UART frequency; that probably slows down the ARM access to DRAM.

I tried with the latest code and my patches that allow for disabled
uart, so that the core shouldn't get slowed down anymore.

It still does feel significantly slower than it should.

We set the memory type to WRITEBACK which translates to index 4 into MAIR

  DCACHE_WRITEBACK = 4 << 2,

->

  #define MT_NORMAL   4

So we need to look at what MAIR 4 looks like:

  #define MEMORY_ATTRIBUTES [...] |
(UL(0xff) << (MT_NORMAL * 8)))

and that is

  Normal Memory, Outer Write-back non-transient
  Outer Read Allocate
  Outer Write Allocate
  Normal Memory, Inner Write-back non-transient
  Inner Read Allocate
  Inner Write Allocate

So we should be using as much cache as we can ;). I'm not quite sure why
it's still slower than you'd expect though. Hrm.


Alex
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Re: [U-Boot] [PATCH] ARM: make ARMV7_LPAE select PHYS_64BIT

[Alexander Graf]

On 11.08.16 15:36, Masahiro Yamada wrote:
> As you see in arch/arm/include/asm/types.h, CONFIG_PHYS_64BIT
> determines the size of phys_addr_t.  The ARM Large Physical Address
> Extension allows CPUs to access a physical address space larger than
> 4GB, so the physical address may not fit in 32bit long phys_addr_t.
> 
> Signed-off-by: Masahiro Yamada 
> ---
> 
> I did Buildman test, but not run-time test.
> 
> Looks like bcm283x (RPI) is the only arch that selects ARMV7_LPAE,
> so I hope Stephen will check this patch.

Well, the bcm2837 still only has a 32bit bus, so we can't actually make
use of addresses bigger than 32bits.

I think it would make most sense to select PHYS_64BIT on whatever 32bit
SoC actually needs to accesses memory above 4GB.

The main reason for having LPAE support for armv7 is not to support
higher addresses (we still map everything 1:1 usually), it's to allow
running in HYP mode which requires LPAE style page tables.


Alex
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Re: [U-Boot] [PATCH v3 00/27] spi/sf: Updates on flash detection

[york sun]

On 08/11/2016 08:12 AM, york@nxp.com wrote:
> On 08/11/2016 01:15 AM, Jagan Teki wrote:
>>
>> Tested on microzed and sandbox
>>
>> Tested-by: Jagan Teki 
>>
>> I've some host issues while running buildman, can anyone please run
>> buildman?
>>
>
> I can compile for power and (limited) arm for you.
>

I can't compile test your v3 patch. They are not in mailing list, or 
patchwork. I only got some of them.

York

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[U-Boot] [PATCH] tools/env: ensure environment starts at erase block boundary

[Andreas Fenkart]

56086921 added support for unaligned environments access.
U-boot itself does not support this:
- env_nand.c fails when using an unaligned offset. It produces an
  error in nand_erase_opts{drivers/mtd/nand/nand_util.c}
- in env_sf/env_flash the unused space at the end is preserved, but
  not in the beginning. block alignment is assumed
- env_sata/env_mmc aligns offset/length to the block size of the
  underlying device. data is silently redirected to the beginning of
  a block

There is seems no use case for unaligned environment. If there is
some useful data at the beginning of the the block (e.g. end of u-boot)
that would be very unsafe. If the redundant environments are hosted by
the same erase block then that invalidates the idea of double buffering.
It might be that unaligned access was allowed in the past, and that
people with legacy u-boot are trapped. But at the time of 56086921
it wasn't supported and due to reasons above I guess it was never
introduced.
I prefer to remove that (unused) feature in favor of simplicity

Signed-off-by: Andreas Fenkart 
---
 tools/env/fw_env.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 6b0dcaa..2ccc617 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -1294,6 +1294,18 @@ static int check_device_config(int dev)
struct stat st;
int fd, rc = 0;
 
+   if (DEVOFFSET(dev) % DEVESIZE(dev) != 0) {
+   fprintf(stderr, "Environment does not start on erase block 
boundary\n");
+   errno = EINVAL;
+   return -1;
+   }
+
+   if (ENVSIZE(i) > ENVSECTORS(i) * DEVESIZE(i)) {
+   fprintf(stderr, "Environment does not fit into available 
sectors\n");
+   errno = EINVAL;
+   return -1;
+   }
+
fd = open(DEVNAME(dev), O_RDONLY);
if (fd < 0) {
fprintf(stderr,
-- 
2.8.1

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Re: [U-Boot] [PATCH v3 00/27] spi/sf: Updates on flash detection

[Tom Rini]

On Thu, Aug 11, 2016 at 09:47:44PM +0530, Jagan Teki wrote:
> On 11 August 2016 at 20:47, york sun  wrote:
> > On 08/11/2016 08:12 AM, york@nxp.com wrote:
> >> On 08/11/2016 01:15 AM, Jagan Teki wrote:
> >>>
> >>> Tested on microzed and sandbox
> >>>
> >>> Tested-by: Jagan Teki 
> >>>
> >>> I've some host issues while running buildman, can anyone please run
> >>> buildman?
> >>>
> >>
> >> I can compile for power and (limited) arm for you.
> >>
> >
> > I can't compile test your v3 patch. They are not in mailing list, or
> > patchwork. I only got some of them.
> 
> Ohh..look like these are not in patchwork, Tom any idea?

They don't appear in the mail archives right now either.  Wolfgang?

-- 
Tom


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[U-Boot] [PATCH v2 7/7] smbios: Provide serial number

[Alexander Graf]

If the system has a valid "serial#" environment variable set (which boards that
can find it out programatically set automatically), use that as input for the
serial number and UUID fields in the SMBIOS tables.

Signed-off-by: Alexander Graf 

---

v1 -> v2:

  - Also populate UUID
---
 lib/smbios.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/lib/smbios.c b/lib/smbios.c
index 4d85155..2d0df23 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -111,11 +111,16 @@ static int smbios_write_type1(uintptr_t *current, int 
handle)
 {
struct smbios_type1 *t = (struct smbios_type1 *)*current;
int len = sizeof(struct smbios_type1);
+   char *serial_str = getenv("serial#");
 
memset(t, 0, sizeof(struct smbios_type1));
fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle);
t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
+   if (serial_str) {
+   strncpy((char*)t->uuid, serial_str, sizeof(t->uuid));
+   t->serial_number = smbios_add_string(t->eos, serial_str);
+   }
 
len = t->length + smbios_string_table_len(t->eos);
*current += len;
-- 
1.8.5.6

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[U-Boot] [PATCH v3] drivers: net: cpsw: always flush cache of size aligned to PKTALIGN

[Lokesh Vutla]

cpsw tries to flush dcache which is not in the range of PKTALIGN.
Because of this the following warning comes while flushing:

CACHE: Misaligned operation at range [dffecec0, dffed016]

Fix it by flushing cache of size aligned to PKTALIGN.

Signed-off-by: Lokesh Vutla 
---
 drivers/net/cpsw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 2ce4ec6..300a534 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -907,7 +907,7 @@ static int _cpsw_send(struct cpsw_priv *priv, void *packet, 
int length)
int timeout = CPDMA_TIMEOUT;
 
flush_dcache_range((unsigned long)packet,
-  (unsigned long)packet + length);
+  (unsigned long)packet + ALIGN(length, PKTALIGN));
 
/* first reap completed packets */
while (timeout-- &&
-- 
2.9.2

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[U-Boot] [PATCH v3 03/27] spi: Use mode for rx mode flags

[Jagan Teki]

Make rx mode flags as generic to spi, earlier mode_rx is
maintained separately because of some flash specific code.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Cc: Vignesh R 
Cc: Mugunthan V N 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/spi_flash.c |  6 +++---
 drivers/spi/cadence_qspi.c  |  2 +-
 drivers/spi/ich.c   |  6 ++
 drivers/spi/spi-uclass.c| 11 ---
 drivers/spi/ti_qspi.c   |  6 +++---
 include/spi.h   | 14 --
 6 files changed, 17 insertions(+), 28 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 5fd408c..041b64f 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1172,11 +1172,11 @@ int spi_flash_scan(struct spi_flash *flash)
 
/* Look for read commands */
flash->read_cmd = CMD_READ_ARRAY_FAST;
-   if (spi->mode_rx & SPI_RX_SLOW)
+   if (spi->mode & SPI_RX_SLOW)
flash->read_cmd = CMD_READ_ARRAY_SLOW;
-   else if (spi->mode_rx & SPI_RX_QUAD && params->flags & RD_QUAD)
+   else if (spi->mode & SPI_RX_QUAD && params->flags & RD_QUAD)
flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST;
-   else if (spi->mode_rx & SPI_RX_DUAL && params->flags & RD_DUAL)
+   else if (spi->mode & SPI_RX_DUAL && params->flags & RD_DUAL)
flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST;
 
/* Look for write commands */
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index a5244ff..1d50f13 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -251,7 +251,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
break;
case CQSPI_INDIRECT_READ:
err = cadence_qspi_apb_indirect_read_setup(plat,
-   priv->cmd_len, dm_plat->mode_rx, cmd_buf);
+   priv->cmd_len, dm_plat->mode, cmd_buf);
if (!err) {
err = cadence_qspi_apb_indirect_read_execute
(plat, data_bytes, din);
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 00b2fed..caf0103 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -649,10 +649,8 @@ static int ich_spi_child_pre_probe(struct udevice *dev)
 * ICH 7 SPI controller only supports array read command
 * and byte program command for SST flash
 */
-   if (plat->ich_version == ICHV_7) {
-   slave->mode_rx = SPI_RX_SLOW;
-   slave->mode = SPI_TX_BYTE;
-   }
+   if (plat->ich_version == ICHV_7)
+   slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
 
return 0;
 }
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 247abfa..d9c49e4 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -164,7 +164,6 @@ static int spi_child_pre_probe(struct udevice *dev)
 
slave->max_hz = plat->max_hz;
slave->mode = plat->mode;
-   slave->mode_rx = plat->mode_rx;
slave->wordlen = SPI_DEFAULT_WORDLEN;
 
return 0;
@@ -381,7 +380,7 @@ void spi_free_slave(struct spi_slave *slave)
 int spi_slave_ofdata_to_platdata(const void *blob, int node,
 struct dm_spi_slave_platdata *plat)
 {
-   int mode = 0, mode_rx = 0;
+   int mode = 0;
int value;
 
plat->cs = fdtdec_get_int(blob, node, "reg", -1);
@@ -413,24 +412,22 @@ int spi_slave_ofdata_to_platdata(const void *blob, int 
node,
break;
}
 
-   plat->mode = mode;
-
value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1);
switch (value) {
case 1:
break;
case 2:
-   mode_rx |= SPI_RX_DUAL;
+   mode |= SPI_RX_DUAL;
break;
case 4:
-   mode_rx |= SPI_RX_QUAD;
+   mode |= SPI_RX_QUAD;
break;
default:
error("spi-rx-bus-width %d not supported\n", value);
break;
}
 
-   plat->mode_rx = mode_rx;
+   plat->mode = mode;
 
return 0;
 }
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index bb72cb0..e51cbd0 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -336,7 +336,7 @@ static void ti_spi_setup_spi_register(struct ti_qspi_priv 
*priv)
QSPI_SETUP0_NUM_D_BYTES_8_BITS |
QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
QSPI_NUM_DUMMY_BITS);
-   slave->mode_rx = SPI_RX_QUAD;
+   slave->mode |= SPI_RX_QUAD;
 #else
memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
@@ -422,7 +422,7 @@ static void __ti_qspi_setup_memorymap(struct ti_qspi_priv 
*priv,
  bool enable)
 {
u32 memval;
-   

[U-Boot] [PATCH v3 05/27] sf: Remove SECT_32K

[Jagan Teki]

SECT_32K never used anywhere in the code.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Cc: Vignesh R 
Cc: Mugunthan V N 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sandbox.c |  5 +
 drivers/mtd/spi/sf_internal.h | 16 +++-
 drivers/mtd/spi/spi_flash.c   |  3 ---
 3 files changed, 8 insertions(+), 16 deletions(-)

diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 53470b9..f59134f 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -292,10 +292,7 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash 
*sbsf, const u8 *rx,
sbsf->data->nr_sectors;
} else if (sbsf->cmd == CMD_ERASE_4K && (flags & SECT_4K)) {
sbsf->erase_size = 4 << 10;
-   } else if (sbsf->cmd == CMD_ERASE_32K && (flags & SECT_32K)) {
-   sbsf->erase_size = 32 << 10;
-   } else if (sbsf->cmd == CMD_ERASE_64K &&
-  !(flags & (SECT_4K | SECT_32K))) {
+   } else if (sbsf->cmd == CMD_ERASE_64K && !(flags & SECT_4K)) {
sbsf->erase_size = 64 << 10;
} else {
debug(" cmd unknown: %#x\n", sbsf->cmd);
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 71ba1a6..9eb0b84 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -27,14 +27,13 @@ enum {
 #else
SECT_4K = BIT(0),
 #endif
-   SECT_32K= BIT(1),
-   E_FSR   = BIT(2),
-   SST_WR  = BIT(3),
-   WR_QPP  = BIT(4),
-   RD_QUAD = BIT(5),
-   RD_DUAL = BIT(6),
-   RD_QUADIO   = BIT(7),
-   RD_DUALIO   = BIT(8),
+   E_FSR   = BIT(1),
+   SST_WR  = BIT(2),
+   WR_QPP  = BIT(3),
+   RD_QUAD = BIT(4),
+   RD_DUAL = BIT(5),
+   RD_QUADIO   = BIT(6),
+   RD_DUALIO   = BIT(7),
 };
 #define RD_FULLRD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO
 
@@ -57,7 +56,6 @@ enum spi_nor_option_flags {
 
 /* Erase commands */
 #define CMD_ERASE_4K   0x20
-#define CMD_ERASE_32K  0x52
 #define CMD_ERASE_CHIP 0xc7
 #define CMD_ERASE_64K  0xd8
 
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 041b64f..2b2a409 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1159,9 +1159,6 @@ int spi_flash_scan(struct spi_flash *flash)
if (params->flags & SECT_4K) {
flash->erase_cmd = CMD_ERASE_4K;
flash->erase_size = 4096 << flash->shift;
-   } else if (params->flags & SECT_32K) {
-   flash->erase_cmd = CMD_ERASE_32K;
-   flash->erase_size = 32768 << flash->shift;
} else {
flash->erase_cmd = CMD_ERASE_64K;
flash->erase_size = flash->sector_size;
-- 
2.7.4

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[U-Boot] [PATCH 3/5] mmc: sd: add erase timeout support

[Peng Fan]

Add timeout in mmc_cmd, we can use this in driver code.
Add mmc_sd_erase_timeout, this function is modified from linux kernel.

Signed-off-by: Peng Fan 
Cc: Jaehoon Chung 
Cc: Simon Glass 
Cc: Bin Meng 
Cc: Stefan Wahren 
Cc: Clemens Gruber 
Cc: Kever Yang 
Cc: Eric Nelson 
Cc: Stephen Warren 
---
 drivers/mmc/mmc_write.c | 29 +
 include/mmc.h   |  1 +
 2 files changed, 30 insertions(+)

diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index 4149f4a..3589f8e 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -15,6 +15,33 @@
 #include 
 #include "mmc_private.h"
 
+/*
+ * Modified from from Linux kernel mmc_sd_erase_timeout.
+ */
+static unsigned int mmc_sd_erase_timeout(struct mmc *mmc,
+unsigned int nr)
+{
+   unsigned int erase_timeout;
+
+   if (mmc->ssr.erase_timeout) {
+   /* Erase timeout specified in SD Status Register (SSR) */
+   erase_timeout = mmc->ssr.erase_timeout * nr +
+   mmc->ssr.erase_offset;
+   } else {
+   /*
+* Erase timeout not specified in SD Status Register (SSR) so
+* use 250ms per write block.
+*/
+   erase_timeout = 250 * nr;
+   }
+
+   /* Must not be less than 1 second */
+   if (erase_timeout < 1000)
+   erase_timeout = 1000;
+
+   return erase_timeout;
+}
+
 static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)
 {
struct mmc_cmd cmd = {0};
@@ -54,6 +81,8 @@ static ulong mmc_erase_t(struct mmc *mmc, ulong start, 
lbaint_t blkcnt)
cmd.cmdidx = MMC_CMD_ERASE;
cmd.cmdarg = MMC_ERASE_ARG;
cmd.resp_type = MMC_RSP_R1b;
+   if (IS_SD(mmc))
+   cmd.timeout = mmc_sd_erase_timeout(mmc, blkcnt);
 
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
diff --git a/include/mmc.h b/include/mmc.h
index f09c36f..c72495c 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -303,6 +303,7 @@ struct mmc_cmd {
uint resp_type;
uint cmdarg;
uint response[4];
+   int timeout;
 };
 
 struct mmc_data {
-- 
2.6.2

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[U-Boot] [PATCH 5/5] mmc: sd: optimize erase

[Peng Fan]

To SD, there is no erase group, then the value erase_grp_size
will be default 1. When erasing SD blocks, the blocks will be
erased one by one, which is time consuming.

use AU_SIZE as a group to speed up the erasing.

Signed-off-by: Peng Fan 
Cc: Jaehoon Chung 
Cc: Simon Glass 
Cc: Bin Meng 
Cc: Stefan Wahren 
Cc: Clemens Gruber 
Cc: Kever Yang 
Cc: Eric Nelson 
Cc: Stephen Warren 
---
 drivers/mmc/mmc_write.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index 3589f8e..6221b4a 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -129,8 +129,13 @@ unsigned long mmc_berase(struct blk_desc *block_dev, 
lbaint_t start,
   & ~(mmc->erase_grp_size - 1)) - 1);
 
while (blk < blkcnt) {
-   blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?
-   mmc->erase_grp_size : (blkcnt - blk);
+   if (IS_SD(mmc) && mmc->ssr.au) {
+   blk_r = ((blkcnt - blk) > mmc->ssr.au) ?
+   mmc->ssr.au : (blkcnt - blk);
+   } else {
+   blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?
+   mmc->erase_grp_size : (blkcnt - blk);
+   }
err = mmc_erase_t(mmc, start + blk, blk_r);
if (err)
break;
-- 
2.6.2

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[U-Boot] [PATCH 2/5] mmc: initialize mmc_cmd with 0

[Peng Fan]

Using {0} to initialize mmc_cmd, before filling the structure.

Signed-off-by: Peng Fan 
Cc: Jaehoon Chung 
Cc: Simon Glass 
Cc: Bin Meng 
Cc: Stefan Wahren 
Cc: Clemens Gruber 
Cc: Kever Yang 
Cc: Eric Nelson 
Cc: Stephen Warren 
---
 drivers/mmc/mmc.c   | 28 ++--
 drivers/mmc/mmc_write.c |  4 ++--
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index efe517a..21bd0dc 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -139,7 +139,7 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 
struct mmc_data *data)
 
 int mmc_send_status(struct mmc *mmc, int timeout)
 {
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
int err, retries = 5;
 
cmd.cmdidx = MMC_CMD_SEND_STATUS;
@@ -183,7 +183,7 @@ int mmc_send_status(struct mmc *mmc, int timeout)
 
 int mmc_set_blocklen(struct mmc *mmc, int len)
 {
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
 
if (mmc->ddr_mode)
return 0;
@@ -198,7 +198,7 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
   lbaint_t blkcnt)
 {
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
struct mmc_data data;
 
if (blkcnt > 1)
@@ -291,7 +291,7 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, 
lbaint_t blkcnt,
 
 static int mmc_go_idle(struct mmc *mmc)
 {
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
int err;
 
udelay(1000);
@@ -314,7 +314,7 @@ static int sd_send_op_cond(struct mmc *mmc)
 {
int timeout = 1000;
int err;
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
 
while (1) {
cmd.cmdidx = MMC_CMD_APP_CMD;
@@ -380,7 +380,7 @@ static int sd_send_op_cond(struct mmc *mmc)
 
 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
 {
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
int err;
 
cmd.cmdidx = MMC_CMD_SEND_OP_COND;
@@ -422,7 +422,7 @@ static int mmc_send_op_cond(struct mmc *mmc)
 
 static int mmc_complete_op_cond(struct mmc *mmc)
 {
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
int timeout = 1000;
uint start;
int err;
@@ -466,7 +466,7 @@ static int mmc_complete_op_cond(struct mmc *mmc)
 
 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
 {
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
struct mmc_data data;
int err;
 
@@ -487,7 +487,7 @@ static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
 
 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 {
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
int timeout = 1000;
int ret;
 
@@ -820,7 +820,7 @@ int mmc_getcd(struct mmc *mmc)
 
 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
 {
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
struct mmc_data data;
 
/* Switch the frequency */
@@ -842,7 +842,7 @@ static int sd_switch(struct mmc *mmc, int mode, int group, 
u8 value, u8 *resp)
 static int sd_change_freq(struct mmc *mmc)
 {
int err;
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
struct mmc_data data;
@@ -952,7 +952,7 @@ retry_scr:
 static int sd_read_ssr(struct mmc *mmc)
 {
int err, i;
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
struct mmc_data data;
int timeout;
@@ -1072,7 +1072,7 @@ static int mmc_startup(struct mmc *mmc)
int err, i;
uint mult, freq;
u64 cmult, csize, capacity;
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
int timeout = 1000;
@@ -1555,7 +1555,7 @@ static int mmc_startup(struct mmc *mmc)
 
 static int mmc_send_if_cond(struct mmc *mmc)
 {
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
int err;
 
cmd.cmdidx = SD_CMD_SEND_IF_COND;
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index 0f8b5c7..4149f4a 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -17,7 +17,7 @@
 
 static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)
 {
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
ulong end;
int err, start_cmd, end_cmd;
 
@@ -119,7 +119,7 @@ unsigned long mmc_berase(struct blk_desc *block_dev, 
lbaint_t start,
 static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start,
lbaint_t blkcnt, const void *src)
 {
-   struct mmc_cmd cmd;
+   struct mmc_cmd cmd = {0};
struct mmc_data data;

[U-Boot] [PATCH v3 00/27] spi/sf: Updates on flash detection

[Jagan Teki]

Updated spi_flash_info table in sync with Linux, and removed
legacy and unsupported code.

Changes for v3:
- New patches
- Fix checkpatch.pl
- Fix BIT positions in spi.h
- Fix ti_qspi.c mode
- Fix commit Nit: s/becuase/because

Changes for v2:
- New patches.

Jagan Teki (27):
  sf: Simplify fastest read cmd code
  sf: Remove e_rd_cmd from param table
  spi: Use mode for rx mode flags
  spi: Remove SPI_RX_FAST
  sf: Remove SECT_32K
  sf: Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flash
  sf: Move flags macro's to spi_flash_params{} members
  sf: Adopt flash table INFO macro from Linux
  sf: Add JEDEC_ID and JEDEC_EXT macro
  sf: Rename spi_flash_params => spi_flash_info
  sf: Add JEDEC_MFR
  sf: Simplify lock ops detection code
  sf: sandbox: Fix ID exctract from spi_flash_info
  sf: Cleanup spi_flash_info{}
  sf: Cleanup sf_params
  sf: nr_sectors -> n_sectors
  sf: Add SPI_FLASH_MAX_ID_LEN
  sf: Increase max id length by 1 byte
  sf: Add INFO6 flash_info macro
  sf: params: Add S25FS256S_64K spi flash support
  sf: Remove legacy idcode detection code
  sf: Remove non-meaningful comments
  sf: Rename sf_params.c to spi_flash_ids
  sf: ids: Use small letter's with flash name
  sf: ids: Use small letter in ext_jedec
  sf: Rename few local functions
  spi: Remove dual flash code

 drivers/mtd/spi/Makefile|   2 +-
 drivers/mtd/spi/sandbox.c   |  16 ++-
 drivers/mtd/spi/sf.c|   4 -
 drivers/mtd/spi/sf_internal.h   |  97 ++-
 drivers/mtd/spi/sf_params.c | 238 +++-
 drivers/mtd/spi/spi_flash.c | 258 +---
 drivers/mtd/spi/spi_flash_ids.c | 176 +++
 drivers/spi/cadence_qspi.c  |   2 +-
 drivers/spi/ich.c   |   6 +-
 drivers/spi/spi-uclass.c|  11 +-
 drivers/spi/ti_qspi.c   |   6 +-
 include/linux/err.h |   5 +
 include/spi.h   |  19 +--
 13 files changed, 454 insertions(+), 386 deletions(-)
 create mode 100644 drivers/mtd/spi/spi_flash_ids.c

-- 
2.7.4

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[U-Boot] [PATCH v3 08/27] sf: Adopt flash table INFO macro from Linux

[Jagan Teki]

INFO macro make flash table entries more adjustable like
adding new flash_info attributes, update ID length bytes
and so on and more over it will sync to Linux way of defining
flash_info attributes.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h |  15 ++-
 drivers/mtd/spi/sf_params.c   | 215 ++
 drivers/mtd/spi/spi_flash.c   |  61 ++--
 include/linux/err.h   |   5 +
 4 files changed, 160 insertions(+), 136 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index cde4cfb..e6cd6da 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -107,8 +107,6 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
  * struct spi_flash_params - SPI/QSPI flash device params structure
  *
  * @name:  Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
- * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
- * @ext_jedec: Device ext_jedec ID
  * @sector_size:   Isn't necessarily a sector size from vendor,
  * the size listed here is what works with CMD_ERASE_64K
  * @nr_sectors:No.of sectors on this device
@@ -116,11 +114,20 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
  */
 struct spi_flash_params {
const char *name;
-   u32 jedec;
-   u16 ext_jedec;
+
+   /*
+* This array stores the ID bytes.
+* The first three bytes are the JEDIC ID.
+* JEDEC ID zero means "no ID" (mostly older chips).
+*/
+   u8  id[5];
+   u8  id_len;
+
u32 sector_size;
u32 nr_sectors;
 
+   u16 page_size;
+
u16 flags;
 #define SECT_4KBIT(0)
 #define E_FSR  BIT(1)
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 5b50114..70d9e18 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -12,125 +12,140 @@
 
 #include "sf_internal.h"
 
+/* Used when the "_ext_id" is two bytes at most */
+#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
+   .id = { \
+   ((_jedec_id) >> 16) & 0xff, \
+   ((_jedec_id) >> 8) & 0xff,  \
+   (_jedec_id) & 0xff, \
+   ((_ext_id) >> 8) & 0xff,\
+   (_ext_id) & 0xff,   \
+   },  \
+   .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),   
\
+   .sector_size = (_sector_size),  \
+   .nr_sectors = (_n_sectors), \
+   .page_size = 256,   \
+   .flags = (_flags),
+
 /* SPI/QSPI flash device params structure */
 const struct spi_flash_params spi_flash_params_table[] = {
 #ifdef CONFIG_SPI_FLASH_ATMEL  /* ATMEL */
-   {"AT45DB011D", 0x1f2200, 0x0,   64 * 1024, 4, SECT_4K},
-   {"AT45DB021D", 0x1f2300, 0x0,   64 * 1024, 8, SECT_4K},
-   {"AT45DB041D", 0x1f2400, 0x0,   64 * 1024, 8, SECT_4K},
-   {"AT45DB081D", 0x1f2500, 0x0,   64 * 1024,16, SECT_4K},
-   {"AT45DB161D", 0x1f2600, 0x0,   64 * 1024,32, SECT_4K},
-   {"AT45DB321D", 0x1f2700, 0x0,   64 * 1024,64, SECT_4K},
-   {"AT45DB641D", 0x1f2800, 0x0,   64 * 1024,   128, SECT_4K},
-   {"AT25DF321A", 0x1f4701, 0x0,   64 * 1024,64, SECT_4K},
-   {"AT25DF321",  0x1f4700, 0x0,   64 * 1024,64, SECT_4K},
-   {"AT26DF081A", 0x1f4501, 0x0,   64 * 1024,16, SECT_4K},
+   {"AT45DB011D", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
+   {"AT45DB021D", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) },
+   {"AT45DB041D", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) },
+   {"AT45DB081D", INFO(0x1f2500, 0x0, 64 * 1024,16, SECT_4K) },
+   {"AT45DB161D", INFO(0x1f2600, 0x0, 64 * 1024,32, SECT_4K) },
+   {"AT45DB321D", INFO(0x1f2700, 0x0, 64 * 1024,64, SECT_4K) },
+   {"AT45DB641D", INFO(0x1f2800, 0x0, 64 * 1024,   128, SECT_4K) },
+   {"AT25DF321A", INFO(0x1f4701, 0x0, 64 * 1024,64, SECT_4K) },
+   {"AT25DF321",  INFO(0x1f4700, 0x0, 64 * 1024,64, SECT_4K) },
+   {"AT26DF081A", INFO(0x1f4501, 0x0, 64 * 1024,16, SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_EON/* EON */
-   {"EN25Q32B",   0x1c3016, 0x0,   64 * 1024,   

[U-Boot] [PATCH v3 21/27] sf: Remove legacy idcode detection code

[Jagan Teki]

Since flash detection code is more mature to
detect even with 6 bytes id length devices
removed old code and related references.

Cc: Yunhui Cui 
Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Michael Trimarchi 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h |  6 
 drivers/mtd/spi/spi_flash.c   | 78 ---
 2 files changed, 84 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index f2ea368..d50fb9a 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -99,12 +99,6 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t 
len,
const void *buf);
 #endif
 
-#ifdef CONFIG_SPI_FLASH_SPANSION
-/* Used for Spansion S25FS-S family flash only. */
-#define CMD_SPANSION_RDAR  0x65 /* Read any device register */
-#define CMD_SPANSION_WRAR  0x71 /* Write any device register */
-#endif
-
 #define JEDEC_MFR(info)((info)->id[0])
 #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
 #define JEDEC_EXT(info)(((info)->id[3]) << 8 | ((info)->id[4]))
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index ba884d7..27b85ba 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -999,94 +999,16 @@ int spi_flash_decode_fdt(const void *blob, struct 
spi_flash *flash)
 }
 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
 
-#ifdef CONFIG_SPI_FLASH_SPANSION
-static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
-{
-   u8 cmd[4];
-   u32 offset = 0x84; /* CR3V register offset */
-   u8 cr3v;
-   int ret;
-
-   cmd[0] = CMD_SPANSION_RDAR;
-   cmd[1] = offset >> 16;
-   cmd[2] = offset >> 8;
-   cmd[3] = offset >> 0;
-
-   ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
-   if (ret)
-   return -EIO;
-   /* CR3V bit3: 4-KB Erase */
-   if (cr3v & 0x8)
-   return 0;
-
-   cmd[0] = CMD_SPANSION_WRAR;
-   cr3v |= 0x8;
-   ret = spi_flash_cmd_write(spi, cmd, 4, &cr3v, 1);
-   if (ret)
-   return -EIO;
-
-   cmd[0] = CMD_SPANSION_RDAR;
-   ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
-   if (ret)
-   return -EIO;
-   if (!(cr3v & 0x8))
-   return -EFAULT;
-
-   return 0;
-}
-#endif
-
 int spi_flash_scan(struct spi_flash *flash)
 {
struct spi_slave *spi = flash->spi;
const struct spi_flash_info *info = NULL;
-   u16 jedec, ext_jedec;
-   u8 idcode[5];
int ret;
 
info = spi_flash_read_id(flash);
if (IS_ERR_OR_NULL(info))
return -ENOENT;
 
-   jedec = idcode[1] << 8 | idcode[2];
-   ext_jedec = idcode[3] << 8 | idcode[4];
-
-#ifdef CONFIG_SPI_FLASH_SPANSION
-   /*
-* The S25FS-S family physical sectors may be configured as a
-* hybrid combination of eight 4-kB parameter sectors
-* at the top or bottom of the address space with all
-* but one of the remaining sectors being uniform size.
-* The Parameter Sector Erase commands (20h or 21h) must
-* be used to erase the 4-kB parameter sectors individually.
-* The Sector (uniform sector) Erase commands (D8h or DCh)
-* must be used to erase any of the remaining
-* sectors, including the portion of highest or lowest address
-* sector that is not overlaid by the parameter sectors.
-* The uniform sector erase command has no effect on parameter sectors.
-*/
-   if ((jedec == 0x0219 || (jedec == 0x0220)) &&
-   (ext_jedec & 0xff00) == 0x4d00) {
-   int ret;
-   u8 id[6];
-
-   /* Read the ID codes again, 6 bytes */
-   ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
-   if (ret)
-   return -EIO;
-
-   ret = memcmp(id, idcode, 5);
-   if (ret)
-   return -EIO;
-
-   /* 0x81: S25FS-S family 0x80: S25FL-S family */
-   if (id[5] == 0x81) {
-   ret = spansion_s25fss_disable_4KB_erase(spi);
-   if (ret)
-   return ret;
-   }
-   }
-#endif
/* Flash powers up read-only, so clear BP# bits */
if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX ||
-- 
2.7.4

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[U-Boot] [PATCH v3 24/27] sf: ids: Use small letter's with flash name

[Jagan Teki]

For readability use small letter's with flash name.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/spi_flash_ids.c | 220 
 1 file changed, 110 insertions(+), 110 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index 61cac59..f3c5e3f 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -41,136 +41,136 @@
 
 const struct spi_flash_info spi_flash_ids[] = {
 #ifdef CONFIG_SPI_FLASH_ATMEL  /* ATMEL */
-   {"AT45DB011D", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
-   {"AT45DB021D", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) },
-   {"AT45DB041D", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) },
-   {"AT45DB081D", INFO(0x1f2500, 0x0, 64 * 1024,16, SECT_4K) },
-   {"AT45DB161D", INFO(0x1f2600, 0x0, 64 * 1024,32, SECT_4K) },
-   {"AT45DB321D", INFO(0x1f2700, 0x0, 64 * 1024,64, SECT_4K) },
-   {"AT45DB641D", INFO(0x1f2800, 0x0, 64 * 1024,   128, SECT_4K) },
-   {"AT25DF321A", INFO(0x1f4701, 0x0, 64 * 1024,64, SECT_4K) },
-   {"AT25DF321",  INFO(0x1f4700, 0x0, 64 * 1024,64, SECT_4K) },
-   {"AT26DF081A", INFO(0x1f4501, 0x0, 64 * 1024,16, SECT_4K) },
+   {"at45db011d", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
+   {"at45db021d", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) },
+   {"at45db041d", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) },
+   {"at45db081d", INFO(0x1f2500, 0x0, 64 * 1024,16, SECT_4K) },
+   {"at45db161d", INFO(0x1f2600, 0x0, 64 * 1024,32, SECT_4K) },
+   {"at45db321d", INFO(0x1f2700, 0x0, 64 * 1024,64, SECT_4K) },
+   {"at45db641d", INFO(0x1f2800, 0x0, 64 * 1024,   128, SECT_4K) },
+   {"at25df321a", INFO(0x1f4701, 0x0, 64 * 1024,64, SECT_4K) },
+   {"at25df321",  INFO(0x1f4700, 0x0, 64 * 1024,64, SECT_4K) },
+   {"at26df081a", INFO(0x1f4501, 0x0, 64 * 1024,16, SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_EON/* EON */
-   {"EN25Q32B",   INFO(0x1c3016, 0x0, 64 * 1024,64, 0) },
-   {"EN25Q64",INFO(0x1c3017, 0x0, 64 * 1024,   128, SECT_4K) },
-   {"EN25Q128B",  INFO(0x1c3018, 0x0, 64 * 1024,   256, 0) },
-   {"EN25S64",INFO(0x1c3817, 0x0, 64 * 1024,   128, 0) },
+   {"en25q32b",   INFO(0x1c3016, 0x0, 64 * 1024,64, 0) },
+   {"en25q64",INFO(0x1c3017, 0x0, 64 * 1024,   128, SECT_4K) },
+   {"en25q128b",  INFO(0x1c3018, 0x0, 64 * 1024,   256, 0) },
+   {"en25s64",INFO(0x1c3817, 0x0, 64 * 1024,   128, 0) },
 #endif
 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
-   {"GD25Q64B",   INFO(0xc84017, 0x0, 64 * 1024,   128, SECT_4K) },
-   {"GD25LQ32",   INFO(0xc86016, 0x0, 64 * 1024,64, SECT_4K) },
+   {"gd25q64b",   INFO(0xc84017, 0x0, 64 * 1024,   128, SECT_4K) },
+   {"gd25lq32",   INFO(0xc86016, 0x0, 64 * 1024,64, SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_ISSI   /* ISSI */
-   {"IS25LP032",  INFO(0x9d6016, 0x0, 64 * 1024,64, 0) },
-   {"IS25LP064",  INFO(0x9d6017, 0x0, 64 * 1024,   128, 0) },
-   {"IS25LP128",  INFO(0x9d6018, 0x0, 64 * 1024,   256, 0) },
+   {"is25lp032",  INFO(0x9d6016, 0x0, 64 * 1024,64, 0) },
+   {"is25lp064",  INFO(0x9d6017, 0x0, 64 * 1024,   128, 0) },
+   {"is25lp128",  INFO(0x9d6018, 0x0, 64 * 1024,   256, 0) },
 #endif
 #ifdef CONFIG_SPI_FLASH_MACRONIX   /* MACRONIX */
-   {"MX25L2006E", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) },
-   {"MX25L4005",  INFO(0xc22013, 0x0, 64 * 1024, 8, 0) },
-   {"MX25L8005",  INFO(0xc22014, 0x0, 64 * 1024,16, 0) },
-   {"MX25L1605D", INFO(0xc22015, 0x0, 64 * 1024,32, 0) },
-   {"MX25L3205D", INFO(0xc22016, 0x0, 64 * 1024,64, 0) },
-   {"MX25L6405D", INFO(0xc22017, 0x0, 64 * 1024,   128, 0) },
-   {"MX25L12805", INFO(0xc22018, 0x0, 64 * 1024,   256, RD_FULL | 
WR_QPP) },
-   {"MX25L25635F",INFO(0xc22019, 0x0, 64 * 1024,   512, RD_FULL | 
WR_QPP) },
-   {"MX25L51235F",INFO(0xc2201a, 0x0, 64 * 1024,  1024, RD_FULL | 
WR_QPP) },
-   {"MX25L12855E",INFO(0xc22618, 0x0, 64 * 1024,   256, RD_FULL | 
WR_QPP) },
+   {"mx25l2006e", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) },
+   {"mx25l4005",  INFO(0xc22013, 0x0, 64 * 1024, 8, 0) },
+   {"mx25l8005",  INFO(0xc22014, 0x0, 64 * 1024,16, 0) },
+   {"mx25l1605d", INFO(0xc22015, 0x0, 64 * 1024,32, 0) },
+   {"mx25l3205d", INFO(0xc22016, 0x0, 64 * 1024,64, 0) },
+   {"mx25l6405d", INFO(0xc22017, 0x0, 64 * 1024,   128, 0) },
+   {"mx25l12805", INFO(0xc22018, 0

Re: [U-Boot] [PATCH v3 00/27] spi/sf: Updates on flash detection

[Jagan Teki]

On 11 August 2016 at 13:36, Jagan Teki  wrote:
> Updated spi_flash_info table in sync with Linux, and removed
> legacy and unsupported code.
>
> Changes for v3:
> - New patches
> - Fix checkpatch.pl
> - Fix BIT positions in spi.h
> - Fix ti_qspi.c mode
> - Fix commit Nit: s/becuase/because
>
> Changes for v2:
> - New patches.
>
> Jagan Teki (27):
>   sf: Simplify fastest read cmd code
>   sf: Remove e_rd_cmd from param table
>   spi: Use mode for rx mode flags
>   spi: Remove SPI_RX_FAST
>   sf: Remove SECT_32K
>   sf: Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flash
>   sf: Move flags macro's to spi_flash_params{} members
>   sf: Adopt flash table INFO macro from Linux
>   sf: Add JEDEC_ID and JEDEC_EXT macro
>   sf: Rename spi_flash_params => spi_flash_info
>   sf: Add JEDEC_MFR
>   sf: Simplify lock ops detection code
>   sf: sandbox: Fix ID exctract from spi_flash_info
>   sf: Cleanup spi_flash_info{}
>   sf: Cleanup sf_params
>   sf: nr_sectors -> n_sectors
>   sf: Add SPI_FLASH_MAX_ID_LEN
>   sf: Increase max id length by 1 byte
>   sf: Add INFO6 flash_info macro
>   sf: params: Add S25FS256S_64K spi flash support
>   sf: Remove legacy idcode detection code
>   sf: Remove non-meaningful comments
>   sf: Rename sf_params.c to spi_flash_ids
>   sf: ids: Use small letter's with flash name
>   sf: ids: Use small letter in ext_jedec
>   sf: Rename few local functions
>   spi: Remove dual flash code

Tested on microzed and sandbox

Tested-by: Jagan Teki 

I've some host issues while running buildman, can anyone please run buildman?

thanks!
-- 
Jagan.
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[U-Boot] [PATCH 4/5] mmc: esdhc: change timeout value

[Peng Fan]

Change timeout according to the timeout value in mmc_cmd->timeout.

Signed-off-by: Peng Fan 
Cc: Jaehoon Chung 
---
 drivers/mmc/fsl_esdhc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 9796d39..eca2f31 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -350,6 +350,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct 
mmc_data *data)
int err = 0;
uintxfertyp;
uintirqstat;
+   int timeout = cmd->timeout;
struct fsl_esdhc_priv *priv = mmc->priv;
struct fsl_esdhc *regs = priv->esdhc_regs;
 
@@ -431,7 +432,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct 
mmc_data *data)
 
/* Workaround for ESDHC errata ENGcm03648 */
if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
-   int timeout = 6000;
+   if (timeout < 6000)
+   timeout = 6000;
 
/* Poll on DATA0 line for cmd with busy signal for 600 ms */
while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
-- 
2.6.2

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Re: [U-Boot] [PATCH 01/21] imx: mx6ull: add iomux header file

[Stefano Babic]

On 11/08/2016 08:02, Peng Fan wrote:
> Add iomux header file for i.MX6ULL.
> 
> Signed-off-by: Peng Fan 
> Signed-off-by: Ye Li 
> Cc: Stefano Babic 
> ---
>  arch/arm/include/asm/arch-mx6/mx6-pins.h|2 +
>  arch/arm/include/asm/arch-mx6/mx6ull_pins.h | 1065 
> +++
>  2 files changed, 1067 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-mx6/mx6ull_pins.h
> 
> diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h 
> b/arch/arm/include/asm/arch-mx6/mx6-pins.h
> index 4b6bb18..b9cd670 100644
> --- a/arch/arm/include/asm/arch-mx6/mx6-pins.h
> +++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
> @@ -37,6 +37,8 @@ enum {
>  #include "mx6sl_pins.h"
>  #elif defined(CONFIG_MX6SX)
>  #include "mx6sx_pins.h"
> +#elif defined(CONFIG_MX6ULL)
> +#include "mx6ull_pins.h"
>  #elif defined(CONFIG_MX6UL)
>  #include "mx6ul_pins.h"
>  #else
> diff --git a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h 
> b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h
> new file mode 100644
> index 000..682430e
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h
> @@ -0,0 +1,1065 @@
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __ASM_ARCH_IMX6ULL_PINS_H__
> +#define __ASM_ARCH_IMX6ULL_PINS_H__
> +
> +#include 
> +
> +enum {
> + MX6_PAD_BOOT_MODE0__GPIO5_IO10 = 
> IOMUX_PAD(0x0044, 0x, IOMUX_CONFIG_LPSR | 5, 0x, 0, 0),
> + MX6_PAD_BOOT_MODE1__GPIO5_IO11 = 
> IOMUX_PAD(0x0048, 0x0004, IOMUX_CONFIG_LPSR | 5, 0x, 0, 0),
> +
> + /*
> +  * The TAMPER Pin can be used for GPIO, which depends on
> +  * TAMPER_PIN_DISABLE[1:0] settings.
> +  */
> + MX6_PAD_SNVS_TAMPER0__GPIO5_IO00   = 
> IOMUX_PAD(0x004C, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x, 0, 0),
> + MX6_PAD_SNVS_TAMPER1__GPIO5_IO01   = 
> IOMUX_PAD(0x0050, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x, 0, 0),
> + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02   = 
> IOMUX_PAD(0x0054, 0x0010, IOMUX_CONFIG_LPSR | 5, 0x, 0, 0),
> + MX6_PAD_SNVS_TAMPER3__GPIO5_IO03   = 
> IOMUX_PAD(0x0058, 0x0014, IOMUX_CONFIG_LPSR | 5, 0x, 0, 0),
> + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04   = 
> IOMUX_PAD(0x005C, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x, 0, 0),
> + MX6_PAD_SNVS_TAMPER5__GPIO5_IO05   = 
> IOMUX_PAD(0x0060, 0x001C, IOMUX_CONFIG_LPSR | 5, 0x, 0, 0),
> + MX6_PAD_SNVS_TAMPER6__GPIO5_IO06   = 
> IOMUX_PAD(0x0064, 0x0020, IOMUX_CONFIG_LPSR | 5, 0x, 0, 0),
> + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07   = 
> IOMUX_PAD(0x0068, 0x0024, IOMUX_CONFIG_LPSR | 5, 0x, 0, 0),
> + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08   = 
> IOMUX_PAD(0x006C, 0x0028, IOMUX_CONFIG_LPSR | 5, 0x, 0, 0),
> + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09   = 
> IOMUX_PAD(0x0070, 0x002C, IOMUX_CONFIG_LPSR | 5, 0x, 0, 0),
> +
> + MX6_PAD_JTAG_MOD__SJC_MOD = 
> IOMUX_PAD(0x02D0, 0x0044, 0, 0x, 0, 0),
> + MX6_PAD_JTAG_MOD__GPT2_CLK= 
> IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0),
> + MX6_PAD_JTAG_MOD__SPDIF_OUT   = 
> IOMUX_PAD(0x02D0, 0x0044, 2, 0x, 0, 0),
> + MX6_PAD_JTAG_MOD__ENET1_REF_CLK_25M   = 
> IOMUX_PAD(0x02D0, 0x0044, 3, 0x, 0, 0),
> + MX6_PAD_JTAG_MOD__CCM_PMIC_RDY= 
> IOMUX_PAD(0x02D0, 0x0044, 4, 0x04C0, 0, 0),
> + MX6_PAD_JTAG_MOD__GPIO1_IO10  = 
> IOMUX_PAD(0x02D0, 0x0044, 5, 0x, 0, 0),
> + MX6_PAD_JTAG_MOD__SDMA_EXT_EVENT00= 
> IOMUX_PAD(0x02D0, 0x0044, 6, 0x0610, 0, 0),
> +
> + MX6_PAD_JTAG_TMS__SJC_TMS = 
> IOMUX_PAD(0x02D4, 0x0048, 0, 0x, 0, 0),
> + MX6_PAD_JTAG_TMS__GPT2_CAPTURE1   = 
> IOMUX_PAD(0x02D4, 0x0048, 1, 0x0598, 0, 0),
> + MX6_PAD_JTAG_TMS__SAI2_MCLK   = 
> IOMUX_PAD(0x02D4, 0x0048, 2, 0x05F0, 0, 0),
> + MX6_PAD_JTAG_TMS__CCM_CLKO1   = 
> IOMUX_PAD(0x02D4, 0x0048, 3, 0x, 0, 0),
> + MX6_PAD_JTAG_TMS__CCM_WAIT= 
> IOMUX_PAD(0x02D4, 0x0048, 4, 0x, 0, 0),
> + MX6_PAD_JTAG_TMS__GPIO1_IO11  = 
> IOMUX_PAD(0x02D4, 0x0048, 5, 0x, 0, 0),
> + MX6_PAD_JTAG_TMS__SDMA_EXT_EVENT01= 
> IOMUX_PAD(0x02D4, 0x0048, 6, 0x0614, 0, 0),
> + MX6_PAD_JTAG_TMS__EPIT1_OUT   = 
> IOMUX_PAD(0x02D4, 0x0048, 8, 0x, 0, 0),
> +
> + MX6_PAD_JTAG_TDO__SJC_TDO = 
> IOMUX_PAD(0x02D8, 0x004C, 0, 0x, 0, 0),
> + MX6_PAD_JTAG_TDO__GPT2_CAPTURE2   = 
> IOMUX_PAD(0x02D8, 0x004C, 1, 0x059C, 0, 0),
> + MX6_PAD_JTAG_TDO__S

[U-Boot] disabling mmc in spl when booting using bootrom

[Sandy Patterson]

Simon,

I am trying to format a patch to disable MMC in the SPL if booting main
u-boot using BOOTROM, therefore the SPL MMC isn't needed.

Is the best solution to wrap every header file (rock2.h firefly-rk3288.h,
etc) with ifdefs on the BACK_TO_BROM define? Or would it be better to move
the SPL MMC define into rk3288-common.h and just have chromebook_jerry
undef it like it does the SPL GPIO code.

With that change, enabling BOOT_TO_BROM shrinks the spl from 32K to 23K.

Sandy
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[U-Boot] [PATCH 1/2] bcm2835_gpio: Implement GPIOF_FUNC

[Alexander Graf]

So far we could only tell the gpio framework that a GPIO was mapped as input or
output, not as alternative function.

This patch adds support for determining whether a function is mapped as
alternative.

Signed-off-by: Alexander Graf 
---
 arch/arm/mach-bcm283x/include/mach/gpio.h |  2 ++
 drivers/gpio/bcm2835_gpio.c   | 30 +-
 2 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-bcm283x/include/mach/gpio.h 
b/arch/arm/mach-bcm283x/include/mach/gpio.h
index e6e5d16..b2df75a 100644
--- a/arch/arm/mach-bcm283x/include/mach/gpio.h
+++ b/arch/arm/mach-bcm283x/include/mach/gpio.h
@@ -66,4 +66,6 @@ struct bcm2835_gpio_platdata {
unsigned long base;
 };
 
+int bcm2835_gpio_get_func_id(struct udevice *dev, unsigned gpio);
+
 #endif /* _BCM2835_GPIO_H_ */
diff --git a/drivers/gpio/bcm2835_gpio.c b/drivers/gpio/bcm2835_gpio.c
index fbc641d..8b88d79 100644
--- a/drivers/gpio/bcm2835_gpio.c
+++ b/drivers/gpio/bcm2835_gpio.c
@@ -44,15 +44,6 @@ static int bcm2835_gpio_direction_output(struct udevice 
*dev, unsigned gpio,
return 0;
 }
 
-static bool bcm2835_gpio_is_output(const struct bcm2835_gpios *gpios, int gpio)
-{
-   u32 val;
-
-   val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
-   val &= BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio);
-   return val ? true : false;
-}
-
 static int bcm2835_get_value(const struct bcm2835_gpios *gpios, unsigned gpio)
 {
unsigned val;
@@ -81,15 +72,28 @@ static int bcm2835_gpio_set_value(struct udevice *dev, 
unsigned gpio,
return 0;
 }
 
-static int bcm2835_gpio_get_function(struct udevice *dev, unsigned offset)
+int bcm2835_gpio_get_func_id(struct udevice *dev, unsigned gpio)
 {
struct bcm2835_gpios *gpios = dev_get_priv(dev);
+   u32 val;
+
+   val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+
+   return (val >> BCM2835_GPIO_FSEL_SHIFT(gpio) & BCM2835_GPIO_FSEL_MASK);
+}
+
+static int bcm2835_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+   int funcid = bcm2835_gpio_get_func_id(dev, offset);
 
-   /* GPIOF_FUNC is not implemented yet */
-   if (bcm2835_gpio_is_output(gpios, offset))
+   switch (funcid) {
+   case BCM2835_GPIO_OUTPUT:
return GPIOF_OUTPUT;
-   else
+   case BCM2835_GPIO_INPUT:
return GPIOF_INPUT;
+   default:
+   return GPIOF_FUNC;
+   }
 }
 
 
-- 
1.8.5.6

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[U-Boot] [PATCH 2/2] serial: bcm283x_mu: Detect disabled serial device

[Alexander Graf]

On the raspberry pi, you can disable the serial port to gain dynamic frequency
scaling which can get handy at times.

However, in such a configuration the serial controller gets its rx queue filled
up with zero bytes which then happily get transmitted on to whoever calls
getc() today.

This patch adds detection logic for that case by checking whether the RX pin is
mapped to GPIO15 and disables the mini uart if it is not mapped properly.

That way we can leave the driver enabled in the tree and can determine during
runtime whether serial is usable or not, having a single binary that allows for
uart and non-uart operation.

Signed-off-by: Alexander Graf 

---

v2 -> v3:

  - Disable and detect pinmux in board file
---
 board/raspberrypi/rpi/rpi.c | 29 +
 configs/rpi_3_32b_defconfig |  1 +
 configs/rpi_3_defconfig |  1 +
 include/configs/rpi.h   |  1 +
 4 files changed, 32 insertions(+)

diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 4c8253d..20b0d1b 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -453,6 +453,35 @@ int board_init(void)
return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
 }
 
+static bool rpi_is_serial_active(void)
+{
+#ifndef CONFIG_PL01X_SERIAL
+   int serial_gpio = 15;
+   struct udevice *dev;
+
+   /*
+* The RPi3 disables the mini uart by default. The easiest way to find
+* out whether it is available is to check if the pin is muxed.
+*/
+   if (uclass_first_device(UCLASS_GPIO, &dev) || !dev)
+   return true;
+
+   if (bcm2835_gpio_get_func_id(dev, serial_gpio) != BCM2835_GPIO_ALT5)
+   return false;
+#endif
+
+   return true;
+}
+
+int board_late_init(void)
+{
+   /* Disable mini-UART I/O if it's not pinmuxed to our pins */
+   if (!rpi_is_serial_active())
+   gd->cur_serial_dev = NULL;
+
+   return 0;
+}
+
 int board_mmc_init(bd_t *bis)
 {
ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1);
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index 922e01b..4c2f106 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -20,3 +20,4 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index bff92df..288214c 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -19,3 +19,4 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index b5543f4..e3b890a 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -22,6 +22,7 @@
 
 /* Architecture, CPU, etc.*/
 #define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOARD_LATE_INIT
 
 /* Use SoC timer for AArch32, but architected timer for AArch64 */
 #ifndef CONFIG_ARM64
-- 
1.8.5.6

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[U-Boot] pull request: u-boot-uniphier/master

[Masahiro Yamada]

Hi Tom,


Please pull these UniPhier SoC updates for v2016.09-rc2.
This series includes L2 cache code fix and refactoring,
PSCI support for ARMv7 SoCs.


The following changes since commit 2e406dbdf5fa6d178c50a2f537588de9f8615d35:

  Merge git://www.denx.de/git/u-boot-ppc4xx (2016-08-09 07:16:01 -0400)

are available in the git repository at:


  git://git.denx.de/u-boot-uniphier.git master

for you to fetch changes up to e8a9293295a1a54f6e43970bed2d3bfd124be02c:

  ARM: uniphier: add PSCI support for UniPhier ARMv7 SoCs (2016-08-11
17:58:06 +0900)


Masahiro Yamada (14):
  ARM: uniphier: refactor outer cache code
  ARM: uniphier: support prefetch and touch operations for outer cache
  ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabled
  ARM: uniphier: refactor L2 zero-touching code in lowlevel_init
  ARM: uniphier: fix ROM boot mode for PH1-sLD3
  ARM: uniphier: move lowlevel debug init code after page table switch
  ARM: uniphier: export uniphier_cache_enable/disable functions
  ARM: uniphier: reuse uniphier_cache_disable() for lowlevel_init
  ARM: uniphier: move outer cache register macros to .c file
  ARM: uniphier: move (and rename) CONFIG_UNIPHIER_L2CACHE_ON to Kconfig
  ARM: uniphier: fix CONFIG_SYS_CACHELINE_SIZE when outer cache is on
  ARM: uniphier: add uniphier_cache_inv_way() to support way invalidation
  ARM: uniphier: add uniphier_cache_set_active_ways()
  ARM: uniphier: add PSCI support for UniPhier ARMv7 SoCs

 arch/arm/mach-uniphier/Kconfig|   9 ++
 arch/arm/mach-uniphier/arm32/Makefile |   1 +
 arch/arm/mach-uniphier/arm32/arm-mpcore.h |   3 +
 arch/arm/mach-uniphier/arm32/cache-uniphier.c | 261
+++-
 arch/arm/mach-uniphier/arm32/cache-uniphier.h |  21 +++
 arch/arm/mach-uniphier/arm32/late_lowlevel_init.S |  10 +-
 arch/arm/mach-uniphier/arm32/lowlevel_init.S  |  61 -
 arch/arm/mach-uniphier/arm32/psci.c   | 153 +
 arch/arm/mach-uniphier/arm32/psci_smp.S   |  40 ++
 arch/arm/mach-uniphier/arm32/ssc-regs.h   |  68 --
 arch/arm/mach-uniphier/debug.h|  68 ++
 arch/arm/mach-uniphier/sbc/sbc-regs.h |   4 +-
 include/configs/uniphier.h|  14 +-
 13 files changed, 537 insertions(+), 176 deletions(-)
 create mode 100644 arch/arm/mach-uniphier/arm32/cache-uniphier.h
 create mode 100644 arch/arm/mach-uniphier/arm32/psci.c
 create mode 100644 arch/arm/mach-uniphier/arm32/psci_smp.S
 delete mode 100644 arch/arm/mach-uniphier/arm32/ssc-regs.h
 create mode 100644 arch/arm/mach-uniphier/debug.h


-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH 1/2 V4] misc: add "call" uclass op

[Stephen Warren]

On 08/08/2016 02:33 PM, Tom Warren wrote:

Simon,


-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Monday, August 08, 2016 12:54 PM
To: Simon Glass 
Cc: U-Boot Mailing List ; Tom Warren
; Stephen Warren ; Tom Rini

Subject: Re: [PATCH 1/2 V4] misc: add "call" uclass op

On 08/08/2016 01:47 PM, Simon Glass wrote:

+Tom

Hi Stephen,

On 8 August 2016 at 10:41, Stephen Warren 

wrote:

On 08/08/2016 10:38 AM, Simon Glass wrote:


Hi Stephen,

On 8 August 2016 at 09:41, Stephen Warren 

wrote:



From: Stephen Warren 

The call op requests that the callee pass a message to the
underlying HW or device, wait for a response, and then pass back
the response error code and message to the callee. It is useful for
drivers that represent some kind of messaging or IPC channel to a
remote device.

Signed-off-by: Stephen Warren 
Acked-by: Simon Glass 
---
v4: Adjust misc_call() to return the response msg size on success.
v3: New patch.
---
 drivers/misc/misc-uclass.c | 11 +++
 include/misc.h | 35 +++
 2 files changed, 46 insertions(+)



Are you planning for the Tegra186 stuff to go into the upcoming release?



I'd like it to if at all possible; it's all pretty much
Tegra-specific drivers so shouldn't cause any fallout for other
platforms. The only exception is the fdt_translate_address() changes,
which are a dependency, which will be built into other platforms, but
there's a simple Boolean parameter that controls the new behaviour, so it

should be pretty safe.


OK, sounds reasonable to me. I'll pick these up later in the week and
send a pull request. Can you bring any other dependencies in via
Tegra?


Yes, I was assuming that TomW would take everything else; it's all Tegra
drivers.

>

Stephen and I are working together to get it all packaged up and in to 
u-boot-tegra ASAP.


Simon, any word on the u-boot-dm pull request? TomW is waiting for it 
before applying all the Tegra commits on top of it so he won't have to 
rebase, and he'd probably best send a Tegra pull request on Friday in 
order to make -rc2, which would be good to do. Thanks.

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[U-Boot] [PATCH 1/2] ARM: tegra: reduce CSITE clock from 204M to 136M

[Stephen Warren]

From: Bryan Wu 

The L4T kernel complains about a CSITE clock rate above 144MHz, presumably
because the HW is only characterized for a clock less than that. Adjust the
rate to 136MHz to avoid the warning and stay in spec.

Signed-off-by: Bryan Wu 
(swarren, re-wrote commit description)
Signed-off-by: Stephen Warren 
---
 arch/arm/mach-tegra/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h
index 3f38969a44f1..1154f8b37ef8 100644
--- a/arch/arm/mach-tegra/cpu.h
+++ b/arch/arm/mach-tegra/cpu.h
@@ -16,7 +16,7 @@
 #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
 #define NVBL_PLLP_KHZ  408000
-#define CSITE_KHZ  204000
+#define CSITE_KHZ  136000
 #else
 #error "Unknown Tegra chip!"
 #endif
-- 
2.9.2

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[U-Boot] [PATCH 2/2] ARM: tegra: set vdd_core for Jetson TK1

[Stephen Warren]

From: Bibek Basu 

Program vdd_core for Jetson TK1 to 1V, which is the max safe voltage for
ultra low temperature operations. vdd_cpu and vdd_gpu are already at 1V.

Signed-off-by: Bibek Basu 
(swarren: fixed comments to better match the code)
(swarren: moved board ifdef around data in header, made code generic)
(swarren: fixed typos in commit description)
Signed-off-by: Stephen Warren 
---
 board/nvidia/venice2/as3722_init.c | 13 -
 board/nvidia/venice2/as3722_init.h |  4 +++-
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/board/nvidia/venice2/as3722_init.c 
b/board/nvidia/venice2/as3722_init.c
index 960fea7ee7e3..1770ec2468de 100644
--- a/board/nvidia/venice2/as3722_init.c
+++ b/board/nvidia/venice2/as3722_init.c
@@ -32,7 +32,18 @@ void pmic_enable_cpu_vdd(void)
 {
debug("%s entry\n", __func__);
 
-   /* Don't need to set up VDD_CORE - already done - by OTP */
+#ifdef AS3722_SD1VOLTAGE_DATA
+   /* Set up VDD_CORE, for boards where OTP is incorrect*/
+   debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
+   /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
+   tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+   tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
+   /*
+* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+* tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
+*/
+   udelay(10 * 1000);
+#endif
 
debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
/*
diff --git a/board/nvidia/venice2/as3722_init.h 
b/board/nvidia/venice2/as3722_init.h
index 992b11f64351..c6b1247149e4 100644
--- a/board/nvidia/venice2/as3722_init.h
+++ b/board/nvidia/venice2/as3722_init.h
@@ -25,8 +25,10 @@
 #endif
 #define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
 
-#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
+#ifdef CONFIG_TARGET_JETSON_TK1
+#define AS3722_SD1VOLTAGE_DATA (0x2800 | AS3722_SD1VOLTAGE_REG)
 #define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
+#endif
 
 #define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
 #define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
-- 
2.9.2

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Re: [U-Boot] [PATCH 1/2] bcm2835_gpio: Implement GPIOF_FUNC

[Simon Glass]

On 11 August 2016 at 05:38, Alexander Graf  wrote:
> So far we could only tell the gpio framework that a GPIO was mapped as input 
> or
> output, not as alternative function.
>
> This patch adds support for determining whether a function is mapped as
> alternative.
>
> Signed-off-by: Alexander Graf 
> ---
>  arch/arm/mach-bcm283x/include/mach/gpio.h |  2 ++
>  drivers/gpio/bcm2835_gpio.c   | 30 +-
>  2 files changed, 19 insertions(+), 13 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 2/2] serial: bcm283x_mu: Detect disabled serial device

[Simon Glass]

Hi Alex,

On 11 August 2016 at 05:38, Alexander Graf  wrote:
> On the raspberry pi, you can disable the serial port to gain dynamic frequency
> scaling which can get handy at times.
>
> However, in such a configuration the serial controller gets its rx queue 
> filled
> up with zero bytes which then happily get transmitted on to whoever calls
> getc() today.
>
> This patch adds detection logic for that case by checking whether the RX pin 
> is
> mapped to GPIO15 and disables the mini uart if it is not mapped properly.
>
> That way we can leave the driver enabled in the tree and can determine during
> runtime whether serial is usable or not, having a single binary that allows 
> for
> uart and non-uart operation.
>
> Signed-off-by: Alexander Graf 
>
> ---
>
> v2 -> v3:
>
>   - Disable and detect pinmux in board file
> ---
>  board/raspberrypi/rpi/rpi.c | 29 +
>  configs/rpi_3_32b_defconfig |  1 +
>  configs/rpi_3_defconfig |  1 +
>  include/configs/rpi.h   |  1 +
>  4 files changed, 32 insertions(+)
>
> diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
> index 4c8253d..20b0d1b 100644
> --- a/board/raspberrypi/rpi/rpi.c
> +++ b/board/raspberrypi/rpi/rpi.c
> @@ -453,6 +453,35 @@ int board_init(void)
> return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
>  }
>
> +static bool rpi_is_serial_active(void)
> +{
> +#ifndef CONFIG_PL01X_SERIAL
> +   int serial_gpio = 15;
> +   struct udevice *dev;
> +
> +   /*
> +* The RPi3 disables the mini uart by default. The easiest way to find
> +* out whether it is available is to check if the pin is muxed.
> +*/
> +   if (uclass_first_device(UCLASS_GPIO, &dev) || !dev)
> +   return true;
> +
> +   if (bcm2835_gpio_get_func_id(dev, serial_gpio) != BCM2835_GPIO_ALT5)
> +   return false;

Do you mean gpio_get_function()?


> +#endif
> +
> +   return true;
> +}
> +
> +int board_late_init(void)
> +{
> +   /* Disable mini-UART I/O if it's not pinmuxed to our pins */
> +   if (!rpi_is_serial_active())
> +   gd->cur_serial_dev = NULL;
> +
> +   return 0;
> +}
> +
>  int board_mmc_init(bd_t *bis)
>  {
> ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1);
> diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
> index 922e01b..4c2f106 100644
> --- a/configs/rpi_3_32b_defconfig
> +++ b/configs/rpi_3_32b_defconfig
> @@ -20,3 +20,4 @@ CONFIG_CMD_FAT=y
>  CONFIG_CMD_FS_GENERIC=y
>  CONFIG_PHYS_TO_BUS=y
>  CONFIG_OF_LIBFDT=y
> +# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
> diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
> index bff92df..288214c 100644
> --- a/configs/rpi_3_defconfig
> +++ b/configs/rpi_3_defconfig
> @@ -19,3 +19,4 @@ CONFIG_CMD_FAT=y
>  CONFIG_CMD_FS_GENERIC=y
>  CONFIG_PHYS_TO_BUS=y
>  CONFIG_OF_LIBFDT=y
> +# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
> diff --git a/include/configs/rpi.h b/include/configs/rpi.h
> index b5543f4..e3b890a 100644
> --- a/include/configs/rpi.h
> +++ b/include/configs/rpi.h
> @@ -22,6 +22,7 @@
>
>  /* Architecture, CPU, etc.*/
>  #define CONFIG_ARCH_CPU_INIT
> +#define CONFIG_BOARD_LATE_INIT
>
>  /* Use SoC timer for AArch32, but architected timer for AArch64 */
>  #ifndef CONFIG_ARM64
> --
> 1.8.5.6
>

Regards,
Simon
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