Re: [U-Boot] [PULL] u-boot-atmel/master -> u-boot/master
On Fri, Oct 28, 2016 at 07:05:42PM +0200, Andreas Bießmann wrote: > Hi Tom, > > please pull the following changes into u-boot/master for 2016.11. > > One of the patches introduce a build warning (-Wunused-function) which is > removed with the following patch. This is due to introducing the new feature, > then switch to the feature and remove the old code in a two step procedure. > Therefore I think this is Ok. > > Andreas > > The following changes since commit 5ac5861c4ba851b473e6a24940b412b397627d8d: > > travis-ci: Add test.py for various qemu platforms (2016-10-24 08:06:29 > -0400) > > are available in the git repository at: > > git://git.denx.de/u-boot-atmel.git master > > for you to fetch changes up to 0eafd4b77615efdd948e698d83be746dcf026a53: > > dm: at91: Add driver model support for the spi driver (2016-10-28 18:37:15 > +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] Please pull u-boot-imx
On Fri, Oct 28, 2016 at 04:44:35PM +0200, Stefano Babic wrote: > Hi Tom, > > please pull from u-boot-imx, thanks ! > > There are two major patchsets in this PR: > > - plugin support from Peng > - Jagan's support for Engicam i.CoreM6 , with several > move to Kconfig. > > > The following changes since commit ebf7fff20ab8127f318b238e47a21856497bd6fe: > > spl: move FDT_FIXUP_PARTITIONS to Kconfig (2016-10-15 08:12:46 -0400) > > are available in the git repository at: > > git://www.denx.de/git/u-boot-imx.git master > > for you to fetch changes up to 1c140f7bbf4a008fcd78b407ea80c60a2a18fc1f: > > imx6: icorem6: Add default mtd nand partition table (2016-10-26 > 19:00:06 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-mmc master
On Fri, Oct 28, 2016 at 11:47:18AM +0900, Jaehoon Chung wrote: > Dear Tom, > > Could you these patches on u-boot/master? > > The following changes since commit b03380805b5a184b7017dc428a53c8e1e9c9f99c: > > i2c: designware: Avoid overwriting the cmd_data register (2016-10-24 > 18:15:47 +0200) > > are available in the git repository at: > > http://git.denx.de/u-boot-mmc.git master > > for you to fetch changes up to 2a1bedaa03a27b3d4a94f9e251f269814ed72e3e: > > mmc: sdhci: assign to clk_mul when host version is upper than SD3.0 > (2016-10-28 11:02:16 +0900) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] cmd: crosec: Move crosec_decode_region helper to cmd/cros_ec.c
The cros_ec_decode_region() function is only used in combination
with the crosec cmds. Move the function to the correct place.
Signed-off-by: Moritz Fischer
Cc: Simon Glass
Cc: Masahiro Yamada
Cc: u-boot@lists.denx.de
---
cmd/cros_ec.c | 16
drivers/misc/cros_ec.c | 16
include/cros_ec.h | 9 -
3 files changed, 16 insertions(+), 25 deletions(-)
diff --git a/cmd/cros_ec.c b/cmd/cros_ec.c
index abf11f0..3a45149 100644
--- a/cmd/cros_ec.c
+++ b/cmd/cros_ec.c
@@ -19,6 +19,22 @@ static const char * const ec_current_image_name[] =
{"unknown", "RO", "RW"};
DECLARE_GLOBAL_DATA_PTR;
+int cros_ec_decode_region(int argc, char * const argv[])
+{
+ if (argc > 0) {
+ if (0 == strcmp(*argv, "rw"))
+ return EC_FLASH_REGION_RW;
+ else if (0 == strcmp(*argv, "ro"))
+ return EC_FLASH_REGION_RO;
+
+ debug("%s: Invalid region '%s'\n", __func__, *argv);
+ } else {
+ debug("%s: Missing region parameter\n", __func__);
+ }
+
+ return -1;
+}
+
/**
* Perform a flash read or write command
*
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 9159498..cf851ff 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -1070,22 +1070,6 @@ int cros_ec_register(struct udevice *dev)
return 0;
}
-int cros_ec_decode_region(int argc, char * const argv[])
-{
- if (argc > 0) {
- if (0 == strcmp(*argv, "rw"))
- return EC_FLASH_REGION_RW;
- else if (0 == strcmp(*argv, "ro"))
- return EC_FLASH_REGION_RO;
-
- debug("%s: Invalid region '%s'\n", __func__, *argv);
- } else {
- debug("%s: Missing region parameter\n", __func__);
- }
-
- return -1;
-}
-
int cros_ec_decode_ec_flash(const void *blob, int node,
struct fdt_cros_ec *config)
{
diff --git a/include/cros_ec.h b/include/cros_ec.h
index f280c1d..26b4680 100644
--- a/include/cros_ec.h
+++ b/include/cros_ec.h
@@ -252,15 +252,6 @@ void cros_ec_dump_data(const char *name, int cmd, const
uint8_t *data, int len);
*/
int cros_ec_calc_checksum(const uint8_t *data, int size);
-/**
- * Decode a flash region parameter
- *
- * @param argc Number of params remaining
- * @param argv List of remaining parameters
- * @return flash region (EC_FLASH_REGION_...) or -1 on error
- */
-int cros_ec_decode_region(int argc, char * const argv[]);
-
int cros_ec_flash_erase(struct cros_ec_dev *dev, uint32_t offset,
uint32_t size);
--
2.7.4
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Re: [U-Boot] [PATCH 00/11] sunxi: Add full SPL support for sun9i (A80)
On Sat, Oct 29, 2016 at 1:30 AM, Hans de Goede wrote: > Hi Chen-Yu, > > On 28-10-16 12:21, Chen-Yu Tsai wrote: >> >> Hi everyone, >> >> This series adds full SPL with DRAM initialization for sun9i (A80). >> The bulk of the work was done by the people at Theobroma Systems. >> Their work can be found here: >> >> https://git.theobroma-systems.com/armadillo-u-boot.git/ >> >> I picked the essential patches and cleaned them up a bit more, >> and added commit messages if they were missing. >> >> As the DRAM bits are essentially a code dump with some cleanups and >> some bits disabled, expect many warnings. Checkpatch is still not >> happy with it. >> >> I've tested the series on both my A80 boards, which I've added >> defconfigs for in the last 2 patches. My A80 Optimus does not >> boot from micro SD, so I'm still FEL booting that one. But my >> Cubieboard 4 is now standalone. >> >> As usual, please have a look, test if possible. > > > Awesome, thanks for doing this and it was good to have > some face2face time at ELCE. > > I've merged this into my personal sunxi-wip u-boot branch, > I've made 2 changes: > > 1) in : ¨sunxi: DRAM initialisation for sun9i" there are a > lot of #if 0 #endif blocks, most of these document some features > which we may want to enable in the future, but a few were just > dead weight IMHO, so I've pruned a few Thanks. I suppose some of the testing and verbose debug calls aren't needed. Most of the #if 0 blocks within data structures were C99 // comments that I fixed up to get checkpatch happy. About the features, I was already half way through the clock code cleanup when Maxime pointed me to Theobroma's repository, so I could add and test sigma delta modulation for PLL DDR. For the other types of DRAM we could clean it up, but there's really no hardware to test it on. > 2) in : "sunxi: Add support for A80 Optimus board", we already > have a configs/Merrii_A80_Optimus_defconfig, so I've made the patch > update that instead of adding a new defconfig Cool. I didn't notice. > I have not tested this yet, I will do tomorrow, assuming it > works for me too I will include it in my next pull-req (*) and > try to get it included in the 2016.11 release, yes the merge > window has closed, but the changes here are very isolated so > I will try and see what Tom says :) Do you need me to send a v2 addressing review comments? Thanks ChenYu > > Regards, > > Hans > > > *) Which I hope to send out this weekend > > > > >> >> >> Regards >> ChenYu >> >> >> Chen-Yu Tsai (5): >> sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80) >> sunxi: Add support for SID e-fuses on sun9i >> sunxi: Add default zq value for sun9i (A80) >> sunxi: Add support for A80 Optimus board >> sunxi: Add support for Cubieboard4 >> >> Philipp Tomsich (6): >> sunxi: DRAM initialisation for sun9i >> sunxi: add gtbus-initialisation for sun9i >> sunxi: Enable SMP mode for the boot CPU on sun9i (A80) >> sunxi: add initial clock setup for sun9i for SPL >> sunxi: enable SPL for sun9i >> sunxi: add MMC pinmux setup for SDC2 on sun9i >> >> arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 116 ++- >> arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 10 + >> arch/arm/include/asm/arch-sunxi/dram.h|2 + >> arch/arm/include/asm/arch-sunxi/dram_sun9i.h | 275 +++ >> arch/arm/include/asm/arch-sunxi/gtbus.h | 21 + >> arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h | 89 +++ >> arch/arm/mach-sunxi/Makefile |2 + >> arch/arm/mach-sunxi/board.c |3 +- >> arch/arm/mach-sunxi/clock.c |6 + >> arch/arm/mach-sunxi/clock_sun9i.c | 146 +++- >> arch/arm/mach-sunxi/dram_sun9i.c | 1059 >> + >> arch/arm/mach-sunxi/gtbus_sun9i.c | 48 ++ >> board/sunxi/Kconfig | 10 +- >> board/sunxi/MAINTAINERS | 10 + >> board/sunxi/board.c |7 + >> configs/A80_Optimus_defconfig | 18 + >> configs/Cubieboard4_defconfig | 18 + >> 17 files changed, 1818 insertions(+), 22 deletions(-) >> create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h >> create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h >> create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h >> create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c >> create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c >> create mode 100644 configs/A80_Optimus_defconfig >> create mode 100644 configs/Cubieboard4_defconfig >> > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Resend RFC PATCH 1/2] armv8: Fix dcache disable function
On 10/28/2016 11:32 AM, Stephen Warren wrote: > On 10/28/2016 12:17 PM, york sun wrote: >> On 10/28/2016 10:57 AM, Stephen Warren wrote: >>> On 10/28/2016 11:38 AM, york sun wrote: On 10/26/2016 02:02 PM, york@nxp.com wrote: > > I came back from my testing and I have more questions than answers. > > For _this_ patch, I proposed to flush cache before disabling them, > noting once the dcache is disabled, the staled data in dirty cache is > not visible to the core. My argument was if we flush L1/L2, they could > end up in L3 (I don't know for sure). If I want to skip flushing L3, I > have to fix it. > > During this discussion, I thought I made a mistake by flushing L1/L2 by > way/set first, then flushing by VA. Actually I didn't. I flushed by VA > first. > > With my today's test, the baseline (working in the sense of booting > Linux) is > > PATCH 1/2 armv8: Fix dcache disable function > PATCH 2/2 armv8: Fix flush_dcache_all function > > With these two patches, I flush the stack up to top of U-Boot by VA, > followed by flush by set/way. L3 is not flushed. Then d-cache is > disabled. I know this is not a real "flush all" procedure. With this > modified procedure, I can continue to boot Linux. > > If I revert patch 1, i.e. to disable dcache before flushing, I can see > the data is not visible from the core (debug with JTAG tool). My hope > was the staled data should be flushed to main memory if flushed by VA. > That's not the case. The main memory doesn't have the correct data. So > my new question is, why flushing by VA doesn't flush the data to main > memory? Do I need to flush the cache while cache is enabled? > Guys, I think I found the root cause of my data loss. Current code disables D-cache and MMU before flushing the cache. I think the problem is turning off MMU. MMU should stay on when we flush D-cache. We can turn it off after the flushing. Once I make this change, I can see the correct data in memory after flushing (by VA). Do you agree we should leave MMU on during flushing? >>> >>> If you're "flushing" by VA, then I'm not surprised since the MMU is what >>> defines the VA->PA mapping, and perhaps you have some physically tagged >>> caches. >>> >>> However, I believe U-Boot mainline currently "flushes" by set/way, which >>> I wouldn't expect MMU status to influence at all. >> >> Flushing by set/way (only) is what I am trying to change. It would be >> better if we don't have to flush L3. Do you agree? > > It depends on whether the L3 is before or after the Point of Coherency. > If it's before, then it needs to be cleaned. If it's after, then I > believe it's irrelevant and can be skipped. I don't believe there's any > other factor that will allow/prevent you from skipping operations on > your L3; there's no wiggle-room or leeway. As Mark pointed, out my L3 is before PoC. Flushing by set/way only cleans L1/L2 cache. If not flushing L3, or flushing by VA, my stack is corrupted. > > Related, consider the following from the Linux kernel's > Documentation/arm64/booting.txt: > >> - Caches, MMUs >> The MMU must be off. >> Instruction cache may be on or off. >> The address range corresponding to the loaded kernel image must be >> cleaned to the PoC. > > (That only applies to the kernel image specifically, but doing the same > for the entire cache content seems reasonable, perhaps even required for > other reasons?) Booting Linux is not an issue here. The kernel image is flushed by VA. I am struggling on the dcache_disable() which implies all dcache is flushed. I don't have a reasonable way to flush all if I want to skip L3. I tried to benchmark flushing by VA to cover my entire 16GB memory. It took 30+ seconds. On the other side, flushing by set/way and flushing L3 together took 7 ms. If I only flush U-Boot stack in this function, it can run really fast, but that defeats the purpose of flush all cache. I thought of parsing each set/way to find the address of each cache line (I don't know how to do that yet), but the tag only contains physical address not VA. The ARM document shows example code to clean entire data or unified cache to PoC, very similar to the code we have in U-Boot armv8/cache.S. Unless there are other cache maintenance instruction I am not aware of, I don't see how to flush to PoC by set/way. At this point, I don't see a reasonable way to implement flush all dcache without flushing L3. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v11] dm: at91: Add driver model support for the spi driver
Hi Jagan,
On 28.10.16 20:07, Jagan Teki wrote:
> On Fri, Oct 28, 2016 at 10:19 PM, Andreas Bießmann
> wrote:
>> Dear Wenyou Yang,
>>
>> Wenyou Yang writes:
>>> Add driver model support while retaining the existing legacy code.
>>> This allows the driver to support boards that have converted to
>>> driver model as well as those that have not.
>>>
>>> Signed-off-by: Wenyou Yang
>>> Reviewed-by: Simon Glass
>>> Acked-by: Stephen Warren
>>> ---
>>>
>>> Changes in v11:
>>> - Set cs_gpio direction to output and active.
>>> - Use wait_for_bit() to replace do {} while ().
>>> - Add more description for help of ATMEL_SPI.
>>>
>>> Changes in v10:
>>> - Add Acked-by tag.
>>>
>>> Changes in v9:
>>> - Due to the peripheral clock driver improvement, remove the
>>> unneccessary clock calling.
>>>
>>> Changes in v8:
>>> - Fix compile error for AVR32.
>>>
>>> Changes in v7:
>>> - Move gpio_request_list_by_name() to _probe(), remove
>>> *_ofdata_to_platdata().
>>>
>>> Changes in v6:
>>> - Remove the two flash related options.
>>>
>>> Changes in v5:
>>> - Change clk_client.h -> clk.h to adapt to clk API conversion.
>>>
>>> Changes in v4:
>>> - Collect Reviewed-by tag.
>>> - Update the clk API based on [PATCH] clk: convert API to match
>>> reset/mailbox fstyle (http://patchwork.ozlabs.org/patch/625342/).
>>> - Remove check on dev_get_parent() return.
>>> - Fixed the return value, -ENODEV->-EINVAL.
>>> - Retain #include line.
>>>
>>> Changes in v3:
>>> - Remove redundant log print.
>>>
>>> Changes in v2:
>>> - Add clock support.
>>>
>>> drivers/spi/Kconfig | 8 ++
>>> drivers/spi/atmel_spi.c | 288
>>>
>>> 2 files changed, 296 insertions(+)
>>
>> applied to u-boot-atmel/master, thanks!
>
> Sorry, don't know how come this is applied w/o any Ack/Review tag from
> the maintainer?
>
This patch is now in v11 and posted first in April this year, it was
most times delegated to me [1]. Sorry, when adding it today I did not
think of asking for your reviewed/acked-by. I try to respect this in future.
With your comment here I started a retrospective on this patch and
figured out it was once delegated to you (v7) and got a reviewed-by from
you which did not make it into the patch.
Do you have any objections? Should I remove this patch from the pull
request?
Andreas
[1]
http://patchwork.ozlabs.org/project/uboot/list/?submitter=&state=*&q=dm%3A+at91%3A+Add+driver+model+support+for+the+spi+driver&archive=&delegate=
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Re: [U-Boot] [PATCH 2/4] serial: pxa: integrate optional driver model handling
On 10/28/2016 10:50 PM, Marcel Ziswiler wrote:
> Optional driver model handling integration.
>
> Signed-off-by: Marcel Ziswiler
> ---
>
> drivers/serial/serial_pxa.c | 181
> ++
> include/dm/platform_data/serial_pxa.h | 56 +++
> 2 files changed, 174 insertions(+), 63 deletions(-)
> create mode 100644 include/dm/platform_data/serial_pxa.h
>
> diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c
> index 1eb19ec..b927a3e 100644
> --- a/drivers/serial/serial_pxa.c
> +++ b/drivers/serial/serial_pxa.c
> @@ -14,6 +14,9 @@
> *
> * Copyright (C) 1999 2000 2001 Erik Mouw (j.a.k.m...@its.tudelft.nl)
> *
> + * Modified to add driver model (DM) support
> + * (C) Copyright 2016 Marcel Ziswiler
> + *
> * SPDX-License-Identifier: GPL-2.0+
> */
>
> @@ -21,75 +24,32 @@
> #include
> #include
> #include
> +#include
> +#include
> #include
> #include
> #include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -/*
> - * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
> - * easily handle enabling of clock.
> - */
> -#ifdef CONFIG_CPU_MONAHANS
> -#define UART_CLK_BASE CKENA_21_BTUART
> -#define UART_CLK_REGCKENA
> -#define BTUART_INDEX0
> -#define FFUART_INDEX1
> -#define STUART_INDEX2
> -#elifCONFIG_CPU_PXA25X
> -#define UART_CLK_BASE (1 << 4)/* HWUART */
> -#define UART_CLK_REGCKEN
> -#define HWUART_INDEX0
> -#define STUART_INDEX1
> -#define FFUART_INDEX2
> -#define BTUART_INDEX3
> -#else/* PXA27x */
> -#define UART_CLK_BASE CKEN5_STUART
> -#define UART_CLK_REGCKEN
> -#define STUART_INDEX0
> -#define FFUART_INDEX1
> -#define BTUART_INDEX2
> -#endif
> -
> -/*
> - * Only PXA250 has HWUART, to avoid poluting the code with more macros,
> - * artificially introduce this.
> - */
> -#ifndef CONFIG_CPU_PXA25X
> -#define HWUART_INDEX0xff
> -#endif
> -
> -static uint32_t pxa_uart_get_baud_divider(void)
> +static uint32_t pxa_uart_get_baud_divider(int baudrate)
> {
While at it:
/* Do we even need this check ? */
if (baudrate != 1200 || baudrate != 9600 || baudrate != 19200 ||
baudrate != 38400 || baudrate != 57600 || baudrate != 115200)
return 0;
return 921600 / baudrate;
> - if (gd->baudrate == 1200)
> + if (baudrate == 1200)
> return 768;
> - else if (gd->baudrate == 9600)
> + else if (baudrate == 9600)
> return 96;
> - else if (gd->baudrate == 19200)
> + else if (baudrate == 19200)
> return 48;
> - else if (gd->baudrate == 38400)
> + else if (baudrate == 38400)
> return 24;
> - else if (gd->baudrate == 57600)
> + else if (baudrate == 57600)
> return 16;
> - else if (gd->baudrate == 115200)
> + else if (baudrate == 115200)
> return 8;
> else/* Unsupported baudrate */
> return 0;
> }
>
> -static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
> -{
> - switch (uart_index) {
> - case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
> - case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
> - case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
> - case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE;
> - default:
> - return NULL;
> - }
> -}
> -
> static void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
> {
> uint32_t clk_reg, clk_offset, reg;
> @@ -110,20 +70,13 @@ static void pxa_uart_toggle_clock(uint32_t uart_index,
> int enable)
> /*
> * Enable clock and set baud rate, parity etc.
> */
> -void pxa_setbrg_dev(uint32_t uart_index)
> +void pxa_setbrg_common(struct pxa_uart_regs *uart_regs, int port, int
> baudrate)
> {
> - uint32_t divider = 0;
> - struct pxa_uart_regs *uart_regs;
> -
> - divider = pxa_uart_get_baud_divider();
> + uint32_t divider = pxa_uart_get_baud_divider(baudrate);
> if (!divider)
> hang();
>
> - uart_regs = pxa_uart_index_to_regs(uart_index);
> - if (!uart_regs)
> - hang();
> -
> - pxa_uart_toggle_clock(uart_index, 1);
> + pxa_uart_toggle_clock(port, 1);
>
> /* Disable interrupts and FIFOs */
> writel(0, &uart_regs->ier);
> @@ -139,13 +92,38 @@ void pxa_setbrg_dev(uint32_t uart_index)
> writel(IER_UUE, &uart_regs->ier);
> }
>
> +#ifndef CONFIG_DM_SERIAL
> +static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
> +{
> + switch (uart_index) {
> + case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
> + case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
> + case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
> + case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE;
> +
[U-Boot] [PATCH 1/4] serial: pxa: use kconfig for serial configuration
Migrate the PXA serial driver to be configured via Kconfig. Signed-off-by: Marcel Ziswiler --- configs/colibri_pxa270_defconfig | 1 + configs/h2200_defconfig | 1 + configs/zipitz2_defconfig| 1 + drivers/serial/Kconfig | 6 ++ include/configs/colibri_pxa270.h | 1 - include/configs/h2200.h | 2 -- include/configs/zipitz2.h| 1 - scripts/config_whitelist.txt | 1 - 8 files changed, 9 insertions(+), 5 deletions(-) diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig index 9a57041..85740c2 100644 --- a/configs/colibri_pxa270_defconfig +++ b/configs/colibri_pxa270_defconfig @@ -13,6 +13,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_PXA_SERIAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/h2200_defconfig b/configs/h2200_defconfig index c1b359e..a47159a 100644 --- a/configs/h2200_defconfig +++ b/configs/h2200_defconfig @@ -24,3 +24,4 @@ CONFIG_SYS_PROMPT="> " # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set +CONFIG_PXA_SERIAL=y diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig index 8eb9be4..5846579 100644 --- a/configs/zipitz2_defconfig +++ b/configs/zipitz2_defconfig @@ -14,6 +14,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_PXA_SERIAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 541cf2e..cb6a2a2 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -386,4 +386,10 @@ config MSM_SERIAL for example APQ8016 and MSM8916. Single baudrate is supported in current implementation (115200). +config PXA_SERIAL + bool "PXA serial port support" + help + If you have a machine based on a Marvell XScale PXA2xx CPU you + can enable its onboard serial ports by enabling this option. + endmenu diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 429f571..5245609 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -44,7 +44,6 @@ /* * Serial Console Configuration */ -#defineCONFIG_PXA_SERIAL #defineCONFIG_FFUART 1 #define CONFIG_CONS_INDEX 3 #defineCONFIG_BAUDRATE 115200 diff --git a/include/configs/h2200.h b/include/configs/h2200.h index 8e77982..18b5488 100644 --- a/include/configs/h2200.h +++ b/include/configs/h2200.h @@ -107,8 +107,6 @@ /* * Serial port */ - -#define CONFIG_PXA_SERIAL #define CONFIG_FFUART #define CONFIG_CONS_INDEX 3 diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index ed2c9ac..97dfc0e 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -49,7 +49,6 @@ * Serial Console Configuration * STUART - the lower serial port on Colibri board */ -#defineCONFIG_PXA_SERIAL #defineCONFIG_STUART 1 #define CONFIG_CONS_INDEX 2 #defineCONFIG_BAUDRATE 115200 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 11b5a22..1aef1bc 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3740,7 +3740,6 @@ CONFIG_PWM_IMX CONFIG_PXA_LCD CONFIG_PXA_MMC_GENERIC CONFIG_PXA_PWR_I2C -CONFIG_PXA_SERIAL CONFIG_PXA_STD_I2C CONFIG_PXA_VGA CONFIG_PXA_VIDEO -- 2.5.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/4] serial: pxa: kconfig and optional driver model integration
This series integrates both Kconfig as well as optional driver model support for the PXA serial driver. As I do not have any of the other hardware available for testing for now I only transitioned the Colibri PXA270 to actually make use of DM_SERIAL. As space on this mostly NOR based hardware is rather constrained I decided against also integrating device tree support for now but rather use olde platform data. Your input on this is more than welcome. Marcel Ziswiler (4): serial: pxa: use kconfig for serial configuration serial: pxa: integrate optional driver model handling colibri_pxa270: drop lzma support for space reason colibri_pxa270: transition to driver model for serial board/toradex/colibri_pxa270/colibri_pxa270.c | 18 ++- configs/colibri_pxa270_defconfig | 3 + configs/h2200_defconfig | 1 + configs/zipitz2_defconfig | 1 + drivers/serial/Kconfig| 6 + drivers/serial/serial_pxa.c | 181 +- include/configs/colibri_pxa270.h | 4 - include/configs/h2200.h | 2 - include/configs/zipitz2.h | 1 - include/dm/platform_data/serial_pxa.h | 56 scripts/config_whitelist.txt | 1 - 11 files changed, 201 insertions(+), 73 deletions(-) create mode 100644 include/dm/platform_data/serial_pxa.h -- 2.5.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] colibri_pxa270: drop lzma support for space reason
As the upcoming driver model integration takes up some more precious flash space first make sure to drop expensive LZMA support. Signed-off-by: Marcel Ziswiler --- include/configs/colibri_pxa270.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 5245609..b16abdc 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -39,7 +39,6 @@ #defineCONFIG_TIMESTAMP #defineCONFIG_CMDLINE_TAG #defineCONFIG_SETUP_MEMORY_TAGS -#defineCONFIG_LZMA /* LZMA compression support */ /* * Serial Console Configuration -- 2.5.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] colibri_pxa270: transition to driver model for serial
Add serial platform data to board file.
Enable driver model for PXA serial driver.
Signed-off-by: Marcel Ziswiler
---
board/toradex/colibri_pxa270/colibri_pxa270.c | 18 --
configs/colibri_pxa270_defconfig | 2 ++
include/configs/colibri_pxa270.h | 2 --
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c
b/board/toradex/colibri_pxa270/colibri_pxa270.c
index 3def0a6..2e3e03a 100644
--- a/board/toradex/colibri_pxa270/colibri_pxa270.c
+++ b/board/toradex/colibri_pxa270/colibri_pxa270.c
@@ -8,10 +8,13 @@
#include
#include
-#include
#include
-#include
+#include
+#include
#include
+#include
+#include
+#include
#include
#include
@@ -105,3 +108,14 @@ int board_mmc_init(bd_t *bis)
return 0;
}
#endif
+
+static const struct pxa_serial_platdata serial_platdata = {
+ .base = (struct pxa_uart_regs *)FFUART_BASE,
+ .port = FFUART_INDEX,
+ .baudrate = CONFIG_BAUDRATE,
+};
+
+U_BOOT_DEVICE(pxa_serials) = {
+ .name = "serial_pxa",
+ .platdata = &serial_platdata,
+};
diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig
index 85740c2..46b3137 100644
--- a/configs/colibri_pxa270_defconfig
+++ b/configs/colibri_pxa270_defconfig
@@ -13,6 +13,8 @@ CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
CONFIG_PXA_SERIAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index b16abdc..66dba74 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -43,8 +43,6 @@
/*
* Serial Console Configuration
*/
-#defineCONFIG_FFUART 1
-#define CONFIG_CONS_INDEX 3
#defineCONFIG_BAUDRATE 115200
/*
--
2.5.5
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[U-Boot] [PATCH 2/4] serial: pxa: integrate optional driver model handling
Optional driver model handling integration.
Signed-off-by: Marcel Ziswiler
---
drivers/serial/serial_pxa.c | 181 ++
include/dm/platform_data/serial_pxa.h | 56 +++
2 files changed, 174 insertions(+), 63 deletions(-)
create mode 100644 include/dm/platform_data/serial_pxa.h
diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c
index 1eb19ec..b927a3e 100644
--- a/drivers/serial/serial_pxa.c
+++ b/drivers/serial/serial_pxa.c
@@ -14,6 +14,9 @@
*
* Copyright (C) 1999 2000 2001 Erik Mouw (j.a.k.m...@its.tudelft.nl)
*
+ * Modified to add driver model (DM) support
+ * (C) Copyright 2016 Marcel Ziswiler
+ *
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -21,75 +24,32 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
DECLARE_GLOBAL_DATA_PTR;
-/*
- * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
- * easily handle enabling of clock.
- */
-#ifdef CONFIG_CPU_MONAHANS
-#defineUART_CLK_BASE CKENA_21_BTUART
-#defineUART_CLK_REGCKENA
-#defineBTUART_INDEX0
-#defineFFUART_INDEX1
-#defineSTUART_INDEX2
-#elif CONFIG_CPU_PXA25X
-#defineUART_CLK_BASE (1 << 4)/* HWUART */
-#defineUART_CLK_REGCKEN
-#defineHWUART_INDEX0
-#defineSTUART_INDEX1
-#defineFFUART_INDEX2
-#defineBTUART_INDEX3
-#else /* PXA27x */
-#defineUART_CLK_BASE CKEN5_STUART
-#defineUART_CLK_REGCKEN
-#defineSTUART_INDEX0
-#defineFFUART_INDEX1
-#defineBTUART_INDEX2
-#endif
-
-/*
- * Only PXA250 has HWUART, to avoid poluting the code with more macros,
- * artificially introduce this.
- */
-#ifndefCONFIG_CPU_PXA25X
-#defineHWUART_INDEX0xff
-#endif
-
-static uint32_t pxa_uart_get_baud_divider(void)
+static uint32_t pxa_uart_get_baud_divider(int baudrate)
{
- if (gd->baudrate == 1200)
+ if (baudrate == 1200)
return 768;
- else if (gd->baudrate == 9600)
+ else if (baudrate == 9600)
return 96;
- else if (gd->baudrate == 19200)
+ else if (baudrate == 19200)
return 48;
- else if (gd->baudrate == 38400)
+ else if (baudrate == 38400)
return 24;
- else if (gd->baudrate == 57600)
+ else if (baudrate == 57600)
return 16;
- else if (gd->baudrate == 115200)
+ else if (baudrate == 115200)
return 8;
else/* Unsupported baudrate */
return 0;
}
-static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
-{
- switch (uart_index) {
- case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
- case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
- case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
- case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE;
- default:
- return NULL;
- }
-}
-
static void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
{
uint32_t clk_reg, clk_offset, reg;
@@ -110,20 +70,13 @@ static void pxa_uart_toggle_clock(uint32_t uart_index, int
enable)
/*
* Enable clock and set baud rate, parity etc.
*/
-void pxa_setbrg_dev(uint32_t uart_index)
+void pxa_setbrg_common(struct pxa_uart_regs *uart_regs, int port, int baudrate)
{
- uint32_t divider = 0;
- struct pxa_uart_regs *uart_regs;
-
- divider = pxa_uart_get_baud_divider();
+ uint32_t divider = pxa_uart_get_baud_divider(baudrate);
if (!divider)
hang();
- uart_regs = pxa_uart_index_to_regs(uart_index);
- if (!uart_regs)
- hang();
-
- pxa_uart_toggle_clock(uart_index, 1);
+ pxa_uart_toggle_clock(port, 1);
/* Disable interrupts and FIFOs */
writel(0, &uart_regs->ier);
@@ -139,13 +92,38 @@ void pxa_setbrg_dev(uint32_t uart_index)
writel(IER_UUE, &uart_regs->ier);
}
+#ifndef CONFIG_DM_SERIAL
+static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
+{
+ switch (uart_index) {
+ case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
+ case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
+ case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
+ case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE;
+ default:
+ return NULL;
+ }
+}
+
+/*
+ * Enable clock and set baud rate, parity etc.
+ */
+void pxa_setbrg_dev(uint32_t uart_index)
+{
+ struct pxa_uart_regs *uart_regs = pxa_uart_index_to_regs(uart_index);
+ if (!uart_regs)
+ hang();
+
+ pxa_setbrg_common(uart_regs, uart_index, gd->baudrate);
+}
+
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bi
Re: [U-Boot] [PATCH v3 2/2] image: Protect against overflow in unknown_msg()
On Fri, Oct 28, 2016 at 12:41:05PM -0700, Simon Glass wrote:
> Hi Tom,
>
> On 28 October 2016 at 11:59, Tom Rini wrote:
> > On Thu, Oct 27, 2016 at 08:18:39PM -0600, Simon Glass wrote:
> >> Coverity complains that this can overflow. If we later increase the size
> >> of one of the strings in the table, it could happen.
> >>
> >> Adjust the code to protect against this.
> >>
> >> Signed-off-by: Simon Glass
> >> Reported-by: Coverity (CID: 150964)
> >> ---
> >>
> >> Changes in v3:
> >> - Adjust to deal with what strncpy() actually does (I think)
> >>
> >> Changes in v2:
> >> - Drop unwanted #include
> >>
> >> common/image.c | 6 --
> >> 1 file changed, 4 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/common/image.c b/common/image.c
> >> index 0e86c13..016f263 100644
> >> --- a/common/image.c
> >> +++ b/common/image.c
> >> @@ -588,9 +588,11 @@ const table_entry_t *get_table_entry(const
> >> table_entry_t *table, int id)
> >> static const char *unknown_msg(enum ih_category category)
> >> {
> >> static char msg[30];
> >> + static char unknown_str = "Unknown ";
> >>
> >> - strcpy(msg, "Unknown ");
> >> - strcat(msg, table_info[category].desc);
> >> + strcpy(msg, unknown_str);
> >> + strncat(msg, table_info[category].desc,
> >> + sizeof(msg) - sizeof(unknown_str));
> >
> > We still need to subtract 1 more here at the end, for the NUL don't we?
>
> I was hoping that the sizeof(msg) would take care of that?
No, and you didn't compile test this did you? ;) I was trying to throw
up a stupid test to confirm what all everything would be.
test.c:6:28: warning: initialization makes integer from pointer without a cast
[-Wint-conversion]
static char unknown_str = "Unknown ";
^~
test.c:6:28: error: initializer element is not computable at load time
Correcting that to be *unknown_str gives us back the sizeof(char *) not
the string in question. So we need to use strlen(unknown_str), and
strlen does not include the NUL, so we would need to still add in the -
1 after all of the above.
And I'm being verbose above because string handling can be annoying and
I didn't get it 100% right in my head so I figured it's worth showing
the work. And since we're going with "Coverity says we've got string
problems" we should really correct it, and not just be wrong in a
different way :)
--
Tom
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Re: [U-Boot] [PATCH v3 2/2] image: Protect against overflow in unknown_msg()
Hi Tom,
On 28 October 2016 at 11:59, Tom Rini wrote:
> On Thu, Oct 27, 2016 at 08:18:39PM -0600, Simon Glass wrote:
>> Coverity complains that this can overflow. If we later increase the size
>> of one of the strings in the table, it could happen.
>>
>> Adjust the code to protect against this.
>>
>> Signed-off-by: Simon Glass
>> Reported-by: Coverity (CID: 150964)
>> ---
>>
>> Changes in v3:
>> - Adjust to deal with what strncpy() actually does (I think)
>>
>> Changes in v2:
>> - Drop unwanted #include
>>
>> common/image.c | 6 --
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/common/image.c b/common/image.c
>> index 0e86c13..016f263 100644
>> --- a/common/image.c
>> +++ b/common/image.c
>> @@ -588,9 +588,11 @@ const table_entry_t *get_table_entry(const
>> table_entry_t *table, int id)
>> static const char *unknown_msg(enum ih_category category)
>> {
>> static char msg[30];
>> + static char unknown_str = "Unknown ";
>>
>> - strcpy(msg, "Unknown ");
>> - strcat(msg, table_info[category].desc);
>> + strcpy(msg, unknown_str);
>> + strncat(msg, table_info[category].desc,
>> + sizeof(msg) - sizeof(unknown_str));
>
> We still need to subtract 1 more here at the end, for the NUL don't we?
I was hoping that the sizeof(msg) would take care of that?
Regards,
Simon
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Re: [U-Boot] [Resend RFC PATCH 1/2] armv8: Fix dcache disable function
On 10/26/2016 02:02 PM, york@nxp.com wrote: > > I came back from my testing and I have more questions than answers. > > For _this_ patch, I proposed to flush cache before disabling them, > noting once the dcache is disabled, the staled data in dirty cache is > not visible to the core. My argument was if we flush L1/L2, they could > end up in L3 (I don't know for sure). If I want to skip flushing L3, I > have to fix it. > > During this discussion, I thought I made a mistake by flushing L1/L2 by > way/set first, then flushing by VA. Actually I didn't. I flushed by VA > first. > > With my today's test, the baseline (working in the sense of booting > Linux) is > > PATCH 1/2 armv8: Fix dcache disable function > PATCH 2/2 armv8: Fix flush_dcache_all function > > With these two patches, I flush the stack up to top of U-Boot by VA, > followed by flush by set/way. L3 is not flushed. Then d-cache is > disabled. I know this is not a real "flush all" procedure. With this > modified procedure, I can continue to boot Linux. > > If I revert patch 1, i.e. to disable dcache before flushing, I can see > the data is not visible from the core (debug with JTAG tool). My hope > was the staled data should be flushed to main memory if flushed by VA. > That's not the case. The main memory doesn't have the correct data. So > my new question is, why flushing by VA doesn't flush the data to main > memory? Do I need to flush the cache while cache is enabled? > Guys, I think I found the root cause of my data loss. Current code disables D-cache and MMU before flushing the cache. I think the problem is turning off MMU. MMU should stay on when we flush D-cache. We can turn it off after the flushing. Once I make this change, I can see the correct data in memory after flushing (by VA). Do you agree we should leave MMU on during flushing? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/2] image: Protect against overflow in unknown_msg()
On Thu, Oct 27, 2016 at 08:18:39PM -0600, Simon Glass wrote:
> Coverity complains that this can overflow. If we later increase the size
> of one of the strings in the table, it could happen.
>
> Adjust the code to protect against this.
>
> Signed-off-by: Simon Glass
> Reported-by: Coverity (CID: 150964)
> ---
>
> Changes in v3:
> - Adjust to deal with what strncpy() actually does (I think)
>
> Changes in v2:
> - Drop unwanted #include
>
> common/image.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/common/image.c b/common/image.c
> index 0e86c13..016f263 100644
> --- a/common/image.c
> +++ b/common/image.c
> @@ -588,9 +588,11 @@ const table_entry_t *get_table_entry(const table_entry_t
> *table, int id)
> static const char *unknown_msg(enum ih_category category)
> {
> static char msg[30];
> + static char unknown_str = "Unknown ";
>
> - strcpy(msg, "Unknown ");
> - strcat(msg, table_info[category].desc);
> + strcpy(msg, unknown_str);
> + strncat(msg, table_info[category].desc,
> + sizeof(msg) - sizeof(unknown_str));
We still need to subtract 1 more here at the end, for the NUL don't we?
--
Tom
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Re: [U-Boot] [PATCH 01/11] sunxi: DRAM initialisation for sun9i
On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai wrote:
> From: Philipp Tomsich
>
> This adds DRAM initialisation code for sun9i, which calculates the
> appropriate timings based on timing information for the supplied
> DDR3 bin and the clock speeds used.
>
> With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
> (i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.
>
> [w...@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
> Signed-off-by: Chen-Yu Tsai
> ---
> arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 34 +-
> arch/arm/include/asm/arch-sunxi/cpu_sun9i.h |6 +
> arch/arm/include/asm/arch-sunxi/dram.h|2 +
> arch/arm/include/asm/arch-sunxi/dram_sun9i.h | 275 +++
> arch/arm/mach-sunxi/Makefile |1 +
> arch/arm/mach-sunxi/dram_sun9i.c | 1059
> +
> board/sunxi/Kconfig |6 +-
> 7 files changed, 1368 insertions(+), 15 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h
> create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c
Checkpatch:
total: 45 errors, 77 warnings, 42 checks, 1464 lines checked
>
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
> b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
> index a61934fb3661..82881ff8bdaf 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
> @@ -37,57 +37,61 @@ struct sunxi_ccm_reg {
> u8 reserved3[0x04]; /* 0x7c */
> u32 ats_cfg;/* 0x80 ats clock configuration */
> u32 trace_cfg; /* 0x84 trace clock configuration */
> - u8 reserved4[0xf8]; /* 0x88 */
> + u8 reserved4[0x14]; /* 0x88 */
> + u32 pll_stable_status; /* 0x9c */
> + u8 reserved5[0xe0]; /* 0xa0 */
> u32 clk_output_a; /* 0x180 clk_output_a */
> u32 clk_output_b; /* 0x184 clk_output_a */
> - u8 reserved5[0x278];/* 0x188 */
> + u8 reserved6[0x278];/* 0x188 */
>
> u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */
> u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
> - u8 reserved6[0x08]; /* 0x408 */
> + u8 reserved7[0x08]; /* 0x408 */
> u32 sd0_clk_cfg;/* 0x410 sd0 clock configuration */
> u32 sd1_clk_cfg;/* 0x414 sd1 clock configuration */
> u32 sd2_clk_cfg;/* 0x418 sd2 clock configuration */
> u32 sd3_clk_cfg;/* 0x41c sd3 clock configuration */
> - u8 reserved7[0x08]; /* 0x420 */
> + u8 reserved8[0x08]; /* 0x420 */
> u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */
> u32 ss_clk_cfg; /* 0x42c security system clock cfg */
> u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */
> u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */
> u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */
> u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */
> - u8 reserved8[0x50]; /* 0x440 */
> + u8 reserved9[0x44]; /* 0x440 */
> + u32 dram_clk_cfg; /* 0x484 DRAM (controller) clock
> configuration */
> + u8 reserved10[0x8]; /* 0x488 */
> u32 de_clk_cfg; /* 0x490 display engine clock configuration */
> - u8 reserved9[0x04]; /* 0x494 */
> + u8 reserved11[0x04];/* 0x494 */
> u32 mp_clk_cfg; /* 0x498 mp clock configuration */
> u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */
> u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */
> - u8 reserved10[0x1c];/* 0x4a4 */
> + u8 reserved12[0x1c];/* 0x4a4 */
> u32 csi_isp_clk_cfg;/* 0x4c0 CSI ISP module clock */
> u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */
> u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */
> u32 fd_clk_cfg; /* 0x4cc FD module clock */
> u32 ve_clk_cfg; /* 0x4d0 VE module clock */
> u32 avs_clk_cfg;/* 0x4d4 AVS module clock */
> - u8 reserved11[0x18];/* 0x4d8 */
> + u8 reserved13[0x18];/* 0x4d8 */
> u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */
> u32 gpu_mem_clk_cfg;/* 0x4f4 GPU memory clock config */
> u32 gpu_axi_clk_cfg;/* 0x4f8 GPU AXI clock config */
> - u8 reserved12[0x10];/* 0x4fc */
> + u8 reserved14[0x10];/* 0x4fc */
> u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */
> - u8 reserved13[0x70];/* 0x510 */
> + u8 reserved15[0x70];/* 0x510 */
>
> u32 ahb_gate0; /* 0x580 AHB0 Gating Register */
> u32 ahb_gate1; /* 0x584 AHB1 Gating Register */
> u32 ahb_gate2; /* 0x588 AHB2 Gating Register */
> - u8 reserved14[0x04];/* 0x5
[U-Boot] [PATCH 2/2][v2] armv8: ls1046aqds: add lpuart support
From: Shaohui Xie
LPUART0 is used by default, and it's using platform clock.
Signed-off-by: Shaohui Xie
---
changes in v2:
1. dropped CONFIG_LPUART_CLK.
2. uses CONFIG_SYS_FSL_DDR4 in defconfig.
arch/arm/dts/Makefile | 1 +
arch/arm/dts/fsl-ls1046a-qds-lpuart.dts | 16 ++
arch/arm/dts/fsl-ls1046a-qds.dtsi | 4 +++
arch/arm/dts/fsl-ls1046a.dtsi | 54 +
board/freescale/ls1046aqds/ls1046aqds.c | 18 +++
configs/ls1046aqds_lpuart_defconfig | 30 ++
include/configs/ls1046aqds.h| 8 +
7 files changed, 131 insertions(+)
create mode 100644 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
create mode 100644 configs/ls1046aqds_lpuart_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8dbaea0..afc68e1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -148,6 +148,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
fsl-ls1046a-qds-duart.dtb \
+ fsl-ls1046a-qds-lpuart.dtb \
fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
new file mode 100644
index 000..21243d0
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1046a-qds.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &lpuart0;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi
b/arch/arm/dts/fsl-ls1046a-qds.dtsi
index c512293..a49ca08 100644
--- a/arch/arm/dts/fsl-ls1046a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi
@@ -75,3 +75,7 @@
&duart1 {
status = "okay";
};
+
+&lpuart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 87dd997..359a9d1 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -151,6 +151,60 @@
clocks = <&clockgen 4 0>;
};
+ lpuart0: serial@295 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x295 0x0 0x1000>;
+ interrupts = <0 48 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart1: serial@296 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x296 0x0 0x1000>;
+ interrupts = <0 49 0x4>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial@297 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x297 0x0 0x1000>;
+ interrupts = <0 50 0x4>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart3: serial@298 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x298 0x0 0x1000>;
+ interrupts = <0 51 0x4>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart4: serial@299 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x299 0x0 0x1000>;
+ interrupts = <0 52 0x4>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart5: serial@29a {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x29a 0x0 0x1000>;
+ interrupts = <0 53 0x4>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
qspi: quadspi@155 {
compatible = "fsl,vf610-qspi";
#address-cells = <1>;
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c
b/board/freescale/ls1046aqds/ls1046aqds.c
index 8c18538..552365b 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -120,6 +120,13 @@ unsigned long get_board_ddr_clk(void)
return ;
}
+#ifdef CONFIG_LPUART
+u32 get_lpuart_clk(void)
[U-Boot] [PATCH 1/2][v2] lpuart: add a get_lpuart_clk function
From: Shaohui Xie
It's not always true that LPUART clock is CONFIG_SYS_CLK_FREQ, this
patch provides a weak function get_lpuart_clk, so that the clock can be
ovreride on a specific board which uses different clock for LPUART.
Signed-off-by: Shaohui Xie
---
changes in v2:
none.
drivers/serial/serial_lpuart.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 042e9a2..beb4243 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -170,9 +170,14 @@ static int lpuart_serial_probe(struct udevice *dev)
}
#else
+u32 __weak get_lpuart_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate)
{
- u32 clk = CONFIG_SYS_CLK_FREQ;
+ u32 clk = get_lpuart_clk();
u32 sbr;
sbr = (clk / (16 * baudrate));
--
2.1.0.27.g96db324
___
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Re: [U-Boot] [PATCH V1] Add support of ls1021a-iot
Hi York/Alison, I have already sent patch to upstream at 10/13/2016. And the u-boot have too many changes now. Do you means that I will git the latest u-boot and repatch/ review/upstream it again ? > -Original Message- > From: Alison Wang > Sent: Thursday, October 27, 2016 3:43 PM > To: Feng Li ; york sun ; u- > b...@lists.denx.de > Cc: Feng Li > Subject: RE: [U-Boot] [PATCH V1] Add support of ls1021a-iot > > Hi, Feng, > > > From: Feng Li > > > > The patch add support ls1021a-iot. > > It supports I2C, MMC, PCIe, eTSEC, SATA, EEPROM, CPLD, HDMI, Serial > > port, HXCI, DSPI, SD boot, QSPI boot, Broadcom wifi card, QCA wifi card. > > > > Signed-off-by: Feng Li > > --- > > > > diff --git a/include/configs/ls1021aiot.h > > b/include/configs/ls1021aiot.h new file mode 100644 index > > 000..dc8e955 > > --- /dev/null > > +++ b/include/configs/ls1021aiot.h > > @@ -0,0 +1,375 @@ > > +/* > > + * Copyright 2016 Freescale Semiconductor, Inc. > > + * > > + * SPDX-License-Identifier:GPL-2.0+ > > + */ > > + > > +#ifndef __CONFIG_H > > +#define __CONFIG_H > > + > > +#define CONFIG_LS102XA > > +#define CONFIG_ARMV7_PSCI_1_0 > > +#define CONFIG_ARMV7_PSCI_GTE_1_0 > [Alison Wang] Where is this macro mentioned? I didn't find any related code. > > > +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR > > + > > +#define CONFIG_SYS_FSL_CLK > > + > > +#define CONFIG_DISPLAY_CPUINFO > > +#define CONFIG_DISPLAY_BOARDINFO > > + > > +#define CONFIG_BOARD_EARLY_INIT_F > > + > > > > + > > +#define CONFIG_ARMV7_NONSEC > > +#define CONFIG_ARMV7_VIRT > [Alison Wang] For selecting ARMV7_PSCI correctly, these two lines need to be > removed, and CPU_V7_HAS_NONSEC and CPU_V7_HAS_VIRT are added in > Kconfig. > Please refer to commits adee1d4, 217f92b and 1544698. > > From adee1d4c9eb16a49ec1396b3367d027b7c3d2940 Mon Sep 17 00:00:00 > 2001 > From: Hongbo Zhang > Date: Wed, 21 Sep 2016 18:31:04 +0800 > Subject: [PATCH] ARMv7: LS102xA: Move two macros from header files to > Kconfig > > Following commits 217f92b and 1544698, these two config > CPU_V7_HAS_NONSEC and CPU_V7_HAS_VIRT are moved to Kconfig, for > correctly select ARMV7_PSCI. > > Signed-off-by: Hongbo Zhang [York Sun: > Reformatted commit message] > Reviewed-by: York Sun > > > +#define CONFIG_PEN_ADDR_BIG_ENDIAN > > +#define CONFIG_LAYERSCAPE_NS_ACCESS > > +#define CONFIG_SMP_PEN_ADDR0x01ee0200 > > +#define CONFIG_TIMER_CLK_FREQ 1250 > > + > > +#define CONFIG_HWCONFIG > > +#define HWCONFIG_BUFFER_SIZE 256 > > + > > +#define CONFIG_FSL_DEVICE_DISABLE > > + > > +#define CONFIG_EXTRA_ENV_SETTINGS \ > > + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ > > +"initrd_high=0x\0" \ > > +"fdt_high=0x\0" > > + > > Best Regards, > Alison Wang Thanks, Feng Li ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/11] sunxi: add gtbus-initialisation for sun9i
On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai wrote:
> From: Philipp Tomsich
>
> On sun9i, the GTBUS manages transaction priority and bandwidth
> for multiple read ports when accessing DRAM. The initialisation
> mirrors the settings from Allwinner's boot0 for now, even though
> this may not be optimal for all applications (e.g. headless
> systems might want to give priority to IO modules).
>
> Adding a common callout to gtbus_init() from the SPL clock init
> with a weakly defined implementation in sunxi/clock.c to fallback
> to for platforms that don't require this.
>
> [w...@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
> Signed-off-by: Chen-Yu Tsai
> ---
> arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 2 +
> arch/arm/include/asm/arch-sunxi/gtbus.h | 21 +++
> arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h | 89
> +++
> arch/arm/mach-sunxi/Makefile | 1 +
> arch/arm/mach-sunxi/clock.c | 6 ++
> arch/arm/mach-sunxi/gtbus_sun9i.c | 48 +++
> 6 files changed, 167 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h
> create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
> create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c
>
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
> b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
> index acbc94f4c3b8..ba18a0f551ad 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
> @@ -23,6 +23,8 @@
> #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
> #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
>
> +#define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
> +
> #define SUNXI_MMC0_BASE(REGS_AHB0_BASE + 0x0f000)
> #define SUNXI_MMC1_BASE(REGS_AHB0_BASE + 0x1)
> #define SUNXI_MMC2_BASE(REGS_AHB0_BASE + 0x11000)
> diff --git a/arch/arm/include/asm/arch-sunxi/gtbus.h
> b/arch/arm/include/asm/arch-sunxi/gtbus.h
> new file mode 100644
> index ..b8308d513545
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-sunxi/gtbus.h
> @@ -0,0 +1,21 @@
> +/*
> + * GTBUS initialisation
> + *
> + * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
> + *Philipp Tomsich
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#ifndef _SUNXI_GTBUS_H
> +#define _SUNXI_GTBUS_H
> +
> +#if defined(CONFIG_MACH_SUN9I)
> +#include
> +#endif
> +
> +#ifndef __ASSEMBLY__
> +void gtbus_init(void);
> +#endif
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
> b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
> new file mode 100644
> index ..91bc2bdb5103
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
> @@ -0,0 +1,89 @@
> +/*
> + * GTBUS initialisation for sun9i
> + *
> + * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
> + *Philipp Tomsich
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#ifndef _SUNXI_GTBUS_SUN9I_H
> +#define _SUNXI_GTBUS_SUN9I_H
> +
> +#include
> +
> +struct sunxi_gtbus_reg {
> + u32 mst_cfg[36]; /* 0x000 */
> + u8 reserved1[0x70]; /* 0x090 */
> + u32 bw_wdw_cfg;/* 0x100 */
> + u32 mst_read_prio_cfg[2]; /* 0x104 */
> + u32 lvl2_mst_cfg; /* 0x10c */
> + u32 sw_clk_on; /* 0x110 */
> + u32 sw_clk_off;/* 0x114 */
> + u32 pmu_mst_en;/* 0x118 */
> + u32 pmu_cfg; /* 0x11c */
> + u32 pmu_cnt[19]; /* 0x120 */
> + u32 reserved2[0x94]; /* 0x16c */
> + u32 cci400_config[3]; /* 0x200 */
> + u32 cci400_status[2]; /* 0x20c */
> +};
> +
> +/* for register GT_MST_CFG_REG(n) */
> +#define GT_ENABLE_REQ (1<<31) /* clock on */
> +#define GT_DISABLE_REQ (1<<30) /* clock off */
> +#define GT_QOS_SHIFT28
> +#define GT_THD1_SHIFT 16
> +#define GT_REQN_MAX 0xf /* max number master requests in one
> cycle */
> +#define GT_REQN_SHIFT 12
> +#define GT_THD0_SHIFT 0
> +
> +#define GT_QOS_MAX 0x3
> +#define GT_THD_MAX 0xfff
> +#define GT_BW_WDW_MAX 0x
> +
> +/* mst_read_prio_cfg */
> +#define GT_PRIO_LOW 0
> +#define GT_PRIO_HIGH1
> +
> +/* GTBUS port ids */
> +#define GT_PORT_CPUM1 0
> +#define GT_PORT_CPUM2 1
> +#define GT_PORT_SATA2
> +#defineGT_PORT_USB33
> +#defineGT_PORT_FE0 4
> +#defineGT_PORT_BE1 5
> +#defineGT_PORT_BE2 6
> +#defineGT_PORT_IEP07
> +#defineGT_PORT_FE1 8
> +#defineGT_PORT_BE0 9
> +#defineGT_PORT_FE2 10
> +#defineGT_PORT_IEP111
> +#defineGT_PORT_VED 12
> +#
Re: [U-Boot] [Resend RFC PATCH 1/2] armv8: Fix dcache disable function
On 10/28/2016 10:57 AM, Stephen Warren wrote: > On 10/28/2016 11:38 AM, york sun wrote: >> On 10/26/2016 02:02 PM, york@nxp.com wrote: >>> >>> I came back from my testing and I have more questions than answers. >>> >>> For _this_ patch, I proposed to flush cache before disabling them, >>> noting once the dcache is disabled, the staled data in dirty cache is >>> not visible to the core. My argument was if we flush L1/L2, they could >>> end up in L3 (I don't know for sure). If I want to skip flushing L3, I >>> have to fix it. >>> >>> During this discussion, I thought I made a mistake by flushing L1/L2 by >>> way/set first, then flushing by VA. Actually I didn't. I flushed by VA >>> first. >>> >>> With my today's test, the baseline (working in the sense of booting >>> Linux) is >>> >>> PATCH 1/2 armv8: Fix dcache disable function >>> PATCH 2/2 armv8: Fix flush_dcache_all function >>> >>> With these two patches, I flush the stack up to top of U-Boot by VA, >>> followed by flush by set/way. L3 is not flushed. Then d-cache is >>> disabled. I know this is not a real "flush all" procedure. With this >>> modified procedure, I can continue to boot Linux. >>> >>> If I revert patch 1, i.e. to disable dcache before flushing, I can see >>> the data is not visible from the core (debug with JTAG tool). My hope >>> was the staled data should be flushed to main memory if flushed by VA. >>> That's not the case. The main memory doesn't have the correct data. So >>> my new question is, why flushing by VA doesn't flush the data to main >>> memory? Do I need to flush the cache while cache is enabled? >>> >> >> Guys, >> >> I think I found the root cause of my data loss. >> >> Current code disables D-cache and MMU before flushing the cache. I think >> the problem is turning off MMU. MMU should stay on when we flush >> D-cache. We can turn it off after the flushing. Once I make this change, >> I can see the correct data in memory after flushing (by VA). >> >> Do you agree we should leave MMU on during flushing? > > If you're "flushing" by VA, then I'm not surprised since the MMU is what > defines the VA->PA mapping, and perhaps you have some physically tagged > caches. > > However, I believe U-Boot mainline currently "flushes" by set/way, which > I wouldn't expect MMU status to influence at all. Flushing by set/way (only) is what I am trying to change. It would be better if we don't have to flush L3. Do you agree? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Resend RFC PATCH 1/2] armv8: Fix dcache disable function
On 10/28/2016 12:17 PM, york sun wrote: On 10/28/2016 10:57 AM, Stephen Warren wrote: On 10/28/2016 11:38 AM, york sun wrote: On 10/26/2016 02:02 PM, york@nxp.com wrote: I came back from my testing and I have more questions than answers. For _this_ patch, I proposed to flush cache before disabling them, noting once the dcache is disabled, the staled data in dirty cache is not visible to the core. My argument was if we flush L1/L2, they could end up in L3 (I don't know for sure). If I want to skip flushing L3, I have to fix it. During this discussion, I thought I made a mistake by flushing L1/L2 by way/set first, then flushing by VA. Actually I didn't. I flushed by VA first. With my today's test, the baseline (working in the sense of booting Linux) is PATCH 1/2 armv8: Fix dcache disable function PATCH 2/2 armv8: Fix flush_dcache_all function With these two patches, I flush the stack up to top of U-Boot by VA, followed by flush by set/way. L3 is not flushed. Then d-cache is disabled. I know this is not a real "flush all" procedure. With this modified procedure, I can continue to boot Linux. If I revert patch 1, i.e. to disable dcache before flushing, I can see the data is not visible from the core (debug with JTAG tool). My hope was the staled data should be flushed to main memory if flushed by VA. That's not the case. The main memory doesn't have the correct data. So my new question is, why flushing by VA doesn't flush the data to main memory? Do I need to flush the cache while cache is enabled? Guys, I think I found the root cause of my data loss. Current code disables D-cache and MMU before flushing the cache. I think the problem is turning off MMU. MMU should stay on when we flush D-cache. We can turn it off after the flushing. Once I make this change, I can see the correct data in memory after flushing (by VA). Do you agree we should leave MMU on during flushing? If you're "flushing" by VA, then I'm not surprised since the MMU is what defines the VA->PA mapping, and perhaps you have some physically tagged caches. However, I believe U-Boot mainline currently "flushes" by set/way, which I wouldn't expect MMU status to influence at all. Flushing by set/way (only) is what I am trying to change. It would be better if we don't have to flush L3. Do you agree? It depends on whether the L3 is before or after the Point of Coherency. If it's before, then it needs to be cleaned. If it's after, then I believe it's irrelevant and can be skipped. I don't believe there's any other factor that will allow/prevent you from skipping operations on your L3; there's no wiggle-room or leeway. Related, consider the following from the Linux kernel's Documentation/arm64/booting.txt: - Caches, MMUs The MMU must be off. Instruction cache may be on or off. The address range corresponding to the loaded kernel image must be cleaned to the PoC. (That only applies to the kernel image specifically, but doing the same for the entire cache content seems reasonable, perhaps even required for other reasons?) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v11] dm: at91: Add driver model support for the spi driver
On Fri, Oct 28, 2016 at 10:19 PM, Andreas Bießmann
wrote:
> Dear Wenyou Yang,
>
> Wenyou Yang writes:
>>Add driver model support while retaining the existing legacy code.
>>This allows the driver to support boards that have converted to
>>driver model as well as those that have not.
>>
>>Signed-off-by: Wenyou Yang
>>Reviewed-by: Simon Glass
>>Acked-by: Stephen Warren
>>---
>>
>>Changes in v11:
>> - Set cs_gpio direction to output and active.
>> - Use wait_for_bit() to replace do {} while ().
>> - Add more description for help of ATMEL_SPI.
>>
>>Changes in v10:
>> - Add Acked-by tag.
>>
>>Changes in v9:
>> - Due to the peripheral clock driver improvement, remove the
>> unneccessary clock calling.
>>
>>Changes in v8:
>> - Fix compile error for AVR32.
>>
>>Changes in v7:
>> - Move gpio_request_list_by_name() to _probe(), remove
>> *_ofdata_to_platdata().
>>
>>Changes in v6:
>> - Remove the two flash related options.
>>
>>Changes in v5:
>> - Change clk_client.h -> clk.h to adapt to clk API conversion.
>>
>>Changes in v4:
>> - Collect Reviewed-by tag.
>> - Update the clk API based on [PATCH] clk: convert API to match
>> reset/mailbox fstyle (http://patchwork.ozlabs.org/patch/625342/).
>> - Remove check on dev_get_parent() return.
>> - Fixed the return value, -ENODEV->-EINVAL.
>> - Retain #include line.
>>
>>Changes in v3:
>> - Remove redundant log print.
>>
>>Changes in v2:
>> - Add clock support.
>>
>> drivers/spi/Kconfig | 8 ++
>> drivers/spi/atmel_spi.c | 288
>>
>> 2 files changed, 296 insertions(+)
>
> applied to u-boot-atmel/master, thanks!
Sorry, don't know how come this is applied w/o any Ack/Review tag from
the maintainer?
thanks!
--
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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[U-Boot] [PATCH] MAINTAINERS: Update Jagan's email
Signed-off-by: Jagan Teki --- MAINTAINERS| 2 +- doc/git-mailrc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8e67202..0bd8995 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -417,7 +417,7 @@ T: git git://git.denx.de/u-boot-sparc.git F: arch/sparc/ SPI -M: Jagan Teki +M: Jagan Teki S: Maintained T: git git://git.denx.de/u-boot-spi.git F: drivers/mtd/spi/ diff --git a/doc/git-mailrc b/doc/git-mailrc index a14629c..d01a8c7 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -24,7 +24,7 @@ alias hs Heiko Schocher alias ijcIan Campbell alias iwamatsu Nobuhiro Iwamatsu alias jaehoonJaehoon Chung -alias jagan Jagan Teki +alias jagan Jagan Teki alias jasonjin Jason Jin alias jhersh Joe Hershberger alias jwrdegoede Hans de Goede -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Resend RFC PATCH 1/2] armv8: Fix dcache disable function
On 10/28/2016 11:38 AM, york sun wrote: On 10/26/2016 02:02 PM, york@nxp.com wrote: I came back from my testing and I have more questions than answers. For _this_ patch, I proposed to flush cache before disabling them, noting once the dcache is disabled, the staled data in dirty cache is not visible to the core. My argument was if we flush L1/L2, they could end up in L3 (I don't know for sure). If I want to skip flushing L3, I have to fix it. During this discussion, I thought I made a mistake by flushing L1/L2 by way/set first, then flushing by VA. Actually I didn't. I flushed by VA first. With my today's test, the baseline (working in the sense of booting Linux) is PATCH 1/2 armv8: Fix dcache disable function PATCH 2/2 armv8: Fix flush_dcache_all function With these two patches, I flush the stack up to top of U-Boot by VA, followed by flush by set/way. L3 is not flushed. Then d-cache is disabled. I know this is not a real "flush all" procedure. With this modified procedure, I can continue to boot Linux. If I revert patch 1, i.e. to disable dcache before flushing, I can see the data is not visible from the core (debug with JTAG tool). My hope was the staled data should be flushed to main memory if flushed by VA. That's not the case. The main memory doesn't have the correct data. So my new question is, why flushing by VA doesn't flush the data to main memory? Do I need to flush the cache while cache is enabled? Guys, I think I found the root cause of my data loss. Current code disables D-cache and MMU before flushing the cache. I think the problem is turning off MMU. MMU should stay on when we flush D-cache. We can turn it off after the flushing. Once I make this change, I can see the correct data in memory after flushing (by VA). Do you agree we should leave MMU on during flushing? If you're "flushing" by VA, then I'm not surprised since the MMU is what defines the VA->PA mapping, and perhaps you have some physically tagged caches. However, I believe U-Boot mainline currently "flushes" by set/way, which I wouldn't expect MMU status to influence at all. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: dts: Pine64: add Ethernet alias
On Thu, Oct 27, 2016 at 2:20 AM, André Przywara wrote:
> On 26/10/16 19:51, Jagan Teki wrote:
> Hi,
>
>> On Fri, Oct 21, 2016 at 5:41 AM, Andre Przywara
>> wrote:
>>> The sun8i-emac driver works fine with the A64 Ethernet IP, but we are
>>> missing an alias entry to trigger the driver instantiation by U-Boot.
>>> Add the line to point U-Boot to the Ethernet DT node.
>>> This enables TFTP boot on the Pine64.
>>>
>>> Signed-off-by: Andre Przywara
>>> ---
>>> arch/arm/dts/sun50i-a64-pine64-common.dtsi | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
>>> b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
>>> index d5a7249..c0fde44 100644
>>> --- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
>>> +++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
>>> @@ -46,6 +46,7 @@
>>>
>>> aliases {
>>> serial0 = &uart0;
>>> + ethernet0 = &emac;
>>
>> Better to have this alias on sun50i-a64.dtsi since the node is defined there?
>
> Mmh, I find examples for both ways (.dtsi vs. .dts) in the kernel. I
> need to learn what's the best practice here.
>
> But the U-Boot DTs need to get replaced anyway soon-ish, since the Linux
> DTs (which are WIP) have already diverged.
> So what about we keep this alias here next to the existing one for the
> 2016.11 release and possibly fix this later once we replace the DTs
> anyway with what gets merged into the kernel eventually?
OK, but please stick with the current discussion and still I see a
good point to see alias on dtsi because the dts files which are using
this dtsi shouldn't separately define the alias.
And also status on dtsi is showing "disabled" are you enabled it some
other patches? or missed?
thanks!
--
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH 00/11] sunxi: Add full SPL support for sun9i (A80)
Hi Chen-Yu, On 28-10-16 12:21, Chen-Yu Tsai wrote: Hi everyone, This series adds full SPL with DRAM initialization for sun9i (A80). The bulk of the work was done by the people at Theobroma Systems. Their work can be found here: https://git.theobroma-systems.com/armadillo-u-boot.git/ I picked the essential patches and cleaned them up a bit more, and added commit messages if they were missing. As the DRAM bits are essentially a code dump with some cleanups and some bits disabled, expect many warnings. Checkpatch is still not happy with it. I've tested the series on both my A80 boards, which I've added defconfigs for in the last 2 patches. My A80 Optimus does not boot from micro SD, so I'm still FEL booting that one. But my Cubieboard 4 is now standalone. As usual, please have a look, test if possible. Awesome, thanks for doing this and it was good to have some face2face time at ELCE. I've merged this into my personal sunxi-wip u-boot branch, I've made 2 changes: 1) in : ¨sunxi: DRAM initialisation for sun9i" there are a lot of #if 0 #endif blocks, most of these document some features which we may want to enable in the future, but a few were just dead weight IMHO, so I've pruned a few 2) in : "sunxi: Add support for A80 Optimus board", we already have a configs/Merrii_A80_Optimus_defconfig, so I've made the patch update that instead of adding a new defconfig I have not tested this yet, I will do tomorrow, assuming it works for me too I will include it in my next pull-req (*) and try to get it included in the 2016.11 release, yes the merge window has closed, but the changes here are very isolated so I will try and see what Tom says :) Regards, Hans *) Which I hope to send out this weekend Regards ChenYu Chen-Yu Tsai (5): sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80) sunxi: Add support for SID e-fuses on sun9i sunxi: Add default zq value for sun9i (A80) sunxi: Add support for A80 Optimus board sunxi: Add support for Cubieboard4 Philipp Tomsich (6): sunxi: DRAM initialisation for sun9i sunxi: add gtbus-initialisation for sun9i sunxi: Enable SMP mode for the boot CPU on sun9i (A80) sunxi: add initial clock setup for sun9i for SPL sunxi: enable SPL for sun9i sunxi: add MMC pinmux setup for SDC2 on sun9i arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 116 ++- arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 10 + arch/arm/include/asm/arch-sunxi/dram.h|2 + arch/arm/include/asm/arch-sunxi/dram_sun9i.h | 275 +++ arch/arm/include/asm/arch-sunxi/gtbus.h | 21 + arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h | 89 +++ arch/arm/mach-sunxi/Makefile |2 + arch/arm/mach-sunxi/board.c |3 +- arch/arm/mach-sunxi/clock.c |6 + arch/arm/mach-sunxi/clock_sun9i.c | 146 +++- arch/arm/mach-sunxi/dram_sun9i.c | 1059 + arch/arm/mach-sunxi/gtbus_sun9i.c | 48 ++ board/sunxi/Kconfig | 10 +- board/sunxi/MAINTAINERS | 10 + board/sunxi/board.c |7 + configs/A80_Optimus_defconfig | 18 + configs/Cubieboard4_defconfig | 18 + 17 files changed, 1818 insertions(+), 22 deletions(-) create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c create mode 100644 configs/A80_Optimus_defconfig create mode 100644 configs/Cubieboard4_defconfig ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/5] sf: Add support for status register protect
On Fri, Oct 28, 2016 at 10:36 PM, George McCollister wrote: > On Mon, Oct 10, 2016 at 1:57 PM, George McCollister > wrote: >> Many SPI NOR flash devices support status register protection through >> one or two status register protection bits. Protection of the status >> register is essential in defending the device from rogue software which >> may attempt to modify block protection bits in order to make malicious >> modifications to the data stored in flash. This patch series adds >> status register protect support for STMICRO, SST, Winbond and Spansion >> devices and also implements an sf sub-command to set the used >> protection method. >> >> George McCollister (5): >> sf: Add status register protection mechanism >> sf: Add status register protect for STMICRO, SST >> sf: Use stm_lock/unlock for Spansion and Winbond >> sf: Add status register protect for Winbond >> sf: Add sr-protect sub-command >> >> cmd/sf.c | 28 >> drivers/mtd/spi/sf_internal.h | 2 + >> drivers/mtd/spi/spi_flash.c | 103 >> +- >> include/spi_flash.h | 17 +++ >> 4 files changed, 149 insertions(+), 1 deletion(-) >> >> -- >> 2.9.3 >> > > Jagan, > > I think get_maintainer.pl may have given me an old email address for > you and you may have missed it on the mailing list. Either way if you > get a chance I'd like hear what you think. I'm not sure which > tree/branch you're working with (u-boot-spi > master?) but if you need it rebased just let me know. But this still active. about the patches please wait for some time will get back to you. thanks! -- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] imx: mx6: ddr: add register MPZQLP2CTL for LPDDR2
Add constants for the MPZQLP2CTL DDR register for both banks to allow setting the LPDDR2 timing values in .cfg files using a named constant instead of hex addresses as is currently done in mx6slevk and other board files. Signed-off-by: Eric Nelson --- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 9922409..53eb5fa 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -495,6 +495,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840 #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848 #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850 +#define MX6_MMDC_P0_MPZQLP2CTL 0x021b085C #define MX6_MMDC_P0_MPMUR0 0x021b08b8 #define MX6_MMDC_P1_MDCTL 0x021b4000 @@ -522,6 +523,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840 #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848 #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850 +#define MX6_MMDC_P1_MPZQLP2CTL 0x021b485C #define MX6_MMDC_P1_MPMUR0 0x021b48b8 #endif /*__ASM_ARCH_MX6_DDR_H__ */ -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/5] sf: Add support for status register protect
On Mon, Oct 10, 2016 at 1:57 PM, George McCollister wrote: > Many SPI NOR flash devices support status register protection through > one or two status register protection bits. Protection of the status > register is essential in defending the device from rogue software which > may attempt to modify block protection bits in order to make malicious > modifications to the data stored in flash. This patch series adds > status register protect support for STMICRO, SST, Winbond and Spansion > devices and also implements an sf sub-command to set the used > protection method. > > George McCollister (5): > sf: Add status register protection mechanism > sf: Add status register protect for STMICRO, SST > sf: Use stm_lock/unlock for Spansion and Winbond > sf: Add status register protect for Winbond > sf: Add sr-protect sub-command > > cmd/sf.c | 28 > drivers/mtd/spi/sf_internal.h | 2 + > drivers/mtd/spi/spi_flash.c | 103 > +- > include/spi_flash.h | 17 +++ > 4 files changed, 149 insertions(+), 1 deletion(-) > > -- > 2.9.3 > Jagan, I think get_maintainer.pl may have given me an old email address for you and you may have missed it on the mailing list. Either way if you get a chance I'd like hear what you think. I'm not sure which tree/branch you're working with (u-boot-spi master?) but if you need it rebased just let me know. Thanks, George ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PULL] u-boot-atmel/master -> u-boot/master
Hi Tom, please pull the following changes into u-boot/master for 2016.11. One of the patches introduce a build warning (-Wunused-function) which is removed with the following patch. This is due to introducing the new feature, then switch to the feature and remove the old code in a two step procedure. Therefore I think this is Ok. Andreas The following changes since commit 5ac5861c4ba851b473e6a24940b412b397627d8d: travis-ci: Add test.py for various qemu platforms (2016-10-24 08:06:29 -0400) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to 0eafd4b77615efdd948e698d83be746dcf026a53: dm: at91: Add driver model support for the spi driver (2016-10-28 18:37:15 +0200) Heiko Schocher (3): arm: at91: mpddrc: add missing MPDDRC_MD defines ARM: at91: clock: correct PRES offset for at91sam9x5 arm, at91: add icache support Robert P. J. Day (1): AT91: Correct misspelling of "redundent" in partition names Wenyou Yang (16): clk: at91: Fix at91-pmc and at91-sckc's class ID ARM: at91/dt: sama5d2: Fix the warning from dtc clk: clk-uclass: Assign clk->dev before call .of_xlate clk: at91: Improve the clock implementation gpio: atmel_pio4: Remove unnecessary clock calling i2c: at91_i2c: Remove unnecessary clock calling i2c: at91_i2c: Change error return -ENODEV to -EINVAL usb: ehci-atmel: Remove unnecessary clock calling mmc: atmel_sdhci: Remove unnecessary clock calling serial: Kconfig: Add ATMEL_USART option serial: atmel_usart: Support enable an early debug UART board: sama5d2_xplained: Move config options to defconfigs board: sama5d2_xplained: Clean up code board: sama5d2_xplained: Set 'ethaddr' got from AT24MAC board: sama5d2_xplained: Enable an early debug UART dm: at91: Add driver model support for the spi driver arch/arm/dts/sama5d2.dtsi | 140 ++-- arch/arm/mach-at91/arm926ejs/Makefile | 1 + arch/arm/mach-at91/arm926ejs/cache.c| 29 +++ arch/arm/mach-at91/arm926ejs/clock.c| 6 + arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 3 + board/atmel/sama5d2_xplained/sama5d2_xplained.c | 167 ++ board/bluewater/gurnard/gurnard.c | 6 - configs/sama5d2_xplained_mmc_defconfig | 37 ++- configs/sama5d2_xplained_spiflash_defconfig | 37 ++- drivers/clk/at91/Kconfig| 1 + drivers/clk/at91/clk-generated.c| 87 --- drivers/clk/at91/clk-peripheral.c | 72 -- drivers/clk/at91/clk-system.c | 57 +++-- drivers/clk/at91/pmc.c | 72 -- drivers/clk/at91/pmc.h | 5 +- drivers/clk/at91/sckc.c | 17 +- drivers/clk/clk-uclass.c| 3 + drivers/gpio/atmel_pio4.c | 12 - drivers/i2c/at91_i2c.c | 18 +- drivers/mmc/atmel_sdhci.c | 27 +-- drivers/serial/Kconfig | 14 ++ drivers/serial/atmel_usart.c| 22 ++ drivers/spi/Kconfig | 8 + drivers/spi/atmel_spi.c | 288 drivers/usb/host/ehci-atmel.c | 15 -- include/configs/at91-sama5_common.h | 2 +- include/configs/at91sam9rlek.h | 2 +- include/configs/sama5d2_xplained.h | 31 +-- 28 files changed, 795 insertions(+), 384 deletions(-) create mode 100644 arch/arm/mach-at91/arm926ejs/cache.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 3/4] board: sama5d2_xplained: Set 'ethaddr' got from AT24MAC
Dear Wenyou Yang, Wenyou Yang writes: >If 'ethaddr' is not set, we will get the ethernet address from AT24MAC, >and set it to 'ethaddr' variable. > >Signed-off-by: Wenyou Yang >Signed-off-by: Songjun Wu >Reviewed-by: Andreas Bießmann >--- > >Changes in v3: > - Collect Reviewed-by tag. > - Rename CONFIG_AT24MAC_ADDR and CONFIG_AT24MAC_REG to AT24MAC_ADDR > and AT24MAC_REG, removing the prefix CONFIG_, to avoid compile > warning. > >Changes in v2: None > > board/atmel/sama5d2_xplained/sama5d2_xplained.c | 51 + > include/configs/sama5d2_xplained.h | 6 +++ > 2 files changed, 57 insertions(+) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 4/4] board: sama5d2_xplained: Enable an early debug UART
Dear Wenyou Yang, Wenyou Yang writes: >Enable an early debug UART to debug problems when an ICE or other >debug mechanism is not available. > >Signed-off-by: Wenyou Yang >Reviewed-by: Simon Glass >Reviewed-by: Andreas Bießmann >--- > >Changes in v3: > - Collect Reviewed-by tag. > >Changes in v2: > - Collect Reviewed-by tags. > > board/atmel/sama5d2_xplained/sama5d2_xplained.c | 14 ++ > configs/sama5d2_xplained_mmc_defconfig | 6 ++ > configs/sama5d2_xplained_spiflash_defconfig | 6 ++ > include/configs/sama5d2_xplained.h | 2 ++ > 4 files changed, 28 insertions(+) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 2/4] board: sama5d2_xplained: Clean up code
Dear Wenyou Yang, Wenyou Yang writes: >Since the introduction of pinctrl and clk driver, and the dts file, >remove unneeded the pin configurations and the clock enabling code. > >Signed-off-by: Wenyou Yang >Reviewed-by: Simon Glass >Reviewed-by: Andreas Bießmann >--- > >Changes in v3: > - Collect Reviewed-by tag. > >Changes in v2: None > > board/atmel/sama5d2_xplained/sama5d2_xplained.c | 104 > 1 file changed, 104 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 1/4] board: sama5d2_xplained: Move config options to defconfigs
Dear Wenyou Yang, Wenyou Yang writes: >Move the config options from the include/configs/sama5d2_xplained.h >to configs/sama5d2_xplained_*_defconfig. > >Signed-off-by: Wenyou Yang >Reviewed-by: Andreas Bießmann >--- > >Changes in v3: > - Collect Reviewed-by tag. > >Changes in v2: None > > board/atmel/sama5d2_xplained/sama5d2_xplained.c | 2 ++ > configs/sama5d2_xplained_mmc_defconfig | 31 - > configs/sama5d2_xplained_spiflash_defconfig | 31 - > include/configs/sama5d2_xplained.h | 25 > 4 files changed, 62 insertions(+), 27 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 7/7] mmc: atmel_sdhci: Remove unnecessary clock calling
Dear Wenyou Yang, Wenyou Yang writes: >Due to the peripheral and generated clock driver improvement, >remove the unnecessary clock calling. > >Signed-off-by: Wenyou Yang >Reviewed-by: Jaehoon Chung >--- > >Changes in v3: > - Fix typo, unneccessary -> unnecessary. > - Add Reviewed-by tag. > >Changes in v2: None > > drivers/mmc/atmel_sdhci.c | 27 ++- > 1 file changed, 2 insertions(+), 25 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 2/2] serial: atmel_usart: Support enable an early debug UART
Dear Wenyou Yang, Wenyou Yang writes: >Add support to enable an early debug UART for debugging. > >Signed-off-by: Wenyou Yang >Reviewed-by: Simon Glass >Reviewed-by: Andreas Bießmann >--- > >Changes in v3: > - Collect Reviewed-by tag. > >Changes in v2: > - Collect Reviewed-by tag. > > drivers/serial/Kconfig | 7 +++ > drivers/serial/atmel_usart.c | 22 ++ > 2 files changed, 29 insertions(+) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 1/2] serial: Kconfig: Add ATMEL_USART option
Dear Wenyou Yang, Wenyou Yang writes: >Add ATMEL_USART option to support to enable the Atmel usart driver >from Kconfig. > >Signed-off-by: Wenyou Yang >Reviewed-by: Andreas Bießmann >--- > >Changes in v3: > - Collect Reviewed-by tag. > >Changes in v2: None > > drivers/serial/Kconfig | 7 +++ > 1 file changed, 7 insertions(+) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v11] dm: at91: Add driver model support for the spi driver
Dear Wenyou Yang,
Wenyou Yang writes:
>Add driver model support while retaining the existing legacy code.
>This allows the driver to support boards that have converted to
>driver model as well as those that have not.
>
>Signed-off-by: Wenyou Yang
>Reviewed-by: Simon Glass
>Acked-by: Stephen Warren
>---
>
>Changes in v11:
> - Set cs_gpio direction to output and active.
> - Use wait_for_bit() to replace do {} while ().
> - Add more description for help of ATMEL_SPI.
>
>Changes in v10:
> - Add Acked-by tag.
>
>Changes in v9:
> - Due to the peripheral clock driver improvement, remove the
> unneccessary clock calling.
>
>Changes in v8:
> - Fix compile error for AVR32.
>
>Changes in v7:
> - Move gpio_request_list_by_name() to _probe(), remove
> *_ofdata_to_platdata().
>
>Changes in v6:
> - Remove the two flash related options.
>
>Changes in v5:
> - Change clk_client.h -> clk.h to adapt to clk API conversion.
>
>Changes in v4:
> - Collect Reviewed-by tag.
> - Update the clk API based on [PATCH] clk: convert API to match
> reset/mailbox fstyle (http://patchwork.ozlabs.org/patch/625342/).
> - Remove check on dev_get_parent() return.
> - Fixed the return value, -ENODEV->-EINVAL.
> - Retain #include line.
>
>Changes in v3:
> - Remove redundant log print.
>
>Changes in v2:
> - Add clock support.
>
> drivers/spi/Kconfig | 8 ++
> drivers/spi/atmel_spi.c | 288
> 2 files changed, 296 insertions(+)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bießmann
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Re: [U-Boot] [U-Boot, v3, 3/7] gpio: atmel_pio4: Remove unnecessary clock calling
Dear Wenyou Yang, Wenyou Yang writes: >Due to the peripheral clock driver improvement, remove the >unnecessary clock calling. > >Signed-off-by: Wenyou Yang >Acked-by: Stephen Warren >--- > >Changes in v3: None >Changes in v2: > - Add Acked-by tag for gpio/atmel_pio4. > > drivers/gpio/atmel_pio4.c | 12 > 1 file changed, 12 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 6/7] usb: ehci-atmel: Remove unnecessary clock calling
Dear Wenyou Yang, Wenyou Yang writes: >Due to the peripheral clock driver improvement, remove the >unnecessary clock calling. > >Signed-off-by: Wenyou Yang >Reviewed-by: Andreas Bießmann >--- > >Changes in v3: None >Changes in v2: None > > drivers/usb/host/ehci-atmel.c | 15 --- > 1 file changed, 15 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 1/7] clk: clk-uclass: Assign clk->dev before call .of_xlate
Dear Wenyou Yang, Wenyou Yang writes: >In order to make clk->dev available in ops->of_xlate() to get the >clock ID from the 'reg' property of the clock node, assign the >clk->dev before calling ops->of_xlate(). > >Signed-off-by: Wenyou Yang >Acked-by: Stephen Warren >Acked-by: Simon Glass >--- > >Changes in v3: None >Changes in v2: > - Add Acked-by tag. > > drivers/clk/clk-uclass.c | 3 +++ > 1 file changed, 3 insertions(+) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1] ARM: at91/dt: sama5d2: Fix the warning from dtc
Dear Wenyou Yang, Wenyou Yang writes: >Fix the warning from dtc like, >---8< >Warning (unit_address_vs_reg): Node >/ahb/apb/pmc@f0014000/periph64ck/sdmmc0_hclk has a reg or ranges property, but >no unit name >--->8 > >Signed-off-by: Wenyou Yang >Acked-by: Stephen Warren >--- > > arch/arm/dts/sama5d2.dtsi | 140 +++--- > 1 file changed, 70 insertions(+), 70 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 4/7] i2c: at91_i2c: Remove unnecessary clock calling
Dear Wenyou Yang, Wenyou Yang writes: >Due to the peripheral clock driver improvement, remove the >unnecessary clock calling. > >Signed-off-by: Wenyou Yang >Reviewed-by: Heiko Schocher >--- > >Changes in v3: None >Changes in v2: None > > drivers/i2c/at91_i2c.c | 16 > 1 file changed, 16 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 5/7] i2c: at91_i2c: Change error return -ENODEV to -EINVAL
Dear Wenyou Yang, Wenyou Yang writes: >Change the error return value -ENODEV from to -EINVAL for more >reasonable. > >Signed-off-by: Wenyou Yang >Reviewed-by: Heiko Schocher >--- > >Changes in v3: None >Changes in v2: None > > drivers/i2c/at91_i2c.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 2/7] clk: at91: Improve the clock implementation
Dear Wenyou Yang, Wenyou Yang writes: >For the peripheral clock, provide the clock ops for the clock >provider, such as spi0_clk. The .of_xlate is to get the clk->id, >the .enable is to enable the spi0 peripheral clock, the .get_rate >is to get the clock frequency. > >The driver for periph32ck node is responsible for recursively >binding its children as clk devices, not provide the clock ops. > >So do the generated clock and system clock. > >Signed-off-by: Wenyou Yang >Acked-by: Stephen Warren >--- > >Changes in v3: > - Remove the unneeded wrapper functions. > - Fix typo, Invaild -> Invalid. > - Add Acked-by tag. > >Changes in v2: > - For the periph32ck, periph64ck, gck, systemck nodes, they aren't > the clock providers, are to house various actual clock providers, > use UCLASS_MISC, instead of UCLASS_CLK. > - For *_of_xlate(), add argument check. > - Fix the implementation of the *_get_rate(). > - Use documentation-wise variables for *_clk_probe(). > - Remove the duplicated code, use the common functions. > > drivers/clk/at91/Kconfig | 1 + > drivers/clk/at91/clk-generated.c | 87 +++ > drivers/clk/at91/clk-peripheral.c | 72 ++-- > drivers/clk/at91/clk-system.c | 57 ++--- > drivers/clk/at91/pmc.c| 62 > drivers/clk/at91/pmc.h| 5 ++- > 6 files changed, 195 insertions(+), 89 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,3/6] arm, at91: add icache support
Dear Heiko Schocher, Heiko Schocher writes: >add at least icache support for at91 based boards. >This speeds up NOR flash access on an at91sam9g15 >based board from 15.2 seconds reading 8 MiB from >a SPI NOR flash to 5.7 seconds. > >Signed-off-by: Heiko Schocher >Reviewed-by: Simon Glass >Reviewed-by: Andreas Bießmann >--- >removed the dcache enable in the gurnard board. Comment >says that enabling dcache breaks Ethernet MAC ... why >is it then enabled? > >@Simon: If you need dache enabled for the gurnard board, >arch/arm/mach-at91/arm926ejs/cache.c is the correct place >for doing this, I think. Please add there the common functions >needed for dcache support on at91 plattforms and undef in >the gurnard board configuration CONFIG_SYS_DCACHE_OFF. > > arch/arm/mach-at91/arm926ejs/Makefile | 1 + > arch/arm/mach-at91/arm926ejs/cache.c | 29 + > board/bluewater/gurnard/gurnard.c | 6 -- > 3 files changed, 30 insertions(+), 6 deletions(-) > create mode 100644 arch/arm/mach-at91/arm926ejs/cache.c applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] AT91: Correct misspelling of "redundent" in partition names
Dear "Robert P. J. Day", Robert P. J. Day writes: >Signed-off-by: Robert P. J. Day >Reviewed-by: Andreas Bießmann >--- > > given that this misspelling is being used for partition names, i >won't treat it as a normal typo, so sending a separate patch just for >this. applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/6] ARM: at91: clock: correct PRES offset for at91sam9x5
Dear Heiko Schocher, Heiko Schocher writes: >on at91sam9x5 PRES offset is 4 in the PMC master >clock register. > >Signed-off-by: Heiko Schocher >Acked-by: Wenyou Yang >Acked-by: Andreas Bießmann >--- > > arch/arm/mach-at91/arm926ejs/clock.c | 6 ++ > 1 file changed, 6 insertions(+) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] clk: at91: Fix at91-pmc and at91-sckc's class ID
Dear Wenyou Yang, Wenyou Yang writes: >The at91-pmc and at91-sckc aren't the clock providers, change their >class ID from UCLASS_CLK to UCLASS_SIMPLE_BUS, they also don't >need to bind the child nodes explicitly, the .post_bind callback >of simple_bus uclass will do it for them. > >Signed-off-by: Wenyou Yang >Acked-by: Stephen Warren >Reviewed-by: Simon Glass >--- > >Changes in v2: > - Collect the tags. > > drivers/clk/at91/pmc.c | 10 ++ > drivers/clk/at91/sckc.c | 17 + > 2 files changed, 7 insertions(+), 20 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/6] arm: at91: mpddrc: add missing MPDDRC_MD defines
Dear Heiko Schocher, Heiko Schocher writes: >add missing MPDDRC_MD defines > >Signed-off-by: Heiko Schocher >Acked-by: Wenyou Yang >Reviewed-by: Andreas Bießmann >--- > > arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 3 +++ > 1 file changed, 3 insertions(+) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/13] imx: mx6sl: ddr: add IOM_GRP registers
Add IOM_GRP register definitions for i.MX6SL to allow them to be named in DDR configuration (.cfg) files. Signed-off-by: Eric Nelson --- arch/arm/include/asm/arch-mx6/mx6sl-ddr.h | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h index c3c4d69..98a259e 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h @@ -42,4 +42,17 @@ #define MX6_IOM_DRAM_SDWE_B0x020e0354 +#define MX6_IOM_GRP_ADDDS 0x020e05ac +#define MX6_IOM_GRP_DDRMODE_CTL0x020e05b0 +#define MX6_IOM_GRP_DDRPKE 0x020e05b4 +#define MX6_IOM_GRP_DDRPK 0x020e05b8 +#define MX6_IOM_GRP_DDRHYS 0x020e05bc +#define MX6_IOM_GRP_DDRMODE0x020e05c0 +#define MX6_IOM_GRP_B0DS 0x020e05c4 +#define MX6_IOM_GRP_CTLDS 0x020e05c8 +#define MX6_IOM_GRP_B1DS 0x020e05cc +#define MX6_IOM_GRP_DDR_TYPE 0x020e05d0 +#define MX6_IOM_GRP_B2DS 0x020e05d4 +#define MX6_IOM_GRP_B3DS 0x020e05d8 + #endif /*__ASM_ARCH_MX6SL_DDR_H__ */ -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] FSL PowerPC platform: Not able to boot Linux with ramdisk size > 100MB
2016-10-29 0:32 GMT+09:00 york sun : > On 10/27/2016 10:11 PM, Scott Wood wrote: >> On 10/27/2016 04:27 AM, Prabhakar Kushwaha wrote: >>> Hi Masahiro, >>> >>> I am not able to boot Linux onF PowerPC platform with ramdisk size > 100MB. >>> I tried u-boot master with top commit as " >>> 5ac5861c4ba851b473e6a24940b412b397627d8d ". >>> >>> I tried git-bisect and figured out below patch causing this problem. If I >>> revert this patch, Linux boots properly. >>> >>> commit 20e072f37402c17741f67d9693eaabdd835b80f2 >>> Author: Masahiro Yamada >>> Date: Thu Dec 17 17:19:35 2015 +0900 >>> >>> image: check "bootm_low" and "bootm_size" if "initrd_high" is missing >>> >>> To boot Linux, we should prevent Initramdisk and FDT from going too >>> high. >>> >>> Currently, boot_relocate_fdt() checks "fdt_high" environment first, >>> and then falls back to getenv_bootm_mapsize() + getenv_bootm_low() >>> if "fdt_high" is missing. >>> >>> On the other hand, boot_ramdisk_high() only checks "initrd_high" to >>> get the address limit for the Initramdisk. We also want to let this >>> case fall back to getenv_bootm_mapsize() + getenv_bootm_low(). >>> >>> Signed-off-by: Masahiro Yamada >>> >>> Please advise!! >> >> On PPC the initrd does not need to be loaded within the boot mapping. >> This assumption of what the absence of initrd_high means is not >> universally appropriate. Why not just set initrd_high on the platforms >> that need it? >> > > Masahiro, > > If I read Scott correctly, he suggests to revert this patch and have the > those platforms who need to set initrd_high to do so. I wonder how many > of them exist. It makes sense to not restrict the loading if initrd_high > is not set. > > York I think this part is completely messed up. Every developer (including me) expands or hacks it for his purpose without deep insight. I do not know why U-Boot relocates initrd and fdt to the tail of memory region. I want somebody to re-design it. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node
On 10/27/2016 02:06 AM, Wenbin song wrote:
> The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
> and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose
> which offset will be used. If GIC_ADDR_BIT bit is set, 4K alignment is used,
> or else 64K alignment is used. The rev1.0 silicon only supports the CIG offset
> with 4K alignment.
>
> GIC offset is decided by SVR and GIC_ADDR_BIT bit.
>
> Overriding the weak smp_kick_all_cpus, the new impletment is able to detect
> GIC offset.
>
> Signed-off-by: Wenbin Song
> Signed-off-by: Mingkai Hu
> ---
> Changes in v5:
> Replace fix_gic_off with get_gic_off.
> Add #if condition to check CONFIG_GICV2 and CONFIG_GICV3 on
> smp_kick_all_cpus.
> Fixup gic node with 64K alignment when running on rev1.1 with
> GIC_ADDR_BIT cleared.
> ---
>
> +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
> +static void fdt_fixup_gic(void *blob)
> +{
> + int offset, err;
> + u64 reg[8];
> + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> + unsigned int rev;
> + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
> + int align_4k = 1;
> +
> + rev = gur_in32(&gur->svr) & 0xff;
> +
> + if (rev > REV1_0) {
> + rev = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
> + if (!rev)
> + align_4k = 0;
> + }
> +
Does this register scfg->gic_align exist for other SoCs? Can you get a
consistent reading from this register if not set by PBI? If yes, can you
revert the logic in PBI command to set this bit in backward compatible way?
York
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[U-Boot] [PATCH v4] efi_loader: console: Correctly report modes
Add support for EFI console modes.
Mode 0 is always 80x25 and present by EFI specification.
Mode 1 is always 80x50 and not mandatory.
Mode 2 and above is freely usable.
If the terminal can handle mode 1, we mark it as supported.
If the terminal size is greater than mode 0 and different than mode 1,
we install it as mode 2.
Modes can be switch with cout_set_mode.
Changes in V4:
Reset cursor positon on mode switch
Use local variables in console query code
Changes in V3:
Valid mode are 0 to EFIMode-1
Fix style
Changes in V2:
Add mode switch
Report only the modes that we support
Signed-off-by: Emmanuel Vadot
---
lib/efi_loader/efi_console.c | 90
1 file changed, 74 insertions(+), 16 deletions(-)
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index 2e0228c..c22eb3e 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -9,11 +9,38 @@
#include
#include
-/* If we can't determine the console size, default to 80x24 */
-static int console_columns = 80;
-static int console_rows = 24;
static bool console_size_queried;
+#define EFI_COUT_MODE_2 2
+#define EFI_MAX_COUT_MODE 3
+
+struct cout_mode {
+ unsigned long columns;
+ unsigned long rows;
+ int present;
+};
+
+static struct cout_mode efi_cout_modes[] = {
+ /* EFI Mode 0 is 80x25 and always present */
+ {
+ .columns = 80,
+ .rows = 25,
+ .present = 1,
+ },
+ /* EFI Mode 1 is always 80x50 */
+ {
+ .columns = 80,
+ .rows = 50,
+ .present = 0,
+ },
+ /* Value are unknown until we query the console */
+ {
+ .columns = 0,
+ .rows = 0,
+ .present = 0,
+ },
+};
+
const efi_guid_t efi_guid_console_control = CONSOLE_CONTROL_GUID;
#define cESC '\x1b'
@@ -56,8 +83,9 @@ const struct efi_console_control_protocol efi_console_control
= {
.lock_std_in = efi_cin_lock_std_in,
};
+/* Default to mode 0 */
static struct simple_text_output_mode efi_con_mode = {
- .max_mode = 0,
+ .max_mode = 1,
.mode = 0,
.attribute = 0,
.cursor_column = 0,
@@ -131,8 +159,10 @@ static efi_status_t EFIAPI efi_cout_output_string(
struct efi_simple_text_output_protocol *this,
const unsigned short *string)
{
+ struct cout_mode *mode;
u16 ch;
+ mode = &efi_cout_modes[efi_con_mode.mode];
EFI_ENTRY("%p, %p", this, string);
for (;(ch = *string); string++) {
print_unicode_in_utf8(ch);
@@ -140,13 +170,12 @@ static efi_status_t EFIAPI efi_cout_output_string(
if (ch == '\n') {
efi_con_mode.cursor_column = 1;
efi_con_mode.cursor_row++;
- } else if (efi_con_mode.cursor_column > console_columns) {
+ } else if (efi_con_mode.cursor_column > mode->columns) {
efi_con_mode.cursor_column = 1;
efi_con_mode.cursor_row++;
}
- if (efi_con_mode.cursor_row > console_rows) {
- efi_con_mode.cursor_row = console_rows;
- }
+ if (efi_con_mode.cursor_row > mode->rows)
+ efi_con_mode.cursor_row = mode->rows;
}
return EFI_EXIT(EFI_SUCCESS);
@@ -170,6 +199,8 @@ static efi_status_t EFIAPI efi_cout_query_mode(
if (!console_size_queried) {
/* Ask the terminal about its size */
int n[3];
+ int cols;
+ int rows;
u64 timeout;
console_size_queried = true;
@@ -191,15 +222,38 @@ static efi_status_t EFIAPI efi_cout_query_mode(
goto out;
}
- console_columns = n[2];
- console_rows = n[1];
+ cols = n[2];
+ rows = n[1];
+ /* Test if we can have Mode 1 */
+ if (cols >= 80 && rows >= 50) {
+ efi_cout_modes[1].present = 1;
+ efi_con_mode.max_mode = 2;
+ }
+
+ /*
+* Install our mode as mode 2 if it is different
+* than mode 0 or 1 and set it as the currently selected mode
+*/
+ if ((cols != 80 && rows != 25) || (cols != 80 && rows != 50)) {
+ efi_cout_modes[EFI_COUT_MODE_2].columns = cols;
+ efi_cout_modes[EFI_COUT_MODE_2].rows = rows;
+ efi_cout_modes[EFI_COUT_MODE_2].present = 1;
+ efi_con_mode.max_mode = EFI_MAX_COUT_MODE;
+ efi_con_mode.mode = EFI_COUT_MODE_2;
+ }
}
+ if (mode_number >= efi_con_mode.max_mode)
+ return EFI_EXIT(
Re: [U-Boot] FSL PowerPC platform: Not able to boot Linux with ramdisk size > 100MB
On 10/27/2016 10:11 PM, Scott Wood wrote: > On 10/27/2016 04:27 AM, Prabhakar Kushwaha wrote: >> Hi Masahiro, >> >> I am not able to boot Linux onF PowerPC platform with ramdisk size > 100MB. >> I tried u-boot master with top commit as " >> 5ac5861c4ba851b473e6a24940b412b397627d8d ". >> >> I tried git-bisect and figured out below patch causing this problem. If I >> revert this patch, Linux boots properly. >> >> commit 20e072f37402c17741f67d9693eaabdd835b80f2 >> Author: Masahiro Yamada >> Date: Thu Dec 17 17:19:35 2015 +0900 >> >> image: check "bootm_low" and "bootm_size" if "initrd_high" is missing >> >> To boot Linux, we should prevent Initramdisk and FDT from going too >> high. >> >> Currently, boot_relocate_fdt() checks "fdt_high" environment first, >> and then falls back to getenv_bootm_mapsize() + getenv_bootm_low() >> if "fdt_high" is missing. >> >> On the other hand, boot_ramdisk_high() only checks "initrd_high" to >> get the address limit for the Initramdisk. We also want to let this >> case fall back to getenv_bootm_mapsize() + getenv_bootm_low(). >> >> Signed-off-by: Masahiro Yamada >> >> Please advise!! > > On PPC the initrd does not need to be loaded within the boot mapping. > This assumption of what the absence of initrd_high means is not > universally appropriate. Why not just set initrd_high on the platforms > that need it? > Masahiro, If I read Scott correctly, he suggests to revert this patch and have the those platforms who need to set initrd_high to do so. I wonder how many of them exist. It makes sense to not restrict the loading if initrd_high is not set. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/8] dm: Update on serial driver progress
On Wed, 2016-10-26 at 16:30 +, Simon Glass wrote: > Hi, > > On 21 October 2016 at 01:10, Marek Vasut wrote: > > > > On 10/21/2016 08:52 AM, Marcel Ziswiler wrote: > > > > > > Hi Simon > > > > > > On Thu, 2016-10-20 at 13:06 -0600, Simon Glass wrote: > > > > > > > > Only three serial drivers remain to be converted. This series > > > > drops > > > > two of those, since the boards appear to be unmaintained. > > > > > > > > With this, only blackfin remains. > > > > > > > > The blackfin driver probably needs to be converted as there is > > > > recent > > > > activity with these boards. I am copying the maintainer so that > > > > this > > > > work can be completed. > > > Could you please hold off with dropping the PXA serial driver and > > > accompanying PXA270 support. I will have a look at it ASAP. We do > > > actually continue to sell the Colibri PXA270 (as we are the > > > Colibri > > > PXA320) and I have been maintaining it lately with sending > > > patches as > > > recently as last week! It would be rather sad to see it drop like > > > the > > > PXA3xx support did a couple years back when we were too busy with > > > other > > > issues. > OK we can hold off - when do you expect to do this? Thanks Simon, I'm looking into it right now. > Also re PXA3xx, please feel free to bring it back. If I recall it was > only removed long after the deadline for conversion. Yeah, I guess the only constant is change (;-p). > > > > > > > > > Cheers > > > > > > Marcel > > > > > > > > > > > Simon Glass (8): > > > > arm: Remove colibri_pxa270 board > > > > arm: Remove h2200 board > > > > arm: Remove zipitz2 board > > > > arm: Drop pxa serial driver > > Whoa, would be nice to keep me on Cc regarding PXA stuff. Thanks > > for > > CCing me, Marcel. And I would like to NAK these first four patches. > > > > > > > > > > > > > serial: Update docs to indicate mcfuart supports DM_SERIAL > > > > arm: Remove smdk2410 board > > > > arm: Remove VCMA9 board > > > > serial: Drop the s3c24x0 serial driver > > -- > > Best regards, > > Marek Vasut > Regards, > Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] drivers: usb: fsl-dt-fixup: Fix the dt for multiple USB nodes in single traversal of device tree
On Freitag, 28. Oktober 2016 01:52:26 CEST Marek Vasut wrote:
[...]
> > +
> > +enum fdt_fsl_usb_erratum {
> > + A006261,
> > + A007075,
> > + A007792,
> > + A005697,
> > + A008751,
> > + FSL_USB_ERRATUM_END
>
> The compiler can assign completely arbitrary numbers to the enum
> elements. Moreover, you don't need this "terminating entry" anyway, see
> below.
Not true. According to
http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1256.pdf
6.7.2.2 Enumeration specifiers
...
An enumerator with = defines its enumeration constant as the value of the
constant expression. If the first enumerator has no =, the value of its
enumeration constant is 0. Each subsequent enumerator with no = defines its
enumeration constant as the value of the constant expression obtained by
adding 1 to the value of the previous enumeration constant.
Kind regards,
Stefan
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[U-Boot] [PULL] Please pull u-boot-imx
Hi Tom, please pull from u-boot-imx, thanks ! There are two major patchsets in this PR: - plugin support from Peng - Jagan's support for Engicam i.CoreM6 , with several move to Kconfig. The following changes since commit ebf7fff20ab8127f318b238e47a21856497bd6fe: spl: move FDT_FIXUP_PARTITIONS to Kconfig (2016-10-15 08:12:46 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to 1c140f7bbf4a008fcd78b407ea80c60a2a18fc1f: imx6: icorem6: Add default mtd nand partition table (2016-10-26 19:00:06 +0200) Diego Dorta (2): mx6sabresd: Add Falcon mode support mx6sabresd: Add README file Gary Bisson (4): arm: imx-common: add SECURE_BOOT option to Kconfig mx6_common: add secure boot support mx7_common: add secure boot support nitrogen6x: add secure boot support Jagan Teki (21): serial: Kconfig: Add MXC_UART entry thermal: Kconfig: Add IMX_THERMAL entry config: Move CONFIG_DEFAULT_FDT_FILE to defconfigs arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support net: Kconfig: Add FEC_MXC entry imx6: icorem6: Add ENET support imx: s/docs\/README.imximage/doc\/README.imximage/g arm: dts: Add devicetree for i.MX6DL arm: dts: Add devicetree for i.MX6DQL arm: dts: imx6dl: Add pinctrl defines dt-bindings: clock: imx6qdl: Add clock defines arm: imx6q: Add devicetree support for Engicam i.CoreM6 DualLite/Solo imx6q: icorem6: Enable pinctrl driver engicam: icorem6: Add DM_GPIO, DM_MMC support arm: dts: Add devicetree for i.MX6Q arm: dts: imx6q: Add pinctrl defines arm: imx6q: Add devicetree support for Engicam i.CoreM6 Quad/Dual mtd: nand: Kconfig: Add NAND_MXS entry imx6: icorem6: Add NAND support imx6: icorem6: Enable MTD device support imx6: icorem6: Add default mtd nand partition table Peng Fan (9): arm: imx-common: introduce back usec2ticks tools: imximage: add plugin support imx: mx6: Add plugin support imx: mx7: Add plugin support imx-common: introduce USE_IMXIMG_PLUGIN Kconfig imx-common: compile plugin code imx: mx6ullevk: support plugin imx: mx6ullevk: correct boot device macro imx: mx6ull_14x14_evk: add plugin defconfig arch/arm/cpu/armv7/mx6/Kconfig | 11 ++ arch/arm/dts/Makefile |4 +- arch/arm/dts/imx6dl-icore.dts | 59 ++ arch/arm/dts/imx6dl-pinfunc.h | 1091 arch/arm/dts/imx6dl.dtsi| 133 + arch/arm/dts/imx6q-icore.dts| 59 ++ arch/arm/dts/imx6q-pinfunc.h| 1047 +++ arch/arm/dts/imx6q.dtsi | 300 + arch/arm/dts/imx6qdl-icore.dtsi | 196 +++ arch/arm/dts/imx6qdl.dtsi | 1281 ++ arch/arm/imx-common/Kconfig | 14 ++ arch/arm/imx-common/Makefile| 29 ++- arch/arm/imx-common/timer.c | 16 ++ arch/arm/include/asm/arch-mx6/mx6_plugin.S | 159 arch/arm/include/asm/arch-mx7/mx7_plugin.S | 111 +++ arch/arm/include/asm/imx-common/sys_proto.h |2 + board/barco/titanium/imximage.cfg |2 +- board/boundary/nitrogen6x/nitrogen6dl.cfg |3 + board/boundary/nitrogen6x/nitrogen6dl2g.cfg |3 + board/boundary/nitrogen6x/nitrogen6q.cfg|3 + board/boundary/nitrogen6x/nitrogen6q2g.cfg |3 + board/boundary/nitrogen6x/nitrogen6s.cfg|3 + board/boundary/nitrogen6x/nitrogen6s1g.cfg |3 + board/ccv/xpress/imximage.cfg |2 +- board/denx/m53evk/imximage.cfg |2 +- board/engicam/icorem6/Kconfig | 12 ++ board/engicam/icorem6/MAINTAINERS |6 + board/engicam/icorem6/Makefile |6 + board/engicam/icorem6/README| 38 board/engicam/icorem6/icorem6.c | 537 +++ board/freescale/mx6sabresd/README | 103 ++ board/freescale/mx6sabresd/mx6dlsabresd.cfg |2 +- board/freescale/mx6sabresd/mx6sabresd.c | 12 ++ board/freescale/mx6slevk/imximage.cfg |2 +- board/freescale/mx6ullevk/imximage.cfg |8 +- board/freescale/mx6ullevk/plugin.S | 139 ++ board/freescale/mx7dsabresd/imximage.cfg|2 +- board/freescale/s32v234evb/s32v234evb.cfg |2 +- board/freescale/vf610
Re: [U-Boot] u-boot on qemu vexpress-a9
Hello, On Thu, Oct 27, 2016 at 3:00 PM, Nicolae Rosia wrote: > [0] https://bugs.launchpad.net/qemu/+bug/1579327?comments=all Booting a Linux kernel with -smp 4 works just fine, so I believe the bug is in u-boot. Thanks, Nicolae ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] FSL PowerPC platform: Not able to boot Linux with ramdisk size > 100MB
Thanks Scott, > -Original Message- > From: Scott Wood > Sent: Friday, October 28, 2016 10:41 AM > To: Prabhakar Kushwaha ; u- > b...@lists.denx.de; yamada.masah...@socionext.com > Cc: york sun > Subject: Re: FSL PowerPC platform: Not able to boot Linux with ramdisk size > > 100MB > > On 10/27/2016 04:27 AM, Prabhakar Kushwaha wrote: > > Hi Masahiro, > > > > I am not able to boot Linux onF PowerPC platform with ramdisk size > 100MB. > > I tried u-boot master with top commit as " > 5ac5861c4ba851b473e6a24940b412b397627d8d ". > > > > I tried git-bisect and figured out below patch causing this problem. If I > > revert > this patch, Linux boots properly. > > > > commit 20e072f37402c17741f67d9693eaabdd835b80f2 > > Author: Masahiro Yamada > > Date: Thu Dec 17 17:19:35 2015 +0900 > > > > image: check "bootm_low" and "bootm_size" if "initrd_high" is missing > > > > To boot Linux, we should prevent Initramdisk and FDT from going too > > high. > > > > Currently, boot_relocate_fdt() checks "fdt_high" environment first, > > and then falls back to getenv_bootm_mapsize() + getenv_bootm_low() > > if "fdt_high" is missing. > > > > On the other hand, boot_ramdisk_high() only checks "initrd_high" to > > get the address limit for the Initramdisk. We also want to let this > > case fall back to getenv_bootm_mapsize() + getenv_bootm_low(). > > > > Signed-off-by: Masahiro Yamada > > > > Please advise!! > > On PPC the initrd does not need to be loaded within the boot mapping. > This assumption of what the absence of initrd_high means is not > universally appropriate. Why not just set initrd_high on the platforms > that need it? > After setting initrd_high=0x\0. Now linux is working with > 100M. --prabhakar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 21/23] imx6: icorem6: Add NAND support
On 28/10/2016 16:02, Jagan Teki wrote: > On Thu, Oct 27, 2016 at 7:37 PM, Stefano Babic wrote: >> On 26/10/2016 18:35, Jagan Teki wrote: >>> On Wed, Oct 26, 2016 at 8:38 PM, Stefano Babic wrote: Hi Jagan, On 25/10/2016 08:23, Jagan Teki wrote: > From: Jagan Teki > > Add NAND support for Engicam i.CoreM6 qdl board. > > Boot Log: > > > U-Boot SPL 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43) > Trying to boot from NAND > NAND : 512 MiB > > U-Boot 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43 +0530) > > CPU: Freescale i.MX6SOLO rev1.3 at 792MHz > CPU: Industrial temperature grade (-40C to 105C) at 55C > Reset cause: WDOG > Model: Engicam i.CoreM6 DualLite/Solo Starter Kit > DRAM: 256 MiB > NAND: 512 MiB > MMC: FSL_SDHC: 0 > In:serial > Out: serial > Err: serial > Net: FEC [PRIME] > Hit any key to stop autoboot: 0 > icorem6qdl> > > Cc: Scott Wood > Cc: Stefano Babic > Cc: Peng Fan > Cc: Matteo Lisi > Cc: Michael Trimarchi > Signed-off-by: Jagan Teki > --- > Changes for v9: > - Add below configs on defconfig > # CONFIG_BLK is not set > # CONFIG_DM_MMC_OPS is not set It was nice if it was set. But if you simply grep in this poathc, they are not. Just changelog was touched. But let's see what we can do to improve. I have merged patches up to 14 (without NAND support). I will push them to the server and they are part of my next PR. As I propose, I could fix this myself in this patch if you agree - or then please post the rest of patches, but after checking the board can be built. >>> >>> I am OK, please fix from you side and also please apply this [1] >>> series as well, all Acked-by Jeo >> >> All series applied to u-boot-imx, thanks ! > > Thanks. > >> >>> >>> [1] [PATCH v7 0/5] net: fec_mxc: Convert to DM >> >> This is the next... > > OK, that means the coming release right? yes, I see there is already a lot of new patches in u-boot-imx - I'll send my PR to Tom, and afterwards I start to check the pending patches. Regards, Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 21/23] imx6: icorem6: Add NAND support
On Thu, Oct 27, 2016 at 7:37 PM, Stefano Babic wrote: > On 26/10/2016 18:35, Jagan Teki wrote: >> On Wed, Oct 26, 2016 at 8:38 PM, Stefano Babic wrote: >>> Hi Jagan, >>> >>> >>> On 25/10/2016 08:23, Jagan Teki wrote: From: Jagan Teki Add NAND support for Engicam i.CoreM6 qdl board. Boot Log: U-Boot SPL 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43) Trying to boot from NAND NAND : 512 MiB U-Boot 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43 +0530) CPU: Freescale i.MX6SOLO rev1.3 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 55C Reset cause: WDOG Model: Engicam i.CoreM6 DualLite/Solo Starter Kit DRAM: 256 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In:serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 icorem6qdl> Cc: Scott Wood Cc: Stefano Babic Cc: Peng Fan Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- Changes for v9: - Add below configs on defconfig # CONFIG_BLK is not set # CONFIG_DM_MMC_OPS is not set >>> >>> It was nice if it was set. But if you simply grep in this poathc, they >>> are not. Just changelog was touched. >>> >>> But let's see what we can do to improve. I have merged patches up to 14 >>> (without NAND support). I will push them to the server and they are part >>> of my next PR. >>> >>> As I propose, I could fix this myself in this patch if you agree - or >>> then please post the rest of patches, but after checking the board can >>> be built. >> >> I am OK, please fix from you side and also please apply this [1] >> series as well, all Acked-by Jeo > > All series applied to u-boot-imx, thanks ! Thanks. > >> >> [1] [PATCH v7 0/5] net: fec_mxc: Convert to DM > > This is the next... OK, that means the coming release right? thanks! -- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 7/7] imx6: icorem6: Add I2C support
From: Jagan Teki Add I2C support for Engicam i.CoreM6 qdl board. icorem6qdl> i2c bus Bus 0: i2c@021a Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 icorem6qdl> i2c dev 2 Setting bus to 2 icorem6qdl> i2c speed 10 Setting bus speed to 10 Hz icorem6qdl> i2c probe Valid chip addresses: 2C icorem6qdl> i2c md 2C 0xff 00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00...d Cc: Stefano Babic Cc: Heiko Schocher Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- arch/arm/cpu/armv7/mx6/Kconfig | 1 + configs/imx6qdl_icore_mmc_defconfig | 3 ++- configs/imx6qdl_icore_nand_defconfig | 3 ++- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 8456b0e..c04536c 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -102,6 +102,7 @@ config TARGET_MX6Q_ICORE select DM select DM_ETH select DM_GPIO + select DM_I2C select DM_MMC select DM_THERMAL select SUPPORT_SPL diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index e530fad..396cd53 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_DM_MMC_OPS is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_MEMTEST=y @@ -33,13 +34,13 @@ CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_I2C_MXC=y CONFIG_VIDEO=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index e50b4c4..5de607c 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_IMLS is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_MEMTEST=y @@ -29,12 +30,12 @@ CONFIG_IMX_THERMAL=y # CONFIG_DM_MMC_OPS is not set CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_I2C_MXC=y CONFIG_VIDEO=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_DMA_SUPPORT=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 5/7] i2c: mxc: Print hex instead of decimal for bus address
From: Jagan Teki
Better to print the hex value for bus address instead of
decimal, for more readbility on bus addressing.
Before:
--
U-Boot> i2c dev 1
Setting bus to 1
i2c bus 1 at 35274752, no gpio pinctrl state.
After:
--
U-Boot> i2c dev 1
Setting bus to 1
i2c bus 1 at 0x21a4000, no gpio pinctrl state.
Cc: Simon Glass
Cc: Heiko Schocher
Cc: Peng Fan
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
drivers/i2c/mxc_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 6247d33..03a5ce9 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -775,7 +775,7 @@ static int mxc_i2c_probe(struct udevice *bus)
*/
ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
if (ret < 0) {
- dev_info(dev, "i2c bus %d at %lu, no gpio pinctrl state.\n",
bus->seq, i2c_bus->base);
+ dev_info(dev, "i2c bus %d at 0x%2lx, no gpio pinctrl state.\n",
bus->seq, i2c_bus->base);
} else {
ret = gpio_request_by_name_nodev(fdt, node, "scl-gpios",
0, &i2c_bus->scl_gpio,
--
2.7.4
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[U-Boot] [PATCH v2 6/7] i2c: mxc: Make 'no gpio pinctrl state' print as debug
From: Jagan Teki
Some I2C bus devicetree nodes, doesn't require to have
gpio pinctrl so replace the dev_info to debug so the
print never comes on the console and for bus that uses
gpio pinctrl anyway have dev_err.
Before:
--
U-Boot> i2c dev 1
Setting bus to 1
i2c bus 1 at 0x21a4000, no gpio pinctrl state.
After:
--
U-Boot> i2c dev 1
Setting bus to 1
Cc: Simon Glass
Cc: Heiko Schocher
Cc: Peng Fan
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
drivers/i2c/mxc_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 03a5ce9..94d9027 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -775,7 +775,7 @@ static int mxc_i2c_probe(struct udevice *bus)
*/
ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
if (ret < 0) {
- dev_info(dev, "i2c bus %d at 0x%2lx, no gpio pinctrl state.\n",
bus->seq, i2c_bus->base);
+ debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n",
bus->seq, i2c_bus->base);
} else {
ret = gpio_request_by_name_nodev(fdt, node, "scl-gpios",
0, &i2c_bus->scl_gpio,
--
2.7.4
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[U-Boot] [PATCH v2 4/7] i2c: Kconfig: Add SYS_I2C_MXC entry
From: Jagan Teki Added kconfig for SYS_I2C_MXC driver. Cc: Stefano Babic Cc: Heiko Schocher Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- drivers/i2c/Kconfig | 8 1 file changed, 8 insertions(+) diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 1537b67..051f911 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -109,6 +109,14 @@ config SYS_I2C_INTEL the I2C API meaning that any I2C operations will immediately fail for now. +config SYS_I2C_MXC + bool "NXP i.MX I2C driver" + depends on MX6 + help + Add support for the NXP i.MX I2C driver. This supports upto for bus + channels and operating on standard mode upto 100 kbits/s and fast + mode upto 400 kbits/s. + config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" depends on DM_I2C -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/7] imx6: icorem6: Add custom splashscreen support
From: Jagan Teki
Add custom splashscreen, engicam.bmp support for
Engicam i.CoreM6 qdl board.
Cc: Anatolij Gustschin
Cc: Stefano Babic
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
include/configs/imx6qdl_icore.h | 2 ++
tools/logos/engicam.bmp | Bin 0 -> 60214 bytes
2 files changed, 2 insertions(+)
create mode 100755 tools/logos/engicam.bmp
diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h
index e2b286c..670aa0f 100644
--- a/include/configs/imx6qdl_icore.h
+++ b/include/configs/imx6qdl_icore.h
@@ -37,6 +37,7 @@
/* Default environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
+ "splashpos=m,m\0" \
"image=zImage\0" \
"console=ttymxc3\0" \
"fdt_high=0x\0" \
@@ -155,6 +156,7 @@
# define CONFIG_IMX_VIDEO_SKIP
# define CONFIG_SPLASH_SCREEN
+# define CONFIG_SPLASH_SCREEN_ALIGN
# define CONFIG_BMP_16BPP
# define CONFIG_VIDEO_BMP_RLE8
# define CONFIG_VIDEO_LOGO
diff --git a/tools/logos/engicam.bmp b/tools/logos/engicam.bmp
new file mode 100755
index
..f6c60fb810d29830941e18d6725ef95785d95967
GIT binary patch
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[U-Boot] [PATCH v2 0/7] imx6: icorem6: Add framebuffer and I2C support
From: Jagan Teki This series support framebuffer and I2C on top of u-boot-imx.git with latest u-boot.git merge. Changes for v2: - Rebase on u-boot-imx.git and u-boot.git Jagan Teki (7): video: Kconfig: Add VIDEO_IPV3 entry imx6: icorem6: Add framebuffer support imx6: icorem6: Add custom splashscreen support i2c: Kconfig: Add SYS_I2C_MXC entry i2c: mxc: Print hex instead of decimal for bus address i2c: mxc: Make 'no gpio pinctrl state' print as debug imx6: icorem6: Add I2C support arch/arm/cpu/armv7/mx6/Kconfig | 1 + board/engicam/icorem6/icorem6.c | 113 +++ configs/imx6qdl_icore_mmc_defconfig | 5 +- configs/imx6qdl_icore_nand_defconfig | 5 +- drivers/i2c/Kconfig | 8 +++ drivers/i2c/mxc_i2c.c| 2 +- drivers/video/Kconfig| 8 +++ include/configs/imx6qdl_icore.h | 14 + tools/logos/engicam.bmp | Bin 0 -> 60214 bytes 9 files changed, 153 insertions(+), 3 deletions(-) create mode 100755 tools/logos/engicam.bmp -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/7] imx6: icorem6: Add framebuffer support
From: Jagan Teki
Add IPUv3 framebuffer support for Engicam i.CoreM6 qdl board.
Cc: Anatolij Gustschin
Cc: Stefano Babic
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
board/engicam/icorem6/icorem6.c | 113 +++
configs/imx6qdl_icore_mmc_defconfig | 2 +
configs/imx6qdl_icore_nand_defconfig | 2 +
include/configs/imx6qdl_icore.h | 12
4 files changed, 129 insertions(+)
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index 587775e..3b25757 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -90,6 +91,113 @@ static void setup_gpmi_nand(void)
}
#endif
+#if defined(CONFIG_VIDEO)
+static iomux_v3_cfg_t const rgb_pads[] = {
+ IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
+ IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
+ IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
+ IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
+ IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
+ IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
+ IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
+ IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
+ IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
+ IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
+ IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
+ IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
+ IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
+ IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
+ IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
+ IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
+ IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
+ IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
+ IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
+ IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
+ IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
+ IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
+};
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+ SETUP_IOMUX_PADS(rgb_pads);
+}
+
+struct display_info_t const displays[] = {
+ {
+ .bus= -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = NULL,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "Amp-WD",
+ .refresh= 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 3,
+ .left_margin= 30,
+ .right_margin = 30,
+ .upper_margin = 5,
+ .lower_margin = 5,
+ .hsync_len = 64,
+ .vsync_len = 20,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+ },
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+
+ /* Turn on LDB0,IPU,IPU DI0 clocks */
+ reg = __raw_readl(&mxc_ccm->CCGR3);
+ reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0x);
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+ MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+ (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+ IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+ IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+}
+#e
[U-Boot] [PATCH v2 1/7] video: Kconfig: Add VIDEO_IPV3 entry
From: Jagan Teki Added kconfig entry for CONFIG_VIDEO_IPV3 driver. Cc: Anatolij Gustschin Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- drivers/video/Kconfig | 8 1 file changed, 8 insertions(+) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 577e6d7..134f1c8 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -443,6 +443,14 @@ config VIDEO model. Video drivers typically provide a colour text console and cursor. +config VIDEO_IPUV3 + bool "i.MX IPUv3 Core video support" + depends on MX6 + default y if VIDEO + help + This enables framebuffer driver for i.MX processors working + on the IPUv3(Image Processing Unit) internal graphic processor. + config CFB_CONSOLE bool "Enable colour frame buffer console" depends on VIDEO -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/6] Add ARMv8 PSCI framework
On Wed, Sep 28, 2016 at 03:16:38PM +0800, Hongbo Zhang wrote: > On Wed, Sep 28, 2016 at 1:23 AM, Tom Rini wrote: > > On Tue, Sep 27, 2016 at 05:29:00PM +0800, macro.wav...@gmail.com wrote: > >> From: Hongbo Zhang > >> > >> This patch set introduces ARMv8 PSCI framework, all the PSCI functions are > >> implemented a default dummy one, it is up to each platform to implement > >> their > >> own specific ones. > >> > >> The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI. > >> Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up. > >> The last 6/6 adds a most simple implementation on NXP LS1043 platform, to > >> verify this framework. > >> > >> This patch set mainly introduces ARMv8 PSCI framework, for easier review > >> and > >> merge, further PSCI implementation on LS1043 is coming later. > >> > >> Hongbo Zhang (6): > >> ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition > >> ARMv8: Add secure sections for PSCI text and data > >> ARMv8: Add basic PSCI framework > >> ARMv8: Setup PSCI memory and dt > >> ARMv8: Enable SMC instruction > >> ARMv8: LS1043A: Enable LS1043A default PSCI support > > > > Conceptually this is good. I have some issues around order of the > > patches, and where the Kconfig entries end up. Looking over the series > > we introduce usage of some CONFIG symbols prior to declaring them in > > Kconfig. This is more of a hard no now as it will break bisecting when > > the test for no new CONFIG symbols is tripped. The other problem is > > that I think the symbols you're adding in > > board/freescale/ls1043ardb/Kconfig need to be in > > arch/arm/cpu/armv8/Kconfig and then use default ... if ... to give the > > right address for the layerscape boards. > > Thanks Tom for quick response. > > For config options introduced: > CONFIG_ARMV8_PSCI > CONFIG_ARMV8_PSCI_NR_CPUS > CONFIG_CPU_PER_CLUSTER > CONFIG_ARMV8_SECURE_BASE > > I've tested adding patch one by one, there is no problem with the > check-config script. OK. > And my idea was like this: let the CONFIG_ARMV8_PSCI to be an overall > switch, and if it is enabled even without the other three ones, the > default PSCI still works, as I've tested, this really works because > any of the other three macros, when used, there is a #ifdef to check > if it exists, if no, a default value is used or it isn't used at all. > The later three macros, because they are platform specific so I > intended to let every platform to define them. > > This is slightly different from ARMv7, plan was if this get accepted, > I would like to send patch to update ARMv7's. I think that at the end of the day we need to have less options be defined and asked under board/ and make more and in some cases better use of the common Kconfig files. Looking at how things are done in the Linux Kernel, in general, can be instructive here. Maybe the right answer here is to have CONFIG_ARCH_WANT_GENERIC_PSCI_... with default y (if most cases would be the generic one) and in the negative use the other option which is board specific values. But re-reading patch 6/6, I'm still not convinced that we shouldn't start out with these being all in arch/arm/cpu/armv8/Kconfig, under the PSCI option, for everyone, and default ... if layerscape. And that reminds that I wonder if we shouldn't have some higher level option to say "I am ARMv8 Layerscape" to cover the cases where today we test vs a number of TARGET_LS choices. Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] arm: cpu: armv7: omap-common: Clear XN bit in the ARMV7_DCACHE_POLICY
On Fri, Oct 28, 2016 at 12:01:44PM +0530, Keerthy wrote: > Clear the XN bit in the ARMV7_DCACHE_POLICY so as to mark > the regions as execute okay. > > Signed-off-by: Keerthy Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode
On Fri, Oct 28, 2016 at 12:01:43PM +0530, Keerthy wrote:
> While we setup the mmu initially we mark set_section_dcache with
> DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
> is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
> 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with
> DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
> keeps all the regions execute okay and this leads to random speculative
> fetches in random memory regions which was eventually caught by kernel
> omap-l3-noc driver.
>
> Fix this to mark the regions as XN by default.
>
> Signed-off-by: Keerthy
> ---
> arch/arm/include/asm/system.h | 2 +-
> arch/arm/lib/cache-cp15.c | 5 +
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
> index b928bd8..2f430ad 100644
> --- a/arch/arm/include/asm/system.h
> +++ b/arch/arm/include/asm/system.h
> @@ -329,7 +329,7 @@ static inline void set_dacr(unsigned int val)
>
> /* options available for data cache on each page */
> enum dcache_option {
> - DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
> + DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
> DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
> DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
> DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> index 70e94f0..4d9903e 100644
> --- a/arch/arm/lib/cache-cp15.c
> +++ b/arch/arm/lib/cache-cp15.c
> @@ -71,8 +71,13 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start,
> size_t size,
>
> end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
> start = start >> MMU_SECTION_SHIFT;
> +#ifdef CONFIG_ARMV7_LPAE
> + debug("%s: start=%pa, size=%zu, option=%llu\n", __func__, &start, size,
> + option);
> +#else
> debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
> option);
> +#endif
Does it really make sense to be printing option in decimal rather than
hex here?
--
Tom
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Re: [U-Boot] [PATCH v3] pci: Move CONFIG_PCI_PNP to Kconfig
On Fri, Oct 28, 2016 at 07:13:37AM -0400, Tom Rini wrote: > From: Bin Meng > > Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig > to use that. > > Signed-off-by: Bin Meng > Reviewed-by: Tom Rini > [trini: Re-generate configs and include/configs/ changes] > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,v2] drivers/pci/Kconfig: Add PCI
On Wed, Oct 26, 2016 at 05:15:37PM -0400, Tom Rini wrote: > Add 'PCI' as a menu option and migrate all existing users. > > Signed-off-by: Tom Rini > Acked-by: Stephen Warren Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] pci: Move CONFIG_PCI_PNP to Kconfig
From: Bin Meng Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig to use that. Signed-off-by: Bin Meng Reviewed-by: Tom Rini [trini: Re-generate configs and include/configs/ changes] Signed-off-by: Tom Rini --- configs/bamboo_defconfig | 1 + configs/gdppc440etx_defconfig | 1 + configs/yellowstone_defconfig | 1 + configs/yosemite_defconfig| 1 + drivers/pci/Kconfig | 7 +++ include/configs/B4860QDS.h| 1 - include/configs/BSC9132QDS.h | 2 -- include/configs/C29XPCIE.h| 2 -- include/configs/CPCI2DP.h | 1 - include/configs/CPCI4052.h| 1 - include/configs/M54455EVB.h | 1 - include/configs/M5475EVB.h| 1 - include/configs/M5485EVB.h| 1 - include/configs/MIP405.h | 1 - include/configs/MPC8308RDB.h | 2 -- include/configs/MPC8313ERDB.h | 1 - include/configs/MPC8315ERDB.h | 2 -- include/configs/MPC8323ERDB.h | 1 - include/configs/MPC832XEMDS.h | 1 - include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349ITX.h | 2 -- include/configs/MPC837XEMDS.h | 2 -- include/configs/MPC837XERDB.h | 1 - include/configs/MPC8536DS.h | 3 --- include/configs/MPC8540ADS.h | 3 --- include/configs/MPC8541CDS.h | 1 - include/configs/MPC8544DS.h | 2 -- include/configs/MPC8548CDS.h | 3 --- include/configs/MPC8555CDS.h | 1 - include/configs/MPC8560ADS.h | 3 --- include/configs/MPC8568MDS.h | 3 --- include/configs/MPC8569MDS.h | 3 --- include/configs/MPC8572DS.h | 2 -- include/configs/MPC8610HPCD.h | 1 - include/configs/MPC8641HPCN.h | 2 -- include/configs/P1010RDB.h| 2 -- include/configs/P1022DS.h | 1 - include/configs/P1023RDB.h| 1 - include/configs/P2041RDB.h| 1 - include/configs/PIP405.h | 1 - include/configs/PLU405.h | 1 - include/configs/PMC405DE.h| 1 - include/configs/PMC440.h | 1 - include/configs/T102xQDS.h| 1 - include/configs/T102xRDB.h| 1 - include/configs/T1040QDS.h| 2 -- include/configs/T104xRDB.h| 2 -- include/configs/T208xQDS.h| 1 - include/configs/T208xRDB.h| 1 - include/configs/T4240RDB.h| 1 - include/configs/TQM5200.h | 1 - include/configs/TQM834x.h | 1 - include/configs/UCP1020.h | 1 - include/configs/a4m072.h | 1 - include/configs/advantech_dms-ba16.h | 1 - include/configs/apalis_t30.h | 1 - include/configs/aria.h| 2 -- include/configs/bamboo.h | 1 - include/configs/bayleybay.h | 2 -- include/configs/beaver.h | 1 - include/configs/boston.h | 1 - include/configs/bubinga.h | 1 - include/configs/canyonlands.h | 1 - include/configs/cardhu.h | 1 - include/configs/cei-tk1-som.h | 1 - include/configs/clearfog.h| 1 - include/configs/conga-qeval20-qa3-e3845.h | 2 -- include/configs/controlcenterd.h | 1 - include/configs/corenet_ds.h | 1 - include/configs/cougarcanyon2.h | 2 -- include/configs/crownbay.h| 2 -- include/configs/cyrus.h | 1 - include/configs/db-88f6820-amc.h | 1 - include/configs/db-88f6820-gp.h | 1 - include/configs/db-mv784mp-gp.h | 1 - include/configs/dfi-bt700.h | 2 -- include/configs/digsy_mtc.h | 1 - include/configs/galileo.h | 2 -- include/configs/gdppc440etx.h | 1 - include/configs/ge_bx50v3.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/hrcon.h | 2 -- include/configs/icon.h| 1 - include/configs/inka4x0.h | 1 - include/configs/integratorap.h| 1 - include/configs/intip.h | 1 - include/configs/ipek01.h | 1 - include/configs/jetson-tk1.h | 1 - include/configs/jupiter.h | 1 - include/configs/katmai.h | 1 - include/configs/kilauea.h | 1 - include/configs/km/kmp204x-common.h | 1 - include/configs/ls1012aqds.h | 1 - include/configs/ls1012ardb.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - include/configs/ls1043
Re: [U-Boot] [U-Boot, v3, 6/7] usb: ehci-atmel: Remove unnecessary clock calling
On Tue, Sep 27, 2016 at 11:00:33AM +0800, Wenyou Yang wrote:
> Due to the peripheral clock driver improvement, remove the
> unnecessary clock calling.
>
> Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/usb/host/ehci-atmel.c | 15 ---
> 1 file changed, 15 deletions(-)
>
> diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
> index 2b138c5..a5c6d34 100644
> --- a/drivers/usb/host/ehci-atmel.c
> +++ b/drivers/usb/host/ehci-atmel.c
> @@ -56,9 +56,7 @@ struct ehci_atmel_priv {
>
> static int ehci_atmel_enable_clk(struct udevice *dev)
> {
> - struct udevice *dev_clk;
> struct clk clk;
> - int periph;
> int ret;
>
> ret = clk_get_by_index(dev, 0, &clk);
> @@ -73,19 +71,6 @@ static int ehci_atmel_enable_clk(struct udevice *dev)
> if (ret)
> return -EINVAL;
>
> - periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1);
> - if (periph < 0)
> - return -EINVAL;
> -
> - dev_clk = dev_get_parent(clk.dev);
> - if (!dev_clk)
> - return -ENODEV;
> -
> - ret = clk_request(dev_clk, &clk);
> - if (ret)
> - return ret;
> -
> - clk.id = periph;
> ret = clk_enable(&clk);
> if (ret)
> return ret;
___
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Re: [U-Boot] [PATCH v3] efi_loader: console: Correctly report modes
On Fri, 28 Oct 2016 11:33:19 +0200
Alexander Graf wrote:
> On 10/28/2016 10:04 AM, Emmanuel Vadot wrote:
> > Add support for EFI console modes.
> > Mode 0 is always 80x25 and present by EFI specification.
> > Mode 1 is always 80x50 and not mandatory.
> > Mode 2 and above is freely usable.
> >
> > If the terminal can handle mode 1, we mark it as supported.
> > If the terminal size is greater than mode 0 and different than mode 1,
> > we install it as mode 2.
> >
> > Modes can be switch with cout_set_mode.
> >
> > Changes in V3:
> > Valid mode are 0 to EFIMode-1
> > Fix style
> >
> > Changes in V2:
> > Add mode switch
> > Report only the modes that we support
> >
> > Signed-off-by: Emmanuel Vadot
> > ---
> > lib/efi_loader/efi_console.c | 84
> > +++-
> > 1 file changed, 68 insertions(+), 16 deletions(-)
> >
> > diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
> > index 2e0228c..eabf54f 100644
> > --- a/lib/efi_loader/efi_console.c
> > +++ b/lib/efi_loader/efi_console.c
> > @@ -9,11 +9,38 @@
> > #include
> > #include
> >
> > -/* If we can't determine the console size, default to 80x24 */
> > -static int console_columns = 80;
> > -static int console_rows = 24;
> > static bool console_size_queried;
> >
> > +#define EFI_COUT_MODE_2 2
> > +#define EFI_MAX_COUT_MODE 3
> > +
> > +struct cout_mode {
> > + unsigned long columns;
> > + unsigned long rows;
> > + int present;
> > +};
> > +
> > +static struct cout_mode efi_cout_modes[] = {
> > + /* EFI Mode 0 is 80x25 and always present */
> > + {
> > + .columns = 80,
> > + .rows = 25,
> > + .present = 1,
> > + },
> > + /* EFI Mode 1 is always 80x50 */
> > + {
> > + .columns = 80,
> > + .rows = 50,
> > + .present = 0,
> > + },
> > + /* Value are unknown until we query the console */
> > + {
> > + .columns = 0,
> > + .rows = 0,
> > + .present = 0,
> > + },
> > +};
> > +
> > const efi_guid_t efi_guid_console_control = CONSOLE_CONTROL_GUID;
> >
> > #define cESC '\x1b'
> > @@ -56,8 +83,9 @@ const struct efi_console_control_protocol
> > efi_console_control = {
> > .lock_std_in = efi_cin_lock_std_in,
> > };
> >
> > +/* Default to mode 0 */
> > static struct simple_text_output_mode efi_con_mode = {
> > - .max_mode = 0,
> > + .max_mode = 1,
> > .mode = 0,
> > .attribute = 0,
> > .cursor_column = 0,
> > @@ -131,8 +159,10 @@ static efi_status_t EFIAPI efi_cout_output_string(
> > struct efi_simple_text_output_protocol *this,
> > const unsigned short *string)
> > {
> > + struct cout_mode *mode;
> > u16 ch;
> >
> > + mode = &efi_cout_modes[efi_con_mode.mode];
> > EFI_ENTRY("%p, %p", this, string);
> > for (;(ch = *string); string++) {
> > print_unicode_in_utf8(ch);
> > @@ -140,13 +170,12 @@ static efi_status_t EFIAPI efi_cout_output_string(
> > if (ch == '\n') {
> > efi_con_mode.cursor_column = 1;
> > efi_con_mode.cursor_row++;
> > - } else if (efi_con_mode.cursor_column > console_columns) {
> > + } else if (efi_con_mode.cursor_column > mode->columns) {
> > efi_con_mode.cursor_column = 1;
> > efi_con_mode.cursor_row++;
> > }
> > - if (efi_con_mode.cursor_row > console_rows) {
> > - efi_con_mode.cursor_row = console_rows;
> > - }
> > + if (efi_con_mode.cursor_row > mode->rows)
> > + efi_con_mode.cursor_row = mode->rows;
> > }
> >
> > return EFI_EXIT(EFI_SUCCESS);
> > @@ -191,15 +220,36 @@ static efi_status_t EFIAPI efi_cout_query_mode(
> > goto out;
> > }
> >
> > - console_columns = n[2];
> > - console_rows = n[1];
> > + /* Test if we can have Mode 1 */
> > + if (n[2] >= 80 && n[1] >= 50) {
>
> This is going to be very tedious to read for someone who isn't familiar
> with the return semantics of term_read_reply(). Please put n[x] into
> local col/row variables and use them in all conditionals afterwards.
Will do.
> > + efi_cout_modes[1].present = 1;
> > + efi_con_mode.max_mode = 2;
> > + }
> > +
> > + /*
> > +* Install our mode as mode 2 if it is different
> > +* than mode 0 or 1 and set it to the default one
>
> I guess you want to say "set it as the currently selected mode"?
Yes, I'll change this.
> > +*/
> > + if ((n[2] != 80 && n[1] != 25) || (n[2] != 80 && n[1] != 50)) {
> > + efi_cout_modes[EFI_COUT_MODE_2].columns = n[2];
> > + efi_cout_modes[EFI_COUT_MODE_2].rows = n[1];
> > + efi_cout_modes[EFI_COUT_MODE_2].present = 1;
> > +
[U-Boot] [PATCH 00/11] sunxi: Add full SPL support for sun9i (A80)
Hi everyone, This series adds full SPL with DRAM initialization for sun9i (A80). The bulk of the work was done by the people at Theobroma Systems. Their work can be found here: https://git.theobroma-systems.com/armadillo-u-boot.git/ I picked the essential patches and cleaned them up a bit more, and added commit messages if they were missing. As the DRAM bits are essentially a code dump with some cleanups and some bits disabled, expect many warnings. Checkpatch is still not happy with it. I've tested the series on both my A80 boards, which I've added defconfigs for in the last 2 patches. My A80 Optimus does not boot from micro SD, so I'm still FEL booting that one. But my Cubieboard 4 is now standalone. As usual, please have a look, test if possible. Regards ChenYu Chen-Yu Tsai (5): sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80) sunxi: Add support for SID e-fuses on sun9i sunxi: Add default zq value for sun9i (A80) sunxi: Add support for A80 Optimus board sunxi: Add support for Cubieboard4 Philipp Tomsich (6): sunxi: DRAM initialisation for sun9i sunxi: add gtbus-initialisation for sun9i sunxi: Enable SMP mode for the boot CPU on sun9i (A80) sunxi: add initial clock setup for sun9i for SPL sunxi: enable SPL for sun9i sunxi: add MMC pinmux setup for SDC2 on sun9i arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 116 ++- arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 10 + arch/arm/include/asm/arch-sunxi/dram.h|2 + arch/arm/include/asm/arch-sunxi/dram_sun9i.h | 275 +++ arch/arm/include/asm/arch-sunxi/gtbus.h | 21 + arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h | 89 +++ arch/arm/mach-sunxi/Makefile |2 + arch/arm/mach-sunxi/board.c |3 +- arch/arm/mach-sunxi/clock.c |6 + arch/arm/mach-sunxi/clock_sun9i.c | 146 +++- arch/arm/mach-sunxi/dram_sun9i.c | 1059 + arch/arm/mach-sunxi/gtbus_sun9i.c | 48 ++ board/sunxi/Kconfig | 10 +- board/sunxi/MAINTAINERS | 10 + board/sunxi/board.c |7 + configs/A80_Optimus_defconfig | 18 + configs/Cubieboard4_defconfig | 18 + 17 files changed, 1818 insertions(+), 22 deletions(-) create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c create mode 100644 configs/A80_Optimus_defconfig create mode 100644 configs/Cubieboard4_defconfig -- 2.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/11] sunxi: add gtbus-initialisation for sun9i
From: Philipp Tomsich
On sun9i, the GTBUS manages transaction priority and bandwidth
for multiple read ports when accessing DRAM. The initialisation
mirrors the settings from Allwinner's boot0 for now, even though
this may not be optimal for all applications (e.g. headless
systems might want to give priority to IO modules).
Adding a common callout to gtbus_init() from the SPL clock init
with a weakly defined implementation in sunxi/clock.c to fallback
to for platforms that don't require this.
[w...@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai
---
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 2 +
arch/arm/include/asm/arch-sunxi/gtbus.h | 21 +++
arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h | 89 +++
arch/arm/mach-sunxi/Makefile | 1 +
arch/arm/mach-sunxi/clock.c | 6 ++
arch/arm/mach-sunxi/gtbus_sun9i.c | 48 +++
6 files changed, 167 insertions(+)
create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h
create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index acbc94f4c3b8..ba18a0f551ad 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -23,6 +23,8 @@
#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
+#define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
+
#define SUNXI_MMC0_BASE(REGS_AHB0_BASE + 0x0f000)
#define SUNXI_MMC1_BASE(REGS_AHB0_BASE + 0x1)
#define SUNXI_MMC2_BASE(REGS_AHB0_BASE + 0x11000)
diff --git a/arch/arm/include/asm/arch-sunxi/gtbus.h
b/arch/arm/include/asm/arch-sunxi/gtbus.h
new file mode 100644
index ..b8308d513545
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gtbus.h
@@ -0,0 +1,21 @@
+/*
+ * GTBUS initialisation
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ *Philipp Tomsich
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_GTBUS_H
+#define _SUNXI_GTBUS_H
+
+#if defined(CONFIG_MACH_SUN9I)
+#include
+#endif
+
+#ifndef __ASSEMBLY__
+void gtbus_init(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
new file mode 100644
index ..91bc2bdb5103
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
@@ -0,0 +1,89 @@
+/*
+ * GTBUS initialisation for sun9i
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ *Philipp Tomsich
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_GTBUS_SUN9I_H
+#define _SUNXI_GTBUS_SUN9I_H
+
+#include
+
+struct sunxi_gtbus_reg {
+ u32 mst_cfg[36]; /* 0x000 */
+ u8 reserved1[0x70]; /* 0x090 */
+ u32 bw_wdw_cfg;/* 0x100 */
+ u32 mst_read_prio_cfg[2]; /* 0x104 */
+ u32 lvl2_mst_cfg; /* 0x10c */
+ u32 sw_clk_on; /* 0x110 */
+ u32 sw_clk_off;/* 0x114 */
+ u32 pmu_mst_en;/* 0x118 */
+ u32 pmu_cfg; /* 0x11c */
+ u32 pmu_cnt[19]; /* 0x120 */
+ u32 reserved2[0x94]; /* 0x16c */
+ u32 cci400_config[3]; /* 0x200 */
+ u32 cci400_status[2]; /* 0x20c */
+};
+
+/* for register GT_MST_CFG_REG(n) */
+#define GT_ENABLE_REQ (1<<31) /* clock on */
+#define GT_DISABLE_REQ (1<<30) /* clock off */
+#define GT_QOS_SHIFT28
+#define GT_THD1_SHIFT 16
+#define GT_REQN_MAX 0xf /* max number master requests in one
cycle */
+#define GT_REQN_SHIFT 12
+#define GT_THD0_SHIFT 0
+
+#define GT_QOS_MAX 0x3
+#define GT_THD_MAX 0xfff
+#define GT_BW_WDW_MAX 0x
+
+/* mst_read_prio_cfg */
+#define GT_PRIO_LOW 0
+#define GT_PRIO_HIGH1
+
+/* GTBUS port ids */
+#define GT_PORT_CPUM1 0
+#define GT_PORT_CPUM2 1
+#define GT_PORT_SATA2
+#defineGT_PORT_USB33
+#defineGT_PORT_FE0 4
+#defineGT_PORT_BE1 5
+#defineGT_PORT_BE2 6
+#defineGT_PORT_IEP07
+#defineGT_PORT_FE1 8
+#defineGT_PORT_BE0 9
+#defineGT_PORT_FE2 10
+#defineGT_PORT_IEP111
+#defineGT_PORT_VED 12
+#defineGT_PORT_VEE 13
+#defineGT_PORT_FD 14
+#defineGT_PORT_CSI 15
+#defineGT_PORT_MP 16
+#defineGT_PORT_HSI 17
+#defineGT_PORT_SS 18
+#defineGT_PORT_TS 19
+#defineGT_PORT_DMA 20
+#defineGT_PORT_NDFC0 21
+#define
[U-Boot] [PATCH 01/11] sunxi: DRAM initialisation for sun9i
From: Philipp Tomsich
This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.
With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
(i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.
[w...@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai
---
arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 34 +-
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h |6 +
arch/arm/include/asm/arch-sunxi/dram.h|2 +
arch/arm/include/asm/arch-sunxi/dram_sun9i.h | 275 +++
arch/arm/mach-sunxi/Makefile |1 +
arch/arm/mach-sunxi/dram_sun9i.c | 1059 +
board/sunxi/Kconfig |6 +-
7 files changed, 1368 insertions(+), 15 deletions(-)
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h
create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index a61934fb3661..82881ff8bdaf 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -37,57 +37,61 @@ struct sunxi_ccm_reg {
u8 reserved3[0x04]; /* 0x7c */
u32 ats_cfg;/* 0x80 ats clock configuration */
u32 trace_cfg; /* 0x84 trace clock configuration */
- u8 reserved4[0xf8]; /* 0x88 */
+ u8 reserved4[0x14]; /* 0x88 */
+ u32 pll_stable_status; /* 0x9c */
+ u8 reserved5[0xe0]; /* 0xa0 */
u32 clk_output_a; /* 0x180 clk_output_a */
u32 clk_output_b; /* 0x184 clk_output_a */
- u8 reserved5[0x278];/* 0x188 */
+ u8 reserved6[0x278];/* 0x188 */
u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */
u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
- u8 reserved6[0x08]; /* 0x408 */
+ u8 reserved7[0x08]; /* 0x408 */
u32 sd0_clk_cfg;/* 0x410 sd0 clock configuration */
u32 sd1_clk_cfg;/* 0x414 sd1 clock configuration */
u32 sd2_clk_cfg;/* 0x418 sd2 clock configuration */
u32 sd3_clk_cfg;/* 0x41c sd3 clock configuration */
- u8 reserved7[0x08]; /* 0x420 */
+ u8 reserved8[0x08]; /* 0x420 */
u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */
u32 ss_clk_cfg; /* 0x42c security system clock cfg */
u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */
u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */
u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */
u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */
- u8 reserved8[0x50]; /* 0x440 */
+ u8 reserved9[0x44]; /* 0x440 */
+ u32 dram_clk_cfg; /* 0x484 DRAM (controller) clock configuration
*/
+ u8 reserved10[0x8]; /* 0x488 */
u32 de_clk_cfg; /* 0x490 display engine clock configuration */
- u8 reserved9[0x04]; /* 0x494 */
+ u8 reserved11[0x04];/* 0x494 */
u32 mp_clk_cfg; /* 0x498 mp clock configuration */
u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */
u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */
- u8 reserved10[0x1c];/* 0x4a4 */
+ u8 reserved12[0x1c];/* 0x4a4 */
u32 csi_isp_clk_cfg;/* 0x4c0 CSI ISP module clock */
u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */
u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */
u32 fd_clk_cfg; /* 0x4cc FD module clock */
u32 ve_clk_cfg; /* 0x4d0 VE module clock */
u32 avs_clk_cfg;/* 0x4d4 AVS module clock */
- u8 reserved11[0x18];/* 0x4d8 */
+ u8 reserved13[0x18];/* 0x4d8 */
u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */
u32 gpu_mem_clk_cfg;/* 0x4f4 GPU memory clock config */
u32 gpu_axi_clk_cfg;/* 0x4f8 GPU AXI clock config */
- u8 reserved12[0x10];/* 0x4fc */
+ u8 reserved14[0x10];/* 0x4fc */
u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */
- u8 reserved13[0x70];/* 0x510 */
+ u8 reserved15[0x70];/* 0x510 */
u32 ahb_gate0; /* 0x580 AHB0 Gating Register */
u32 ahb_gate1; /* 0x584 AHB1 Gating Register */
u32 ahb_gate2; /* 0x588 AHB2 Gating Register */
- u8 reserved14[0x04];/* 0x58c */
+ u8 reserved16[0x04];/* 0x58c */
u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */
u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */
- u8 reserved15[0x08];/* 0x598 */
+ u8 reserved17[0x08];/* 0x598 */
u32 ahb_reset0_cfg
[U-Boot] [PATCH 07/11] sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80)
In Allwinner's SDK the A80 is clocked to 1008 MHz by default. Signed-off-by: Chen-Yu Tsai --- board/sunxi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index ee6ae37fb7ef..5cca1eae73b3 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -255,7 +255,7 @@ endif config SYS_CLK_FREQ default 81600 if MACH_SUN50I default 91200 if MACH_SUN7I - default 100800 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I + default 100800 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I config SYS_CONFIG_NAME default "sun4i" if MACH_SUN4I -- 2.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/11] sunxi: Add default zq value for sun9i (A80)
Both the A80 Optimus board and the Cubieboard 4 use a zq value of 4145117, or 0x3f3fdd. Signed-off-by: Chen-Yu Tsai --- board/sunxi/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 5cca1eae73b3..e1d4ab148f08 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -163,6 +163,7 @@ config DRAM_ZQ int "sunxi dram zq value" default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I default 127 if MACH_SUN7I + default 4145117 if MACH_SUN9I ---help--- Set the dram zq value. -- 2.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 08/11] sunxi: Add support for SID e-fuses on sun9i
The A80 has SID e-fuses. Like other newer SoCs, the actual e-fuses are at an offset of 0x200 within the SID address space. Signed-off-by: Chen-Yu Tsai --- arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h index ba18a0f551ad..c775bcc515a0 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -24,6 +24,8 @@ #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000) #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000) +/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */ +#define SUNXI_SID_BASE (REGS_AHB0_BASE + 0xe200) #define SUNXI_MMC0_BASE(REGS_AHB0_BASE + 0x0f000) #define SUNXI_MMC1_BASE(REGS_AHB0_BASE + 0x1) -- 2.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/11] sunxi: Enable SMP mode for the boot CPU on sun9i (A80)
From: Philipp Tomsich Since the A80 has many cores which we intend to use in SMP fashion, we should set the SMP bit for the boot CPU. [w...@csie.org: Added commit message] Signed-off-by: Chen-Yu Tsai --- arch/arm/mach-sunxi/board.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 7713813a68a8..0f8ead980cdc 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -182,7 +182,8 @@ void s_init(void) #if defined CONFIG_MACH_SUN6I || \ defined CONFIG_MACH_SUN7I || \ -defined CONFIG_MACH_SUN8I +defined CONFIG_MACH_SUN8I || \ +defined CONFIG_MACH_SUN9I /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ asm volatile( "mrc p15, 0, r0, c1, c0, 1\n" -- 2.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/11] sunxi: Add support for A80 Optimus board
The A80 Optimus Board was launched with the Allwinner A80 SoC. It was jointly developed by Allwinner and Merrii. This board has a UART port, a JTAG connector, 2 USB host ports, a USB 3.0 OTG connector, an HDMI output, a micro SD slot, 16G eMMC flash, 2G DRAM, a camera sensor interface, a WiFi/BT combo chip, a headphone jack, IR receiver, and additional GPIO headers. Signed-off-by: Chen-Yu Tsai --- board/sunxi/MAINTAINERS | 5 + configs/A80_Optimus_defconfig | 18 ++ 2 files changed, 23 insertions(+) create mode 100644 configs/A80_Optimus_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index f7129b7d53a5..6e0aa24eb859 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -94,6 +94,11 @@ M: Stefan Mavrodiev S: Maintained F: configs/A33-OLinuXino_defconfig +A80 OPTIMUS BOARD +M: Chen-Yu Tsai +S: Maintained +F: configs/A80_Optimus_defconfig + AINOL AW1 BOARD M: Paul Kocialkowski S: Maintained diff --git a/configs/A80_Optimus_defconfig b/configs/A80_Optimus_defconfig new file mode 100644 index ..6397de5de5fd --- /dev/null +++ b/configs/A80_Optimus_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN9I=y +CONFIG_DRAM_CLK=672 +CONFIG_MMC0_CD_PIN="PH18" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +CONFIG_USB0_ID_DET="PH3" +CONFIG_USB1_VBUS_PIN="PH4" +CONFIG_USB3_VBUS_PIN="PH5" +CONFIG_AXP_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus" +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_AXP809_POWER=y -- 2.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 06/11] sunxi: add MMC pinmux setup for SDC2 on sun9i
From: Philipp Tomsich
The A80 can support 8-bit eMMC with reset on the PC pingroups.
Signed-off-by: Chen-Yu Tsai
---
board/sunxi/board.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 6281c9d70379..53656383d512 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -307,6 +307,13 @@ static void mmc_pinmux_setup(int sdc)
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#elif defined(CONFIG_MACH_SUN9I)
+ /* SDC2: PC6-PC16 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
#endif
break;
--
2.9.3
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[U-Boot] [PATCH 04/11] sunxi: add initial clock setup for sun9i for SPL
From: Philipp Tomsich
This is a cleaned up version set_pll() from Allwinner's boot0 source
(bootloader/basic_loader/bsp/bsp_for_a80/common/common.c).
[w...@csie.org: Added commit message; style cleanup]
Signed-off-by: Chen-Yu Tsai
---
arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 82 ++-
arch/arm/mach-sunxi/clock_sun9i.c | 146 +-
2 files changed, 223 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index 82881ff8bdaf..acff26126178 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -96,9 +96,6 @@ struct sunxi_ccm_reg {
u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */
};
-/* pll4_periph0_cfg */
-#define PLL4_CFG_DEFAULT 0x90002800 /* 960 MHz */
-
#define CCM_PLL4_CTRL_N_SHIFT 8
#define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT)
#define CCM_PLL4_CTRL_P_SHIFT 16
@@ -106,6 +103,80 @@ struct sunxi_ccm_reg {
#define CCM_PLL4_CTRL_M_SHIFT 18
#define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT)
+/* pllx_cfg bits */
+#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8)
+#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16)
+#define CCM_PLL1_CTRL_EN (1 << 31)
+#define CCM_PLL1_CLOCK_TIME_2 (2 << 24)
+
+#define CCM_PLL2_CTRL_N(n) (((n) & 0xff) << 8)
+#define CCM_PLL2_CTRL_P(n) (((n) & 0x1) << 16)
+#define CCM_PLL2_CTRL_EN (1 << 31)
+#define CCM_PLL2_CLOCK_TIME_2 (2 << 24)
+
+#define CCM_PLL4_CTRL_N(n) (((n) & 0xff) << 8)
+#define CCM_PLL4_CTRL_EN (1 << 31)
+
+#define CCM_PLL6_CTRL_N(n) (((n) & 0xff) << 8)
+#define CCM_PLL6_CTRL_P(p) (((p) & 0x1) << 16)
+#define CCM_PLL6_CTRL_EN (1 << 31)
+#define CCM_PLL6_CFG_UPDATE (1 << 30)
+
+#define CCM_PLL12_CTRL_N(n)(((n) & 0xff) << 8)
+#define CCM_PLL12_CTRL_EN (1 << 31)
+
+#define PLL_C0CPUX_STATUS (1 << 0)
+#define PLL_C1CPUX_STATUS (1 << 1)
+#define PLL_DDR_STATUS (1 << 5)
+#define PLL_PERIPH1_STATUS (1 << 11)
+
+/* cpu_clk_source bits */
+#define C0_CPUX_CLK_SRC_SHIFT 0
+#define C1_CPUX_CLK_SRC_SHIFT 8
+#define C0_CPUX_CLK_SRC_MASK(1 << C0_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_MASK(1 << C1_CPUX_CLK_SRC_SHIFT)
+#define C0_CPUX_CLK_SRC_OSC24M (0 << C0_CPUX_CLK_SRC_SHIFT)
+#define C0_CPUX_CLK_SRC_PLL1 (1 << C0_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_OSC24M (0 << C1_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_PLL2 (1 << C1_CPUX_CLK_SRC_SHIFT)
+
+/* c0_cfg */
+#define C0_CFG_AXI0_CLK_DIV_RATIO(n)(((n - 1) & 0x3) << 0)
+#define C0_CFG_APB0_CLK_DIV_RATIO(n)(((n - 1) & 0x3) << 8)
+
+/* ahbx_cfg */
+#define AHBx_SRC_CLK_SELECT_SHIFT 24
+#define AHBx_SRC_MASK (0x3 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB0_SRC_GTBUS_CLK (0x0 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB1_SRC_GTBUS_CLK (0x0 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB2_SRC_OSC24M (0x0 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_SRC_PLL_PERIPH0(0x1 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_SRC_PLL_PERIPH1(0x2 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0)
+
+/* apb0_cfg */
+#define APB0_SRC_CLK_SELECT_SHIFT 24
+#define APB0_SRC_MASK (0x1 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_SRC_OSC24M (0x0 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_SRC_PLL_PERIPH0(0x1 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0)
+
+/* gtbus_clk_cfg */
+#define GTBUS_SRC_CLK_SELECT_SHIFT 24
+#define GTBUS_SRC_MASK (0x3 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_OSC24M(0x0 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_PLL_PERIPH0 (0x1 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_PLL_PERIPH1 (0x2 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0)
+
+/* cci400_clk_cfg */
+#define CCI400_SRC_CLK_SELECT_SHIFT 24
+#define CCI400_SRC_MASK (0x3 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_OSC24M (0x0 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_PLL_PERIPH0 (0x1 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_PLL_PERIPH1 (0x2 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0)
+
/* sd#_clk_cfg fields */
#define CCM_MMC_CTRL_M(x) ((x) - 1)
#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
@@ -145,6 +216,11 @@ struct sun
[U-Boot] [PATCH 11/11] sunxi: Add support for Cubieboard4
The Cubieboard4 is an A80 SoC based development board from Cubietech. This board has a UART port, 4 USB host ports, a USB 3.0 OTG connector, HDMI and VGA outputs, a micro SD slot, 8G eMMC flash, 2G DRAM, a WiFi/BT combo chip, headphone and microphone jacks, IR receiver, and GPIO headers. Signed-off-by: Chen-Yu Tsai --- board/sunxi/MAINTAINERS | 5 + configs/Cubieboard4_defconfig | 18 ++ 2 files changed, 23 insertions(+) create mode 100644 configs/Cubieboard4_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 6e0aa24eb859..df05b3284807 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -122,6 +122,11 @@ F: include/configs/sun7i.h F: configs/Cubieboard2_defconfig F: configs/Cubietruck_defconfig +CUBIEBOARD4 BOARD +M: Chen-Yu Tsai +S: Maintained +F: configs/Cubieboard4_defconfig + CUBIETRUCK-PLUS BOARD M: Chen-Yu Tsai S: Maintained diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig new file mode 100644 index ..4d36d39e5974 --- /dev/null +++ b/configs/Cubieboard4_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN9I=y +CONFIG_DRAM_CLK=672 +CONFIG_MMC0_CD_PIN="PH18" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +CONFIG_USB0_ID_DET="PH16" +CONFIG_USB1_VBUS_PIN="PH14" +CONFIG_USB3_VBUS_PIN="PH15" +CONFIG_AXP_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cubieboard4" +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_AXP809_POWER=y -- 2.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 05/11] sunxi: enable SPL for sun9i
From: Philipp Tomsich Now that DRAM initialization and clock setup is supported, we can enable SPL for the A80. [w...@csie.org: Added commit message] Signed-off-by: Chen-Yu Tsai --- board/sunxi/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index a126c3e30140..ee6ae37fb7ef 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -119,6 +119,7 @@ config MACH_SUN9I bool "sun9i (Allwinner A80)" select CPU_V7 select SUNXI_GEN_SUN6I + select SUPPORT_SPL config MACH_SUN50I bool "sun50i (Allwinner A64)" -- 2.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/6] ARM: at91: clock: correct PRES offset for at91sam9x5
On Wed, Aug 17, 2016 at 09:13:24AM +0200, Heiko Schocher wrote: > on at91sam9x5 PRES offset is 4 in the PMC master > clock register. > > Signed-off-by: Heiko Schocher > Acked-by: Wenyou Yang Acked-by: Andreas Bießmann > --- > > arch/arm/mach-at91/arm926ejs/clock.c | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm/mach-at91/arm926ejs/clock.c > b/arch/arm/mach-at91/arm926ejs/clock.c > index c8d24ae..e3181fa 100644 > --- a/arch/arm/mach-at91/arm926ejs/clock.c > +++ b/arch/arm/mach-at91/arm926ejs/clock.c > @@ -162,7 +162,13 @@ int at91_clock_init(unsigned long main_clock) > gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); > freq = gd->arch.mck_rate_hz; > > +#if defined(CONFIG_AT91SAM9X5) > + /* different in prescale on at91sam9x5 */ > + freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4)); > +#else > freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ > +#endif > + > #if defined(CONFIG_AT91SAM9G20) > /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ > gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] efi_loader: console: Correctly report modes
On 10/28/2016 10:04 AM, Emmanuel Vadot wrote:
Add support for EFI console modes.
Mode 0 is always 80x25 and present by EFI specification.
Mode 1 is always 80x50 and not mandatory.
Mode 2 and above is freely usable.
If the terminal can handle mode 1, we mark it as supported.
If the terminal size is greater than mode 0 and different than mode 1,
we install it as mode 2.
Modes can be switch with cout_set_mode.
Changes in V3:
Valid mode are 0 to EFIMode-1
Fix style
Changes in V2:
Add mode switch
Report only the modes that we support
Signed-off-by: Emmanuel Vadot
---
lib/efi_loader/efi_console.c | 84 +++-
1 file changed, 68 insertions(+), 16 deletions(-)
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index 2e0228c..eabf54f 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -9,11 +9,38 @@
#include
#include
-/* If we can't determine the console size, default to 80x24 */
-static int console_columns = 80;
-static int console_rows = 24;
static bool console_size_queried;
+#define EFI_COUT_MODE_2 2
+#define EFI_MAX_COUT_MODE 3
+
+struct cout_mode {
+ unsigned long columns;
+ unsigned long rows;
+ int present;
+};
+
+static struct cout_mode efi_cout_modes[] = {
+ /* EFI Mode 0 is 80x25 and always present */
+ {
+ .columns = 80,
+ .rows = 25,
+ .present = 1,
+ },
+ /* EFI Mode 1 is always 80x50 */
+ {
+ .columns = 80,
+ .rows = 50,
+ .present = 0,
+ },
+ /* Value are unknown until we query the console */
+ {
+ .columns = 0,
+ .rows = 0,
+ .present = 0,
+ },
+};
+
const efi_guid_t efi_guid_console_control = CONSOLE_CONTROL_GUID;
#define cESC '\x1b'
@@ -56,8 +83,9 @@ const struct efi_console_control_protocol efi_console_control
= {
.lock_std_in = efi_cin_lock_std_in,
};
+/* Default to mode 0 */
static struct simple_text_output_mode efi_con_mode = {
- .max_mode = 0,
+ .max_mode = 1,
.mode = 0,
.attribute = 0,
.cursor_column = 0,
@@ -131,8 +159,10 @@ static efi_status_t EFIAPI efi_cout_output_string(
struct efi_simple_text_output_protocol *this,
const unsigned short *string)
{
+ struct cout_mode *mode;
u16 ch;
+ mode = &efi_cout_modes[efi_con_mode.mode];
EFI_ENTRY("%p, %p", this, string);
for (;(ch = *string); string++) {
print_unicode_in_utf8(ch);
@@ -140,13 +170,12 @@ static efi_status_t EFIAPI efi_cout_output_string(
if (ch == '\n') {
efi_con_mode.cursor_column = 1;
efi_con_mode.cursor_row++;
- } else if (efi_con_mode.cursor_column > console_columns) {
+ } else if (efi_con_mode.cursor_column > mode->columns) {
efi_con_mode.cursor_column = 1;
efi_con_mode.cursor_row++;
}
- if (efi_con_mode.cursor_row > console_rows) {
- efi_con_mode.cursor_row = console_rows;
- }
+ if (efi_con_mode.cursor_row > mode->rows)
+ efi_con_mode.cursor_row = mode->rows;
}
return EFI_EXIT(EFI_SUCCESS);
@@ -191,15 +220,36 @@ static efi_status_t EFIAPI efi_cout_query_mode(
goto out;
}
- console_columns = n[2];
- console_rows = n[1];
+ /* Test if we can have Mode 1 */
+ if (n[2] >= 80 && n[1] >= 50) {
This is going to be very tedious to read for someone who isn't familiar
with the return semantics of term_read_reply(). Please put n[x] into
local col/row variables and use them in all conditionals afterwards.
+ efi_cout_modes[1].present = 1;
+ efi_con_mode.max_mode = 2;
+ }
+
+ /*
+* Install our mode as mode 2 if it is different
+* than mode 0 or 1 and set it to the default one
I guess you want to say "set it as the currently selected mode"?
+*/
+ if ((n[2] != 80 && n[1] != 25) || (n[2] != 80 && n[1] != 50)) {
+ efi_cout_modes[EFI_COUT_MODE_2].columns = n[2];
+ efi_cout_modes[EFI_COUT_MODE_2].rows = n[1];
+ efi_cout_modes[EFI_COUT_MODE_2].present = 1;
+ efi_con_mode.max_mode = EFI_MAX_COUT_MODE;
+ efi_con_mode.mode = EFI_COUT_MODE_2;
+ }
}
+ if (mode_number >= efi_con_mode.max_mode)
+ return EFI_EXIT(EFI_UNSUPPORTED);
+
+ if (efi_cout_modes[mode_number].present != 1)
+ return EFI_EXIT(EFI_UNSUPPORTED);
+
out:
if (c
[U-Boot] [PATCH v3] efi_loader: console: Correctly report modes
Add support for EFI console modes.
Mode 0 is always 80x25 and present by EFI specification.
Mode 1 is always 80x50 and not mandatory.
Mode 2 and above is freely usable.
If the terminal can handle mode 1, we mark it as supported.
If the terminal size is greater than mode 0 and different than mode 1,
we install it as mode 2.
Modes can be switch with cout_set_mode.
Changes in V3:
Valid mode are 0 to EFIMode-1
Fix style
Changes in V2:
Add mode switch
Report only the modes that we support
Signed-off-by: Emmanuel Vadot
---
lib/efi_loader/efi_console.c | 84 +++-
1 file changed, 68 insertions(+), 16 deletions(-)
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index 2e0228c..eabf54f 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -9,11 +9,38 @@
#include
#include
-/* If we can't determine the console size, default to 80x24 */
-static int console_columns = 80;
-static int console_rows = 24;
static bool console_size_queried;
+#define EFI_COUT_MODE_2 2
+#define EFI_MAX_COUT_MODE 3
+
+struct cout_mode {
+ unsigned long columns;
+ unsigned long rows;
+ int present;
+};
+
+static struct cout_mode efi_cout_modes[] = {
+ /* EFI Mode 0 is 80x25 and always present */
+ {
+ .columns = 80,
+ .rows = 25,
+ .present = 1,
+ },
+ /* EFI Mode 1 is always 80x50 */
+ {
+ .columns = 80,
+ .rows = 50,
+ .present = 0,
+ },
+ /* Value are unknown until we query the console */
+ {
+ .columns = 0,
+ .rows = 0,
+ .present = 0,
+ },
+};
+
const efi_guid_t efi_guid_console_control = CONSOLE_CONTROL_GUID;
#define cESC '\x1b'
@@ -56,8 +83,9 @@ const struct efi_console_control_protocol efi_console_control
= {
.lock_std_in = efi_cin_lock_std_in,
};
+/* Default to mode 0 */
static struct simple_text_output_mode efi_con_mode = {
- .max_mode = 0,
+ .max_mode = 1,
.mode = 0,
.attribute = 0,
.cursor_column = 0,
@@ -131,8 +159,10 @@ static efi_status_t EFIAPI efi_cout_output_string(
struct efi_simple_text_output_protocol *this,
const unsigned short *string)
{
+ struct cout_mode *mode;
u16 ch;
+ mode = &efi_cout_modes[efi_con_mode.mode];
EFI_ENTRY("%p, %p", this, string);
for (;(ch = *string); string++) {
print_unicode_in_utf8(ch);
@@ -140,13 +170,12 @@ static efi_status_t EFIAPI efi_cout_output_string(
if (ch == '\n') {
efi_con_mode.cursor_column = 1;
efi_con_mode.cursor_row++;
- } else if (efi_con_mode.cursor_column > console_columns) {
+ } else if (efi_con_mode.cursor_column > mode->columns) {
efi_con_mode.cursor_column = 1;
efi_con_mode.cursor_row++;
}
- if (efi_con_mode.cursor_row > console_rows) {
- efi_con_mode.cursor_row = console_rows;
- }
+ if (efi_con_mode.cursor_row > mode->rows)
+ efi_con_mode.cursor_row = mode->rows;
}
return EFI_EXIT(EFI_SUCCESS);
@@ -191,15 +220,36 @@ static efi_status_t EFIAPI efi_cout_query_mode(
goto out;
}
- console_columns = n[2];
- console_rows = n[1];
+ /* Test if we can have Mode 1 */
+ if (n[2] >= 80 && n[1] >= 50) {
+ efi_cout_modes[1].present = 1;
+ efi_con_mode.max_mode = 2;
+ }
+
+ /*
+* Install our mode as mode 2 if it is different
+* than mode 0 or 1 and set it to the default one
+*/
+ if ((n[2] != 80 && n[1] != 25) || (n[2] != 80 && n[1] != 50)) {
+ efi_cout_modes[EFI_COUT_MODE_2].columns = n[2];
+ efi_cout_modes[EFI_COUT_MODE_2].rows = n[1];
+ efi_cout_modes[EFI_COUT_MODE_2].present = 1;
+ efi_con_mode.max_mode = EFI_MAX_COUT_MODE;
+ efi_con_mode.mode = EFI_COUT_MODE_2;
+ }
}
+ if (mode_number >= efi_con_mode.max_mode)
+ return EFI_EXIT(EFI_UNSUPPORTED);
+
+ if (efi_cout_modes[mode_number].present != 1)
+ return EFI_EXIT(EFI_UNSUPPORTED);
+
out:
if (columns)
- *columns = console_columns;
+ *columns = efi_cout_modes[mode_number].columns;
if (rows)
- *rows = console_rows;
+ *rows = efi_cout_modes[mode_number].rows;
return EFI_EXIT(EFI_SUCCESS);
}
@@ -210,11 +260,13 @@ static efi_status_t EFIAPI efi_cout_set_
[U-Boot] [PATCH v1] dfu: align array in dfu_get_dev_type with enum dfu_device_type
Signed-off-by: Patrick Delaunay
---
drivers/dfu/dfu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index 20dfcbb..8dacc1a 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -482,7 +482,7 @@ int dfu_config_entities(char *env, char *interface, char
*devstr)
const char *dfu_get_dev_type(enum dfu_device_type t)
{
- const char *dev_t[] = {NULL, "eMMC", "OneNAND", "NAND", "RAM" };
+ const char *dev_t[] = {NULL, "eMMC", "OneNAND", "NAND", "RAM", "SF" };
return dev_t[t];
}
--
1.9.1
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Re: [U-Boot] FSL PowerPC platform: Not able to boot Linux with ramdisk size > 100MB
On 10/27/2016 04:27 AM, Prabhakar Kushwaha wrote: > Hi Masahiro, > > I am not able to boot Linux onF PowerPC platform with ramdisk size > 100MB. > I tried u-boot master with top commit as " > 5ac5861c4ba851b473e6a24940b412b397627d8d ". > > I tried git-bisect and figured out below patch causing this problem. If I > revert this patch, Linux boots properly. > > commit 20e072f37402c17741f67d9693eaabdd835b80f2 > Author: Masahiro Yamada > Date: Thu Dec 17 17:19:35 2015 +0900 > > image: check "bootm_low" and "bootm_size" if "initrd_high" is missing > > To boot Linux, we should prevent Initramdisk and FDT from going too > high. > > Currently, boot_relocate_fdt() checks "fdt_high" environment first, > and then falls back to getenv_bootm_mapsize() + getenv_bootm_low() > if "fdt_high" is missing. > > On the other hand, boot_ramdisk_high() only checks "initrd_high" to > get the address limit for the Initramdisk. We also want to let this > case fall back to getenv_bootm_mapsize() + getenv_bootm_low(). > > Signed-off-by: Masahiro Yamada > > Please advise!! On PPC the initrd does not need to be loaded within the boot mapping. This assumption of what the absence of initrd_high means is not universally appropriate. Why not just set initrd_high on the platforms that need it? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] arm: cpu: armv7: omap-common: Clear XN bit in the ARMV7_DCACHE_POLICY
On Friday 28 October 2016 12:56 PM, Alexander Graf wrote: On 28/10/2016 08:31, Keerthy wrote: Clear the XN bit in the ARMV7_DCACHE_POLICY so as to mark the regions as execute okay. Signed-off-by: Keerthy How did you ever get the bit set in DCACHE_WRITEALLOC or WRITEBACK in the first place? Both are RAM mapping flags which shouldn't have the XN mask set. Just searched through none of them have the bit sit so that is redundant. I added to be doubly sure and can be removed. This patch is not needed. Alex --- arch/arm/cpu/armv7/omap-common/omap-cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c index b37163a..a71aa0d 100644 --- a/arch/arm/cpu/armv7/omap-common/omap-cache.c +++ b/arch/arm/cpu/armv7/omap-common/omap-cache.c @@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; */ #ifdef CONFIG_ARMV7_LPAE -#define ARMV7_DCACHE_POLICYDCACHE_WRITEALLOC +#define ARMV7_DCACHE_POLICYDCACHE_WRITEALLOC & ~TTB_SECT_XN_MASK #else #define ARMV7_DCACHE_POLICYDCACHE_WRITEBACK & ~TTB_SECT_XN_MASK #endif ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 6/7] board: sama5d3_xplained: enable early debug UART
Enable early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang
---
board/atmel/sama5d3_xplained/sama5d3_xplained.c | 16 +++-
configs/sama5d3_xplained_mmc_defconfig | 6 ++
configs/sama5d3_xplained_nandflash_defconfig| 6 ++
include/configs/sama5d3_xplained.h | 2 ++
4 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index c4d67a7..692fec6 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -67,12 +68,25 @@ static void sama5d3_xplained_mci0_hw_init(void)
}
#endif
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
{
at91_seriald_hw_init();
+}
+#endif
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#else
+ sama5d4_xplained_serial3_hw_init();
+ at91_seriald_hw_init();
+#endif
return 0;
}
+#endif
int board_init(void)
{
diff --git a/configs/sama5d3_xplained_mmc_defconfig
b/configs/sama5d3_xplained_mmc_defconfig
index 8940f16..a9890cc 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -46,6 +46,12 @@ CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_DM_USB=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig
b/configs/sama5d3_xplained_nandflash_defconfig
index 6020513..05798d6 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -44,6 +44,12 @@ CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_DM_USB=y
diff --git a/include/configs/sama5d3_xplained.h
b/include/configs/sama5d3_xplained.h
index fe5d19a..7cf65f9 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -15,6 +15,8 @@
#include "at91-sama5_common.h"
+#define CONFIG_BOARD_EARLY_INIT_F
+
/*
* This needs to be defined for the OHCI code to work but it is defined as
* ATMEL_ID_UHPHS in the CPU specific header files.
--
2.7.4
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