date:20161029

Re: [U-Boot] [linux-sunxi] Re: [PATCH 00/11] sunxi: Add full SPL support for sun9i (A80)

2016-10-29 Thread Chen-Yu Tsai

On Sat, Oct 29, 2016 at 8:06 PM, Hans de Goede  wrote:
> Hi,
>
>
> On 28-10-16 19:30, Hans de Goede wrote:
>>
>> Hi Chen-Yu,
>>
>> On 28-10-16 12:21, Chen-Yu Tsai wrote:
>>>
>>> Hi everyone,
>>>
>>> This series adds full SPL with DRAM initialization for sun9i (A80).
>>> The bulk of the work was done by the people at Theobroma Systems.
>>> Their work can be found here:
>>>
>>> https://git.theobroma-systems.com/armadillo-u-boot.git/
>>>
>>> I picked the essential patches and cleaned them up a bit more,
>>> and added commit messages if they were missing.
>>>
>>> As the DRAM bits are essentially a code dump with some cleanups and
>>> some bits disabled, expect many warnings. Checkpatch is still not
>>> happy with it.
>>>
>>> I've tested the series on both my A80 boards, which I've added
>>> defconfigs for in the last 2 patches. My A80 Optimus does not
>>> boot from micro SD, so I'm still FEL booting that one. But my
>>> Cubieboard 4 is now standalone.
>>>
>>> As usual, please have a look, test if possible.
>>
>>
>> Awesome, thanks for doing this and it was good to have
>> some face2face time at ELCE.
>>
>> I've merged this into my personal sunxi-wip u-boot branch,
>> I've made 2 changes:
>>
>> 1) in : ¨sunxi: DRAM initialisation for sun9i" there are a
>> lot of #if 0 #endif blocks, most of these document some features
>> which we may want to enable in the future, but a few were just
>> dead weight IMHO, so I've pruned a few
>>
>> 2) in : "sunxi: Add support for A80 Optimus board", we already
>> have a configs/Merrii_A80_Optimus_defconfig, so I've made the patch
>> update that instead of adding a new defconfig
>>
>> I have not tested this yet, I will do tomorrow, assuming it
>> works for me too I will include it in my next pull-req (*)
>
>
> Ok, just finished testing, u-boot seems to work well. I do
> seem to have one kernel issue (with the last 4.8 based
> sunxi-next kernel, I still need to upgrade that) :
>
> [1.137105] Division by zero in kernel.
> [1.140988] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.0+ #475
> [1.147089] Hardware name: Allwinner sun9i Family
> [1.151830] [] (unwind_backtrace) from []
> (show_stack+0x18/0x1c)
> [1.159596] [] (show_stack) from []
> (dump_stack+0x80/0x9c)
> [1.166839] [] (dump_stack) from [] (Ldiv0+0x8/0x10)
> [1.173558] [] (Ldiv0) from []
> (sun4i_a10_get_mod0_factors+0x2c/0x8c)
> [1.181758] [] (sun4i_a10_get_mod0_factors) from []
> (clk_factors_determine_rate+0xb8/0xf8)
> [1.191781] [] (clk_factors_determine_rate) from []
> (clk_composite_determine_rate+0x58/0x1cc)
> [1.202062] [] (clk_composite_determine_rate) from []
> (clk_calc_new_rates+0xa0/0x240)
> [1.211647] [] (clk_calc_new_rates) from []
> (clk_core_set_rate_nolock+0x4c/0xbc)
> [1.220798] [] (clk_core_set_rate_nolock) from []
> (clk_set_rate+0x28/0x38)
> [1.229432] [] (clk_set_rate) from []
> (sunxi_ir_probe+0xfc/0x480)
> [1.420454] [] (sunxi_ir_probe) from []
> (platform_drv_pro
> be+0x58/0xa4)
>
> ...
>
> And it fails to find any mmc controllers, but that might be related to
> the above oops (maybe it stops probing after that due to a stuck lock).

This is related to the regulators, specifically cold boot default
values for ldo_ios causing the regulators to fail to register. You
actually fixed this for the axp22x's before.

There's also the addressing issue for the axp806.

See the top of https://github.com/wens/linux/commits/sun9i-gmac-wifi
for the bunch of fixes I need to send.

> Anyways the u-boot side looks good. One issue I see is that your
> optimus has an emmc, where as mine has a nand. We may want to
> gave 2 optimus defconfigs for this once we've nand support.

Hmm... This implies the need for 2 versions of dts files as well.
Any ideas on probing for nand/emmc during boot?

Regards
ChenYu

> Regards,
>
> Hans
>
>
>
>> and try to get it included in the 2016.11 release, yes the merge
>> window has closed, but the changes here are very isolated so
>> I will try and see what Tom says :)
>>
>> Regards,
>>
>> Hans
>>
>>
>> *) Which I hope to send out this weekend
>>
>>
>>
>>>
>>>
>>> Regards
>>> ChenYu
>>>
>>>
>>> Chen-Yu Tsai (5):
>>>   sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80)
>>>   sunxi: Add support for SID e-fuses on sun9i
>>>   sunxi: Add default zq value for sun9i (A80)
>>>   sunxi: Add support for A80 Optimus board
>>>   sunxi: Add support for Cubieboard4
>>>
>>> Philipp Tomsich (6):
>>>   sunxi: DRAM initialisation for sun9i
>>>   sunxi: add gtbus-initialisation for sun9i
>>>   sunxi: Enable SMP mode for the boot CPU on sun9i (A80)
>>>   sunxi: add initial clock setup for sun9i for SPL
>>>   sunxi: enable SPL for sun9i
>>>   sunxi: add MMC pinmux setup for SDC2 on sun9i
>>>
>>>  arch/arm/include/asm/arch-sunxi/clock_sun9i.h |  116 ++-
>>>  arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |   10 +
>>>  arch/arm/include/asm/arch-sunxi/dram.h|2 +
>>>

Re: [U-Boot] [PATCH v2 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-10-29 Thread Keerthy




On Saturday 29 October 2016 11:19 PM, Marek Vasut wrote:

On 10/29/2016 07:47 PM, Tom Rini wrote:

On Sat, Oct 29, 2016 at 07:44:34PM +0200, Marek Vasut wrote:

On 10/29/2016 07:41 PM, Tom Rini wrote:

On Sat, Oct 29, 2016 at 03:19:10PM +0530, Keerthy wrote:


While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.

Fix this to mark the regions as XN by default.

Signed-off-by: Keerthy 
Reviewed-by: Alexander Graf 


Reviewed-by: Tom Rini 


Isn't this patch exactly undoing the following one ?

commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
Author: Marek Vasut <>
Date:   Tue Dec 29 19:44:02 2015 +0100

arm: Remove S bit from MMU section entry

Restore the old behavior of the MMU section entries configuration,
which is without the S-bit.


Is it?  I guess perhaps you and Keerthy need to chat then as there's
some other problem they're addressing.


U, wait a second, I think this one adds XN bit and the previous one
removed S bit. I think I was wrong, but please double-check this. I
recall we had some odd cache issues on V7 back then.


Marek,

First and foremost if we git blame on the file: 
arch/arm/include/asm/system.h


your commit:
8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc

arm: Remove S bit from MMU section entry

It is removing S bit under
#elif defined(CONFIG_CPU_V7)

I am adding the missing XN bit under:
#ifdef CONFIG_ARMV7_LPAE

So we are dealing with different modes.

In a nutshell your patch removes S bit from MMU section entry for 
non-LPAE cases for ARMV7 and mine adds XN bit for LPAE cases.


Hope this clears out the confusion.

- Keerthy





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[U-Boot] [PATCH] travis.yml: Add in uniphier as a job, modify aarch64 builds a bit

2016-10-29 Thread Tom Rini

- Add in system aarch64-linux-gnu toolchain
- Now that all VMs will have aarch64 available, don't exclude them from
  other jobs but instead exclude them from the catch-all aarch64 build
- Add JOB= to the Freescale/ARM build to be clear about what it does.
- Add uniphier as a stand-alone job

Signed-off-by: Tom Rini 
---
 .travis.yml | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index cda2d979ee4a..bb9325bacc33 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -27,6 +27,7 @@ addons:
 - qemu-system-x86
 - gcc-powerpc-linux-gnu
 - gcc-arm-linux-gnueabihf
+- gcc-aarch64-linux-gnu
 - iasl
 
 install:
@@ -54,7 +55,6 @@ env:
 
 before_script:
   # install toolchains based on TOOLCHAIN} variable
-  - if [[ "${TOOLCHAIN}" == *aarch64* ]]; then ./tools/buildman/buildman 
--fetch-arch aarch64 ; fi
   - if [[ "${TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman 
--fetch-arch avr32 ; fi
   - if [[ "${TOOLCHAIN}" == *bfin* ]]; then ./tools/buildman/buildman 
--fetch-arch bfin ; fi
   - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman 
--fetch-arch m68k ; fi
@@ -113,7 +113,8 @@ matrix:
 - env:
 - BUILDMAN="denx"
 - env:
-- BUILDMAN="freescale -x powerpc,m68k,aarch64"
+- JOB="Freescale ARM"
+  BUILDMAN="freescale -x powerpc,m68k"
 - env:
 - BUILDMAN="sandbox x86"
   TOOLCHAIN="x86_64"
@@ -155,11 +156,13 @@ matrix:
 - env:
 - BUILDMAN="siemens"
 - env:
-- BUILDMAN="tegra -x aarch64"
+- BUILDMAN="tegra"
 - env:
 - BUILDMAN="ti"
 - env:
-- BUILDMAN="aarch64"
+- BUILDMAN="uniphier"
+- env:
+- BUILDMAN="aarch64 -x tegra,freescale,uniphier"
   TOOLCHAIN="aarch64"
 - env:
 - BUILDMAN="sh4"
-- 
1.9.1

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Re: [U-Boot] [RFC] 0/4] Add Pl330 DMA support

2016-10-29 Thread Marek Vasut

On 10/18/2016 05:50 PM, Dinh Nguyen wrote:
> On Sun, Oct 16, 2016 at 10:59 AM, Marek Vasut  wrote:
>> On 10/15/2016 12:10 AM, Dinh Nguyen wrote:
>>>
>>>
>>> On 10/10/2016 10:52 AM, Dinh Nguyen wrote:
 Hi,

 This patchset adds the PL330 DMA driver to U-Boot. The SoCFPGA platform 
 makes
 use of the PL330 to transfer zereos to the SDRAM which enables the ECC bit.

 This is only an RFC because after rebasing to v2016.11-rc1, I had to revert
 the following patch "a78cd8613204 ARM: Rework and correct barrier 
 definitions"
 in order for this patch set to work correctly. With the above patch 
 applied,
 after the SDRAM scrubbing is complete, the SPL is failing to find the MMC
 device.

>>>
>>> I kinda figured out why patch "a78cd8613204 ARM: Rework and correct
>>> barrier definitions" is causing SPL to fail after the SDRAM scrub
>>> operation. It appears that before the above mentioned patch, the dmb()
>>> operation is defined as this:
>>>
>>> #define dmb()  __asm__ __volatile__ ("" : : : "memory")
>>>
>>> after the patch, the dmb is now:
>>>
>>> #define DMBasm volatile ("dmb sy" : : : "memory")
>>>
>>> So the "dmb sy" as described in the ARM documentation is a "Full system
>>> DMB operation". For whatever reason, this change is causing the SPL
>>> error after the SDRAM scrub operation.
>>
>> Thanks for looking into this, can you poke into it some more ?
>>
> 
> Of course..

The patch is causing a failure even in normal operation -- if you boot
the socfpga board and type "reset", it won't reset with the patch.

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH] engicam: icorem6: Fix config files

2016-10-29 Thread Jagan Teki

From: Jagan Teki 

Config file names on MAINTAINERS and README in
board/engicam/icorem6 seems to be wrong, hence fixed the same.

Cc: Stefano Babic 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 board/engicam/icorem6/MAINTAINERS | 5 +++--
 board/engicam/icorem6/README  | 2 +-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/board/engicam/icorem6/MAINTAINERS 
b/board/engicam/icorem6/MAINTAINERS
index 3e06c6b..a425afb 100644
--- a/board/engicam/icorem6/MAINTAINERS
+++ b/board/engicam/icorem6/MAINTAINERS
@@ -2,5 +2,6 @@ ICOREM6QDL BOARD
 M: Jagan Teki 
 S: Maintained
 F: board/engicam/icorem6
-F: include/configs/icorem6qdl.h
-F: configs/icorem6qdl_defconfig
+F: include/configs/imx6qdl_icore.h
+F: configs/imx6qdl_icore_mmc_defconfig
+F: configs/imx6qdl_icore_nand_defconfig
diff --git a/board/engicam/icorem6/README b/board/engicam/icorem6/README
index 12d1e21..e47f85f 100644
--- a/board/engicam/icorem6/README
+++ b/board/engicam/icorem6/README
@@ -4,7 +4,7 @@ How to use U-Boot on Engicam i.CoreM6 DualLite/Solo and 
Quad/Dual Starter Kit:
 - Configure U-Boot for Engicam i.CoreM6 QDL:
 
 $ make mrproper
-$ make icorem6qdl_mmc_defconfig
+$ make imx6qdl_icore_mmc_defconfig
 
 - Build for i.CoreM6 DualLite/Solo
 
-- 
2.7.4

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[U-Boot] [PATCH] MAINTAINERS: SUNXI: Add Jagan as Co-Maintainer

2016-10-29 Thread Jagan Teki

Due to the discussion from thread[1] about the Hans
stepping down as sunix custodian, I would like to
volunteer as a co-maintainer for sunxi and discussed
the same with Hans as well.

[1] http://lists.denx.de/pipermail/u-boot/2016-July/259688.html

Cc: Maxime Ripard 
Cc: Ian Campbell 
Cc: Hans De Goede 
Signed-off-by: Jagan Teki 
---
 MAINTAINERS| 1 +
 doc/git-mailrc | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 0bd8995..c96625a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -169,6 +169,7 @@ F:  arch/arm/include/asm/arch-stv0991/
 ARM SUNXI
 M: Ian Campbell 
 M: Hans De Goede 
+M: Jagan Teki 
 S: Maintained
 T: git git://git.denx.de/u-boot-sunxi.git
 F: arch/arm/cpu/armv7/sunxi/
diff --git a/doc/git-mailrc b/doc/git-mailrc
index d01a8c7..9e26c4d 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -70,7 +70,7 @@ alias s5pc   samsung
 alias samsunguboot, prom
 alias snapdragon uboot, mateusz
 alias socfpgauboot, marex, Dinh Nguyen 
-alias sunxi  uboot, ijc, jwrdegoede
+alias sunxi  uboot, ijc, jwrdegoede, jagan
 alias tegra  uboot, sjg, Tom Warren , Stephen 
Warren 
 alias tegra2 tegra
 alias ti uboot, trini
-- 
2.7.4

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[U-Boot] [PULL] u-boot-socfpga/master

2016-10-29 Thread Marek Vasut

The following changes since commit 5ac5861c4ba851b473e6a24940b412b397627d8d:

  travis-ci: Add test.py for various qemu platforms (2016-10-24 08:06:29
-0400)

are available in the git repository at:

  git://git.denx.de/u-boot-socfpga.git master

for you to fetch changes up to 4f9378cf67c657c8de20284ed1be8be38a6e47bc:


  dm: mmc: socfpga: fix MMC_OPS support (2016-10-28 04:21:21 +0200)





Chin Liang See (9):

  ddr: altera: Configuring SDRAM extra cycles timing parameters

  arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1
  arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1
  arm: socfpga: socrates: Adding handoff for SDRAM ctrlcfg.extratime1
  arm: socfpga: is1: Adding handoff for SDRAM ctrlcfg.extratime1
  arm: socfpga: vining_fpga: Adding handoff for SDRAM ctrlcfg.extratime1
  arm: socfpga: sr1500: Adding handoff for SDRAM ctrlcfg.extratime1
  arm: socfpga: de0-nano-soc: Adding handoff for SDRAM
ctrlcfg.extratime1
  arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1

Sylvain Lesne (1):
  dm: mmc: socfpga: fix MMC_OPS support

 arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++-
 arch/arm/mach-socfpga/qts-filter.sh| 2 +-
 arch/arm/mach-socfpga/wrap_sdram_config.c  | 7 +++
 board/altera/arria5-socdk/qts/sdram_config.h   | 3 +++
 board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++
 board/denx/mcvevk/qts/sdram_config.h   | 3 +++
 board/ebv/socrates/qts/sdram_config.h  | 3 +++
 board/is1/qts/sdram_config.h   | 3 +++
 board/samtec/vining_fpga/qts/sdram_config.h| 3 +++
 board/sr1500/qts/sdram_config.h| 3 +++
 board/terasic/de0-nano-soc/qts/sdram_config.h  | 3 +++
 board/terasic/sockit/qts/sdram_config.h| 3 +++
 drivers/ddr/altera/sdram.c | 3 +++
 drivers/mmc/socfpga_dw_mmc.c   | 2 ++
 14 files changed, 47 insertions(+), 2 deletions(-)
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[U-Boot] [PULL] u-boot-usb/master

2016-10-29 Thread Marek Vasut

The following changes since commit 5ac5861c4ba851b473e6a24940b412b397627d8d:

  travis-ci: Add test.py for various qemu platforms (2016-10-24 08:06:29
-0400)

are available in the git repository at:

  git://git.denx.de/u-boot-usb.git master

for you to fetch changes up to 57faca19a82fc9b43a227824c30aeb76a43d1957:

  drivers: USB: OHCI: allow compilation for 64-bit targets (2016-10-29
19:45:40 +0200)


Andre Przywara (1):
  drivers: USB: OHCI: allow compilation for 64-bit targets

Masahiro Yamada (2):
  usb: ehci-vf: use ehci_deregister() for .remove callback
  usb: xhci-mvebu: use xhci_deregister() for .remove callback

 drivers/usb/host/ehci-vf.c| 13 +
 drivers/usb/host/ohci-hcd.c   | 21 +++--
 drivers/usb/host/ohci-sunxi.c |  2 +-
 drivers/usb/host/ohci.h   | 11 +++
 drivers/usb/host/xhci-mvebu.c |  7 +--
 5 files changed, 21 insertions(+), 33 deletions(-)
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Re: [U-Boot] [U-Boot, 1/2] drivers: USB: OHCI: allow compilation for 64-bit targets

2016-10-29 Thread Marek Vasut

On 10/29/2016 02:50 PM, Hans de Goede wrote:
> Hi,
> 
> On 21-10-16 03:24, Andre Przywara wrote:
>> OHCI has a known limitation of allowing only 32-bit DMA buffer
>> addresses, so we have a lot of u32 variables around, which are assigned
>> to pointers and vice versa. This obviously creates issues with 64-bit
>> systems, so the compiler complains here and there.
>> To allow compilation for 64-bit boards which use only memory below 4GB
>> anyway (and to avoid more invasive fixes), adjust some casts and types
>> and assume that the EDs and TDs are all located in the lower 4GB.
>> This fixes compilation of the OHCI driver for the Pine64.
>>
>> Signed-off-by: Andre Przywara 
> 
> Patch looks good to me:
> 
> Reviewed-by: Hans de Goede 

Applied, thanks.

Andre, it would be nice if you CC'd me on the original submission.

> Regards,
> 
> Hans
> 
> p.s.
> 
> About the ohci_writel macro changes also giving the macro parameters
> more sensible names, I believe it is fine to do this while at it and
> that this does not need to be split out.

Indeed, I am fine with it as well.

-- 
Best regards,
Marek Vasut
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[U-Boot] OMAP3630 Falcon Mode Questions

2016-10-29 Thread Adam Ford

I am trying to utilize Falcon mode on an OMAP3630 (DM3730), but it
just hangs, and I was hoping someone might find something obvious that
I missed.  I am able to boot from NAND through U-boot, so I know my
kernel and device tree are OK as are the boot parameters, MLO and
U-boot.

I have read through the ./doc/README.falcon, and I read through some
of the am33 docs regarding this, and I think I'm doing it right, but
I'm obviously missing something.

I have reset my partition structure to:
device nand0 , # parts = 6
 #: namesizeoffset  mask_flags
 0: MLO 0x0008  0x  0
 1: u-boot  0x001c  0x0008  0
 2: spl-os  0x0002  0x0024  0
 3: u-boot-env  0x0002  0x0026  0
 4: kernel  0x0080  0x0028  0
 5: fs  0x1f58  0x00a8  0

My defines in the header file are set as follows:

#define CONFIG_CMD_SPL_NAND_OFS 0x24
(matches spl-os offset)

#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x28
(matches kernel offset)

#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000


#define CONFIG_SYS_TEXT_BASE 0x8010
#define CONFIG_SPL_BSS_START_ADDR 0x8000
#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10


I build my uImage with LOADADDR=0x80008000

My bootargs are as follows:
console=ttyO0,115200n8 ignore_loglevel early_printk no_console_suspend
root=ubi0:rootfs rw ubi.mtd=fs noinitrd rootfstype=ubifs rootwait
display=15 ignore_loglevel early_printk no_console_suspend
mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),8m(kernel),-(fs)


I can load uImage and fdtimage, then with the bootargs set, I run

spl export fdt $loadaddr - $fdtaddr

## Booting kernel from Legacy Image at 8100 ...
   Image Name:   Linux-4.9.0-rc2-00040-g9fe68ca-d
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:3869952 Bytes = 3.7 MiB
   Load Address: 80008000
   Entry Point:  80008000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 8600
   Booting using the fdt blob at 0x8600
   Loading Kernel Image ... OK
   Loading Device Tree to 8df1f000, end 8df33114 ... OK
subcommand not supported
subcommand not supported
   Loading Device Tree to 8df07000, end 8df1e114 ... OK
Argument image is now in RAM: 0x8df07000

I then write this blob to my spl-os partition with the following:

nand write 0x8df07000 spl-os 0x2

When I eject the SD card and I boot from NAND (attempting) with Falcon
it just hangs:

U-Boot SPL 2016.11-rc2-00164-g7904673-dirty (Oct 29 2016 - 10:28:32)
Trying to boot from NAND

Does anyone know if I missed a step somewhere, or do I have something
configured incorrectly?

I don't think it's an ECC issue, because I can boot to and read/write
from the UBI partition from Linux going through U-boot.

adam
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Re: [U-Boot] [PATCH v2 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-10-29 Thread Marek Vasut

On 10/29/2016 07:47 PM, Tom Rini wrote:
> On Sat, Oct 29, 2016 at 07:44:34PM +0200, Marek Vasut wrote:
>> On 10/29/2016 07:41 PM, Tom Rini wrote:
>>> On Sat, Oct 29, 2016 at 03:19:10PM +0530, Keerthy wrote:
>>>
 While we setup the mmu initially we mark set_section_dcache with
 DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
 is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
 4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
 DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
 keeps all the regions execute okay and this leads to random speculative
 fetches in random memory regions which was eventually caught by kernel
 omap-l3-noc driver.

 Fix this to mark the regions as XN by default.

 Signed-off-by: Keerthy 
 Reviewed-by: Alexander Graf 
>>>
>>> Reviewed-by: Tom Rini 
>>>
>> Isn't this patch exactly undoing the following one ?
>>
>> commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
>> Author: Marek Vasut <>
>> Date:   Tue Dec 29 19:44:02 2015 +0100
>>
>> arm: Remove S bit from MMU section entry
>>
>> Restore the old behavior of the MMU section entries configuration,
>> which is without the S-bit.
> 
> Is it?  I guess perhaps you and Keerthy need to chat then as there's
> some other problem they're addressing.

U, wait a second, I think this one adds XN bit and the previous one
removed S bit. I think I was wrong, but please double-check this. I
recall we had some odd cache issues on V7 back then.

-- 
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Marek Vasut
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Re: [U-Boot] [PATCH v2 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-10-29 Thread Tom Rini

On Sat, Oct 29, 2016 at 07:44:34PM +0200, Marek Vasut wrote:
> On 10/29/2016 07:41 PM, Tom Rini wrote:
> > On Sat, Oct 29, 2016 at 03:19:10PM +0530, Keerthy wrote:
> > 
> >> While we setup the mmu initially we mark set_section_dcache with
> >> DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
> >> is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
> >> 4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
> >> DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
> >> keeps all the regions execute okay and this leads to random speculative
> >> fetches in random memory regions which was eventually caught by kernel
> >> omap-l3-noc driver.
> >>
> >> Fix this to mark the regions as XN by default.
> >>
> >> Signed-off-by: Keerthy 
> >> Reviewed-by: Alexander Graf 
> > 
> > Reviewed-by: Tom Rini 
> > 
> Isn't this patch exactly undoing the following one ?
> 
> commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
> Author: Marek Vasut <>
> Date:   Tue Dec 29 19:44:02 2015 +0100
> 
> arm: Remove S bit from MMU section entry
> 
> Restore the old behavior of the MMU section entries configuration,
> which is without the S-bit.

Is it?  I guess perhaps you and Keerthy need to chat then as there's
some other problem they're addressing.

-- 
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Re: [U-Boot] [PATCH v2 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-10-29 Thread Marek Vasut

On 10/29/2016 07:41 PM, Tom Rini wrote:
> On Sat, Oct 29, 2016 at 03:19:10PM +0530, Keerthy wrote:
> 
>> While we setup the mmu initially we mark set_section_dcache with
>> DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
>> is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
>> 4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
>> DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
>> keeps all the regions execute okay and this leads to random speculative
>> fetches in random memory regions which was eventually caught by kernel
>> omap-l3-noc driver.
>>
>> Fix this to mark the regions as XN by default.
>>
>> Signed-off-by: Keerthy 
>> Reviewed-by: Alexander Graf 
> 
> Reviewed-by: Tom Rini 
> 
Isn't this patch exactly undoing the following one ?

commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
Author: Marek Vasut <>
Date:   Tue Dec 29 19:44:02 2015 +0100

arm: Remove S bit from MMU section entry

Restore the old behavior of the MMU section entries configuration,
which is without the S-bit.

-- 
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Re: [U-Boot] [PATCH] configs/chromebox_panther_defconfig: Re-enable CONFIG_DM_PCI

2016-10-29 Thread Tom Rini

On Sat, Oct 29, 2016 at 08:42:19AM -0400, Tom Rini wrote:

> This was turned off by accident, re-enble.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 6/6] travis-ci: compile with buildman when running test/py

2016-10-29 Thread Tom Rini

On Wed, Oct 26, 2016 at 11:05:36AM -0600, Stephen Warren wrote:

> From: Stephen Warren 
> 
> Use buildman to compile any U-Boot binary tested by test/py. This
> re-uses all the work done elsewhere to make buildman work within
> Travis-CI, in particular related to toolchain downloading and buildman
> config file creation.
> 
> Signed-off-by: Stephen Warren 
> Reviewed-by: Heiko Schocher 

Fixed the typo for qemu-x86 and applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH v2 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-10-29 Thread Tom Rini

On Sat, Oct 29, 2016 at 03:19:10PM +0530, Keerthy wrote:

> While we setup the mmu initially we mark set_section_dcache with
> DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
> is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
> 4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
> DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
> keeps all the regions execute okay and this leads to random speculative
> fetches in random memory regions which was eventually caught by kernel
> omap-l3-noc driver.
> 
> Fix this to mark the regions as XN by default.
> 
> Signed-off-by: Keerthy 
> Reviewed-by: Alexander Graf 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] MAINTAINERS: Update Jagan's email

2016-10-29 Thread Tom Rini

On Fri, Oct 28, 2016 at 11:27:34PM +0530, Jagan Teki wrote:

> Signed-off-by: Jagan Teki 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH v2 1/2] arm: print the cache config option in hex instead of decimal

2016-10-29 Thread Tom Rini

On Sat, Oct 29, 2016 at 03:19:09PM +0530, Keerthy wrote:

> Printing the option value in hex makes it more comprehensible.
> 
> Signed-off-by: Keerthy 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] travis-ci: build Tegra boards

2016-10-29 Thread Tom Rini

On Wed, Oct 26, 2016 at 01:05:52PM -0600, Stephen Warren wrote:

> From: Stephen Warren 
> 
> ARMv7 Tegra boards aren't currently covered by any other travis-ci jobs.
> Add a new job to build them.
> 
> Signed-off-by: Stephen Warren 
> Reviewed-by: Tom Rini 
> Reviewed-by: Heiko Schocher 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot,4/6] travis-ci: use buildman -P everywhere

2016-10-29 Thread Tom Rini

On Wed, Oct 26, 2016 at 11:05:34AM -0600, Stephen Warren wrote:

> From: Stephen Warren 
> 
> This places build results into a board-specific directory rather than a
> buildman-thread-specific directory. This is required so that we can
> access the directory from test.py, and there's no risk of a particular
> build's results being over-written by another build performed by the
> same thread.
> 
> In theory, this can lead to slower builds when building many different
> boards in a single buildman thread, since it removes the possibility of
> incremental builds between boards. In practice however I didn't notice
> longer build times when when enabling this option; if anything build
> times decreased although I suspect that's simply due to general
> variations in build performance across different machines within the
> Travis CI infra-structure.
> 
> Signed-off-by: Stephen Warren 
> Reviewed-by: Heiko Schocher 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot, 3/6] travis-ci: centralize ~/.buildman editing

2016-10-29 Thread Tom Rini

On Wed, Oct 26, 2016 at 11:05:33AM -0600, Stephen Warren wrote:

> From: Stephen Warren 
> 
> Any time an x86 toolchain is used, we need to edit ~/.buildman to
> reference it. Move the editing logic into a central place so that it
> doesn't have to be duplicated everywhere that uses the x86 toolchain;
> future patches will add additional cases where it's used.
> 
> It would be nice if we could unconditionally write all of ~/.buildman at
> once. Unfortunately, buildman fails if any toolchain mentioned in a
> toolchain-prefix entry doesn't exist, even if it doesn't need to use it
> for the current build.
> 
> The sandbox/x86 build definition currently does nothing more than edit
> ~/.buildman; no builds are run. Fix this by not defining a custom script
> for this build, and hence preventing that stanza from replacing the
> default script.
> 
> Signed-off-by: Stephen Warren 
> Reviewed-by: Heiko Schocher 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot,5/6] travis-ci: don't invoke exit on success

2016-10-29 Thread Tom Rini

On Wed, Oct 26, 2016 at 11:05:35AM -0600, Stephen Warren wrote:

> From: Stephen Warren 
> 
> Invoking exit prevents any subsequent build commands from running, and
> future patches will add extra commands.
> 
> Signed-off-by: Stephen Warren 
> Reviewed-by: Heiko Schocher 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot, 1/6] travis-ci: Use = not : when writing ~/.buildman

2016-10-29 Thread Tom Rini

On Wed, Oct 26, 2016 at 11:05:31AM -0600, Stephen Warren wrote:

> From: Stephen Warren 
> 
> Travis CI seems to be confused when there's a colon in an echo command,
> and this is currently worked around using a variable that contains the
> text we want to echo. Use = syntax instead so that we can remove the
> work-around; it's rather confusing until you find out what it's for.
> 
> Signed-off-by: Stephen Warren 
> Reviewed-by: Heiko Schocher 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot, 2/6] travis-ci: use correct exit code on errors

2016-10-29 Thread Tom Rini

On Wed, Oct 26, 2016 at 11:05:32AM -0600, Stephen Warren wrote:

> From: Stephen Warren 
> 
> The phrase "if [ $? -ne 0 ]; then exit $?; fi" doesn't work correctly;
> by the time the "exit" statement runs, $? has already been over-written
> by the result of the [ command. Fix this by explicitly storing $? and
> then using that stored value in both the test and the error-case exit
> statement.
> 
> This change also converts from textual comparison to integer comparison,
> since the exit code is an integer and there's no need to convert it to
> a string for comparison.
> 
> Signed-off-by: Stephen Warren 
> Reviewed-by: Heiko Schocher 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot,2/2] travis-ci: remove duplicate build

2016-10-29 Thread Tom Rini

On Mon, Oct 24, 2016 at 04:41:49PM -0600, Stephen Warren wrote:

> From: Stephen Warren 
> 
> There were two sub-jobs to build arm1136. Remove the duplicate.
> 
> Signed-off-by: Stephen Warren 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot,1/2] travis-ci: set env vars to name jobs

2016-10-29 Thread Tom Rini

On Mon, Oct 24, 2016 at 04:41:48PM -0600, Stephen Warren wrote:

> From: Stephen Warren 
> 
> Travis CI names sub-jobs after the first environment variable that is set
> for a script. This doesn't produce meaningful results for any of the non-
> buildman jobs. Add a dummy variable to give the jobs meaningful names.
> 
> Signed-off-by: Stephen Warren 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH] MAINTAINERS: Update Jagan's email

2016-10-29 Thread Jagan Teki

On Fri, Oct 28, 2016 at 11:27 PM, Jagan Teki  wrote:
> Signed-off-by: Jagan Teki 
> ---
>  MAINTAINERS| 2 +-
>  doc/git-mailrc | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8e67202..0bd8995 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -417,7 +417,7 @@ T:  git git://git.denx.de/u-boot-sparc.git
>  F: arch/sparc/
>
>  SPI
> -M: Jagan Teki 
> +M: Jagan Teki 
>  S: Maintained
>  T: git git://git.denx.de/u-boot-spi.git
>  F: drivers/mtd/spi/
> diff --git a/doc/git-mailrc b/doc/git-mailrc
> index a14629c..d01a8c7 100644
> --- a/doc/git-mailrc
> +++ b/doc/git-mailrc
> @@ -24,7 +24,7 @@ alias hs Heiko Schocher 
>  alias ijcIan Campbell 
>  alias iwamatsu   Nobuhiro Iwamatsu 
>  alias jaehoonJaehoon Chung 
> -alias jagan  Jagan Teki 
> +alias jagan  Jagan Teki 
>  alias jasonjin   Jason Jin 
>  alias jhersh Joe Hershberger 
>  alias jwrdegoede Hans de Goede 

Tom, can you apply this?

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [U-Boot,2/2] sunxi: A64: enable USB support

2016-10-29 Thread Hans de Goede


Hi,

On 21-10-16 03:24, Andre Przywara wrote:

From: Amit Singh Tomar 

Mostly by adding MACH_SUN50I to some existing #ifdefs enable support
for the the HCI0 USB host controller on the A64.
Fix up some minor 64-bit hiccups on the way.
Add the bare minimum DT bits to the A64 .dtsi and enable the controllers
and the PHY on the Pine64.
This is limited to the first USB controller at the moment, which is
connected to the lower USB socket on the Pine64 board.
[Andre: remove unneeded defines, enable OHCI, add commit message]

Signed-off-by: Amit Singh Tomar 
Signed-off-by: Andre Przywara 


Other then CONFIG_USB_MAX_CONTROLLER_COUNT no longer being necessary
(it should be dropped from include/configs/sun50i.h) this patch looks
good to me and is:

Reviewed-by: Hans de Goede 

Note I cannot merged it till Marek merges the first patch in
the series, which really needs to go through the u-boot-usb tree.

Regards,

Hans



---
 arch/arm/dts/sun50i-a64-pine64-common.dtsi  | 12 
 arch/arm/dts/sun50i-a64.dtsi| 29 +
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |  2 +-
 arch/arm/mach-sunxi/usb_phy.c   |  5 +++--
 configs/pine64_plus_defconfig   |  1 +
 drivers/usb/host/ehci-sunxi.c   |  7 ---
 drivers/usb/host/ohci-sunxi.c   |  1 +
 include/configs/sun50i.h|  5 +
 8 files changed, 56 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi 
b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
index c0fde44..9ec81c6 100644
--- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
@@ -79,3 +79,15 @@
pinctrl-0 = <_pins>;
status = "okay";
 };
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 7d0dc76..bef0d00 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -653,5 +653,34 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+   usbphy: phy@1c1b810 {
+   compatible = "allwinner,sun50i-a64-usb-phy",
+"allwinner,sun8i-a33-usb-phy";
+   reg = <0x01c1b810 0x14>, <0x01c1b800 0x4>;
+   reg-names = "phy_ctrl", "pmu1";
+   status = "disabled";
+   #phy-cells = <1>;
+   };
+
+   ehci1: usb@01c1b000 {
+   compatible = "allwinner,sun50i-a64-ehci",
+"generic-ehci";
+   reg = <0x01c1b000 0x100>;
+   interrupts = ;
+   phys = < 1>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
+   ohci1: usb@01c1b400 {
+   compatible = "allwinner,sun50i-a64-ohci",
+"generic-ohci";
+   reg = <0x01c1b400 0x100>;
+   interrupts = ;
+   phys = < 1>;
+   phy-names = "usb";
+   status = "enabled";
+   };
};
 };
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 5f93830..7232f6d 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -56,7 +56,7 @@
 #define SUNXI_USB2_BASE0x01c1c000
 #endif
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-#ifdef CONFIG_MACH_SUN8I_H3
+#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
 #define SUNXI_USBPHY_BASE  0x01c19000
 #define SUNXI_USB0_BASE0x01c1a000
 #define SUNXI_USB1_BASE0x01c1b000
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index bd1bbee..278587b 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -146,12 +146,13 @@ __maybe_unused static void usb_phy_write(struct 
sunxi_usb_phy *phy, int addr,
}
 }

-#if defined CONFIG_MACH_SUN8I_H3
+#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
 {
+#if defined CONFIG_MACH_SUN8I_H3
if (phy->id == 0)
clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
-
+#endif
clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
 }
 #elif defined CONFIG_MACH_SUN8I_A83T
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 6f82190..bd3e2e6 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -10,3 +10,4 @@

Re: [U-Boot] [U-Boot, 1/2] drivers: USB: OHCI: allow compilation for 64-bit targets

2016-10-29 Thread Hans de Goede


Hi,

On 21-10-16 03:24, Andre Przywara wrote:

OHCI has a known limitation of allowing only 32-bit DMA buffer
addresses, so we have a lot of u32 variables around, which are assigned
to pointers and vice versa. This obviously creates issues with 64-bit
systems, so the compiler complains here and there.
To allow compilation for 64-bit boards which use only memory below 4GB
anyway (and to avoid more invasive fixes), adjust some casts and types
and assume that the EDs and TDs are all located in the lower 4GB.
This fixes compilation of the OHCI driver for the Pine64.

Signed-off-by: Andre Przywara 


Patch looks good to me:

Reviewed-by: Hans de Goede 

Regards,

Hans

p.s.

About the ohci_writel macro changes also giving the macro parameters
more sensible names, I believe it is fine to do this while at it and
that this does not need to be split out.



---
 drivers/usb/host/ohci-hcd.c   | 21 +++--
 drivers/usb/host/ohci-sunxi.c |  2 +-
 drivers/usb/host/ohci.h   | 11 +++
 3 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index ccbfc02..0f6d03e 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -682,7 +682,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
ed->hwNextED = 0;
flush_dcache_ed(ed);
if (ohci->ed_controltail == NULL)
-   ohci_writel(ed, >regs->ed_controlhead);
+   ohci_writel((uintptr_t)ed, >regs->ed_controlhead);
else
ohci->ed_controltail->hwNextED =
   m32_swap((unsigned long)ed);
@@ -700,7 +700,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
ed->hwNextED = 0;
flush_dcache_ed(ed);
if (ohci->ed_bulktail == NULL)
-   ohci_writel(ed, >regs->ed_bulkhead);
+   ohci_writel((uintptr_t)ed, >regs->ed_bulkhead);
else
ohci->ed_bulktail->hwNextED =
   m32_swap((unsigned long)ed);
@@ -753,7 +753,7 @@ static void periodic_unlink(struct ohci *ohci, volatile 
struct ed *ed,

/* ED might have been unlinked through another path */
while (*ed_p != 0) {
-   if (((struct ed *)
+   if (((struct ed *)(uintptr_t)
m32_swap((unsigned long)ed_p)) == ed) {
*ed_p = ed->hwNextED;
aligned_ed_p = (unsigned long)ed_p;
@@ -762,7 +762,7 @@ static void periodic_unlink(struct ohci *ohci, volatile 
struct ed *ed,
aligned_ed_p + ARCH_DMA_MINALIGN);
break;
}
-   ed_p = &(((struct ed *)
+   ed_p = &(((struct ed *)(uintptr_t)
 m32_swap((unsigned long)ed_p))->hwNextED);
}
}
@@ -798,7 +798,7 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi)
if (ohci->ed_controltail == ed) {
ohci->ed_controltail = ed->ed_prev;
} else {
-   ((ed_t *)m32_swap(
+   ((ed_t *)(uintptr_t)m32_swap(
*((__u32 *)>hwNextED)))->ed_prev = ed->ed_prev;
}
break;
@@ -819,7 +819,7 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi)
if (ohci->ed_bulktail == ed) {
ohci->ed_bulktail = ed->ed_prev;
} else {
-   ((ed_t *)m32_swap(
+   ((ed_t *)(uintptr_t)m32_swap(
 *((__u32 *)>hwNextED)))->ed_prev = ed->ed_prev;
}
break;
@@ -914,12 +914,13 @@ static void td_fill(ohci_t *ohci, unsigned int info,

/* fill the old dummy TD */
td = urb_priv->td [index] =
-(td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf);
+(td_t *)(uintptr_t)
+(m32_swap(urb_priv->ed->hwTailP) & ~0xf);

td->ed = urb_priv->ed;
td->next_dl_td = NULL;
td->index = index;
-   td->data = (__u32)data;
+   td->data = (uintptr_t)data;
 #ifdef OHCI_FILL_TRACE
if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
for (i = 0; i < len; i++)
@@ -1099,7 +1100,7 @@ static void check_status(td_t *td_list)
  * we reverse the reversed done-list */
 static td_t *dl_reverse_done_list(ohci_t *ohci)
 {
-   __u32 td_list_hc;
+   uintptr_t td_list_hc;
td_t *td_rev = NULL;
td_t *td_list = NULL;

@@ -1862,7 +1863,7 @@ static int hc_start(ohci_t *ohci)
ohci_writel(0,

[U-Boot] [PATCH] configs/chromebox_panther_defconfig: Re-enable CONFIG_DM_PCI

2016-10-29 Thread Tom Rini

This was turned off by accident, re-enble.

Signed-off-by: Tom Rini 
---
 configs/chromebox_panther_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/chromebox_panther_defconfig 
b/configs/chromebox_panther_defconfig
index b8248218cb3d..8bf94cbd83f9 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -40,6 +40,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_RTL8169=y
+CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_SYS_NS16550=y
 CONFIG_ICH_SPI=y
-- 
1.9.1

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Re: [U-Boot] [PATCH v1 1/1] ARM:SUNXI: Update DRAM clock for Olimex A20 boards

2016-10-29 Thread Hans de Goede


Hi,

On 27-10-16 12:33, Stefan Mavrodiev wrote:

Hi,

I've notice that you've reduced DRAM clock for Lime2 and Lime, but not for 
A20-SOM.

Is there any specific reason for this?


Sorry, as I mentioned I had received a patch similar to
yours and I had already merged that patch. I did not
notice that your patch also modified the A20-SOM
where as the patch I merged did not.

I've added the A20-SOM part of your patch (with you
as the author) to my tree now and will include it
in my next pull-req.

Regards,

Hans





Regards,

Stefan Mavrodiev

Olimex LDT


On 10/11/2016 12:38 PM, Hans de Goede wrote:

Hi,

On 10/11/2016 10:44 AM, Stefan Mavrodiev wrote:

Originally dram clock was set to 480MHz, but this behaves
unstable. To improve stability the clock is reduced to 384MHz

Signed-off-by: Stefan Mavrodiev 


The exact same change is already in u-boot-sunxi/next, and I've already
send out a pullreq to get this merged.

Regards,

Hans


---
 configs/A20-OLinuXino-Lime2_defconfig | 2 +-
 configs/A20-OLinuXino-Lime_defconfig  | 2 +-
 configs/A20-Olimex-SOM-EVB_defconfig  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/configs/A20-OLinuXino-Lime2_defconfig 
b/configs/A20-OLinuXino-Lime2_defconfig
index 5688622..4751fe0 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
diff --git a/configs/A20-OLinuXino-Lime_defconfig 
b/configs/A20-OLinuXino-Lime_defconfig
index c4f6e1a..024dc2d 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig 
b/configs/A20-Olimex-SOM-EVB_defconfig
index 7a14a7b..3f4e90d 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH0"
 CONFIG_MMC3_PINS="PH"




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Re: [U-Boot] [PATCH] tools: add mksunxiboot to tools-all target

2016-10-29 Thread Hans de Goede


Hi,

On 29-10-16 12:23, Stefan Brüns wrote:

mksunxiboot is useful outside of u-boot, it is e.g. used by sunxi-tools.

Signed-off-by: Stefan Brüns 



Thank you I've applied this to my tree and will
include it in my next pull-req.

Regards,

Hans





---
 tools/Makefile  | 1 +
 tools/mksunxiboot.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/tools/Makefile b/tools/Makefile
index e6f7993..8e6dede 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -13,6 +13,7 @@ CONFIG_CMD_NET = y
 CONFIG_XWAY_SWAP_BYTES = y
 CONFIG_NETCONSOLE = y
 CONFIG_SHA1_CHECK_UB_IMG = y
+CONFIG_SUNXI = y
 endif

 subdir-$(HOST_TOOLS_ALL) += easylogo
diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
index 9c1c5b7..0f0b003 100644
--- a/tools/mksunxiboot.c
+++ b/tools/mksunxiboot.c
@@ -15,7 +15,7 @@
 #include 
 #include 
 #include 
-#include "asm/arch/spl.h"
+#include "../arch/arm/include/asm/arch-sunxi/spl.h"

 #define STAMP_VALUE 0x5F0A6C39



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Re: [U-Boot] [linux-sunxi] [PATCH] arm: dts: Pine64: add Ethernet alias

2016-10-29 Thread Hans de Goede


Hi,

On 21-10-16 02:11, Andre Przywara wrote:

The sun8i-emac driver works fine with the A64 Ethernet IP, but we are
missing an alias entry to trigger the driver instantiation by U-Boot.
Add the line to point U-Boot to the Ethernet DT node.
This enables TFTP boot on the Pine64.

Signed-off-by: Andre Przywara 



Thank you I've applied this to my tree and will
include it in my next pull-req.

Regards,

Hans





---
 arch/arm/dts/sun50i-a64-pine64-common.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi 
b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
index d5a7249..c0fde44 100644
--- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
@@ -46,6 +46,7 @@

aliases {
serial0 = 
+   ethernet0 = 
};

soc {


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Re: [U-Boot] [PATCH 3/3] ARM: sunxi: remove unneeded CONFIG_USB_MAX_CONTROLLER_COUNT defines

2016-10-29 Thread Hans de Goede


Hi,

On 13-10-16 17:40, Masahiro Yamada wrote:

ARCH_SUNXI selects DM_USB, where CONFIG_USB_MAX_CONTROLLER_COUNT
is not used.

Signed-off-by: Masahiro Yamada 


Thank you I've applied this to my tree and will
include it in my next pull-req.

Regards,

Hans



---

 include/configs/sun4i.h | 1 -
 include/configs/sun5i.h | 1 -
 include/configs/sun6i.h | 1 -
 include/configs/sun7i.h | 1 -
 include/configs/sun8i.h | 1 -
 5 files changed, 5 deletions(-)

diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h
index ea079eb..3dfd95a 100644
--- a/include/configs/sun4i.h
+++ b/include/configs/sun4i.h
@@ -14,7 +14,6 @@

 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT2
 #endif

 #define CONFIG_SUNXI_USB_PHYS  3
diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
index d257659..ec8f319 100644
--- a/include/configs/sun5i.h
+++ b/include/configs/sun5i.h
@@ -14,7 +14,6 @@

 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT1
 #endif

 #define CONFIG_SUNXI_USB_PHYS  2
diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h
index 67a26c2..6c1eca4 100644
--- a/include/configs/sun6i.h
+++ b/include/configs/sun6i.h
@@ -17,7 +17,6 @@

 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT2
 #endif

 #define CONFIG_SUNXI_USB_PHYS  3
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index d8e6e20..5455901 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -15,7 +15,6 @@

 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT2
 #endif

 #define CONFIG_SUNXI_USB_PHYS  3
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index 011d70f..a4c3fb6 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -15,7 +15,6 @@

 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT1
 #endif

 #ifdef CONFIG_MACH_SUN8I_H3


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Re: [U-Boot] [PATCH] sunxi: Rename CONFIG_SUNXI to CONFIG_ARCH_SUNXI

2016-10-29 Thread Hans de Goede


Hi,

On 13-10-16 10:49, Jagan Teki wrote:

CONFIG_SUNXI -> CONFIG_ARCH_SUNXI
and removed CONFIG_SUNIX from config_whitelist.txt

Cc: Simon Glass 
Cc: Ian Campbell 
Cc: Hans de Goede 
Signed-off-by: Jagan Teki 


Thank you I've applied this to my tree and will
include it in my next pull-req.

Regards,

Hans



---
 Makefile   | 2 +-
 arch/arm/cpu/armv7/Makefile| 2 +-
 drivers/i2c/mvtwsi.c   | 6 +++---
 include/configs/sunxi-common.h | 1 -
 scripts/Makefile.spl   | 2 +-
 scripts/config_whitelist.txt   | 1 -
 tools/Makefile | 2 +-
 7 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/Makefile b/Makefile
index dcba7db..e88c8b3 100644
--- a/Makefile
+++ b/Makefile
@@ -1096,7 +1096,7 @@ u-boot-x86-16bit.bin: u-boot FORCE
$(call if_changed,objcopy)
 endif

-ifneq ($(CONFIG_SUNXI),)
+ifneq ($(CONFIG_ARCH_SUNXI),)
 OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
   --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
 u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 0d4bfbc..d182200 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -12,7 +12,7 @@ obj-y += cache_v7.o cache_v7_asm.o
 obj-y  += cpu.o cp15.o
 obj-y  += syslib.o

-ifneq 
($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
+ifneq 
($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y  += lowlevel_init.o
 endif
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 60c8ea1..cea3da0 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #include 
 #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
 #include 
-#elif defined(CONFIG_SUNXI)
+#elif defined(CONFIG_ARCH_SUNXI)
 #include 
 #else
 #error Driver mvtwsi not supported by SoC or board
@@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR;
  * TWSI register structure
  */

-#ifdef CONFIG_SUNXI
+#ifdef CONFIG_ARCH_SUNXI

 struct  mvtwsi_registers {
u32 slave_address;
@@ -399,7 +399,7 @@ static int twsi_stop(struct mvtwsi_registers *twsi, uint 
tick)
  */
 static uint twsi_calc_freq(const int n, const int m)
 {
-#ifdef CONFIG_SUNXI
+#ifdef CONFIG_ARCH_SUNXI
return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
 #else
return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index d261fb3..a6ca80a 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -35,7 +35,6 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_SUNXI   /* sunxi family */
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */
 #endif
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index e8cf9f3..e0b0117 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -166,7 +166,7 @@ ifdef CONFIG_ARCH_SOCFPGA
 ALL-y  += $(obj)/$(SPL_BIN).sfp
 endif

-ifdef CONFIG_SUNXI
+ifdef CONFIG_ARCH_SUNXI
 ALL-y  += $(obj)/sunxi-spl.bin
 endif

diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 3621c91..5dc2ed7 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4372,7 +4372,6 @@ CONFIG_STV0991_HZ
 CONFIG_STV0991_HZ_CLOCK
 CONFIG_ST_SMI
 CONFIG_SUN4
-CONFIG_SUNXI
 CONFIG_SUNXI_AHCI
 CONFIG_SUNXI_EMAC
 CONFIG_SUNXI_GMAC
diff --git a/tools/Makefile b/tools/Makefile
index e6f7993..556f397 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -169,7 +169,7 @@ hostprogs-$(CONFIG_MX23) += mxsboot
 hostprogs-$(CONFIG_MX28) += mxsboot
 HOSTCFLAGS_mxsboot.o := -pedantic

-hostprogs-$(CONFIG_SUNXI) += mksunxiboot
+hostprogs-$(CONFIG_ARCH_SUNXI) += mksunxiboot

 hostprogs-$(CONFIG_NETCONSOLE) += ncb
 hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1


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Re: [U-Boot] [PATCH 00/11] sunxi: Add full SPL support for sun9i (A80)

2016-10-29 Thread Hans de Goede


Hi,

On 29-10-16 03:16, Chen-Yu Tsai wrote:

On Sat, Oct 29, 2016 at 1:30 AM, Hans de Goede  wrote:

Hi Chen-Yu,

On 28-10-16 12:21, Chen-Yu Tsai wrote:


Hi everyone,

This series adds full SPL with DRAM initialization for sun9i (A80).
The bulk of the work was done by the people at Theobroma Systems.
Their work can be found here:

https://git.theobroma-systems.com/armadillo-u-boot.git/

I picked the essential patches and cleaned them up a bit more,
and added commit messages if they were missing.

As the DRAM bits are essentially a code dump with some cleanups and
some bits disabled, expect many warnings. Checkpatch is still not
happy with it.

I've tested the series on both my A80 boards, which I've added
defconfigs for in the last 2 patches. My A80 Optimus does not
boot from micro SD, so I'm still FEL booting that one. But my
Cubieboard 4 is now standalone.

As usual, please have a look, test if possible.



Awesome, thanks for doing this and it was good to have
some face2face time at ELCE.

I've merged this into my personal sunxi-wip u-boot branch,
I've made 2 changes:

1) in : ¨sunxi: DRAM initialisation for sun9i" there are a
lot of #if 0 #endif blocks, most of these document some features
which we may want to enable in the future, but a few were just
dead weight IMHO, so I've pruned a few


Thanks. I suppose some of the testing and verbose debug calls
aren't needed. Most of the #if 0 blocks within data structures
were C99 // comments that I fixed up to get checkpatch happy.

About the features, I was already half way through the clock
code cleanup when Maxime pointed me to Theobroma's repository,
so I could add and test sigma delta modulation for PLL DDR.


If you want to, I would be fine with adding that, but IIRC
we are not doing that on a number of other SoC generations
either, not sure what this would bring it us. So it is up to
you.


For the other types of DRAM we could clean it up, but there's
really no hardware to test it on.


I would not bother with this until someone with the relevant
hardware comes forward.


2) in : "sunxi: Add support for A80 Optimus board", we already
have a configs/Merrii_A80_Optimus_defconfig, so I've made the patch
update that instead of adding a new defconfig


Cool. I didn't notice.


I have not tested this yet, I will do tomorrow, assuming it
works for me too I will include it in my next pull-req (*) and
try to get it included in the 2016.11 release, yes the merge
window has closed, but the changes here are very isolated so
I will try and see what Tom says :)


Do you need me to send a v2 addressing review comments?


No need, I've fixed everything up in my own tree.

Regards,

Hans





Thanks
ChenYu



Regards,

Hans


*) Which I hope to send out this weekend







Regards
ChenYu


Chen-Yu Tsai (5):
  sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80)
  sunxi: Add support for SID e-fuses on sun9i
  sunxi: Add default zq value for sun9i (A80)
  sunxi: Add support for A80 Optimus board
  sunxi: Add support for Cubieboard4

Philipp Tomsich (6):
  sunxi: DRAM initialisation for sun9i
  sunxi: add gtbus-initialisation for sun9i
  sunxi: Enable SMP mode for the boot CPU on sun9i (A80)
  sunxi: add initial clock setup for sun9i for SPL
  sunxi: enable SPL for sun9i
  sunxi: add MMC pinmux setup for SDC2 on sun9i

 arch/arm/include/asm/arch-sunxi/clock_sun9i.h |  116 ++-
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |   10 +
 arch/arm/include/asm/arch-sunxi/dram.h|2 +
 arch/arm/include/asm/arch-sunxi/dram_sun9i.h  |  275 +++
 arch/arm/include/asm/arch-sunxi/gtbus.h   |   21 +
 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h |   89 +++
 arch/arm/mach-sunxi/Makefile  |2 +
 arch/arm/mach-sunxi/board.c   |3 +-
 arch/arm/mach-sunxi/clock.c   |6 +
 arch/arm/mach-sunxi/clock_sun9i.c |  146 +++-
 arch/arm/mach-sunxi/dram_sun9i.c  | 1059
+
 arch/arm/mach-sunxi/gtbus_sun9i.c |   48 ++
 board/sunxi/Kconfig   |   10 +-
 board/sunxi/MAINTAINERS   |   10 +
 board/sunxi/board.c   |7 +
 configs/A80_Optimus_defconfig |   18 +
 configs/Cubieboard4_defconfig |   18 +
 17 files changed, 1818 insertions(+), 22 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
 create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c
 create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c
 create mode 100644 configs/A80_Optimus_defconfig
 create mode 100644 configs/Cubieboard4_defconfig




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Re: [U-Boot] [PATCH 00/11] sunxi: Add full SPL support for sun9i (A80)

2016-10-29 Thread Hans de Goede


Hi,

On 28-10-16 19:30, Hans de Goede wrote:

Hi Chen-Yu,

On 28-10-16 12:21, Chen-Yu Tsai wrote:

Hi everyone,

This series adds full SPL with DRAM initialization for sun9i (A80).
The bulk of the work was done by the people at Theobroma Systems.
Their work can be found here:

https://git.theobroma-systems.com/armadillo-u-boot.git/

I picked the essential patches and cleaned them up a bit more,
and added commit messages if they were missing.

As the DRAM bits are essentially a code dump with some cleanups and
some bits disabled, expect many warnings. Checkpatch is still not
happy with it.

I've tested the series on both my A80 boards, which I've added
defconfigs for in the last 2 patches. My A80 Optimus does not
boot from micro SD, so I'm still FEL booting that one. But my
Cubieboard 4 is now standalone.

As usual, please have a look, test if possible.


Awesome, thanks for doing this and it was good to have
some face2face time at ELCE.

I've merged this into my personal sunxi-wip u-boot branch,
I've made 2 changes:

1) in : ¨sunxi: DRAM initialisation for sun9i" there are a
lot of #if 0 #endif blocks, most of these document some features
which we may want to enable in the future, but a few were just
dead weight IMHO, so I've pruned a few

2) in : "sunxi: Add support for A80 Optimus board", we already
have a configs/Merrii_A80_Optimus_defconfig, so I've made the patch
update that instead of adding a new defconfig

I have not tested this yet, I will do tomorrow, assuming it
works for me too I will include it in my next pull-req (*)


Ok, just finished testing, u-boot seems to work well. I do
seem to have one kernel issue (with the last 4.8 based
sunxi-next kernel, I still need to upgrade that) :

[1.137105] Division by zero in kernel.
[1.140988] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.0+ #475
[1.147089] Hardware name: Allwinner sun9i Family
[1.151830] [] (unwind_backtrace) from [] 
(show_stack+0x18/0x1c)
[1.159596] [] (show_stack) from [] 
(dump_stack+0x80/0x9c)
[1.166839] [] (dump_stack) from [] (Ldiv0+0x8/0x10)
[1.173558] [] (Ldiv0) from [] 
(sun4i_a10_get_mod0_factors+0x2c/0x8c)
[1.181758] [] (sun4i_a10_get_mod0_factors) from [] 
(clk_factors_determine_rate+0xb8/0xf8)
[1.191781] [] (clk_factors_determine_rate) from [] 
(clk_composite_determine_rate+0x58/0x1cc)
[1.202062] [] (clk_composite_determine_rate) from [] 
(clk_calc_new_rates+0xa0/0x240)
[1.211647] [] (clk_calc_new_rates) from [] 
(clk_core_set_rate_nolock+0x4c/0xbc)
[1.220798] [] (clk_core_set_rate_nolock) from [] 
(clk_set_rate+0x28/0x38)
[1.229432] [] (clk_set_rate) from [] 
(sunxi_ir_probe+0xfc/0x480)
[1.420454] [] (sunxi_ir_probe) from [] (platform_drv_pro
be+0x58/0xa4)

...

And it fails to find any mmc controllers, but that might be related to
the above oops (maybe it stops probing after that due to a stuck lock).

Anyways the u-boot side looks good. One issue I see is that your
optimus has an emmc, where as mine has a nand. We may want to
gave 2 optimus defconfigs for this once we've nand support.

Regards,

Hans



and try to get it included in the 2016.11 release, yes the merge
window has closed, but the changes here are very isolated so
I will try and see what Tom says :)

Regards,

Hans


*) Which I hope to send out this weekend






Regards
ChenYu


Chen-Yu Tsai (5):
  sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80)
  sunxi: Add support for SID e-fuses on sun9i
  sunxi: Add default zq value for sun9i (A80)
  sunxi: Add support for A80 Optimus board
  sunxi: Add support for Cubieboard4

Philipp Tomsich (6):
  sunxi: DRAM initialisation for sun9i
  sunxi: add gtbus-initialisation for sun9i
  sunxi: Enable SMP mode for the boot CPU on sun9i (A80)
  sunxi: add initial clock setup for sun9i for SPL
  sunxi: enable SPL for sun9i
  sunxi: add MMC pinmux setup for SDC2 on sun9i

 arch/arm/include/asm/arch-sunxi/clock_sun9i.h |  116 ++-
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |   10 +
 arch/arm/include/asm/arch-sunxi/dram.h|2 +
 arch/arm/include/asm/arch-sunxi/dram_sun9i.h  |  275 +++
 arch/arm/include/asm/arch-sunxi/gtbus.h   |   21 +
 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h |   89 +++
 arch/arm/mach-sunxi/Makefile  |2 +
 arch/arm/mach-sunxi/board.c   |3 +-
 arch/arm/mach-sunxi/clock.c   |6 +
 arch/arm/mach-sunxi/clock_sun9i.c |  146 +++-
 arch/arm/mach-sunxi/dram_sun9i.c  | 1059 +
 arch/arm/mach-sunxi/gtbus_sun9i.c |   48 ++
 board/sunxi/Kconfig   |   10 +-
 board/sunxi/MAINTAINERS   |   10 +
 board/sunxi/board.c   |7 +
 configs/A80_Optimus_defconfig |   18 +
 configs/Cubieboard4_defconfig |   18 +
 17 files changed, 1818 insertions(+), 22 deletions(-)
 create mode 100644

Re: [U-Boot] [PATCH 02/11] sunxi: add gtbus-initialisation for sun9i

2016-10-29 Thread Hans de Goede


Hi,

On 29-10-16 13:08, Chen-Yu Tsai wrote:

On Sat, Oct 29, 2016 at 2:45 AM, Jagan Teki  wrote:

On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai  wrote:

From: Philipp Tomsich 

On sun9i, the GTBUS manages transaction priority and bandwidth
for multiple read ports when accessing DRAM. The initialisation
mirrors the settings from Allwinner's boot0 for now, even though
this may not be optimal for all applications (e.g. headless
systems might want to give priority to IO modules).

Adding a common callout to gtbus_init() from the SPL clock init
with a weakly defined implementation in sunxi/clock.c to fallback
to for platforms that don't require this.

[w...@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |  2 +
 arch/arm/include/asm/arch-sunxi/gtbus.h   | 21 +++
 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h | 89 +++
 arch/arm/mach-sunxi/Makefile  |  1 +
 arch/arm/mach-sunxi/clock.c   |  6 ++
 arch/arm/mach-sunxi/gtbus_sun9i.c | 48 +++
 6 files changed, 167 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
 create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index acbc94f4c3b8..ba18a0f551ad 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -23,6 +23,8 @@
 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)

+#define SUNXI_GTBUS_BASE   (REGS_AHB0_BASE + 0x9000)
+
 #define SUNXI_MMC0_BASE(REGS_AHB0_BASE + 0x0f000)
 #define SUNXI_MMC1_BASE(REGS_AHB0_BASE + 0x1)
 #define SUNXI_MMC2_BASE(REGS_AHB0_BASE + 0x11000)
diff --git a/arch/arm/include/asm/arch-sunxi/gtbus.h 
b/arch/arm/include/asm/arch-sunxi/gtbus.h
new file mode 100644
index ..b8308d513545
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gtbus.h
@@ -0,0 +1,21 @@
+/*
+ * GTBUS initialisation
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ *Philipp Tomsich 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_GTBUS_H
+#define _SUNXI_GTBUS_H
+
+#if defined(CONFIG_MACH_SUN9I)
+#include 
+#endif
+
+#ifndef __ASSEMBLY__
+void gtbus_init(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
new file mode 100644
index ..91bc2bdb5103
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
@@ -0,0 +1,89 @@
+/*
+ * GTBUS initialisation for sun9i
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ *Philipp Tomsich 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_GTBUS_SUN9I_H
+#define _SUNXI_GTBUS_SUN9I_H
+
+#include 
+
+struct sunxi_gtbus_reg {
+   u32 mst_cfg[36];   /* 0x000 */
+   u8  reserved1[0x70];   /* 0x090 */
+   u32 bw_wdw_cfg;/* 0x100 */
+   u32 mst_read_prio_cfg[2];  /* 0x104 */
+   u32 lvl2_mst_cfg;  /* 0x10c */
+   u32 sw_clk_on; /* 0x110 */
+   u32 sw_clk_off;/* 0x114 */
+   u32 pmu_mst_en;/* 0x118 */
+   u32 pmu_cfg;   /* 0x11c */
+   u32 pmu_cnt[19];   /* 0x120 */
+   u32 reserved2[0x94];   /* 0x16c */
+   u32 cci400_config[3];  /* 0x200 */
+   u32 cci400_status[2];  /* 0x20c */
+};
+
+/* for register GT_MST_CFG_REG(n) */
+#define GT_ENABLE_REQ   (1<<31) /* clock on */
+#define GT_DISABLE_REQ  (1<<30) /* clock off */
+#define GT_QOS_SHIFT28
+#define GT_THD1_SHIFT   16
+#define GT_REQN_MAX 0xf /* max number master requests in one 
cycle */
+#define GT_REQN_SHIFT   12
+#define GT_THD0_SHIFT   0
+
+#define GT_QOS_MAX  0x3
+#define GT_THD_MAX  0xfff
+#define GT_BW_WDW_MAX   0x
+
+/* mst_read_prio_cfg */
+#define GT_PRIO_LOW 0
+#define GT_PRIO_HIGH1
+
+/* GTBUS port ids */
+#define GT_PORT_CPUM1   0
+#define GT_PORT_CPUM2   1
+#define GT_PORT_SATA2
+#defineGT_PORT_USB33
+#defineGT_PORT_FE0 4
+#defineGT_PORT_BE1 5
+#defineGT_PORT_BE2 6
+#defineGT_PORT_IEP07
+#defineGT_PORT_FE1 8
+#defineGT_PORT_BE0 9
+#defineGT_PORT_FE2 10
+#defineGT_PORT_IEP111
+#defineGT_PORT_VED 12
+#define

Re: [U-Boot] [PATCH 02/11] sunxi: add gtbus-initialisation for sun9i

2016-10-29 Thread Chen-Yu Tsai

On Sat, Oct 29, 2016 at 2:45 AM, Jagan Teki  wrote:
> On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai  wrote:
>> From: Philipp Tomsich 
>>
>> On sun9i, the GTBUS manages transaction priority and bandwidth
>> for multiple read ports when accessing DRAM. The initialisation
>> mirrors the settings from Allwinner's boot0 for now, even though
>> this may not be optimal for all applications (e.g. headless
>> systems might want to give priority to IO modules).
>>
>> Adding a common callout to gtbus_init() from the SPL clock init
>> with a weakly defined implementation in sunxi/clock.c to fallback
>> to for platforms that don't require this.
>>
>> [w...@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
>> Signed-off-by: Chen-Yu Tsai 
>> ---
>>  arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |  2 +
>>  arch/arm/include/asm/arch-sunxi/gtbus.h   | 21 +++
>>  arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h | 89 
>> +++
>>  arch/arm/mach-sunxi/Makefile  |  1 +
>>  arch/arm/mach-sunxi/clock.c   |  6 ++
>>  arch/arm/mach-sunxi/gtbus_sun9i.c | 48 +++
>>  6 files changed, 167 insertions(+)
>>  create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h
>>  create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
>>  create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h 
>> b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
>> index acbc94f4c3b8..ba18a0f551ad 100644
>> --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
>> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
>> @@ -23,6 +23,8 @@
>>  #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
>>  #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
>>
>> +#define SUNXI_GTBUS_BASE   (REGS_AHB0_BASE + 0x9000)
>> +
>>  #define SUNXI_MMC0_BASE(REGS_AHB0_BASE + 0x0f000)
>>  #define SUNXI_MMC1_BASE(REGS_AHB0_BASE + 0x1)
>>  #define SUNXI_MMC2_BASE(REGS_AHB0_BASE + 0x11000)
>> diff --git a/arch/arm/include/asm/arch-sunxi/gtbus.h 
>> b/arch/arm/include/asm/arch-sunxi/gtbus.h
>> new file mode 100644
>> index ..b8308d513545
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-sunxi/gtbus.h
>> @@ -0,0 +1,21 @@
>> +/*
>> + * GTBUS initialisation
>> + *
>> + * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
>> + *Philipp Tomsich 
>> 
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#ifndef _SUNXI_GTBUS_H
>> +#define _SUNXI_GTBUS_H
>> +
>> +#if defined(CONFIG_MACH_SUN9I)
>> +#include 
>> +#endif
>> +
>> +#ifndef __ASSEMBLY__
>> +void gtbus_init(void);
>> +#endif
>> +
>> +#endif
>> diff --git a/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h 
>> b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
>> new file mode 100644
>> index ..91bc2bdb5103
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
>> @@ -0,0 +1,89 @@
>> +/*
>> + * GTBUS initialisation for sun9i
>> + *
>> + * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
>> + *Philipp Tomsich 
>> 
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#ifndef _SUNXI_GTBUS_SUN9I_H
>> +#define _SUNXI_GTBUS_SUN9I_H
>> +
>> +#include 
>> +
>> +struct sunxi_gtbus_reg {
>> +   u32 mst_cfg[36];   /* 0x000 */
>> +   u8  reserved1[0x70];   /* 0x090 */
>> +   u32 bw_wdw_cfg;/* 0x100 */
>> +   u32 mst_read_prio_cfg[2];  /* 0x104 */
>> +   u32 lvl2_mst_cfg;  /* 0x10c */
>> +   u32 sw_clk_on; /* 0x110 */
>> +   u32 sw_clk_off;/* 0x114 */
>> +   u32 pmu_mst_en;/* 0x118 */
>> +   u32 pmu_cfg;   /* 0x11c */
>> +   u32 pmu_cnt[19];   /* 0x120 */
>> +   u32 reserved2[0x94];   /* 0x16c */
>> +   u32 cci400_config[3];  /* 0x200 */
>> +   u32 cci400_status[2];  /* 0x20c */
>> +};
>> +
>> +/* for register GT_MST_CFG_REG(n) */
>> +#define GT_ENABLE_REQ   (1<<31) /* clock on */
>> +#define GT_DISABLE_REQ  (1<<30) /* clock off */
>> +#define GT_QOS_SHIFT28
>> +#define GT_THD1_SHIFT   16
>> +#define GT_REQN_MAX 0xf /* max number master requests in 
>> one cycle */
>> +#define GT_REQN_SHIFT   12
>> +#define GT_THD0_SHIFT   0
>> +
>> +#define GT_QOS_MAX  0x3
>> +#define GT_THD_MAX  0xfff
>> +#define GT_BW_WDW_MAX   0x
>> +
>> +/* mst_read_prio_cfg */
>> +#define GT_PRIO_LOW 0
>> +#define GT_PRIO_HIGH1
>> +
>> +/* GTBUS port ids */
>> +#define GT_PORT_CPUM1   0
>> +#define GT_PORT_CPUM2   1
>> +#define GT_PORT_SATA2
>>

Re: [U-Boot] [PATCH 01/11] sunxi: DRAM initialisation for sun9i

2016-10-29 Thread Chen-Yu Tsai

On Sat, Oct 29, 2016 at 6:39 PM, Hans de Goede  wrote:
> Hi,
>
> On 28-10-16 20:54, Jagan Teki wrote:
>>
>> On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai  wrote:
>>>
>>> From: Philipp Tomsich 
>>>
>>> This adds DRAM initialisation code for sun9i, which calculates the
>>> appropriate timings based on timing information for the supplied
>>> DDR3 bin and the clock speeds used.
>>>
>>> With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
>>> (i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.
>>>
>>> [w...@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style
>>> cleanup]
>>> Signed-off-by: Chen-Yu Tsai 
>>> ---
>>>  arch/arm/include/asm/arch-sunxi/clock_sun9i.h |   34 +-
>>>  arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |6 +
>>>  arch/arm/include/asm/arch-sunxi/dram.h|2 +
>>>  arch/arm/include/asm/arch-sunxi/dram_sun9i.h  |  275 +++
>>>  arch/arm/mach-sunxi/Makefile  |1 +
>>>  arch/arm/mach-sunxi/dram_sun9i.c  | 1059
>>> +
>>>  board/sunxi/Kconfig   |6 +-
>>>  7 files changed, 1368 insertions(+), 15 deletions(-)
>>>  create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h
>>>  create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c
>>
>>
>> Checkpatch:
>> total: 45 errors, 77 warnings, 42 checks, 1464 lines checked
>
>
> Ugh, ok I've fixed this up locally in my tree, Chen-Yu next time
> please remember to run your patches through check-patch.

Sorry about that. Checkpatch considers #if 0 dead code, but the
reality is that a lot of the marked code may or may not be used
later. We just don't know. A lot of it was marked with C99 style
( // ) comments. Using #if 0 is easier to retain trailing comments
within the currently unused sections. Switching to traditional
C style comments means we might be editing those same lines again.

Otherwise I think I cleaned up most of the 'used' code.

Regards
ChenYu

> Jagan, thanks for the review I've addressed all your comments
> in my tree.
>
> Regards,
>
> Hans
>
>
>
>>
>>>
>>> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
>>> b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
>>> index a61934fb3661..82881ff8bdaf 100644
>>> --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
>>> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
>>> @@ -37,57 +37,61 @@ struct sunxi_ccm_reg {
>>> u8 reserved3[0x04]; /* 0x7c */
>>> u32 ats_cfg;/* 0x80 ats clock configuration */
>>> u32 trace_cfg;  /* 0x84 trace clock configuration */
>>> -   u8 reserved4[0xf8]; /* 0x88 */
>>> +   u8 reserved4[0x14]; /* 0x88 */
>>> +   u32 pll_stable_status;  /* 0x9c */
>>> +   u8 reserved5[0xe0]; /* 0xa0 */
>>> u32 clk_output_a;   /* 0x180 clk_output_a */
>>> u32 clk_output_b;   /* 0x184 clk_output_a */
>>> -   u8 reserved5[0x278];/* 0x188 */
>>> +   u8 reserved6[0x278];/* 0x188 */
>>>
>>> u32 nand0_clk_cfg;  /* 0x400 nand0 clock configuration0 */
>>> u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
>>> -   u8 reserved6[0x08]; /* 0x408 */
>>> +   u8 reserved7[0x08]; /* 0x408 */
>>> u32 sd0_clk_cfg;/* 0x410 sd0 clock configuration */
>>> u32 sd1_clk_cfg;/* 0x414 sd1 clock configuration */
>>> u32 sd2_clk_cfg;/* 0x418 sd2 clock configuration */
>>> u32 sd3_clk_cfg;/* 0x41c sd3 clock configuration */
>>> -   u8 reserved7[0x08]; /* 0x420 */
>>> +   u8 reserved8[0x08]; /* 0x420 */
>>> u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */
>>> u32 ss_clk_cfg; /* 0x42c security system clock cfg */
>>> u32 spi0_clk_cfg;   /* 0x430 spi0 clock configuration */
>>> u32 spi1_clk_cfg;   /* 0x434 spi1 clock configuration */
>>> u32 spi2_clk_cfg;   /* 0x438 spi2 clock configuration */
>>> u32 spi3_clk_cfg;   /* 0x43c spi3 clock configuration */
>>> -   u8 reserved8[0x50]; /* 0x440 */
>>> +   u8 reserved9[0x44]; /* 0x440 */
>>> +   u32 dram_clk_cfg;   /* 0x484 DRAM (controller) clock
>>> configuration */
>>> +   u8 reserved10[0x8]; /* 0x488 */
>>> u32 de_clk_cfg; /* 0x490 display engine clock
>>> configuration */
>>> -   u8 reserved9[0x04]; /* 0x494 */
>>> +   u8 reserved11[0x04];/* 0x494 */
>>> u32 mp_clk_cfg; /* 0x498 mp clock configuration */
>>> u32 lcd0_clk_cfg;   /* 0x49c LCD0 module clock */
>>> u32 lcd1_clk_cfg;   /* 0x4a0 LCD1 module clock */
>>> -   u8 reserved10[0x1c];/* 0x4a4 */
>>> +   u8 reserved12[0x1c];/* 0x4a4 */
>>> u32 csi_isp_clk_cfg;/* 0x4c0 CSI ISP module clock */
>>> u32 csi0_clk_cfg;   /* 0x4c4 CSI0

Re: [U-Boot] [PATCH 01/11] sunxi: DRAM initialisation for sun9i

2016-10-29 Thread Hans de Goede


Hi,

On 28-10-16 20:54, Jagan Teki wrote:

On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai  wrote:

From: Philipp Tomsich 

This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.

With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
(i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.

[w...@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/clock_sun9i.h |   34 +-
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |6 +
 arch/arm/include/asm/arch-sunxi/dram.h|2 +
 arch/arm/include/asm/arch-sunxi/dram_sun9i.h  |  275 +++
 arch/arm/mach-sunxi/Makefile  |1 +
 arch/arm/mach-sunxi/dram_sun9i.c  | 1059 +
 board/sunxi/Kconfig   |6 +-
 7 files changed, 1368 insertions(+), 15 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h
 create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c


Checkpatch:
total: 45 errors, 77 warnings, 42 checks, 1464 lines checked


Ugh, ok I've fixed this up locally in my tree, Chen-Yu next time
please remember to run your patches through check-patch.

Jagan, thanks for the review I've addressed all your comments
in my tree.

Regards,

Hans







diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index a61934fb3661..82881ff8bdaf 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -37,57 +37,61 @@ struct sunxi_ccm_reg {
u8 reserved3[0x04]; /* 0x7c */
u32 ats_cfg;/* 0x80 ats clock configuration */
u32 trace_cfg;  /* 0x84 trace clock configuration */
-   u8 reserved4[0xf8]; /* 0x88 */
+   u8 reserved4[0x14]; /* 0x88 */
+   u32 pll_stable_status;  /* 0x9c */
+   u8 reserved5[0xe0]; /* 0xa0 */
u32 clk_output_a;   /* 0x180 clk_output_a */
u32 clk_output_b;   /* 0x184 clk_output_a */
-   u8 reserved5[0x278];/* 0x188 */
+   u8 reserved6[0x278];/* 0x188 */

u32 nand0_clk_cfg;  /* 0x400 nand0 clock configuration0 */
u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
-   u8 reserved6[0x08]; /* 0x408 */
+   u8 reserved7[0x08]; /* 0x408 */
u32 sd0_clk_cfg;/* 0x410 sd0 clock configuration */
u32 sd1_clk_cfg;/* 0x414 sd1 clock configuration */
u32 sd2_clk_cfg;/* 0x418 sd2 clock configuration */
u32 sd3_clk_cfg;/* 0x41c sd3 clock configuration */
-   u8 reserved7[0x08]; /* 0x420 */
+   u8 reserved8[0x08]; /* 0x420 */
u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */
u32 ss_clk_cfg; /* 0x42c security system clock cfg */
u32 spi0_clk_cfg;   /* 0x430 spi0 clock configuration */
u32 spi1_clk_cfg;   /* 0x434 spi1 clock configuration */
u32 spi2_clk_cfg;   /* 0x438 spi2 clock configuration */
u32 spi3_clk_cfg;   /* 0x43c spi3 clock configuration */
-   u8 reserved8[0x50]; /* 0x440 */
+   u8 reserved9[0x44]; /* 0x440 */
+   u32 dram_clk_cfg;   /* 0x484 DRAM (controller) clock configuration 
*/
+   u8 reserved10[0x8]; /* 0x488 */
u32 de_clk_cfg; /* 0x490 display engine clock configuration */
-   u8 reserved9[0x04]; /* 0x494 */
+   u8 reserved11[0x04];/* 0x494 */
u32 mp_clk_cfg; /* 0x498 mp clock configuration */
u32 lcd0_clk_cfg;   /* 0x49c LCD0 module clock */
u32 lcd1_clk_cfg;   /* 0x4a0 LCD1 module clock */
-   u8 reserved10[0x1c];/* 0x4a4 */
+   u8 reserved12[0x1c];/* 0x4a4 */
u32 csi_isp_clk_cfg;/* 0x4c0 CSI ISP module clock */
u32 csi0_clk_cfg;   /* 0x4c4 CSI0 module clock */
u32 csi1_clk_cfg;   /* 0x4c8 CSI1 module clock */
u32 fd_clk_cfg; /* 0x4cc FD module clock */
u32 ve_clk_cfg; /* 0x4d0 VE module clock */
u32 avs_clk_cfg;/* 0x4d4 AVS module clock */
-   u8 reserved11[0x18];/* 0x4d8 */
+   u8 reserved13[0x18];/* 0x4d8 */
u32 gpu_core_clk_cfg;   /* 0x4f0 GPU core clock config */
u32 gpu_mem_clk_cfg;/* 0x4f4 GPU memory clock config */
u32 gpu_axi_clk_cfg;/* 0x4f8 GPU AXI clock config */
-   u8 reserved12[0x10];/* 0x4fc */
+   u8 reserved14[0x10];/* 0x4fc */
u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */
-   u8 reserved13[0x70];/* 0x510 */
+   u8 reserved15[0x70];/* 0x510 */

u32 ahb_gate0;  /* 0x580 AHB0 Gating Register */
u32

[U-Boot] [PATCH] tools: add mksunxiboot to tools-all target

2016-10-29 Thread Stefan Brüns

mksunxiboot is useful outside of u-boot, it is e.g. used by sunxi-tools.

Signed-off-by: Stefan Brüns 
---
 tools/Makefile  | 1 +
 tools/mksunxiboot.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/tools/Makefile b/tools/Makefile
index e6f7993..8e6dede 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -13,6 +13,7 @@ CONFIG_CMD_NET = y
 CONFIG_XWAY_SWAP_BYTES = y
 CONFIG_NETCONSOLE = y
 CONFIG_SHA1_CHECK_UB_IMG = y
+CONFIG_SUNXI = y
 endif
 
 subdir-$(HOST_TOOLS_ALL) += easylogo
diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
index 9c1c5b7..0f0b003 100644
--- a/tools/mksunxiboot.c
+++ b/tools/mksunxiboot.c
@@ -15,7 +15,7 @@
 #include 
 #include 
 #include 
-#include "asm/arch/spl.h"
+#include "../arch/arm/include/asm/arch-sunxi/spl.h"
 
 #define STAMP_VALUE 0x5F0A6C39
 
-- 
2.10.1

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[U-Boot] [PATCH v2 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-10-29 Thread Keerthy

While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.

Fix this to mark the regions as XN by default.

Signed-off-by: Keerthy 
Reviewed-by: Alexander Graf 
---

Changes in v2:

  * Changed printing option value from decimal to hex.

 arch/arm/include/asm/system.h | 2 +-
 arch/arm/lib/cache-cp15.c | 5 +
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index b928bd8..2f430ad 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -329,7 +329,7 @@ static inline void set_dacr(unsigned int val)
 
 /* options available for data cache on each page */
 enum dcache_option {
-   DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
+   DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index e9f9fc9..e9bbcf5 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -71,8 +71,13 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, 
size_t size,
 
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
start = start >> MMU_SECTION_SHIFT;
+#ifdef CONFIG_ARMV7_LPAE
+   debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, , size,
+ option);
+#else
debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, , size,
  option);
+#endif
for (upto = start; upto < end; upto++)
set_section_dcache(upto, option);
 
-- 
1.9.1

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[U-Boot] [PATCH v2 1/2] arm: print the cache config option in hex instead of decimal

2016-10-29 Thread Keerthy

Printing the option value in hex makes it more comprehensible.

Signed-off-by: Keerthy 
---
 arch/arm/lib/cache-cp15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 70e94f0..e9f9fc9 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -71,7 +71,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, 
size_t size,
 
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
start = start >> MMU_SECTION_SHIFT;
-   debug("%s: start=%pa, size=%zu, option=%d\n", __func__, , size,
+   debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, , size,
  option);
for (upto = start; upto < end; upto++)
set_section_dcache(upto, option);
-- 
1.9.1

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Re: [U-Boot] [PATCH 1/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-10-29 Thread Keerthy




On Friday 28 October 2016 06:42 PM, Tom Rini wrote:

On Fri, Oct 28, 2016 at 12:01:43PM +0530, Keerthy wrote:

While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.

Fix this to mark the regions as XN by default.

Signed-off-by: Keerthy 
---
 arch/arm/include/asm/system.h | 2 +-
 arch/arm/lib/cache-cp15.c | 5 +
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index b928bd8..2f430ad 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -329,7 +329,7 @@ static inline void set_dacr(unsigned int val)

 /* options available for data cache on each page */
 enum dcache_option {
-   DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
+   DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 70e94f0..4d9903e 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -71,8 +71,13 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, 
size_t size,

end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
start = start >> MMU_SECTION_SHIFT;
+#ifdef CONFIG_ARMV7_LPAE
+   debug("%s: start=%pa, size=%zu, option=%llu\n", __func__, , size,
+ option);
+#else
debug("%s: start=%pa, size=%zu, option=%d\n", __func__, , size,
  option);
+#endif


Does it really make sense to be printing option in decimal rather than
hex here?


Okay. I will change that to hex and re-post.




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[U-Boot] Patchwork breaks commit log format ?

2016-10-29 Thread Masahiro Yamada

Hello Patchwork developers,


I noticed Patchwork sometimes modifies
commit-log in a wrong way.


Please compare the following two:

[1] Original patch I sent:
http://lists.denx.de/pipermail/u-boot/2016-October/271173.html


[2] After Patchwork picked it up:
http://patchwork.ozlabs.org/patch/687707/


Please see the first line of the commit-log.

In my original patch, the hyphens are aligned as follows:

  - Constify UMC setting data arrays
  - Merge data arrays *_d0 and *_d1.
  - Add PHY parameters for LD20 C1 board


In the picked up one, the first line went left:

- Constify UMC setting data arrays
  - Merge data arrays *_d0 and *_d1.
  - Add PHY parameters for LD20 C1 board



Is this a Patchwork bug?


-- 
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[U-Boot] pull request: u-boot-uniphier/master

2016-10-29 Thread Masahiro Yamada

Hi Tom,

Please pull some more UniPhier SoC updates:
  - DRAM init code updates
  - Misc SoC-related fixes


The following changes since commit 1df182ddf700de49fb4400ba67c3029278ea88e7:

  Merge branch 'master' of git://git.denx.de/u-boot-atmel (2016-10-28
14:14:18 -0400)

are available in the git repository at:


  git://git.denx.de/u-boot-uniphier.git master

for you to fetch changes up to 6eeb624148c1aaedd1cf4f89286c7719bb140fd0:

  ARM: uniphier: update DRAM init code for LD11 SoC (2016-10-29 17:24:30 +0900)


Masahiro Yamada (13):
  ARM: uniphier: adjust fdt_file environment handling to latest Linux
  ARM: uniphier: remove unneeded mdelay() in PLL setting function
  ARM: uniphier: enable SSC for more PLLs for LD20 SoC
  ARM: uniphier: remove unused board attribute macros
  ARM: uniphier: update DRAM init code for LD20 SoC (3rd)
  ARM: uniphier: rename ddrphy-ld20-regs.h to ddruqphy-regs.h
  ARM: uniphier: fix DRAM init poll address for LD4, Pro4, sLD8
  ARM: uniphier: enable clocks to MIO/STDMAC on LD11 if USB is enabled
  ARM: uniphier: do not run harmful code for USB boot mode of LD11 ES3
  ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoC
  ARM: uniphier: refactor DDR PHY parameter dump command
  ARM: uniphier: support DDR PHY parameter dump command for LD11
  ARM: uniphier: update DRAM init code for LD11 SoC

 arch/arm/mach-uniphier/Kconfig |   3 +-
 arch/arm/mach-uniphier/board_late_init.c   |  21 +-
 arch/arm/mach-uniphier/clk/clk-ld11.c  |  19 +-
 arch/arm/mach-uniphier/clk/dpll-ld20.c |   9 +-
 arch/arm/mach-uniphier/clk/pll-base-ld20.c |   2 -
 arch/arm/mach-uniphier/clk/pll-ld20.c  |  15 +-
 arch/arm/mach-uniphier/dram/cmd_ddrphy.c   | 236
+---
 arch/arm/mach-uniphier/dram/ddrphy-init.h  |  17 ++
 arch/arm/mach-uniphier/dram/ddrphy-ld4.c   |  50 ++--
 arch/arm/mach-uniphier/dram/ddrphy-regs.h  | 285
+--
 arch/arm/mach-uniphier/dram/ddrphy-training.c  |  98 +++
 .../mach-uniphier/dram/{ddrphy-ld20-regs.h => ddruqphy-regs.h} |   7 +-
 arch/arm/mach-uniphier/dram/umc-ld11.c | 412
++--
 arch/arm/mach-uniphier/dram/umc-ld20.c | 113 +---
 arch/arm/mach-uniphier/dram/umc-ld4.c  |   4 +-
 arch/arm/mach-uniphier/dram/umc-pro4.c |   4 +-
 arch/arm/mach-uniphier/dram/umc-sld8.c |   4 +-
 arch/arm/mach-uniphier/init.h  |  10 +-
 arch/arm/mach-uniphier/sc64-regs.h |   2 +
 19 files changed, 879 insertions(+), 432 deletions(-)
 create mode 100644 arch/arm/mach-uniphier/dram/ddrphy-init.h
 rename arch/arm/mach-uniphier/dram/{ddrphy-ld20-regs.h =>
ddruqphy-regs.h} (96%)


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Re: [U-Boot] [PATCH 00/11] ARM: uniphier: UniPhier SoC code updates

2016-10-29 Thread Masahiro Yamada

2016-10-27 23:46 GMT+09:00 Masahiro Yamada :
>  - DDR PHY init code updates
>  - Some bug fixes
>
>
>
> Masahiro Yamada (11):
>   ARM: uniphier: enable SSC for more PLLs for LD20 SoC
>   ARM: uniphier: remove unused board attribute macros
>   ARM: uniphier: update DRAM init code for LD20 SoC (3rd)
>   ARM: uniphier: rename ddrphy-ld20-regs.h to ddruqphy-regs.h
>   ARM: uniphier: fix DRAM init poll address for LD4, Pro4, sLD8
>   ARM: uniphier: enable clocks to MIO/STDMAC on LD11 if USB is enabled
>   ARM: uniphier: do not run harmful code for USB boot mode of LD11 ES3
>   ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoC
>   ARM: uniphier: refactor DDR PHY parameter dump command
>   ARM: uniphier: support DDR PHY parameter dump command for LD11
>   ARM: uniphier: update DRAM init code for LD11 SoC

Series, applied to u-boot-uniphier/master.



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Re: [U-Boot] [PATCH 1/2] ARM: uniphier: remove unneeded mdelay(1) in PLL setting function

2016-10-29 Thread Masahiro Yamada

2016-10-19 16:26 GMT+09:00 Masahiro Yamada :
> This delay is already cared by the callers of this function.
>
> Signed-off-by: Masahiro Yamada 
> ---


Applied to u-boot-uniphier/master.

-- 
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