Re: [U-Boot] [PATCH v2 2/4] arm: Remove smdk2410 board

[ELSOFT AG]

Simon Glass wrote:
> This board has not been converted to DM_SERIAL by the deadline.
> Remove it.
> 
> Signed-off-by: Simon Glass 

Acked-by: David Müller 



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Re: [U-Boot] [PATCH v2 3/4] arm: Remove VCMA9 board

[ELSOFT AG]

Simon Glass wrote:
> This board has not been converted to DM_SERIAL by the deadline.
> Remove it.
> 
> Signed-off-by: Simon Glass 

Acked-by: David Müller 


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Re: [U-Boot] [PATCH v2 4/4] serial: Drop the s3c24x0 serial driver

[ELSOFT AG]

Simon Glass wrote:
> This is not used by any boards. Drop it.
> 
> Signed-off-by: Simon Glass 

Acked-by: David Müller 


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[U-Boot] [PATCH] compiler.h: use u-boot endian macros on OpenBSD

[Jonathan Gray]

When building u-boot on sparc64 and powerpc hosts it became clear that
u-boot expects endian conversion defines to be macros:

lib/crc32.c:87: error: braced-group within expression allowed only inside a 
function

For OpenBSD switch from using system definitions equivalent to the u-boot ones
and define glibc __BYTE_ORDER __BIG_ENDIAN __LITTLE_ENDIAN names, as at least
some parts of the non-cross build assumes those names are present (ie crc32.c).

Signed-off-by: Jonathan Gray 
---
 include/compiler.h | 18 --
 1 file changed, 4 insertions(+), 14 deletions(-)

diff --git a/include/compiler.h b/include/compiler.h
index 65b826e..a43fb6a 100644
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -52,6 +52,9 @@ typedef unsigned long ulong;
 # include  /* htole32 and friends */
 #elif defined(__OpenBSD__)
 # include 
+# define __BYTE_ORDER BYTE_ORDER
+# define __LITTLE_ENDIAN LITTLE_ENDIAN
+# define __BIG_ENDIAN BIG_ENDIAN
 #endif
 
 #include 
@@ -84,20 +87,7 @@ typedef unsigned int uint;
 # define uswap_64(x) _uswap_64(x, )
 #endif
 
-#if defined(__OpenBSD__)
-#define cpu_to_le16(x) htole16(x)
-#define cpu_to_le32(x) htole32(x)
-#define cpu_to_le64(x) htole64(x)
-#define le16_to_cpu(x) letoh16(x)
-#define le32_to_cpu(x) letoh32(x)
-#define le64_to_cpu(x) letoh64(x)
-#define cpu_to_be16(x) htobe16(x)
-#define cpu_to_be32(x) htobe32(x)
-#define cpu_to_be64(x) htobe64(x)
-#define be16_to_cpu(x) betoh16(x)
-#define be32_to_cpu(x) betoh32(x)
-#define be64_to_cpu(x) betoh64(x)
-#elif __BYTE_ORDER == __LITTLE_ENDIAN
+#if __BYTE_ORDER == __LITTLE_ENDIAN
 # define cpu_to_le16(x)(x)
 # define cpu_to_le32(x)(x)
 # define cpu_to_le64(x)(x)
-- 
2.10.2

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Re: [U-Boot] [PATCH v2 10/22] spi: Add error checking for invalid bus widths

[Jagan Teki]

On Sat, Nov 26, 2016 at 1:08 AM, Simon Glass  wrote:
> Hi,
>
> On 25 November 2016 at 09:59, Fabio Estevam  wrote:
>> On Fri, Nov 25, 2016 at 2:57 PM, Jagan Teki  wrote:
>>
>>> Yeah, ie what if dts has a wrong value and do print that and continue
>>> with default width, so-that the user will update this for next run.
>>> Since it's not key a attribute to break or decide functionality better
>>> to go with it.
>>
>> Agreed. This also matches with the kernel behaviour.
>
> So it is correct to print an error, and then continue? This error will
> almost never occur and thus it wastes code space. SPI is sensitive
> because it can be used in SPL. Linux doesn't care about code size as
> much.
>
> So how about either:
> 1. debug() and return an error
> 2. debug() and skip the error

I prefer 2. for SPL and replace debug with printf for U-Boot.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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[U-Boot] [PATCH v6 11/13] sunxi: Use binman for sunxi boards

[Simon Glass]

Move sunxi boards to use binman. This involves adding the image definition
to the device tree and using it in the Makefile.

Signed-off-by: Simon Glass 
---

Changes in v6: None
Changes in v5:
- Add a dependency on u-boot.dtb for buildman

Changes in v4:
- Remove RFC tag
- Use binman for all sunxi boards

Changes in v3:
- Use a -u-boot.dtsi file for the binman changes

Changes in v2: None

 Makefile   |  6 ++
 arch/arm/dts/sunxi-u-boot.dtsi | 14 ++
 scripts/Makefile.lib   |  4 ++--
 3 files changed, 18 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/dts/sunxi-u-boot.dtsi

diff --git a/Makefile b/Makefile
index b4fb7d5..751f70e 100644
--- a/Makefile
+++ b/Makefile
@@ -1114,10 +1114,8 @@ u-boot-x86-16bit.bin: u-boot FORCE
 endif
 
 ifneq ($(CONFIG_ARCH_SUNXI),)
-OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
-  --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
-   $(call if_changed,pad_cat)
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
+   $(call if_changed,binman)
 endif
 
 ifneq ($(CONFIG_TEGRA),)
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
new file mode 100644
index 000..5adfd9b
--- /dev/null
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -0,0 +1,14 @@
+#include 
+
+/ {
+   binman {
+   filename = "u-boot-sunxi-with-spl.bin";
+   pad-byte = <0xff>;
+   blob {
+   filename = "spl/sunxi-spl.bin";
+   };
+   u-boot-img {
+   pos = ;
+   };
+   };
+};
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 60265f4..348de2d 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -310,8 +310,8 @@ quiet_cmd_dtc = DTC $@
 # Modified for U-Boot
 # Bring in any U-Boot-specific include after the '/dts-v1/;' header
 cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
-   cat $< $(if $(u-boot-dtsi),\
-   | sed 's%^/ {$$%\#include \"$(u-boot-dtsi)\"\n&%')  | \
+   cat $< $(if $(u_boot_dtsi),\
+   | sed 's%^/ {$$%\#include \"$(u_boot_dtsi)\"\n&%')  | \
$(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) - ; 
\
$(DTC) -O dtb -o $@ -b 0 \
-i $(dir $<) $(DTC_FLAGS) \
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v6 13/13] binman: Drop microcode features from ifdtool

[Simon Glass]

Now that binman supports creating images with microcode, drop the code from
ifdtool.

Signed-off-by: Simon Glass 
---

Changes in v6: None
Changes in v5:
- Add a new patch to drop microcode features from ifdtool

Changes in v4: None
Changes in v3: None
Changes in v2: None

 tools/ifdtool.c | 254 ++--
 1 file changed, 5 insertions(+), 249 deletions(-)

diff --git a/tools/ifdtool.c b/tools/ifdtool.c
index 48059c0..195b153 100644
--- a/tools/ifdtool.c
+++ b/tools/ifdtool.c
@@ -33,16 +33,9 @@
 #define FLREG_BASE(reg)((reg & 0x0fff) << 12);
 #define FLREG_LIMIT(reg)   (((reg & 0x0fff) >> 4) | 0xfff);
 
-enum input_file_type_t {
-   IF_normal,
-   IF_fdt,
-   IF_uboot,
-};
-
 struct input_file {
char *fname;
unsigned int addr;
-   enum input_file_type_t type;
 };
 
 /**
@@ -760,219 +753,6 @@ static int write_data(char *image, int size, unsigned int 
addr,
return write_size;
 }
 
-static int scan_ucode(const void *blob, char *ucode_base, int *countp,
- const char **datap, int *data_sizep)
-{
-   const char *data = NULL;
-   int node, count;
-   int data_size;
-   char *ucode;
-
-   for (node = 0, count = 0, ucode = ucode_base; node >= 0; count++) {
-   node = fdt_node_offset_by_compatible(blob, node,
-"intel,microcode");
-   if (node < 0)
-   break;
-
-   data = fdt_getprop(blob, node, "data", _size);
-   if (!data) {
-   debug("Missing microcode data in FDT '%s': %s\n",
- fdt_get_name(blob, node, NULL),
- fdt_strerror(data_size));
-   return -ENOENT;
-   }
-
-   if (ucode_base)
-   memcpy(ucode, data, data_size);
-   ucode += data_size;
-   }
-
-   if (countp)
-   *countp = count;
-   if (datap)
-   *datap = data;
-   if (data_sizep)
-   *data_sizep = data_size;
-
-   return ucode - ucode_base;
-}
-
-static int remove_ucode(char *blob)
-{
-   int node, count;
-   int ret;
-
-   /* Keep going until we find no more microcode to remove */
-   do {
-   for (node = 0, count = 0; node >= 0;) {
-   int ret;
-
-   node = fdt_node_offset_by_compatible(blob, node,
-"intel,microcode");
-   if (node < 0)
-   break;
-
-   ret = fdt_delprop(blob, node, "data");
-
-   /*
-* -FDT_ERR_NOTFOUND means we already removed the
-* data for this one, so we just continue.
-* 0 means we did remove it, so offsets may have
-* changed and we need to restart our scan.
-* Anything else indicates an error we should report.
-*/
-   if (ret == -FDT_ERR_NOTFOUND)
-   continue;
-   else if (!ret)
-   node = 0;
-   else
-   return ret;
-   }
-   } while (count);
-
-   /* Pack down to remove excees space */
-   ret = fdt_pack(blob);
-   if (ret)
-   return ret;
-
-   return fdt_totalsize(blob);
-}
-
-static int write_ucode(char *image, int size, struct input_file *fdt,
-  int fdt_size, unsigned int ucode_ptr,
-  int collate_ucode)
-{
-   const char *data = NULL;
-   char *ucode_buf;
-   const void *blob;
-   char *ucode_base;
-   uint32_t *ptr;
-   int ucode_size;
-   int data_size;
-   int offset;
-   int count;
-   int ret;
-
-   blob = (void *)image + (uint32_t)(fdt->addr + size);
-
-   debug("DTB at %lx\n", (char *)blob - image);
-
-   /* Find out about the micrcode we have */
-   ucode_size = scan_ucode(blob, NULL, , , _size);
-   if (ucode_size < 0)
-   return ucode_size;
-   if (!count) {
-   debug("No microcode found in FDT\n");
-   return -ENOENT;
-   }
-
-   if (count > 1 && !collate_ucode) {
-   fprintf(stderr,
-   "Cannot handle multiple microcode blocks - please use 
-C flag to collate them\n");
-   return -EMLINK;
-   }
-
-   /*
-* Collect the microcode into a buffer, remove it from the device
-* tree and place it immediately above the (now smaller) device tree.
-*/
-   if (collate_ucode && count > 1) {
-   ucode_buf = malloc(ucode_size);
-   if 

[U-Boot] [PATCH v6 12/13] x86: Use binman all x86 boards

[Simon Glass]

Change x86 boards to use binman to produce the ROM. This involves adding the
image definition to the device tree and using it in the Makefile. The
existing ifdtool features are no-longer needed.

Note that the u-boot.dtsi file is common and is used for all x86 boards which
use microcode. A separate emulation-u-boot-dtsi is used for the others.

Signed-off-by: Simon Glass 
---

Changes in v6: None
Changes in v5: None
Changes in v4:
- Remove RFC tag
- Use binman for all x86 boards

Changes in v3:
- Put the binman definition in u-boot.dtsi

Changes in v2:
- Add automated test coverage
- Put the binman definition in a common file for x86
- Various changes and improvements based on using this tool for a while

 Makefile   | 45 ++-
 arch/x86/dts/emulation-u-boot.dtsi | 18 +++
 arch/x86/dts/u-boot.dtsi   | 62 ++
 3 files changed, 83 insertions(+), 42 deletions(-)
 create mode 100644 arch/x86/dts/emulation-u-boot.dtsi
 create mode 100644 arch/x86/dts/u-boot.dtsi

diff --git a/Makefile b/Makefile
index 751f70e..4121b25 100644
--- a/Makefile
+++ b/Makefile
@@ -1053,50 +1053,11 @@ endif
 
 # x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
 # reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
-# the middle.
+# the middle. This is handled by binman based on an image description in the
+# board's device tree.
 ifneq ($(CONFIG_X86_RESET_VECTOR),)
 rom: u-boot.rom FORCE
 
-IFDTOOL=$(objtree)/tools/ifdtool
-IFDTOOL_FLAGS  = -f 0:$(objtree)/u-boot.dtb
-IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' 
' -f1)
-IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-nodtb.bin
-IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin
-IFDTOOL_FLAGS += -C
-
-ifneq ($(CONFIG_HAVE_INTEL_ME),)
-IFDTOOL_ME_FLAGS  = -D $(srctree)/board/$(BOARDDIR)/descriptor.bin
-IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin
-endif
-
-ifneq ($(CONFIG_HAVE_MRC),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
-endif
-
-ifneq ($(CONFIG_HAVE_FSP),)
-IFDTOOL_FLAGS += -w 
$(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE)
-endif
-
-ifneq ($(CONFIG_HAVE_CMC),)
-IFDTOOL_FLAGS += -w 
$(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
-endif
-
-ifneq ($(CONFIG_HAVE_VGA_BIOS),)
-IFDTOOL_FLAGS += -w 
$(CONFIG_VGA_BIOS_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_VGA_BIOS_FILE)
-endif
-
-ifneq ($(CONFIG_HAVE_REFCODE),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_REFCODE_ADDR):refcode.bin
-endif
-
-quiet_cmd_ifdtool = IFDTOOL $@
-cmd_ifdtool  = $(IFDTOOL) -c -r $(CONFIG_ROM_SIZE) u-boot.tmp;
-ifneq ($(CONFIG_HAVE_INTEL_ME),)
-cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_ME_FLAGS) u-boot.tmp;
-endif
-cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp;
-cmd_ifdtool += mv u-boot.tmp $@
-
 refcode.bin: $(srctree)/board/$(BOARDDIR)/refcode.bin FORCE
$(call if_changed,copy)
 
@@ -1106,7 +1067,7 @@ cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \
 
 u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE \
$(if $(CONFIG_HAVE_REFCODE),refcode.bin)
-   $(call if_changed,ifdtool)
+   $(call if_changed,binman)
 
 OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
 u-boot-x86-16bit.bin: u-boot FORCE
diff --git a/arch/x86/dts/emulation-u-boot.dtsi 
b/arch/x86/dts/emulation-u-boot.dtsi
new file mode 100644
index 000..56d34af
--- /dev/null
+++ b/arch/x86/dts/emulation-u-boot.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+
+#ifdef CONFIG_ROM_SIZE
+/ {
+   binman {
+   u-boot-with-ucode-ptr {
+   optional-ucode;
+   };
+   };
+};
+#endif
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
new file mode 100644
index 000..724913f
--- /dev/null
+++ b/arch/x86/dts/u-boot.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+
+#ifdef CONFIG_ROM_SIZE
+/ {
+   binman {
+   filename = "u-boot.rom";
+   end-at-4gb;
+   sort-by-pos;
+   pad-byte = <0xff>;
+   size = ;
+#ifdef CONFIG_HAVE_INTEL_ME
+   intel-descriptor {
+   };
+   intel-me {
+   };
+#endif
+   u-boot-with-ucode-ptr {
+   pos = ;
+   };
+   u-boot-dtb-with-ucode {
+   };
+   u-boot-ucode {
+   align = <16>;
+   };
+#ifdef CONFIG_HAVE_MRC
+   intel-mrc {
+   pos = ;
+   };
+#endif
+#ifdef CONFIG_HAVE_FSP
+   intel-fsp {

[U-Boot] [PATCH v6 10/13] tegra: Use a U-Boot-specific .dtsi file

[Simon Glass]

With the new device-tree rules it is possible to put device-tree changes
needed by U-Boot into their own file. As an example of this approach, move
Tegra over to use it.

Signed-off-by: Simon Glass 
---

Changes in v6:
- Drop unwanted root-node properties from tegra20-u-boot.dtsi

Changes in v5:
- Add a new tegra patch to use an automatically included .dtsi file

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/dts/tegra124-nyan-big-u-boot.dtsi | 15 +++
 arch/arm/dts/tegra124-nyan-big.dts |  2 --
 arch/arm/dts/tegra20-u-boot.dtsi   |  8 
 arch/arm/dts/tegra20.dtsi  |  2 --
 4 files changed, 23 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
 create mode 100644 arch/arm/dts/tegra20-u-boot.dtsi

diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi 
b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
new file mode 100644
index 000..fff1d78
--- /dev/null
+++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/ {
+   host1x@5000 {
+   u-boot,dm-pre-reloc;
+   dc@5420 {
+   u-boot,dm-pre-reloc;
+   };
+   };
+};
diff --git a/arch/arm/dts/tegra124-nyan-big.dts 
b/arch/arm/dts/tegra124-nyan-big.dts
index 3758395..62f89d0 100644
--- a/arch/arm/dts/tegra124-nyan-big.dts
+++ b/arch/arm/dts/tegra124-nyan-big.dts
@@ -27,9 +27,7 @@
};
 
host1x@5000 {
-   u-boot,dm-pre-reloc;
dc@5420 {
-   u-boot,dm-pre-reloc;
display-timings {
timing@0 {
clock-frequency = <6950>;
diff --git a/arch/arm/dts/tegra20-u-boot.dtsi b/arch/arm/dts/tegra20-u-boot.dtsi
new file mode 100644
index 000..9b9835d
--- /dev/null
+++ b/arch/arm/dts/tegra20-u-boot.dtsi
@@ -0,0 +1,8 @@
+/ {
+   host1x@5000 {
+   u-boot,dm-pre-reloc;
+   dc@5420 {
+   u-boot,dm-pre-reloc;
+   };
+   };
+};
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 84bb1b0..e21ee25 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -10,7 +10,6 @@
interrupt-parent = <>;
 
host1x@5000 {
-   u-boot,dm-pre-reloc;
compatible = "nvidia,tegra20-host1x", "simple-bus";
reg = <0x5000 0x00024000>;
interrupts = , /* syncpt */
@@ -78,7 +77,6 @@
};
 
dc@5420 {
-   u-boot,dm-pre-reloc;
compatible = "nvidia,tegra20-dc";
reg = <0x5420 0x0004>;
interrupts = ;
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v6 05/13] binman: Add support for building x86 ROMs with SPL

[Simon Glass]

When building for 64-bit x86 we need an SPL binary in the ROM. Add support
for this. Also increase entry test code coverage to 100%.

Signed-off-by: Simon Glass 
---

Changes in v6:
- Deal with optional microcode in SPL

Changes in v5:
- Add a new for optional microcode

Changes in v4: None
Changes in v3: None
Changes in v2: None

 tools/binman/etype/u_boot_dtb_with_ucode.py  |   4 +-
 tools/binman/etype/u_boot_spl_bss_pad.py |  26 +++
 tools/binman/etype/u_boot_spl_with_ucode_ptr.py  |  28 
 tools/binman/etype/x86_start16_spl.py|  17 +
 tools/binman/func_test.py|  88 +++
 tools/binman/test/37_x86_no_ucode.dts|  20 ++
 tools/binman/test/38_x86_ucode_missing_node.dts  |  26 +++
 tools/binman/test/39_x86_ucode_missing_node2.dts |  23 ++
 tools/binman/test/40_x86_ucode_not_in_image.dts  |  28 
 tools/binman/test/41_unknown_pos_size.dts|  11 +++
 tools/binman/test/44_x86_optional_ucode.dts  |  30 
 tools/binman/test/u_boot_no_ucode_ptr| Bin 0 -> 4182 bytes
 tools/binman/test/u_boot_no_ucode_ptr.c  |  15 
 13 files changed, 315 insertions(+), 1 deletion(-)
 create mode 100644 tools/binman/etype/u_boot_spl_bss_pad.py
 create mode 100644 tools/binman/etype/u_boot_spl_with_ucode_ptr.py
 create mode 100644 tools/binman/etype/x86_start16_spl.py
 create mode 100644 tools/binman/test/37_x86_no_ucode.dts
 create mode 100644 tools/binman/test/38_x86_ucode_missing_node.dts
 create mode 100644 tools/binman/test/39_x86_ucode_missing_node2.dts
 create mode 100644 tools/binman/test/40_x86_ucode_not_in_image.dts
 create mode 100644 tools/binman/test/41_unknown_pos_size.dts
 create mode 100644 tools/binman/test/44_x86_optional_ucode.dts
 create mode 100755 tools/binman/test/u_boot_no_ucode_ptr
 create mode 100644 tools/binman/test/u_boot_no_ucode_ptr.c

diff --git a/tools/binman/etype/u_boot_dtb_with_ucode.py 
b/tools/binman/etype/u_boot_dtb_with_ucode.py
index 732d10a..fc02c67 100644
--- a/tools/binman/etype/u_boot_dtb_with_ucode.py
+++ b/tools/binman/etype/u_boot_dtb_with_ucode.py
@@ -31,7 +31,9 @@ class Entry_u_boot_dtb_with_ucode(Entry_blob):
 Entry_blob.ObtainContents(self)
 
 # If the image does not need microcode, there is nothing to do
-ucode_dest_entry = self.image.FindEntryType('u-boot-with-ucode-ptr')
+ucode_dest_entry = 
self.image.FindEntryType('u-boot-spl-with-ucode-ptr')
+if not ucode_dest_entry or not ucode_dest_entry.target_pos:
+ucode_dest_entry = 
self.image.FindEntryType('u-boot-with-ucode-ptr')
 if not ucode_dest_entry or not ucode_dest_entry.target_pos:
 return True
 
diff --git a/tools/binman/etype/u_boot_spl_bss_pad.py 
b/tools/binman/etype/u_boot_spl_bss_pad.py
new file mode 100644
index 000..c005f28
--- /dev/null
+++ b/tools/binman/etype/u_boot_spl_bss_pad.py
@@ -0,0 +1,26 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass 
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+# Entry-type module for BSS padding for spl/u-boot-spl.bin. This padding
+# can be added after the SPL binary to ensure that anything concatenated
+# to it will appear to SPL to be at the end of BSS rather than the start.
+#
+
+import command
+from entry import Entry
+from blob import Entry_blob
+import tools
+
+class Entry_u_boot_spl_bss_pad(Entry_blob):
+def __init__(self, image, etype, node):
+Entry_blob.__init__(self, image, etype, node)
+
+def ObtainContents(self):
+fname = tools.GetInputFilename('spl/u-boot-spl')
+args = [['nm', fname], ['grep', '__bss_size']]
+out = command.RunPipe(args, capture=True).stdout.splitlines()
+bss_size = int(out[0].split()[0], 16)
+self.data = chr(0) * bss_size
+self.contents_size = bss_size
diff --git a/tools/binman/etype/u_boot_spl_with_ucode_ptr.py 
b/tools/binman/etype/u_boot_spl_with_ucode_ptr.py
new file mode 100644
index 000..764c282
--- /dev/null
+++ b/tools/binman/etype/u_boot_spl_with_ucode_ptr.py
@@ -0,0 +1,28 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass 
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+# Entry-type module for an SPL binary with an embedded microcode pointer
+#
+
+import struct
+
+import command
+from entry import Entry
+from blob import Entry_blob
+from u_boot_with_ucode_ptr import Entry_u_boot_with_ucode_ptr
+import tools
+
+class Entry_u_boot_spl_with_ucode_ptr(Entry_u_boot_with_ucode_ptr):
+"""U-Boot SPL with embedded microcode pointer
+
+See Entry_u_boot_ucode for full details of the entries involved in this
+process.
+"""
+def __init__(self, image, etype, node):
+Entry_blob.__init__(self, image, etype, node)
+self.elf_fname = 'spl/u-boot-spl'
+
+def GetDefaultFilename(self):
+return 'spl/u-boot-spl.bin'
diff --git 

[U-Boot] [PATCH v6 06/13] binman: Add support for building x86 images with FSP/CMC

[Simon Glass]

Add support for two more from the inexhaustible supply of x86 binary blob
types.

Signed-off-by: Simon Glass 
---

Changes in v6: None
Changes in v5: None
Changes in v4:
- Add new patch to support building x86 images with FSP/CMC

Changes in v3: None
Changes in v2: None

 tools/binman/etype/intel_cmc.py| 17 +
 tools/binman/etype/intel_fsp.py| 17 +
 tools/binman/func_test.py  | 14 ++
 tools/binman/test/42_intel-fsp.dts | 13 +
 tools/binman/test/43_intel-cmc.dts | 13 +
 5 files changed, 74 insertions(+)
 create mode 100644 tools/binman/etype/intel_cmc.py
 create mode 100644 tools/binman/etype/intel_fsp.py
 create mode 100644 tools/binman/test/42_intel-fsp.dts
 create mode 100644 tools/binman/test/43_intel-cmc.dts

diff --git a/tools/binman/etype/intel_cmc.py b/tools/binman/etype/intel_cmc.py
new file mode 100644
index 000..9bce8ae
--- /dev/null
+++ b/tools/binman/etype/intel_cmc.py
@@ -0,0 +1,17 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass 
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+# Entry-type module for Intel Chip Microcode binary blob
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_intel_cmc(Entry_blob):
+def __init__(self, image, etype, node):
+Entry_blob.__init__(self, image, etype, node)
+
+def GetDefaultFilename(self):
+return 'cmc.bin'
diff --git a/tools/binman/etype/intel_fsp.py b/tools/binman/etype/intel_fsp.py
new file mode 100644
index 000..d75be5b
--- /dev/null
+++ b/tools/binman/etype/intel_fsp.py
@@ -0,0 +1,17 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass 
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+# Entry-type module for Intel Firmware Support Package binary blob
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_intel_fsp(Entry_blob):
+def __init__(self, image, etype, node):
+Entry_blob.__init__(self, image, etype, node)
+
+def GetDefaultFilename(self):
+return 'fsp.bin'
diff --git a/tools/binman/func_test.py b/tools/binman/func_test.py
index cb8bd31..740fa9e 100644
--- a/tools/binman/func_test.py
+++ b/tools/binman/func_test.py
@@ -36,6 +36,8 @@ VGA_DATA= 'vga'
 U_BOOT_DTB_DATA = 'udtb'
 X86_START16_DATA= 'start16'
 U_BOOT_NODTB_DATA   = 'nodtb with microcode pointer somewhere in here'
+FSP_DATA= 'fsp'
+CMC_DATA= 'cmc'
 
 class TestFunctional(unittest.TestCase):
 """Functional tests for binman
@@ -70,6 +72,8 @@ class TestFunctional(unittest.TestCase):
 TestFunctional._MakeInputFile('u-boot.dtb', U_BOOT_DTB_DATA)
 TestFunctional._MakeInputFile('u-boot-x86-16bit.bin', X86_START16_DATA)
 TestFunctional._MakeInputFile('u-boot-nodtb.bin', U_BOOT_NODTB_DATA)
+TestFunctional._MakeInputFile('fsp.bin', FSP_DATA)
+TestFunctional._MakeInputFile('cmc.bin', CMC_DATA)
 self._output_setup = False
 
 # ELF file with a '_dt_ucode_base_size' symbol
@@ -806,3 +810,13 @@ class TestFunctional(unittest.TestCase):
 self._DoReadFile('41_unknown_pos_size.dts', True)
 self.assertIn("Image '/binman': Unable to set pos/size for unknown "
 "entry 'invalid-entry'", str(e.exception))
+
+def testPackFsp(self):
+"""Test that an image with a FSP binary can be created"""
+data = self._DoReadFile('42_intel-fsp.dts')
+self.assertEqual(FSP_DATA, data[:len(FSP_DATA)])
+
+def testPackCmc(self):
+"""Test that an image with a FSP binary can be created"""
+data = self._DoReadFile('43_intel-cmc.dts')
+self.assertEqual(CMC_DATA, data[:len(CMC_DATA)])
diff --git a/tools/binman/test/42_intel-fsp.dts 
b/tools/binman/test/42_intel-fsp.dts
new file mode 100644
index 000..e0a1e76
--- /dev/null
+++ b/tools/binman/test/42_intel-fsp.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   binman {
+   size = <16>;
+
+   intel-fsp {
+   };
+   };
+};
diff --git a/tools/binman/test/43_intel-cmc.dts 
b/tools/binman/test/43_intel-cmc.dts
new file mode 100644
index 000..26c456d
--- /dev/null
+++ b/tools/binman/test/43_intel-cmc.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   binman {
+   size = <16>;
+
+   intel-cmc {
+   };
+   };
+};
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v6 09/13] binman: Automatically include a U-Boot .dtsi file

[Simon Glass]

For boards that need U-Boot-specific additions to the device tree, it is
a minor annoyance to have to add these each time the tree is synced with
upstream.

Add a means to include a file (e.g. u-boot.dtsi) automatically into the .dts
file before it is compiled.

The file uses is the first one that exists in this list:

   arch//dts/-u-boot.dtsi
   arch//dts/-u-boot.dtsi
   arch//dts/-u-boot.dtsi
   arch//dts/-u-boot.dtsi
   arch//dts/u-boot.dtsi

Signed-off-by: Simon Glass 
Suggested-by: Tom Rini 
---

Changes in v6: None
Changes in v5:
- Add a Makefile 'warning' line for debugging
- Add documentation for this feature
- Change the Makefile variable from binman_... to u_boot_...

Changes in v4:
- Add an option to bring in an soc .dtsi file also

Changes in v3:
- Add a new patch to automatically include a U-Boot .dtsi file

Changes in v2: None

 scripts/Makefile.lib | 20 +++-
 tools/binman/README  | 39 +++
 2 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index a237b7b..60265f4 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -164,6 +164,21 @@ cpp_flags  = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) 
$(UBOOTINCLUDE) \
 
 ld_flags   = $(LDFLAGS) $(ldflags-y)
 
+dts_dir = $(srctree)/arch/$(ARCH)/dts
+
+# Try these files in order to find the U-Boot-specific .dtsi include file
+u_boot_dtsi_options = $(wildcard $(dts_dir)/$(basename $(notdir 
$<))-u-boot.dtsi) \
+   $(wildcard $(dts_dir)/$(subst $\",,$(CONFIG_SYS_SOC))-u-boot.dtsi) \
+   $(wildcard $(dts_dir)/$(subst $\",,$(CONFIG_SYS_CPU))-u-boot.dtsi) \
+   $(wildcard $(dts_dir)/$(subst $\",,$(CONFIG_SYS_VENDOR))-u-boot.dtsi) \
+   $(wildcard $(dts_dir)/u-boot.dtsi)
+
+# Uncomment for debugging
+# $(warning u_boot_dtsi_options: $(u_boot_dtsi_options))
+
+# We use the first match
+u_boot_dtsi = $(firstword $(u_boot_dtsi_options))
+
 # Modified for U-Boot
 dtc_cpp_flags  = -Wp,-MD,$(depfile).pre.tmp -nostdinc\
 -I$(srctree)/arch/$(ARCH)/dts   \
@@ -293,8 +308,11 @@ $(obj)/%.dtb.S: $(obj)/%.dtb
 
 quiet_cmd_dtc = DTC $@
 # Modified for U-Boot
+# Bring in any U-Boot-specific include after the '/dts-v1/;' header
 cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
-   $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+   cat $< $(if $(u-boot-dtsi),\
+   | sed 's%^/ {$$%\#include \"$(u-boot-dtsi)\"\n&%')  | \
+   $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) - ; 
\
$(DTC) -O dtb -o $@ -b 0 \
-i $(dir $<) $(DTC_FLAGS) \
-d $(depfile).dtc.tmp $(dtc-tmp) ; \
diff --git a/tools/binman/README b/tools/binman/README
index 45e741e..cb47e73 100644
--- a/tools/binman/README
+++ b/tools/binman/README
@@ -422,6 +422,45 @@ stage the position and size of entries should not be 
adjusted.
 step.
 
 
+Automatic .dtsi inclusion
+-
+
+It is sometimes inconvenient to add a 'binman' node to the .dts file for each
+board. This can be done by using #include to bring in a common file. Another
+approach supported by the U-Boot build system is to automatically include
+a common header. You can then put the binman node (and anything else that is
+specific to U-Boot, such as u-boot,dm-pre-reloc properies) in that header
+file.
+
+Binman will search for the following files in arch//dts:
+
+   -u-boot.dtsi where  is the base name of the .dts file
+   -u-boot.dtsi
+   -u-boot.dtsi
+   -u-boot.dtsi
+   u-boot.dtsi
+
+U-Boot will only use the first one that it finds. If you need to include a
+more general file you can do that from the more specific file using #include.
+If you are having trouble figuring out what is going on, you can uncomment
+the 'warning' line in scripts/Makefile.lib to see what it has found:
+
+   # Uncomment for debugging
+   # $(warning binman_dtsi_options: $(binman_dtsi_options))
+
+
+Code coverage
+-
+
+Binman is a critical tool and is designed to be very testable. Entry
+implementations target 100% test coverage. Run 'binman -T' to check this.
+
+To enable Python test coverage on Debian-type distributions (e.g. Ubuntu):
+
+   $ sudo apt-get install python-pip python-pytest
+   $ sudo pip install coverage
+
+
 Advanced Features / Technical docs
 --
 
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v6 08/13] binman: Allow configuration options to be used in .dts files

[Simon Glass]

It is sometimes useful to be able to reference configuration options in a
device tree source file. Add the necessary includes so that this works.

Signed-off-by: Simon Glass 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 scripts/Makefile.lib | 5 +
 1 file changed, 5 insertions(+)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 956a8a9..a237b7b 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -168,6 +168,11 @@ ld_flags   = $(LDFLAGS) $(ldflags-y)
 dtc_cpp_flags  = -Wp,-MD,$(depfile).pre.tmp -nostdinc\
 -I$(srctree)/arch/$(ARCH)/dts   \
 -I$(srctree)/arch/$(ARCH)/dts/include   \
+-Iinclude   \
+-I$(srctree)/include\
+-I$(srctree)/arch/$(ARCH)/include   \
+-include $(srctree)/include/linux/kconfig.h \
+-D__ASSEMBLY__  \
 -undef -D__DTS__
 
 # Finds the multi-part object the current object will be linked into
-- 
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[U-Boot] [PATCH v6 07/13] binman: Add a build rule for binman

[Simon Glass]

Add a standard command definition for binman so that it can be used in
makefiles.

Signed-off-by: Simon Glass 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 Makefile | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Makefile b/Makefile
index 153e076..b4fb7d5 100644
--- a/Makefile
+++ b/Makefile
@@ -903,6 +903,12 @@ u-boot.ldr:u-boot
$(LDR) -T $(CONFIG_CPU) -c $@ $< $(LDR_FLAGS)
$(BOARD_SIZE_CHECK)
 
+# binman
+# ---
+quiet_cmd_binman = BINMAN  $@
+cmd_binman = $(srctree)/tools/binman/binman -d u-boot.dtb -O . \
+   -I . -I $(srctree)/board/$(BOARDDIR) $<
+
 OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
 
 OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
-- 
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[U-Boot] [PATCH v6 02/13] binman: Add basic entry types for U-Boot

[Simon Glass]

Add entries to support some standard U-Boot binaries, such as u-boot.bin,
u-boot.dtb, etc. Also add some tests for these.

Signed-off-by: Simon Glass 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 tools/binman/entry_test.py |  27 +
 tools/binman/etype/_testing.py |  26 +
 tools/binman/etype/blob.py |  37 ++
 tools/binman/etype/u_boot.py   |  17 +
 tools/binman/etype/u_boot_dtb.py   |  17 +
 tools/binman/etype/u_boot_nodtb.py |  17 +
 tools/binman/etype/u_boot_spl.py   |  17 +
 tools/binman/func_test.py  | 542 +
 tools/binman/test/01_invalid.dts   |   5 +
 tools/binman/test/02_missing_node.dts  |   6 +
 tools/binman/test/03_empty.dts |   9 +
 tools/binman/test/04_invalid_entry.dts |  11 +
 tools/binman/test/05_simple.dts|  11 +
 tools/binman/test/06_dual_image.dts|  22 +
 tools/binman/test/07_bad_align.dts |  12 +
 tools/binman/test/08_pack.dts  |  30 ++
 tools/binman/test/09_pack_extra.dts|  35 ++
 tools/binman/test/10_pack_align_power2.dts |  12 +
 tools/binman/test/11_pack_align_size_power2.dts|  12 +
 tools/binman/test/12_pack_inv_align.dts|  13 +
 tools/binman/test/13_pack_inv_size_align.dts   |  13 +
 tools/binman/test/14_pack_overlap.dts  |  16 +
 tools/binman/test/15_pack_overflow.dts |  12 +
 tools/binman/test/16_pack_image_overflow.dts   |  13 +
 tools/binman/test/17_pack_image_size.dts   |  13 +
 tools/binman/test/18_pack_image_align.dts  |  13 +
 tools/binman/test/19_pack_inv_image_align.dts  |  14 +
 .../binman/test/20_pack_inv_image_align_power2.dts |  13 +
 tools/binman/test/21_image_pad.dts |  16 +
 tools/binman/test/22_image_name.dts|  21 +
 tools/binman/test/23_blob.dts  |  12 +
 tools/binman/test/24_sorted.dts|  17 +
 tools/binman/test/25_pack_zero_size.dts|  15 +
 tools/binman/test/26_pack_u_boot_dtb.dts   |  14 +
 34 files changed, 1080 insertions(+)
 create mode 100644 tools/binman/entry_test.py
 create mode 100644 tools/binman/etype/_testing.py
 create mode 100644 tools/binman/etype/blob.py
 create mode 100644 tools/binman/etype/u_boot.py
 create mode 100644 tools/binman/etype/u_boot_dtb.py
 create mode 100644 tools/binman/etype/u_boot_nodtb.py
 create mode 100644 tools/binman/etype/u_boot_spl.py
 create mode 100644 tools/binman/func_test.py
 create mode 100644 tools/binman/test/01_invalid.dts
 create mode 100644 tools/binman/test/02_missing_node.dts
 create mode 100644 tools/binman/test/03_empty.dts
 create mode 100644 tools/binman/test/04_invalid_entry.dts
 create mode 100644 tools/binman/test/05_simple.dts
 create mode 100644 tools/binman/test/06_dual_image.dts
 create mode 100644 tools/binman/test/07_bad_align.dts
 create mode 100644 tools/binman/test/08_pack.dts
 create mode 100644 tools/binman/test/09_pack_extra.dts
 create mode 100644 tools/binman/test/10_pack_align_power2.dts
 create mode 100644 tools/binman/test/11_pack_align_size_power2.dts
 create mode 100644 tools/binman/test/12_pack_inv_align.dts
 create mode 100644 tools/binman/test/13_pack_inv_size_align.dts
 create mode 100644 tools/binman/test/14_pack_overlap.dts
 create mode 100644 tools/binman/test/15_pack_overflow.dts
 create mode 100644 tools/binman/test/16_pack_image_overflow.dts
 create mode 100644 tools/binman/test/17_pack_image_size.dts
 create mode 100644 tools/binman/test/18_pack_image_align.dts
 create mode 100644 tools/binman/test/19_pack_inv_image_align.dts
 create mode 100644 tools/binman/test/20_pack_inv_image_align_power2.dts
 create mode 100644 tools/binman/test/21_image_pad.dts
 create mode 100644 tools/binman/test/22_image_name.dts
 create mode 100644 tools/binman/test/23_blob.dts
 create mode 100644 tools/binman/test/24_sorted.dts
 create mode 100644 tools/binman/test/25_pack_zero_size.dts
 create mode 100644 tools/binman/test/26_pack_u_boot_dtb.dts

diff --git a/tools/binman/entry_test.py b/tools/binman/entry_test.py
new file mode 100644
index 000..8a9ae01
--- /dev/null
+++ b/tools/binman/entry_test.py
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass 
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+# Test for the Entry class
+
+import collections
+import unittest
+
+import entry
+
+class TestEntry(unittest.TestCase):
+def testEntryContents(self):
+"""Test the Entry bass class"""
+base_entry = entry.Entry(None, None, None, read_node=False)
+self.assertEqual(True, base_entry.ObtainContents())
+
+def testUnknownEntry(self):
+"""Test that 

[U-Boot] [PATCH v6 01/13] binman: Introduce binman, a tool for building binary images

[Simon Glass]

This adds the basic code for binman, including command parsing, processing
of entries and generation of images.

So far no entry types are supported. These will be added in future commits
as examples of how to add new types.

See the README for documentation.

Signed-off-by: Simon Glass 
---

Changes in v6:
- Use __import__() when importlib is not available

Changes in v5:
- Add instructions on how to generate html code coverage
- Print 'binman' before all errors
- Remove commented-out PYTHONPATH code which is not needed now

Changes in v4: None
Changes in v3: None
Changes in v2:
- Add test for code coverage
- Fix the -b option
- drop the unused __len__() method

 tools/binman/.gitignore |   1 +
 tools/binman/README | 491 
 tools/binman/binman |   1 +
 tools/binman/binman.py  | 114 ++
 tools/binman/cmdline.py |  53 +
 tools/binman/control.py | 118 +++
 tools/binman/etype/entry.py | 200 ++
 tools/binman/fdt_test.py|  48 +
 tools/binman/image.py   | 229 +
 9 files changed, 1255 insertions(+)
 create mode 100644 tools/binman/.gitignore
 create mode 100644 tools/binman/README
 create mode 12 tools/binman/binman
 create mode 100755 tools/binman/binman.py
 create mode 100644 tools/binman/cmdline.py
 create mode 100644 tools/binman/control.py
 create mode 100644 tools/binman/etype/entry.py
 create mode 100644 tools/binman/fdt_test.py
 create mode 100644 tools/binman/image.py

diff --git a/tools/binman/.gitignore b/tools/binman/.gitignore
new file mode 100644
index 000..0d20b64
--- /dev/null
+++ b/tools/binman/.gitignore
@@ -0,0 +1 @@
+*.pyc
diff --git a/tools/binman/README b/tools/binman/README
new file mode 100644
index 000..c73fb3c
--- /dev/null
+++ b/tools/binman/README
@@ -0,0 +1,491 @@
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+Introduction
+
+
+Firmware often consists of several components which must be packaged together.
+For example, we may have SPL, U-Boot, a device tree and an environment area
+grouped together and placed in MMC flash. When the system starts, it must be
+able to find these pieces.
+
+So far U-Boot has not provided a way to handle creating such images in a
+general way. Each SoC does what it needs to build an image, often packing or
+concatenating images in the U-Boot build system.
+
+Binman aims to provide a mechanism for building images, from simple
+SPL + U-Boot combinations, to more complex arrangements with many parts.
+
+
+What it does
+
+
+Binman reads your board's device tree and finds a node which describes the
+required image layout. It uses this to work out what to place where. The
+output file normally contains the device tree, so it is in principle possible
+to read an image and extract its constituent parts.
+
+
+Features
+
+
+So far binman is pretty simple. It supports binary blobs, such as 'u-boot',
+'spl' and 'fdt'. It supports empty entries (such as setting to 0xff). It can
+place entries at a fixed location in the image, or fit them together with
+suitable padding and alignment. It provides a way to process binaries before
+they are included, by adding a Python plug-in. The device tree is available
+to U-Boot at run-time so that the images can be interpreted.
+
+Binman does not yet update the device tree with the final location of
+everything when it is done. A simple C structure could be generated for
+constrained environments like SPL (using dtoc) but this is also not
+implemented.
+
+Binman can also support incorporating filesystems in the image if required.
+For example x86 platforms may use CBFS in some cases.
+
+Binman is intended for use with U-Boot but is designed to be general enough
+to be useful in other image-packaging situations.
+
+
+Motivation
+--
+
+Packaging of firmware is quite a different task from building the various
+parts. In many cases the various binaries which go into the image come from
+separate build systems. For example, ARM Trusted Firmware is used on ARMv8
+devices but is not built in the U-Boot tree. If a Linux kernel is included
+in the firmware image, it is built elsewhere.
+
+It is of course possible to add more and more build rules to the U-Boot
+build system to cover these cases. It can shell out to other Makefiles and
+build scripts. But it seems better to create a clear divide between building
+software and packaging it.
+
+At present this is handled by manual instructions, different for each board,
+on how to create images that will boot. By turning these instructions into a
+standard format, we can support making valid images for any board without
+manual effort, lots of READMEs, etc.
+
+Benefits:
+- Each binary can have its own build system and tool chain without creating
+any dependencies between them
+- Avoids the need for a single-shot build: individual parts can be 

[U-Boot] [PATCH v6 04/13] binman: Add support for u-boot.img as an input binary

[Simon Glass]

Add an entry type for u-boot.img (a legacy U-Boot image) and a simple test.

Signed-off-by: Simon Glass 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 tools/binman/etype/u_boot_img.py| 17 +
 tools/binman/func_test.py   |  5 +
 tools/binman/test/36_u_boot_img.dts | 11 +++
 3 files changed, 33 insertions(+)
 create mode 100644 tools/binman/etype/u_boot_img.py
 create mode 100644 tools/binman/test/36_u_boot_img.dts

diff --git a/tools/binman/etype/u_boot_img.py b/tools/binman/etype/u_boot_img.py
new file mode 100644
index 000..744f1b4
--- /dev/null
+++ b/tools/binman/etype/u_boot_img.py
@@ -0,0 +1,17 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass 
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+# Entry-type module for U-Boot binary
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot_img(Entry_blob):
+def __init__(self, image, etype, node):
+Entry_blob.__init__(self, image, etype, node)
+
+def GetDefaultFilename(self):
+return 'u-boot.img'
diff --git a/tools/binman/func_test.py b/tools/binman/func_test.py
index 341957b..8dd118b 100644
--- a/tools/binman/func_test.py
+++ b/tools/binman/func_test.py
@@ -713,3 +713,8 @@ class TestFunctional(unittest.TestCase):
 first = data[:len(U_BOOT_NODTB_DATA)]
 self.assertEqual('nodtb with microcode' + pos_and_size +
 ' somewhere in here', first)
+
+def testUBootImg(self):
+"""Test that u-boot.img can be put in a file"""
+data = self._DoReadFile('36_u_boot_img.dts')
+self.assertEqual(U_BOOT_IMG_DATA, data)
diff --git a/tools/binman/test/36_u_boot_img.dts 
b/tools/binman/test/36_u_boot_img.dts
new file mode 100644
index 000..aa5a3fe
--- /dev/null
+++ b/tools/binman/test/36_u_boot_img.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   binman {
+   u-boot-img {
+   };
+   };
+};
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v6 03/13] binman: Add support for building x86 ROMs

[Simon Glass]

The structure of x86 ROMs is pretty complex. There are various binary blobs
to place in the image. Microcode requires special handling so that it is
available to very early code and can be used without any memory whatsoever.

Add support for the various entry types that are currently needed, along
with some tests.

Signed-off-by: Simon Glass 
---

Changes in v6: None
Changes in v5:
- Add documentation for the 'optional-ucode' property
- Add missing 'descriptor.bin' file
- Allow microcode to be optional
- Allow the compiled device tree to be returned from _DoReadFileDtb()
- Put the code to calculate dtb total length in a function

Changes in v4:
- Fix incorrect comments at the top of intel_*.py

Changes in v3: None
Changes in v2: None

 tools/binman/README |  11 ++
 tools/binman/etype/intel_descriptor.py  |  55 +
 tools/binman/etype/intel_me.py  |  17 +++
 tools/binman/etype/intel_mrc.py |  17 +++
 tools/binman/etype/intel_vga.py |  17 +++
 tools/binman/etype/u_boot_dtb_with_ucode.py |  76 
 tools/binman/etype/u_boot_ucode.py  |  84 +
 tools/binman/etype/u_boot_with_ucode_ptr.py |  87 ++
 tools/binman/etype/x86_start16.py   |  17 +++
 tools/binman/func_test.py   | 179 +++-
 tools/binman/test/27_pack_4gb_no_size.dts   |  18 +++
 tools/binman/test/28_pack_4gb_outside.dts   |  19 +++
 tools/binman/test/29_x86-rom.dts|  19 +++
 tools/binman/test/30_x86-rom-me-no-desc.dts |  15 +++
 tools/binman/test/31_x86-rom-me.dts |  18 +++
 tools/binman/test/32_intel-vga.dts  |  13 ++
 tools/binman/test/33_x86-start16.dts|  13 ++
 tools/binman/test/34_x86_ucode.dts  |  29 +
 tools/binman/test/35_x86_single_ucode.dts   |  26 
 tools/binman/test/descriptor.bin| Bin 0 -> 4096 bytes
 tools/binman/test/u_boot_ucode_ptr  | Bin 0 -> 4175 bytes
 tools/binman/test/u_boot_ucode_ptr.c|  15 +++
 tools/binman/test/u_boot_ucode_ptr.lds  |  18 +++
 23 files changed, 760 insertions(+), 3 deletions(-)
 create mode 100644 tools/binman/etype/intel_descriptor.py
 create mode 100644 tools/binman/etype/intel_me.py
 create mode 100644 tools/binman/etype/intel_mrc.py
 create mode 100644 tools/binman/etype/intel_vga.py
 create mode 100644 tools/binman/etype/u_boot_dtb_with_ucode.py
 create mode 100644 tools/binman/etype/u_boot_ucode.py
 create mode 100644 tools/binman/etype/u_boot_with_ucode_ptr.py
 create mode 100644 tools/binman/etype/x86_start16.py
 create mode 100644 tools/binman/test/27_pack_4gb_no_size.dts
 create mode 100644 tools/binman/test/28_pack_4gb_outside.dts
 create mode 100644 tools/binman/test/29_x86-rom.dts
 create mode 100644 tools/binman/test/30_x86-rom-me-no-desc.dts
 create mode 100644 tools/binman/test/31_x86-rom-me.dts
 create mode 100644 tools/binman/test/32_intel-vga.dts
 create mode 100644 tools/binman/test/33_x86-start16.dts
 create mode 100644 tools/binman/test/34_x86_ucode.dts
 create mode 100644 tools/binman/test/35_x86_single_ucode.dts
 create mode 100644 tools/binman/test/descriptor.bin
 create mode 100755 tools/binman/test/u_boot_ucode_ptr
 create mode 100644 tools/binman/test/u_boot_ucode_ptr.c
 create mode 100644 tools/binman/test/u_boot_ucode_ptr.lds

diff --git a/tools/binman/README b/tools/binman/README
index c73fb3c..45e741e 100644
--- a/tools/binman/README
+++ b/tools/binman/README
@@ -369,6 +369,17 @@ Examples of the above options can be found in the tests. 
See the
 tools/binman/test directory.
 
 
+Special properties
+--
+
+Some entries support special properties, documented here:
+
+u-boot-with-ucode-ptr:
+   optional-ucode: boolean property to make microcode optional. If the
+   u-boot.bin image does not include microcode, no error will
+   be generated.
+
+
 Order of image creation
 ---
 
diff --git a/tools/binman/etype/intel_descriptor.py 
b/tools/binman/etype/intel_descriptor.py
new file mode 100644
index 000..7f4ea0b
--- /dev/null
+++ b/tools/binman/etype/intel_descriptor.py
@@ -0,0 +1,55 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass 
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+# Entry-type module for 'u-boot'
+#
+
+import struct
+
+from entry import Entry
+from blob import Entry_blob
+
+FD_SIGNATURE   = struct.pack('> 4) | 0xfff
+self.size = self.limit - self.base + 1
+
+class Entry_intel_descriptor(Entry_blob):
+"""Intel flash descriptor block (4KB)

[U-Boot] [PATCH v6 00/13] binman: A tool for creating firmware images

[Simon Glass]

This series introduces binman, a tool designed to create firmware images.
It provides a way to bring together various binaries and place them in an
image, at particular positions and with configurable alignment.

Packaging of firmware is quite a different task from building the various
parts. In many cases the various binaries which go into the image come from
separate build systems. For example, ARM Trusted Firmware is used on ARMv8
devices but is not built in the U-Boot tree. If a Linux kernel is included
in the firmware image, it is built elsewhere.

It is of course possible to add more and more build rules to the U-Boot
build system to cover these cases. It can shell out to other Makefiles and
build scripts. But it seems better to create a clear divide between building
software and packaging it.

U-Boot supports a very large number of boards. Many of these have their own
specific rules for how an image should be put together so that it boots
correctly. At present these rules are described by manual instructions,
different for each board. By turning these instructions into a standard
format, we can support making valid images for any board without manual
effort, lots of READMEs, etc.

Images consist of a number of entries which are combined to make up the
final image. The image is described in the device tree for the board, meaning
that it can be accessed at run-time if desired.

Binman is an extensible tool. A set of standard entries is provides, but
new entries can be created fairly easily. Entries can be as simple as
providing the name of a file to include. They can also handle more complex
requirements, such as adjusting the input file or reading header information
from one entry to control the position of another.

U-Boot's mkimage builds FIT images and various other binaries. Binman
augments this by allowing these binaries to be packed together. While FIT
should be used where possible, it cannot be used everywhere. For example,
many devices require executable code at a particular offset in the image.
X86 machines require lots of binary blobs at particular places, and a
microcode collection easily accessible at boot.

So far binman has enough functionality to be useful, so sunxi and x86 boards
are switched over to use it, as examples.

The series is available at u-boot-dm/binman-working

Future work and missing features are documented in the README.

Changes in v6:
- Deal with optional microcode in SPL
- Drop unwanted root-node properties from tegra20-u-boot.dtsi
- Use __import__() when importlib is not available

Changes in v5:
- Add a Makefile 'warning' line for debugging
- Add a dependency on u-boot.dtb for buildman
- Add a new for optional microcode
- Add a new patch to drop microcode features from ifdtool
- Add a new tegra patch to use an automatically included .dtsi file
- Add documentation for the 'optional-ucode' property
- Add documentation for this feature
- Add instructions on how to generate html code coverage
- Add missing 'descriptor.bin' file
- Allow microcode to be optional
- Allow the compiled device tree to be returned from _DoReadFileDtb()
- Change the Makefile variable from binman_... to u_boot_...
- Print 'binman' before all errors
- Put the code to calculate dtb total length in a function
- Remove commented-out PYTHONPATH code which is not needed now

Changes in v4:
- Add an option to bring in an soc .dtsi file also
- Add new patch to support building x86 images with FSP/CMC
- Fix incorrect comments at the top of intel_*.py
- Remove RFC tag
- Use binman for all sunxi boards
- Use binman for all x86 boards

Changes in v3:
- Add a new patch to automatically include a U-Boot .dtsi file
- Put the binman definition in u-boot.dtsi
- Use a -u-boot.dtsi file for the binman changes

Changes in v2:
- Add automated test coverage
- Add test for code coverage
- Fix the -b option
- Put the binman definition in a common file for x86
- Various changes and improvements based on using this tool for a while
- drop the unused __len__() method

Simon Glass (13):
  binman: Introduce binman, a tool for building binary images
  binman: Add basic entry types for U-Boot
  binman: Add support for building x86 ROMs
  binman: Add support for u-boot.img as an input binary
  binman: Add support for building x86 ROMs with SPL
  binman: Add support for building x86 images with FSP/CMC
  binman: Add a build rule for binman
  binman: Allow configuration options to be used in .dts files
  binman: Automatically include a U-Boot .dtsi file
  tegra: Use a U-Boot-specific .dtsi file
  sunxi: Use binman for sunxi boards
  x86: Use binman all x86 boards
  binman: Drop microcode features from ifdtool

 Makefile   |  57 +-
 arch/arm/dts/sunxi-u-boot.dtsi |  14 +
 arch/arm/dts/tegra124-nyan-big-u-boot.dtsi |  15 +
 arch/arm/dts/tegra124-nyan-big.dts |   2 -
 arch/arm/dts/tegra20-u-boot.dtsi   |   8 +
 

Re: [U-Boot] Macronix NOR_SPI and Quad I/O

[Jagan Teki]

On Fri, Nov 25, 2016 at 10:07 PM, Champ, Andy  wrote:
> Hi all,
>
>
> in the table in drivers/mtd/spi/spi_flash_ids.c there is a flag WR_QPP set 
> against Macronix devices (including the ones Dumitru is just adding).
>
>
> This is used when programming the devices on a 4-bit bus to select the 
> command to use for programming - either CMD_QUAD_PAGE_PROGRAM (0x32) or 
> CMD_PAGE_PROGRAM (0x2).
>
>
> The Macronix devices that I have a spec for do not mention command 0x32. Each 
> of the devices that I have a spec for ( MX25L25635F MX25U51245G MX25V8035F 
> and MX25V1635F ) use command 0x38 instead.

We need to fix this, till now no Macronix has been tested with QUAD I
think, please send the suitable fix will review.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH] armv8/spin_table.c: fix spin table release address

[Masahiro Yamada]

2016-11-25 7:38 GMT+09:00 Tsung-Han Lin :
> Since only the master core will relocate itself, the spin-table release
> address seen by master core and other slave cores is different.
> This commit fixes this issue by recalculating the spin-table release
> address' offset instead of leaving it to compiler.

No.
You should bring the slaves cores in after relocation
so that the slaves enter the *relocated* _start.

-- 
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Masahiro Yamada
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Re: [U-Boot] [PATCH v2] libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORY

[Masahiro Yamada]

Hi Simon,


2016-11-26 4:37 GMT+09:00 Simon Glass :

> Unfortunately this breaks sandbox - can you please take a look?
>
> 02: libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORY
>sandbox:  +   sandbox sandbox_spl sandbox_noblk
> +common/built-in.o: In function `image_setup_libfdt':
> +build/../common/image-fdt.c:477: undefined reference to `arch_fixup_fdt'
> +collect2: error: ld returned 1 exit status
> +make[1]: *** [u-boot] Error 1
> +make: *** [sub-make] Error 2

Oops.
I've posted v3.  Thanks.


-- 
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Masahiro Yamada
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[U-Boot] Please pull u-boot-rockchip (take 2)

[Simon Glass]

Hi Tom,

I fixed up the checking of voltage and current to correct the test
failure. Sorry for not spotting this correctly.


The following changes since commit 543bd27353d2c5679057fe09aa2d02259687ff32:

  MAINTAINERS: SUNXI: Update maintainership (2016-11-22 09:07:26 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-rockchip.git

for you to fetch changes up to 6b388f0bed0e3d021128b4fc3c41da4572984e3b:

  rockchip: configs: correct partitions 'boot' size (2016-11-25 17:59:32 -0700)


Andreas Färber (2):
  arm: dts: Fix Rockchip sort order
  arm: rockchip: Fix typo in ROCKCHIP_RK3288 help

Jacob Chen (1):
  rockchip: configs: correct partitions 'boot' size

Keerthy (3):
  power: regulator: Introduce regulator_set_value_force function
  power: regulator: Add limits checking while setting voltage
  power: regulator: Add limits checking while setting current

Kever Yang (5):
  evb-rk3399: deduced the dram node size when space reserved
  config: evb-rk3399: enable PWM_ROCKCHIP
  config: rk3036: enable configs for USB HOST
  config: rk3036: enable fix regulator
  dts: arm: rk3036: add usb vbus node

Simon Glass (21):
  rockchip: video: Correct HDMI data source selection
  rockchip: video: Correct VOP clock selection
  rockchip: Allow jerry to use of-platdata
  stdio: Correct code style nits
  stdio: Correct numbering logic in stdio_probe_device()
  spi: Add of-platdata support to SPI and SPI flash
  rockchip: spi: Add support for of-platdata
  rockchip: spi: Honour the deactivation delay
  spi: Add a debug() on bind failure
  video: Use cache-alignment in video_sync()
  video: Track whether a display is in use
  rockchip: video: Check for device in use
  rockchip: Move jerry to use of-platdata
  rockchip: Rename jerry files to veyron
  rockchip: veyron: Add a note about the SDRAM voltage
  rockchip: Move jerry SDRAM settings into its own .dts file
  rockchip: clk: Support setting ACLK
  rockchip: veyron: Adjust ARM clock after relocation
  rockchip: video: Avoid using u8 in the HDMI driver
  rockchip: Add support for veyron-mickey (Chromebit)
  rockchip: Add support for veyron-minnie (ASUS Chromebook Flip)

 arch/arm/dts/Makefile  |   6 +-
 arch/arm/dts/rk3036-sdk.dts|  37 +++-
 arch/arm/dts/rk3288-veyron-chromebook.dtsi |   2 +
 arch/arm/dts/{rk3288-jerry.dts => rk3288-veyron-jerry.dts} |  16 +-
 arch/arm/dts/rk3288-veyron-mickey.dts  | 277

 arch/arm/dts/rk3288-veyron-minnie.dts  | 301
++
 arch/arm/dts/rk3288-veyron.dtsi|   8 -
 arch/arm/mach-rockchip/Kconfig |   2 +-
 arch/arm/mach-rockchip/rk3288-board-spl.c  |   4 +
 arch/arm/mach-rockchip/rk3288-board.c  |  44 
 arch/arm/mach-rockchip/rk3288/Kconfig  |  21 +-
 board/google/chromebook_jerry/Kconfig  |  15 --
 board/google/chromebook_jerry/MAINTAINERS  |   6 -
 board/google/chromebook_jerry/jerry.c  |   7 -
 board/google/veyron/Kconfig|  47 
 board/google/veyron/MAINTAINERS|  20 ++
 board/google/{chromebook_jerry => veyron}/Makefile |   2 +-
 board/google/veyron/veyron.c   |  13 ++
 board/rockchip/evb_rk3399/evb-rk3399.c |   2 +-
 cmd/regulator.c|   5 +-
 common/stdio.c |   9 +-
 configs/chromebit_mickey_defconfig |  84 +++
 configs/chromebook_jerry_defconfig |  10 +-
 configs/chromebook_minnie_defconfig|  82 +++
 configs/evb-rk3399_defconfig   |   1 +
 configs/kylin-rk3036_defconfig |   4 +
 drivers/clk/rockchip/clk_rk3288.c  |   7 +
 drivers/mtd/spi/spi_flash.c|   2 +-
 drivers/power/regulator/regulator-uclass.c |  28 +++
 drivers/spi/rk_spi.c   |  44 +++-
 drivers/spi/spi-uclass.c   |  18 +-
 drivers/video/display-uclass.c |  18 +-
 drivers/video/rockchip/rk_hdmi.c   |  33 +--
 drivers/video/rockchip/rk_vop.c|  16 +-
 drivers/video/video-uclass.c   |   3 +-
 include/configs/rk3036_common.h|   7 +
 include/configs/rockchip-common.h  |   2 +-
 

[U-Boot] [PATCH v3] libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORY

[Masahiro Yamada]

Commit e2f88dfd2d96 ("libfdt: Introduce new ARCH_FIXUP_FDT option")
allows us to skip memory setup of DTB, but a problem for ARM is that
spin_table_update_dt() and psci_update_dt() are skipped as well if
CONFIG_ARCH_FIXUP_FDT is disabled.

This commit allows us to skip only fdt_fixup_memory_banks() instead
of the whole of arch_fixup_fdt().  It will be useful when we want to
use a memory node from a kernel DTB as is, but need some fixups for
Spin-Table/PSCI.

Signed-off-by: Masahiro Yamada 
Acked-by: Alexey Brodkin 
Acked-by: Simon Glass 
---

Changes in v3:
  - Add an empty stub to sandbox to fix a build error

Changes in v2:
  - Add empty stub to ARC, PowerPC, Microblaze instead of
a weak function common/image-fdt.c

 Kconfig | 5 ++---
 arch/arc/lib/bootm.c| 5 +
 arch/arm/lib/bootm-fdt.c| 2 --
 arch/arm/lib/bootm.c| 2 --
 arch/microblaze/lib/bootm.c | 5 +
 arch/mips/lib/bootm.c   | 2 --
 arch/powerpc/lib/bootm.c| 5 +
 arch/sandbox/lib/bootm.c| 5 +
 common/fdt_support.c| 2 ++
 common/image-fdt.c  | 2 --
 include/fdt_support.h   | 8 
 11 files changed, 32 insertions(+), 11 deletions(-)

diff --git a/Kconfig b/Kconfig
index f3a9f73..70347e7 100644
--- a/Kconfig
+++ b/Kconfig
@@ -325,9 +325,8 @@ config SYS_CLK_FREQ
help
  TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
 
-config ARCH_FIXUP_FDT
-   bool "Enable arch_fixup_fdt() call"
-   depends on ARM || MIPS
+config ARCH_FIXUP_FDT_MEMORY
+   bool "Enable arch_fixup_memory_banks() call"
default y
help
  Enable FDT memory map syncup before OS boot. This feature can be
diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c
index 04d9d9c..5798149 100644
--- a/arch/arc/lib/bootm.c
+++ b/arch/arc/lib/bootm.c
@@ -37,6 +37,11 @@ void arch_lmb_reserve(struct lmb *lmb)
lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
 }
 
+int arch_fixup_fdt(void *blob)
+{
+   return 0;
+}
+
 static int cleanup_before_linux(void)
 {
disable_interrupts();
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index a517550..4481f9e 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -25,7 +25,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_ARCH_FIXUP_FDT
 int arch_fixup_fdt(void *blob)
 {
bd_t *bd = gd->bd;
@@ -61,4 +60,3 @@ int arch_fixup_fdt(void *blob)
 
return 0;
 }
-#endif
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index dedcd1e..638e6d8 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -379,10 +379,8 @@ void boot_prep_vxworks(bootm_headers_t *images)
if (images->ft_addr) {
off = fdt_path_offset(images->ft_addr, "/memory");
if (off < 0) {
-#ifdef CONFIG_ARCH_FIXUP_FDT
if (arch_fixup_fdt(images->ft_addr))
puts("## WARNING: fixup memory failed!\n");
-#endif
}
}
 #endif
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 3eb3440..2732203 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -17,6 +17,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int arch_fixup_fdt(void *blob)
+{
+   return 0;
+}
+
 int do_bootm_linux(int flag, int argc, char * const argv[],
   bootm_headers_t *images)
 {
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 0c6a4ab..aa0475a 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -253,7 +253,6 @@ static int boot_reloc_fdt(bootm_headers_t *images)
 #endif
 }
 
-#ifdef CONFIG_ARCH_FIXUP_FDT
 int arch_fixup_fdt(void *blob)
 {
 #if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
@@ -265,7 +264,6 @@ int arch_fixup_fdt(void *blob)
return 0;
 #endif
 }
-#endif
 
 static int boot_setup_fdt(bootm_headers_t *images)
 {
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index ef15e7a..17c5ed1 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -38,6 +38,11 @@ static void set_clocks_in_mhz (bd_t *kbd);
 #define CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE   (768*1024*1024)
 #endif
 
+int arch_fixup_fdt(void *blob)
+{
+   return 0;
+}
+
 static void boot_jump_linux(bootm_headers_t *images)
 {
void(*kernel)(bd_t *, ulong r4, ulong r5, ulong r6,
diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c
index 0c9a797..4cdd18f 100644
--- a/arch/sandbox/lib/bootm.c
+++ b/arch/sandbox/lib/bootm.c
@@ -50,6 +50,11 @@ int bootz_setup(ulong image, ulong *start, ulong *end)
return ret;
 }
 
+int arch_fixup_fdt(void *blob)
+{
+   return 0;
+}
+
 int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
 {
if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
diff --git a/common/fdt_support.c b/common/fdt_support.c

[U-Boot] [PATCH v2 2/3] ARM: ti: consolidate dfu environment variables

[Sekhar Nori]

Introduce include/environment/ti/dfu.h that
consolidates environment variable definitions
for various TI boards that support DFU today.

Tested on AM335x EVM, AM437x SK EVM and DRA74x
EVM by using DFU to write to SD card.

Signed-off-by: Sekhar Nori 
---
 include/configs/am335x_evm.h | 33 +--
 include/configs/am43xx_evm.h | 34 ++--
 include/configs/dra7xx_evm.h | 51 ++
 include/configs/omap5_uevm.h | 37 ++
 include/environment/ti/dfu.h | 75 
 5 files changed, 82 insertions(+), 148 deletions(-)
 create mode 100644 include/environment/ti/dfu.h

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index ec70b72970e3..5213184c7ba9 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -17,6 +17,7 @@
 #define __CONFIG_AM335X_EVM_H
 
 #include 
+#include 
 
 #ifndef CONFIG_SPL_BUILD
 # define CONFIG_TIMESTAMP
@@ -330,38 +331,6 @@
 
 /* USB Device Firmware Update support */
 #ifndef CONFIG_SPL_BUILD
-#define DFU_ALT_INFO_MMC \
-   "dfu_alt_info_mmc=" \
-   "boot part 0 1;" \
-   "rootfs part 0 2;" \
-   "MLO fat 0 1;" \
-   "MLO.raw raw 0x100 0x100;" \
-   "u-boot.img.raw raw 0x300 0x400;" \
-   "spl-os-args.raw raw 0x80 0x80;" \
-   "spl-os-image.raw raw 0x900 0x2000;" \
-   "spl-os-args fat 0 1;" \
-   "spl-os-image fat 0 1;" \
-   "u-boot.img fat 0 1;" \
-   "uEnv.txt fat 0 1\0"
-#ifdef CONFIG_NAND
-#define DFU_ALT_INFO_NAND \
-   "dfu_alt_info_nand=" \
-   "SPL part 0 1;" \
-   "SPL.backup1 part 0 2;" \
-   "SPL.backup2 part 0 3;" \
-   "SPL.backup3 part 0 4;" \
-   "u-boot part 0 5;" \
-   "u-boot-spl-os part 0 6;" \
-   "kernel part 0 8;" \
-   "rootfs part 0 9\0"
-#else
-#define DFU_ALT_INFO_NAND ""
-#endif
-#define DFU_ALT_INFO_RAM \
-   "dfu_alt_info_ram=" \
-   "kernel ram 0x8020 0xD8;" \
-   "fdt ram 0x80F8 0x8;" \
-   "ramdisk ram 0x8100 0x400\0"
 #define DFUARGS \
"dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
DFU_ALT_INFO_MMC \
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 20f207c3f3a7..256182a9704b 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -14,6 +14,7 @@
 #define CONFIG_MAX_RAM_BANK_SIZE   (1024 << 21)/* 2GB */
 #define CONFIG_SYS_TIMERBASE   0x4804  /* Use Timer2 */
 
+#include 
 #include 
 
 /* NS16550 Configuration */
@@ -122,43 +123,12 @@
 
 #ifndef CONFIG_SPL_BUILD
 /* USB Device Firmware Update support */
-
-#define DFU_ALT_INFO_MMC \
-   "dfu_alt_info_mmc=" \
-   "boot part 0 1;" \
-   "rootfs part 0 2;" \
-   "MLO fat 0 1;" \
-   "spl-os-args fat 0 1;" \
-   "spl-os-image fat 0 1;" \
-   "u-boot.img fat 0 1;" \
-   "uEnv.txt fat 0 1\0"
-
-#define DFU_ALT_INFO_EMMC \
-   "dfu_alt_info_emmc=" \
-   "MLO raw 0x100 0x100 mmcpart 0;" \
-   "u-boot.img raw 0x300 0x1000 mmcpart 0\0"
-
-#define DFU_ALT_INFO_RAM \
-   "dfu_alt_info_ram=" \
-   "kernel ram 0x8020 0x400;" \
-   "fdt ram 0x80f8 0x8;" \
-   "ramdisk ram 0x8100 0x400\0"
-
-#define DFU_ALT_INFO_QSPI \
-   "dfu_alt_info_qspi=" \
-   "u-boot.bin raw 0x0 0x08;" \
-   "u-boot.backup raw 0x08 0x08;" \
-   "u-boot-spl-os raw 0x10 0x01;" \
-   "u-boot-env raw 0x11 0x01;" \
-   "u-boot-env.backup raw 0x12 0x01;" \
-   "kernel raw 0x13 0x80\0"
-
 #define DFUARGS \
"dfu_bufsiz=0x1\0" \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_EMMC \
DFU_ALT_INFO_RAM \
-   DFU_ALT_INFO_QSPI
+   DFU_ALT_INFO_QSPI_XIP
 #else
 #define DFUARGS
 #endif
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 798002d4cd88..2d703a757db7 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -12,6 +12,8 @@
 #ifndef __CONFIG_DRA7XX_EVM_H
 #define __CONFIG_DRA7XX_EVM_H
 
+#include 
+
 #define CONFIG_DRA7XX
 #define CONFIG_BOARD_EARLY_INIT_F
 
@@ -68,50 +70,6 @@
"name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \
"name=userdata,size=-,uuid=${uuid_gpt_userdata}"
 
-#define DFU_ALT_INFO_MMC \
-   "dfu_alt_info_mmc=" \
-   "boot part 0 1;" \
-   "rootfs part 0 2;" \
-   "MLO fat 0 1;" \
-   "MLO.raw raw 0x100 0x100;" \
-   "u-boot.img.raw raw 0x300 0x400;" \
-   "spl-os-args.raw raw 0x80 0x80;" \
-   "spl-os-image.raw raw 0x900 0x2000;" \
-   "spl-os-args fat 0 1;" \
-   "spl-os-image fat 0 1;" \
-   "u-boot.img fat 0 1;" \
-   "uEnv.txt fat 0 1\0"
-
-#define DFU_ALT_INFO_EMMC \
-   "dfu_alt_info_emmc=" \
-   "rawemmc raw 0 3751936;" \
-   "boot part 1 1;" \
-   "rootfs part 1 2;" \
-   "MLO fat 1 1;" \
-   "MLO.raw raw 0x100 0x100;" \
-   

[U-Boot] [PATCH v2 0/3] ARM: ti: DFU environment consolidation + AM57x DFU

[Sekhar Nori]

This patch series consolidates DFU environment
variables into newly created include/environment/ti/dfu.h

Then goes on to add DFU support for AM57x GP EVM.

Build tested using the following buildman commands:

$ tools/buildman/buildman -j 16 -b dfu -c 3 -o test am33xx
$ tools/buildman/buildman -j 16 -b dfu -c 3 -o test omap

v1 submission here:
https://www.mail-archive.com/u-boot@lists.denx.de/msg222838.html

Sekhar Nori (3):
  board: ti: am57xx-evm: fix build warnings
  ARM: ti: consolidate dfu environment variables
  ARM: am57xx_evm: enable DFU support

 board/ti/am57xx/board.c | 20 ---
 configs/am57xx_evm_defconfig| 12 +++
 configs/am57xx_hs_evm_defconfig | 12 +++
 include/configs/am335x_evm.h| 33 +-
 include/configs/am43xx_evm.h| 34 ++-
 include/configs/am57xx_evm.h|  8 +
 include/configs/dra7xx_evm.h| 51 ++--
 include/configs/omap5_uevm.h| 37 ++--
 include/environment/ti/dfu.h| 75 +
 9 files changed, 114 insertions(+), 168 deletions(-)
 create mode 100644 include/environment/ti/dfu.h

-- 
2.9.0

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Re: [U-Boot] [PATCH] armv8/spin_table.c: fix spin table release address

[Tsung-Han Lin]

Hi,

Sorry that I sent this patch twice and they are actually the same one.
I thought the first mail was failed because I got a message from the mail
server said that it is not sent to one of the maintainers.

Regards,
Tsung-Han

2016-11-25 19:44 GMT+09:00 Tsung-Han Lin :

> Since only the master core will relocate itself, the spin-table release
> address seen by master core and other slave cores is different.
> This commit fixes this issue by recalculating the spin-table release
> address' offset instead of leaving it to compiler.
>
> Signed-off-by: Tsung-Han Lin 
> ---
>  arch/arm/cpu/armv8/spin_table.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv8/spin_table.c b/arch/arm/cpu/armv8/spin_
> table.c
> index ec1c9b8ddb6f..1169e2df5f47 100644
> --- a/arch/arm/cpu/armv8/spin_table.c
> +++ b/arch/arm/cpu/armv8/spin_table.c
> @@ -11,12 +11,16 @@
>
>  int spin_table_update_dt(void *fdt)
>  {
> +   extern unsigned long _start;
> int cpus_offset, offset;
> const char *prop;
> int ret;
> unsigned long rsv_addr = (unsigned long)_table_reserve_begin;
> unsigned long rsv_size = _table_reserve_end -
> _table_reserve_begin;
> +   unsigned long unreloc_spin_release_addr = CONFIG_SYS_TEXT_BASE +
> +   (unsigned long)_table_cpu_release_addr -
> +   (unsigned long)&_start;
>
> cpus_offset = fdt_path_offset(fdt, "/cpus");
> if (cpus_offset < 0)
> @@ -47,7 +51,7 @@ int spin_table_update_dt(void *fdt)
> continue;
>
> ret = fdt_setprop_u64(fdt, offset, "cpu-release-addr",
> -   (unsigned long)_table_cpu_release_
> addr);
> +   unreloc_spin_release_addr);
> if (ret)
> return -ENOSPC;
> }
> --
> 2.7.4
>
>


-- 
Tsung-Han "*Johnny*" Lin

Page: http://tsunghanlin.github.com/
Email: tsunghan...@gmail.com
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Re: [U-Boot] Please pull u-boot-rockchip

[Tom Rini]

On Fri, Nov 25, 2016 at 12:39:13PM -0700, Simon Glass wrote:
> Hi Tom,
> 
> This includes support for minnie and mickey Chromebooks, rk3036 USB
> support, some power improvements and other minor things.
> 
> 
> The following changes since commit 543bd27353d2c5679057fe09aa2d02259687ff32:
> 
>   MAINTAINERS: SUNXI: Update maintainership (2016-11-22 09:07:26 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-rockchip.git
> 
> for you to fetch changes up to fc334a074b7309e08c8f9571f4e5025f345a:
> 
>   rockchip: configs: correct partitions 'boot' size (2016-11-25 10:03:32 
> -0700)
> 
> 
> Andreas Färber (2):
>   arm: dts: Fix Rockchip sort order
>   arm: rockchip: Fix typo in ROCKCHIP_RK3288 help
> 
> Jacob Chen (1):
>   rockchip: configs: correct partitions 'boot' size
> 
> Keerthy (3):
>   power: regulator: Introduce regulator_set_value_force function
>   power: regulator: Add limits checking while setting voltage
>   power: regulator: Add limits checking while setting current

NAK, this breaks test.py:
commit b98356a47db2884ce1051bfbb3694062ed9136ab
Author: Keerthy 
Date:   Wed Oct 26 13:42:32 2016 +0530

power: regulator: Add limits checking while setting current

introduces:
=== FAILURES 
===
 test_ut[ut_dm_power_regulator_set_get_current] 


u_boot_console = 
ut_subtest = 'dm power_regulator_set_get_current'

def test_ut(u_boot_console, ut_subtest):
"""Execute a "ut" subtest."""

output = u_boot_console.run_command('ut ' + ut_subtest)
>   assert output.endswith('Failures: 0')
E   assert ('Failures: 0')
E+  where  = 
'Test: dm_test_power_regulator_set_get_current\r\r\n../test/dm/regulator.c:154, 
dm_test_power_regulator_set_get_current(): -ENOSYS == 
regulator_set_current(dev, 0): Expected -38, got -22\r\r\nFailures: 1'.endswith

-- 
Tom


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[U-Boot] [PATCH 14/14] mips: jz47xx: Add Creator CI20 platform

[Marek Vasut]

From: Paul Burton 

Add support for the Creator CI20 platform based on the JZ4780 SoC.
The DTS file comes from Linux 4.6 as of revision
78800558d104e003f9ae92e0107f1de39cf9de9f

So far, there are still a few details which will have to be fixed
once they are fleshed out in Linux:
- pinmux: Thus far, this board just pokes the pinmux registers to
  set the pinmux. For MMC in SPL, this will have to stay.
  But for full u-boot a proper pinmux driver will have to
  be added once the pinmux semantics in DT are in mainline
  Linux.
- ethernet,efuse: DT bindings are missing from mainline Linux.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 arch/mips/dts/Makefile|   1 +
 arch/mips/dts/ci20.dts| 114 ++
 arch/mips/mach-jz47xx/Kconfig |  11 ++
 board/imgtec/ci20/Kconfig |  35 +
 board/imgtec/ci20/Makefile|   5 +
 board/imgtec/ci20/README  |  10 ++
 board/imgtec/ci20/ci20.c  | 354 ++
 configs/ci20_defconfig|  28 
 include/configs/ci20.h| 105 +
 9 files changed, 663 insertions(+)
 create mode 100644 arch/mips/dts/ci20.dts
 create mode 100644 board/imgtec/ci20/Kconfig
 create mode 100644 board/imgtec/ci20/Makefile
 create mode 100644 board/imgtec/ci20/README
 create mode 100644 board/imgtec/ci20/ci20.c
 create mode 100644 configs/ci20_defconfig
 create mode 100644 include/configs/ci20.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 30fcc2b..e3473d9 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
+dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/ci20.dts b/arch/mips/dts/ci20.dts
new file mode 100644
index 000..9dab5e6
--- /dev/null
+++ b/arch/mips/dts/ci20.dts
@@ -0,0 +1,114 @@
+/dts-v1/;
+
+#include "jz4780.dtsi"
+
+/ {
+   compatible = "img,ci20", "ingenic,jz4780";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial3 = 
+   serial4 = 
+   };
+
+   chosen {
+   stdout-path = 
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x0 0x1000
+  0x3000 0x3000>;
+   };
+};
+
+ {
+   clock-frequency = <4800>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+
+   nandc: nand-controller@1 {
+   compatible = "ingenic,jz4780-nand";
+   reg = <1 0 0x100>;
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ingenic,bch-controller = <>;
+
+   ingenic,nemc-tAS = <10>;
+   ingenic,nemc-tAH = <5>;
+   ingenic,nemc-tBP = <10>;
+   ingenic,nemc-tAW = <15>;
+   ingenic,nemc-tSTRV = <100>;
+
+   nand@1 {
+   reg = <1>;
+
+   nand-ecc-step-size = <1024>;
+   nand-ecc-strength = <24>;
+   nand-ecc-mode = "hw";
+   nand-on-flash-bbt;
+
+   partitions {
+   compatible = "fixed-partitions";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   partition@0 {
+   label = "u-boot-spl";
+   reg = <0x0 0x0 0x0 0x80>;
+   };
+
+   partition@0x80 {
+   label = "u-boot";
+   reg = <0x0 0x80 0x0 0x20>;
+   };
+
+   partition@0xa0 {
+   label = "u-boot-env";
+   reg = <0x0 0xa0 0x0 0x20>;
+   };
+
+   partition@0xc0 {
+   label = "boot";
+   reg = <0x0 0xc0 0x0 0x400>;
+   };
+
+   partition@0x8c0 {
+   label = "system";
+   reg = <0x0 0x4c0 0x1 0xfb40>;
+   };
+   };
+   };
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   

[U-Boot] [PATCH 13/14] mips: jz47xx: Add minimal JZ MMC node

[Marek Vasut]

Add minimal JZ MMC node into the JZ4780 device tree.
This piece is picked from the CI20 Linux repository.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 arch/mips/dts/jz4780.dtsi | 20 
 1 file changed, 20 insertions(+)

diff --git a/arch/mips/dts/jz4780.dtsi b/arch/mips/dts/jz4780.dtsi
index b868b42..2b022c3 100644
--- a/arch/mips/dts/jz4780.dtsi
+++ b/arch/mips/dts/jz4780.dtsi
@@ -44,6 +44,26 @@
#clock-cells = <1>;
};
 
+   msc0: msc@1345 {
+   compatible = "ingenic,jz4780-mmc";
+   reg = <0x1345 0x1000>;
+
+   status = "disabled";
+
+   clocks = < JZ4780_CLK_MSC0>;
+   clock-names = "mmc";
+   };
+
+   msc1: msc@1346 {
+   compatible = "ingenic,jz4780-mmc";
+   reg = <0x1346 0x1000>;
+
+   clocks = < JZ4780_CLK_MSC1>;
+   clock-names = "mmc";
+
+   status = "disabled";
+   };
+
uart0: serial@1003 {
compatible = "ingenic,jz4780-uart";
reg = <0x1003 0x100>;
-- 
2.10.2

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[U-Boot] [PATCH 09/14] gpio: Add JZ47xx GPIO driver

[Marek Vasut]

From: Paul Burton 

Add primitive GPIO controller driver for the JZ47xx SoC.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 drivers/gpio/Kconfig   |  8 +
 drivers/gpio/Makefile  |  1 +
 drivers/gpio/gpio-jz47xx.c | 79 ++
 3 files changed, 88 insertions(+)
 create mode 100644 drivers/gpio/gpio-jz47xx.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 8d9ab52..4515883 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -221,4 +221,12 @@ config MPC85XX_GPIO
 
  The driver has been tested on MPC85XX, but it is likely that other
  PowerQUICC III devices will work as well.
+
+config JZ47XX_GPIO
+   bool "Ingenic JZ47xx GPIO driver"
+   depends on ARCH_JZ47XX
+   default y
+   help
+ Supports GPIO access on Ingenic JZ47xx SoCs.
+
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 8939226..e562022 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -58,3 +58,4 @@ obj-$(CONFIG_MVEBU_GPIO)  += mvebu_gpio.o
 obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
 obj-$(CONFIG_$(SPL_)PCF8575_GPIO)  += pcf8575_gpio.o
 obj-$(CONFIG_PM8916_GPIO)  += pm8916_gpio.o
+obj-$(CONFIG_JZ47XX_GPIO)  += gpio-jz47xx.o
diff --git a/drivers/gpio/gpio-jz47xx.c b/drivers/gpio/gpio-jz47xx.c
new file mode 100644
index 000..210120d
--- /dev/null
+++ b/drivers/gpio/gpio-jz47xx.c
@@ -0,0 +1,79 @@
+/*
+ * Ingenic JZ47xx GPIO
+ *
+ * Copyright (C) 2011 Marek Vasut 
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int gpio_get_value(unsigned gpio)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin);
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   if (value)
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT0S(port));
+   else
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT0C(port));
+
+   return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port));
+
+   return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port));
+
+   gpio_set_value(gpio, value);
+
+   return 0;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+   int port = gpio / 32;
+
+   if (port >= 6)
+   return -EINVAL;
+
+   return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+   return 0;
+}
-- 
2.10.2

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[U-Boot] [PATCH 11/14] mips: Add SPL header

[Marek Vasut]

From: Paul Burton 

Add header with SPL boot mode and type definitions.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 arch/mips/include/asm/spl.h | 35 +++
 1 file changed, 35 insertions(+)
 create mode 100644 arch/mips/include/asm/spl.h

diff --git a/arch/mips/include/asm/spl.h b/arch/mips/include/asm/spl.h
new file mode 100644
index 000..01baab6
--- /dev/null
+++ b/arch/mips/include/asm/spl.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef_ASM_SPL_H_
+#define_ASM_SPL_H_
+
+enum {
+   BOOT_DEVICE_RAM,
+   BOOT_DEVICE_MMC1,
+   BOOT_DEVICE_MMC2,
+   BOOT_DEVICE_MMC2_2,
+   BOOT_DEVICE_NAND,
+   BOOT_DEVICE_ONENAND,
+   BOOT_DEVICE_NOR,
+   BOOT_DEVICE_UART,
+   BOOT_DEVICE_SPI,
+   BOOT_DEVICE_USB,
+   BOOT_DEVICE_SATA,
+   BOOT_DEVICE_I2C,
+   BOOT_DEVICE_BOARD,
+   BOOT_DEVICE_NONE
+};
+
+/* Linker symbols. */
+extern char __bss_start[];
+extern ulong __bss_end;
+
+#ifndef CONFIG_DM
+extern gd_t gdata;
+#endif
+
+#endif
-- 
2.10.2

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[U-Boot] [PATCH 12/14] mips: jz47xx: Add JZ4780 SoC support

[Marek Vasut]

From: Paul Burton 

Add initial support for the Ingenic JZ47xx MIPS SoC.
The DTSI file comes from Linux 4.6 as of revision
78800558d104e003f9ae92e0107f1de39cf9de9f

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 arch/mips/Kconfig|   7 +
 arch/mips/Makefile   |   1 +
 arch/mips/dts/jz4780.dtsi| 137 ++
 arch/mips/mach-jz47xx/Kconfig|  15 +
 arch/mips/mach-jz47xx/Makefile   |   7 +
 arch/mips/mach-jz47xx/include/mach/jz4780.h  |  99 +
 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h | 457 
 arch/mips/mach-jz47xx/jz4780/Makefile|   5 +
 arch/mips/mach-jz47xx/jz4780/jz4780.c| 135 ++
 arch/mips/mach-jz47xx/jz4780/pll.c   | 527 +++
 arch/mips/mach-jz47xx/jz4780/sdram.c | 271 
 arch/mips/mach-jz47xx/jz4780/timer.c | 238 ++
 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds  |  52 +++
 arch/mips/mach-jz47xx/start.S|  99 +
 include/dt-bindings/clock/jz4780-cgu.h   |  88 
 15 files changed, 2138 insertions(+)
 create mode 100644 arch/mips/dts/jz4780.dtsi
 create mode 100644 arch/mips/mach-jz47xx/Kconfig
 create mode 100644 arch/mips/mach-jz47xx/Makefile
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780.h
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
 create mode 100644 arch/mips/mach-jz47xx/jz4780/Makefile
 create mode 100644 arch/mips/mach-jz47xx/jz4780/jz4780.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/pll.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/sdram.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/timer.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
 create mode 100644 arch/mips/mach-jz47xx/start.S
 create mode 100644 include/dt-bindings/clock/jz4780-cgu.h

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 097ad58..ec381b0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -70,6 +70,12 @@ config ARCH_ATH79
select OF_CONTROL
select DM
 
+config ARCH_JZ47XX
+   bool "Support Ingenic JZ47xx"
+   select SUPPORT_SPL
+   select OF_CONTROL
+   select DM
+
 config MACH_PIC32
bool "Support Microchip PIC32"
select OF_CONTROL
@@ -116,6 +122,7 @@ source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
 source "arch/mips/mach-ath79/Kconfig"
+source "arch/mips/mach-jz47xx/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index efe7e44..4f0f797 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -15,6 +15,7 @@ libs-y += arch/mips/lib/
 
 machine-$(CONFIG_SOC_AU1X00) += au1x00
 machine-$(CONFIG_ARCH_ATH79) += ath79
+machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
 machine-$(CONFIG_MACH_PIC32) += pic32
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
diff --git a/arch/mips/dts/jz4780.dtsi b/arch/mips/dts/jz4780.dtsi
new file mode 100644
index 000..b868b42
--- /dev/null
+++ b/arch/mips/dts/jz4780.dtsi
@@ -0,0 +1,137 @@
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "ingenic,jz4780";
+
+   cpuintc: interrupt-controller {
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "mti,cpu-interrupt-controller";
+   };
+
+   intc: interrupt-controller@10001000 {
+   compatible = "ingenic,jz4780-intc";
+   reg = <0x10001000 0x50>;
+
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interrupt-parent = <>;
+   interrupts = <2>;
+   };
+
+   ext: ext {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   };
+
+   rtc: rtc {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
+
+   cgu: jz4780-cgu@1000 {
+   compatible = "ingenic,jz4780-cgu";
+   reg = <0x1000 0x100>;
+
+   clocks = <>, <>;
+   clock-names = "ext", "rtc";
+
+   #clock-cells = <1>;
+   };
+
+   uart0: serial@1003 {
+   compatible = "ingenic,jz4780-uart";
+   reg = <0x1003 0x100>;
+
+   interrupt-parent = <>;
+   interrupts = <51>;
+
+   clocks = <>, < JZ4780_CLK_UART0>;
+   clock-names = "baud", "module";
+
+   status = "disabled";
+   };
+
+   uart1: serial@10031000 {
+   compatible = "ingenic,jz4780-uart";
+   reg = <0x10031000 0x100>;
+
+   

[U-Boot] [PATCH 10/14] misc: Add JZ47xx efuse driver

[Marek Vasut]

From: Paul Burton 

Add driver for the efuse block in the JZ47xx SOC.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 drivers/misc/Kconfig|   6 +++
 drivers/misc/Makefile   |   1 +
 drivers/misc/jz4780_efuse.c | 100 
 3 files changed, 107 insertions(+)
 create mode 100644 drivers/misc/jz4780_efuse.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 1aae4bc..ed0659b 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -83,6 +83,12 @@ config FSL_SEC_MON
  Security Monitor can be transitioned on any security failures,
  like software violations or hardware security violations.
 
+config JZ4780_EFUSE
+   bool "Ingenic JZ4780 eFUSE support"
+   depends on ARCH_JZ47XX
+   help
+ This selects support for the eFUSE on Ingenic JZ4780 SoCs.
+
 config MXC_OCOTP
bool "Enable MXC OCOTP Driver"
help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 9fbb5a7..6904a76 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -51,3 +51,4 @@ obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
 obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
 obj-$(CONFIG_QFW) += qfw.o
+obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
diff --git a/drivers/misc/jz4780_efuse.c b/drivers/misc/jz4780_efuse.c
new file mode 100644
index 000..e866b46
--- /dev/null
+++ b/drivers/misc/jz4780_efuse.c
@@ -0,0 +1,100 @@
+/*
+ * JZ4780 EFUSE driver
+ *
+ * Copyright (c) 2014 Imagination Technologies
+ * Author: Alex Smith 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define EFUSE_EFUCTRL  0xd0
+#define EFUSE_EFUCFG   0xd4
+#define EFUSE_EFUSTATE 0xd8
+#define EFUSE_EFUDATA(n)   (0xdc + ((n) * 4))
+
+#define EFUSE_EFUCTRL_RD_ENBIT(0)
+#define EFUSE_EFUCTRL_LEN_BIT  16
+#define EFUSE_EFUCTRL_LEN_MASK 0x1f
+#define EFUSE_EFUCTRL_ADDR_BIT 21
+#define EFUSE_EFUCTRL_ADDR_MASK0x1ff
+#define EFUSE_EFUCTRL_CS   BIT(30)
+
+#define EFUSE_EFUCFG_RD_STROBE_BIT 16
+#define EFUSE_EFUCFG_RD_STROBE_MASK0xf
+#define EFUSE_EFUCFG_RD_ADJ_BIT20
+#define EFUSE_EFUCFG_RD_ADJ_MASK   0xf
+
+#define EFUSE_EFUSTATE_RD_DONE BIT(0)
+
+static void jz4780_efuse_read_chunk(size_t addr, size_t count, u8 *buf)
+{
+   void __iomem *regs = (void __iomem *)NEMC_BASE;
+   size_t i;
+   u32 val;
+
+   val = EFUSE_EFUCTRL_RD_EN |
+ ((count - 1) << EFUSE_EFUCTRL_LEN_BIT) |
+ (addr << EFUSE_EFUCTRL_ADDR_BIT) |
+ ((addr > 0x200) ? EFUSE_EFUCTRL_CS : 0);
+   writel(val, regs + EFUSE_EFUCTRL);
+   /* FIXME -- wait_bit() */
+   while (!(readl(regs + EFUSE_EFUSTATE) & EFUSE_EFUSTATE_RD_DONE))
+   ;
+
+   if ((count % 4) == 0) {
+   for (i = 0; i < count / 4; i++) {
+   val = readl(regs + EFUSE_EFUDATA(i));
+   put_unaligned(val, (u32 *)(buf + (i * 4)));
+   }
+   } else {
+   val = readl(regs + EFUSE_EFUDATA(0));
+   if (count > 2)
+   buf[2] = (val >> 16) & 0xff;
+   if (count > 1)
+   buf[1] = (val >> 8) & 0xff;
+   buf[0] = val & 0xff;
+   }
+}
+
+static inline int jz4780_efuse_chunk_size(size_t count)
+{
+   if (count >= 32)
+   return 32;
+   else if ((count / 4) > 0)
+   return (count / 4) * 4;
+   else
+   return count % 4;
+}
+
+void jz4780_efuse_read(size_t addr, size_t count, u8 *buf)
+{
+   size_t chunk;
+
+   while (count > 0) {
+   chunk = jz4780_efuse_chunk_size(count);
+   jz4780_efuse_read_chunk(addr, chunk, buf);
+   addr += chunk;
+   buf += chunk;
+   count -= chunk;
+   }
+}
+
+void jz4780_efuse_init(u32 ahb2_rate)
+{
+   void __iomem *regs = (void __iomem *)NEMC_BASE;
+   u32 rd_adj, rd_strobe, tmp;
+
+   rd_adj = (((6500 * (ahb2_rate / 100)) / 100) + 0xf) / 2;
+   tmp = (((35000 * (ahb2_rate / 100)) / 100) - 4) - rd_adj;
+   rd_strobe = ((tmp + 0xf) / 2 < 7) ? 7 : (tmp + 0xf) / 2;
+
+   tmp = (rd_adj << EFUSE_EFUCFG_RD_ADJ_BIT) |
+ (rd_strobe << EFUSE_EFUCFG_RD_STROBE_BIT);
+   writel(tmp, regs + EFUSE_EFUCFG);
+}
-- 
2.10.2

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[U-Boot] [PATCH 04/14] serial: 16550: Add getfcr accessor

[Marek Vasut]

Add function which allows fetching the default FCR register setting
from platform data for DM , while retaining old behavior for non-DM
by returning UART_FCRVAL.

Signed-off-by: Marek Vasut 
Cc: Tom Rini 
Cc: Simon Glass 
---
V2: If CONFIG_DM_SERIAL and DEBUG_UART are enabled, the ns16550_getfcr()
can be invoked with NULL plat data . Check for this case and return
the default UART_FCRVAL then.
V3: It turns out that if DEBUG_UART is defined, $port points directly to
hardware registers. Add additional ifdef to handle the case where
debug uart is enabled with DM_SERIAL correctly.
V4: Use UART_FCRVAL in _debug_uart_init() directly
---
 drivers/serial/ns16550.c | 18 --
 include/ns16550.h|  1 +
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 6e9b946..3c9f3b0 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -121,6 +121,13 @@ static int ns16550_readb(NS16550_t port, int offset)
return serial_in_shift(addr + plat->reg_offset, plat->reg_shift);
 }
 
+static u32 ns16550_getfcr(NS16550_t port)
+{
+   struct ns16550_platdata *plat = port->plat;
+
+   return plat->fcr;
+}
+
 /* We can clean these up once everything is moved to driver model */
 #define serial_out(value, addr)\
ns16550_writeb(com_port, \
@@ -128,6 +135,11 @@ static int ns16550_readb(NS16550_t port, int offset)
 #define serial_in(addr) \
ns16550_readb(com_port, \
(unsigned char *)addr - (unsigned char *)com_port)
+#else
+static u32 ns16550_getfcr(NS16550_t port)
+{
+   return UART_FCRVAL;
+}
 #endif
 
 int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
@@ -171,7 +183,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out(0x7, _port->mdr1);   /* mode select reset TL16C750*/
 #endif
serial_out(UART_MCRVAL, _port->mcr);
-   serial_out(UART_FCRVAL, _port->fcr);
+   serial_out(ns16550_getfcr(com_port), _port->fcr);
if (baud_divisor != -1)
NS16550_setbrg(com_port, baud_divisor);
 #if defined(CONFIG_OMAP) || \
@@ -192,7 +204,7 @@ void NS16550_reinit(NS16550_t com_port, int baud_divisor)
serial_out(CONFIG_SYS_NS16550_IER, _port->ier);
NS16550_setbrg(com_port, 0);
serial_out(UART_MCRVAL, _port->mcr);
-   serial_out(UART_FCRVAL, _port->fcr);
+   serial_out(ns16550_getfcr(com_port), _port->fcr);
NS16550_setbrg(com_port, baud_divisor);
 }
 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
@@ -420,6 +432,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
return -EINVAL;
}
 
+   plat->fcr = UART_FCRVAL;
+
return 0;
 }
 #endif
diff --git a/include/ns16550.h b/include/ns16550.h
index 1311f4c..45fd68b 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -57,6 +57,7 @@ struct ns16550_platdata {
int reg_shift;
int clock;
int reg_offset;
+   u32 fcr;
 };
 
 struct udevice;
-- 
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[U-Boot] [PATCH 05/14] serial: 16550: Add port type as driver data

[Marek Vasut]

Add driver data to each compatible string to identify the type of
the port. Since all the ports in the driver are entirely compatible
with 16550 for now, all are marked with PORT_NS16550. But, there
are ports which have specific quirks, like the JZ4780 UART, which
do not have any DT property to denote the quirks. Instead, Linux
uses the compatible string to discern such ports and enable the
necessary quirks.

Signed-off-by: Marek Vasut 
Cc: Tom Rini 
Cc: Simon Glass 
---
 drivers/serial/ns16550.c | 26 --
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 3c9f3b0..3130a1d 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -360,6 +360,12 @@ int ns16550_serial_probe(struct udevice *dev)
return 0;
 }
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+enum {
+   PORT_NS16550 = 0,
+};
+#endif
+
 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 {
@@ -453,16 +459,16 @@ const struct dm_serial_ops ns16550_serial_ops = {
  * compatible string to your dts.
  */
 static const struct udevice_id ns16550_serial_ids[] = {
-   { .compatible = "ns16550" },
-   { .compatible = "ns16550a" },
-   { .compatible = "nvidia,tegra20-uart" },
-   { .compatible = "snps,dw-apb-uart" },
-   { .compatible = "ti,omap2-uart" },
-   { .compatible = "ti,omap3-uart" },
-   { .compatible = "ti,omap4-uart" },
-   { .compatible = "ti,am3352-uart" },
-   { .compatible = "ti,am4372-uart" },
-   { .compatible = "ti,dra742-uart" },
+   { .compatible = "ns16550",  .data = PORT_NS16550 },
+   { .compatible = "ns16550a", .data = PORT_NS16550 },
+   { .compatible = "nvidia,tegra20-uart",  .data = PORT_NS16550 },
+   { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
+   { .compatible = "ti,omap2-uart",.data = PORT_NS16550 },
+   { .compatible = "ti,omap3-uart",.data = PORT_NS16550 },
+   { .compatible = "ti,omap4-uart",.data = PORT_NS16550 },
+   { .compatible = "ti,am3352-uart",   .data = PORT_NS16550 },
+   { .compatible = "ti,am4372-uart",   .data = PORT_NS16550 },
+   { .compatible = "ti,dra742-uart",   .data = PORT_NS16550 },
{}
 };
 #endif
-- 
2.10.2

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[U-Boot] [PATCH 08/14] mmc: Add JZ47xx SD/MMC controller driver

[Marek Vasut]

From: Paul Burton 

Add driver for the JZ47xx MSC controller.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 drivers/mmc/Kconfig  |   6 +
 drivers/mmc/Makefile |   1 +
 drivers/mmc/jz_mmc.c | 443 +++
 3 files changed, 450 insertions(+)
 create mode 100644 drivers/mmc/jz_mmc.c

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index aca438b8..761b886 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -102,6 +102,12 @@ config MMC_UNIPHIER
help
  This selects support for the SD/MMC Host Controller on UniPhier SoCs.
 
+config JZ47XX_MMC
+   bool "Ingenic JZ47xx SD/MMC Host Controller support"
+   depends on ARCH_JZ47XX
+   help
+ This selects support for the SD Card Controller on Ingenic JZ47xx 
SoCs.
+
 config SANDBOX_MMC
bool "Sandbox MMC support"
depends on MMC && SANDBOX
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index d850758..5f7cca3 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
 obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
 obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
 obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o
+obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
new file mode 100644
index 000..213fe63
--- /dev/null
+++ b/drivers/mmc/jz_mmc.c
@@ -0,0 +1,443 @@
+/*
+ * Ingenic JZ MMC driver
+ *
+ * Copyright (c) 2013 Imagination Technologies
+ * Author: Paul Burton 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Registers */
+#define MSC_STRPCL 0x000
+#define MSC_STAT   0x004
+#define MSC_CLKRT  0x008
+#define MSC_CMDAT  0x00c
+#define MSC_RESTO  0x010
+#define MSC_RDTO   0x014
+#define MSC_BLKLEN 0x018
+#define MSC_NOB0x01c
+#define MSC_SNOB   0x020
+#define MSC_IMASK  0x024
+#define MSC_IREG   0x028
+#define MSC_CMD0x02c
+#define MSC_ARG0x030
+#define MSC_RES0x034
+#define MSC_RXFIFO 0x038
+#define MSC_TXFIFO 0x03c
+#define MSC_LPM0x040
+#define MSC_DMAC   0x044
+#define MSC_DMANDA 0x048
+#define MSC_DMADA  0x04c
+#define MSC_DMALEN 0x050
+#define MSC_DMACMD 0x054
+#define MSC_CTRL2  0x058
+#define MSC_RTCNT  0x05c
+#define MSC_DBG0x0fc
+
+/* MSC Clock and Control Register (MSC_STRPCL) */
+
+#define MSC_STRPCL_EXIT_MULTIPLE   BIT(7)
+#define MSC_STRPCL_EXIT_TRANSFER   BIT(6)
+#define MSC_STRPCL_START_READWAIT  BIT(5)
+#define MSC_STRPCL_STOP_READWAIT   BIT(4)
+#define MSC_STRPCL_RESET   BIT(3)
+#define MSC_STRPCL_START_OPBIT(2)
+#define MSC_STRPCL_CLOCK_CONTROL_STOP  BIT(0)
+#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
+
+/* MSC Status Register (MSC_STAT) */
+
+#define MSC_STAT_AUTO_CMD_DONE BIT(31)
+#define MSC_STAT_IS_RESETTING  BIT(15)
+#define MSC_STAT_SDIO_INT_ACTIVE   BIT(14)
+#define MSC_STAT_PRG_DONE  BIT(13)
+#define MSC_STAT_DATA_TRAN_DONEBIT(12)
+#define MSC_STAT_END_CMD_RES   BIT(11)
+#define MSC_STAT_DATA_FIFO_AFULL   BIT(10)
+#define MSC_STAT_IS_READWAIT   BIT(9)
+#define MSC_STAT_CLK_ENBIT(8)
+#define MSC_STAT_DATA_FIFO_FULLBIT(7)
+#define MSC_STAT_DATA_FIFO_EMPTY   BIT(6)
+#define MSC_STAT_CRC_RES_ERR   BIT(5)
+#define MSC_STAT_CRC_READ_ERRORBIT(4)
+#define MSC_STAT_CRC_WRITE_ERROR   BIT(2)
+#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
+#define MSC_STAT_TIME_OUT_RES  BIT(1)
+#define MSC_STAT_TIME_OUT_READ BIT(0)
+
+/* MSC Bus Clock Control Register (MSC_CLKRT) */
+#define MSC_CLKRT_CLK_RATE_MASK0x7
+
+/* MSC Command Sequence Control Register (MSC_CMDAT) */
+
+#define MSC_CMDAT_IO_ABORT BIT(11)
+#define MSC_CMDAT_BUS_WIDTH_1BIT   (0x0 << 9)
+#define MSC_CMDAT_BUS_WIDTH_4BIT   (0x2 << 9)
+#define MSC_CMDAT_DMA_EN   BIT(8)
+#define MSC_CMDAT_INIT BIT(7)
+#define MSC_CMDAT_BUSY BIT(6)
+#define MSC_CMDAT_STREAM_BLOCK BIT(5)
+#define MSC_CMDAT_WRITEBIT(4)
+#define MSC_CMDAT_DATA_EN  

[U-Boot] [PATCH 06/14] serial: 16550: Add Ingenic JZ4780 support

[Marek Vasut]

Add compatibility string for the Ingenic JZ4780 SoC, the necessary
UART enable bit into FCR and register shift. Neither are encoded
in the DTS coming from Linux, so we need to support it this way.

Signed-off-by: Marek Vasut 
Cc: Tom Rini 
Cc: Simon Glass 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 drivers/serial/ns16550.c | 7 +++
 include/ns16550.h| 3 +++
 2 files changed, 10 insertions(+)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 3130a1d..d00161c 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -363,6 +363,7 @@ int ns16550_serial_probe(struct udevice *dev)
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 enum {
PORT_NS16550 = 0,
+   PORT_JZ4780,
 };
 #endif
 
@@ -370,6 +371,7 @@ enum {
 int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 {
struct ns16550_platdata *plat = dev->platdata;
+   const u32 port_type = dev_get_driver_data(dev);
fdt_addr_t addr;
struct clk clk;
int err;
@@ -439,6 +441,10 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
}
 
plat->fcr = UART_FCRVAL;
+   if (port_type == PORT_JZ4780) {
+   plat->fcr |= UART_FCR_UME;
+   plat->reg_shift = 2;
+   }
 
return 0;
 }
@@ -461,6 +467,7 @@ const struct dm_serial_ops ns16550_serial_ops = {
 static const struct udevice_id ns16550_serial_ids[] = {
{ .compatible = "ns16550",  .data = PORT_NS16550 },
{ .compatible = "ns16550a", .data = PORT_NS16550 },
+   { .compatible = "ingenic,jz4780-uart",  .data = PORT_JZ4780  },
{ .compatible = "nvidia,tegra20-uart",  .data = PORT_NS16550 },
{ .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
{ .compatible = "ti,omap2-uart",.data = PORT_NS16550 },
diff --git a/include/ns16550.h b/include/ns16550.h
index 45fd68b..7c97036 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -118,6 +118,9 @@ typedef struct NS16550 *NS16550_t;
 #define UART_FCR_RXSR  0x02 /* Receiver soft reset */
 #define UART_FCR_TXSR  0x04 /* Transmitter soft reset */
 
+/* Ingenic JZ47xx specific UART-enable bit. */
+#define UART_FCR_UME   0x10
+
 /*
  * These are the definitions for the Modem Control Register
  */
-- 
2.10.2

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[U-Boot] [PATCH 07/14] mmc: Tinification of the mmc code

[Marek Vasut]

Add new configuration option CONFIG_MMC_TINY which strips away all
memory allocation within the MMC code and code for handling multiple
cards. This allows extremely space-constrained SPL code use the MMC
framework.

Signed-off-by: Marek Vasut 
Cc: Tom Rini 
Cc: Simon Glass 
---
V2: Switch the MMC_TINY option to Kconfig
---
 common/spl/spl_mmc.c |  6 +-
 drivers/mmc/Kconfig  | 16 
 drivers/mmc/mmc.c| 31 ++-
 drivers/mmc/mmc_legacy.c | 32 
 include/mmc.h|  1 +
 5 files changed, 84 insertions(+), 2 deletions(-)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 43c1030..3cad998 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -306,7 +306,11 @@ static int spl_mmc_load_image(struct spl_image_info 
*spl_image,
if (part == 7)
part = 0;
 
-   err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
+   if (CONFIG_IS_ENABLED(MMC_TINY))
+   err = mmc_switch_part(mmc, part);
+   else
+   err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), 
part);
+
if (err) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
puts("spl: mmc partition switch failed\n");
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 24f4b28..aca438b8 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -26,6 +26,22 @@ config DM_MMC_OPS
  option will be removed as soon as all DM_MMC drivers use it, as it
  will the only supported behaviour.
 
+config SPL_MMC_TINY
+   bool "Tiny MMC framework in SPL"
+   default n
+   help
+ Enable MMC framework tinification support. This option is useful if
+ if your SPL is extremely size constrained. Heed the warning, enable
+ this option if and only if you know exactly what you are doing, if
+ you are reading this help text, you most likely have no idea :-)
+
+ The MMC framework is reduced to bare minimum to be useful. No malloc
+ support is needed for the MMC framework operation with this option
+ enabled. The framework supports exactly one MMC device and exactly
+ one MMC driver. The MMC driver can be adjusted to avoid any malloc
+ operations too, which can remove the need for malloc support in SPL
+ and thus further reduce footprint.
+
 config MSM_SDHCI
bool "Qualcomm SDHCI controller"
depends on DM_MMC && BLK && DM_MMC_OPS
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 6e25b67..19c4225 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -30,6 +30,29 @@ static const unsigned int sd_au_size[] = {
SZ_16M / 512,   (SZ_16M + SZ_8M) / 512, SZ_32M / 512,   SZ_64M / 512,
 };
 
+#if CONFIG_IS_ENABLED(MMC_TINY)
+static struct mmc mmc_static;
+struct mmc *find_mmc_device(int dev_num)
+{
+   return _static;
+}
+
+void mmc_do_preinit(void)
+{
+   struct mmc *m = _static;
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+   mmc_set_preinit(m, 1);
+#endif
+   if (m->preinit)
+   mmc_start_init(m);
+}
+
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
+{
+   return >block_dev;
+}
+#endif
+
 #ifndef CONFIG_DM_MMC_OPS
 __weak int board_mmc_getwp(struct mmc *mmc)
 {
@@ -259,7 +282,11 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t 
start, lbaint_t blkcnt,
if (!mmc)
return 0;
 
-   err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
+   if (CONFIG_IS_ENABLED(MMC_TINY))
+   err = mmc_switch_part(mmc, block_dev->hwpart);
+   else
+   err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
+
if (err < 0)
return 0;
 
@@ -1804,8 +1831,10 @@ int mmc_initialize(bd_t *bis)
initialized = 1;
 
 #ifndef CONFIG_BLK
+#if !CONFIG_IS_ENABLED(MMC_TINY)
mmc_list_init();
 #endif
+#endif
ret = mmc_probe(bis);
if (ret)
return ret;
diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c
index 25361d1..bdf9d98 100644
--- a/drivers/mmc/mmc_legacy.c
+++ b/drivers/mmc/mmc_legacy.c
@@ -13,6 +13,7 @@
 static struct list_head mmc_devices;
 static int cur_dev_num = -1;
 
+#if !CONFIG_IS_ENABLED(MMC_TINY)
 struct mmc *find_mmc_device(int dev_num)
 {
struct mmc *m;
@@ -62,6 +63,7 @@ void mmc_do_preinit(void)
mmc_start_init(m);
}
 }
+#endif
 
 void mmc_list_init(void)
 {
@@ -109,6 +111,35 @@ void print_mmc_devices(char separator)
 void print_mmc_devices(char separator) { }
 #endif
 
+#if CONFIG_IS_ENABLED(MMC_TINY)
+static struct mmc mmc_static = {
+   .dsr_imp= 0,
+   .dsr= 0x,
+   .block_dev = {
+   .if_type= 

[U-Boot] [PATCH 01/14] mips: Let cache.h be included from assembly source

[Marek Vasut]

Add ifdef __ASSEMBLY__ around the function prototype to let cache.h
be included from assembly code.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 arch/mips/include/asm/cache.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 669c362..83165d5 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -19,6 +19,7 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
 
+#ifndef __ASSEMBLY__
 /**
  * mips_cache_probe() - Probe the properties of the caches
  *
@@ -27,5 +28,6 @@
  * functions such as flush_cache may be called.
  */
 void mips_cache_probe(void);
+#endif
 
 #endif /* __MIPS_CACHE_H__ */
-- 
2.10.2

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[U-Boot] [PATCH 03/14] mmc: Fix warning if debug() is not used

[Marek Vasut]

If debug() is not used, then the whole content of debug(...) will
be removed by the preprocessor, which will result in the following
warning. This patch adds __maybe_unused annotation to fix this.

drivers/mmc/mmc.c: In function ‘mmc_init’:
drivers/mmc/mmc.c:1685:11: warning: variable ‘start’ set but not used 
[-Wunused-but-set-variable]
  unsigned start;

Signed-off-by: Marek Vasut 
Cc: Pantelis Antoniou 
Cc: Tom Rini 
---
 drivers/mmc/mmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index d6b7e4f..6e25b67 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1708,7 +1708,7 @@ static int mmc_complete_init(struct mmc *mmc)
 int mmc_init(struct mmc *mmc)
 {
int err = 0;
-   unsigned start;
+   __maybe_unused unsigned start;
 #ifdef CONFIG_DM_MMC
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
 
-- 
2.10.2

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[U-Boot] [PATCH 02/14] spl: mmc: Fix build without LIBCOMMON_SUPPORT

[Marek Vasut]

If CONFIG_SPL_LIBCOMMON_SUPPORT is undefined, the following error
will happen, so fix it.

In file included from common/spl/spl_mmc.c:11:0:
common/spl/spl_mmc.c: In function ‘spl_mmc_load_image’:
include/spl.h:18:30: error: label at end of compound statement
 #define MMCSD_MODE_UNDEFINED 0
  ^
common/spl/spl_mmc.c:335:7: note: in expansion of macro ‘MMCSD_MODE_UNDEFINED’
  case MMCSD_MODE_UNDEFINED:
   ^
Signed-off-by: Marek Vasut 
Cc: Pantelis Antoniou 
Cc: Tom Rini 
---
 common/spl/spl_mmc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 0b681c2..43c1030 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -343,10 +343,12 @@ static int spl_mmc_load_image(struct spl_image_info 
*spl_image,
 
break;
case MMCSD_MODE_UNDEFINED:
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
default:
+   {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
puts("spl: mmc: wrong boot mode\n");
 #endif
+   }
}
 
return err;
-- 
2.10.2

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[U-Boot] [PATCH 13/14] tools: Allow crc8 to be used

[Olliver Schinagl]

This patch enables crc8 to be used from within the tools directory using
u-boot/crc.h.

Signed-off-by: Olliver Schinagl 
Reviewed-by: Joe Hershberger 
Signed-off-by: Olliver Schinagl 
---
 include/u-boot/crc.h | 3 +++
 tools/Makefile   | 1 +
 2 files changed, 4 insertions(+)

diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h
index 754ac72..6764d58 100644
--- a/include/u-boot/crc.h
+++ b/include/u-boot/crc.h
@@ -9,6 +9,9 @@
 #ifndef _UBOOT_CRC_H
 #define _UBOOT_CRC_H
 
+/* lib/crc8.c */
+unsigned int crc8(unsigned int crc_start, const unsigned char *vptr, int len);
+
 /* lib/crc32.c */
 uint32_t crc32 (uint32_t, const unsigned char *, uint);
 uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint);
diff --git a/tools/Makefile b/tools/Makefile
index 400588c..06afdb0 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -191,6 +191,7 @@ fdtgrep-objs += $(LIBFDT_OBJS) fdtgrep.o
 # that won't build on some weird host compiler -- though there are lots of
 # exceptions for files that aren't complaint.
 HOSTCFLAGS_crc32.o := -pedantic
+HOSTCFLAGS_crc8.o := -pedantic
 HOSTCFLAGS_md5.o := -pedantic
 HOSTCFLAGS_sha1.o := -pedantic
 HOSTCFLAGS_sha256.o := -pedantic
-- 
2.10.2

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[U-Boot] Rockchip RK3288 u-boot with mainline kernel

[Rick Bronson]

Hi All,

  I've got unsupported RK3288 hardware running the latest git u-boot to
SPL as explained in
http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.rockchip.  My goal
is to run the mainline (ie. not Android) Linux kernel on this hardware
and wondered:

 - Do I need to get the latest git u-boot to run before I can run the
mainline kernel?  Or can I use
github.com/linux-rockchip/u-boot-rockchip.git, which I have running
u-boot fully.

 - The device tree seems to be in two places, once via:

resource_tool --image=resource2.img --pack linux/logo.bmp ${DTS}.dtb

  that gets put into the resource file and then again at the end of the
kernel via CONFIG_ARM_APPENDED_DTB.  Do I need both?  When I do both
I get things like:


Unknow param: MACHINE_MODEL:rk30sdk!
Unknow param: MACHINE_ID:007!


  Thanks much for any help.

  Rick Bronson


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[U-Boot] [PATCH] armv8/spin_table.c: fix spin table release address

[Tsung-Han Lin]

Since only the master core will relocate itself, the spin-table release
address seen by master core and other slave cores is different.
This commit fixes this issue by recalculating the spin-table release
address' offset instead of leaving it to compiler.

Signed-off-by: Tsung-Han Lin 
---
 arch/arm/cpu/armv8/spin_table.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/spin_table.c b/arch/arm/cpu/armv8/spin_table.c
index ec1c9b8ddb6f..1169e2df5f47 100644
--- a/arch/arm/cpu/armv8/spin_table.c
+++ b/arch/arm/cpu/armv8/spin_table.c
@@ -11,12 +11,16 @@
 
 int spin_table_update_dt(void *fdt)
 {
+   extern unsigned long _start;
int cpus_offset, offset;
const char *prop;
int ret;
unsigned long rsv_addr = (unsigned long)_table_reserve_begin;
unsigned long rsv_size = _table_reserve_end -
_table_reserve_begin;
+   unsigned long unreloc_spin_release_addr = CONFIG_SYS_TEXT_BASE +
+   (unsigned long)_table_cpu_release_addr -
+   (unsigned long)&_start;
 
cpus_offset = fdt_path_offset(fdt, "/cpus");
if (cpus_offset < 0)
@@ -47,7 +51,7 @@ int spin_table_update_dt(void *fdt)
continue;
 
ret = fdt_setprop_u64(fdt, offset, "cpu-release-addr",
-   (unsigned long)_table_cpu_release_addr);
+   unreloc_spin_release_addr);
if (ret)
return -ENOSPC;
}
-- 
2.7.4

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Re: [U-Boot] [PATCH] sun8i_emac: Fix mdio read sequence

[Dr. Philipp Tomsich]

Jagan,

> On 25 Nov 2016, at 17:18, Jagan Teki  wrote:
> 
> On Wed, Nov 16, 2016 at 7:10 AM, Andre Przywara  
> wrote:
>> From: Philipp Tomsich 
>> 
>> To send a parametrized command to the PHY over MDIO, we should write
>> the data first, the trigger the execution by the command register
>> write. Fix the access pattern in our MDIO write routine.
>> Apparently this doesn't really matter with the Realtek PHY on the
>> Pine64, but other PHYs (which require more setup) will choke on
>> the wrong order.
> 
> Any tested-by this on non-realtek, because I always remember to have
> CMD with DATA sequence for mdio write for most of the PHY's and ie
> default sequence though.

We have a KSZ9031 on all our boards… so it was tested against the KSZ9031.

Cheers,
Philipp.
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[U-Boot] (no subject)

[Rick Bronson]

Hi All,

  I've got nsupported RK3288 hardware running the latest git u-boot to SPL
as explained in
http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.rockchip.  My goal
is to run the mainline (ie. not Android) Linux kernel on this hardware
and wondered:

 - Do I need to get the latest git u-boot to run before I can run the
mainline kernel?  Or can I use
github.com/linux-rockchip/u-boot-rockchip.git, which I have running
u-boot fully.

 - The device tree seems to be in two places, once via:

resource_tool --image=resource2.img --pack linux/logo.bmp ${DTS}.dtb

  that gets put into the resource file and then again at the end of the
kernel via CONFIG_ARM_APPENDED_DTB.  Do I need both?  When I do both
I get things like:


Unknow param: MACHINE_MODEL:rk30sdk!
Unknow param: MACHINE_ID:007!


  Thanks much.

  Rick


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[U-Boot] [PATCH] armv8/spin_table.c: fix spin table release address

[Tsung-Han Lin]

Since only the master core will relocate itself, the spin-table release
address seen by master core and other slave cores is different.
This commit fixes this issue by recalculating the spin-table release
address' offset instead of leaving it to compiler.

Signed-off-by: Tsung-Han Lin 
---
 arch/arm/cpu/armv8/spin_table.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/spin_table.c b/arch/arm/cpu/armv8/spin_table.c
index ec1c9b8ddb6f..1169e2df5f47 100644
--- a/arch/arm/cpu/armv8/spin_table.c
+++ b/arch/arm/cpu/armv8/spin_table.c
@@ -11,12 +11,16 @@
 
 int spin_table_update_dt(void *fdt)
 {
+   extern unsigned long _start;
int cpus_offset, offset;
const char *prop;
int ret;
unsigned long rsv_addr = (unsigned long)_table_reserve_begin;
unsigned long rsv_size = _table_reserve_end -
_table_reserve_begin;
+   unsigned long unreloc_spin_release_addr = CONFIG_SYS_TEXT_BASE +
+   (unsigned long)_table_cpu_release_addr -
+   (unsigned long)&_start;
 
cpus_offset = fdt_path_offset(fdt, "/cpus");
if (cpus_offset < 0)
@@ -47,7 +51,7 @@ int spin_table_update_dt(void *fdt)
continue;
 
ret = fdt_setprop_u64(fdt, offset, "cpu-release-addr",
-   (unsigned long)_table_cpu_release_addr);
+   unreloc_spin_release_addr);
if (ret)
return -ENOSPC;
}
-- 
2.7.4

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[U-Boot] About U-boot's TPM

[Ronny Ko]

Hi Simon,

I have a question about using a TPM from U-Boot. I try to run U-Boot
on Minnowboard MAX, which has a firmware TPM (fTPM), instead of discrete
TPM (dTPM). I wonder if the way of using fTPM from U-Boot is the same as
using dTPM. I suppose the answer is yes, if an fTPM is simply a virtual
version of dTPM. Or is it not so?

Ronny
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[U-Boot] Macronix NOR_SPI and Quad I/O

[Champ, Andy]

Hi all,


in the table in drivers/mtd/spi/spi_flash_ids.c there is a flag WR_QPP set 
against Macronix devices (including the ones Dumitru is just adding).


This is used when programming the devices on a 4-bit bus to select the command 
to use for programming - either CMD_QUAD_PAGE_PROGRAM (0x32) or 
CMD_PAGE_PROGRAM (0x2).


The Macronix devices that I have a spec for do not mention command 0x32. Each 
of the devices that I have a spec for ( MX25L25635F MX25U51245G MX25V8035F and 
MX25V1635F ) use command 0x38 instead.


This would suggest to me that devices that support quad I/O, and have Macronix 
NOR-SPI, won't be able to program them.


Am I missing something, or is this a problem?


I'm not able to check because we don't use Quad I/O.


Regards

Andy Champ

Amazon Lab126

Cambridge, UK.
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[U-Boot] [PATCH 14/14] tools: Add tool to add crc8 to a mac address

[Olliver Schinagl]

This patch adds a little tool that takes a generic MAC address and
generates a CRC byte for it. The output is the full MAC address without
any separators, ready written into an EEPROM.

Signed-off-by: Olliver Schinagl 
Signed-off-by: Olliver Schinagl 
---
 tools/.gitignore|  1 +
 tools/Makefile  |  4 +++
 tools/gen_ethaddr_crc.c | 75 +
 3 files changed, 80 insertions(+)
 create mode 100644 tools/gen_ethaddr_crc.c

diff --git a/tools/.gitignore b/tools/.gitignore
index cb1e722..0d1f076 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -6,6 +6,7 @@
 /fit_check_sign
 /fit_info
 /gen_eth_addr
+/gen_ethaddr_crc
 /ifdtool
 /img2srec
 /kwboot
diff --git a/tools/Makefile b/tools/Makefile
index 06afdb0..4879ded 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -43,6 +43,10 @@ envcrc-objs := envcrc.o lib/crc32.o common/env_embedded.o 
lib/sha1.o
 hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr
 HOSTCFLAGS_gen_eth_addr.o := -pedantic
 
+hostprogs-$(CONFIG_CMD_NET) += gen_ethaddr_crc
+gen_ethaddr_crc-objs := gen_ethaddr_crc.o lib/crc8.o
+HOSTCFLAGS_gen_ethaddr_crc.o := -pedantic
+
 hostprogs-$(CONFIG_CMD_LOADS) += img2srec
 HOSTCFLAGS_img2srec.o := -pedantic
 
diff --git a/tools/gen_ethaddr_crc.c b/tools/gen_ethaddr_crc.c
new file mode 100644
index 000..fe9896d
--- /dev/null
+++ b/tools/gen_ethaddr_crc.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2016
+ * Olliver Schinagl 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ARP_HLEN 6 /* Length of hardware address */
+#define ARP_HLEN_ASCII (ARP_HLEN * 2) + (ARP_HLEN - 1) /* with separators */
+#define ARP_HLEN_LAZY (ARP_HLEN * 2) /* separatorless hardware address length 
*/
+
+uint8_t nibble_to_hex(const char *nibble, bool lo)
+{
+   return (strtol(nibble, NULL, 16) << (lo ? 0 : 4)) & (lo ? 0x0f : 0xf0);
+}
+
+int process_mac(const char *mac_address)
+{
+   uint8_t ethaddr[ARP_HLEN + 1] = { 0x00 };
+   uint_fast8_t i = 0;
+
+   while (*mac_address != '\0') {
+   char nibble[2] = { 0x00, '\n' }; /* for strtol */
+
+   nibble[0] = *mac_address++;
+   if (isxdigit(nibble[0])) {
+   if (isupper(nibble[0]))
+   nibble[0] = tolower(nibble[0]);
+   ethaddr[i >> 1] |= nibble_to_hex(nibble, (i % 2) != 0);
+   i++;
+   }
+   }
+
+   for (i = 0; i < ARP_HLEN; i++)
+   printf("%.2x", ethaddr[i]);
+   printf("%.2x\n", crc8(0, ethaddr, ARP_HLEN));
+
+   return 0;
+}
+
+void print_usage(char *cmdname)
+{
+   printf("Usage: %s \n", cmdname);
+   puts(" may be with or without separators.");
+   puts("Valid seperators are ':' and '-'.");
+   puts(" digits are in base 16.\n");
+}
+
+int main(int argc, char *argv[])
+{
+   if (argc < 2) {
+   print_usage(argv[0]);
+   return 1;
+   }
+
+   if (!((strlen(argv[1]) == ARP_HLEN_ASCII) || (strlen(argv[1]) == 
ARP_HLEN_LAZY))) {
+   puts("The MAC address is not valid.\n");
+   print_usage(argv[0]);
+   return 1;
+   }
+
+   if (process_mac(argv[1])) {
+   puts("Failed to calculate the MAC's checksum.");
+   return 1;
+   }
+
+   return 0;
+}
-- 
2.10.2

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[U-Boot] [PATCH] arm: imx: wandboard: fix compile error if CONFIG_VIDEO is deactivated

[Sven Ebenfeld]

When I tried to deactivate VIDEO support for the Wandboard, it still
tried to initialize the Framebuffer and so on. That is the reason for
the added ifdefs. CONFIG_VIDEO is enabled in the configuration as default
and therefore nothing changes for the default user.

The structs mx6dl_i2c2_pad_info and mx6q_i2c2_pad_info are only available
when CONFIG_IPUV3 are set and should not be tried to access, when that
define is not defined.

Signed-off-by: Sven Ebenfeld 
---
 board/wandboard/wandboard.c | 2 ++
 include/configs/wandboard.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index b3f3b34..2c9dc8b 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -442,11 +442,13 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#if defined(CONFIG_VIDEO_IPUV3)
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, _i2c2_pad_info);
if (is_mx6dq())
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, _i2c2_pad_info);
else
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, _i2c2_pad_info);
+#endif
 
return 0;
 }
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 8c5cf33..406591c 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -74,6 +74,7 @@
 #define CONFIG_PHY_ATHEROS
 
 /* Framebuffer */
+#ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
@@ -85,6 +86,7 @@
 #define CONFIG_CMD_HDMIDETECT
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
+#endif
 
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define CONFIG_EXTRA_ENV_SETTINGS \
-- 
2.7.4

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Re: [U-Boot] [Pull request v2]: u-boot-spi/sunxi

[Tom Rini]

On Fri, Nov 25, 2016 at 07:42:02PM +0530, Jagan Teki wrote:
> On Fri, Nov 25, 2016 at 6:32 AM, Chen-Yu Tsai  wrote:
> > Hi,
> >
> > On Fri, Nov 25, 2016 at 3:00 AM, Jagan Teki  wrote:
> >> Hi Tom,
> >>
> >> These are the pending patches, from u-boot-sunxi/next.
> >>
> >> Will send sunxi PR on top of u-boot-sunxi repo once I get the access,
> >> meanwhile please take this PR.
> >>
> >> Hans, Let me know if I miss any patches from next.
> >>
> >> Changes for v2:
> >> - Dropped 3 patches, which are still in review.
> >>
> >> thanks!
> >> Jagan.
> >>
> >> The following changes since commit 
> >> fc127d184aea293ec415dd66e3282dba0b66c5f3:
> >>
> >>   colibri_pxa270: drop edit, elf, fpga, hush, regex et al. for space 
> >> reason (2016-11-23 13:53:20 +0100)
> >>
> >> are available in the git repository at:
> >>
> >>   git://git.denx.de/u-boot-spi.git sunxi
> >>
> >> for you to fetch changes up to 2e34089969b9443b969c3b209b73799df4451eb1:
> >>
> >>   mtd: nand: add support for the TC58NVG2S0H chip (2016-11-25 00:23:25 
> >> +0530)
> >>
> >> 
> >> Boris Brezillon (1):
> >>   mtd: nand: add support for the TC58NVG2S0H chip
> >>
> >> Chen-Yu Tsai (9):
> >>   ARM: PSCI: Set ARMV7_PSCI_NR_CPUS default to 8 for sun9i/A80
> >>   sunxi: Add CCI-400 and CPUCFG registers base address for sun9i/A80
> >>   sunxi: Add base address of secure SRAM B for sun9i/A80
> >>   sunxi: Use secure SRAM B for secure RAM for sun9i/A80
> >>   sunxi: Add PRCM register definition for sun9i/A80
> >>   sunxi: Add CPUCFG register definitions for sun9i/A80
> >>   sunxi: Add support for TZPC on sun9i/A80
> >>   sunxi: Add basic PSCI implementation for A80
> >>   sunxi: Enable PSCI on sun9i/A80
> >
> > Can you drop the last enablement patch?
> >
> > The GIC setup is buggy at the moment. It will either respond to interrupts,
> > then return from exceptions in secure mode, or, if the GIC base address
> > is fixed, not return at all. :(
> >
> > This is something I'm still trying to wrap my head around.
> 
> OK, then as a matter of better review(something more) and look like
> these are related please work on all 9 patches.

And I'll wait for a v3 PR, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] mx6sx: Add initial support for UDOO Neo Board

[Fabio Estevam]

On Fri, Nov 25, 2016 at 4:56 PM, Breno Lima  wrote:
> UDOO Neo Board is a development board from Seco that has three models:
>  - UDOO Neo Basic
>  - UDOO Neo Basic Kick Starter
>  - UDOO Neo Extended
>  - UDOO Neo Full
>
> All versions are based on the i.MX6 SoloX processor.
>
> For more details about the UDOO Neo board, please refer to:
> http://www.udoo.org/udoo-neo/
>
> This work is based on a previous commit of Francesco Montefoschi
> :
> https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed574961844
>
> Only tested on the UDOO Neo Full board.
>
> Signed-off-by: Breno Lima 

Looks good:

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH v2 10/22] spi: Add error checking for invalid bus widths

[Fabio Estevam]

On Fri, Nov 25, 2016 at 5:38 PM, Simon Glass  wrote:

> So it is correct to print an error, and then continue? This error will
> almost never occur and thus it wastes code space. SPI is sensitive
> because it can be used in SPL. Linux doesn't care about code size as
> much.
>
> So how about either:
> 1. debug() and return an error
> 2. debug() and skip the error

I prefer option 2, thanks.
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Re: [U-Boot] [PATCH 0/9] Switch bcm283x platform to use OF_CONTROL

[Simon Glass]

Hi,

On 16 November 2016 at 06:43, Fabian Vogt  wrote:
> Hi,
>
> any news on this? As far as I can tell nothing happened after my last
> reply to this thread, so: Ping!

Adding Tom - the patches are assigned to him in Patchwork.

- Simon

>
> Thanks,
> Fabian
>
> Am Montag, 26. September 2016, 14:26:42 CET schrieben Sie:
>> This patch series modifies the used drivers to work with OF_CONTROL
>> and switches the board code and configs to use it.
>> The added device trees are directly from the linux kernel tree
>> and can thus be used for booting the (upstream) kernel.
>>
>> Fabian Vogt (9):
>>   gpio: bcm2835: add device tree support
>>   serial: bcm283x_mu: add device tree support
>>   serial: pl01x: expose skip_init platdata option in DT
>>   fdt: add dt-bindings for bcm2835
>>   fdt: import bcm283x device tree sources from the linux kernel tree
>>   fdt: adjust bcm283x device tree for u-boot
>>   serial: bcm283x_mu: support disabling after initialization
>>   board: rpi: move uart deactivation to board_init
>>   ARM: bcm283x: use OF_CONTROL for bcm283x
>>
>>  arch/arm/Kconfig   |   1 +
>>  arch/arm/dts/Makefile  |   9 +
>>  arch/arm/dts/bcm2835-rpi-a-plus.dts|  35 +++
>>  arch/arm/dts/bcm2835-rpi-a.dts |  28 ++
>>  arch/arm/dts/bcm2835-rpi-b-plus.dts|  36 +++
>>  arch/arm/dts/bcm2835-rpi-b-rev2.dts|  29 ++
>>  arch/arm/dts/bcm2835-rpi-b.dts |  23 ++
>>  arch/arm/dts/bcm2835-rpi.dtsi  |  86 ++
>>  arch/arm/dts/bcm2835.dtsi  |  25 ++
>>  arch/arm/dts/bcm2836-rpi-2-b.dts   |  40 +++
>>  arch/arm/dts/bcm2836.dtsi  |  78 +
>>  arch/arm/dts/bcm2837-rpi-3-b.dts   |  30 ++
>>  arch/arm/dts/bcm2837.dtsi  |  76 +
>>  arch/arm/dts/bcm283x-rpi-smsc9512.dtsi |  19 ++
>>  arch/arm/dts/bcm283x-rpi-smsc9514.dtsi |  19 ++
>>  arch/arm/dts/bcm283x-uboot.dtsi|  22 ++
>>  arch/arm/dts/bcm283x.dtsi  | 323 
>> +
>>  board/raspberrypi/rpi/rpi.c|  77 ++---
>>  configs/rpi_2_defconfig|   2 +
>>  configs/rpi_3_32b_defconfig|   2 +
>>  configs/rpi_3_defconfig|   2 +
>>  configs/rpi_defconfig  |   2 +
>>  doc/device-tree-bindings/gpio/bcm2835-gpio.txt |   5 +
>>  .../serial/bcm2835-aux-uart.txt|  10 +
>>  doc/device-tree-bindings/serial/pl01x.txt  |   3 +
>>  drivers/gpio/bcm2835_gpio.c|  24 ++
>>  drivers/serial/serial_bcm283x_mu.c |  46 ++-
>>  drivers/serial/serial_pl01x.c  |   2 +
>>  include/configs/rpi.h  |   1 -
>>  include/dt-bindings/clock/bcm2835-aux.h|  17 ++
>>  include/dt-bindings/clock/bcm2835.h|  66 +
>>  include/dt-bindings/pinctrl/bcm2835.h  |  27 ++
>>  include/dt-bindings/power/raspberrypi-power.h  |  41 +++
>>  33 files changed, 1152 insertions(+), 54 deletions(-)
>>  create mode 100644 arch/arm/dts/bcm2835-rpi-a-plus.dts
>>  create mode 100644 arch/arm/dts/bcm2835-rpi-a.dts
>>  create mode 100644 arch/arm/dts/bcm2835-rpi-b-plus.dts
>>  create mode 100644 arch/arm/dts/bcm2835-rpi-b-rev2.dts
>>  create mode 100644 arch/arm/dts/bcm2835-rpi-b.dts
>>  create mode 100644 arch/arm/dts/bcm2835-rpi.dtsi
>>  create mode 100644 arch/arm/dts/bcm2835.dtsi
>>  create mode 100644 arch/arm/dts/bcm2836-rpi-2-b.dts
>>  create mode 100644 arch/arm/dts/bcm2836.dtsi
>>  create mode 100644 arch/arm/dts/bcm2837-rpi-3-b.dts
>>  create mode 100644 arch/arm/dts/bcm2837.dtsi
>>  create mode 100644 arch/arm/dts/bcm283x-rpi-smsc9512.dtsi
>>  create mode 100644 arch/arm/dts/bcm283x-rpi-smsc9514.dtsi
>>  create mode 100644 arch/arm/dts/bcm283x-uboot.dtsi
>>  create mode 100644 arch/arm/dts/bcm283x.dtsi
>>  create mode 100644 doc/device-tree-bindings/gpio/bcm2835-gpio.txt
>>  create mode 100644 doc/device-tree-bindings/serial/bcm2835-aux-uart.txt
>>  create mode 100644 include/dt-bindings/clock/bcm2835-aux.h
>>  create mode 100644 include/dt-bindings/clock/bcm2835.h
>>  create mode 100644 include/dt-bindings/pinctrl/bcm2835.h
>>  create mode 100644 include/dt-bindings/power/raspberrypi-power.h
>>
>>
>
>
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Re: [U-Boot] Please pull u-boot-fdt

[Simon Glass]

+Tom

On 25 November 2016 at 09:51, Simon Glass  wrote:
> Hi Tom.
>
> The following changes since commit 543bd27353d2c5679057fe09aa2d02259687ff32:
>
>   MAINTAINERS: SUNXI: Update maintainership (2016-11-22 09:07:26 -0500)
>
> are available in the git repository at:
>
>   git://git.denx.de/u-boot-fdt.git
>
> for you to fetch changes up to 643f8d4c07788f28ad283e3fcb29d88a4b16a4be:
>
>   MAINTAINERS: Fix syntax and update filename for FDT (2016-11-25
> 09:48:09 -0700)
>
> 
> Andreas Färber (1):
>   MAINTAINERS: Fix syntax and update filename for FDT
>
>  MAINTAINERS | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> Regards,
> Simon
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[U-Boot] Please pull u-boot-rockchip

[Simon Glass]

Hi Tom,

This includes support for minnie and mickey Chromebooks, rk3036 USB
support, some power improvements and other minor things.


The following changes since commit 543bd27353d2c5679057fe09aa2d02259687ff32:

  MAINTAINERS: SUNXI: Update maintainership (2016-11-22 09:07:26 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-rockchip.git

for you to fetch changes up to fc334a074b7309e08c8f9571f4e5025f345a:

  rockchip: configs: correct partitions 'boot' size (2016-11-25 10:03:32 -0700)


Andreas Färber (2):
  arm: dts: Fix Rockchip sort order
  arm: rockchip: Fix typo in ROCKCHIP_RK3288 help

Jacob Chen (1):
  rockchip: configs: correct partitions 'boot' size

Keerthy (3):
  power: regulator: Introduce regulator_set_value_force function
  power: regulator: Add limits checking while setting voltage
  power: regulator: Add limits checking while setting current

Kever Yang (5):
  evb-rk3399: deduced the dram node size when space reserved
  config: evb-rk3399: enable PWM_ROCKCHIP
  config: rk3036: enable configs for USB HOST
  config: rk3036: enable fix regulator
  dts: arm: rk3036: add usb vbus node

Simon Glass (21):
  rockchip: video: Correct HDMI data source selection
  rockchip: video: Correct VOP clock selection
  rockchip: Allow jerry to use of-platdata
  stdio: Correct code style nits
  stdio: Correct numbering logic in stdio_probe_device()
  spi: Add of-platdata support to SPI and SPI flash
  rockchip: spi: Add support for of-platdata
  rockchip: spi: Honour the deactivation delay
  spi: Add a debug() on bind failure
  video: Use cache-alignment in video_sync()
  video: Track whether a display is in use
  rockchip: video: Check for device in use
  rockchip: Move jerry to use of-platdata
  rockchip: Rename jerry files to veyron
  rockchip: veyron: Add a note about the SDRAM voltage
  rockchip: Move jerry SDRAM settings into its own .dts file
  rockchip: clk: Support setting ACLK
  rockchip: veyron: Adjust ARM clock after relocation
  rockchip: video: Avoid using u8 in the HDMI driver
  rockchip: Add support for veyron-mickey (Chromebit)
  rockchip: Add support for veyron-minnie (ASUS Chromebook Flip)

 arch/arm/dts/Makefile  |   6 +-
 arch/arm/dts/rk3036-sdk.dts|  37 +++-
 arch/arm/dts/rk3288-veyron-chromebook.dtsi |   2 +
 arch/arm/dts/{rk3288-jerry.dts => rk3288-veyron-jerry.dts} |  16 +-
 arch/arm/dts/rk3288-veyron-mickey.dts  | 277

 arch/arm/dts/rk3288-veyron-minnie.dts  | 301
++
 arch/arm/dts/rk3288-veyron.dtsi|   8 -
 arch/arm/mach-rockchip/Kconfig |   2 +-
 arch/arm/mach-rockchip/rk3288-board-spl.c  |   4 +
 arch/arm/mach-rockchip/rk3288-board.c  |  44 
 arch/arm/mach-rockchip/rk3288/Kconfig  |  21 +-
 board/google/chromebook_jerry/Kconfig  |  15 --
 board/google/chromebook_jerry/MAINTAINERS  |   6 -
 board/google/chromebook_jerry/jerry.c  |   7 -
 board/google/veyron/Kconfig|  47 
 board/google/veyron/MAINTAINERS|  20 ++
 board/google/{chromebook_jerry => veyron}/Makefile |   2 +-
 board/google/veyron/veyron.c   |  13 ++
 board/rockchip/evb_rk3399/evb-rk3399.c |   2 +-
 cmd/regulator.c|   5 +-
 common/stdio.c |   9 +-
 configs/chromebit_mickey_defconfig |  84 +++
 configs/chromebook_jerry_defconfig |  10 +-
 configs/chromebook_minnie_defconfig|  82 +++
 configs/evb-rk3399_defconfig   |   1 +
 configs/kylin-rk3036_defconfig |   4 +
 drivers/clk/rockchip/clk_rk3288.c  |   7 +
 drivers/mtd/spi/spi_flash.c|   2 +-
 drivers/power/regulator/regulator-uclass.c |  24 ++
 drivers/spi/rk_spi.c   |  44 +++-
 drivers/spi/spi-uclass.c   |  18 +-
 drivers/video/display-uclass.c |  18 +-
 drivers/video/rockchip/rk_hdmi.c   |  33 +--
 drivers/video/rockchip/rk_vop.c|  16 +-
 drivers/video/video-uclass.c   |   3 +-
 include/configs/rk3036_common.h|   7 +
 include/configs/rockchip-common.h  |   2 +-
 

Re: [U-Boot] [PATCH v2 2/4] board: popmetal: de-assert the host rst pin in board init

[Simon Glass]

Hi Kever,

On 24 November 2016 at 00:29, Kever Yang  wrote:
> The PopMetal board have a on board FE1.1 usb 2.0 hub which connect to
> the usb host port, we need to de-assert its reset pin to enable it.
>
> Signed-off-by: Kever Yang 
> ---
>
> Changes in v2:
> - move the vbus power enable into dwc2 driver
>
>  board/chipspark/popmetal_rk3288/popmetal-rk3288.c | 17 +
>  1 file changed, 17 insertions(+)
>
> diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c 
> b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
> index aad74ef..ed82b2b 100644
> --- a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
> +++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
> @@ -6,6 +6,7 @@
>
>  #include 
>  #include 
> +#include 
>
>  void board_boot_order(u32 *spl_boot_list)
>  {
> @@ -13,3 +14,19 @@ void board_boot_order(u32 *spl_boot_list)
> spl_boot_list[0] = BOOT_DEVICE_MMC2;
> spl_boot_list[1] = BOOT_DEVICE_MMC1;
>  }
> +
> +#define GPIO7A3_HUB_RST227
> +
> +int rk_board_late_init(void)
> +{
> +   int ret;
> +
> +   ret = gpio_request(GPIO7A3_HUB_RST, "hub_rst");
> +   if (ret)
> +   return ret;
> +   ret = gpio_direction_output(GPIO7A3_HUB_RST, 1);
> +   if (ret)

Can we get this from the device tree instead of hard-coding it? Then
it can go in generic code.

> +   return ret;
> +
> +   return 0;
> +}
> --
> 1.9.1
>

Regards,
Simon
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Re: [U-Boot] [PATCH v2 22/22] rockchip: Add support for veyron-mickey (Chromebit)

[Simon Glass]

On 13 November 2016 at 14:22, Simon Glass  wrote:
> This adds support for the Asus Chromebit, and RK3288-based device designed
> to plug directly into an HDMI monitor. The device tree file comes from
> Linux v4.8.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2:
> - Enable only the active eMMC port
>
>  arch/arm/dts/Makefile |   1 +
>  arch/arm/dts/rk3288-veyron-mickey.dts | 277 
> ++
>  arch/arm/mach-rockchip/rk3288-board-spl.c |   3 +-
>  arch/arm/mach-rockchip/rk3288/Kconfig |   9 +
>  board/google/veyron/Kconfig   |  16 ++
>  board/google/veyron/MAINTAINERS   |   7 +
>  configs/chromebit_mickey_defconfig|  84 +
>  7 files changed, 396 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/rk3288-veyron-mickey.dts
>  create mode 100644 configs/chromebit_mickey_defconfig

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Re: [U-Boot] [PATCH v2 17/22] rockchip: veyron: Add a note about the SDRAM voltage

[Simon Glass]

On 13 November 2016 at 14:22, Simon Glass  wrote:
> Add a comment to indicate that we are not supporting the PWM regulator
> yet.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2:
> - Add new patch with note about the SDRAM voltage
>
>  board/google/veyron/veyron.c | 6 ++
>  1 file changed, 6 insertions(+)

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Re: [U-Boot] [PATCH v2 19/22] rockchip: clk: Support setting ACLK

[Simon Glass]

On 13 November 2016 at 14:22, Simon Glass  wrote:
> Add basic support for setting the ARM clock, since this allows us to run
> at maximum speed in U-Boot. Currently only a single speed is supported
> (1.8GHz).
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  drivers/clk/rockchip/clk_rk3288.c | 7 +++
>  1 file changed, 7 insertions(+)

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Re: [U-Boot] [PATCH v2 13/22] video: Track whether a display is in use

[Simon Glass]

On 13 November 2016 at 14:22, Simon Glass  wrote:
> Mark a display as in use when display_enable() is called. This can avoid
> a display being used by multiple video-output devices.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  drivers/video/display-uclass.c | 18 +-
>  include/display.h  | 10 ++
>  2 files changed, 27 insertions(+), 1 deletion(-)

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Re: [U-Boot] [PATCH v2 16/22] rockchip: Rename jerry files to veyron

[Simon Glass]

On 13 November 2016 at 14:22, Simon Glass  wrote:
> At present we have a single rk3288-based Chromebook: chromebook_jerry. But
> all such Chromebooks can use the same binary with only device-tree
> differences. The family name is 'veyron', so rename the files accordingly.
>
> Also update the device-tree filename since this currently differs from
> Linux.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  arch/arm/dts/Makefile  | 2 +-
>  arch/arm/dts/{rk3288-jerry.dts => rk3288-veyron-jerry.dts} | 0
>  arch/arm/mach-rockchip/rk3288/Kconfig  | 2 +-
>  board/google/{chromebook_jerry => veyron}/Kconfig  | 4 ++--
>  board/google/{chromebook_jerry => veyron}/MAINTAINERS  | 4 ++--
>  board/google/{chromebook_jerry => veyron}/Makefile | 2 +-
>  board/google/{chromebook_jerry/jerry.c => veyron/veyron.c} | 0
>  configs/chromebook_jerry_defconfig | 2 +-
>  include/configs/{chromebook_jerry.h => veyron.h}   | 0
>  9 files changed, 8 insertions(+), 8 deletions(-)
>  rename arch/arm/dts/{rk3288-jerry.dts => rk3288-veyron-jerry.dts} (100%)
>  rename board/google/{chromebook_jerry => veyron}/Kconfig (74%)
>  rename board/google/{chromebook_jerry => veyron}/MAINTAINERS (60%)
>  rename board/google/{chromebook_jerry => veyron}/Makefile (81%)
>  rename board/google/{chromebook_jerry/jerry.c => veyron/veyron.c} (100%)
>  rename include/configs/{chromebook_jerry.h => veyron.h} (100%)

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Re: [U-Boot] [PATCH v2 12/22] video: Use cache-alignment in video_sync()

[Simon Glass]

On 13 November 2016 at 14:22, Simon Glass  wrote:
> Sometimes the frame buffer is not a multiple of the cache line size.
> Adjust the cache-flushing code to avoid cache warnings/errors in this
> case.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  drivers/video/video-uclass.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

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Re: [U-Boot] [PATCH v2 06/22] stdio: Correct numbering logic in stdio_probe_device()

[Simon Glass]

On 13 November 2016 at 14:22, Simon Glass  wrote:
> The current code assumes that the devices are ordered corresponding to
> their alias value. But (for example) video1 can come before video0 in the
> device tree.
>
> Correct this, by always looking for device 0 first. After that we can fall
> back to finding the first available device.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  common/stdio.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

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Re: [U-Boot] [PATCH v2 10/22] spi: Add error checking for invalid bus widths

[Simon Glass]

Hi,

On 25 November 2016 at 09:59, Fabio Estevam  wrote:
> On Fri, Nov 25, 2016 at 2:57 PM, Jagan Teki  wrote:
>
>> Yeah, ie what if dts has a wrong value and do print that and continue
>> with default width, so-that the user will update this for next run.
>> Since it's not key a attribute to break or decide functionality better
>> to go with it.
>
> Agreed. This also matches with the kernel behaviour.

So it is correct to print an error, and then continue? This error will
almost never occur and thus it wastes code space. SPI is sensitive
because it can be used in SPL. Linux doesn't care about code size as
much.

So how about either:
1. debug() and return an error
2. debug() and skip the error

Regards,
Simon
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Re: [U-Boot] [PATCH v2 05/22] stdio: Correct code style nits

[Simon Glass]

On 13 November 2016 at 14:21, Simon Glass  wrote:
> Fix a few code style nits in stdio_get_by_name().
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  common/stdio.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

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Re: [U-Boot] [PATCH 3/4] dts: arm: rk3036: add usb vbus node

[Simon Glass]

On 11 November 2016 at 09:17, Simon Glass  wrote:
> On 8 November 2016 at 03:13, Kever Yang  wrote:
>> add fix regulator node for usb vbus power control.
>>
>> Signed-off-by: Kever Yang 
>> ---
>>
>>  arch/arm/dts/rk3036-sdk.dts | 37 +
>>  1 file changed, 33 insertions(+), 4 deletions(-)
>
> Acked-by: Simon Glass 

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Re: [U-Boot] [PATCH v2 03/22] rockchip: Allow jerry to use of-platdata

[Simon Glass]

On 13 November 2016 at 14:21, Simon Glass  wrote:
> This board always boots from SPI, so update the code to support that with
> of-platdata. The boot source is not currently available with of-platdata.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  arch/arm/mach-rockchip/rk3288-board-spl.c | 2 ++
>  1 file changed, 2 insertions(+)

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Re: [U-Boot] [PATCH 1/4] config: rk3036: enable configs for USB HOST

[Simon Glass]

On 11 November 2016 at 09:16, Simon Glass  wrote:
> Hi Kever,
>
> On 8 November 2016 at 03:13, Kever Yang  wrote:
>> rk3036 using dwc2 usb controller, need enable relate configs for it.
>>
>> Signed-off-by: Kever Yang 
>> ---
>>
>>  configs/kylin-rk3036_defconfig  | 3 +++
>>  include/configs/rk3036_common.h | 7 +++
>>  2 files changed, 10 insertions(+)
>
> Acked-by: Simon Glass 
>
> Are these added in the right order? Did you use 'make savedefconfig' 
> afterwards?

No response - please send a follow-up patch if needed.

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Re: [U-Boot] [PATCH 2/4] config: rk3036: enable fix regulator

[Simon Glass]

On 11 November 2016 at 09:17, Simon Glass  wrote:
> On 8 November 2016 at 03:13, Kever Yang  wrote:
>> usb host vbus power is using gpio fix regulator, enable it.
>>
>> Signed-off-by: Kever Yang 
>> ---
>>
>>  configs/kylin-rk3036_defconfig | 1 +
>>  1 file changed, 1 insertion(+)
>
> Acked-by: Simon Glass 

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Re: [U-Boot] [PATCH v2 01/22] rockchip: video: Correct HDMI data source selection

[Simon Glass]

On 13 November 2016 at 14:21, Simon Glass  wrote:
> This code currently always selects the second source. It only worked
> because both sources are set up.
>
> With the change to only init video devices that are present in the stdout
> environment variable, this fails. Fix it.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  drivers/video/rockchip/rk_hdmi.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

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Re: [U-Boot] [PATCH] evb-rk3399: deduced the dram node size when space reserved

[Simon Glass]

On 11 November 2016 at 09:16, Simon Glass  wrote:
> On 7 November 2016 at 02:40, Andreas Färber  wrote:
>> Am 07.11.2016 um 09:30 schrieb Kever Yang:
>>> The size dram node need to be deduced by the same amount of reserved space.
>>>
>>>
>>
>> Reported-by: Andreas Färber 
>>
>>> Signed-off-by: Kever Yang 
>>
>> Reviewed-by: Andreas Färber 
>
> Acked-by: Simon Glass 

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Re: [U-Boot] [PATCH] config: evb-rk3399: enable PWM_ROCKCHIP

[Simon Glass]

On 11 November 2016 at 09:16, Simon Glass  wrote:
> On 7 November 2016 at 01:30, Kever Yang  wrote:
>> PWM_ROCKCHIP need to enable for PWM regulator, this config
>> is missing during rebase and new patch set in previous submission.
>>
>> Signed-off-by: Kever Yang 
>> ---
>>
>>  configs/evb-rk3399_defconfig | 1 +
>>  1 file changed, 1 insertion(+)
>
> Acked-by: Simon Glass 

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Re: [U-Boot] [PATCH 2/3] power: regulator: Add limits checking while setting voltage

[Simon Glass]

On 26 October 2016 at 10:31, Simon Glass  wrote:
> On 26 October 2016 at 01:12, Keerthy  wrote:
>> Currently the specific set ops functions are directly
>> called without any check for voltage limits for a regulator.
>> Check for them and proceed.
>>
>> Signed-off-by: Keerthy 
>> ---
>>  drivers/power/regulator/regulator-uclass.c | 5 +
>>  1 file changed, 5 insertions(+)
>
> Reviewed-by: Simon Glass 

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Re: [U-Boot] [PATCH] arm: rockchip: Fix typo in ROCKCHIP_RK3288 help

[Simon Glass]

On 2 November 2016 at 14:14, Simon Glass  wrote:
> On 2 November 2016 at 11:03, Andreas Färber  wrote:
>> UART,s -> UARTs, to avoid this spreading via copy
>>
>> Signed-off-by: Andreas Färber 
>> ---
>>  arch/arm/mach-rockchip/Kconfig | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> Acked-by: Simon Glass 

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Re: [U-Boot] [PATCH 1/3] power: regulator: Introduce regulator_set_value_force function

[Simon Glass]

On 26 October 2016 at 10:31, Simon Glass  wrote:
> On 26 October 2016 at 01:12, Keerthy  wrote:
>> In case we want to force a particular value on a regulator
>> irrespective of the min/max constraints for testing purposes
>> one can call regulator_set_value_force function.
>>
>> Signed-off-by: Keerthy 
>> ---
>>  cmd/regulator.c|  5 -
>>  drivers/power/regulator/regulator-uclass.c | 14 ++
>>  include/power/regulator.h  | 10 ++
>>  3 files changed, 28 insertions(+), 1 deletion(-)
>
> Reviewed-by: Simon Glass 

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Re: [U-Boot] [PATCH] arm: dts: Fix Rockchip sort order

[Simon Glass]

On 2 November 2016 at 14:14, Simon Glass  wrote:
> On 2 November 2016 at 11:02, Andreas Färber  wrote:
>> Sort rk3036 before rk3288.
>>
>> Signed-off-by: Andreas Färber 
>> ---
>>  arch/arm/dts/Makefile | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> Acked-by: Simon Glass 

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Re: [U-Boot] [PATCH 3/3] power: regulator: Add limits checking while setting current

[Simon Glass]

On 27 October 2016 at 19:52, Simon Glass  wrote:
> Hi Keethy,
>
> On 26 October 2016 at 20:20, Keerthy  wrote:
>>
>>
>> On Wednesday 26 October 2016 10:01 PM, Simon Glass wrote:
>>>
>>> Hi Keerthy,
>>>
>>> On 26 October 2016 at 01:12, Keerthy  wrote:

 Currently the specific set ops functions are directly
 called without any check for min/max current limits for a regulator.
 Check for them and proceed.

 Signed-off-by: Keerthy 
 ---
  drivers/power/regulator/regulator-uclass.c | 5 +
  1 file changed, 5 insertions(+)

 diff --git a/drivers/power/regulator/regulator-uclass.c
 b/drivers/power/regulator/regulator-uclass.c
 index 34087c8..4c4bd29 100644
 --- a/drivers/power/regulator/regulator-uclass.c
 +++ b/drivers/power/regulator/regulator-uclass.c
 @@ -80,6 +80,11 @@ int regulator_get_current(struct udevice *dev)
  int regulator_set_current(struct udevice *dev, int uA)
  {
 const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
 +   struct dm_regulator_uclass_platdata *uc_pdata;
 +
 +   uc_pdata = dev_get_uclass_platdata(dev);
 +   if (uA < uc_pdata->min_uA || uA > uc_pdata->max_uA)
 +   return -EINVAL;
>>>
>>>
>>> Do all drivers have these values set?
>>
>> Simon,
>>
>> Agree that not all drivers set this. But when someone calls set_current with
>> some value there needs to be some boundary conditions for this right? Hence
>> i made this patch.
>>
>
> I think your patch is good. I'm just worried about breaking boards.
> Can you take a quick look at existing users and make sure that won't
> happen?

This seems OK in my testing, so:

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Re: [U-Boot] [PATCH] cmd/fdt: Make fdt get value endian-safe for single-cell properties

[Simon Glass]

Hi Andreas,

On 15 November 2016 at 17:18, Simon Glass  wrote:
> Hi Andreas,
>
> On 15 November 2016 at 10:07, Andreas Färber  wrote:
>> Hi Simon,
>>
>> Am 28.10.2016 um 03:52 schrieb Simon Glass:
>>> On 27 October 2016 at 05:44, Andreas Färber  wrote:
 Am 26.10.2016 um 21:19 schrieb Simon Glass:
> On 26 October 2016 at 09:02, Andreas Färber  wrote:
>> On a Raspberry Pi 2 disagreements on cell endianness can be observed:
>>
>>   U-Boot> fdt print /soc/gpio@7e20 phandle
>>   phandle = <0x000d>
>>   U-Boot> fdt get value myvar /soc/gpio@7e20 phandle; printenv myvar
>>   myvar=0x0D00
>>
>> Fix this by always treating the pointer as __be32 and converting it in
>> fdt_value_setenv(), like its counterpart fdt_parse_prop() already does.
>>
>> Fixes: bc80295 ("fdt: Add get commands to fdt")
>> Cc: Joe Hershberger 
>> Cc: Gerald Van Baren 
>> Signed-off-by: Andreas Färber 
>> ---
>>  cmd/fdt.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> The patch looks good, but please can you add a function comment to
> fdt_value_setenv() ?

 Where and what should it say? There is a general comment above the
 function already, and by choosing __be32* instead of uint32_t* I thought
 my code was fairly self-documenting.
>>>
>>> It should explain what the function does and, importantly, what the
>>> arguments and return value are.
>>
>> Can you please do general documentation updates in a separate patch on
>> top of this bug fix, so that we can get this merged soonish?
>
> Actually that is what I was asking you to do. A separate patch is fine :-)

Are you able to respin this or send another patch? If we are going to
get this applied for he next release, now is the time...

Also I think it is better to use fdt32_to_cpu() instead __be32_to_cpu().

Regards,
Simon
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Re: [U-Boot] [PATCH 00/82] x86: Add initial support for 64-bit U-Boot

[Simon Glass]

Hi Bin,

On 17 October 2016 at 19:25, Bin Meng  wrote:
> Hi Simon,
>
> On Tue, Oct 18, 2016 at 6:17 AM, Simon Glass  wrote:
>> Hi Bin,
>>
>> On 10 October 2016 at 23:36, Bin Meng  wrote:
>>> Hi Simon,
>>>
>>> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
 At present U-Boot runs entirely in 32-bit mode on x86, except for the
 initial switch from 16-bit mode. On 64-bit machines it is possible to run
 in 64-bit mode. This series starts the process of adding this support.

 The main benefit of 64-bit mode for a boot loader is direct access to all
 available memory. There are also more registers, but this makes very little
 difference.

 This feature is implemented by putting all of the 32-bit code in an SPL
 build. SPL then runs through all the init that has to be done in 32-bit
 mode, changes to 64-bit mode and then jumps to U-Boot proper.

 Typically the total code size increases slightly. For example, on link in
 32-bit mode, U-Boot has around 480KB of code (admittedly with a large
 number of features enabled). In 64-bit mode, U-Boot falls to around 460KB,
 but SPL adds another 60KB, for a net increase of 40KB. Partly this is due
 to code duplication and partly it is due to the worse code density of
 64-bit code on x86.

 Many major features are not implemented yet, for example:
 - SDRAM sizing
 - Booting linux
 - FSP support
 - EFI support
 - SCSI device init
 - Running video ROMs

 Still, this is a big step forward towards full 64-bit support. To enable 
 it,
 select CONFIG_X86_RUN_64BIT.

 This series is available at u-boot-x86/64-working

>>>
>>> Looks it requires a 64-bit toolchain to compile 64-bit U-Boot. For
>>> example, I used kernel.org i386 toolchain to compile 64-bit U-Boot, I
>>> got:
>>>
>>> include/asm-generic/bitops/__fls.h: In function '__fls':
>>> include/asm-generic/bitops/__fls.h:17:2: warning: left shift count >=
>>> width of type
>>>   if (!(word & (~0ul << 32))) {
>>>   ^
>>> include/asm-generic/bitops/__fls.h:19:3: warning: left shift count >=
>>> width of type
>>>word <<= 32;
>>>^
>>> include/asm-generic/bitops/__fls.h:22:2: warning: left shift count >=
>>> width of type
>>>   if (!(word & (~0ul << (BITS_PER_LONG-16 {
>>>   ^
>>> include/asm-generic/bitops/__fls.h:26:2: warning: left shift count >=
>>> width of type
>>>   if (!(word & (~0ul << (BITS_PER_LONG-8 {
>>>   ^
>>> include/asm-generic/bitops/__fls.h:30:2: warning: left shift count >=
>>> width of type
>>>   if (!(word & (~0ul << (BITS_PER_LONG-4 {
>>>   ^
>>> include/asm-generic/bitops/__fls.h:34:2: warning: left shift count >=
>>> width of type
>>>   if (!(word & (~0ul << (BITS_PER_LONG-2 {
>>>   ^
>>> include/asm-generic/bitops/__fls.h:38:2: warning: left shift count >=
>>> width of type
>>>   if (!(word & (~0ul << (BITS_PER_LONG-1
>>>   ^
>>> arch/x86/cpu/intel_common/microcode.c: In function 'microcode_read_rev':
>>> arch/x86/cpu/intel_common/microcode.c:79:2: error: PIC register
>>> clobbered by 'ebx' in 'asm'
>>>   asm volatile (
>>>   ^
>>> make[2]: *** [arch/x86/cpu/intel_common/microcode.o] Error 1
>>
>> Yes, that is expected.
>
> Can we make the i386 toolchain work? Linux 64-bit kernel build does
> not require the toolchain to be 64-bit.

I can fix the header file warnings, but things like pushq do not seem
to be supported on the i386 toolchain. Perhaps this is something to
look at later.

>
>>>
>>> After I switched to 64-bit toolchain from kernel.org (x86_64-linux),
>>> there was no such warnings/errors, but I still got build failure at
>>> last.
>>>
>>>   ./tools/binman/binman -d u-boot.dtb -O . -I . -I
>>> ./board/google/chromebook_link u-boot-x86-16bit.bin
>>> Traceback (most recent call last):
>>>   File "./tools/binman/binman", line 31, in 
>>> import control
>>>   File "./tools/binman/control.py", line 17, in 
>>> from image import Image
>>>   File "./tools/binman/image.py", line 12, in 
>>> import entry
>>>   File "./tools/binman/etype/entry.py", line 8, in 
>>> import importlib
>>> ImportError: No module named importlib
>>> make: *** [u-boot.rom] Error 1
>>
>> What version of python do you use?
>
> $ python -V
> Python 2.7.12

I thought importlib was implemented in 2.7 (I am using 2.7.6 which is
older). But I'll add a work-around for this as it seems I was wrong.

Regards,
Simon
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Re: [U-Boot] [PATCH v2] libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORY

[Simon Glass]

Hi,

On 23 October 2016 at 21:01, Simon Glass  wrote:
> On 21 October 2016 at 01:12, Alexey Brodkin  
> wrote:
>> Hello Masahiro-san,
>>
>> On Fri, 2016-10-21 at 10:58 +0900, Masahiro Yamada wrote:
>>> Hi Alexey,
>>>
>>> 2016-10-20 20:55 GMT+09:00 Alexey Brodkin :
>>> >
>>> > Hello Masahiro-san,
>>> >
>>> > On Thu, 2016-10-20 at 09:15 +0900, Masahiro Yamada wrote:
>>> > >
>>> > > Commit e2f88dfd2d96 ("libfdt: Introduce new ARCH_FIXUP_FDT option")
>>> > > allows us to skip memory setup of DTB, but a problem for ARM is that
>>> > > spin_table_update_dt() and psci_update_dt() are skipped as well if
>>> > > CONFIG_ARCH_FIXUP_FDT is disabled.
>>> > >
>>> > > This commit allows us to skip only fdt_fixup_memory_banks() instead
>>> > > of the whole of arch_fixup_fdt().  It will be useful when we want to
>>> > > use a memory node from a kernel DTB as is, but need some fixups for
>>> > > Spin-Table/PSCI.
>>> > >
>>> > > Signed-off-by: Masahiro Yamada 
>>> > > ---
>>> > >
>>> > > Changes in v2:
>>> > >  - Add empty stub to ARC, PowerPC, Microblaze instead of
>>> > >a weak function common/image-fdt.c
>>> >
>>> > [snip]
>>> >
>>> > >
>>> > > diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c
>>> > > index 04d9d9c..5798149 100644
>>> > > --- a/arch/arc/lib/bootm.c
>>> > > +++ b/arch/arc/lib/bootm.c
>>> > > @@ -37,6 +37,11 @@ void arch_lmb_reserve(struct lmb *lmb)
>>> > >   lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
>>> > >  }
>>> > >
>>> > > +int arch_fixup_fdt(void *blob)
>>> > > +{
>>> > > + return 0;
>>> > > +}
>>> > > +
>>> >
>>> > I'm wondering why don't we add weak implementation of arch_fixup_fdt()
>>> > right in say common/image-fdt.c? This will allow us to not add dummy stubs
>>> > for those arches that don't really use it.
>>>
>>>
>>> I fully agree with you.
>>>
>>>
>>> I used a weak function in v1:
>>> http://patchwork.ozlabs.org/patch/678049/
>>>
>>> But, it was change-request'ed by Simon.
>>
>> Ok, thanks for the reference.
>> Indeed Simon's comments make sense.
>>
>> So for ARC changes
>>
>> Acked-by: Alexey Brodkin 
>
> Acked-by: Simon Glass 

Unfortunately this breaks sandbox - can you please take a look?

02: libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORY
   sandbox:  +   sandbox sandbox_spl sandbox_noblk
+common/built-in.o: In function `image_setup_libfdt':
+build/../common/image-fdt.c:477: undefined reference to `arch_fixup_fdt'
+collect2: error: ld returned 1 exit status
+make[1]: *** [u-boot] Error 1
+make: *** [sub-make] Error 2

Regards,
Simon
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[U-Boot] [PATCH] mx6sx: Add initial support for UDOO Neo Board

[Breno Lima]

UDOO Neo Board is a development board from Seco that has three models:
 - UDOO Neo Basic
 - UDOO Neo Basic Kick Starter
 - UDOO Neo Extended
 - UDOO Neo Full

All versions are based on the i.MX6 SoloX processor.

For more details about the UDOO Neo board, please refer to:
http://www.udoo.org/udoo-neo/

This work is based on a previous commit of Francesco Montefoschi
:
https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed574961844

Only tested on the UDOO Neo Full board.

Signed-off-by: Breno Lima 
---
 arch/arm/cpu/armv7/mx6/Kconfig |   5 +
 board/udoo/neo/Kconfig |  12 ++
 board/udoo/neo/MAINTAINERS |   7 +
 board/udoo/neo/Makefile|   6 +
 board/udoo/neo/neo.c   | 441 +
 configs/udoo_neo_defconfig |  30 +++
 include/configs/udoo_neo.h |  94 +
 7 files changed, 595 insertions(+)
 create mode 100644 board/udoo/neo/Kconfig
 create mode 100644 board/udoo/neo/MAINTAINERS
 create mode 100644 board/udoo/neo/Makefile
 create mode 100644 board/udoo/neo/neo.c
 create mode 100644 configs/udoo_neo_defconfig
 create mode 100644 include/configs/udoo_neo.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 762a581..ea8b693 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -192,6 +192,10 @@ config TARGET_UDOO
bool "udoo"
select SUPPORT_SPL
 
+config TARGET_UDOO_NEO
+   bool "UDOO Neo"
+   select SUPPORT_SPL
+
 config TARGET_WANDBOARD
bool "wandboard"
select SUPPORT_SPL
@@ -253,6 +257,7 @@ source "board/technexion/pico-imx6ul/Kconfig"
 source "board/tbs/tbs2910/Kconfig"
 source "board/tqc/tqma6/Kconfig"
 source "board/udoo/Kconfig"
+source "board/udoo/neo/Kconfig"
 source "board/wandboard/Kconfig"
 source "board/warp/Kconfig"
 
diff --git a/board/udoo/neo/Kconfig b/board/udoo/neo/Kconfig
new file mode 100644
index 000..8f474df
--- /dev/null
+++ b/board/udoo/neo/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_UDOO_NEO
+
+config SYS_VENDOR
+   default "udoo"
+
+config SYS_BOARD
+   default "neo"
+
+config SYS_CONFIG_NAME
+   default "udoo_neo"
+
+endif
diff --git a/board/udoo/neo/MAINTAINERS b/board/udoo/neo/MAINTAINERS
new file mode 100644
index 000..743fe33
--- /dev/null
+++ b/board/udoo/neo/MAINTAINERS
@@ -0,0 +1,7 @@
+UDOO NEO BOARD
+M: Breno Lima 
+M: Francesco Montefoschi 
+S: Maintained
+F: board/udoo/neo/
+F: include/configs/udoo_neo.h
+F: configs/udoo_neo_defconfig
diff --git a/board/udoo/neo/Makefile b/board/udoo/neo/Makefile
new file mode 100644
index 000..150cbc1
--- /dev/null
+++ b/board/udoo/neo/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 UDOO Team
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := neo.o
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
new file mode 100644
index 000..7f17469
--- /dev/null
+++ b/board/udoo/neo/neo.c
@@ -0,0 +1,441 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) Jasbir Matharu
+ * Copyright (C) UDOO Team
+ *
+ * Author: Breno Lima 
+ * Author: Francesco Montefoschi 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+   UDOO_NEO_TYPE_BASIC,
+   UDOO_NEO_TYPE_BASIC_KS,
+   UDOO_NEO_TYPE_FULL,
+   UDOO_NEO_TYPE_EXTENDED,
+};
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |\
+   PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |   \
+   PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |\
+   PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |   \
+   PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
+   PAD_CTL_DSE_40ohm)
+
+#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+   PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |   \
+   PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) |\
+   MUX_MODE_SION)
+
+int dram_init(void)
+{
+   gd->ram_size = imx_ddr_size();
+   return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+   MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+   MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+   MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   

[U-Boot] [PATCH v2 3/3] ARM: am57xx_evm: enable DFU support

[Sekhar Nori]

AM57xx GP EVM has USB2 port of the SoC exposed as
USB client port.

It is useful to be able to use this port for USB
DFU downloads.

Enable USB DFU support. Tested on AM57x GP EVM Rev
A3 using DFU to download to connected SD card.

configs for HS version of the AM57x EVM are
included in the patch but not really tested.

Signed-off-by: Sekhar Nori 
---
 configs/am57xx_evm_defconfig| 12 
 configs/am57xx_hs_evm_defconfig | 12 
 include/configs/am57xx_evm.h|  8 
 3 files changed, 32 insertions(+)

diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 06f7f7677222..5b9e2fa7ea54 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -26,6 +26,9 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_MMC=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
@@ -60,5 +63,14 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_USB_STORAGE=y
 CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 6631bb25a8e2..a583b72fccdb 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -27,6 +27,9 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_MMC=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
@@ -55,5 +58,14 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_USB_STORAGE=y
 CONFIG_SPL_OF_LIBFDT=y
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index d865f415bccd..80a3c5d67cf1 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -12,6 +12,8 @@
 #ifndef __CONFIG_AM57XX_EVM_H
 #define __CONFIG_AM57XX_EVM_H
 
+#include 
+
 #define CONFIG_AM57XX
 
 #ifdef CONFIG_SPL_BUILD
@@ -41,6 +43,12 @@
"uuid_disk=${uuid_gpt_disk};" \
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
 
+#define DFUARGS \
+   "dfu_bufsiz=0x1\0" \
+   DFU_ALT_INFO_MMC \
+   DFU_ALT_INFO_EMMC \
+   DFU_ALT_INFO_RAM \
+
 #include 
 
 /* Enhance our eMMC support / experience. */
-- 
2.9.0

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[U-Boot] [PATCH v2 1/3] board: ti: am57xx-evm: fix build warnings

[Sekhar Nori]

USB1 is not used on AM57xx GP EVM in device mode.
Enabling DWC3 USB support for AM57xx EVM gives
the following warnings:

  CC  board/ti/am57xx/board.o
../board/ti/am57xx/board.c:448:27: warning: 'usb_otg_ss1' defined but not used 
[-Wunused-variable]
 static struct dwc3_device usb_otg_ss1 = {
   ^
../board/ti/am57xx/board.c:455:32: warning: 'usb_otg_ss1_glue' defined but not 
used [-Wunused-variable]
 static struct dwc3_omap_device usb_otg_ss1_glue = {
^
../board/ti/am57xx/board.c:461:33: warning: 'usb_phy1_device' defined but not 
used [-Wunused-variable]
 static struct ti_usb_phy_device usb_phy1_device = {

Fix it by getting rid of USB1 related structures from
board.c. They can be added back if there is a need for
them.

Signed-off-by: Sekhar Nori 
Reviewed-by: Lokesh Vutla 
---
 board/ti/am57xx/board.c | 20 
 1 file changed, 20 deletions(-)

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 64de60254136..f3e3f0bd3d60 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -447,26 +447,6 @@ int spl_start_uboot(void)
 #endif
 
 #ifdef CONFIG_USB_DWC3
-static struct dwc3_device usb_otg_ss1 = {
-   .maximum_speed = USB_SPEED_SUPER,
-   .base = DRA7_USB_OTG_SS1_BASE,
-   .tx_fifo_resize = false,
-   .index = 0,
-};
-
-static struct dwc3_omap_device usb_otg_ss1_glue = {
-   .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
-   .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-   .index = 0,
-};
-
-static struct ti_usb_phy_device usb_phy1_device = {
-   .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
-   .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
-   .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
-   .index = 0,
-};
-
 static struct dwc3_device usb_otg_ss2 = {
.maximum_speed = USB_SPEED_HIGH,
.base = DRA7_USB_OTG_SS2_BASE,
-- 
2.9.0

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Re: [U-Boot] [PATCH] usb: xhci: Limit transfer length in a single TD

[Marek Vasut]

On 11/22/2016 03:42 AM, Dongwoo Lee wrote:
> On 2016년 11월 18일 23:01, Marek Vasut wrote:
>> On 11/18/2016 08:24 AM, Jaehoon Chung wrote:
>>> Hi,
>>>
>>> Added Marek as USB maintainer.
>>>
>>> On 11/17/2016 01:21 PM, Dongwoo Lee wrote:
 The transfer request exceeding 4032KB (the maximum number of TRBs per
 TD * the maximum size of transfer buffer on TRB) fails on xhci host
 with timed out error or babble error state. This failure occurs when
 accessing large files on USB mass-storage. Currently with xhci as well
 as ehci host, the driver requests maximum 30MB (65536 blks * 512 byte)
 to storage at once. However, xhci cannot handle this request because
 of the reason mentioned above, even though ehci can handle this. Thus,
 transfer request larger than this size should be splitted in order to
 limit the length of data in a single TD.

 Even though the single request is splitted into multiple requests,
 the transfer speed has affected insignificantly in comparison with
 ehci host: 22.6 MB/s on ehci and 22.3 MB/s on xhci for 100MB tranfer.
>>>
>>> I don't have USB knowledge..So i wonder that this is correct way.
>>> Have other guys ever seen the similar issue?
>>
>> Is this a controller limitation ?
>>
>> btw can you fix your mailer to NOT send HTML email to the list?
>>
> 
> If my understanding for xhci spec.(rev. 1.1) 4.9.2 is right, the controller 
> has no limitation for transfer size because it can support a very large TRB 
> ring with multiple Ring Segments. 
> 
> However, the xhci driver seems not to be implemented for supporting it; 
> the TRB ring is comprised of only a single segment. As a result, it cannot 
> handle the request exceeding 4032KB (TRB_MAX_BUFF_SIZE(64KB) * 
> (TRBS_PER_SEGMENT(64) - link TRB(1)), thus the request should be divided.  

Can we update the driver ?

> This issue can be reproduced by using the following command on Odroid-XU3/XU4
> with USB mass-storage connected to xhci host:
> 
>   >fatload usb 0 4080 {a file exceeding 4032KB}
> 
> About HTML email, I just mailed with git-send-email, but I will double-check 
> the setting.

OK

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

[Jagan Teki]

On Fri, Nov 25, 2016 at 11:16 PM, Marek Vasut  wrote:
> On 11/25/2016 06:42 PM, Jagan Teki wrote:
>> On Thu, Nov 24, 2016 at 11:05 AM, Vignesh R  wrote:
>>> According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
>>> TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
>>> data interface writes until the last word of an indirect transfer
>>> otherwise indirect writes is known to fails sometimes. So, make sure
>>> that QSPI indirect writes are 32 bit sized except for the last write. If
>>> the txbuf is unaligned then use bounce buffer to avoid data aborts.
>>>
>>> So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
>>> for all boards that use Cadence QSPI driver.
>>>
>>> [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
>>>
>>> Signed-off-by: Vignesh R 
>>> ---
>>>
>>> v2:
>>>  - Use bounce buffer
>>>  - Link to v1: https://patchwork.ozlabs.org/patch/693069/
>>>
>>>  drivers/spi/cadence_qspi_apb.c   | 26 --
>>>  include/configs/k2g_evm.h|  1 +
>>>  include/configs/socfpga_common.h |  1 +
>>>  include/configs/stv0991.h|  1 +
>>>  4 files changed, 23 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
>>> index e285d3c1e761..6ce98acf747d 100644
>>> --- a/drivers/spi/cadence_qspi_apb.c
>>> +++ b/drivers/spi/cadence_qspi_apb.c
>>> @@ -30,6 +30,7 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>>  #include "cadence_qspi.h"
>>>
>>>  #define CQSPI_REG_POLL_US  (1) /* 1us */
>>> @@ -741,6 +742,17 @@ int cadence_qspi_apb_indirect_write_execute(struct 
>>> cadence_spi_platdata *plat,
>>> unsigned int remaining = n_tx;
>>> unsigned int write_bytes;
>>> int ret;
>>> +   struct bounce_buffer bb;
>>> +   u8 *bb_txbuf;
>>> +
>>> +   /*
>>> +* Handle non-4-byte aligned accesses via bounce buffer to
>>> +* avoid data abort.
>>> +*/
>>> +   ret = bounce_buffer_start(, (void *)txbuf, n_tx, GEN_BB_READ);
>>> +   if (ret)
>>> +   return ret;
>>> +   bb_txbuf = bb.bounce_buffer;
>>>
>>> /* Configure the indirect read transfer bytes */
>>> writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
>>> @@ -751,11 +763,11 @@ int cadence_qspi_apb_indirect_write_execute(struct 
>>> cadence_spi_platdata *plat,
>>>
>>> while (remaining > 0) {
>>> write_bytes = remaining > page_size ? page_size : remaining;
>>> -   /* Handle non-4-byte aligned access to avoid data abort. */
>>> -   if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
>>> -   writesb(plat->ahbbase, txbuf, write_bytes);
>>> -   else
>>> -   writesl(plat->ahbbase, txbuf, write_bytes >> 2);
>>> +   writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
>>> +   if (write_bytes % 4)
>>> +   writesb(plat->ahbbase,
>>> +   bb_txbuf + rounddown(write_bytes, 4),
>>> +   write_bytes % 4);
>>>
>>> ret = wait_for_bit("QSPI", plat->regbase + 
>>> CQSPI_REG_SDRAMLEVEL,
>>>CQSPI_REG_SDRAMLEVEL_WR_MASK <<
>>> @@ -765,7 +777,7 @@ int cadence_qspi_apb_indirect_write_execute(struct 
>>> cadence_spi_platdata *plat,
>>> goto failwr;
>>> }
>>>
>>> -   txbuf += write_bytes;
>>> +   bb_txbuf += write_bytes;
>>> remaining -= write_bytes;
>>> }
>>>
>>> @@ -776,6 +788,7 @@ int cadence_qspi_apb_indirect_write_execute(struct 
>>> cadence_spi_platdata *plat,
>>> printf("Indirect write completion error (%i)\n", ret);
>>> goto failwr;
>>> }
>>> +   bounce_buffer_stop();
>>>
>>> /* Clear indirect completion status */
>>> writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
>>> @@ -786,6 +799,7 @@ failwr:
>>> /* Cancel the indirect write */
>>> writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
>>>plat->regbase + CQSPI_REG_INDIRECTWR);
>>> +   bounce_buffer_stop();
>>> return ret;
>>>  }
>>>
>>> diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
>>> index a14544526c71..1d603e0c002f 100644
>>> --- a/include/configs/k2g_evm.h
>>> +++ b/include/configs/k2g_evm.h
>>> @@ -79,6 +79,7 @@
>>>  #define CONFIG_CADENCE_QSPI
>>>  #define CONFIG_CQSPI_REF_CLK 38400
>>>  #define CONFIG_CQSPI_DECODER 0x0
>>> +#define CONFIG_BOUNCE_BUFFER
>>
>> Better define this on Kconfig and add it on defconfig.
>
> Such change is unrelated to this patch and should be fixed in a
> separate/subsequent one.

Agreed it should be a separate patch.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH] MAINTAINERS: Fix ALTERA SOCFPGA Files

[Jagan Teki]

Replace arch/arm/cpu/armv7/socfpga/ path with
arch/arm/mach-socfpga/ and removed board file path
since board/altera has different boards with relevant
board maintainers.

Cc: Marek Vasut 
Signed-off-by: Jagan Teki 
---
 MAINTAINERS | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 48d4cec..387b40b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -69,8 +69,7 @@ ARM ALTERA SOCFPGA
 M: Marek Vasut 
 S: Maintainted
 T: git git://git.denx.de/u-boot-socfpga.git
-F: arch/arm/cpu/armv7/socfpga/
-F: board/altera/socfpga/
+F: arch/arm/mach-socfpga/
 
 ARM ATMEL AT91
 M: Andreas Bießmann 
-- 
1.9.1

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Re: [U-Boot] [PATCH v2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

[Marek Vasut]

On 11/25/2016 06:42 PM, Jagan Teki wrote:
> On Thu, Nov 24, 2016 at 11:05 AM, Vignesh R  wrote:
>> According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
>> TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
>> data interface writes until the last word of an indirect transfer
>> otherwise indirect writes is known to fails sometimes. So, make sure
>> that QSPI indirect writes are 32 bit sized except for the last write. If
>> the txbuf is unaligned then use bounce buffer to avoid data aborts.
>>
>> So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
>> for all boards that use Cadence QSPI driver.
>>
>> [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
>>
>> Signed-off-by: Vignesh R 
>> ---
>>
>> v2:
>>  - Use bounce buffer
>>  - Link to v1: https://patchwork.ozlabs.org/patch/693069/
>>
>>  drivers/spi/cadence_qspi_apb.c   | 26 --
>>  include/configs/k2g_evm.h|  1 +
>>  include/configs/socfpga_common.h |  1 +
>>  include/configs/stv0991.h|  1 +
>>  4 files changed, 23 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
>> index e285d3c1e761..6ce98acf747d 100644
>> --- a/drivers/spi/cadence_qspi_apb.c
>> +++ b/drivers/spi/cadence_qspi_apb.c
>> @@ -30,6 +30,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include "cadence_qspi.h"
>>
>>  #define CQSPI_REG_POLL_US  (1) /* 1us */
>> @@ -741,6 +742,17 @@ int cadence_qspi_apb_indirect_write_execute(struct 
>> cadence_spi_platdata *plat,
>> unsigned int remaining = n_tx;
>> unsigned int write_bytes;
>> int ret;
>> +   struct bounce_buffer bb;
>> +   u8 *bb_txbuf;
>> +
>> +   /*
>> +* Handle non-4-byte aligned accesses via bounce buffer to
>> +* avoid data abort.
>> +*/
>> +   ret = bounce_buffer_start(, (void *)txbuf, n_tx, GEN_BB_READ);
>> +   if (ret)
>> +   return ret;
>> +   bb_txbuf = bb.bounce_buffer;
>>
>> /* Configure the indirect read transfer bytes */
>> writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
>> @@ -751,11 +763,11 @@ int cadence_qspi_apb_indirect_write_execute(struct 
>> cadence_spi_platdata *plat,
>>
>> while (remaining > 0) {
>> write_bytes = remaining > page_size ? page_size : remaining;
>> -   /* Handle non-4-byte aligned access to avoid data abort. */
>> -   if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
>> -   writesb(plat->ahbbase, txbuf, write_bytes);
>> -   else
>> -   writesl(plat->ahbbase, txbuf, write_bytes >> 2);
>> +   writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
>> +   if (write_bytes % 4)
>> +   writesb(plat->ahbbase,
>> +   bb_txbuf + rounddown(write_bytes, 4),
>> +   write_bytes % 4);
>>
>> ret = wait_for_bit("QSPI", plat->regbase + 
>> CQSPI_REG_SDRAMLEVEL,
>>CQSPI_REG_SDRAMLEVEL_WR_MASK <<
>> @@ -765,7 +777,7 @@ int cadence_qspi_apb_indirect_write_execute(struct 
>> cadence_spi_platdata *plat,
>> goto failwr;
>> }
>>
>> -   txbuf += write_bytes;
>> +   bb_txbuf += write_bytes;
>> remaining -= write_bytes;
>> }
>>
>> @@ -776,6 +788,7 @@ int cadence_qspi_apb_indirect_write_execute(struct 
>> cadence_spi_platdata *plat,
>> printf("Indirect write completion error (%i)\n", ret);
>> goto failwr;
>> }
>> +   bounce_buffer_stop();
>>
>> /* Clear indirect completion status */
>> writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
>> @@ -786,6 +799,7 @@ failwr:
>> /* Cancel the indirect write */
>> writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
>>plat->regbase + CQSPI_REG_INDIRECTWR);
>> +   bounce_buffer_stop();
>> return ret;
>>  }
>>
>> diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
>> index a14544526c71..1d603e0c002f 100644
>> --- a/include/configs/k2g_evm.h
>> +++ b/include/configs/k2g_evm.h
>> @@ -79,6 +79,7 @@
>>  #define CONFIG_CADENCE_QSPI
>>  #define CONFIG_CQSPI_REF_CLK 38400
>>  #define CONFIG_CQSPI_DECODER 0x0
>> +#define CONFIG_BOUNCE_BUFFER
> 
> Better define this on Kconfig and add it on defconfig.

Such change is unrelated to this patch and should be fixed in a
separate/subsequent one.


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

[Jagan Teki]

On Thu, Nov 24, 2016 at 11:05 AM, Vignesh R  wrote:
> According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
> TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
> data interface writes until the last word of an indirect transfer
> otherwise indirect writes is known to fails sometimes. So, make sure
> that QSPI indirect writes are 32 bit sized except for the last write. If
> the txbuf is unaligned then use bounce buffer to avoid data aborts.
>
> So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
> for all boards that use Cadence QSPI driver.
>
> [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
>
> Signed-off-by: Vignesh R 
> ---
>
> v2:
>  - Use bounce buffer
>  - Link to v1: https://patchwork.ozlabs.org/patch/693069/
>
>  drivers/spi/cadence_qspi_apb.c   | 26 --
>  include/configs/k2g_evm.h|  1 +
>  include/configs/socfpga_common.h |  1 +
>  include/configs/stv0991.h|  1 +
>  4 files changed, 23 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index e285d3c1e761..6ce98acf747d 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -30,6 +30,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include "cadence_qspi.h"
>
>  #define CQSPI_REG_POLL_US  (1) /* 1us */
> @@ -741,6 +742,17 @@ int cadence_qspi_apb_indirect_write_execute(struct 
> cadence_spi_platdata *plat,
> unsigned int remaining = n_tx;
> unsigned int write_bytes;
> int ret;
> +   struct bounce_buffer bb;
> +   u8 *bb_txbuf;
> +
> +   /*
> +* Handle non-4-byte aligned accesses via bounce buffer to
> +* avoid data abort.
> +*/
> +   ret = bounce_buffer_start(, (void *)txbuf, n_tx, GEN_BB_READ);
> +   if (ret)
> +   return ret;
> +   bb_txbuf = bb.bounce_buffer;
>
> /* Configure the indirect read transfer bytes */
> writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
> @@ -751,11 +763,11 @@ int cadence_qspi_apb_indirect_write_execute(struct 
> cadence_spi_platdata *plat,
>
> while (remaining > 0) {
> write_bytes = remaining > page_size ? page_size : remaining;
> -   /* Handle non-4-byte aligned access to avoid data abort. */
> -   if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
> -   writesb(plat->ahbbase, txbuf, write_bytes);
> -   else
> -   writesl(plat->ahbbase, txbuf, write_bytes >> 2);
> +   writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
> +   if (write_bytes % 4)
> +   writesb(plat->ahbbase,
> +   bb_txbuf + rounddown(write_bytes, 4),
> +   write_bytes % 4);
>
> ret = wait_for_bit("QSPI", plat->regbase + 
> CQSPI_REG_SDRAMLEVEL,
>CQSPI_REG_SDRAMLEVEL_WR_MASK <<
> @@ -765,7 +777,7 @@ int cadence_qspi_apb_indirect_write_execute(struct 
> cadence_spi_platdata *plat,
> goto failwr;
> }
>
> -   txbuf += write_bytes;
> +   bb_txbuf += write_bytes;
> remaining -= write_bytes;
> }
>
> @@ -776,6 +788,7 @@ int cadence_qspi_apb_indirect_write_execute(struct 
> cadence_spi_platdata *plat,
> printf("Indirect write completion error (%i)\n", ret);
> goto failwr;
> }
> +   bounce_buffer_stop();
>
> /* Clear indirect completion status */
> writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
> @@ -786,6 +799,7 @@ failwr:
> /* Cancel the indirect write */
> writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
>plat->regbase + CQSPI_REG_INDIRECTWR);
> +   bounce_buffer_stop();
> return ret;
>  }
>
> diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
> index a14544526c71..1d603e0c002f 100644
> --- a/include/configs/k2g_evm.h
> +++ b/include/configs/k2g_evm.h
> @@ -79,6 +79,7 @@
>  #define CONFIG_CADENCE_QSPI
>  #define CONFIG_CQSPI_REF_CLK 38400
>  #define CONFIG_CQSPI_DECODER 0x0
> +#define CONFIG_BOUNCE_BUFFER

Better define this on Kconfig and add it on defconfig.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH v2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

[Marek Vasut]

On 11/24/2016 06:35 AM, Vignesh R wrote:
> According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
> TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
> data interface writes until the last word of an indirect transfer
> otherwise indirect writes is known to fails sometimes. So, make sure
> that QSPI indirect writes are 32 bit sized except for the last write. If
> the txbuf is unaligned then use bounce buffer to avoid data aborts.
> 
> So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
> for all boards that use Cadence QSPI driver.
> 
> [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
> 
> Signed-off-by: Vignesh R 
> ---

Reviewed-by: Marek Vasut 

I'd like to have at least Dinh's/Chin's ack on this.

btw don't you need BB for READ as well ?

> v2:
>  - Use bounce buffer
>  - Link to v1: https://patchwork.ozlabs.org/patch/693069/
> 
>  drivers/spi/cadence_qspi_apb.c   | 26 --
>  include/configs/k2g_evm.h|  1 +
>  include/configs/socfpga_common.h |  1 +
>  include/configs/stv0991.h|  1 +
>  4 files changed, 23 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index e285d3c1e761..6ce98acf747d 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -30,6 +30,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include "cadence_qspi.h"
>  
>  #define CQSPI_REG_POLL_US(1) /* 1us */
> @@ -741,6 +742,17 @@ int cadence_qspi_apb_indirect_write_execute(struct 
> cadence_spi_platdata *plat,
>   unsigned int remaining = n_tx;
>   unsigned int write_bytes;
>   int ret;
> + struct bounce_buffer bb;
> + u8 *bb_txbuf;
> +
> + /*
> +  * Handle non-4-byte aligned accesses via bounce buffer to
> +  * avoid data abort.
> +  */
> + ret = bounce_buffer_start(, (void *)txbuf, n_tx, GEN_BB_READ);
> + if (ret)
> + return ret;
> + bb_txbuf = bb.bounce_buffer;
>  
>   /* Configure the indirect read transfer bytes */
>   writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
> @@ -751,11 +763,11 @@ int cadence_qspi_apb_indirect_write_execute(struct 
> cadence_spi_platdata *plat,
>  
>   while (remaining > 0) {
>   write_bytes = remaining > page_size ? page_size : remaining;
> - /* Handle non-4-byte aligned access to avoid data abort. */
> - if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
> - writesb(plat->ahbbase, txbuf, write_bytes);
> - else
> - writesl(plat->ahbbase, txbuf, write_bytes >> 2);
> + writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
> + if (write_bytes % 4)
> + writesb(plat->ahbbase,
> + bb_txbuf + rounddown(write_bytes, 4),
> + write_bytes % 4);
>  
>   ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
>  CQSPI_REG_SDRAMLEVEL_WR_MASK <<
> @@ -765,7 +777,7 @@ int cadence_qspi_apb_indirect_write_execute(struct 
> cadence_spi_platdata *plat,
>   goto failwr;
>   }
>  
> - txbuf += write_bytes;
> + bb_txbuf += write_bytes;
>   remaining -= write_bytes;
>   }
>  
> @@ -776,6 +788,7 @@ int cadence_qspi_apb_indirect_write_execute(struct 
> cadence_spi_platdata *plat,
>   printf("Indirect write completion error (%i)\n", ret);
>   goto failwr;
>   }
> + bounce_buffer_stop();
>  
>   /* Clear indirect completion status */
>   writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
> @@ -786,6 +799,7 @@ failwr:
>   /* Cancel the indirect write */
>   writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
>  plat->regbase + CQSPI_REG_INDIRECTWR);
> + bounce_buffer_stop();
>   return ret;
>  }
>  
> diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
> index a14544526c71..1d603e0c002f 100644
> --- a/include/configs/k2g_evm.h
> +++ b/include/configs/k2g_evm.h
> @@ -79,6 +79,7 @@
>  #define CONFIG_CADENCE_QSPI
>  #define CONFIG_CQSPI_REF_CLK 38400
>  #define CONFIG_CQSPI_DECODER 0x0
> +#define CONFIG_BOUNCE_BUFFER
>  #endif
>  
>  #endif /* __CONFIG_K2G_EVM_H */
> diff --git a/include/configs/socfpga_common.h 
> b/include/configs/socfpga_common.h
> index d37e5958b586..2de57b063334 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -208,6 +208,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>  #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
>  #endif
>  #define CONFIG_CQSPI_DECODER 0
> +#define CONFIG_BOUNCE_BUFFER
>  
>  /*
>   * Designware SPI support
> diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
> index bfd1bd719285..09a3064bd6d6 100644
> --- 

Re: [U-Boot] [PATCH v2 3/14] bch: Allow to build for the host

[Jagan Teki]

On Tue, Nov 22, 2016 at 6:08 PM, Maxime Ripard
 wrote:
> We will need the bch functions in the tool to generate the SPL images for
> the Allwinner SoCs.
>
> Do the needed adjustments so that we can use it on the host.
>
> Signed-off-by: Maxime Ripard 
> ---
>  lib/bch.c | 48 
>  1 file changed, 48 insertions(+), 0 deletions(-)
>
> diff --git a/lib/bch.c b/lib/bch.c
> index 147715afd06a..ec53483774b5 100644
> --- a/lib/bch.c
> +++ b/lib/bch.c
> @@ -54,10 +54,27 @@
>   * finite fields GF(2^q). In Rapport de recherche INRIA no 2829, 1996.
>   */
>
> +#ifndef USE_HOSTCC
>  #include 
>  #include 
>
>  #include 
> +#else
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#undef cpu_to_be32
> +#define cpu_to_be32 htobe32
> +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
> +#define kmalloc(size, flags)   malloc(size)
> +#define kzalloc(size, flags)   calloc(1, size)
> +#define kfree free
> +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
> +#endif
> +
>  #include 
>  #include 
>
> @@ -95,6 +112,37 @@ struct gf_poly_deg1 {
> unsigned int   c[2];
>  };
>
> +#ifdef USE_HOSTCC
> +static int fls(int x)
> +{

This look redundant definition to me,  can't we use this from
include/linux/bitops.h ?

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH v2 10/22] spi: Add error checking for invalid bus widths

[Fabio Estevam]

On Fri, Nov 25, 2016 at 2:57 PM, Jagan Teki  wrote:

> Yeah, ie what if dts has a wrong value and do print that and continue
> with default width, so-that the user will update this for next run.
> Since it's not key a attribute to break or decide functionality better
> to go with it.

Agreed. This also matches with the kernel behaviour.
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Re: [U-Boot] [PATCH v2 10/22] spi: Add error checking for invalid bus widths

[Jagan Teki]

Hi Simon,

On Thu, Nov 24, 2016 at 7:51 AM, Simon Glass  wrote:
> Hi Jagan,
>
> On 21 November 2016 at 10:57, Jagan Teki  wrote:
>> On Sun, Nov 20, 2016 at 2:19 AM, Fabio Estevam  wrote:
>>> On Sat, Nov 19, 2016 at 6:04 PM, Simon Glass  wrote:
>>>
> EPROTONOSUPPORT means: /* Protocol not supported */, which does not
> seem to be very appropriate here.

 This is a protocol as far as I can see - you can either use one pin or
 four pins.
>>>
>>> Actually they are SPI modes: one, two or four pins.
>>>
> Why not return -EINVAL instead?

 The value is valid but is not supported. If we just return -EINVAL for
 anything we don't like, it makes it harder to root-cause the error. In
 particular we use -EINVAL when decoding the device tree. But
 EPROTONOSUPPORT is not widely used.
>>>
>>> I think the current behaviour of not returning an error code on an
>>> invalid mode is correct and it matches what the kernel does in
>>> drivers/spi/spi.c.
>>>
>>> If an invalid mode is passed we just ignore it and operate in single
>>> mode instead.
>>>
>>> Maybe we can make this clearer by printing a message like this:
>>>
>>> --- a/drivers/spi/spi-uclass.c
>>> +++ b/drivers/spi/spi-uclass.c
>>> @@ -408,7 +408,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int 
>>> node,
>>> mode |= SPI_TX_QUAD;
>>> break;
>>> default:
>>> -   error("spi-tx-bus-width %d not supported\n", value);
>>> +   printf("spi-tx-bus-width %d not supported, operating
>>> in single mode\n", value);
>>> break;
>>> }
>>>
>>> @@ -423,7 +423,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int 
>>> node,
>>> mode |= SPI_RX_QUAD;
>>> break;
>>> default:
>>> -   error("spi-rx-bus-width %d not supported\n", value);
>>> +   printf("spi-rx-bus-width %d not supported, operating
>>> in single mode\n", value);
>>> break;
>>
>> Yes, this is what I am commenting about.
>>
>> -EINVAL not needed, we can print "%d is not supporting and operating
>> in normal/single mode and move on", So-that the dts will fix if
>> something went wrong.
>
> Well if you add printf() values you will bloat the code for little
> benefit. If the device tree is invalid it really should be fixed.

Yeah, ie what if dts has a wrong value and do print that and continue
with default width, so-that the user will update this for next run.
Since it's not key a attribute to break or decide functionality better
to go with it.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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[U-Boot] Please pull u-boot-fdt

[Simon Glass]

Hi Tom.

The following changes since commit 543bd27353d2c5679057fe09aa2d02259687ff32:

  MAINTAINERS: SUNXI: Update maintainership (2016-11-22 09:07:26 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-fdt.git

for you to fetch changes up to 643f8d4c07788f28ad283e3fcb29d88a4b16a4be:

  MAINTAINERS: Fix syntax and update filename for FDT (2016-11-25
09:48:09 -0700)


Andreas Färber (1):
  MAINTAINERS: Fix syntax and update filename for FDT

 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Regards,
Simon
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Re: [U-Boot] [PATCH v2 1/4] usb: dwc2: add support for external vbus supply

[Marek Vasut]

On 11/24/2016 08:29 AM, Kever Yang wrote:
> Some board do not use the dwc2 internal VBUS_DRV signal, but
> use a gpio pin to enable the 5.0V VBUS power, add interface to
> enable the power in dwc2 driver.
> 
> Signed-off-by: Kever Yang 
> ---
> 
> Changes in v2: None
> 
>  drivers/usb/host/dwc2.c | 29 +
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
> index d08879d..8292aa8 100644
> --- a/drivers/usb/host/dwc2.c
> +++ b/drivers/usb/host/dwc2.c
> @@ -15,6 +15,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  #include "dwc2.h"
>  
> @@ -55,6 +56,8 @@ DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, 
> DWC2_STATUS_BUF_SIZE,
>  static struct dwc2_priv local;
>  #endif
>  
> +static struct udevice *g_dwc2_udev;

Can we avoid the static global var ?

> +
>  /*
>   * DWC2 IP interface
>   */
> @@ -159,6 +162,29 @@ static void dwc_otg_core_reset(struct dwc2_core_regs 
> *regs)
>   mdelay(100);
>  }
>  
> +static int dwc_vbus_supply_init(void)
> +{
> +#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) && \
> + !defined(CONFIG_SPL_BUILD)

Why does this not work for SPL ?

btw, I'd rather see this as:

#if FOO
function bar()
{
 ...
}
#else
static inline function bar()
{
 return 0;
}
#endif

> + struct udevice *vbus_supply;
> + int ret;
> +
> + ret = device_get_supply_regulator(g_dwc2_udev, "vbus-supply",
> +   _supply);

Is this compatible with the Linux DWC2 DT bindings ?

> + if (ret) {
> + debug("%s: No vbus supply\n", g_dwc2_udev->name);
> + return 0;
> + }
> +
> + ret = regulator_set_enable(vbus_supply, true);

Shouldn't the regulator be enabled when we enable VBUS for a port
instead of here ? And where is it disabled ?

> + if (ret) {
> + error("Error enabling vbus supply\n");
> + return ret;
> + }
> +#endif
> + return 0;
> +}
> +
>  /*
>   * This function initializes the DWC_otg controller registers for
>   * host mode.
> @@ -248,6 +274,8 @@ static void dwc_otg_core_host_init(struct dwc2_core_regs 
> *regs)
>   writel(hprt0, >hprt0);
>   }
>   }
> +
> + dwc_vbus_supply_init();
>  }
>  
>  /*
> @@ -1194,6 +1222,7 @@ static int dwc2_usb_ofdata_to_platdata(struct udevice 
> *dev)
>   const void *prop;
>   fdt_addr_t addr;
>  
> + g_dwc2_udev = dev;
>   addr = dev_get_addr(dev);
>   if (addr == FDT_ADDR_T_NONE)
>   return -EINVAL;
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] sun8i_emac: Fix mdio read sequence

[Jagan Teki]

On Wed, Nov 16, 2016 at 7:10 AM, Andre Przywara  wrote:
> From: Philipp Tomsich 
>
> To send a parametrized command to the PHY over MDIO, we should write
> the data first, the trigger the execution by the command register
> write. Fix the access pattern in our MDIO write routine.
> Apparently this doesn't really matter with the Realtek PHY on the
> Pine64, but other PHYs (which require more setup) will choke on
> the wrong order.

Any tested-by this on non-realtek, because I always remember to have
CMD with DATA sequence for mdio write for most of the PHY's and ie
default sequence though.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH v2 2/8] spi: cadence_qspi: Fix baud rate calculation

[Jagan Teki]

On Fri, Nov 25, 2016 at 9:23 PM, Marek Vasut  wrote:
> On 11/25/2016 04:19 PM, Phil Edworthy wrote:
>> Hi Marek,
>>
>> On 25 November 2016 14:58 Marek Vasut wrote:
>>> On 11/25/2016 03:38 PM, Phil Edworthy wrote:
 With the existing code, when the requested SPI clock rate is near
 to the lowest that can be achieved by the hardware (max divider
 of the ref clock is 32), the generated clock rate is wrong.
 For example, with a 50MHz ref clock, when asked for anything less
 than a 1.5MHz SPI clock, the code sets up the divider to generate
 25MHz.

 This change fixes the calculation.

 Signed-off-by: Phil Edworthy 
 ---
 v2:
  - Use the DIV_ROUND_UP macro
 ---
  drivers/spi/cadence_qspi_apb.c | 23 +++
  1 file changed, 7 insertions(+), 16 deletions(-)

 diff --git a/drivers/spi/cadence_qspi_apb.c 
 b/drivers/spi/cadence_qspi_apb.c
 index 2403e71..b9e0df7 100644
 --- a/drivers/spi/cadence_qspi_apb.c
 +++ b/drivers/spi/cadence_qspi_apb.c
 @@ -273,22 +273,13 @@ void cadence_qspi_apb_config_baudrate_div(void
>>> *reg_base,
 reg = readl(reg_base + CQSPI_REG_CONFIG);
 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK <<
>>> CQSPI_REG_CONFIG_BAUD_LSB);

 -   div = ref_clk_hz / sclk_hz;
 -
 -   if (div > 32)
 -   div = 32;
 -
 -   /* Check if even number. */
 -   if ((div & 1)) {
 -   div = (div / 2);
 -   } else {
 -   if (ref_clk_hz % sclk_hz)
 -   /* ensure generated SCLK doesn't exceed user
 -   specified sclk_hz */
 -   div = (div / 2);
 -   else
 -   div = (div / 2) - 1;
 -   }
 +   /*
 +* The baud_div field in the config reg is 4 bits, and the ref clock is
 +* divided by 2 * (baud_div + 1). Round up the divider to ensure the
 +* SPI clock rate is less than or equal to the requested clock rate.
 +*/
 +   div = DIV_ROUND_UP(ref_clk_hz, sclk_hz);
 +   div = DIV_ROUND_UP(div, 2) - 1;
>>>
>>> Same as you did for u-boot, right ?
>> Eh? This is u-boot :)
>
> Yeah, I realized that too when I saw the later patches. I thought this
> was for the CQSPI in Linux at right.

Yes, and look good as well.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH v2 4/8] spi: cadence_qspi: Use #define for bits instead of bit shifts

[Jagan Teki]

On Fri, Nov 25, 2016 at 8:08 PM, Phil Edworthy
 wrote:
> Most of the code already uses #defines for the bit value, rather
> than the shift required to get the value. This changes the remaining
> code over.
>
> Whislt at it, fix the names of the "Rd Data Capture" register defs.
>
> Signed-off-by: Phil Edworthy 
> ---
>  drivers/spi/cadence_qspi_apb.c | 37 +++--
>  1 file changed, 19 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index 3ae4b5a..cd46a15 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -57,9 +57,9 @@
>   * Controller's configuration and status register (offset from QSPI_BASE)
>   
> /
>  #defineCQSPI_REG_CONFIG0x00
> -#defineCQSPI_REG_CONFIG_CLK_POL_LSB1
> -#defineCQSPI_REG_CONFIG_CLK_PHA_LSB2
>  #defineCQSPI_REG_CONFIG_ENABLE_MASKBIT(0)
> +#defineCQSPI_REG_CONFIG_CLK_POLBIT(1)
> +#defineCQSPI_REG_CONFIG_CLK_PHABIT(2)
>  #defineCQSPI_REG_CONFIG_DIRECT_MASKBIT(7)
>  #defineCQSPI_REG_CONFIG_DECODE_MASKBIT(9)
>  #defineCQSPI_REG_CONFIG_XIP_IMM_MASK   BIT(18)
> @@ -94,10 +94,10 @@
>  #defineCQSPI_REG_DELAY_TSD2D_MASK  0xFF
>  #defineCQSPI_REG_DELAY_TSHSL_MASK  0xFF
>
> -#defineCQSPI_READLCAPTURE  0x10
> -#defineCQSPI_READLCAPTURE_BYPASS_LSB   0
> -#defineCQSPI_READLCAPTURE_DELAY_LSB1
> -#defineCQSPI_READLCAPTURE_DELAY_MASK   0xF
> +#defineCQSPI_REG_RD_DATA_CAPTURE   0x10
> +#defineCQSPI_REG_RD_DATA_CAPTURE_BYPASSBIT(0)
> +#defineCQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
> +#defineCQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK0xF
>
>  #defineCQSPI_REG_SIZE  0x14
>  #defineCQSPI_REG_SIZE_ADDRESS_LSB  0
> @@ -244,20 +244,20 @@ void cadence_qspi_apb_readdata_capture(void *reg_base,
> unsigned int reg;
> cadence_qspi_apb_controller_disable(reg_base);
>
> -   reg = readl(reg_base + CQSPI_READLCAPTURE);
> +   reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
>
> if (bypass)
> -   reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
> +   reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
> else
> -   reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
> +   reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
>
> -   reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
> -   << CQSPI_READLCAPTURE_DELAY_LSB);
> +   reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
> +   << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
>
> -   reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
> -   << CQSPI_READLCAPTURE_DELAY_LSB);
> +   reg |= ((delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
> +   << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
>
> -   writel(reg, reg_base + CQSPI_READLCAPTURE);
> +   writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
>
> cadence_qspi_apb_controller_enable(reg_base);
> return;
> @@ -302,11 +302,12 @@ void cadence_qspi_apb_set_clk_mode(void *reg_base,
>
> cadence_qspi_apb_controller_disable(reg_base);
> reg = readl(reg_base + CQSPI_REG_CONFIG);
> -   reg &= ~(1 << CQSPI_REG_CONFIG_CLK_POL_LSB);
> -   reg &= ~(1 << CQSPI_REG_CONFIG_CLK_PHA_LSB);
> +   reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
>
> -   reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
> -   reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
> +   if (clk_pol)
> +   reg |= CQSPI_REG_CONFIG_CLK_POL;
> +   if (clk_pha)
> +   reg |= CQSPI_REG_CONFIG_CLK_PHA;

Take the mode directly from cadence_spi_set_mode and do mode checking
here, this defiantly reduce one func arg and local variables from
cadence_spi_set_mode

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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