Re: [U-Boot] [v3 25/30] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Dinh Nguyen]

On 01/06/2017 05:19 AM, Chee Tien Fong wrote:

From: Tien Fong Chee 

Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.



In Linux, I was able to use the same reset manager driver to support 
both gen5 and Arria10 devices, are you sure you can't do the same here?


Take a look at this commit:

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commi/drivers/rese/resetsocfpga.c?id=27e44646dc0083c931b71bbb8e179aeb38010d31

My guess is that you can probably use the same driver but with different 
macro defines.



Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Reverted license changes, removing extern and volatile declaration
---
 arch/arm/mach-socfpga/Makefile |   16 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  155 ++--
 arch/arm/mach-socfpga/reset_manager.c  |  112 +--
 arch/arm/mach-socfpga/reset_manager_arria10.c  |  407 
 .../{reset_manager.c => reset_manager_gen5.c}  |   94 ++---
 5 files changed, 570 insertions(+), 214 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
 copy arch/arm/mach-socfpga/{reset_manager.c => reset_manager_gen5.c} (58%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..b8fcf6e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,21 +2,27 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
-# Copyright (C) 2012 Altera Corporation 
+# Copyright (C) 2012-2016 Altera Corporation 
 #
 # SPDX-License-Identifier: GPL-2.0+
 #

 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
+   reset_manager_gen5.o

-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o wrap_iocsr_config.o \
+   wrap_pinmux_config.o wrap_sdram_config.o
+endif

+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
-  wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6225118..13f9731 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,15 +7,27 @@
 #ifndef_RESET_MANAGER_H_
 #define_RESET_MANAGER_H_

+/* Common function prototypes */
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
-
 void socfpga_bridges_reset(int enable);
-
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);

 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+void reset_deassert_peripherals_handoff(void);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void watchdog_disable(void);
+void reset_deassert_noc_ddr_scheduler(void);
+int is_wdt_in_reset(void);
+void emac_manage_reset(ulong emacbase, uint state);
+int reset_deassert_bridges_handoff(void);
+void reset_assert_fpga_connected_peripherals(void);
+void reset_deassert_osc1wd0(void);
+void reset_assert_uart(void);
+void reset_deassert_uart(void);


Not sure why you need these new functions instead of re-using 
socfpga_per_reset()?



+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -29,40 +41,40 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 struct socfpga_reset_manager {
-   u32 stat;
-   u32 ramstat;
-   u32 miscstat;
-   u32 ctrl;
-   u32 hdsken;
-   u32 hdskreq;
-   u32 hdskack;
-   u32 counts;
-   u32 mpu_mod_reset;
-   u32 

[U-Boot] [PATCH] am335x: configs: Use ISW_ENTRY_ADDR to set SPL_TEXT_BASE

[Andrew F. Davis]

The SPL load address changes based on boot type in HS devices,
ISW_ENTRY_ADDR is used to set this address for AM43xx based SoCs
for similar reasons. Add this same logic for AM33xx devices.

Also make the default value for ISW_ENTRY_ADDR correct for GP
devices based on SoC, HS devices already pick the correct
value in their defconfig.

Signed-off-by: Andrew F. Davis 
---
 arch/arm/mach-omap2/am33xx/Kconfig | 3 ++-
 include/configs/ti_am335x_common.h | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/am33xx/Kconfig 
b/arch/arm/mach-omap2/am33xx/Kconfig
index 8fd32c2a46..56c44062c4 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -119,7 +119,8 @@ config ISW_ENTRY_ADDR
  point address depending on the device type
  (secure/non-secure), boot media (xip/non-xip) and
  image headers.
-   default 0x402F4000
+   default 0x402F4000 if AM43XX
+   default 0x402F0400 if AM33XX
 
 config PUB_ROM_DATA_SIZE
hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
diff --git a/include/configs/ti_am335x_common.h 
b/include/configs/ti_am335x_common.h
index d841b3f7b6..809d015cf9 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -56,7 +56,7 @@
  * supports X-MODEM loading via UART, and we leverage this and then use
  * Y-MODEM to load u-boot.img, when booted over UART.
  */
-#define CONFIG_SPL_TEXT_BASE   0x402F0400
+#define CONFIG_SPL_TEXT_BASE   CONFIG_ISW_ENTRY_ADDR
 #define CONFIG_SYS_SPL_ARGS_ADDR   (CONFIG_SYS_SDRAM_BASE + \
 (128 << 20))
 
-- 
2.11.0

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[U-Boot] [PATCH] Makefile: Make EFI build quiet

[Andrew F. Davis]

Make building EFI example less noisy.

Signed-off-by: Andrew F. Davis 
---
 scripts/Makefile.lib | 16 +++-
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 13c975b8a4..81ac7eb12c 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -363,19 +363,25 @@ cmd_S_efi=
\
 $(obj)/%_efi.S: $(obj)/%.efi
$(call cmd,S_efi)
 
-$(obj)/%.efi: $(obj)/%.so
-   $(OBJCOPY) -j .header -j .text -j .sdata -j .data -j .dynamic \
-   -j .dynsym  -j .rel* -j .rela* -j .reloc \
+quiet_cmd_efi_objcopy = OBJCOPY $@
+cmd_efi_objcopy = $(OBJCOPY) -j .header -j .text -j .sdata -j .data -j \
+   .dynamic -j .dynsym  -j .rel* -j .rela* -j .reloc \
$(if $(EFI_TARGET),$(EFI_TARGET),-O binary) $^ $@
 
+$(obj)/%.efi: $(obj)/%.so
+   $(call cmd,efi_objcopy)
+
+quiet_cmd_efi_ld = LD  $@
+cmd_efi_ld = $(LD) -nostdlib -znocombreloc -T $(EFI_LDS_PATH) -shared \
+   -Bsymbolic $^ -o $@
+
 EFI_LDS_PATH = $(srctree)/arch/$(ARCH)/lib/$(EFI_LDS)
 
 $(obj)/helloworld.so: $(EFI_LDS_PATH)
 
 $(obj)/helloworld.so: $(obj)/helloworld.o arch/$(ARCH)/lib/$(EFI_CRT0) \
arch/$(ARCH)/lib/$(EFI_RELOC)
-   $(LD) -nostdlib -znocombreloc -T $(EFI_LDS_PATH) -shared -Bsymbolic \
-   $^ -o $@
+   $(call cmd,efi_ld)
 
 # ACPI
 # ---
-- 
2.11.0

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[U-Boot] [PATCH 1/1] arm: mach-omap2: Fix secure file generation

[Andrew F. Davis]

When TI_SECURE_DEV_PKG is not defined we warn that the file '*_HS' was
not generated but generate an unsigned one anyway, first fix this
warning to say that it was generated but not secured.

When the user then exports TI_SECURE_DEV_PKG after getting this warning,
and tries to re-build, 'make' will detect the build artifacts as
unchanged and so assume they do not need to be re-generated. This causes
it to fail to sign the files and it will pack unsigned files into the
final image, even though TI_SECURE_DEV_PKG is now correctly defined and
working.

Fix this by using FORCE on the targets causes them to be re-run even if
the dependent files have not changed.

This then causes another issue. We currently rename the signed dtb files
to overwrite the non-signed ones. We do this so the 'mkimage' tool gives
the packaged dtb sections the correct name. If we do not rename the files
then SPL will not find them during boot.

Fix this by renaming the dtb files by appending _HS to the end of the
filename, after the ".dtb", this causes them to still be named correctly
in the FIT blob.

Signed-off-by: Andrew F. Davis 
---
 arch/arm/mach-omap2/config_secure.mk | 36 +---
 1 file changed, 17 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-omap2/config_secure.mk 
b/arch/arm/mach-omap2/config_secure.mk
index 1122439e38..0c843338d7 100644
--- a/arch/arm/mach-omap2/config_secure.mk
+++ b/arch/arm/mach-omap2/config_secure.mk
@@ -3,7 +3,7 @@
 #
 # SPDX-License-Identifier: GPL-2.0+
 #
-quiet_cmd_mkomapsecimg = MKIMAGE $@
+quiet_cmd_mkomapsecimg = SECURE  $@
 ifneq ($(TI_SECURE_DEV_PKG),)
 ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
 ifneq ($(CONFIG_SPL_BUILD),)
@@ -18,11 +18,12 @@ endif
 else
 cmd_mkomapsecimg = echo "WARNING:" \
"$(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh not found." \
-   "$@ was NOT created!"
+   "$@ was NOT secured!"; cp $< $@
 endif
 else
 cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
-   "variable must be defined for TI secure devices. $@ was NOT created!"
+   "variable must be defined for TI secure devices. \
+   $@ was NOT secured!"; cp $< $@
 endif
 
 ifdef CONFIG_SPL_LOAD_FIT
@@ -35,51 +36,51 @@ cmd_omapsecureimg = 
$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh \
 else
 cmd_omapsecureimg = echo "WARNING:" \
"$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \
-   "$@ was NOT created!"; cp $< $@
+   "$@ was NOT secured!"; cp $< $@
 endif
 else
 cmd_omapsecureimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
"variable must be defined for TI secure devices." \
-   "$@ was NOT created!"; cp $< $@
+   "$@ was NOT secured!"; cp $< $@
 endif
 endif
 
 
 # Standard X-LOADER target (QPSI, NOR flash)
-u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin
+u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkomapsecimg)
 
 # For MLO targets (SD card boot) the final file name that is copied to the SD
 # card FAT partition must be MLO, so we make a copy of the output file to a new
 # file with that name
-u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin
+u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkomapsecimg)
@if [ -f $@ ]; then \
cp -f $@ MLO; \
fi
 
 # Standard 2ND target (certain peripheral boot modes)
-u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin
+u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkomapsecimg)
 
 # Standard ULO target (certain peripheral boot modes)
-u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin
+u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkomapsecimg)
 
 # Standard ISSW target (certain devices, various boot modes)
-u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin
+u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkomapsecimg)
 
 # For SPI flash on AM335x and AM43xx, these require special byte swap handling
 # so we use the SPI_X-LOADER target instead of X-LOADER and let the
 # create-boot-image.sh script handle that
-u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin
+u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkomapsecimg)
 
 # For supporting single stage XiP QSPI on AM43xx, the image is a full u-boot
 # file, not an SPL. In this case the mkomapsecimg command looks for a
 # u-boot-HS_* prefix
-u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin
+u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin FORCE
$(call if_changed,mkomapsecimg)
 
 # For supporting the SPL loading and interpreting of FIT images whose
@@ -90,21 +91,18 @@ ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
-   $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
+   

[U-Boot] [PATCH v2 2/4] i2c: i2c-cdns: Reorder timeout loop for interrupt waiting

[Moritz Fischer]

Reorder the timeout loop such that we first check if the
condition is already true, and then call udelay() so if
the condition is already true, break early.

Reviewed-by: Michal Simek 
Signed-off-by: Moritz Fischer 
Cc: Heiko Schocher 
Cc: Michal Simek 
Cc: u-boot@lists.denx.de
---
Changes from v1:
- None

---
 drivers/i2c/i2c-cdns.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index c1d6427..1c9fda8 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -130,10 +130,10 @@ static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, 
u32 mask)
int timeout, int_status;
 
for (timeout = 0; timeout < 100; timeout++) {
-   udelay(100);
int_status = readl(_i2c->interrupt_status);
if (int_status & mask)
break;
+   udelay(100);
}
 
/* Clear interrupt status flags */
-- 
2.7.4

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[U-Boot] [PATCH v2 4/4] i2c: i2c-cdns: No need for dedicated probe function

[Moritz Fischer]

The generic probe code in dm works, so get rid of the leftover cruft.

Signed-off-by: Moritz Fischer 
Cc: Heiko Schocher 
Cc: Michal Simek 
Cc: u-boot@lists.denx.de
---
Changes from v1:
- None
---
 drivers/i2c/i2c-cdns.c | 21 -
 1 file changed, 21 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 89d429b..dec1820 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -226,26 +226,6 @@ static int cdns_i2c_set_bus_speed(struct udevice *dev, 
unsigned int speed)
return 0;
 }
 
-/* Probe to see if a chip is present. */
-static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
-   uint chip_flags)
-{
-   struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
-   struct cdns_i2c_regs *regs = i2c_bus->regs;
-
-   /* Attempt to read a byte */
-   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
-   CDNS_I2C_CONTROL_RW);
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
-   writel(0xFF, >interrupt_status);
-   writel(chip_addr, >address);
-   writel(1, >transfer_size);
-
-   return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
-   CDNS_I2C_INTERRUPT_NACK) &
-   CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
-}
-
 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
*data,
   u32 len)
 {
@@ -453,7 +433,6 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
 
 static const struct dm_i2c_ops cdns_i2c_ops = {
.xfer = cdns_i2c_xfer,
-   .probe_chip = cdns_i2c_probe_chip,
.set_bus_speed = cdns_i2c_set_bus_speed,
 };
 
-- 
2.7.4

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[U-Boot] [PATCH v2 1/4] i2c: i2c-cdns: Detect unsupported sequences for rev 1.0

[Moritz Fischer]

Revision 1.0 of this IP has a couple of issues, such as not supporting
repeated start conditions for read transfers.

So scan through the list of i2c messages for these conditions
and report an error if they are attempted.

This has been fixed for revision 1.4 of the IP, so only report the error
when the IP can really not do it.

Signed-off-by: Moritz Fischer 
Cc: Heiko Schocher 
Cc: Michal Simek 
Cc: u-boot@lists.denx.de
---
Changes from v1:
- Removed additional blank lines
- No longer modify printout paths
- Rebased on top of prior patches for r1p14 support
---
 drivers/i2c/i2c-cdns.c | 66 +++---
 1 file changed, 52 insertions(+), 14 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index ef85a70..c1d6427 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -67,6 +67,7 @@ struct cdns_i2c_regs {
 
 #define CDNS_I2C_FIFO_DEPTH16
 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
+#define CDNS_I2C_BROKEN_HOLD_BIT   BIT(0)
 
 #ifdef DEBUG
 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
@@ -114,6 +115,13 @@ struct i2c_cdns_bus {
int id;
unsigned int input_freq;
struct cdns_i2c_regs __iomem *regs; /* register base */
+
+   int hold_flag;
+   u32 quirks;
+};
+
+struct cdns_i2c_platform_data {
+   u32 quirks;
 };
 
 /* Wait for an interrupt */
@@ -236,18 +244,14 @@ static int cdns_i2c_probe_chip(struct udevice *bus, uint 
chip_addr,
 }
 
 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
*data,
-  u32 len, bool next_is_read)
+  u32 len)
 {
u8 *cur_data = data;
 
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
-   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
-   CDNS_I2C_CONTROL_HOLD);
+   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
 
-   /* if next is a read, we need to clear HOLD, doesn't work */
-   if (next_is_read)
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
 
clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
 
@@ -267,7 +271,9 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
}
 
/* All done... release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+   if (!i2c_bus->hold_flag)
+   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
/* Wait for the address and data to be sent */
if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
return -ETIMEDOUT;
@@ -285,7 +291,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, 
u32 addr, u8 *data,
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
/* Check the hardware can handle the requested bytes */
-   if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
+   if ((len < 0))
return -EINVAL;
 
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
@@ -310,7 +316,8 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, 
u32 addr, u8 *data,
*(cur_data++) = readl(>data);
} while (readl(>transfer_size) != 0);
/* All done... release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+   if (!i2c_bus->hold_flag)
+   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
 
 #ifdef DEBUG
cdns_i2c_debug_status(regs);
@@ -322,19 +329,41 @@ static int cdns_i2c_xfer(struct udevice *dev, struct 
i2c_msg *msg,
 int nmsgs)
 {
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
-   int ret;
+   int ret, count;
+   bool hold_quirk;
+
+   hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
+
+   if (nmsgs > 1) {
+   /*
+* This controller does not give completion interrupt after a
+* master receive message if HOLD bit is set (repeated start),
+* resulting in SW timeout. Hence, if a receive message is
+* followed by any other message, an error is returned
+* indicating that this sequence is not supported.
+*/
+   for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
+   if (msg[count].flags & I2C_M_RD) {
+   printf("Can't do repeated start after a receive 
message\n");
+   return -EOPNOTSUPP;
+   }
+   }
+
+   i2c_bus->hold_flag = 1;
+   setbits_le32(_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
+   } else {
+   i2c_bus->hold_flag = 0;
+   }
 
debug("i2c_xfer: %d messages\n", nmsgs);
for (; nmsgs > 0; nmsgs--, msg++) {
-   bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
-
   

[U-Boot] [PATCH v2 3/4] i2c: i2c-cdns: Implement workaround for hold quirk of the rev 1.0

[Moritz Fischer]

Revision 1.0 of this IP has a quirk where if during a long read transfer
the transfer_size register will go to 0, the master will send a NACK to
the slave prematurely.
The way to work around this is to reprogram the transfer_size register
mid-transfer when the only the receive fifo is known full, i.e. the I2C
bus is known non-active.
The workaround is based on the implementation in the linux-kernel.

Signed-off-by: Moritz Fischer 
Cc: Heiko Schocher 
Cc: Michal Simek 
Cc: u-boot@lists.denx.de
---
Changes from v1:
- Fixed the removal/addition of printf/debug
---
 drivers/i2c/i2c-cdns.c | 119 -
 1 file changed, 89 insertions(+), 30 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 1c9fda8..89d429b 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -67,6 +68,8 @@ struct cdns_i2c_regs {
 
 #define CDNS_I2C_FIFO_DEPTH16
 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
+#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
+
 #define CDNS_I2C_BROKEN_HOLD_BIT   BIT(0)
 
 #ifdef DEBUG
@@ -247,15 +250,21 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
   u32 len)
 {
u8 *cur_data = data;
-
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
+   /* Set the controller in Master transmit mode and clear FIFO */
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
-
-
clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
 
+   /* Check message size against FIFO depth, and set hold bus bit
+* if it is greater than FIFO depth
+*/
+   if (len > CDNS_I2C_FIFO_DEPTH)
+   setbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
+   /* Clear the interrupts in status register */
writel(0xFF, >interrupt_status);
+
writel(addr, >address);
 
while (len--) {
@@ -280,48 +289,98 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
return 0;
 }
 
+static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
+{
+   return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
+}
+
 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
- u32 len)
+ u32 recv_count)
 {
-   u32 status;
-   u32 i = 0;
u8 *cur_data = data;
-
-   /* TODO: Fix this */
struct cdns_i2c_regs *regs = i2c_bus->regs;
+   int curr_recv_count;
+   int updatetx, hold_quirk;
 
/* Check the hardware can handle the requested bytes */
-   if ((len < 0))
+   if ((recv_count < 0))
return -EINVAL;
 
+   curr_recv_count = recv_count;
+
+   /* Check for the message size against the FIFO depth */
+   if (recv_count > CDNS_I2C_FIFO_DEPTH)
+   setbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
CDNS_I2C_CONTROL_RW);
 
+   if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
+   curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
+   writel(curr_recv_count, >transfer_size);
+   } else {
+   writel(recv_count, >transfer_size);
+   }
+
/* Start reading data */
writel(addr, >address);
-   writel(len, >transfer_size);
-
-   /* Wait for data */
-   do {
-   status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
-   CDNS_I2C_INTERRUPT_DATA);
-   if (!status) {
-   /* Release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
-   return -ETIMEDOUT;
+
+   updatetx = recv_count > curr_recv_count;
+
+   hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
+
+   while (recv_count) {
+   while (readl(>status) & CDNS_I2C_STATUS_RXDV) {
+   if (recv_count < CDNS_I2C_FIFO_DEPTH &&
+   !i2c_bus->hold_flag) {
+   clrbits_le32(>control,
+CDNS_I2C_CONTROL_HOLD);
+   }
+   *(cur_data)++ = readl(>data);
+   recv_count--;
+   curr_recv_count--;
+
+   if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
+   break;
}
-   debug("Read %d bytes\n",
- len - readl(>transfer_size));
-   for (; i < len - readl(>transfer_size); i++)
-   *(cur_data++) = readl(>data);
-   } while (readl(>transfer_size) != 0);
-   /* All done... 

Re: [U-Boot] [PATCH] powerpc: mpc83xx: Enable pre-relocation malloc

[Joakim Tjernlund]

On Fri, 2017-01-06 at 14:56 +0100, Mario Six wrote:
> To enable DM on MPC83xx, we need pre-relocation malloc, which is
> implemented in this patch.
> 

Would be nice if you could avoid using r1, each time you modify r1 gdb will be
upset/confused if you ever try to debug start.S with gdb.

I guess the whole file need a bit of trimming to avoid using r1 but one has to 
start somewhere.

 Jocke
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[U-Boot] [PATCH 1/2] spl: Move check for SPL_LIBCOMMON support to header

[Andrew F. Davis]

Print statements in SPL depend on lib/common support, so many such
statements are ifdef'd, move the check to the common.h header and
remove these inline checks.

Signed-off-by: Andrew F. Davis 
---
 common/spl/spl.c |  2 --
 common/spl/spl_ext.c |  8 
 common/spl/spl_fat.c |  6 --
 common/spl/spl_fit.c |  4 
 common/spl/spl_mmc.c | 18 --
 common/spl/spl_sata.c|  2 --
 common/spl/spl_usb.c |  2 --
 drivers/mmc/mmc.c| 10 --
 drivers/mmc/mmc_legacy.c |  2 --
 include/common.h |  2 +-
 10 files changed, 1 insertion(+), 55 deletions(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index f7df834e32..bcf408ce8e 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -314,12 +314,10 @@ static int boot_from_devices(struct spl_image_info 
*spl_image,
struct spl_image_loader *loader;
 
loader = spl_ll_find_loader(spl_boot_list[i]);
-#if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
if (loader)
printf("Trying to boot from %s", loader->name);
else
puts("SPL: Unsupported Boot Device!\n");
-#endif
if (loader && !spl_load_image(spl_image, loader))
return 0;
}
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index 1b8e15e37d..6165f88d2b 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -31,9 +31,7 @@ int spl_load_image_ext(struct spl_image_info *spl_image,
 
err = ext4fs_mount(0);
if (!err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: ext4fs mount err - %d\n", __func__, err);
-#endif
goto end;
}
 
@@ -57,11 +55,9 @@ int spl_load_image_ext(struct spl_image_info *spl_image,
err = ext4fs_read((char *)spl_image->load_addr, 0, filelen, );
 
 end:
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
if (err < 0)
printf("%s: error reading image %s, err - %d\n",
   __func__, filename, err);
-#endif
 
return err < 0;
 }
@@ -84,9 +80,7 @@ int spl_load_image_ext_os(struct spl_image_info *spl_image,
 
err = ext4fs_mount(0);
if (!err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: ext4fs mount err - %d\n", __func__, err);
-#endif
return -1;
}
 #if defined(CONFIG_SPL_ENV_SUPPORT)
@@ -129,10 +123,8 @@ defaults:
 
err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, filelen, 
);
if (err < 0) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: error reading image %s, err - %d\n",
   __func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err);
-#endif
return -1;
}
 
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index a14acceebb..aa5a39e4f7 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -29,9 +29,7 @@ static int spl_register_fat_device(struct blk_desc 
*block_dev, int partition)
 
err = fat_register_device(block_dev, partition);
if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: fat register err - %d\n", __func__, err);
-#endif
return err;
}
 
@@ -93,11 +91,9 @@ int spl_load_image_fat(struct spl_image_info *spl_image,
}
 
 end:
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
if (err <= 0)
printf("%s: error reading image %s, err - %d\n",
   __func__, filename, err);
-#endif
 
return (err <= 0);
 }
@@ -143,10 +139,8 @@ defaults:
err = file_fat_read(CONFIG_SPL_FS_LOAD_ARGS_NAME,
(void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
if (err <= 0) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: error reading image %s, err - %d\n",
   __func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err);
-#endif
return -1;
}
 
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index aae556f97d..37ce7cc35f 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -40,10 +40,8 @@ static int spl_fit_select_fdt(const void *fdt, int images, 
int *fdt_offsetp)
 node = fdt_next_subnode(fdt, node)) {
name = fdt_getprop(fdt, node, "description", );
if (!name) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: Missing FDT description in DTB\n",
   __func__);
-#endif
return -EINVAL;
}
if (board_fit_config_name_match(name))
@@ -72,7 +70,6 @@ static int spl_fit_select_fdt(const void *fdt, int images, 
int *fdt_offsetp)
return len;
}
 
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("No matching DT out of these options:\n");
for (node = fdt_first_subnode(fdt, conf);
 node >= 0;
@@ -80,7 +77,6 @@ static int 

[U-Boot] [PATCH 2/2] spl: Remove inline ifdef check for EXT and FAT support

[Andrew F. Davis]

These files are only included for build by the make system
when CONFIG_SPL_{EXT,FAT}_SUPPORT is enabled, remove the unneed
checks for these in the source files.

Signed-off-by: Andrew F. Davis 
---
 common/spl/spl_ext.c | 2 --
 common/spl/spl_fat.c | 2 --
 2 files changed, 4 deletions(-)

diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index 6165f88d2b..a58f7ef3fe 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -9,7 +9,6 @@
 #include 
 #include 
 
-#ifdef CONFIG_SPL_EXT_SUPPORT
 int spl_load_image_ext(struct spl_image_info *spl_image,
   struct blk_desc *block_dev, int partition,
   const char *filename)
@@ -138,4 +137,3 @@ int spl_load_image_ext_os(struct spl_image_info *spl_image,
return -ENOSYS;
 }
 #endif
-#endif
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index aa5a39e4f7..66917ffa4f 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -19,7 +19,6 @@
 
 static int fat_registered;
 
-#ifdef CONFIG_SPL_FAT_SUPPORT
 static int spl_register_fat_device(struct blk_desc *block_dev, int partition)
 {
int err = 0;
@@ -154,4 +153,3 @@ int spl_load_image_fat_os(struct spl_image_info *spl_image,
return -ENOSYS;
 }
 #endif
-#endif
-- 
2.11.0

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Re: [U-Boot] [PATCH 1/2] spl: Move check for SPL_LIBCOMMON support to header

[Andrew F. Davis]

This is not based on the latest upstream, please ignore.

Sorry for the noise.

Andrew

On 01/06/2017 01:09 PM, Andrew F. Davis wrote:
> Print statements in SPL depend on lib/common support, so many such
> statements are ifdef'd, move the check to the common.h header and
> remove these inline checks.
> 
> Signed-off-by: Andrew F. Davis 
> ---
>  common/spl/spl.c |  2 --
>  common/spl/spl_ext.c |  8 
>  common/spl/spl_fat.c |  6 --
>  common/spl/spl_fit.c |  4 
>  common/spl/spl_mmc.c | 18 --
>  common/spl/spl_sata.c|  2 --
>  common/spl/spl_usb.c |  2 --
>  drivers/mmc/mmc.c| 10 --
>  drivers/mmc/mmc_legacy.c |  2 --
>  include/common.h |  3 ++-
>  10 files changed, 2 insertions(+), 55 deletions(-)
> 
> diff --git a/common/spl/spl.c b/common/spl/spl.c
> index b7ec333c8a..30b540797f 100644
> --- a/common/spl/spl.c
> +++ b/common/spl/spl.c
> @@ -404,9 +404,7 @@ static int spl_load_image(u32 boot_device)
>   return spl_board_load_image();
>  #endif
>   default:
> -#if defined(CONFIG_SPL_SERIAL_SUPPORT) && 
> defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
>   puts("SPL: Unsupported Boot Device!\n");
> -#endif
>   return -ENODEV;
>   }
>  
> diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
> index a85dc85ffe..9fe1c026bf 100644
> --- a/common/spl/spl_ext.c
> +++ b/common/spl/spl_ext.c
> @@ -31,9 +31,7 @@ int spl_load_image_ext(struct blk_desc *block_dev,
>  
>   err = ext4fs_mount(0);
>   if (!err) {
> -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
>   printf("%s: ext4fs mount err - %d\n", __func__, err);
> -#endif
>   goto end;
>   }
>  
> @@ -57,11 +55,9 @@ int spl_load_image_ext(struct blk_desc *block_dev,
>   err = ext4fs_read((char *)spl_image.load_addr, filelen, );
>  
>  end:
> -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
>   if (err < 0)
>   printf("%s: error reading image %s, err - %d\n",
>  __func__, filename, err);
> -#endif
>  
>   return err < 0;
>  }
> @@ -83,9 +79,7 @@ int spl_load_image_ext_os(struct blk_desc *block_dev, int 
> partition)
>  
>   err = ext4fs_mount(0);
>   if (!err) {
> -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
>   printf("%s: ext4fs mount err - %d\n", __func__, err);
> -#endif
>   return -1;
>   }
>  #if defined(CONFIG_SPL_ENV_SUPPORT)
> @@ -127,10 +121,8 @@ defaults:
>  
>   err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, );
>   if (err < 0) {
> -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
>   printf("%s: error reading image %s, err - %d\n",
>  __func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err);
> -#endif
>   return -1;
>   }
>  
> diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
> index 73d33f54fc..bb78445d6a 100644
> --- a/common/spl/spl_fat.c
> +++ b/common/spl/spl_fat.c
> @@ -29,9 +29,7 @@ static int spl_register_fat_device(struct blk_desc 
> *block_dev, int partition)
>  
>   err = fat_register_device(block_dev, partition);
>   if (err) {
> -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
>   printf("%s: fat register err - %d\n", __func__, err);
> -#endif
>   return err;
>   }
>  
> @@ -93,11 +91,9 @@ int spl_load_image_fat(struct blk_desc *block_dev,
>   }
>  
>  end:
> -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
>   if (err <= 0)
>   printf("%s: error reading image %s, err - %d\n",
>  __func__, filename, err);
> -#endif
>  
>   return (err <= 0);
>  }
> @@ -141,10 +137,8 @@ defaults:
>   err = file_fat_read(CONFIG_SPL_FS_LOAD_ARGS_NAME,
>   (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
>   if (err <= 0) {
> -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
>   printf("%s: error reading image %s, err - %d\n",
>  __func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err);
> -#endif
>   return -1;
>   }
>  
> diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> index be86072c24..372eae85ce 100644
> --- a/common/spl/spl_fit.c
> +++ b/common/spl/spl_fit.c
> @@ -40,10 +40,8 @@ static int spl_fit_select_fdt(const void *fdt, int images, 
> int *fdt_offsetp)
>node = fdt_next_subnode(fdt, node)) {
>   name = fdt_getprop(fdt, node, "description", );
>   if (!name) {
> -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
>   printf("%s: Missing FDT description in DTB\n",
>  __func__);
> -#endif
>   return -EINVAL;
>   }
>   if (board_fit_config_name_match(name))
> @@ -72,7 +70,6 @@ static int spl_fit_select_fdt(const void *fdt, int images, 
> int *fdt_offsetp)
>   return len;
>   }
>  
> -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
>   printf("No matching DT out of these options:\n");
>   for (node = fdt_first_subnode(fdt, conf);
>node >= 

[U-Boot] [PATCH] mkimage: Add support for signing with pkcs11

[George McCollister]

Add support for signing with the pkcs11 engine. This allows FIT images
to be signed with keys securely stored on a smartcard, hardware security
module, etc without exposing the keys.

Support for other engines can be added in the future by modifying
rsa_engine_get_pub_key() and rsa_engine_get_priv_key() to construct
correct key_id strings.

Signed-off-by: George McCollister 
---
 doc/uImage.FIT/signature.txt | 143 +
 include/image.h  |   5 +-
 lib/rsa/rsa-sign.c   | 244 +--
 tools/fit_image.c|   3 +-
 tools/image-host.c   |  30 +++---
 tools/imagetool.h|   1 +
 tools/mkimage.c  |  10 +-
 7 files changed, 408 insertions(+), 28 deletions(-)

diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt
index e4874018fa..7cdb7bf324 100644
--- a/doc/uImage.FIT/signature.txt
+++ b/doc/uImage.FIT/signature.txt
@@ -385,6 +385,149 @@ Test Verified Boot Run: signed config with bad hash: OK
 Test passed
 
 
+Hardware Signing with PKCS#11
+-
+
+Securely managing private signing keys can challenging, especially when the
+keys are stored on the file system of a computer that is connected to the
+Internet. If an attacker is able to steal the key, they can sign malicious FIT
+images which will appear genuine to your devices.
+
+An alternative solution is to keep your signing key securely stored on hardware
+device like a smartcard, USB token or Hardware Security Module (HSM) and have
+them perform the signing. PKCS#11 is standard for interfacing with these crypto
+device.
+
+Requirements:
+Smartcard/USB token/HSM which can work with the pkcs11 engine
+openssl
+libp11 (provides pkcs11 engine)
+p11-kit (recommended to simplify setup)
+opensc (for smartcards and smartcard like USB devices)
+gnutls (recommended for key generation, p11tool)
+
+The following examples use the Nitrokey Pro. Instructions for other devices 
may vary.
+
+Notes on pkcs11 engine setup:
+
+Make sure p11-kit, opensc are installed and that p11-kit is setup to use 
opensc.
+/usr/share/p11-kit/modules/opensc.module should be present on your system.
+
+
+Generating Keys On the Nitrokey:
+
+$ gpg --card-edit
+
+Reader ...: Nitrokey Nitrokey Pro () 00 00
+Application ID ...: 
+Version ..: 2.1
+Manufacturer .: ZeitControl
+Serial number : 
+Name of cardholder: [not set]
+Language prefs ...: de
+Sex ..: unspecified
+URL of public key : [not set]
+Login data ...: [not set]
+Signature PIN : forced
+Key attributes ...: rsa2048 rsa2048 rsa2048
+Max. PIN lengths .: 32 32 32
+PIN retry counter : 3 0 3
+Signature counter : 0
+Signature key : [none]
+Encryption key: [none]
+Authentication key: [none]
+General key info..: [none]
+
+gpg/card> generate
+Make off-card backup of encryption key? (Y/n) n
+
+Please note that the factory settings of the PINs are
+  PIN = '123456' Admin PIN = '12345678'
+You should change them using the command --change-pin
+
+What keysize do you want for the Signature key? (2048) 4096
+The card will now be re-configured to generate a key of 4096 bits
+Note: There is no guarantee that the card supports the requested size.
+  If the key generation does not succeed, please check the
+  documentation of your card to see what sizes are allowed.
+What keysize do you want for the Encryption key? (2048) 4096
+The card will now be re-configured to generate a key of 4096 bits
+What keysize do you want for the Authentication key? (2048) 4096
+The card will now be re-configured to generate a key of 4096 bits
+Please specify how long the key should be valid.
+  0 = key does not expire
+   = key expires in n days
+  w = key expires in n weeks
+  m = key expires in n months
+  y = key expires in n years
+Key is valid for? (0)
+Key does not expire at all
+Is this correct? (y/N) y
+
+GnuPG needs to construct a user ID to identify your key.
+
+Real name: John Doe
+Email address: john@email.com
+Comment:
+You selected this USER-ID:
+  "John Doe "
+
+Change (N)ame, (C)omment, (E)mail or (O)kay/(Q)uit? o
+
+
+Using p11tool to get the token URL:
+
+Depending on system configuration, gpg-agent may need to be killed first.
+
+$ p11tool --provider /usr/lib/opensc-pkcs11.so --list-tokens
+Token 0:
+URL: 
pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000x;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29
+Label: OpenPGP card (User PIN (sig))
+Type: Hardware token
+Manufacturer: ZeitControl
+Model: PKCS#15 emulated
+Serial: 000x
+Module: (null)
+
+
+Token 1:
+URL: 
pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000x;token=OpenPGP%20card%20%28User%20PIN%29
+Label: OpenPGP card (User PIN)
+Type: Hardware token
+Manufacturer: ZeitControl
+Model: PKCS#15 emulated
+Serial: 

[U-Boot] [PATCH 2/2] spl: Remove inline ifdef check for EXT and FAT support

[Andrew F. Davis]

These files are only included for build by the make system
when CONFIG_SPL_{EXT,FAT}_SUPPORT is enabled, remove the unneed
checks for these in the source files.

Signed-off-by: Andrew F. Davis 
---
 common/spl/spl_ext.c | 2 --
 common/spl/spl_fat.c | 2 --
 2 files changed, 4 deletions(-)

diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index 9fe1c026bf..954891f570 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -9,7 +9,6 @@
 #include 
 #include 
 
-#ifdef CONFIG_SPL_EXT_SUPPORT
 int spl_load_image_ext(struct blk_desc *block_dev,
int partition,
const char *filename)
@@ -135,4 +134,3 @@ int spl_load_image_ext_os(struct blk_desc *block_dev, int 
partition)
return -ENOSYS;
 }
 #endif
-#endif
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index bb78445d6a..9339dc81a3 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -19,7 +19,6 @@
 
 static int fat_registered;
 
-#ifdef CONFIG_SPL_FAT_SUPPORT
 static int spl_register_fat_device(struct blk_desc *block_dev, int partition)
 {
int err = 0;
@@ -151,4 +150,3 @@ int spl_load_image_fat_os(struct blk_desc *block_dev, int 
partition)
return -ENOSYS;
 }
 #endif
-#endif
-- 
2.11.0

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[U-Boot] [PATCH 1/2] spl: Move check for SPL_LIBCOMMON support to header

[Andrew F. Davis]

Print statements in SPL depend on lib/common support, so many such
statements are ifdef'd, move the check to the common.h header and
remove these inline checks.

Signed-off-by: Andrew F. Davis 
---
 common/spl/spl.c |  2 --
 common/spl/spl_ext.c |  8 
 common/spl/spl_fat.c |  6 --
 common/spl/spl_fit.c |  4 
 common/spl/spl_mmc.c | 18 --
 common/spl/spl_sata.c|  2 --
 common/spl/spl_usb.c |  2 --
 drivers/mmc/mmc.c| 10 --
 drivers/mmc/mmc_legacy.c |  2 --
 include/common.h |  3 ++-
 10 files changed, 2 insertions(+), 55 deletions(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index b7ec333c8a..30b540797f 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -404,9 +404,7 @@ static int spl_load_image(u32 boot_device)
return spl_board_load_image();
 #endif
default:
-#if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
puts("SPL: Unsupported Boot Device!\n");
-#endif
return -ENODEV;
}
 
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index a85dc85ffe..9fe1c026bf 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -31,9 +31,7 @@ int spl_load_image_ext(struct blk_desc *block_dev,
 
err = ext4fs_mount(0);
if (!err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: ext4fs mount err - %d\n", __func__, err);
-#endif
goto end;
}
 
@@ -57,11 +55,9 @@ int spl_load_image_ext(struct blk_desc *block_dev,
err = ext4fs_read((char *)spl_image.load_addr, filelen, );
 
 end:
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
if (err < 0)
printf("%s: error reading image %s, err - %d\n",
   __func__, filename, err);
-#endif
 
return err < 0;
 }
@@ -83,9 +79,7 @@ int spl_load_image_ext_os(struct blk_desc *block_dev, int 
partition)
 
err = ext4fs_mount(0);
if (!err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: ext4fs mount err - %d\n", __func__, err);
-#endif
return -1;
}
 #if defined(CONFIG_SPL_ENV_SUPPORT)
@@ -127,10 +121,8 @@ defaults:
 
err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, );
if (err < 0) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: error reading image %s, err - %d\n",
   __func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err);
-#endif
return -1;
}
 
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 73d33f54fc..bb78445d6a 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -29,9 +29,7 @@ static int spl_register_fat_device(struct blk_desc 
*block_dev, int partition)
 
err = fat_register_device(block_dev, partition);
if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: fat register err - %d\n", __func__, err);
-#endif
return err;
}
 
@@ -93,11 +91,9 @@ int spl_load_image_fat(struct blk_desc *block_dev,
}
 
 end:
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
if (err <= 0)
printf("%s: error reading image %s, err - %d\n",
   __func__, filename, err);
-#endif
 
return (err <= 0);
 }
@@ -141,10 +137,8 @@ defaults:
err = file_fat_read(CONFIG_SPL_FS_LOAD_ARGS_NAME,
(void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
if (err <= 0) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: error reading image %s, err - %d\n",
   __func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err);
-#endif
return -1;
}
 
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index be86072c24..372eae85ce 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -40,10 +40,8 @@ static int spl_fit_select_fdt(const void *fdt, int images, 
int *fdt_offsetp)
 node = fdt_next_subnode(fdt, node)) {
name = fdt_getprop(fdt, node, "description", );
if (!name) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: Missing FDT description in DTB\n",
   __func__);
-#endif
return -EINVAL;
}
if (board_fit_config_name_match(name))
@@ -72,7 +70,6 @@ static int spl_fit_select_fdt(const void *fdt, int images, 
int *fdt_offsetp)
return len;
}
 
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("No matching DT out of these options:\n");
for (node = fdt_first_subnode(fdt, conf);
 node >= 0;
@@ -80,7 +77,6 @@ static int spl_fit_select_fdt(const void *fdt, int images, 
int *fdt_offsetp)
name = fdt_getprop(fdt, node, "description", );
printf("   %s\n", name);
}
-#endif
 
return -ENOENT;
 }
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 

Re: [U-Boot] [v3 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

[Dinh Nguyen]

On 01/06/2017 05:19 AM, Chee Tien Fong wrote:

From: Tien Fong Chee 

Enhanced defconfig file for Arria10 to enable SPL build and supporting
device tree build for SDMMC.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Removed boot header info setup since it already fixed in mainline
---


You can probably just roll this patch together with the previous patch 
for socfpga_arria10_defconfig "[v3 07/30] arm: socfpga: arria10: add

socfpga_arria10_defconfig"

Dinh
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Re: [U-Boot] [PATCHv2 1/2] armv8: Enable CPUECTLR.SMPEN for coherency

[york sun]

On 01/06/2017 03:19 AM, Masahiro Yamada wrote:
> Hi.
>
>
> 2017-01-06 18:41 GMT+09:00 Zhiqiang Hou :
>> From: Mingkai Hu 
>>
>> For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
>> set. The SMPEN bit should be set before enabling the data cache.
>> If not enabled, the cache is not coherent with other cores and
>> data corruption could occur.
>>
>> For A57/A72, SMPEN bit enables the processor to receive instruction
>> cache and TLB maintenance operations broadcast from other processors
>> in the cluster. This bit should be set before enabling the caches and
>> MMU, or performing any cache and TLB maintenance operations.
>>
>> Signed-off-by: Mingkai Hu 
>> Signed-off-by: Gong Qianyu 
>> Signed-off-by: Mateusz Kulikowski 
>> Signed-off-by: Hou Zhiqiang 
>> ---
>> V2:
>>  - Revised the help information.
>>
>>  arch/arm/cpu/armv8/Kconfig | 18 ++
>>  arch/arm/cpu/armv8/start.S | 11 +++
>>  2 files changed, 29 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
>> index 22dce88..472b2ba 100644
>> --- a/arch/arm/cpu/armv8/Kconfig
>> +++ b/arch/arm/cpu/armv8/Kconfig
>> @@ -3,6 +3,24 @@ if ARM64
>>  config ARMV8_MULTIENTRY
>>  bool "Enable multiple CPUs to enter into U-Boot"
>>
>> +config ARMV8_SET_SMPEN
>> +bool "Enable data coherency with other cores in cluster"
>> +help
>> + Say Y here if there is not any trust firmware to set
>> + CPUECTLR_EL1.SMPEN bit before U-Boot.
>
>
> I am a bit curious about this.
> Are you planning to implement Trusted Firmware in the future?

Yes, trusted firmware has been planned and is on the way.

> It this option a temporary work-around until then?

Yes. Actually there are other things need to be disabled once U-Boot 
starts at EL2.

York
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Re: [U-Boot] [PATCH] powerpc: mpc83xx: Enable pre-relocation malloc

[york sun]

On 01/06/2017 05:57 AM, Mario Six wrote:
> To enable DM on MPC83xx, we need pre-relocation malloc, which is
> implemented in this patch.
>
> Signed-off-by: Mario Six 
> ---
>  arch/powerpc/cpu/mpc83xx/cpu_init.c|  3 +--
>  arch/powerpc/cpu/mpc83xx/spl_minimal.c |  4 +---
>  arch/powerpc/cpu/mpc83xx/start.S   | 23 +++
>  3 files changed, 25 insertions(+), 5 deletions(-)
>

Patch looks good.

Reviewed-by: York Sun 
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Re: [U-Boot] [PATCH][v3] armv8: fsl-layerscape: Add support of GPIO structure

[york sun]

On 01/06/2017 04:02 AM, Prabhakar Kushwaha wrote:
>> Prabhakar,
>>
>> My comment to your v1 still stands. You didn't use this structure for
>> lsch2. Do you have follow-up patches?
>>
>
> This structure is required while supporting Ethernet in LS1012AFRDM.
> Ethernet support will be added in future.
>

OK. I will hold this patch for now.

York

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Re: [U-Boot] [u-boot-release] [PATCH] arm: PSCI: remove CONFIG_MP to support LS1012A

[york sun]

On 01/06/2017 02:16 AM, Chenhui Zhao wrote:
> To support PSCI on LS1012A, remove the macro CONFIG_MP.
> And, do code cleanup.
>
> Signed-off-by: Chenhui Zhao 
> ---
>  arch/arm/cpu/armv8/cpu-dt.c   | 14 
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c   | 33 
> +--
>  arch/arm/cpu/armv8/sec_firmware.c |  2 +-
>  arch/arm/include/asm/arch-fsl-layerscape/mp.h |  4 
>  arch/arm/include/asm/armv8/sec_firmware.h |  7 ++
>  5 files changed, 33 insertions(+), 27 deletions(-)

Chenhui

The patch looks good but the commit message doesn't match. There is 
nothing specific to LS1012A. Can you rewrite the subject and commit message?

York
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[U-Boot] [PATCH] arm: PSCI: remove CONFIG_MP to support LS1012A

[Chenhui Zhao]

To support PSCI on LS1012A, remove the macro CONFIG_MP.
And, do code cleanup.

Signed-off-by: Chenhui Zhao 
---
 arch/arm/cpu/armv8/cpu-dt.c   | 14 
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c   | 33 +--
 arch/arm/cpu/armv8/sec_firmware.c |  2 +-
 arch/arm/include/asm/arch-fsl-layerscape/mp.h |  4 
 arch/arm/include/asm/armv8/sec_firmware.h |  7 ++
 5 files changed, 33 insertions(+), 27 deletions(-)

diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 9ffb49c..247d8da 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -6,26 +6,22 @@
 
 #include 
 #include 
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include 
-#endif
 
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 int psci_update_dt(void *fdt)
 {
-#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_PSCI)
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/*
 * If the PSCI in SEC Firmware didn't work, avoid to update the
 * device node of PSCI. But still return 0 instead of an error
 * number to support detecting PSCI dynamically and then switching
 * the SMP boot method between PSCI and spin-table.
 */
-   if (sec_firmware_support_psci_version() == 0x)
+   if (sec_firmware_support_psci_version() == PSCI_INVALID_VER)
return 0;
-#endif
+
fdt_psci(fdt);
-#endif
-#endif
+
return 0;
 }
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 0b516e3..a2b6c02 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -14,18 +14,14 @@
 #include 
 #include 
 #include 
-#ifdef CONFIG_MP
 #include 
-#endif
 #include 
 #include 
 #include 
 #ifdef CONFIG_FSL_ESDHC
 #include 
 #endif
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include 
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -391,28 +387,31 @@ int cpu_eth_init(bd_t *bis)
return error;
 }
 
+static inline int check_psci(void)
+{
+   unsigned int psci_ver;
+
+   psci_ver = sec_firmware_support_psci_version();
+   if (psci_ver == PSCI_INVALID_VER)
+   return 1;
+
+   return 0;
+}
+
 int arch_early_init_r(void)
 {
-#ifdef CONFIG_MP
-   int rv = 1;
-   u32 psci_ver = 0x;
-#endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
erratum_a009635();
 #endif
 
-#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
-   /* Check the psci version to determine if the psci is supported */
-   psci_ver = sec_firmware_support_psci_version();
-#endif
-   if (psci_ver == 0x) {
-   rv = fsl_layerscape_wake_seconday_cores();
-   if (rv)
+   if (check_psci()) {
+   printf("PSCI: PSCI does not exist.\n");
+
+   /* if PSCI does not exist, boot secondary cores here */
+   if (fsl_layerscape_wake_seconday_cores())
printf("Did not wake secondary cores\n");
}
-#endif
 
 #ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
diff --git a/arch/arm/cpu/armv8/sec_firmware.c 
b/arch/arm/cpu/armv8/sec_firmware.c
index 2ddd67e..ecab451 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -227,7 +227,7 @@ unsigned int sec_firmware_support_psci_version(void)
if (sec_firmware_addr & SEC_FIRMWARE_RUNNING)
return _sec_firmware_support_psci_version();
 
-   return 0x;
+   return PSCI_INVALID_VER;
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h 
b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
index f7306ff..7f01423 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
@@ -29,7 +29,11 @@ extern u64 __spin_table[];
 extern u64 __real_cntfrq;
 extern u64 *secondary_boot_code;
 extern size_t __secondary_boot_code_size;
+#ifdef CONFIG_MP
 int fsl_layerscape_wake_seconday_cores(void);
+#else
+static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
+#endif
 void *get_spin_tbl_addr(void);
 phys_addr_t determine_mp_bootpg(void);
 void secondary_boot_func(void);
diff --git a/arch/arm/include/asm/armv8/sec_firmware.h 
b/arch/arm/include/asm/armv8/sec_firmware.h
index eb68185..f3e6a80 100644
--- a/arch/arm/include/asm/armv8/sec_firmware.h
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -11,12 +11,19 @@
 #include 
 #endif
 
+#define PSCI_INVALID_VER   0x
+
 int sec_firmware_init(const void *, u32 *, u32 *);
 int _sec_firmware_entry(const void *, u32 *, u32 *);
 bool sec_firmware_is_valid(const void *);
 #ifdef CONFIG_ARMV8_PSCI
 unsigned int sec_firmware_support_psci_version(void);
 unsigned int _sec_firmware_support_psci_version(void);
+#else
+static inline unsigned int sec_firmware_support_psci_version(void)
+{
+   return PSCI_INVALID_VER;
+}
 

Re: [U-Boot] [PATCH] README: mxc_hab: Adapt the CONFIG_SECURE_BOOT text to Kconfig

[Gary Bisson]

Hi Fabio

On Thu, Jan 05, 2017 at 09:33:08PM -0200, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> Commit 6e1f4d2652e79 ("arm: imx-common: add SECURE_BOOT option to
> Kconfig") moved the CONFIG_SECURE_BOOT option to Kconfig, so update
> the mxc_hab README file to reflect that.
> 
> Signed-off-by: Fabio Estevam 

Good catch, completely forgot about the README.

Reviewed-by: Gary Bisson 

Thanks,
Gary
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[U-Boot] [PATCH] powerpc: mpc83xx: Enable pre-relocation malloc

[Mario Six]

To enable DM on MPC83xx, we need pre-relocation malloc, which is
implemented in this patch.

Signed-off-by: Mario Six 
---
 arch/powerpc/cpu/mpc83xx/cpu_init.c|  3 +--
 arch/powerpc/cpu/mpc83xx/spl_minimal.c |  4 +---
 arch/powerpc/cpu/mpc83xx/start.S   | 23 +++
 3 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c 
b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index f911275..3a0916b 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -205,8 +205,7 @@ void cpu_init_f (volatile immap_t * im)
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
-   /* Clear initial global data */
-   memset ((void *) gd, 0, sizeof (gd_t));
+   /* global data region was cleared in start.S */
 
/* system performance tweaking */
clrsetbits_be32(>arbiter.acr, acr_mask, acr_val);
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c 
b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
index 845861e..026da12 100644
--- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -23,9 +23,7 @@ void cpu_init_f (volatile immap_t * im)
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
-   /* Clear initial global data */
-   for (i = 0; i < sizeof(gd_t); i++)
-   ((char *)gd)[i] = 0;
+   /* global data region was cleared in start.S */
 
/* system performance tweaking */
 
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 9bd86d8..f8044ac 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -265,6 +265,29 @@ in_flash:
lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + 
CONFIG_SYS_GBL_DATA_OFFSET)@l
 
+   /* r3 = end of GD area */
+   addi r3,r1,GENERATED_GBL_DATA_SIZE
+
+   /* Zero GD area */
+   li  r0, 0
+1:
+   subir3, r3, 1
+   stb r0, 0(r3)
+   cmplw   r1, r3
+   bne 1b
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+
+#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > 
CONFIG_SYS_INIT_RAM_SIZE
+#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#endif
+
+   /* r1 = stack pointer / pre-reloc malloc area */
+   subir1, r1, CONFIG_SYS_MALLOC_F_LEN
+
+   /* Set pointer to pre-reloc malloc area in GD */
+   stw r1, GD_MALLOC_BASE(r3)
+#endif
li  r0, 0   /* Make room for stack frame header and */
stwur0, -4(r1)  /* clear final stack frame so that  */
stwur0, -4(r1)  /* stack backtraces terminate cleanly   */
-- 
2.9.0

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[U-Boot] usb start hangs

[Tony O'Brien]

Hi -


We recently updated our U-Boot release to v2016.11 and now our USB devices 
don't work.  When usb start is executed with a device inserted it hangs at 
'scanning bus 0 for devices...' and doesn't recover.  Our product uses an NXP 
T2081 and I can reproduce this issue on the T2080RDB development board using 
the tip of U-Boot.  For testing I am using both an EMTEC 16GB USB thumb drive 
and an Edimax Fast Ethernet adapter.  The code always hangs at 
drivers/usb/host/ehci-hcd.c:557 in ehci_submit_async, just before the call to 
handshake.


I have traced the issue to 'Commit cb1629f91a48 powerpc: Disable flush or 
invalidate dcache by range for some SoCs', which is prior to the v2016.07 
release.  Commit ac337168ad81 mentioned in this patch removes the original 
empty functions for the MPC85xx (and others), allowing the functions to be 
used, but I don't know how they would have worked before this.


Either reverting cb1629f91a48 or adding '|| defined(MPC85xx) ' to the #if 
statements makes usb work again.


diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S
index 66cf02dbd0..ad28c7c369 100644
--- a/arch/powerpc/lib/ppccache.S
+++ b/arch/powerpc/lib/ppccache.S
@@ -65,7 +65,7 @@ ppcSync:
 * flush_dcache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(flush_dcache_range)
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
   li  r5,L1_CACHE_BYTES-1
   andcr3,r3,r5
   subfr4,r3,r4
@@ -89,7 +89,7 @@ _GLOBAL(flush_dcache_range)
 * invalidate_dcache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(invalidate_dcache_range)
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
   li  r5,L1_CACHE_BYTES-1
   andcr3,r3,r5
   subfr4,r3,r4

Do you have any thoughts on this before I submit the patch?


Cheers,

Tony O'Brien
Senior Software/Hardware Engineer
Allied Telesis Labs
27 Nazareth Avenue
Christchurch 8024
New Zealand
Ph: +64-3-339 3000
DDI: +64-3-339 9210
Web: http://AlliedTelesis.com


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Re: [U-Boot] [PATCH 00/24] Lift mpc85xx config options to Kconfig

[york sun]

On 01/05/2017 05:28 AM, Tom Rini wrote:
>
> There were a few minor problems in this series which I fixed up.  The
> only remaining "issue" here is that sbc8641d has a ~3KiB size increase.
> This is due to the issue that previously it did _not_ define
> CONFIG_SYS_FSL_DDR2 but only CONFIG_SYS_FSL_DDR_86XX and that was a
> valid build.  Now that CONFIG_SYS_FSL_DDR2 is set too, other files are
> being included and linked.
>

I found out why. Another config macro CONFIG_SPD_EEPROM is undefined in 
sbc8641 header file to skip the DDR driver. This board has the option to 
go both ways. A proper fix will be lifting this config macro to Kconfig. 
It is on my to-do list.

York
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[U-Boot] Create ramdisk image

[Vered Zvi]

Hello,

In order to create a ram disk image I'm running:

genext2fs -d /local/rootfs -b 16384 -D rootfs_devices.tab ramdisk.img

gzip -v9 ramdisk.img

mkimage -A ARM -T ramdisk -C gzip -n 'Ramdisk Image' -d ramdisk.img.gz 
uRootfs.gz

Am I right ?

I'm asking because upon boot I'm getting:

/sbin/init exists but couldn't execute it (error -8)
/bin/sh exists but couldn't execute it (error -8)

Thank you,
Z.V
The information contained in this communication is proprietary to Israel 
Aerospace Industries Ltd. and/or third parties, may contain confidential or 
privileged information, and is intended only for the use of the intended 
addressee thereof. If you are not the intended addressee, please be aware that 
any use, disclosure, distribution and/or copying of this communication is 
strictly prohibited. If you receive this communication in error, please notify 
the sender immediately and delete it from your computer.

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[U-Boot] [PATCH] powerpc: Enable flush and invalidate dcache by range for MPC85xx

[Tony O'Brien]

Commit ac337168a unified functions to flush and invalidate dcache by
range. These two functions were no-ops for SoCs other than 4xx and
MPC86xx. Adding these functions seemed to be correct but introduced
issues in some drivers when the dcache was flushed. While the root
cause was under investigation, these functions were disabled in
Commit cb1629f91a for affected SoCs, including the MPC85xx, to make
the various drivers work.

On the T208x USB stopped working after v2016.07 was pulled.  After
re-enabling the dcache functions for the MPC85xx it started working
again.  The USB and DPPA Ethernet drivers have been seen as
operational after this change but other drivers cannot be tested.

Reviewed-by: Chris Packham 
Signed-off-by: Tony O'Brien 
Cc: Marek Vasut 
Cc: York Sun 
---
The USB and Ethernet functionality has been tested on both the
T2080RDB and our own design but we don't have the hardware to test
any of the other drivers.  We will wait and see if it causes us any
issues with other drivers.
 arch/powerpc/lib/ppccache.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S
index 66cf02dbd0..ad28c7c369 100644
--- a/arch/powerpc/lib/ppccache.S
+++ b/arch/powerpc/lib/ppccache.S
@@ -65,7 +65,7 @@ ppcSync:
  * flush_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(flush_dcache_range)
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
li  r5,L1_CACHE_BYTES-1
andcr3,r3,r5
subfr4,r3,r4
@@ -89,7 +89,7 @@ _GLOBAL(flush_dcache_range)
  * invalidate_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(invalidate_dcache_range)
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
li  r5,L1_CACHE_BYTES-1
andcr3,r3,r5
subfr4,r3,r4
-- 
2.11.0

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Re: [U-Boot] [PATCH 00/24] Lift mpc85xx config options to Kconfig

[york sun]

On 01/05/2017 05:28 AM, Tom Rini wrote:
> On Wed, Dec 28, 2016 at 08:43:26AM -0800, York Sun wrote:
>
>> In this set, more mpc85xx config options are moved into Kconfig, including
>> some shared configuration for DDR, crypto, mmc, etc.
>>
>> York Sun (24):
>>   powerpc: E500: Move CONFIG_E500 and CONFIG_E500MC to Kconfig
>>   powerpc: mpc85xx: Move CONFIG_SYS_NUM_TLBCAMS to Kconfig
>>   powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to Kconfig
>>   crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig
>>   crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig
>>   powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014
>>   powerpc: T1023RDB: Remove macro CONFIG_T1023RDB
>>   powerpc: T1024RDB: Remove macro CONFIG_T1024RDB
>>   powerpc: T1040QDS: Remove macro CONFIG_T1040QDS
>>   powerpc: T2080QDS: Remove macro T2080QDS
>>   powerpc: T2080RDB: Remove macro CONFIG_T2080RDB
>>   powerpc: T2081QDS: Remove macro T2081QDS
>>   powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS
>>   fsl_ddr: Move DDR config options to driver Kconfig
>>   arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig
>>   mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* to Kconfig
>>   powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig
>>   ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig
>>   ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and
>> CONFIG_SYS_NUM_DDR_CTRLS
>>   ddr: fsl: Move CONFIG_SYS_FSL_DDR_VER to Kconfig
>>   powerpc: mpc85xx: Remove unused ifdef in config header
>>   powerpc: E6500: Move macro CONFIG_E6500 to Kconfig
>>   powerpc: mpc85xx: Move CONFIG_SYS_FSL_QORIQ_CHASSIS* to Kconfig
>>   powerpc: mpc85xx: Move macro CONFIG_SYS_PPC64 to Kconfig
>
> There were a few minor problems in this series which I fixed up.  The
> only remaining "issue" here is that sbc8641d has a ~3KiB size increase.
> This is due to the issue that previously it did _not_ define
> CONFIG_SYS_FSL_DDR2 but only CONFIG_SYS_FSL_DDR_86XX and that was a
> valid build.  Now that CONFIG_SYS_FSL_DDR2 is set too, other files are
> being included and linked.
>

Thanks, Tom. I will look into SBC8641.

York
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Re: [U-Boot] [PATCH][v3] armv8: fsl-layerscape: Add support of GPIO structure

[Prabhakar Kushwaha]

Hi York

> -Original Message-
> From: york sun
> Sent: Thursday, January 05, 2017 1:28 AM
> To: Prabhakar Kushwaha ; u-
> b...@lists.denx.de
> Cc: Mingkai Hu ; Pratiyush Srivastava
> 
> Subject: Re: [PATCH][v3] armv8: fsl-layerscape: Add support of GPIO structure
> 
> On 12/08/2016 06:58 PM, Prabhakar Kushwaha wrote:
> > Layerscape Gen2 SoC supports GPIO registers to control GPIO
> > signals. Adding support of GPIO structure to access GPIO
> > registers.
> >
> > Signed-off-by: Pratiyush Srivastava 
> > Signed-off-by: Prabhakar Kushwaha 
> > ---
> > Changes for v2: Incorporated York's comments
> > - Removed CONFIG_SYS_GPIO1_ADDR as bool
> > - Renamed CONFIG_SYS_GPIO1_ADDR
> >
> > Changes for v3:
> > - Corrected the GPIO address
> > - updated patch description
> >
> > This structure is required while supporting ethernent in LS1012AFRDM.
> >
> >
> >  arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 15
> +++
> >  1 file changed, 15 insertions(+)
> >
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > index d684a07..33f3e2e 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > @@ -52,6 +52,11 @@
> >  #define QSPI0_BASE_ADDR(CONFIG_SYS_IMMR +
> 0x0055)
> >  #define DSPI1_BASE_ADDR(CONFIG_SYS_IMMR +
> 0x0110)
> >
> > +#define GPIO1_BASE_ADDR(CONFIG_SYS_IMMR +
> 0x130)
> > +#define GPIO2_BASE_ADDR(CONFIG_SYS_IMMR +
> 0x131)
> > +#define GPIO3_BASE_ADDR(CONFIG_SYS_IMMR +
> 0x132)
> > +#define GPIO4_BASE_ADDR(CONFIG_SYS_IMMR +
> 0x133)
> > +
> >  #define LPUART_BASE(CONFIG_SYS_IMMR +
> 0x0195)
> >
> >  #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR +
> 0x0220)
> > @@ -588,6 +593,16 @@ struct ccsr_cci400 {
> > u8 res_e004[0x1 - 0xe004];
> >  };
> >
> > +struct ccsr_gpio {
> > +   u32 gpdir;
> > +   u32 gpodr;
> > +   u32 gpdat;
> > +   u32 gpier;
> > +   u32 gpimr;
> > +   u32 gpicr;
> > +   u32 gpibe;
> > +};
> > +
> >  /* MMU 500 */
> >  #define SMMU_SCR0  (SMMU_BASE + 0x0)
> >  #define SMMU_SCR1  (SMMU_BASE + 0x4)
> >
> 
> Prabhakar,
> 
> My comment to your v1 still stands. You didn't use this structure for
> lsch2. Do you have follow-up patches?
> 

This structure is required while supporting Ethernet in LS1012AFRDM.  
Ethernet support will be added in future. 

--prabhakar
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[U-Boot] [v3 30/30] arm: socfpga: arria10: Enable fpga driver build for SPL.

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- resolved build error of undefined some functions in fpga driver for SPL
  build
---
 drivers/Makefile |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/Makefile b/drivers/Makefile
index c19fa14..c15796b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)PINCTRL)+= pinctrl/
 obj-$(CONFIG_$(SPL_)RAM)   += ram/
 
 ifdef CONFIG_SPL_BUILD
-
+obj-$(CONFIG_FPGA) += fpga/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
 obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
-- 
1.7.7.4

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[U-Boot] [v3 27/30] arm: socfpga: arria10: Added drivers for Arria10 clock manager

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Reverted license changes, removing extern and volatile declaration.
---
 arch/arm/mach-socfpga/clock_manager.c  |  752 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  |  954 
 .../{clock_manager.c => clock_manager_gen5.c}  |  240 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h |  356 ++--
 4 files changed, 1573 insertions(+), 729 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..d209f7d 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,416 +7,287 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Function prototypes */
+/* Common prototypes */
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+static void cm_print_clock_quick_summary(void);
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void cm_wait_for_lock(uint32_t mask);
+void cm_wait_for_fsm(void);
+unsigned int cm_get_main_vco_clk_hz(void);
+unsigned int cm_get_per_vco_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+/* Common functions */
+int set_cpu_clk_info(void)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
-   do {
-   inter_val = readl(_manager_base->inter) & mask;
-   if (inter_val == mask)
-   retry++;
-   else
-   retry = 0;
-   if (retry >= 10)
-   break;
-   } while (1);
-}
+   /* Calculate the clock frequencies required for drivers */
+   cm_get_l4_sp_clk_hz();
+   cm_get_mmc_controller_clk_hz();
 
-/* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
-{
-   while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
+   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
+   gd->bd->bi_dsp_freq = 0;
 
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, _manager_base->bypass);
-   cm_wait_for_fsm();
-}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, _manager_base->ctrl);
-   cm_wait_for_fsm();
+   return 0;
 }
 
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
+unsigned int cm_get_spi_controller_clk_hz(void)
 {
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
+   uint32_t clock = 0;
 
-   writel(value, reg_address);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   uint32_t reg;
+   clock = cm_get_per_vco_clk_hz();
 
-   while (readl(reg_address) & mask)
-   ;
-}
+   /* get the clock prior L4 SP divider (periph_base_clk) */
+   reg = readl(_manager_base->per_pll.perbaseclk);
+   clock /= (reg + 1);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   clock = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
+#endif
 
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * 

[U-Boot] [v3 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

[Chee Tien Fong]

From: Tien Fong Chee 

This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- Created common spl_boot_device() for both gen5 and Arria10.
Changes for V2
- Release UART from reset before enalbing console, and reverting license
  changes.
---
 arch/arm/mach-socfpga/spl.c |   79 +--
 1 files changed, 76 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index fec4c7a..d381904 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -19,37 +19,58 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define BOOTINFO_BSEL_SHIFT0
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define BOOTINFO_BSEL_SHIFT12
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
const u32 bsel = readl(_regs->bootinfo);
 
-   switch (bsel & 0x7) {
+   switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7) {
case 0x1:   /* FPGA (HPS2FPGA Bridge) */
return BOOT_DEVICE_RAM;
case 0x2:   /* NAND Flash (1.8V) */
case 0x3:   /* NAND Flash (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+#endif
return BOOT_DEVICE_NAND;
case 0x4:   /* SD/MMC External Transceiver (1.8V) */
case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+#endif
return BOOT_DEVICE_MMC1;
case 0x6:   /* QSPI Flash (1.8V) */
case 0x7:   /* QSPI Flash (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+#endif
return BOOT_DEVICE_SPI;
default:
printf("Invalid boot device (bsel=%08x)!\n", bsel);
@@ -68,6 +89,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
writel(0x1, _regs->lwhps2fpgaregs);
@@ -182,3 +204,54 @@ void board_init_f(ulong dummy)
/* Configure simple malloc base pointer into RAM. */
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void board_init_f(ulong dummy)
+{
+   memset(__bss_start, 0, __bss_end - __bss_start);
+   /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+   cm_use_intosc();
+
+   watchdog_disable();
+
+   arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* release osc1 watchdog timer 0 from reset */
+   reset_deassert_osc1wd0();
+
+   /* reconfigure and enable the watchdog */
+   hw_watchdog_init();
+   WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_OF_CONTROL
+   /* We need to access to FDT as this stage */
+   /* FDT is at end of image */
+   gd->fdt_blob = (void *)(__bss_end);
+   /* Check whether we have a valid FDT or not. */
+   if (fdtdec_prepare_fdt()) {
+   panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+   "doc/README.fdt-control");
+   }
+#endif /* CONFIG_OF_CONTROL */
+
+   /* Initialize the timer */
+   timer_init();
+
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   config_dedicated_pins(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   /* Release UART from reset */
+   reset_deassert_uart();
+
+   /* enable console uart printing */
+   preloader_console_init();
+}
+#endif
-- 
1.7.7.4

___

[U-Boot] [v3 28/30] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Removed extern declaration.
---
 arch/arm/mach-socfpga/include/mach/pinmux.h |   17 +
 arch/arm/mach-socfpga/pinmux.c  |  104 +++
 2 files changed, 121 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/pinmux.c

diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h 
b/arch/arm/mach-socfpga/include/mach/pinmux.h
new file mode 100644
index 000..ff54caa
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_PINMUX_H_
+#define_PINMUX_H_
+
+#ifndef __ASSEMBLY__
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+#endif
+
+
+
+#endif /* _PINMUX_H_ */
diff --git a/arch/arm/mach-socfpga/pinmux.c b/arch/arm/mach-socfpga/pinmux.c
new file mode 100644
index 000..d45722f
--- /dev/null
+++ b/arch/arm/mach-socfpga/pinmux.c
@@ -0,0 +1,104 @@
+/*
+ *  Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+static int __do_pinctr_pins(const void *blob, int child, const char 
*node_name);
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name);
+
+static int __do_pinctr_pins(const void *blob, int child, const char *node_name)
+{
+   int len;
+   fdt_addr_t base_addr;
+   fdt_size_t size;
+   const u32 *cell;
+   u32 offset, value;
+
+   base_addr = fdtdec_get_addr_size(blob, child, "reg", );
+   if (base_addr != FDT_ADDR_T_NONE) {
+   cell = fdt_getprop(blob, child, "pinctrl-single,pins",
+   );
+   if (cell != NULL) {
+   debug("%p %d\n", cell, len);
+   for (;len > 0; len -= (2*sizeof(u32))) {
+   offset = fdt32_to_cpu(*cell++);
+   value = fdt32_to_cpu(*cell++);
+   debug("<0x%x 0x%x>\n", offset, value);
+   writel(value, base_addr + offset);
+   }
+   return 0;
+   }
+   }
+   return 1;
+}
+
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
+{
+   int child, len;
+   const char *node_name;
+
+   child = fdt_first_subnode(blob, node);
+
+   if (child < 0)
+   return 2;
+
+   node_name = fdt_get_name(blob, child, );
+
+   while (node_name) {
+   if (!strcmp(child_name, node_name)) {
+   __do_pinctr_pins(blob, child, node_name);
+   return(0);
+   }
+   child = fdt_next_subnode(blob, child);
+
+   if (child < 0)
+   break;
+
+   node_name = fdt_get_name(blob, child, );
+   }
+
+   return 1;
+}
+
+int config_dedicated_pins(const void *blob)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
+   return 2;
+
+   if (do_pinctrl_pins(blob, node, "dedicated"))
+   return 3;
+
+   return 0;
+}
+
+int config_pins(const void *blob, const char *pin_grp)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, pin_grp))
+   return 2;
+
+   return 0;
+}
-- 
1.7.7.4

___
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[U-Boot] [v3 24/30] arm: socfpga: arria10: Added support for Arria 10 socdk

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Separate patch, reuse socfpga_common.h
---
 arch/arm/mach-socfpga/system_manager.c  |4 ++-
 drivers/fpga/socfpga.c  |7 +++-
 include/configs/socfpga_arria10_socdk.h |   56 +++
 include/configs/socfpga_common.h|   33 --
 4 files changed, 71 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 9e1c3fd..e1f0082 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Altera Corporation 
+ * Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -11,8 +11,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /*
  * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index bfefafd..7fd922e 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2012-2016 Altera Corporation 
  * All rights reserved.
  *
  * SPDX-License-Identifier:BSD-3-Clause
@@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)
@@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
}
 
/* Prior programming the FPGA, all bridges need to be shut off */
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Disable all signals from hps peripheral controller to fpga */
writel(0, _regs->fpgaintfgrp_module);
+#endif
 
/* Disable all signals from FPGA to HPS SDRAM */
 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS0x5080
diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
index 577f60f..105c4c0 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2015 Altera Corporation 
+ *  Copyright (C) 2015-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0
  */
@@ -8,31 +8,20 @@
 #define __CONFIG_SOCFGPA_ARRIA10_H__
 
 #include 
+
 /* U-Boot Commands */
-#define CONFIG_SYS_NO_FLASH
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FAT_WRITE
 #define CONFIG_HW_WATCHDOG
 
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_PING
 
-/*
- * Memory configurations
- */
-#define PHYS_SDRAM_1_SIZE  0x200
-
 /* Booting Linux */
-#define CONFIG_BOOTDELAY   3
 #define CONFIG_BOOTFILE"zImage"
 #define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND  "run mmcload; run mmcboot"
@@ -40,24 +29,30 @@
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /*
- * Display CPU and Board Info
+ * U-Boot general configurations
+ */
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+
+/*
+ * U-Boot console configurations
  */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DOS_PARTITION
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE  0x8000
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9031
-
 #endif
 
+/*
+ * U-Boot environment configurations
+ */
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
-#define CONFIG_ENV_OFFSET  512/* just after the MBR */
 
 /*
  * arguments passed to the bootz command. The value of
@@ -89,6 +84,23 @@
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
"bootm ${loadaddr} - ${fdt_addr}\0"
 
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload 

[U-Boot] [v3 26/30] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions. and
arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Populating base address of UART based on handoff setting.
---
 arch/arm/mach-socfpga/Makefile|6 +-
 arch/arm/mach-socfpga/include/mach/misc.h |   32 ++
 arch/arm/mach-socfpga/misc.c  |  427 +
 arch/arm/mach-socfpga/misc_arria10.c  |  255 +++
 arch/arm/mach-socfpga/{misc.c => misc_gen5.c} |  232 ++
 5 files changed, 337 insertions(+), 615 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 create mode 100644 arch/arm/mach-socfpga/misc_arria10.c
 copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (66%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b8fcf6e..1ab68be 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,9 +9,11 @@
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o 
\
+   clock_manager_arria10.o pinmux.o
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
-   reset_manager_gen5.o
+   reset_manager_gen5.o misc_gen5.o \
+   clock_manager_gen5.o
 
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
new file mode 100644
index 000..045268d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _MISC_H_
+#define_MISC_H_
+
+extern void dwmac_deassert_reset(const unsigned int of_reset_id,
+const u32 phymode);
+
+struct bsel{
+   const char  *mode;
+   const char  *name;
+};
+
+extern struct bsel bsel_str[];
+
+#ifdef CONFIG_FPGA
+extern void socfpga_fpga_add(void);
+#else
+inline void socfpga_fpga_add(void) {}
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+unsigned int dedicated_uart_com_port(const void *blob);
+unsigned int shared_uart_com_port(const void *blob);
+unsigned int uart_com_port(const void *blob);
+#endif
+
+#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 510aa1d..7fd5c0e 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,45 +7,33 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#include 
-#else
-#include 
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
+static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct socfpga_system_manager *sysmgr_regs =
-   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_reset_manager *reset_manager_base =
-   (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-static struct nic301_registers *nic301_regs =
-   (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-#else
-static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
-   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
-static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
-   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
-#endif
-static struct scu_registers *scu_regs =
-   (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
+struct bselbsel_str[] = {
+   { "rsvd", "Reserved", },
+   { "fpga", "FPGA (HPS2FPGA Bridge)", },
+   { "nand", "NAND Flash (1.8V)", },
+   { "nand", "NAND Flash (3.0V)", },
+   { "sd", "SD/MMC External Transceiver (1.8V)", },
+   { "sd", "SD/MMC Internal Transceiver (3.0V)", },
+   { "qspi", "QSPI Flash (1.8V)", },
+   { "qspi", "QSPI Flash (3.0V)", },
+};
 
 int dram_init(void)
 {
@@ -84,219 +72,6 @@ void v7_outer_cache_disable(void)
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
 }
 
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void 

[U-Boot] [v3 23/30] arm: socfpga: arria10: Added some hardware base address for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for v3
- no changes
changes for v2
- Separate patch for adding some HW base address for Arria 10.
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |5 -
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index 902c321..2d66580 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Altera Corporation 
+ * Copyright (C) 2014-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -36,10 +36,13 @@
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 
 #define SOCFPGA_SDR_ADDRESS0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST   0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13500
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS  0xffd13300
-- 
1.7.7.4

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[U-Boot] [v3 25/30] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Chee Tien Fong]

From: Tien Fong Chee 

Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Reverted license changes, removing extern and volatile declaration
---
 arch/arm/mach-socfpga/Makefile |   16 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  155 ++--
 arch/arm/mach-socfpga/reset_manager.c  |  112 +--
 arch/arm/mach-socfpga/reset_manager_arria10.c  |  407 
 .../{reset_manager.c => reset_manager_gen5.c}  |   94 ++---
 5 files changed, 570 insertions(+), 214 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
 copy arch/arm/mach-socfpga/{reset_manager.c => reset_manager_gen5.c} (58%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..b8fcf6e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,21 +2,27 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
-# Copyright (C) 2012 Altera Corporation 
+# Copyright (C) 2012-2016 Altera Corporation 
 #
 # SPDX-License-Identifier: GPL-2.0+
 #
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
+   reset_manager_gen5.o
 
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o wrap_iocsr_config.o \
+   wrap_pinmux_config.o wrap_sdram_config.o
+endif
 
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
-  wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6225118..13f9731 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,15 +7,27 @@
 #ifndef_RESET_MANAGER_H_
 #define_RESET_MANAGER_H_
 
+/* Common function prototypes */
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
-
 void socfpga_bridges_reset(int enable);
-
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+void reset_deassert_peripherals_handoff(void);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void watchdog_disable(void);
+void reset_deassert_noc_ddr_scheduler(void);
+int is_wdt_in_reset(void);
+void emac_manage_reset(ulong emacbase, uint state);
+int reset_deassert_bridges_handoff(void);
+void reset_assert_fpga_connected_peripherals(void);
+void reset_deassert_osc1wd0(void);
+void reset_assert_uart(void);
+void reset_deassert_uart(void);
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -29,40 +41,40 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 struct socfpga_reset_manager {
-   u32 stat;
-   u32 ramstat;
-   u32 miscstat;
-   u32 ctrl;
-   u32 hdsken;
-   u32 hdskreq;
-   u32 hdskack;
-   u32 counts;
-   u32 mpu_mod_reset;
-   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
-   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
-   u32 brg_mod_reset;
-   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
-   u32 coldmodrst;
-   u32 nrstmodrst;
-   u32 dbgmodrst;
-   u32 mpuwarmmask;
-   u32 per0warmmask;
-   u32 per1warmmask;
-   u32 brgwarmmask;
-   u32 syswarmmask;
-   u32 nrstwarmmask;
-   u32 l3warmmask;
-   

[U-Boot] [v3 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

[Chee Tien Fong]

From: Tien Fong Chee 

Enhanced defconfig file for Arria10 to enable SPL build and supporting
device tree build for SDMMC.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Removed boot header info setup since it already fixed in mainline
---
 configs/socfpga_arria10_defconfig |   18 +-
 1 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
index 422261b..755bb66 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y
 CONFIG_TARGET_SOCFPGA_ARRIA10=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_IDENT_STRING="socfpga_arria10"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_DWAPB_GPIO=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
-- 
1.7.7.4

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[U-Boot] [v3 20/30] arm: socfpga: arria10: Enable SPL for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

This patch enables SPL build and implementation for Arria 10.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes.
Changes for V2
- Commit messages changed.
---
 arch/arm/Kconfig |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80c5992..0ed36cd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,9 +561,9 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
-   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
+   select SUPPORT_SPL
select OF_CONTROL
-   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
+   select SPL_OF_CONTROL
select DM
select DM_SPI_FLASH
select DM_SPI
-- 
1.7.7.4

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[U-Boot] [v3 19/30] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

[Chee Tien Fong]

From: Tien Fong Chee 

This is initial version of device tree for the Intel socfpga arria10
development kit with sdmmc.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- modified the handoff.dtsi to board specific, and moving some chosen
  config to handoff.dtsi because these config would be generated by tool
---
 arch/arm/dts/Makefile  |3 +-
 arch/arm/dts/socfpga_arria10.dtsi  |  859 
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |   30 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   |  479 +++
 4 files changed, 1370 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3ee608b..024aa5f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -137,7 +137,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb   \
socfpga_cyclone5_sr1500.dtb \
-   socfpga_cyclone5_vining_fpga.dtb
+   socfpga_cyclone5_vining_fpga.dtb\
+   socfpga_arria10_socdk_sdmmc.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
dra72-evm-revc.dtb dra71-evm.dtb
diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
new file mode 100644
index 000..f63c4b4
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -0,0 +1,859 @@
+/*
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include "skeleton.dtsi"
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   aliases {
+   ethernet0 = 
+   ethernet1 = 
+   ethernet2 = 
+   serial0 = 
+   serial1 = 
+   timer0 = 
+   timer1 = 
+   timer2 = 
+   timer3 = 
+   spi0 = 
+   spi1 = 
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <>;
+   };
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <>;
+   };
+   };
+
+   intc: intc@d000 {
+   compatible = "arm,cortex-a9-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0xd000 0x1000>,
+ <0xc100 0x100>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   interrupt-parent = <>;
+   ranges;
+
+   amba {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   pdma: pdma@ffda1000 {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0xffda1000 0x1000>;
+   interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
+<0 84 IRQ_TYPE_LEVEL_HIGH>,
+<0 85 IRQ_TYPE_LEVEL_HIGH>,
+<0 86 IRQ_TYPE_LEVEL_HIGH>,
+<0 87 IRQ_TYPE_LEVEL_HIGH>,
+<0 88 IRQ_TYPE_LEVEL_HIGH>,
+<0 89 IRQ_TYPE_LEVEL_HIGH>,
+<0 90 IRQ_TYPE_LEVEL_HIGH>,
+<0 91 IRQ_TYPE_LEVEL_HIGH>;
+   #dma-cells = <1>;
+   #dma-channels = <8>;
+   #dma-requests = <32>;
+   clocks = <_main_clk>;
+   clock-names = "apb_pclk";
+   };
+   };
+

[U-Boot] [v3 22/30] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Chee Tien Fong]

From: Tien Fong Chee 

These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Added only compat strings with matching drivers in this series patches
---
 include/fdtdec.h |8 
 lib/fdtdec.c |8 
 2 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index d074478..73e3a46 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -155,6 +155,14 @@ enum fdt_compat_id {
COMPAT_INTEL_BAYTRAIL_FSP_MDP,  /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
COMPAT_SUNXI_NAND,  /* SUNXI NAND controller */
+   COMPAT_ALTERA_SOCFPGA_CLK,  /* SoCFPGA Clock initialization */
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,   /* pinctrl-single */
+   COMPAT_ALTERA_SOCFPGA_H2F_BRG,  /* Arria10 hps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* Arria10 lwhps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_F2H_BRG,  /* Arria10 fpga2hps bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR0,   /* Arria10 fpga2SDRAM0 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR1,   /* Arria10 fpga2SDRAM1 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR2,   /* Arria10 fpga2SDRAM2 bridge */
 
COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 81f47ef..ebe4a9a 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -66,6 +66,14 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+   COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+   COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
+   COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
1.7.7.4

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[U-Boot] [v3 18/30] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

[Chee Tien Fong]

From: Tien Fong Chee 

Add base address header file for Stratix10 SoC

Signed-off-by: Chin Liang See 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ley Foon Tan 
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   48 
 1 files changed, 48 insertions(+), 0 deletions(-)
 create mode 100755 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100755
index 000..411518d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SMMU_ADDRESS   0xfa00
+#define SOCFPGA_EMAC0_ADDRESS  0xff80
+#define SOCFPGA_EMAC1_ADDRESS  0xff802000
+#define SOCFPGA_EMAC2_ADDRESS  0xff804000
+#define SOCFPGA_SDMMC_ADDRESS  0xff808000
+#define SOCFPGA_USB0_ADDRESS   0xffb0
+#define SOCFPGA_USB1_ADDRESS   0xffb4
+#define SOCFPGA_NANDREGS_ADDRESS   0xffb8
+#define SOCFPGA_NANDDATA_ADDRESS   0xffb9
+#define SOCFPGA_UART0_ADDRESS  0xffc02000
+#define SOCFPGA_UART1_ADDRESS  0xffc02100
+#define SOCFPGA_I2C0_ADDRESS   0xffc02800
+#define SOCFPGA_I2C1_ADDRESS   0xffc02900
+#define SOCFPGA_I2C2_ADDRESS   0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS   0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS   0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS   0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS   0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS  0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS  0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd0
+#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00200
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00300
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00400
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00500
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd1
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS   0xffda
+#define SOCFPGA_DMASECURE_ADDRESS  0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS  0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS  0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS  0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS  0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS  0xffe0
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
-- 
1.7.7.4

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[U-Boot] [v3 17/30] arm: socfpga: arria10: update dwmac reset function to support Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.

Update the dwmac_deassert_reset function to support both GEN5 and Arria10
devices.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 .../arm/mach-socfpga/include/mach/system_manager.h |4 +---
 arch/arm/mach-socfpga/misc.c   |   14 ++
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 9ca889a..831ba4a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -133,9 +133,7 @@ struct socfpga_system_manager {
u32  usb0_l3master;
u32  usb1_l3master;
u32  emac_global;
-   u32  emac0;
-   u32  emac1;
-   u32  emac2;
+   u32  emac[3];
u32  _pad_0x50_0x5f[4];
u32  fpgaintf_en_global;
u32  fpgaintf_en_0;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c97caea..510aa1d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -21,7 +21,11 @@
 #include 
 #include 
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#else
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -95,15 +99,25 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
} else if (of_reset_id == EMAC1_RESET) {
physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
reset = SOCFPGA_RESET(EMAC1);
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+   } else if (of_reset_id == EMAC2_RESET) {
+   reset = SOCFPGA_RESET(EMAC2);
+#endif
} else {
printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
return;
}
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* configure to PHY interface select choosed */
clrsetbits_le32(_regs->emacgrp_ctrl,
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
phymode << physhift);
+#else
+   clrsetbits_le32(_regs->emac[of_reset_id - EMAC0_RESET],
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+   phymode);
+#endif
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
1.7.7.4

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[U-Boot] [v3 16/30] arm: socfpga: add reset manager defines for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.

[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 include/dt-bindings/reset/altr,rst-mgr-a10.h |  103 ++
 1 files changed, 103 insertions(+), 0 deletions(-)
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h 
b/include/dt-bindings/reset/altr,rst-mgr-a10.h
new file mode 100644
index 000..7619ca2
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET  2
+#define SCUPER_RESET   3
+
+/* PER0MODRST */
+#define EMAC0_RESET32
+#define EMAC1_RESET33
+#define EMAC2_RESET34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+#define QSPI_RESET 38
+#define SDMMC_RESET39
+#define EMAC0_OCP_RESET40
+#define EMAC1_OCP_RESET41
+#define EMAC2_OCP_RESET42
+#define USB0_OCP_RESET 43
+#define USB1_OCP_RESET 44
+#define NAND_OCP_RESET 45
+#define QSPI_OCP_RESET 46
+#define SDMMC_OCP_RESET47
+#define DMA_RESET  48
+#define SPIM0_RESET49
+#define SPIM1_RESET50
+#define SPIS0_RESET51
+#define SPIS1_RESET52
+#define DMA_OCP_RESET  53
+#define EMAC_PTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET   56
+#define DMAIF1_RESET   57
+#define DMAIF2_RESET   58
+#define DMAIF3_RESET   59
+#define DMAIF4_RESET   60
+#define DMAIF5_RESET   61
+#define DMAIF6_RESET   62
+#define DMAIF7_RESET   63
+
+/* PER1MODRST */
+#define L4WD0_RESET64
+#define L4WD1_RESET65
+#define L4SYSTIMER0_RESET  66
+#define L4SYSTIMER1_RESET  67
+#define SPTIMER0_RESET 68
+#define SPTIMER1_RESET 69
+/* 70-71 is reserved */
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is reserved */
+#define UART0_RESET80
+#define UART1_RESET81
+/* 82-87 is reserved */
+#define GPIO0_RESET88
+#define GPIO1_RESET89
+#define GPIO2_RESET90
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET   97
+#define FPGA2HPS_RESET 98
+#define F2SSDRAM0_RESET99
+#define F2SSDRAM1_RESET100
+#define F2SSDRAM2_RESET101
+#define DDRSCH_RESET   102
+
+/* SYSMODRST*/
+#define ROM_RESET  128
+#define OCRAM_RESET129
+/* 130 is reserved */
+#define FPGAMGR_RESET  131
+#define S2F_RESET  132
+#define SYSDBG_RESET   133
+#define OCRAM_OCP_RESET134
+
+/* COLDMODRST */
+#define CLKMGRCOLD_RESET   160
+/* 161-162 is reserved */
+#define S2FCOLD_RESET  163
+#define TIMESTAMPCOLD_RESET164
+#define TAPCOLD_RESET  165
+#define HMCCOLD_RESET  166
+#define IOMGRCOLD_RESET167
+
+/* NRSTMODRST */
+#define NRSTPINOE_RESET192
+
+/* DBGMODRST */
+#define DBG_RESET  224
+#endif
-- 
1.7.7.4

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[U-Boot] [v3 15/30] arm: socfpga: combine clrbits/setbits into a single clrsetbits

[Chee Tien Fong]

From: Tien Fong Chee 

There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/misc.c |9 +++--
 1 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 2645129..c97caea 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -100,13 +100,10 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
return;
}
 
-   /* Clearing emac0 PHY interface select to 0 */
-   clrbits_le32(_regs->emacgrp_ctrl,
-SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
-
/* configure to PHY interface select choosed */
-   setbits_le32(_regs->emacgrp_ctrl,
-phymode << physhift);
+   clrsetbits_le32(_regs->emacgrp_ctrl,
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
+   phymode << physhift);
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
1.7.7.4

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[U-Boot] [v3 14/30] arm: socfpga: arria10: remove board_init and s_init

[Chee Tien Fong]

From: Tien Fong Chee 

These functions are already in arch/arm/mach-socfpga/board.c

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 board/altera/arria10-socdk/socfpga.c |   17 -
 1 files changed, 0 insertions(+), 17 deletions(-)

diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
index abedc22..8516633 100644
--- a/board/altera/arria10-socdk/socfpga.c
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -5,20 +5,3 @@
  */
 
 #include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void)
-{
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-   /* Address of boot parameters for ATAG (if ATAG is used) */
-   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-   return 0;
-}
-- 
1.7.7.4

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[U-Boot] [v3 13/30] arm: socfpga: arria10 fpga does not have bridges mapped

[Chee Tien Fong]

From: Tien Fong Chee 

On the Arria10 device, the bridges are not mapped through the interconnect.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/fpga/socfpga.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..bfefafd 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -278,8 +278,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset(1);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Unmap the bridges from NIC-301 */
writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+#endif
 
/* Initialize the FPGA Manager */
status = fpgamgr_program_init();
-- 
1.7.7.4

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[U-Boot] [v3 11/30] arm: socfpga: wrap system manager functions for A5/C5 devices

[Chee Tien Fong]

From: Tien Fong Chee 

The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/system_manager.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 75a65f3..9e1c3fd 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -19,6 +19,7 @@ static struct socfpga_system_manager *sysmgr_regs =
  * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
  * CONFIG_SYSMGR_ISWGRP_HANDOFF.
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void populate_sysmgr_fpgaintf_module(void)
 {
uint32_t handoff_val = 0;
@@ -83,3 +84,4 @@ void sysmgr_config_warmrstcfgio(int enable)
clrbits_le32(_regs->romcodegrp_ctrl,
 SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
 }
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
-- 
1.7.7.4

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[U-Boot] [v3 10/30] arm: socfpga: arria10: add reset manager for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the defines for the reset manager and some basic reset functionality.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   65 
 arch/arm/mach-socfpga/reset_manager.c  |   24 +++-
 2 files changed, 88 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..6225118 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable);
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -28,6 +29,42 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
+#else
+struct socfpga_reset_manager {
+   u32 stat;
+   u32 ramstat;
+   u32 miscstat;
+   u32 ctrl;
+   u32 hdsken;
+   u32 hdskreq;
+   u32 hdskack;
+   u32 counts;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
+   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
+   u32 brg_mod_reset;
+   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
+   u32 coldmodrst;
+   u32 nrstmodrst;
+   u32 dbgmodrst;
+   u32 mpuwarmmask;
+   u32 per0warmmask;
+   u32 per1warmmask;
+   u32 brgwarmmask;
+   u32 syswarmmask;
+   u32 nrstwarmmask;
+   u32 l3warmmask;
+   u32 tststa;
+   u32 tstscratch;
+   u32 hdsktimeout;
+   u32 hmcintr;
+   u32 hmcintren;
+   u32 hmcintrens;
+   u32 hmcintrenr;
+   u32 hmcgpout;
+   u32 hmcgpin;
+};
+#endif
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
@@ -55,6 +92,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)\
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 /*
  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
  * 0 ... mpumodrst
@@ -75,6 +113,33 @@ struct socfpga_reset_manager {
 #define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 22)
 #define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
+#else
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
+#define RSTMGR_L4WD0   RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1   RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0   RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1   RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPIRSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH  RSTMGR_DEFINE(3, 6)
+#endif
 
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)   RSTMGR_##_name
diff --git a/arch/arm/mach-socfpga/reset_manager.c 
b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..d0ff6c4 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -18,7 +18,9 @@ static const struct socfpga_reset_manager *reset_manager_base 
=
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-/* Assert or de-assert SoCFPGA reset manager reset. */
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
 void socfpga_per_reset(u32 reset, int set)
 {
const void *reg;
@@ -46,13 +48,29 @@ void socfpga_per_reset(u32 reset, int set)
  * Assert reset on every peripheral but L4WD0.
  * Watchdog must be kept intact to prevent glitches
  * and/or hangs.
+ * For the Arria10, we disable all the peripherals except L4 watchdog0,
+ * L4 Timer 0, and ECC.
  */
 void 

[U-Boot] [v3 12/30] arm: socfpga: arria10: don't build GEN5 sdram for arria10

[Chee Tien Fong]

From: Tien Fong Chee 

The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/Kconfig  |2 ++
 drivers/ddr/Kconfig  |1 +
 drivers/ddr/altera/Kconfig   |6 ++
 include/configs/socfpga_common.h |5 -
 4 files changed, 9 insertions(+), 5 deletions(-)
 create mode 100644 drivers/ddr/Kconfig
 create mode 100644 drivers/ddr/altera/Kconfig

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 0e5d97d..3e6bbac 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
 
 source "drivers/crypto/Kconfig"
 
+source "drivers/ddr/Kconfig"
+
 source "drivers/demo/Kconfig"
 
 source "drivers/ddr/fsl/Kconfig"
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
new file mode 100644
index 000..b764add
--- /dev/null
+++ b/drivers/ddr/Kconfig
@@ -0,0 +1 @@
+source "drivers/ddr/altera/Kconfig"
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
new file mode 100644
index 000..9554da7
--- /dev/null
+++ b/drivers/ddr/altera/Kconfig
@@ -0,0 +1,6 @@
+config ALTERA_SDRAM
+   bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices"
+   default y if TARGET_SOCFPGA_GEN5
+   help
+ This is for building the SDRAM controller for the Arria5/Cyclone5
+ devices.
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 31f1338..bbbde1e 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -77,11 +77,6 @@
 #define CONFIG_SYS_PL310_BASE  SOCFPGA_MPUL2_ADDRESS
 
 /*
- * SDRAM controller
- */
-#define CONFIG_ALTERA_SDRAM
-
-/*
  * EPCS/EPCQx1 Serial Flash Controller
  */
 #ifdef CONFIG_ALTERA_SPI
-- 
1.7.7.4

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[U-Boot] [v3 09/30] arm: socfpga: add define for bootinfo bsel bit shift

[Chee Tien Fong]

From: Tien Fong Chee 

On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.

Suggested-by: Marek Vasut 
Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 .../arm/mach-socfpga/include/mach/system_manager.h |2 ++
 arch/arm/mach-socfpga/misc.c   |4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index e688c50..9ca889a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -203,8 +203,10 @@ struct socfpga_system_manager {
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 0
 #else
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 12
 #endif
 
 #define SYSMGR_SDMMC_DRVSEL_SHIFT  0
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c1e5969..2645129 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -261,12 +261,12 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+   const u32 bsel = (readl(_regs->bootinfo) >>
+ SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-   const u32 bsel = readl(_regs->bootinfo) & 0x7;
puts("CPU:   Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
 #else
-   const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7;
puts("CPU:   Altera SoCFPGA Arria 10\n");
 #endif
printf("BOOT:  %s\n", bsel_str[bsel].name);
-- 
1.7.7.4

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[U-Boot] [v3 08/30] arm: socfpga: arria10: add config option build for arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/Kconfig  |4 ++--
 arch/arm/mach-socfpga/Kconfig |   10 ++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0ed36cd..80c5992 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,9 +561,9 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
-   select SUPPORT_SPL
+   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
-   select SPL_OF_CONTROL
+   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
select DM
select DM_SPI_FLASH
select DM_SPI
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 6991af8..d9a5178 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -31,6 +31,9 @@ config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_ARRIA10
+   bool
+
 config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
@@ -50,6 +53,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+   bool "Altera SOCFPGA SoCDK (Arria 10)"
+   select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_DENX_MCVEVK
bool "DENX MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -86,6 +93,7 @@ endchoice
 
 config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -98,6 +106,7 @@ config SYS_BOARD
 
 config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -111,6 +120,7 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
-- 
1.7.7.4

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[U-Boot] [v3 07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig

[Chee Tien Fong]

From: Tien Fong Chee 

Add a defconfig file for Arria10, which does not include enabling SPL.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Acked-by: Marek Vasut 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 configs/socfpga_arria10_defconfig |   16 
 1 files changed, 16 insertions(+), 0 deletions(-)
 create mode 100644 configs/socfpga_arria10_defconfig

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
new file mode 100644
index 000..422261b
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_ARRIA10=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DM_MMC=y
-- 
1.7.7.4

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[U-Boot] [v3 06/30] arm: socfpga: arria10: add socfpga_arria10_socdk config

[Chee Tien Fong]

From: Tien Fong Chee 

Add config for the Arria10 SoC Development Kit.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Acked-by: Marek Vasut 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 include/configs/socfpga_arria10_socdk.h |   94 +++
 1 files changed, 94 insertions(+), 0 deletions(-)
 create mode 100644 include/configs/socfpga_arria10_socdk.h

diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 000..577f60f
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include 
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1_SIZE  0x200
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY   3
+#define CONFIG_BOOTFILE"zImage"
+#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND  "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR0x0100
+#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
+#define CONFIG_ENV_OFFSET  512/* just after the MBR */
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "verify=n\0" \
+   "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "bootimage=zImage\0" \
+   "fdt_addr=100\0" \
+   "fdtimage=socfpga.dtb\0" \
+   "fsloadcmd=ext2load\0" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "mmcroot=/dev/mmcblk0p2\0" \
+   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${mmcroot} rw rootwait;" \
+   "bootz ${loadaddr} - ${fdt_addr}\0" \
+   "mmcload=mmc rescan;" \
+   "load mmc 0:1 ${loadaddr} ${bootimage};" \
+   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+   "qspiroot=/dev/mtdblock0\0" \
+   "qspirootfstype=jffs2\0" \
+   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+   "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include 
+#endif /* __CONFIG_H */
-- 
1.7.7.4

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[U-Boot] [v3 04/30] arm: socfpga: arria10: add system manager defines

[Chee Tien Fong]

From: Tien Fong Chee 

Add system manager defines for Arria10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 .../arm/mach-socfpga/include/mach/system_manager.h |  122 
 1 files changed, 122 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index c45edea..e688c50 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -15,6 +15,7 @@ void sysmgr_config_warmrstcfgio(int enable);
 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_system_manager {
/* System Manager Module */
u32 siliconid1; /* 0x00 */
@@ -115,6 +116,77 @@ struct socfpga_system_manager {
u32 _pad_0x734;
u32 spim0usefpga;   /* 0x738 */
 };
+#else /* Arria10 System Manager */
+struct socfpga_system_manager {
+   u32  siliconid1;
+   u32  siliconid2;
+   u32  wddbg;
+   u32  bootinfo;
+   u32  mpu_ctrl_l2_ecc;
+   u32  _pad_0x14_0x1f[3];
+   u32  dma;
+   u32  dma_periph;
+   u32  sdmmcgrp_ctrl;
+   u32  sdmmc_l3master;
+   u32  nand_bootstrap;
+   u32  nand_l3master;
+   u32  usb0_l3master;
+   u32  usb1_l3master;
+   u32  emac_global;
+   u32  emac0;
+   u32  emac1;
+   u32  emac2;
+   u32  _pad_0x50_0x5f[4];
+   u32  fpgaintf_en_global;
+   u32  fpgaintf_en_0;
+   u32  fpgaintf_en_1;
+   u32  fpgaintf_en_2;
+   u32  fpgaintf_en_3;
+   u32  _pad_0x74_0x7f[3];
+   u32  noc_addr_remap_value;
+   u32  noc_addr_remap_set;
+   u32  noc_addr_remap_clear;
+   u32  _pad_0x8c_0x8f;
+   u32  ecc_intmask_value;
+   u32  ecc_intmask_set;
+   u32  ecc_intmask_clr;
+   u32  ecc_intstatus_serr;
+   u32  ecc_intstatus_derr;
+   u32  mpu_status_l2_ecc;
+   u32  mpu_clear_l2_ecc;
+   u32  mpu_status_l1_parity;
+   u32  mpu_clear_l1_parity;
+   u32  mpu_set_l1_parity;
+   u32  _pad_0xb8_0xbf[2];
+   u32  noc_timeout;
+   u32  noc_idlereq_set;
+   u32  noc_idlereq_clr;
+   u32  noc_idlereq_value;
+   u32  noc_idleack;
+   u32  noc_idlestatus;
+   u32  fpga2soc_ctrl;
+   u32  _pad_0xdc_0xff[9];
+   u32  tsmc_tsel_0;
+   u32  tsmc_tsel_1;
+   u32  tsmc_tsel_2;
+   u32  tsmc_tsel_3;
+   u32  _pad_0x110_0x200[60];
+   u32  romhw_ctrl;
+   u32  romcode_ctrl;
+   u32  romcode_cpu1startaddr;
+   u32  romcode_initswstate;
+   u32  romcode_initswlastld;
+   u32  _pad_0x214_0x217;
+   u32  warmram_enable;
+   u32  warmram_datastart;
+   u32  warmram_length;
+   u32  warmram_execution;
+   u32  warmram_crc;
+   u32  _pad_0x22c_0x22f;
+   u32  isw_handoff[8];
+   u32  romcode_bootromswstate[8];
+};
+#endif
 
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX(1 << 0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO(1 << 1)
@@ -146,4 +218,54 @@ struct socfpga_system_manager {
 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3
 
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V 0x0
+#define VOLTAGE_SEL_1P8V   0x1
+#define VOLTAGE_SEL_2P5V   0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE  0
+#define INPUT_BUF_1P8V 1
+#define INPUT_BUF_2P5V3V   2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE  0
+#define WK_PU_ENABLE   1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW 0
+#define PU_SLW_RT_FAST 1
+#define PU_SLW_RT_DEFAULT  PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW 0
+#define PD_SLW_RT_FAST 1
+#define PD_SLW_RT_DEFAULT  PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT0x10
+#define PD_DRV_STRG_DEFAULT0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB0
+#define PD_SLW_RT_LSB  5
+#define PU_DRV_STRG_LSB8
+#define PU_SLW_RT_LSB  13
+#define WK_PU_LSB  16
+#define INPUT_BUF_LSB  17
+#define BIAS_TRIM_LSB  19
+#define VOLTAGE_SEL_LSB0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x0001
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK   0x0010
+#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x0100
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK  0x0001
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK  0x0010
+#define 

[U-Boot] [v3 05/30] arm: socfpga: arria10: add misc functions for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/misc.c |   51 ++
 1 files changed, 51 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index dd6b53b..c1e5969 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -30,8 +31,15 @@ static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 static struct socfpga_reset_manager *reset_manager_base =
(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+#else
+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
+   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
+   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+#endif
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 
@@ -253,9 +261,14 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const u32 bsel = readl(_regs->bootinfo) & 0x7;
puts("CPU:   Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
+#else
+   const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7;
+   puts("CPU:   Altera SoCFPGA Arria 10\n");
+#endif
printf("BOOT:  %s\n", bsel_str[bsel].name);
return 0;
 }
@@ -338,6 +351,7 @@ int arch_cpu_init(void)
return 0;
 }
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 /*
  * Convert all NIC-301 AMBA slaves from secure to non-secure
  */
@@ -461,6 +475,43 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
 
return 0;
 }
+#else
+/*
++ * This function initializes security policies to be consistent across
++ * all logic units in the Arria 10.
++ *
++ * The idea is to set all security policies to be normal, nonsecure
++ * for all units.
++ */
+static void initialize_security_policies(void)
+{
+   /* Put OCRAM in non-secure */
+   writel(0x003f, _fw_ocram_base->region0);
+   writel(0x1, _fw_ocram_base->enable);
+
+   /* Put DDR in non-secure */
+   writel(0x, _fw_ddr_l3_base->hpsregion0addr);
+   writel(0x1, _fw_ddr_l3_base->enable);
+}
+
+int arch_early_init_r(void)
+{
+   initialize_security_policies();
+
+   /* Configure the L2 controller to make SDRAM start at 0 */
+   writel(0x1, >pl310_addr_filter_start);
+
+   /* assert reset to all except L4WD0 and L4TIMER0 */
+   socfpga_per_reset_all();
+
+   /* configuring the clock based on handoff */
+   /* TODO: Add call to cm_basic_init() */
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
+   return 0;
+}
+#endif
 
 U_BOOT_CMD(
bridge, 2, 1, do_bridge,
-- 
1.7.7.4

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[U-Boot] [v3 03/30] arm: socfpga: arria10: add board files for the Arria10 SoCDK

[Chee Tien Fong]

From: Tien Fong Chee 

Add minimal support for the Arria10 SoCDK.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 board/altera/arria10-socdk/Kconfig   |   18 ++
 board/altera/arria10-socdk/Makefile  |7 +++
 board/altera/arria10-socdk/socfpga.c |   24 
 3 files changed, 49 insertions(+), 0 deletions(-)
 create mode 100644 board/altera/arria10-socdk/Kconfig
 create mode 100644 board/altera/arria10-socdk/Makefile
 create mode 100644 board/altera/arria10-socdk/socfpga.c

diff --git a/board/altera/arria10-socdk/Kconfig 
b/board/altera/arria10-socdk/Kconfig
new file mode 100644
index 000..b80cc6d
--- /dev/null
+++ b/board/altera/arria10-socdk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+   default "armv7"
+
+config SYS_BOARD
+   default "socfpga_arria10"
+
+config SYS_VENDOR
+   default "altera"
+
+config SYS_SOC
+   default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+   default "socfpga_arria10"
+
+endif
diff --git a/board/altera/arria10-socdk/Makefile 
b/board/altera/arria10-socdk/Makefile
new file mode 100644
index 000..1d885ce
--- /dev/null
+++ b/board/altera/arria10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Altera Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
new file mode 100644
index 000..abedc22
--- /dev/null
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+   /* Address of boot parameters for ATAG (if ATAG is used) */
+   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+   return 0;
+}
-- 
1.7.7.4

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[U-Boot] [v3 01/30] arm: socfpga: arria10: add additional i2c nodes for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add remaining 3 I2C base addresses for the Arria10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Reviewed-by: Stefan Roese 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4..902c321 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -29,6 +29,9 @@
 #define SOCFPGA_MPUL2_ADDRESS  0xf000
 #define SOCFPGA_I2C0_ADDRESS   0xffc02200
 #define SOCFPGA_I2C1_ADDRESS   0xffc02300
+#define SOCFPGA_I2C2_ADDRESS   0xffc02400
+#define SOCFPGA_I2C3_ADDRESS   0xffc02500
+#define SOCFPGA_I2C4_ADDRESS   0xffc02600
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
-- 
1.7.7.4

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[U-Boot] [v3 02/30] arm: socfpga: arria10: add sdram defines for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the structures for the SDRAM controller on Arria10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/sdram_a10.h |  380 
 1 files changed, 380 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
new file mode 100644
index 000..0403531
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_SOCFPGA_SDRAM_A10_H_
+#define_SOCFPGA_SDRAM_A10_H_
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_ecc_hmc {
+   u32 ip_rev_id;
+   u32 _pad_0x4_0x7;
+   u32 ddrioctrl;
+   u32 ddrcalstat;
+   u32 mpr_0beat1;
+   u32 mpr_1beat1;
+   u32 mpr_2beat1;
+   u32 mpr_3beat1;
+   u32 mpr_4beat1;
+   u32 mpr_5beat1;
+   u32 mpr_6beat1;
+   u32 mpr_7beat1;
+   u32 mpr_8beat1;
+   u32 mpr_0beat2;
+   u32 mpr_1beat2;
+   u32 mpr_2beat2;
+   u32 mpr_3beat2;
+   u32 mpr_4beat2;
+   u32 mpr_5beat2;
+   u32 mpr_6beat2;
+   u32 mpr_7beat2;
+   u32 mpr_8beat2;
+   u32 _pad_0x58_0x5f[2];
+   u32 auto_precharge;
+   u32 _pad_0x64_0xff[39];
+   u32 eccctrl;
+   u32 eccctrl2;
+   u32 _pad_0x108_0x10f[2];
+   u32 errinten;
+   u32 errintens;
+   u32 errintenr;
+   u32 intmode;
+   u32 intstat;
+   u32 diaginttest;
+   u32 modstat;
+   u32 derraddra;
+   u32 serraddra;
+   u32 _pad_0x134_0x137;
+   u32 autowb_corraddr;
+   u32 serrcntreg;
+   u32 autowb_drop_cntreg;
+   u32 _pad_0x144_0x147;
+   u32 ecc_reg2wreccdatabus;
+   u32 ecc_rdeccdata2regbus;
+   u32 ecc_reg2rdeccdatabus;
+   u32 _pad_0x154_0x15f[3];
+   u32 ecc_diagon;
+   u32 ecc_decstat;
+   u32 _pad_0x168_0x16f[2];
+   u32 ecc_errgenaddr_0;
+   u32 ecc_errgenaddr_1;
+   u32 ecc_errgenaddr_2;
+   u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+   u32 ddr_t_main_scheduler_id_coreid;
+   u32 ddr_t_main_scheduler_id_revisionid;
+   u32 ddr_t_main_scheduler_ddrconf;
+   u32 ddr_t_main_scheduler_ddrtiming;
+   u32 ddr_t_main_scheduler_ddrmode;
+   u32 ddr_t_main_scheduler_readlatency;
+   u32 _pad_0x20_0x34[8];
+   u32 ddr_t_main_scheduler_activate;
+   u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 region0;
+   u32 region1;
+   u32 region2;
+   u32 region3;
+   u32 region4;
+   u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 _pad_0xc_0xf;
+   u32 mpuregion0addr;
+   u32 mpuregion1addr;
+   u32 mpuregion2addr;
+   u32 mpuregion3addr;
+   u32 fpga2sdram0region0addr;
+   u32 fpga2sdram0region1addr;
+   u32 fpga2sdram0region2addr;
+   u32 fpga2sdram0region3addr;
+   u32 fpga2sdram1region0addr;
+   u32 fpga2sdram1region1addr;
+   u32 fpga2sdram1region2addr;
+   u32 fpga2sdram1region3addr;
+   u32 fpga2sdram2region0addr;
+   u32 fpga2sdram2region1addr;
+   u32 fpga2sdram2region2addr;
+   u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 hpsregion0addr;
+   u32 hpsregion1addr;
+   u32 hpsregion2addr;
+   u32 hpsregion3addr;
+   u32 hpsregion4addr;
+   u32 hpsregion5addr;
+   u32 hpsregion6addr;
+   u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+   u32 dbgcfg0;
+   u32 dbgcfg1;
+   u32 dbgcfg2;
+   u32 dbgcfg3;
+   u32 dbgcfg4;
+   u32 dbgcfg5;
+   u32 dbgcfg6;
+   u32 reserve0;
+   u32 reserve1;
+   u32 reserve2;
+   u32 ctrlcfg0;
+   u32 ctrlcfg1;
+   u32 ctrlcfg2;
+   u32 ctrlcfg3;
+   u32 ctrlcfg4;
+   u32 ctrlcfg5;
+   u32 ctrlcfg6;
+   u32 ctrlcfg7;
+   u32 ctrlcfg8;
+   u32 ctrlcfg9;
+   u32 dramtiming0;
+   u32 dramodt0;
+   u32 dramodt1;
+   u32 sbcfg0;
+   u32 sbcfg1;
+   u32 sbcfg2;
+   u32 sbcfg3;
+   u32 sbcfg4;
+   u32 sbcfg5;
+   u32 sbcfg6;
+   u32 sbcfg7;
+   u32 caltiming0;
+   u32 caltiming1;
+   u32 caltiming2;
+   u32 caltiming3;
+   u32 

Re: [U-Boot] [PATCHv2 1/2] armv8: Enable CPUECTLR.SMPEN for coherency

[Masahiro Yamada]

Hi.


2017-01-06 18:41 GMT+09:00 Zhiqiang Hou :
> From: Mingkai Hu 
>
> For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
> set. The SMPEN bit should be set before enabling the data cache.
> If not enabled, the cache is not coherent with other cores and
> data corruption could occur.
>
> For A57/A72, SMPEN bit enables the processor to receive instruction
> cache and TLB maintenance operations broadcast from other processors
> in the cluster. This bit should be set before enabling the caches and
> MMU, or performing any cache and TLB maintenance operations.
>
> Signed-off-by: Mingkai Hu 
> Signed-off-by: Gong Qianyu 
> Signed-off-by: Mateusz Kulikowski 
> Signed-off-by: Hou Zhiqiang 
> ---
> V2:
>  - Revised the help information.
>
>  arch/arm/cpu/armv8/Kconfig | 18 ++
>  arch/arm/cpu/armv8/start.S | 11 +++
>  2 files changed, 29 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
> index 22dce88..472b2ba 100644
> --- a/arch/arm/cpu/armv8/Kconfig
> +++ b/arch/arm/cpu/armv8/Kconfig
> @@ -3,6 +3,24 @@ if ARM64
>  config ARMV8_MULTIENTRY
>  bool "Enable multiple CPUs to enter into U-Boot"
>
> +config ARMV8_SET_SMPEN
> +bool "Enable data coherency with other cores in cluster"
> +help
> + Say Y here if there is not any trust firmware to set
> + CPUECTLR_EL1.SMPEN bit before U-Boot.


I am a bit curious about this.
Are you planning to implement Trusted Firmware in the future?
It this option a temporary work-around until then?





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Re: [U-Boot] rockchip: rk3288: Possible regression in sdram setup

[Romain Perier]

Add Rockchip Engineers to Cc:


Le 06/01/2017 à 11:28, Romain Perier a écrit :

Hello,

I have a strange behaviour with the SPL on rk3288.

When I build u-boot-rockchip master for the rock2 (rock2_defconfig), I 
can easily start u-boot SPL and u-boot from an sdcard (the emmc boot 
partition is erased so my board starts in maskrom mode by default) 
without any issues.



Now, I load uboot SPL and uboot over usb:

- I power up the board

- I generate an image for the bootrom:

# tools/mkimage -n rk3288 -T rkimage -d spl/u-boot-spl-dtb.bin out

- I uploaded this image via usb to the board

# cat out | openssl rc4 -K 7c4e0304550509072d2c7b38170d1711 | 
../tools/rkflashtool/rkflashtool l


I get no output from the SPL. I have investigated and found that it is 
caused by sdram_rk3288.c: sdram_init(). More especially by the 
function phy_pctrl_reset(). I enabled EARLY_UART and added 2 
printascii() in this function. This functions hangs in the second for 
loop. I hacked this function locally, I reduce the number of 
iterations from 4 to 3 then I added 2 uart outputs to this function 
and "OH!":   it works, I get the following output:


pctrl_reset:for
pctrl_reset:end for
pctrl_reset:for
pctrl_reset:end for

U-Boot SPL 2016.11-08675-ga4ae4ddda3-dirty (Jan 06 2017 - 10:35:41)



Now, if I remove my printascii() functions completly, it's no longer 
working. Which suggests that it might have something to do with busy 
wait delays... (I could be wrong)


From the sdram setup point of view, I don't see a real difference 
between an SPL loaded from sdcard and an SPL loaded via usb.


Rockchip guys: Would you have an idea about the problem ?


Thanks,

Regards,

Romain

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[U-Boot] rockchip: rk3288: Possible regression in sdram setup

[Romain Perier]

Hello,

I have a strange behaviour with the SPL on rk3288.

When I build u-boot-rockchip master for the rock2 (rock2_defconfig), I 
can easily start u-boot SPL and u-boot from an sdcard (the emmc boot 
partition is erased so my board starts in maskrom mode by default) 
without any issues.



Now, I load uboot SPL and uboot over usb:

- I power up the board

- I generate an image for the bootrom:

# tools/mkimage -n rk3288 -T rkimage -d spl/u-boot-spl-dtb.bin out

- I uploaded this image via usb to the board

# cat out | openssl rc4 -K 7c4e0304550509072d2c7b38170d1711 | 
../tools/rkflashtool/rkflashtool l


I get no output from the SPL. I have investigated and found that it is 
caused by sdram_rk3288.c: sdram_init(). More especially by the function 
phy_pctrl_reset(). I enabled EARLY_UART and added 2 printascii() in this 
function. This functions hangs in the second for loop. I hacked this 
function locally, I reduce the number of iterations from 4 to 3 then I 
added 2 uart outputs to this function and "OH!":   it works, I get the 
following output:


pctrl_reset:for
pctrl_reset:end for
pctrl_reset:for
pctrl_reset:end for

U-Boot SPL 2016.11-08675-ga4ae4ddda3-dirty (Jan 06 2017 - 10:35:41)



Now, if I remove my printascii() functions completly, it's no longer 
working. Which suggests that it might have something to do with busy 
wait delays... (I could be wrong)


From the sdram setup point of view, I don't see a real difference 
between an SPL loaded from sdcard and an SPL loaded via usb.


Rockchip guys: Would you have an idea about the problem ?


Thanks,

Regards,

Romain

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Re: [U-Boot] [PATCH v4] BOARD: MCCMON6: Provide support for iMX6q based mccmon6 board

[Lukasz Majewski]

Hi Stefano,

Thank you for the review.

> Hi Lukasz,
> 
> On 02/01/2017 15:51, Lukasz Majewski wrote:
> > This patch provides u-boot support for Liebherr (LWN) mccmon6 board.
> > 
> > Signed-off-by: Lukasz Majewski 
> > ---
> > Changes for v4:
> > - Update board/liebherr/mccmon6/MAINTAINERS entry to quiet buildman
> > warnings
> > 
> > Changes for v3:
> > - Define CONFIG_SYS_UBOOT_START to load u-boot image from NOR to
> > correct address (so the SPL: NOR: Add
> > CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE define to enable whole image copy
> > from NOR can be dropped)
> > - Update author information
> > 
> > Changes for v2:
> > - Provide space after "quiet" console boot parameter to not pollute
> > next parameters
> > ---
> >  arch/arm/cpu/armv7/mx6/Kconfig   |   5 +
> >  board/liebherr/mccmon6/Kconfig   |  12 +
> >  board/liebherr/mccmon6/MAINTAINERS   |   7 +
> >  board/liebherr/mccmon6/Makefile  |   8 +
> >  board/liebherr/mccmon6/mccmon6.c | 490
> > +++
> > board/liebherr/mccmon6/mon6_imximage_nor.cfg |   9 +
> > board/liebherr/mccmon6/mon6_imximage_sd.cfg  |   9 +
> > board/liebherr/mccmon6/spl.c | 317
> > + configs/mccmon6_nor_defconfig|
> > 36 ++ configs/mccmon6_sd_defconfig |  37 ++
> > include/configs/mccmon6.h| 333
> > ++ 11 files changed, 1263 insertions(+) create mode
> > 100644 board/liebherr/mccmon6/Kconfig create mode 100644
> > board/liebherr/mccmon6/MAINTAINERS create mode 100644
> > board/liebherr/mccmon6/Makefile create mode 100644
> > board/liebherr/mccmon6/mccmon6.c create mode 100644
> > board/liebherr/mccmon6/mon6_imximage_nor.cfg create mode 100644
> > board/liebherr/mccmon6/mon6_imximage_sd.cfg create mode 100644
> > board/liebherr/mccmon6/spl.c create mode 100644
> > configs/mccmon6_nor_defconfig create mode 100644
> > configs/mccmon6_sd_defconfig create mode 100644
> > include/configs/mccmon6.h
> > 
> > diff --git a/arch/arm/cpu/armv7/mx6/Kconfig
> > b/arch/arm/cpu/armv7/mx6/Kconfig index c646966..9eddd7e 100644
> > --- a/arch/arm/cpu/armv7/mx6/Kconfig
> > +++ b/arch/arm/cpu/armv7/mx6/Kconfig
> > @@ -114,6 +114,10 @@ config TARGET_KOSAGI_NOVENA
> > bool "Kosagi Novena"
> > select SUPPORT_SPL
> >  
> > +config TARGET_MCCMON6
> > +   bool "mccmon6"
> > +   select SUPPORT_SPL
> > +
> >  config TARGET_MX6CUBOXI
> > bool "Solid-run mx6 boards"
> > select SUPPORT_SPL
> > @@ -327,6 +331,7 @@ source "board/phytec/pcm058/Kconfig"
> >  source "board/gateworks/gw_ventana/Kconfig"
> >  source "board/kosagi/novena/Kconfig"
> >  source "board/samtec/vining_2000/Kconfig"
> > +source "board/liebherr/mccmon6/Kconfig"
> >  source "board/seco/Kconfig"
> >  source "board/solidrun/mx6cuboxi/Kconfig"
> >  source "board/technexion/pico-imx6ul/Kconfig"
> > diff --git a/board/liebherr/mccmon6/Kconfig
> > b/board/liebherr/mccmon6/Kconfig new file mode 100644
> > index 000..4cc7fc2
> > --- /dev/null
> > +++ b/board/liebherr/mccmon6/Kconfig
> > @@ -0,0 +1,12 @@
> > +if TARGET_MCCMON6
> > +
> > +config SYS_BOARD
> > +   default "mccmon6"
> > +
> > +config SYS_VENDOR
> > +   default "liebherr"
> > +
> > +config SYS_CONFIG_NAME
> > +   default "mccmon6"
> > +
> > +endif
> > diff --git a/board/liebherr/mccmon6/MAINTAINERS
> > b/board/liebherr/mccmon6/MAINTAINERS new file mode 100644
> > index 000..c9c7183
> > --- /dev/null
> > +++ b/board/liebherr/mccmon6/MAINTAINERS
> > @@ -0,0 +1,7 @@
> > +MCCMON6 BOARD
> > +M: Lukasz Majewski 
> > +S: Maintained
> > +F: board/liebherr/mccmon6/
> > +F: include/configs/mccmon6.h
> > +F: configs/mccmon6_nor_defconfig
> > +F: configs/mccmon6_sd_defconfig
> > diff --git a/board/liebherr/mccmon6/Makefile
> > b/board/liebherr/mccmon6/Makefile new file mode 100644
> > index 000..e37baf8
> > --- /dev/null
> > +++ b/board/liebherr/mccmon6/Makefile
> > @@ -0,0 +1,8 @@
> > +#
> > +# (C) Copyright 2016-2017
> > +# Lukasz Majewski, DENX Software Engineering, lu...@denx.de
> > +#
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> > +
> > +obj-y  := mccmon6.o spl.o
> > diff --git a/board/liebherr/mccmon6/mccmon6.c
> > b/board/liebherr/mccmon6/mccmon6.c new file mode 100644
> > index 000..eb5eae4
> > --- /dev/null
> > +++ b/board/liebherr/mccmon6/mccmon6.c
> > @@ -0,0 +1,490 @@
> > +/*
> > + * Copyright (C) 2016-2017
> > + * Lukasz Majewski, DENX Software Engineering, lu...@denx.de
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP
> > |   \
> 

[U-Boot] [PATCHv2 1/2] armv8: Enable CPUECTLR.SMPEN for coherency

[Zhiqiang Hou]

From: Mingkai Hu 

For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.

For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.

Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
Signed-off-by: Mateusz Kulikowski 
Signed-off-by: Hou Zhiqiang 
---
V2:
 - Revised the help information.

 arch/arm/cpu/armv8/Kconfig | 18 ++
 arch/arm/cpu/armv8/start.S | 11 +++
 2 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 22dce88..472b2ba 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -3,6 +3,24 @@ if ARM64
 config ARMV8_MULTIENTRY
 bool "Enable multiple CPUs to enter into U-Boot"
 
+config ARMV8_SET_SMPEN
+bool "Enable data coherency with other cores in cluster"
+help
+ Say Y here if there is not any trust firmware to set
+ CPUECTLR_EL1.SMPEN bit before U-Boot.
+
+ For A53, it enables data coherency with other cores in the
+ cluster, and for A57/A72, it enables receiving of instruction
+ cache and TLB maintenance operations.
+ Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
+ for single core systems. Unfortunately write access to this
+ register may be controlled by EL3/EL2 firmware. To be more
+ precise, by default (if there is EL2/EL3 firmware running)
+ this register is RO for NS EL1.
+ This switch can be used to avoid writing to CPUECTLR_EL1,
+ it can be safely enabled when EL2/EL3 initialized SMPEN bit
+ or when CPU implementation doesn't include that register.
+
 config ARMV8_SPIN_TABLE
bool "Support spin-table enable method"
depends on ARMV8_MULTIENTRY && OF_LIBFDT
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4f5f6d8..5308702 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -86,6 +86,17 @@ save_boot_params_ret:
msr cpacr_el1, x0   /* Enable FP/SIMD */
 0:
 
+   /*
+* Enalbe SMPEN bit for coherency.
+* This register is not architectural but at the moment
+* this bit should be set for A53/A57/A72.
+*/
+#ifdef CONFIG_ARMV8_SET_SMPEN
+   mrs x0, S3_1_c15_c2_1   /* cpuactlr_el1 */
+   orr x0, x0, #0x40
+   msr S3_1_c15_c2_1, x0
+#endif
+
/* Apply ARM core specific erratas */
bl  apply_core_errata
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCHv2 2/2] ARMv8/fsl-layerscape: Enable data coherency between cores in cluster

[Zhiqiang Hou]

From: Hou Zhiqiang 

Signed-off-by: Hou Zhiqiang 
---
V2:
 - No change 

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index cc0dc88..f71a243 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,5 +1,6 @@
 config ARCH_LS1012A
bool
+   select ARMV8_SET_SMPEN
select FSL_LSCH2
select SYS_FSL_DDR_BE
select SYS_FSL_MMDC
@@ -7,6 +8,7 @@ config ARCH_LS1012A
 
 config ARCH_LS1043A
bool
+   select ARMV8_SET_SMPEN
select FSL_LSCH2
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
@@ -15,6 +17,7 @@ config ARCH_LS1043A
 
 config ARCH_LS1046A
bool
+   select ARMV8_SET_SMPEN
select FSL_LSCH2
select SYS_FSL_DDR_BE
select SYS_FSL_DDR4
@@ -24,6 +27,7 @@ config ARCH_LS1046A
 
 config ARCH_LS2080A
bool
+   select ARMV8_SET_SMPEN
select FSL_LSCH3
select SYS_FSL_DDR4
select SYS_FSL_DDR_LE
-- 
2.1.0.27.g96db324

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Re: [U-Boot] am335x based board nand boot crashes to ubi0 error

[matti kaasinen]

It seems that
http://www.denx.de/wiki/publish/DULG/DULG-enbw_cmc.html#Section_9.1.5.2.
Chapter 9.1.5.3.4. Installing UBI images (if no UBI Volumes exist): is
mentioning a problem like this. Figures in error message are swapped,
though. Anyhow, the root problem could be the fact that my ubiformat
statement misses '-s' switch. I'll try that on Monday.

2017-01-05 16:16 GMT+02:00 matti kaasinen :

> Hi!
> I would need help related to nand boot with am335x based board. Board
> boots from mmc (sd card), but not from nand flash.
> I have been using yocto/poky build system with meta-ti layer that brings
> up u-boot-ti-staging. Current u-boot version is 2016.05 and
> linux-ti-staging-rt-4.4.
>
> I have used am335x_evm config (include/configs/am335x_evm.h) that I have
> made minor modifications to suit it to my board. Most of the modifications
> are made to board/ti/am335x/board.c and mux.c to adapt to different
> memories and pin mappings and lack of card id eeprom.
>
> This story is "follow up" to http://lists.denx.de/
> pipermail/u-boot/2017-January/277168.html. So, I2C was initialized
> somehow when booting from mmc, but not when booting from nand.
>
> "Follow up" part:
> Board did still not start booting kernel even though I2C init problem was
> fixed.
>
> The reason was that boot_targets variable has been assigned with
> mmc0 legacy_mmc0 mmc1 legacy_mmc1 nand0 pxe dhcp
> when main u-boot is brought up. These values are iterated when
> distro_bootcmd is executed.
> distro_bootcmd=for target in ${boot_targets}; do run bootcmd_${target};
> done
> I made minor modification to distro_bootcmd:
> distro_bootcmd=for target in ${boot_targets}; do echo "=== ${target}
> ===" ; run bootcmd_${target}; done
> Please find the distro_bootcmd running results below:
> => run distro_bootcmd
> === mmc0 ===
> Card did not respond to voltage select!
> === legacy_mmc0 ===
> Card did not respond to voltage select!
> Card did not respond to voltage select!
> === mmc1 ===
> data abort
> pc : [<8ff70fa0>]  lr : [<8ff701e9>]
> reloc pc : [<8081dfa0>]lr : [<8081d1e9>]
> sp : 8ef286f0  ip : 8ff5891d fp : 0003
> r10: 8ffb3b18  r9 : 8ef32ed8 r8 : 8ef41b10
> r7 : 8ff584bd  r6 : 8ef39478 r5 : 8ef39500  r4 : 4781
> r3 : 8ff70f91  r2 : 00014892 r1 :   r0 : 8ef39500
> Flags: nZCv  IRQs off  FIQs on  Mode SVC_32
> Resetting CPU ...
>
> So, MMC1 was troublemaker this time.
> I removed mmc1 from that command - I do not have mmc1 on my board.
> => setenv boot_targets ' mmc0 legacy_mmc0  nand0 '
>
> Please find modified command results below:
> => run distro_bootcmd
> === mmc0 ===
> Card did not respond to voltage select!
> === legacy_mmc0 ===
> Card did not respond to voltage select!
> Card did not respond to voltage select!
> === nand0 ===
> ## Error: "bootcmd_nand0" not defined
>
> NOTE!! Is this a bug in u-boot-ti? There is no bootcmd_nand0 in u-boot
> memory at this time. However, there is bootcmd_nand. So, I changed nand0 to
> nand
> => setenv boot_targets ' mmc0 legacy_mmc0  nand'
> => run distro_bootcmd
> === mmc0 ===
> Card did not respond to voltage select!
> === legacy_mmc0 ===
> Card did not respond to voltage select!
> Card did not respond to voltage select!
> === nand ===
> Booting from nand ...
>
> NAND read: device 0 offset 0x8, size 0x4
>  262144 bytes read: OK
>
> NAND read: device 0 offset 0x20, size 0x80
>  8388608 bytes read: OK
> Kernel image @ 0x8200 [ 0x00 - 0x2c4fd8 ]
> ## Flattened Device Tree blob at 8800
>Booting using the fdt blob at 0x8800
>Loading Device Tree to 8ef1b000, end 8ef27614 ... OK
>
> Starting kernel ...
>
> [0.00] Booting Linux on physical CPU 0x0
> [0.00] Initializing cgroup subsys cpu
>
> ... lots of listing and then ..
> [1.172458] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
> [1.179257] nand: Micron MT29F2G08ABAEAWP
> [1.183469] nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048,
> OOB size: 64
> [1.191491] nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme
> [1.197164] 10 ofpart partitions found on MTD device 800.nand
> [1.203607] Creating 10 MTD partitions on "800.nand":
> [1.209285] 0x-0x0002 : "NAND.SPL"
> [1.216261] 0x0002-0x0004 : "NAND.SPL.backup1"
> [1.223834] 0x0004-0x0006 : "NAND.SPL.backup2"
> [1.231275] 0x0006-0x0008 : "NAND.SPL.backup3"
> [1.238794] 0x0008-0x000c : "NAND.u-boot-spl-os"
> [1.246571] 0x000c-0x001c : "NAND.u-boot"
> [1.254316] 0x001c-0x001e : "NAND.u-boot-env"
> [1.261612] 0x001e-0x0020 : "NAND.u-boot-env.backup1"
> [1.269653] 0x0020-0x00a0 : "NAND.kernel"
> [1.283112] 0x00a0-0x1000 : "NAND.file-system"
> [1.520856]