Re: [U-Boot] rockchip: rk3288: Possible regression in sdram setup

[Kever Yang]

Hi Romain,

Thanks for your report and debug.

On 01/06/2017 06:52 PM, Romain Perier wrote:

Add Rockchip Engineers to Cc:


Le 06/01/2017 à 11:28, Romain Perier a écrit :

Hello,

I have a strange behaviour with the SPL on rk3288.

When I build u-boot-rockchip master for the rock2 (rock2_defconfig), 
I can easily start u-boot SPL and u-boot from an sdcard (the emmc 
boot partition is erased so my board starts in maskrom mode by 
default) without any issues.



Now, I load uboot SPL and uboot over usb:

- I power up the board

- I generate an image for the bootrom:

# tools/mkimage -n rk3288 -T rkimage -d spl/u-boot-spl-dtb.bin out

- I uploaded this image via usb to the board

# cat out | openssl rc4 -K 7c4e0304550509072d2c7b38170d1711 | 
../tools/rkflashtool/rkflashtool l


I get no output from the SPL. I have investigated and found that it 
is caused by sdram_rk3288.c: sdram_init(). More especially by the 
function phy_pctrl_reset(). I enabled EARLY_UART and added 2 
printascii() in this function. This functions hangs in the second for 
loop. I hacked this function locally, I reduce the number of 
iterations from 4 to 3 then I added 2 uart outputs to this function 
and "OH!":   it works, I get the following output:


pctrl_reset:for
pctrl_reset:end for
pctrl_reset:for
pctrl_reset:end for

U-Boot SPL 2016.11-08675-ga4ae4ddda3-dirty (Jan 06 2017 - 10:35:41)



Now, if I remove my printascii() functions completly, it's no longer 
working. Which suggests that it might have something to do with busy 
wait delays... (I could be wrong)


From the sdram setup point of view, I don't see a real difference 
between an SPL loaded from sdcard and an SPL loaded via usb.


Rockchip guys: Would you have an idea about the problem ?



SPL load from sdcard/emmc and loaded via usb, one difference may be cpu 
frequency.


I agree that the udelay() may not correct, could you help to do:
- delay 1 S or more with udelay(), then we can see if it's correct, I 
don't know how the udelay is implement on rk3288,

if it's using ARM generic timer, then it's related to cpu frequency;
- using rockchip_udelay() instead of udelay(), this interface is using 
rktimer, it should be correct.


Thanks,
- Kever


Thanks,

Regards,

Romain

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Re: [U-Boot] [linux-sunxi] Re: [PATCH 1/2] sunxi: power: add AXP803 support

[Maxime Ripard]

On Fri, Jan 06, 2017 at 06:47:30AM +0800, Icenowy Zheng wrote:
> > > +++ b/drivers/power/axp803.c 
> > > @@ -0,0 +1,255 @@ 
> > > +/* 
> > > + * AXP803 driver based on AXP818 driver 
> > > + * 
> > > + * Based on axp818.c 
> > > + * (C) Copyright 2015 Vishnu Patekar  
> > > + * 
> > > + * Based on axp221.c 
> > > + * (C) Copyright 2014 Hans de Goede  
> > > + * (C) Copyright 2013 Oliver Schinagl  
> > > + * 
> > > + * SPDX-License-Identifier: GPL-2.0+ 
> > > + */ 
> > > + 
> > > +#include  
> > > +#include  
> > > +#include  
> > > +#include  
> > > +#include  
> > > + 
> > > +static u8 axp803_mvolt_to_cfg(int mvolt, int min, int max, int div) 
> > > +{ 
> > > + if (mvolt < min) 
> > > + mvolt = min; 
> > > + else if (mvolt > max) 
> > > + mvolt = max; 
> > > + 
> > > + return  (mvolt - min) / div; 
> > > +} 
> > > + 
> > > +int axp_set_dcdc1(unsigned int mvolt) 
> > > +{ 
> > > + int ret; 
> > > + u8 cfg = axp803_mvolt_to_cfg(mvolt, 1600, 3400, 100); 
> > > + 
> > > + if (mvolt == 0) 
> > > + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1, 
> > > + AXP803_OUTPUT_CTRL1_DCDC1_EN); 
> > > + 
> > > + ret = pmic_bus_write(AXP803_DCDC1_CTRL, cfg); 
> > > + if (ret) 
> > > + return ret; 
> > > + 
> > > + return pmic_bus_setbits(AXP803_OUTPUT_CTRL1, 
> > > + AXP803_OUTPUT_CTRL1_DCDC1_EN); 
> > > +} 
> > > + 
> > > +int axp_set_dcdc2(unsigned int mvolt) 
> > > +{ 
> > > + int ret; 
> > > + u8 cfg; 
> > > + 
> > > + if (mvolt >= 1220) 
> > > + cfg = 70 + axp803_mvolt_to_cfg(mvolt, 1220, 1300, 20); 
> > > + else 
> > > + cfg = axp803_mvolt_to_cfg(mvolt, 500, 1200, 10); 
> > > + 
> > > + if (mvolt == 0) 
> > > + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1, 
> > > + AXP803_OUTPUT_CTRL1_DCDC2_EN); 
> > > + 
> > > + ret = pmic_bus_write(AXP803_DCDC2_CTRL, cfg); 
> > > + if (ret) 
> > > + return ret; 
> > > + 
> > > + return pmic_bus_setbits(AXP803_OUTPUT_CTRL1, 
> > > + AXP803_OUTPUT_CTRL1_DCDC2_EN); 
> > > +} 
> > > + 
> > > +int axp_set_dcdc3(unsigned int mvolt) 
> > > +{ 
> > > + int ret; 
> > > + u8 cfg; 
> > > + 
> > > + if (mvolt >= 1220) 
> > > + cfg = 70 + axp803_mvolt_to_cfg(mvolt, 1220, 1300, 20); 
> > > + else 
> > > + cfg = axp803_mvolt_to_cfg(mvolt, 500, 1200, 10); 
> > > + 
> > > + if (mvolt == 0) 
> > > + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1, 
> > > + AXP803_OUTPUT_CTRL1_DCDC3_EN); 
> > > + 
> > > + ret = pmic_bus_write(AXP803_DCDC3_CTRL, cfg); 
> > > + if (ret) 
> > > + return ret; 
> > > + 
> > > + return pmic_bus_setbits(AXP803_OUTPUT_CTRL1, 
> > > + AXP803_OUTPUT_CTRL1_DCDC3_EN); 
> > > +} 
> > > + 
> > > +int axp_set_dcdc5(unsigned int mvolt) 
> > > +{ 
> > > + int ret; 
> > > + u8 cfg; 
> > > + 
> > > + if (mvolt >= 1140) 
> > > + cfg = 32 + axp803_mvolt_to_cfg(mvolt, 1140, 1840, 20); 
> > > + else 
> > > + cfg = axp803_mvolt_to_cfg(mvolt, 800, 1120, 10); 
> > > + 
> > > + if (mvolt == 0) 
> > > + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1, 
> > > + AXP803_OUTPUT_CTRL1_DCDC5_EN); 
> > > + 
> > > + ret = pmic_bus_write(AXP803_DCDC5_CTRL, cfg); 
> > > + if (ret) 
> > > + return ret; 
> > > + 
> > > + return pmic_bus_setbits(AXP803_OUTPUT_CTRL1, 
> > > + AXP803_OUTPUT_CTRL1_DCDC5_EN); 
> > > +} 
> > > + 
> > > +int axp_set_aldo(int aldo_num, unsigned int mvolt) 
> > > +{ 
> > > + int ret; 
> > > + u8 cfg; 
> > > + 
> > > + if (aldo_num < 1 || aldo_num > 3) 
> > > + return -EINVAL; 
> > > + 
> > > + if (mvolt == 0) 
> > > + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL3, 
> > > + AXP803_OUTPUT_CTRL3_ALDO1_EN << (aldo_num - 1)); 
> > > + 
> > > + cfg = axp803_mvolt_to_cfg(mvolt, 700, 3300, 100); 
> > > + ret = pmic_bus_write(AXP803_ALDO1_CTRL + (aldo_num - 1), cfg); 
> > > + if (ret) 
> > > + return ret; 
> > > + 
> > > + return pmic_bus_setbits(AXP803_OUTPUT_CTRL3, 
> > > + AXP803_OUTPUT_CTRL3_ALDO1_EN << (aldo_num - 1)); 
> > > +} 
> > > + 
> > > +/* TODO: re-work other AXP drivers to consolidate ALDO functions. */ 
> > > +int axp_set_aldo1(unsigned int mvolt) 
> > > +{ 
> > > + return axp_set_aldo(1, mvolt); 
> > > +} 
> > > + 
> > > +int axp_set_aldo2(unsigned int mvolt) 
> > > +{ 
> > > + return axp_set_aldo(2, mvolt); 
> > > +} 
> > > + 
> > > +int axp_set_aldo3(unsigned int mvolt) 
> > > +{ 
> > > + return axp_set_aldo(3, mvolt); 
> > > +} 
> > > + 
> > > +int axp_set_dldo(int dldo_num, unsigned int mvolt) 
> > > +{ 
> > > + int ret; 
> > > + u8 cfg; 
> > > + 
> > > + if (dldo_num < 1 || dldo_num > 4) 
> > > + return -EINVAL; 
> > > + 
> > > + if (mvolt == 0) 
> > > + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL2, 
> > > + AXP803_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1)); 
> > > + 
> > > + cfg = axp803_mvolt_to_cfg(mvolt, 700, 3300, 100); 
> > > + if (dldo_num == 2 && mvolt > 3300) 
> > > + cfg += 1 + axp803_mvolt_to_cfg(mvolt, 3400, 4200, 200); 
> > > + ret = pmic_bus_write(AXP803_DLDO1_CTRL + (dldo_num - 1), cfg); 
> > > + if (ret) 
> > > + return ret; 
> > > + 
> > > + return pmic_bus_setbits(AXP803_OUTPUT_CTRL2, 
> > > + 

[U-Boot] [PATCH V3 1/7] ARM: dts: exynos4: use the node's name for i2c

[Jaehoon Chung]

Use the node's name for i2c.

Signed-off-by: Jaehoon Chung 
---
 arch/arm/dts/exynos4.dtsi | 27 +++
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi
index 7de227c..a5a00c8 100644
--- a/arch/arm/dts/exynos4.dtsi
+++ b/arch/arm/dts/exynos4.dtsi
@@ -10,6 +10,17 @@
 #include "skeleton.dtsi"
 
 / {
+   aliases {
+   i2c0 = _0;
+   i2c1 = _1;
+   i2c2 = _2;
+   i2c3 = _3;
+   i2c4 = _4;
+   i2c5 = _5;
+   i2c6 = _6;
+   i2c7 = _7;
+   };
+
combiner: interrupt-controller@1044 {
compatible = "samsung,exynos4210-combiner";
#interrupt-cells = <2>;
@@ -47,7 +58,7 @@
id = <4>;
};
 
-   i2c@1386 {
+   i2c_0: i2c@1386 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -55,7 +66,7 @@
interrupts = <0 56 0>;
};
 
-   i2c@1387 {
+   i2c_1: i2c@1387 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -63,7 +74,7 @@
interrupts = <1 57 0>;
};
 
-   i2c@1388 {
+   i2c_2: i2c@1388 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -71,7 +82,7 @@
interrupts = <2 58 0>;
};
 
-   i2c@1389 {
+   i2c_3: i2c@1389 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -79,7 +90,7 @@
interrupts = <3 59 0>;
};
 
-   i2c@138a {
+   i2c_4: i2c@138a {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -87,7 +98,7 @@
interrupts = <4 60 0>;
};
 
-   i2c@138b {
+   i2c_5: i2c@138b {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -95,7 +106,7 @@
interrupts = <5 61 0>;
};
 
-   i2c@138c {
+   i2c_6: i2c@138c {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -103,7 +114,7 @@
interrupts = <6 62 0>;
};
 
-   i2c@138d {
+   i2c_7: i2c@138d {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
-- 
2.10.2

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[U-Boot] [PATCH V3 7/7] board: samsung: universal_c210: remove the codes relevant to soft_i2c

[Jaehoon Chung]

Removes the codes of soft_i2c.
There is no usasge for universal_c210, also didn't define
CONFIG_SOFT_I2C_GPIO_SCL.
This code seems a dead code.

Signed-off-by: Jaehoon Chung 
---
 board/samsung/universal_c210/universal.c | 11 ---
 1 file changed, 11 deletions(-)

diff --git a/board/samsung/universal_c210/universal.c 
b/board/samsung/universal_c210/universal.c
index 0645843..feb8a34 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -355,9 +355,6 @@ void exynos_enable_ldo(unsigned int onoff)
 
 int exynos_init(void)
 {
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
-   char buf[16];
-#endif
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
 
switch (get_hwrev()) {
@@ -382,14 +379,6 @@ int exynos_init(void)
break;
}
 
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
-   /* Request soft I2C gpios */
-   strcpy(buf, "soft_i2c_scl");
-   gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf);
-
-   strcpy(buf, "soft_i2c_sda");
-   gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf);
-#endif
check_hw_revision();
printf("HW Revision:\t0x%x\n", board_rev);
 
-- 
2.10.2

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[U-Boot] [PATCH V3 6/7] i2c: Kconfig: Add SYS_I2C_S3C24X0 entry

[Jaehoon Chung]

Adding Kconfig for SYS_I2C_S3C24X0.

Signed-off-by: Jaehoon Chung 
---
 drivers/i2c/Kconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 051f911..71cc173 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -155,6 +155,11 @@ config SYS_I2C_SANDBOX
};
};
 
+config SYS_I2C_S3C24X0
+   bool "Samsung I2C driver"
+   depends on ARCH_EXYNOS4 && DM_I2C
+   help
+ Support for Samsung I2C controller as Samsung SoCs.
 
 config SYS_I2C_UNIPHIER
bool "UniPhier I2C driver"
-- 
2.10.2

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[U-Boot] [PATCH V3 4/7] board: samsung: universal_210: use the driver model for max8998

[Jaehoon Chung]

Revmoe the "ifndef CONFIG_DM_I2C".
Intead, use the driver model for max8998.

Signed-off-by: Jaehoon Chung 
---
 board/samsung/universal_c210/universal.c | 169 +--
 1 file changed, 94 insertions(+), 75 deletions(-)

diff --git a/board/samsung/universal_c210/universal.c 
b/board/samsung/universal_c210/universal.c
index c3946ee..0645843 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -27,33 +27,21 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 unsigned int board_rev;
+static int init_pmic_lcd(void);
 
 u32 get_board_rev(void)
 {
return board_rev;
 }
 
-static int get_hwrev(void)
+int exynos_power_init(void)
 {
-   return board_rev & 0xFF;
+   return init_pmic_lcd();
 }
 
-int exynos_power_init(void)
+static int get_hwrev(void)
 {
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
-   int ret;
-
-   /*
-* For PMIC the I2C bus is named as I2C5, but it is connected
-* to logical I2C adapter 0
-*/
-   ret = pmic_init(I2C_0);
-   if (ret)
-   return ret;
-
-   init_pmic_lcd();
-#endif
-   return 0;
+   return board_rev & 0xFF;
 }
 
 static unsigned short get_adc_value(int channel)
@@ -83,23 +71,29 @@ static unsigned short get_adc_value(int channel)
 
 static int adc_power_control(int on)
 {
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
+   struct udevice *dev;
int ret;
-   struct pmic *p = pmic_get("MAX8998_PMIC");
-   if (!p)
-   return -ENODEV;
+   u8 reg;
 
-   if (pmic_probe(p))
-   return -1;
+   ret = pmic_get("max8998-pmic", );
+   if (ret) {
+   puts("Failed to get MAX8998!\n");
+   return ret;
+   }
 
-   ret = pmic_set_output(p,
- MAX8998_REG_ONOFF1,
- MAX8998_LDO4, !!on);
+   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+   if (on)
+   reg |= MAX8998_LDO4;
+   else
+   reg &= ~MAX8998_LDO4;
+
+   ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
+   if (ret) {
+   puts("MAX8998 LDO setting error\n");
+   return -EINVAL;
+   }
 
-   return ret;
-#else
return 0;
-#endif
 }
 
 static unsigned int get_hw_revision(void)
@@ -147,39 +141,50 @@ static void check_hw_revision(void)
 #ifdef CONFIG_USB_GADGET
 static int s5pc210_phy_control(int on)
 {
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
-   int ret = 0;
-   struct pmic *p = pmic_get("MAX8998_PMIC");
-   if (!p)
-   return -ENODEV;
+   struct udevice *dev;
+   int ret;
+   u8 reg;
 
-   if (pmic_probe(p))
-   return -1;
+   ret = pmic_get("max8998-pmic", );
+   if (ret) {
+   puts("Failed to get MAX8998!\n");
+   return ret;
+   }
 
if (on) {
-   ret |= pmic_set_output(p,
-  MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
-  MAX8998_SAFEOUT1, LDO_ON);
-   ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
- MAX8998_LDO3, LDO_ON);
-   ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
- MAX8998_LDO8, LDO_ON);
+   reg = pmic_reg_read(dev, MAX8998_REG_BUCK_ACTIVE_DISCHARGE3);
+   reg |= MAX8998_SAFEOUT1;
+   ret |= pmic_reg_write(dev,
+   MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, reg);
+
+   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+   reg |= MAX8998_LDO3;
+   ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
+
+   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+   reg |= MAX8998_LDO8;
+   ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
 
} else {
-   ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
- MAX8998_LDO8, LDO_OFF);
-   ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
- MAX8998_LDO3, LDO_OFF);
-   ret |= pmic_set_output(p,
-  MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
-  MAX8998_SAFEOUT1, LDO_OFF);
+   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+   reg &= ~MAX8998_LDO8;
+   ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
+
+   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+   reg &= ~MAX8998_LDO3;
+   ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
+
+   reg = pmic_reg_read(dev, MAX8998_REG_BUCK_ACTIVE_DISCHARGE3);
+   reg &= ~MAX8998_SAFEOUT1;
+   ret |= pmic_reg_write(dev,
+   

[U-Boot] [PATCH V3 2/7] ARM: dts: exnyos4210-universl_c210: add i2c_5 and pmic nodes

[Jaehoon Chung]

Add the i2c_5 node and pmic as its child node.

Signed-off-by: Jaehoon Chung 
---
 arch/arm/dts/exynos4210-universal_c210.dts | 164 +
 1 file changed, 164 insertions(+)

diff --git a/arch/arm/dts/exynos4210-universal_c210.dts 
b/arch/arm/dts/exynos4210-universal_c210.dts
index 8cac7dd..5763627 100644
--- a/arch/arm/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -94,3 +94,167 @@
samsung,rgb-mode = <0>;
};
 };
+
+_5 {
+   clock-frequency = <10>;
+   status = "okay";
+
+   max8998-pmic@66 {
+   compatible = "maxim,max8998";
+   reg = <0x66 0 0>;
+   voltage-regulators {
+   ldo2_reg: LDO2 {
+   regulator-name = "VALIVE_1.2V";
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   regulator-always-on;
+   };
+
+   ldo3_reg: LDO3 {
+   regulator-name = "VUSB+MIPI_1.1V";
+   regulator-min-microvolt = <110>;
+   regulator-max-microvolt = <110>;
+   regulator-always-on;
+   };
+
+   ldo4_reg: LDO4 {
+   regulator-name = "VADC_3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   ldo5_reg: LDO5 {
+   regulator-name = "VTF_2.8V";
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   };
+
+   ldo6_reg: LDO6 {
+   regulator-name = "LDO6";
+   regulator-min-microvolt = <200>;
+   regulator-max-microvolt = <200>;
+   };
+
+   ldo7_reg: LDO7 {
+   regulator-name = "VLCD+VMIPI_1.8V";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   };
+
+   ldo8_reg: LDO8 {
+   regulator-name = "VUSB+VDAC_3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   };
+
+   ldo9_reg: LDO9 {
+   regulator-name = "VCC_2.8V";
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   regulator-always-on;
+   };
+
+   ldo10_reg: LDO10 {
+   regulator-name = "VPLL_1.1V";
+   regulator-min-microvolt = <110>;
+   regulator-max-microvolt = <110>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   ldo11_reg: LDO11 {
+   regulator-name = "CAM_AF_3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   ldo12_reg: LDO12 {
+   regulator-name = "PS_2.8V";
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   };
+
+   ldo13_reg: LDO13 {
+   regulator-name = "VHIC_1.2V";
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   };
+
+   ldo14_reg: LDO14 {
+   regulator-name = "CAM_I_HOST_1.8V";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   };
+
+   ldo15_reg: LDO15 {
+   regulator-name = "CAM_S_DIG+FM33_CORE_1.2V";
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   };
+
+   ldo16_reg: LDO16 {
+   regulator-name = "CAM_S_ANA_2.8V";
+   

[U-Boot] [PATCH V3 0/7] dm: universal_c210: support the DM_PMIC

[Jaehoon Chung]

This patchset is for supporting pmic driver-mode on universal_c210 board.
It's using i2c-s3c24x0.c file. (Fixes some complier error issue.)

Remove the soft_i2c codes in universal.c.
It seems a deadcode because of no usage.
Before time, it had used the soft-i2c as gpio_request(), not using s3c24x0-i2c.c
(gpb6/7 were used the sda/scl.)
There is no reason not to use the s3c24x0-i2c.c

*dm tree
 i2c [ + ]|-- i2c@138b
 pmic[ + ]|   `-- max8998-pmic@66

*dm uclass
uclass 20: i2c
-   i2c@1386 @ 5ae652d8, seq -1, (req 0)
-   i2c@1387 @ 5ae65330, seq -1, (req 1)
-   i2c@1388 @ 5ae65388, seq -1, (req 2)
-   i2c@1389 @ 5ae653e0, seq -1, (req 3)
-   i2c@138a @ 5ae65438, seq -1, (req 4)
- * i2c@138b @ 5ae65490, seq 5, (req 5)
-   i2c@138c @ 5ae65570, seq -1, (req 6)
-   i2c@138d @ 5ae655c8, seq -1, (req 7)
 i2c [ + ]|-- i2c@138b
 pmic[ + ]|   `-- max8998-pmic@66

*After using pmic command.
Universal # pmic list
| Name| Parent name | Parent uclass @ seq
| max8998-pmic@66 | i2c@138b| i2c @ 5

Changelog on V3:
- Changes the patches sequence for fixing the buildman error
- Adds the commit message in more details.

Changelog on V2:
- Changes to "depends on ARCH_EXYNOS4" in Kconfig (fixes buildman error.)

Jaehoon Chung (7):
  ARM: dts: exynos4: use the node's name for i2c
  ARM: dts: exnyos4210-universl_c210: add i2c_5 and pmic nodes
  configs: s5pc210_universal: enable the DM_PMIC and MAX8998
  board: samsung: universal_210: use the driver model for max8998
  i2c: s3c24x0: fix the compiler error for exynos4
  i2c: Kconfig: Add SYS_I2C_S3C24X0 entry
  board: samsung: universal_c210: remove the codes relevant to soft_i2c

 arch/arm/dts/exynos4.dtsi  |  27 +++--
 arch/arm/dts/exynos4210-universal_c210.dts | 164 ++
 board/samsung/universal_c210/universal.c   | 180 +++--
 configs/s5pc210_universal_defconfig|   3 +
 drivers/i2c/Kconfig|   5 +
 drivers/i2c/s3c24x0_i2c.c  |   8 +-
 6 files changed, 292 insertions(+), 95 deletions(-)

-- 
2.10.2

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[U-Boot] [PATCH V3 5/7] i2c: s3c24x0: fix the compiler error for exynos4

[Jaehoon Chung]

If CONFIG_SYS_I2C_S3C24X0_SLAVE isn't defined, then complie error should
be occurred.
This patch is for preventing it.

Signed-off-by: Jaehoon Chung 
---
 drivers/i2c/s3c24x0_i2c.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index 2ece9f4..363cd04 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -24,6 +24,12 @@
 #include 
 #include "s3c24x0_i2c.h"
 
+#ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
+#define SYS_I2C_S3C24X0_SLAVE_ADDR 0
+#else
+#define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -87,7 +93,7 @@ static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, 
unsigned int speed)
i2c_bus->clock_frequency = speed;
 
i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
-   CONFIG_SYS_I2C_S3C24X0_SLAVE);
+   SYS_I2C_S3C24X0_SLAVE_ADDR);
 
return 0;
 }
-- 
2.10.2

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[U-Boot] [PATCH V3 3/7] configs: s5pc210_universal: enable the DM_PMIC and MAX8998

[Jaehoon Chung]

Enable the CONFIG_DM_PMIC and CONFIG_DM_PMIC_MAX8998.
s5pc210_universal board is using max8998 pmic.
To use the i2c/pmic driver model, enable these configurations.

Signed-off-by: Jaehoon Chung 
---
 configs/s5pc210_universal_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/s5pc210_universal_defconfig 
b/configs/s5pc210_universal_defconfig
index b6cefb1..538e0ce 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -32,6 +32,9 @@ CONFIG_DFU_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_S5P=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_MAX8998=y
+CONFIG_SYS_I2C_S3C24X0=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
-- 
2.10.2

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Re: [U-Boot] [v3 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

[Chee, Tien Fong]

On Jum, 2017-01-06 at 12:12 -0600, Dinh Nguyen wrote:
> 
> On 01/06/2017 05:19 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > Enhanced defconfig file for Arria10 to enable SPL build and
> > supporting
> > device tree build for SDMMC.
> > 
> > Signed-off-by: Tien Fong Chee 
> > Cc: Marek Vasut 
> > Cc: Dinh Nguyen 
> > Cc: Chin Liang See 
> > Cc: Tien Fong 
> > ---
> > Changes for V3
> > - no changes
> > Changes for V2
> > - Removed boot header info setup since it already fixed in mainline
> > ---
> You can probably just roll this patch together with the previous
> patch 
> for socfpga_arria10_defconfig "[v3 07/30] arm: socfpga: arria10: add
> socfpga_arria10_defconfig"
> 
> Dinh

Okay, noted.
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Re: [U-Boot] Please update scripts/config_whitelist.txt

[Tom Rini]

On Mon, Jan 09, 2017 at 12:58:22AM +0900, Masahiro Yamada wrote:

> Hi Tom.
> 
> Could you run "scripts/build-whitelist.sh"
> before or after the v2017.01 release, please?
> 
> This will sync scripts/config_whitelist.txt,
> so we will see the progress of Kconfig moves.

Good idea, thanks!

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Re: [U-Boot] [PATCH 2/2] armv8: add asserts of sizes to u-boot-spl.lds

[Tom Rini]

On Mon, Dec 26, 2016 at 04:20:41PM +0200, Oded Gabbay wrote:

> This patch copies from arm u-boot-spl.lds some asserts that check that the
> size of the SPL image and BSS doesn't violate their max size.
> 
> Signed-off-by: Oded Gabbay 
> Cc: Albert Aribaud 

This shows a few problems with the uniphier platforms so I'm not
applying this currently.  Masahiro, can you take a look please?  Thanks!
https://travis-ci.org/trini/u-boot/jobs/190080917

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Re: [U-Boot] [PATCH v2 2/2] lib: net_utils: enforce '.' as octet separator in string_to_ip

[Wolfgang Denk]

Dear Chris,

In message  
you wrote:
>
> > The old code was forgiving and would accept 192,168,1,2 as well.
> 
> Technically you can't enter that. The env_flags.c code prevents that
> from being added to environment variables that have been tagged as ip
> addresses. These patches are pushing the logic down a bit further. The
> code handling env_flags_vartype_ipaddr could be updated to use
> string_to_ip instead.

I'm not 100% sure about that.  U-Boot environment is a complex thing.
For example, what happens if we use "env import" to import variable
settings from text or binary formats?  Are all these checks present
then, too?  [Sorry for asking, I really don't know.]

> > Also, at least crtitical parts of the network code (NFS, TFTP) do not
> > check the return value of string_to_ip() - so what is the benefit of
> > this change?
> >
> 
> The reasoning behind this change is to prepare for parsing ipv6
> addresses, which can contain ipv4 format addresses provided they are
> at the end.
> 
> e.g. This is a valid ipv6 address ":::192.168.1.1" and so is
> ":::0192:0168:0001:0001" but the former triggers the ipv4 mapping
> logic.

Ah, I see.  Makes sense.

Should we add error handling to TFTP and NFS, then?

Best regards,

Wolfgang Denk

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[U-Boot] Please update scripts/config_whitelist.txt

[Masahiro Yamada]

Hi Tom.

Could you run "scripts/build-whitelist.sh"
before or after the v2017.01 release, please?

This will sync scripts/config_whitelist.txt,
so we will see the progress of Kconfig moves.



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[U-Boot] [PATCH v2 7/7] arm64: mvebu: Add default configuraton for MACCHIATOBin board

[kostap]

From: Konstantin Porotchkin 

Add default configuration for MACHHIATOBin community board
based on Aramda-8040 SoC.

Change-Id: I60efcca5b31060340ad0a948561f082646f6556c
Signed-off-by: Konstantin Porotchkin 
Cc: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
Changes for v2:
- None, copy

 configs/mvebu_mcbin-88f8040_defconfig | 65 +++
 1 file changed, 65 insertions(+)
 create mode 100644 configs/mvebu_mcbin-88f8040_defconfig

diff --git a/configs/mvebu_mcbin-88f8040_defconfig 
b/configs/mvebu_mcbin-88f8040_defconfig
new file mode 100644
index 000..ed6e9db
--- /dev/null
+++ b/configs/mvebu_mcbin-88f8040_defconfig
@@ -0,0 +1,65 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MVEBU_ARMADA_8K=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-8040-mcbin"
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_BLOCK_CACHE=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_DM_GPIO=y
+CONFIG_MVEBU_GPIO=y
+CONFIG_MISC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=2
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_MMC=y
+CONFIG_XENON_SDHCI=y
+CONFIG_SMBIOS_MANUFACTURER=""
+CONFIG_PINCTRL=y
+CONFIG_HUSH_PARSER=y
-- 
2.7.4

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[U-Boot] [PATCH v2 6/7] arm64: mvebu: dts: Add DTS file for MACCHIATOBin board

[kostap]

From: Rabeeh Khoury 

Added A8040 dts file for community board MACCHIATIBin.
The patch includes the following features:
AP -  eMMC, Serial console (connected to onboard FTDI usb to serial)
CP0 - PCIe x4, SATA, I2C and 10G KR
  (connected to Marvell 3310 10G copper / SFP+ phy)
CP1 - Boot SPI, USB3 host, 2xSATA, 10G KR
  (connected to Marvell 3310 10G copper / SFP+ phy),
  SGMII connected to onboard 1512 1Gbps copper phy,
  and additional SGMII connected to SFP
  (default 1Gbps can be configured to 2.5Gbps).

Network interface naming -
egiga0 - CP0 KR
egiga1 - CP1 KR
egiga2 - CP1 RJ45 1Gbps connector (recommended for TFTP boot)
egiga3 - CP1 SFP default 1Gbps and can be modified to 2.5Gbps

Change-Id: Icb844eff9a8f07cd76ca8f86ffb01fe297bde836
Signed-off-by: Konstantin Porotchkin 
Signed-off-by: Rabeeh Khoury 
Cc: Stefan Roese 
Cc: Nadav Haklai 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
Changes for v2:
- None, copy

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/armada-8040-mcbin.dts | 253 +
 2 files changed, 254 insertions(+)
 create mode 100644 arch/arm/dts/armada-8040-mcbin.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ff78385..10e0536 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -76,6 +76,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=   \
armada-385-amc.dtb  \
armada-7040-db.dtb  \
armada-8040-db.dtb  \
+   armada-8040-mcbin.dtb   \
armada-xp-gp.dtb\
armada-xp-maxbcm.dtb\
armada-xp-synology-ds414.dtb\
diff --git a/arch/arm/dts/armada-8040-mcbin.dts 
b/arch/arm/dts/armada-8040-mcbin.dts
new file mode 100644
index 000..682e6f7
--- /dev/null
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -0,0 +1,253 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include "armada-8040.dtsi" /* include SoC device tree */
+
+/ {
+   model = "MACCHIATOBin-8040";
+   compatible = "marvell,armada8040-mcbin",
+"marvell,armada8040";
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   aliases {
+   i2c0 = _i2c0;
+   i2c1 = _i2c1;
+   spi0 = _spi1;
+   gpio0 = _gpio0;
+   gpio1 = _gpio0;
+   gpio2 = _gpio1;
+   };
+
+   memory@ {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x8000>;
+   };
+};
+
+/* Accessible over the mini-USB CON9 connector on the main board */
+ {
+   status = "okay";
+};
+
+_pinctl {
+   /*
+* MPP Bus:
+* eMMC [0-10]
+* UART0 [11,19]
+*/
+ /* 0 1 2 3 4 5 6 7 8 9 */
+   pin-func = < 1 1 1 1 1 1 1 1 1 1
+1 3 0 0 0 0 0 0 0 3 >;
+};
+
+/* on-board eMMC */
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_emmc_pins>;
+   bus-width= <8>;
+   status = "okay";
+};
+
+_pinctl {
+   /*
+* MPP Bus:
+* [0-31] = 0xff: Keep default CP0_shared_pins:
+* [11] CLKOUT_MPP_11 (out)
+* [23] LINK_RD_IN_CP2CP (in)
+* [25] CLKOUT_MPP_25 (out)
+* [29] AVS_FB_IN_CP2CP (in)
+* [32,34] SMI
+* [33]MSS power down
+* [35-38] CP0 I2C1 and I2C0
+* [39] MSS CKE Enable
+* [40,41] CP0 UART1 TX/RX
+* [42,43] XSMI (controls two 10G phys)
+* [47] USB VBUS EN
+* [48] FAN PWM
+* [49] 10G port 1 interrupt
+* [50] 10G port 0 interrupt
+* [51] 2.5G SFP TX fault
+* [52] PCIe reset out
+* [53] 2.5G SFP mode
+* [54] 2.5G SFP LOS
+* [55] Micro SD card detect
+* [56-61] Micro SD
+* [62] CP1 KR SFP FAULT
+*/
+   /*   0123456789 */
+   pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+0xff 070xa  722220xa
+7788000000
+0090000xe  0xe  0xe  0xe
+0xe  0xe  0 >;
+};
+
+/* PCIe x4 */
+_pcie0 {
+   num-lanes = <4>;
+   marvell,reset-gpio = <_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */
+   status = "okay";
+};
+
+_i2c0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c0_pins>;
+   status = "okay";
+   

[U-Boot] [PATCH v2 5/7] mvebu: pcie: Add support for GPIO reset for PCIe device

[kostap]

From: Konstantin Porotchkin 

Add support for "marvell,reset-gpio" property to mvebu DW PCIe
driver.
This option is valid when CONFIG_DM_GPIO=y

Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986
Signed-off-by: Konstantin Porotchkin 
Signed-off-by: Rabeeh Khoury 
Cc: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
Changes for v2:
- Move PCIe reset GPIO support from board-specific function to mvebu PCIe driver
- Increase delay after releasing the PCIe reset GPIO

 doc/device-tree-bindings/pci/armada8k-pcie.txt | 49 ++
 drivers/pci/pcie_dw_mvebu.c| 20 +++
 2 files changed, 69 insertions(+)
 create mode 100644 doc/device-tree-bindings/pci/armada8k-pcie.txt

diff --git a/doc/device-tree-bindings/pci/armada8k-pcie.txt 
b/doc/device-tree-bindings/pci/armada8k-pcie.txt
new file mode 100644
index 000..7230f10
--- /dev/null
+++ b/doc/device-tree-bindings/pci/armada8k-pcie.txt
@@ -0,0 +1,49 @@
+Armada-8K PCIe DT details:
+==
+
+Armada-8k uses synopsis designware PCIe controller.
+
+Required properties:
+- compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie".
+- reg: base addresses and lengths of the pcie control and global control 
registers.
+ "ctrl" registers points to the global control registers, while the "config" 
space
+ points to the pcie configuration registers as mentioned in dw-pcie dt 
bindings in the link below.
+- interrupt-map-mask and interrupt-map, standard PCI properties to
+  define the mapping of the PCIe interface to interrupt numbers.
+- All other definitions as per generic PCI bindings
+See Linux kernel documentation:
+"Documentation/devicetree/bindings/pci/designware-pcie.txt"
+
+Optional properties:
+PHY support is still not supported for armada-8k, once it will, the following 
parameters can be used:
+- phys : phandle to phy node associated with pcie controller.
+- phy-names: must be "pcie-phy"
+- marvell,reset-gpio :  specifies a gpio that needs to be activated for plug-in
+   card reset signal release.
+Example:
+
+cpm_pcie0: pcie@f260 {
+   compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+   reg = <0 0xf260 0 0x1>,
+ <0 0xf6f0 0 0x8>;
+   reg-names = "ctrl", "config";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   device_type = "pci";
+   dma-coherent;
+
+   bus-range = <0 0xff>;
+   ranges =
+   /* downstream I/O */
+   <0x8100 0 0xf900 0  0xf900 0 0x1
+   /* non-prefetchable memory */
+   0x8200 0 0xf600 0  0xf600 0 0xf0>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+   interrupts = ;
+   num-lanes = <1>;
+   clocks = <_syscon0 1 13>;
+   marvell,reset-gpio = <_gpio1 20 GPIO_ACTIVE_HIGH>;
+   status = "disabled";
+};
diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index 17fa024..d4776a9 100644
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -461,6 +462,25 @@ static int pcie_dw_mvebu_probe(struct udevice *dev)
struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+#ifdef CONFIG_DM_GPIO
+   struct gpio_desc reset_gpio;
+
+   gpio_request_by_name(dev, "marvell,reset-gpio", 0, _gpio,
+GPIOD_IS_OUT);
+   /*
+* Issue reset to add-in card trough the dedicated GPIO.
+* Some boards are connecting the card reset pin to common system
+* reset wire and others are using separate GPIO port.
+* In the last case we have to release a reset of the addon card
+* using this GPIO.
+*/
+   if (dm_gpio_is_valid(_gpio)) {
+   dm_gpio_set_value(_gpio, 1);
+   mdelay(200);
+   }
+#else
+   debug("PCIE Reset on GPIO support is missing\n");
+#endif /* CONFIG_DM_GPIO */
 
pcie->first_busno = dev->seq;
 
-- 
2.7.4

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[U-Boot] [PATCH v2 2/7] arm64: mvebu: gpio: Add GPIO nodes to A8K family devices

[kostap]

From: Konstantin Porotchkin 

Add GPIO nodes to AP-806 and CP-110-master DTSI files.

Change-Id: I05958698d460cb721b7d8683d34f74a5ea32532c
Signed-off-by: Konstantin Porotchkin 
Cc: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
Changes for v2:
- None, copy

 arch/arm/dts/armada-7040.dtsi |  1 +
 arch/arm/dts/armada-8040.dtsi |  1 +
 arch/arm/dts/armada-ap806.dtsi|  8 
 arch/arm/dts/armada-cp110-master.dtsi | 18 ++
 arch/arm/dts/armada-cp110-slave.dtsi  | 18 ++
 5 files changed, 46 insertions(+)

diff --git a/arch/arm/dts/armada-7040.dtsi b/arch/arm/dts/armada-7040.dtsi
index 78d995d..b5be0c4 100644
--- a/arch/arm/dts/armada-7040.dtsi
+++ b/arch/arm/dts/armada-7040.dtsi
@@ -45,6 +45,7 @@
  * one CP110.
  */
 
+#include 
 #include "armada-ap806-quad.dtsi"
 #include "armada-cp110-master.dtsi"
 
diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi
index 9c1b28c..96cc112 100644
--- a/arch/arm/dts/armada-8040.dtsi
+++ b/arch/arm/dts/armada-8040.dtsi
@@ -45,6 +45,7 @@
  * two CP110.
  */
 
+#include 
 #include "armada-ap806-quad.dtsi"
 #include "armada-cp110-master.dtsi"
 #include "armada-cp110-slave.dtsi"
diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi
index b6d31af..d86e5dd 100644
--- a/arch/arm/dts/armada-ap806.dtsi
+++ b/arch/arm/dts/armada-ap806.dtsi
@@ -158,6 +158,14 @@
};
};
 
+   ap_gpio0: gpio@6F5040 {
+   compatible = "marvell,orion-gpio";
+   reg = <0x6F5040 0x40>;
+   ngpios = <20>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
xor@40 {
compatible = "marvell,mv-xor-v2";
reg = <0x40 0x1000>,
diff --git a/arch/arm/dts/armada-cp110-master.dtsi 
b/arch/arm/dts/armada-cp110-master.dtsi
index d637867..a3e922d 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -113,6 +113,24 @@
};
};
 
+   cpm_gpio0: gpio@440100 {
+   compatible = "marvell,orion-gpio";
+   reg = <0x440100 0x40>;
+   ngpios = <32>;
+   gpiobase = <20>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   cpm_gpio1: gpio@440140 {
+   compatible = "marvell,orion-gpio";
+   reg = <0x440140 0x40>;
+   ngpios = <31>;
+   gpiobase = <52>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
cpm_sata0: sata@54 {
compatible = "marvell,armada-8k-ahci";
reg = <0x54 0x3>;
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi 
b/arch/arm/dts/armada-cp110-slave.dtsi
index 92ef55c..ff3fbed 100644
--- a/arch/arm/dts/armada-cp110-slave.dtsi
+++ b/arch/arm/dts/armada-cp110-slave.dtsi
@@ -100,6 +100,24 @@
};
};
 
+   cps_gpio0: gpio@440100 {
+   compatible = "marvell,orion-gpio";
+   reg = <0x440100 0x40>;
+   ngpios = <32>;
+   gpiobase = <20>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   cps_gpio1: gpio@440140 {
+   compatible = "marvell,orion-gpio";
+   reg = <0x440140 0x40>;
+   ngpios = <31>;
+   gpiobase = <52>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
cps_sata0: sata@54 {
compatible = "marvell,armada-8k-ahci";
reg = <0x54 0x3>;
-- 
2.7.4

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[U-Boot] [PATCH v2 4/7] mvebu: usb: xhci: Add support for VBUS controlled by GPIO

[kostap]

From: Konstantin Porotchkin 

Add support for "marvell,vbus-gpio" property to mvebu XHCI
host adapter driver.
This option is valid when CONFIG_DM_GPIO=y

Change-Id: I930b3ebe001e50ae8d5abe1f3c774bcdb1739e64
Signed-off-by: Konstantin Porotchkin 
Cc: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
Changes for v2:
- Move VBUS GPIO support from board-specific function to mvebu XHCI driver
- Increase delay after VBUS GPIO activation

 doc/device-tree-bindings/usb/marvell.xhci-usb.txt | 29 +++
 drivers/usb/host/xhci-mvebu.c | 14 +++
 2 files changed, 43 insertions(+)
 create mode 100644 doc/device-tree-bindings/usb/marvell.xhci-usb.txt

diff --git a/doc/device-tree-bindings/usb/marvell.xhci-usb.txt 
b/doc/device-tree-bindings/usb/marvell.xhci-usb.txt
new file mode 100644
index 000..b0a53ad
--- /dev/null
+++ b/doc/device-tree-bindings/usb/marvell.xhci-usb.txt
@@ -0,0 +1,29 @@
+Marvell SOC USB controllers
+
+This controller is integrated in Armada 3700/8K.
+It uses the same properties as a generic XHCI host controller
+
+Required properties :
+ - compatible: should be one or more of:
+   - "marvell,armada3700-xhci", "generic-xhci" for Armada 37xx SoCs
+   - "marvell,armada-8k-xhci", "generic-xhci" for Armada A8K SoCs
+ - reg: should contain address and length of the standard XHCI
+register set for the device.
+ - interrupts: one XHCI interrupt should be described here.
+
+Optional properties:
+ - clocks: reference to a clock
+ - marvell,vbus-gpio : If present, specifies a gpio that needs to be
+   activated for the bus to be powered.
+
+Example:
+   cpm_usb3_0: usb3@50 {
+   compatible = "marvell,armada-8k-xhci",
+"generic-xhci";
+   reg = <0x50 0x4000>;
+   interrupts = ;
+   clocks = <_syscon0 1 22>;
+   marvell,vbus-gpio = <_gpio1 15 GPIO_ACTIVE_HIGH>;
+   status = "disabled";
+   };
+
diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c
index 46eb937..64801e7 100644
--- a/drivers/usb/host/xhci-mvebu.c
+++ b/drivers/usb/host/xhci-mvebu.c
@@ -45,6 +45,20 @@ static int xhci_usb_probe(struct udevice *dev)
struct mvebu_xhci *ctx = dev_get_priv(dev);
struct xhci_hcor *hcor;
int len;
+#ifdef CONFIG_DM_GPIO
+   struct gpio_desc vbus_gpio;
+
+   gpio_request_by_name(dev, "marvell,vbus-gpio", 0, _gpio,
+GPIOD_IS_OUT);
+
+   if (dm_gpio_is_valid(_gpio)) {
+   dm_gpio_set_value(_gpio, 1);
+   /* Wait for the GPIO VBUS output set */
+   mdelay(500);
+   }
+#else
+   debug("USB VBUS on GPIO support is missing\n");
+#endif /* CONFIG_DM_GPIO */
 
ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
len = HC_LENGTH(xhci_readl(>hcd->cr_capbase));
-- 
2.7.4

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[U-Boot] [PATCH v2 1/7] arm64: mvebu: Update bubt command MMC block device access

[kostap]

From: Konstantin Porotchkin 

Update the MMC block device access code in bubt command
implementation according to the latest MMC driver changes.

Change-Id: Ie852ceefa0b040ffe1362bdb7815fcea9b2d923b
Signed-off-by: Konstantin Porotchkin 
Cc: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
Changes for v2:
- Allow MMC support for builds without CONFIG_BLK

 cmd/mvebu/bubt.c | 25 ++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
index 1cbfcf0..b752927 100644
--- a/cmd/mvebu/bubt.c
+++ b/cmd/mvebu/bubt.c
@@ -18,6 +18,9 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_BLK
+#include 
+#endif
 #include 
 #include 
 
@@ -116,7 +119,9 @@ static int mmc_burn_image(size_t image_size)
ulong   blk_written;
int err;
const u8mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
-
+#ifdef CONFIG_BLK
+   struct blk_desc *blk_desc;
+#endif
mmc = find_mmc_device(mmc_dev_num);
if (!mmc) {
printf("No SD/MMC/eMMC card found\n");
@@ -144,13 +149,27 @@ static int mmc_burn_image(size_t image_size)
 * MMC/eMMC boots from LBA-0
 */
start_lba = IS_SD(mmc) ? 1 : 0;
+#ifdef CONFIG_BLK
+   blk_count = image_size / mmc->write_bl_len;
+   if (image_size % mmc->write_bl_len)
+   blk_count += 1;
+
+   blk_desc = mmc_get_blk_desc(mmc);
+   if (!blk_desc) {
+   printf("Error - failed to obtain block descriptor\n");
+   return -ENODEV;
+   }
+   blk_written = blk_dwrite(blk_desc, start_lba, blk_count,
+(void *)get_load_addr());
+#else
blk_count = image_size / mmc->block_dev.blksz;
if (image_size % mmc->block_dev.blksz)
blk_count += 1;
 
blk_written = mmc->block_dev.block_write(mmc_dev_num,
-   start_lba, blk_count,
-   (void *)get_load_addr());
+start_lba, blk_count,
+(void *)get_load_addr());
+#endif /* CONFIG_BLK */
if (blk_written != blk_count) {
printf("Error - written %#lx blocks\n", blk_written);
return -ENOSPC;
-- 
2.7.4

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[U-Boot] [PATCH v2 3/7] arm64: mvebu: dts: Add i2c1 pin definitions to CPM

[kostap]

From: Konstantin Porotchkin 

Add i2c-1 pin mappings to CP0(master) DTSI file

Change-Id: I0c6e6de8a557393f518f7df8e6daa6dfce1788b0
Signed-off-by: Konstantin Porotchkin 
Cc: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
Changes for v2:
- None, copy

 arch/arm/dts/armada-cp110-master.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/armada-cp110-master.dtsi 
b/arch/arm/dts/armada-cp110-master.dtsi
index a3e922d..3776e4e 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -94,6 +94,10 @@
marvell,pins = < 37 38 >;
marvell,function = <2>;
};
+   cpm_i2c1_pins: cpm-i2c-pins-1 {
+   marvell,pins = < 35 36 >;
+   marvell,function = <2>;
+   };
cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 {
marvell,pins = < 44 45 46 47 48 49 50 51
 52 53 54 55 >;
-- 
2.7.4

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[U-Boot] [PATCH v2 0/7] arm64: mvebu: Add support for A8K community board

[kostap]

From: Konstantin Porotchkin 

This patch series adds initil support for A8K community board
MACCHIATOBin manufactured by SolidRun.
It should be applied on top of Stefan Roese patches adding support
for SD/eMMC devices on Marvell A37x0/A80x0/A70x0 SoCs.
The top level patch is called:
"arm64: mvebu: Enable SDHCI/MMC support for the db-88f7040/8040"
The default board DTS file is based on the original work of Rabeeh
Khory from SolidRun.

Changes for v2:
- Move PCIe reset GPIO support from board-specific function to mvebu PCIe driver
- Move VBUS GPIO support from board-specific function to mvebu XHCI driver
- Allow MMC support for "bubt" command with and without CONFIG_BLK

Konstantin Porotchkin (6):
  arm64: mvebu: Update bubt command MMC block device access
  arm64: mvebu: gpio: Add GPIO nodes to A8K family devices
  arm64: mvebu: dts: Add i2c1 pin definitions to CPM
  mvebu: usb: xhci: Add support for VBUS controlled by GPIO
  mvebu: pcie: Add support for GPIO reset for PCIe device
  arm64: mvebu: Add default configuraton for MACCHIATOBin board

Rabeeh Khoury (1):
  arm64: mvebu: dts: Add DTS file for MACCHIATOBin board

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/armada-7040.dtsi |   1 +
 arch/arm/dts/armada-8040-mcbin.dts| 253 ++
 arch/arm/dts/armada-8040.dtsi |   1 +
 arch/arm/dts/armada-ap806.dtsi|   8 +
 arch/arm/dts/armada-cp110-master.dtsi |  22 ++
 arch/arm/dts/armada-cp110-slave.dtsi  |  18 ++
 cmd/mvebu/bubt.c  |  25 ++-
 configs/mvebu_mcbin-88f8040_defconfig |  65 ++
 doc/device-tree-bindings/pci/armada8k-pcie.txt|  49 +
 doc/device-tree-bindings/usb/marvell.xhci-usb.txt |  29 +++
 drivers/pci/pcie_dw_mvebu.c   |  20 ++
 drivers/usb/host/xhci-mvebu.c |  14 ++
 13 files changed, 503 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/armada-8040-mcbin.dts
 create mode 100644 configs/mvebu_mcbin-88f8040_defconfig
 create mode 100644 doc/device-tree-bindings/pci/armada8k-pcie.txt
 create mode 100644 doc/device-tree-bindings/usb/marvell.xhci-usb.txt

-- 
2.7.4

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[U-Boot] Baremetal && Qemu vexpress && U-boot

[Mark L .]

Hi,

I have a problem with a baremetal program I would like U-boot to launch inside 
a QEMU.
Versions:
Qemu: 2.2.1. Machine vexpress-a9
U-boot: fetched "latest" from ftp (dated as 11/07/2016)
U-boot machine: vexpress_ca9x4_config

I followed the instructions in this link:
https://balau82.wordpress.com/2010/03/10/u-boot-for-arm-on-qemu/

I end up with:
"Wrong Image Format for bootm command
ERROR: can’t get kernel image!"

When executing iminfo, I get: 
"## Checking Image at 80008000 ...
Unknown image format!"

Even modifying the test.ld with a start address of 80008000 instead of 1, 
and the same for mkimage won't give any result.
I provide a raw binary (just like the tuto) for my app with no headers.

I think the "cat u-boot test.uimg > flash.bin" has become more than useless now.
After u-boot compilation, I can't use the binary version: no prompt will show 
and a crash is waiting to happen. One has to use the u-boot image.
How can I plug my baremetal application in this case?

I tried hard with "md" to find my code (in U-boot) but the code is so scattered 
that I lost myself in the process.

Any help would be very appreciated

Thanks

-- 
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[U-Boot] Porting u-boot to a new soc, unsure of standards to follow.

[Marty Plummer]

Greetings,

So, out of a desire to learn (or simply pure masochism), I've taken it
upon myself to work on mainlining support for a new arm SoC and board,
which the vendor SDK only provides source for release 2010.06 (which I
had to find via taobao since the vendor in question is not being nice
in regards to providing gpl source code from their sdks, but this is
besides the point).

Having already cobbled together devicetree files for the SoC which has
allowed me to boot mainline linux from Linus' tree using the u-boot on
the board, I figured I'd take a go at using devicetree in u-boot itself
to describe the hardware. Asking about this on irc, I was pointed at the
firefly-rk3288 as an example of how to do this. Referencing the source
code and the datasheet in question, I started to wrap my head around
bootrom, spl, u-boot, and their interactions, and began the task of
defining the various system controller registers, using the rockhip code
as a guide.

However, upon mentioning the structs on irc, I was asked by Marex to not
use this method, instead using macros and hex offsets. At this point
I've become a bit confused as to how I should proceed. The coding style
guide[1] says one should use "a C structure to map out the registers in
an I/O region", which appears to be what the rk3288 code does, but is at
odds with Marex's request and instruction to use macros.

So, I'm asking the ml and whatever powers that be how I should proceed,
as I'd really hate to write a bunch of code that has to be changed to
such a degree that it may as well be discarded and started from scratch.

Regards,
Marty Plummer

[1] http://www.denx.de/wiki/U-Boot/CodingStyle


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