Re: [U-Boot] [PATCH] armv8: ls1043a/ls1046aqds: fix the offsets of MTD partitions on Nor flash
On 03/16/2017 06:05 PM, Wenbin Song wrote: > Hi york, > > Do you mean it is not necessary to supply so much partitions for user, just > supplying two partitions, one is reserved for firmware(including RCW, U-boot, > Env, PPA, kernel.itb and so on), the other is the rest of flashes, if not, > Could you give me more details? Wenbin, I think it depends on what you expect users to do with those partitions. That's why I said you don't have use SDK layout. If you don't expect users to modify (eg. RCW and/or U-Boot), you can mark them as "ro". For some space, if you are not sure if the FIT image will be there, you can skip it. That's the benefit of using offsets. York > > Best Regards > Wenbin Song > > > > -Original Message- > From: york sun > Sent: Thursday, March 16, 2017 1:14 AM > To: Wenbin Song ; Mingkai Hu ; > s...@chromium.org; Z.Q. Hou ; M.H. Lian > ; u-boot@lists.denx.de > Subject: Re: [PATCH] armv8: ls1043a/ls1046aqds: fix the offsets of MTD > partitions on Nor flash > > On 03/13/2017 11:06 PM, Wenbin song wrote: >> Fix the offsets of MTD partitions on Nor flash on ls1043ardb, >> ls1043aqds and ls1046aqds boards. >> >> Signed-off-by: Wenbin Song >> --- >> include/configs/ls1043a_common.h | 7 --- >> include/configs/ls1046aqds.h | 7 --- >> 2 files changed, 8 insertions(+), 6 deletions(-) >> >> diff --git a/include/configs/ls1043a_common.h >> b/include/configs/ls1043a_common.h >> index c4b05e0..ca845b6 100644 >> --- a/include/configs/ls1043a_common.h >> +++ b/include/configs/ls1043a_common.h >> @@ -192,10 +192,11 @@ >> #else >> #define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \ >> "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ >> -"1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ >> -"1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ >> +"1m(nor_bank0_fman_uconde),"\ >> +"40m@110(nor_bank0_fit)," \ >> +"1m@400(nor_bank4_rcw),1m(nor_bank4_uboot)," \ >> "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ >> -"40m(nor_bank4_fit);7e80.flash:" \ >> +"40m@510(nor_bank4_fit);7e80.flash:" \ >> "1m(nand_uboot),1m(nand_uboot_env)," \ >> "20m(nand_fit);spi0.0:1m(uboot)," \ >> "5m(kernel),1m(dtb),9m(file_system)" >> diff --git a/include/configs/ls1046aqds.h >> b/include/configs/ls1046aqds.h index 4b3b21e..e045249 100644 >> --- a/include/configs/ls1046aqds.h >> +++ b/include/configs/ls1046aqds.h >> @@ -487,10 +487,11 @@ unsigned long get_board_ddr_clk(void); #else >> #define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \ >> "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ >> -"1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ >> -"1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ >> +"1m(nor_bank0_fman_uconde),"\ >> +"40m@110(nor_bank0_fit)," \ >> +"1m@400(nor_bank4_rcw),1m(nor_bank4_uboot)," \ >> "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ >> -"40m(nor_bank4_fit);7e80.flash:" \ >> +"40m@510(nor_bank4_fit);7e80.flash:" \ >> "4m(nand_uboot),36m(nand_kernel)," \ >> "472m(nand_free);spi0.0:2m(uboot)," \ >> "14m(free)" >> > > Wenbin, > > Maybe you can use more generic partitions for the NOR and put more detail in > comment. I believe the RCW, U-Boot, Env, Fman ucode, PPA are at fixed > locations. But the rest is up to user. We cannot assume the layout is > identical to SDK. Same goes to NAND partitions. > > York > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] driver: pci: Fix regions for local memory
On 03/16/2017 08:14 PM, Simon Glass wrote: > Hi York, > > On 16 March 2017 at 16:47, Simon Glass wrote: >> On 9 February 2017 at 11:35, York Sun wrote: >>> When adding local memory to PCI region, gd->ram_size is correct only >>> if the memory is in one continuous block. In case memory is split >>> into several banks, each bank should be added separately. >>> >>> Signed-off-by: York Sun >>> CC: Simon Glass >>> --- >>> It was spotted when I was rewriting the code to reserve secure memory >>> and forgot to reduce gd->ram_size. PCIe resumes working after fixing >>> gd->ram_size. For my case, the memory is split into two banks. So >>> base + gd->ram_size is not in memory. I don't know how it worked before. >>> This change seems reasonable without digging into PCI code. >>> >>> drivers/pci/pci-uclass.c | 18 +- >>> 1 file changed, 17 insertions(+), 1 deletion(-) >>> >> >> Acked-by: Simon Glass > > Unfortunately this breaks chromebook_link (x86). > > Do you have any ideas or should I dig into it? > Sorry I have no idea. If you can look into it, that will be great. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 03/22] x86: baytrail: acpi: Add APIs for determining/clearing sleep state
On 16 March 2017 at 08:26, Bin Meng wrote: > This adds APIs for determining previous sleep state from ACPI I/O > registers, as well as clearing sleep state on BayTrail SoC. > > Signed-off-by: Bin Meng > --- > > arch/x86/cpu/baytrail/acpi.c | 47 > ++ > arch/x86/include/asm/arch-baytrail/iomap.h | 24 +++ > 2 files changed, 71 insertions(+) > Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 01/22] dm: rtc: Add 16-bit read/write support
On 16 March 2017 at 08:26, Bin Meng wrote: > At present there are only 8-bit and 32-bit read/write routines in > the rtc uclass driver. This adds the 16-bit support. > > Signed-off-by: Bin Meng > --- > > drivers/rtc/rtc-uclass.c | 30 ++ > include/rtc.h| 20 > 2 files changed, 50 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 04/22] x86: Add post codes for OS resume
On 16 March 2017 at 08:26, Bin Meng wrote: > This adds OS_RESUME (0x40) and RESUME_FAILURE (0xed) post codes. > > Signed-off-by: Bin Meng > --- > > arch/x86/include/asm/post.h | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 02/22] x86: acpi: Add Kconfig option and header file for ACPI resume
Hi Bin,
On 16 March 2017 at 08:26, Bin Meng wrote:
> This introduces a Kconfig option for ACPI S3 resume, as well as a
> header file to include anything related to ACPI S3 resume.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/Kconfig | 12 +
> arch/x86/include/asm/acpi_s3.h | 58
> ++
> 2 files changed, 70 insertions(+)
> create mode 100644 arch/x86/include/asm/acpi_s3.h
Reviewed-by: Simon Glass
A few nits below
>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index dfdd756..7ea9148 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -571,6 +571,18 @@ config GENERATE_ACPI_TABLE
>
> endmenu
>
> +config HAVE_ACPI_RESUME
> + bool "Enable ACPI S3 resume"
> + help
> + Select this to enable ACPI S3 resume. S3 is an ACPI defined sleeping
ACPI-defined
> + state where all system context is lost except system memory. U-Boot
> + is responsible for restore the machine state as it is before sleep.
restoring
as it was before
> + It needs restore the memory controller, not overwriting memory which
s/not/without/ ?
> + is not marked as reserved. For the peripherals which lose their
> + registers, U-Boot needs to write the original value. When everything
> + is done, U-Boot needs to find out the wakeup vector provided by OSes
> + and jump there.
> +
> config MAX_PIRQ_LINKS
> int
> default 8
> diff --git a/arch/x86/include/asm/acpi_s3.h b/arch/x86/include/asm/acpi_s3.h
> new file mode 100644
> index 000..6fbfc3e
> --- /dev/null
> +++ b/arch/x86/include/asm/acpi_s3.h
> @@ -0,0 +1,58 @@
> +/*
> + * Copyright (C) 2017, Bin Meng
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#ifndef __ASM_ACPI_S3_H__
> +#define __ASM_ACPI_S3_H__
> +
> +/* PM1_STATUS register */
> +#define WAK_STS(1 << 15)
> +#define PCIEXPWAK_STS (1 << 14)
> +#define RTC_STS(1 << 10)
> +#define SLPBTN_STS (1 << 9)
> +#define PWRBTN_STS (1 << 8)
> +#define GBL_STS(1 << 5)
> +#define BM_STS (1 << 4)
> +#define TMR_STS(1 << 0)
> +
> +/* PM1_CNT register */
> +#define SLP_EN (1 << 13)
> +#define SLP_TYP_SHIFT 10
> +#define SLP_TYP(7 << SLP_TYP_SHIFT)
> +#define SLP_TYP_S0 0
> +#define SLP_TYP_S1 1
> +#define SLP_TYP_S3 5
> +#define SLP_TYP_S4 6
> +#define SLP_TYP_S5 7
> +
> +enum acpi_sleep_state {
> + ACPI_S0,
> + ACPI_S1,
> + ACPI_S2,
> + ACPI_S3,
> + ACPI_S4,
> + ACPI_S5,
> +};
> +
> +/* Given the provided PM1 control register return the ACPI sleep type */
@return ...
Does this need to be inline?
> +static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt)
> +{
> + switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
> + case SLP_TYP_S0:
> + return ACPI_S0;
> + case SLP_TYP_S1:
> + return ACPI_S1;
> + case SLP_TYP_S3:
> + return ACPI_S3;
> + case SLP_TYP_S4:
> + return ACPI_S4;
> + case SLP_TYP_S5:
> + return ACPI_S5;
> + }
> +
> + return -1;
-EINVAL ?
> +}
> +
> +#endif /* __ASM_ACPI_S3_H__ */
> --
> 2.9.2
>
Regards,
Simon
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Re: [U-Boot] [PATCH 00/22] x86: Add ACPI S3 resume support
Hi Bin, On 16 March 2017 at 08:26, Bin Meng wrote: > This adds ACPI S3 (suspend to ram) resume capability in U-Boot. > With S3 support within U-Boot, the board wakes up and resumes to > OS very quickly. > > This so far is enabled and tested on Intel MinnowMax board. Please > check README.x86 for how to test it with a plain Linux kernel. > Note testing with Ubuntu or Windows has some issues and fixes are > still being worked out. > > This series is available for testing in u-boot-x86/s3-working. It's great to see this! Nice work. I'll try it out at some point. Regards, SImon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] driver: pci: Fix regions for local memory
Hi York, On 16 March 2017 at 16:47, Simon Glass wrote: > On 9 February 2017 at 11:35, York Sun wrote: >> When adding local memory to PCI region, gd->ram_size is correct only >> if the memory is in one continuous block. In case memory is split >> into several banks, each bank should be added separately. >> >> Signed-off-by: York Sun >> CC: Simon Glass >> --- >> It was spotted when I was rewriting the code to reserve secure memory >> and forgot to reduce gd->ram_size. PCIe resumes working after fixing >> gd->ram_size. For my case, the memory is split into two banks. So >> base + gd->ram_size is not in memory. I don't know how it worked before. >> This change seems reasonable without digging into PCI code. >> >> drivers/pci/pci-uclass.c | 18 +- >> 1 file changed, 17 insertions(+), 1 deletion(-) >> > > Acked-by: Simon Glass Unfortunately this breaks chromebook_link (x86). Do you have any ideas or should I dig into it? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: dts: skeleton: fix unit name warning from dtc
Hi Simon,
> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: 2017年3月13日 21:24
> To: Masahiro Yamada
> Cc: Wenyou Yang - A41535 ; U-Boot Mailing
> List ; Stephen Warren
> Subject: Re: [U-Boot] [PATCH] ARM: dts: skeleton: fix unit name warning from
> dtc
>
> Hi,
>
> On 13 March 2017 at 03:00, Masahiro Yamada
> wrote:
> > 2017-03-13 16:53 GMT+09:00 Wenyou Yang :
> >> Fix the following warning from dtc by adding the unit name for the
> >> memory node.
> >> ---8<---
> >> Warning (unit_address_vs_reg): Node /memory has a reg or ranges
> >> property, but no unit name
> >> ---<8---
> >>
> >> Signed-off-by: Wenyou Yang
> >> ---
> >>
> >> arch/arm/dts/skeleton.dtsi | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm/dts/skeleton.dtsi b/arch/arm/dts/skeleton.dtsi
> >> index b41d241de2..a20da0a7a6 100644
> >> --- a/arch/arm/dts/skeleton.dtsi
> >> +++ b/arch/arm/dts/skeleton.dtsi
> >> @@ -9,5 +9,5 @@
> >> #size-cells = <1>;
> >> chosen { };
> >> aliases { };
> >> - memory { device_type = "memory"; reg = <0 0>; };
> >> + memory@0 { device_type = "memory"; reg = <0 0>; };
> >> };
> >> --
> >> 2.11.0
> >>
> >
> >
> >
> > As far as I can tell, the DT community decided to deprecate
> > skeleton.dtsi (and people are fixing DT files to not include it).
> >
> >
> >
> > commit 9c0da3cc61f1233c2782e2d3d91e3d0707dd4ba5
> > Author: Mark Rutland
> > Date: Fri Sep 2 17:34:50 2016 +0100
> >
> > ARM: dts: explicitly mark skeleton.dtsi as deprecated
> >
> > As noted in commit 3ebee5a2e141496b ("arm64: dts: kill skeleton.dtsi"),
> > there are a number of problems with skeleton.dtsi, and it would be
> > prefereable to remove it entirely. As there are a large number of
> > existing users, fixing these up will take a while.
> >
> > This patch adds a note to arm's skeleton.dtsi noting that this is the
> > case, to make this more obvious and hopefully minimize new uptake of
> > skeleton.dtsi in the mean time.
> >
> > Signed-off-by: Mark Rutland
> > Acked-by: Rob Herring
> > Cc: Arnd Bergmann
> > Cc: Olof Johansson
> > Signed-off-by: Arnd Bergmann
> >
> >
>
> OK so perhaps a patch to mark it deprecated, and a patch to remove it from the
> Atmel boards would be better?
Thank you for your information.
I will send a patch to remove it from the Atmel boards.
Best Regards,
Wenyou Yang
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Re: [U-Boot] [PATCH] armv8: ls1043a/ls1046aqds: fix the offsets of MTD partitions on Nor flash
Hi york, Do you mean it is not necessary to supply so much partitions for user, just supplying two partitions, one is reserved for firmware(including RCW, U-boot, Env, PPA, kernel.itb and so on), the other is the rest of flashes, if not, Could you give me more details? Best Regards Wenbin Song -Original Message- From: york sun Sent: Thursday, March 16, 2017 1:14 AM To: Wenbin Song ; Mingkai Hu ; s...@chromium.org; Z.Q. Hou ; M.H. Lian ; u-boot@lists.denx.de Subject: Re: [PATCH] armv8: ls1043a/ls1046aqds: fix the offsets of MTD partitions on Nor flash On 03/13/2017 11:06 PM, Wenbin song wrote: > Fix the offsets of MTD partitions on Nor flash on ls1043ardb, > ls1043aqds and ls1046aqds boards. > > Signed-off-by: Wenbin Song > --- > include/configs/ls1043a_common.h | 7 --- > include/configs/ls1046aqds.h | 7 --- > 2 files changed, 8 insertions(+), 6 deletions(-) > > diff --git a/include/configs/ls1043a_common.h > b/include/configs/ls1043a_common.h > index c4b05e0..ca845b6 100644 > --- a/include/configs/ls1043a_common.h > +++ b/include/configs/ls1043a_common.h > @@ -192,10 +192,11 @@ > #else > #define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \ > "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ > - "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ > - "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ > + "1m(nor_bank0_fman_uconde),"\ > + "40m@110(nor_bank0_fit)," \ > + "1m@400(nor_bank4_rcw),1m(nor_bank4_uboot)," \ > "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ > - "40m(nor_bank4_fit);7e80.flash:" \ > + "40m@510(nor_bank4_fit);7e80.flash:" \ > "1m(nand_uboot),1m(nand_uboot_env)," \ > "20m(nand_fit);spi0.0:1m(uboot)," \ > "5m(kernel),1m(dtb),9m(file_system)" > diff --git a/include/configs/ls1046aqds.h > b/include/configs/ls1046aqds.h index 4b3b21e..e045249 100644 > --- a/include/configs/ls1046aqds.h > +++ b/include/configs/ls1046aqds.h > @@ -487,10 +487,11 @@ unsigned long get_board_ddr_clk(void); #else > #define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \ > "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ > - "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ > - "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ > + "1m(nor_bank0_fman_uconde),"\ > + "40m@110(nor_bank0_fit)," \ > + "1m@400(nor_bank4_rcw),1m(nor_bank4_uboot)," \ > "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ > - "40m(nor_bank4_fit);7e80.flash:" \ > + "40m@510(nor_bank4_fit);7e80.flash:" \ > "4m(nand_uboot),36m(nand_kernel)," \ > "472m(nand_free);spi0.0:2m(uboot)," \ > "14m(free)" > Wenbin, Maybe you can use more generic partitions for the NOR and put more detail in comment. I believe the RCW, U-Boot, Env, Fman ucode, PPA are at fixed locations. But the rest is up to user. We cannot assume the layout is identical to SDK. Same goes to NAND partitions. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] ARM: dts: Makefile: use board id to decide which dts compile
Hi Simon, > -Original Message- > From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass > Sent: 2017年3月13日 21:24 > To: Wenyou Yang - A41535 > Cc: U-Boot Mailing List ; Stephen Warren > ; Andreas Bießmann ; Albert > Aribaud ; Wenyou Yang - A41535 > > Subject: Re: [PATCH v2] ARM: dts: Makefile: use board id to decide which dts > compile > > Hi Wenyou, > > On 13 March 2017 at 01:39, Wenyou Yang wrote: > > To avoid to compile all AT91 SoCs' board device tree files, use the > > board id to decide which device tree file will be compiled, instead of > > compile all AT91 family files. > > > > Signed-off-by: Wenyou Yang > > --- > > > > Changes in v2: > > - Improve the message log. > > > > arch/arm/dts/Makefile | 8 > > 1 file changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index > > eb68c204bb..77039b88d5 100644 > > --- a/arch/arm/dts/Makefile > > +++ b/arch/arm/dts/Makefile > > @@ -2,10 +2,10 @@ > > # SPDX-License-Identifier: GPL-2.0+ > > # > > > > -dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \ > > - at91sam9g20-taurus.dtb \ > > - at91sam9g45-corvus.dtb \ > > - at91sam9g45-gurnard.dtb > > +dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb > > +dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb > > +dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb > > +dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb > > What is the motivation for this change? I thought when building a board, only one device tree to be build. > > I think we should encourage building the DT for all related boards and > avoiding > TARGET in this Makefile. It reduces the number of boards we have to build to > find > a problem. One of the benefits of DT is to support different boards with > largely the > same code. Also it is very fast to build these files so this change probably > does > not reduce build time. Okay, accepted. Ignored the patch. > > > > > dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb > > dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb > > -- > > 2.11.0 > > > > Regards, > Simon Best Regards, Wenyou Yang ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Please pull u-boot-rockchip
Hi Tom, This is an updated version of the previous pull request, includes support for rk3188 from Heiko Stübner and and rk3328 from Kever Yang. Also included is SPL support for rk3399 and a fix for rk3288 to get it booting again (spl_early_init()). The following changes since commit 2808576491ae36b6ea96743005058f370d936beb: arm64: booti: allow to place kernel image anywhere in physical memory (2017-03-14 20:40:23 -0400) are available in the git repository at: git://git.denx.de/u-boot-rockchip.git for you to fetch changes up to 520c174b3564ae183f0e7c118dc8ce3770ae20b0: rockchip: video: Remove CSC initialization (HDMI) (2017-03-16 16:03:47 -0600) Eddie Cai (7): spl: Add spl_early_init() rockchip: rk3288: use spl_early_init() instead of spl_init() rockchip: tinker: configs: use correct mmc instance as boot target device dts: rk3399: add mmc alias for rk3399 dts: rk3036: add sdmmc for rk3036 rockchip: dts: tinker: add usb host power supply node rockchip: config: enable the USB host for rk3288 based board Heiko Stübner (20): dm: allow limiting pre-reloc markings to spl or tpl rockchip: clk: rk3288: limit gpll and cpll init to SPL build rockchip: rk3288: sdram: use constants in ddrconf table rockchip: rk3288: sdram: style fixes from rk3188 sdram review rockchip: Move bootrom helper compilation to a hidden option rockchip: Move bootrom-related declarations to a header rockchip: mkimage: Allow encoding of loader code in spl images rockchip: mkimage: Add support rk3188 serial rockchip: serial: Adapt rockchip of-platdata driver for rk3188 rockchip: rk3188: Add header files for PMU and GRF rockchip: rk3188: Add pinctrl driver rockchip: rk3188: Add sysreset driver rockchip: rk3188: Add rk3066/rk3188 clock bindings rockchip: rk3188: Add clock driver rockchip: rk3188: Add core devicetree files rockchip: rk3188: Add core support rockchip: rk3188: Add sdram driver rockchip: rk3188: Add main, spl and tpl boards dm: Return actual bools in dm_fdt_pre_reloc rockchip: rk3188: drop CONFIG_SYS_NO_FLASH Jacob Chen (3): rockchip: firefly: configs: remove config_spl_of_platdata ARM: dts: rockchip: enable gmac for rk3288 boards rockchip: configs: Enable networking support on rk3288 boards Jernej Skrabec (2): rockchip: video: Fix HDMI audio clocks rockchip: video: Remove CSC initialization (HDMI) Kever Yang (17): rockchip: arm64: rk3399: move grf register definitions to grf_rk3399.h rockchip: clk: rk3399: update driver for spl rockchip: sdhci: rk3399: update driver to support of-platdata rockchip: pinctrl: rk3399: add the of-platdata support rockchip: arm64: rk3399: syscon addition for rk3399 rockchip: arm64: rk3399: add ddr controller driver rockchip: dts: rk3399: update for spl require driver rockchip: arm64: rk3399: add SPL support rockchip: config: rk3399: enable SPL config for evb-rk3399 rockchip: rk3328: add device tree file rockchip: rk3328: add soc basic support rockchip: rk3328: add clock driver rockchip: rk3328: add pinctrl driver rockchip: rk3328: add sysreset driver rockchip: rk3328: add evb-rk3328 support rockchip: rk3328: add defconfig for evb-rk3328 rockchip: rk3036: dts: bind usb vbus-supply source arch/arm/dts/Makefile |1 + arch/arm/dts/rk3036-sdk.dts|2 + arch/arm/dts/rk3036.dtsi | 13 + arch/arm/dts/rk3188.dtsi | 601 arch/arm/dts/rk3288-evb.dtsi | 22 + arch/arm/dts/rk3288-popmetal.dtsi |2 +- arch/arm/dts/rk3288-tinker.dts | 11 + arch/arm/dts/rk3288-tinker.dtsi| 14 +- arch/arm/dts/rk3328-evb.dts| 45 ++ arch/arm/dts/rk3328.dtsi | 1477 ++ arch/arm/dts/rk3399-evb.dts|2 + arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi | 1536 arch/arm/dts/rk3399.dtsi | 46 ++ arch/arm/dts/rk3xxx.dtsi | 417 +++ arch/arm/include/asm/arch-rockchip/bootrom.h | 22 + arch/arm/include/asm/arch-rockchip/clock.h |9 + arch/arm/include/asm/arch-rockchip/cru_rk3188.h| 191 + arch/arm/include/asm/arch-rockchip/cru_rk3328.h| 70 ++ arch/arm/include/asm/arch-rockchip/cru_rk3399.h|5 + arch/arm/include/asm/arch-rockchip/ddr_rk3188.h| 25 + arch/arm/include/asm/arch-rockchip/ddr_rk3288.h|8 +
Re: [U-Boot] [PATCHv3 3/3] lib: move hash CONFIG options to Kconfig
On Thu, Mar 16, 2017 at 04:06:40PM -0600, Simon Glass wrote:
> Hi Tom,
>
> On 9 March 2017 at 11:44, Tom Rini wrote:
> > On Tue, Mar 07, 2017 at 11:20:08AM -0500, Tom Rini wrote:
> >> Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support
> >> using hardware acceleration.") created entries for CONFIG_SHA1,
> >> CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL.
> >> However, no defconfig has migrated to it. Complete the move by first
> >> adding additional logic to various Kconfig files to select this when
> >> required and then use the moveconfig tool. In many cases we can select
> >> these because they are required to implement other drivers. We also
> >> correct how we include the various hashing algorithms in SPL.
> >>
> >> This commit was generated as follows (after Kconfig additions):
> >>
> >> [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL
> >> [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL
> >>
> >> Note:
> >> We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously
> >> because there is dependency between them.
> >
> > This, oddly, breaks the verified boot tests on sandbox. And I can't
> > obviously see why. The u-boot.map files are identical even.
>
> It looks like this is not U-Boot itself:
>
> => +build-sandbox/tools/fit_check_sign -f
> u-boot/files/build-sandbox/test.fit -k u-boot/files/build-sandbox/ -k
> files/build-sandbox/sandbox-u-boot.dtb
> Signature check Bad (error 1)
> Verifying Hash Integrity ... sha1,rsa2048:dev-
> Failed to verify required signature 'key-dev'
>
> It SHA1 somehow missing with the fit_check_sign tool with this commit?
Ah, I think that's the crumb I needed. We move SHA1/SHA256 from
include/images.h to Kconfig select'ing them and thus what the host tools
(likely) are doing is broken. I'll figure this out now I think, thanks!
--
Tom
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Re: [U-Boot] [PATCH v3] Add single register pin controller driver
Hi, On 11 March 2017 at 04:52, James wrote: > Hi Felix, > > Not 'hijacking' a patch, just following Linux Developer's Certificate of > Origin 1.1 guidelines. > > As you know, I contacted you directly with this patch suggestion prior to > posting to the mailing list (keeping strictly to rule c). I had hoped you > would make a new version: > >> On 09.03.2017 08:53, James Balean wrote: >>> Did you want to test/submit this? > > Perhaps I misinterpreted your response, which stated: > > On Fri, 10 Mar 2017 at 04:13, Felix Brack wrote: >> This and probably more has to be accessible by _all_ mailing list > subscribers. Please post there. > > This was confusing, as I could see no way to convert this work to a patch > of your unapproved v2 patch (being new to this process). > > On Sat, 11 Mar 2017 at 00:07, Felix Brack wrote: >> Remove this "Signed-off-by" tag as I neither made nor tested these > modifications. > > My understanding from the 'submitting patches' guide is that the square > bracket nomenclature I used indicates minor changes to an existing patch, > thereby providing you with credit whilst also denoting that you do not > endorse the changes. > >> What if I fix a > bug in my v2 patch? Should I then increase from v2 to v4? > > Perhaps someone can clarify, but it seems logical that the version number > is in order of contribution to the project, rather than being tied to any > specific user. Especially given the software license it is under. It is better to make comments on the patch and let the original author respin it. If you have not heard after a week then I suppose you can resend it with the changes, i.w.c. I think you DO need to keep the original author's sign-off and increment the version. Felix, are you planning to resend this? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] driver: pci: Fix regions for local memory
On 9 February 2017 at 11:35, York Sun wrote: > When adding local memory to PCI region, gd->ram_size is correct only > if the memory is in one continuous block. In case memory is split > into several banks, each bank should be added separately. > > Signed-off-by: York Sun > CC: Simon Glass > --- > It was spotted when I was rewriting the code to reserve secure memory > and forgot to reduce gd->ram_size. PCIe resumes working after fixing > gd->ram_size. For my case, the memory is split into two banks. So > base + gd->ram_size is not in memory. I don't know how it worked before. > This change seems reasonable without digging into PCI code. > > drivers/pci/pci-uclass.c | 18 +- > 1 file changed, 17 insertions(+), 1 deletion(-) > Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] spl: Add spl_early_init()
On 03/16/2017 11:39 PM, Simon Glass wrote: > Hi Marek, > > On 16 March 2017 at 16:37, Marek Vasut wrote: >> On 03/16/2017 11:28 PM, Simon Glass wrote: >>> Hi Marek, >>> >>> On 16 March 2017 at 16:24, Marek Vasut wrote: On 03/16/2017 11:21 PM, Simon Glass wrote: > Hi Marek, > > On 16 March 2017 at 16:17, Marek Vasut wrote: >> On 03/15/2017 01:06 AM, Simon Glass wrote: >>> From: Eddie Cai >>> >>> At present malloc_base/_limit/_ptr are not initialised in spl_init() >>> when >>> we call spl_init() in board_init_f(). >> >> Are you even supposed to call spl_init() from board_init_f() ? >> I was under the impression that's supposed to be called by >> board_init_r() only. >> > > If you need to use DM then yes you must call it. SoCFPGA uses DM and doesn't call it until board_init_r() . I think there's some significant confusion about how this whole malloc stuff should work. >>> >>> OK, well if you want to use DM within board_init_f() you must call >>> this function If not, then board_init_r() will do it for you. When >>> does SoCFPGA start using DM? >> >> In _r . I don't see anyone using DM in _f though. What is that needed >> for , serial ? > > See for example board_init_f() in arch/arm/mach-rockchip/rk3288-board-spl.c > > It include sclock, pintctrl, SDRAM at least. Haaa, OK -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] spl: Add spl_early_init()
Hi Marek, On 16 March 2017 at 16:37, Marek Vasut wrote: > On 03/16/2017 11:28 PM, Simon Glass wrote: >> Hi Marek, >> >> On 16 March 2017 at 16:24, Marek Vasut wrote: >>> On 03/16/2017 11:21 PM, Simon Glass wrote: Hi Marek, On 16 March 2017 at 16:17, Marek Vasut wrote: > On 03/15/2017 01:06 AM, Simon Glass wrote: >> From: Eddie Cai >> >> At present malloc_base/_limit/_ptr are not initialised in spl_init() when >> we call spl_init() in board_init_f(). > > Are you even supposed to call spl_init() from board_init_f() ? > I was under the impression that's supposed to be called by > board_init_r() only. > If you need to use DM then yes you must call it. >>> >>> SoCFPGA uses DM and doesn't call it until board_init_r() . I think >>> there's some significant confusion about how this whole malloc stuff >>> should work. >> >> OK, well if you want to use DM within board_init_f() you must call >> this function If not, then board_init_r() will do it for you. When >> does SoCFPGA start using DM? > > In _r . I don't see anyone using DM in _f though. What is that needed > for , serial ? See for example board_init_f() in arch/arm/mach-rockchip/rk3288-board-spl.c It include sclock, pintctrl, SDRAM at least. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/1] usb: gadget: avoid variable name clipping in cb_getvar
On 03/13/2017 11:30 AM, Nicolas le bayon wrote:
> From: Nicolas Le Bayon
>
> Instead of using a fixed-size array to store variable name, preferring a
> dynamic allocation treats correctly all variable name lengths.
> Variable names are growing through releases and features. By this way, name
> clipping is prevented.
>
> Signed-off-by: Nicolas Le Bayon
> ---
> drivers/usb/gadget/f_fastboot.c | 13 +++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_
> fastboot.c
> index 2160b1c..11005e0 100644
> --- a/drivers/usb/gadget/f_fastboot.c
> +++ b/drivers/usb/gadget/f_fastboot.c
> @@ -432,9 +432,16 @@ static void cb_getvar(struct usb_ep *ep, struct
> usb_request *req)
> else
> strcpy(response, "FAILValue not set");
> } else {
> - char envstr[32];
> + char *envstr;
>
> - snprintf(envstr, sizeof(envstr) - 1, "fastboot.%s", cmd);
> + envstr = malloc(strlen("fastboot.") + strlen(cmd) + 1);
> + if (!envstr) {
> + error("malloc fail");
Just drop the error() here ... if your malloc failed, you're screwed anyway.
The rest looks OK IMO .
> + fastboot_tx_write_str("FAILmalloc error");
> + return;
> + }
> +
> + sprintf(envstr, "fastboot.%s", cmd);
> s = getenv(envstr);
> if (s) {
> strncat(response, s, chars_left);
> @@ -442,6 +449,8 @@ static void cb_getvar(struct usb_ep *ep, struct
> usb_request *req)
> printf("WARNING: unknown variable: %s\n", cmd);
> strcpy(response, "FAILVariable not implemented");
> }
> +
> + free(envstr);
> }
> fastboot_tx_write_str(response);
> }
> --
> 1.9.1
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v3 1/2] spl: Add spl_early_init()
On 03/16/2017 11:28 PM, Simon Glass wrote: > Hi Marek, > > On 16 March 2017 at 16:24, Marek Vasut wrote: >> On 03/16/2017 11:21 PM, Simon Glass wrote: >>> Hi Marek, >>> >>> On 16 March 2017 at 16:17, Marek Vasut wrote: On 03/15/2017 01:06 AM, Simon Glass wrote: > From: Eddie Cai > > At present malloc_base/_limit/_ptr are not initialised in spl_init() when > we call spl_init() in board_init_f(). Are you even supposed to call spl_init() from board_init_f() ? I was under the impression that's supposed to be called by board_init_r() only. >>> >>> If you need to use DM then yes you must call it. >> >> SoCFPGA uses DM and doesn't call it until board_init_r() . I think >> there's some significant confusion about how this whole malloc stuff >> should work. > > OK, well if you want to use DM within board_init_f() you must call > this function If not, then board_init_r() will do it for you. When > does SoCFPGA start using DM? In _r . I don't see anyone using DM in _f though. What is that needed for , serial ? -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] spl: Add spl_early_init()
Hi Marek, On 16 March 2017 at 16:24, Marek Vasut wrote: > On 03/16/2017 11:21 PM, Simon Glass wrote: >> Hi Marek, >> >> On 16 March 2017 at 16:17, Marek Vasut wrote: >>> On 03/15/2017 01:06 AM, Simon Glass wrote: From: Eddie Cai At present malloc_base/_limit/_ptr are not initialised in spl_init() when we call spl_init() in board_init_f(). >>> >>> Are you even supposed to call spl_init() from board_init_f() ? >>> I was under the impression that's supposed to be called by >>> board_init_r() only. >>> >> >> If you need to use DM then yes you must call it. > > SoCFPGA uses DM and doesn't call it until board_init_r() . I think > there's some significant confusion about how this whole malloc stuff > should work. OK, well if you want to use DM within board_init_f() you must call this function If not, then board_init_r() will do it for you. When does SoCFPGA start using DM? > >> At present with SPL >> it is not normally available until board_init_r(). At some point we >> will have all the boards consistent and we might be able to change >> this by default. >> >> [..] Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] spl: Add spl_early_init()
On 03/16/2017 11:21 PM, Simon Glass wrote: > Hi Marek, > > On 16 March 2017 at 16:17, Marek Vasut wrote: >> On 03/15/2017 01:06 AM, Simon Glass wrote: >>> From: Eddie Cai >>> >>> At present malloc_base/_limit/_ptr are not initialised in spl_init() when >>> we call spl_init() in board_init_f(). >> >> Are you even supposed to call spl_init() from board_init_f() ? >> I was under the impression that's supposed to be called by >> board_init_r() only. >> > > If you need to use DM then yes you must call it. SoCFPGA uses DM and doesn't call it until board_init_r() . I think there's some significant confusion about how this whole malloc stuff should work. > At present with SPL > it is not normally available until board_init_r(). At some point we > will have all the boards consistent and we might be able to change > this by default. > > [..] > > Regards, > Simon > -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2] Pass empty CFLAGS on invocation of libfdt/setup.py
When building u-boot tools in cross-build environment CFLAGS environment variable set up for target is taken into an account when building code for host. Make it empty on invocation of python. This fixes the following build errors when cross-compiling for xtensa: cc1: error: unrecognized command line option "-mlongcalls" cc1: error: unrecognized command line option "-mauto-litpools" Signed-off-by: Max Filippov Reviewed-by: Simon Glass --- Changes v1->v2: - remove "" after CFLAGS= tools/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/Makefile b/tools/Makefile index 1c840d7..f3de657 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -120,7 +120,7 @@ _libfdt.so-sharedobjs += $(LIBFDT_OBJS) libfdt: tools/_libfdt.so: $(patsubst %.o,%.c,$(LIBFDT_OBJS)) tools/libfdt_wrap.c - LDFLAGS="$(HOSTLDFLAGS)" python $(srctree)/lib/libfdt/setup.py \ + LDFLAGS="$(HOSTLDFLAGS)" CFLAGS= python $(srctree)/lib/libfdt/setup.py \ "$(_hostc_flags)" $^ mv _libfdt.so $@ -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 2/2] rockchip: rk3288: use spl_early_init() instead of spl_init()
Hi Kever, On 16 March 2017 at 01:08, Kever Yang wrote: > Hi Eddie, Simon, > > Could you help to correct rk3188, rk3399 spl at the same time? I don't have boards to test with for these, sorry. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 2/2] rockchip: rk3288: use spl_early_init() instead of spl_init()
On 16 March 2017 at 09:04, Eddie Cai wrote: > > > 2017-03-15 22:43 GMT+08:00 Simon Glass : >> >> From: Eddie Cai >> >> Use spl_early_init() to make sure that early malloc() is initialised. This >> fixes booting on firefly-rk3288, for example. >> >> Signed-off-by: Eddie Cai >> Signed-off-by: Simon Glass > > Reviewed-by: Eddie Cai Applied to u-boot-rockchip. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/2] spl: Add spl_early_init()
On 16 March 2017 at 09:02, Eddie Cai wrote:
>
>
> 2017-03-15 22:43 GMT+08:00 Simon Glass :
>>
>> From: Eddie Cai
>>
>> At present malloc_base/_limit/_ptr are not initialised in spl_init() when
>> we call spl_init() in board_init_f(). This is due to a recent change aimed
>> at avoiding overwriting the malloc area set up on some boards by
>> spl_relocate_stack_gd().
>>
>> However if CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN is not defined, we now
>> skip setting up the memory area in spl_init() which is obviously wrong.
>>
>> To fix this, add a new function spl_early_init() which can be called in
>> board_init_f().
>>
>> Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit)
>> Signed-off-by: Eddie Cai
>> Rewrote spl_{,early_}init() to avoid duplicate code:
>> Rewrite/expand commit message:
>> Signed-off-by: Simon Glass
>
> Reviewed-by: Eddie Cai
Applied to u-boot-rockchip.
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Re: [U-Boot] [PATCH v3 1/2] spl: Add spl_early_init()
Hi Marek, On 16 March 2017 at 16:17, Marek Vasut wrote: > On 03/15/2017 01:06 AM, Simon Glass wrote: >> From: Eddie Cai >> >> At present malloc_base/_limit/_ptr are not initialised in spl_init() when >> we call spl_init() in board_init_f(). > > Are you even supposed to call spl_init() from board_init_f() ? > I was under the impression that's supposed to be called by > board_init_r() only. > If you need to use DM then yes you must call it. At present with SPL it is not normally available until board_init_r(). At some point we will have all the boards consistent and we might be able to change this by default. [..] Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] spl: Add spl_early_init()
On 03/15/2017 01:06 AM, Simon Glass wrote:
> From: Eddie Cai
>
> At present malloc_base/_limit/_ptr are not initialised in spl_init() when
> we call spl_init() in board_init_f().
Are you even supposed to call spl_init() from board_init_f() ?
I was under the impression that's supposed to be called by
board_init_r() only.
> This is due to a recent change aimed
> at avoiding overwriting the malloc area set up on some boards by
> spl_relocate_stack_gd().
>
> However if CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN is not defined, we now
> skip setting up the memory area in spl_init() which is obviously wrong.
>
> To fix this, add a new function spl_early_init() which can be called in
> board_init_f().
>
> Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit)
> Signed-off-by: Eddie Cai
> Rewrote spl_{,early_}init() to avoid duplicate code:
> Rewrite/expand commit message:
> Signed-off-by: Simon Glass
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> common/spl/spl.c | 46
> +--
> include/asm-generic/global_data.h | 1 +
> include/spl.h | 24 +---
> 3 files changed, 57 insertions(+), 14 deletions(-)
>
> diff --git a/common/spl/spl.c b/common/spl/spl.c
> index 766fb3d6f4..2bc8b42027 100644
> --- a/common/spl/spl.c
> +++ b/common/spl/spl.c
> @@ -170,22 +170,20 @@ __weak void __noreturn jump_to_image_no_args(struct
> spl_image_info *spl_image)
> image_entry();
> }
>
> -int spl_init(void)
> +static int spl_common_init(bool setup_malloc)
> {
> int ret;
>
> - debug("spl_init()\n");
> -/*
> - * with CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN we set malloc_base and
> - * malloc_limit in spl_relocate_stack_gd
> - */
> -#if defined(CONFIG_SYS_MALLOC_F_LEN) && \
> - !defined(CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN)
> + debug("spl_early_init()\n");
> +
> +#if defined(CONFIG_SYS_MALLOC_F_LEN)
> + if (setup_malloc) {
> #ifdef CONFIG_MALLOC_F_ADDR
> - gd->malloc_base = CONFIG_MALLOC_F_ADDR;
> + gd->malloc_base = CONFIG_MALLOC_F_ADDR;
> #endif
> - gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
> - gd->malloc_ptr = 0;
> + gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
> + gd->malloc_ptr = 0;
> + }
> #endif
> if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) {
> ret = fdtdec_setup();
> @@ -202,6 +200,32 @@ int spl_init(void)
> return ret;
> }
> }
> +
> + return 0;
> +}
> +
> +int spl_early_init(void)
> +{
> + int ret;
> +
> + ret = spl_common_init(true);
> + if (ret)
> + return ret;
> + gd->flags |= GD_FLG_SPL_EARLY_INIT;
> +
> + return 0;
> +}
> +
> +int spl_init(void)
> +{
> + int ret;
> +
> + if (!(gd->flags & GD_FLG_SPL_EARLY_INIT)) {
> + ret = spl_common_init(
> + !IS_ENABLED(CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN));
> + if (ret)
> + return ret;
> + }
> gd->flags |= GD_FLG_SPL_INIT;
>
> return 0;
> diff --git a/include/asm-generic/global_data.h
> b/include/asm-generic/global_data.h
> index e02863dc03..5b356dd231 100644
> --- a/include/asm-generic/global_data.h
> +++ b/include/asm-generic/global_data.h
> @@ -127,5 +127,6 @@ typedef struct global_data {
> #define GD_FLG_SKIP_RELOC0x00800 /* Don't relocate */
> #define GD_FLG_RECORD0x01000 /* Record console
>*/
> #define GD_FLG_ENV_DEFAULT 0x02000 /* Default variable flag */
> +#define GD_FLG_SPL_EARLY_INIT0x04000 /* Early SPL init is done
>*/
>
> #endif /* __ASM_GENERIC_GBL_DATA_H */
> diff --git a/include/spl.h b/include/spl.h
> index bde44374ea..cdd196d187 100644
> --- a/include/spl.h
> +++ b/include/spl.h
> @@ -213,11 +213,29 @@ int spl_load_image_ext_os(struct spl_image_info
> *spl_image,
> struct blk_desc *block_dev, int partition);
>
> /**
> - * spl_init() - Set up device tree and driver model in SPL if enabled
> + * spl_early_init() - Set up device tree and driver model in SPL if enabled
> *
> * Call this function in board_init_f() if you want to use device tree and
> - * driver model early, before board_init_r() is called. This function will
> - * be called from board_init_r() if not called earlier.
> + * driver model early, before board_init_r() is called.
> + *
> + * If this is not called, then driver model will be inactive in SPL's
> + * board_init_f(), and no device tree will be available.
> + */
> +int spl_early_init(void);
> +
> +/**
> + * spl_init() - Set up device tree and driver model in SPL if enabled
> + *
> + * You can optionally call spl_early_init(), then optionally call spl_init().
> + * This function will be called from board_init_r() if not called earlier.
> + *
> + * Both spl_early_init() and spl_init() perform a similar function except
> t
Re: [U-Boot] [PATCH v2 2/8] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"
On 03/16/2017 11:11 PM, Rush, Jason A. wrote: > Marek Vasut wrote: >> On 03/14/2017 03:23 PM, Rush, Jason A. wrote: >>> Marek Vasut wrote: On 03/07/2017 04:18 PM, Rush, Jason A. wrote: > Marek Vasut wrote: >> On 03/03/2017 04:17 PM, Rush, Jason A. wrote: >>> Marek Vasut wrote: On 03/01/2017 05:36 PM, Rush, Jason A. wrote: > This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f. > > The Cadence QSPI device does not work with caching (introduced with > the bounce buffer in this commit) on the Altera SoC platform. > > Signed-off-by: Jason A. Rush Do we really need the reverts or can we just fix the commit(s) up somehow ? >>> >>> Would you prefer I squash the 2 reverts and the subsequent patch >>> together >>> as a single commit? >> >> I would prefer if you answered my question :) So let me re-iterate, can >> we incrementally fix the driver instead of doing the revert(s) ? > > I think I misunderstood your question. Could you clarify what you mean by > incrementally fix the driver? That means change it to the final form without reverting patches. >>> >>> Yes, I can definitely change this so it does not revert the patches. >> >> OK >> > Are you asking if there is a way to fix the cache issue with the CQSPI on > the > Altera SoC platform? If so, I don't know if I have the knowledge to > answer that. > Do you have any suggestions on where one would start looking to fix the > caching problem? Uh, there is a cache problem on socfpga ? Is this series working around it then ? >>> >>> Yes, there seems to be a cache issue with the CQSPI on the socfpga. And >>> yes, >>> this patch series is working around this cache issue. >> >> OK, that means I'm not accepting this series. Let's fix the cache issue >> properly. >> >>> In addition, this series >>> introduces the trigger-address DT that Linux introduced and is required by >>> the CQSPI on socfpga. >> >> Can we split this part from the patchset, so it can go in separately ? >> >>> Here's a quick recap of the cache issue and this patch series... The >>> original >>> commits used a bounce buffer implementation to fix 32-bit read alignment >>> issues with the CQSPI on a TI SoC device. The bounce buffer implementation >>> was a clean solution to the 32-bit alignment issue, but this implementation >>> returned random data from the QSPI flash on socfpga. You suggested I try >>> disabling the dcache, as you recalled some caching problem on the CQSPI in >>> the past. Running 'dcache off' solved the random data issue on socfpga >>> while using the bounce buffer implementation. >>> >>> That's when Vignesh and I decided to work around the cache problem by >>> reverting the two original commits and using a previous patch Vignesh had >>> written to fix the alignment problem. >>> >>> If I clean the series up to change it to the final form and not revert the >>> patches, is this an acceptable approach? >> >> No, if we know there is a bug and we only pile workarounds, we will end >> up with shitty code. Let's fix this properly please. >> > > I agree a workaround is no good. I have no knowledge or experience with > fixing a cache problem though, so I think someone else is going to have to > tackle this bug. Why don't you just gain that experience ? You can ask questions on the list ... > If you'd like, I can submit a separate patch for adopting the Linux DT > trigger-address property, but the CQSPI will still be broken for the socfpga > until someone fixes the cache problem with the CQSPI. I think that's still an improvement ... -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/8] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"
Marek Vasut wrote: > On 03/14/2017 03:23 PM, Rush, Jason A. wrote: >> Marek Vasut wrote: >>> On 03/07/2017 04:18 PM, Rush, Jason A. wrote: Marek Vasut wrote: > On 03/03/2017 04:17 PM, Rush, Jason A. wrote: >> Marek Vasut wrote: >>> On 03/01/2017 05:36 PM, Rush, Jason A. wrote: This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f. The Cadence QSPI device does not work with caching (introduced with the bounce buffer in this commit) on the Altera SoC platform. Signed-off-by: Jason A. Rush >>> >>> Do we really need the reverts or can we just fix the commit(s) up >>> somehow ? >>> >> >> Would you prefer I squash the 2 reverts and the subsequent patch together >> as a single commit? > > I would prefer if you answered my question :) So let me re-iterate, can > we incrementally fix the driver instead of doing the revert(s) ? I think I misunderstood your question. Could you clarify what you mean by incrementally fix the driver? >>> >>> That means change it to the final form without reverting patches. >> >> Yes, I can definitely change this so it does not revert the patches. > > OK > Are you asking if there is a way to fix the cache issue with the CQSPI on the Altera SoC platform? If so, I don't know if I have the knowledge to answer that. Do you have any suggestions on where one would start looking to fix the caching problem? >>> >>> Uh, there is a cache problem on socfpga ? Is this series working around >>> it then ? >>> >> >> Yes, there seems to be a cache issue with the CQSPI on the socfpga. And yes, >> this patch series is working around this cache issue. > > OK, that means I'm not accepting this series. Let's fix the cache issue > properly. > >> In addition, this series >> introduces the trigger-address DT that Linux introduced and is required by >> the CQSPI on socfpga. > > Can we split this part from the patchset, so it can go in separately ? > >> Here's a quick recap of the cache issue and this patch series... The original >> commits used a bounce buffer implementation to fix 32-bit read alignment >> issues with the CQSPI on a TI SoC device. The bounce buffer implementation >> was a clean solution to the 32-bit alignment issue, but this implementation >> returned random data from the QSPI flash on socfpga. You suggested I try >> disabling the dcache, as you recalled some caching problem on the CQSPI in >> the past. Running 'dcache off' solved the random data issue on socfpga >> while using the bounce buffer implementation. >> >> That's when Vignesh and I decided to work around the cache problem by >> reverting the two original commits and using a previous patch Vignesh had >> written to fix the alignment problem. >> >> If I clean the series up to change it to the final form and not revert the >> patches, is this an acceptable approach? > > No, if we know there is a bug and we only pile workarounds, we will end > up with shitty code. Let's fix this properly please. > I agree a workaround is no good. I have no knowledge or experience with fixing a cache problem though, so I think someone else is going to have to tackle this bug. If you'd like, I can submit a separate patch for adopting the Linux DT trigger-address property, but the CQSPI will still be broken for the socfpga until someone fixes the cache problem with the CQSPI. -- Regards, Jason ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 00/20] Add Intel Arria 10 SoC support
On 03/09/2017 01:26 AM, Ley Foon Tan wrote: > This is the 2nd version of patchset to adds support for Intel Arria 10 SoC. > This version mainly resolved comments from Marek in [v1]. > > This is initial patchset enables the basic support for Arria 10 and other > features will come after this. > > This series is working on top of “arm: socfpga: Move to using distro boot” > series [1] from Dalon Westergreen. > > [1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg239560.html I have to wonder, will the A10 SoCDK be usable with mainline U-Boot with just this patchset or is something else missing, like ie. the DDR driver ? -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] armv7m: add instruction & data cache support
Hi Vikas,
On 14 March 2017 at 11:27, Vikas Manocha wrote:
> This patch adds armv7m instruction & data cache support.
>
> Signed-off-by: Vikas Manocha
> cc: Christophe KERELLO
> ---
>
> Changed in v3:
> - uint32 replcaed with u32.
> - multiple read of hardware register replaced with single.
> - pointers replaced with macros for base address.
> - register names added as comment for system control block registers.
>
> Changed in v2:
> - changed strucures for memory mapped cache registers to macros
> - added lines better readability.
> - replaced magic numbers with macros.
>
> arch/arm/cpu/armv7m/Makefile | 2 +-
> arch/arm/cpu/armv7m/cache.c | 291
> ++
> arch/arm/include/asm/armv7m.h | 26 +++-
> arch/arm/lib/Makefile | 2 +
> 4 files changed, 318 insertions(+), 3 deletions(-)
> create mode 100644 arch/arm/cpu/armv7m/cache.c
>
> diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
> index aff60e8..41efe11 100644
> --- a/arch/arm/cpu/armv7m/Makefile
> +++ b/arch/arm/cpu/armv7m/Makefile
> @@ -6,4 +6,4 @@
> #
>
> extra-y := start.o
> -obj-y += cpu.o
> +obj-y += cpu.o cache.o
> diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
> new file mode 100644
> index 000..9021525
> --- /dev/null
> +++ b/arch/arm/cpu/armv7m/cache.c
> @@ -0,0 +1,291 @@
> +/*
> + * (C) Copyright 2017
> + * Vikas Manocha, ST Micoelectronics, vikas.mano...@st.com.
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
put this one below common.h
> +
> +/* Cache maintenance operation registers */
> +
> +#define IC_IALLU (V7M_CACHE_MAINT_BASE + 0x00)
> +#define INVAL_ICACHE_POU 0
> +#define IC_IMVALU (V7M_CACHE_MAINT_BASE + 0x08)
> +#define DC_IMVAC (V7M_CACHE_MAINT_BASE + 0x0C)
> +#define DC_ISW (V7M_CACHE_MAINT_BASE + 0x10)
> +#define DC_CMVAU (V7M_CACHE_MAINT_BASE + 0x14)
> +#define DC_CMVAC (V7M_CACHE_MAINT_BASE + 0x18)
> +#define DC_CSW (V7M_CACHE_MAINT_BASE + 0x1C)
> +#define DC_CIMVAC (V7M_CACHE_MAINT_BASE + 0x20)
> +#define DC_CISW(V7M_CACHE_MAINT_BASE + 0x24)
> +#define WAYS_SHIFT 30
> +#define SETS_SHIFT 5
> +
> +/* armv7m processor feature registers */
> +
> +#define CLIDR (V7M_PROC_FTR_BASE + 0x00)
> +#define CTR(V7M_PROC_FTR_BASE + 0x04)
> +#define CCSIDR (V7M_PROC_FTR_BASE + 0x08)
> +#define MASK_NUM_WAYS GENMASK(12, 3)
> +#define MASK_NUM_SETS GENMASK(27, 13)
> +#define CLINE_SIZE_MASKGENMASK(2, 0)
> +#define NUM_WAYS_SHIFT 3
> +#define NUM_SETS_SHIFT 13
> +#define CSSELR (V7M_PROC_FTR_BASE + 0x0C)
> +#define SEL_I_OR_D BIT(0)
> +
> +enum cache_type {
> + DCACHE = 0,
Do you need the =0 ?
> + ICACHE,
> +};
> +
> +/* PoU : Point of Unification, Poc: Point of Coherency */
> +enum cache_action {
> + INVALIDATE_POU, /* for i-cache invalidate by address */
> + INVALIDATE_POC, /* for d-cache invalidate by address */
> + INVALIDATE_SET_WAY, /* for d-cache invalidate by sets/ways */
> + FLUSH_POU,
> + FLUSH_POC,
> + FLUSH_SET_WAY,
> + FLUSH_INVAL_POC,
> + FLUSH_INVAL_SET_WAY,
Can you add comments for the rest?
> +};
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +struct dcache_config {
> + u32 ways;
> + u32 sets;
> +};
> +
> +static void get_cache_ways_sets(struct dcache_config *cache)
> +{
> + u32 cache_size_id = readl(CCSIDR);
blank line here
> + cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
> + cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT;
> +}
> +
> +static u32 *get_action_reg_set_ways(enum cache_action action)
Can you please add a function comment? What does this return?
> +{
> + switch (action) {
> + case INVALIDATE_SET_WAY:
> + return (u32 *)DC_ISW;
Can you drop these casts by using a C structure or by putting thecast
in the #define?
> + case FLUSH_SET_WAY:
> + return (u32 *)DC_CSW;
> + case FLUSH_INVAL_SET_WAY:
> + return (u32 *)DC_CISW;
> + default:
> + break;
> + };
> +
> + return NULL;
> +}
> +
> +static u32 *get_action_reg_range(enum cache_action action)
> +{
> + switch (action) {
> + case INVALIDATE_POU:
> + return (u32 *)IC_IMVALU;
> + case INVALIDATE_POC:
> + return (u32 *)DC_IMVAC;
> + case FLUSH_POU:
> + return (u32 *)DC_CMVAU;
> + case FLUSH_POC:
> + return (u32 *)DC_CMVAC;
> + case FLUSH_INVAL_POC:
> + return (u32 *)DC_CIMVAC;
> + default:
> + break;
> + }
> +
> + return NULL;
> +}
>
Re: [U-Boot] [PATCH 2/4] Kconfig: introduce md5sum command selection
On 14 March 2017 at 19:19, Andre Przywara wrote: > So far CONFIG_MD5SUM would need to be set by a board's include file. > Since the command is really generic, move it over to Kconfig to allow > it to be defined by either a board's defconfig, menuconfig or some > config snippet merged via mergeconfig.sh. > > Signed-off-by: Andre Przywara > --- > cmd/Kconfig | 14 ++ > lib/Kconfig | 4 > 2 files changed, 18 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] Pass empty CFLAGS on invocation of libfdt/setup.py
Hi Max, On 16 March 2017 at 12:38, Max Filippov wrote: > > When building u-boot tools in cross-build environment CFLAGS environment > variable set up for target is taken into an account when building code > for host. Set it to empty on invocation of python. > > This fixes the following build errors when cross-compiling for xtensa: > > cc1: error: unrecognized command line option "-mlongcalls" > cc1: error: unrecognized command line option "-mauto-litpools" > > Signed-off-by: Max Filippov > --- > tools/Makefile | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Simon Glass Please see below > > diff --git a/tools/Makefile b/tools/Makefile > index 1c840d7..c224e8a 100644 > --- a/tools/Makefile > +++ b/tools/Makefile > @@ -120,7 +120,7 @@ _libfdt.so-sharedobjs += $(LIBFDT_OBJS) > libfdt: > > tools/_libfdt.so: $(patsubst %.o,%.c,$(LIBFDT_OBJS)) tools/libfdt_wrap.c > - LDFLAGS="$(HOSTLDFLAGS)" python $(srctree)/lib/libfdt/setup.py \ > + LDFLAGS="$(HOSTLDFLAGS)" CFLAGS="" python > $(srctree)/lib/libfdt/setup.py \ Can we drop the "" ? > "$(_hostc_flags)" $^ > mv _libfdt.so $@ > > -- > 2.1.4 > Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] kirkwood: remove get_random_hex() and MD5 dependency
On 14 March 2017 at 19:19, Andre Przywara wrote:
> Commit 19a5944fcd62 ("mvgbe: remove setting of ethaddr within the
> driver") removed the usage of get_random_hex() from the mvgbe driver
> about six years ago. However the prototype of that function survived
> till today in some kirkwood header file.
> Remove that prototype and the CONFIG_MD5 dependency triggered by that.
>
> Signed-off-by: Andre Przywara
> ---
> arch/arm/mach-kirkwood/include/mach/config.h | 1 -
> arch/arm/mach-kirkwood/include/mach/cpu.h| 1 -
> 2 files changed, 2 deletions(-)
Reviewed-by: Simon Glass
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Re: [U-Boot] [PATCHv3 3/3] lib: move hash CONFIG options to Kconfig
Hi Tom,
On 9 March 2017 at 11:44, Tom Rini wrote:
> On Tue, Mar 07, 2017 at 11:20:08AM -0500, Tom Rini wrote:
>> Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support
>> using hardware acceleration.") created entries for CONFIG_SHA1,
>> CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL.
>> However, no defconfig has migrated to it. Complete the move by first
>> adding additional logic to various Kconfig files to select this when
>> required and then use the moveconfig tool. In many cases we can select
>> these because they are required to implement other drivers. We also
>> correct how we include the various hashing algorithms in SPL.
>>
>> This commit was generated as follows (after Kconfig additions):
>>
>> [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL
>> [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL
>>
>> Note:
>> We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously
>> because there is dependency between them.
>
> This, oddly, breaks the verified boot tests on sandbox. And I can't
> obviously see why. The u-boot.map files are identical even.
It looks like this is not U-Boot itself:
=> +build-sandbox/tools/fit_check_sign -f
u-boot/files/build-sandbox/test.fit -k u-boot/files/build-sandbox/ -k
files/build-sandbox/sandbox-u-boot.dtb
Signature check Bad (error 1)
Verifying Hash Integrity ... sha1,rsa2048:dev-
Failed to verify required signature 'key-dev'
It SHA1 somehow missing with the fit_check_sign tool with this commit?
Regards,
Simon
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Re: [U-Boot] [PATCH 3/4] Kconfig: define MD5 dependency for FIT support
On 14 March 2017 at 19:19, Andre Przywara wrote: > FIT images require MD5 support to verify image checksums. So far this > was expressed by defining a CPP symbol in image.h. Since MD5 is now a > first class Kconfig citizen, express that in Kconfig instead. > > Signed-off-by: Andre Przywara > --- > Kconfig | 1 + > include/image.h | 1 - > 2 files changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] configs: move CMD_MD5SUM definition to defconfigs
Hi Andre, On 14 March 2017 at 19:19, Andre Przywara wrote: > Boards with an apparent need for the md5sum command had the connected > config symbol defined in their board header file. > Move this over to the respective defconfig files now that md5sum is > configured via Kconfig. > (This is a manual effort, which differs from moveconfig.py, not sure > who is right here. Boards except sandbox loose the md5sum command with > moveconfig.py, though it was explicitly mentioned in their config.h's) > > Signed-off-by: Andre Przywara > --- > configs/dragonboard410c_defconfig | 1 + > configs/sandbox_defconfig | 1 + > configs/sandbox_noblk_defconfig | 1 + > configs/sandbox_spl_defconfig | 1 + > configs/sh7752evb_defconfig | 1 + > configs/sh7753evb_defconfig | 1 + > configs/sh7757lcr_defconfig | 1 + > include/configs/dragonboard410c.h | 4 > include/configs/sandbox.h | 1 - > include/configs/sh7752evb.h | 2 -- > include/configs/sh7753evb.h | 2 -- > include/configs/sh7757lcr.h | 2 -- > scripts/config_whitelist.txt | 3 --- > 13 files changed, 7 insertions(+), 14 deletions(-) Reviewed-by: Simon Glass That's odd - did you check that these boards actually do end up with it. I've not seen that problem with moveconfig.py before. Regards, SImon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] armv7m: add instruction & data cache support
On 03/16/2017 10:39 PM, vikas wrote:
> Thanks Marek,
>
> On 03/16/2017 02:40 PM, Marek Vasut wrote:
>> On 03/13/2017 10:45 PM, vikas wrote:
>>> Thanks Marek,
>>>
>>> On 03/11/2017 10:02 PM, Marek Vasut wrote:
On 03/12/2017 01:13 AM, Vikas Manocha wrote:
> This patch adds armv7m instruction & data cache support.
>
> Signed-off-by: Vikas Manocha
> ---
>
> Changed in v2:
> - changed strucures for memory mapped cache registers to MACROs
Macro is written in lowercase, FYI ...
>>>
>>> ok.
>>>
> - added lines better readability.
> - replaced magic numbers with MACROs.
>
> arch/arm/cpu/armv7m/Makefile | 2 +-
> arch/arm/cpu/armv7m/cache.c | 294
> ++
> arch/arm/include/asm/armv7m.h | 26 +++-
> arch/arm/lib/Makefile | 2 +
> 4 files changed, 321 insertions(+), 3 deletions(-)
> create mode 100644 arch/arm/cpu/armv7m/cache.c
>
> diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
> index aff60e8..41efe11 100644
> --- a/arch/arm/cpu/armv7m/Makefile
> +++ b/arch/arm/cpu/armv7m/Makefile
> @@ -6,4 +6,4 @@
> #
>
> extra-y := start.o
> -obj-y += cpu.o
> +obj-y += cpu.o cache.o
> diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
> new file mode 100644
> index 000..cc17366
> --- /dev/null
> +++ b/arch/arm/cpu/armv7m/cache.c
> @@ -0,0 +1,294 @@
> +/*
> + * (C) Copyright 2017
> + * Vikas Manocha, ST Micoelectronics, vikas.mano...@st.com.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +/* Cache maintenance operation registers */
> +
> +#define IC_IALLU 0x00
> +#define INVAL_ICACHE_POU 0
> +
> +#define IC_IMVALU0x08
> +#define DC_IMVAC 0x0C
> +#define DC_ISW 0x10
> +#define DC_CMVAU 0x14
> +#define DC_CMVAC 0x18
> +#define DC_CSW 0x1C
> +#define DC_CIMVAC0x20
> +#define DC_CISW 0x24
Would be nice to have some more distinguishing name here, so one can
easily git grep for those reg names and make sense of their name without
reading the datasheet .
>>>
>>> these names are consistent with the arch manual to help relating them with
>>> manual.
>>
>> Clearly, I'm not getting through here. Something like CACHE_V7M_REG_FOO
>> is much easier to grep for than FOO.
>
> ok, i will make them V7M_IC_* for instruction cache & V7M_DC_* for data cache
> specific regs.
Which is still pretty cryptic ...
> +#define WAYS_SHIFT 30
> +#define SETS_SHIFT 5
Is this always 30 and 5 , on all CPUs ?
>>>
>>> Yes for all armv7m arch.
>>
>> OK
>>
> +/* armv7m processor feature registers */
> +
> +#define CLIDR0x00
> +#define CTR 0x04
> +
> +#define CCSIDR 0x08
> +#define MASK_NUM_WAYSGENMASK(12, 3)
> +#define MASK_NUM_SETSGENMASK(27, 13)
> +#define NUM_WAYS_SHIFT 3
> +#define NUM_SETS_SHIFT 13
> +
> +#define CSSELR 0x0C
> +#define SEL_I_OR_D BIT(0)
> +
> +void *const v7m_cache_maint = (void *)V7M_CACHE_MAINT_BASE;
> +void *const v7m_processor = (void *)V7M_PROC_FTR_BASE;
Needed ? Why don't you just use the macro directly ?
>>>
>>> Yes it is possible. I was trying to avoid typecasting macro to pointer each
>>> time before passing to
>>> functions required it as address pointer.
>>
>> Eh? This is just a value, you can use it directly ...
>
> done in v3, i will send the v4 with rest of the modifications.
Could you give the patch a few days on the list to gather feedback ? I
believe I warned you about this before already, but the maintainers are
already saturated by patches, sending one revision after the other does
NOT help anyone and only congests the maintainers further.
>> [...]
>>
> + debug("cache line size is %d\n", size);
> +
> + return size;
> +}
> +
> +int action_cache_range(enum cache_action action, uint32_t start_addr,
> +int64_t size)
static ?
>>>
>>> this function at present is not being used as we are invalidating/flushing
>>> all cache but helper function
>>> to flush/invalidate parts/range of cache.
>>> Making it static leads to "function not used" compilation warning.
>>> attribute "unused" can be used also
>>> but not sure...
>>> Please suggest.
>>
>> So basically this is a workaround to silence the compiler which
>> correctly warns you about dead code ? I think you know what to do (hint:
>> remove dead code ...)
>
> ok.
>
>>
You're never checking if s
Re: [U-Boot] [PATCH v2 1/2] armv7m: add instruction & data cache support
Thanks Marek,
On 03/16/2017 02:40 PM, Marek Vasut wrote:
> On 03/13/2017 10:45 PM, vikas wrote:
>> Thanks Marek,
>>
>> On 03/11/2017 10:02 PM, Marek Vasut wrote:
>>> On 03/12/2017 01:13 AM, Vikas Manocha wrote:
This patch adds armv7m instruction & data cache support.
Signed-off-by: Vikas Manocha
---
Changed in v2:
- changed strucures for memory mapped cache registers to MACROs
>>>
>>> Macro is written in lowercase, FYI ...
>>
>> ok.
>>
>>>
- added lines better readability.
- replaced magic numbers with MACROs.
arch/arm/cpu/armv7m/Makefile | 2 +-
arch/arm/cpu/armv7m/cache.c | 294
++
arch/arm/include/asm/armv7m.h | 26 +++-
arch/arm/lib/Makefile | 2 +
4 files changed, 321 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/cpu/armv7m/cache.c
diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
index aff60e8..41efe11 100644
--- a/arch/arm/cpu/armv7m/Makefile
+++ b/arch/arm/cpu/armv7m/Makefile
@@ -6,4 +6,4 @@
#
extra-y := start.o
-obj-y += cpu.o
+obj-y += cpu.o cache.o
diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
new file mode 100644
index 000..cc17366
--- /dev/null
+++ b/arch/arm/cpu/armv7m/cache.c
@@ -0,0 +1,294 @@
+/*
+ * (C) Copyright 2017
+ * Vikas Manocha, ST Micoelectronics, vikas.mano...@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+/* Cache maintenance operation registers */
+
+#define IC_IALLU 0x00
+#define INVAL_ICACHE_POU 0
+
+#define IC_IMVALU 0x08
+#define DC_IMVAC 0x0C
+#define DC_ISW0x10
+#define DC_CMVAU 0x14
+#define DC_CMVAC 0x18
+#define DC_CSW0x1C
+#define DC_CIMVAC 0x20
+#define DC_CISW 0x24
>>>
>>> Would be nice to have some more distinguishing name here, so one can
>>> easily git grep for those reg names and make sense of their name without
>>> reading the datasheet .
>>
>> these names are consistent with the arch manual to help relating them with
>> manual.
>
> Clearly, I'm not getting through here. Something like CACHE_V7M_REG_FOO
> is much easier to grep for than FOO.
ok, i will make them V7M_IC_* for instruction cache & V7M_DC_* for data cache
specific regs.
>
+#define WAYS_SHIFT30
+#define SETS_SHIFT5
>>>
>>> Is this always 30 and 5 , on all CPUs ?
>>
>> Yes for all armv7m arch.
>
> OK
>
+/* armv7m processor feature registers */
+
+#define CLIDR 0x00
+#define CTR 0x04
+
+#define CCSIDR0x08
+#define MASK_NUM_WAYS GENMASK(12, 3)
+#define MASK_NUM_SETS GENMASK(27, 13)
+#define NUM_WAYS_SHIFT3
+#define NUM_SETS_SHIFT13
+
+#define CSSELR0x0C
+#define SEL_I_OR_DBIT(0)
+
+void *const v7m_cache_maint = (void *)V7M_CACHE_MAINT_BASE;
+void *const v7m_processor = (void *)V7M_PROC_FTR_BASE;
>>>
>>> Needed ? Why don't you just use the macro directly ?
>>
>> Yes it is possible. I was trying to avoid typecasting macro to pointer each
>> time before passing to
>> functions required it as address pointer.
>
> Eh? This is just a value, you can use it directly ...
done in v3, i will send the v4 with rest of the modifications.
>
> [...]
>
+ debug("cache line size is %d\n", size);
+
+ return size;
+}
+
+int action_cache_range(enum cache_action action, uint32_t start_addr,
+ int64_t size)
>>>
>>> static ?
>>
>> this function at present is not being used as we are invalidating/flushing
>> all cache but helper function
>> to flush/invalidate parts/range of cache.
>> Making it static leads to "function not used" compilation warning. attribute
>> "unused" can be used also
>> but not sure...
>> Please suggest.
>
> So basically this is a workaround to silence the compiler which
> correctly warns you about dead code ? I think you know what to do (hint:
> remove dead code ...)
ok.
>
>>>
>>> You're never checking if start_addr and size are cache-line aligned ,
>>> see arm926ejs and armv7a
>>>
+{
+ uint32_t cline_size;
+ uint32_t *action_reg;
>>>
>>> u32 , fix globally
>>>
+ enum cache_type type;
+
+ action_reg = get_action_reg_range(action);
+ if (!action_reg)
+ return -EINVAL;
+ if (action == INVALIDATE_POU)
+ type = ICACHE;
+ else
+ type = DCACHE;
+
+ /* cache line size is minium size for
Re: [U-Boot] [PATCH 29/31] ARM: dts: k2g: Add DT support for K2G Industrial Communication Engine evm
On 03/09/2017 07:09 AM, Tom Rini wrote: > On Thu, Mar 02, 2017 at 01:04:33PM -0600, Franklin S Cooper Jr wrote: > >> Add basic DT support for K2G ICE evm. Only minimal peripherals are >> supported to allow console output and MMC boot. >> >> Signed-off-by: Franklin S Cooper Jr >> --- >> arch/arm/dts/Makefile | 3 ++- >> arch/arm/dts/keystone-k2g-ice.dts | 25 + > > Has this been pushed up to Linux yet? Thanks! Not yet. > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 28/31] ARM: dts: k2g: Disable netcp by default
On 03/09/2017 07:09 AM, Tom Rini wrote: > On Thu, Mar 02, 2017 at 01:04:32PM -0600, Franklin S Cooper Jr wrote: > >> Disable netcp by default like all other peripherals in the dtsi file. >> Enable the peripheral explicitly in the board specific dts file. >> >> Signed-off-by: Franklin S Cooper Jr > > Has this been pushed up to Linux yet? Thanks! Only an extremely bare minimal dts exist in upstream. So this patch isn't applicable. > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] Pass empty CFLAGS on invocation of libfdt/setup.py
On Thu, Mar 16, 2017 at 2:11 PM, Tom Rini wrote: > On Thu, Mar 16, 2017 at 11:38:00AM -0700, Max Filippov wrote: > >> When building u-boot tools in cross-build environment CFLAGS environment >> variable set up for target is taken into an account when building code >> for host. Set it to empty on invocation of python. >> >> This fixes the following build errors when cross-compiling for xtensa: >> >> cc1: error: unrecognized command line option "-mlongcalls" >> cc1: error: unrecognized command line option "-mauto-litpools" >> >> Signed-off-by: Max Filippov >> --- >> tools/Makefile | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/tools/Makefile b/tools/Makefile >> index 1c840d7..c224e8a 100644 >> --- a/tools/Makefile >> +++ b/tools/Makefile >> @@ -120,7 +120,7 @@ _libfdt.so-sharedobjs += $(LIBFDT_OBJS) >> libfdt: >> >> tools/_libfdt.so: $(patsubst %.o,%.c,$(LIBFDT_OBJS)) tools/libfdt_wrap.c >> - LDFLAGS="$(HOSTLDFLAGS)" python $(srctree)/lib/libfdt/setup.py \ >> + LDFLAGS="$(HOSTLDFLAGS)" CFLAGS="" python >> $(srctree)/lib/libfdt/setup.py \ > > I think we need to be passing in HOSTCFLAGS or we'll end up being broken > on certain other cases (which are broken today I suspect). I believe that the $(_hostc_flags) in the next line is meant to do exactly that. There's code in the lib/libfdt/setup.py that uses that parameter. -- Thanks. -- Max ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 17/17] aspeed: Network Driver configuration for EVB
Enable Network Driver along with network related commands -- ping, dhcp,
mii -- in ast2500 Eval Board's defconfig.
Add MAC devices' configuration to Eval Board Device Tree.
Signed-off-by: Maxim Sloyko
---
---
arch/arm/dts/ast2500-evb.dts | 14 ++
configs/evb-ast2500_defconfig | 7 +++
2 files changed, 21 insertions(+)
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 723941ac0b..c47ad684a5 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -36,3 +36,17 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&mac0 {
+ compatible = "aspeed,ast2500-nic";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mac1link_default>, <&pinctrl_mdio1_default>;
+};
+
+&mac1 {
+ compatible = "aspeed,ast2500-nic";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mac2link_default>, <&pinctrl_mdio2_default>;
+};
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 08b5f85a34..d1548f7f3c 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -21,3 +21,10 @@ CONFIG_PINCTRL=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_ASPEED=y
CONFIG_CMD_I2C=y
+CONFIG_DM_ETH=y
+CONFIG_AST_NIC=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_MII=y
+CONFIG_CMD_MII=y
--
2.12.0.367.g23dc2f6d3c-goog
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 18/31] defconfig: keystone2: Enable U-boot runtime DTB detection
On 03/09/2017 07:08 AM, Tom Rini wrote: > On Thu, Mar 02, 2017 at 01:04:22PM -0600, Franklin S Cooper Jr wrote: > >> Enable various config options to allow U-boot at runtime to select the >> proper dtb to use from the list of dtb's within the FIT image. >> >> Signed-off-by: Franklin S Cooper Jr > > ... but is the goal here to eventually support more than one EVM in a > single binary, on all of these platforms? Yes the goal is to have a single binary that support multiple evms for a given SoC family. Similar to what we are doing for OMAP devices except using U-boot instead of SPL. > > Reviewed-by: Tom Rini > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot 0/3] introduce Rockchip rockusb
On 03/15/2017 08:56 AM, Eddie Cai wrote: > rockusb is a protocol run between host pc and device. it help people get > device > info, flash image to device. this patch implement rockusb on device side. What is the benefit of this yet-another NIH protocol compared to ie. DFU/UMS/Thor/Fastboot ? > Eddie Cai (3): > drivers: usb: gadget: add the rockusb gadget > cmd: add rockusb command > rockchip: rk3288: enable rockusb support on rk3288 based device > > cmd/Kconfig | 12 + > cmd/Makefile| 1 + > cmd/rockusb.c | 79 > drivers/usb/gadget/Makefile | 1 + > drivers/usb/gadget/f_rockusb.c | 801 > > include/configs/rk3288_common.h | 4 + > include/rockusb.h | 13 + > 7 files changed, 911 insertions(+) > create mode 100644 cmd/rockusb.c > create mode 100644 drivers/usb/gadget/f_rockusb.c > create mode 100644 include/rockusb.h > -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/8] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"
On 03/14/2017 03:23 PM, Rush, Jason A. wrote: > Marek Vasut wrote: >> On 03/07/2017 04:18 PM, Rush, Jason A. wrote: >>> Marek Vasut wrote: On 03/03/2017 04:17 PM, Rush, Jason A. wrote: > Marek Vasut wrote: >> On 03/01/2017 05:36 PM, Rush, Jason A. wrote: >>> This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f. >>> >>> The Cadence QSPI device does not work with caching (introduced with >>> the bounce buffer in this commit) on the Altera SoC platform. >>> >>> Signed-off-by: Jason A. Rush >> >> Do we really need the reverts or can we just fix the commit(s) up >> somehow ? >> > > Would you prefer I squash the 2 reverts and the subsequent patch together > as a single commit? I would prefer if you answered my question :) So let me re-iterate, can we incrementally fix the driver instead of doing the revert(s) ? >>> >>> I think I misunderstood your question. Could you clarify what you mean by >>> incrementally fix the driver? >> >> That means change it to the final form without reverting patches. > > Yes, I can definitely change this so it does not revert the patches. OK >>> Are you asking if there is a way to fix the cache issue with the CQSPI on >>> the >>> Altera SoC platform? If so, I don't know if I have the knowledge to answer >>> that. >>> Do you have any suggestions on where one would start looking to fix the >>> caching problem? >> >> Uh, there is a cache problem on socfpga ? Is this series working around >> it then ? >> > > Yes, there seems to be a cache issue with the CQSPI on the socfpga. And yes, > this patch series is working around this cache issue. OK, that means I'm not accepting this series. Let's fix the cache issue properly. > In addition, this series > introduces the trigger-address DT that Linux introduced and is required by > the CQSPI on socfpga. Can we split this part from the patchset, so it can go in separately ? > Here's a quick recap of the cache issue and this patch series... The original > commits used a bounce buffer implementation to fix 32-bit read alignment > issues with the CQSPI on a TI SoC device. The bounce buffer implementation > was a clean solution to the 32-bit alignment issue, but this implementation > returned random data from the QSPI flash on socfpga. You suggested I try > disabling the dcache, as you recalled some caching problem on the CQSPI in > the past. Running 'dcache off' solved the random data issue on socfpga > while using the bounce buffer implementation. > > That's when Vignesh and I decided to work around the cache problem by > reverting the two original commits and using a previous patch Vignesh had > written to fix the alignment problem. > > If I clean the series up to change it to the final form and not revert the > patches, is this an acceptable approach? No, if we know there is a bug and we only pile workarounds, we will end up with shitty code. Let's fix this properly please. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 14/17] aspeed: Refactor SCU to use consistent mask & shift
Refactor SCU header to use consistent Mask & Shift values.
Now, consistently, to read value from SCU register, mask needs
to be applied before shift.
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 12
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 5 ++--
drivers/clk/aspeed/clk_ast2500.c | 39 +-
3 files changed, 27 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index fe877b5430..590aed2f6c 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -8,8 +8,8 @@
#define SCU_UNLOCK_VALUE 0x1688a8a8
-#define SCU_HWSTRAP_VGAMEM_MASK3
#define SCU_HWSTRAP_VGAMEM_SHIFT 2
+#define SCU_HWSTRAP_VGAMEM_MASK(3 << SCU_HWSTRAP_VGAMEM_SHIFT)
#define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
#define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
#define SCU_HWSTRAP_DDR4 (1 << 24)
@@ -18,17 +18,17 @@
#define SCU_MPLL_DENUM_SHIFT 0
#define SCU_MPLL_DENUM_MASK0x1f
#define SCU_MPLL_NUM_SHIFT 5
-#define SCU_MPLL_NUM_MASK 0xff
+#define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT)
#define SCU_MPLL_POST_SHIFT13
-#define SCU_MPLL_POST_MASK 0x3f
+#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
#define SCU_PCLK_DIV_SHIFT 23
-#define SCU_PCLK_DIV_MASK 7
+#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT)
#define SCU_HPLL_DENUM_SHIFT 0
#define SCU_HPLL_DENUM_MASK0x1f
#define SCU_HPLL_NUM_SHIFT 5
-#define SCU_HPLL_NUM_MASK 0xff
+#define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT)
#define SCU_HPLL_POST_SHIFT13
-#define SCU_HPLL_POST_MASK 0x3f
+#define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT)
#define SCU_MACCLK_SHIFT 16
#define SCU_MACCLK_MASK(7 << SCU_MACCLK_SHIFT)
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index efcf452b17..6383f727f2 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -183,9 +183,8 @@ static int ast2500_sdrammc_ddr4_calibrate_vref(struct
dram_info *info)
static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
{
size_t vga_mem_size_base = 8 * 1024 * 1024;
- u32 vga_hwconf = (readl(&info->scu->hwstrap)
- >> SCU_HWSTRAP_VGAMEM_SHIFT)
- & SCU_HWSTRAP_VGAMEM_MASK;
+ u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK)
+ >> SCU_HWSTRAP_VGAMEM_SHIFT;
return vga_mem_size_base << vga_hwconf;
}
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 7b4b5c64ac..ccf47a1da1 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -52,11 +52,11 @@ struct ast2500_div_config {
*/
static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
{
- const ulong num = (mpll_reg >> SCU_MPLL_NUM_SHIFT) & SCU_MPLL_NUM_MASK;
- const ulong denum = (mpll_reg >> SCU_MPLL_DENUM_SHIFT)
- & SCU_MPLL_DENUM_MASK;
- const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT)
- & SCU_MPLL_POST_MASK;
+ const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
+ const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
+ >> SCU_MPLL_DENUM_SHIFT;
+ const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
+ >> SCU_MPLL_POST_SHIFT;
return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}
@@ -67,11 +67,11 @@ static ulong ast2500_get_mpll_rate(ulong clkin, u32
mpll_reg)
*/
static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
{
- const ulong num = (hpll_reg >> SCU_HPLL_NUM_SHIFT) & SCU_HPLL_NUM_MASK;
- const ulong denum = (hpll_reg >> SCU_HPLL_DENUM_SHIFT)
- & SCU_HPLL_DENUM_MASK;
- const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT)
- & SCU_HPLL_POST_MASK;
+ const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
+ const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
+ >> SCU_HPLL_DENUM_SHIFT;
+ const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
+ >> SCU_HPLL_POST_SHIFT;
return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}
@@ -136,11 +136,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
case BCLK_PCLK:
{
ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
-
[U-Boot] [PATCH 15/17] aspeed: Cleanup ast2500-u-boot.dtsi Device Tree
Remove unnecessary apb and ahb nodes and just override necessary
nodes/values.
Signed-off-by: Maxim Sloyko
---
arch/arm/dts/ast2500-u-boot.dtsi | 41
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index f826646095..7f80bad7d0 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -34,32 +34,33 @@
apb {
u-boot,dm-pre-reloc;
+ };
- timer: timer@1e782000 {
- u-boot,dm-pre-reloc;
- };
+ };
+};
- uart1: serial@1e783000 {
- clocks = <&scu PCLK_UART1>;
- };
+&uart1 {
+ clocks = <&scu PCLK_UART1>;
+};
- uart2: serial@1e78d000 {
- clocks = <&scu PCLK_UART2>;
- };
+&uart2 {
+ clocks = <&scu PCLK_UART2>;
+};
- uart3: serial@1e78e000 {
- clocks = <&scu PCLK_UART3>;
- };
+&uart3 {
+ clocks = <&scu PCLK_UART3>;
+};
- uart4: serial@1e78f000 {
- clocks = <&scu PCLK_UART4>;
- };
+&uart4 {
+ clocks = <&scu PCLK_UART4>;
+};
- uart5: serial@1e784000 {
- clocks = <&scu PCLK_UART5>;
- };
- };
- };
+&uart5 {
+ clocks = <&scu PCLK_UART5>;
+};
+
+&timer {
+ u-boot,dm-pre-reloc;
};
&mac0 {
--
2.12.0.367.g23dc2f6d3c-goog
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 16/17] aspeed: Add AST2500/AST2400 compatible NIC Driver
The device that Aspeed uses is basically Faraday FTGMAC100, but with
some differences here and there. Since I don't have access to a properly
implemented FTGMAC100 though, I can't really test it and so I don't
feel comfortable claiming compatibility, even though I reused a lot of
FTGMAC100 driver code.
Signed-off-by: Maxim Sloyko
---
drivers/net/Kconfig | 8 +
drivers/net/Makefile | 1 +
drivers/net/ast_nic.c | 584 ++
drivers/net/ast_nic.h | 198 +
4 files changed, 791 insertions(+)
create mode 100644 drivers/net/ast_nic.c
create mode 100644 drivers/net/ast_nic.h
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 70e36611ea..6de8b35d9f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -208,4 +208,12 @@ config GMAC_ROCKCHIP
This driver provides Rockchip SoCs network support based on the
Synopsys Designware driver.
+config AST_NIC
+ bool "Support Aspeed ast2500/ast2400 NIC"
+ depends on DM_ETH
+ help
+ This driver provides support for ast2500/ast2400 network devices.
+ It uses Driver Model and so can support multiple devices on the same
SoC.
+ The device itself is basically a variation of Faraday FTGMAC100.
+
endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 2493a48b88..792bebb9cc 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -78,3 +78,4 @@ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
obj-$(CONFIG_VSC9953) += vsc9953.o
obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_AST_NIC) += ast_nic.o
diff --git a/drivers/net/ast_nic.c b/drivers/net/ast_nic.c
new file mode 100644
index 00..881d20151c
--- /dev/null
+++ b/drivers/net/ast_nic.c
@@ -0,0 +1,584 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang
+ *
+ * (C) Copyright 2010 Andes Technology
+ * Macpaul Lin
+ *
+ * Copyright 2017 Google Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * This device is basically Faraday FTGMAC100, with some differences,
+ * which do not seem to be very big, but are in very random places, like
+ * some registers removed and completely different ones put in their place.
+ */
+
+#include
+#include
+#include
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#include
+#endif
+#include
+#include
+#include
+#include "ast_nic.h"
+
+#define ETH_ZLEN 60
+#define RBSR_DEFAULT_VALUE 0x640
+
+#define PKTBUFSTX 4
+
+#define MAX_PHY_ADDR 32
+
+struct ast_nic_xdes {
+ u32 des[4];
+} __aligned(16);
+
+struct ast_nic_xdes ast_txdes[PKTBUFSTX];
+struct ast_nic_xdes ast_rxdes[PKTBUFSRX];
+
+struct ast_nic_priv {
+ struct ast_nic_xdes *txdes;
+ struct ast_nic_xdes *rxdes;
+ struct ast_nic_regs *regs;
+ int tx_index;
+ int rx_index;
+ int phy_addr;
+};
+
+static int ast_nic_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ast_nic_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *platdata = dev_get_platdata(dev);
+
+ priv->regs = dev_get_addr_ptr(dev);
+ priv->txdes = ast_txdes;
+ priv->rxdes = ast_rxdes;
+ platdata->iobase = (phys_addr_t)priv->regs;
+
+ return 0;
+}
+
+static void ast_nic_reset(struct udevice *dev)
+{
+ struct ast_nic_priv *priv = dev_get_priv(dev);
+
+ setbits_le32(&priv->regs->maccr, MAC_MACCR_SW_RST);
+ while (readl(&priv->regs->maccr) & MAC_MACCR_SW_RST)
+ ;
+ /*
+* Only needed for ast2400, for ast2500 this is the no-op,
+* because the register is marked read-only.
+*/
+ setbits_le32(&priv->regs->fear0, MAC_FEAR_NEW_MD_IFACE);
+}
+
+static int ast_nic_phy_read(struct udevice *dev, int phy_addr,
+ int regnum, u16 *value)
+{
+ struct ast_nic_priv *priv = dev_get_priv(dev);
+ int phycr;
+ int i;
+
+ phycr = MAC_PHYCR_FIRE | MAC_PHYCR_ST_22 | MAC_PHYCR_READ |
+ (phy_addr << MAC_PHYCR_PHYAD_SHIFT) |
+ (regnum << MAC_PHYCR_REGAD_SHIFT);
+
+ writel(phycr, &priv->regs->phycr);
+
+ for (i = 0; i < 10; i++) {
+ phycr = readl(&priv->regs->phycr);
+
+ if ((phycr & MAC_PHYCR_FIRE) == 0) {
+ int data;
+
+ data = readl(&priv->regs->phydata);
+ *value = (data & MAC_PHYDATA_MIIRDATA_MASK) >>
+ MAC_PHYDATA_MIIRDATA_SHIFT;
+
+ return 0;
+ }
+
+ mdelay(10);
+ }
+
+ debug("mdio read timed out\n");
+ return -ETIMEDOUT;
+}
+
+static int ast_nic_phy_write(struct udevice *dev, int phy_addr,
+ int regnum, u16 value)
+{
+ struct ast_nic_priv *priv = dev_get_priv(dev);
+ int phycr;
+ int i;
+
+ phycr = (value << MAC_PHYDATA_MIIWDATA_SHIFT) |
+ MAC_PHYCR_FI
Re: [U-Boot] [PATCH v2 1/2] armv7m: add instruction & data cache support
On 03/13/2017 10:45 PM, vikas wrote:
> Thanks Marek,
>
> On 03/11/2017 10:02 PM, Marek Vasut wrote:
>> On 03/12/2017 01:13 AM, Vikas Manocha wrote:
>>> This patch adds armv7m instruction & data cache support.
>>>
>>> Signed-off-by: Vikas Manocha
>>> ---
>>>
>>> Changed in v2:
>>> - changed strucures for memory mapped cache registers to MACROs
>>
>> Macro is written in lowercase, FYI ...
>
> ok.
>
>>
>>> - added lines better readability.
>>> - replaced magic numbers with MACROs.
>>>
>>> arch/arm/cpu/armv7m/Makefile | 2 +-
>>> arch/arm/cpu/armv7m/cache.c | 294
>>> ++
>>> arch/arm/include/asm/armv7m.h | 26 +++-
>>> arch/arm/lib/Makefile | 2 +
>>> 4 files changed, 321 insertions(+), 3 deletions(-)
>>> create mode 100644 arch/arm/cpu/armv7m/cache.c
>>>
>>> diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
>>> index aff60e8..41efe11 100644
>>> --- a/arch/arm/cpu/armv7m/Makefile
>>> +++ b/arch/arm/cpu/armv7m/Makefile
>>> @@ -6,4 +6,4 @@
>>> #
>>>
>>> extra-y := start.o
>>> -obj-y += cpu.o
>>> +obj-y += cpu.o cache.o
>>> diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
>>> new file mode 100644
>>> index 000..cc17366
>>> --- /dev/null
>>> +++ b/arch/arm/cpu/armv7m/cache.c
>>> @@ -0,0 +1,294 @@
>>> +/*
>>> + * (C) Copyright 2017
>>> + * Vikas Manocha, ST Micoelectronics, vikas.mano...@st.com.
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0+
>>> + */
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +/* Cache maintenance operation registers */
>>> +
>>> +#define IC_IALLU 0x00
>>> +#define INVAL_ICACHE_POU 0
>>> +
>>> +#define IC_IMVALU 0x08
>>> +#define DC_IMVAC 0x0C
>>> +#define DC_ISW 0x10
>>> +#define DC_CMVAU 0x14
>>> +#define DC_CMVAC 0x18
>>> +#define DC_CSW 0x1C
>>> +#define DC_CIMVAC 0x20
>>> +#define DC_CISW0x24
>>
>> Would be nice to have some more distinguishing name here, so one can
>> easily git grep for those reg names and make sense of their name without
>> reading the datasheet .
>
> these names are consistent with the arch manual to help relating them with
> manual.
Clearly, I'm not getting through here. Something like CACHE_V7M_REG_FOO
is much easier to grep for than FOO.
>>> +#define WAYS_SHIFT 30
>>> +#define SETS_SHIFT 5
>>
>> Is this always 30 and 5 , on all CPUs ?
>
> Yes for all armv7m arch.
OK
>>> +/* armv7m processor feature registers */
>>> +
>>> +#define CLIDR 0x00
>>> +#define CTR0x04
>>> +
>>> +#define CCSIDR 0x08
>>> +#define MASK_NUM_WAYS GENMASK(12, 3)
>>> +#define MASK_NUM_SETS GENMASK(27, 13)
>>> +#define NUM_WAYS_SHIFT 3
>>> +#define NUM_SETS_SHIFT 13
>>> +
>>> +#define CSSELR 0x0C
>>> +#define SEL_I_OR_D BIT(0)
>>> +
>>> +void *const v7m_cache_maint = (void *)V7M_CACHE_MAINT_BASE;
>>> +void *const v7m_processor = (void *)V7M_PROC_FTR_BASE;
>>
>> Needed ? Why don't you just use the macro directly ?
>
> Yes it is possible. I was trying to avoid typecasting macro to pointer each
> time before passing to
> functions required it as address pointer.
Eh? This is just a value, you can use it directly ...
[...]
>>> + debug("cache line size is %d\n", size);
>>> +
>>> + return size;
>>> +}
>>> +
>>> +int action_cache_range(enum cache_action action, uint32_t start_addr,
>>> + int64_t size)
>>
>> static ?
>
> this function at present is not being used as we are invalidating/flushing
> all cache but helper function
> to flush/invalidate parts/range of cache.
> Making it static leads to "function not used" compilation warning. attribute
> "unused" can be used also
> but not sure...
> Please suggest.
So basically this is a workaround to silence the compiler which
correctly warns you about dead code ? I think you know what to do (hint:
remove dead code ...)
>>
>> You're never checking if start_addr and size are cache-line aligned ,
>> see arm926ejs and armv7a
>>
>>> +{
>>> + uint32_t cline_size;
>>> + uint32_t *action_reg;
>>
>> u32 , fix globally
>>
>>> + enum cache_type type;
>>> +
>>> + action_reg = get_action_reg_range(action);
>>> + if (!action_reg)
>>> + return -EINVAL;
>>> + if (action == INVALIDATE_POU)
>>> + type = ICACHE;
>>> + else
>>> + type = DCACHE;
>>> +
>>> + /* cache line size is minium size for the cache action */
>>> + cline_size = get_cline_size(type);
>>> + do {
>>> + writel(start_addr, action_reg);
>>> + size -= cline_size;
>>> + start_addr += cline_size;
>>> + } while (size > cline_size);
>>> + debug("cache action on range done\n");
>>> + dsb();
>>> + isb();
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int action_dcache_a
[U-Boot] [PATCH 12/17] aspeed: Enable I2C in EVB defconfig
Enable I2C driver in ast2500 Eval Board defconfig. Also enable i2c command. Signed-off-by: Maxim Sloyko --- configs/evb-ast2500_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index f8ef9b779c..08b5f85a34 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -18,3 +18,6 @@ CONFIG_TIMER=y CONFIG_WDT=y CONFIG_DM_RESET=y CONFIG_PINCTRL=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_ASPEED=y +CONFIG_CMD_I2C=y -- 2.12.0.367.g23dc2f6d3c-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 11/17] aspeed: Add I2C Driver
Add Device Model based I2C driver for ast2500/ast2400 SoCs.
The driver is very limited, it only supports master mode and
synchronous byte-by-byte reads/writes, no DMA or Pool Buffers.
Signed-off-by: Maxim Sloyko
---
drivers/i2c/Kconfig | 9 ++
drivers/i2c/Makefile | 1 +
drivers/i2c/ast_i2c.c | 355 ++
drivers/i2c/ast_i2c.h | 132 +++
4 files changed, 497 insertions(+)
create mode 100644 drivers/i2c/ast_i2c.c
create mode 100644 drivers/i2c/ast_i2c.h
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 39f62daf5d..e661a308b0 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -100,6 +100,15 @@ config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
enable status register. This config option can be enabled in such
cases.
+config SYS_I2C_ASPEED
+ bool "Aspeed I2C Controller"
+ depends on DM_I2C && ARCH_ASPEED
+ help
+ Say yes here to select Aspeed I2C Host Controller. The driver
+ supports AST2500 and AST2400 controllers, but is very limited.
+ Only single master mode is supported and only byte-by-byte
+ synchronous reads and writes are supported, no Pool Buffers or DMA.
+
config SYS_I2C_INTEL
bool "Intel I2C/SMBUS driver"
depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 7c86198863..229fd476db 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
+obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
new file mode 100644
index 00..0b60b08cf2
--- /dev/null
+++ b/drivers/i2c/ast_i2c.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2012-2020 ASPEED Technology Inc.
+ * Copyright 2016 IBM Corporation
+ * Copyright 2017 Google, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "ast_i2c.h"
+
+#define I2C_TIMEOUT_US 10
+#define I2C_SLEEP_STEP_US 20
+
+#define HIGHSPEED_TTIMEOUT 3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Device private data
+ */
+struct ast_i2c_priv {
+ /* This device's clock */
+ struct clk clk;
+ /* Device registers */
+ struct ast_i2c_regs *regs;
+ /* I2C speed in Hz */
+ int speed;
+};
+
+/*
+ * Given desired divider ratio, return the value that needs to be set
+ * in Clock and AC Timing Control register
+ */
+static u32 get_clk_reg_val(ulong divider_ratio)
+{
+ ulong inc = 0, div;
+ ulong scl_low, scl_high, data;
+
+ for (div = 0; divider_ratio >= 16; div++) {
+ inc |= (divider_ratio & 1);
+ divider_ratio >>= 1;
+ }
+ divider_ratio += inc;
+ scl_low = (divider_ratio >> 1) - 1;
+ scl_high = divider_ratio - scl_low - 2;
+ data = I2CD_CACTC_BASE
+ | (scl_high << I2CD_TCKHIGH_SHIFT)
+ | (scl_low << I2CD_TCKLOW_SHIFT)
+ | (div << I2CD_BASE_DIV_SHIFT);
+
+ return data;
+}
+
+static void ast_i2c_clear_interrupts(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+
+ writel(~0, &priv->regs->isr);
+}
+
+static void ast_i2c_init_bus(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+
+ /* Reset device */
+ writel(0, &priv->regs->fcr);
+ /* Enable Master Mode. Assuming single-master */
+ writel(I2CD_MASTER_EN
+ | I2CD_M_SDA_LOCK_EN
+ | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
+ &priv->regs->fcr);
+ /* Enable Interrupts */
+ writel(I2CD_INTR_TX_ACK
+ | I2CD_INTR_TX_NAK
+ | I2CD_INTR_RX_DONE
+ | I2CD_INTR_BUS_RECOVER_DONE
+ | I2CD_INTR_NORMAL_STOP
+ | I2CD_INTR_ABNORMAL, &priv->regs->icr);
+}
+
+static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->regs = dev_get_addr_ptr(dev);
+ if (IS_ERR(priv->regs))
+ return PTR_ERR(priv->regs);
+
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0) {
+ debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ast_i2c_probe(struct udevice *dev)
+{
+ struct ast2500_scu *scu;
+
+ debug("Enabling I2C%u\n", dev->seq);
+
+ /*
+* Get all I2C devices out of Reset.
+* Only needs to be done once, but doing it for every
+
Re: [U-Boot] [PATCH v3 1/2] armv7m: add instruction & data cache support
On 03/14/2017 06:27 PM, Vikas Manocha wrote: > This patch adds armv7m instruction & data cache support. > > Signed-off-by: Vikas Manocha > cc: Christophe KERELLO > --- > > Changed in v3: > - uint32 replcaed with u32. > - multiple read of hardware register replaced with single. > - pointers replaced with macros for base address. > - register names added as comment for system control block registers. > > Changed in v2: > - changed strucures for memory mapped cache registers to macros > - added lines better readability. > - replaced magic numbers with macros. > > arch/arm/cpu/armv7m/Makefile | 2 +- > arch/arm/cpu/armv7m/cache.c | 291 > ++ > arch/arm/include/asm/armv7m.h | 26 +++- > arch/arm/lib/Makefile | 2 + > 4 files changed, 318 insertions(+), 3 deletions(-) > create mode 100644 arch/arm/cpu/armv7m/cache.c Please address comments on V2 before sending V3 ... -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 08/17] aspeed: AST2500 Pinctrl Driver
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.
Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/pinctrl.h | 52 ++
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 19
drivers/pinctrl/Kconfig| 9 ++
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/aspeed/Makefile| 1 +
drivers/pinctrl/aspeed/pinctrl_ast2500.c | 127 +
6 files changed, 209 insertions(+)
create mode 100644 arch/arm/include/asm/arch-aspeed/pinctrl.h
create mode 100644 drivers/pinctrl/aspeed/Makefile
create mode 100644 drivers/pinctrl/aspeed/pinctrl_ast2500.c
diff --git a/arch/arm/include/asm/arch-aspeed/pinctrl.h
b/arch/arm/include/asm/arch-aspeed/pinctrl.h
new file mode 100644
index 00..365dc21dbc
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/pinctrl.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef _ASM_ARCH_PERIPH_H
+#define _ASM_ARCH_PERIPH_H
+
+/*
+ * Peripherals supported by the hardware.
+ * These are used to specify pinctrl settings.
+ */
+
+enum periph_id {
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+ PERIPH_ID_UART4,
+ PERIPH_ID_LPC,
+ PERIPH_ID_PWM0,
+ PERIPH_ID_PWM1,
+ PERIPH_ID_PWM2,
+ PERIPH_ID_PWM3,
+ PERIPH_ID_PWM4,
+ PERIPH_ID_PWM5,
+ PERIPH_ID_PWM6,
+ PERIPH_ID_PWM7,
+ PERIPH_ID_PWM8,
+ PERIPH_ID_MAC1,
+ PERIPH_ID_MAC2,
+ PERIPH_ID_VIDEO,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SPI2,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
+ PERIPH_ID_I2C8,
+ PERIPH_ID_I2C9,
+ PERIPH_ID_I2C10,
+ PERIPH_ID_I2C11,
+ PERIPH_ID_I2C12,
+ PERIPH_ID_I2C13,
+ PERIPH_ID_I2C14,
+ PERIPH_ID_SD1,
+ PERIPH_ID_SD2,
+};
+
+#endif /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index e2556f920d..1cdd3b9198 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -10,6 +10,8 @@
#define SCU_HWSTRAP_VGAMEM_MASK3
#define SCU_HWSTRAP_VGAMEM_SHIFT 2
+#define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
+#define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
#define SCU_HWSTRAP_DDR4 (1 << 24)
#define SCU_HWSTRAP_CLKIN_25MHZ(1 << 23)
@@ -59,6 +61,23 @@
#define SCU_SYSRESET_AHB (1 << 1)
#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
+/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */
+#define SCU_PINMUX_CTRL5_I2C (1 << 16)
+
+/*
+ * The values are grouped by function, not by register.
+ * They are actually scattered across multiple loosely related registers.
+ */
+#define SCU_PIN_FUN_MAC1_MDC (1 << 30)
+#define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
+#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
+#define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
+#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
+#define SCU_PIN_FUN_SCL1 (1 << 12)
+#define SCU_PIN_FUN_SCL2 (1 << 14)
+#define SCU_PIN_FUN_SDA1 (1 << 13)
+#define SCU_PIN_FUN_SDA2 (1 << 15)
+
#ifndef __ASSEMBLY__
struct ast2500_clk_priv {
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index efcb4c0003..3b7dd5f0c5 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -175,6 +175,15 @@ config PIC32_PINCTRL
by a device tree node which contains both GPIO defintion and pin
control
functions.
+config ASPEED_AST2500_PINCTRL
+ bool "Aspeed AST2500 pin control driver"
+ depends on DM && PINCTRL_GENERIC && ASPEED_AST2500
+ default y
+ help
+Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses
+ Generic Pinctrl framework and is compatible with the Linux driver,
+ i.e. it uses the same device tree configuration.
+
endif
source "drivers/pinctrl/meson/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 512112af64..5392c3ed45 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON)+= meson/
obj-$(CONFIG_PINCTRL_MVEBU)+= mvebu/
+obj-$(CONFIG_ARCH_ASPEED) += aspeed/
diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pin
[U-Boot] [PATCH 07/17] aspeed: Refactor AST2500 RAM Driver and Sysreset Driver
This change switches all existing users of ast2500 Watchdog to Driver
Model based Watchdog driver.
To perform system reset Sysreset Driver uses first Watchdog device found
via uclass_first_device call. Since the system is going to be reset
anyway it does not make much difference which watchdog is used.
Instead of using Watchdog to reset itself, SDRAM driver now uses Reset
driver to do that.
These were the only users of the old Watchdog API, so that API is
removed.
This all is done in one change to avoid having to maintain dual API for
watchdog in between.
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/wdt.h | 39 -
arch/arm/mach-aspeed/Kconfig | 8 +
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 12 +--
arch/arm/mach-aspeed/ast_wdt.c | 51
configs/evb-ast2500_defconfig| 2 ++
drivers/sysreset/sysreset_ast.c | 24 ++---
6 files changed, 24 insertions(+), 112 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h
b/arch/arm/include/asm/arch-aspeed/wdt.h
index 981fa05a56..db8ecbcbe4 100644
--- a/arch/arm/include/asm/arch-aspeed/wdt.h
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -100,45 +100,6 @@ u32 ast_reset_mask_from_flags(ulong flags);
* @reset_mask: Reset Mask
*/
ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
-
-#ifndef CONFIG_WDT
-/**
- * Stop WDT
- *
- * @wdt: watchdog to stop
- *
- * When using driver model this function has different signature
- */
-void wdt_stop(struct ast_wdt *wdt);
-
-/**
- * Stop WDT
- *
- * @wdt: watchdog to start
- * @timeoutwatchdog timeout in number of clock ticks
- *
- * When using driver model this function has different signature
- */
-void wdt_start(struct ast_wdt *wdt, u32 timeout);
-#endif /* CONFIG_WDT */
-
-/**
- * Reset peripherals specified by mask
- *
- * Note, that this is only supported by ast2500 SoC
- *
- * @wdt: watchdog to use for this reset
- * @mask: reset mask.
- */
-int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask);
-
-/**
- * ast_get_wdt() - get a pointer to watchdog registers
- *
- * @wdt_number: 0-based WDT peripheral number
- * @return pointer to registers or -ve error on error
- */
-struct ast_wdt *ast_get_wdt(u8 wdt_number);
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARCH_WDT_H */
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
index c5b90bd96a..4f021baa06 100644
--- a/arch/arm/mach-aspeed/Kconfig
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -11,19 +11,13 @@ config SYS_TEXT_BASE
config ASPEED_AST2500
bool "Support Aspeed AST2500 SoC"
+ depends on DM_RESET
select CPU_ARM1176
help
The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU.
It is used as Board Management Controller on many server boards,
which is enabled by support of LPC and eSPI peripherals.
-config WDT_NUM
- int "Number of Watchdog Timers"
- default 3 if ASPEED_AST2500
- help
- The number of Watchdot Timers on a SoC.
- AST2500 has three WDTsk earlier versions have two or fewer.
-
source "arch/arm/mach-aspeed/ast2500/Kconfig"
endif
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index cb6e03fa34..efcf452b17 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -328,6 +329,7 @@ static void ast2500_sdrammc_lock(struct dram_info *info)
static int ast2500_sdrammc_probe(struct udevice *dev)
{
+ struct reset_ctl reset_ctl;
struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
struct ast2500_sdrammc_regs *regs = priv->regs;
int i;
@@ -345,9 +347,15 @@ static int ast2500_sdrammc_probe(struct udevice *dev)
}
clk_set_rate(&priv->ddr_clk, priv->clock_rate);
- ret = ast_wdt_reset_masked(ast_get_wdt(0), WDT_RESET_SDRAM);
+ ret = reset_get_by_index(dev, 0, &reset_ctl);
if (ret) {
- debug("%s(): SDRAM reset failed\n", __func__);
+ debug("%s(): Failed to get reset signal\n", __func__);
+ return ret;
+ }
+
+ ret = reset_assert(&reset_ctl);
+ if (ret) {
+ debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
return ret;
}
diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c
index 895fba3366..1a858b1020 100644
--- a/arch/arm/mach-aspeed/ast_wdt.c
+++ b/arch/arm/mach-aspeed/ast_wdt.c
@@ -28,54 +28,3 @@ ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32
reset_mask)
return ret;
}
-
-#ifndef CONFIG_WDT
-void wdt_stop(struct ast_wdt *wdt)
-{
- clrbits_le32(&wdt->ctrl, WDT_CTRL_EN);
-}
-
-void wdt_start(struct ast_wdt *wdt, u32 timeout)
-{
-
[U-Boot] [PATCH 13/17] aspeed: Add support for Clocks needed by MACs
Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.
The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.
The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.
So, the network driver would only need to enable these clocks, no need
to configure the rate.
Signed-off-by: Maxim Sloyko
---
arch/arm/dts/ast2500-u-boot.dtsi | 8 +
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 62 +-
drivers/clk/aspeed/clk_ast2500.c | 265 ++---
include/dt-bindings/clock/ast2500-scu.h| 2 +
4 files changed, 304 insertions(+), 33 deletions(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index faeeec1be4..f826646095 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -61,3 +61,11 @@
};
};
};
+
+&mac0 {
+ clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
+};
+
+&mac1 {
+ clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
+};
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 319d75e05c..fe877b5430 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -30,9 +30,36 @@
#define SCU_HPLL_POST_SHIFT13
#define SCU_HPLL_POST_MASK 0x3f
+#define SCU_MACCLK_SHIFT 16
+#define SCU_MACCLK_MASK(7 << SCU_MACCLK_SHIFT)
+
+#define SCU_MISC2_RGMII_HPLL (1 << 23)
+#define SCU_MISC2_RGMII_CLKDIV_SHIFT 20
+#define SCU_MISC2_RGMII_CLKDIV_MASK(3 << SCU_MISC2_RGMII_CLKDIV_SHIFT)
+#define SCU_MISC2_RMII_MPLL(1 << 19)
+#define SCU_MISC2_RMII_CLKDIV_SHIFT16
+#define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT)
#define SCU_MISC2_UARTCLK_SHIFT24
+#define SCU_MISC_D2PLL_OFF (1 << 4)
#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
+#define SCU_MISC_GCRT_USB20CLK (1 << 21)
+
+#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT0
+#define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\
+<< SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT6
+#define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\
+<< SCU_MICDS_MAC2RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12
+#define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18
+#define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_TXFALL (1 << 24)
+#define SCU_MICDS_MAC2RMII_TXFALL (1 << 25)
+#define SCU_MICDS_RMII1_RCLKEN (1 << 29)
+#define SCU_MICDS_RMII2_RCLKEN (1 << 30)
+#define SCU_MICDS_RGMIIPLL (1 << 31)
/*
* SYSRESET is actually more like a Power register,
@@ -71,14 +98,45 @@
*/
#define SCU_PIN_FUN_MAC1_MDC (1 << 30)
#define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
-#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
+#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
#define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
-#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
+#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
#define SCU_PIN_FUN_SCL1 (1 << 12)
#define SCU_PIN_FUN_SCL2 (1 << 14)
#define SCU_PIN_FUN_SDA1 (1 << 13)
#define SCU_PIN_FUN_SDA2 (1 << 15)
+#define SCU_CLKSTOP_MAC1 (1 << 20)
+#define SCU_CLKSTOP_MAC2 (1 << 21)
+
+#define SCU_D2PLL_EXT1_OFF (1 << 0)
+#define SCU_D2PLL_EXT1_BYPASS (1 << 1)
+#define SCU_D2PLL_EXT1_RESET (1 << 2)
+#define SCU_D2PLL_EXT1_MODE_SHIFT 3
+#define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT)
+#define SCU_D2PLL_EXT1_PARAM_SHIFT 5
+#define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT)
+
+#define SCU_D2PLL_NUM_SHIFT0
+#define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT)
+#define SCU_D2PLL_DENUM_SHIFT 8
+#define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT)
+#define SCU_D2PLL_POST_SHIFT 13
+#define SCU_D2PLL_POST_MASK(0x3f << SCU_D2PLL_POST_SHIFT)
+#define SCU_D2PLL_ODIV_SHIFT 19
+#define SCU_D2PLL_ODIV_MASK(7 << SCU_D2PLL_ODIV_SHIFT)
+#define SCU_D2PLL_SIC_SHIFT22
+#define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT)
+#define SCU_D2PLL_SIP_SHIFT27
+#define SCU_D2PLL_SIP_MASK (0x1f << SCU_
[U-Boot] [PATCH 03/17] aspeed: Watchdog Timer Driver
This driver supports ast2500 and ast2400 SoCs.
Only ast2500 supports reset_mask and thus the option of resettting
individual peripherals using WDT.
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/wdt.h | 53 --
arch/arm/mach-aspeed/ast_wdt.c | 40 ---
drivers/watchdog/Kconfig | 13
drivers/watchdog/Makefile | 1 +
drivers/watchdog/ast_wdt.c | 125 +
5 files changed, 219 insertions(+), 13 deletions(-)
create mode 100644 drivers/watchdog/ast_wdt.c
diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h
b/arch/arm/include/asm/arch-aspeed/wdt.h
index b292a0e67b..981fa05a56 100644
--- a/arch/arm/include/asm/arch-aspeed/wdt.h
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -67,15 +67,60 @@ struct ast_wdt {
u32 timeout_status;
u32 clr_timeout_status;
u32 reset_width;
-#ifdef CONFIG_ASPEED_AST2500
+ /* On pre-ast2500 SoCs this register is reserved. */
u32 reset_mask;
-#else
- u32 reserved0;
-#endif
};
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mode value from it.
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mode value
+ */
+u32 ast_reset_mode_from_flags(ulong flags);
+
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mask value from it. Reset Mask is only supported on ast2500
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mask value
+ */
+u32 ast_reset_mask_from_flags(ulong flags);
+
+/**
+ * Given Reset Mask and Reset Mode values, converts them to flags,
+ * suitable for passing into wdt_start or wdt_reset uclass functions.
+ *
+ * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they
+ * can both be packed into single 32 bits wide value.
+ *
+ * @reset_mode: Reset Mode
+ * @reset_mask: Reset Mask
+ */
+ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
+
+#ifndef CONFIG_WDT
+/**
+ * Stop WDT
+ *
+ * @wdt: watchdog to stop
+ *
+ * When using driver model this function has different signature
+ */
void wdt_stop(struct ast_wdt *wdt);
+
+/**
+ * Stop WDT
+ *
+ * @wdt: watchdog to start
+ * @timeoutwatchdog timeout in number of clock ticks
+ *
+ * When using driver model this function has different signature
+ */
void wdt_start(struct ast_wdt *wdt, u32 timeout);
+#endif /* CONFIG_WDT */
/**
* Reset peripherals specified by mask
diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c
index 22481ab7ea..895fba3366 100644
--- a/arch/arm/mach-aspeed/ast_wdt.c
+++ b/arch/arm/mach-aspeed/ast_wdt.c
@@ -9,6 +9,27 @@
#include
#include
+u32 ast_reset_mode_from_flags(ulong flags)
+{
+ return flags & WDT_CTRL_RESET_MASK;
+}
+
+u32 ast_reset_mask_from_flags(ulong flags)
+{
+ return flags >> 2;
+}
+
+ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask)
+{
+ ulong ret = reset_mode & WDT_CTRL_RESET_MASK;
+
+ if (ret == WDT_CTRL_RESET_SOC)
+ ret |= (reset_mask << 2);
+
+ return ret;
+}
+
+#ifndef CONFIG_WDT
void wdt_stop(struct ast_wdt *wdt)
{
clrbits_le32(&wdt->ctrl, WDT_CTRL_EN);
@@ -26,15 +47,7 @@ void wdt_start(struct ast_wdt *wdt, u32 timeout)
setbits_le32(&wdt->ctrl,
WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);
}
-
-struct ast_wdt *ast_get_wdt(u8 wdt_number)
-{
- if (wdt_number > CONFIG_WDT_NUM - 1)
- return ERR_PTR(-EINVAL);
-
- return (struct ast_wdt *)(WDT_BASE +
- sizeof(struct ast_wdt) * wdt_number);
-}
+#endif /* CONFIG_WDT */
int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask)
{
@@ -57,3 +70,12 @@ int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask)
return -EINVAL;
#endif
}
+
+struct ast_wdt *ast_get_wdt(u8 wdt_number)
+{
+ if (wdt_number > CONFIG_WDT_NUM - 1)
+ return ERR_PTR(-EINVAL);
+
+ return (struct ast_wdt *)(WDT_BASE +
+ sizeof(struct ast_wdt) * wdt_number);
+}
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 0d7366f3df..10f34f5efa 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -9,3 +9,16 @@ config WDT
start, restart, stop and reset (expire immediately).
What exactly happens when the timer expires is up to a particular
device/driver.
+
+config WDT_ASPEED
+ bool "Aspeed ast2400/ast2500 watchdog timer support"
+ depends on WDT
+ default y if ARCH_ASPEED
+ help
+ Select this to enable watchdog timer for Aspeed ast2500/ast2400
devices.
+ The watchdog timer is stopped when initialized. It performs reset,
either
+ full SoC reset or CPU or just some peripherals, based on the flags.
+ It currently does not support Boot Fla
[U-Boot] [PATCH 10/17] aspeed: Add P-Bus clock in ast2500 clock driver
Add P-Bus Clock support to ast2500 clock driver.
This is the clock used by I2C devices.
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 3 ++-
drivers/clk/aspeed/clk_ast2500.c | 11 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 1cdd3b9198..319d75e05c 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -21,7 +21,8 @@
#define SCU_MPLL_NUM_MASK 0xff
#define SCU_MPLL_POST_SHIFT13
#define SCU_MPLL_POST_MASK 0x3f
-
+#define SCU_PCLK_DIV_SHIFT 23
+#define SCU_PCLK_DIV_MASK 7
#define SCU_HPLL_DENUM_SHIFT 0
#define SCU_HPLL_DENUM_MASK0x1f
#define SCU_HPLL_NUM_SHIFT 5
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 504731271c..9e4c66ea85 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -110,6 +110,17 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = ast2500_get_mpll_rate(clkin,
readl(&priv->scu->m_pll_param));
break;
+ case BCLK_PCLK:
+ {
+ ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
+ >> SCU_PCLK_DIV_SHIFT) &
+SCU_PCLK_DIV_MASK);
+ rate = ast2500_get_hpll_rate(clkin,
+readl(&priv->scu->
+ h_pll_param));
+ rate = rate / apb_div;
+ }
+ break;
case PCLK_UART1:
rate = ast2500_get_uart_clk_rate(priv->scu, 1);
break;
--
2.12.0.367.g23dc2f6d3c-goog
___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH 09/17] aspeed: Enable Pinctrl Driver in AST2500 EVB
Enable Pinctrl Driver in AST2500 Eval Board's defconfig Signed-off-by: Maxim Sloyko --- configs/evb-ast2500_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 74808a71ee..f8ef9b779c 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -17,3 +17,4 @@ CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_WDT=y CONFIG_DM_RESET=y +CONFIG_PINCTRL=y -- 2.12.0.367.g23dc2f6d3c-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 04/17] aspeed: Make SCU lock/unlock functions part of SCU API
Make functions for locking and unlocking SCU part of SCU API.
Many drivers need to modify settings in SCU and thus need to unlock it
first. This change makes it possible.
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 14 ++
arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 15 +++
drivers/clk/aspeed/clk_ast2500.c | 18 ++
3 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index fc0c01ae33..0fa3ecb9b9 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -120,6 +120,20 @@ int ast_get_clk(struct udevice **devp);
*/
void *ast_get_scu(void);
+/**
+ * ast_scu_unlock() - unlock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_unlock(struct ast2500_scu *scu);
+
+/**
+ * ast_scu_lock() - lock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_lock(struct ast2500_scu *scu);
+
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
index 079909fa64..30cfac1af0 100644
--- a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
@@ -6,6 +6,7 @@
#include
#include
+#include
#include
int ast_get_clk(struct udevice **devp)
@@ -28,3 +29,17 @@ void *ast_get_scu(void)
return priv->scu;
}
+
+void ast_scu_unlock(struct ast2500_scu *scu)
+{
+ writel(SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (!readl(&scu->protection_key))
+ ;
+}
+
+void ast_scu_lock(struct ast2500_scu *scu)
+{
+ writel(~SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (readl(&scu->protection_key))
+ ;
+}
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 26a5e58221..504731271c 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -132,20 +132,6 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
return rate;
}
-static void ast2500_scu_unlock(struct ast2500_scu *scu)
-{
- writel(SCU_UNLOCK_VALUE, &scu->protection_key);
- while (!readl(&scu->protection_key))
- ;
-}
-
-static void ast2500_scu_lock(struct ast2500_scu *scu)
-{
- writel(~SCU_UNLOCK_VALUE, &scu->protection_key);
- while (readl(&scu->protection_key))
- ;
-}
-
static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
{
ulong clkin = ast2500_get_clkin(scu);
@@ -197,9 +183,9 @@ static ulong ast2500_configure_ddr(struct ast2500_scu *scu,
ulong rate)
| (best_num << SCU_MPLL_NUM_SHIFT)
| (best_denum << SCU_MPLL_DENUM_SHIFT);
- ast2500_scu_unlock(scu);
+ ast_scu_unlock(scu);
writel(mpll_reg, &scu->m_pll_param);
- ast2500_scu_lock(scu);
+ ast_scu_lock(scu);
return ast2500_get_mpll_rate(clkin, mpll_reg);
}
--
2.12.0.367.g23dc2f6d3c-goog
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 06/17] aspeed: Device Tree configuration for Reset Driver
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals
Signed-off-by: Maxim Sloyko
---
arch/arm/dts/ast2500-evb.dts | 15 +++
arch/arm/dts/ast2500-u-boot.dtsi | 10 +++
include/dt-bindings/reset/ast2500-reset.h | 45 +++
3 files changed, 70 insertions(+)
create mode 100644 include/dt-bindings/reset/ast2500-reset.h
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index dc13952fb8..723941ac0b 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -21,3 +21,18 @@
&sdrammc {
clock-frequency = <4>;
};
+
+&wdt1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&wdt2 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&wdt3 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index c95a7ba835..faeeec1be4 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,4 +1,5 @@
#include
+#include
#include "ast2500.dtsi"
@@ -11,12 +12,21 @@
#reset-cells = <1>;
};
+ rst: reset-controller {
+ u-boot,dm-pre-reloc;
+ compatible = "aspeed,ast2500-reset";
+ aspeed,wdt = <&wdt1>;
+ #reset-cells = <1>;
+ };
+
sdrammc: sdrammc@1e6e {
u-boot,dm-pre-reloc;
compatible = "aspeed,ast2500-sdrammc";
reg = <0x1e6e 0x174
0x1e6e0200 0x1d4 >;
+ #reset-cells = <1>;
clocks = <&scu PLL_MPLL>;
+ resets = <&rst AST_RESET_SDRAM>;
};
ahb {
diff --git a/include/dt-bindings/reset/ast2500-reset.h
b/include/dt-bindings/reset/ast2500-reset.h
new file mode 100644
index 00..eb5e1db97b
--- /dev/null
+++ b/include/dt-bindings/reset/ast2500-reset.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_
+#define _ABI_MACH_ASPEED_AST2500_RESET_H_
+
+/*
+ * The values are intentionally layed out as flags in
+ * WDT reset parameter.
+ */
+
+#define AST_RESET_SOC 0
+#define AST_RESET_CHIP 1
+#define AST_RESET_CPU (1 << 1)
+#define AST_RESET_ARM (1 << 2)
+#define AST_RESET_COPROC (1 << 3)
+#define AST_RESET_SDRAM(1 << 4)
+#define AST_RESET_AHB (1 << 5)
+#define AST_RESET_I2C (1 << 6)
+#define AST_RESET_MAC1 (1 << 7)
+#define AST_RESET_MAC2 (1 << 8)
+#define AST_RESET_GCRT (1 << 9)
+#define AST_RESET_USB20(1 << 10)
+#define AST_RESET_USB11_HOST (1 << 11)
+#define AST_RESET_USB11_HID(1 << 12)
+#define AST_RESET_VIDEO(1 << 13)
+#define AST_RESET_HAC (1 << 14)
+#define AST_RESET_LPC (1 << 15)
+#define AST_RESET_SDIO (1 << 16)
+#define AST_RESET_MIC (1 << 17)
+#define AST_RESET_CRT2D(1 << 18)
+#define AST_RESET_PWM (1 << 19)
+#define AST_RESET_PECI (1 << 20)
+#define AST_RESET_JTAG (1 << 21)
+#define AST_RESET_ADC (1 << 22)
+#define AST_RESET_GPIO (1 << 23)
+#define AST_RESET_MCTP (1 << 24)
+#define AST_RESET_XDMA (1 << 25)
+#define AST_RESET_SPI (1 << 26)
+#define AST_RESET_MISC (1 << 27)
+
+#endif /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */
--
2.12.0.367.g23dc2f6d3c-goog
___
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https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 05/17] aspeed: Reset Driver
Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
perform resets and thus depends on it. The actual Watchdog device used
needs to be configured in Device Tree using "aspeed,wdt" property, which
must be WDT phandle, for example:
rst: reset-controller {
compatible = "aspeed,ast2500-reset";
aspeed,wdt = <&wdt1>;
}
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 28 +++
drivers/reset/Kconfig | 10 +++
drivers/reset/Makefile | 1 +
drivers/reset/ast2500-reset.c | 109 +
4 files changed, 148 insertions(+)
create mode 100644 drivers/reset/ast2500-reset.c
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 0fa3ecb9b9..e2556f920d 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -31,6 +31,34 @@
#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
+/*
+ * SYSRESET is actually more like a Power register,
+ * except that corresponding bit set to 1 means that
+ * the peripheral is off.
+ */
+#define SCU_SYSRESET_XDMA (1 << 25)
+#define SCU_SYSRESET_MCTP (1 << 24)
+#define SCU_SYSRESET_ADC (1 << 23)
+#define SCU_SYSRESET_JTAG (1 << 22)
+#define SCU_SYSRESET_MIC (1 << 18)
+#define SCU_SYSRESET_SDIO (1 << 16)
+#define SCU_SYSRESET_USB11HOST (1 << 15)
+#define SCU_SYSRESET_USBHUB(1 << 14)
+#define SCU_SYSRESET_CRT (1 << 13)
+#define SCU_SYSRESET_MAC2 (1 << 12)
+#define SCU_SYSRESET_MAC1 (1 << 11)
+#define SCU_SYSRESET_PECI (1 << 10)
+#define SCU_SYSRESET_PWM (1 << 9)
+#define SCU_SYSRESET_PCI_VGA (1 << 8)
+#define SCU_SYSRESET_2D(1 << 7)
+#define SCU_SYSRESET_VIDEO (1 << 6)
+#define SCU_SYSRESET_LPC (1 << 5)
+#define SCU_SYSRESET_HAC (1 << 4)
+#define SCU_SYSRESET_USBHID(1 << 3)
+#define SCU_SYSRESET_I2C (1 << 2)
+#define SCU_SYSRESET_AHB (1 << 1)
+#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
+
#ifndef __ASSEMBLY__
struct ast2500_clk_priv {
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c42b0bcf0e..eb54189d4b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -43,4 +43,14 @@ config RESET_UNIPHIER
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
+config AST2500_RESET
+ bool "Reset controller driver for AST2500 SoCs"
+ depends on DM_RESET && WDT_ASPEED
+ default y if ASPEED_AST2500
+ help
+ Support for reset controller on AST2500 SoC. This controller uses
+ watchdog to reset different peripherals and thus only supports
+ resets that are supported by watchdog. The main limitation though
+ is that some reset signals, like I2C or MISC reset multiple devices.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 5c4305cc1d..16ad7eed5b 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
+obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
new file mode 100644
index 00..0afa4bd01a
--- /dev/null
+++ b/drivers/reset/ast2500-reset.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ast2500_reset_priv {
+ /* WDT used to perform resets. */
+ struct udevice *wdt;
+ struct ast2500_scu *scu;
+};
+
+static int ast2500_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ast2500_reset_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
+ &priv->wdt);
+ if (ret) {
+ debug("%s: can't find WDT for reset controller", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ u32 reset_mode, reset_mask;
+ bool reset_sdram;
+ int ret;
+
+ if (IS_ERR(priv))
+ return PTR_ERR(priv);
+
+ /*
+* To reset SDRAM, specifal flag in SYSRESET register
+* needs to be enabled first
+*/
+ reset_mode = ast_reset_mode_from_flags(r
[U-Boot] [PATCH 02/17] dm: Simple Watchdog uclass
This is a simple uclass for Watchdog Timers. It has four operations:
start, restart, reset, stop. Drivers must implement start, restart and
stop operations, while implementing reset is optional: It's default
implementation expires watchdog timer in one clock tick.
Signed-off-by: Maxim Sloyko
---
drivers/watchdog/Kconfig | 11 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/wdt-uclass.c | 79 +++
include/dm/uclass-id.h| 1 +
include/wdt.h | 97 +++
5 files changed, 189 insertions(+)
create mode 100644 drivers/watchdog/wdt-uclass.c
create mode 100644 include/wdt.h
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index e69de29bb2..0d7366f3df 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -0,0 +1,11 @@
+menu "Watchdog Timer Support"
+
+config WDT
+ bool "Enable driver model for watchdog timer drivers"
+ depends on DM
+ help
+ Enable driver model for watchdog timer. At the moment the API
+ is very simple and only supports four operations:
+ start, restart, stop and reset (expire immediately).
+ What exactly happens when the timer expires is up to a particular
+ device/driver.
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index a007ae8234..1aabcb97ae 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
+obj-$(CONFIG_WDT) += wdt-uclass.o
diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
new file mode 100644
index 00..98a8b529f9
--- /dev/null
+++ b/drivers/watchdog/wdt-uclass.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Implement a simple watchdog uclass. Watchdog is basically a timer that
+ * is used to detect or recover from malfunction. During normal operation
+ * the watchdog would be regularly reset to prevent it from timing out.
+ * If, due to a hardware fault or program error, the computer fails to reset
+ * the watchdog, the timer will elapse and generate a timeout signal.
+ * The timeout signal is used to initiate corrective action or actions,
+ * which typically include placing the system in a safe, known state.
+ */
+
+int wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ const struct wdt_ops *ops = device_get_ops(dev);
+
+ if (!ops->start)
+ return -ENOSYS;
+
+ return ops->start(dev, timeout, flags);
+}
+
+int wdt_stop(struct udevice *dev)
+{
+ const struct wdt_ops *ops = device_get_ops(dev);
+
+ if (!ops->stop)
+ return -ENOSYS;
+
+ return ops->stop(dev);
+}
+
+int wdt_restart(struct udevice *dev)
+{
+ const struct wdt_ops *ops = device_get_ops(dev);
+
+ if (!ops->restart)
+ return -ENOSYS;
+
+ return ops->restart(dev);
+}
+
+int wdt_reset(struct udevice *dev, ulong flags)
+{
+ const struct wdt_ops *ops;
+
+ debug("WDT Resettting: %lu\n", flags);
+ ops = device_get_ops(dev);
+ if (ops->reset) {
+ return ops->reset(dev, flags);
+ } else {
+ if (!ops->start)
+ return -ENOSYS;
+
+ ops->start(dev, 1, flags);
+ while (1)
+ ;
+ }
+
+ return 0;
+}
+
+UCLASS_DRIVER(wdt) = {
+ .id = UCLASS_WDT,
+ .name = "wdt",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 8c92d0b030..b73a7fd436 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -83,6 +83,7 @@ enum uclass_id {
UCLASS_VIDEO, /* Video or LCD device */
UCLASS_VIDEO_BRIDGE,/* Video bridge, e.g. DisplayPort to LVDS */
UCLASS_VIDEO_CONSOLE, /* Text console driver for video device */
+ UCLASS_WDT, /* Watchdot Timer driver */
UCLASS_COUNT,
UCLASS_INVALID = -1,
diff --git a/include/wdt.h b/include/wdt.h
new file mode 100644
index 00..1da5a962df
--- /dev/null
+++ b/include/wdt.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _WDT_H_
+#define _WDT_H_
+
+/*
+ * Start the timer
+ *
+ * @dev: WDT Device
+ * @timeout: Number of ticks before timer expires
+ * @flags: Driver specific flags. This might be used to specify
+ * which action needs to be executed when the timer expires
+ * @return: 0 if OK, -ve on error
+ */
+int wdt_start(struct udevice *dev, u64 timeout, ulong flags);
+
+/*
+ * Stop the timer
+ *
+ * @dev: WDT Device
+ * @return: 0 if OK, -
[U-Boot] [PATCH 01/17] aspeed: Update ast2500 Device Tree
Pull in the Device Tree for ast2500 from the mainline Linux kernel
Signed-off-by: Maxim Sloyko
---
arch/arm/dts/ast2500.dtsi | 881 +-
1 file changed, 880 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index 97fac69d11..7e0ad3a41a 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -1,6 +1,6 @@
/*
* This device tree is copied from
- * https://raw.githubusercontent.com/torvalds/linux/02440622/arch/arm/boot/dts/
+ *
https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
*/
#include "skeleton.dtsi"
@@ -36,6 +36,22 @@
reg = <0x1e6c0080 0x80>;
};
+ mac0: ethernet@1e66 {
+ compatible = "faraday,ftgmac100";
+ reg = <0x1e66 0x180>;
+ interrupts = <2>;
+ no-hw-checksum;
+ status = "disabled";
+ };
+
+ mac1: ethernet@1e68 {
+ compatible = "faraday,ftgmac100";
+ reg = <0x1e68 0x180>;
+ interrupts = <3>;
+ no-hw-checksum;
+ status = "disabled";
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -48,6 +64,822 @@
reg = <0x1e6e2070 0x04>;
};
+ syscon: syscon@1e6e2000 {
+ compatible = "aspeed,g5-scu", "syscon",
"simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl {
+ compatible = "aspeed,g5-pinctrl";
+ aspeed,external-nodes = <&gfx &lhc>;
+
+ pinctrl_acpi_default: acpi_default {
+ function = "ACPI";
+ groups = "ACPI";
+ };
+
+ pinctrl_adc0_default: adc0_default {
+ function = "ADC0";
+ groups = "ADC0";
+ };
+
+ pinctrl_adc1_default: adc1_default {
+ function = "ADC1";
+ groups = "ADC1";
+ };
+
+ pinctrl_adc10_default: adc10_default {
+ function = "ADC10";
+ groups = "ADC10";
+ };
+
+ pinctrl_adc11_default: adc11_default {
+ function = "ADC11";
+ groups = "ADC11";
+ };
+
+ pinctrl_adc12_default: adc12_default {
+ function = "ADC12";
+ groups = "ADC12";
+ };
+
+ pinctrl_adc13_default: adc13_default {
+ function = "ADC13";
+ groups = "ADC13";
+ };
+
+ pinctrl_adc14_default: adc14_default {
+ function = "ADC14";
+ groups = "ADC14";
+ };
+
+ pinctrl_adc15_default: adc15_default {
+ function = "ADC15";
+ groups = "ADC15";
+ };
+
+ pinctrl_adc2_default: adc2_default {
+ function = "ADC2";
+ groups = "ADC2";
+ };
+
+ pinctrl_adc3_default: adc3_default {
+ function = "ADC3";
+ groups = "ADC3";
+ };
+
+ pinctrl_adc4_default: adc4_default {
+ function = "ADC4";
+ groups = "AD
[U-Boot] [PATCH 00/17] Expand Aspeed AST2500 Support
This series expands support for Aspeed AST2500 SoC, commonly used as Board Management Controller in many servers, to the point where it can actually be useful. The main goal of this series is I2C and Network drivers, the rest are either cleanups or supporting patches. Most notable among them is addition of Watchdog Uclass, so that watchdog drivers can now use Driver Model. One notable thing that is *missing* from this series is Device Tree configuration for I2C driver. The Linux Kernel I2C driver is still under review and it may affect the details of how devices need to be configured in the Device Tree. So, I decided to wait until it will show up in Linux Kernel DT and then pull it into U-Boot. Maxim Sloyko (17): aspeed: Update ast2500 Device Tree dm: Simple Watchdog uclass aspeed: Watchdog Timer Driver aspeed: Make SCU lock/unlock functions part of SCU API aspeed: Reset Driver aspeed: Device Tree configuration for Reset Driver aspeed: Refactor AST2500 RAM Driver and Sysreset Driver aspeed: AST2500 Pinctrl Driver aspeed: Enable Pinctrl Driver in AST2500 EVB aspeed: Add P-Bus clock in ast2500 clock driver aspeed: Add I2C Driver aspeed: Enable I2C in EVB defconfig aspeed: Add support for Clocks needed by MACs aspeed: Refactor SCU to use consistent mask & shift aspeed: Cleanup ast2500-u-boot.dtsi Device Tree aspeed: Add AST2500/AST2400 compatible NIC Driver aspeed: Network Driver configuration for EVB arch/arm/dts/ast2500-evb.dts | 29 + arch/arm/dts/ast2500-u-boot.dtsi | 59 +- arch/arm/dts/ast2500.dtsi | 881 - arch/arm/include/asm/arch-aspeed/pinctrl.h | 52 ++ arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 132 +++- arch/arm/include/asm/arch-aspeed/wdt.h | 38 +- arch/arm/mach-aspeed/Kconfig | 8 +- arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 15 + arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 17 +- arch/arm/mach-aspeed/ast_wdt.c | 47 +- configs/evb-ast2500_defconfig | 13 + drivers/clk/aspeed/clk_ast2500.c | 321 +++-- drivers/i2c/Kconfig| 9 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 355 ++ drivers/i2c/ast_i2c.h | 132 drivers/net/Kconfig| 8 + drivers/net/Makefile | 1 + drivers/net/ast_nic.c | 584 drivers/net/ast_nic.h | 198 ++ drivers/pinctrl/Kconfig| 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/aspeed/Makefile| 1 + drivers/pinctrl/aspeed/pinctrl_ast2500.c | 127 drivers/reset/Kconfig | 10 + drivers/reset/Makefile | 1 + drivers/reset/ast2500-reset.c | 109 +++ drivers/sysreset/sysreset_ast.c| 24 +- drivers/watchdog/Kconfig | 24 + drivers/watchdog/Makefile | 2 + drivers/watchdog/ast_wdt.c | 125 drivers/watchdog/wdt-uclass.c | 79 +++ include/dm/uclass-id.h | 1 + include/dt-bindings/clock/ast2500-scu.h| 2 + include/dt-bindings/reset/ast2500-reset.h | 45 ++ include/wdt.h | 97 +++ 36 files changed, 3390 insertions(+), 167 deletions(-) create mode 100644 arch/arm/include/asm/arch-aspeed/pinctrl.h create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.h create mode 100644 drivers/net/ast_nic.c create mode 100644 drivers/net/ast_nic.h create mode 100644 drivers/pinctrl/aspeed/Makefile create mode 100644 drivers/pinctrl/aspeed/pinctrl_ast2500.c create mode 100644 drivers/reset/ast2500-reset.c create mode 100644 drivers/watchdog/ast_wdt.c create mode 100644 drivers/watchdog/wdt-uclass.c create mode 100644 include/dt-bindings/reset/ast2500-reset.h create mode 100644 include/wdt.h -- 2.12.0.367.g23dc2f6d3c-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] Kconfig: Don't use RSA_FREESCALE_EXP on IMX
The CAAM in IMX parts doesn't support public key hardware acceleration (PKHA), so don't use RSA_FREESCALE_EXP. If you try to use it on IMX (assuming you have the clocks enabled first) you will get back an "Invalid KEY Command" error since PKHA isn't a valid key destination for these parts. Signed-off-by: George McCollister --- lib/rsa/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig index 09ec358242..fde1ac108d 100644 --- a/lib/rsa/Kconfig +++ b/lib/rsa/Kconfig @@ -1,6 +1,6 @@ config RSA bool "Use RSA Library" - select RSA_FREESCALE_EXP if FSL_CAAM + select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5 select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP help RSA support. This enables the RSA algorithm used for FIT image @@ -29,7 +29,7 @@ config RSA_SOFTWARE_EXP config RSA_FREESCALE_EXP bool "Enable RSA Modular Exponentiation with FSL crypto accelerator" - depends on DM && RSA && FSL_CAAM + depends on DM && RSA && FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5 help Enables driver for RSA modular exponentiation using Freescale cryptographic accelerator - CAAM. -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v2] Add support for Microchip LAN78xx
On Fri, Mar 10, 2017 at 06:38:10PM +, yuiko.osh...@microchip.com wrote: > From: Yuiko Oshino > > Add support for Microchip LAN7800 and 7850, USB to 10/100/1000 Ethernet > Controllers > > Signed-off-by: Yuiko Oshino > Cc: Marek Vasut > --- > Changes for v2: >- lan78xx.c header comment cleanup > > drivers/usb/eth/Makefile |1 + > drivers/usb/eth/lan78xx.c| 1319 > ++ > drivers/usb/eth/usb_ether.c |7 + > include/usb_ether.h |6 + > scripts/config_whitelist.txt |1 + NAK. You don't add to the whitelist, you start adding to Kconfig. Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] Pass empty CFLAGS on invocation of libfdt/setup.py
On Thu, Mar 16, 2017 at 11:38:00AM -0700, Max Filippov wrote: > When building u-boot tools in cross-build environment CFLAGS environment > variable set up for target is taken into an account when building code > for host. Set it to empty on invocation of python. > > This fixes the following build errors when cross-compiling for xtensa: > > cc1: error: unrecognized command line option "-mlongcalls" > cc1: error: unrecognized command line option "-mauto-litpools" > > Signed-off-by: Max Filippov > --- > tools/Makefile | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tools/Makefile b/tools/Makefile > index 1c840d7..c224e8a 100644 > --- a/tools/Makefile > +++ b/tools/Makefile > @@ -120,7 +120,7 @@ _libfdt.so-sharedobjs += $(LIBFDT_OBJS) > libfdt: > > tools/_libfdt.so: $(patsubst %.o,%.c,$(LIBFDT_OBJS)) tools/libfdt_wrap.c > - LDFLAGS="$(HOSTLDFLAGS)" python $(srctree)/lib/libfdt/setup.py \ > + LDFLAGS="$(HOSTLDFLAGS)" CFLAGS="" python > $(srctree)/lib/libfdt/setup.py \ I think we need to be passing in HOSTCFLAGS or we'll end up being broken on certain other cases (which are broken today I suspect). Can you test that out? Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARM: am43xx: fix SOC revision print outs
Currently, AM43xx just re-uses the version strings from AM33xx which is
wrong; the actual values for AM43xx are different. Fix this by adding
a separate version string array for AM43xx and use this instead.
Signed-off-by: Tero Kristo
Reported-by: Sekhar Nori
---
arch/arm/mach-omap2/am33xx/sys_info.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c
b/arch/arm/mach-omap2/am33xx/sys_info.c
index f0f72fa..e4fc461 100644
--- a/arch/arm/mach-omap2/am33xx/sys_info.c
+++ b/arch/arm/mach-omap2/am33xx/sys_info.c
@@ -74,6 +74,10 @@ static char *cpu_revs[] = {
"2.0",
"2.1"};
+static char *cpu_revs_am43xx[] = {
+ "1.0",
+ "1.1",
+ "1.2"};
static char *dev_types[] = {
"TST",
@@ -87,6 +91,7 @@ static char *dev_types[] = {
int print_cpuinfo(void)
{
char *cpu_s, *sec_s, *rev_s;
+ char **cpu_rev_arr = cpu_revs;
switch (get_cpu_type()) {
case AM335X:
@@ -97,6 +102,7 @@ int print_cpuinfo(void)
break;
case AM437X:
cpu_s = "AM437X";
+ cpu_rev_arr = cpu_revs_am43xx;
break;
default:
cpu_s = "Unknown CPU type";
@@ -104,7 +110,7 @@ int print_cpuinfo(void)
}
if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
- rev_s = cpu_revs[get_cpu_rev()];
+ rev_s = cpu_rev_arr[get_cpu_rev()];
else
rev_s = "?";
--
1.9.1
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[U-Boot] Why is ns16550 guarded by !OF_PLATDATA ?
I'm trying to use the ns16550 DM driver in a platform where havind a dtb in SPL is not plausible, so we're using platdata. Now for ns16550 The U_BOOT_DRIVER is guarded by !OF_PLATDATA, so the driver is not compiled in SPL. This seems inconsistent with other U_BOOT_DRIVERs. This was introduced in the following commit [1]: * b2927fb dm: serial: ns16550: Update to support of-platdata The reasoning was that the platdata structure is unknown, but one would have to provide a 'struct ns16550_platdata' when using platdata, and that is the case with the boards that use this driver with platdata. Is this a misguided change, or am I missing something deeper? I can prepare a patch to resolve this, if this is the consensus. Alex [1] https://lists.denx.de/pipermail/u-boot/2016-July/259744.html ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] armv8/fsl-layerscape: fdt: On ls1012 don't check sysclk for USB
USB requires 100MHz clock. On ls1012, sysclk(125MHz) is not for USB. Another 100MHz clock is for USB. So For USB, check if sysclk is 100MHz is failed on ls1012, sysclk is not for USB. Don't check sysclk for USB on ls1012. Signed-off-by: Yingxi Yu --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 26d4a30..762a95b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -387,8 +387,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); #endif +#ifndef CONFIG_LS1012A fsl_fdt_disable_usb(blob); - +#endif #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN fdt_fixup_gic(blob); #endif -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] iMX6 (Arm) failing to initialize console. Hangs when running relocation code.
I have a board that is running u-boot based on "U-Boot 2009.08". I am in the process of developing another board that is very similar but want to upgrade the u-boot to "U-Boot 2013.06". The boards are NXP iMX6DL CPU (ARM) based with 32 bit DDR3 and console via UART1. These designs are based on the SabreSD reference design. The u-boot implmentations are copies of the SabreSD files optimized for my board. I am loading the boards serially via USB using the imx_usb utility available from https://github.com/boundarydevices/imx_usb_loader.git I do not have a debugger/JTAG interface. I have verified that I am working by manipulating GPIO pins. Using the older design, I can run the old boot loader fine. When I run the new version of u-boot, the board boots but does not output anything via the serial console. It gets through the board_init_f function but does not reach the board_late_init function. (Nor do I see it access board_init_r.) Any suggestions as to how to determine why the serial port is not outputting? (I can determine that the serial port initialization functions are running and I have verified that the IOMuxC setting for the pins is valid.) The code between the board_init_f and board_late_init functions appears to be code that relocates the executable image. (arch/arm/lib/crt0.S) Since the iMX6 loads the software into RAM before executing u-boot, I am wondering why I am running this code at all. Why does the u-boot run the relocation firmware in this case? Regards, Doug Bailey ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v7,8/9] STiH410-B2260: Add device tree
On Tue, Feb 21, 2017 at 01:37:11PM +0100, Patrice Chotard wrote: > From: Patrice Chotard > > This device tree has been extracted from v4.9 kernel > > Signed-off-by: Patrice Chotard > Reviewed-by: Tom Rini > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v7,3/9] STiH410: Add STi sysreset driver
On Tue, Feb 21, 2017 at 01:37:06PM +0100, Patrice Chotard wrote: > From: Patrice Chotard > > Signed-off-by: Patrice Chotard > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v7,7/9] STiH410: Add STi pinctrl driver
On Tue, Feb 21, 2017 at 01:37:10PM +0100, Patrice Chotard wrote: > From: Patrice Chotard > > Add STMicroelectronics STiH410 pinctrl driver > > Signed-off-by: Patrice Chotard > Reviewed-by: Tom Rini > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] tools: fix cross-compiling tools when HOSTCC is overridden
On Mon, Mar 13, 2017 at 05:43:16PM +0900, Masahiro Yamada wrote: > Richard reported U-Boot tools issues in OpenEmbedded/Yocto project. > > OE needs to be able to change the default compiler. If we pass in > HOSTCC through the make command, it overwrites all HOSTCC instances, > including ones in tools/Makefile and tools/env/Makefile, which breaks > "make cross_tools" and "make env", respectively. > > Add "override" directives to avoid overriding HOSTCC instances that > really need to point to the cross-compiler. > > Signed-off-by: Masahiro Yamada > Reported-by: Richard Purdie > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v7, 5/9] gpio: do not include for ARCH_STI
On Tue, Feb 21, 2017 at 01:37:08PM +0100, Patrice Chotard wrote: > From: Patrice Chotard > > As no gpio.h is defined in arch/arm/include/asm/arch-stih410, > to avoid compilation failure, do not include asm/arch/gpio.h. > > This is needed for example when including sdhci.h, which include > asm/gpio.h>. > > Signed-off-by: Patrice Chotard > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v7, 9/9] board: Add STMicroelectronics STiH410-B2260 support
On Tue, Feb 21, 2017 at 01:37:12PM +0100, Patrice Chotard wrote: > From: Patrice Chotard > > This is a 96Board compliant board based on STiH410 SoC: > - 1GB DDR > - On-Board USB combo WiFi/Bluetooth RTL8723BU > with PCB soldered antenna > - Ethernet 1000-BaseT > - SATA > - HDMI > - 2 x USB2.0 type A > - 1 x USB2.0 type micro-AB > - SD card slot > - High speed connector (SD/I2C/USB interfaces) > - Low speed connector (UART/I2C/GPIO/SPI/PCM interfaces) > > Signed-off-by: Patrice Chotard > Reviewed-by: Tom Rini > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v7,2/9] STiH410: Add STi timer driver
On Tue, Feb 21, 2017 at 01:37:05PM +0100, Patrice Chotard wrote: > From: Patrice Chotard > > Add ARM global timer based timer > > Signed-off-by: Patrice Chotard > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3] arm64: booti: allow to place kernel image anywhere in physical memory
On Thu, Mar 09, 2017 at 04:28:25PM +0900, Masahiro Yamada wrote:
> At first, the ARM64 Linux booting requirement recommended that the
> kernel image be placed text_offset bytes from 2MB aligned base near
> the start of usable system RAM because memory below that base address
> was unusable at that time.
>
> This requirement was relaxed by Linux commit a7f8de168ace ("arm64:
> allow kernel Image to be loaded anywhere in physical memory").
> Since then, the bit 3 of the flags field indicates the tolerance
> of the kernel physical placement. If this bit is set, the 2MB
> aligned base may be anywhere in physical memory. For details, see
> Documentation/arm64/booting.txt of Linux.
>
> The booti command should be also relaxed. If the bit 3 is set,
> images->ep is respected, and the image is placed at the nearest
> bootable location. Otherwise, it is relocated to the start of the
> system RAM to keep the original behavior.
>
> Another wrinkle we need to take care of is the unknown endianness of
> text_offset for a kernel older than commit a2c1d73b94ed (i.e. v3.16).
> We can detect this based on the image_size field. If the field is
> zero, just use a fixed offset 0x8.
>
> Signed-off-by: Masahiro Yamada
Applied to u-boot/master, thanks!
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Re: [U-Boot] [U-Boot,v7,4/9] STiH410: Add STi serial driver
On Tue, Feb 21, 2017 at 01:37:07PM +0100, Patrice Chotard wrote: > From: Patrice Chotard > > This patch adds support to ASC (asynchronous serial controller) > driver, which is basically a standard serial driver. This IP > is common across other STMicroelectronics SoCs > > Signed-off-by: Patrice Chotard > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v7,6/9] STiH410: Add STi SDHCI driver
On Tue, Feb 21, 2017 at 01:37:09PM +0100, Patrice Chotard wrote: > From: Patrice Chotard > > Add SDHCI host controller found on STMicroelectronics SoCs > > On some ST SoCs, i.e. STiH407/STiH410, the MMC devices can live > inside a dedicated flashSS sub-system that provides an extend subset > of registers that can be used to configure the Arasan MMC/SD Host > Controller. > > This means, that the SDHCI Arasan Controller can be configured to be > eMMC4.5 or 4.3 spec compliant. > > W/o these settings the SDHCI will configure and use the MMC/SD > controller with limited features e.g. PIO mode, no DMA, no HS etc. > > Signed-off-by: Patrice Chotard > Reviewed-by: Simon Glass > Reviewed-by: Jaehoon Chung Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,1/2] igep00x0: disable environment
On Sun, Feb 19, 2017 at 12:23:39AM +0100, Ladislav Michl wrote: > ISEE's U-Boot and Linux are using 1bit ECC scheme, while we > switched to 8bit ECC to fullfill flash specification requirements. > However when trying to run U-Boot on board with 1bit ECC'd data > on flash, UBI code takes several minutes to pass scan as reading > of every block ends with ecc error (which is also printed on > console). > So, until proper solution is developed, disable environment > alltogether. > > Signed-off-by: Ladislav Michl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v7, 1/9] arm: Add support for STMicroelectronics STiH410 soc
On Tue, Feb 21, 2017 at 01:37:04PM +0100, Patrice Chotard wrote: > From: Patrice Chotard > > The STiH410 is an advanced multi-HD AVC processor with 3D > graphics acceleration and 1.5-GHz ARM Cortex-A9 SMP CPU > part of the STiH407 family. > > It has wide connectivity including USB 3.0, PCI-e, SATA > and gigabit ethernet. > > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v3] armv7m: Add SysTick timer driver
On Fri, Feb 17, 2017 at 08:22:17AM +, Phil Edworthy wrote: > The SysTick is a 24-bit down counter that is found on all ARM Cortex > M3, M4, M7 devices and is always located at a fixed address. > > The number of reference clock ticks that correspond to 10ms is normally > defined in the SysTick Calibration register's TENMS field. However, on some > devices this is wrong, so this driver allows the clock rate to be defined > using CONFIG_SYS_HZ_CLOCK. > > Signed-off-by: Phil Edworthy > Reviewed-by: Vikas MANOCHA Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/2] igep00x0: fixup FDT according to detected flash type
On Sun, Feb 19, 2017 at 12:24:49AM +0100, Ladislav Michl wrote: > Leave only detected flash type enabled in FTD as otherwise GPMC CS is > claimed (and never freed) by Linux, causing 'concurent' flash type > not to be probed. > > Signed-off-by: Ladislav Michl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] tiny-printf: add static to locally used functions
On Sun, Feb 12, 2017 at 06:08:43PM +0900, Masahiro Yamada wrote: > These two functions are only used in lib/tiny-printf.c . > > Signed-off-by: Masahiro Yamada > Tested-by: Andreas Färber > Reviewed-by: Stefan Roese Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v4] tools: omapimage: Fix size in header
On Wed, Feb 15, 2017 at 06:42:54PM +0530, Lokesh Vutla wrote: > The size field in GP header that is expected by ROM is size of the > image + size of the header. But omapimage generates a gp header > only with size of the image as size field. Fix it > > Signed-off-by: Lokesh Vutla Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] pull request: u-boot-uniphier/master
On Tue, Mar 14, 2017 at 05:57:31AM +0900, Masahiro Yamada wrote: > Hi Tom, > > Please pull my first round of UniPhier changes for v2017.05: > > - Fix regression of DRAM settings > - DT updates (fix W=1 warnings, re-sync with Linux) > > > (For Linux, I had already sent equivalent patches > to fix no unit name warnings, remove skeleton.dtsi inclusion. > They will be merged for linux-4.12-rc1, so Linux and U-Boot > will be kept synced.) > > > The following changes since commit 8537ddd769f460d7fb7a62a3dcc9669049702e51: > > Prepare v2017.03 (2017-03-13 13:54:16 -0400) > > are available in the git repository at: > > git://git.denx.de/u-boot-uniphier.git master > > for you to fetch changes up to 7317a94085b2146811d9d1350b26d562b98aebac: > > ARM: dts: uniphier: more re-sync DT with Linux (2017-03-14 05:52:53 +0900) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [Resend] Please pull u-boot-fsl-qoriq master
Tom, The following changes since commit 8537ddd769f460d7fb7a62a3dcc9669049702e51: Prepare v2017.03 (2017-03-13 13:54:16 -0400) are available in the git repository at: git://git.denx.de/u-boot-fsl-qoriq.git for you to fetch changes up to 9b6639fa85bddd90df4c371f25a89c791a6ee6ef: LS1021ATWR: Modify u-boot size for sd secure boot (2017-03-14 08:44:03 -0700) Hou Zhiqiang (1): armv8/ls104xa: remove the DDR interactive debugging info from SPL Priyanka Jain (3): armv8: fsl-layerscape: Updates DCFG register map armv8: fsl-lsch3: Update VID support armv8: fsl-layerscape: Add vid support for LS2080AQDS Tang Yuantian (1): armv8: fsl-lsch2: add workaround for erratum A-010635 Vinitha Pillai (1): LS1021ATWR: Modify u-boot size for sd secure boot York Sun (11): armv8: Add global variable resv_ram armv8: ls2080a: Move CONFIG_FSL_MC_ENET to Kconfig armv8: ls2080a: Move CONFIG_SYS_MC_RSV_MEM_ALIGN to Kconfig efi: Add a hook to allow adding memory mapping armv8: layerscape: Rewrite memory reservation driver: net: fsl-mc: Update calculation of MC RAM armv8: layerscape: Update MMU mapping with actual DDR size armv8: layerscape: Fix the sequence of changing MMU table armv8: ls2080a: Drop early MMU for SPL build armv8: mmu: Add a function to change mapping attributes armv8: layerscape: Update early MMU for DDR after initialization arch/arm/cpu/armv8/cache_v8.c | 72 - arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 26 ++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 331 +++-- arch/arm/cpu/armv8/fsl-layerscape/soc.c| 2 - arch/arm/cpu/armv8/fsl-layerscape/spl.c| 3 - arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 +- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 69 +++-- arch/arm/include/asm/arch-fsl-layerscape/mmu.h | 2 +- arch/arm/include/asm/armv8/mmu.h | 5 + arch/arm/include/asm/fsl_secure_boot.h | 4 +- arch/arm/include/asm/global_data.h | 7 + arch/arm/include/asm/system.h | 1 + board/freescale/common/vid.c | 174 ++- board/freescale/ls1012afrdm/ls1012afrdm.c | 34 +-- board/freescale/ls1012aqds/ls1012aqds.c| 34 +-- board/freescale/ls1012ardb/ls1012ardb.c| 34 +-- board/freescale/ls1043aqds/ddr.c | 29 -- board/freescale/ls1043aqds/ls1043aqds.c| 5 + board/freescale/ls1043ardb/ddr.c | 29 -- board/freescale/ls1043ardb/ls1043ardb.c| 7 - board/freescale/ls1046aqds/ddr.c | 29 -- board/freescale/ls1046aqds/ls1046aqds.c| 5 + board/freescale/ls1046ardb/ddr.c | 29 -- board/freescale/ls1046ardb/ls1046ardb.c| 7 - board/freescale/ls2080a/ddr.c | 55 board/freescale/ls2080a/ls2080a.c | 17 +- board/freescale/ls2080aqds/ddr.c | 55 board/freescale/ls2080aqds/ls2080aqds.c| 26 +- board/freescale/ls2080ardb/ddr.c | 55 board/freescale/ls2080ardb/ls2080ardb.c| 26 +- cmd/bdinfo.c | 4 + common/board_f.c | 32 +- drivers/net/fsl-mc/mc.c| 75 + include/configs/ls1021atwr.h | 4 +- include/configs/ls1043aqds.h | 2 + include/configs/ls1043ardb.h | 2 + include/configs/ls1046aqds.h | 2 + include/configs/ls1046ardb.h | 2 + include/configs/ls2080a_common.h | 2 - lib/efi_loader/efi_memory.c| 14 +- scripts/config_whitelist.txt | 2 - 42 files changed, 750 insertions(+), 579 deletions(-) Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] Pass empty CFLAGS on invocation of libfdt/setup.py
When building u-boot tools in cross-build environment CFLAGS environment variable set up for target is taken into an account when building code for host. Set it to empty on invocation of python. This fixes the following build errors when cross-compiling for xtensa: cc1: error: unrecognized command line option "-mlongcalls" cc1: error: unrecognized command line option "-mauto-litpools" Signed-off-by: Max Filippov --- tools/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/Makefile b/tools/Makefile index 1c840d7..c224e8a 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -120,7 +120,7 @@ _libfdt.so-sharedobjs += $(LIBFDT_OBJS) libfdt: tools/_libfdt.so: $(patsubst %.o,%.c,$(LIBFDT_OBJS)) tools/libfdt_wrap.c - LDFLAGS="$(HOSTLDFLAGS)" python $(srctree)/lib/libfdt/setup.py \ + LDFLAGS="$(HOSTLDFLAGS)" CFLAGS="" python $(srctree)/lib/libfdt/setup.py \ "$(_hostc_flags)" $^ mv _libfdt.so $@ -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 2/2] rockchip: rk3288: use spl_early_init() instead of spl_init()
2017-03-15 22:43 GMT+08:00 Simon Glass :
> From: Eddie Cai
>
> Use spl_early_init() to make sure that early malloc() is initialised. This
> fixes booting on firefly-rk3288, for example.
>
> Signed-off-by: Eddie Cai
> Signed-off-by: Simon Glass
>
Reviewed-by: Eddie Cai
> ---
>
> Changes in v4:
> - Change debug() message to match new function name
>
> Changes in v3:
> - Rewrite both commit messages
>
> Changes in v2:
> - Add v2 to the series since this is a new version
>
> arch/arm/mach-rockchip/rk3288-board-spl.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c
> b/arch/arm/mach-rockchip/rk3288-board-spl.c
> index e51e19bb2d..74f3379194 100644
> --- a/arch/arm/mach-rockchip/rk3288-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
> @@ -185,9 +185,9 @@ void board_init_f(ulong dummy)
> debug_uart_init();
> #endif
>
> - ret = spl_init();
> + ret = spl_early_init();
> if (ret) {
> - debug("spl_init() failed: %d\n", ret);
> + debug("spl_early_init() failed: %d\n", ret);
> hang();
> }
>
> --
> 2.12.0.367.g23dc2f6d3c-goog
>
>
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Re: [U-Boot] [PATCH v4 1/2] spl: Add spl_early_init()
2017-03-15 22:43 GMT+08:00 Simon Glass :
> From: Eddie Cai
>
> At present malloc_base/_limit/_ptr are not initialised in spl_init() when
> we call spl_init() in board_init_f(). This is due to a recent change aimed
> at avoiding overwriting the malloc area set up on some boards by
> spl_relocate_stack_gd().
>
> However if CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN is not defined, we now
> skip setting up the memory area in spl_init() which is obviously wrong.
>
> To fix this, add a new function spl_early_init() which can be called in
> board_init_f().
>
> Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit)
> Signed-off-by: Eddie Cai
> Rewrote spl_{,early_}init() to avoid duplicate code:
> Rewrite/expand commit message:
> Signed-off-by: Simon Glass
>
Reviewed-by: Eddie Cai
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Rewrote spl_{,early_}init() to avoid duplicate code
> - Rewrite commit message
>
> common/spl/spl.c | 46 +-
> -
> include/asm-generic/global_data.h | 1 +
> include/spl.h | 24 +---
> 3 files changed, 57 insertions(+), 14 deletions(-)
>
> diff --git a/common/spl/spl.c b/common/spl/spl.c
> index 766fb3d6f4..2bc8b42027 100644
> --- a/common/spl/spl.c
> +++ b/common/spl/spl.c
> @@ -170,22 +170,20 @@ __weak void __noreturn jump_to_image_no_args(struct
> spl_image_info *spl_image)
> image_entry();
> }
>
> -int spl_init(void)
> +static int spl_common_init(bool setup_malloc)
> {
> int ret;
>
> - debug("spl_init()\n");
> -/*
> - * with CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN we set malloc_base and
> - * malloc_limit in spl_relocate_stack_gd
> - */
> -#if defined(CONFIG_SYS_MALLOC_F_LEN) && \
> - !defined(CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN)
> + debug("spl_early_init()\n");
> +
> +#if defined(CONFIG_SYS_MALLOC_F_LEN)
> + if (setup_malloc) {
> #ifdef CONFIG_MALLOC_F_ADDR
> - gd->malloc_base = CONFIG_MALLOC_F_ADDR;
> + gd->malloc_base = CONFIG_MALLOC_F_ADDR;
> #endif
> - gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
> - gd->malloc_ptr = 0;
> + gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
> + gd->malloc_ptr = 0;
> + }
> #endif
> if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA))
> {
> ret = fdtdec_setup();
> @@ -202,6 +200,32 @@ int spl_init(void)
> return ret;
> }
> }
> +
> + return 0;
> +}
> +
> +int spl_early_init(void)
> +{
> + int ret;
> +
> + ret = spl_common_init(true);
> + if (ret)
> + return ret;
> + gd->flags |= GD_FLG_SPL_EARLY_INIT;
> +
> + return 0;
> +}
> +
> +int spl_init(void)
> +{
> + int ret;
> +
> + if (!(gd->flags & GD_FLG_SPL_EARLY_INIT)) {
> + ret = spl_common_init(
> + !IS_ENABLED(CONFIG_SPL_STACK_
> R_MALLOC_SIMPLE_LEN));
> + if (ret)
> + return ret;
> + }
> gd->flags |= GD_FLG_SPL_INIT;
>
> return 0;
> diff --git a/include/asm-generic/global_data.h
> b/include/asm-generic/global_data.h
> index e02863dc03..5b356dd231 100644
> --- a/include/asm-generic/global_data.h
> +++ b/include/asm-generic/global_data.h
> @@ -127,5 +127,6 @@ typedef struct global_data {
> #define GD_FLG_SKIP_RELOC 0x00800 /* Don't relocate
> */
> #define GD_FLG_RECORD 0x01000 /* Record console
> */
> #define GD_FLG_ENV_DEFAULT 0x02000 /* Default variable flag
> */
> +#define GD_FLG_SPL_EARLY_INIT 0x04000 /* Early SPL init is done
> */
>
> #endif /* __ASM_GENERIC_GBL_DATA_H */
> diff --git a/include/spl.h b/include/spl.h
> index bde44374ea..cdd196d187 100644
> --- a/include/spl.h
> +++ b/include/spl.h
> @@ -213,11 +213,29 @@ int spl_load_image_ext_os(struct spl_image_info
> *spl_image,
> struct blk_desc *block_dev, int partition);
>
> /**
> - * spl_init() - Set up device tree and driver model in SPL if enabled
> + * spl_early_init() - Set up device tree and driver model in SPL if
> enabled
> *
> * Call this function in board_init_f() if you want to use device tree and
> - * driver model early, before board_init_r() is called. This function will
> - * be called from board_init_r() if not called earlier.
> + * driver model early, before board_init_r() is called.
> + *
> + * If this is not called, then driver model will be inactive in SPL's
> + * board_init_f(), and no device tree will be available.
> + */
> +int spl_early_init(void);
> +
> +/**
> + * spl_init() - Set up device tree and driver model in SPL if enabled
> + *
> + * You can optionally call spl_early_init(), then optionally call
> spl_init().
> + * This function will be called from board_init_r() if not called earlier.
> + *
> + * Both spl_early_init() and spl_init() perform a similar function except
> that
> + * the latter
Re: [U-Boot] [U-Boot 0/2] add spl_early_init to fix rk3288 board broken issue
2017-03-16 9:39 GMT+08:00 Simon Glass : > Hi Eddie, > > On 6 March 2017 at 00:03, Eddie Cai wrote: > > Hi Simon > > I guess you may lost this patch. So a friendly ping. > > I did not lose it, but I thought I commented on it, that we needed to > remove the duplicate code. Perhaps I imagined it sorry. > I checked but didn't find that mail. > > Anyway I have sent out an updated version (now at v4) so please take a > look. I think your approach is the right way to solve it, but I just wanted > to unified the code a bit. > Sure, i will review it. > > > > > > 2017-02-23 9:59 GMT+08:00 Eddie Cai : > >> > >> Andrew F. Davis's below patch broke rk3288 based board. that is because > we > >> call > >> spl_init in board_init_f which is at very early stage. What Andrew want > to > >> fix > >> is calling spl_init very late. That patch will make malloc_base, limit, > >> ptr not > >> initualized in spl_init when we call spl_init in board_init_f. This > patch > >> set > >> add spl_early_init. it can be called in board_init_f. So we can fix this > >> issue > >> by using spl_early_init. > >> > >> commit b3d2861eb20a795b99292b823c923935df26dfc6 > >> Author: Andrew F. Davis > >> Date: Fri Jan 27 10:39:19 2017 -0600 > >> > >> spl: Remove overwrite of relocated malloc limit > >> > >> Eddie Cai (2): > >> spl: add spl_early_init > >> rockchip: use spl_early_init instead of spl_init > >> > >> arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +- > >> common/spl/spl.c | 54 > >> ++- > >> include/asm-generic/global_data.h | 1 + > >> include/spl.h | 12 ++- > >> 4 files changed, 59 insertions(+), 10 deletions(-) > >> > >> -- > >> 2.7.4 > >> > > > > Regards, > Simon > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 13/22] x86: fsp: Save stack address to CMOS for next S3 boot
At the end of pre-relocation phase, save the new stack address
to CMOS and use it as the stack on next S3 boot for fsp_init()
continuation function.
Signed-off-by: Bin Meng
---
arch/x86/cpu/cpu.c | 8
arch/x86/include/asm/cmos_layout.h | 31 +++
arch/x86/include/asm/u-boot-x86.h | 1 +
arch/x86/lib/fsp/fsp_common.c | 30 +-
4 files changed, 69 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/include/asm/cmos_layout.h
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index afc8645..9e2aee2 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -278,6 +278,14 @@ int reserve_arch(void)
high_table_reserve();
#endif
+#if defined(CONFIG_HAVE_ACPI_RESUME) && defined(CONFIG_HAVE_FSP)
+ /*
+* Save stack address to CMOS so that at next S3 boot,
+* we can use it as the stack address for fsp_contiue()
+*/
+ fsp_save_s3_stack();
+#endif
+
return 0;
}
#endif
diff --git a/arch/x86/include/asm/cmos_layout.h
b/arch/x86/include/asm/cmos_layout.h
new file mode 100644
index 000..0a0a51e
--- /dev/null
+++ b/arch/x86/include/asm/cmos_layout.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2017, Bin Meng
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __CMOS_LAYOUT_H
+#define __CMOS_LAYOUT_H
+
+/*
+ * The RTC internal registers and RAM is organized as two banks of 128 bytes
+ * each, called the standard and extended banks. The first 14 bytes of the
+ * standard bank contain the RTC time and date information along with four
+ * registers, A - D, that are used for configuration of the RTC. The extended
+ * bank contains a full 128 bytes of battery backed SRAM.
+ *
+ * For simplicity in U-Boot we only support CMOS in the standard bank, and
+ * its base address starts from offset 0x10, which leaves us 112 bytes space.
+ */
+#define CMOS_BASE 0x10
+
+/*
+ * The file records all offsets off CMOS_BASE that is currently used by
+ * U-Boot for various reasons. It is put in such a unified place in order
+ * to be consistent across platforms.
+ */
+
+/* stack address for S3 boot in a FSP configuration, 4 bytes */
+#define CMOS_FSP_STACK_ADDRCMOS_BASE
+
+#endif /* __CMOS_LAYOUT_H */
diff --git a/arch/x86/include/asm/u-boot-x86.h
b/arch/x86/include/asm/u-boot-x86.h
index 4f901f9..024aaf4 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -56,6 +56,7 @@ u32 isa_map_rom(u32 bus_addr, int size);
int video_bios_init(void);
/* arch/x86/lib/fsp/... */
+int fsp_save_s3_stack(void);
int x86_fsp_init(void);
void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index 2b33fba..df73a2a 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -5,8 +5,12 @@
*/
#include
+#include
#include
+#include
#include
+#include
+#include
#include
#include
#include
@@ -71,9 +75,32 @@ static __maybe_unused void *fsp_prepare_mrc_cache(void)
return cache->data;
}
+#ifdef CONFIG_HAVE_ACPI_RESUME
+int fsp_save_s3_stack(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (gd->arch.prev_sleep_state == ACPI_S3)
+ return 0;
+
+ ret = uclass_get_device(UCLASS_RTC, 0, &dev);
+ if (ret) {
+ debug("Cannot find RTC: err=%d\n", ret);
+ return -ENODEV;
+ }
+
+ /* Save the stack address to CMOS */
+ rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp);
+
+ return 0;
+}
+#endif
+
int x86_fsp_init(void)
{
void *nvs;
+ int stack = CONFIG_FSP_TEMP_RAM_ADDR;
int boot_mode = BOOT_FULL_CONFIG;
#ifdef CONFIG_HAVE_ACPI_RESUME
int prev_sleep_state = chipset_prev_sleep_state();
@@ -102,6 +129,7 @@ int x86_fsp_init(void)
panic("Reboot System");
}
+ stack = cmos_read32(CMOS_FSP_STACK_ADDR);
boot_mode = BOOT_ON_S3_RESUME;
}
#endif
@@ -110,7 +138,7 @@ int x86_fsp_init(void)
* Note the execution does not return to this function,
* instead it jumps to fsp_continue().
*/
- fsp_init(CONFIG_FSP_TEMP_RAM_ADDR, boot_mode, nvs);
+ fsp_init(stack, boot_mode, nvs);
} else {
/*
* The second time we enter here, adjust the size of malloc()
--
2.9.2
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[U-Boot] [PATCH 02/22] x86: acpi: Add Kconfig option and header file for ACPI resume
This introduces a Kconfig option for ACPI S3 resume, as well as a
header file to include anything related to ACPI S3 resume.
Signed-off-by: Bin Meng
---
arch/x86/Kconfig | 12 +
arch/x86/include/asm/acpi_s3.h | 58 ++
2 files changed, 70 insertions(+)
create mode 100644 arch/x86/include/asm/acpi_s3.h
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index dfdd756..7ea9148 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -571,6 +571,18 @@ config GENERATE_ACPI_TABLE
endmenu
+config HAVE_ACPI_RESUME
+ bool "Enable ACPI S3 resume"
+ help
+ Select this to enable ACPI S3 resume. S3 is an ACPI defined sleeping
+ state where all system context is lost except system memory. U-Boot
+ is responsible for restore the machine state as it is before sleep.
+ It needs restore the memory controller, not overwriting memory which
+ is not marked as reserved. For the peripherals which lose their
+ registers, U-Boot needs to write the original value. When everything
+ is done, U-Boot needs to find out the wakeup vector provided by OSes
+ and jump there.
+
config MAX_PIRQ_LINKS
int
default 8
diff --git a/arch/x86/include/asm/acpi_s3.h b/arch/x86/include/asm/acpi_s3.h
new file mode 100644
index 000..6fbfc3e
--- /dev/null
+++ b/arch/x86/include/asm/acpi_s3.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2017, Bin Meng
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ACPI_S3_H__
+#define __ASM_ACPI_S3_H__
+
+/* PM1_STATUS register */
+#define WAK_STS(1 << 15)
+#define PCIEXPWAK_STS (1 << 14)
+#define RTC_STS(1 << 10)
+#define SLPBTN_STS (1 << 9)
+#define PWRBTN_STS (1 << 8)
+#define GBL_STS(1 << 5)
+#define BM_STS (1 << 4)
+#define TMR_STS(1 << 0)
+
+/* PM1_CNT register */
+#define SLP_EN (1 << 13)
+#define SLP_TYP_SHIFT 10
+#define SLP_TYP(7 << SLP_TYP_SHIFT)
+#define SLP_TYP_S0 0
+#define SLP_TYP_S1 1
+#define SLP_TYP_S3 5
+#define SLP_TYP_S4 6
+#define SLP_TYP_S5 7
+
+enum acpi_sleep_state {
+ ACPI_S0,
+ ACPI_S1,
+ ACPI_S2,
+ ACPI_S3,
+ ACPI_S4,
+ ACPI_S5,
+};
+
+/* Given the provided PM1 control register return the ACPI sleep type */
+static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt)
+{
+ switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
+ case SLP_TYP_S0:
+ return ACPI_S0;
+ case SLP_TYP_S1:
+ return ACPI_S1;
+ case SLP_TYP_S3:
+ return ACPI_S3;
+ case SLP_TYP_S4:
+ return ACPI_S4;
+ case SLP_TYP_S5:
+ return ACPI_S5;
+ }
+
+ return -1;
+}
+
+#endif /* __ASM_ACPI_S3_H__ */
--
2.9.2
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[U-Boot] [PATCH 12/22] x86: Add an early CMOS access library
This adds a library that provides CMOS (inside RTC SRAM) access
at a very early stage when driver model is not available yet.
Signed-off-by: Bin Meng
---
arch/x86/include/asm/early_cmos.h | 43 +
arch/x86/lib/Makefile | 1 +
arch/x86/lib/early_cmos.c | 51 +++
3 files changed, 95 insertions(+)
create mode 100644 arch/x86/include/asm/early_cmos.h
create mode 100644 arch/x86/lib/early_cmos.c
diff --git a/arch/x86/include/asm/early_cmos.h
b/arch/x86/include/asm/early_cmos.h
new file mode 100644
index 000..cd2634d
--- /dev/null
+++ b/arch/x86/include/asm/early_cmos.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2017, Bin Meng
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __EARLY_CMOS_H
+#define __EARLY_CMOS_H
+
+/* CMOS actually resides in the RTC SRAM */
+#define CMOS_IO_PORT 0x70
+
+/**
+ * cmos_read8() - Get 8-bit data stored at the given address
+ *
+ * This reads from CMOS for the 8-bit data stored at the given address.
+ *
+ * @addr: RTC SRAM address
+ * @return:8-bit data stored at the given address
+ */
+u8 cmos_read8(u8 addr);
+
+/**
+ * cmos_read16() - Get 16-bit data stored at the given address
+ *
+ * This reads from CMOS for the 16-bit data stored at the given address.
+ *
+ * @addr: RTC SRAM address
+ * @return:16-bit data stored at the given address
+ */
+u16 cmos_read16(u8 addr);
+
+/**
+ * cmos_read32() - Get 32-bit data stored at the given address
+ *
+ * This reads from CMOS for the 32-bit data stored at the given address.
+ *
+ * @addr: RTC SRAM address
+ * @return:32-bit data stored at the given address
+ */
+u32 cmos_read32(u8 addr);
+
+#endif /* __EARLY_CMOS_H */
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index c61f931..cd4e976 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
endif
obj-y += cmd_boot.o
obj-$(CONFIG_SEABIOS) += coreboot_table.o
+obj-y += early_cmos.o
obj-$(CONFIG_EFI) += efi/
obj-y += e820.o
obj-y += gcc.o
diff --git a/arch/x86/lib/early_cmos.c b/arch/x86/lib/early_cmos.c
new file mode 100644
index 000..fa0b327
--- /dev/null
+++ b/arch/x86/lib/early_cmos.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2017, Bin Meng
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * This library provides CMOS (inside RTC SRAM) access routines at a very
+ * early stage when driver model is not available yet. Only read access is
+ * provided. The 16-bit/32-bit read are compatible with driver model RTC
+ * uclass write ops, that data is stored in little-endian mode.
+ */
+
+#include
+#include
+#include
+
+u8 cmos_read8(u8 addr)
+{
+ outb(addr, CMOS_IO_PORT);
+
+ return inb(CMOS_IO_PORT + 1);
+}
+
+u16 cmos_read16(u8 addr)
+{
+ u16 value = 0;
+ u16 data;
+ int i;
+
+ for (i = 0; i < sizeof(value); i++) {
+ data = cmos_read8(addr + i);
+ value |= data << (i << 3);
+ }
+
+ return value;
+}
+
+u32 cmos_read32(u8 addr)
+{
+ u32 value = 0;
+ u32 data;
+ int i;
+
+ for (i = 0; i < sizeof(value); i++) {
+ data = cmos_read8(addr + i);
+ value |= data << (i << 3);
+ }
+
+ return value;
+}
--
2.9.2
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[U-Boot] [PATCH 16/22] x86: apci: Change PM1_CNT register access to RMW
In enter_acpi_mode() PM1_CNT register is changed to PM1_CNT_SCI_EN
directly without preserving its previous value. Update to change
the register access to read-modify-write (RMW).
Signed-off-by: Bin Meng
---
arch/x86/lib/acpi_table.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index f118345..8be8120 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -306,6 +306,8 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
static void enter_acpi_mode(int pm1_cnt)
{
+ u16 val = inw(pm1_cnt);
+
/*
* PM1_CNT register bit0 selects the power management event to be
* either an SCI or SMI interrupt. When this bit is set, then power
@@ -320,7 +322,7 @@ static void enter_acpi_mode(int pm1_cnt)
* system, and expose ourselves to OSPM as working under ACPI mode
* already, turn this bit on.
*/
- outw(PM1_CNT_SCI_EN, pm1_cnt);
+ outw(val | PM1_CNT_SCI_EN, pm1_cnt);
}
/*
--
2.9.2
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[U-Boot] [PATCH 19/22] x86: acpi: Turn on ACPI mode for S3
Before jumping to OS waking up vector, we need turn on ACPI mode
for S3, just like what we do for a normal boot.
Signed-off-by: Bin Meng
---
arch/x86/lib/acpi_s3.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c
index e5cc3b0..0b62b75 100644
--- a/arch/x86/lib/acpi_s3.c
+++ b/arch/x86/lib/acpi_s3.c
@@ -24,6 +24,9 @@ void acpi_resume(struct acpi_fadt *fadt)
{
void *wake_vec;
+ /* Turn on ACPI mode for S3 */
+ enter_acpi_mode(fadt->pm1a_cnt_blk);
+
wake_vec = acpi_find_wakeup_vector(fadt);
post_code(POST_OS_RESUME);
--
2.9.2
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[U-Boot] [PATCH 18/22] x86: acpi: Refactor acpi_resume()
To do something more in acpi_resume() like turning on ACPI mode,
we need locate ACPI FADT table pointer first. But currently this
is done in acpi_find_wakeup_vector().
This changes acpi_resume() signature to accept ACPI FADT pointer
as the parameter. A new API acpi_find_fadt() is introduced, and
acpi_find_wakeup_vector() is updated to use FADT pointer as the
parameter as well.
Signed-off-by: Bin Meng
---
arch/x86/cpu/cpu.c| 6 +++---
arch/x86/include/asm/acpi_s3.h| 5 +++--
arch/x86/include/asm/acpi_table.h | 3 ++-
arch/x86/lib/acpi_s3.c| 7 ++-
arch/x86/lib/acpi_table.c | 16 +++-
5 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index bd5aeb8..42fe8a2 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -208,10 +208,10 @@ int last_stage_init(void)
board_final_cleanup();
#if CONFIG_HAVE_ACPI_RESUME
- void *wake_vector = acpi_find_wakeup_vector();
+ struct acpi_fadt *fadt = acpi_find_fadt();
- if (wake_vector != NULL && gd->arch.prev_sleep_state == ACPI_S3)
- acpi_resume(wake_vector);
+ if (fadt != NULL && gd->arch.prev_sleep_state == ACPI_S3)
+ acpi_resume(fadt);
#endif
write_tables();
diff --git a/arch/x86/include/asm/acpi_s3.h b/arch/x86/include/asm/acpi_s3.h
index 5892a8b..567ed3e 100644
--- a/arch/x86/include/asm/acpi_s3.h
+++ b/arch/x86/include/asm/acpi_s3.h
@@ -100,15 +100,16 @@ enum acpi_sleep_state chipset_prev_sleep_state(void);
*/
void chipset_clear_sleep_state(void);
+struct acpi_fadt;
/**
* acpi_resume() - Do ACPI S3 resume
*
* This calls U-Boot wake up assembly stub and jumps to OS's wake up vector.
*
- * @wake_vec: OS wake up vector
+ * @fadt: FADT table pointer in the ACPI table
* @return:Never returns
*/
-void acpi_resume(void *wake_vec);
+void acpi_resume(struct acpi_fadt *fadt);
#endif /* __ASSEMBLY__ */
diff --git a/arch/x86/include/asm/acpi_table.h
b/arch/x86/include/asm/acpi_table.h
index 3e11362..c9eba42 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -318,4 +318,5 @@ u32 acpi_fill_madt(u32 current);
void acpi_create_gnvs(struct acpi_global_nvs *gnvs);
void enter_acpi_mode(int pm1_cnt);
ulong write_acpi_tables(ulong start);
-void *acpi_find_wakeup_vector(void);
+struct acpi_fadt *acpi_find_fadt(void);
+void *acpi_find_wakeup_vector(struct acpi_fadt *);
diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c
index f679c06..e5cc3b0 100644
--- a/arch/x86/lib/acpi_s3.c
+++ b/arch/x86/lib/acpi_s3.c
@@ -6,6 +6,7 @@
#include
#include
+#include
#include
static void asmlinkage (*acpi_do_wakeup)(void *vector) = (void *)WAKEUP_BASE;
@@ -19,8 +20,12 @@ static void acpi_jump_to_wakeup(void *vector)
acpi_do_wakeup(vector);
}
-void acpi_resume(void *wake_vec)
+void acpi_resume(struct acpi_fadt *fadt)
{
+ void *wake_vec;
+
+ wake_vec = acpi_find_wakeup_vector(fadt);
+
post_code(POST_OS_RESUME);
acpi_jump_to_wakeup(wake_vec);
}
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 87a71ca..01d5b6f 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -460,18 +460,14 @@ static struct acpi_rsdp *acpi_valid_rsdp(struct acpi_rsdp
*rsdp)
return rsdp;
}
-void *acpi_find_wakeup_vector(void)
+struct acpi_fadt *acpi_find_fadt(void)
{
char *p, *end;
struct acpi_rsdp *rsdp = NULL;
struct acpi_rsdt *rsdt;
struct acpi_fadt *fadt = NULL;
- struct acpi_facs *facs;
- void *wake_vec;
int i;
- debug("Trying to find the wakeup vector...\n");
-
/* Find RSDP */
for (p = (char *)ROM_TABLE_ADDR; p < (char *)ROM_TABLE_END; p += 16) {
rsdp = acpi_valid_rsdp((struct acpi_rsdp *)p);
@@ -499,6 +495,16 @@ void *acpi_find_wakeup_vector(void)
return NULL;
debug("FADT found at %p\n", fadt);
+ return fadt;
+}
+
+void *acpi_find_wakeup_vector(struct acpi_fadt *fadt)
+{
+ struct acpi_facs *facs;
+ void *wake_vec;
+
+ debug("Trying to find the wakeup vector...\n");
+
facs = (struct acpi_facs *)fadt->firmware_ctrl;
if (facs == NULL) {
--
2.9.2
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