[U-Boot] [PATCHv3 1/5] mtd: nand: add initialization flag
From: Hou Zhiqiang
Add initialization flag to avoid initializing NAND Flash multiple
times, otherwise it will calculate a wrong total size.
Signed-off-by: Hou Zhiqiang
---
V3:
- no change
drivers/mtd/nand/nand.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index 0551241..3ea2dcf 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -133,6 +133,16 @@ static void create_mtd_concat(void)
void nand_init(void)
{
+ static int initialized;
+
+ /*
+* Avoid initializing NAND Flash multiple times,
+* otherwise it will calculate a wrong total size.
+*/
+ if (initialized)
+ return;
+ initialized = 1;
+
#ifdef CONFIG_SYS_NAND_SELF_INIT
board_nand_init();
#else
--
2.1.0.27.g96db324
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[U-Boot] [PATCHv3 2/5] mtd: nand: remove nand size print from nand_init function
From: Hou Zhiqiang
Add nand_size() function to move the nand size print into initr_nand().
Remove nand size print from nand_init() to allow other function to call
nand_init() without printing nand size.
Signed-off-by: Hou Zhiqiang
---
V3:
- no change
common/board_r.c| 1 +
drivers/mtd/nand/nand.c | 7 +--
include/nand.h | 1 +
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c
index 5c9e698..3344913 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -426,6 +426,7 @@ static int initr_nand(void)
{
puts("NAND: ");
nand_init();
+ printf("%lu MiB\n", nand_size() / 1024);
return 0;
}
#endif
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index 3ea2dcf..168bac6 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -131,6 +131,11 @@ static void create_mtd_concat(void)
}
#endif
+unsigned long nand_size(void)
+{
+ return total_nand_size;
+}
+
void nand_init(void)
{
static int initialized;
@@ -152,8 +157,6 @@ void nand_init(void)
nand_init_chip(i);
#endif
- printf("%lu MiB\n", total_nand_size / 1024);
-
#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
/*
* Select the chip in the board/cpu specific driver
diff --git a/include/nand.h b/include/nand.h
index b6eb223..a1f6632 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -28,6 +28,7 @@
#endif
extern void nand_init(void);
+extern unsigned long nand_size(void);
#include
#include
--
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[U-Boot] [PATCHv3 3/5] fsl PPA: add support PPA image loading from NAND and SD
From: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
V3:
- Added checking for return value of mmc initialization.
- Added checking the fdt header before getting the size of PPA image.
arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 143 +++-
1 file changed, 142 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
index b68e87d..b35ad5f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier:GPL-2.0+
*/
#include
+#include
#include
#include
#include
@@ -21,9 +22,17 @@
#include
#endif
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_NAND
+#include
+#elif defined(CONFIG_SYS_LS_PPA_FW_IN_MMC)
+#include
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
int ppa_init(void)
{
- const void *ppa_fit_addr;
+ void *ppa_fit_addr;
u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
int ret;
@@ -34,10 +43,137 @@ int ppa_init(void)
#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
+ debug("%s: PPA image load from XIP\n", __func__);
+#else /* !CONFIG_SYS_LS_PPA_FW_IN_XIP */
+ size_t fw_length, fdt_header_len = sizeof(struct fdt_header);
+
+ /* Copy PPA image from MMC/SD/NAND to allocated memory */
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_MMC
+ struct mmc *mmc;
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+ struct fdt_header *fitp;
+ u32 cnt;
+ u32 blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512;
+
+ debug("%s: PPA image load from eMMC/SD\n", __func__);
+
+ ret = mmc_initialize(gd->bd);
+ if (ret) {
+ printf("%s: mmc_initialize() failed\n", __func__);
+ return ret;
+ }
+ mmc = find_mmc_device(dev);
+ if (!mmc) {
+ printf("PPA: MMC cannot find device for PPA firmware\n");
+ return -ENODEV;
+ }
+
+ ret = mmc_init(mmc);
+ if (ret) {
+ printf("%s: mmc_init() failed\n", __func__);
+ return ret;
+ }
+
+ fitp = malloc(roundup(fdt_header_len, 512));
+ if (!fitp) {
+ printf("PPA: malloc failed for FIT header(size 0x%zx)\n",
+ roundup(fdt_header_len, 512));
+ return -ENOMEM;
+ }
+
+ cnt = DIV_ROUND_UP(fdt_header_len, 512);
+ debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n",
+ __func__, dev, blk, cnt);
+ ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, fitp);
+ if (ret != cnt) {
+ free(fitp);
+ printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
+ CONFIG_SYS_LS_PPA_FW_ADDR);
+ return -EIO;
+ }
+
+ /* flush cache after read */
+ flush_cache((ulong)fitp, cnt * 512);
+
+ ret = fdt_check_header(fitp);
+ if (ret) {
+ free(fitp);
+ printf("%s: fdt_check_header() failed\n", __func__);
+ return ret;
+ }
+
+ fw_length = fdt_totalsize(fitp);
+ free(fitp);
+
+ fw_length = roundup(fw_length, 512);
+ ppa_fit_addr = malloc(fw_length);
+ if (!ppa_fit_addr) {
+ printf("PPA: malloc failed for PPA image(size 0x%zx)\n",
+ fw_length);
+ return -ENOMEM;
+ }
+
+ cnt = DIV_ROUND_UP(fw_length, 512);
+ debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n",
+ __func__, dev, blk, cnt);
+ ret = mmc->block_dev.block_read(&mmc->block_dev,
+ blk, cnt, ppa_fit_addr);
+ if (ret != cnt) {
+ free(ppa_fit_addr);
+ printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
+ CONFIG_SYS_LS_PPA_FW_ADDR);
+ return -EIO;
+ }
+
+ /* flush cache after read */
+ flush_cache((ulong)ppa_fit_addr, cnt * 512);
+
+#elif defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
+ struct fdt_header fit;
+
+ debug("%s: PPA image load from NAND\n", __func__);
+
+ nand_init();
+ ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
+ &fdt_header_len, (u_char *)&fit);
+ if (ret == -EUCLEAN) {
+ printf("NAND read of PPA FIT header at offset 0x%x failed\n",
+ CONFIG_SYS_LS_PPA_FW_ADDR);
+ return -EIO;
+ }
+
+ ret = fdt_check_header(&fit);
+ if (ret) {
+ printf("%s: fdt_check_header() failed\n", __func__);
+ return ret;
+ }
+
+ fw_length = fdt_totalsize(&fit);
+
+ ppa_fit_addr = malloc(fw_length);
+ if (!ppa_fit_addr) {
+ printf("PPA: malloc failed for PPA image(size 0x%zx)\n",
+ fw_length);
+ return -ENOMEM;
+ }
+
+ ret = nand_read(nand_
[U-Boot] [PATCHv3 5/5] fsl-layerscape/ls104xardb: enable PPA support for eMMC/SD and NAND boot
From: Hou Zhiqiang Signed-off-by: Hou Zhiqiang --- V3: - no change configs/ls1043ardb_nand_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + configs/ls1046ardb_emmc_defconfig | 1 + configs/ls1046ardb_sdcard_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 4f4ae5a..ed429cb 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" CONFIG_NAND_BOOT=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index e57c42b..02b5b54 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_SD_BOOT=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 9beb050..711fc10 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,EMMC_BOOT" CONFIG_SD_BOOT=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 032aab3..a3965f2 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL" CONFIG_SD_BOOT=y -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv3 4/5] Kconfig: fsl-ppa: support load PPA from eMMC/SD and NAND Flash
From: Hou Zhiqiang Signed-off-by: Hou Zhiqiang --- V3: - no change arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a99b1c6..6494d7b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -134,6 +134,8 @@ config FSL_LS_PPA choice prompt "FSL Layerscape PPA firmware loading-media select" depends on FSL_LS_PPA + default SYS_LS_PPA_FW_IN_MMC if SD_BOOT + default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT default SYS_LS_PPA_FW_IN_XIP config SYS_LS_PPA_FW_IN_XIP @@ -142,12 +144,24 @@ config SYS_LS_PPA_FW_IN_XIP Say Y here if the PPA firmware locate at XIP flash, such as NOR or QSPI flash. +config SYS_LS_PPA_FW_IN_MMC + bool "eMMC or SD Card" + help + Say Y here if the PPA firmware locate at eMMC/SD card. + +config SYS_LS_PPA_FW_IN_NAND + bool "NAND" + help + Say Y here if the PPA firmware locate at NAND flash. + endchoice config SYS_LS_PPA_FW_ADDR hex "Address of PPA firmware loading from" depends on FSL_LS_PPA default 0x4050 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT + default 0x50 if SYS_LS_PPA_FW_IN_MMC + default 0x50 if SYS_LS_PPA_FW_IN_NAND default 0x6050 if SYS_LS_PPA_FW_IN_XIP help If the PPA firmware locate at XIP flash, such as NOR or -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: am43xx: fix SOC revision print outs
On Thu, 16 Mar 2017 09:48:54 +0200
Tero Kristo wrote:
> Currently, AM43xx just re-uses the version strings from AM33xx which
> is wrong; the actual values for AM43xx are different. Fix this by
> adding a separate version string array for AM43xx and use this
> instead.
>
> Signed-off-by: Tero Kristo
> Reported-by: Sekhar Nori
> ---
> arch/arm/mach-omap2/am33xx/sys_info.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c
> b/arch/arm/mach-omap2/am33xx/sys_info.c index f0f72fa..e4fc461 100644
> --- a/arch/arm/mach-omap2/am33xx/sys_info.c
> +++ b/arch/arm/mach-omap2/am33xx/sys_info.c
> @@ -74,6 +74,10 @@ static char *cpu_revs[] = {
> "2.0",
> "2.1"};
>
> +static char *cpu_revs_am43xx[] = {
> + "1.0",
> + "1.1",
> + "1.2"};
>
> static char *dev_types[] = {
> "TST",
> @@ -87,6 +91,7 @@ static char *dev_types[] = {
> int print_cpuinfo(void)
> {
> char *cpu_s, *sec_s, *rev_s;
> + char **cpu_rev_arr = cpu_revs;
>
> switch (get_cpu_type()) {
> case AM335X:
> @@ -97,6 +102,7 @@ int print_cpuinfo(void)
> break;
> case AM437X:
> cpu_s = "AM437X";
> + cpu_rev_arr = cpu_revs_am43xx;
> break;
> default:
> cpu_s = "Unknown CPU type";
> @@ -104,7 +110,7 @@ int print_cpuinfo(void)
> }
>
> if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
> - rev_s = cpu_revs[get_cpu_rev()];
> + rev_s = cpu_rev_arr[get_cpu_rev()];
> else
> rev_s = "?";
>
Reviewed-by: Lukasz Majewski
Best regards,
Lukasz Majewski
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Re: [U-Boot] [PATCH 02/17] dm: Simple Watchdog uclass
Hi Maxim,
> This is a simple uclass for Watchdog Timers. It has four operations:
> start, restart, reset, stop. Drivers must implement start, restart and
> stop operations, while implementing reset is optional: It's default
> implementation expires watchdog timer in one clock tick.
>
> Signed-off-by: Maxim Sloyko
Reviewed-by: Lukasz Majewski
> ---
>
> drivers/watchdog/Kconfig | 11 +
> drivers/watchdog/Makefile | 1 +
> drivers/watchdog/wdt-uclass.c | 79
> +++ include/dm/uclass-id.h|
> 1 + include/wdt.h | 97
> +++ 5 files changed, 189
> insertions(+) create mode 100644 drivers/watchdog/wdt-uclass.c
> create mode 100644 include/wdt.h
>
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index e69de29bb2..0d7366f3df 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -0,0 +1,11 @@
> +menu "Watchdog Timer Support"
> +
> +config WDT
> + bool "Enable driver model for watchdog timer drivers"
> + depends on DM
> + help
> + Enable driver model for watchdog timer. At the moment the
> API
> + is very simple and only supports four operations:
> + start, restart, stop and reset (expire immediately).
> + What exactly happens when the timer expires is up to a
> particular
> + device/driver.
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index a007ae8234..1aabcb97ae 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -15,3 +15,4 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
> obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
> obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
> obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
> +obj-$(CONFIG_WDT) += wdt-uclass.o
> diff --git a/drivers/watchdog/wdt-uclass.c
> b/drivers/watchdog/wdt-uclass.c new file mode 100644
> index 00..98a8b529f9
> --- /dev/null
> +++ b/drivers/watchdog/wdt-uclass.c
> @@ -0,0 +1,79 @@
> +/*
> + * Copyright 2017 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * Implement a simple watchdog uclass. Watchdog is basically a timer
> that
> + * is used to detect or recover from malfunction. During normal
> operation
> + * the watchdog would be regularly reset to prevent it from timing
> out.
> + * If, due to a hardware fault or program error, the computer fails
> to reset
> + * the watchdog, the timer will elapse and generate a timeout signal.
> + * The timeout signal is used to initiate corrective action or
> actions,
> + * which typically include placing the system in a safe, known state.
> + */
> +
> +int wdt_start(struct udevice *dev, u64 timeout, ulong flags)
> +{
> + const struct wdt_ops *ops = device_get_ops(dev);
> +
> + if (!ops->start)
> + return -ENOSYS;
> +
> + return ops->start(dev, timeout, flags);
> +}
> +
> +int wdt_stop(struct udevice *dev)
> +{
> + const struct wdt_ops *ops = device_get_ops(dev);
> +
> + if (!ops->stop)
> + return -ENOSYS;
> +
> + return ops->stop(dev);
> +}
> +
> +int wdt_restart(struct udevice *dev)
> +{
> + const struct wdt_ops *ops = device_get_ops(dev);
> +
> + if (!ops->restart)
> + return -ENOSYS;
> +
> + return ops->restart(dev);
> +}
> +
> +int wdt_reset(struct udevice *dev, ulong flags)
> +{
> + const struct wdt_ops *ops;
> +
> + debug("WDT Resettting: %lu\n", flags);
> + ops = device_get_ops(dev);
> + if (ops->reset) {
> + return ops->reset(dev, flags);
> + } else {
> + if (!ops->start)
> + return -ENOSYS;
> +
> + ops->start(dev, 1, flags);
> + while (1)
> + ;
> + }
> +
> + return 0;
> +}
> +
> +UCLASS_DRIVER(wdt) = {
> + .id = UCLASS_WDT,
> + .name = "wdt",
> +};
> diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
> index 8c92d0b030..b73a7fd436 100644
> --- a/include/dm/uclass-id.h
> +++ b/include/dm/uclass-id.h
> @@ -83,6 +83,7 @@ enum uclass_id {
> UCLASS_VIDEO, /* Video or LCD device */
> UCLASS_VIDEO_BRIDGE,/* Video bridge, e.g.
> DisplayPort to LVDS */ UCLASS_VIDEO_CONSOLE, /* Text console
> driver for video device */
> + UCLASS_WDT, /* Watchdot Timer driver */
>
> UCLASS_COUNT,
> UCLASS_INVALID = -1,
> diff --git a/include/wdt.h b/include/wdt.h
> new file mode 100644
> index 00..1da5a962df
> --- /dev/null
> +++ b/include/wdt.h
> @@ -0,0 +1,97 @@
> +/*
> + * Copyright 2017 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef _WDT_H_
> +#define _WDT_H_
> +
> +/*
> + * Start the timer
> + *
> + * @dev: WDT Device
> + * @timeout: Number of ticks before timer expires
> + * @flags: Driver sp
[U-Boot] [PATCH v5 1/1] usb: gadget: avoid variable name clipping in cb_getvar
From: Nicolas Le Bayon
Instead of using a fixed-size array to store variable name, preferring a
dynamic allocation treats correctly all variable name lengths.
Variable names are growing through releases and features. By this way, name
clipping is prevented.
Signed-off-by: Nicolas Le Bayon
---
drivers/usb/gadget/f_fastboot.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_
fastboot.c
index 2160b1c..7cd6d24 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -432,9 +432,15 @@ static void cb_getvar(struct usb_ep *ep, struct
usb_request *req)
else
strcpy(response, "FAILValue not set");
} else {
- char envstr[32];
+ char *envstr;
- snprintf(envstr, sizeof(envstr) - 1, "fastboot.%s", cmd);
+ envstr = malloc(strlen("fastboot.") + strlen(cmd) + 1);
+ if (!envstr) {
+ fastboot_tx_write_str("FAILmalloc error");
+ return;
+ }
+
+ sprintf(envstr, "fastboot.%s", cmd);
s = getenv(envstr);
if (s) {
strncat(response, s, chars_left);
@@ -442,6 +448,8 @@ static void cb_getvar(struct usb_ep *ep, struct
usb_request *req)
printf("WARNING: unknown variable: %s\n", cmd);
strcpy(response, "FAILVariable not implemented");
}
+
+ free(envstr);
}
fastboot_tx_write_str(response);
}
--
1.9.1
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Re: [U-Boot] [PATCH] tools: imximage: add set bit command
On 16/03/2017 07:35, Peng Fan wrote:
> Add set bit command support.
> Usage: SET_BIT 4 [address] [bitmask]
>
> Signed-off-by: Peng Fan
> Cc: Stefano Babic
> ---
> tools/imximage.c | 12
> tools/imximage.h | 4 +++-
> 2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/tools/imximage.c b/tools/imximage.c
> index 0c43196..eb7e682 100644
> --- a/tools/imximage.c
> +++ b/tools/imximage.c
> @@ -23,6 +23,7 @@ static table_entry_t imximage_cmds[] = {
> {CMD_BOOT_OFFSET, "BOOT_OFFSET", "Boot offset",},
> {CMD_WRITE_DATA,"DATA", "Reg Write Data", },
> {CMD_WRITE_CLR_BIT, "CLR_BIT", "Reg clear bit", },
> + {CMD_WRITE_SET_BIT, "SET_BIT", "Reg set bit", },
> {CMD_CHECK_BITS_SET,"CHECK_BITS_SET", "Reg Check bits set", },
> {CMD_CHECK_BITS_CLR,"CHECK_BITS_CLR", "Reg Check bits clr", },
> {CMD_CSF, "CSF", "Command Sequence File", },
> @@ -204,6 +205,15 @@ static void set_dcd_param_v2(struct imx_header *imxhdr,
> uint32_t dcd_len,
> d->write_dcd_command.length = cpu_to_be16(4);
> d->write_dcd_command.param = DCD_WRITE_CLR_BIT_PARAM;
> break;
> + case CMD_WRITE_SET_BIT:
> + if ((d->write_dcd_command.tag == DCD_WRITE_DATA_COMMAND_TAG) &&
> + (d->write_dcd_command.param == DCD_WRITE_SET_BIT_PARAM))
> + break;
> + d = d2;
> + d->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
> + d->write_dcd_command.length = cpu_to_be16(4);
> + d->write_dcd_command.param = DCD_WRITE_SET_BIT_PARAM;
> + break;
> /*
>* Check data command only supports one entry,
>*/
> @@ -636,6 +646,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr,
> int32_t cmd, char *token,
> break;
> case CMD_WRITE_DATA:
> case CMD_WRITE_CLR_BIT:
> + case CMD_WRITE_SET_BIT:
> case CMD_CHECK_BITS_SET:
> case CMD_CHECK_BITS_CLR:
> value = get_cfg_value(token, name, lineno);
> @@ -686,6 +697,7 @@ static void parse_cfg_fld(struct imx_header *imxhdr,
> int32_t *cmd,
> switch(*cmd) {
> case CMD_WRITE_DATA:
> case CMD_WRITE_CLR_BIT:
> + case CMD_WRITE_SET_BIT:
> case CMD_CHECK_BITS_SET:
> case CMD_CHECK_BITS_CLR:
>
> diff --git a/tools/imximage.h b/tools/imximage.h
> index db8b9a3..78d48bb 100644
> --- a/tools/imximage.h
> +++ b/tools/imximage.h
> @@ -50,7 +50,8 @@
> #define DCD_VERSION 0x40
> #define DCD_WRITE_DATA_COMMAND_TAG 0xCC
> #define DCD_WRITE_DATA_PARAM 0x4
> -#define DCD_WRITE_CLR_BIT_PARAM 0xC
> +#define DCD_WRITE_CLR_BIT_PARAM 0xC
> +#define DCD_WRITE_SET_BIT_PARAM 0x1C
> #define DCD_CHECK_DATA_COMMAND_TAG 0xCF
> #define DCD_CHECK_BITS_SET_PARAM 0x14
> #define DCD_CHECK_BITS_CLR_PARAM 0x04
> @@ -62,6 +63,7 @@ enum imximage_cmd {
> CMD_BOOT_OFFSET,
> CMD_WRITE_DATA,
> CMD_WRITE_CLR_BIT,
> + CMD_WRITE_SET_BIT,
> CMD_CHECK_BITS_SET,
> CMD_CHECK_BITS_CLR,
> CMD_CSF,
>
Reviewed-by: Stefano Babic
Best regards,
Stefano Babic
--
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Re: [U-Boot] [PATCH] da850: Add instructions to copy AIS image to NAND
On Thursday 16 March 2017 04:02 PM, Axel Haslam wrote: > Add instructions to write an AIS image to NAND > by using the u-boot nand tools. > > Signed-off-by: Axel Haslam > --- > board/davinci/da8xxevm/README.da850 | 22 ++ > 1 file changed, 22 insertions(+) > > diff --git a/board/davinci/da8xxevm/README.da850 > b/board/davinci/da8xxevm/README.da850 > index 29cb4ec..81b7b58 100644 > --- a/board/davinci/da8xxevm/README.da850 > +++ b/board/davinci/da8xxevm/README.da850 > @@ -47,6 +47,28 @@ U-Boot > sf erase 0 +32 > U-Boot > tftp u-boot.ais > U-Boot > sf write c070 0 $filesize > > +Flashing the images to NAND > +=== > +The AIS image can be written to NAND using the u-boot "nand" > +commands. > + > +Example: > + > +The OMAPL138_LCDK requires the AIS image to be written to block 1 of > +the NAND flash. > + > + 1 - Find out the block size using "nand info" > + 2 - Download the AIS image to memory > + 3 - Write the AIS image form memory to the first block > + > +In the case of the LCDK: > + U-Boot > nand info > + Erase size131072 b (0x2) > + U-Boot > tftp u-boot.ais > + Load address: 0xc070 > + Bytes transferred = 477448 (74908 hex) > + U-Boot > nand write 0xc070 0x2 0x75000 Need to erase nand before this step. Also, if mtdparts are defined, the steps can be as simple as U-Boot > nand erase.part NAND.u-boot.ais U-Boot > tftp u-boot.ais U-Boot > nand write 0xc070 NAND.u-boot.ais No need to find the erase size or doing manual of filesize to next erase block boundary. Thanks, Sekhar ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] da850: Add instructions to copy AIS image to NAND
On Friday 17 March 2017 03:50 PM, Sekhar Nori wrote: > No need to find the erase size or doing manual of filesize to next erase > block boundary. Should have read as: No need to find nand erase size or doing manual adjustment of downloaded file size to next erase block boundary. Thanks, Sekhar ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] da850: Add instructions to copy AIS image to NAND
Hi Sekhar On Fri, Mar 17, 2017 at 11:26 AM, Sekhar Nori wrote: > On Friday 17 March 2017 03:50 PM, Sekhar Nori wrote: >> No need to find the erase size or doing manual of filesize to next erase >> block boundary. > > Should have read as: > > No need to find nand erase size or doing manual adjustment of downloaded > file size to next erase block boundary. Ill send v2 adding the case were partitions are defined, and add the erase command to the instructions. Regards -Axel. > > Thanks, > Sekhar > > > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 10/14] drivers: net: add MV88E6xx to Kconfig
On 13/03/2017 16:51, Tim Harvey wrote: > Signed-off-by: Tim Harvey > --- > drivers/net/Kconfig | 18 ++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > index 078d5a8..a24bb06 100644 > --- a/drivers/net/Kconfig > +++ b/drivers/net/Kconfig > @@ -141,6 +141,24 @@ config MACB > GEM (Gigabit Ethernet MAC) found in some ARM SoC devices. > Say Y to include support for the MACB/GEM chip. > > +config MV88E61XX_SWITCH > + bool "Marvell MV88E61xx Gigabit switch support" > + help > + This driver supports the mv88e6176 and similar switches. > + > +if MV88E61XX_SWITCH > + > +config MV88E61XX_CPU_PORT > + int "CPU Port" > + > +config MV88E61XX_PHY_PORTS > + hex "Bitmask of PHY Ports" > + > +config MV88E61XX_FIXED_PORTS > + hex "Bitmask of PHYless serdes Ports" > + > +endif # MV88E61XX_SWITCH > + > config PCH_GBE > bool "Intel Platform Controller Hub EG20T GMAC driver" > depends on DM_ETH && DM_PCI > I do not understand this patch: the switch is already added into drivers/net/phy/Kconfig, where it should be, and it should not be in drivers/net/Kconfig where you want to put it. So I am expecting you add if MV88E61XX_SWITCH into drivers/net/phy/Kconfig and not here. Added Joe as network maintainer. Regards, Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 00/14] Gateworks Ventana add support for new boards
On 13/03/2017 16:51, Tim Harvey wrote: > This is a series of minor cleanups and addition of some new boards in the > Gateworks Ventana product family. > > Tim Harvey (14): > imx: ventana: add additional DRAM configurations > imx: ventana: config: add gzwrite support > imx: ventana: move mmc_init to common > imx: ventana: use mmc_root in boot scripts > imx: ventana: change name of rs232_en to indicate polarity > imx: ventana: fix hwconfig > imx: ventana: make OTG VBUS power enable board specific > imx: ventana: make SD3_VSELECT board specific > imx: ventana: add EMMC configuration > drivers: net: add MV88E6xx to Kconfig > imx: ventana: add GW5904 support > imx: ventana: add GW560x support > imx: ventana: add GW5903 support > imx: ventana: config: add EMMC boot options > > board/gateworks/gw_ventana/README | 17 +- > board/gateworks/gw_ventana/common.c | 553 > ++-- > board/gateworks/gw_ventana/common.h | 6 +- > board/gateworks/gw_ventana/eeprom.c | 15 +- > board/gateworks/gw_ventana/gsc.c| 4 + > board/gateworks/gw_ventana/gw_ventana.c | 95 +++-- > board/gateworks/gw_ventana/gw_ventana_spl.c | 93 + > board/gateworks/gw_ventana/ventana_eeprom.h | 3 + > configs/gwventana_defconfig | 64 > configs/gwventana_emmc_defconfig| 63 > configs/gwventana_gw5904_defconfig | 68 > configs/gwventana_nand_defconfig| 64 > drivers/net/Kconfig | 18 + > include/configs/gw_ventana.h| 18 +- > 14 files changed, 924 insertions(+), 157 deletions(-) > delete mode 100644 configs/gwventana_defconfig > create mode 100644 configs/gwventana_emmc_defconfig > create mode 100644 configs/gwventana_gw5904_defconfig > create mode 100644 configs/gwventana_nand_defconfig > Reviewed-by: Stefano Babic Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 01/14] imx: ventana: add additional DRAM configurations
On 13/03/2017 16:51, Tim Harvey wrote:
> - 64bit 8gB density (4GiB) IMX6DQ
> - 64bit 4gB density (2GiB) IMX6SDL
>
> Signed-off-by: Tim Harvey
> ---
> board/gateworks/gw_ventana/gw_ventana_spl.c | 45
> +
> 1 file changed, 45 insertions(+)
>
> diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c
> b/board/gateworks/gw_ventana/gw_ventana_spl.c
> index b610e06..8cc2a57 100644
> --- a/board/gateworks/gw_ventana/gw_ventana_spl.c
> +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
> @@ -355,6 +355,25 @@ static struct mx6_mmdc_calibration
> mx6dq_256x64_mmdc_calib = {
> .p1_mpwrdlctl = 0X40304239,
> };
>
> +static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
> + /* write leveling calibration determine */
> + .p0_mpwldectrl0 = 0x0048004A,
> + .p0_mpwldectrl1 = 0x003F004A,
> + .p1_mpwldectrl0 = 0x001E0028,
> + .p1_mpwldectrl1 = 0x002C0043,
> + /* Read DQS Gating calibration */
> + .p0_mpdgctrl0 = 0x02250219,
> + .p0_mpdgctrl1 = 0x01790202,
> + .p1_mpdgctrl0 = 0x02080208,
> + .p1_mpdgctrl1 = 0x016C0175,
> + /* Read Calibration: DQS delay relative to DQ read access */
> + .p0_mprddlctl = 0x4A4C4D4C,
> + .p1_mprddlctl = 0x494C4A48,
> + /* Write Calibration: DQ/DM delay relative to DQS write access */
> + .p0_mpwrdlctl = 0x403F3437,
> + .p1_mpwrdlctl = 0x383A3930,
> +};
> +
> static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
> /* write leveling calibration determine */
> .p0_mpwldectrl0 = 0x002A0025,
> @@ -368,6 +387,25 @@ static struct mx6_mmdc_calibration
> mx6dq_512x32_mmdc_calib = {
> .p0_mpwrdlctl = 0x303E3C36,
> };
>
> +static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
> + /* write leveling calibration determine */
> + .p0_mpwldectrl0 = 0x00230020,
> + .p0_mpwldectrl1 = 0x002F002A,
> + .p1_mpwldectrl0 = 0x001D0027,
> + .p1_mpwldectrl1 = 0x00100023,
> + /* Read DQS Gating calibration */
> + .p0_mpdgctrl0 = 0x03250339,
> + .p0_mpdgctrl1 = 0x031C0316,
> + .p1_mpdgctrl0 = 0x03210331,
> + .p1_mpdgctrl1 = 0x031C025A,
> + /* Read Calibration: DQS delay relative to DQ read access */
> + .p0_mprddlctl = 0x40373C40,
> + .p1_mprddlctl = 0x3A373646,
> + /* Write Calibration: DQ/DM delay relative to DQS write access */
> + .p0_mpwrdlctl = 0x2E353933,
> + .p1_mpwrdlctl = 0x3C2F3F35,
> +};
> +
> static void spl_dram_init(int width, int size_mb, int board_model)
> {
> struct mx6_ddr3_cfg *mem = NULL;
> @@ -468,7 +506,14 @@ static void spl_dram_init(int width, int size_mb, int
> board_model)
> mem = &mt41k256m16ha_125;
> if (is_cpu_type(MXC_CPU_MX6Q))
> calib = &mx6dq_256x64_mmdc_calib;
> + else
> + calib = &mx6sdl_256x64_mmdc_calib;
> debug("4gB density\n");
> + } else if (width == 64 && size_mb == 4096) {
> + mem = &mt41k512m16ha_125;
> + if (is_cpu_type(MXC_CPU_MX6Q))
> + calib = &mx6dq_512x64_mmdc_calib;
> + debug("8gB density\n");
> }
>
> if (!(mem && calib)) {
>
Reviewed-by: Stefano Babic
Best regards,
Stefano Babic
--
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Re: [U-Boot] [PATCH 02/14] imx: ventana: config: add gzwrite support
On 13/03/2017 16:51, Tim Harvey wrote: > Signed-off-by: Tim Harvey > --- > include/configs/gw_ventana.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h > index 24e3150..31b3010 100644 > --- a/include/configs/gw_ventana.h > +++ b/include/configs/gw_ventana.h > @@ -143,6 +143,7 @@ > #define CONFIG_CMD_HDMIDETECT/* detect HDMI output device */ > #define CONFIG_CMD_GSC > #define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */ > +#define CONFIG_CMD_UNZIP /* gzwrite */ > #define CONFIG_RBTREE > > /* Ethernet support */ > Reviewed-by: Stefano Babic Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 03/14] imx: ventana: move mmc_init to common
On 13/03/2017 16:51, Tim Harvey wrote:
> Signed-off-by: Tim Harvey
> ---
> board/gateworks/gw_ventana/common.c | 35
> +
> board/gateworks/gw_ventana/gw_ventana.c | 33 ---
> 2 files changed, 35 insertions(+), 33 deletions(-)
>
> diff --git a/board/gateworks/gw_ventana/common.c
> b/board/gateworks/gw_ventana/common.c
> index 4065c56..eb14cb7 100644
> --- a/board/gateworks/gw_ventana/common.c
> +++ b/board/gateworks/gw_ventana/common.c
> @@ -6,10 +6,12 @@
> * SPDX-License-Identifier: GPL-2.0+
> */
>
> +#include
> #include
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -35,6 +37,17 @@ void setup_iomux_uart(void)
> SETUP_IOMUX_PADS(uart2_pads);
> }
>
> +/* MMC */
> +static iomux_v3_cfg_t const usdhc3_pads[] = {
> + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> +};
> +
> /* I2C1: GSC */
> static struct i2c_pads_info mx6q_i2c_pad_info0 = {
> .scl = {
> @@ -964,3 +977,25 @@ void setup_pmic(void)
> }
> }
> }
> +
> +#ifdef CONFIG_FSL_ESDHC
> +static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + /* Only one USDHC controller on Ventana */
> + SETUP_IOMUX_PADS(usdhc3_pads);
> + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> + usdhc_cfg.max_bus_width = 4;
> +
> + return fsl_esdhc_initialize(bis, &usdhc_cfg);
> +}
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + /* Card Detect */
> + gpio_request(GP_SD3_CD, "sd_cd");
> + gpio_direction_input(GP_SD3_CD);
> + return !gpio_get_value(GP_SD3_CD);
> +}
> +#endif /* CONFIG_FSL_ESDHC */
> diff --git a/board/gateworks/gw_ventana/gw_ventana.c
> b/board/gateworks/gw_ventana/gw_ventana.c
> index 5d871ce..ba648f5 100644
> --- a/board/gateworks/gw_ventana/gw_ventana.c
> +++ b/board/gateworks/gw_ventana/gw_ventana.c
> @@ -52,17 +52,6 @@ struct ventana_board_info ventana_info;
>
> static int board_type;
>
> -/* MMC */
> -static iomux_v3_cfg_t const usdhc3_pads[] = {
> - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> -};
> -
> /* ENET */
> static iomux_v3_cfg_t const enet_pads[] = {
> IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> @@ -193,28 +182,6 @@ int board_ehci_power(int port, int on)
> }
> #endif /* CONFIG_USB_EHCI_MX6 */
>
> -#ifdef CONFIG_FSL_ESDHC
> -static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
> -
> -int board_mmc_getcd(struct mmc *mmc)
> -{
> - /* Card Detect */
> - gpio_request(GP_SD3_CD, "sd_cd");
> - gpio_direction_input(GP_SD3_CD);
> - return !gpio_get_value(GP_SD3_CD);
> -}
> -
> -int board_mmc_init(bd_t *bis)
> -{
> - /* Only one USDHC controller on Ventana */
> - SETUP_IOMUX_PADS(usdhc3_pads);
> - usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> - usdhc_cfg.max_bus_width = 4;
> -
> - return fsl_esdhc_initialize(bis, &usdhc_cfg);
> -}
> -#endif /* CONFIG_FSL_ESDHC */
> -
> #ifdef CONFIG_MXC_SPI
> iomux_v3_cfg_t const ecspi1_pads[] = {
> /* SS1 */
>
Reviewed-by: Stefano Babic
Best regards,
Stefano Babic
--
=
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Re: [U-Boot] [PATCH 05/14] imx: ventana: change name of rs232_en to indicate polarity
On 13/03/2017 16:51, Tim Harvey wrote:
> Signed-off-by: Tim Harvey
> ---
> board/gateworks/gw_ventana/common.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/gateworks/gw_ventana/common.c
> b/board/gateworks/gw_ventana/common.c
> index eb14cb7..49d6e52 100644
> --- a/board/gateworks/gw_ventana/common.c
> +++ b/board/gateworks/gw_ventana/common.c
> @@ -738,7 +738,7 @@ void setup_iomux_gpio(int board, struct
> ventana_board_info *info)
>
> /* RS232_EN# */
> if (gpio_cfg[board].rs232_en) {
> - gpio_request(gpio_cfg[board].rs232_en, "rs232_en");
> + gpio_request(gpio_cfg[board].rs232_en, "rs232_en#");
> gpio_direction_output(gpio_cfg[board].rs232_en, 0);
> }
>
>
Reviewed-by: Stefano Babic
Best regards,
Stefano Babic
--
=
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [U-Boot] [PATCH 06/14] imx: ventana: fix hwconfig
On 13/03/2017 16:51, Tim Harvey wrote:
> Signed-off-by: Tim Harvey
> ---
> board/gateworks/gw_ventana/gw_ventana.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/gateworks/gw_ventana/gw_ventana.c
> b/board/gateworks/gw_ventana/gw_ventana.c
> index ba648f5..22a3c8e 100644
> --- a/board/gateworks/gw_ventana/gw_ventana.c
> +++ b/board/gateworks/gw_ventana/gw_ventana.c
> @@ -739,7 +739,7 @@ int misc_init_r(void)
>
> /* Set a non-initialized hwconfig based on board configuration */
> if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) {
> - sprintf(buf, "hwconfig=");
> + buf[0] = 0;
> if (gpio_cfg[board_type].rs232_en)
> strcat(buf, "rs232;");
> for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
>
Reviewed-by: Stefano Babic
Best regards,
Stefano Babic
--
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Re: [U-Boot] [PATCH 08/14] imx: ventana: make SD3_VSELECT board specific
On 13/03/2017 16:51, Tim Harvey wrote:
> Signed-off-by: Tim Harvey
> ---
> board/gateworks/gw_ventana/common.c | 30 +-
> board/gateworks/gw_ventana/common.h | 2 +-
> 2 files changed, 18 insertions(+), 14 deletions(-)
>
> diff --git a/board/gateworks/gw_ventana/common.c
> b/board/gateworks/gw_ventana/common.c
> index a33c112..3dc5f88 100644
> --- a/board/gateworks/gw_ventana/common.c
> +++ b/board/gateworks/gw_ventana/common.c
> @@ -143,12 +143,6 @@ void setup_ventana_i2c(void)
> * Baseboard specific GPIO
> */
>
> -/* common to add baseboards */
> -static iomux_v3_cfg_t const gw_gpio_pads[] = {
> - /* SD3_VSELECT */
> - IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
> -};
> -
> /* prototype */
> static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
> /* RS232_EN# */
> @@ -196,6 +190,8 @@ static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
> };
>
> static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
> + /* SD3_VSELECT */
> + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
> /* RS232_EN# */
> IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
> /* MSATA_EN */
> @@ -229,6 +225,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
> };
>
> static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
> + /* SD3_VSELECT */
> + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
> /* RS232_EN# */
> IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
> /* MSATA_EN */
> @@ -262,6 +260,8 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
> };
>
> static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
> + /* SD3_VSELECT */
> + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
> /* RS232_EN# */
> IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
> /* MSATA_EN */
> @@ -338,11 +338,12 @@ static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
> };
>
> static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
> + /* SD3_VSELECT */
> + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
> /* PANLEDG# */
> IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
> /* PANLEDR# */
> IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG),
> -
> /* VID_PWR */
> IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
> /* PCI_RST# */
> @@ -629,6 +630,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
> .msata_en = GP_MSATA_SEL,
> .rs232_en = GP_RS232_EN,
> .otgpwr_en = IMX_GPIO_NR(3, 22),
> + .vsel_pin = IMX_GPIO_NR(6, 14),
> },
>
> /* GW53xx */
> @@ -651,6 +653,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
> .msata_en = GP_MSATA_SEL,
> .rs232_en = GP_RS232_EN,
> .otgpwr_en = IMX_GPIO_NR(3, 22),
> + .vsel_pin = IMX_GPIO_NR(6, 14),
> },
>
> /* GW54xx */
> @@ -675,6 +678,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
> .msata_en = GP_MSATA_SEL,
> .rs232_en = GP_RS232_EN,
> .otgpwr_en = IMX_GPIO_NR(3, 22),
> + .vsel_pin = IMX_GPIO_NR(6, 14),
> },
>
> /* GW551x */
> @@ -721,6 +725,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
> .vidin_en = IMX_GPIO_NR(5, 20),
> .wdis = IMX_GPIO_NR(7, 12),
> .otgpwr_en = IMX_GPIO_NR(3, 22),
> + .vsel_pin = IMX_GPIO_NR(6, 14),
> },
> };
>
> @@ -728,9 +733,6 @@ void setup_iomux_gpio(int board, struct
> ventana_board_info *info)
> {
> int i;
>
> - /* iomux common to all Ventana boards */
> - SETUP_IOMUX_PADS(gw_gpio_pads);
> -
> if (board >= GW_UNKNOWN)
> return;
>
> @@ -827,9 +829,11 @@ void setup_iomux_gpio(int board, struct
> ventana_board_info *info)
> }
>
> /* sense vselect pin to see if we support uhs-i */
> - gpio_request(GP_SD3_VSELECT, "sd3_vselect");
> - gpio_direction_input(GP_SD3_VSELECT);
> - gpio_cfg[board].usd_vsel = !gpio_get_value(GP_SD3_VSELECT);
> + if (gpio_cfg[board].vsel_pin) {
> + gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect");
> + gpio_direction_input(gpio_cfg[board].vsel_pin);
> + gpio_cfg[board].usd_vsel =
> !gpio_get_value(gpio_cfg[board].vsel_pin);
> + }
> }
>
> /* setup GPIO pinmux and default configuration per baseboard and env */
> diff --git a/board/gateworks/gw_ventana/common.h
> b/board/gateworks/gw_ventana/common.h
> index 6939233..18909a0 100644
> --- a/board/gateworks/gw_ventana/common.h
> +++ b/board/gateworks/gw_ventana/common.h
> @@ -16,7 +16,6 @@
> #define GP_SD3_CDIMX_GPIO_NR(7, 0)
> #define GP_RS232_EN IMX_GPIO_NR(2, 11)
> #define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
> -#define GP_SD3_VSELECT IMX_GPIO_NR(6, 14)
>
> #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> @@ -79,6 +78,7 @@ struct ventana {
> int msat
Re: [U-Boot] [PATCH 07/14] imx: ventana: make OTG VBUS power enable board specific
On 13/03/2017 16:51, Tim Harvey wrote:
> Signed-off-by: Tim Harvey
> ---
> board/gateworks/gw_ventana/common.c | 16
> board/gateworks/gw_ventana/common.h | 2 +-
> board/gateworks/gw_ventana/gw_ventana.c | 8 +---
> 3 files changed, 18 insertions(+), 8 deletions(-)
>
> diff --git a/board/gateworks/gw_ventana/common.c
> b/board/gateworks/gw_ventana/common.c
> index 49d6e52..a33c112 100644
> --- a/board/gateworks/gw_ventana/common.c
> +++ b/board/gateworks/gw_ventana/common.c
> @@ -586,6 +586,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
> .rs485en = IMX_GPIO_NR(3, 24),
> .dioi2c_en = IMX_GPIO_NR(4, 5),
> .pcie_sson = IMX_GPIO_NR(1, 20),
> + .otgpwr_en = IMX_GPIO_NR(3, 22),
> },
>
> /* GW51xx */
> @@ -604,6 +605,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
> .gps_shdn = IMX_GPIO_NR(1, 2),
> .vidin_en = IMX_GPIO_NR(5, 20),
> .wdis = IMX_GPIO_NR(7, 12),
> + .otgpwr_en = IMX_GPIO_NR(3, 22),
> },
>
> /* GW52xx */
> @@ -626,6 +628,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
> .wdis = IMX_GPIO_NR(7, 12),
> .msata_en = GP_MSATA_SEL,
> .rs232_en = GP_RS232_EN,
> + .otgpwr_en = IMX_GPIO_NR(3, 22),
> },
>
> /* GW53xx */
> @@ -647,6 +650,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
> .wdis = IMX_GPIO_NR(7, 12),
> .msata_en = GP_MSATA_SEL,
> .rs232_en = GP_RS232_EN,
> + .otgpwr_en = IMX_GPIO_NR(3, 22),
> },
>
> /* GW54xx */
> @@ -670,6 +674,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
> .wdis = IMX_GPIO_NR(5, 17),
> .msata_en = GP_MSATA_SEL,
> .rs232_en = GP_RS232_EN,
> + .otgpwr_en = IMX_GPIO_NR(3, 22),
> },
>
> /* GW551x */
> @@ -715,6 +720,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
> .pcie_rst = IMX_GPIO_NR(1, 0),
> .vidin_en = IMX_GPIO_NR(5, 20),
> .wdis = IMX_GPIO_NR(7, 12),
> + .otgpwr_en = IMX_GPIO_NR(3, 22),
> },
> };
>
> @@ -725,10 +731,6 @@ void setup_iomux_gpio(int board, struct
> ventana_board_info *info)
> /* iomux common to all Ventana boards */
> SETUP_IOMUX_PADS(gw_gpio_pads);
>
> - /* OTG power off */
> - gpio_request(GP_USB_OTG_PWR, "usbotg_pwr");
> - gpio_direction_output(GP_USB_OTG_PWR, 0);
> -
> if (board >= GW_UNKNOWN)
> return;
>
> @@ -818,6 +820,12 @@ void setup_iomux_gpio(int board, struct
> ventana_board_info *info)
> gpio_direction_output(gpio_cfg[board].wdis, 1);
> }
>
> + /* OTG power off */
> + if (gpio_cfg[board].otgpwr_en) {
> + gpio_request(gpio_cfg[board].otgpwr_en, "usbotg_pwr");
> + gpio_direction_output(gpio_cfg[board].otgpwr_en, 0);
> + }
> +
> /* sense vselect pin to see if we support uhs-i */
> gpio_request(GP_SD3_VSELECT, "sd3_vselect");
> gpio_direction_input(GP_SD3_VSELECT);
> diff --git a/board/gateworks/gw_ventana/common.h
> b/board/gateworks/gw_ventana/common.h
> index 3d7aff1..6939233 100644
> --- a/board/gateworks/gw_ventana/common.h
> +++ b/board/gateworks/gw_ventana/common.h
> @@ -13,7 +13,6 @@
>
> /* GPIO's common to all baseboards */
> #define GP_PHY_RST IMX_GPIO_NR(1, 30)
> -#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
> #define GP_SD3_CDIMX_GPIO_NR(7, 0)
> #define GP_RS232_EN IMX_GPIO_NR(2, 11)
> #define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
> @@ -79,6 +78,7 @@ struct ventana {
> int wdis;
> int msata_en;
> int rs232_en;
> + int otgpwr_en;
> /* various features */
> bool usd_vsel;
> };
> diff --git a/board/gateworks/gw_ventana/gw_ventana.c
> b/board/gateworks/gw_ventana/gw_ventana.c
> index 22a3c8e..3f9d2f7 100644
> --- a/board/gateworks/gw_ventana/gw_ventana.c
> +++ b/board/gateworks/gw_ventana/gw_ventana.c
> @@ -175,9 +175,11 @@ int board_ehci_hcd_init(int port)
>
> int board_ehci_power(int port, int on)
> {
> - if (port)
> - return 0;
> - gpio_set_value(GP_USB_OTG_PWR, on);
> + /* enable OTG VBUS */
> + if (!port && board_type < GW_UNKNOWN) {
> + if (gpio_cfg[board_type].otgpwr_en)
> + gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
> + }
> return 0;
> }
> #endif /* CONFIG_USB_EHCI_MX6 */
>
Reviewed-by: Stefano Babic
Best regards,
Stefano Babic
--
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Re: [U-Boot] [PATCH 04/14] imx: ventana: use mmc_root in boot scripts
On 13/03/2017 16:51, Tim Harvey wrote:
> Signed-off-by: Tim Harvey
> ---
> include/configs/gw_ventana.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
> index 31b3010..d51bcc9 100644
> --- a/include/configs/gw_ventana.h
> +++ b/include/configs/gw_ventana.h
> @@ -296,14 +296,14 @@
> "fi\0" \
> \
> "uimage=uImage\0" \
> - "mmc_root=/dev/mmcblk0p1 rootfstype=${fs} rootwait rw\0" \
> + "mmc_root=mmcblk0p1\0" \
> "mmc_boot=" \
> "setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \
> "mmc dev ${disk} && mmc rescan && " \
> "setenv dtype mmc; run loadscript; " \
> "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
> "setenv bootargs console=${console},${baudrate} " \
> - "root=/dev/mmcblk0p1 rootfstype=${fs} " \
> + "root=/dev/${mmc_root} rootfstype=${fs} " \
> "rootwait rw ${video} ${extra}; " \
> "if run loadfdt; then " \
> "bootm ${loadaddr} - ${fdt_addr}; " \
>
Reviewed-by: Stefano Babic
Best regards,
Stefano Babic
--
=
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [U-Boot] [PATCH 11/14] imx: ventana: add GW5904 support
On 13/03/2017 16:51, Tim Harvey wrote:
> Signed-off-by: Tim Harvey
> ---
> board/gateworks/gw_ventana/common.c | 222
> ++--
> board/gateworks/gw_ventana/common.h | 2 +-
> board/gateworks/gw_ventana/eeprom.c | 9 +-
> board/gateworks/gw_ventana/gw_ventana.c | 35 -
> board/gateworks/gw_ventana/gw_ventana_spl.c | 14 ++
> board/gateworks/gw_ventana/ventana_eeprom.h | 1 +
> configs/gwventana_gw5904_defconfig | 68 +
> 7 files changed, 336 insertions(+), 15 deletions(-)
> create mode 100644 configs/gwventana_gw5904_defconfig
>
> diff --git a/board/gateworks/gw_ventana/common.c
> b/board/gateworks/gw_ventana/common.c
> index 3dc5f88..f7e93e2 100644
> --- a/board/gateworks/gw_ventana/common.c
> +++ b/board/gateworks/gw_ventana/common.c
> @@ -38,6 +38,19 @@ void setup_iomux_uart(void)
> }
>
> /* MMC */
> +static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
> + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> +};
> static iomux_v3_cfg_t const usdhc3_pads[] = {
> IOMUX_PADS(PAD_SD3_CLK__SD3_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> IOMUX_PADS(PAD_SD3_CMD__SD3_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> @@ -352,6 +365,41 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
> IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
> };
>
> +static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
> + /* USB_HUBRST# */
> + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
> + /* PANLEDG# */
> + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
> + /* PANLEDR# */
> + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
> + /* MX6_LOCLED# */
> + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
> + /* IOEXP_PWREN# */
> + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
> + /* IOEXP_IRQ# */
> + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
> + /* DIOI2C_DIS# */
> + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
> + /* UART_RS485 */
> + IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG),
> + /* UART_HALF */
> + IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG),
> + /* SKT1_WDIS# */
> + IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG),
> + /* SKT1_RST# */
> + IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG),
> + /* SKT2_WDIS# */
> + IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG),
> + /* SKT2_RST# */
> + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
> + /* M2_OFF# */
> + IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
> + /* M2_WDIS# */
> + IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
> + /* M2_RST# */
> + IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
> +};
> +
> /* Digital I/O */
> struct dio_cfg gw51xx_dio[] = {
> {
> @@ -566,6 +614,81 @@ struct dio_cfg gw553x_dio[] = {
> },
> };
>
> +struct dio_cfg gw5904_dio[] = {
> + {
> + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
> + IMX_GPIO_NR(1, 16),
> + { 0, 0 },
> + 0
> + },
> + {
> + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
> + IMX_GPIO_NR(1, 19),
> + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
> + 2
> + },
> + {
> + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
> + IMX_GPIO_NR(1, 17),
> + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
> + 3
> + },
> + {
> + {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
> + IMX_GPIO_NR(1, 20),
> + { 0, 0 },
> + 0
> + },
> + {
> + {IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) },
> + IMX_GPIO_NR(2, 0),
> + { 0, 0 },
> + 0
> + },
> + {
> + {IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) },
> + IMX_GPIO_NR(2, 1),
> + { 0, 0 },
> + 0
> + },
> + {
> + {IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) },
> + IMX_GPIO_NR(2, 2),
> + { 0, 0 },
> + 0
> + },
> + {
> + {IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) },
> +
Re: [U-Boot] [PATCH 12/14] imx: ventana: add GW560x support
On 13/03/2017 16:51, Tim Harvey wrote:
> Signed-off-by: Tim Harvey
> ---
> board/gateworks/gw_ventana/common.c | 181
>
> board/gateworks/gw_ventana/eeprom.c | 4 +
> board/gateworks/gw_ventana/gsc.c| 4 +
> board/gateworks/gw_ventana/gw_ventana.c | 4 +-
> board/gateworks/gw_ventana/ventana_eeprom.h | 1 +
> include/configs/gw_ventana.h| 1 -
> 6 files changed, 167 insertions(+), 28 deletions(-)
>
> diff --git a/board/gateworks/gw_ventana/common.c
> b/board/gateworks/gw_ventana/common.c
> index f7e93e2..69dc8fc 100644
> --- a/board/gateworks/gw_ventana/common.c
> +++ b/board/gateworks/gw_ventana/common.c
> @@ -51,6 +51,20 @@ static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
> IOMUX_PADS(PAD_SD3_CMD__SD3_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> };
> +/* 8-bit eMMC on SD2/NAND */
> +static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
> + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> +};
> +
> static iomux_v3_cfg_t const usdhc3_pads[] = {
> IOMUX_PADS(PAD_SD3_CLK__SD3_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> IOMUX_PADS(PAD_SD3_CMD__SD3_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> @@ -365,6 +379,39 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
> IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
> };
>
> +static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
> + /* RS232_EN# */
> + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
> + /* CAN_STBY */
> + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
> + /* USB_HUBRST# */
> + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
> + /* PANLEDG# */
> + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
> + /* PANLEDR# */
> + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
> + /* MX6_LOCLED# */
> + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
> + /* IOEXP_PWREN# */
> + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
> + /* IOEXP_IRQ# */
> + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
> + /* DIOI2C_DIS# */
> + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
> + /* VID_EN */
> + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
> + /* PCI_RST# */
> + IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG),
> + /* RS485_EN */
> + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
> + /* PCIESKT_WDIS# */
> + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
> + /* USBH2_PEN (OTG) */
> + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
> + /* 12V0_PWR_EN */
> + IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
> +};
> +
> static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
> /* USB_HUBRST# */
> IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
> @@ -614,6 +661,33 @@ struct dio_cfg gw553x_dio[] = {
> },
> };
>
> +struct dio_cfg gw560x_dio[] = {
> + {
> + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
> + IMX_GPIO_NR(1, 16),
> + { 0, 0 },
> + 0
> + },
> + {
> + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
> + IMX_GPIO_NR(1, 19),
> + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
> + 2
> + },
> + {
> + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
> + IMX_GPIO_NR(1, 17),
> + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
> + 3
> + },
> + {
> + {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
> + IMX_GPIO_NR(1, 20),
> + { 0, 0 },
> + 0
> + },
> +};
> +
> struct dio_cfg gw5904_dio[] = {
> {
> { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
> @@ -856,6 +930,27 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
> .mmc_cd = IMX_GPIO_NR(7, 0),
> },
>
> + /* GW560x */
> + {
> + .gpio_pads = gw560x_gpio_pads,
> + .num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
> + .dio_cfg = gw560x_dio,
> + .dio_num = ARRAY_SIZE(gw560x_dio),
> + .leds = {
> + IMX_GPIO_NR(4, 6),
> + IMX_GPIO_NR
Re: [U-Boot] [PATCH 13/14] imx: ventana: add GW5903 support
On 13/03/2017 16:51, Tim Harvey wrote:
> Signed-off-by: Tim Harvey
> ---
> board/gateworks/gw_ventana/common.c | 103
>
> board/gateworks/gw_ventana/eeprom.c | 2 +
> board/gateworks/gw_ventana/gw_ventana.c | 13
> board/gateworks/gw_ventana/gw_ventana_spl.c | 42 ++--
> board/gateworks/gw_ventana/ventana_eeprom.h | 1 +
> 5 files changed, 157 insertions(+), 4 deletions(-)
>
> diff --git a/board/gateworks/gw_ventana/common.c
> b/board/gateworks/gw_ventana/common.c
> index 69dc8fc..188f7f5 100644
> --- a/board/gateworks/gw_ventana/common.c
> +++ b/board/gateworks/gw_ventana/common.c
> @@ -51,6 +51,17 @@ static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
> IOMUX_PADS(PAD_SD3_CMD__SD3_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> };
> +/* 4-bit microSD on SD2 */
> +static iomux_v3_cfg_t const gw5904_mmc_pads[] = {
> + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + /* CD */
> + IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> +};
> /* 8-bit eMMC on SD2/NAND */
> static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
> IOMUX_PADS(PAD_SD2_CLK__SD2_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> @@ -412,6 +423,39 @@ static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
> IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
> };
>
> +static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
> + /* BKLT_12VEN */
> + IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
> + /* EMMY_PDN# */
> + IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG),
> + /* EMMY_CFG1# */
> + IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
> + /* EMMY_CFG1# */
> + IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG),
> + /* USBH1_PEN (EHCI) */
> + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
> + /* USBH2_PEN (OTG) */
> + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
> + /* USBDPC_PEN */
> + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
> + /* TOUCH_RST */
> + IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
> + /* AUDIO_RST# */
> + IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
> + /* UART1_TEN# */
> + IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG),
> + /* MX6_LOCLED# */
> + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
> + /* LVDS_BKLEN # */
> + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
> + /* RGMII_PDWN# */
> + IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG),
> + /* TOUCH_IRQ# */
> + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
> + /* TOUCH_RST# */
> + IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
> +};
> +
> static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
> /* USB_HUBRST# */
> IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
> @@ -688,6 +732,9 @@ struct dio_cfg gw560x_dio[] = {
> },
> };
>
> +struct dio_cfg gw5903_dio[] = {
> +};
> +
> struct dio_cfg gw5904_dio[] = {
> {
> { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
> @@ -951,6 +998,19 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
> .mmc_cd = IMX_GPIO_NR(7, 0),
> },
>
> + /* GW5903 */
> + {
> + .gpio_pads = gw5903_gpio_pads,
> + .num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2,
> + .dio_cfg = gw5903_dio,
> + .dio_num = ARRAY_SIZE(gw5903_dio),
> + .leds = {
> + IMX_GPIO_NR(6, 14),
> + },
> + .otgpwr_en = IMX_GPIO_NR(4, 15),
> + .mmc_cd = IMX_GPIO_NR(6, 11),
> + },
> +
> /* GW5904 */
> {
> .gpio_pads = gw5904_gpio_pads,
> @@ -1081,6 +1141,22 @@ void setup_iomux_gpio(int board, struct
> ventana_board_info *info)
> gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
> gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
> break;
> + case GW5903:
> + gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
> + gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
> + gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr");
> + gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
> + gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr");
> + gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
> + gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en");
> + gpio_direction_output(IMX_GPIO_NR(1, 25), 1);
> + gpio_request(IMX_GPI
Re: [U-Boot] [RFC PATCH] driver: pci: Fix regions for local memory
Hi York,
On 16 March 2017 at 21:29, york sun wrote:
> On 03/16/2017 08:14 PM, Simon Glass wrote:
>> Hi York,
>>
>> On 16 March 2017 at 16:47, Simon Glass wrote:
>>> On 9 February 2017 at 11:35, York Sun wrote:
When adding local memory to PCI region, gd->ram_size is correct only
if the memory is in one continuous block. In case memory is split
into several banks, each bank should be added separately.
Signed-off-by: York Sun
CC: Simon Glass
---
It was spotted when I was rewriting the code to reserve secure memory
and forgot to reduce gd->ram_size. PCIe resumes working after fixing
gd->ram_size. For my case, the memory is split into two banks. So
base + gd->ram_size is not in memory. I don't know how it worked before.
This change seems reasonable without digging into PCI code.
drivers/pci/pci-uclass.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
>>>
>>> Acked-by: Simon Glass
>>
>> Unfortunately this breaks chromebook_link (x86).
>>
>> Do you have any ideas or should I dig into it?
>>
>
> Sorry I have no idea. If you can look into it, that will be great.
The problem is that x86 sets up PCI before relocation, thus before
gd->bd is available.
I think several changes are needed:
1. Something like:
bool use_dram_banks = false;
#ifdef CONFIG_NR_DRAM_BANKS
use_dram_banks = gd->bd != NULL;
#endif
if (use_dram_banks) {
your new code
} else {
old code
}
2. DRAM banks can have a size of 0, so check for that and skip if needed.
3. Check you don't overflow the size of the pci controller regions[] array.
Sorry I didn't notice this when reviewing it. It looked fine to me!
Regards,
Simon
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[U-Boot] [PATCH] pci: Add a command to show PCI regions
Add 'pci regions' which lists the I/O and memory regions accessible from
the PCI controller.
Signed-off-by: Simon Glass
---
cmd/pci.c | 49 +++--
1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/cmd/pci.c b/cmd/pci.c
index 7993c1a099..84d663d442 100644
--- a/cmd/pci.c
+++ b/cmd/pci.c
@@ -606,6 +606,45 @@ static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong
size, ulong value,
return 0;
}
+static const struct pci_flag_info {
+ uint flag;
+ const char *name;
+} pci_flag_info[] = {
+ { PCI_REGION_IO, "io" },
+ { PCI_REGION_PREFETCH, "prefetch" },
+ { PCI_REGION_SYS_MEMORY, "sysmem" },
+ { PCI_REGION_RO, "readonly" },
+ { PCI_REGION_IO, "io" },
+};
+
+static void pci_show_regions(struct udevice *bus)
+{
+ struct pci_controller *hose = dev_get_uclass_priv(bus);
+ const struct pci_region *reg;
+ int i, j;
+
+ if (!hose) {
+ printf("Bus '%s' is not a PCI controller\n", bus->name);
+ return;
+ }
+
+ printf("# %-16s %-16s %-16s %s\n", "Bus start", "Phys start", "Size",
+ "Flags");
+ for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
+ printf("%d %#016llx %#016llx %#016llx ", i,
+ (unsigned long long)reg->bus_start,
+ (unsigned long long)reg->phys_start,
+ (unsigned long long)reg->size);
+ if (!(reg->flags & PCI_REGION_TYPE))
+ printf("mem ");
+ for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
+ if (reg->flags & pci_flag_info[j].flag)
+ printf("%s ", pci_flag_info[j].name);
+ }
+ printf("\n");
+ }
+}
+
/* PCI Configuration Space access commands
*
* Syntax:
@@ -657,10 +696,11 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
pci_init();
return 0;
#endif
+ case 'r': /* no break */
default:/* scan bus */
value = 1; /* short listing */
if (argc > 1) {
- if (argv[argc-1][0] == 'l') {
+ if (cmd != 'r' && argv[argc-1][0] == 'l') {
value = 0;
argc--;
}
@@ -673,7 +713,10 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
printf("No such bus\n");
return CMD_RET_FAILURE;
}
- pciinfo(bus, value);
+ if (cmd == 'r')
+ pci_show_regions(bus);
+ else
+ pciinfo(bus, value);
#else
pciinfo(busnum, value);
#endif
@@ -745,6 +788,8 @@ static char pci_help_text[] =
#ifdef CONFIG_DM_PCI
"pci bar b.d.f\n"
"- show BARs base and size for device b.d.f'\n"
+ "pci regions\n"
+ "- show PCI regions\n"
#endif
"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
"- display PCI configuration space (CFG)\n"
--
2.12.0.367.g23dc2f6d3c-goog
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Re: [U-Boot] [Resend] Please pull u-boot-fsl-qoriq master
On Thu, Mar 16, 2017 at 08:31:43PM +, york sun wrote: > Tom, > > The following changes since commit 8537ddd769f460d7fb7a62a3dcc9669049702e51: > >Prepare v2017.03 (2017-03-13 13:54:16 -0400) > > are available in the git repository at: > >git://git.denx.de/u-boot-fsl-qoriq.git > > for you to fetch changes up to 9b6639fa85bddd90df4c371f25a89c791a6ee6ef: > >LS1021ATWR: Modify u-boot size for sd secure boot (2017-03-14 > 08:44:03 -0700) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [GIT PULL] Xilinx changes for v2017.05
On Thu, Mar 16, 2017 at 10:24:42AM +0100, Michal Simek wrote: > Hi Tom, > > please pull these changes to your tree. > > Thanks, > Michal > > The following changes since commit 85d0bea153c76f4a3912b5683222885bfd37c769: > > Prepare v2017.03-rc2 (2017-02-13 11:47:45 -0500) > > are available in the git repository at: > > git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2017.05 > > for you to fetch changes up to 61e745d1311532a90de537cc470da12d306ee193: > > mmc: zynq: Add fdt max-frequency support (2017-02-17 10:22:47 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/2] spl: Add spl_early_init()
On Wed, Mar 15, 2017 at 08:43:28AM -0600, Simon Glass wrote:
> From: Eddie Cai
>
> At present malloc_base/_limit/_ptr are not initialised in spl_init() when
> we call spl_init() in board_init_f(). This is due to a recent change aimed
> at avoiding overwriting the malloc area set up on some boards by
> spl_relocate_stack_gd().
>
> However if CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN is not defined, we now
> skip setting up the memory area in spl_init() which is obviously wrong.
>
> To fix this, add a new function spl_early_init() which can be called in
> board_init_f().
>
> Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit)
> Signed-off-by: Eddie Cai
> Rewrote spl_{,early_}init() to avoid duplicate code:
> Rewrite/expand commit message:
> Signed-off-by: Simon Glass
Reviewed-by: Tom Rini
--
Tom
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Re: [U-Boot] [PATCH v2 00/20] Add Intel Arria 10 SoC support
Hi Marek On Fri, Mar 17, 2017 at 5:56 AM, Marek Vasut wrote: > On 03/09/2017 01:26 AM, Ley Foon Tan wrote: >> This is the 2nd version of patchset to adds support for Intel Arria 10 SoC. >> This version mainly resolved comments from Marek in [v1]. >> >> This is initial patchset enables the basic support for Arria 10 and other >> features will come after this. >> >> This series is working on top of “arm: socfpga: Move to using distro boot” >> series [1] from Dalon Westergreen. >> >> [1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg239560.html > > I have to wonder, will the A10 SoCDK be usable with mainline U-Boot with > just this patchset or is something else missing, like ie. the > DDR driver ? We want to get the basic upstream first and then will submit the patchset for DDR and other components after this. Regards Ley Foon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] kirkwood: remove get_random_hex() and MD5 dependency
On 15.03.2017 02:19, Andre Przywara wrote:
Commit 19a5944fcd62 ("mvgbe: remove setting of ethaddr within the
driver") removed the usage of get_random_hex() from the mvgbe driver
about six years ago. However the prototype of that function survived
till today in some kirkwood header file.
Remove that prototype and the CONFIG_MD5 dependency triggered by that.
Signed-off-by: Andre Przywara
---
arch/arm/mach-kirkwood/include/mach/config.h | 1 -
arch/arm/mach-kirkwood/include/mach/cpu.h| 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h
b/arch/arm/mach-kirkwood/include/mach/config.h
index 446457f..b786df0 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -24,7 +24,6 @@
#endif /* CONFIG_KW88F6281 */
#include
-#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h
b/arch/arm/mach-kirkwood/include/mach/cpu.h
index 926d347..ab704d9 100644
--- a/arch/arm/mach-kirkwood/include/mach/cpu.h
+++ b/arch/arm/mach-kirkwood/include/mach/cpu.h
@@ -139,7 +139,6 @@ struct kwgpio_registers {
/*
* functions
*/
-unsigned char get_random_hex(void);
unsigned int mvebu_sdram_bar(enum memory_bank bank);
unsigned int mvebu_sdram_bs(enum memory_bank bank);
void mvebu_sdram_size_adjust(enum memory_bank bank);
Reviewed-by: Stefan Roese
Thanks,
Stefan
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Re: [U-Boot] [PATCH 10/14] drivers: net: add MV88E6xx to Kconfig
On Fri, Mar 17, 2017 at 3:59 AM, Stefano Babic wrote: > On 13/03/2017 16:51, Tim Harvey wrote: >> Signed-off-by: Tim Harvey >> --- >> drivers/net/Kconfig | 18 ++ >> 1 file changed, 18 insertions(+) >> >> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig >> index 078d5a8..a24bb06 100644 >> --- a/drivers/net/Kconfig >> +++ b/drivers/net/Kconfig >> @@ -141,6 +141,24 @@ config MACB >> GEM (Gigabit Ethernet MAC) found in some ARM SoC devices. >> Say Y to include support for the MACB/GEM chip. >> >> +config MV88E61XX_SWITCH >> + bool "Marvell MV88E61xx Gigabit switch support" >> + help >> + This driver supports the mv88e6176 and similar switches. >> + >> +if MV88E61XX_SWITCH >> + >> +config MV88E61XX_CPU_PORT >> + int "CPU Port" >> + >> +config MV88E61XX_PHY_PORTS >> + hex "Bitmask of PHY Ports" >> + >> +config MV88E61XX_FIXED_PORTS >> + hex "Bitmask of PHYless serdes Ports" >> + >> +endif # MV88E61XX_SWITCH >> + >> config PCH_GBE >> bool "Intel Platform Controller Hub EG20T GMAC driver" >> depends on DM_ETH && DM_PCI >> > > > I do not understand this patch: the switch is already added into > drivers/net/phy/Kconfig, where it should be, and it should not be in > drivers/net/Kconfig where you want to put it. So I am expecting you add > if MV88E61XX_SWITCH into drivers/net/phy/Kconfig and not here. > > Added Joe as network maintainer. > Stefano, Your right - I must have typo'd my grep when I was looking for it in Kconfig. drop this patch please, and I will submit a v2 of 'imx: ventana: add GW5904 support' that adds the switch properly. Let me know if you would rather I resubmit the series. Thanks, Tim ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 10/14] drivers: net: add MV88E6xx to Kconfig
On 17/03/2017 14:13, Tim Harvey wrote: > On Fri, Mar 17, 2017 at 3:59 AM, Stefano Babic wrote: >> On 13/03/2017 16:51, Tim Harvey wrote: >>> Signed-off-by: Tim Harvey >>> --- >>> drivers/net/Kconfig | 18 ++ >>> 1 file changed, 18 insertions(+) >>> >>> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig >>> index 078d5a8..a24bb06 100644 >>> --- a/drivers/net/Kconfig >>> +++ b/drivers/net/Kconfig >>> @@ -141,6 +141,24 @@ config MACB >>> GEM (Gigabit Ethernet MAC) found in some ARM SoC devices. >>> Say Y to include support for the MACB/GEM chip. >>> >>> +config MV88E61XX_SWITCH >>> + bool "Marvell MV88E61xx Gigabit switch support" >>> + help >>> + This driver supports the mv88e6176 and similar switches. >>> + >>> +if MV88E61XX_SWITCH >>> + >>> +config MV88E61XX_CPU_PORT >>> + int "CPU Port" >>> + >>> +config MV88E61XX_PHY_PORTS >>> + hex "Bitmask of PHY Ports" >>> + >>> +config MV88E61XX_FIXED_PORTS >>> + hex "Bitmask of PHYless serdes Ports" >>> + >>> +endif # MV88E61XX_SWITCH >>> + >>> config PCH_GBE >>> bool "Intel Platform Controller Hub EG20T GMAC driver" >>> depends on DM_ETH && DM_PCI >>> >> >> >> I do not understand this patch: the switch is already added into >> drivers/net/phy/Kconfig, where it should be, and it should not be in >> drivers/net/Kconfig where you want to put it. So I am expecting you add >> if MV88E61XX_SWITCH into drivers/net/phy/Kconfig and not here. >> >> Added Joe as network maintainer. >> > > Stefano, > > Your right - I must have typo'd my grep when I was looking for it in Kconfig. > > drop this patch please, and I will submit a v2 of 'imx: ventana: add > GW5904 support' that adds the switch properly. Let me know if you > would rather I resubmit the series. You can submit just the V2. Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [u-boot PATCH v4 00/10] am57xx-idk LCD and am571x-idk 6 port ethernet pinmux
On Mon, Mar 13, 2017 at 03:04:23PM +0200, Roger Quadros wrote: > Hi, > > This series contains > > - Support am571x-idk LCD vs 6 port ethernet pinmux configuration. > - AM57xx-idk LCD detection support. > - K2G: pick up PRUSS ethernet MAC addresses from board EEPROM. > > Build tests: > https://travis-ci.org/rogerq/u-boot/builds/210547470 Woo, thanks for pushing this through travis-ci! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] ARM: ti: Update layout for MMC and eMMC (env and dfu)
On Thu, Mar 16, 2017 at 02:30:10PM +0100, Jean-Jacques Hiblot wrote: > The problems with the current DFU layout are: > MMC: The space allocated for u-boot is too small for the latest u-boot > (>750KB). We need to increase it. eMMC uses a much bigger area (2MB). > eMMC: region "u-boot.img.raw" overlaps the environment area and the region > "spl-os-image.raw". > both: region "spl-os-image.raw" is quite small and can't handle android > kernels > > Fixing this requires growing some regions and moving others. > Care has been taken to leave some room for further growth of > "spl-os-args.raw". > Also the "env" now appears in the dfu so that it's apparent that the > region is not free space that can be used to grow "u-boot.img.raw". > The total space allocated for those raw binaries is 16MB, of which 13+MB > are reserved for the kernel image. [snip] > - "MLO.raw raw 0x100 0x100;" \ > - "u-boot.img.raw raw 0x300 0x400;" \ > - "spl-os-args.raw raw 0x80 0x80;" \ > - "spl-os-image.raw raw 0x900 0x2000;" \ > + "MLO.raw raw 0x100 0x200;" \ > + "u-boot.img.raw raw 0x300 0x1000;" \ > + "u-env.raw raw 0x1300 0x200;" \ > + "spl-os-args.raw raw 0x1500 0x200;" \ > + "spl-os-image.raw raw 0x1700 0x6900;" \ I'm not sure about changing the MLO raw size. The first TRM I checked (am335x) does say that you can exceed 128KiB with the drawback being that redundancy into the following location is lost. But we need to take care in that we still have SRAM size constraints to deal with. I think we should leave MLO.raw alone for now. Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [u-boot PATCH v4 03/10] ti_armv7_keystone2: Define scratch space in SRAM
On Mon, Mar 13, 2017 at 03:04:26PM +0200, Roger Quadros wrote: > From: Franklin S Cooper Jr > > Scratch space can be used for features such as board detection. Define > an area within SRAM that can be used for this purpose. > > [rog...@ti.com] Rename EEPROM macro > > Signed-off-by: Franklin S Cooper Jr > Signed-off-by: Roger Quadros > --- > include/configs/ti_armv7_keystone2.h | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/include/configs/ti_armv7_keystone2.h > b/include/configs/ti_armv7_keystone2.h > index 5d4ef58..f76e0a5 100644 > --- a/include/configs/ti_armv7_keystone2.h > +++ b/include/configs/ti_armv7_keystone2.h > @@ -55,6 +55,13 @@ > #define CONFIG_SPL_SPI_LOAD > #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO > > +/* SRAM scratch space entries */ > +#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8 > + > +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR) > +#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + > 0x200) > +#define KEYSTONE_SRAM_SCRATCH_SPACE_END > (TI_SRAM_SCRATCH_BOARD_EEPROM_END) > + > /* UART Configuration */ > #define CONFIG_SYS_NS16550_MEM32 > #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) I think I said this in Franklin's posting of this patch as well, we need to move this to some header elsewhere rather than include/configs/, Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] Kconfig: Don't use RSA_FREESCALE_EXP on IMX
On Thu, Mar 16, 2017 at 04:17:06PM -0500, George McCollister wrote: > The CAAM in IMX parts doesn't support public key hardware acceleration > (PKHA), so don't use RSA_FREESCALE_EXP. If you try to use it on IMX > (assuming you have the clocks enabled first) you will get back an > "Invalid KEY Command" error since PKHA isn't a valid key destination for > these parts. > > Signed-off-by: George McCollister Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: am43xx: fix SOC revision print outs
On Thu, Mar 16, 2017 at 09:48:54AM +0200, Tero Kristo wrote: > Currently, AM43xx just re-uses the version strings from AM33xx which is > wrong; the actual values for AM43xx are different. Fix this by adding > a separate version string array for AM43xx and use this instead. > > Signed-off-by: Tero Kristo > Reported-by: Sekhar Nori Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [u-boot PATCH v4 10/10] net: don't override ethernet address environment
On Mon, Mar 13, 2017 at 03:04:33PM +0200, Roger Quadros wrote: > If the ethernet address environment is set with a valid > ethernet address prevent overriding it as it is most likely > set by the user and he/she doesn't want board code to > automatically override it whatsoever. > > Signed-off-by: Roger Quadros Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 29/31] ARM: dts: k2g: Add DT support for K2G Industrial Communication Engine evm
On Thu, Mar 16, 2017 at 04:56:44PM -0500, Franklin S Cooper Jr wrote: > > > On 03/09/2017 07:09 AM, Tom Rini wrote: > > On Thu, Mar 02, 2017 at 01:04:33PM -0600, Franklin S Cooper Jr wrote: > > > >> Add basic DT support for K2G ICE evm. Only minimal peripherals are > >> supported to allow console output and MMC boot. > >> > >> Signed-off-by: Franklin S Cooper Jr > >> --- > >> arch/arm/dts/Makefile | 3 ++- > >> arch/arm/dts/keystone-k2g-ice.dts | 25 + > > > > Has this been pushed up to Linux yet? Thanks! > > Not yet. OK. The point for here (and patch 28) is that I'd like to see the DTS queued up in the appropriate tree for the kernel before we pull it in here (or at least the maintainer saying they'll pull it when gathering stuff next) so that we don't have them getting out of sync. Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 11/14] imx: ventana: add GW5904 support
Signed-off-by: Tim Harvey
---
v2:
- remove unnecessary error print on registering esdhc
- register mmc_cd gpio once
- move PHYLIB to defconfigs
Signed-off-by: Tim Harvey
---
board/gateworks/gw_ventana/common.c | 224 ++--
board/gateworks/gw_ventana/common.h | 2 +-
board/gateworks/gw_ventana/eeprom.c | 9 +-
board/gateworks/gw_ventana/gw_ventana.c | 35 -
board/gateworks/gw_ventana/gw_ventana_spl.c | 14 ++
board/gateworks/gw_ventana/ventana_eeprom.h | 1 +
configs/gwventana_emmc_defconfig| 1 +
configs/gwventana_gw5904_defconfig | 68 +
configs/gwventana_nand_defconfig| 1 +
include/configs/gw_ventana.h| 1 -
10 files changed, 340 insertions(+), 16 deletions(-)
create mode 100644 configs/gwventana_gw5904_defconfig
diff --git a/board/gateworks/gw_ventana/common.c
b/board/gateworks/gw_ventana/common.c
index 3dc5f88..d609894 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -38,6 +38,19 @@ void setup_iomux_uart(void)
}
/* MMC */
+static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -352,6 +365,41 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
+static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
+ /* USB_HUBRST# */
+ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+ /* PANLEDG# */
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+ /* PANLEDR# */
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+ /* MX6_LOCLED# */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+ /* IOEXP_PWREN# */
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+ /* IOEXP_IRQ# */
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+ /* DIOI2C_DIS# */
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+ /* UART_RS485 */
+ IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG),
+ /* UART_HALF */
+ IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG),
+ /* SKT1_WDIS# */
+ IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG),
+ /* SKT1_RST# */
+ IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG),
+ /* SKT2_WDIS# */
+ IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG),
+ /* SKT2_RST# */
+ IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+ /* M2_OFF# */
+ IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
+ /* M2_WDIS# */
+ IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
+ /* M2_RST# */
+ IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
+};
+
/* Digital I/O */
struct dio_cfg gw51xx_dio[] = {
{
@@ -566,6 +614,81 @@ struct dio_cfg gw553x_dio[] = {
},
};
+struct dio_cfg gw5904_dio[] = {
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+ IMX_GPIO_NR(1, 20),
+ { 0, 0 },
+ 0
+ },
+ {
+ {IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) },
+ IMX_GPIO_NR(2, 0),
+ { 0, 0 },
+ 0
+ },
+ {
+ {IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) },
+ IMX_GPIO_NR(2, 1),
+ { 0, 0 },
+ 0
+ },
+ {
+ {IOMUX_PADS(PAD_NAN
[U-Boot] [PATCH v2 12/14] imx: ventana: add GW560x support
Signed-off-by: Tim Harvey
---
v2:
- remove unnecessary error print on registering esdhc
Signed-off-by: Tim Harvey
---
board/gateworks/gw_ventana/common.c | 177
board/gateworks/gw_ventana/eeprom.c | 4 +
board/gateworks/gw_ventana/gsc.c| 4 +
board/gateworks/gw_ventana/gw_ventana.c | 4 +-
board/gateworks/gw_ventana/ventana_eeprom.h | 1 +
include/configs/gw_ventana.h| 1 -
6 files changed, 163 insertions(+), 28 deletions(-)
diff --git a/board/gateworks/gw_ventana/common.c
b/board/gateworks/gw_ventana/common.c
index d609894..017494f 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -51,6 +51,20 @@ static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
+/* 8-bit eMMC on SD2/NAND */
+static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -365,6 +379,39 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
+static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
+ /* RS232_EN# */
+ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+ /* CAN_STBY */
+ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+ /* USB_HUBRST# */
+ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+ /* PANLEDG# */
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+ /* PANLEDR# */
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+ /* MX6_LOCLED# */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+ /* IOEXP_PWREN# */
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+ /* IOEXP_IRQ# */
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+ /* DIOI2C_DIS# */
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+ /* VID_EN */
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+ /* PCI_RST# */
+ IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG),
+ /* RS485_EN */
+ IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+ /* USBH2_PEN (OTG) */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+ /* 12V0_PWR_EN */
+ IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
+};
+
static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
/* USB_HUBRST# */
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
@@ -614,6 +661,33 @@ struct dio_cfg gw553x_dio[] = {
},
};
+struct dio_cfg gw560x_dio[] = {
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+ IMX_GPIO_NR(1, 20),
+ { 0, 0 },
+ 0
+ },
+};
+
struct dio_cfg gw5904_dio[] = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
@@ -856,6 +930,27 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.mmc_cd = IMX_GPIO_NR(7, 0),
},
+ /* GW560x */
+ {
+ .gpio_pads = gw560x_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
+ .dio_cfg = gw560x_dio,
+ .dio_num = ARRAY_SIZE(gw560x_dio),
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 7),
+
[U-Boot] [PATCH v2 13/14] imx: ventana: add GW5903 support
Signed-off-by: Tim Harvey
---
v2:
- remove unecessary/inconsistent print on error registering esdhc
Signed-off-by: Tim Harvey
---
board/gateworks/gw_ventana/common.c | 99 +
board/gateworks/gw_ventana/eeprom.c | 2 +
board/gateworks/gw_ventana/gw_ventana.c | 13
board/gateworks/gw_ventana/gw_ventana_spl.c | 42 ++--
board/gateworks/gw_ventana/ventana_eeprom.h | 1 +
5 files changed, 153 insertions(+), 4 deletions(-)
diff --git a/board/gateworks/gw_ventana/common.c
b/board/gateworks/gw_ventana/common.c
index 017494f..ec04060 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -51,6 +51,17 @@ static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
+/* 4-bit microSD on SD2 */
+static iomux_v3_cfg_t const gw5904_mmc_pads[] = {
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ /* CD */
+ IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
/* 8-bit eMMC on SD2/NAND */
static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -412,6 +423,39 @@ static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
};
+static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
+ /* BKLT_12VEN */
+ IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
+ /* EMMY_PDN# */
+ IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG),
+ /* EMMY_CFG1# */
+ IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
+ /* EMMY_CFG1# */
+ IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG),
+ /* USBH1_PEN (EHCI) */
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+ /* USBH2_PEN (OTG) */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+ /* USBDPC_PEN */
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+ /* TOUCH_RST */
+ IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
+ /* AUDIO_RST# */
+ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
+ /* UART1_TEN# */
+ IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG),
+ /* MX6_LOCLED# */
+ IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
+ /* LVDS_BKLEN # */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+ /* RGMII_PDWN# */
+ IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG),
+ /* TOUCH_IRQ# */
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+ /* TOUCH_RST# */
+ IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
+};
+
static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
/* USB_HUBRST# */
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
@@ -688,6 +732,9 @@ struct dio_cfg gw560x_dio[] = {
},
};
+struct dio_cfg gw5903_dio[] = {
+};
+
struct dio_cfg gw5904_dio[] = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
@@ -951,6 +998,19 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.mmc_cd = IMX_GPIO_NR(7, 0),
},
+ /* GW5903 */
+ {
+ .gpio_pads = gw5903_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2,
+ .dio_cfg = gw5903_dio,
+ .dio_num = ARRAY_SIZE(gw5903_dio),
+ .leds = {
+ IMX_GPIO_NR(6, 14),
+ },
+ .otgpwr_en = IMX_GPIO_NR(4, 15),
+ .mmc_cd = IMX_GPIO_NR(6, 11),
+ },
+
/* GW5904 */
{
.gpio_pads = gw5904_gpio_pads,
@@ -1087,6 +1147,22 @@ void setup_iomux_gpio(int board, struct
ventana_board_info *info)
gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
break;
+ case GW5903:
+ gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
+ gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
+ gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr");
+ gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
+ gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr");
+ gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
+ gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en");
+ gpio_direction_output(IMX_GPIO_NR(1, 25), 1);
+ gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#
Re: [U-Boot] building cross_tools, _POSIX_C_SOURCE and _XOPEN_SOURCE are redefined
On Wed, Mar 15, 2017 at 04:02:20AM -0400, Robert P. J. Day wrote: > > to build cross_tools, i ran: > > $ make sandbox_defconfig > $ make cross_tools > > and while it appeared to work, i got: > > ... snip ... > > LDFLAGS="" python ./lib/libfdt/setup.py \ > "-Wall -Wstrict-prototypes -O2 -fomit-frame-pointer > -DCONFIG_FIT_SIGNATURE -include ./include/libfdt_env.h -idirafterinclude > -idirafter./arch/sandbox/include -I./lib/libfdt -I./tools -DUSE_HOSTCC > -D__KERNEL_STRICT_NAMES -D_GNU_SOURCE " lib/libfdt/fdt.c lib/libfdt/fdt_ro.c > lib/libfdt/fdt_rw.c lib/libfdt/fdt_strerror.c lib/libfdt/fdt_wip.c > lib/libfdt/fdt_region.c lib/libfdt/fdt_sw.c tools/libfdt_wrap.c > In file included from /usr/include/python2.7/pyconfig.h:6:0, > from /usr/include/python2.7/Python.h:8, > from tools/libfdt_wrap.c:143: > /usr/include/python2.7/pyconfig-64.h:1203:0: warning: "_POSIX_C_SOURCE" > redefined > #define _POSIX_C_SOURCE 200112L > ^ > In file included from /usr/include/stdint.h:25:0, > from > /usr/lib/gcc/x86_64-redhat-linux/5.3.1/include/stdint.h:9, > from ././include/compiler.h:19, > from ././include/libfdt_env.h:12, > from :0: > /usr/include/features.h:225:0: note: this is the location of the previous > definition > # define _POSIX_C_SOURCE 200809L > ^ > In file included from /usr/include/python2.7/pyconfig.h:6:0, > from /usr/include/python2.7/Python.h:8, > from tools/libfdt_wrap.c:143: > /usr/include/python2.7/pyconfig-64.h:1225:0: warning: "_XOPEN_SOURCE" > redefined > #define _XOPEN_SOURCE 600 > ^ > In file included from /usr/include/stdint.h:25:0, > from > /usr/lib/gcc/x86_64-redhat-linux/5.3.1/include/stdint.h:9, > from ././include/compiler.h:19, > from ././include/libfdt_env.h:12, > from :0: > /usr/include/features.h:166:0: note: this is the location of the previous > definition > # define _XOPEN_SOURCE 700 > ^ > > > not sure if that concerns anyone enough to want to tweak it. This is the second report I've gotten about this. But, we don't set any of those things directly. It's something related to the python install you have. Can you please dig a bit more? Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 10/14] drivers: net: phy: add MV88E6xx options to Kconfig
Signed-off-by: Tim Harvey --- v2: moved options to drivers/net/phy where MV88E6xx config already lived Signed-off-by: Tim Harvey --- drivers/net/phy/Kconfig | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 1d514e9..6ee8bc3 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -15,6 +15,19 @@ if PHYLIB config MV88E61XX_SWITCH bool "Marvel MV88E61xx Ethernet switch PHY support." +if MV88E61XX_SWITCH + +config MV88E61XX_CPU_PORT + int "CPU Port" + +config MV88E61XX_PHY_PORTS + hex "Bitmask of PHY Ports" + +config MV88E61XX_FIXED_PORTS + hex "Bitmask of PHYless serdes Ports" + +endif # MV88E61XX_SWITCH + config PHYLIB_10G bool "Generic 10G PHY support" -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] .gitignore: Ignore the generated top-level "sandbox/" directory
On Sun, Mar 12, 2017 at 12:36:38PM -0400, Robert P. J. Day wrote: > > Signed-off-by: Robert P. J. Day > > --- > > am i safe in assuming that the top-level sandbox/ directory only > ever exists as the result of a build? > > diff --git a/.gitignore b/.gitignore > index 7fac5b3..32a8d5b 100644 > --- a/.gitignore > +++ b/.gitignore > @@ -48,6 +48,7 @@ > /LOG > /spl/ > /tpl/ > +/sandbox/ > /defconfig What are you doing to make it exist? -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] driver: pci: Fix regions for local memory
On 03/17/2017 04:43 AM, Simon Glass wrote:
> Hi York,
>
> On 16 March 2017 at 21:29, york sun wrote:
>> On 03/16/2017 08:14 PM, Simon Glass wrote:
>>> Hi York,
>>>
>>> On 16 March 2017 at 16:47, Simon Glass wrote:
On 9 February 2017 at 11:35, York Sun wrote:
> When adding local memory to PCI region, gd->ram_size is correct only
> if the memory is in one continuous block. In case memory is split
> into several banks, each bank should be added separately.
>
> Signed-off-by: York Sun
> CC: Simon Glass
> ---
> It was spotted when I was rewriting the code to reserve secure memory
> and forgot to reduce gd->ram_size. PCIe resumes working after fixing
> gd->ram_size. For my case, the memory is split into two banks. So
> base + gd->ram_size is not in memory. I don't know how it worked before.
> This change seems reasonable without digging into PCI code.
>
> drivers/pci/pci-uclass.c | 18 +-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
Acked-by: Simon Glass
>>>
>>> Unfortunately this breaks chromebook_link (x86).
>>>
>>> Do you have any ideas or should I dig into it?
>>>
>>
>> Sorry I have no idea. If you can look into it, that will be great.
>
> The problem is that x86 sets up PCI before relocation, thus before
> gd->bd is available.
That explains it.
>
> I think several changes are needed:
>
> 1. Something like:
>
> bool use_dram_banks = false;
>
> #ifdef CONFIG_NR_DRAM_BANKS
> use_dram_banks = gd->bd != NULL;
> #endif
> if (use_dram_banks) {
>your new code
> } else {
>old code
> }
>
> 2. DRAM banks can have a size of 0, so check for that and skip if needed.
>
> 3. Check you don't overflow the size of the pci controller regions[] array.
>
> Sorry I didn't notice this when reviewing it. It looked fine to me!
>
Thanks for the explanation.
York
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Re: [U-Boot] [PATCH v5 1/1] usb: gadget: avoid variable name clipping in cb_getvar
On 03/17/2017 10:57 AM, Nicolas le bayon wrote:
> From: Nicolas Le Bayon
>
> Instead of using a fixed-size array to store variable name, preferring a
> dynamic allocation treats correctly all variable name lengths.
> Variable names are growing through releases and features. By this way, name
> clipping is prevented.
>
> Signed-off-by: Nicolas Le Bayon
FYI, you should keep changelog on patchsets > V1 .
Reviewed-by: Marek Vasut
You still need Ack from Lukasz ...
> ---
> drivers/usb/gadget/f_fastboot.c | 12 ++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_
> fastboot.c
> index 2160b1c..7cd6d24 100644
> --- a/drivers/usb/gadget/f_fastboot.c
> +++ b/drivers/usb/gadget/f_fastboot.c
> @@ -432,9 +432,15 @@ static void cb_getvar(struct usb_ep *ep, struct
> usb_request *req)
> else
> strcpy(response, "FAILValue not set");
> } else {
> - char envstr[32];
> + char *envstr;
>
> - snprintf(envstr, sizeof(envstr) - 1, "fastboot.%s", cmd);
> + envstr = malloc(strlen("fastboot.") + strlen(cmd) + 1);
> + if (!envstr) {
> + fastboot_tx_write_str("FAILmalloc error");
> + return;
> + }
> +
> + sprintf(envstr, "fastboot.%s", cmd);
> s = getenv(envstr);
> if (s) {
> strncat(response, s, chars_left);
> @@ -442,6 +448,8 @@ static void cb_getvar(struct usb_ep *ep, struct
> usb_request *req)
> printf("WARNING: unknown variable: %s\n", cmd);
> strcpy(response, "FAILVariable not implemented");
> }
> +
> + free(envstr);
> }
> fastboot_tx_write_str(response);
> }
> --
> 1.9.1
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2 00/20] Add Intel Arria 10 SoC support
On 03/17/2017 01:25 PM, Ley Foon Tan wrote: > Hi Marek Hi! > On Fri, Mar 17, 2017 at 5:56 AM, Marek Vasut wrote: >> On 03/09/2017 01:26 AM, Ley Foon Tan wrote: >>> This is the 2nd version of patchset to adds support for Intel Arria 10 SoC. >>> This version mainly resolved comments from Marek in [v1]. >>> >>> This is initial patchset enables the basic support for Arria 10 and other >>> features will come after this. >>> >>> This series is working on top of “arm: socfpga: Move to using distro boot” >>> series [1] from Dalon Westergreen. >>> >>> [1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg239560.html >> >> I have to wonder, will the A10 SoCDK be usable with mainline U-Boot with >> just this patchset or is something else missing, like ie. the >> DDR driver ? > > We want to get the basic upstream first and then will submit the > patchset for DDR and other components after this. Do you have the full patchset, which can be used to boot Arria10 SoCDK, available somewhere ? I would like to know how the pieces fit together. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: socfpga: Update README with BSP/header generation instructions
On 03/10/2017 09:03 PM, Steve Arnold wrote:
> From: Steve Arnold
Hi!
lots of nitpicks below, but it really is starting to get into a good
shape, thanks for the work and sorry for my delayed reply.
> This patch adds back the steps to manually (re)build a Quartus FPGA
^
'- back? It's not like we ever had those in ...
> project, generate the required BSP glue, and update u-boot headers
> for mainline SPL support (updated from an earlier patch submitted
> by Stefan Roese). Requires Quartus toolchain and current U-Boot.
Which was based on earlier docs by me, but do we really need that info
in commit message ?
> Signed-off-by: Steve Arnold
> Cc: Dinh Nguyen
> Cc: Stefan Roese
> Cc: Marek Vasut
> ---
> doc/README.socfpga | 141
> +++--
> 1 file changed, 136 insertions(+), 5 deletions(-)
>
> diff --git a/doc/README.socfpga b/doc/README.socfpga
> index cb805cfd3a..4783fdc52f 100644
> --- a/doc/README.socfpga
> +++ b/doc/README.socfpga
> @@ -1,18 +1,149 @@
> -
> -
> +
> SOCFPGA Documentation for U-Boot and SPL
> -
> +
>
> This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
> based SOCFPGA. To know more about the hardware itself, please refer to
> www.altera.com.
>
>
> -
> socfpga_dw_mmc
> -
> +--
> +
> Here are macro and detailed configuration required to enable DesignWare SDMMC
> controller support within SOCFPGA
>
> #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
> -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
> +
> +---
> +Generating the header files for SPL intergration as a replacement for the
> Preloader
> +---
"integration" (type) , but you can reword it in much shorter way
Generating the handoff header files for U-Boot SPL
> +This text has been updated based on testing with Quartus Lite 16.1 and a
> rebuilt
This text is assuming quartus 16.1 , but newer versions will probably
work just fine too.
> +DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB).
> The
> +FB project can now be built manually (as below) or with the project Makefile.
You should make it clear that the user should use his own quartus
project for his own board here.
> +Note: it *should* work from Quartus 14.0.200 onwards.
> +
> +Rebuilding your Quartus project
> +---
> +
> +Using the cli
command line instead of cli please
> +~
> +
> +First run the embedded command shell, using your path to the Quartus install:
> +
> + $ ${HOME}/intelFPGA/16.1/embedded/embedded_command_shell.sh
Replace ${HOME} with /path/to/ , since the tools are usually not
installed in ~
> +Then (if necessary) update the IP cores in the project, generate HDL code,
> and
> +build the project:
> +
> + $ cd path/to/project/dir
> + $ qsys-generate soc_system.qsys --upgrade-ip-cores
> + $ qsys-generate soc_system.qsys --synthesis=[VERILOG|VHDL]
> + $ quartus_map
> + $ quartus_fit
> + $ quartus_asm
You can replace the last three with
$ quartus_sh --flow compile
> +Convert the .sof file to a firmware blob:
> +
> + $ quartus_cpf -c .sof soc_system.rbf
Convert the .sof file (SRAM object file) to .rbf file (Raw bit file):
> +Now you can skip the GUI section.
OK
> +Using the Qsys GUI
> +~~
> +
> + 1) Navigate to your project directory
> + 2) Run Quartus II
> + 3) Open Project (Ctrl+J), select .qpf
> + 4) Run QSys [Tools->QSys]
> +4.1) In the Open dialog, select 'mcv_hps.qsys'
probably not mcv_hps.qsys , right ?
> +4.2) In the Open System dialog, wait until completion and press 'Close'
> +4.3) In the Qsys window, click on 'Generate HDL...' in bottom right
> corner
> + 4.3.1) In the 'Generation' window, click 'Generate'
> + 4.3.2) In the 'Generate' dialog, wait until completion and click
> 'Close'
> +4.4) In the QSys window, click 'Finish'
> + 4.4.1) In the 'Quartus II' pop up window, click 'OK'
> + 5) Back in Quartus II main window, do the following
> +5.1) Use Processing -> Start -> Start Analysis & Synthesis (Ctrl+K)
> +5.2) Use Processing -> Start Compilation (Ctrl+L)
> +... this may take some time, have patience ...
> +
> + 6) Launch a separate terminal window
Here you're entering the embedded command shell again, see the command
line section above , we should make sure this bit of documentation is
not duplicated.
> +6.1) Change directory to 'software/spl_bsp'
> +6.2) Export path to embedded command shell and friends
> + $
[U-Boot] [PATCHv2] da850: Add instructions to copy AIS image to NAND
Add instructions to write an AIS image to NAND by using the u-boot nand tools. Signed-off-by: Axel Haslam --- Changes in V2: - add erase command before write - Add write info when MTD partitions are defined board/davinci/da8xxevm/README.da850 | 41 + 1 file changed, 41 insertions(+) diff --git a/board/davinci/da8xxevm/README.da850 b/board/davinci/da8xxevm/README.da850 index 29cb4ec..519267e 100644 --- a/board/davinci/da8xxevm/README.da850 +++ b/board/davinci/da8xxevm/README.da850 @@ -47,6 +47,47 @@ U-Boot > sf erase 0 +32 U-Boot > tftp u-boot.ais U-Boot > sf write c070 0 $filesize +Flashing the images to NAND +=== +The AIS image can be written to NAND using the u-boot "nand" commands. + +Example: + +OMAPL138_LCDK requires the AIS image to be written to the second block of +the NAND flash. + +From the "nand info" command we see that the second block would start at +offset 0x2: + + U-Boot > nand info + sector size 128 KiB (0x2) + Page size 2048 b + +From the tftp command we see that we need to copy 0x74908 bytes from +memory address 0xc070 (0x75000 if we align a page of 2048): + + U-Boot > tftp u-boot.ais + Load address: 0xc070 + Bytes transferred = 477448 (74908 hex) + +The commands to write the image from memory to NAND would be: + + U-Boot > nand erase 0x2 0x75000 + U-Boot > nand write 0xc070 0x2 0x75000 + +Alternatively, MTD partitions may be defined. Using "mtdparts" to +conveniently have a bootloader partition starting at the second block +(offset 0x2): + + setenv mtdids nand0=davinci_nand.0 + setenv mtdparts mtdparts=davinci_nand.0:128k(bootenv),2m(bootloader) + +In this case the commands would be simplified to: + + U-Boot > tftp u-boot.ais + U-Boot > nand erase.part bootloader + U-Boot > nand write 0xc070 bootloader + Flashing the images to MMC == If the boot pins are set to boot from mmc, the RBL will try to load the -- 2.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3] NS2: Add PCI support
Please disregard this patch. I meant to send out v3 of the core NS2
support, and not a half-baked PCI driver.
Thanks,
Jon
On Wed, Mar 15, 2017 at 1:38 PM, Jon Mason wrote:
> From: Jon Mason
>
> Write a new driver to add PCI support to iProc devices. Currently, this
> will only work for NS2 (due to some hard coding done in the driver), but
> should be extensible in the future. Some hacks had to be made due to
> time constraints, but are documented in the code.
>
> PCI was verified by tftpbooting over an e1000 PCI NIC.
>
> Signed-off-by: Jon Mason
> ---
> configs/bcm958712k_defconfig | 2 +
> drivers/pci/Kconfig | 6 +
> drivers/pci/Makefile | 1 +
> drivers/pci/pcie_iproc.c | 285
> +++
> include/configs/bcm_northstar2.h | 3 +
> 5 files changed, 297 insertions(+)
> create mode 100644 drivers/pci/pcie_iproc.c
>
> diff --git a/configs/bcm958712k_defconfig b/configs/bcm958712k_defconfig
> index 96e4bce..0c4e566 100644
> --- a/configs/bcm958712k_defconfig
> +++ b/configs/bcm958712k_defconfig
> @@ -6,5 +6,7 @@ CONFIG_BOOTDELAY=5
> # CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_SYS_PROMPT="u-boot> "
> # CONFIG_CMD_IMLS is not set
> +CONFIG_PCI=y
> +CONFIG_PCIE_IPROC=y
> CONFIG_SYS_NS16550=y
> CONFIG_OF_LIBFDT=y
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index 692a398..001ddc1 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -79,4 +79,10 @@ config PCIE_LAYERSCAPE
> PCIe controllers. The PCIe may works in RC or EP mode according to
> RCW[HOST_AGT_PEX] setting.
>
> +config PCIE_IPROC
> + bool "iProc PCI support"
> + depends on TARGET_BCMNS2
> + help
> + PCIe Support on iProc based SoCs
> +
> endif
> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> index ad44e83..ddfde4c 100644
> --- a/drivers/pci/Makefile
> +++ b/drivers/pci/Makefile
> @@ -22,6 +22,7 @@ obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
> obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
> obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
> obj-$(CONFIG_PCIE_IMX) += pcie_imx.o
> +obj-$(CONFIG_PCIE_IPROC) += pcie_iproc.o
> obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
> obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o
> obj-$(CONFIG_SH4_PCI) += pci_sh4.o
> diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c
> new file mode 100644
> index 000..66f5cb5
> --- /dev/null
> +++ b/drivers/pci/pcie_iproc.c
> @@ -0,0 +1,285 @@
> +/*
> + * Broadcom iProc PCI Express Root-Complex driver
> + *
> + * Copyright (C) 2016 Broadcom
> + *
> + * SPDX-License-Identifier:GPL-2.0
> + */
> +#include
> +#include
> +#include
> +#include
> +#include
> +//#include
> +//#include
> +
> +#ifdef DEBUG
> +#define pr_debug printf
> +#else
> +#define pr_debug(...) do {} while (0)
> +#endif
> +
> +enum iproc_pcie_type {
> + IPROC_PCI_GEN,
> + IPROC_PCI_NITRO,
> +};
> +
> +struct iproc_pcie {
> + void __iomem *reg;
> +
> + struct pci_controller hose;
> + enum iproc_pcie_type type;
> +};
> +
> +#define GEN_CFG_IND_ADDR_OFFSET0x120
> +#define GEN_CFG_IND_DATA_OFFSET0x124
> +
> +#define NITRO_CFG_IND_ADDR_OFFSET 0x1f0
> +#define NITRO_CFG_IND_DATA_OFFSET 0x1f4
> +
> +#define CLK_CONTROL_OFFSET 0x000
> +#define EP_PERST_SOURCE_SELECT_SHIFT 2
> +#define EP_PERST_SOURCE_SELECT (1 << EP_PERST_SOURCE_SELECT_SHIFT)
> +#define EP_MODE_SURVIVE_PERST_SHIFT1
> +#define EP_MODE_SURVIVE_PERST (1 << EP_MODE_SURVIVE_PERST_SHIFT)
> +#define RC_PCIE_RST_OUTPUT_SHIFT 0
> +#define RC_PCIE_RST_OUTPUT (1 << RC_PCIE_RST_OUTPUT_SHIFT)
> +
> +#define CFG_ADDR_OFFSET0x1F8
> +#define CFG_ADDR_BUS_NUM_SHIFT 20
> +#define CFG_ADDR_BUS_NUM_MASK 0x0FF0
> +#define CFG_ADDR_DEV_NUM_SHIFT 15
> +#define CFG_ADDR_DEV_NUM_MASK 0x000F8000
> +#define CFG_ADDR_FUNC_NUM_SHIFT12
> +#define CFG_ADDR_FUNC_NUM_MASK 0x7000
> +#define CFG_ADDR_REG_NUM_SHIFT 2
> +#define CFG_ADDR_REG_NUM_MASK 0x0FFC
> +#define CFG_ADDR_CFG_TYPE_SHIFT0
> +#define CFG_ADDR_CFG_TYPE_MASK 0x0003
> +
> +#define CFG_DATA_OFFSET0x1FC
> +#define CFG_IND_ADDR_MASK 0x1FFC
> +
> +#define PCIE_LINK_STATUS_OFFSET0xF0C
> +#define PCIE_PHYLINKUP_SHITF 3
> +#define PCIE_PHYLINKUP (1 << PCIE_PHYLINKUP_SHITF)
> +#define PCIE_DL_ACTIVE_SHIFT 2
> +#define PCIE_DL_ACTIVE (1 << PCIE_DL_ACTIVE_SHIFT)
> +
> +#define INVALID_ACCESS_OFFSET 0x
> +
> +#define PAXC_ROOT 0x60c0
> +#define PAXB_0_CLK_CONTROL 0x2002
> +
> +
> +
> +static u32 iproc_pcie_conf_access(struct pci_controller *hose, pci_dev_t d,
> + int where)
> +{
> +
[U-Boot] [PATCH v3] board: ns2: Add support for Broadcom Northstar 2
Add support for the Broadcom Northstar2 SoC and SVK (bcm958712k). The
BCM5871X is a series of quad-core 64-bit 2GHz ARMv8 Cortex-A57
processors targeting a broad range of networking applications.
Signed-off-by: Jon Mason
---
arch/arm/Kconfig | 9 ++
board/broadcom/bcm958712k/MAINTAINERS | 6
board/broadcom/bcmns2/Kconfig | 15 +
board/broadcom/bcmns2/Makefile| 7 +
board/broadcom/bcmns2/northstar2.c| 58 +++
configs/bcm958712k_defconfig | 10 ++
include/configs/bcm_northstar2.h | 55 +
7 files changed, 160 insertions(+)
create mode 100644 board/broadcom/bcm958712k/MAINTAINERS
create mode 100644 board/broadcom/bcmns2/Kconfig
create mode 100644 board/broadcom/bcmns2/Makefile
create mode 100644 board/broadcom/bcmns2/northstar2.c
create mode 100644 configs/bcm958712k_defconfig
create mode 100644 include/configs/bcm_northstar2.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0a05662..c3adf6e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -537,6 +537,14 @@ config TARGET_BCMNSP
bool "Support bcmnsp"
select CPU_V7
+config TARGET_BCMNS2
+ bool "Support Broadcom Northstar2"
+ select ARM64
+ help
+ Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
+ ARMv8 Cortex-A57 processors targeting a broad range of networking
+ applications
+
config ARCH_EXYNOS
bool "Samsung EXYNOS"
select DM
@@ -1197,6 +1205,7 @@ source "board/broadcom/bcm23550_w1d/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
+source "board/broadcom/bcmns2/Kconfig"
source "board/cavium/thunderx/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
diff --git a/board/broadcom/bcm958712k/MAINTAINERS
b/board/broadcom/bcm958712k/MAINTAINERS
new file mode 100644
index 000..024fb14
--- /dev/null
+++ b/board/broadcom/bcm958712k/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM958712K BOARD
+M: Jon Mason
+S: Maintained
+F: board/broadcom/bcmns2/
+F: include/configs/bcm_northstar2.h
+F: configs/bcm958712k_defconfig
diff --git a/board/broadcom/bcmns2/Kconfig b/board/broadcom/bcmns2/Kconfig
new file mode 100644
index 000..3ac6724
--- /dev/null
+++ b/board/broadcom/bcmns2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BCMNS2
+
+config SYS_BOARD
+ default "bcmns2"
+
+config SYS_VENDOR
+ default "broadcom"
+
+config SYS_SOC
+ default "ns2"
+
+config SYS_CONFIG_NAME
+ default "bcm_northstar2"
+
+endif
diff --git a/board/broadcom/bcmns2/Makefile b/board/broadcom/bcmns2/Makefile
new file mode 100644
index 000..f6ddd80
--- /dev/null
+++ b/board/broadcom/bcmns2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Broadcom Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := northstar2.o
diff --git a/board/broadcom/bcmns2/northstar2.c
b/board/broadcom/bcmns2/northstar2.c
new file mode 100644
index 000..a64431d
--- /dev/null
+++ b/board/broadcom/bcmns2/northstar2.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2016 Broadcom Ltd.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include
+#include
+#include
+
+static struct mm_region ns2_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x8000UL,
+ .phys = 0x8000UL,
+ .size = 0xff8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = ns2_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
diff --git a/configs/bcm958712k_defconfig b/configs/bcm958712k_defconfig
new file mode 100644
index 000..96e4bce
--- /dev/null
+++ b/configs/bcm958712k_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BCMNS2=y
+CONFIG_IDENT_STRING=" Broadcom Northstar 2"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="u-boot> "
+# CONFIG_
Re: [U-Boot] [PATCH v2 2/4] regmap: use fdt address translation
On 16 February 2017 at 13:43, Simon Glass wrote: > On 14 February 2017 at 03:20, Jean-Jacques Hiblot wrote: >> >> >> On 14/02/2017 06:23, Simon Glass wrote: >>> >>> Hi, >>> >>> On 13 February 2017 at 08:17, Jean-Jacques Hiblot wrote: In the DTS, the addresses are defined relative to the parent bus. We need to translate them to get the address as seen by the CPU core. Signed-off-by: Jean-Jacques Hiblot --- to: s...@chromium.org drivers/core/regmap.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) >>> >>> This says v2 but I don't see a change log. Can you please resend this? >> >> Hi Simon, >> >> Sorry, I didn't think about sending the whole series to you. The series is >> marked v2 but this particular patch that you and stephen warren have already >> reviewed hasn't changed a bit. >> >> Jean-Jacques > > OK thanks. It's good to have 'v2: no changes' in the patch for this > sort of situation. E.g. patman will do this for you. > > Regards, > Simon Applied to u-boot-dm, thanks! You mention above some review tags but I don't see them in this patch. I think you may have forgotten to add then to you v2, along with the change log? - Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 01/21] reset: Add STi reset support
From: Patrice Chotard
This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device.
Driver code has been mainly extracted from kernel
drivers/reset/sti/reset-stih407.c
Signed-off-by: Patrice Chotard
---
arch/arm/Kconfig| 1 +
configs/stih410-b2260_defconfig | 1 +
drivers/reset/Kconfig | 8 +
drivers/reset/Makefile | 1 +
drivers/reset/sti-reset.c | 321
5 files changed, 332 insertions(+)
create mode 100644 drivers/reset/sti-reset.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 20434dc..af5157e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1100,6 +1100,7 @@ config ARCH_STI
select DM_SERIAL
select BLK
select DM_MMC
+ select DM_RESET
help
Support for STMicroelectronics STiH407/10 SoC family.
This SoC is used on Linaro 96Board STiH410-B2260
diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig
index 4e6942f..9ee2fe4 100644
--- a/configs/stih410-b2260_defconfig
+++ b/configs/stih410-b2260_defconfig
@@ -20,6 +20,7 @@ CONFIG_SYSCON=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_STI=y
CONFIG_PINCTRL=y
+CONFIG_STI_RESET=y
CONFIG_STI_ASC_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c42b0bc..fa77ee4 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -20,6 +20,14 @@ config SANDBOX_RESET
simply accepts requests to reset various HW modules without actually
doing anything beyond a little error checking.
+config STI_RESET
+ bool "Enable the STi reset"
+ depends on ARCH_STI
+ help
+ Support for reset controllers on STMicroelectronics STiH407 family
SoCs.
+ Say Y if you want to control reset signals provided by system config
+ block.
+
config TEGRA_CAR_RESET
bool "Enable Tegra CAR-based reset driver"
depends on TEGRA_CAR
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 5c4305c..2b96396 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_DM_RESET) += reset-uclass.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
+obj-$(CONFIG_STI_RESET) += sti-reset.o
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c
new file mode 100644
index 000..7ce4605
--- /dev/null
+++ b/drivers/reset/sti-reset.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2017
+ * Patrice Chotard
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sti_reset {
+ const struct syscfg_reset_controller_data *data;
+};
+
+/**
+ * Reset channel description for a system configuration register based
+ * reset controller.
+ *
+ * @compatible: Compatible string of the syscon containing this
+ * channel's control and ack (status) bits.
+ * @reset_offset: Reset register offset in sysconf bank.
+ * @reset_bit: Bit number in reset register.
+ * @ack_offset: Ack reset register offset in syscon bank.
+ * @ack_bit: Bit number in Ack reset register.
+ */
+
+struct syscfg_reset_channel_data {
+ const char *compatible;
+ int reset_offset;
+ int reset_bit;
+ int ack_offset;
+ int ack_bit;
+};
+
+/**
+ * Description of a system configuration register based reset controller.
+ *
+ * @wait_for_ack: The controller will wait for reset assert and de-assert to
+ *be "ack'd" in a channel's ack field.
+ * @active_low: Are the resets in this controller active low, i.e. clearing
+ * the reset bit puts the hardware into reset.
+ * @nr_channels: The number of reset channels in this controller.
+ * @channels: An array of reset channel descriptions.
+ */
+struct syscfg_reset_controller_data {
+ bool wait_for_ack;
+ bool active_low;
+ int nr_channels;
+ const struct syscfg_reset_channel_data *channels;
+};
+
+/* STiH407 Peripheral powerdown definitions. */
+static const char stih407_core[] = "st,stih407-core-syscfg";
+static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
+static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
+
+#define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \
+ { .compatible = _c, \
+ .reset_offset = _rr, \
+ .reset_bit= _rb, \
+ .ack_offset = _ar, \
+ .ack_bit = _ab,
[U-Boot] [PATCH 03/21] ARM: dts: stih410-family: Add missing reset_names for mmc1 node
From: Patrice Chotard reset-names property is needed to use the reset API for STi sdhci driver. Signed-off-by: Patrice Chotard --- arch/arm/dts/stih407-family.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/stih407-family.dtsi b/arch/arm/dts/stih407-family.dtsi index af66b53..452ac1c 100644 --- a/arch/arm/dts/stih407-family.dtsi +++ b/arch/arm/dts/stih407-family.dtsi @@ -563,6 +563,7 @@ clocks = <&clk_s_c0_flexgen CLK_MMC_1>, <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; resets = <&softreset STIH407_MMC1_SOFTRESET>; + reset-names = "softreset"; bus-width = <4>; }; -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] dm: core: Fix Handling of global_data moving in SPL
On 12 February 2017 at 20:51, Lokesh Vutla wrote:
> commit 2f11cd9121658 ("dm: core: Handle global_data moving in SPL")
> handles relocation of GD in SPL if spl_init() is called before
> board_init_r(). So, uclass_root.next need not be initialized always
> and accessing uclass_root.next->prev gives an abort. Update the
> uclass_root only if it is available.
>
> Reviewed-by: Simon Glass
> Signed-off-by: Lokesh Vutla
> ---
> drivers/core/root.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/core/root.c b/drivers/core/root.c
> index 9edfc1efb6..4c935f40b6 100644
> --- a/drivers/core/root.c
> +++ b/drivers/core/root.c
> @@ -44,8 +44,10 @@ struct udevice *dm_root(void)
> void dm_fixup_for_gd_move(struct global_data *new_gd)
> {
> /* The sentinel node has moved, so update things that point to it */
> - new_gd->uclass_root.next->prev = &new_gd->uclass_root;
> - new_gd->uclass_root.prev->next = &new_gd->uclass_root;
> + if (gd->dm_root) {
> + new_gd->uclass_root.next->prev = &new_gd->uclass_root;
> + new_gd->uclass_root.prev->next = &new_gd->uclass_root;
> + }
> }
>
> fdt_addr_t dm_get_translation_offset(void)
> --
> 2.11.0
>
Applied to u-boot-dm, thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 02/21] mmc: sti_sdhci: Rework sti_mmc_core_config()
From: Patrice Chotard
Use struct udevice* as input parameter. Previous
parameters are retrieved through plat and priv data.
This to prepare to use the reset framework.
Signed-off-by: Patrice Chotard
---
drivers/mmc/sti_sdhci.c | 33 ++---
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c
index 2a07082..d6c4d67 100644
--- a/drivers/mmc/sti_sdhci.c
+++ b/drivers/mmc/sti_sdhci.c
@@ -16,6 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
struct sti_sdhci_plat {
struct mmc_config cfg;
struct mmc mmc;
+ int instance;
};
/*
@@ -26,8 +27,8 @@ struct sti_sdhci_plat {
/**
* sti_mmc_core_config: configure the Arasan HC
- * @regbase: base address
- * @mmc_instance: mmc instance id
+ * @dev : udevice
+ *
* Description: this function is to configure the Arasan MMC HC.
* This should be called when the system starts in case of, on the SoC,
* it is needed to configure the host controller.
@@ -36,33 +37,35 @@ struct sti_sdhci_plat {
* W/o these settings the SDHCI could configure and use the embedded controller
* with limited features.
*/
-static void sti_mmc_core_config(const u32 regbase, int mmc_instance)
+static void sti_mmc_core_config(struct udevice *dev)
{
+ struct sti_sdhci_plat *plat = dev_get_platdata(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
unsigned long *sysconf;
/* only MMC1 has a reset line */
- if (mmc_instance) {
+ if (plat->instance) {
sysconf = (unsigned long *)(STIH410_SYSCONF5_BASE +
ST_MMC_CCONFIG_REG_5);
generic_set_bit(SYSCONF_MMC1_ENABLE_BIT, sysconf);
}
writel(STI_FLASHSS_MMC_CORE_CONFIG_1,
- regbase + FLASHSS_MMC_CORE_CONFIG_1);
+ host->ioaddr + FLASHSS_MMC_CORE_CONFIG_1);
- if (mmc_instance) {
+ if (plat->instance) {
writel(STI_FLASHSS_MMC_CORE_CONFIG2,
- regbase + FLASHSS_MMC_CORE_CONFIG_2);
+ host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2);
writel(STI_FLASHSS_MMC_CORE_CONFIG3,
- regbase + FLASHSS_MMC_CORE_CONFIG_3);
+ host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3);
} else {
writel(STI_FLASHSS_SDCARD_CORE_CONFIG2,
- regbase + FLASHSS_MMC_CORE_CONFIG_2);
+ host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2);
writel(STI_FLASHSS_SDCARD_CORE_CONFIG3,
- regbase + FLASHSS_MMC_CORE_CONFIG_3);
+ host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3);
}
writel(STI_FLASHSS_MMC_CORE_CONFIG4,
- regbase + FLASHSS_MMC_CORE_CONFIG_4);
+ host->ioaddr + FLASHSS_MMC_CORE_CONFIG_4);
}
static int sti_sdhci_probe(struct udevice *dev)
@@ -70,7 +73,7 @@ static int sti_sdhci_probe(struct udevice *dev)
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sti_sdhci_plat *plat = dev_get_platdata(dev);
struct sdhci_host *host = dev_get_priv(dev);
- int ret, mmc_instance;
+ int ret;
/*
* identify current mmc instance, mmc1 has a reset, not mmc0
@@ -79,11 +82,11 @@ static int sti_sdhci_probe(struct udevice *dev)
*/
if (fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "resets", NULL))
- mmc_instance = 1;
+ plat->instance = 1;
else
- mmc_instance = 0;
+ plat->instance = 0;
- sti_mmc_core_config((const u32) host->ioaddr, mmc_instance);
+ sti_mmc_core_config(dev);
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
SDHCI_QUIRK_32BIT_DMA_ADDR |
--
1.9.1
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[U-Boot] [PATCH 04/21] mmc: sti_sdhci: Use reset framework
From: Patrice Chotard
Signed-off-by: Patrice Chotard
---
drivers/mmc/sti_sdhci.c | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c
index d6c4d67..8b1b2c0 100644
--- a/drivers/mmc/sti_sdhci.c
+++ b/drivers/mmc/sti_sdhci.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
@@ -16,6 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
struct sti_sdhci_plat {
struct mmc_config cfg;
struct mmc mmc;
+ struct reset_ctl reset;
int instance;
};
@@ -37,17 +39,19 @@ struct sti_sdhci_plat {
* W/o these settings the SDHCI could configure and use the embedded controller
* with limited features.
*/
-static void sti_mmc_core_config(struct udevice *dev)
+static int sti_mmc_core_config(struct udevice *dev)
{
struct sti_sdhci_plat *plat = dev_get_platdata(dev);
struct sdhci_host *host = dev_get_priv(dev);
- unsigned long *sysconf;
+ int ret;
/* only MMC1 has a reset line */
if (plat->instance) {
- sysconf = (unsigned long *)(STIH410_SYSCONF5_BASE +
- ST_MMC_CCONFIG_REG_5);
- generic_set_bit(SYSCONF_MMC1_ENABLE_BIT, sysconf);
+ ret = reset_deassert(&plat->reset);
+ if (ret < 0) {
+ error("MMC1 deassert failed: %d", ret);
+ return ret;
+ }
}
writel(STI_FLASHSS_MMC_CORE_CONFIG_1,
@@ -66,6 +70,8 @@ static void sti_mmc_core_config(struct udevice *dev)
}
writel(STI_FLASHSS_MMC_CORE_CONFIG4,
host->ioaddr + FLASHSS_MMC_CORE_CONFIG_4);
+
+ return 0;
}
static int sti_sdhci_probe(struct udevice *dev)
@@ -80,13 +86,20 @@ static int sti_sdhci_probe(struct udevice *dev)
* MMC0 is wired to the SD slot,
* MMC1 is wired on the high speed connector
*/
-
- if (fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "resets", NULL))
+ if (fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "resets", NULL)) {
plat->instance = 1;
- else
+ ret = reset_get_by_name(dev, "softreset", &plat->reset);
+ if (ret) {
+ error("can't get reset for %s (%d)", dev->name, ret);
+ return ret;
+ }
+ } else {
plat->instance = 0;
+ }
- sti_mmc_core_config(dev);
+ ret = sti_mmc_core_config(dev);
+ if (ret)
+ return ret;
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
SDHCI_QUIRK_32BIT_DMA_ADDR |
--
1.9.1
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[U-Boot] [PATCH 00/21] STiH410-B2260: add reset, usb and fastboot support
From: Patrice Chotard This series adds : _ add reset driver _ update existing sdhci driver to use reset framework _ add usb phy driver _ add ehci support _ add ohci support _ add xhci support _ add fastboot support With all this feature enable, it's now possible to _ boot on usb mass storage device _ boot from kernel image and dtb previously loaded using tftp _ update mmc partiton using fastboot Patrice Chotard (21): reset: Add STi reset support mmc: sti_sdhci: Rework sti_mmc_core_config() ARM: dts: stih410-family: Add missing reset_names for mmc1 node mmc: sti_sdhci: Use reset framework phy: Add STi phy usb support usb: ehci: Add STi ehci support STiH410-B2260: enable USB related flags usb: ohci: Add STi ohci support STiH410-B2260: enable OHCI related flags usb: xhci: Add STi xhci support STiH410-B2260: enable XHCI related flags STiH410-B2260: Enabling USB Host Networking usb: dwc3: Add dwc3 support for STi STiH410-B2260: enable DWC3 support board: STiH410-B2260: add fastboot support STiH410-B2260: enable USB download gadget related flags STiH410-B2260: enable FASTBOOT related flags STiH410-B2260: enable OF_LIBFDT_OVERLAY STiH410-B2260: enable CMD_EXT4_WRITE STiH410-B2260: enable CMD_GPT STiH410-B2260: enable CMD_PART arch/arm/Kconfig | 1 + arch/arm/dts/stih407-family.dtsi | 1 + arch/arm/include/asm/arch-stih410/sys_proto.h | 11 + board/st/stih410-b2260/board.c| 44 configs/stih410-b2260_defconfig | 33 +++ drivers/mmc/sti_sdhci.c | 60 +++-- drivers/reset/Kconfig | 8 + drivers/reset/Makefile| 1 + drivers/reset/sti-reset.c | 321 ++ drivers/usb/Kconfig | 4 + drivers/usb/dwc3/Kconfig | 8 + drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-sti.c | 137 +++ drivers/usb/host/Kconfig | 26 +++ drivers/usb/host/Makefile | 3 + drivers/usb/host/ehci-sti.c | 91 drivers/usb/host/ohci-sti.c | 90 drivers/usb/host/xhci-sti.c | 156 + drivers/usb/phy/Kconfig | 11 + drivers/usb/phy/Makefile | 1 + drivers/usb/phy/sti_phy_usb.c | 158 + include/configs/stih410-b2260.h | 16 ++ include/dwc3-sti-uboot.h | 50 23 files changed, 1210 insertions(+), 22 deletions(-) create mode 100644 arch/arm/include/asm/arch-stih410/sys_proto.h create mode 100644 drivers/reset/sti-reset.c create mode 100644 drivers/usb/dwc3/dwc3-sti.c create mode 100644 drivers/usb/host/ehci-sti.c create mode 100644 drivers/usb/host/ohci-sti.c create mode 100644 drivers/usb/host/xhci-sti.c create mode 100644 drivers/usb/phy/Kconfig create mode 100644 drivers/usb/phy/sti_phy_usb.c create mode 100644 include/dwc3-sti-uboot.h -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 10/21] usb: xhci: Add STi xhci support
From: Patrice Chotard
Add support for on-chip DWC3 controller available
on STMicrolectronics STiH407 family SoCs.
On B2260 board, the type AB USB connector is managed
by a DWC3 IP. As USB3 signals are not wired, only USB2
is supported.
Signed-off-by: Patrice Chotard
---
drivers/usb/host/Kconfig| 8 +++
drivers/usb/host/Makefile | 1 +
drivers/usb/host/xhci-sti.c | 156
include/configs/stih410-b2260.h | 1 +
4 files changed, 166 insertions(+)
create mode 100644 drivers/usb/host/xhci-sti.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 33ded5d..58b64df 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -37,6 +37,14 @@ config USB_XHCI_ROCKCHIP
help
Enables support for the on-chip xHCI controller on Rockchip SoCs.
+config USB_XHCI_STI
+ bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB
controller"
+ depends on ARCH_STI
+ default y
+ help
+ Enables support for the on-chip xHCI controller on STMicroelectronics
+ STiH407 family SoCs.
+
config USB_XHCI_ZYNQMP
bool "Support for Xilinx ZynqMP on-chip xHCI USB controller"
depends on ARCH_ZYNQMP
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index b78e632..40ff830 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
+obj-$(CONFIG_USB_XHCI_STI) += xhci-sti.o
# designware
obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/xhci-sti.c b/drivers/usb/host/xhci-sti.c
new file mode 100644
index 000..00f17ce
--- /dev/null
+++ b/drivers/usb/host/xhci-sti.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2017
+ * Patrice Chotard
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "xhci.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sti_xhci_platdata {
+ struct reset_ctl powerdown_ctl;
+ struct reset_ctl softreset_ctl;
+ phys_addr_t dwc3_regs;
+};
+
+struct sti_xhci_priv {
+ struct xhci_ctrl ctrl;
+};
+
+
+static int sti_xhci_ofdata_to_platdata(struct udevice *dev)
+{
+ struct sti_xhci_platdata *plat = dev_get_platdata(dev);
+ struct udevice *dev_phy;
+ int ret;
+ int phy_node;
+ int dwc3_node;
+ u32 reg[2];
+
+ /* get powerdown reset */
+ ret = reset_get_by_name(dev, "powerdown", &plat->powerdown_ctl);
+ if (ret) {
+ error("can't get powerdown reset for %s (%d)", dev->name, ret);
+ return ret;
+ }
+
+ /* get softreset reset */
+ ret = reset_get_by_name(dev, "softreset", &plat->softreset_ctl);
+ if (ret) {
+ error("can't get soft reset for %s (%d)", dev->name, ret);
+ return ret;
+ }
+
+ /* deassert both powerdown and softreset */
+ ret = reset_deassert(&plat->powerdown_ctl);
+ if (ret < 0) {
+ error("DWC3 powerdown reset deassert failed: %d", ret);
+ return ret;
+ }
+
+ ret = reset_deassert(&plat->softreset_ctl);
+ if (ret < 0) {
+ error("DWC3 soft reset deassert failed: %d", ret);
+ return ret;
+ }
+
+ /* check if dwc3 subnode is present */
+ dwc3_node = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
+ if (dwc3_node <= 0) {
+ error("Can't find subnode for st_dwc3 glue driver\n");
+ return -ENODEV;
+ }
+
+ if (fdt_node_check_compatible(gd->fdt_blob, dwc3_node,
+ "snps,dwc3") != 0) {
+ error("Can't find dwv3 subnode for st_dwc3 glue driver\n");
+ return -ENODEV;
+ }
+
+ /*
+* now parse the dwc3 node
+* first get the phy node: only usb2-phy, no need to get usb3-phy as
+* usb3 is not wired
+*/
+ phy_node = fdtdec_lookup_phandle(gd->fdt_blob, dwc3_node, "phys");
+ if (phy_node <= 0) {
+ error("Can't find usb phy device\n");
+ return -ENODEV;
+ }
+
+ /* get the dwc3 register space base address */
+ if (fdtdec_get_int_array(gd->fdt_blob, dwc3_node, "reg", reg,
+ARRAY_SIZE(reg))) {
+ debug("dwc3 node has bad/missing 'reg' property\n");
+ return -FDT_ERR_NOTFOUND;
+ }
+ plat->dwc3_regs = reg[0];
+
+ /* probe associated phy */
+ return uclass_get_device_by_of_offset(UCLASS_MISC, phy_node, &dev_phy);
+};
+
+static int sti_xhci_core_init(struct dwc3 *dwc3_reg)
+{
+ int ret;
+
+ ret = dwc3_core_init(dwc3_reg);
+ if (ret) {
+ debug("failed to
[U-Boot] [PATCH 20/21] STiH410-B2260: enable CMD_GPT
From: Patrice Chotard Signed-off-by: Patrice Chotard --- configs/stih410-b2260_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 90de12a..4c6a0a1 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -15,6 +15,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x3DF0 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 # CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 07/21] STiH410-B2260: enable USB related flags
From: Patrice Chotard Signed-off-by: Patrice Chotard --- configs/stih410-b2260_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index ade618f..c2c7256 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_SYS_PROMPT="stih410-b2260 => " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT2=y @@ -25,4 +26,8 @@ CONFIG_STI_RESET=y CONFIG_STI_ASC_SERIAL=y CONFIG_SYSRESET=y CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y CONFIG_SPL_OF_LIBFDT=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 14/21] STiH410-B2260: enable DWC3 support
From: Patrice Chotard Signed-off-by: Patrice Chotard --- configs/stih410-b2260_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index fd13ea3..6deca22 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -35,5 +35,8 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_STI=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_STI=y CONFIG_USB_STORAGE=y CONFIG_SPL_OF_LIBFDT=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 17/21] STiH410-B2260: enable FASTBOOT related flags
From: Patrice Chotard Signed-off-by: Patrice Chotard --- configs/stih410-b2260_defconfig | 8 1 file changed, 8 insertions(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 839da4d..f79173c 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -6,6 +6,14 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="stih410-b2260 => " +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_BUF_ADDR=0x4000 +CONFIG_FASTBOOT_BUF_SIZE=0x3DF0 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 18/21] STiH410-B2260: enable OF_LIBFDT_OVERLAY
From: Patrice Chotard Signed-off-by: Patrice Chotard --- configs/stih410-b2260_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index f79173c..83a1e3c 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -52,4 +52,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="STMicroelectronics" CONFIG_G_DNL_VENDOR_NUM=0x483 CONFIG_G_DNL_PRODUCT_NUM=0x7270 +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SPL_OF_LIBFDT=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 16/21] STiH410-B2260: enable USB download gadget related flags
From: Patrice Chotard Signed-off-by: Patrice Chotard --- configs/stih410-b2260_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 6deca22..839da4d 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -39,4 +39,9 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_STI=y CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="STMicroelectronics" +CONFIG_G_DNL_VENDOR_NUM=0x483 +CONFIG_G_DNL_PRODUCT_NUM=0x7270 CONFIG_SPL_OF_LIBFDT=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 21/21] STiH410-B2260: enable CMD_PART
From: Patrice Chotard Signed-off-by: Patrice Chotard --- configs/stih410-b2260_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 4c6a0a1..c1113fc 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -17,6 +17,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0 # CONFIG_CMD_IMLS is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 08/21] usb: ohci: Add STi ohci support
From: Patrice Chotard
Add support for on-chip ohci controller available
on STMicrolectronics SoCs.
Ohci support will be then available on both type A
USB 2.0 connectors.
Signed-off-by: Patrice Chotard
---
drivers/usb/host/Kconfig| 9 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ohci-sti.c | 90 +
include/configs/stih410-b2260.h | 3 ++
4 files changed, 103 insertions(+)
create mode 100644 drivers/usb/host/ohci-sti.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index d66f49e..33ded5d 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -168,6 +168,15 @@ config USB_OHCI_GENERIC
---help---
Enables support for generic OHCI controller.
+config USB_OHCI_STI
+ bool "Support for STMicroelectronics OHCI USB controller"
+ depends on ARCH_STI
+ depends on OF_CONTROL
+ depends on DM_USB
+ select USB_HOST
+ ---help---
+ Enables support for the on-chip OHCI controller on STMicroelectronics
SoCs.
+
endif # USB_OHCI_HCD
config USB_UHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 303aa32..b78e632 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o
obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o
+obj-$(CONFIG_USB_OHCI_STI) += ohci-sti.o
# echi
obj-$(CONFIG_USB_EHCI) += ehci-hcd.o
diff --git a/drivers/usb/host/ohci-sti.c b/drivers/usb/host/ohci-sti.c
new file mode 100644
index 000..62b63cd
--- /dev/null
+++ b/drivers/usb/host/ohci-sti.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2017
+ * Patrice Chotard
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include "ohci.h"
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_USB_OHCI_NEW)
+# error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW"
+#endif
+
+struct sti_ohci_priv {
+ ohci_t ohci;
+ struct reset_ctl power_ctl;
+ struct reset_ctl softreset_ctl;
+};
+
+static int ohci_usb_probe(struct udevice *dev)
+{
+ struct sti_ohci_priv *priv = dev_get_priv(dev);
+ struct ohci_regs *regs;
+ struct udevice *dev_phy;
+ int ret, phy_node;
+
+ regs = (struct ohci_regs *)dev_get_addr(dev);
+ if (regs == (void *)FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ ret = reset_get_by_name(dev, "power", &priv->power_ctl);
+ if (ret) {
+ error("can't get power reset for %s (%d)", dev->name, ret);
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "softreset", &priv->softreset_ctl);
+ if (ret) {
+ error("can't get soft reset for %s (%d)", dev->name, ret);
+ return ret;
+ }
+
+ ret = reset_deassert(&priv->power_ctl);
+ if (ret < 0) {
+ error("OHCI power reset deassert failed: %d", ret);
+ return ret;
+ }
+
+ ret = reset_deassert(&priv->softreset_ctl);
+ if (ret < 0) {
+ error("OHCI soft reset deassert failed: %d", ret);
+ return ret;
+ }
+
+ /* get phy node */
+ phy_node = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "phys");
+ if (phy_node <= 0) {
+ error("Not found usb phy device\n");
+ return -ENODEV;
+ }
+
+ /* probe associated phy node */
+ ret = uclass_get_device_by_of_offset(UCLASS_MISC, phy_node, &dev_phy);
+
+ return ohci_register(dev, regs);
+}
+
+static const struct udevice_id sti_usb_ids[] = {
+ { .compatible = "st,st-ohci-300x" },
+ { }
+};
+
+U_BOOT_DRIVER(ohci_sti) = {
+ .name = "ohci_sti",
+ .id = UCLASS_USB,
+ .of_match = sti_usb_ids,
+ .probe = ohci_usb_probe,
+ .remove = ohci_deregister,
+ .ops = &ohci_usb_ops,
+ .priv_auto_alloc_size = sizeof(struct sti_ohci_priv),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h
index 28e2f7f..4a5da82 100644
--- a/include/configs/stih410-b2260.h
+++ b/include/configs/stih410-b2260.h
@@ -57,4 +57,7 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+
#endif /* __CONFIG_H */
--
1.9.1
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[U-Boot] [PATCH 19/21] STiH410-B2260: enable CMD_EXT4_WRITE
From: Patrice Chotard Signed-off-by: Patrice Chotard --- configs/stih410-b2260_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 83a1e3c..90de12a 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 11/21] STiH410-B2260: enable XHCI related flags
From: Patrice Chotard Signed-off-by: Patrice Chotard --- configs/stih410-b2260_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 46c20e1..835f982 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -28,6 +28,8 @@ CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_STI=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 12/21] STiH410-B2260: Enabling USB Host Networking
From: Patrice Chotard Signed-off-by: Patrice Chotard --- configs/stih410-b2260_defconfig | 2 ++ include/configs/stih410-b2260.h | 12 2 files changed, 14 insertions(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 835f982..fd13ea3 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -9,6 +9,8 @@ CONFIG_SYS_PROMPT="stih410-b2260 => " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT2=y diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index bbf64d7..0a52af3 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -57,8 +57,20 @@ #define CONFIG_SKIP_LOWLEVEL_INIT +/* USB Configs */ #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX + +/* NET Configs */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + #endif /* __CONFIG_H */ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 05/21] phy: Add STi phy usb support
From: Patrice Chotard
This is the generic phy driver for the picoPHY ports
used by USB2 and USB3 Host controllers available on
STiH407 SoC families.
Signed-off-by: Patrice Chotard
---
configs/stih410-b2260_defconfig | 1 +
drivers/usb/Kconfig | 4 +
drivers/usb/phy/Kconfig | 11 +++
drivers/usb/phy/Makefile| 1 +
drivers/usb/phy/sti_phy_usb.c | 158
5 files changed, 175 insertions(+)
create mode 100644 drivers/usb/phy/Kconfig
create mode 100644 drivers/usb/phy/sti_phy_usb.c
diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig
index 9ee2fe4..ade618f 100644
--- a/configs/stih410-b2260_defconfig
+++ b/configs/stih410-b2260_defconfig
@@ -17,6 +17,7 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_STI=y
CONFIG_PINCTRL=y
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index da3ec2f..e30c9d6 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -94,4 +94,8 @@ endif
source "drivers/usb/gadget/Kconfig"
+comment "USB PHY"
+
+source "drivers/usb/phy/Kconfig"
+
endif
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
new file mode 100644
index 000..1a86c6e
--- /dev/null
+++ b/drivers/usb/phy/Kconfig
@@ -0,0 +1,11 @@
+menu "USB PHY drivers"
+
+config STI_PHY_USB
+ bool "STMicroelectronics USB2 picoPHY driver for STiH407 family"
+ default n
+ help
+ This is the generic phy driver for the picoPHY ports
+ used by USB2 and USB3 Host controllers available on
+ STiH407 SoC families.
+
+endmenu
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 4e548c2..b50fb5a 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -8,3 +8,4 @@
obj-$(CONFIG_TWL4030_USB) += twl4030.o
obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o
obj-$(CONFIG_ROCKCHIP_USB2_PHY) += rockchip_usb2_phy.o
+obj-$(CONFIG_STI_PHY_USB) += sti_phy_usb.o
diff --git a/drivers/usb/phy/sti_phy_usb.c b/drivers/usb/phy/sti_phy_usb.c
new file mode 100644
index 000..214d7ff
--- /dev/null
+++ b/drivers/usb/phy/sti_phy_usb.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2017
+ * Patrice Chotard
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Default PHY_SEL and REFCLKSEL configuration */
+#define STIH407_USB_PICOPHY_CTRL_PORT_CONF 0x6
+
+/* ports parameters overriding */
+#define STIH407_USB_PICOPHY_PARAM_DEF 0x39a4dc
+
+#define PHYPARAM_REG 1
+#define PHYCTRL_REG2
+#define PHYPARAM_NB3
+
+struct sti_phy_usb {
+ struct regmap *regmap;
+ struct reset_ctl global_ctl;
+ struct reset_ctl port_ctl;
+ int param;
+ int ctrl;
+};
+
+static int sti_phy_usb_deassert(struct sti_phy_usb *phy)
+{
+ int ret;
+
+ ret = reset_deassert(&phy->global_ctl);
+ if (ret < 0) {
+ error("PHY global deassert failed: %d", ret);
+ return ret;
+ }
+
+ ret = reset_deassert(&phy->port_ctl);
+ if (ret < 0)
+ error("PHY port deassert failed: %d", ret);
+
+ return ret;
+}
+
+static void sti_phy_usb_init(struct sti_phy_usb *phy)
+{
+ void __iomem *reg;
+ u32 val;
+
+ /* set ctrl picophy value */
+ reg = (void __iomem *)phy->regmap->base + phy->ctrl;
+ val = readl(reg);
+ /* CTRL_PORT mask is 0x1f */
+ bitfield_replace(val, 0, 5, STIH407_USB_PICOPHY_CTRL_PORT_CONF);
+ writel(val, reg);
+
+ /* set ports parameters overriding */
+ reg = (void __iomem *)phy->regmap->base + phy->param;
+ val = readl(reg);
+ /* PARAM_DEF mask is 0x */
+ bitfield_replace(val, 0, 31, STIH407_USB_PICOPHY_PARAM_DEF);
+ writel(val, reg);
+}
+
+int sti_phy_usb_probe(struct udevice *dev)
+{
+ struct sti_phy_usb *priv = dev_get_priv(dev);
+ struct udevice *syscon;
+ struct fdtdec_phandle_args syscfg_phandle;
+ u32 cells[PHYPARAM_NB];
+ int ret, count;
+
+ /* get corresponding syscon phandle */
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+"st,syscfg", NULL, 0, 0,
+&syscfg_phandle);
+ if (ret < 0) {
+ error("Can't get syscfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_SYSCON, syscfg_phandle.node,
+&syscon);
+ if (ret) {
+ error("unable to find syscon device (%d)\n", ret);
+ return ret;
+ }
+
+ priv->regmap = syscon_get_regmap(syscon);
+ if (!priv->regmap) {
+ error("unable to find regm
[U-Boot] [PATCH 09/21] STiH410-B2260: enable OHCI related flags
From: Patrice Chotard Signed-off-by: Patrice Chotard --- configs/stih410-b2260_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index c2c7256..46c20e1 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -29,5 +29,7 @@ CONFIG_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_STI=y CONFIG_USB_STORAGE=y CONFIG_SPL_OF_LIBFDT=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 06/21] usb: ehci: Add STi ehci support
From: Patrice Chotard
Add support for on-chip ehci controller available
on STMicrolectronics SoCs.
ehci support will be then available on both type A
USB 2.0 connectors.
Signed-off-by: Patrice Chotard
---
drivers/usb/host/Kconfig| 9 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-sti.c | 91 +
3 files changed, 101 insertions(+)
create mode 100644 drivers/usb/host/ehci-sti.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 5129a57..d66f49e 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -120,6 +120,15 @@ config USB_EHCI_MSM
This driver supports combination of Chipidea USB controller
and Synapsys USB PHY in host mode only.
+config USB_EHCI_STI
+ bool "Support for STMicroelectronics on-chip EHCI USB controller"
+ depends on ARCH_STI
+ select STI_PHY_USB
+ default y
+ ---help---
+ Enables support for the on-chip EHCI controller on
+ STMicroelectronics SoCs.
+
config USB_EHCI_ZYNQ
bool "Support for Xilinx Zynq on-chip EHCI USB controller"
depends on ARCH_ZYNQ
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 58c0cf5..303aa32 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o
obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
+obj-$(CONFIG_USB_EHCI_STI) += ehci-sti.o
obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
diff --git a/drivers/usb/host/ehci-sti.c b/drivers/usb/host/ehci-sti.c
new file mode 100644
index 000..89ca66a
--- /dev/null
+++ b/drivers/usb/host/ehci-sti.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2017
+ * Patrice Chotard
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include "ehci.h"
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sti_ehci_priv {
+ struct ehci_ctrl ctrl;
+ struct reset_ctl power_ctl;
+ struct reset_ctl softreset_ctl;
+};
+
+static int sti_ehci_probe(struct udevice *dev)
+{
+ struct sti_ehci_priv *priv = dev_get_priv(dev);
+ struct ehci_hccr *hccr = priv->ctrl.hccr;
+ struct ehci_hcor *hcor;
+ struct udevice *dev_phy;
+ int ret, phy_node;
+
+ hccr = (struct ehci_hccr *)dev_get_addr(dev);
+
+ if (hccr == (void *)FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ ret = reset_get_by_name(dev, "power", &priv->power_ctl);
+ if (ret) {
+ error("can't get power reset for %s (%d)", dev->name, ret);
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "softreset", &priv->softreset_ctl);
+ if (ret) {
+ error("can't get soft reset for %s (%d)", dev->name, ret);
+ return ret;
+ }
+
+ ret = reset_deassert(&priv->power_ctl);
+ if (ret < 0) {
+ error("EHCI power reset deassert failed: %d", ret);
+ return ret;
+ }
+
+ ret = reset_deassert(&priv->softreset_ctl);
+ if (ret < 0) {
+ error("EHCI soft reset deassert failed: %d", ret);
+ return ret;
+ }
+
+ /* get phy node */
+ phy_node = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "phys");
+ if (phy_node <= 0) {
+ error("Not found usb phy device\n");
+ return -ENODEV;
+ }
+
+ /* probe associated phy */
+ ret = uclass_get_device_by_of_offset(UCLASS_MISC, phy_node, &dev_phy);
+
+ hcor = (struct ehci_hcor *)((phys_addr_t)hccr +
+ HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
+
+ return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
+}
+
+static const struct udevice_id sti_usb_ids[] = {
+ { .compatible = "st,st-ehci-300x" },
+ { }
+};
+
+U_BOOT_DRIVER(ehci_sti) = {
+ .name = "ehci_sti",
+ .id = UCLASS_USB,
+ .of_match = sti_usb_ids,
+ .probe = sti_ehci_probe,
+ .remove = ehci_deregister,
+ .ops = &ehci_usb_ops,
+ .priv_auto_alloc_size = sizeof(struct sti_ehci_priv),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
--
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[U-Boot] [PATCH 13/21] usb: dwc3: Add dwc3 support for STi
From: Patrice Chotard
This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It configures the internal glue
logic and syscfg registers.
Part of this code been extracted from kernel.org driver
(drivers/usb/dwc3/dwc3-st.c)
Signed-off-by: Patrice Chotard
---
arch/arm/include/asm/arch-stih410/sys_proto.h | 11 +++
drivers/usb/dwc3/Kconfig | 8 ++
drivers/usb/dwc3/Makefile | 1 +
drivers/usb/dwc3/dwc3-sti.c | 137 ++
include/dwc3-sti-uboot.h | 50 ++
5 files changed, 207 insertions(+)
create mode 100644 arch/arm/include/asm/arch-stih410/sys_proto.h
create mode 100644 drivers/usb/dwc3/dwc3-sti.c
create mode 100644 include/dwc3-sti-uboot.h
diff --git a/arch/arm/include/asm/arch-stih410/sys_proto.h
b/arch/arm/include/asm/arch-stih410/sys_proto.h
new file mode 100644
index 000..5c40d3b
--- /dev/null
+++ b/arch/arm/include/asm/arch-stih410/sys_proto.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2017
+ * Patrice Chotard
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SYS_PROTO_H
+#define _ASM_ARCH_SYS_PROTO_H
+
+#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index e93398f..51a7a00 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -37,6 +37,14 @@ config USB_DWC3_OMAP
Say 'Y' here if you have one such device
+config USB_DWC3_STI
+ bool "STMicroelectronics STiH407 family glue driver"
+ help
+ STMicroelectronics STiH407 family SoCs use this IP for
+ USB2/3 functionality.
+
+ Say 'Y' here if you have one such device
+
menu "PHY Subsystem"
config USB_DWC3_PHY_OMAP
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 2964bae..753912d 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o
obj-$(CONFIG_USB_DWC3_OMAP)+= dwc3-omap.o
obj-$(CONFIG_USB_DWC3_PHY_OMAP)+= ti_usb_phy.o
obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o
+obj-$(CONFIG_USB_DWC3_STI) += dwc3-sti.o
diff --git a/drivers/usb/dwc3/dwc3-sti.c b/drivers/usb/dwc3/dwc3-sti.c
new file mode 100644
index 000..5ff3e76
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-sti.c
@@ -0,0 +1,137 @@
+/*
+ * dwc3-sti.c - STiH407 family DWC3 specific Glue layer
+ * Copyright (c) 2017
+ * Patrice Chotard
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int __board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
+/*int board_usb_init(int index, enum usb_init_type init)*/
+/*__attribute__((weak, alias("__board_usb_init")));*/
+
+static int sti_dwc3_drd_init(struct sti_dwc3_platdata *plat)
+{
+ unsigned long val;
+
+ val = readl(plat->syscfg_base + plat->syscfg_offset);
+
+ val &= USB3_CONTROL_MASK;
+
+ switch (plat->mode) {
+ case USB_DR_MODE_PERIPHERAL:
+ val &= ~(USB3_DELAY_VBUSVALID
+ | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
+ | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
+ | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
+
+ val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID;
+ break;
+
+ case USB_DR_MODE_HOST:
+ val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID
+ | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
+ | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
+ | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
+
+ val |= USB3_DELAY_VBUSVALID;
+ break;
+
+ default:
+ error("Unsupported mode of operation %d\n", plat->mode);
+ return -EINVAL;
+ }
+ return writel(val, plat->syscfg_base + plat->syscfg_offset);
+}
+
+static void sti_dwc3_init(struct sti_dwc3_platdata *plat)
+{
+ unsigned long reg;
+
+ reg = readl(plat->glue_base + CLKRST_CTRL);
+
+ reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION;
+ reg &= ~SW_PIPEW_RESET_N;
+
+ writel(reg, plat->glue_base + CLKRST_CTRL);
+
+ /* configure mux for vbus, powerpresent and bvalid signals */
+ reg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1);
+
+ reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) |
+ SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) |
+ SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG);
+
+ writel(reg, plat->glue_base + USB2_VBUS_MNGMNT_SEL1);
+
+ reg = readl(plat->glue_base + CLKRST_CTRL);
+ reg |= SW_PIPEW_RESET_N;
+ writel(reg, plat->glue_base + CLKRST_CTRL);
+}
+
+int sti_dwc3_glue_init(en
[U-Boot] [PATCH 15/21] board: STiH410-B2260: add fastboot support
From: Patrice Chotard
Add usb_gadget_handle_interrupts(), board_usb_init(),
board_usb_cleanup() and g_dnl_board_usb_cable_connected()
callbacks needed for FASTBOOT support
Signed-off-by: Patrice Chotard
---
board/st/stih410-b2260/board.c | 44 ++
1 file changed, 44 insertions(+)
diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c
index 0c06bca..363c016 100644
--- a/board/st/stih410-b2260/board.c
+++ b/board/st/stih410-b2260/board.c
@@ -7,6 +7,9 @@
*/
#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -26,3 +29,44 @@ int board_init(void)
{
return 0;
}
+
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device dwc3_device_data = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+ dwc3_uboot_handle_interrupt(index);
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int node;
+ const void *blob = gd->fdt_blob;
+
+ /* find the snps,dwc3 node */
+ node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
+
+ dwc3_device_data.base = fdtdec_get_addr(blob, node, "reg");
+
+ /* init dwc3 glue with mode forced to PERIPHERAL */
+ sti_dwc3_glue_init(USB_DR_MODE_PERIPHERAL);
+
+ return dwc3_uboot_init(&dwc3_device_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ dwc3_uboot_exit(index);
+ return 0;
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+ return 1;
+}
+#endif
--
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Re: [U-Boot] [PATCH 05/21] phy: Add STi phy usb support
On 03/17/2017 05:25 PM, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> This is the generic phy driver for the picoPHY ports
> used by USB2 and USB3 Host controllers available on
> STiH407 SoC families.
>
> Signed-off-by: Patrice Chotard
> ---
> configs/stih410-b2260_defconfig | 1 +
> drivers/usb/Kconfig | 4 +
> drivers/usb/phy/Kconfig | 11 +++
> drivers/usb/phy/Makefile| 1 +
> drivers/usb/phy/sti_phy_usb.c | 158
>
> 5 files changed, 175 insertions(+)
> create mode 100644 drivers/usb/phy/Kconfig
> create mode 100644 drivers/usb/phy/sti_phy_usb.c
>
> diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig
> index 9ee2fe4..ade618f 100644
> --- a/configs/stih410-b2260_defconfig
> +++ b/configs/stih410-b2260_defconfig
> @@ -17,6 +17,7 @@ CONFIG_CMD_FS_GENERIC=y
> CONFIG_OF_CONTROL=y
> CONFIG_REGMAP=y
> CONFIG_SYSCON=y
> +CONFIG_MISC=y
> CONFIG_MMC_SDHCI=y
> CONFIG_MMC_SDHCI_STI=y
> CONFIG_PINCTRL=y
> diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
> index da3ec2f..e30c9d6 100644
> --- a/drivers/usb/Kconfig
> +++ b/drivers/usb/Kconfig
> @@ -94,4 +94,8 @@ endif
>
> source "drivers/usb/gadget/Kconfig"
>
> +comment "USB PHY"
> +
> +source "drivers/usb/phy/Kconfig"
> +
> endif
> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
> new file mode 100644
> index 000..1a86c6e
> --- /dev/null
> +++ b/drivers/usb/phy/Kconfig
> @@ -0,0 +1,11 @@
> +menu "USB PHY drivers"
> +
> +config STI_PHY_USB
> + bool "STMicroelectronics USB2 picoPHY driver for STiH407 family"
> + default n
> + help
> + This is the generic phy driver for the picoPHY ports
> + used by USB2 and USB3 Host controllers available on
> + STiH407 SoC families.
> +
> +endmenu
> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
> index 4e548c2..b50fb5a 100644
> --- a/drivers/usb/phy/Makefile
> +++ b/drivers/usb/phy/Makefile
> @@ -8,3 +8,4 @@
> obj-$(CONFIG_TWL4030_USB) += twl4030.o
> obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o
> obj-$(CONFIG_ROCKCHIP_USB2_PHY) += rockchip_usb2_phy.o
> +obj-$(CONFIG_STI_PHY_USB) += sti_phy_usb.o
> diff --git a/drivers/usb/phy/sti_phy_usb.c b/drivers/usb/phy/sti_phy_usb.c
> new file mode 100644
> index 000..214d7ff
> --- /dev/null
> +++ b/drivers/usb/phy/sti_phy_usb.c
> @@ -0,0 +1,158 @@
> +/*
> + * Copyright (c) 2017
> + * Patrice Chotard
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* Default PHY_SEL and REFCLKSEL configuration */
> +#define STIH407_USB_PICOPHY_CTRL_PORT_CONF 0x6
> +
> +/* ports parameters overriding */
> +#define STIH407_USB_PICOPHY_PARAM_DEF0x39a4dc
> +
> +#define PHYPARAM_REG 1
> +#define PHYCTRL_REG 2
> +#define PHYPARAM_NB 3
> +
> +struct sti_phy_usb {
> + struct regmap *regmap;
> + struct reset_ctl global_ctl;
> + struct reset_ctl port_ctl;
> + int param;
> + int ctrl;
> +};
> +
> +static int sti_phy_usb_deassert(struct sti_phy_usb *phy)
> +{
> + int ret;
> +
> + ret = reset_deassert(&phy->global_ctl);
> + if (ret < 0) {
> + error("PHY global deassert failed: %d", ret);
> + return ret;
> + }
> +
> + ret = reset_deassert(&phy->port_ctl);
> + if (ret < 0)
> + error("PHY port deassert failed: %d", ret);
> +
> + return ret;
> +}
> +
> +static void sti_phy_usb_init(struct sti_phy_usb *phy)
> +{
> + void __iomem *reg;
> + u32 val;
> +
> + /* set ctrl picophy value */
> + reg = (void __iomem *)phy->regmap->base + phy->ctrl;
> + val = readl(reg);
> + /* CTRL_PORT mask is 0x1f */
> + bitfield_replace(val, 0, 5, STIH407_USB_PICOPHY_CTRL_PORT_CONF);
> + writel(val, reg);
> +
> + /* set ports parameters overriding */
> + reg = (void __iomem *)phy->regmap->base + phy->param;
> + val = readl(reg);
> + /* PARAM_DEF mask is 0x */
> + bitfield_replace(val, 0, 31, STIH407_USB_PICOPHY_PARAM_DEF);
is that clrsetbits_le32() here ?
> + writel(val, reg);
> +}
> +
> +int sti_phy_usb_probe(struct udevice *dev)
> +{
> + struct sti_phy_usb *priv = dev_get_priv(dev);
> + struct udevice *syscon;
> + struct fdtdec_phandle_args syscfg_phandle;
> + u32 cells[PHYPARAM_NB];
> + int ret, count;
> +
> + /* get corresponding syscon phandle */
> + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
> + "st,syscfg", NULL, 0, 0,
> + &syscfg_phandle);
> + if (ret < 0) {
> + error("Can't get syscfg phandle: %d\n", ret);
> + return ret;
> + }
> +
> + ret = uclass_get_device_by_of_offset(UCLASS
Re: [U-Boot] [PATCH 06/21] usb: ehci: Add STi ehci support
On 03/17/2017 05:25 PM, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Add support for on-chip ehci controller available
> on STMicrolectronics SoCs.
> ehci support will be then available on both type A
> USB 2.0 connectors.
>
> Signed-off-by: Patrice Chotard
> ---
> drivers/usb/host/Kconfig| 9 +
> drivers/usb/host/Makefile | 1 +
> drivers/usb/host/ehci-sti.c | 91
> +
> 3 files changed, 101 insertions(+)
> create mode 100644 drivers/usb/host/ehci-sti.c
>
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 5129a57..d66f49e 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -120,6 +120,15 @@ config USB_EHCI_MSM
> This driver supports combination of Chipidea USB controller
> and Synapsys USB PHY in host mode only.
>
> +config USB_EHCI_STI
> + bool "Support for STMicroelectronics on-chip EHCI USB controller"
> + depends on ARCH_STI
> + select STI_PHY_USB
> + default y
> + ---help---
> + Enables support for the on-chip EHCI controller on
> + STMicroelectronics SoCs.
> +
> config USB_EHCI_ZYNQ
> bool "Support for Xilinx Zynq on-chip EHCI USB controller"
> depends on ARCH_ZYNQ
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 58c0cf5..303aa32 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -46,6 +46,7 @@ obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
> obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o
> obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
> obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
> +obj-$(CONFIG_USB_EHCI_STI) += ehci-sti.o
> obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
> obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
> obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
> diff --git a/drivers/usb/host/ehci-sti.c b/drivers/usb/host/ehci-sti.c
> new file mode 100644
> index 000..89ca66a
> --- /dev/null
> +++ b/drivers/usb/host/ehci-sti.c
> @@ -0,0 +1,91 @@
> +/*
> + * Copyright (c) 2017
> + * Patrice Chotard
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include "ehci.h"
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct sti_ehci_priv {
> + struct ehci_ctrl ctrl;
> + struct reset_ctl power_ctl;
> + struct reset_ctl softreset_ctl;
> +};
> +
> +static int sti_ehci_probe(struct udevice *dev)
> +{
> + struct sti_ehci_priv *priv = dev_get_priv(dev);
> + struct ehci_hccr *hccr = priv->ctrl.hccr;
> + struct ehci_hcor *hcor;
> + struct udevice *dev_phy;
> + int ret, phy_node;
> +
> + hccr = (struct ehci_hccr *)dev_get_addr(dev);
> +
> + if (hccr == (void *)FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + ret = reset_get_by_name(dev, "power", &priv->power_ctl);
> + if (ret) {
> + error("can't get power reset for %s (%d)", dev->name, ret);
power or reset ? I think the error messages could use some improvement,
the code looks mostly OK.
> + return ret;
> + }
> +
> + ret = reset_get_by_name(dev, "softreset", &priv->softreset_ctl);
> + if (ret) {
> + error("can't get soft reset for %s (%d)", dev->name, ret);
> + return ret;
> + }
> +
> + ret = reset_deassert(&priv->power_ctl);
> + if (ret < 0) {
> + error("EHCI power reset deassert failed: %d", ret);
> + return ret;
> + }
> +
> + ret = reset_deassert(&priv->softreset_ctl);
> + if (ret < 0) {
> + error("EHCI soft reset deassert failed: %d", ret);
> + return ret;
> + }
> +
> + /* get phy node */
> + phy_node = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "phys");
> + if (phy_node <= 0) {
> + error("Not found usb phy device\n");
"USB PHY DT node not found."
> + return -ENODEV;
> + }
> +
> + /* probe associated phy */
> + ret = uclass_get_device_by_of_offset(UCLASS_MISC, phy_node, &dev_phy);
> +
> + hcor = (struct ehci_hcor *)((phys_addr_t)hccr +
> + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
> +
> + return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
> +}
> +
> +static const struct udevice_id sti_usb_ids[] = {
> + { .compatible = "st,st-ehci-300x" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(ehci_sti) = {
> + .name = "ehci_sti",
> + .id = UCLASS_USB,
> + .of_match = sti_usb_ids,
> + .probe = sti_ehci_probe,
> + .remove = ehci_deregister,
You should put the core into reset state on removal ...
> + .ops = &ehci_usb_ops,
> + .priv_auto_alloc_size = sizeof(struct sti_ehci_priv),
> + .flags = DM_FLAG_ALLOC_PRIV_DMA,
> +};
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 08/21] usb: ohci: Add STi ohci support
On 03/17/2017 05:25 PM, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Add support for on-chip ohci controller available
> on STMicrolectronics SoCs.
> Ohci support will be then available on both type A
> USB 2.0 connectors.
>
> Signed-off-by: Patrice Chotard
> ---
> drivers/usb/host/Kconfig| 9 +
> drivers/usb/host/Makefile | 1 +
> drivers/usb/host/ohci-sti.c | 90
> +
> include/configs/stih410-b2260.h | 3 ++
> 4 files changed, 103 insertions(+)
> create mode 100644 drivers/usb/host/ohci-sti.c
>
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index d66f49e..33ded5d 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -168,6 +168,15 @@ config USB_OHCI_GENERIC
> ---help---
> Enables support for generic OHCI controller.
>
> +config USB_OHCI_STI
> + bool "Support for STMicroelectronics OHCI USB controller"
> + depends on ARCH_STI
> + depends on OF_CONTROL
> + depends on DM_USB
> + select USB_HOST
> + ---help---
> + Enables support for the on-chip OHCI controller on STMicroelectronics
> SoCs.
> +
> endif # USB_OHCI_HCD
>
> config USB_UHCI_HCD
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 303aa32..b78e632 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -22,6 +22,7 @@ obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
> obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o
> obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
> obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o
> +obj-$(CONFIG_USB_OHCI_STI) += ohci-sti.o
>
> # echi
> obj-$(CONFIG_USB_EHCI) += ehci-hcd.o
> diff --git a/drivers/usb/host/ohci-sti.c b/drivers/usb/host/ohci-sti.c
> new file mode 100644
> index 000..62b63cd
> --- /dev/null
> +++ b/drivers/usb/host/ohci-sti.c
> @@ -0,0 +1,90 @@
> +/*
> + * Copyright (c) 2017
> + * Patrice Chotard
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include "ohci.h"
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#if !defined(CONFIG_USB_OHCI_NEW)
> +# error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW"
> +#endif
> +
> +struct sti_ohci_priv {
> + ohci_t ohci;
> + struct reset_ctl power_ctl;
> + struct reset_ctl softreset_ctl;
> +};
> +
> +static int ohci_usb_probe(struct udevice *dev)
> +{
> + struct sti_ohci_priv *priv = dev_get_priv(dev);
> + struct ohci_regs *regs;
> + struct udevice *dev_phy;
> + int ret, phy_node;
> +
> + regs = (struct ohci_regs *)dev_get_addr(dev);
> + if (regs == (void *)FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + ret = reset_get_by_name(dev, "power", &priv->power_ctl);
> + if (ret) {
> + error("can't get power reset for %s (%d)", dev->name, ret);
> + return ret;
> + }
> +
> + ret = reset_get_by_name(dev, "softreset", &priv->softreset_ctl);
> + if (ret) {
> + error("can't get soft reset for %s (%d)", dev->name, ret);
> + return ret;
> + }
> +
> + ret = reset_deassert(&priv->power_ctl);
> + if (ret < 0) {
> + error("OHCI power reset deassert failed: %d", ret);
> + return ret;
> + }
> +
> + ret = reset_deassert(&priv->softreset_ctl);
> + if (ret < 0) {
> + error("OHCI soft reset deassert failed: %d", ret);
> + return ret;
> + }
> +
> + /* get phy node */
> + phy_node = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "phys");
> + if (phy_node <= 0) {
> + error("Not found usb phy device\n");
> + return -ENODEV;
> + }
> +
> + /* probe associated phy node */
> + ret = uclass_get_device_by_of_offset(UCLASS_MISC, phy_node, &dev_phy);
> +
> + return ohci_register(dev, regs);
> +}
> +
> +static const struct udevice_id sti_usb_ids[] = {
> + { .compatible = "st,st-ohci-300x" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(ohci_sti) = {
> + .name = "ohci_sti",
> + .id = UCLASS_USB,
> + .of_match = sti_usb_ids,
> + .probe = ohci_usb_probe,
> + .remove = ohci_deregister,
> + .ops = &ohci_usb_ops,
> + .priv_auto_alloc_size = sizeof(struct sti_ohci_priv),
> + .flags = DM_FLAG_ALLOC_PRIV_DMA,
> +};
> diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h
> index 28e2f7f..4a5da82 100644
> --- a/include/configs/stih410-b2260.h
> +++ b/include/configs/stih410-b2260.h
> @@ -57,4 +57,7 @@
>
> #define CONFIG_SKIP_LOWLEVEL_INIT
>
> +#define CONFIG_USB_OHCI_NEW
> +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Is this max_root_ports still needed ? :(
btw this board-thing should likely be split into separate patch
> #endif /* __CONFIG_H */
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 13/21] usb: dwc3: Add dwc3 support for STi
On 03/17/2017 05:25 PM, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> This patch adds the ST glue logic to manage the DWC3 HC
> on STiH407 SoC family. It configures the internal glue
> logic and syscfg registers.
>
> Part of this code been extracted from kernel.org driver
> (drivers/usb/dwc3/dwc3-st.c)
>
> Signed-off-by: Patrice Chotard
> ---
> arch/arm/include/asm/arch-stih410/sys_proto.h | 11 +++
> drivers/usb/dwc3/Kconfig | 8 ++
> drivers/usb/dwc3/Makefile | 1 +
> drivers/usb/dwc3/dwc3-sti.c | 137
> ++
> include/dwc3-sti-uboot.h | 50 ++
> 5 files changed, 207 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-stih410/sys_proto.h
> create mode 100644 drivers/usb/dwc3/dwc3-sti.c
> create mode 100644 include/dwc3-sti-uboot.h
>
> diff --git a/arch/arm/include/asm/arch-stih410/sys_proto.h
> b/arch/arm/include/asm/arch-stih410/sys_proto.h
> new file mode 100644
> index 000..5c40d3b
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-stih410/sys_proto.h
> @@ -0,0 +1,11 @@
> +/*
> + * Copyright (c) 2017
> + * Patrice Chotard
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef _ASM_ARCH_SYS_PROTO_H
> +#define _ASM_ARCH_SYS_PROTO_H
> +
> +#endif /* _ASM_ARCH_SYS_PROTO_H */
> diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> index e93398f..51a7a00 100644
> --- a/drivers/usb/dwc3/Kconfig
> +++ b/drivers/usb/dwc3/Kconfig
> @@ -37,6 +37,14 @@ config USB_DWC3_OMAP
>
> Say 'Y' here if you have one such device
>
> +config USB_DWC3_STI
> + bool "STMicroelectronics STiH407 family glue driver"
> + help
> + STMicroelectronics STiH407 family SoCs use this IP for
> + USB2/3 functionality.
> +
> + Say 'Y' here if you have one such device
> +
> menu "PHY Subsystem"
>
> config USB_DWC3_PHY_OMAP
> diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
> index 2964bae..753912d 100644
> --- a/drivers/usb/dwc3/Makefile
> +++ b/drivers/usb/dwc3/Makefile
> @@ -11,3 +11,4 @@ obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o
> ep0.o
> obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
> obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o
> obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o
> +obj-$(CONFIG_USB_DWC3_STI) += dwc3-sti.o
> diff --git a/drivers/usb/dwc3/dwc3-sti.c b/drivers/usb/dwc3/dwc3-sti.c
> new file mode 100644
> index 000..5ff3e76
> --- /dev/null
> +++ b/drivers/usb/dwc3/dwc3-sti.c
> @@ -0,0 +1,137 @@
> +/*
> + * dwc3-sti.c - STiH407 family DWC3 specific Glue layer
> + * Copyright (c) 2017
> + * Patrice Chotard
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +__weak int __board_usb_init(int index, enum usb_init_type init)
> +{
> + return 0;
> +}
> +/*int board_usb_init(int index, enum usb_init_type init)*/
> +/*__attribute__((weak, alias("__board_usb_init")));*/
> +
> +static int sti_dwc3_drd_init(struct sti_dwc3_platdata *plat)
> +{
> + unsigned long val;
> +
> + val = readl(plat->syscfg_base + plat->syscfg_offset);
> +
> + val &= USB3_CONTROL_MASK;
> +
> + switch (plat->mode) {
> + case USB_DR_MODE_PERIPHERAL:
> + val &= ~(USB3_DELAY_VBUSVALID
> + | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
> + | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
> + | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
> +
> + val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID;
> + break;
> +
> + case USB_DR_MODE_HOST:
> + val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID
> + | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
> + | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
> + | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
> +
> + val |= USB3_DELAY_VBUSVALID;
> + break;
> +
> + default:
> + error("Unsupported mode of operation %d\n", plat->mode);
> + return -EINVAL;
> + }
> + return writel(val, plat->syscfg_base + plat->syscfg_offset);
> +}
> +
> +static void sti_dwc3_init(struct sti_dwc3_platdata *plat)
> +{
> + unsigned long reg;
> +
> + reg = readl(plat->glue_base + CLKRST_CTRL);
> +
> + reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION;
> + reg &= ~SW_PIPEW_RESET_N;
> +
> + writel(reg, plat->glue_base + CLKRST_CTRL);
> +
> + /* configure mux for vbus, powerpresent and bvalid signals */
> + reg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1);
> +
> + reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) |
> +SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) |
> +
Re: [U-Boot] [PATCH 21/21] STiH410-B2260: enable CMD_PART
On 03/17/2017 05:25 PM, patrice.chot...@st.com wrote: > From: Patrice Chotard Just squash all the config patches into a single patch please ... > Signed-off-by: Patrice Chotard > --- > configs/stih410-b2260_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig > index 4c6a0a1..c1113fc 100644 > --- a/configs/stih410-b2260_defconfig > +++ b/configs/stih410-b2260_defconfig > @@ -17,6 +17,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0 > # CONFIG_CMD_IMLS is not set > CONFIG_CMD_GPT=y > CONFIG_CMD_MMC=y > +CONFIG_CMD_PART=y > CONFIG_CMD_USB=y > CONFIG_CMD_DHCP=y > CONFIG_CMD_PING=y > -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] uboot information
+Bin Hi Sebastian, On 17 March 2017 at 11:23, Sébastien Basset wrote: > > Hello, > > Sorry for the inconvenience, i have problem for read mmc on my board with > braswell cpu, i would like test on other board, i have nuc intel with > braswell,is there possible when there is already bios to load uboot ? > > else has any chance, I use coreboot + uboot, i would like run kernel on > sdmmc, but i have an problem for communicate with sdcard. I read cid & > reference of card but when try read SCR(version & bus width) of card, doesn't > work . For read scr, it's first Transfer mode in SDMA .i had no error for > read data but buffer is empty, why ?I use coreboot + uboot, i would like run > kernel on sdmmc, but i have an problem for communicate with sdcard. I read > cid & reference of card but when try read SCR(version & bus width) of card, > doesn't work . For read scr, it's first Transfer mode in SDMA .i had no error > for read data but buffer is empty, why ? Just to be clear, are you running U-Boot on top of Coreboot? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Linker error when using CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+ML Hi Dan, On 17 March 2017 at 12:16, Dan Murphy wrote: > Simon > > I wanted to drop you a note to see if you have any advice on how to fix this > issue. > > In the attached .config file we enable > > CONFIG_SPL_SYS_MALLOC_SIMPLE and CONFIG_SPL_DFU_SUPPORT which we need > CONFIG_SPL_DFU_RAM > > When doing this we find that there is a build error > > common/built-in.o: In function `xrealloc': > common/cli_hush.c:3349: undefined reference to `realloc_simple' > common/built-in.o: In function `done_word': > common/cli_hush.c:2494: undefined reference to `realloc_simple' > cli_hush.c:2499: undefined reference to `realloc_simple' > common/built-in.o: In function `b_check_space': > common/cli_hush.c:876: undefined reference to `realloc_simple' > make[1]: *** [spl/u-boot-spl] Error 1 > make: *** [spl/u-boot-spl] Error 2 > > In digging into this I am finding that realloc_simple is not defined anywhere > in uboot. malloc_simple.c seems > to be missing the implementation. > > I am looking to see if you have a patch that fixes this issue or if you can > guide us to a resolution. > > Right now our only work around is to disable the HUSH_PARSER or turn off the > MALLOC simple. Which according to > Lokesh, CC'd, is needed for DM support. So SPL is using hush? Is there a description somewhere of what it does with that? If you have enough space for hush I wonder whether you can just use full malloc() in SPL? You could implement realloc_simple() by just calling malloc_simple() and copying the old data over, but it is inefficient. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Linker error when using CONFIG_SPL_SYS_MALLOC_SIMPLE=y
Simon On 03/17/2017 01:24 PM, Simon Glass wrote: > +ML > > Hi Dan, > > On 17 March 2017 at 12:16, Dan Murphy wrote: >> Simon >> >> I wanted to drop you a note to see if you have any advice on how to fix this >> issue. >> >> In the attached .config file we enable >> >> CONFIG_SPL_SYS_MALLOC_SIMPLE and CONFIG_SPL_DFU_SUPPORT which we need >> CONFIG_SPL_DFU_RAM >> >> When doing this we find that there is a build error >> >> common/built-in.o: In function `xrealloc': >> common/cli_hush.c:3349: undefined reference to `realloc_simple' >> common/built-in.o: In function `done_word': >> common/cli_hush.c:2494: undefined reference to `realloc_simple' >> cli_hush.c:2499: undefined reference to `realloc_simple' >> common/built-in.o: In function `b_check_space': >> common/cli_hush.c:876: undefined reference to `realloc_simple' >> make[1]: *** [spl/u-boot-spl] Error 1 >> make: *** [spl/u-boot-spl] Error 2 >> >> In digging into this I am finding that realloc_simple is not defined >> anywhere in uboot. malloc_simple.c seems >> to be missing the implementation. >> >> I am looking to see if you have a patch that fixes this issue or if you can >> guide us to a resolution. >> >> Right now our only work around is to disable the HUSH_PARSER or turn off the >> MALLOC simple. Which according to >> Lokesh, CC'd, is needed for DM support. > So SPL is using hush? Is there a description somewhere of what it does > with that? HUSH_PARSER was added to the TI config in commit adad96e60 configs: Re-sync HUSH options. HUSH calls realloc in the builtin functions. I am not sure what SPL would do with the HUSH. > If you have enough space for hush I wonder whether you can just use > full malloc() in SPL? You could implement realloc_simple() by just > calling malloc_simple() and copying the old data over, but it is > inefficient. We could work around it but the undef reference will still exist for other code that would need realloc. Lokesh Do we run out of room using full malloc support in the SPL with the DM code added? Dan > Regards, > Simon -- -- Dan Murphy ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] configs: dra7x/am57x: Enable the SYSCON and REGMAP features
Hi, On 10 February 2017 at 09:22, Simon Glass wrote: > On 7 February 2017 at 08:45, Jean-Jacques Hiblot wrote: >> This is required by the ti_qspi driver to get from the DTS the address of >> the ctrl_mod_mmap register. >> >> Signed-off-by: Jean-Jacques Hiblot >> --- >> configs/am57xx_evm_defconfig| 2 ++ >> configs/am57xx_hs_evm_defconfig | 2 ++ >> configs/dra7xx_evm_defconfig| 2 ++ >> configs/dra7xx_hs_evm_defconfig | 2 ++ >> 4 files changed, 8 insertions(+) > > Reviewed-by: Simon Glass This doesn't apply, and given that patch 1 has been dropped in favour of something else, would you mind checking this and resending what you need to on top of dm/testing? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/4] drivers: ti_qspi: use syscon to get the address ctrl_mod_mmap register
On 13 February 2017 at 08:17, Jean-Jacques Hiblot wrote: > We used to get the address of the optionnal ctrl_mod_mmap register as the > third memory range of the "reg" property. the linux driver moved to use a > syscon instead. In order to keep the DTS as close as possible to that of > linux, we move to using a syscon as well. > > If SYSCON is not supported, the driver reverts to the old way of getting > the address from the 3rd memory range > > Signed-off-by: Jean-Jacques Hiblot > --- > drivers/spi/ti_qspi.c | 47 ++- > 1 file changed, 42 insertions(+), 5 deletions(-) Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] dtoc: make ScanTree recurse into subnodes
On 22 February 2017 at 19:23, Simon Glass wrote:
> On 22 February 2017 at 11:06, Philipp Tomsich
> wrote:
>>
>> Previously, dtoc could only process the top-level nodes which led to
>> device nodes in hierarchical trees to be ignored. E.g. the mmc0 node
>> in the following example would be ignored, as only the soc node was
>> processed:
>>
>> / {
>> soc {
>> mmc0 {
>> /* ... */
>> };
>> };
>> };
>>
>> This introduces a recursive helper method ScanNode, which is used by
>> ScanTree to recursively parse the entire tree hierarchy.
>>
>> Signed-off-by: Philipp Tomsich
>> ---
>> tools/dtoc/dtoc.py | 19 ++-
>> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> Reviewed-by: Simon Glass
Applied to u-boot-dm, thanks!
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Re: [U-Boot] Linker error when using CONFIG_SPL_SYS_MALLOC_SIMPLE=y
Hi Dan, On 17 March 2017 at 12:33, Dan Murphy wrote: > Simon > > On 03/17/2017 01:24 PM, Simon Glass wrote: >> +ML >> >> Hi Dan, >> >> On 17 March 2017 at 12:16, Dan Murphy wrote: >>> Simon >>> >>> I wanted to drop you a note to see if you have any advice on how to fix >>> this issue. >>> >>> In the attached .config file we enable >>> >>> CONFIG_SPL_SYS_MALLOC_SIMPLE and CONFIG_SPL_DFU_SUPPORT which we need >>> CONFIG_SPL_DFU_RAM >>> >>> When doing this we find that there is a build error >>> >>> common/built-in.o: In function `xrealloc': >>> common/cli_hush.c:3349: undefined reference to `realloc_simple' >>> common/built-in.o: In function `done_word': >>> common/cli_hush.c:2494: undefined reference to `realloc_simple' >>> cli_hush.c:2499: undefined reference to `realloc_simple' >>> common/built-in.o: In function `b_check_space': >>> common/cli_hush.c:876: undefined reference to `realloc_simple' >>> make[1]: *** [spl/u-boot-spl] Error 1 >>> make: *** [spl/u-boot-spl] Error 2 >>> >>> In digging into this I am finding that realloc_simple is not defined >>> anywhere in uboot. malloc_simple.c seems >>> to be missing the implementation. >>> >>> I am looking to see if you have a patch that fixes this issue or if you can >>> guide us to a resolution. >>> >>> Right now our only work around is to disable the HUSH_PARSER or turn off >>> the MALLOC simple. Which according to >>> Lokesh, CC'd, is needed for DM support. >> So SPL is using hush? Is there a description somewhere of what it does >> with that? > > HUSH_PARSER was added to the TI config in commit adad96e60 configs: Re-sync > HUSH options. > > HUSH calls realloc in the builtin functions. I am not sure what SPL would do > with the HUSH. > >> If you have enough space for hush I wonder whether you can just use >> full malloc() in SPL? You could implement realloc_simple() by just >> calling malloc_simple() and copying the old data over, but it is >> inefficient. > We could work around it but the undef reference will still exist for other > code that would need realloc. Right, but the point of simple malloc() is to be simple, and realloc() is assumed not to be needed until you have a proper malloc(). > > Lokesh > > Do we run out of room using full malloc support in the SPL with the DM code > added? > > Dan Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] libfdt: use CONFIG_IS_ENABLED for OF_LIBFDT
Hi, On 13 February 2017 at 01:08, Lokesh Vutla wrote: > > > On Monday 13 February 2017 01:04 PM, Vignesh R wrote: >> Use CONFIG_IS_ENABLED() macro to check whether OF_LIBFDT is enabled, so >> that code block is compiled irrespective of SPL or U-Boot build >> depending on CONFIG_SPL_OF_LIBFDT(for SPL) or CONFIG_OF_LIBFDT(for >> U-Boot). >> >> Signed-off-by: Vignesh R > > Reviewed-by: Lokesh Vutla > > Thanks and regards, > Lokesh Unfortunately this breaks boards which use SPL and OF_CONTROL: 06: dtoc: make ScanTree recurse into subnodes aarch64: + xilinx_zynqmp_zc1751_xm018_dc4 xilinx_zynqmp_zcu102 xilinx_zynqmp_zc1751_xm015_dc1 xilinx_zynqmp_zc1751_xm019_dc5 xilinx_zynqmp_zc1751_xm016_dc2 xilinx_zynqmp_ep xilinx_zynqmp_zcu102_revB arm: + socfpga_de0_nano_soc uniphier_pro4 uniphier_ld4_sld8 zynq_zc770_xm010 zynq_zc770_xm012 zynq_zc706 evb-rk3288 socfpga_arria5 zynq_zybo rock2 socfpga_socrates uniphier_sld3 zynq_microzed socfpga_sr1500 tinker-rk3288 zynq_zed socfpga_de1_soc firefly-rk3288 sama5d2_xplained_spiflash topic_miami sama5d2_xplained_mmc socfpga_sockit zynq_zc702 socfpga_is1 zynq_picozed fennec-rk3288 zynq_zc770_xm011 zynq_zc770_xm013 popmetal-rk3288 socfpga_mcvevk topic_miamiplus socfpga_cyclone5 socfpga_vining_fpga uniphier_pxs2_ld6b microblaze: + microblaze-generic x86: + qemu-x86_64 chromebook_link64 +lib/built-in.o: In function `fdtdec_get_addr_size_fixed': +build/../lib/fdtdec.c:117: undefined reference to `fdt_translate_address' +make[2]: *** [spl/u-boot-spl] Error 1 +make[1]: *** [spl/u-boot-spl] Error 2 +build/../lib/fdtdec. You can move the position of fdt_support.o in common/Makefile to fix this. It also bloats SPL on many boards which currently don't need address translation. For example firefly-rk3288 goes from ~20KB to ~26KB. Can you add an option to enable address translation in SPL perhaps? Then it will be disabled by default on existing boards. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] libfdt: use CONFIG_IS_ENABLED for OF_LIBFDT
On Fri, Mar 17, 2017 at 12:46:17PM -0600, Simon Glass wrote: > Hi, > > On 13 February 2017 at 01:08, Lokesh Vutla wrote: > > > > > > On Monday 13 February 2017 01:04 PM, Vignesh R wrote: > >> Use CONFIG_IS_ENABLED() macro to check whether OF_LIBFDT is enabled, so > >> that code block is compiled irrespective of SPL or U-Boot build > >> depending on CONFIG_SPL_OF_LIBFDT(for SPL) or CONFIG_OF_LIBFDT(for > >> U-Boot). > >> > >> Signed-off-by: Vignesh R > > > > Reviewed-by: Lokesh Vutla > > > > Thanks and regards, > > Lokesh > > Unfortunately this breaks boards which use SPL and OF_CONTROL: > > 06: dtoc: make ScanTree recurse into subnodes >aarch64: + xilinx_zynqmp_zc1751_xm018_dc4 xilinx_zynqmp_zcu102 > xilinx_zynqmp_zc1751_xm015_dc1 xilinx_zynqmp_zc1751_xm019_dc5 > xilinx_zynqmp_zc1751_xm016_dc2 xilinx_zynqmp_ep > xilinx_zynqmp_zcu102_revB >arm: + socfpga_de0_nano_soc uniphier_pro4 uniphier_ld4_sld8 > zynq_zc770_xm010 zynq_zc770_xm012 zynq_zc706 evb-rk3288 socfpga_arria5 > zynq_zybo rock2 socfpga_socrates uniphier_sld3 zynq_microzed > socfpga_sr1500 tinker-rk3288 zynq_zed socfpga_de1_soc firefly-rk3288 > sama5d2_xplained_spiflash topic_miami sama5d2_xplained_mmc > socfpga_sockit zynq_zc702 socfpga_is1 zynq_picozed fennec-rk3288 > zynq_zc770_xm011 zynq_zc770_xm013 popmetal-rk3288 socfpga_mcvevk > topic_miamiplus socfpga_cyclone5 socfpga_vining_fpga > uniphier_pxs2_ld6b > microblaze: + microblaze-generic >x86: + qemu-x86_64 chromebook_link64 > +lib/built-in.o: In function `fdtdec_get_addr_size_fixed': > +build/../lib/fdtdec.c:117: undefined reference to `fdt_translate_address' > +make[2]: *** [spl/u-boot-spl] Error 1 > +make[1]: *** [spl/u-boot-spl] Error 2 > +build/../lib/fdtdec. > > You can move the position of fdt_support.o in common/Makefile to fix this. > > It also bloats SPL on many boards which currently don't need address > translation. For example firefly-rk3288 goes from ~20KB to ~26KB. > > Can you add an option to enable address translation in SPL perhaps? > Then it will be disabled by default on existing boards. Does that include when we use gcc-6.x and are able to discard all of the unused strings (which is I assume what's bloating things) ? At some point we will need to say that SoC $X/$Y/$Z only work with gcc-6.x and later due to size issues. Not that we're strictly at that point yet, and may indeed want to fix this by moving functions around to allow for the older toolchains to be able to discard the strings. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Linker error when using CONFIG_SPL_SYS_MALLOC_SIMPLE=y
Simon On 03/17/2017 01:46 PM, Simon Glass wrote: > Hi Dan, > > On 17 March 2017 at 12:33, Dan Murphy wrote: >> Simon >> >> On 03/17/2017 01:24 PM, Simon Glass wrote: >>> +ML >>> >>> Hi Dan, >>> >>> On 17 March 2017 at 12:16, Dan Murphy wrote: Simon I wanted to drop you a note to see if you have any advice on how to fix this issue. In the attached .config file we enable CONFIG_SPL_SYS_MALLOC_SIMPLE and CONFIG_SPL_DFU_SUPPORT which we need CONFIG_SPL_DFU_RAM When doing this we find that there is a build error common/built-in.o: In function `xrealloc': common/cli_hush.c:3349: undefined reference to `realloc_simple' common/built-in.o: In function `done_word': common/cli_hush.c:2494: undefined reference to `realloc_simple' cli_hush.c:2499: undefined reference to `realloc_simple' common/built-in.o: In function `b_check_space': common/cli_hush.c:876: undefined reference to `realloc_simple' make[1]: *** [spl/u-boot-spl] Error 1 make: *** [spl/u-boot-spl] Error 2 In digging into this I am finding that realloc_simple is not defined anywhere in uboot. malloc_simple.c seems to be missing the implementation. I am looking to see if you have a patch that fixes this issue or if you can guide us to a resolution. Right now our only work around is to disable the HUSH_PARSER or turn off the MALLOC simple. Which according to Lokesh, CC'd, is needed for DM support. >>> So SPL is using hush? Is there a description somewhere of what it does >>> with that? >> HUSH_PARSER was added to the TI config in commit adad96e60 configs: Re-sync >> HUSH options. >> >> HUSH calls realloc in the builtin functions. I am not sure what SPL would >> do with the HUSH. >> >>> If you have enough space for hush I wonder whether you can just use >>> full malloc() in SPL? You could implement realloc_simple() by just >>> calling malloc_simple() and copying the old data over, but it is >>> inefficient. >> We could work around it but the undef reference will still exist for other >> code that would need realloc. > Right, but the point of simple malloc() is to be simple, and realloc() > is assumed not to be needed until you have a proper malloc(). By proper malloc you mean the dlmalloc code? If thats true then why is realloc even defined in the simple malloc case? Dan >> Lokesh >> >> Do we run out of room using full malloc support in the SPL with the DM code >> added? >> >> Dan > Regards, > Simon -- -- Dan Murphy ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/10] stm32f7: add clock and pin control drivers
Hi, Just a gentle reminder to pick the series whenever you get time. Cheers, Vikas > -Original Message- > From: Tom Rini [mailto:tr...@konsulko.com] > Sent: Wednesday, March 01, 2017 7:39 AM > To: Vikas MANOCHA > Cc: u-boot@lists.denx.de > Subject: Re: [PATCH v3 00/10] stm32f7: add clock and pin control drivers > > On Mon, Feb 27, 2017 at 05:33:58PM +, Vikas MANOCHA wrote: > > > Hi Tom, > > > > If it is ok, please apply this patchset. > > I'll pick it up early in the next release, thanks! > > -- > Tom ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] armv7m: add instruction & data cache support
Thanks Simon,
On 03/16/2017 03:06 PM, Simon Glass wrote:
> Hi Vikas,
>
> On 14 March 2017 at 11:27, Vikas Manocha wrote:
>> This patch adds armv7m instruction & data cache support.
>>
>> Signed-off-by: Vikas Manocha
>> cc: Christophe KERELLO
>> ---
>>
>> Changed in v3:
>> - uint32 replcaed with u32.
>> - multiple read of hardware register replaced with single.
>> - pointers replaced with macros for base address.
>> - register names added as comment for system control block registers.
>>
>> Changed in v2:
>> - changed strucures for memory mapped cache registers to macros
>> - added lines better readability.
>> - replaced magic numbers with macros.
>>
>> arch/arm/cpu/armv7m/Makefile | 2 +-
>> arch/arm/cpu/armv7m/cache.c | 291
>> ++
>> arch/arm/include/asm/armv7m.h | 26 +++-
>> arch/arm/lib/Makefile | 2 +
>> 4 files changed, 318 insertions(+), 3 deletions(-)
>> create mode 100644 arch/arm/cpu/armv7m/cache.c
>>
>> diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
>> index aff60e8..41efe11 100644
>> --- a/arch/arm/cpu/armv7m/Makefile
>> +++ b/arch/arm/cpu/armv7m/Makefile
>> @@ -6,4 +6,4 @@
>> #
>>
>> extra-y := start.o
>> -obj-y += cpu.o
>> +obj-y += cpu.o cache.o
>> diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
>> new file mode 100644
>> index 000..9021525
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7m/cache.c
>> @@ -0,0 +1,291 @@
>> +/*
>> + * (C) Copyright 2017
>> + * Vikas Manocha, ST Micoelectronics, vikas.mano...@st.com.
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>
> put this one below common.h
oh yes, ok.
>
>> +
>> +/* Cache maintenance operation registers */
>> +
>> +#define IC_IALLU (V7M_CACHE_MAINT_BASE + 0x00)
>> +#define INVAL_ICACHE_POU 0
>> +#define IC_IMVALU (V7M_CACHE_MAINT_BASE + 0x08)
>> +#define DC_IMVAC (V7M_CACHE_MAINT_BASE + 0x0C)
>> +#define DC_ISW (V7M_CACHE_MAINT_BASE + 0x10)
>> +#define DC_CMVAU (V7M_CACHE_MAINT_BASE + 0x14)
>> +#define DC_CMVAC (V7M_CACHE_MAINT_BASE + 0x18)
>> +#define DC_CSW (V7M_CACHE_MAINT_BASE + 0x1C)
>> +#define DC_CIMVAC (V7M_CACHE_MAINT_BASE + 0x20)
>> +#define DC_CISW(V7M_CACHE_MAINT_BASE + 0x24)
>> +#define WAYS_SHIFT 30
>> +#define SETS_SHIFT 5
>> +
>> +/* armv7m processor feature registers */
>> +
>> +#define CLIDR (V7M_PROC_FTR_BASE + 0x00)
>> +#define CTR(V7M_PROC_FTR_BASE + 0x04)
>> +#define CCSIDR (V7M_PROC_FTR_BASE + 0x08)
>> +#define MASK_NUM_WAYS GENMASK(12, 3)
>> +#define MASK_NUM_SETS GENMASK(27, 13)
>> +#define CLINE_SIZE_MASKGENMASK(2, 0)
>> +#define NUM_WAYS_SHIFT 3
>> +#define NUM_SETS_SHIFT 13
>> +#define CSSELR (V7M_PROC_FTR_BASE + 0x0C)
>> +#define SEL_I_OR_D BIT(0)
>> +
>> +enum cache_type {
>> + DCACHE = 0,
>
> Do you need the =0 ?
No :-), thanks.
>
>> + ICACHE,
>> +};
>> +
>> +/* PoU : Point of Unification, Poc: Point of Coherency */
>> +enum cache_action {
>> + INVALIDATE_POU, /* for i-cache invalidate by address */
>> + INVALIDATE_POC, /* for d-cache invalidate by address */
>> + INVALIDATE_SET_WAY, /* for d-cache invalidate by sets/ways */
>> + FLUSH_POU,
>> + FLUSH_POC,
>> + FLUSH_SET_WAY,
>> + FLUSH_INVAL_POC,
>> + FLUSH_INVAL_SET_WAY,
>
> Can you add comments for the rest?
sure.
>
>> +};
>> +
>> +#ifndef CONFIG_SYS_DCACHE_OFF
>> +struct dcache_config {
>> + u32 ways;
>> + u32 sets;
>> +};
>> +
>> +static void get_cache_ways_sets(struct dcache_config *cache)
>> +{
>> + u32 cache_size_id = readl(CCSIDR);
>
> blank line here
ok.
>
>> + cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
>> + cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT;
>> +}
>> +
>> +static u32 *get_action_reg_set_ways(enum cache_action action)
>
> Can you please add a function comment? What does this return?
this function returns the io register to perform required cache action like
clean or clean & invalidate
by sets/ways. The procedure to perform on these io register is same for
cleaning & clean/invalidate.
I will add the comment in code.
>
>> +{
>> + switch (action) {
>> + case INVALIDATE_SET_WAY:
>> + return (u32 *)DC_ISW;
>
> Can you drop these casts by using a C structure or by putting thecast
> in the #define?
C structures was the first choice but they were removed after v1 as per review
comment & replaced with #defines.
ok for the casting in #defines.
>
>> + case FLUSH_SET_WAY:
>> + return (u32 *)DC_CSW;
>> + case FLUSH_INVAL_SET_WAY:
>> +
Re: [U-Boot] [PATCH v2 1/2] armv7m: add instruction & data cache support
Hi Marek,
On 03/16/2017 03:06 PM, Marek Vasut wrote:
> On 03/16/2017 10:39 PM, vikas wrote:
>> Thanks Marek,
>>
>> On 03/16/2017 02:40 PM, Marek Vasut wrote:
>>> On 03/13/2017 10:45 PM, vikas wrote:
Thanks Marek,
On 03/11/2017 10:02 PM, Marek Vasut wrote:
> On 03/12/2017 01:13 AM, Vikas Manocha wrote:
>> This patch adds armv7m instruction & data cache support.
>>
>> Signed-off-by: Vikas Manocha
>> ---
>>
>> Changed in v2:
>> - changed strucures for memory mapped cache registers to MACROs
>
> Macro is written in lowercase, FYI ...
ok.
>
>> - added lines better readability.
>> - replaced magic numbers with MACROs.
>>
>> arch/arm/cpu/armv7m/Makefile | 2 +-
>> arch/arm/cpu/armv7m/cache.c | 294
>> ++
>> arch/arm/include/asm/armv7m.h | 26 +++-
>> arch/arm/lib/Makefile | 2 +
>> 4 files changed, 321 insertions(+), 3 deletions(-)
>> create mode 100644 arch/arm/cpu/armv7m/cache.c
>>
>> diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
>> index aff60e8..41efe11 100644
>> --- a/arch/arm/cpu/armv7m/Makefile
>> +++ b/arch/arm/cpu/armv7m/Makefile
>> @@ -6,4 +6,4 @@
>> #
>>
>> extra-y := start.o
>> -obj-y += cpu.o
>> +obj-y += cpu.o cache.o
>> diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
>> new file mode 100644
>> index 000..cc17366
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7m/cache.c
>> @@ -0,0 +1,294 @@
>> +/*
>> + * (C) Copyright 2017
>> + * Vikas Manocha, ST Micoelectronics, vikas.mano...@st.com.
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +/* Cache maintenance operation registers */
>> +
>> +#define IC_IALLU0x00
>> +#define INVAL_ICACHE_POU0
>> +
>> +#define IC_IMVALU 0x08
>> +#define DC_IMVAC0x0C
>> +#define DC_ISW 0x10
>> +#define DC_CMVAU0x14
>> +#define DC_CMVAC0x18
>> +#define DC_CSW 0x1C
>> +#define DC_CIMVAC 0x20
>> +#define DC_CISW 0x24
>
> Would be nice to have some more distinguishing name here, so one can
> easily git grep for those reg names and make sense of their name without
> reading the datasheet .
these names are consistent with the arch manual to help relating them with
manual.
>>>
>>> Clearly, I'm not getting through here. Something like CACHE_V7M_REG_FOO
>>> is much easier to grep for than FOO.
>>
>> ok, i will make them V7M_IC_* for instruction cache & V7M_DC_* for data
>> cache specific regs.
>
> Which is still pretty cryptic ...
ok, will make them V7M_CACHE_REG_FOO.
>
>> +#define WAYS_SHIFT 30
>> +#define SETS_SHIFT 5
>
> Is this always 30 and 5 , on all CPUs ?
Yes for all armv7m arch.
>>>
>>> OK
>>>
>> +/* armv7m processor feature registers */
>> +
>> +#define CLIDR 0x00
>> +#define CTR 0x04
>> +
>> +#define CCSIDR 0x08
>> +#define MASK_NUM_WAYS GENMASK(12, 3)
>> +#define MASK_NUM_SETS GENMASK(27, 13)
>> +#define NUM_WAYS_SHIFT 3
>> +#define NUM_SETS_SHIFT 13
>> +
>> +#define CSSELR 0x0C
>> +#define SEL_I_OR_D BIT(0)
>> +
>> +void *const v7m_cache_maint = (void *)V7M_CACHE_MAINT_BASE;
>> +void *const v7m_processor = (void *)V7M_PROC_FTR_BASE;
>
> Needed ? Why don't you just use the macro directly ?
Yes it is possible. I was trying to avoid typecasting macro to pointer
each time before passing to
functions required it as address pointer.
>>>
>>> Eh? This is just a value, you can use it directly ...
>>
>> done in v3, i will send the v4 with rest of the modifications.
>
> Could you give the patch a few days on the list to gather feedback ? I
> believe I warned you about this before already, but the maintainers are
> already saturated by patches, sending one revision after the other does
> NOT help anyone and only congests the maintainers further.
ok.
>
>>> [...]
>>>
>> +debug("cache line size is %d\n", size);
>> +
>> +return size;
>> +}
>> +
>> +int action_cache_range(enum cache_action action, uint32_t start_addr,
>> + int64_t size)
>
> static ?
this function at present is not being used as we are invalidating/flushing
all cache but helper function
to flush/invalidate parts/range of cache.
Making it static leads to "function not used" compilation warning.
attri
[U-Boot] [PATCH 2/3] rockchip: rk3399: spl: add UART0 support for SPL
The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).
To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
iomux setup to the rk3399 SPL code.
As we are already touching this code, we also move the board-specific
UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
is set.
Signed-off-by: Philipp Tomsich
---
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 8 +++
arch/arm/mach-rockchip/rk3399-board-spl.c | 29 ++---
2 files changed, 29 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index 62d8496..4701cfb 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -333,6 +333,14 @@ enum {
GRF_GPIO2B4_SEL_MASK= 3 << GRF_GPIO2B4_SEL_SHIFT,
GRF_SPI2TPM_CSN0= 1,
+ /* GRF_GPIO2C_IOMUX */
+ GRF_GPIO2C0_SEL_SHIFT = 0,
+ GRF_GPIO2C0_SEL_MASK= 3 << GRF_GPIO2C0_SEL_SHIFT,
+ GRF_UART0BT_SIN = 1,
+ GRF_GPIO2C1_SEL_SHIFT = 2,
+ GRF_GPIO2C1_SEL_MASK= 3 << GRF_GPIO2C1_SEL_SHIFT,
+ GRF_UART0BT_SOUT= 1,
+
/* GRF_GPIO3A_IOMUX */
GRF_GPIO3A4_SEL_SHIFT = 8,
GRF_GPIO3A4_SEL_MASK= 3 << GRF_GPIO3A4_SEL_SHIFT,
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c
b/arch/arm/mach-rockchip/rk3399-board-spl.c
index 7b4e0a1..da3e262 100644
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -57,19 +57,22 @@ void secure_timer_init(void)
writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
}
-#define GRF_EMMCCORE_CON11 0xff77f02c
-void board_init_f(ulong dummy)
+void board_debug_uart_init(void)
{
- struct udevice *pinctrl;
- struct udevice *dev;
- int ret;
-
- /* Example code showing how to enable the debug UART on RK3288 */
#include
- /* Enable early UART2 channel C on the RK3399 */
#define GRF_BASE 0xff77
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xFF18)
+ /* Enable early UART0 on the RK3399 */
+ rk_clrsetreg(&grf->gpio2c_iomux,
+GRF_GPIO2C0_SEL_MASK,
+GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio2c_iomux,
+GRF_GPIO2C1_SEL_MASK,
+GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
+#else
+ /* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C3_SEL_MASK,
GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
@@ -80,6 +83,16 @@ void board_init_f(ulong dummy)
rk_clrsetreg(&grf->soc_con7,
GRF_UART_DBG_SEL_MASK,
GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
+#endif
+}
+
+#define GRF_EMMCCORE_CON11 0xff77f02c
+void board_init_f(ulong dummy)
+{
+ struct udevice *pinctrl;
+ struct udevice *dev;
+ int ret;
+
#define EARLY_UART
#ifdef EARLY_UART
/*
--
1.9.1
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[U-Boot] [PATCH 1/3] Kconfig: make CONFIG_BAUDRATE a first-class citizen
Signed-off-by: Philipp Tomsich --- drivers/serial/Kconfig | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index b11f3ff..d570a2b 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -4,6 +4,15 @@ menu "Serial drivers" +config BAUDRATE +int "Default baudrate" + default 115200 + help + Select a default baudrate, where "default" has a driver-specific + meaning of either setting the baudrate for the early debug UART + in the SPL stage (most drivers) or for choosing a default baudrate + in the absence of an environment setting (serial_mxc.c). + config REQUIRE_SERIAL_CONSOLE bool "Require a serial port for console" # Running without a serial console is not supported by the -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/3] rockchip: rk3399: spl: Make baudrate and UART configurable
The default configuration for debug output from the RK3399 SPL is UART2 at 1.5MBaud. While this works reasonably well for the EVB, custom boards may want to change these settings. To simplify the enablement (i.e. to use the RS232 connector on our baseboard and to improve the compatibility with commonly available RS232-to-UART dongles) for the RK3399-Q7 SoM, we need to make both the UART and the baudrate configurable. This patch-series makes CONFIG_BAUDRATE a first-class citizen within the Kconfig framework (so we can set it via defconfig) and adds the required iomux support for UART0 in the RK3399 SPL. Finally, we use the new infrastructure across the RK3399 config files and defconfigs. Philipp Tomsich (3): Kconfig: make CONFIG_BAUDRATE a first-class citizen rockchip: rk3399: spl: add UART0 support for SPL rockchip: config: rk3399: update defconfigs and rk3399_common arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 8 +++ arch/arm/mach-rockchip/rk3399-board-spl.c | 29 ++--- configs/evb-rk3399_defconfig| 2 ++ configs/puma_defconfig | 4 +++- drivers/serial/Kconfig | 9 include/configs/rk3399_common.h | 1 - 6 files changed, 43 insertions(+), 10 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/3] rockchip: config: rk3399: update defconfigs and rk3399_common
With everything set up to define CONFIG_BAUDRATE via defconfig and with to have the SPL debug UART either on UART0 or UART2, the configs for the RK3399 EVB and for the RK3399-Q7 can be updated. Signed-off-by: Philipp Tomsich --- configs/evb-rk3399_defconfig| 2 ++ configs/puma_defconfig | 4 +++- include/configs/rk3399_common.h | 1 - 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 22405ce..7a82869 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -43,7 +43,9 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xFF1A CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/puma_defconfig b/configs/puma_defconfig index 515185e..8e29d96 100644 --- a/configs/puma_defconfig +++ b/configs/puma_defconfig @@ -43,8 +43,10 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=115200 CONFIG_DEBUG_UART=y -CONFIG_DEBUG_UART_BASE=0xFF1A +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xFF18 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index bc91eb6..c1ea616 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -12,7 +12,6 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_SIZE0x2000 #define CONFIG_SYS_MAXARGS 16 -#define CONFIG_BAUDRATE150 #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
