Re: [U-Boot] [PATCH resend v2 00/13] sunxi: Add support for R40 SoC
On Tue, Apr 18, 2017 at 10:20:16AM +0800, Chen-Yu Tsai wrote: > Hi everyone, > > This is a resend of my Allwinner R40 SoC support series v2. > This is rebased on v2017.05-rc2. Maxime's ack for the first > two patches have been added, and the defconfig has been > regenerated which moved the CONFIG_SPL_I2C_SUPPORT=y line > around. > > The patches can also be found here: > > https://github.com/wens/u-boot-sunxi/tree/r40 Merged and pushed. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 00/14] STiH410-B2260: add reset, usb and fastboot support
fyi , a v3 has been send On 03/22/2017 10:54 AM, patrice.chot...@st.com wrote: > From: Patrice Chotard > > This series adds : > _ add reset driver > _ update existing sdhci driver to use reset framework > _ add usb phy driver > _ add ehci support > _ add ohci support > _ add xhci support > _ add fastboot support > > With all this feature enable, it's now possible to > _ boot on usb mass storage device > _ boot from kernel image and dtb previously loaded using tftp > _ update mmc partiton using fastboot > > v2: _ add Reviewed-by: Jaehoon Chung in patches > 2,3 and 4 > _ fix remarks done by Marek Vasut : > _ patch 5 : replace bitfield_replace() by clrsetbits_le32() > _ patch 6 : update error messages and add remove callback > _ patch 8 : put board specific defines in a separate patch > _ patch 7: use setbits_le32() instead of read, modify, write > sequence and add missing parenthesis > _ squash previous patches 7,9,11,12,14,16,17,18,19,20 and 21 > in patch 14 > > Patrice Chotard (14): > reset: Add STi reset support > mmc: sti_sdhci: Rework sti_mmc_core_config() > ARM: dts: stih410-family: Add missing reset_names for mmc1 node > mmc: sti_sdhci: Use reset framework > phy: Add STi phy usb support > usb: ehci: Add STi ehci support > usb: ohci: Add STi ohci support > board: STiH410-B2260: add OHCI related defines > usb: xhci: Add STi xhci support > board: STiH410-B2260: add XHCI related define > usb: dwc3: Add dwc3 support for STi > board: STiH410-B2260: add fastboot support > STiH410-B2260: enable USB Host Networking > STiH410-B2260: enable USB, fastboot, reset related flags > > arch/arm/Kconfig | 1 + > arch/arm/dts/stih407-family.dtsi | 1 + > arch/arm/include/asm/arch-stih410/sys_proto.h | 11 + > board/st/stih410-b2260/board.c| 44 > configs/stih410-b2260_defconfig | 36 ++- > drivers/mmc/sti_sdhci.c | 60 +++-- > drivers/reset/Kconfig | 8 + > drivers/reset/Makefile| 1 + > drivers/reset/sti-reset.c | 320 > ++ > drivers/usb/Kconfig | 4 + > drivers/usb/dwc3/Kconfig | 8 + > drivers/usb/dwc3/Makefile | 1 + > drivers/usb/dwc3/dwc3-sti.c | 135 +++ > drivers/usb/host/Kconfig | 26 +++ > drivers/usb/host/Makefile | 3 + > drivers/usb/host/ehci-sti.c | 115 + > drivers/usb/host/ohci-sti.c | 90 > drivers/usb/host/xhci-sti.c | 156 + > drivers/usb/phy/Kconfig | 11 + > drivers/usb/phy/Makefile | 1 + > drivers/usb/phy/sti_phy_usb.c | 153 > include/configs/stih410-b2260.h | 16 ++ > include/dwc3-sti-uboot.h | 50 > 23 files changed, 1225 insertions(+), 26 deletions(-) > create mode 100644 arch/arm/include/asm/arch-stih410/sys_proto.h > create mode 100644 drivers/reset/sti-reset.c > create mode 100644 drivers/usb/dwc3/dwc3-sti.c > create mode 100644 drivers/usb/host/ehci-sti.c > create mode 100644 drivers/usb/host/ohci-sti.c > create mode 100644 drivers/usb/host/xhci-sti.c > create mode 100644 drivers/usb/phy/Kconfig > create mode 100644 drivers/usb/phy/sti_phy_usb.c > create mode 100644 include/dwc3-sti-uboot.h > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 5/7] rockchip: rk3368: Add initial support for RK3368 based GeekBox
Hi Andreas: On 2017年04月21日 10:59, Andreas Färber wrote: Hi Andy, Sorry for forgetting about this, and thank you for picking it up. Am 21.04.2017 um 04:32 schrieb Andy Yan: From: Andreas Färber The GeekBox is a TV box from GeekBuying, based on an MXM3 module. The module can be used with base boards such as the GeekBox Landingship. This adds basic support to chain-load U-Boot from Rockchip's miniloader. $ ./lollipop_u-boot/tools/loaderimage --pack u-boot.bin u-boot.img Implemented is the serial console, but no boot media drivers yet. Note that flashing the resulting U-Boot will not allow you to enter the rockusb mode any more via "Update" button. Instead, you will need to short two pins on the bottom of the module to enter MaskRom mode and re-flash the loader: ":"? See also below. Signed-off-by: Andreas Färber Signed-off-by: Andy Yan --- arch/arm/dts/Makefile | 2 + arch/arm/dts/rk3368-geekbox.dts | 319 ++ arch/arm/mach-rockchip/rk3368/Kconfig | 11 ++ board/geekbuying/geekbox/Kconfig | 15 ++ board/geekbuying/geekbox/MAINTAINERS | 6 + board/geekbuying/geekbox/Makefile | 7 + board/geekbuying/geekbox/geekbox.c| 28 +++ configs/geekbox_defconfig | 21 +++ include/configs/geekbox.h | 18 ++ 9 files changed, 427 insertions(+) create mode 100644 arch/arm/dts/rk3368-geekbox.dts create mode 100644 board/geekbuying/geekbox/Kconfig create mode 100644 board/geekbuying/geekbox/MAINTAINERS create mode 100644 board/geekbuying/geekbox/Makefile create mode 100644 board/geekbuying/geekbox/geekbox.c create mode 100644 configs/geekbox_defconfig create mode 100644 include/configs/geekbox.h One reason this series stalled is that I was asked to add a README instead of the text in the commit message - this is still missing in your submission, it seems. Thanks for pointing out this, I will add a README in next version. diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ce34e3e..fbc97e8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -41,8 +41,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ rk3328-evb.dtb \ + rk3368-geekbox.dtb \ rk3399-evb.dtb \ rk3399-puma.dtb + rk3368-geekbox.dtb Mismerge. dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-odroidc2.dtb [snip] Regards, Andreas ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] AM335x Falcon Mode
Hello Ayoub,
Am 20.04.2017 um 16:35 schrieb ayoub.z...@embexus.com:
Hi Andy,
Thanks for the answer, I figured out what the problem is, in the fact I was
using a zImage, using an uImage format solve the problem :-)
It should maybe added to the documentation ;-)
Patches are welcome!
;-)
bye,
Heiko
best regards,
Ayoub Zaki
On 20 April 2017 at 16:31:21 +02:00, Andy Pont wrote:
Ayoub wrote...
=> run args_mmc
=> run loadimage
8942296 bytes read in 610 ms (14 MiB/s)
=> run loadfdt
58129 bytes read in 56 ms (1013.7 KiB/s)
=> spl export fdt ${loadaddr} - ${fdtaddr}
I have AM335x Falcon mode running with SPI flash (albeit an old 2014.xx U-Boot
version) and the commands for settings it up look the same as the ones you have
used.
Do you get any more information about where the data abort is coming from if
you build and run U-Boot with #define DEBUG?
-Andy.
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Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released
Am 21.04.2017 um 01:23 schrieb Andreas Färber: > Hi, > > Using -rc2 with firefly-rk3288 defconfig I can only boot into SPL but > not into full U-Boot. I am using the old documented way of dd'ing to > sector 256 on SD (doc/README.rockchip). > > Looking at include/configs/rk3288_common.h I also tried putting > u-boot.img on a FAT partition, to no effect. > > v2017.03 doesn't even show SPL working. > v2017.01 worked okay. Cutting a long thread short: U-Boot can only handle either BROM-style booting or SPL-style booting. Since v2017.03 booting defaults to BROM, which requires u-boot.bin immediately after the rksd, as opposed to u-boot.img at sector 256 as before. That works for -rc2, but still leaves v2017.03 without serial output. Regards, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/8] drivers: i2c: davinci_i2c: Convert driver to DM
Hi Franklin, On Thursday 20 April 2017 08:55 PM, Franklin S Cooper Jr wrote: > This patch series converts the davinci i2c driver to use device model. > This updated driver has been verified on both Keystone K2G and Keystone > K2L evms by performing several i2c operations in U-boot prompt. > > Some additional work was required to get things working on K2G due to > the code that reads the on board EEPROM. DM I2C sets the default address > length to a default value of 1 when the on EEPROM requires an address > length of 2. Therefore, an additional function and minor changes were > required to get things working properly. > You can add property: u-boot,i2c-offset-len = <2>; to the i2c slave DT node help to achieve this, right? Have you tried this option? -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] Add Basic support for RK808
ok - -wrong title.. It's Add Basic support for RK818 2017-04-21 11:34 GMT+08:00 Jacob Chen : > > The RK818 chip is a power management IC for multimedia and handheld > devices. It contains the following components: > > - Regulators > - RTC > - Clkout > - battery support > > This series patch just give it a basic support, to make rk818 board work. > > > Jacob Chen (4): > power: pmic: append rk818 regs to rk808 > power: pmic: rk808: add RK818 support > power: regulator: rk808: replace vsel_bits with vsel_mask > power: regulator: rk808: add rk818 support > > drivers/power/pmic/rk808.c | 29 +++ > drivers/power/regulator/rk808.c | 96 +- > include/power/rk808_pmic.h | 176 > +--- > 3 files changed, 249 insertions(+), 52 deletions(-) > > -- > 2.7.4 > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/4] power: regulator: rk808: add rk818 support
Add support for the rk818 regulator. The regulator module consists
of 4 DCDCs, 9 LDOs, 1 switch and 1 BOOST converter which is used to
power OTG and HDMI5V.
TODO: I don't know how to deal with BOOST and LDO9,
so just ignore them now.
Signed-off-by: Jacob Chen
---
drivers/power/regulator/rk808.c | 55 ++---
1 file changed, 51 insertions(+), 4 deletions(-)
diff --git a/drivers/power/regulator/rk808.c b/drivers/power/regulator/rk808.c
index 441806c..71ab76e 100644
--- a/drivers/power/regulator/rk808.c
+++ b/drivers/power/regulator/rk808.c
@@ -25,6 +25,12 @@
#define RK808_BUCK4_VSEL_MASK 0xf
#define RK808_LDO_VSEL_MASK0x1f
+#define RK818_BUCK_VSEL_MASK 0x3f
+#define RK818_BUCK4_VSEL_MASK 0x1f
+#define RK818_LDO_VSEL_MASK0x1f
+#define RK818_LDO3_ON_VSEL_MASK0xf
+#define RK818_BOOST_ON_VSEL_MASK 0xe0
+
struct rk808_reg_info {
uint min_uv;
uint step_uv;
@@ -50,10 +56,51 @@ static const struct rk808_reg_info rk808_ldo[] = {
{ 180, 10, REG_LDO8_ON_VSEL, RK808_LDO_VSEL_MASK, },
};
+static const struct rk808_reg_info rk818_buck[] = {
+ { 712500, 12500, REG_BUCK1_ON_VSEL, RK818_BUCK_VSEL_MASK, },
+ { 712500, 12500, REG_BUCK2_ON_VSEL, RK818_BUCK_VSEL_MASK, },
+ { 712500, 12500, -1, RK818_BUCK_VSEL_MASK, },
+ { 180, 10, REG_BUCK4_ON_VSEL, RK818_BUCK4_VSEL_MASK, },
+};
+
+static const struct rk808_reg_info rk818_ldo[] = {
+ { 180, 10, REG_LDO1_ON_VSEL, RK818_LDO_VSEL_MASK, },
+ { 180, 10, REG_LDO2_ON_VSEL, RK818_LDO_VSEL_MASK, },
+ { 80, 10, REG_LDO3_ON_VSEL, RK818_LDO3_ON_VSEL_MASK, },
+ { 180, 10, REG_LDO4_ON_VSEL, RK818_LDO_VSEL_MASK, },
+ { 180, 10, REG_LDO5_ON_VSEL, RK818_LDO_VSEL_MASK, },
+ { 80, 10, REG_LDO6_ON_VSEL, RK818_LDO_VSEL_MASK, },
+ { 80, 10, REG_LDO7_ON_VSEL, RK818_LDO_VSEL_MASK, },
+ { 180, 10, REG_LDO8_ON_VSEL, RK818_LDO_VSEL_MASK, },
+};
+
+static const struct rk808_reg_info *get_buck_reg(struct udevice *pmic,
+int num)
+{
+ struct rk808_priv *rk808 = dev_get_priv(pmic);
+ switch (rk808->variant) {
+ case RK818_ID:
+ return &rk818_buck[num];
+ default:
+ return &rk808_buck[num];
+ }
+}
+
+static const struct rk808_reg_info *get_ldo_reg(struct udevice *pmic,
+int num)
+{
+ struct rk808_priv *rk808 = dev_get_priv(pmic);
+ switch (rk808->variant) {
+ case RK818_ID:
+ return &rk818_ldo[num - 1];
+ default:
+ return &rk808_ldo[num - 1];
+ }
+}
static int _buck_set_value(struct udevice *pmic, int buck, int uvolt)
{
- const struct rk808_reg_info *info = &rk808_buck[buck - 1];
+ const struct rk808_reg_info *info = get_buck_reg(pmic, buck - 1);
int mask = info->vsel_mask;
int val;
@@ -89,7 +136,7 @@ static int _buck_set_enable(struct udevice *pmic, int buck,
bool enable)
static int buck_get_value(struct udevice *dev)
{
int buck = dev->driver_data - 1;
- const struct rk808_reg_info *info = &rk808_buck[buck];
+ const struct rk808_reg_info *info = get_buck_reg(dev->parent, buck);
int mask = info->vsel_mask;
int ret, val;
@@ -135,7 +182,7 @@ static bool buck_get_enable(struct udevice *dev)
static int ldo_get_value(struct udevice *dev)
{
int ldo = dev->driver_data - 1;
- const struct rk808_reg_info *info = &rk808_ldo[ldo];
+ const struct rk808_reg_info *info = get_ldo_reg(dev->parent, ldo);
int mask = info->vsel_mask;
int ret, val;
@@ -152,7 +199,7 @@ static int ldo_get_value(struct udevice *dev)
static int ldo_set_value(struct udevice *dev, int uvolt)
{
int ldo = dev->driver_data - 1;
- const struct rk808_reg_info *info = &rk808_ldo[ldo];
+ const struct rk808_reg_info *info = get_ldo_reg(dev->parent, ldo);
int mask = info->vsel_mask;
int val;
--
2.7.4
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[U-Boot] [PATCH 2/4] power: pmic: rk808: add RK818 support
The RK818 chip is a Power Management IC (PMIC) for multimedia and handheld
devices.
For boards use rk818, the input current should be set in the early stage, before
ddr initialization.
To use rk818,below configs should be enabled:
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
and rk818 device should probe in spl board_init_f.
Signed-off-by: Jacob Chen
---
drivers/power/pmic/rk808.c | 29 +
include/power/rk808_pmic.h | 12
2 files changed, 41 insertions(+)
diff --git a/drivers/power/pmic/rk808.c b/drivers/power/pmic/rk808.c
index 3f5f316..2d764d9 100644
--- a/drivers/power/pmic/rk808.c
+++ b/drivers/power/pmic/rk808.c
@@ -80,6 +80,33 @@ static int rk808_bind(struct udevice *dev)
}
#endif
+static int rk808_probe(struct udevice *dev)
+{
+ struct rk808_priv *priv = dev_get_priv(dev);
+ uint8_t msb, lsb;
+
+ /* read Chip variant */
+ rk808_read(dev, ID_MSB, &msb, 1);
+ rk808_read(dev, ID_LSB, &lsb, 1);
+
+ priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
+
+#ifdef CONFIG_SPL_BUILD
+ if (priv->variant == RK818_ID) {
+ uint8_t txdata;
+ /*
+* Increase USB input current selection to 2A and close charger
+* when usb lower then 3.4V.
+*/
+ txdata = 0x77;
+ rk808_write(dev, REG_USB_CTRL, &txdata, 1);
+ udelay(3);
+ }
+#endif
+
+ return 0;
+}
+
static struct dm_pmic_ops rk808_ops = {
.reg_count = rk808_reg_count,
.read = rk808_read,
@@ -88,6 +115,7 @@ static struct dm_pmic_ops rk808_ops = {
static const struct udevice_id rk808_ids[] = {
{ .compatible = "rockchip,rk808" },
+ { .compatible = "rockchip,rk818" },
{ }
};
@@ -98,5 +126,6 @@ U_BOOT_DRIVER(pmic_rk808) = {
#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
.bind = rk808_bind,
#endif
+ .probe = rk808_probe,
.ops = &rk808_ops,
};
diff --git a/include/power/rk808_pmic.h b/include/power/rk808_pmic.h
index d29c2b3..c370c32 100644
--- a/include/power/rk808_pmic.h
+++ b/include/power/rk808_pmic.h
@@ -170,12 +170,24 @@ enum {
RK808_NUM_OF_REGS,
};
+enum {
+ RK805_ID = 0x8050,
+ RK808_ID = 0x,
+ RK818_ID = 0x8180,
+};
+
+#define RK8XX_ID_MSK 0xfff0
+
struct rk808_reg_table {
char *name;
u8 reg_ctl;
u8 reg_vol;
};
+struct rk808_priv {
+ int variant;
+};
+
int rk808_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
#endif
--
2.7.4
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[U-Boot] [PATCH 1/4] power: pmic: append rk818 regs to rk808
Both RK808 and RK818 chips are using a similar register map,
so we can reuse them.
I have also add reg prefix to exist registers, to keep them same style.
Signed-off-by: Jacob Chen
---
drivers/power/regulator/rk808.c | 18 ++---
include/power/rk808_pmic.h | 164
2 files changed, 143 insertions(+), 39 deletions(-)
diff --git a/drivers/power/regulator/rk808.c b/drivers/power/regulator/rk808.c
index adef8f5..f1a00c5 100644
--- a/drivers/power/regulator/rk808.c
+++ b/drivers/power/regulator/rk808.c
@@ -35,14 +35,14 @@ static const struct rk808_reg_info rk808_buck[] = {
};
static const struct rk808_reg_info rk808_ldo[] = {
- { 180, 10, LDO1_ON_VSEL, 5, },
- { 180, 10, LDO2_ON_VSEL, 5, },
- { 80, 10, LDO3_ON_VSEL, 4, },
- { 180, 10, LDO4_ON_VSEL, 5, },
- { 180, 10, LDO5_ON_VSEL, 5, },
- { 80, 10, LDO6_ON_VSEL, 5, },
- { 80, 10, LDO7_ON_VSEL, 5, },
- { 180, 10, LDO8_ON_VSEL, 5, },
+ { 180, 10, REG_LDO1_ON_VSEL, 5, },
+ { 180, 10, REG_LDO2_ON_VSEL, 5, },
+ { 80, 10, REG_LDO3_ON_VSEL, 4, },
+ { 180, 10, REG_LDO4_ON_VSEL, 5, },
+ { 180, 10, REG_LDO5_ON_VSEL, 5, },
+ { 80, 10, REG_LDO6_ON_VSEL, 5, },
+ { 80, 10, REG_LDO7_ON_VSEL, 5, },
+ { 180, 10, REG_LDO8_ON_VSEL, 5, },
};
@@ -69,7 +69,7 @@ static int _buck_set_enable(struct udevice *pmic, int buck,
bool enable)
buck--;
mask = 1 << buck;
if (enable) {
- ret = pmic_clrsetbits(pmic, DCDC_ILMAX, 0, 3 << (buck * 2));
+ ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX, 0, 3 << (buck * 2));
if (ret)
return ret;
ret = pmic_clrsetbits(pmic, REG_DCDC_UV_ACT, 1 << buck, 0);
diff --git a/include/power/rk808_pmic.h b/include/power/rk808_pmic.h
index fb0800b..d29c2b3 100644
--- a/include/power/rk808_pmic.h
+++ b/include/power/rk808_pmic.h
@@ -9,12 +9,37 @@
#define _PMIC_RK808_H_
enum {
- REG_DCDC_EN = 0x23,
+ REG_SECONDS = 0x00,
+ REG_MINUTES,
+ REG_HOURS,
+ REG_DAYS,
+ REG_MONTHS,
+ REG_YEARS,
+ REG_WEEKS,
+ REG_ALARM_SECONDS,
+ REG_ALARM_MINUTES,
+ REG_ALARM_HOURS,
+ REG_ALARM_DAYS,
+ REG_ALARM_MONTHS,
+ REG_ALARM_YEARS,
+
+ REG_RTC_CTRL= 0x10,
+ REG_RTC_STATUS,
+ REG_RTC_INT,
+ REG_RTC_COMP_LSB,
+ REG_RTC_COMP_MSB,
+
+ ID_MSB = 0x17,
+ ID_LSB,
+
+ REG_CLK32OUT= 0x20,
+ REG_VB_MON,
+ REG_THERMAL,
+ REG_DCDC_EN,
REG_LDO_EN,
REG_SLEEP_SET_OFF1,
REG_SLEEP_SET_OFF2,
REG_DCDC_UV_STS,
-
REG_DCDC_UV_ACT,
REG_LDO_UV_STS,
REG_LDO_UV_ACT,
@@ -23,7 +48,6 @@ enum {
REG_VOUT_MON_TDB,
REG_BUCK1_CONFIG,
REG_BUCK1_ON_VSEL,
-
REG_BUCK1_SLP_VSEL,
REG_BUCK1_DVS_VSEL,
REG_BUCK2_CONFIG,
@@ -32,37 +56,117 @@ enum {
REG_BUCK2_DVS_VSEL,
REG_BUCK3_CONFIG,
REG_BUCK4_CONFIG,
-
REG_BUCK4_ON_VSEL,
REG_BUCK4_SLP_VSEL,
- LDO1_ON_VSEL= 0x3b,
- LDO1_SLP_VSEL,
- LDO2_ON_VSEL,
- LDO2_SLP_VSEL,
- LDO3_ON_VSEL,
-
- LDO3_SLP_VSEL,
- LDO4_ON_VSEL,
- LDO4_SLP_VSEL,
- LDO5_ON_VSEL,
- LDO5_SLP_VSEL,
- LDO6_ON_VSEL,
- LDO6_SLP_VSEL,
- LDO7_ON_VSEL,
-
- LDO7_SLP_VSEL,
- LDO8_ON_VSEL,
- LDO8_SLP_VSEL,
- DEVCTRL,
- INT_STS1,
- INT_STS_MSK1,
- INT_STS2,
- INT_STS_MSK2,
- IO_POL,
+ REG_BOOST_CONFIG_REG,
+ REG_LDO1_ON_VSEL,
+ REG_LDO1_SLP_VSEL,
+ REG_LDO2_ON_VSEL,
+ REG_LDO2_SLP_VSEL,
+ REG_LDO3_ON_VSEL,
+ REG_LDO3_SLP_VSEL,
+ REG_LDO4_ON_VSEL,
+ REG_LDO4_SLP_VSEL,
+ REG_LDO5_ON_VSEL,
+ REG_LDO5_SLP_VSEL,
+ REG_LDO6_ON_VSEL,
+ REG_LDO6_SLP_VSEL,
+ REG_LDO7_ON_VSEL,
+ REG_LDO7_SLP_VSEL,
+ REG_LDO8_ON_VSEL,
+ REG_LDO8_SLP_VSEL,
+ REG_DEVCTRL,
+ REG_INT_STS1,
+ REG_INT_STS_MSK1,
+ REG_INT_STS2,
+ REG_INT_STS_MSK2,
+ REG_IO_POL,
+ REG_OTP_VDD_EN,
+ REG_H5V_EN,
+ REG_SLEEP_SET_OFF,
+ REG_BOOST_LDO9_ON_VSEL,
+ REG_BOOST_LDO9_SLP_VSEL,
+ REG_BOOST_CTRL,
/* Not sure what this does */
- DCDC_ILMAX = 0x90,
-
+ REG_DCDC_ILMAX = 0x90,
+ REG_CHRG_COMP = 0x9a,
+ REG_SUP_STS = 0xa0,
+ REG_USB_CTRL,
+ REG1_CHRG_CTRL,
+ REG2_CHRG_CTRL,
+ REG3_CHRG_CTRL,
+ REG_BAT_CTRL,
+ REG_BAT_HTS_TS1,
+ REG_
[U-Boot] [PATCH 3/4] power: regulator: rk808: replace vsel_bits with vsel_mask
Using mask is more flexible than bits.
Signed-off-by: Jacob Chen
---
drivers/power/regulator/rk808.c | 39 ++-
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/power/regulator/rk808.c b/drivers/power/regulator/rk808.c
index f1a00c5..441806c 100644
--- a/drivers/power/regulator/rk808.c
+++ b/drivers/power/regulator/rk808.c
@@ -20,36 +20,41 @@
#define ENABLE_DRIVER
#endif
+/* Field Definitions */
+#define RK808_BUCK_VSEL_MASK 0x3f
+#define RK808_BUCK4_VSEL_MASK 0xf
+#define RK808_LDO_VSEL_MASK0x1f
+
struct rk808_reg_info {
uint min_uv;
uint step_uv;
s8 vsel_reg;
- u8 vsel_bits;
+ u8 vsel_mask;
};
static const struct rk808_reg_info rk808_buck[] = {
- { 712500, 12500, REG_BUCK1_ON_VSEL, 6, },
- { 712500, 12500, REG_BUCK2_ON_VSEL, 6, },
- { 712500, 12500, -1, 6, },
- { 180, 10, REG_BUCK4_ON_VSEL, 4, },
+ { 712500, 12500, REG_BUCK1_ON_VSEL, RK808_BUCK_VSEL_MASK, },
+ { 712500, 12500, REG_BUCK2_ON_VSEL, RK808_BUCK_VSEL_MASK, },
+ { 712500, 12500, -1, RK808_BUCK_VSEL_MASK, },
+ { 180, 10, REG_BUCK4_ON_VSEL, RK808_BUCK4_VSEL_MASK, },
};
static const struct rk808_reg_info rk808_ldo[] = {
- { 180, 10, REG_LDO1_ON_VSEL, 5, },
- { 180, 10, REG_LDO2_ON_VSEL, 5, },
- { 80, 10, REG_LDO3_ON_VSEL, 4, },
- { 180, 10, REG_LDO4_ON_VSEL, 5, },
- { 180, 10, REG_LDO5_ON_VSEL, 5, },
- { 80, 10, REG_LDO6_ON_VSEL, 5, },
- { 80, 10, REG_LDO7_ON_VSEL, 5, },
- { 180, 10, REG_LDO8_ON_VSEL, 5, },
+ { 180, 10, REG_LDO1_ON_VSEL, RK808_LDO_VSEL_MASK, },
+ { 180, 10, REG_LDO2_ON_VSEL, RK808_LDO_VSEL_MASK, },
+ { 80, 10, REG_LDO3_ON_VSEL, RK808_BUCK4_VSEL_MASK, },
+ { 180, 10, REG_LDO4_ON_VSEL, RK808_LDO_VSEL_MASK, },
+ { 180, 10, REG_LDO5_ON_VSEL, RK808_LDO_VSEL_MASK, },
+ { 80, 10, REG_LDO6_ON_VSEL, RK808_LDO_VSEL_MASK, },
+ { 80, 10, REG_LDO7_ON_VSEL, RK808_LDO_VSEL_MASK, },
+ { 180, 10, REG_LDO8_ON_VSEL, RK808_LDO_VSEL_MASK, },
};
static int _buck_set_value(struct udevice *pmic, int buck, int uvolt)
{
const struct rk808_reg_info *info = &rk808_buck[buck - 1];
- int mask = (1 << info->vsel_bits) - 1;
+ int mask = info->vsel_mask;
int val;
if (info->vsel_reg == -1)
@@ -85,7 +90,7 @@ static int buck_get_value(struct udevice *dev)
{
int buck = dev->driver_data - 1;
const struct rk808_reg_info *info = &rk808_buck[buck];
- int mask = (1 << info->vsel_bits) - 1;
+ int mask = info->vsel_mask;
int ret, val;
if (info->vsel_reg == -1)
@@ -131,7 +136,7 @@ static int ldo_get_value(struct udevice *dev)
{
int ldo = dev->driver_data - 1;
const struct rk808_reg_info *info = &rk808_ldo[ldo];
- int mask = (1 << info->vsel_bits) - 1;
+ int mask = info->vsel_mask;
int ret, val;
if (info->vsel_reg == -1)
@@ -148,7 +153,7 @@ static int ldo_set_value(struct udevice *dev, int uvolt)
{
int ldo = dev->driver_data - 1;
const struct rk808_reg_info *info = &rk808_ldo[ldo];
- int mask = (1 << info->vsel_bits) - 1;
+ int mask = info->vsel_mask;
int val;
if (info->vsel_reg == -1)
--
2.7.4
___
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https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/4] Add Basic support for RK808
The RK818 chip is a power management IC for multimedia and handheld devices. It contains the following components: - Regulators - RTC - Clkout - battery support This series patch just give it a basic support, to make rk818 board work. Jacob Chen (4): power: pmic: append rk818 regs to rk808 power: pmic: rk808: add RK818 support power: regulator: rk808: replace vsel_bits with vsel_mask power: regulator: rk808: add rk818 support drivers/power/pmic/rk808.c | 29 +++ drivers/power/regulator/rk808.c | 96 +- include/power/rk808_pmic.h | 176 +--- 3 files changed, 249 insertions(+), 52 deletions(-) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC,v2 2/2] NVMe: add nvme commands
Add nvme commands in U-Boot command line.
1. "nvme list" - show all available NVMe blk devices
2. "nvme info" - show current or a specific NVMe blk device
3. "nvme device" - show or set current device
4. "nvme part" - print partition table
5. "nvme read" - read data from NVMe blk device
6. "nvme write" - write data to NVMe blk device
Signed-off-by: Zhikang Zhang
Signed-off-by: Wenbin Song
---
Changes for v2:
- remove the calling of "initialie" in fuction "do_nvmecops"
- change the function "do_nvme_info" to support BLK uclass
---
cmd/Kconfig | 9 +++
cmd/Makefile| 1 +
cmd/nvme.c | 173
disk/part.c | 6 ++
doc/README.nvme | 54 ++
5 files changed, 243 insertions(+)
create mode 100644 cmd/nvme.c
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 13dc46a..e30814b 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -502,6 +502,15 @@ config CMD_USB
help
USB support.
+config CMD_NVME
+ bool "NVMe"
+ depends on NVME
+ help
+ NVMe support.
+ This enables nvme commands in command line
+ You can use comamnd "nvme" to show what commands it supports
+ such as "nvme info" "nvme list".
+
config CMD_DFU
bool "dfu"
select USB_FUNCTION_DFU
diff --git a/cmd/Makefile b/cmd/Makefile
index 97c862f..941100e 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -111,6 +111,7 @@ obj-$(CONFIG_CMD_REISER) += reiser.o
obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o
obj-$(CONFIG_SANDBOX) += host.o
obj-$(CONFIG_CMD_SATA) += sata.o
+obj-$(CONFIG_CMD_NVME) += nvme.o
obj-$(CONFIG_CMD_SF) += sf.o
obj-$(CONFIG_SCSI) += scsi.o disk.o
obj-$(CONFIG_CMD_SHA1SUM) += sha1sum.o
diff --git a/cmd/nvme.c b/cmd/nvme.c
new file mode 100644
index 000..8dc1f14
--- /dev/null
+++ b/cmd/nvme.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2017 NXP Semiconductors
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static int nvme_curr_device;
+
+static int do_nvme_list(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ blk_list_devices(IF_TYPE_NVME);
+ return CMD_RET_SUCCESS;
+}
+
+static int do_nvme_info(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int devnum;
+ struct udevice *udev;
+ int ret;
+ if (argc > 1)
+ devnum = (int)simple_strtoul(argv[1], NULL, 10);
+ else
+ devnum = nvme_curr_device;
+ ret = blk_get_device(IF_TYPE_NVME, devnum, &udev);
+ if (ret < 0)
+ return ret;
+
+ nvme_print_info(udev);
+ return CMD_RET_SUCCESS;
+}
+
+static int do_nvme_device(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ if (argc > 1) {
+ int devnum = (int)simple_strtoul(argv[1], NULL, 10);
+ if (!blk_show_device(IF_TYPE_NVME, devnum)) {
+ nvme_curr_device = devnum;
+ printf("... is now current device\n");
+ } else {
+ return CMD_RET_FAILURE;
+ }
+ } else {
+ blk_show_device(IF_TYPE_NVME, nvme_curr_device);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_nvme_part(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ if (argc > 1) {
+ int devnum = (int)simple_strtoul(argv[2], NULL, 10);
+ if (blk_print_part_devnum(IF_TYPE_NVME, devnum)) {
+ printf("\nNVME device %d not available\n", devnum);
+ return CMD_RET_FAILURE;
+ }
+ } else {
+ blk_print_part_devnum(IF_TYPE_NVME, nvme_curr_device);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_nvme_read(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ unsigned long time;
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ ulong addr = simple_strtoul(argv[1], NULL, 16);
+ ulong cnt = simple_strtoul(argv[3], NULL, 16);
+ ulong n;
+ lbaint_t blk = simple_strtoul(argv[2], NULL, 16);
+
+ printf("\nNVME read: device %d block # %ld, count %ld ... ",
+ nvme_curr_device, blk, cnt);
+
+ time = get_timer(0);
+ n = blk_read_devnum(IF_TYPE_NVME, nvme_curr_device, blk,
+ cnt, (ulong *)addr);
+ time = get_timer(time);
+
+ printf("read: %s\n", (n == cnt) ? "OK" : "ERROR");
+ printf("%lu bytes read in %lu ms", cnt * 512, time);
+ if (time > 0) {
+ puts(" (");
+ print_size(div_u64(cnt * 512, time) * 1000, "/s");
+ puts(")");
+ }
+ puts("\n");
+ return (n == cnt) ? 0 : 1;
+}
+
+static int do_nvme_write(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+
[U-Boot] [RFC,v2 1/2] NVMe: add NVMe driver support
Add Support of devices that follow the NVM Express standard
basic functions: nvme Read/Write
Signed-off-by: Zhikang Zhang
Signed-off-by: Wenbin Song
---
Changes for v2:
- add UCLASS_NVME (drivers/block/nvme-uclasss.c)
- remove the support of non-BLK
- remove common/nvme.c
---
common/board_r.c| 13 +
doc/README.nvme | 30 ++
drivers/block/Kconfig | 8 +
drivers/block/Makefile | 2 +
drivers/block/blk-uclass.c | 3 +-
drivers/block/nvme-uclass.c | 64 +++
drivers/block/nvme.c| 966
drivers/block/nvme.h| 133 ++
drivers/block/nvme_uapi.h | 574 ++
include/blk.h | 1 +
include/dm/uclass-id.h | 1 +
include/nvme.h | 12 +
12 files changed, 1806 insertions(+), 1 deletion(-)
create mode 100644 doc/README.nvme
create mode 100644 drivers/block/nvme-uclass.c
create mode 100644 drivers/block/nvme.c
create mode 100644 drivers/block/nvme.h
create mode 100644 drivers/block/nvme_uapi.h
create mode 100644 include/nvme.h
diff --git a/common/board_r.c b/common/board_r.c
index d69a33c..d25b8e8 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -44,6 +44,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -450,6 +451,15 @@ static int initr_dataflash(void)
}
#endif
+#ifdef CONFIG_NVME
+static int initr_nvme(void)
+{
+ puts("NVMe: ");
+ nvme_initialize();
+ return 0;
+}
+#endif
+
/*
* Tell if it's OK to load the environment early in boot.
*
@@ -912,6 +922,9 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_PS2KBD
initr_kbd,
#endif
+#ifdef CONFIG_NVME
+ initr_nvme,
+#endif
run_main_loop,
};
diff --git a/doc/README.nvme b/doc/README.nvme
new file mode 100644
index 000..b429715
--- /dev/null
+++ b/doc/README.nvme
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 NXP Semiconductors
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+NVMe NVM Express (NVMe) is a register level interface that allows
+ host software to communicate with a non-volatile memory
subsystem.
+ This interface is optimized for Enterprise and Client solid
state drives,
+ typically attached to the PCI Express interface.
+
+namespace A quantity of non-volatile memory that be formatted into
logical blocks.
+ An NVM Express namespace is equivalent to a SCSI LUN
+ Each namespace is operated as an independent "device".
+
+How it works:
+-
+First, the NVMe controller("nvme"), which based on UCLASS_NVME,
+should be bind throuth PCIe DM driver.
+Then, we can scan the namespaces(based on UCLASS_BLK) in the controller,
+and bind/probe namespace as a standard Block device through BLK DM driver.
+
+Basic functions:
+
+It only support basic Read/Write functions in the driver.
+You can also get/set other features through standard commands.
+
+NVMe Config Switches:
+-
+CONFIG_NVMEenables basic NVMe device support
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 88e66e2..07d84bb 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -49,3 +49,11 @@ config SATA_CEVA
AHCI 1.3 specifications with hot-plug detect feature.
endmenu
+
+config NVME
+ bool "Support NVMe devices"
+ depends on BLK
+ depends on PCI
+ help
+ This option enables supporting for NVMe devices.
+ It supports basic functions of NVMe(read/write).
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index f415b33..c449391 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -30,3 +30,5 @@ obj-$(CONFIG_SANDBOX) += sandbox.o sandbox_scsi.o
sata_sandbox.o
obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
obj-$(CONFIG_SYSTEMACE) += systemace.o
obj-$(CONFIG_BLOCK_CACHE) += blkcache.o
+obj-$(CONFIG_NVME) += nvme.o
+obj-$(CONFIG_NVME) += nvme-uclass.o
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index af3c35f..1af764d 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -4,7 +4,6 @@
*
* SPDX-License-Identifier:GPL-2.0+
*/
-
#include
#include
#include
@@ -22,6 +21,7 @@ static const char *if_typename_str[IF_TYPE_COUNT] = {
[IF_TYPE_SATA] = "sata",
[IF_TYPE_HOST] = "host",
[IF_TYPE_SYSTEMACE] = "ace",
+ [IF_TYPE_NVME] = "nvme",
};
static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = {
@@ -34,6 +34,7 @@ static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = {
[IF_TYPE_SD]= UCLASS_INVALID,
[IF_TYPE_SATA] = UCLASS_AHCI,
[IF_TYPE_HOST] = UCLASS_ROOT,
+ [IF_TYPE_NVME] = UCLASS_NVME,
[IF_TYPE_SYSTEMACE] = UCLASS_INVALID,
};
diff --git a/drivers/block/nvme-uclass.c b/driv
[U-Boot] (no subject)
Test for NVMe driver: platform: LS1046AQDS NVMe SSD: Intel P3700 400G The test logs are as follow: => nvme list Device 0: Vendor: 0x8086 Rev: 8DV10131 Prod: CVFT535600LS400BGN Type: Hard Disk Capacity: 381554.0 MB = 372.6 GB (781422768 x 512) => nvme device 0 Device 0: Vendor: 0x8086 Rev: 8DV10131 Prod: CVFT535600LS400BGN Type: Hard Disk Capacity: 381554.0 MB = 372.6 GB (781422768 x 512) ... is now current device => nvme info Blk device 0: Optional Admin Command Support: Namespace Management/Attachment: no Firmware Commit/Image download: yes Format NVM: yes Security Send/Receive: no Blk device 0: Optional NVM Command Support: Reservation: no Save/Select field in the Set/Get features: no Write Zeroes: yes Dataset Management: yes Write Uncorrectable: no Blk device 0: Format NVM Attributes: Support Cryptographic Erase: yes Support erase a particular namespace: No Support format a particular namespace: No Blk device 0: LBA Format Support: LBA Foramt 0 Support: (current) Metadata Size: 0 LBA Data Size: 512 Relative Performance: Good LBA Foramt 1 Support: Metadata Size: 8 LBA Data Size: 512 Relative Performance: Good LBA Foramt 2 Support: Metadata Size: 16 LBA Data Size: 512 Relative Performance: Good LBA Foramt 3 Support: Metadata Size: 0 LBA Data Size: 4096 Relative Performance: Best LBA Foramt 4 Support: Metadata Size: 8 LBA Data Size: 4096 Relative Performance: Best LBA Foramt 5 Support: Metadata Size: 64 LBA Data Size: 4096 Relative Performance: Best Blk device 0: End-to-End DataProtect Capabilities: As last eight bytes: yes As first eight bytes: No Support Type3: No Support Type2: No Support Type1: yes Blk device 0: Metadata capabilities: As part of a separate buffer: No As part of an extended data LBA: yes => nvme part Partition Map for UNKNOWN device 0 -- Partition Type: DOS PartStart SectorNum Sectors UUIDType 1 20482048000 ffc18949-01 83 => nvme read 9000 0 10 NVME read: device 0 block # 0, count 1048576 ... read: OK 536870912 bytes read in 1086 ms (471.5 MiB/s) => nvme write 9000 0 10 NVME write: device 0 block # 0, count 1048576 ... write: OK 536870912 bytes read in 1070 ms (478.5 MiB/s) => fatls nvme 0 32376967 kernel.itb 22929408 100m 2 file(s), 0 dir(s) => fatload nvme 0 9000 kernel.itb reading kernel.itb 32376967 bytes read in 128 ms (241.2 MiB/s) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 00/11] Add mipi dsi display support for rockchip soc.
Hi Eric, On 19 April 2017 at 22:45, Eric Gao wrote: > Add mipi dsi display support for rockchip soc. > > Changes in v4: > -Clear irrelevant change > -Clear irrelevant change. > -Move this patch to an early stage. > > Changes in v3: > -Split GRF changes as a single patch > -Split mipi dsi driver file and header as a single patch. > -Split Makefile changes to a single patch. > -Split Kconfig changes to a single patch. > -Improve indentation relationship > -Add more description in the commit message > -Add ret value in debug message. > > Changes in v2: > -Fix rk_display_init() function report error(err:-19). > -Add mipi display mode for vop. > -Add compatible items for rk3399 vop. > -Change the bitwidth for different display mode. > -Extend frame buffer size for mipi display > -Add pwm0 pinctrl init for lcd backlight. > -Add dts config for mipi display. > -Add defconfigs for mipi display, so that it can be enabled by default. > > Eric Gao (11): > rockchip: include: grf: Add GRF register declaration for mipi dsi > rockchip: video: Add mipi driver for rockchip soc > rockchip: video: Makefile: Add mipi driver addition. > rockchip: video: Kconfig: Add mipi driver addition. > rockchip: video: vop: Fix rk_display_init() return error > rockchip: video: vop: Add mipi display mode for rk3399 > rockchip: video: vop: Set different bitwidth for different display > mode > rockchip: video: vop: Reserve enough space for mipi dispaly > rockchip: board: evb_rk3399: initialize pwm0 for dispaly backlight > rockchip: dts: Add mipi dsi support for rk3399 > rockchip: configs: Enable mipi dsi for rk3399 > > arch/arm/dts/rk3399-evb.dts| 84 > arch/arm/dts/rk3399.dtsi | 72 +++ > arch/arm/include/asm/arch-rockchip/grf_rk3399.h| 23 + > .../include/asm/arch-rockchip/rockchip_mipi_dsi.h | 195 > arch/arm/include/asm/arch-rockchip/vop_rk3288.h| 1 + > board/rockchip/evb_rk3399/evb-rk3399.c | 7 + > configs/evb-rk3399_defconfig | 6 + > drivers/video/rockchip/Kconfig | 8 +- > drivers/video/rockchip/Makefile| 1 + > drivers/video/rockchip/rk_mipi.c | 491 > + > drivers/video/rockchip/rk_vop.c| 38 +- > 11 files changed, 916 insertions(+), 10 deletions(-) > create mode 100644 arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h > create mode 100644 drivers/video/rockchip/rk_mipi.c > > -- > 1.9.1 > > When you send the next version can you please rebase against u-boot-rockchip/next? Thanks, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released
Hi Andreas, On 20 April 2017 at 20:54, Andreas Färber wrote: > Am 21.04.2017 um 04:43 schrieb Andreas Färber: >> Am 21.04.2017 um 04:24 schrieb Andreas Färber: >>> Hi Simon, >>> >>> Am 21.04.2017 um 04:10 schrieb Simon Glass: I just tested mainline with those two changes and it works for me. I pushed my patch to u-boot-rockchip/firefly-working. Can you try again? >>> >>> Confirming that with your defconfig it fully works again. >>> >>> I had instead run menuconfig and manually (un)selected the options. >>> Maybe those options influence other defaults? I was at the same qoriq >>> merge commit your branch is based off. >> >> Here's a quick diff against master: >> >> diff -u firefly/.config firefly/simon_config >> --- firefly/.config 2017-04-21 04:39:49.484215791 +0200 >> +++ firefly/simon_config 2017-04-21 04:39:07.123727380 +0200 >> @@ -169,9 +169,8 @@ >> CONFIG_ROCKCHIP_RK3288=y >> # CONFIG_ROCKCHIP_RK3328 is not set >> # CONFIG_ROCKCHIP_RK3399 is not set >> -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y >> -CONFIG_ROCKCHIP_BROM_HELPER=y >> -# CONFIG_SPL_MMC_SUPPORT is not set >> +# CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is not set >> +CONFIG_SPL_MMC_SUPPORT=y >> CONFIG_SPL_SERIAL_SUPPORT=y >> CONFIG_BOARD_SPECIFIC_OPTIONS=y >> # CONFIG_TARGET_CHROMEBOOK_JERRY is not set >> @@ -510,7 +509,7 @@ >> CONFIG_OF_SEPARATE=y >> # CONFIG_OF_EMBED is not set >> CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names >> interrupt-parent assigned-clocks assigned-clock-rates >> assigned-clock-parents" >> -# CONFIG_SPL_OF_PLATDATA is not set >> +CONFIG_SPL_OF_PLATDATA=y >> CONFIG_NET=y >> CONFIG_NET_RANDOM_ETHADDR=y >> # CONFIG_NETCONSOLE is not set >> @@ -848,6 +847,7 @@ >> # CONFIG_FSL_LPUART is not set >> # CONFIG_MVEBU_A3700_UART is not set >> CONFIG_SYS_NS16550=y >> +CONFIG_ROCKCHIP_SERIAL=y >> # CONFIG_MSM_SERIAL is not set >> # CONFIG_PXA_SERIAL is not set >> >> At least SERIAL looks important... > > ... but enabling SPL_OF_PLATDATA and ROCKCHIP_SERIAL on master (via > menuconfig) still sits at "Returning to boot ROM...". Can you diff the resulting config? There might perhaps be a broken dependency. > > Regards, > Andreas > > diff -u firefly/.config firefly/simon_config > --- firefly/.config 2017-04-21 04:47:11.165310486 +0200 > +++ firefly/simon_config2017-04-21 04:39:07.123727380 +0200 > @@ -169,9 +169,8 @@ > CONFIG_ROCKCHIP_RK3288=y > # CONFIG_ROCKCHIP_RK3328 is not set > # CONFIG_ROCKCHIP_RK3399 is not set > -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y > -CONFIG_ROCKCHIP_BROM_HELPER=y > -# CONFIG_SPL_MMC_SUPPORT is not set > +# CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is not set > +CONFIG_SPL_MMC_SUPPORT=y > CONFIG_SPL_SERIAL_SUPPORT=y > CONFIG_BOARD_SPECIFIC_OPTIONS=y > # CONFIG_TARGET_CHROMEBOOK_JERRY is not set > > -- > SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany > GF: Felix Imendörffer, Jane Smithard, Graham Norton > HRB 21284 (AG Nürnberg) Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 5/7] rockchip: rk3368: Add initial support for RK3368 based GeekBox
Hi Andy, Sorry for forgetting about this, and thank you for picking it up. Am 21.04.2017 um 04:32 schrieb Andy Yan: > From: Andreas Färber > > The GeekBox is a TV box from GeekBuying, based on an MXM3 module. > The module can be used with base boards such as the GeekBox Landingship. > > This adds basic support to chain-load U-Boot from Rockchip's miniloader. > > $ ./lollipop_u-boot/tools/loaderimage --pack u-boot.bin u-boot.img > > Implemented is the serial console, but no boot media drivers yet. > > Note that flashing the resulting U-Boot will not allow you to enter the > rockusb mode any more via "Update" button. Instead, you will need to > short two pins on the bottom of the module to enter MaskRom mode and > re-flash the loader: ":"? See also below. > > Signed-off-by: Andreas Färber > Signed-off-by: Andy Yan > --- > > arch/arm/dts/Makefile | 2 + > arch/arm/dts/rk3368-geekbox.dts | 319 > ++ > arch/arm/mach-rockchip/rk3368/Kconfig | 11 ++ > board/geekbuying/geekbox/Kconfig | 15 ++ > board/geekbuying/geekbox/MAINTAINERS | 6 + > board/geekbuying/geekbox/Makefile | 7 + > board/geekbuying/geekbox/geekbox.c| 28 +++ > configs/geekbox_defconfig | 21 +++ > include/configs/geekbox.h | 18 ++ > 9 files changed, 427 insertions(+) > create mode 100644 arch/arm/dts/rk3368-geekbox.dts > create mode 100644 board/geekbuying/geekbox/Kconfig > create mode 100644 board/geekbuying/geekbox/MAINTAINERS > create mode 100644 board/geekbuying/geekbox/Makefile > create mode 100644 board/geekbuying/geekbox/geekbox.c > create mode 100644 configs/geekbox_defconfig > create mode 100644 include/configs/geekbox.h One reason this series stalled is that I was asked to add a README instead of the text in the commit message - this is still missing in your submission, it seems. > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index ce34e3e..fbc97e8 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -41,8 +41,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ > rk3288-veyron-mickey.dtb \ > rk3288-veyron-minnie.dtb \ > rk3328-evb.dtb \ > + rk3368-geekbox.dtb \ > rk3399-evb.dtb \ > rk3399-puma.dtb > + rk3368-geekbox.dtb Mismerge. > dtb-$(CONFIG_ARCH_MESON) += \ > meson-gxbb-odroidc2.dtb [snip] Regards, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released
Am 21.04.2017 um 04:43 schrieb Andreas Färber: > Am 21.04.2017 um 04:24 schrieb Andreas Färber: >> Hi Simon, >> >> Am 21.04.2017 um 04:10 schrieb Simon Glass: >>> I just tested mainline with those two changes and it works for me. I >>> pushed my patch to u-boot-rockchip/firefly-working. Can you try again? >> >> Confirming that with your defconfig it fully works again. >> >> I had instead run menuconfig and manually (un)selected the options. >> Maybe those options influence other defaults? I was at the same qoriq >> merge commit your branch is based off. > > Here's a quick diff against master: > > diff -u firefly/.config firefly/simon_config > --- firefly/.config 2017-04-21 04:39:49.484215791 +0200 > +++ firefly/simon_config 2017-04-21 04:39:07.123727380 +0200 > @@ -169,9 +169,8 @@ > CONFIG_ROCKCHIP_RK3288=y > # CONFIG_ROCKCHIP_RK3328 is not set > # CONFIG_ROCKCHIP_RK3399 is not set > -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y > -CONFIG_ROCKCHIP_BROM_HELPER=y > -# CONFIG_SPL_MMC_SUPPORT is not set > +# CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is not set > +CONFIG_SPL_MMC_SUPPORT=y > CONFIG_SPL_SERIAL_SUPPORT=y > CONFIG_BOARD_SPECIFIC_OPTIONS=y > # CONFIG_TARGET_CHROMEBOOK_JERRY is not set > @@ -510,7 +509,7 @@ > CONFIG_OF_SEPARATE=y > # CONFIG_OF_EMBED is not set > CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names > interrupt-parent assigned-clocks assigned-clock-rates > assigned-clock-parents" > -# CONFIG_SPL_OF_PLATDATA is not set > +CONFIG_SPL_OF_PLATDATA=y > CONFIG_NET=y > CONFIG_NET_RANDOM_ETHADDR=y > # CONFIG_NETCONSOLE is not set > @@ -848,6 +847,7 @@ > # CONFIG_FSL_LPUART is not set > # CONFIG_MVEBU_A3700_UART is not set > CONFIG_SYS_NS16550=y > +CONFIG_ROCKCHIP_SERIAL=y > # CONFIG_MSM_SERIAL is not set > # CONFIG_PXA_SERIAL is not set > > At least SERIAL looks important... ... but enabling SPL_OF_PLATDATA and ROCKCHIP_SERIAL on master (via menuconfig) still sits at "Returning to boot ROM...". Regards, Andreas diff -u firefly/.config firefly/simon_config --- firefly/.config 2017-04-21 04:47:11.165310486 +0200 +++ firefly/simon_config2017-04-21 04:39:07.123727380 +0200 @@ -169,9 +169,8 @@ CONFIG_ROCKCHIP_RK3288=y # CONFIG_ROCKCHIP_RK3328 is not set # CONFIG_ROCKCHIP_RK3399 is not set -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y -CONFIG_ROCKCHIP_BROM_HELPER=y -# CONFIG_SPL_MMC_SUPPORT is not set +# CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is not set +CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOARD_SPECIFIC_OPTIONS=y # CONFIG_TARGET_CHROMEBOOK_JERRY is not set -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released
Am 21.04.2017 um 04:24 schrieb Andreas Färber: > Hi Simon, > > Am 21.04.2017 um 04:10 schrieb Simon Glass: >> On 20 April 2017 at 18:47, Andreas Färber wrote: >>> Am 21.04.2017 um 02:34 schrieb Andreas Färber: Am 21.04.2017 um 01:44 schrieb Simon Glass: > On 20 April 2017 at 17:23, Andreas Färber wrote: >> Using -rc2 with firefly-rk3288 defconfig I can only boot into SPL but >> not into full U-Boot. I am using the old documented way of dd'ing to >> sector 256 on SD (doc/README.rockchip). >> >> Looking at include/configs/rk3288_common.h I also tried putting >> u-boot.img on a FAT partition, to no effect. >> >> v2017.03 doesn't even show SPL working. >> v2017.01 worked okay. >> >> Build log for -rc2: >> https://build.opensuse.org/build/Base:System:Staging/openSUSE_Factory_ARM/armv7l/u-boot-firefly-rk3288/_log > > Can you try removing RETURN_TO_BROM (or imilsar) and adding > CONFIG_SPL_OF_PLATDATA? As an interim update I can share that latest master behaves slightly differently: U-Boot SPL 2017.05-rc2-00053-g3c476d8 (Apr 21 2017 - 02:29:48) Returning to boot ROM... compared to: U-Boot SPL 2017.05-rc2 (Apr 20 2017 - 14:33:20) >>> >>> Disabling the ROCKCHIP_SPL_BACK_TO_BROM option I get: >>> >>> U-Boot SPL 2017.05-rc2-00053-g3c476d8 (Apr 21 2017 - 02:38:52) >>> SPL: Unsupported Boot Device! >>> SPL: failed to boot from all boot devices >>> ### ERROR ### Please RESET the board ### >>> >>> If I additionally enable SPL_OF_PLATDATA then I am back to the v2017.03 >>> state of no serial output. >> >> I just tested mainline with those two changes and it works for me. I >> pushed my patch to u-boot-rockchip/firefly-working. Can you try again? > > Confirming that with your defconfig it fully works again. > > I had instead run menuconfig and manually (un)selected the options. > Maybe those options influence other defaults? I was at the same qoriq > merge commit your branch is based off. Here's a quick diff against master: diff -u firefly/.config firefly/simon_config --- firefly/.config 2017-04-21 04:39:49.484215791 +0200 +++ firefly/simon_config2017-04-21 04:39:07.123727380 +0200 @@ -169,9 +169,8 @@ CONFIG_ROCKCHIP_RK3288=y # CONFIG_ROCKCHIP_RK3328 is not set # CONFIG_ROCKCHIP_RK3399 is not set -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y -CONFIG_ROCKCHIP_BROM_HELPER=y -# CONFIG_SPL_MMC_SUPPORT is not set +# CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is not set +CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOARD_SPECIFIC_OPTIONS=y # CONFIG_TARGET_CHROMEBOOK_JERRY is not set @@ -510,7 +509,7 @@ CONFIG_OF_SEPARATE=y # CONFIG_OF_EMBED is not set CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -# CONFIG_SPL_OF_PLATDATA is not set +CONFIG_SPL_OF_PLATDATA=y CONFIG_NET=y CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_NETCONSOLE is not set @@ -848,6 +847,7 @@ # CONFIG_FSL_LPUART is not set # CONFIG_MVEBU_A3700_UART is not set CONFIG_SYS_NS16550=y +CONFIG_ROCKCHIP_SERIAL=y # CONFIG_MSM_SERIAL is not set # CONFIG_PXA_SERIAL is not set At least SERIAL looks important... Regards, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 7/7] rockchip: rk3368: add Sheep board
Sheep board is designed by Rockchip as a EVB for rk3368.
Currently it is able to boot a linux kernel and system
to console with the miniloader run as fist level loader.
Signed-off-by: Andy Yan
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3368-sheep.dts | 283 +
arch/arm/mach-rockchip/rk3368/Kconfig | 8 +-
board/rockchip/sheep_rk3368/Kconfig| 15 ++
board/rockchip/sheep_rk3368/MAINTAINERS| 6 +
board/rockchip/sheep_rk3368/Makefile | 7 +
board/rockchip/sheep_rk3368/sheep_rk3368.c | 37
configs/sheep-rk3368_defconfig | 28 +++
include/configs/sheep_rk3368.h | 22 +++
9 files changed, 406 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3368-sheep.dts
create mode 100644 board/rockchip/sheep_rk3368/Kconfig
create mode 100644 board/rockchip/sheep_rk3368/MAINTAINERS
create mode 100644 board/rockchip/sheep_rk3368/Makefile
create mode 100644 board/rockchip/sheep_rk3368/sheep_rk3368.c
create mode 100644 configs/sheep-rk3368_defconfig
create mode 100644 include/configs/sheep_rk3368.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d786611..caad028 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-minnie.dtb \
rk3328-evb.dtb \
rk3368-geekbox.dtb \
+ rk3368-sheep.dtb \
rk3368-px5-evb.dtb \
rk3399-evb.dtb \
rk3399-puma.dtb \
diff --git a/arch/arm/dts/rk3368-sheep.dts b/arch/arm/dts/rk3368-sheep.dts
new file mode 100644
index 000..e2f37ed
--- /dev/null
+++ b/arch/arm/dts/rk3368-sheep.dts
@@ -0,0 +1,283 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "rk3368.dtsi"
+#include
+
+/ {
+ model = "Rockchip sheep board";
+ compatible = "rockchip,sheep", "rockchip,rk3368";
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x8000>;
+ };
+
+ ext_gmac: gmac-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ ir: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_int>;
+ };
+
+ keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+ power {
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = ;
+ wakeup-source;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+
+ blue {
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ label = "geekbox:blue:led";
+ default-state = "on";
+ };
+
+ red {
+ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ label = "geekbox:red:led";
+ default-state = "off";
+ };
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&emmc {
+ status = "okay";
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ clock-frequency = <15000>;
+ disable-wp;
+ keep-power-in-suspend;
+ non-removable;
+ num-slots = <1>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_flash>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
+};
+
+&gmac {
+ status = "okay";
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&pmic_sleep>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc_sys>
[U-Boot] [PATCH 6/7] rockchip: rk3368: Add PX5 Evaluation board
PX5 EVB is designed by Rockchip for automotive field
with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS
HDMI video input/output interface, audio codec ES8396,
WIFI / BT (on RTL8723BS), Gsensor BMA250E and light&proximity
sensor STK3410.
Signed-off-by: Andy Yan
---
arch/arm/dts/Makefile | 5 +-
arch/arm/dts/rk3368-px5-evb.dts | 319 ++
arch/arm/mach-rockchip/rk3368/Kconfig | 9 +
board/rockchip/evb_px5/Kconfig| 15 ++
board/rockchip/evb_px5/MAINTAINERS| 6 +
board/rockchip/evb_px5/Makefile | 7 +
board/rockchip/evb_px5/evb-px5.c | 47 +
configs/evb-px5_defconfig | 30
include/configs/evb_px5.h | 18 ++
9 files changed, 454 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/rk3368-px5-evb.dts
create mode 100644 board/rockchip/evb_px5/Kconfig
create mode 100644 board/rockchip/evb_px5/MAINTAINERS
create mode 100644 board/rockchip/evb_px5/Makefile
create mode 100644 board/rockchip/evb_px5/evb-px5.c
create mode 100644 configs/evb-px5_defconfig
create mode 100644 include/configs/evb_px5.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fbc97e8..d786611 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -42,9 +42,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-minnie.dtb \
rk3328-evb.dtb \
rk3368-geekbox.dtb \
+ rk3368-px5-evb.dtb \
rk3399-evb.dtb \
- rk3399-puma.dtb
- rk3368-geekbox.dtb
+ rk3399-puma.dtb \
+ rk3399-evb.dtb
dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-odroidc2.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
diff --git a/arch/arm/dts/rk3368-px5-evb.dts b/arch/arm/dts/rk3368-px5-evb.dts
new file mode 100644
index 000..c7478f7
--- /dev/null
+++ b/arch/arm/dts/rk3368-px5-evb.dts
@@ -0,0 +1,319 @@
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3368.dtsi"
+#include
+
+/ {
+ model = "PX5 EVB";
+ compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
+
+ chosen {
+ stdout-path = "serial4:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x4000>;
+ };
+
+ ext_gmac: gmac-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ ir: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_int>;
+ };
+
+ keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+ power {
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
[U-Boot] [PATCH 5/7] rockchip: rk3368: Add initial support for RK3368 based GeekBox
From: Andreas Färber
The GeekBox is a TV box from GeekBuying, based on an MXM3 module.
The module can be used with base boards such as the GeekBox Landingship.
This adds basic support to chain-load U-Boot from Rockchip's miniloader.
$ ./lollipop_u-boot/tools/loaderimage --pack u-boot.bin u-boot.img
Implemented is the serial console, but no boot media drivers yet.
Note that flashing the resulting U-Boot will not allow you to enter the
rockusb mode any more via "Update" button. Instead, you will need to
short two pins on the bottom of the module to enter MaskRom mode and
re-flash the loader:
Signed-off-by: Andreas Färber
Signed-off-by: Andy Yan
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/rk3368-geekbox.dts | 319 ++
arch/arm/mach-rockchip/rk3368/Kconfig | 11 ++
board/geekbuying/geekbox/Kconfig | 15 ++
board/geekbuying/geekbox/MAINTAINERS | 6 +
board/geekbuying/geekbox/Makefile | 7 +
board/geekbuying/geekbox/geekbox.c| 28 +++
configs/geekbox_defconfig | 21 +++
include/configs/geekbox.h | 18 ++
9 files changed, 427 insertions(+)
create mode 100644 arch/arm/dts/rk3368-geekbox.dts
create mode 100644 board/geekbuying/geekbox/Kconfig
create mode 100644 board/geekbuying/geekbox/MAINTAINERS
create mode 100644 board/geekbuying/geekbox/Makefile
create mode 100644 board/geekbuying/geekbox/geekbox.c
create mode 100644 configs/geekbox_defconfig
create mode 100644 include/configs/geekbox.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce34e3e..fbc97e8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -41,8 +41,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
rk3328-evb.dtb \
+ rk3368-geekbox.dtb \
rk3399-evb.dtb \
rk3399-puma.dtb
+ rk3368-geekbox.dtb
dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-odroidc2.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
diff --git a/arch/arm/dts/rk3368-geekbox.dts b/arch/arm/dts/rk3368-geekbox.dts
new file mode 100644
index 000..46cdddf
--- /dev/null
+++ b/arch/arm/dts/rk3368-geekbox.dts
@@ -0,0 +1,319 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3368.dtsi"
+#include
+
+/ {
+ model = "GeekBox";
+ compatible = "geekbuying,geekbox", "rockchip,rk3368";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x8000>;
+ };
+
+ ext_gmac: gmac-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ ir: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl
[U-Boot] [PATCH 4/7] rockchip: rk3368: Add sysreset driver
Add sysreset driver to reset rk3368 SOC.
Signed-off-by: Andy Yan
---
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_rk3368.c | 58 ++
2 files changed, 59 insertions(+)
create mode 100644 drivers/sysreset/sysreset_rk3368.c
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 49b8bb6..ffc61c3 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -12,6 +12,7 @@ endif
obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
+obj-$(CONFIG_ROCKCHIP_RK3368) += sysreset_rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
diff --git a/drivers/sysreset/sysreset_rk3368.c
b/drivers/sysreset/sysreset_rk3368.c
new file mode 100644
index 000..32ebc47
--- /dev/null
+++ b/drivers/sysreset/sysreset_rk3368.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static void rk3368_pll_enter_slow_mode(struct rk3368_cru *cru)
+{
+ struct rk3368_pll *pll;
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ pll = &cru->pll[i];
+ rk_clrreg(&pll->con3, PLL_MODE_MASK);
+ }
+}
+
+static int rk3368_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct rk3368_cru *cru = rockchip_get_cru();
+
+ if (IS_ERR(cru))
+ return PTR_ERR(cru);
+ switch (type) {
+ case SYSRESET_WARM:
+ rk3368_pll_enter_slow_mode(cru);
+ writel(0xeca8, &cru->glb_srst_snd_val);
+ break;
+ case SYSRESET_COLD:
+ rk3368_pll_enter_slow_mode(cru);
+ writel(0xfdb9, &cru->glb_srst_fst_val);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk3368_sysreset = {
+ .request= rk3368_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk3368) = {
+ .name = "rk3368_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops= &rk3368_sysreset,
+};
--
2.7.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/7] rockchip: rk3368: Add core start-up code for RK3368
From: Andreas Färber
The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
This adds basic support to chain-load U-Boot from Rockchip's
miniloader.
Signed-off-by: Andreas Färber
Signed-off-by: Andy Yan
---
arch/arm/dts/rk3368.dtsi | 1090 +
arch/arm/mach-rockchip/Kconfig| 13 +
arch/arm/mach-rockchip/Makefile |1 +
arch/arm/mach-rockchip/rk3368/Kconfig |8 +
arch/arm/mach-rockchip/rk3368/Makefile|8 +
arch/arm/mach-rockchip/rk3368/clk_rk3368.c| 32 +
arch/arm/mach-rockchip/rk3368/rk3368.c| 84 ++
arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 25 +
include/configs/rk3368_common.h | 43 +
include/dt-bindings/clock/rk3368-cru.h| 384 +
10 files changed, 1688 insertions(+)
create mode 100644 arch/arm/dts/rk3368.dtsi
create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3368/clk_rk3368.c
create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c
create mode 100644 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
create mode 100644 include/configs/rk3368_common.h
create mode 100644 include/dt-bindings/clock/rk3368-cru.h
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
new file mode 100644
index 000..025dc32
--- /dev/null
+++ b/arch/arm/dts/rk3368.dtsi
@@ -0,0 +1,1090 @@
+/*
+ * Copyright (c) 2015 Heiko Stuebner
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "rockchip,rk3368";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &gmac;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu_b0>;
+ };
+ core1 {
+ cpu = <&cpu_b1>;
+ };
+ core2 {
+ cpu = <&cpu_b2>;
+ };
+ core3 {
+ cpu = <&cpu_b3>;
+ };
+ };
+
+ cluster1 {
+ cor
[U-Boot] [PATCH 2/7] rockchip: rk3368: Add pinctrl driver
Add driver to support iomux setup for the most commonly
used peripherals on rk3368.
Signed-off-by: Andy Yan
---
arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 443
drivers/pinctrl/Kconfig | 9 +
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl_rk3368.c | 243 +
4 files changed, 696 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3368.h
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3368.c
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
new file mode 100644
index 000..f37beb8
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -0,0 +1,443 @@
+/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_GRF_RK3368_H
+#define _ASM_ARCH_GRF_RK3368_H
+
+#include
+
+#define GRF_BASE 0xff77
+#define PMU_GRF_BASE 0xff738000
+
+struct rk3368_grf {
+ u32 gpio1a_iomux;
+ u32 gpio1b_iomux;
+ u32 gpio1c_iomux;
+ u32 gpio1d_iomux;
+ u32 gpio2a_iomux;
+ u32 gpio2b_iomux;
+ u32 gpio2c_iomux;
+ u32 gpio2d_iomux;
+ u32 gpio3a_iomux;
+ u32 gpio3b_iomux;
+ u32 gpio3c_iomux;
+ u32 gpio3d_iomux;
+ u32 reserved[0x34];
+ u32 gpio1a_pull;
+ u32 gpio1b_pull;
+ u32 gpio1c_pull;
+ u32 gpio1d_pull;
+ u32 gpio2a_pull;
+ u32 gpio2b_pull;
+ u32 gpio2c_pull;
+ u32 gpio2d_pull;
+ u32 gpio3a_pull;
+ u32 gpio3b_pull;
+ u32 gpio3c_pull;
+ u32 gpio3d_pull;
+ u32 reserved1[0x34];
+ u32 gpio1a_drv;
+ u32 gpio1b_drv;
+ u32 gpio1c_drv;
+ u32 gpio1d_drv;
+ u32 gpio2a_drv;
+ u32 gpio2b_drv;
+ u32 gpio2c_drv;
+ u32 gpio2d_drv;
+ u32 gpio3a_drv;
+ u32 gpio3b_drv;
+ u32 gpio3c_drv;
+ u32 gpio3d_drv;
+ u32 reserved2[0x34];
+ u32 gpio1l_sr;
+ u32 gpio1h_sr;
+ u32 gpio2l_sr;
+ u32 gpio2h_sr;
+ u32 gpio3l_sr;
+ u32 gpio3h_sr;
+ u32 reserved3[0x1a];
+ u32 gpio_smt;
+ u32 reserved4[0x1f];
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 soc_con2;
+ u32 soc_con3;
+ u32 soc_con4;
+ u32 soc_con5;
+ u32 soc_con6;
+ u32 soc_con7;
+ u32 soc_con8;
+ u32 soc_con9;
+ u32 soc_con10;
+ u32 soc_con11;
+ u32 soc_con12;
+ u32 soc_con13;
+ u32 soc_con14;
+ u32 soc_con15;
+ u32 soc_con16;
+ u32 soc_con17;
+};
+check_member(rk3368_grf, soc_con17, 0x444);
+
+struct rk3368_pmu_grf {
+ u32 gpio0a_iomux;
+ u32 gpio0b_iomux;
+ u32 gpio0c_iomux;
+ u32 gpio0d_iomux;
+ u32 gpio0a_pull;
+ u32 gpio0b_pull;
+ u32 gpio0c_pull;
+ u32 gpio0d_pull;
+ u32 gpio0a_drv;
+ u32 gpio0b_drv;
+ u32 gpio0c_drv;
+ u32 gpio0d_drv;
+ u32 gpio0l_sr;
+ u32 gpio0h_sr;
+};
+check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
+
+/*GRF_GPIO0C_IOMUX*/
+enum {
+ GPIO0C7_SHIFT = 14,
+ GPIO0C7_MASK= 3 << GPIO0C7_SHIFT,
+ GPIO0C7_GPIO= 0,
+ GPIO0C7_LCDC_D19,
+ GPIO0C7_TRACE_D9,
+ GPIO0C7_UART1_RTSN,
+
+ GPIO0C6_SHIFT = 12,
+ GPIO0C6_MASK= 3 << GPIO0C6_SHIFT,
+ GPIO0C6_GPIO= 0,
+ GPIO0C6_LCDC_D18,
+ GPIO0C6_TRACE_D8,
+ GPIO0C6_UART1_CTSN,
+
+ GPIO0C5_SHIFT = 10,
+ GPIO0C5_MASK= 3 << GPIO0C5_SHIFT,
+ GPIO0C5_GPIO= 0,
+ GPIO0C5_LCDC_D17,
+ GPIO0C5_TRACE_D7,
+ GPIO0C5_UART1_SOUT,
+
+ GPIO0C4_SHIFT = 8,
+ GPIO0C4_MASK= 3 << GPIO0C4_SHIFT,
+ GPIO0C4_GPIO= 0,
+ GPIO0C4_LCDC_D16,
+ GPIO0C4_TRACE_D6,
+ GPIO0C4_UART1_SIN,
+
+ GPIO0C3_SHIFT = 6,
+ GPIO0C3_MASK= 3 << GPIO0C3_SHIFT,
+ GPIO0C3_GPIO= 0,
+ GPIO0C3_LCDC_D15,
+ GPIO0C3_TRACE_D5,
+ GPIO0C3_MCU_JTAG_TDO,
+
+ GPIO0C2_SHIFT = 4,
+ GPIO0C2_MASK= 3 << GPIO0C2_SHIFT,
+ GPIO0C2_GPIO= 0,
+ GPIO0C2_LCDC_D14,
+ GPIO0C2_TRACE_D4,
+ GPIO0C2_MCU_JTAG_TDI,
+
+ GPIO0C1_SHIFT = 2,
+ GPIO0C1_MASK= 3 << GPIO0C1_SHIFT,
+ GPIO0C1_GPIO= 0,
+ GPIO0C1_LCDC_D13,
+ GPIO0C1_TRACE_D3,
+ GPIO0C1_MCU_JTAG_TRTSN,
+
+ GPIO0C0_SHIFT = 0,
+ GPIO0C0_MASK= 3 << GPIO0C0_SHIFT,
+ GPIO0C0_GPIO= 0,
+ GPIO0C0_LCDC_D12,
+ GPIO0C0_TRACE_D2,
+ GPIO0C0_MCU_JTAG_TDO,
+};
+
+/*GRF_GPIO0D_IOMUX*/
+enum {
+ GPIO0D7_SHIFT = 14,
+ GPIO0D7_MASK= 3 << GPIO0D7_SHIFT,
+
[U-Boot] [PATCH 1/7] rockchip: rk3368: Add clok drvier
Add driver to setup the various PLLs and peripheral
clocks on the RK3368.
Signed-off-by: Andy Yan
---
arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 110 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_rk3368.c | 296
3 files changed, 407 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3368.h
create mode 100644 drivers/clk/rockchip/clk_rk3368.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
new file mode 100644
index 000..122c8be
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_CRU_RK3368_H
+#define _ASM_ARCH_CRU_RK3368_H
+
+#include
+
+#define CRU_BASE 0xff76
+
+/* RK3368 clock numbers */
+enum rk3368_pll_id {
+ APLLB,
+ APLLL,
+ DPLL,
+ CPLL,
+ GPLL,
+ NPLL,
+ PLL_COUNT,
+};
+
+struct rk3368_cru {
+ struct rk3368_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ } pll[6];
+ unsigned int reserved[0x28];
+ unsigned int clksel_con[56];
+ unsigned int reserved1[8];
+ unsigned int clkgate_con[25];
+ unsigned int reserved2[7];
+ unsigned int glb_srst_fst_val;
+ unsigned int glb_srst_snd_val;
+ unsigned int reserved3[0x1e];
+ unsigned int softrst_con[15];
+ unsigned int reserved4[0x11];
+ unsigned int misc_con;
+ unsigned int glb_cnt_th;
+ unsigned int glb_rst_con;
+ unsigned int glb_rst_st;
+ unsigned int reserved5[0x1c];
+ unsigned int sdmmc_con[2];
+ unsigned int sdio0_con[2];
+ unsigned int sdio1_con[2];
+ unsigned int emmc_con[2];
+};
+check_member(rk3368_cru, emmc_con[1], 0x41c);
+
+struct rk3368_clk_priv {
+ struct rk3368_cru *cru;
+ ulong rate;
+ bool has_bwadj;
+};
+
+enum {
+ /*PLL CON0*/
+ PLL_NR_SHIFT= 8,
+ PLL_NR_MASK = GENMASK(13, 8),
+ PLL_OD_SHIFT= 0,
+ PLL_OD_MASK = GENMASK(3, 0),
+
+ /*PLL CON1*/
+ PLL_LOCK_STA= BIT(31),
+ PLL_NF_SHIFT= 0,
+ PLL_NF_MASK = GENMASK(12, 0),
+
+ /*PLL CON2*/
+ PLL_BWADJ_SHIFT = 0,
+ PLL_BWADJ_MASK = GENMASK(11, 0),
+
+ /*PLL CON3*/
+ PLL_MODE_SHIFT = 8,
+ PLL_MODE_MASK = GENMASK(9, 8),
+ PLL_MODE_SLOW = 0,
+ PLL_MODE_NORMAL = 1,
+ PLL_MODE_DEEP_SLOW = 3,
+ PLL_RESET_SHIFT = 5,
+ PLL_RESET = 1,
+ PLL_RESET_MASK = GENMASK(5, 5),
+
+ /*CLKSEL12_CON*/
+ MCU_STCLK_DIV_SHIFT = 8,
+ MCU_STCLK_DIV_MASK = GENMASK(10, 8),
+ MCU_PLL_SEL_SHIFT = 7,
+ MCU_PLL_SEL_MASK= BIT(7),
+ MCU_PLL_SEL_CPLL= 0,
+ MCU_PLL_SEL_GPLL= 1,
+ MCU_CLK_DIV_SHIFT = 0,
+ MCU_CLK_DIV_MASK= GENMASK(4, 0),
+
+ /*CLKSEL51_CON*/
+ MMC_PLL_SEL_SHIFT = 8,
+ MMC_PLL_SEL_MASK= GENMASK(9, 8),
+ MMC_PLL_SEL_CPLL= 0,
+ MMC_PLL_SEL_GPLL,
+ MMC_PLL_SEL_USBPHY_480M,
+ MMC_PLL_SEL_24M,
+ MMC_CLK_DIV_SHIFT = 0,
+ MMC_CLK_DIV_MASK= GENMASK(6, 0),
+
+ /*SOFTRST1_CON*/
+ MCU_PO_SRST_MASK= BIT(13),
+ MCU_SYS_SRST_MASK = BIT(12),
+
+};
+#endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 1091a76..8dc60f8 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
+obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
diff --git a/drivers/clk/rockchip/clk_rk3368.c
b/drivers/clk/rockchip/clk_rk3368.c
new file mode 100644
index 000..626e60c
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -0,0 +1,296 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan
+ * SPDX-License-Identifier:GPL-2.0
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pll_div {
+ u32 nr;
+ u32 nf;
+ u32 no;
+};
+
+#define OSC_HZ (24 * 1000 * 1000)
+#define APLL_L_HZ (800 * 1000 * 1000)
+#define APLL_B_HZ (816 * 1000 * 1000)
+#define GPLL_HZ(576 * 1000 * 1000)
+#define CPLL_HZ
[U-Boot] [PATCH 0/7] Add basic support for Rockchip RK3368 SOC
The RK3368 is an octa-core Cortex-A53 SoC from Rockchip. This adds basic support to chain-load U-Boot from Rockchip's miniloader. Andreas Färber (2): rockchip: rk3368: Add core start-up code for RK3368 rockchip: rk3368: Add initial support for RK3368 based GeekBox Andy Yan (5): rockchip: rk3368: Add clok drvier rockchip: rk3368: Add pinctrl driver rockchip: rk3368: Add sysreset driver rockchip: rk3368: Add PX5 Evaluation board rockchip: rk3368: add Sheep board arch/arm/dts/Makefile |6 +- arch/arm/dts/rk3368-geekbox.dts | 319 +++ arch/arm/dts/rk3368-px5-evb.dts | 319 +++ arch/arm/dts/rk3368-sheep.dts | 283 ++ arch/arm/dts/rk3368.dtsi| 1090 +++ arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 110 +++ arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 443 + arch/arm/mach-rockchip/Kconfig | 13 + arch/arm/mach-rockchip/Makefile |1 + arch/arm/mach-rockchip/rk3368/Kconfig | 34 + arch/arm/mach-rockchip/rk3368/Makefile |8 + arch/arm/mach-rockchip/rk3368/clk_rk3368.c | 32 + arch/arm/mach-rockchip/rk3368/rk3368.c | 84 ++ arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 25 + board/geekbuying/geekbox/Kconfig| 15 + board/geekbuying/geekbox/MAINTAINERS|6 + board/geekbuying/geekbox/Makefile |7 + board/geekbuying/geekbox/geekbox.c | 28 + board/rockchip/evb_px5/Kconfig | 15 + board/rockchip/evb_px5/MAINTAINERS |6 + board/rockchip/evb_px5/Makefile |7 + board/rockchip/evb_px5/evb-px5.c| 47 + board/rockchip/sheep_rk3368/Kconfig | 15 + board/rockchip/sheep_rk3368/MAINTAINERS |6 + board/rockchip/sheep_rk3368/Makefile|7 + board/rockchip/sheep_rk3368/sheep_rk3368.c | 37 + configs/evb-px5_defconfig | 30 + configs/geekbox_defconfig | 21 + configs/sheep-rk3368_defconfig | 28 + drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk_rk3368.c | 296 ++ drivers/pinctrl/Kconfig |9 + drivers/pinctrl/rockchip/Makefile |1 + drivers/pinctrl/rockchip/pinctrl_rk3368.c | 243 + drivers/sysreset/Makefile |1 + drivers/sysreset/sysreset_rk3368.c | 58 ++ include/configs/evb_px5.h | 18 + include/configs/geekbox.h | 18 + include/configs/rk3368_common.h | 43 + include/configs/sheep_rk3368.h | 22 + include/dt-bindings/clock/rk3368-cru.h | 384 41 files changed, 4135 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3368-geekbox.dts create mode 100644 arch/arm/dts/rk3368-px5-evb.dts create mode 100644 arch/arm/dts/rk3368-sheep.dts create mode 100644 arch/arm/dts/rk3368.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3368.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3368.h create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile create mode 100644 arch/arm/mach-rockchip/rk3368/clk_rk3368.c create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c create mode 100644 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c create mode 100644 board/geekbuying/geekbox/Kconfig create mode 100644 board/geekbuying/geekbox/MAINTAINERS create mode 100644 board/geekbuying/geekbox/Makefile create mode 100644 board/geekbuying/geekbox/geekbox.c create mode 100644 board/rockchip/evb_px5/Kconfig create mode 100644 board/rockchip/evb_px5/MAINTAINERS create mode 100644 board/rockchip/evb_px5/Makefile create mode 100644 board/rockchip/evb_px5/evb-px5.c create mode 100644 board/rockchip/sheep_rk3368/Kconfig create mode 100644 board/rockchip/sheep_rk3368/MAINTAINERS create mode 100644 board/rockchip/sheep_rk3368/Makefile create mode 100644 board/rockchip/sheep_rk3368/sheep_rk3368.c create mode 100644 configs/evb-px5_defconfig create mode 100644 configs/geekbox_defconfig create mode 100644 configs/sheep-rk3368_defconfig create mode 100644 drivers/clk/rockchip/clk_rk3368.c create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3368.c create mode 100644 drivers/sysreset/sysreset_rk3368.c create mode 100644 include/configs/evb_px5.h create mode 100644 include/configs/geekbox.h create mode 100644 include/configs/rk3368_common.h create mode 100644 include/configs/sheep_rk3368.h create mode 100644 include/dt-bindings/clock/rk3368-cru.h -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released
Hi Simon, Am 21.04.2017 um 04:10 schrieb Simon Glass: > On 20 April 2017 at 18:47, Andreas Färber wrote: >> Am 21.04.2017 um 02:34 schrieb Andreas Färber: >>> Am 21.04.2017 um 01:44 schrieb Simon Glass: On 20 April 2017 at 17:23, Andreas Färber wrote: > Using -rc2 with firefly-rk3288 defconfig I can only boot into SPL but > not into full U-Boot. I am using the old documented way of dd'ing to > sector 256 on SD (doc/README.rockchip). > > Looking at include/configs/rk3288_common.h I also tried putting > u-boot.img on a FAT partition, to no effect. > > v2017.03 doesn't even show SPL working. > v2017.01 worked okay. > > Build log for -rc2: > https://build.opensuse.org/build/Base:System:Staging/openSUSE_Factory_ARM/armv7l/u-boot-firefly-rk3288/_log Can you try removing RETURN_TO_BROM (or imilsar) and adding CONFIG_SPL_OF_PLATDATA? >>> >>> As an interim update I can share that latest master behaves slightly >>> differently: >>> >>> U-Boot SPL 2017.05-rc2-00053-g3c476d8 (Apr 21 2017 - 02:29:48) >>> Returning to boot ROM... >>> >>> compared to: >>> >>> U-Boot SPL 2017.05-rc2 (Apr 20 2017 - 14:33:20) >> >> Disabling the ROCKCHIP_SPL_BACK_TO_BROM option I get: >> >> U-Boot SPL 2017.05-rc2-00053-g3c476d8 (Apr 21 2017 - 02:38:52) >> SPL: Unsupported Boot Device! >> SPL: failed to boot from all boot devices >> ### ERROR ### Please RESET the board ### >> >> If I additionally enable SPL_OF_PLATDATA then I am back to the v2017.03 >> state of no serial output. > > I just tested mainline with those two changes and it works for me. I > pushed my patch to u-boot-rockchip/firefly-working. Can you try again? Confirming that with your defconfig it fully works again. I had instead run menuconfig and manually (un)selected the options. Maybe those options influence other defaults? I was at the same qoriq merge commit your branch is based off. Anyway, does this allow any conclusions for -rc3? Cheers, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released
Hi Andreas, On 20 April 2017 at 18:47, Andreas Färber wrote: > Am 21.04.2017 um 02:34 schrieb Andreas Färber: >> Hi Simon, >> >> Am 21.04.2017 um 01:44 schrieb Simon Glass: >>> On 20 April 2017 at 17:23, Andreas Färber wrote: Using -rc2 with firefly-rk3288 defconfig I can only boot into SPL but not into full U-Boot. I am using the old documented way of dd'ing to sector 256 on SD (doc/README.rockchip). Looking at include/configs/rk3288_common.h I also tried putting u-boot.img on a FAT partition, to no effect. v2017.03 doesn't even show SPL working. v2017.01 worked okay. Build log for -rc2: https://build.opensuse.org/build/Base:System:Staging/openSUSE_Factory_ARM/armv7l/u-boot-firefly-rk3288/_log >>> >>> Can you try removing RETURN_TO_BROM (or imilsar) and adding >>> CONFIG_SPL_OF_PLATDATA? >> >> As an interim update I can share that latest master behaves slightly >> differently: >> >> U-Boot SPL 2017.05-rc2-00053-g3c476d8 (Apr 21 2017 - 02:29:48) >> Returning to boot ROM... >> >> compared to: >> >> U-Boot SPL 2017.05-rc2 (Apr 20 2017 - 14:33:20) > > Disabling the ROCKCHIP_SPL_BACK_TO_BROM option I get: > > U-Boot SPL 2017.05-rc2-00053-g3c476d8 (Apr 21 2017 - 02:38:52) > SPL: Unsupported Boot Device! > SPL: failed to boot from all boot devices > ### ERROR ### Please RESET the board ### > > If I additionally enable SPL_OF_PLATDATA then I am back to the v2017.03 > state of no serial output. I just tested mainline with those two changes and it works for me. I pushed my patch to u-boot-rockchip/firefly-working. Can you try again? Regards, Simon > > Regards, > Andreas > > -- > SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany > GF: Felix Imendörffer, Jane Smithard, Graham Norton > HRB 21284 (AG Nürnberg) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released
Hi Andreas, On Apr 20, 2017 18:34, "Andreas Färber" wrote: Hi Simon, Am 21.04.2017 um 01:44 schrieb Simon Glass: > On 20 April 2017 at 17:23, Andreas Färber wrote: >> Using -rc2 with firefly-rk3288 defconfig I can only boot into SPL but >> not into full U-Boot. I am using the old documented way of dd'ing to >> sector 256 on SD (doc/README.rockchip). >> >> Looking at include/configs/rk3288_common.h I also tried putting >> u-boot.img on a FAT partition, to no effect. >> >> v2017.03 doesn't even show SPL working. >> v2017.01 worked okay. >> >> Build log for -rc2: >> https://build.opensuse.org/build/Base:System:Staging/openSUS E_Factory_ARM/armv7l/u-boot-firefly-rk3288/_log > > Can you try removing RETURN_TO_BROM (or imilsar) and adding > CONFIG_SPL_OF_PLATDATA? As an interim update I can share that latest master behaves slightly differently: U-Boot SPL 2017.05-rc2-00053-g3c476d8 (Apr 21 2017 - 02:29:48) Returning to boot ROM... compared to: U-Boot SPL 2017.05-rc2 (Apr 20 2017 - 14:33:20) Will tweak options next. Yes I got sick of it hanging with no message! Regards, Simon Thanks, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2] QE: add QE support on SD boot
modify u_qe_init to upload QE firmware from SD card when it is SD
boot
Signed-off-by: Zhao Qiang
---
Changes for v2:
- fix issue of memory leak
drivers/qe/qe.c | 37 -
include/configs/ls1043a_common.h | 2 ++
include/configs/ls1043ardb.h | 4 +---
3 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 4f0a278..52e4d7c 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -8,6 +8,7 @@
*/
#include
+#include
#include
#include
#include
@@ -17,6 +18,10 @@
#include
#endif
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#include
+#endif
+
#define MPC85xx_DEVDISR_QE_DISABLE 0x1
qe_map_t *qe_immr = NULL;
@@ -194,8 +199,38 @@ void u_qe_init(void)
{
qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
- u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
+#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
+ void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+ void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+ u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
+
+ if (mmc_initialize(gd->bd)) {
+ printf("%s: mmc_initialize() failed\n", __func__);
+ return;
+ }
+ struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+ if (!mmc) {
+ free(addr);
+ printf("\nMMC cannot find device for ucode\n");
+ } else {
+ printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
+ dev, blk, cnt);
+ mmc_init(mmc);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+ addr);
+ /* flush cache after read */
+ flush_cache((ulong)addr, cnt * 512);
+ }
+#endif
+ u_qe_upload_firmware(addr);
out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
+ free(addr);
+#endif
}
#endif
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index e269248..80c508e 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -219,6 +219,7 @@
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR(512 * 0x820)
+#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR0x400d
@@ -230,6 +231,7 @@
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* FMan fireware Pre-load address */
#define CONFIG_SYS_FMAN_FW_ADDR0x6030
+#define CONFIG_SYS_QE_FW_ADDR 0x6060
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x1
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 5e570cd..ffa0dba 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -277,11 +277,9 @@
/* QE */
#ifndef SPL_NO_QE
-#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
- !defined(CONFIG_QSPI_BOOT)
+#if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#endif
-#define CONFIG_SYS_QE_FW_ADDR 0x6060
#endif
/* USB */
--
2.1.0.27.g96db324
___
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Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released
Am 21.04.2017 um 02:34 schrieb Andreas Färber: > Hi Simon, > > Am 21.04.2017 um 01:44 schrieb Simon Glass: >> On 20 April 2017 at 17:23, Andreas Färber wrote: >>> Using -rc2 with firefly-rk3288 defconfig I can only boot into SPL but >>> not into full U-Boot. I am using the old documented way of dd'ing to >>> sector 256 on SD (doc/README.rockchip). >>> >>> Looking at include/configs/rk3288_common.h I also tried putting >>> u-boot.img on a FAT partition, to no effect. >>> >>> v2017.03 doesn't even show SPL working. >>> v2017.01 worked okay. >>> >>> Build log for -rc2: >>> https://build.opensuse.org/build/Base:System:Staging/openSUSE_Factory_ARM/armv7l/u-boot-firefly-rk3288/_log >> >> Can you try removing RETURN_TO_BROM (or imilsar) and adding >> CONFIG_SPL_OF_PLATDATA? > > As an interim update I can share that latest master behaves slightly > differently: > > U-Boot SPL 2017.05-rc2-00053-g3c476d8 (Apr 21 2017 - 02:29:48) > Returning to boot ROM... > > compared to: > > U-Boot SPL 2017.05-rc2 (Apr 20 2017 - 14:33:20) Disabling the ROCKCHIP_SPL_BACK_TO_BROM option I get: U-Boot SPL 2017.05-rc2-00053-g3c476d8 (Apr 21 2017 - 02:38:52) SPL: Unsupported Boot Device! SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### If I additionally enable SPL_OF_PLATDATA then I am back to the v2017.03 state of no serial output. Regards, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released
Hi Simon, Am 21.04.2017 um 01:44 schrieb Simon Glass: > On 20 April 2017 at 17:23, Andreas Färber wrote: >> Using -rc2 with firefly-rk3288 defconfig I can only boot into SPL but >> not into full U-Boot. I am using the old documented way of dd'ing to >> sector 256 on SD (doc/README.rockchip). >> >> Looking at include/configs/rk3288_common.h I also tried putting >> u-boot.img on a FAT partition, to no effect. >> >> v2017.03 doesn't even show SPL working. >> v2017.01 worked okay. >> >> Build log for -rc2: >> https://build.opensuse.org/build/Base:System:Staging/openSUSE_Factory_ARM/armv7l/u-boot-firefly-rk3288/_log > > Can you try removing RETURN_TO_BROM (or imilsar) and adding > CONFIG_SPL_OF_PLATDATA? As an interim update I can share that latest master behaves slightly differently: U-Boot SPL 2017.05-rc2-00053-g3c476d8 (Apr 21 2017 - 02:29:48) Returning to boot ROM... compared to: U-Boot SPL 2017.05-rc2 (Apr 20 2017 - 14:33:20) Will tweak options next. Thanks, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released
Hi Andreas, On 20 April 2017 at 17:23, Andreas Färber wrote: > Hi, > > Using -rc2 with firefly-rk3288 defconfig I can only boot into SPL but > not into full U-Boot. I am using the old documented way of dd'ing to > sector 256 on SD (doc/README.rockchip). > > Looking at include/configs/rk3288_common.h I also tried putting > u-boot.img on a FAT partition, to no effect. > > v2017.03 doesn't even show SPL working. > v2017.01 worked okay. > > Build log for -rc2: > https://build.opensuse.org/build/Base:System:Staging/openSUSE_Factory_ARM/armv7l/u-boot-firefly-rk3288/_log Can you try removing RETURN_TO_BROM (or imilsar) and adding CONFIG_SPL_OF_PLATDATA? If that works we should probably create a new board variant with that configuration, or figure out a way to detect which to use. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2017.05-rc2 released
Hi, Using -rc2 with firefly-rk3288 defconfig I can only boot into SPL but not into full U-Boot. I am using the old documented way of dd'ing to sector 256 on SD (doc/README.rockchip). Looking at include/configs/rk3288_common.h I also tried putting u-boot.img on a FAT partition, to no effect. v2017.03 doesn't even show SPL working. v2017.01 worked okay. Build log for -rc2: https://build.opensuse.org/build/Base:System:Staging/openSUSE_Factory_ARM/armv7l/u-boot-firefly-rk3288/_log Regards, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] armv8: layerscape: Fix DDR size calcuation for SPL build
Commit 088454cd dropped return value from initram(), setting
gd->ram_size directly. Three boards were missed for SPL boot.
Signed-off-by: York Sun
---
board/freescale/ls1043aqds/ddr.c | 4 +++-
board/freescale/ls1046aqds/ddr.c | 4 +++-
board/freescale/ls1046ardb/ddr.c | 4 +++-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index 2643f5b..b22d378 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -113,7 +113,9 @@ int fsl_initdram(void)
phys_size_t dram_size;
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- return fsl_ddr_sdram_size();
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
#else
puts("Initializing DDRusing SPD\n");
diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c
index d37af34..5fcfa0f 100644
--- a/board/freescale/ls1046aqds/ddr.c
+++ b/board/freescale/ls1046aqds/ddr.c
@@ -97,7 +97,9 @@ int fsl_initdram(void)
phys_size_t dram_size;
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- return fsl_ddr_sdram_size();
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
#else
puts("Initializing DDRusing SPD\n");
diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c
index a16f7bc..ae5046c 100644
--- a/board/freescale/ls1046ardb/ddr.c
+++ b/board/freescale/ls1046ardb/ddr.c
@@ -101,7 +101,9 @@ int fsl_initdram(void)
phys_size_t dram_size;
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- return fsl_ddr_sdram_size();
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
#else
puts("Initializing DDRusing SPD\n");
--
2.7.4
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Re: [U-Boot] [PATCH v1 1/2] rockchip: dts: Clean up graffiti in rk3399-sdram-ddr3-1333.dtsi
On 17 April 2017 at 22:01, Simon Glass wrote: > On 17 April 2017 at 09:50, Philipp Tomsich > wrote: >> The DDR3-1333 timings for the RK3399-Q7 (Puma) has some unintended >> left-over comments in them. This change cleans the file up. >> >> Signed-off-by: Philipp Tomsich >> --- >> >> arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi | 8 >> 1 file changed, 4 insertions(+), 4 deletions(-) >> > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] rockchip: enable debug uart
On 18 April 2017 at 18:12, Simon Glass wrote: > On 18 April 2017 at 05:17, Eddie Cai wrote: >> enable debug uart for rk3288 and print something to let people know >> where we are >> >> Signed-off-by: Eddie Cai >> --- >> arch/arm/mach-rockchip/rk3288-board-spl.c | 6 ++ >> 1 file changed, 2 insertions(+), 4 deletions(-) >> > > Reviewed-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 4/7] rockchip: spi: rewrite rkspi_set_clk for a more conservative baudrate setting
On 20 April 2017 at 14:05, Philipp Tomsich wrote: > The baudrate in rkspi was calculated by using an integer division > (which implicitly discarded any fractional result), then rounding to > an even number and finally clamping to 0xfffe using a bitwise AND > operator. This introduced two issues: > 1) for very small baudrates (overflowing the 0xfffe range), the >bitwise-AND generates rather random-looking (wildly varying) >actual output bitrates > 2) for higher baudrates, the calculation tends to 'err towards a >higher baudrate' with the actual error increasing as the dividers >become very small. E.g., with a 99MHz input clock, a request >for a 20MBit baudrate (99/20 = 4.95), a 24.75 MBit would be use >(which amounts to a 23.75% error)... for a 34 MBit request this >would be an actual outbout of 49.5 Mbit (i.e. a 45% error). > > This change rewrites the divider selection (i.e. baudrate calculation) > by making sure that > a) for the normal case: the largest representable baudrate below the >requested rate will be chosen; > b) for the denormal case (i.e. when the divider can no longer be >represented), the lowest representable baudrate is chosen. > > Even though the denormal case (b) may be of little concern in real > world applications (even with a 198MHz input clock, this will only > happen at below approx. 3kHz/3kBit), our board-verification team kept > complaining. > > Signed-off-by: Philipp Tomsich > Tested-by: Klaus Goger > --- > > Changes in v4: > - added in v4 after receiving complaints from the board-verification > team > > Changes in v3: None > Changes in v2: None > > drivers/spi/rk_spi.c | 25 ++--- > 1 file changed, 22 insertions(+), 3 deletions(-) Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/5] rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO
On 16 April 2017 at 13:34, Simon Glass wrote: > On 16 April 2017 at 03:44, Ziyuan Xu wrote: >> The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for >> it. >> >> Signed-off-by: Ziyuan Xu >> --- >> >> drivers/clk/rockchip/clk_rk3188.c | 12 >> 1 file changed, 12 insertions(+) > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 5/7] rockchip: pinctrl: rk3399: add support for the SPI5 controller
On 20 April 2017 at 14:05, Philipp Tomsich wrote: > This commit adds support for the pin-configuration of the SPI5 > controller of the RK3399 through the following changes: > * grf_rk3399.h: adds definition for configuring the SPI5 pins > in the GPIO2C group > * periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5 > * pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to > PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3 > through SPI5 to the appropriate pin-config > function; implements the pin-configuration > for PERIPH_ID_SPI5 using the GPIO2C group > > X-AffectedPlatforms: RK3399-Q7 > Signed-off-by: Philipp Tomsich > Tested-by: Jakob Unterwurzacher > Acked-by: Simon Glass > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12 > arch/arm/include/asm/arch-rockchip/periph.h | 3 +++ > drivers/pinctrl/rockchip/pinctrl_rk3399.c | 17 + > 3 files changed, 32 insertions(+) > Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 7/8] rockchip: mkimage: remove placeholder functions from rkimage
On 17 April 2017 at 22:00, Simon Glass wrote: > On 17 April 2017 at 09:48, Philipp Tomsich > wrote: >> The imagetool framework checks whether function pointer for the verify, >> print and extract actions are available and will will handle their >> absence appropriately. >> >> This change removes the unnecessary functions and uses the driver >> structure to convey available functionality to imagetool. This is in >> fact better than having verify just return 0 (which previously broke >> dumpimage, as dumpimage assumed that we had handled the image and did >> not continue to probe further). >> >> Signed-off-by: Philipp Tomsich >> --- >> >> tools/rkimage.c | 21 +++-- >> 1 file changed, 3 insertions(+), 18 deletions(-) > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] rockchip: dts: evb-rk3399: correct pwm3 polarity
On 18 April 2017 at 03:06, Kever Yang wrote:
> The pwm3 on evb-rk3399 is used for pwm regulator, need to invert
> the polarity to make it work correctly.
>
> Signed-off-by: Kever Yang
> Acked-by: Simon Glass
> ---
>
> Changes in v2:
> - commit message description fix
>
> arch/arm/dts/rk3399-evb.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
> index d2ded77..b01ce1e 100644
> --- a/arch/arm/dts/rk3399-evb.dts
> +++ b/arch/arm/dts/rk3399-evb.dts
> @@ -20,7 +20,7 @@
>
> vdd_center: vdd-center {
> compatible = "pwm-regulator";
> - pwms = <&pwm3 0 25000 0>;
> + pwms = <&pwm3 0 25000 1>;
> regulator-name = "vdd_center";
> regulator-min-microvolt = <80>;
> regulator-max-microvolt = <140>;
> --
> 1.9.1
>
Applied to u-boot-rockchip/next, thanks!
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Re: [U-Boot] [PATCH v1 1/8] rockchip: mkimage: rkspi: include the header sector in the SPI size calculation
On 17 April 2017 at 22:00, Simon Glass wrote: > On 17 April 2017 at 09:48, Philipp Tomsich > wrote: >> >> Our earlier change broke the generation of SPI images, by excluding the >> 2K used for header0 from the size-calculation. >> >> This commit makes sure that these are included before calculating the >> required total size (including the padding from the 2K-from-every-4K >> conversion). >> >> Signed-off-by: Philipp Tomsich >> --- >> >> tools/rkspi.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 2/2] rockchip: dts: rk3399-puma: Add DDR3-1600 timings and use for Puma
On 17 April 2017 at 22:01, Simon Glass wrote: > On 17 April 2017 at 09:50, Philipp Tomsich > wrote: >> With the validation done for DDR3-1600 (i.e. 800 MHz bus clock), we >> add the timings (rk3399-sdram-ddr3-1600.dtsi) and change rk3399-puma.dts >> to use these by default. >> >> Signed-off-by: Philipp Tomsich >> >> --- >> >> arch/arm/dts/rk3399-puma.dts | 6 +- >> arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi | 1537 >> ++ >> 2 files changed, 1542 insertions(+), 1 deletion(-) >> create mode 100644 arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 4/8] rockchip: mkimage: rksd: pad SD/MMC images to a full blocksize
On 17 April 2017 at 22:00, Simon Glass wrote: > On 17 April 2017 at 09:48, Philipp Tomsich > wrote: > > Commit message? > >> Signed-off-by: Philipp Tomsich >> --- >> >> tools/rksd.c | 7 +-- >> 1 file changed, 5 insertions(+), 2 deletions(-) >> > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 6/7] rockchip: spi: enable support for the rk_spi driver for the RK3399
On 20 April 2017 at 14:05, Philipp Tomsich wrote: > From: Jakob Unterwurzacher > > The existing Rockchip SPI (rk_spi.c) driver also matches the hardware > block found in the RK3399. This has been confirmed both with SPI NOR > flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5. > > This change adds the 'rockchip,rk3399-spi' string to its compatible > list to allow reuse of the existing driver. > > X-AffectedPlatforms: RK3399-Q7 > Signed-off-by: Philipp Tomsich > Tested-by: Jakob Unterwurzacher > Acked-by: Simon Glass > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > drivers/spi/rk_spi.c | 1 + > 1 file changed, 1 insertion(+) Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 3/8] rockchip: mkimage: Update comments for header size
On 17 April 2017 at 22:00, Simon Glass wrote: > On 17 April 2017 at 09:48, Philipp Tomsich > wrote: >> The calculation of the variable header size in rkcommon_vrec_header >> had been update twice in the earlier series (introducing boot0-style >> images to deal with the alignment of the first instruction in 64bit >> binaries). Unfortunately, I didn't update the comment twice (so it >> remained out-of-date). >> >> This change brings the comment back in-sync with what the code is >> doing. >> >> Signed-off-by: Philipp Tomsich >> --- >> >> tools/rkcommon.c | 22 +- >> 1 file changed, 13 insertions(+), 9 deletions(-) >> > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/2] rockchip: video: Makefile: Modify Makefile for rockchip video driver
On 17 April 2017 at 21:59, Simon Glass wrote: > On 17 April 2017 at 08:24, Eric Gao wrote: >> Modify Makefile for rockchip video driver according to Kconfig, so that >> source code will not be compiled if not needed. >> >> Signed-off-by: Eric Gao >> --- >> >> drivers/video/rockchip/Makefile | 7 ++- >> 1 file changed, 6 insertions(+), 1 deletion(-) >> > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/5] rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO
On 16 April 2017 at 13:34, Simon Glass wrote: > On 16 April 2017 at 03:44, Ziyuan Xu wrote: >> The genunie bus clock is sclk_x for eMMC/SDIO, add support for it. >> >> Signed-off-by: Ziyuan Xu >> --- >> >> drivers/clk/rockchip/clk_rk3036.c | 5 + >> 1 file changed, 5 insertions(+) > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 7/7] rockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for SPL
On 20 April 2017 at 14:05, Philipp Tomsich wrote: > To include the ability to load from an SPI flash in SPL, it's not > sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via > Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support > is already enabled for SPL via Kconfig. > > Signed-off-by: Philipp Tomsich > Acked-by: Simon Glass > > --- > > Changes in v4: > - changed rk3399_common.h to allow a per-board SPI config through > defconfig (previously a stand-along patch, now part of the series) > > Changes in v3: None > Changes in v2: None > > include/configs/rk3399_common.h | 3 +++ > 1 file changed, 3 insertions(+) Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/5] rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO
On 16 April 2017 at 13:34, Simon Glass wrote: > On 16 April 2017 at 03:44, Ziyuan Xu wrote: >> The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for >> it. >> >> Signed-off-by: Ziyuan Xu >> --- >> >> drivers/clk/rockchip/clk_rk3288.c | 12 >> 1 file changed, 12 insertions(+) > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] rockchip: rk3399: correct memory region
On 17 April 2017 at 21:58, Simon Glass wrote: > On 17 April 2017 at 02:42, Kever Yang wrote: >> RK3399 device memory region is 0xf800~0x. >> >> Signed-off-by: Kever Yang >> --- >> >> arch/arm/mach-rockchip/rk3399/rk3399.c | 8 >> 1 file changed, 4 insertions(+), 4 deletions(-) > > Reviewed-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 5/8] rockchip: mkimage: clarify header0 initialisation
On 17 April 2017 at 22:00, Simon Glass wrote: > On 17 April 2017 at 09:48, Philipp Tomsich > wrote: >> This change set adds documentation to the header0 initialisation and >> improves readability for the calculations of various offsets/lengths. >> >> As the U-Boot SPL stage doesn't use any payload beyond what is covered >> by init_size, we no longer add RK_MAX_BOOT_SIZE to init_boot_size. >> >> Signed-off-by: Philipp Tomsich >> --- >> >> tools/rkcommon.c | 20 +--- >> 1 file changed, 17 insertions(+), 3 deletions(-) > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] rockchip: rk3399: use actual dram size
On 19 April 2017 at 02:01, Kever Yang wrote: > Since our sdram driver is ready, we can use the actual size > instead of hard code. > > Signed-off-by: Kever Yang > Acked-by: Simon Glass > --- > > Changes in v2: > - fix compile warning of print type not match > > arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 8 > board/rockchip/evb_rk3399/evb-rk3399.c | 19 ++- > 2 files changed, 22 insertions(+), 5 deletions(-) Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] rockchip: video: Kconfig: Add Kconfig for rockchip video driver
On 17 April 2017 at 21:59, Simon Glass wrote: > On 17 April 2017 at 08:24, Eric Gao wrote: >> 1. add Kconfig for rockchip video driver, so that video port can be >> selected as needed. >> 2. move VIDEO_ROCKCHIP option to new Kconfig for concision. >> >> Signed-off-by: Eric Gao >> >> --- >> >> configs/chromebit_mickey_defconfig | 1 + >> configs/chromebook_jerry_defconfig | 2 ++ >> configs/chromebook_minnie_defconfig | 2 ++ >> configs/firefly-rk3288_defconfig | 1 + >> configs/miqi-rk3288_defconfig | 1 + >> configs/rock2_defconfig | 1 + >> drivers/video/Kconfig | 10 + >> drivers/video/rockchip/Kconfig | 43 + >> 8 files changed, 52 insertions(+), 9 deletions(-) >> create mode 100644 drivers/video/rockchip/Kconfig > > Acked-by: Simon Glass Dropped indenting, as this defeats the config whitelist, and: Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/7] rockchip: spi: rk_spi: dynamically select an module input rate
On 20 April 2017 at 14:05, Philipp Tomsich wrote: > The original clock/bitrate selection code for the rk_spi driver was a > bit limited, as it always selected a 99MHz input clock rate (which > would allow for a maximum bitrate of 49.5MBit/s), but returned -EINVAL > if a bitrate higher than 48MHz was requested. > > To give us better control over the bitrate (i.e. add more operating > points, especially at "higher" bitrate---such as above 9MBit/s), we > try to choose 4x the maximum frequency (clamped to 50MBit) from the > DTS instead of 99MHz... for most use-cases this will yield a frequency > of 198MHz, but is flexible to go beyond this in future configurations. > > This also rewrites the check to allow frequencies of up to half the > SPI module rate as bitrates and then clamps to whatever the DTS allows > as a maximum (board-specific) frequency and does away with the -EINVAL > when trying to select a bitrate (for cases that exceeded the hard > limit) and instead consistently clamps to the lower of the hard limit, > the soft limit for the SPI bus (from the DTS) or the soft limit for > the SPI slave device. > > This replaces > "rockchip: spi: rk_spi: select 198MHz input to the SPI module for the > RK3399" > "rockchip: spi: rk_spi: improve clocking code for the RK3399" > from earlier versions of this series. > > Signed-off-by: Philipp Tomsich > > --- > > Changes in v4: > - rewrite to not introduce a chip-specific define, add a dynamic > module input rate selection and unify the bitrate handling for hard > and soft limits. > (replaces 2 earlier commits mentioned in the commit message) > > Changes in v3: None > Changes in v2: None > > drivers/spi/rk_spi.c | 36 +--- > drivers/spi/rk_spi.h | 9 - > 2 files changed, 37 insertions(+), 8 deletions(-) Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/7] rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5
On 20 April 2017 at 14:05, Philipp Tomsich wrote: > This change adds support for configuring the module clocks for SPI1 and > SPI5 from the 594MHz GPLL. > > Note that the driver (rk_spi.c) always sets this to 99MHz, but the > implemented functionality is more general and will also support > different clock configurations. > > X-AffectedPlatforms: RK3399-Q7 > Signed-off-by: Philipp Tomsich > Tested-by: Jakob Unterwurzacher > Tested-by: Klaus Goger > Acked-by: Simon Glass > > --- > > Changes in v4: None > Changes in v3: > - replaced macro-pasting with a lookup table to improve readability > (as suggested by Simon) > > Changes in v2: > - fixes a wrong macro usage, which caused the SPI module input clock > frequency to be significantly higher than intended > - frequencies have now been validated using an oscilloscope (keep in mind > that all frequencies are derived from a 99MHz module input clock) at the > following measurement points (assuming the other fix for the usage of > DIV_RATE from the series): > * 1 MHz ... 0.99 MHz > * 5 MHz ... 4.95 MHz > * 10 MHz ... 9.9 MHz > * 30 MHz ... 33MHz > * 50 MHz ... 49.5 MHz > > drivers/clk/rockchip/clk_rk3399.c | 112 > -- > 1 file changed, 106 insertions(+), 6 deletions(-) > Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 2/8] rockchip: mkimage: rewrite padding calculation for SD/MMC and SPI images
On 17 April 2017 at 22:00, Simon Glass wrote: > On 17 April 2017 at 09:48, Philipp Tomsich > wrote: >> In (first) breaking and (then) fixing the rkspi tool, I realised that >> the calculation of the required padding (for the header-size and the >> 2K-in-every-4K SPI layout) was not as self-explainatory as it could >> have been. This change rewrites the code (using new, common functions >> in rkcommon.c) and adds verbose in-line comments to ensure that we >> won't fall into the same pit in the future... >> >> Tested on the RK3399 (with has a boot0-style payload) with SD/MMC and SPI. >> >> Signed-off-by: Philipp Tomsich >> --- >> >> tools/rkcommon.c | 20 ++-- >> tools/rkcommon.h | 10 -- >> tools/rksd.c | 23 --- >> tools/rkspi.c | 41 +++-- >> 4 files changed, 65 insertions(+), 29 deletions(-) >> > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 2/7] rockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate
On 20 April 2017 at 14:05, Philipp Tomsich wrote: > For the RK3399, i2c_set_rate (and by extension: our spi_set_rate, > which had been mindlessly following the template of the i2c_set_rate > implementation) miscalculates the rate returned due to a off-by-one > error resulting from the following sequence of events: > 1. calculates 'src_div := src_freq / target_freq' > 2. stores 'src_div - 1' into the register (the actual divider applied > in hardware is biased by adding 1) > 3. returns the result of the DIV_RATE(src_freq, src_div) macro, which > expects the (decremented) divider from the hardware-register and > implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)') > > This can be observed with the SPI driver, which sets a rate of 99MHz > based on the GPLL frequency of 594MHz: the hardware generates a clock > of 99MHz (src_div is 6, the bitfield in the register correctly reads 5), > but reports a frequency of 84MHz (594 / 7) on return. > > To fix, we have two options: > * either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't >make for a particularily nice read > * we simply call the i2c/spi_get_rate function (introducing additional >overhead for the additional register-read), which reads the divider >from the register and then passes it through the DIV_RATE macro > > Given that this code is not time-critical, the more readable solution > (i.e. calling the appropriate get_rate function) is implemented in this > change. > > Signed-off-by: Philipp Tomsich > Tested-by: Klaus Goger > Acked-by: Simon Glass > > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: > - fixes an off-by-one for the RK3399 that cause the SPI module input > clock to be misstated as 84MHz (even though it was running at 99MHz) > > drivers/clk/rockchip/clk_rk3399.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC
On 16 April 2017 at 13:34, Simon Glass wrote: > On 16 April 2017 at 03:44, Ziyuan Xu wrote: >> The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it. >> >> Signed-off-by: Ziyuan Xu >> --- >> >> drivers/clk/rockchip/clk_rk3328.c | 8 >> 1 file changed, 8 insertions(+) > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] rockchip: rk3399: use regulators_enable_boot_on() to init regulator
On 16 April 2017 at 13:30, Simon Glass wrote: > On 11 April 2017 at 22:00, Kever Yang wrote: >> Use regulators_enable_boot_on() instead of init regulators one by one, >> the interface can init all the regulators with regulator-boot-on property. >> >> Signed-off-by: Kever Yang >> --- >> >> board/rockchip/evb_rk3399/evb-rk3399.c | 5 ++--- >> 1 file changed, 2 insertions(+), 3 deletions(-) > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/7] rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5
On 17 April 2017 at 21:59, Simon Glass wrote: > On 17 April 2017 at 09:43, Philipp Tomsich > wrote: >> This change adds support for configuring the module clocks for SPI1 and >> SPI5 from the 594MHz GPLL. >> >> Note that the driver (rk_spi.c) always sets this to 99MHz, but the >> implemented functionality is more general and will also support >> different clock configurations. >> >> X-AffectedPlatforms: RK3399-Q7 >> Signed-off-by: Philipp Tomsich >> Tested-by: Jakob Unterwurzacher >> >> Tested-by: Klaus Goger >> >> Cover-Letter: > > Odd that this came through - is it the capital L? > > >> rockchip: spi: rk3399: add SPI support for the RK3399 >> >> This series adds SPI support for the RK3399 (SPI1 and SPI5). This >> consists of the following individual changes: >> - clock support for the SPI blocks clocked from GRF (i.e. SPI1, SPI2, >> SPI 4 and SPI5) >> - pinctrl for SPI1 and SPI5 >> - changes the SPI module input clock to 198MHz (instead of 99MHz) for >> the RK3399 to improve the available bitrates at higher frequencies >> (e.g. adding the 39MBit and 28MBit operating points) >> - modifies the calculation of the top frequency permissible (as the >> 49.5MBit operating point had not been permissible due to a hard >> limit at 48MBit) >> END >> >> --- >> >> Changes in v3: >> - replaced macro-pasting with a lookup table to improve readability >> (as requested by Simon) >> >> Changes in v2: >> - fixes a wrong macro usage, which caused the SPI module input clock >> frequency to be significantly higher than intended >> - frequencies have now been validated using an oscilloscope (keep in mind >> that all frequencies are derived from a 99MHz module input clock) at the >> following measurement points (assuming the other fix for the usage of >> DIV_RATE from the series): >> * 1 MHz ... 0.99 MHz >> * 5 MHz ... 4.95 MHz >> * 10 MHz ... 9.9 MHz >> * 30 MHz ... 33 MHz >> * 50 MHz ... 49.5 MHz >> >> drivers/clk/rockchip/clk_rk3399.c | 114 >> -- >> 1 file changed, 108 insertions(+), 6 deletions(-) > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] mmc: dw_mmc: rockchip: select proper card clock
On 16 April 2017 at 13:34, Simon Glass wrote: > On 16 April 2017 at 03:44, Ziyuan Xu wrote: >> As you know, biu_clk is used for AMBA AHB/APB interface, ciu_clk is >> used for communication between host and card devices. The real bus clock >> is ciu, so let's rectify it. >> >> Signed-off-by: Ziyuan Xu >> --- >> >> drivers/mmc/rockchip_dw_mmc.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] mkimage: rockchip: add support for rk3328
On 16 April 2017 at 13:33, Simon Glass wrote: > On 14 April 2017 at 00:55, Kever Yang wrote: >> Add support for rk3328 package header in mkimage tool. >> >> Signed-off-by: Kever Yang >> --- >> >> tools/rkcommon.c | 1 + >> 1 file changed, 1 insertion(+) >> > > Reviewed-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] rockchip: tinker: set ethaddr in late init
Hi Jonas,
On 20 April 2017 at 12:23, Jonas Karlman wrote:
> Set ethernet mac address in late init for Tinker Board,
> prevents getting a random mac address each boot.
>
> Read mac address from eeprom, first 6 bytes from m24c08@50.
> Same as /etc/init.d/rockchip.sh on Tinker OS.
>
> Signed-off-by: Jonas Karlman
> ---
>
> Changes in v2:
> - Change to use i2c_eeprom device driver
>
> arch/arm/dts/rk3288-tinker.dts | 7 ++
> board/rockchip/tinker_rk3288/tinker-rk3288.c | 33
>
> configs/tinker-rk3288_defconfig | 3 +++
> 3 files changed, 43 insertions(+)
>
> diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm/dts/rk3288-tinker.dts
> index 22881cb785..ea2f715922 100644
> --- a/arch/arm/dts/rk3288-tinker.dts
> +++ b/arch/arm/dts/rk3288-tinker.dts
> @@ -67,3 +67,10 @@
> &gpio8 {
> u-boot,dm-pre-reloc;
> };
> +
> +&i2c2 {
> +m24c08@50 {
> +compatible = "at,24c08", "i2c-eeprom";
> +reg = <0x50>;
> +};
> +};
> diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c
> b/board/rockchip/tinker_rk3288/tinker-rk3288.c
> index 79541a3939..e0e8744599 100644
> --- a/board/rockchip/tinker_rk3288/tinker-rk3288.c
> +++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c
> @@ -5,3 +5,36 @@
> */
>
> #include
> +#include
> +#include
> +#include
> +
> +static int get_ethaddr_from_eeprom(u8 *addr)
> +{
> + int ret;
> + struct udevice *dev;
> + const struct i2c_eeprom_ops *ops;
> +
> + ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "m24c08@50", &dev);
Can you use uclass_first_device_err()? There is probably only one I2C
eeprom on the board.
> + if (ret)
> + return ret;
> +
> + ops = device_get_ops(dev);
> + if (!ops->read)
> + return -ENOSYS;
> +
> + return ops->read(dev, 0x0, addr, 6);
Unfortunately there is no exported i2c_eeprom_read() / write()
functions, but there should be. Can you please add these to
i2c_eeprom.c in a separate patch? The functions should call the
operation, since things outside a uclass should not access the
operations directly.
The new functions should be declared in the header file too. See pch.h
for an example of how to do that.
Then you can call that here.
Sorry for the extra work.
> +}
> +
> +int rk_board_late_init(void)
> +{
> + u8 ethaddr[6];
> +
> + if (get_ethaddr_from_eeprom(ethaddr))
> + return 0;
> +
> + if (is_valid_ethaddr(ethaddr))
> + eth_setenv_enetaddr("ethaddr", ethaddr);
> +
> + return 0;
> +}
> diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
> index cec39384b3..dc3699d5c4 100644
> --- a/configs/tinker-rk3288_defconfig
> +++ b/configs/tinker-rk3288_defconfig
> @@ -11,6 +11,7 @@ CONFIG_CONSOLE_MUX=y
> # CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> +CONFIG_SPL_I2C_SUPPORT=y
> # CONFIG_CMD_IMLS is not set
> CONFIG_CMD_GPT=y
> CONFIG_CMD_MMC=y
> @@ -39,6 +40,8 @@ CONFIG_CLK=y
> CONFIG_SPL_CLK=y
> CONFIG_ROCKCHIP_GPIO=y
> CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_MISC=y
> +CONFIG_I2C_EEPROM=y
> CONFIG_MMC_DW=y
> CONFIG_MMC_DW_ROCKCHIP=y
> CONFIG_DM_ETH=y
> --
> 2.11.0
>
Regards,
Simon
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Re: [U-Boot] [PATCH 1/2] rockchip: config: rk3399: clean with make savedefconfig
On 16 April 2017 at 13:30, Simon Glass wrote: > On 11 April 2017 at 21:54, Kever Yang wrote: >> Clean the evb-rk3399_defconfig with make savedefconfig. >> >> Signed-off-by: Kever Yang >> --- >> >> configs/evb-rk3399_defconfig | 14 +- >> 1 file changed, 5 insertions(+), 9 deletions(-) >> > > Acked-by: Simon Glass Applied to u-boot-rockchip/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 5/7] rockchip: pinctrl: rk3399: add support for the SPI5 controller
This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
* grf_rk3399.h: adds definition for configuring the SPI5 pins
in the GPIO2C group
* periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
* pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
through SPI5 to the appropriate pin-config
function; implements the pin-configuration
for PERIPH_ID_SPI5 using the GPIO2C group
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich
Tested-by: Jakob Unterwurzacher
Acked-by: Simon Glass
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12
arch/arm/include/asm/arch-rockchip/periph.h | 3 +++
drivers/pinctrl/rockchip/pinctrl_rk3399.c | 17 +
3 files changed, 32 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index c424753..cbcff2e 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -344,6 +344,18 @@ enum {
GRF_GPIO2C1_SEL_SHIFT = 2,
GRF_GPIO2C1_SEL_MASK= 3 << GRF_GPIO2C1_SEL_SHIFT,
GRF_UART0BT_SOUT= 1,
+ GRF_GPIO2C4_SEL_SHIFT = 8,
+ GRF_GPIO2C4_SEL_MASK= 3 << GRF_GPIO2C4_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_RXD = 2,
+ GRF_GPIO2C5_SEL_SHIFT = 10,
+ GRF_GPIO2C5_SEL_MASK= 3 << GRF_GPIO2C5_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_TXD = 2,
+ GRF_GPIO2C6_SEL_SHIFT = 12,
+ GRF_GPIO2C6_SEL_MASK= 3 << GRF_GPIO2C6_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_CLK = 2,
+ GRF_GPIO2C7_SEL_SHIFT = 14,
+ GRF_GPIO2C7_SEL_MASK= 3 << GRF_GPIO2C7_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_CSN0= 2,
/* GRF_GPIO3A_IOMUX */
GRF_GPIO3A0_SEL_SHIFT = 0,
diff --git a/arch/arm/include/asm/arch-rockchip/periph.h
b/arch/arm/include/asm/arch-rockchip/periph.h
index 239a274..8018d47 100644
--- a/arch/arm/include/asm/arch-rockchip/periph.h
+++ b/arch/arm/include/asm/arch-rockchip/periph.h
@@ -27,6 +27,9 @@ enum periph_id {
PERIPH_ID_SPI0,
PERIPH_ID_SPI1,
PERIPH_ID_SPI2,
+ PERIPH_ID_SPI3,
+ PERIPH_ID_SPI4,
+ PERIPH_ID_SPI5,
PERIPH_ID_UART0,
PERIPH_ID_UART1,
PERIPH_ID_UART2,
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index 507bec4..6eb657f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -145,7 +145,19 @@ static int pinctrl_rk3399_spi_config(struct
rk3399_grf_regs *grf,
| GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
| GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
break;
+ case PERIPH_ID_SPI5:
+ if (cs != 0)
+ goto err;
+ rk_clrsetreg(&grf->gpio2c_iomux,
+GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
+| GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
+GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
+| GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
+| GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
+| GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
+ break;
default:
+ printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
goto err;
}
@@ -259,6 +271,9 @@ static int rk3399_pinctrl_request(struct udevice *dev, int
func, int flags)
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
case PERIPH_ID_SPI2:
+ case PERIPH_ID_SPI3:
+ case PERIPH_ID_SPI4:
+ case PERIPH_ID_SPI5:
pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
break;
case PERIPH_ID_UART0:
@@ -307,6 +322,8 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
return PERIPH_ID_SPI1;
case 52:
return PERIPH_ID_SPI2;
+ case 132:
+ return PERIPH_ID_SPI5;
case 57:
return PERIPH_ID_I2C0;
case 59: /* Note strange order */
--
1.9.1
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[U-Boot] [PATCH v4 7/7] rockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for SPL
To include the ability to load from an SPI flash in SPL, it's not sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support is already enabled for SPL via Kconfig. Signed-off-by: Philipp Tomsich Acked-by: Simon Glass --- Changes in v4: - changed rk3399_common.h to allow a per-board SPI config through defconfig (previously a stand-along patch, now part of the series) Changes in v3: None Changes in v2: None include/configs/rk3399_common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index b7b89b0..49f56f2 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -18,6 +18,9 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#if defined(CONFIG_SPL_SPI_SUPPORT) +#define CONFIG_SPL_SPI_LOAD +#endif #define COUNTER_FREQUENCY 2400 -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 4/7] rockchip: spi: rewrite rkspi_set_clk for a more conservative baudrate setting
The baudrate in rkspi was calculated by using an integer division
(which implicitly discarded any fractional result), then rounding to
an even number and finally clamping to 0xfffe using a bitwise AND
operator. This introduced two issues:
1) for very small baudrates (overflowing the 0xfffe range), the
bitwise-AND generates rather random-looking (wildly varying)
actual output bitrates
2) for higher baudrates, the calculation tends to 'err towards a
higher baudrate' with the actual error increasing as the dividers
become very small. E.g., with a 99MHz input clock, a request
for a 20MBit baudrate (99/20 = 4.95), a 24.75 MBit would be use
(which amounts to a 23.75% error)... for a 34 MBit request this
would be an actual outbout of 49.5 Mbit (i.e. a 45% error).
This change rewrites the divider selection (i.e. baudrate calculation)
by making sure that
a) for the normal case: the largest representable baudrate below the
requested rate will be chosen;
b) for the denormal case (i.e. when the divider can no longer be
represented), the lowest representable baudrate is chosen.
Even though the denormal case (b) may be of little concern in real
world applications (even with a 198MHz input clock, this will only
happen at below approx. 3kHz/3kBit), our board-verification team kept
complaining.
Signed-off-by: Philipp Tomsich
Tested-by: Klaus Goger
---
Changes in v4:
- added in v4 after receiving complaints from the board-verification
team
Changes in v3: None
Changes in v2: None
drivers/spi/rk_spi.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 0c627d9..050eacb 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -79,12 +79,31 @@ static void rkspi_enable_chip(struct rockchip_spi *regs,
bool enable)
static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
{
- uint clk_div;
+ /*
+* We should try not to exceed the speed requested by the caller:
+* when selecting a divider, we need to make sure we round up.
+*/
+ uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
+
+ /* The baudrate register (BAUDR) is defined as a 32bit register where
+* the upper 16bit are reserved and having 'Fsclk_out' in the lower
+* 16bits with 'Fsclk_out' defined as follows:
+*
+* Fsclk_out = Fspi_clk/ SCKDV
+* Where SCKDV is any even value between 2 and 65534.
+*/
+ if (clk_div > 0xfffe) {
+ clk_div = 0xfffe;
+ debug("%s: can't divide down to %d hz (actual will be %d hz)\n",
+ __func__, speed, priv->input_rate / clk_div);
+ }
+
+ /* Round up to the next even 16bit number */
+ clk_div = (clk_div + 1) & 0xfffe;
- clk_div = clk_get_divisor(priv->input_rate, speed);
debug("spi speed %u, div %u\n", speed, clk_div);
- writel(clk_div, &priv->regs->baudr);
+ clrsetbits_le32(&priv->regs->baudr, 0x, clk_div);
priv->last_speed_hz = speed;
}
--
1.9.1
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[U-Boot] [PATCH v4 3/7] rockchip: spi: rk_spi: dynamically select an module input rate
The original clock/bitrate selection code for the rk_spi driver was a
bit limited, as it always selected a 99MHz input clock rate (which
would allow for a maximum bitrate of 49.5MBit/s), but returned -EINVAL
if a bitrate higher than 48MHz was requested.
To give us better control over the bitrate (i.e. add more operating
points, especially at "higher" bitrate---such as above 9MBit/s), we
try to choose 4x the maximum frequency (clamped to 50MBit) from the
DTS instead of 99MHz... for most use-cases this will yield a frequency
of 198MHz, but is flexible to go beyond this in future configurations.
This also rewrites the check to allow frequencies of up to half the
SPI module rate as bitrates and then clamps to whatever the DTS allows
as a maximum (board-specific) frequency and does away with the -EINVAL
when trying to select a bitrate (for cases that exceeded the hard
limit) and instead consistently clamps to the lower of the hard limit,
the soft limit for the SPI bus (from the DTS) or the soft limit for
the SPI slave device.
This replaces
"rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399"
"rockchip: spi: rk_spi: improve clocking code for the RK3399"
from earlier versions of this series.
Signed-off-by: Philipp Tomsich
---
Changes in v4:
- rewrite to not introduce a chip-specific define, add a dynamic
module input rate selection and unify the bitrate handling for hard
and soft limits.
(replaces 2 earlier commits mentioned in the commit message)
Changes in v3: None
Changes in v2: None
drivers/spi/rk_spi.c | 36 +---
drivers/spi/rk_spi.h | 9 -
2 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 3e44f17..0c627d9 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -190,6 +190,26 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice
*bus)
return 0;
}
+static int rockchip_spi_calc_modclk(ulong max_freq)
+{
+ unsigned div;
+ const unsigned long gpll_hz = 59400UL;
+
+ /*
+* We need to find an input clock that provides at least twice
+* the maximum frequency and can be generated from the assumed
+* speed of GPLL (594MHz) using an integer divider.
+*
+* To give us more achievable bitrates at higher speeds (these
+* are generated by dividing by an even 16-bit integer from
+* this frequency), we try to have an input frequency of at
+* least 4x our max_freq.
+*/
+
+ div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
+ return gpll_hz / div;
+}
+
static int rockchip_spi_probe(struct udevice *bus)
{
struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
@@ -207,11 +227,13 @@ static int rockchip_spi_probe(struct udevice *bus)
priv->last_transaction_us = timer_get_us();
priv->max_freq = plat->frequency;
- /*
-* Use 99 MHz as our clock since it divides nicely into 594 MHz which
-* is the assumed speed for CLK_GENERAL.
-*/
- ret = clk_set_rate(&priv->clk, 9900);
+ /* Clamp the value from the DTS against any hardware limits */
+ if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
+ priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
+
+ /* Find a module-input clock that fits with the max_freq setting */
+ ret = clk_set_rate(&priv->clk,
+ rockchip_spi_calc_modclk(priv->max_freq));
if (ret < 0) {
debug("%s: Failed to set clock: %d\n", __func__, ret);
return ret;
@@ -371,10 +393,10 @@ static int rockchip_spi_set_speed(struct udevice *bus,
uint speed)
{
struct rockchip_spi_priv *priv = dev_get_priv(bus);
- if (speed > ROCKCHIP_SPI_MAX_RATE)
- return -EINVAL;
+ /* Clamp to the maximum frequency specified in the DTS */
if (speed > priv->max_freq)
speed = priv->max_freq;
+
priv->speed_hz = speed;
return 0;
diff --git a/drivers/spi/rk_spi.h b/drivers/spi/rk_spi.h
index f1ac812..02aa9d0 100644
--- a/drivers/spi/rk_spi.h
+++ b/drivers/spi/rk_spi.h
@@ -119,6 +119,13 @@ enum {
};
#define ROCKCHIP_SPI_TIMEOUT_MS1000
-#define ROCKCHIP_SPI_MAX_RATE 4800
+
+/*
+ * We limit the maximum bitrate to 50MBit/s (50MHz) due to an assumed
+ * hardware limitation... the Linux kernel source has the following
+ * comment:
+ * "sclk_out: spi master internal logic in rk3x can support 50Mhz"
+ */
+#define ROCKCHIP_SPI_MAX_RATE 5000
#endif /* __RK_SPI_H */
--
1.9.1
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[U-Boot] [PATCH v4 0/7] rockchip: spi: rk3399: add SPI support for the RK3399
This series adds SPI support for the RK3399 (SPI1 and SPI5). This consists of the following individual changes: - clock support for the SPI blocks clocked from GRF (i.e. SPI1, SPI2, SPI 4 and SPI5) - pinctrl for SPI1 and SPI5 - changes the SPI module input clock to 198MHz (instead of 99MHz) for the RK3399 to improve the available bitrates at higher frequencies (e.g. adding the 39MBit and 28MBit operating points) - modifies the calculation of the top frequency permissible (as the 49.5MBit operating point had not been permissible due to a hard limit at 48MBit) In addition to these changes, the divider calculation for the baudrate is changed to - try hard not to exceed the requested rate (i.e. err towards a lower rate) - not to overflow the divider field (which may result in a very large actual baudrate for very small requested baudrates) To make it easier to track this change set (and avoid me sending patch series with broken cover letters), this now also includes the change to have a per-board SPI config: rockchip: spl: rk3399: prepare to have SPI config per-board To support SPI flashes (via the device model) and enable loading of later-stage images from SPI in SPL, we need a few adjustments to the common configuration header for the RK3399: - enable SPL_SPI_LOAD if SPI is enabled for SPL (in rk3399_common) - move CONFIG_SPI and CONFIG_SPI_FLASH (from rk3399_common) to defconfig Changes in v4: - rewrite to not introduce a chip-specific define, add a dynamic module input rate selection and unify the bitrate handling for hard and soft limits. (replaces 2 earlier commits mentioned in the commit message) - added an more defensive calculation of the baudrate divider after receiving complaints from the board-verification team - changed rk3399_common.h to allow a per-board SPI config through defconfig (previously a stand-along patch, but it slipped into the series at some point and messed up the coverletter of some of the submissions) Changes in v3: - replaced macro-pasting with a lookup table to improve readability (as suggested by Simon) Changes in v2: - fixes a wrong macro usage, which caused the SPI module input clock frequency to be significantly higher than intended - frequencies have now been validated using an oscilloscope (keep in mind that all frequencies are derived from a 99MHz module input clock) at the following measurement points (assuming the other fix for the usage of DIV_RATE from the series): * 1 MHz ... 0.99 MHz * 5 MHz ... 4.95 MHz * 10 MHz ... 9.9 MHz * 30 MHz ... 33MHz * 50 MHz ... 49.5 MHz - fixes an off-by-one for the RK3399 that cause the SPI module input clock to be misstated as 84MHz (even though it was running at 99MHz) Jakob Unterwurzacher (1): rockchip: spi: enable support for the rk_spi driver for the RK3399 Philipp Tomsich (6): rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5 rockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate rockchip: spi: rk_spi: dynamically select an module input rate rockchip: spi: rewrite rkspi_set_clk for a more conservative baudrate setting rockchip: pinctrl: rk3399: add support for the SPI5 controller rockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for SPL arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12 +++ arch/arm/include/asm/arch-rockchip/periph.h | 3 + drivers/clk/rockchip/clk_rk3399.c | 113 ++-- drivers/pinctrl/rockchip/pinctrl_rk3399.c | 17 drivers/spi/rk_spi.c| 62 ++--- drivers/spi/rk_spi.h| 9 +- include/configs/rk3399_common.h | 3 + 7 files changed, 201 insertions(+), 18 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 6/7] rockchip: spi: enable support for the rk_spi driver for the RK3399
From: Jakob Unterwurzacher
The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
block found in the RK3399. This has been confirmed both with SPI NOR
flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.
This change adds the 'rockchip,rk3399-spi' string to its compatible
list to allow reuse of the existing driver.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich
Tested-by: Jakob Unterwurzacher
Acked-by: Simon Glass
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/spi/rk_spi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 050eacb..ea20980 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -444,6 +444,7 @@ static const struct dm_spi_ops rockchip_spi_ops = {
static const struct udevice_id rockchip_spi_ids[] = {
{ .compatible = "rockchip,rk3288-spi" },
+ { .compatible = "rockchip,rk3399-spi" },
{ }
};
--
1.9.1
___
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[U-Boot] [PATCH v4 2/7] rockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate
For the RK3399, i2c_set_rate (and by extension: our spi_set_rate, which had been mindlessly following the template of the i2c_set_rate implementation) miscalculates the rate returned due to a off-by-one error resulting from the following sequence of events: 1. calculates 'src_div := src_freq / target_freq' 2. stores 'src_div - 1' into the register (the actual divider applied in hardware is biased by adding 1) 3. returns the result of the DIV_RATE(src_freq, src_div) macro, which expects the (decremented) divider from the hardware-register and implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)') This can be observed with the SPI driver, which sets a rate of 99MHz based on the GPLL frequency of 594MHz: the hardware generates a clock of 99MHz (src_div is 6, the bitfield in the register correctly reads 5), but reports a frequency of 84MHz (594 / 7) on return. To fix, we have two options: * either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't make for a particularily nice read * we simply call the i2c/spi_get_rate function (introducing additional overhead for the additional register-read), which reads the divider from the register and then passes it through the DIV_RATE macro Given that this code is not time-critical, the more readable solution (i.e. calling the appropriate get_rate function) is implemented in this change. Signed-off-by: Philipp Tomsich Tested-by: Klaus Goger Acked-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: - fixes an off-by-one for the RK3399 that cause the SPI module input clock to be misstated as 84MHz (even though it was running at 99MHz) drivers/clk/rockchip/clk_rk3399.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index da62757..ac658b9 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -606,7 +606,7 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) return -EINVAL; } - return DIV_TO_RATE(GPLL_HZ, src_clk_div); + return rk3399_i2c_get_clk(cru, clk_id); } /* @@ -695,8 +695,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) ((src_clk_div << spiclk->div_shift) | (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); - - return DIV_TO_RATE(GPLL_HZ, src_clk_div); + return rk3399_spi_get_clk(cru, clk_id); } static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 1/7] rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5
This change adds support for configuring the module clocks for SPI1 and
SPI5 from the 594MHz GPLL.
Note that the driver (rk_spi.c) always sets this to 99MHz, but the
implemented functionality is more general and will also support
different clock configurations.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich
Tested-by: Jakob Unterwurzacher
Tested-by: Klaus Goger
Acked-by: Simon Glass
---
Changes in v4: None
Changes in v3:
- replaced macro-pasting with a lookup table to improve readability
(as suggested by Simon)
Changes in v2:
- fixes a wrong macro usage, which caused the SPI module input clock
frequency to be significantly higher than intended
- frequencies have now been validated using an oscilloscope (keep in mind
that all frequencies are derived from a 99MHz module input clock) at the
following measurement points (assuming the other fix for the usage of
DIV_RATE from the series):
* 1 MHz ... 0.99 MHz
* 5 MHz ... 4.95 MHz
* 10 MHz ... 9.9 MHz
* 30 MHz ... 33MHz
* 50 MHz ... 49.5 MHz
drivers/clk/rockchip/clk_rk3399.c | 112 --
1 file changed, 106 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index f778ddf..da62757 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1,5 +1,6 @@
/*
* (C) Copyright 2015 Google, Inc
+ * (C) 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier:GPL-2.0
*/
@@ -207,12 +208,15 @@ enum {
DCLK_VOP_DIV_CON_SHIFT = 0,
/* CLKSEL_CON58 */
- CLK_SPI_PLL_SEL_MASK= 1,
- CLK_SPI_PLL_SEL_CPLL= 0,
- CLK_SPI_PLL_SEL_GPLL= 1,
- CLK_SPI_PLL_DIV_CON_MASK= 0x7f,
- CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
- CLK_SPI5_PLL_SEL_SHIFT = 15,
+ CLK_SPI_PLL_SEL_WIDTH = 1,
+ CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
+ CLK_SPI_PLL_SEL_CPLL = 0,
+ CLK_SPI_PLL_SEL_GPLL = 1,
+ CLK_SPI_PLL_DIV_CON_WIDTH = 7,
+ CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
+
+ CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
+ CLK_SPI5_PLL_SEL_SHIFT = 15,
/* CLKSEL_CON59 */
CLK_SPI1_PLL_SEL_SHIFT = 15,
@@ -605,6 +609,96 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru,
ulong clk_id, uint hz)
return DIV_TO_RATE(GPLL_HZ, src_clk_div);
}
+/*
+ * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
+ * to select either CPLL or GPLL as the clock-parent. The location within
+ * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
+ */
+
+struct spi_clkreg {
+ uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
+ uint8_t div_shift;
+ uint8_t sel_shift;
+};
+
+/*
+ * The entries are numbered relative to their offset from SCLK_SPI0.
+ *
+ * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
+ * logic is not supported).
+ */
+static const struct spi_clkreg spi_clkregs[] = {
+ [0] = { .reg = 59,
+ .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
+ .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
+ [1] = { .reg = 59,
+ .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
+ .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
+ [2] = { .reg = 60,
+ .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
+ .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
+ [3] = { .reg = 60,
+ .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
+ .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
+ [4] = { .reg = 58,
+ .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
+ .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
+};
+
+static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
+{
+ return (val >> shift) & ((1 << width) - 1);
+}
+
+static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
+{
+ const struct spi_clkreg *spiclk = NULL;
+ u32 div, val;
+
+ switch (clk_id) {
+ case SCLK_SPI0 ... SCLK_SPI5:
+ spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
+ break;
+
+ default:
+ error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
+ return -EINVAL;
+ }
+
+ val = readl(&cru->clksel_con[spiclk->reg]);
+ div = extract_bits(val, CLK_SPI_PLL_DIV_CON_WIDTH, spiclk->div_shift);
+
+ return DIV_TO_RATE(GPLL_HZ, div);
+}
+
+static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
+{
+ const struct spi_clkreg *spiclk = NULL;
+ int src_clk_div;
+
+ src_clk_div = RATE_TO_DIV(GPLL_HZ, hz);
+ assert(src_clk_div < 127);
+
+ switch (clk_id) {
+ case SCLK_SPI1 ... SCLK_SPI5:
+ spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
+ break;
+
Re: [U-Boot] [PATCH v3 01/15] cmd: cpu: fix NULL cpu feature prints
On Tue, Apr 18, 2017 at 10:38:30PM +0200, Álvaro Fernández Rojas wrote: > Commit 740d5d3 added two new features but only one feature name, > which results in NULL prints when device_id feature is selected. > > Before: > HG556a # cpu detail >-1: cpu@0 BCM6358A1 > ID = 0, freq = 300 MHz: L1 cache, MMU, NULL > Device ID 0x2a010 >-1: cpu@1 BCM6358A1 > ID = 1, freq = 300 MHz: L1 cache, MMU, NULL > Device ID 0x2a010 > After: > HG556a # cpu detail >-1: cpu@0 BCM6358A1 > ID = 0, freq = 300 MHz: L1 cache, MMU, Device ID > Device ID 0x2a010 >-1: cpu@1 BCM6358A1 > ID = 1, freq = 300 MHz: L1 cache, MMU, Device ID > Device ID 0x2a010 > > Signed-off-by: Álvaro Fernández Rojas > Reviewed-by: Simon Glass Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 4/4] u-boot.elf: add quiet_cmd_u-boot-elf and cmd_u-boot-elf
On Thu, Apr 20, 2017 at 08:36:28PM +0200, Álvaro Fernández Rojas wrote: > This way we can see output about u-boot.elf being built or not. > > Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 13/16] arm: socfpga: Add SPL support for Arria 10
On Thu, 2017-04-20 at 07:12 -0700, Dalon Westergreen wrote:
> On Wed, 2017-04-19 at 23:58 -0500, Dinh Nguyen wrote:
> >
> > On Wed, Apr 19, 2017 at 6:21 PM, Dalon Westergreen
> > wrote:
> > >
> > >
> > > On Wed, 2017-04-19 at 13:54 -0700, Dalon Westergreen wrote:
> > > >
> > > >
> > > > On Wed, 2017-04-19 at 15:44 -0500, Dinh Nguyen wrote:
> > > > >
> > > > >
> > > > >
> > > > > Really including Dalon
> > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen
> > > > > > wrote:
> > > > > > CC: Dalon Westergreen
> > > > > >
> > > > > > On 04/19/2017 02:49 PM, Dinh Nguyen wrote:
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > On 04/19/2017 04:29 AM, Ley Foon Tan wrote:
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > > Add SPL support for Arria 10.
> > > > > > > >
> > > > > > > > >
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > > >
> > > > > > > > > > > >
> > > > > > > > > > > >
> > > > > > > > > > > > Signed-off-by: Tien Fong Chee
> > > > > > > > > > > > Signed-off-by: Ley Foon Tan
> > > > > > > > ---
> > > > > > > > >
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > > >
> > > > > > > > > > > >
> > > > > > > > > > > >
> > > > > > > > > > > > arch/arm/mach-socfpga/spl.c | 72
> > > > +
> > > > >
> > > > >
> > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > > 1 file changed, 67 insertions(+), 5 deletions(-)
> > > > > > > >
> > > > > > > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > > > > > > > socfpga/spl.c
> > > > > > > > index 0064fc8..f4a3cdd 100644
> > > > > > > > --- a/arch/arm/mach-socfpga/spl.c
> > > > > > > > +++ b/arch/arm/mach-socfpga/spl.c
> > > > > > > > @@ -19,23 +19,32 @@
> > > > > > > > #include
> > > > > > > > #include
> > > > > > > > #include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > > > > > +#include
> > > > > > > > +#endif
> > > > > > > >
> > > > > > > > DECLARE_GLOBAL_DATA_PTR;
> > > > > > > >
> > > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > > > > static struct pl310_regs *const pl310 =
> > > > > > > > (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > > > > > > > static struct scu_registers *scu_regs =
> > > > > > > > (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> > > > > > > > static struct nic301_registers *nic301_regs =
> > > > > > > > (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > > > > > > > -static struct socfpga_system_manager *sysmgr_regs =
> > > > > > > > +#endif
> > > > > > > > +
> > > > > > > > +static const struct socfpga_system_manager *sysmgr_regs =
> > > > > > > > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > > > > > > >
> > > > > > > > u32 spl_boot_device(void)
> > > > > > > > {
> > > > > > > > const u32 bsel = readl(&sysmgr_regs->bootinfo);
> > > > > > > >
> > > > > > > > -switch (bsel & 0x7) {
> > > > > > > > +switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
> > > > > > > > case 0x1: /* FPGA (HPS2FPGA Bridge) */
> > > > > > > > return BOOT_DEVICE_RAM;
> > > > > > > > case 0x2: /* NAND Flash (1.8V) */
> > > > > > > > @@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
> > > > > > > > }
> > > > > > > > #endif
> > > > > > > >
> > > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > > > > static void socfpga_nic301_slave_ns(void)
> > > > > > > > {
> > > > > > > > writel(0x1, &nic301_regs->lwhps2fpgaregs);
> > > > > > > > @@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
> > > > > > > > #endif
> > > > > > > > unsigned long sdram_size;
> > > > > > > > unsigned long reg;
> > > > > > > > +int ret;
> > > > > > > >
> > > > > > > > /*
> > > > > > > > * First C code to run. Clear fake OCRAM ECC first as SBE
> > > > > > > > @@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
> > > > > > > > /* Put everything into reset but L4WD0. */
> > > > > > > > socfpga_per_reset_all();
> > > > > > > > /* Put FPGA bridges into reset too. */
> > > > > > > > -socfpga_bridges_reset(1);
> > > > > > > > +ret = socfpga_bridges_reset(1);
> > > > > > > > +if (ret) {
> > > > > > > > +printf("socfpga_bridges_reset() failed: %d\n",
> > > > > > > > ret);
> > > > > > > > +hang();
> > > > > > > > +}
> > > > > > > >
> > > > > > > > socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
> > > > > > > > socfpga_per
Re: [U-Boot] [PATCH v4 2/4] u-boot.elf: allow overriding entry symbol
On Thu, Apr 20, 2017 at 08:36:26PM +0200, Álvaro Fernández Rojas wrote: > LD gives the following warning when trying to process u-boot-elf.o > warning: cannot find entry symbol __start; defaulting to 8001 > According to gnu-libc the entry symbol for mips is __start and not _start: > https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/mips/dl-machine.h;h=ed47513ccc1d23d23d32ee640053d2f351f3990b;hb=HEAD#l258 > > Signed-off-by: Álvaro Fernández Rojas After a little reading of other platforms, _start seems a reasonable default so: Reviewed-by: Tom Rini Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 09/14] MIPS: add support for Broadcom MIPS BCM6358 SoC family
Signed-off-by: Álvaro Fernández Rojas
---
v4: No changes.
v3: Add cfi-flash defines.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Add PERF_BASE to cpus.
- Merge with "fix ioremap for BCM6358" patch.
- Add a custom ioremap.h instead of modifying the generic one.
arch/mips/dts/brcm,bcm6358.dtsi| 98 ++
arch/mips/mach-bmips/Kconfig | 18 ++-
arch/mips/mach-bmips/include/ioremap.h | 45
include/configs/bmips_bcm6358.h| 30 +++
4 files changed, 190 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/dts/brcm,bcm6358.dtsi
create mode 100644 arch/mips/mach-bmips/include/ioremap.h
create mode 100644 include/configs/bmips_bcm6358.h
diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi
new file mode 100644
index 000..c7ba7e0
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6358.dtsi
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm6358";
+
+ cpus {
+ reg = <0xfffe 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu@0 {
+ compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu@1 {
+ compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <1>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ pflash: nor@1e00 {
+ compatible = "cfi-flash";
+ reg = <0x1e00 0x200>;
+ bank-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_cntl: syscon@fffe {
+ compatible = "syscon";
+ reg = <0xfffe 0xc>;
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&periph_cntl>;
+ offset = <0x8>;
+ mask = <0x1>;
+ };
+
+ uart0: serial@fffe0100 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0xfffe0100 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@fffe0120 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0xfffe0120 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ memory-controller@fffe1200 {
+ compatible = "brcm,bcm6358-mc";
+ reg = <0xfffe1200 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 42a7e41..efdb827 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -2,7 +2,23 @@ menu "Broadcom MIPS platforms"
depends on ARCH_BMIPS
config SYS_SOC
- default "none"
+ default "bcm6358" if SOC_BMIPS_BCM6358
+
+choice
+ prompt "Broadcom MIPS SoC select"
+
+config SOC_BMIPS_BCM6358
+ bool "BMIPS BCM6358 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_SYSCON
+ help
+ This supports BMIPS BCM6358 family including BCM6358 and BCM6359.
+
+endchoice
choice
prompt "Boot mode"
diff --git a/arch/mips/mach-bmips/include/ioremap.h
b/arch/mips/mach-bmips/include/ioremap.h
new file mode 100644
index 000..404690e
--- /dev/null
+++ b/arch/mips/mach-bmips/include/ioremap.h
@@ -0,0 +1,45 @@
+/*
+ * SPDX-License-Identifier:GPL-2.0
+ */
+#ifndef __ASM_MACH_BMIPS_IOREMAP_H
+#define __ASM_MACH_BMIPS_IO
[U-Boot] [PATCH v4 11/14] MIPS: add support for Broadcom MIPS BCM6328 SoC family
Signed-off-by: Álvaro Fernández Rojas
---
v4: No changes.
v3: No changes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Add PERF_BASE to cpus.
arch/mips/dts/brcm,bcm6328.dtsi | 88 +
arch/mips/mach-bmips/Kconfig| 12 ++
include/configs/bmips_bcm6328.h | 25
3 files changed, 125 insertions(+)
create mode 100644 arch/mips/dts/brcm,bcm6328.dtsi
create mode 100644 include/configs/bmips_bcm6328.h
diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
new file mode 100644
index 000..707e755
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm6328";
+
+ cpus {
+ reg = <0x1000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu@0 {
+ compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu@1 {
+ compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <1>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ reset_cntl: syscon@1068 {
+ compatible = "syscon";
+ reg = <0x1068 0x4>;
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&reset_cntl>;
+ offset = <0>;
+ mask = <0x1>;
+ };
+
+ uart0: serial@1100 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x1100 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@1120 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x1120 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ memory-controller@10003000 {
+ compatible = "brcm,bcm6328-mc";
+ reg = <0x10003000 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 2867ad8..4c74cee 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -2,11 +2,23 @@ menu "Broadcom MIPS platforms"
depends on ARCH_BMIPS
config SYS_SOC
+ default "bcm6328" if SOC_BMIPS_BCM6328
default "bcm6358" if SOC_BMIPS_BCM6358
choice
prompt "Broadcom MIPS SoC select"
+config SOC_BMIPS_BCM6328
+ bool "BMIPS BCM6328 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_SYSCON
+ help
+ This supports BMIPS BCM6328 family including BCM63281 and BCM63283.
+
config SOC_BMIPS_BCM6358
bool "BMIPS BCM6358 family"
select SUPPORTS_BIG_ENDIAN
diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h
new file mode 100644
index 000..a5c9a2e
--- /dev/null
+++ b/include/configs/bmips_bcm6328.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6328_H
+#define __CONFIG_BMIPS_BCM6328_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 16000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x8000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x10
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM6328_H */
--
2.1.4
__
[U-Boot] [PATCH v4 05/14] cmd: cpu: refactor to ensure devices are probed and improve code style
Use uclass_first_device and uclass_next_device in order to avoid exceptions
for drivers that aren't probed when cpu ops are requested.
Improve code style and fix indentations.
Fix incorrect line break when cpu info is not available.
Remove unneeded brackets.
Signed-off-by: Álvaro Fernández Rojas
---
v4: Refactor code to use uclass_first_device and uclass_next_device as
requested by Simon Glass.
v3: add new patch to ensure that device is probed.
cmd/cpu.c | 30 +-
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/cmd/cpu.c b/cmd/cpu.c
index adfd54a..6213c72 100644
--- a/cmd/cpu.c
+++ b/cmd/cpu.c
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2015 Google, Inc
* Written by Simon Glass
+ * Copyright (c) 2017 Álvaro Fernández Rojas
*
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -21,20 +22,15 @@ static const char *cpu_feature_name[CPU_FEAT_COUNT] = {
static int print_cpu_list(bool detail)
{
struct udevice *dev;
- struct uclass *uc;
char buf[100];
- int ret;
- ret = uclass_get(UCLASS_CPU, &uc);
- if (ret) {
- printf("Cannot find CPU uclass\n");
- return ret;
- }
- uclass_foreach_dev(dev, uc) {
+ for (uclass_first_device(UCLASS_CPU, &dev);
+dev;
+uclass_next_device(&dev)) {
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
struct cpu_info info;
- bool first;
- int i;
+ bool first = true;
+ int ret, i;
ret = cpu_get_desc(dev, buf, sizeof(buf));
printf("%3d: %-10s %s\n", dev->seq, dev->name,
@@ -45,13 +41,12 @@ static int print_cpu_list(bool detail)
if (ret) {
printf("\t(no detail available");
if (ret != -ENOSYS)
- printf(": err=%d\n", ret);
+ printf(": err=%d", ret);
printf(")\n");
continue;
}
printf("\tID = %d, freq = ", plat->cpu_id);
print_freq(info.cpu_freq, "");
- first = true;
for (i = 0; i < CPU_FEAT_COUNT; i++) {
if (info.features & (1 << i)) {
printf("%s%s", first ? ": " : ", ",
@@ -60,10 +55,9 @@ static int print_cpu_list(bool detail)
}
}
printf("\n");
- if (info.features & (1 << CPU_FEAT_UCODE)) {
+ if (info.features & (1 << CPU_FEAT_UCODE))
printf("\tMicrocode version %#x\n",
plat->ucode_version);
- }
if (info.features & (1 << CPU_FEAT_DEVICE_ID))
printf("\tDevice ID %#lx\n", plat->device_id);
}
@@ -71,7 +65,8 @@ static int print_cpu_list(bool detail)
return 0;
}
-static int do_cpu_list(cmd_tbl_t *cmdtp, int flag, int argc, char *const
argv[])
+static int do_cpu_list(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
{
if (print_cpu_list(false))
return CMD_RET_FAILURE;
@@ -97,7 +92,7 @@ static cmd_tbl_t cmd_cpu_sub[] = {
* Process a cpu sub-command
*/
static int do_cpu(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
+ char * const argv[])
{
cmd_tbl_t *c = NULL;
@@ -106,7 +101,8 @@ static int do_cpu(cmd_tbl_t *cmdtp, int flag, int argc,
argv++;
if (argc)
- c = find_cmd_tbl(argv[0], cmd_cpu_sub, ARRAY_SIZE(cmd_cpu_sub));
+ c = find_cmd_tbl(argv[0], cmd_cpu_sub,
+ARRAY_SIZE(cmd_cpu_sub));
if (c)
return c->cmd(cmdtp, flag, argc, argv);
--
2.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 10/14] MIPS: add BMIPS Huawei HG556a board
Signed-off-by: Álvaro Fernández Rojas
---
v4: No changes.
v3: Add cfi-flash support.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Remove DEBUG_UART from defconfig.
arch/mips/dts/Makefile | 1 +
arch/mips/dts/huawei,hg556a.dts | 31 +
arch/mips/mach-bmips/Kconfig| 12 ++
board/huawei/hg556a/Kconfig | 12 ++
board/huawei/hg556a/MAINTAINERS | 6 +
board/huawei/hg556a/Makefile| 5 +
board/huawei/hg556a/hg556a.c| 7 ++
configs/huawei_hg556a_ram_defconfig | 45 +
include/configs/huawei_hg556a.h | 18 +++
9 files changed, 137 insertions(+)
create mode 100644 arch/mips/dts/huawei,hg556a.dts
create mode 100644 board/huawei/hg556a/Kconfig
create mode 100644 board/huawei/hg556a/MAINTAINERS
create mode 100644 board/huawei/hg556a/Makefile
create mode 100644 board/huawei/hg556a/hg556a.c
create mode 100644 configs/huawei_hg556a_ram_defconfig
create mode 100644 include/configs/huawei_hg556a.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 30fcc2b..1843b77 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -8,6 +8,7 @@ dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
+dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
targets += $(dtb-y)
diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts
new file mode 100644
index 000..08ef2c1
--- /dev/null
+++ b/arch/mips/dts/huawei,hg556a.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6358.dtsi"
+
+/ {
+ model = "Huawei HG556a Board";
+ compatible = "huawei,hg556a", "brcm,bcm6358";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&pflash {
+ status = "okay";
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index efdb827..2867ad8 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -21,6 +21,16 @@ config SOC_BMIPS_BCM6358
endchoice
choice
+ prompt "Board select"
+
+config BOARD_HUAWEI_HG556A
+ bool "Huawei HG556a board"
+ depends on SOC_BMIPS_BCM6358
+ select BMIPS_SUPPORTS_BOOT_RAM
+
+endchoice
+
+choice
prompt "Boot mode"
config BMIPS_BOOT_RAM
@@ -35,4 +45,6 @@ endchoice
config BMIPS_SUPPORTS_BOOT_RAM
bool
+source "board/huawei/hg556a/Kconfig"
+
endmenu
diff --git a/board/huawei/hg556a/Kconfig b/board/huawei/hg556a/Kconfig
new file mode 100644
index 000..88622d0
--- /dev/null
+++ b/board/huawei/hg556a/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_HUAWEI_HG556A
+
+config SYS_BOARD
+ default "hg556a"
+
+config SYS_VENDOR
+ default "huawei"
+
+config SYS_CONFIG_NAME
+ default "huawei_hg556a"
+
+endif
diff --git a/board/huawei/hg556a/MAINTAINERS b/board/huawei/hg556a/MAINTAINERS
new file mode 100644
index 000..3ead7e4
--- /dev/null
+++ b/board/huawei/hg556a/MAINTAINERS
@@ -0,0 +1,6 @@
+HUAWEI HG556A BOARD
+M: Álvaro Fernández Rojas
+S: Maintained
+F: board/huawei/hg556a/
+F: include/configs/huawei_hg556a.h
+F: configs/huawei_hg556a_ram_defconfig
diff --git a/board/huawei/hg556a/Makefile b/board/huawei/hg556a/Makefile
new file mode 100644
index 000..ace0ed3
--- /dev/null
+++ b/board/huawei/hg556a/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += hg556a.o
diff --git a/board/huawei/hg556a/hg556a.c b/board/huawei/hg556a/hg556a.c
new file mode 100644
index 000..d181ca6
--- /dev/null
+++ b/board/huawei/hg556a/hg556a.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
diff --git a/configs/huawei_hg556a_ram_defconfig
b/configs/huawei_hg556a_ram_defconfig
new file mode 100644
index 000..ca8507e
--- /dev/null
+++ b/configs/huawei_hg556a_ram_defconfig
@@ -0,0 +1,45 @@
+CONFIG_ARCH_BMIPS=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_BOARD_HUAWEI_HG556A=y
+CONFIG_CFI_FLASH=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_FLASH=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LOADB=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_MISC is not se
[U-Boot] [PATCH v4 13/14] MIPS: add support for Broadcom MIPS BCM63268 SoC family
Signed-off-by: Álvaro Fernández Rojas
---
v4: No changes.
v3: No changes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Add PERF_BASE to cpus.
arch/mips/dts/brcm,bcm63268.dtsi | 88
arch/mips/mach-bmips/Kconfig | 12 ++
include/configs/bmips_bcm63268.h | 25
3 files changed, 125 insertions(+)
create mode 100644 arch/mips/dts/brcm,bcm63268.dtsi
create mode 100644 include/configs/bmips_bcm63268.h
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
new file mode 100644
index 000..44ff888
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm63268";
+
+ cpus {
+ reg = <0x1000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu@0 {
+ compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu@1 {
+ compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <1>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_cntl: syscon@1000 {
+ compatible = "syscon";
+ reg = <0x1000 0x14>;
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&periph_cntl>;
+ offset = <0x8>;
+ mask = <0x1>;
+ };
+
+ uart0: serial@1180 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x1180 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@11a0 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x11a0 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ memory-controller@10003000 {
+ compatible = "brcm,bcm6328-mc";
+ reg = <0x10003000 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index ffb6ddd..6acad23 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -4,6 +4,7 @@ menu "Broadcom MIPS platforms"
config SYS_SOC
default "bcm6328" if SOC_BMIPS_BCM6328
default "bcm6358" if SOC_BMIPS_BCM6358
+ default "bcm63268" if SOC_BMIPS_BCM63268
choice
prompt "Broadcom MIPS SoC select"
@@ -30,6 +31,17 @@ config SOC_BMIPS_BCM6358
help
This supports BMIPS BCM6358 family including BCM6358 and BCM6359.
+config SOC_BMIPS_BCM63268
+ bool "BMIPS BCM63268 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_SYSCON
+ help
+ This supports BMIPS BCM63268 family including BCM63168, BCM63169,
BCM63268 and BCM63269.
+
endchoice
choice
diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h
new file mode 100644
index 000..91f42e9
--- /dev/null
+++ b/include/configs/bmips_bcm63268.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM63268_H
+#define __CONFIG_BMIPS_BCM63268_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 2
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x8000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x10
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SYS_INIT_SP_OFFS
[U-Boot] [PATCH v4 12/14] MIPS: add BMIPS Comtrend AR-5387un board
Signed-off-by: Álvaro Fernández Rojas
---
v4: No changes.
v3: No changes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Remove DEBUG_UART from defconfig.
arch/mips/dts/Makefile | 1 +
arch/mips/dts/comtrend,ar-5387un.dts| 27 +
arch/mips/mach-bmips/Kconfig| 6 +
board/comtrend/ar5387un/Kconfig | 12 ++
board/comtrend/ar5387un/MAINTAINERS | 6 +
board/comtrend/ar5387un/Makefile| 5
board/comtrend/ar5387un/ar-5387un.c | 7 ++
configs/comtrend_ar5387un_ram_defconfig | 42 +
include/configs/comtrend_ar5387un.h | 15
9 files changed, 121 insertions(+)
create mode 100644 arch/mips/dts/comtrend,ar-5387un.dts
create mode 100644 board/comtrend/ar5387un/Kconfig
create mode 100644 board/comtrend/ar5387un/MAINTAINERS
create mode 100644 board/comtrend/ar5387un/Makefile
create mode 100644 board/comtrend/ar5387un/ar-5387un.c
create mode 100644 configs/comtrend_ar5387un_ram_defconfig
create mode 100644 include/configs/comtrend_ar5387un.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 1843b77..0805819 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -8,6 +8,7 @@ dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
+dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/comtrend,ar-5387un.dts
b/arch/mips/dts/comtrend,ar-5387un.dts
new file mode 100644
index 000..f9c4a1c
--- /dev/null
+++ b/arch/mips/dts/comtrend,ar-5387un.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6328.dtsi"
+
+/ {
+ model = "Comtrend AR-5387un Board";
+ compatible = "comtrend,ar5387-un", "brcm,bcm6328";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 4c74cee..ffb6ddd 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -35,6 +35,11 @@ endchoice
choice
prompt "Board select"
+config BOARD_COMTREND_AR5387UN
+ bool "Comtrend AR-5387un board"
+ depends on SOC_BMIPS_BCM6328
+ select BMIPS_SUPPORTS_BOOT_RAM
+
config BOARD_HUAWEI_HG556A
bool "Huawei HG556a board"
depends on SOC_BMIPS_BCM6358
@@ -57,6 +62,7 @@ endchoice
config BMIPS_SUPPORTS_BOOT_RAM
bool
+source "board/comtrend/ar5387un/Kconfig"
source "board/huawei/hg556a/Kconfig"
endmenu
diff --git a/board/comtrend/ar5387un/Kconfig b/board/comtrend/ar5387un/Kconfig
new file mode 100644
index 000..45ab7e2
--- /dev/null
+++ b/board/comtrend/ar5387un/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_AR5387UN
+
+config SYS_BOARD
+ default "ar5387un"
+
+config SYS_VENDOR
+ default "comtrend"
+
+config SYS_CONFIG_NAME
+ default "comtrend_ar5387un"
+
+endif
diff --git a/board/comtrend/ar5387un/MAINTAINERS
b/board/comtrend/ar5387un/MAINTAINERS
new file mode 100644
index 000..bcaac64
--- /dev/null
+++ b/board/comtrend/ar5387un/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND AR-5387UN BOARD
+M: Álvaro Fernández Rojas
+S: Maintained
+F: board/comtrend/ar-5387un/
+F: include/configs/comtrend_ar5387un.h
+F: configs/comtrend_ar5387un_ram_defconfig
diff --git a/board/comtrend/ar5387un/Makefile b/board/comtrend/ar5387un/Makefile
new file mode 100644
index 000..9de1cd2
--- /dev/null
+++ b/board/comtrend/ar5387un/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ar-5387un.o
diff --git a/board/comtrend/ar5387un/ar-5387un.c
b/board/comtrend/ar5387un/ar-5387un.c
new file mode 100644
index 000..d181ca6
--- /dev/null
+++ b/board/comtrend/ar5387un/ar-5387un.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
diff --git a/configs/comtrend_ar5387un_ram_defconfig
b/configs/comtrend_ar5387un_ram_defconfig
new file mode 100644
index 000..004fd16
--- /dev/null
+++ b/configs/comtrend_ar5387un_ram_defconfig
@@ -0,0 +1,42 @@
+CONFIG_ARCH_BMIPS=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_BOARD_COMTREND_AR5387UN=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+
[U-Boot] [PATCH v4 14/14] MIPS: add BMIPS Comtrend VR-3032u board
Signed-off-by: Álvaro Fernández Rojas
---
v4: No changes.
v3: No changes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Remove DEBUG_UART from defconfig.
arch/mips/dts/Makefile | 1 +
arch/mips/dts/comtrend,vr-3032u.dts| 27 ++
arch/mips/mach-bmips/Kconfig | 6 +
board/comtrend/vr3032u/Kconfig | 12 ++
board/comtrend/vr3032u/MAINTAINERS | 6 +
board/comtrend/vr3032u/Makefile| 5
board/comtrend/vr3032u/vr-3032u.c | 7 ++
configs/comtrend_vr3032u_ram_defconfig | 42 ++
include/configs/comtrend_vr3032u.h | 15
9 files changed, 121 insertions(+)
create mode 100644 arch/mips/dts/comtrend,vr-3032u.dts
create mode 100644 board/comtrend/vr3032u/Kconfig
create mode 100644 board/comtrend/vr3032u/MAINTAINERS
create mode 100644 board/comtrend/vr3032u/Makefile
create mode 100644 board/comtrend/vr3032u/vr-3032u.c
create mode 100644 configs/comtrend_vr3032u_ram_defconfig
create mode 100644 include/configs/comtrend_vr3032u.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 0805819..4c02c48 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
+dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/comtrend,vr-3032u.dts
b/arch/mips/dts/comtrend,vr-3032u.dts
new file mode 100644
index 000..c0fdb28
--- /dev/null
+++ b/arch/mips/dts/comtrend,vr-3032u.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm63268.dtsi"
+
+/ {
+ model = "Comtrend VR-3032u Board";
+ compatible = "comtrend,vr-3032u", "brcm,bcm63268";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 6acad23..5b30f3b 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -57,6 +57,11 @@ config BOARD_HUAWEI_HG556A
depends on SOC_BMIPS_BCM6358
select BMIPS_SUPPORTS_BOOT_RAM
+config BOARD_COMTREND_VR3032U
+ bool "Comtrend VR-3032u board"
+ depends on SOC_BMIPS_BCM63268
+ select BMIPS_SUPPORTS_BOOT_RAM
+
endchoice
choice
@@ -75,6 +80,7 @@ config BMIPS_SUPPORTS_BOOT_RAM
bool
source "board/comtrend/ar5387un/Kconfig"
+source "board/comtrend/vr3032u/Kconfig"
source "board/huawei/hg556a/Kconfig"
endmenu
diff --git a/board/comtrend/vr3032u/Kconfig b/board/comtrend/vr3032u/Kconfig
new file mode 100644
index 000..6f552cf
--- /dev/null
+++ b/board/comtrend/vr3032u/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_VR3032U
+
+config SYS_BOARD
+ default "vr3032u"
+
+config SYS_VENDOR
+ default "comtrend"
+
+config SYS_CONFIG_NAME
+ default "comtrend_vr3032u"
+
+endif
diff --git a/board/comtrend/vr3032u/MAINTAINERS
b/board/comtrend/vr3032u/MAINTAINERS
new file mode 100644
index 000..833d7da
--- /dev/null
+++ b/board/comtrend/vr3032u/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND VR-3032U BOARD
+M: Álvaro Fernández Rojas
+S: Maintained
+F: board/comtrend/vr-3032u/
+F: include/configs/comtrend_vr-3032u.h
+F: configs/comtrend_vr3032u_ram_defconfig
diff --git a/board/comtrend/vr3032u/Makefile b/board/comtrend/vr3032u/Makefile
new file mode 100644
index 000..9e62031
--- /dev/null
+++ b/board/comtrend/vr3032u/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += vr-3032u.o
diff --git a/board/comtrend/vr3032u/vr-3032u.c
b/board/comtrend/vr3032u/vr-3032u.c
new file mode 100644
index 000..d181ca6
--- /dev/null
+++ b/board/comtrend/vr3032u/vr-3032u.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
diff --git a/configs/comtrend_vr3032u_ram_defconfig
b/configs/comtrend_vr3032u_ram_defconfig
new file mode 100644
index 000..4cf15b1
--- /dev/null
+++ b/configs/comtrend_vr3032u_ram_defconfig
@@ -0,0 +1,42 @@
+CONFIG_ARCH_BMIPS=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_BOARD_COMTREND_VR3032U=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_GPIO is no
[U-Boot] [PATCH v4 03/14] MIPS: allow using generic sysreset drivers
Avoid duplicating do_reset definition if SYSRESET is enabled for MIPS
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v4: No changes.
v3: No changes.
v2: No changes.
arch/mips/cpu/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index 1b919ed..55e6498 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -12,6 +12,7 @@
#include
#include
+#ifndef CONFIG_SYSRESET
void __weak _machine_restart(void)
{
fprintf(stderr, "*** reset failed ***\n");
@@ -26,6 +27,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
return 0;
}
+#endif
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
{
--
2.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 08/14] MIPS: add initial infrastructure for Broadcom MIPS SoCs
CFE checks CPU Thread in a different way (using register $22):
mfc0t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnezt1, 2f # if we are running on thread 1, skip init
nop
Signed-off-by: Álvaro Fernández Rojas
---
v4: No changes.
v3: Select CONFIG_REMAKE_ELF.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Replace initdram with dram_init.
- Merge with "fix first CPU check" patch.
arch/mips/Kconfig | 10 ++
arch/mips/Makefile | 1 +
arch/mips/cpu/start.S | 5 +
arch/mips/mach-bmips/Kconfig | 22 ++
arch/mips/mach-bmips/Makefile | 5 +
arch/mips/mach-bmips/dram.c| 37 +
include/configs/bmips_common.h | 27 +++
7 files changed, 107 insertions(+)
create mode 100644 arch/mips/mach-bmips/Kconfig
create mode 100644 arch/mips/mach-bmips/Makefile
create mode 100644 arch/mips/mach-bmips/dram.c
create mode 100644 include/configs/bmips_common.h
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d97930e..c97ea41 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -75,6 +75,15 @@ config ARCH_ATH79
select OF_CONTROL
select DM
+config ARCH_BMIPS
+ bool "Support BMIPS SoCs"
+ select OF_CONTROL
+ select DM
+ select CLK
+ select CPU
+ select RAM
+ select SYSRESET
+
config MACH_PIC32
bool "Support Microchip PIC32"
select OF_CONTROL
@@ -123,6 +132,7 @@ source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
+source "arch/mips/mach-bmips/Kconfig"
source "arch/mips/mach-pic32/Kconfig"
if MIPS
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index efe7e44..c30d4ef 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -15,6 +15,7 @@ libs-y += arch/mips/lib/
machine-$(CONFIG_SOC_AU1X00) += au1x00
machine-$(CONFIG_ARCH_ATH79) += ath79
+machine-$(CONFIG_ARCH_BMIPS) += bmips
machine-$(CONFIG_MACH_PIC32) += pic32
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index f7dee81..5c1ad00 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -151,8 +151,13 @@ reset:
mfc0 t0, CP0_GLOBALNUMBER
#endif
+#ifdef CONFIG_ARCH_BMIPS
+1: mfc0t0, CP0_DIAGNOSTIC, 3
+ and t0, t0, (1 << 31)
+#else
1: mfc0t0, CP0_EBASE
and t0, t0, EBASE_CPUNUM
+#endif
/* Hang if this isn't the first CPU in the system */
2: beqzt0, 4f
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
new file mode 100644
index 000..42a7e41
--- /dev/null
+++ b/arch/mips/mach-bmips/Kconfig
@@ -0,0 +1,22 @@
+menu "Broadcom MIPS platforms"
+ depends on ARCH_BMIPS
+
+config SYS_SOC
+ default "none"
+
+choice
+ prompt "Boot mode"
+
+config BMIPS_BOOT_RAM
+ bool "RAM boot"
+ depends on BMIPS_SUPPORTS_BOOT_RAM
+ help
+ This builds an image that is linked to a RAM address. Caches are
+ disabled and environment is built in.
+
+endchoice
+
+config BMIPS_SUPPORTS_BOOT_RAM
+ bool
+
+endmenu
diff --git a/arch/mips/mach-bmips/Makefile b/arch/mips/mach-bmips/Makefile
new file mode 100644
index 000..f432acc
--- /dev/null
+++ b/arch/mips/mach-bmips/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += dram.o
diff --git a/arch/mips/mach-bmips/dram.c b/arch/mips/mach-bmips/dram.c
new file mode 100644
index 000..b19b28a
--- /dev/null
+++ b/arch/mips/mach-bmips/dram.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2016 Daniel Schwierzeck
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ struct ram_info ram;
+ struct udevice *dev;
+ int err;
+
+ err = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (err) {
+ debug("DRAM init failed: %d\n", err);
+ return 0;
+ }
+
+ err = ram_get_info(dev, &ram);
+ if (err) {
+ debug("Cannot get DRAM size: %d\n", err);
+ return 0;
+ }
+
+ debug("SDRAM base=%zx, size=%x\n", ram.base, ram.size);
+
+ gd->ram_size = ram.size;
+
+ return 0;
+}
diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h
new file mode 100644
index 000..3d67729
--- /dev/null
+++ b/include/configs/bmips_common.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_COMMON_H
+#define __CONFIG_BMIPS_COMMON_H
+
+/* RAM */
+#define CONFIG_SYS_MEMTEST_START 0xa000
+#define CONFIG_SYS_MEMTEST_END 0xa200
+
+/* Serial */
+#define CONFIG_
[U-Boot] [PATCH v4 06/14] cpu: add CPU driver for Broadcom MIPS SoCs
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v4: No changes.
v3: Several improvements:
- Probe driver correctly.
- Allocate size for priv struct.
- Cosmetic fixes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Get register base from DT.
drivers/cpu/Makefile| 2 +
drivers/cpu/bmips_cpu.c | 280
2 files changed, 282 insertions(+)
create mode 100644 drivers/cpu/bmips_cpu.c
diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
index 8710160..db515f6 100644
--- a/drivers/cpu/Makefile
+++ b/drivers/cpu/Makefile
@@ -5,3 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_CPU) += cpu-uclass.o
+
+obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c
new file mode 100644
index 000..d95f51a
--- /dev/null
+++ b/drivers/cpu/bmips_cpu.c
@@ -0,0 +1,280 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * Derived from linux/arch/mips/bcm63xx/cpu.c:
+ * Copyright (C) 2008 Maxime Bizon
+ * Copyright (C) 2009 Florian Fainelli
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define REV_CHIPID_SHIFT 16
+#define REV_CHIPID_MASK(0x << REV_CHIPID_SHIFT)
+#define REV_REVID_SHIFT0
+#define REV_REVID_MASK (0xff << REV_REVID_SHIFT)
+
+#define REG_BCM6328_OTP0x62c
+#define BCM6328_TP1_DISABLED BIT(9)
+
+#define REG_BCM6328_MISC_STRAPBUS 0x1a40
+#define STRAPBUS_6328_FCVO_SHIFT 7
+#define STRAPBUS_6328_FCVO_MASK(0x1f <<
STRAPBUS_6328_FCVO_SHIFT)
+
+#define REG_BCM6358_DDR_DMIPSPLLCFG0x12b8
+#define DMIPSPLLCFG_6358_M1_SHIFT 0
+#define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT)
+#define DMIPSPLLCFG_6358_N1_SHIFT 23
+#define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT)
+#define DMIPSPLLCFG_6358_N2_SHIFT 29
+#define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
+
+#define REG_BCM63268_MISC_STRAPBUS 0x1814
+#define STRAPBUS_63268_FCVO_SHIFT 21
+#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
+
+struct bmips_cpu_priv;
+
+struct bmips_cpu_hw {
+ ulong (*get_cpu_freq)(struct bmips_cpu_priv *);
+ int (*get_cpu_count)(struct bmips_cpu_priv *);
+};
+
+struct bmips_cpu_priv {
+ void __iomem *regs;
+ const struct bmips_cpu_hw *hw;
+};
+
+/* Specific CPU Ops */
+static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+ unsigned int mips_pll_fcvo;
+
+ mips_pll_fcvo = __raw_readl(priv->regs + REG_BCM6328_MISC_STRAPBUS);
+ mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK)
+ >> STRAPBUS_6328_FCVO_SHIFT;
+
+ switch (mips_pll_fcvo) {
+ case 0x12:
+ case 0x14:
+ case 0x19:
+ return 16000;
+ case 0x1c:
+ return 19200;
+ case 0x13:
+ case 0x15:
+ return 2;
+ case 0x1a:
+ return 38400;
+ case 0x16:
+ return 4;
+ default:
+ return 32000;
+ }
+}
+
+static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+ unsigned int tmp, n1, n2, m1;
+
+ tmp = __raw_readl(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG);
+ n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT;
+ n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT;
+ m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT;
+
+ return (16 * 100 * n1 * n2) / m1;
+}
+
+static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+ unsigned mips_pll_fcvo;
+
+ mips_pll_fcvo = __raw_readl(priv->regs + REG_BCM63268_MISC_STRAPBUS);
+ mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK)
+ >> STRAPBUS_63268_FCVO_SHIFT;
+
+ switch (mips_pll_fcvo) {
+ case 0x3:
+ case 0xe:
+ return 32000;
+ case 0xa:
+ return 33300;
+ case 0x2:
+ case 0xb:
+ case 0xf:
+ return 4;
+ default:
+ return 0;
+ }
+}
+
+static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
+{
+ u32 val = __raw_readl(priv->regs + REG_BCM6328_OTP);
+
+ if (val & BCM6328_TP1_DISABLED)
+ return 1;
+ else
+ return 2;
+}
+
+static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
+{
+ return 2;
+}
+
+static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
+ .get_cpu_freq = bcm6328_get_cpu_freq,
+ .get_cpu_count = bcm6328_get_cpu_count,
+};
+
+static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
+ .get_
[U-Boot] [PATCH v4 04/14] serial: add serial driver for BCM6345
It is based on linux/drivers/tty/serial/bcm63xx_uart.c Signed-off-by: Álvaro Fernández Rojas --- v4: Add more missing register configurations based on CFE. v3: Several improvements: - Add missing register configurations based on CFE. - Replace tabs with whitespaces. - Cosmetic fixes. v2: Introduce changes suggested by Daniel Schwierzeck: - Remove unneeded defines. - Fix incorrect multi-line comment. drivers/serial/Kconfig | 14 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_bcm6345.c | 311 3 files changed, 326 insertions(+) create mode 100644 drivers/serial/serial_bcm6345.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index c0ec2ec..ca776d8 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -134,6 +134,14 @@ config DEBUG_UART_ATMEL will need to provide parameters to make this work. The driver will be available until the real driver-model serial is running. +config DEBUG_UART_BCM6345 + bool "BCM6345 UART" + depends on BCM6345_SERIAL + help + Select this to enable a debug UART on BCM6345 SoCs. You + will need to provide parameters to make this work. The driver will + be available until the real driver model serial is running. + config DEBUG_UART_NS16550 bool "ns16550" help @@ -339,6 +347,12 @@ config ATMEL_USART configured in the device tree, and input clock frequency can be got from the clk node. +config BCM6345_SERIAL + bool "Support for BCM6345 UART" + depends on DM_SERIAL + help + Select this to enable UART on BCM6345 SoCs. + config FSL_LPUART bool "Freescale LPUART support" help diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 4382cf9..dca31b2 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o +obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o obj-$(CONFIG_EFI_APP) += serial_efi.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += mcfuart.o diff --git a/drivers/serial/serial_bcm6345.c b/drivers/serial/serial_bcm6345.c new file mode 100644 index 000..e4d3497 --- /dev/null +++ b/drivers/serial/serial_bcm6345.c @@ -0,0 +1,311 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/drivers/tty/serial/bcm63xx_uart.c: + * Copyright (C) 2008 Maxime Bizon + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +/* UART Control register */ +#define UART_CTL_REG 0x0 +#define UART_CTL_RXTIMEOUT_MASK0x1f +#define UART_CTL_RSTRXFIFO_SHIFT 6 +#define UART_CTL_RSTRXFIFO_MASK(1 << UART_CTL_RSTRXFIFO_SHIFT) +#define UART_CTL_RSTTXFIFO_SHIFT 7 +#define UART_CTL_RSTTXFIFO_MASK(1 << UART_CTL_RSTTXFIFO_SHIFT) +#define UART_CTL_STOPBITS_SHIFT8 +#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) +#define UART_CTL_STOPBITS_1(0x7 << UART_CTL_STOPBITS_SHIFT) +#define UART_CTL_BITSPERSYM_SHIFT 12 +#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) +#define UART_CTL_XMITBRK_SHIFT 14 +#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) +#define UART_CTL_RSVD_SHIFT15 +#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) +#define UART_CTL_RXPAREVEN_SHIFT 16 +#define UART_CTL_RXPAREVEN_MASK(1 << UART_CTL_RXPAREVEN_SHIFT) +#define UART_CTL_RXPAREN_SHIFT 17 +#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) +#define UART_CTL_TXPAREVEN_SHIFT 18 +#define UART_CTL_TXPAREVEN_MASK(1 << UART_CTL_TXPAREVEN_SHIFT) +#define UART_CTL_TXPAREN_SHIFT 19 +#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) +#define UART_CTL_LOOPBACK_SHIFT20 +#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) +#define UART_CTL_RXEN_SHIFT21 +#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) +#define UART_CTL_TXEN_SHIFT22 +#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) +#define UART_CTL_BRGEN_SHIFT 23 +#define UART_CTL_BRGEN_MASK(1 << UART_CTL_BRGEN_SHIFT) + +/* UART Baudword register */ +#define UART_BAUD_REG 0x4 + +/* UART FIFO Config register */ +#define UART_FIFO_CFG_REG 0x8 +#define UART_FIFO_CFG_RX_SHIFT 8 +#define UART_FIFO_CFG_RX_MASK (0xf << UART_FIFO_CFG_RX_SHIFT) +#define UART_FIFO_CFG_TX_SHIFT 12 +#define UART_FIFO_CFG_TX_MASK (0xf << UART_FIFO_CFG_TX_SHIFT) + +/
[U-Boot] [PATCH v4 01/14] cmd: cpu: fix NULL cpu feature prints
Commit 740d5d3 added two new features but only one feature name,
which results in NULL prints when device_id feature is selected.
Before:
HG556a # cpu detail
-1: cpu@0 BCM6358A1
ID = 0, freq = 300 MHz: L1 cache, MMU, NULL
Device ID 0x2a010
-1: cpu@1 BCM6358A1
ID = 1, freq = 300 MHz: L1 cache, MMU, NULL
Device ID 0x2a010
After:
HG556a # cpu detail
-1: cpu@0 BCM6358A1
ID = 0, freq = 300 MHz: L1 cache, MMU, Device ID
Device ID 0x2a010
-1: cpu@1 BCM6358A1
ID = 1, freq = 300 MHz: L1 cache, MMU, Device ID
Device ID 0x2a010
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v3: No changes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Add the missing name instead of checking for null names.
cmd/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/cmd/cpu.c b/cmd/cpu.c
index bc4dc5c..adfd54a 100644
--- a/cmd/cpu.c
+++ b/cmd/cpu.c
@@ -15,6 +15,7 @@ static const char *cpu_feature_name[CPU_FEAT_COUNT] = {
"L1 cache",
"MMU",
"Microcode",
+ "Device ID",
};
static int print_cpu_list(bool detail)
--
2.1.4
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[U-Boot] [PATCH v4 07/14] ram: add RAM driver for Broadcom MIPS SoCs
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v4: No changes.
v3: Rename of_match to ids.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
drivers/ram/Makefile| 2 +
drivers/ram/bmips_ram.c | 126
2 files changed, 128 insertions(+)
create mode 100644 drivers/ram/bmips_ram.c
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 0e10249..818dd9f 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -6,3 +6,5 @@
#
obj-$(CONFIG_RAM) += ram-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_ram.o
+
+obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c
new file mode 100644
index 000..28aff0c
--- /dev/null
+++ b/drivers/ram/bmips_ram.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * Derived from linux/arch/mips/bcm63xx/cpu.c:
+ * Copyright (C) 2008 Maxime Bizon
+ * Copyright (C) 2009 Florian Fainelli
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define MEMC_CFG_REG 0x4
+#define MEMC_CFG_32B_SHIFT 1
+#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
+#define MEMC_CFG_COL_SHIFT 3
+#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
+#define MEMC_CFG_ROW_SHIFT 6
+#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
+
+#define DDR_CSEND_REG 0x8
+
+struct bmips_ram_priv;
+
+struct bmips_ram_hw {
+ ulong (*get_ram_size)(struct bmips_ram_priv *);
+};
+
+struct bmips_ram_priv {
+ void __iomem *regs;
+ const struct bmips_ram_hw *hw;
+};
+
+static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
+{
+ return __raw_readl(priv->regs + DDR_CSEND_REG) << 24;
+}
+
+static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
+{
+ unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+ u32 val;
+
+ val = __raw_readl(priv->regs + MEMC_CFG_REG);
+ rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
+ cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
+ is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
+ banks = 2;
+
+ /* 0 => 11 address bits ... 2 => 13 address bits */
+ rows += 11;
+
+ /* 0 => 8 address bits ... 2 => 10 address bits */
+ cols += 8;
+
+ return 1 << (cols + rows + (is_32bits + 1) + banks);
+}
+
+static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct bmips_ram_priv *priv = dev_get_priv(dev);
+ const struct bmips_ram_hw *hw = priv->hw;
+
+ info->base = 0x8000;
+ info->size = hw->get_ram_size(priv);
+
+ return 0;
+}
+
+static const struct ram_ops bmips_ram_ops = {
+ .get_info = bmips_ram_get_info,
+};
+
+static const struct bmips_ram_hw bmips_ram_bcm6328 = {
+ .get_ram_size = bcm6328_get_ram_size,
+};
+
+static const struct bmips_ram_hw bmips_ram_bcm6358 = {
+ .get_ram_size = bcm6358_get_ram_size,
+};
+
+static const struct udevice_id bmips_ram_ids[] = {
+ {
+ .compatible = "brcm,bcm6328-mc",
+ .data = (ulong)&bmips_ram_bcm6328,
+ }, {
+ .compatible = "brcm,bcm6358-mc",
+ .data = (ulong)&bmips_ram_bcm6358,
+ }, {
+ .compatible = "brcm,bcm63268-mc",
+ .data = (ulong)&bmips_ram_bcm6328,
+ },
+ { /* sentinel */ }
+};
+
+static int bmips_ram_probe(struct udevice *dev)
+{
+ struct bmips_ram_priv *priv = dev_get_priv(dev);
+ const struct bmips_ram_hw *hw =
+ (const struct bmips_ram_hw *)dev_get_driver_data(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = dev_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+ priv->hw = hw;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(bmips_ram) = {
+ .name = "bmips-mc",
+ .id = UCLASS_RAM,
+ .of_match = bmips_ram_ids,
+ .probe = bmips_ram_probe,
+ .priv_auto_alloc_size = sizeof(struct bmips_ram_priv),
+ .ops = &bmips_ram_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.1.4
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[U-Boot] [PATCH v4 02/14] sysreset: add syscon-reboot driver
Add a new sysreset driver based on linux/drivers/power/reset/syscon-reboot.c,
which provides a generic driver for platforms that only require writing a mask
to a regmap offset.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v4: Rebased.
v3: Introduce changes suggested by Simon Glass:
- Add missing driver description.
- Alphabetically order includes.
- Add priv struct to store regmap during probe.
- Cosmetic fixes.
v2: No changes.
drivers/sysreset/Kconfig | 8
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_syscon.c | 76 ++
3 files changed, 85 insertions(+)
create mode 100644 drivers/sysreset/sysreset_syscon.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 9664630..b2f7464 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -23,4 +23,12 @@ config SYSRESET_PSCI
must be running on your system.
endif
+
+config SYSRESET_SYSCON
+ bool "Enable support for mfd syscon reboot driver"
+ select REGMAP
+ select SYSCON
+ help
+ Reboot support for generic SYSCON mapped register reset.
+
endmenu
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 7bb8406..bd352e7 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
+obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o
diff --git a/drivers/sysreset/sysreset_syscon.c
b/drivers/sysreset/sysreset_syscon.c
new file mode 100644
index 000..adfddb4
--- /dev/null
+++ b/drivers/sysreset/sysreset_syscon.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * Derived from linux/drivers/power/reset/syscon-reboot.c:
+ * Copyright (C) 2013, Applied Micro Circuits Corporation
+ * Author: Feng Kan
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct syscon_reboot_priv {
+ struct regmap *regmap;
+ unsigned int offset;
+ unsigned int mask;
+};
+
+static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct syscon_reboot_priv *priv = dev_get_priv(dev);
+
+ regmap_write(priv->regmap, priv->offset, priv->mask);
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops syscon_reboot_ops = {
+ .request = syscon_reboot_request,
+};
+
+int syscon_reboot_probe(struct udevice *dev)
+{
+ struct udevice *syscon;
+ struct syscon_reboot_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+ "regmap", &syscon);
+ if (err) {
+ error("unable to find syscon device\n");
+ return err;
+ }
+
+ priv->regmap = syscon_get_regmap(syscon);
+ if (!priv->regmap) {
+ error("unable to find regmap\n");
+ return -ENODEV;
+ }
+
+ priv->offset = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"offset", 0);
+ priv->mask = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "mask",
0);
+
+ return 0;
+}
+
+static const struct udevice_id syscon_reboot_ids[] = {
+ { .compatible = "syscon-reboot" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(syscon_reboot) = {
+ .name = "syscon_reboot",
+ .id = UCLASS_SYSRESET,
+ .of_match = syscon_reboot_ids,
+ .probe = syscon_reboot_probe,
+ .priv_auto_alloc_size = sizeof(struct syscon_reboot_priv),
+ .ops = &syscon_reboot_ops,
+};
--
2.1.4
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[U-Boot] [PATCH v4 00/14] Add support for Broadcom MIPS SoCs
This adds support for some of the xDSL Broadcom MIPS SoCs: - BCM6358 - BCM6328 - BCM63268 However, support for other SoCs could be added in the future: - Other BCM63xx - BCM33xx - BCM71xx v4: Introduce changes suggested by Simon Glass: - Refactor cmd/cpu. - Remove device_probe patch for sysreset. v3: Introduce changes suggested by Simon Glass. v2: Introduce changes suggested by Daniel Schwierzeck. Álvaro Fernández Rojas (14): cmd: cpu: fix NULL cpu feature prints sysreset: add syscon-reboot driver MIPS: allow using generic sysreset drivers serial: add serial driver for BCM6345 cmd: cpu: refactor to ensure devices are probed and improve code style cpu: add CPU driver for Broadcom MIPS SoCs ram: add RAM driver for Broadcom MIPS SoCs MIPS: add initial infrastructure for Broadcom MIPS SoCs MIPS: add support for Broadcom MIPS BCM6358 SoC family MIPS: add BMIPS Huawei HG556a board MIPS: add support for Broadcom MIPS BCM6328 SoC family MIPS: add BMIPS Comtrend AR-5387un board MIPS: add support for Broadcom MIPS BCM63268 SoC family MIPS: add BMIPS Comtrend VR-3032u board arch/mips/Kconfig | 10 + arch/mips/Makefile | 1 + arch/mips/cpu/cpu.c | 2 + arch/mips/cpu/start.S | 5 + arch/mips/dts/Makefile | 3 + arch/mips/dts/brcm,bcm63268.dtsi| 88 + arch/mips/dts/brcm,bcm6328.dtsi | 88 + arch/mips/dts/brcm,bcm6358.dtsi | 98 ++ arch/mips/dts/comtrend,ar-5387un.dts| 27 +++ arch/mips/dts/comtrend,vr-3032u.dts | 27 +++ arch/mips/dts/huawei,hg556a.dts | 31 arch/mips/mach-bmips/Kconfig| 86 + arch/mips/mach-bmips/Makefile | 5 + arch/mips/mach-bmips/dram.c | 37 arch/mips/mach-bmips/include/ioremap.h | 45 + board/comtrend/ar5387un/Kconfig | 12 ++ board/comtrend/ar5387un/MAINTAINERS | 6 + board/comtrend/ar5387un/Makefile| 5 + board/comtrend/ar5387un/ar-5387un.c | 7 + board/comtrend/vr3032u/Kconfig | 12 ++ board/comtrend/vr3032u/MAINTAINERS | 6 + board/comtrend/vr3032u/Makefile | 5 + board/comtrend/vr3032u/vr-3032u.c | 7 + board/huawei/hg556a/Kconfig | 12 ++ board/huawei/hg556a/MAINTAINERS | 6 + board/huawei/hg556a/Makefile| 5 + board/huawei/hg556a/hg556a.c| 7 + cmd/cpu.c | 31 ++-- configs/comtrend_ar5387un_ram_defconfig | 42 + configs/comtrend_vr3032u_ram_defconfig | 42 + configs/huawei_hg556a_ram_defconfig | 45 + drivers/cpu/Makefile| 2 + drivers/cpu/bmips_cpu.c | 280 drivers/ram/Makefile| 2 + drivers/ram/bmips_ram.c | 126 + drivers/serial/Kconfig | 14 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_bcm6345.c | 311 drivers/sysreset/Kconfig| 8 + drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_syscon.c | 76 include/configs/bmips_bcm63268.h| 25 +++ include/configs/bmips_bcm6328.h | 25 +++ include/configs/bmips_bcm6358.h | 30 +++ include/configs/bmips_common.h | 27 +++ include/configs/comtrend_ar5387un.h | 15 ++ include/configs/comtrend_vr3032u.h | 15 ++ include/configs/huawei_hg556a.h | 18 ++ 48 files changed, 1762 insertions(+), 17 deletions(-) create mode 100644 arch/mips/dts/brcm,bcm63268.dtsi create mode 100644 arch/mips/dts/brcm,bcm6328.dtsi create mode 100644 arch/mips/dts/brcm,bcm6358.dtsi create mode 100644 arch/mips/dts/comtrend,ar-5387un.dts create mode 100644 arch/mips/dts/comtrend,vr-3032u.dts create mode 100644 arch/mips/dts/huawei,hg556a.dts create mode 100644 arch/mips/mach-bmips/Kconfig create mode 100644 arch/mips/mach-bmips/Makefile create mode 100644 arch/mips/mach-bmips/dram.c create mode 100644 arch/mips/mach-bmips/include/ioremap.h create mode 100644 board/comtrend/ar5387un/Kconfig create mode 100644 board/comtrend/ar5387un/MAINTAINERS create mode 100644 board/comtrend/ar5387un/Makefile create mode 100644 board/comtrend/ar5387un/ar-5387un.c create mode 100644 board/comtrend/vr3032u/Kconfig create mode 100644 board/comtrend/vr3032u/MAINTAINERS create mode 100644 board/comtrend/vr3032u/Makefile create mode 100644 board/comtrend/vr3032u/vr-3032u.c create mode 100644 board/huawei/hg556a/Kconfig create mode 100644 board/huawei/hg556a/MAINTAINERS create mode 100644 board/huawei/hg556a/Makefile create mode 100644 board/huawei/hg556a/hg556a.c create mode 100644 configs/comtrend_ar5387un_ram_defconfig create mode 100644 configs/comtrend_vr3032u_ram_defconfig create mode 100644 configs/huawei_hg556a_ram
[U-Boot] [PATCH v4 2/4] u-boot.elf: allow overriding entry symbol
LD gives the following warning when trying to process u-boot-elf.o warning: cannot find entry symbol __start; defaulting to 8001 According to gnu-libc the entry symbol for mips is __start and not _start: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/mips/dl-machine.h;h=ed47513ccc1d23d23d32ee640053d2f351f3990b;hb=HEAD#l258 Signed-off-by: Álvaro Fernández Rojas --- v4: Introduce changes suggested by Tom Rini: - __start is the standard for MIPS, not ARM. v3: Introduce changes suggested by Daniel Schwierzeck: - Split patches. v2: Introduce changes suggested by Daniel Schwierzeck: - Fix _start vs __start symbol. Makefile | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 8730550..6cf2568 100644 --- a/Makefile +++ b/Makefile @@ -1184,10 +1184,13 @@ u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE $(call if_changed,pad_cat) # Create a new ELF from a raw binary file. +ifndef PLATFORM_ELFENTRY + PLATFORM_ELFENTRY = "_start" +endif u-boot.elf: u-boot.bin @$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o @$(LD) u-boot-elf.o -o $@ \ - --defsym=_start=$(CONFIG_SYS_TEXT_BASE) \ + --defsym=$(PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \ -Ttext=$(CONFIG_SYS_TEXT_BASE) # Rule to link u-boot -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 4/4] u-boot.elf: add quiet_cmd_u-boot-elf and cmd_u-boot-elf
This way we can see output about u-boot.elf being built or not. Signed-off-by: Álvaro Fernández Rojas --- v4: Introduce changes suggested by Tom Rini: - Add new patch to output u-boot.elf build. Makefile | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 6cf2568..3722b19 100644 --- a/Makefile +++ b/Makefile @@ -1187,11 +1187,13 @@ u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE ifndef PLATFORM_ELFENTRY PLATFORM_ELFENTRY = "_start" endif +quiet_cmd_u-boot-elf ?= LD $@ + cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \ + --defsym=$(PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \ + -Ttext=$(CONFIG_SYS_TEXT_BASE) u-boot.elf: u-boot.bin - @$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o - @$(LD) u-boot-elf.o -o $@ \ - --defsym=$(PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \ - -Ttext=$(CONFIG_SYS_TEXT_BASE) + $(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o + $(call if_changed,u-boot-elf) # Rule to link u-boot # May be overridden by arch/$(ARCH)/config.mk -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 3/4] MIPS: add support for generating u-boot.elf
Define PLATFORM_ELFFLAGS for MIPS in order to be able to generate u-boot.elf Signed-off-by: Álvaro Fernández Rojas --- v4: Introduce changes suggested by Tom Rini: - __start is the standard for MIPS, not ARM. v3: Introduce changes suggested by Daniel Schwierzeck: - Add new patch. arch/mips/config.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/config.mk b/arch/mips/config.mk index dcd3460..2c72c15 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -36,6 +36,8 @@ OBJCOPYFLAGS += -O $(64bit-bfd) endif PLATFORM_CPPFLAGS += -D__MIPS__ +PLATFORM_ELFENTRY = "__start" +PLATFORM_ELFFLAGS += -B mips $(OBJCOPYFLAGS) # # From Linux arch/mips/Makefile -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 1/4] u-boot.elf: remove hard-coded arm64 flags
This is needed in order to allow building it for other archs. Move relocation comment to a better place. Remove no longer needed dts FIXME. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Tom Rini --- v4: no changes v3: Introduce changes suggested by Daniel Schwierzeck: - Split patches. - Avoid building it unconditionally. v2: Introduce changes suggested by Daniel Schwierzeck: - Avoid using a linker script. - Reuse aarch64 u-boot.elf generation for other archs. Makefile | 12 +--- arch/arm/config.mk | 6 ++ 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/Makefile b/Makefile index 131d62e..8730550 100644 --- a/Makefile +++ b/Makefile @@ -747,6 +747,9 @@ BOARD_SIZE_CHECK = endif # Statically apply RELA-style relocations (currently arm64 only) +# This is useful for arm64 where static relocation needs to be performed on +# the raw binary, but certain simulators only accept an ELF file (but don't +# do the relocation). ifneq ($(CONFIG_STATIC_RELA),) # $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base DO_STATIC_RELA = \ @@ -1180,14 +1183,9 @@ OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \ u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE $(call if_changed,pad_cat) -# Create a new ELF from a raw binary file. This is useful for arm64 -# where static relocation needs to be performed on the raw binary, -# but certain simulators only accept an ELF file (but don't do the -# relocation). -# FIXME refactor dts/Makefile to share target/arch detection +# Create a new ELF from a raw binary file. u-boot.elf: u-boot.bin - @$(OBJCOPY) -B aarch64 -I binary -O elf64-littleaarch64 \ - $< u-boot-elf.o + @$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o @$(LD) u-boot-elf.o -o $@ \ --defsym=_start=$(CONFIG_SYS_TEXT_BASE) \ -Ttext=$(CONFIG_SYS_TEXT_BASE) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 907c693..257ad09 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -30,6 +30,12 @@ PLATFORM_RELFLAGS+= $(LLVM_RELFLAGS) PLATFORM_CPPFLAGS += -D__ARM__ +ifdef CONFIG_ARM64 +PLATFORM_ELFFLAGS += -B aarch64 -O elf64-littleaarch64 +else +PLATFORM_ELFFLAGS += -B arm -O elf32-littlearm +endif + # Choose between ARM/Thumb instruction sets ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) AFLAGS_IMPLICIT_IT := $(call as-option,-Wa$(comma)-mimplicit-it=always) -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 0/4] u-boot.elf: support other archs
Provide an u-boot.elf binary for Broadcom MIPS platforms by re-using the already existing Makefile target for aarch64. This u-boot.elf binary should be used as a stage 2 loader until U-Boot can be replace the original Broadcom boot loader. Split patches from main BMIPS support. Álvaro Fernández Rojas (4): u-boot.elf: remove hard-coded arm64 flags u-boot.elf: allow overriding entry symbol MIPS: add support for generating u-boot.elf u-boot.elf: add quiet_cmd_u-boot-elf and cmd_u-boot-elf Makefile| 23 +-- arch/arm/config.mk | 6 ++ arch/mips/config.mk | 2 ++ 3 files changed, 21 insertions(+), 10 deletions(-) -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
