[U-Boot] [PATCH v3 1/2] Move CONFIG_SF_DUAL_FLASH to defconfig

[Mike Looijmans]

Move the only use of CONFIG_SF_DUAL_FLASH to defconfig. This makes the
associated topic_miamiplus.h header obsolete, so remove that as well.

Signed-off-by: Mike Looijmans 
---
 README| 6 --
 configs/topic_miamiplus_defconfig | 3 ++-
 drivers/mtd/spi/Kconfig   | 7 +++
 include/configs/topic_miami.h | 1 -
 include/configs/topic_miamiplus.h | 2 --
 scripts/config_whitelist.txt  | 1 -
 6 files changed, 9 insertions(+), 11 deletions(-)
 delete mode 100644 include/configs/topic_miamiplus.h

diff --git a/README b/README
index 9d351ec..c481016 100644
--- a/README
+++ b/README
@@ -2639,12 +2639,6 @@ The following options need to be configured:
Define this option to include a destructive SPI flash
test ('sf test').
 
-   CONFIG_SF_DUAL_FLASHDual flash memories
-
-   Define this option to use dual flash support where two flash
-   memories can be connected with a given cs line.
-   Currently Xilinx Zynq qspi supports these type of connections.
-
 - SystemACE Support:
CONFIG_SYSTEMACE
 
diff --git a/configs/topic_miamiplus_defconfig 
b/configs/topic_miamiplus_defconfig
index 10762f8..535ce6d 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SYS_VENDOR="topic"
-CONFIG_SYS_CONFIG_NAME="topic_miamiplus"
+CONFIG_SYS_CONFIG_NAME="topic_miami"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x400
 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
@@ -28,6 +28,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_RAM=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SF_DUAL_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 5ca0a71..5700859 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -42,6 +42,13 @@ config SPI_FLASH_BAR
  Bank/Extended address registers are used to access the flash
  which has size > 16MiB in 3-byte addressing.
 
+config SF_DUAL_FLASH
+   bool "SPI DUAL flash memory support"
+   depends on SPI_FLASH
+   help
+ Enable this option to support two flash memories connected to a single
+ controller. Currently Xilinx Zynq qspi supports this.
+
 if SPI_FLASH
 
 config SPI_FLASH_ATMEL
diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
index a289225..ee46d3a 100644
--- a/include/configs/topic_miami.h
+++ b/include/configs/topic_miami.h
@@ -56,7 +56,6 @@
 #undef CONFIG_SF_DEFAULT_SPEED
 #define CONFIG_SF_DEFAULT_SPEED10800
 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#undef CONFIG_SF_DUAL_FLASH
 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
 #undef CONFIG_SPI_FLASH_WINBOND
 #undef CONFIG_SPI_FLASH_ISSI
diff --git a/include/configs/topic_miamiplus.h 
b/include/configs/topic_miamiplus.h
deleted file mode 100644
index 46ca6bd..000
--- a/include/configs/topic_miamiplus.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include "topic_miami.h"
-#define CONFIG_SF_DUAL_FLASH
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index e8f49eb..642c433 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2401,7 +2401,6 @@ CONFIG_SF_DEFAULT_BUS
 CONFIG_SF_DEFAULT_CS
 CONFIG_SF_DEFAULT_MODE
 CONFIG_SF_DEFAULT_SPEED
-CONFIG_SF_DUAL_FLASH
 CONFIG_SGI_IP28
 CONFIG_SH4_PCI
 CONFIG_SH73A0
-- 
1.9.1

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[U-Boot] [PATCH v3 0/2] Add support for the topic-miamilite

[Mike Looijmans]

These two patches add support for the topic-miamilite board.


v2: Rebased, no change
v3: Added missing Kconfig


v2: Moved CONFIG_SF_DUAL_FLASH to defconfig
v3: No change, resend as series
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[U-Boot] [PATCH v3 2/2] ARM: zynq: Add support for the topic-miamilite system-on-module

[Mike Looijmans]

The topic-miamilite SoM contains a Zynq xc7z010 SoC, 1GB DDR3L RAM,
64MB dual-parallel QSPI NOR flash and clock sources.

Signed-off-by: Mike Looijmans 
---
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/zynq-topic-miamilite.dts  |  17 ++
 .../topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c | 227 +
 board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt |  61 ++
 configs/topic_miamilite_defconfig  |  53 +
 5 files changed, 359 insertions(+)
 create mode 100644 arch/arm/dts/zynq-topic-miamilite.dts
 create mode 100644 board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
 create mode 100644 board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt
 create mode 100644 configs/topic_miamilite_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2b1a4e9..8745f04 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -122,6 +122,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
zynq-topic-miami.dtb \
+   zynq-topic-miamilite.dtb \
zynq-topic-miamiplus.dtb \
zynq-zc770-xm010.dtb \
zynq-zc770-xm011.dtb \
diff --git a/arch/arm/dts/zynq-topic-miamilite.dts 
b/arch/arm/dts/zynq-topic-miamilite.dts
new file mode 100644
index 000..f88cb4b
--- /dev/null
+++ b/arch/arm/dts/zynq-topic-miamilite.dts
@@ -0,0 +1,17 @@
+/*
+ * Topic Miami Lite board DTS
+ *
+ * Copyright (C) 2017 Topic Embedded Products
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include "zynq-topic-miami.dts"
+
+/ {
+   model = "Topic Miami Lite Zynq Board";
+   compatible = "topic,miamilite", "xlnx,zynq-7000";
+};
+
+ {
+   is-dual = <1>;
+};
diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c 
b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
new file mode 100644
index 000..ec0cc7d
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
@@ -0,0 +1,227 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include "../ps7_init_gpl.h"
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0xF8000110, 0x0030U, 0x000FA220U),
+   EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+   EMIT_MASKWRITE(0xF8000100, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000100, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000100, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0001U),
+   EMIT_MASKWRITE(0xF8000100, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+   EMIT_MASKWRITE(0xF8000114, 0x0030U, 0x0012C220U),
+   EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x0002U),
+   EMIT_MASKWRITE(0xF8000104, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000104, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000104, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0002U),
+   EMIT_MASKWRITE(0xF8000104, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF8000124, 0xFFF3U, 0x0C23U),
+   EMIT_MASKWRITE(0xF8000118, 0x0030U, 0x00113220U),
+   EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x00024000U),
+   EMIT_MASKWRITE(0xF8000108, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000108, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000108, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0004U),
+   EMIT_MASKWRITE(0xF8000108, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF804, 0xU, 0x767BU),
+   EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00302301U),
+   EMIT_MASKWRITE(0xF8000138, 0x0011U, 0x0011U),
+   EMIT_MASKWRITE(0xF800013C, 0x0011U, 0x0011U),
+   EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100141U),
+   EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100141U),
+   EMIT_MASKWRITE(0xF8000148, 0x3F31U, 0x0C01U),
+   EMIT_MASKWRITE(0xF800014C, 0x3F31U, 0x0601U),
+   EMIT_MASKWRITE(0xF8000150, 0x3F33U, 0x1803U),
+   EMIT_MASKWRITE(0xF8000154, 0x3F33U, 0x0C03U),
+   EMIT_MASKWRITE(0xF8000158, 0x3F33U, 0x0601U),
+   EMIT_MASKWRITE(0xF8000168, 0x3F31U, 0x0601U),
+   EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00100C00U),
+   EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100C00U),
+   EMIT_MASKWRITE(0xF8000190, 0x03F03F30U, 0x00100600U),
+   EMIT_MASKWRITE(0xF80001A0, 0x03F03F30U, 0x00101800U),
+   EMIT_MASKWRITE(0xF80001C4, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
+   

[U-Boot] [PATCH v9 6/8] arm: socfpga: Enable FPGA driver on SPL

[tien . fong . chee]

From: Tien Fong Chee 

This patch is for enabling FPGA driver support on SPL

Signed-off-by: Tien Fong Chee 
---
 configs/socfpga_arria5_defconfig   | 1 +
 configs/socfpga_cyclone5_defconfig | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_de10_nano_defconfig| 1 +
 configs/socfpga_de1_soc_defconfig  | 1 +
 configs/socfpga_is1_defconfig  | 1 +
 configs/socfpga_mcvevk_defconfig   | 1 +
 configs/socfpga_sockit_defconfig   | 1 +
 configs/socfpga_socrates_defconfig | 1 +
 configs/socfpga_sr1500_defconfig   | 1 +
 configs/socfpga_vining_fpga_defconfig  | 1 +
 11 files changed, 11 insertions(+)

diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 6f2a06f..4b1e252 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/socfpga_cyclone5_defconfig 
b/configs/socfpga_cyclone5_defconfig
index 1047657..fe7ac08 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/socfpga_de0_nano_soc_defconfig 
b/configs/socfpga_de0_nano_soc_defconfig
index 72a9e5d..d86a9d6 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/socfpga_de10_nano_defconfig 
b/configs/socfpga_de10_nano_defconfig
index 67864cf..ac8ca70 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/socfpga_de1_soc_defconfig 
b/configs/socfpga_de1_soc_defconfig
index 35c4484..cc0a35d 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index ae688f8..ccfed7a 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index c5e3b7b..9bcb47d 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 3ff7bb7..ef54e1f 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/socfpga_socrates_defconfig 
b/configs/socfpga_socrates_defconfig
index fb9c13f..78daf26 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index d90d6a1..4a12379 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -16,6 +16,7 @@ CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/socfpga_vining_fpga_defconfig 
b/configs/socfpga_vining_fpga_defconfig
index c3fbe40..3fc37dc 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ 

[U-Boot] [PATCH v9 5/8] drivers: Enable FPGA driver build on SPL

[tien . fong . chee]

From: Tien Fong Chee 

Enable FPGA driver build for SPL because FPGA driver is needed for SPL
to configure and getting DDR up before loading U-boot into DDR and
booting from there.

FPGA driver build on SPL must be enabled 1st before applying patch 8 to
avoid build failed, because fpga_manager which would be moved to
drivers/fpga and those functions are expected to be available in SPL.

Signed-off-by: Tien Fong Chee 
---
 drivers/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/Makefile b/drivers/Makefile
index 64c39d3..4478212 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
 endif
 
 ifdef CONFIG_TPL_BUILD
-- 
2.2.0

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[U-Boot] [PATCH v9 7/8] arm: socfpga: Move FPGA manager driver to FPGA driver

[tien . fong . chee]

From: Tien Fong Chee 

Move FPGA manager driver which is Gen5 specific code from arch/arm/
into FPGA driver at driver/fpga/. No functional change.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/Makefile   |  1 -
 arch/arm/mach-socfpga/fpga_manager.c | 78 
 drivers/fpga/socfpga_gen5.c  | 54 +
 3 files changed, 54 insertions(+), 79 deletions(-)
 delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 286bfef..824cd8e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -20,7 +20,6 @@ obj-y += reset_manager_gen5.o
 obj-y  += scan_manager.o
 obj-y  += system_manager_gen5.o
 obj-y  += wrap_pll_config.o
-obj-y  += fpga_manager.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
diff --git a/arch/arm/mach-socfpga/fpga_manager.c 
b/arch/arm/mach-socfpga/fpga_manager.c
deleted file mode 100644
index f909573..000
--- a/arch/arm/mach-socfpga/fpga_manager.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation 
- * All rights reserved.
- *
- * This file contains only support functions used also by the SoCFPGA
- * platform code, the real meat is located in drivers/fpga/socfpga.c .
- *
- * SPDX-License-Identifier:BSD-3-Clause
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Timeout count */
-#define FPGA_TIMEOUT_CNT   0x100
-
-static struct socfpga_fpga_manager *fpgamgr_regs =
-   (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-
-/* Check whether FPGA Init_Done signal is high */
-static int is_fpgamgr_initdone_high(void)
-{
-   unsigned long val;
-
-   val = readl(_regs->gpio_ext_porta);
-   return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
-}
-
-/* Get the FPGA mode */
-int fpgamgr_get_mode(void)
-{
-   unsigned long val;
-
-   val = readl(_regs->stat);
-   return val & FPGAMGRREGS_STAT_MODE_MASK;
-}
-
-/* Check whether FPGA is ready to be accessed */
-int fpgamgr_test_fpga_ready(void)
-{
-   /* Check for init done signal */
-   if (!is_fpgamgr_initdone_high())
-   return 0;
-
-   /* Check again to avoid false glitches */
-   if (!is_fpgamgr_initdone_high())
-   return 0;
-
-   if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
-   return 0;
-
-   return 1;
-}
-
-/* Poll until FPGA is ready to be accessed or timeout occurred */
-int fpgamgr_poll_fpga_ready(void)
-{
-   unsigned long i;
-
-   /* If FPGA is blank, wait till WD invoke warm reset */
-   for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
-   /* check for init done signal */
-   if (!is_fpgamgr_initdone_high())
-   continue;
-   /* check again to avoid false glitches */
-   if (!is_fpgamgr_initdone_high())
-   continue;
-   return 1;
-   }
-
-   return 0;
-}
diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c
index 3dfb030..d8f222a 100644
--- a/drivers/fpga/socfpga_gen5.c
+++ b/drivers/fpga/socfpga_gen5.c
@@ -21,6 +21,60 @@ static struct socfpga_fpga_manager *fpgamgr_regs =
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
+/* Check whether FPGA Init_Done signal is high */
+static int is_fpgamgr_initdone_high(void)
+{
+   unsigned long val;
+
+   val = readl(_regs->gpio_ext_porta);
+   return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
+}
+
+/* Get the FPGA mode */
+int fpgamgr_get_mode(void)
+{
+   unsigned long val;
+
+   val = readl(_regs->stat);
+   return val & FPGAMGRREGS_STAT_MODE_MASK;
+}
+
+/* Check whether FPGA is ready to be accessed */
+int fpgamgr_test_fpga_ready(void)
+{
+   /* Check for init done signal */
+   if (!is_fpgamgr_initdone_high())
+   return 0;
+
+   /* Check again to avoid false glitches */
+   if (!is_fpgamgr_initdone_high())
+   return 0;
+
+   if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
+   return 0;
+
+   return 1;
+}
+
+/* Poll until FPGA is ready to be accessed or timeout occurred */
+int fpgamgr_poll_fpga_ready(void)
+{
+   unsigned long i;
+
+   /* If FPGA is blank, wait till WD invoke warm reset */
+   for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+   /* check for init done signal */
+   if (!is_fpgamgr_initdone_high())
+   continue;
+   /* check again to avoid false glitches */
+   if (!is_fpgamgr_initdone_high())
+   continue;
+   return 1;
+   }
+
+   return 0;
+}
+
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)
 {
-- 
2.2.0

[U-Boot] [PATCH v9 8/8] arm: socfpga: Add FPGA driver support for Arria 10

[tien . fong . chee]

From: Tien Fong Chee 

Add FPGA driver support for Arria 10.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |   2 +
 .../include/mach/fpga_manager_arria10.h| 100 +
 configs/socfpga_arria10_defconfig  |   2 +
 drivers/fpga/Makefile  |   1 +
 drivers/fpga/socfpga_arria10.c | 479 +
 include/configs/socfpga_common.h   |   3 +-
 6 files changed, 585 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
 create mode 100644 drivers/fpga/socfpga_arria10.c

diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
index b046c2c..a21c716 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -12,6 +12,8 @@
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
 #endif
 
 /* FPGA CD Ratio Value */
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
new file mode 100644
index 000..9cbf696
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _FPGA_MANAGER_ARRIA10_H_
+#define _FPGA_MANAGER_ARRIA10_H_
+
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK  BIT(0)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK   BIT(2)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSKBIT(3)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSKBIT(4)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSKBIT(6)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK  BIT(8)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK   BIT(9)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSKBIT(10)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK   BIT(11)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSKBIT(12)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSKBIT(13)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK  BIT(16)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK  BIT(17)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK  BIT(18)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
+   ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
+   ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
+   ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK   BIT(24)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSKBIT(25)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK  BIT(28)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSKBIT(29)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB  16
+
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK  BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK  BIT(1)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK  BIT(2)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK  BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK   BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK   BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK   BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK   BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK  BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK  BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK  BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK  0x0003
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB  16
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_fpga_manager {
+   u32  _pad_0x0_0x7[2];
+   u32  dclkcnt;
+   u32  dclkstat;
+   u32  gpo;
+   u32  gpi;
+   u32  misci;
+   u32  _pad_0x1c_0x2f[5];
+   u32  emr_data0;
+   u32  emr_data1;
+   u32  emr_data2;
+   u32  emr_data3;
+   u32  emr_data4;
+   u32  emr_data5;
+   u32  emr_valid;
+   u32  emr_en;
+   u32  jtag_config;
+   u32  jtag_status;
+   u32  jtag_kick;
+   u32  _pad_0x5c_0x5f;
+   u32  jtag_data_w;
+   u32  jtag_data_r;
+   u32  

[U-Boot] [PATCH v9 4/8] arm: socfpga: Convert FPGA_SOCFPGA configuration to Kconfig

[tien . fong . chee]

From: Tien Fong Chee 

This converts the following to Kconfig:
   CONFIG_FPGA_SOCFPGA

Signed-off-by: Tien Fong Chee 
---
 configs/astro_mcf5373l_defconfig   | 1 +
 configs/socfpga_arria5_defconfig   | 1 +
 configs/socfpga_cyclone5_defconfig | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_de10_nano_defconfig| 1 +
 configs/socfpga_de1_soc_defconfig  | 1 +
 configs/socfpga_is1_defconfig  | 1 +
 configs/socfpga_mcvevk_defconfig   | 1 +
 configs/socfpga_sockit_defconfig   | 1 +
 configs/socfpga_socrates_defconfig | 1 +
 configs/socfpga_sr1500_defconfig   | 1 +
 configs/socfpga_vining_fpga_defconfig  | 1 +
 drivers/fpga/Kconfig   | 8 
 include/configs/socfpga_common.h   | 3 ---
 14 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index d5e8430..80fb1fa 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -10,4 +10,5 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index a565384..6f2a06f 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_cyclone5_defconfig 
b/configs/socfpga_cyclone5_defconfig
index 06fc82c..1047657 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig 
b/configs/socfpga_de0_nano_soc_defconfig
index 0697e2e..72a9e5d 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -39,6 +39,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_de10_nano_defconfig 
b/configs/socfpga_de10_nano_defconfig
index cd64fb9..67864cf 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -37,6 +37,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_de1_soc_defconfig 
b/configs/socfpga_de1_soc_defconfig
index bba90be..35c4484 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -38,6 +38,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index 058791e..ae688f8 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -34,6 +34,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 627b90f..c5e3b7b 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -38,6 +38,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index bf5d63d..3ff7bb7 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_socrates_defconfig 
b/configs/socfpga_socrates_defconfig
index 5915faf..fb9c13f 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -41,6 +41,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 4468d3b..d90d6a1 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -40,6 +40,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y
diff --git 

[U-Boot] [PATCH v9 3/8] arm: socfpga: Convert FPGA and FPGA_ALTERA configuration to Kconfig

[tien . fong . chee]

From: Tien Fong Chee 

This converts the following to Kconfig:
   CONFIG_FPGA
   CONFIG_FPGA_ALTERA

Signed-off-by: Tien Fong Chee 
---
 configs/theadorable_debug_defconfig | 1 +
 configs/theadorable_defconfig   | 1 +
 include/configs/astro_mcf5373l.h| 2 --
 include/configs/theadorable.h   | 2 --
 4 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/configs/theadorable_debug_defconfig 
b/configs/theadorable_debug_defconfig
index 2164237..e07b7b6 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig
index d5eef70..3d2977c 100644
--- a/configs/theadorable_defconfig
+++ b/configs/theadorable_defconfig
@@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_PARTITION_UUIDS is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index 8899579..f4acea1 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -201,10 +201,8 @@
 #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
 
 #define CONFIG_FPGA_COUNT  1
-#define CONFIG_FPGA
 #defineCONFIG_FPGA_XILINX
 #defineCONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT   1000
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 2a671e8..5459f4f 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -89,8 +89,6 @@
 #define CONFIG_SYS_MEM_TOP_HIDE0x8
 
 /* FPGA programming support */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_STRATIX_V
 
 /*
-- 
2.2.0

___
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[U-Boot] [PATCH v9 2/8] arm: socfpga: Restructure FPGA driver in the preparation to support A10

[tien . fong . chee]

From: Tien Fong Chee 

Move FPGA driver which is Gen5 specific code into Gen5 driver file
and keeping common FPGA driver intact. All the changes are still keeping
in driver/fpga/ and no functional change. Subsequent patch would move
FPGA manager driver from arch/arm into driver/fpga/.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/Makefile |   2 +-
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |  68 +-
 .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |  69 +++---
 drivers/fpga/Makefile  |   1 +
 drivers/fpga/socfpga.c | 241 +
 drivers/fpga/{socfpga.c => socfpga_gen5.c} |  54 +
 6 files changed, 49 insertions(+), 386 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => 
fpga_manager_gen5.h} (57%)
 copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (83%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 41b779c..286bfef 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,7 +9,6 @@
 
 obj-y  += board.o
 obj-y  += clock_manager.o
-obj-y  += fpga_manager.o
 obj-y  += misc.o
 obj-y  += reset_manager.o
 obj-y  += timer.o
@@ -21,6 +20,7 @@ obj-y += reset_manager_gen5.o
 obj-y  += scan_manager.o
 obj-y  += system_manager_gen5.o
 obj-y  += wrap_pll_config.o
+obj-y  += fpga_manager.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
index a077e22..b046c2c 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2012-2017 Altera Corporation 
  * All rights reserved.
  *
  * SPDX-License-Identifier:BSD-3-Clause
@@ -10,58 +10,9 @@
 
 #include 
 
-struct socfpga_fpga_manager {
-   /* FPGA Manager Module */
-   u32 stat;   /* 0x00 */
-   u32 ctrl;
-   u32 dclkcnt;
-   u32 dclkstat;
-   u32 gpo;/* 0x10 */
-   u32 gpi;
-   u32 misci;  /* 0x18 */
-   u32 _pad_0x1c_0x82c[517];
-
-   /* Configuration Monitor (MON) Registers */
-   u32 gpio_inten; /* 0x830 */
-   u32 gpio_intmask;
-   u32 gpio_inttype_level;
-   u32 gpio_int_polarity;
-   u32 gpio_intstatus; /* 0x840 */
-   u32 gpio_raw_intstatus;
-   u32 _pad_0x848;
-   u32 gpio_porta_eoi;
-   u32 gpio_ext_porta; /* 0x850 */
-   u32 _pad_0x854_0x85c[3];
-   u32 gpio_1s_sync;   /* 0x860 */
-   u32 _pad_0x864_0x868[2];
-   u32 gpio_ver_id_code;
-   u32 gpio_config_reg2;   /* 0x870 */
-   u32 gpio_config_reg1;
-};
-
-#define FPGAMGRREGS_STAT_MODE_MASK 0x7
-#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
-#define FPGAMGRREGS_STAT_MSEL_LSB  3
-
-#define FPGAMGRREGS_CTRL_CFGWDTH_MASK  0x200
-#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
-#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK  0x4
-#define FPGAMGRREGS_CTRL_NCE_MASK  0x2
-#define FPGAMGRREGS_CTRL_EN_MASK   0x1
-#define FPGAMGRREGS_CTRL_CDRATIO_LSB   6
-
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK0x8
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
-
-/* FPGA Mode */
-#define FPGAMGRREGS_MODE_FPGAOFF   0x0
-#define FPGAMGRREGS_MODE_RESETPHASE0x1
-#define FPGAMGRREGS_MODE_CFGPHASE  0x2
-#define FPGAMGRREGS_MODE_INITPHASE 0x3
-#define FPGAMGRREGS_MODE_USERMODE  0x4
-#define FPGAMGRREGS_MODE_UNKNOWN   0x5
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include 
+#endif
 
 /* FPGA CD Ratio Value */
 #define CDRATIO_x1 0x0
@@ -69,9 +20,14 @@ struct socfpga_fpga_manager {
 #define CDRATIO_x4 0x2
 #define CDRATIO_x8 0x3
 
-/* SoCFPGA support functions */
-int fpgamgr_test_fpga_ready(void);
-int fpgamgr_poll_fpga_ready(void);
+#ifndef __ASSEMBLY__
+
+/* Common prototypes */
 int fpgamgr_get_mode(void);
+int fpgamgr_poll_fpga_ready(void);
+void fpgamgr_program_write(const void *rbf_data, size_t rbf_size);
+int fpgamgr_test_fpga_ready(void);
+int fpgamgr_dclkcnt_set(unsigned long cnt);
 
+#endif /* __ASSEMBLY__ */
 #endif /* _FPGA_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
similarity index 57%
copy from arch/arm/mach-socfpga/include/mach/fpga_manager.h
copy to 

[U-Boot] [PATCH v9 1/8] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset

[tien . fong . chee]

From: Tien Fong Chee 

Remove parameter from socfpga_bridges_reset(), and keeping this function
for single purpose which is just triggering reset on bridges.
socfpga_reset_deassert_bridges_handoff() can be called for releasing reset
on any bridges based on the bridge setting defined in fdt.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h | 2 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c  | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 7922db8..b6d7f4f 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -17,7 +17,7 @@ int socfpga_reset_deassert_bridges_handoff(void);
 void socfpga_reset_assert_fpga_connected_peripherals(void);
 void socfpga_reset_deassert_osc1wd0(void);
 void socfpga_reset_uart(int assert);
-int socfpga_bridges_reset(int enable);
+int socfpga_bridges_reset(void);
 
 struct socfpga_reset_manager {
u32 stat;
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c 
b/arch/arm/mach-socfpga/reset_manager_arria10.c
index d8c858c..66f1ec2 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -318,13 +318,13 @@ void socfpga_per_reset_all(void)
 }
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
 {
/* For SoCFPGA-VT, this is NOP. */
return 0;
 }
 #else
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
 {
int ret;
 
-- 
2.2.0

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[U-Boot] [PATCH v9 0/8] Add Intel Arria 10 SoC FPGA driver

[tien . fong . chee]

From: Tien Fong Chee 

This is the 9th version of patchset to adds support for Intel Arria 10 SoC FPGA
driver. This version mainly resolved comments from Marek in [v8].
This series is working on top of u-boot-socfpga.git - 
http://git.denx.de/u-boot-socfpga.git

[v8]: https://www.mail-archive.com/u-boot@lists.denx.de/msg252196.html

v8 -> v9 changes:
-
- Separate patch for different Kconfig conversion.
- Swapping order between patch 4 and patch 5 of v7.
- Updated commit messages in patch 5.

Patchset history

[v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg247788.html
[v2]: https://www.mail-archive.com/u-boot@lists.denx.de/msg248541.html
[v3]: https://www.mail-archive.com/u-boot@lists.denx.de/msg249160.html
[v4]: https://www.mail-archive.com/u-boot@lists.denx.de/msg250149.html
[v5]: https://www.mail-archive.com/u-boot@lists.denx.de/msg250517.html
[v6]: https://www.mail-archive.com/u-boot@lists.denx.de/msg250687.html
[v7]: https://www.mail-archive.com/u-boot@lists.denx.de/msg251213.html

Tien Fong Chee (8):
  arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
  arm: socfpga: Restructure FPGA driver in the preparation to support
A10
  arm: socfpga: Convert FPGA and FPGA_ALTERA configuration to Kconfig
  arm: socfpga: Convert FPGA_SOCFPGA configuration to Kconfig
  drivers: Enable FPGA driver build on SPL
  arm: socfpga: Enable FPGA driver on SPL
  arm: socfpga: Move FPGA manager driver to FPGA driver
  arm: socfpga: Add FPGA driver support for Arria 10

 arch/arm/mach-socfpga/Makefile |   1 -
 arch/arm/mach-socfpga/fpga_manager.c   |  78 
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |  70 +--
 .../include/mach/fpga_manager_arria10.h| 100 +
 .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |  69 ++-
 .../include/mach/reset_manager_arria10.h   |   2 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c  |   4 +-
 configs/astro_mcf5373l_defconfig   |   1 +
 configs/socfpga_arria10_defconfig  |   2 +
 configs/socfpga_arria5_defconfig   |   2 +
 configs/socfpga_cyclone5_defconfig |   2 +
 configs/socfpga_de0_nano_soc_defconfig |   2 +
 configs/socfpga_de10_nano_defconfig|   2 +
 configs/socfpga_de1_soc_defconfig  |   2 +
 configs/socfpga_is1_defconfig  |   2 +
 configs/socfpga_mcvevk_defconfig   |   2 +
 configs/socfpga_sockit_defconfig   |   2 +
 configs/socfpga_socrates_defconfig |   2 +
 configs/socfpga_sr1500_defconfig   |   2 +
 configs/socfpga_vining_fpga_defconfig  |   2 +
 configs/theadorable_debug_defconfig|   1 +
 configs/theadorable_defconfig  |   1 +
 drivers/Makefile   |   1 +
 drivers/fpga/Kconfig   |   8 +
 drivers/fpga/Makefile  |   2 +
 drivers/fpga/socfpga.c | 241 +--
 drivers/fpga/socfpga_arria10.c | 479 +
 drivers/fpga/{socfpga.c => socfpga_gen5.c} |  98 ++---
 include/configs/astro_mcf5373l.h   |   2 -
 include/configs/socfpga_common.h   |   6 +-
 include/configs/theadorable.h  |   2 -
 31 files changed, 719 insertions(+), 471 deletions(-)
 delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
 copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => 
fpga_manager_gen5.h} (57%)
 create mode 100644 drivers/fpga/socfpga_arria10.c
 copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (85%)

-- 
2.2.0

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[U-Boot] standalone application

[Ran Shalit]

Hello,

I am trying to load standalone application.
It works fine with the hello_world example ( bin format).
Then I move to build and run another application (uc/os) in eclipse.
The problem is that the bin format is very large.
Is there a way to load other a standalone application in another format ?

Regards,
Ran
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Re: [U-Boot] [linux-sunxi] [RFC PATCH 7/8] sunxi: Add basic PSCI implementation for multi-cluster SoCs

[Chen-Yu Tsai]

On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng  wrote:
> From: Chen-Yu Tsai 
>
> Allwinner A80 and A83T SoCs have two clusters of CPU, each cluster
> contains 4 cores. A80 is Cortex-A15 + Cortex-A7 configuration, while
> A83T has two clusters of Cortex-A7.
>
> This patch adds a basic version that allows bringing up the four cores
> in the first cluster. The structure is based on existing sunxi PSCI code.
>
> Signed-off-by: Chen-Yu Tsai 
> [Icenowy: adapt for A83T]
> Signed-off-by: Icenowy Zheng 
> ---
>  arch/arm/cpu/armv7/sunxi/Makefile|   4 +
>  arch/arm/cpu/armv7/sunxi/psci-mcpm.c | 258 
> +++
>  2 files changed, 262 insertions(+)
>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci-mcpm.c
>

I suggest using --find-copies and --find-copies-harder when you
generate the patch.
It should limit the patch to differences between psci.c and psci-mcpm.c.

> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
> b/arch/arm/cpu/armv7/sunxi/Makefile
> index 8c026ff052..c789f686fd 100644
> --- a/arch/arm/cpu/armv7/sunxi/Makefile
> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
> @@ -14,8 +14,12 @@ obj-$(CONFIG_MACH_SUN8I_H3)  += tzpc.o
>  obj-$(CONFIG_MACH_SUN8I_A83T)  += tzpc.o
>
>  ifndef CONFIG_SPL_BUILD
> +ifdef CONFIG_MACH_SUN8I_A83T
> +obj-$(CONFIG_ARMV7_PSCI)   += psci-mcpm.o
> +else
>  obj-$(CONFIG_ARMV7_PSCI)   += psci.o
>  endif
> +endif
>
>  ifdef CONFIG_SPL_BUILD
>  obj-y  += fel_utils.o
> diff --git a/arch/arm/cpu/armv7/sunxi/psci-mcpm.c 
> b/arch/arm/cpu/armv7/sunxi/psci-mcpm.c
> new file mode 100644
> index 00..ba8d669c7e
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/sunxi/psci-mcpm.c
> @@ -0,0 +1,258 @@
> +/*
> + * Copyright (C) 2016
> + * Author: Chen-Yu Tsai 
> + *
> + * Based on assembly code by Marc Zyngier ,
> + * which was based on code by Carl van Schaik .
> + *
> + * SPDX-License-Identifier:GPL-2.0
> + */
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +/*
> + * NOTE dense CPU IDs (0~3 for first cluster of 4 cores, 4~7 for the
> + * second cluster) are used throughout the PSCI code. Any MPIDR style
> + * values must be converted.
> + */
> +
> +/*
> + * Provide a dense CPU ID for 2-cluster systems. This must be coded in
> + * assembly as it gets called from psci_stack_setup, when the stack isn't
> + * available yet.
> + *
> + * Only r0 and r3 is usable. r8 - r12 are available if this function is
> + * only called from psci_stack_setup, which we cannot guarantee.
> + */
> +u32 __secure __naked psci_get_cpu_id(void)
> +{
> +   asm volatile (
> +   "mrcp15, 0, r3, c0, c0, 5   @ Get MPIDR\n"
> +   "lsrr0, r3, #6\n"
> +   "andr3, r3, #3\n"
> +   "andr0, r0, #4\n"
> +   "orrr0, r0, r3\n"
> +   "bx lr\n"
> +   );
> +
> +   /*
> +* The last five lines are the compiler generated assembly code for
> +*
> +*  return (reg & 0x3) | (((reg >> 8) & 0x1) << 2);
> +*
> +* We can't guarantee that all compilers correctly use only r0 and
> +* r3, so we use inline assembly here.
> +*/
> +}
> +
> +static void __secure cp15_write_cntp_tval(u32 tval)
> +{
> +   asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
> +}
> +
> +static void __secure cp15_write_cntp_ctl(u32 val)
> +{
> +   asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
> +}
> +
> +static u32 __secure cp15_read_cntp_ctl(void)
> +{
> +   u32 val;
> +
> +   asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
> +
> +   return val;
> +}
> +
> +#define ONE_US (COUNTER_FREQUENCY / 100)
> +
> +/* Use a different name to avoid clashing with the non-secure function */
> +static void __secure __udelay_sec(unsigned long us)
> +{
> +   u32 reg = ONE_US * us;
> +
> +   cp15_write_cntp_tval(reg);
> +   isb();
> +   cp15_write_cntp_ctl(3);
> +
> +   do {
> +   isb();
> +   reg = cp15_read_cntp_ctl();
> +   } while (!(reg & BIT(2)));
> +
> +   cp15_write_cntp_ctl(0);
> +   isb();
> +}
> +
> +static void __secure clamp_release(u32 *clamp)
> +{
> +   writel(0xff, clamp);
> +   __udelay_sec(10);
> +   writel(0xfe, clamp);
> +   __udelay_sec(10);
> +   writel(0xf8, clamp);
> +   __udelay_sec(10);
> +   writel(0xf0, clamp);
> +   __udelay_sec(10);
> +   writel(0x00, clamp);
> +}
> +
> +static void __secure clamp_set(u32 *clamp)
> +{
> +   writel(0xff, clamp);
> +}
> +
> +static void __secure sunxi_core_power_switch(u32 *clamp, u32 *pwroff,
> +bool on, int cpu)
> +{
> +   if (on) {
> +   /* Release power clamp */
> +   clamp_release(clamp);
> +
> +  

Re: [U-Boot] [PATCH] drivers/net/phy/fixed: do not overwrite addr

[Hannes Schmelzer]

On 06/06/2017 02:57 PM, Christian Gmeiner wrote:

2017-06-06 14:51 GMT+02:00 Hannes Schmelzer
:

"U-Boot"  schrieb am 06.06.2017 14:35:29:


Von: Christian Gmeiner 
An: u-boot@lists.denx.de,
Kopie: joe.hershber...@ni.com, oe5...@oevsv.at
Datum: 06.06.2017 14:35
Betreff: [U-Boot] [PATCH] drivers/net/phy/fixed: do not overwrite addr
Gesendet von: "U-Boot" 

phy_device_create(..) sets the addr of phy_device with a sane value.
There is no need overwrite it.

Hi Christian,

The addr=0 was not an accident.
Since there is no real phy in this case outside, i did set the address to
zero (no real phy has address #0),
later on in the board_phy_config(...) i look at the phydev->addr for
detecting that i deal with the "fixed-link" driver.

But for sure there are better ways to handle this, any suggestion ?


I have a similar use case where I have one variant of a device with
fixed-link and an
other variant with a 'real' phy.

Here is how I handle that case:

---8<--

int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
{
 int phy_reg;

 /* MR variant has a fixed phy at address 5 */
 if (addr == 5) {
 *phy_id = PHY_FIXED_ID;
 return 0;
 }

 /* Grab the bits from PHYIR1, and put them
  * in the upper half */
 phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);

 if (phy_reg < 0)
 return -EIO;

 *phy_id = (phy_reg & 0x) << 16;

 /* Grab the bits from PHYIR2, and put them in the lower half */
 phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);

 if (phy_reg < 0)
 return -EIO;

 *phy_id |= (phy_reg & 0x);

 return 0;
}

int board_eth_init(bd_t *bis)
{
 uint32_t base = IMX_FEC_BASE;
 struct mii_dev *bus = NULL;
 struct phy_device *phydev = NULL;
 int ret;

 setup_iomux_enet();

 bus = fec_get_miibus(base, -1);
 if (!bus)
 return -EINVAL;

 /* scan phy 0 and 5 */
 phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
 if (!phydev) {
 ret = -EINVAL;
 goto free_bus;
 }

 /* depending on the phy address we can detect our board version */
 if (phydev->addr == 0)
 setenv("boardver", "");
 else
 setenv("boardver", "mr");

 ret = fec_probe(bis, -1, base, bus, phydev);
 if (ret)
 goto free_phydev;

 return 0;

free_phydev:
 free(phydev);
free_bus:
 free(bus);
 return ret;
}

---8<--

As you can see I use phydev->addr to detect my board variant and with this patch
everything works as expected.

Hi Christian,

yes doing that stuff using the phy-id is much more elegant.
I will adapt my board-code doing so.

Reviewed-by: Hannes Schmelzer 
Tested-by: Hannes Schmelzer 

greets
--
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https://www.youtube.com/user/AloryOFFICIAL
https://soundcloud.com/christian-gmeiner

cheers,
Hannes

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Re: [U-Boot] [PATCH v3 4/6] drivers/i2c/muxes/pca954x: Add pca9547 I2C mux support

[Heiko Schocher]

Hello Marek,

Am 06.06.2017 um 14:04 schrieb Marek Behun:

From: Marek Behún 

This I2C mux is found, for example, on the Turris Omnia board.

Signed-off-by: Marek Behun 


Reviewed-by: Heiko Schocher 

bye,
Heiko


diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c
index 1a6761858c..383f72f552 100644
--- a/drivers/i2c/muxes/pca954x.c
+++ b/drivers/i2c/muxes/pca954x.c
@@ -13,11 +13,40 @@

  DECLARE_GLOBAL_DATA_PTR;

+enum pca_type {
+   PCA9544,
+   PCA9547,
+   PCA9548
+};
+
+struct chip_desc {
+   u8 enable;
+   enum muxtype {
+   pca954x_ismux = 0,
+   pca954x_isswi,
+   } muxtype;
+};
+
  struct pca954x_priv {
u32 addr; /* I2C mux address */
u32 width; /* I2C mux width - number of busses */
  };

+static const struct chip_desc chips[] = {
+   [PCA9544] = {
+   .enable = 0x4,
+   .muxtype = pca954x_ismux,
+   },
+   [PCA9547] = {
+   .enable = 0x8,
+   .muxtype = pca954x_ismux,
+   },
+   [PCA9548] = {
+   .enable = 0x8,
+   .muxtype = pca954x_isswi,
+   },
+};
+
  static int pca954x_deselect(struct udevice *mux, struct udevice *bus,
uint channel)
  {
@@ -31,7 +60,13 @@ static int pca954x_select(struct udevice *mux, struct 
udevice *bus,
  uint channel)
  {
struct pca954x_priv *priv = dev_get_priv(mux);
-   uchar byte = 1 << channel;
+   const struct chip_desc *chip = [dev_get_driver_data(mux)];
+   uchar byte;
+
+   if (chip->muxtype == pca954x_ismux)
+   byte = channel | chip->enable;
+   else
+   byte = 1 << channel;

return dm_i2c_write(mux, priv->addr, , 1);
  }
@@ -42,8 +77,9 @@ static const struct i2c_mux_ops pca954x_ops = {
  };

  static const struct udevice_id pca954x_ids[] = {
-   { .compatible = "nxp,pca9548", .data = (ulong)8 },
-   { .compatible = "nxp,pca9544", .data = (ulong)4 },
+   { .compatible = "nxp,pca9544", .data = PCA9544 },
+   { .compatible = "nxp,pca9547", .data = PCA9547 },
+   { .compatible = "nxp,pca9548", .data = PCA9548 },
{ }
  };




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Re: [U-Boot] [PATCH 1/2] power: pmic: tps65218: Add DCDC3 configuration

[Jaehoon Chung]

On 06/02/2017 06:30 PM, Keerthy wrote:
> Some boards like am437x-gp-evm require dcdc3 also to be configured
> as it feeds on to ddr. Hence add the capability as well.
> 
> Signed-off-by: Keerthy 

Applied to u-boot-mmc for pmic. Thanks!

Best Regards,
Jaehoon Chung

> ---
>  drivers/power/pmic/pmic_tps65218.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/power/pmic/pmic_tps65218.c 
> b/drivers/power/pmic/pmic_tps65218.c
> index c5e768a..911f639 100644
> --- a/drivers/power/pmic/pmic_tps65218.c
> +++ b/drivers/power/pmic/pmic_tps65218.c
> @@ -96,7 +96,8 @@ int tps65218_reg_write(uchar prot_level, uchar dest_reg, 
> uchar dest_val,
>  int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
>  {
>   if ((dc_cntrl_reg != TPS65218_DCDC1) &&
> - (dc_cntrl_reg != TPS65218_DCDC2))
> + (dc_cntrl_reg != TPS65218_DCDC2) &&
> + (dc_cntrl_reg != TPS65218_DCDC3))
>   return 1;
>  
>   /* set voltage level */
> 

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Re: [U-Boot] [PATCH 2/2] board: ti: AM43XX: Add ddr voltage rail configuration

[Jaehoon Chung]

On 06/02/2017 06:30 PM, Keerthy wrote:
> Add ddr voltage rail (dcdc3) configuration. Set the dcdc3
> DDR supply to 1.35V.
> 
> Signed-off-by: Keerthy 

Applied to u-boot-mmc for pmic. Thanks!

Best Regards,
Jaehoon Chung

> ---
>  board/ti/am43xx/board.c  | 7 +++
>  include/power/tps65218.h | 1 +
>  2 files changed, 8 insertions(+)
> 
> diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
> index c15d8fa..2c02909 100644
> --- a/board/ti/am43xx/board.c
> +++ b/board/ti/am43xx/board.c
> @@ -441,6 +441,13 @@ void scale_vcores_generic(u32 m)
>   printf("%s failure\n", __func__);
>   return;
>   }
> +
> + /* Set DCDC3 (DDR) voltage */
> + if (tps65218_voltage_update(TPS65218_DCDC3,
> + TPS65218_DCDC3_VOLT_SEL_1350MV)) {
> + printf("%s failure\n", __func__);
> + return;
> + }
>  }
>  
>  void scale_vcores_idk(u32 m)
> diff --git a/include/power/tps65218.h b/include/power/tps65218.h
> index e3538e2..43b9c9a 100644
> --- a/include/power/tps65218.h
> +++ b/include/power/tps65218.h
> @@ -63,6 +63,7 @@ enum {
>  #define TPS65218_DCDC_VOLT_SEL_1200MV0x23
>  #define TPS65218_DCDC_VOLT_SEL_1260MV0x29
>  #define TPS65218_DCDC_VOLT_SEL_1330MV0x30
> +#define TPS65218_DCDC3_VOLT_SEL_1350MV   0x12
>  
>  #define TPS65218_CC_STAT (BIT(0) | BIT(1))
>  #define TPS65218_STATE   (BIT(2) | BIT(3))
> 

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Re: [U-Boot] [linux-sunxi] [RFC PATCH 4/8] sunxi: add SUNXI_R_CPUCFG_BASE for A83T SoC

[Chen-Yu Tsai]

On Wed, Jun 7, 2017 at 11:48 AM, Chen-Yu Tsai  wrote:
> On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng  wrote:
>> A83T SoC has two part of CPUCFG configurations -- one part is at
>> 0x0170, which contains most of the controls, and is like the one in
>> A80; the another part is at 0x01f01c00 (like other post-sun6i SoCs), but
>> contains now only a few registers.
>>
>> Call it SUNXI_R_CPUCFG_BASE, like what the BSP Linux source code did.
>>
>> Signed-off-by: Icenowy Zheng 
>> ---
>>  arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
>> b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
>> index a96680d8e8..5c74714084 100644
>> --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
>> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
>> @@ -179,6 +179,8 @@ defined(CONFIG_MACH_SUN50I)
>>  !defined CONFIG_MACH_SUN8I_A83T && \
>>  !defined CONFIG_MACH_SUN8I_R40
>>  #define SUNXI_CPUCFG_BASE  0x01f01c00
>> +#elif defined CONFIG_MACH_SUN8I_A83T
>> +#define SUNXI_R_CPUCFG_BASE0x01f01c00
>>  #endif
>
> Since this is unrelated to CPUCFG (which we might use later on),
> Just put it in a separate #ifdef section, instead of with the
> other CPUCFG ones.

Also this looks like you don't define CPUCFG, which you later use
in the implementation? Can you elaborate on that?

ChenYu
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Re: [U-Boot] [PATCH] power: regulator: palmas: Add smps12 dual regulator for tps65917

[Jaehoon Chung]

Hi

On 06/02/2017 02:21 PM, Keerthy wrote:
> Add smps12 dual regulator for tps65917
> 
> Signed-off-by: Keerthy 

Applied to u-boot-mmc for pmic. Thanks!

Best Regards,
Jaehoon Chung

> ---
>  drivers/power/regulator/palmas_regulator.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/power/regulator/palmas_regulator.c 
> b/drivers/power/regulator/palmas_regulator.c
> index 399f7a5..841c03a 100644
> --- a/drivers/power/regulator/palmas_regulator.c
> +++ b/drivers/power/regulator/palmas_regulator.c
> @@ -377,7 +377,11 @@ static int palmas_smps_probe(struct udevice *dev)
>   uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
>   uc_pdata->volt_reg = palmas_smps_volt[type][idx];
>   break;
> -
> + case 12:
> + idx = 0;
> + uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
> + uc_pdata->volt_reg = palmas_smps_volt[type][idx];
> + break;
>   default:
>   printf("Wrong ID for regulator\n");
>   }
> 

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[U-Boot] [PATCH v2 2/2] power: regulator: lp87565: add regulator support

[Keerthy]

The driver provides regulator set/get voltage
enable/disable functions for lp87565 family of PMICs.

Signed-off-by: Keerthy 
---

Changes in v2:

  * updated Kconfig description.
  * Used -EINVAL instead of hardcoded -1.
  * removed couple of unwanted braces.
  * Changed volt2hex to volt2val and hex2volt to val2volt.

 drivers/power/regulator/Kconfig |  10 ++
 drivers/power/regulator/Makefile|   1 +
 drivers/power/regulator/lp87565_regulator.c | 199 
 3 files changed, 210 insertions(+)
 create mode 100644 drivers/power/regulator/lp87565_regulator.c

diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index ef057e0..f213487 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -149,3 +149,13 @@ config DM_REGULATOR_LP873X
This enables implementation of driver-model regulator uclass
features for REGULATOR LP873X and the family of LP873X PMICs.
The driver implements get/set api for: value and enable.
+
+config DM_REGULATOR_LP87565
+   bool "Enable driver for LP87565 PMIC regulators"
+depends on PMIC_LP87565
+   ---help---
+   This enables implementation of driver-model regulator uclass
+   features for REGULATOR LP87565 and the family of LP87565 PMICs.
+   LP87565 series of PMICs have 4 single phase BUCKs that can also
+   be configured in multi phase modes. The driver implements
+   get/set api for value and enable.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 3e01021..ce14d08 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
 obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
diff --git a/drivers/power/regulator/lp87565_regulator.c 
b/drivers/power/regulator/lp87565_regulator.c
new file mode 100644
index 000..3811396
--- /dev/null
+++ b/drivers/power/regulator/lp87565_regulator.c
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2017
+ * Texas Instruments Incorporated, 
+ *
+ * Keerthy 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char lp87565_buck_ctrl1[LP87565_BUCK_NUM] = {0x2, 0x4, 0x6, 0x8, 
0x2, 0x6};
+static const char lp87565_buck_vout[LP87565_BUCK_NUM] = {0xA, 0xC, 0xE, 0x10, 
0xA, 0xE };
+
+static int lp87565_buck_enable(struct udevice *dev, int op, bool *enable)
+{
+   int ret;
+   unsigned int adr;
+   struct dm_regulator_uclass_platdata *uc_pdata;
+
+   uc_pdata = dev_get_uclass_platdata(dev);
+   adr = uc_pdata->ctrl_reg;
+
+   ret = pmic_reg_read(dev->parent, adr);
+   if (ret < 0)
+   return ret;
+
+   if (op == PMIC_OP_GET) {
+   ret &= LP87565_BUCK_MODE_MASK;
+
+   if (ret)
+   *enable = true;
+   else
+   *enable = false;
+
+   return 0;
+   } else if (op == PMIC_OP_SET) {
+   if (*enable)
+   ret |= LP87565_BUCK_MODE_MASK;
+   else
+   ret &= ~LP87565_BUCK_MODE_MASK;
+   ret = pmic_reg_write(dev->parent, adr, ret);
+   if (ret)
+   return ret;
+   }
+
+   return 0;
+}
+
+static int lp87565_buck_volt2val(int uV)
+{
+   if (uV > LP87565_BUCK_VOLT_MAX)
+   return -EINVAL;
+   else if (uV > 140)
+   return (uV - 142) / 2 + 0x9E;
+   else if (uV > 73)
+   return (uV - 735000) / 5000 + 0x18;
+   else if (uV >= 50)
+   return (uV - 50) / 1;
+   else
+   return -EINVAL;
+}
+
+static int lp87565_buck_val2volt(int val)
+{
+   if (val > LP87565_BUCK_VOLT_MAX_HEX)
+   return -EINVAL;
+   else if (val > 0x9D)
+   return 140 + (val - 0x9D) * 2;
+   else if (val > 0x17)
+   return 73 + (val - 0x17) * 5000;
+   else if (val >= 0x0)
+   return 50 + val * 1;
+   else
+   return -EINVAL;
+}
+
+static int lp87565_buck_val(struct udevice *dev, int op, int *uV)
+{
+   unsigned int hex, adr;
+   int ret;
+   struct dm_regulator_uclass_platdata *uc_pdata;
+
+   uc_pdata = dev_get_uclass_platdata(dev);
+
+   if (op == PMIC_OP_GET)
+   *uV = 0;
+
+   adr = uc_pdata->volt_reg;
+
+   ret = pmic_reg_read(dev->parent, adr);
+   if (ret < 0)
+   return ret;
+
+   if (op == PMIC_OP_GET) {
+   ret &= LP87565_BUCK_VOLT_MASK;
+ 

[U-Boot] [PATCH v2 1/2] power: pmic: lp87565: Add the basic pmic support

[Keerthy]

Add support to bind the regulators/child nodes with the pmic.

Signed-off-by: Keerthy 
---

Changes in v2:

  * Used dev_read_subnode function to fetch the regulators node.
 
 drivers/power/pmic/Kconfig   |  7 
 drivers/power/pmic/Makefile  |  1 +
 drivers/power/pmic/lp87565.c | 85 
 include/power/lp87565.h  | 12 +++
 4 files changed, 105 insertions(+)
 create mode 100644 drivers/power/pmic/lp87565.c
 create mode 100644 include/power/lp87565.h

diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 3f50c12..e3f9e4d 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -188,6 +188,13 @@ config PMIC_LP873X
The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
This driver binds the pmic children.
 
+config PMIC_LP87565
+   bool "Enable driver for Texas Instruments LP87565 PMIC"
+   depends on DM_PMIC
+   ---help---
+   The LP87565 is a PMIC containing a bunch of SMPS.
+   This driver binds the pmic children.
+
 config POWER_MC34VR500
bool "Enable driver for Freescale MC34VR500 PMIC"
---help---
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index f409e3a..f488799 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
 obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
 obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
 obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
+obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
 
 obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
 obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
diff --git a/drivers/power/pmic/lp87565.c b/drivers/power/pmic/lp87565.c
new file mode 100644
index 000..9803bf9
--- /dev/null
+++ b/drivers/power/pmic/lp87565.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2017 Texas Instruments Incorporated, 
+ * Keerthy 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+   { .prefix = "buck", .driver = LP87565_BUCK_DRIVER },
+   { },
+};
+
+static int lp87565_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+   if (dm_i2c_write(dev, reg, buff, len)) {
+   error("write error to device: %p register: %#x!", dev, reg);
+   return -EIO;
+   }
+
+   return 0;
+}
+
+static int lp87565_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+   if (dm_i2c_read(dev, reg, buff, len)) {
+   error("read error from device: %p register: %#x!", dev, reg);
+   return -EIO;
+   }
+
+   return 0;
+}
+
+static int lp87565_bind(struct udevice *dev)
+{
+   ofnode regulators_node;
+   int children;
+
+   regulators_node = dev_read_subnode(dev, "regulators");
+   if (!ofnode_valid(regulators_node)) {
+   debug("%s: %s regulators subnode not found!", __func__,
+ dev->name);
+   return -ENXIO;
+   }
+
+   debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+   children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+   if (!children)
+   printf("%s: %s - no child found\n", __func__, dev->name);
+
+   /* Always return success for this device */
+   return 0;
+}
+
+static struct dm_pmic_ops lp87565_ops = {
+   .read = lp87565_read,
+   .write = lp87565_write,
+};
+
+static const struct udevice_id lp87565_ids[] = {
+   { .compatible = "ti,lp87565", .data = LP87565 },
+   { .compatible = "ti,lp87565-q1", .data = LP87565_Q1 },
+   { }
+};
+
+U_BOOT_DRIVER(pmic_lp87565) = {
+   .name = "lp87565_pmic",
+   .id = UCLASS_PMIC,
+   .of_match = lp87565_ids,
+   .bind = lp87565_bind,
+   .ops = _ops,
+};
diff --git a/include/power/lp87565.h b/include/power/lp87565.h
new file mode 100644
index 000..5160f5d
--- /dev/null
+++ b/include/power/lp87565.h
@@ -0,0 +1,12 @@
+#define LP875650x0
+#define LP87565_Q1 0x1
+
+#define LP87565_BUCK_NUM   6
+
+/* Drivers name */
+#define LP87565_BUCK_DRIVER"lp87565_buck"
+
+#define LP87565_BUCK_VOLT_MASK 0xFF
+#define LP87565_BUCK_VOLT_MAX_HEX  0xFF
+#define LP87565_BUCK_VOLT_MAX  336
+#define LP87565_BUCK_MODE_MASK 0x80
-- 
1.9.1

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[U-Boot] [PATCH v2 0/2] power: pmic: Add support for LP87565 family of PMICs

[Keerthy]

The series adds support for LP87565 family of PMICs.
Implements functions to configure regulators. Enable/Disable
Get/Set voltages of regulators. 

Keerthy (2):
  power: pmic: lp87565: Add the basic pmic support
  power: regulator: lp87565: add regulator support

 drivers/power/pmic/Kconfig  |   7 +
 drivers/power/pmic/Makefile |   1 +
 drivers/power/pmic/lp87565.c|  85 
 drivers/power/regulator/Kconfig |  10 ++
 drivers/power/regulator/Makefile|   1 +
 drivers/power/regulator/lp87565_regulator.c | 199 
 include/power/lp87565.h |  12 ++
 7 files changed, 315 insertions(+)
 create mode 100644 drivers/power/pmic/lp87565.c
 create mode 100644 drivers/power/regulator/lp87565_regulator.c
 create mode 100644 include/power/lp87565.h

-- 
1.9.1

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Re: [U-Boot] u-boot-flasher fails with current u-boot

[Peter.Chubb]

> "Simon" == Simon Glass  writes:

:
Simon> Oh dear. I cannot find my board but will see if I can repeat
Simon> this on a beaver.
Thanks.

If there's any additional logging you'd like me to collect on the
Jetson, let me know.

Peter C
--
Dr Peter Chubb Tel: +61 2 9490 5852  http://ts.data61.csiro.au/
Trustworthy Systems Group   Data61 (formerly NICTA)
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Re: [U-Boot] [PATCH 1/3] dm: blk: Add a way to obtain a block device from its parent

[Jaehoon Chung]

Hi Simon,

On 05/28/2017 02:37 AM, Simon Glass wrote:
> Many devices support a child block device (e.g. MMC, USB). Add a
> convenient way to get this device given the parent device.
> 
> Signed-off-by: Simon Glass 
> ---
> 
>  drivers/block/blk-uclass.c | 26 ++
>  include/blk.h  |  7 +++
>  test/dm/blk.c  | 18 ++
>  3 files changed, 51 insertions(+)
> 
> diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
> index 6145675271..23f131b7ad 100644
> --- a/drivers/block/blk-uclass.c
> +++ b/drivers/block/blk-uclass.c
> @@ -453,6 +453,32 @@ int blk_prepare_device(struct udevice *dev)
>   return 0;
>  }
>  
> +int blk_get_from_parent(struct udevice *parent, struct udevice **devp)
> +{
> + struct udevice *dev;
> + enum uclass_id id;
> + int ret;
> +
> + device_find_first_child(parent, );
> + if (!dev) {
> + debug("%s: No block device found for parent '%s'\n", __func__,
> +   parent->name);
> + return -ENODEV;
> + }
> + id = device_get_uclass_id(dev);
> + if (id != UCLASS_BLK) {
> + debug("%s: Incorrect uclass %s for block device '%s'\n",
> +   __func__, uclass_get_name(id), dev->name);
> + return -ENOTBLK;
> + }
> + ret = device_probe(dev);
> + if (ret)
> + return ret;
> + *devp = dev;
> +
> + return 0;
> +}
> +
>  int blk_find_max_devnum(enum if_type if_type)
>  {
>   struct udevice *dev;
> diff --git a/include/blk.h b/include/blk.h
> index a128ee4841..4d60987f61 100644
> --- a/include/blk.h
> +++ b/include/blk.h
> @@ -616,4 +616,11 @@ ulong blk_write_devnum(enum if_type if_type, int devnum, 
> lbaint_t start,
>   */
>  int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart);
>  
> +/**
> + * blk_get_from_parent() - obtain a block device by looking up its parent
> + *
> + * All devices with
> + */
> +int blk_get_from_parent(struct udevice *parent, struct udevice **devp);

Don't need to consider whether CONFIG_BLK is defined or not?
blk_get_from_parent() is declared in blk-uclass.c

Best Regards,
Jaehoon Chung

> +
>  #endif
> diff --git a/test/dm/blk.c b/test/dm/blk.c
> index 5c5eb829a0..923e8d95f0 100644
> --- a/test/dm/blk.c
> +++ b/test/dm/blk.c
> @@ -150,3 +150,21 @@ static int dm_test_blk_devnum(struct unit_test_state 
> *uts)
>   return 0;
>  }
>  DM_TEST(dm_test_blk_devnum, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
> +
> +/* Test that we can get a block from its parent */
> +static int dm_test_blk_get_from_parent(struct unit_test_state *uts)
> +{
> + struct udevice *dev, *blk;
> +
> + ut_assertok(uclass_get_device(UCLASS_MMC, 0, ));
> + ut_assertok(blk_get_from_parent(dev, ));
> +
> + ut_assertok(uclass_get_device(UCLASS_I2C, 0, ));
> + ut_asserteq(-ENOTBLK, blk_get_from_parent(dev, ));
> +
> + ut_assertok(uclass_get_device(UCLASS_GPIO, 0, ));
> + ut_asserteq(-ENODEV, blk_get_from_parent(dev, ));
> +
> + return 0;
> +}
> +DM_TEST(dm_test_blk_get_from_parent, DM_TESTF_SCAN_PDATA | 
> DM_TESTF_SCAN_FDT);
> 

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Re: [U-Boot] [linux-sunxi] [RFC PATCH 4/8] sunxi: add SUNXI_R_CPUCFG_BASE for A83T SoC

[Chen-Yu Tsai]

On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng  wrote:
> A83T SoC has two part of CPUCFG configurations -- one part is at
> 0x0170, which contains most of the controls, and is like the one in
> A80; the another part is at 0x01f01c00 (like other post-sun6i SoCs), but
> contains now only a few registers.
>
> Call it SUNXI_R_CPUCFG_BASE, like what the BSP Linux source code did.
>
> Signed-off-by: Icenowy Zheng 
> ---
>  arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
> b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> index a96680d8e8..5c74714084 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> @@ -179,6 +179,8 @@ defined(CONFIG_MACH_SUN50I)
>  !defined CONFIG_MACH_SUN8I_A83T && \
>  !defined CONFIG_MACH_SUN8I_R40
>  #define SUNXI_CPUCFG_BASE  0x01f01c00
> +#elif defined CONFIG_MACH_SUN8I_A83T
> +#define SUNXI_R_CPUCFG_BASE0x01f01c00
>  #endif

Since this is unrelated to CPUCFG (which we might use later on),
Just put it in a separate #ifdef section, instead of with the
other CPUCFG ones.

ChenYu

>
>  #define SUNXI_R_TWI_BASE   0x01f02400
> --
> 2.12.2
>
> --
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Re: [U-Boot] [linux-sunxi] [RFC PATCH 8/8] sunxi: enable PSCI for A83T SoC

[Chen-Yu Tsai]

On Wed, Jun 7, 2017 at 11:40 AM, Icenowy Zheng  wrote:
>
>
> 于 2017年6月7日 GMT+08:00 上午11:36:27, Chen-Yu Tsai  写到:
>>On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng  wrote:
>>> As we have now a basical implementation of PSCI for A83T, enable
>>> non-secure boot support and PSCI on A83T now.
>>>
>>> Signed-off-by: Icenowy Zheng 
>>> ---
>>>  arch/arm/mach-sunxi/Kconfig | 4 
>>>  1 file changed, 4 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-sunxi/Kconfig
>>b/arch/arm/mach-sunxi/Kconfig
>>> index 7ced838d6a..31d29de428 100644
>>> --- a/arch/arm/mach-sunxi/Kconfig
>>> +++ b/arch/arm/mach-sunxi/Kconfig
>>> @@ -98,8 +98,12 @@ config MACH_SUN8I_A33
>>>  config MACH_SUN8I_A83T
>>> bool "sun8i (Allwinner A83T)"
>>> select CPU_V7
>>> +   select CPU_V7_HAS_NONSEC
>>> +   select CPU_V7_HAS_VIRT
>>> +   select ARCH_SUPPORT_PSCI
>>> select SUNXI_GEN_SUN6I
>>> select SUPPORT_SPL
>>> +   select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
>>
>>The kernel does not work yet. Please have it boot to secure by default
>>regardless of the kernel. We can have it boot non-secure once the
>>kernel
>>has been working for a reasonable amount of time.
>>
>>I don't want clueless users coming and asking why it suddenly stopped
>>working. This should be an experimental feature.
>
> Maybe you should send out the fix, and tag them to also apply to
> stable tree.
>
> GIC is really broken, UP systems only work by chance. We
> shouldn't depend on this behavior.

As I previously explained, it is not the GIC that is broken. I believe
the GIC is working exactly as it is supposed to with regards to its
input signals.

Allwinner's security extensions implementation simply does not properly
forward the AXI secure bit when the e-fuse's secure bit isn't burned.

ChenYu
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Re: [U-Boot] [linux-sunxi] [RFC PATCH 5/8] sunxi: Add CPUCFG register definitions for A80/A83T SoCs

[Icenowy Zheng]

于 2017年6月7日 GMT+08:00 上午11:43:40, Chen-Yu Tsai  写到:
>On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng  wrote:
>> From: Chen-Yu Tsai 
>>
>> The A80/A83T SoCs has a different CPUCFG register layout, likely due
>to
>> having 2 clusters. The A83T SoC has also a small extra CPUCFG part
>> located at single cluster SoCs' CPUCFG address (in CPUs domain).
>>
>> Add a cpucfg header file for it, rename the original cpucfg.h to
>> cpucfg_sun4i.h and add a new cpucfg.h to automatically switch between
>> the two cpucfg header file.
>>
>> Signed-off-by: Chen-Yu Tsai 
>> Signed-off-by: Icenowy Zheng 
>> ---
>>  arch/arm/include/asm/arch-sunxi/cpucfg.h   | 64
>+++-
>>  arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h | 68
>++
>>  arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h | 60
>+++
>>  3 files changed, 134 insertions(+), 58 deletions(-)
>>  create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>>  create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h
>b/arch/arm/include/asm/arch-sunxi/cpucfg.h
>> index 297cdd28c0..cf60ff81b6 100644
>> --- a/arch/arm/include/asm/arch-sunxi/cpucfg.h
>> +++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
>> @@ -1,7 +1,5 @@
>>  /*
>> - * Sunxi A31 CPUCFG register definition.
>> - *
>> - * (C) Copyright 2014 Hans de Goede > + * (C) Copyright 2017 Icenowy Zheng 
>>   *
>>   * SPDX-License-Identifier:GPL-2.0+
>>   */
>> @@ -9,60 +7,10 @@
>>  #ifndef _SUNXI_CPUCFG_H
>>  #define _SUNXI_CPUCFG_H
>>
>> -#include 
>> -#include 
>> -
>> -#ifndef __ASSEMBLY__
>> -
>> -struct __packed sunxi_cpucfg_cpu {
>> -   u32 rst;/* base + 0x0 */
>> -   u32 ctrl;   /* base + 0x4 */
>> -   u32 status; /* base + 0x8 */
>> -   u8 res[0x34];   /* base + 0xc */
>> -};
>> -
>> -struct __packed sunxi_cpucfg_reg {
>> -   u8 res0[0x40];  /* 0x000 */
>> -   struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */
>> -   u8 res1[0x44];  /* 0x140 */
>> -   u32 gen_ctrl;   /* 0x184 */
>> -   u32 l2_status;  /* 0x188 */
>> -   u8 res2[0x4];   /* 0x18c */
>> -   u32 event_in;   /* 0x190 */
>> -   u8 res3[0xc];   /* 0x194 */
>> -   u32 super_standy_flag;  /* 0x1a0 */
>> -   u32 priv0;  /* 0x1a4 */
>> -   u32 priv1;  /* 0x1a8 */
>> -   u8 res4[0x4];   /* 0x1ac */
>> -   u32 cpu1_pwr_clamp; /* 0x1b0 sun7i only */
>> -   u32 cpu1_pwroff;/* 0x1b4 sun7i only */
>> -   u8 res5[0x2c];  /* 0x1b8 */
>> -   u32 dbg_ctrl1;  /* 0x1e4 */
>> -   u8 res6[0x18];  /* 0x1e8 */
>> -   u32 idle_cnt0_low;  /* 0x200 */
>> -   u32 idle_cnt0_high; /* 0x204 */
>> -   u32 idle_cnt0_ctrl; /* 0x208 */
>> -   u8 res8[0x4];   /* 0x20c */
>> -   u32 idle_cnt1_low;  /* 0x210 */
>> -   u32 idle_cnt1_high; /* 0x214 */
>> -   u32 idle_cnt1_ctrl; /* 0x218 */
>> -   u8 res9[0x4];   /* 0x21c */
>> -   u32 idle_cnt2_low;  /* 0x220 */
>> -   u32 idle_cnt2_high; /* 0x224 */
>> -   u32 idle_cnt2_ctrl; /* 0x228 */
>> -   u8 res10[0x4];  /* 0x22c */
>> -   u32 idle_cnt3_low;  /* 0x230 */
>> -   u32 idle_cnt3_high; /* 0x234 */
>> -   u32 idle_cnt3_ctrl; /* 0x238 */
>> -   u8 res11[0x4];  /* 0x23c */
>> -   u32 idle_cnt4_low;  /* 0x240 */
>> -   u32 idle_cnt4_high; /* 0x244 */
>> -   u32 idle_cnt4_ctrl; /* 0x248 */
>> -   u8 res12[0x34]; /* 0x24c */
>> -   u32 cnt64_ctrl; /* 0x280 */
>> -   u32 cnt64_low;  /* 0x284 */
>> -   u32 cnt64_high; /* 0x288 */
>> -};
>> +#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN9I)
>> +#include 
>> +#else
>> +#include 
>> +#endif
>>
>> -#endif /* __ASSEMBLY__ */
>>  #endif /* _SUNXI_CPUCFG_H */
>> diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>b/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>> new file mode 100644
>> index 00..af1a1d56c9
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>> @@ -0,0 +1,68 @@
>> +/*
>> + * Sunxi A31 CPUCFG register definition.
>> + *
>> + * (C) Copyright 2014 Hans de Goede > + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#ifndef _SUNXI_CPUCFG_SUN4I_H
>> +#define _SUNXI_CPUCFG_SUN4I_H
>> +
>> +#include 
>> +#include 
>> +
>> +#ifndef __ASSEMBLY__
>> +
>> +struct __packed sunxi_cpucfg_cpu {
>> +   u32 rst;/* base + 0x0 */
>> +   u32 ctrl;   /* base + 0x4 */
>> +   u32 status; /* base + 0x8 */
>> +   u8 res[0x34];   /* base + 0xc 

Re: [U-Boot] [linux-sunxi] [RFC PATCH 5/8] sunxi: Add CPUCFG register definitions for A80/A83T SoCs

[Chen-Yu Tsai]

On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng  wrote:
> From: Chen-Yu Tsai 
>
> The A80/A83T SoCs has a different CPUCFG register layout, likely due to
> having 2 clusters. The A83T SoC has also a small extra CPUCFG part
> located at single cluster SoCs' CPUCFG address (in CPUs domain).
>
> Add a cpucfg header file for it, rename the original cpucfg.h to
> cpucfg_sun4i.h and add a new cpucfg.h to automatically switch between
> the two cpucfg header file.
>
> Signed-off-by: Chen-Yu Tsai 
> Signed-off-by: Icenowy Zheng 
> ---
>  arch/arm/include/asm/arch-sunxi/cpucfg.h   | 64 +++-
>  arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h | 68 
> ++
>  arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h | 60 +++
>  3 files changed, 134 insertions(+), 58 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>  create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
>
> diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h 
> b/arch/arm/include/asm/arch-sunxi/cpucfg.h
> index 297cdd28c0..cf60ff81b6 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpucfg.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
> @@ -1,7 +1,5 @@
>  /*
> - * Sunxi A31 CPUCFG register definition.
> - *
> - * (C) Copyright 2014 Hans de Goede  + * (C) Copyright 2017 Icenowy Zheng 
>   *
>   * SPDX-License-Identifier:GPL-2.0+
>   */
> @@ -9,60 +7,10 @@
>  #ifndef _SUNXI_CPUCFG_H
>  #define _SUNXI_CPUCFG_H
>
> -#include 
> -#include 
> -
> -#ifndef __ASSEMBLY__
> -
> -struct __packed sunxi_cpucfg_cpu {
> -   u32 rst;/* base + 0x0 */
> -   u32 ctrl;   /* base + 0x4 */
> -   u32 status; /* base + 0x8 */
> -   u8 res[0x34];   /* base + 0xc */
> -};
> -
> -struct __packed sunxi_cpucfg_reg {
> -   u8 res0[0x40];  /* 0x000 */
> -   struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */
> -   u8 res1[0x44];  /* 0x140 */
> -   u32 gen_ctrl;   /* 0x184 */
> -   u32 l2_status;  /* 0x188 */
> -   u8 res2[0x4];   /* 0x18c */
> -   u32 event_in;   /* 0x190 */
> -   u8 res3[0xc];   /* 0x194 */
> -   u32 super_standy_flag;  /* 0x1a0 */
> -   u32 priv0;  /* 0x1a4 */
> -   u32 priv1;  /* 0x1a8 */
> -   u8 res4[0x4];   /* 0x1ac */
> -   u32 cpu1_pwr_clamp; /* 0x1b0 sun7i only */
> -   u32 cpu1_pwroff;/* 0x1b4 sun7i only */
> -   u8 res5[0x2c];  /* 0x1b8 */
> -   u32 dbg_ctrl1;  /* 0x1e4 */
> -   u8 res6[0x18];  /* 0x1e8 */
> -   u32 idle_cnt0_low;  /* 0x200 */
> -   u32 idle_cnt0_high; /* 0x204 */
> -   u32 idle_cnt0_ctrl; /* 0x208 */
> -   u8 res8[0x4];   /* 0x20c */
> -   u32 idle_cnt1_low;  /* 0x210 */
> -   u32 idle_cnt1_high; /* 0x214 */
> -   u32 idle_cnt1_ctrl; /* 0x218 */
> -   u8 res9[0x4];   /* 0x21c */
> -   u32 idle_cnt2_low;  /* 0x220 */
> -   u32 idle_cnt2_high; /* 0x224 */
> -   u32 idle_cnt2_ctrl; /* 0x228 */
> -   u8 res10[0x4];  /* 0x22c */
> -   u32 idle_cnt3_low;  /* 0x230 */
> -   u32 idle_cnt3_high; /* 0x234 */
> -   u32 idle_cnt3_ctrl; /* 0x238 */
> -   u8 res11[0x4];  /* 0x23c */
> -   u32 idle_cnt4_low;  /* 0x240 */
> -   u32 idle_cnt4_high; /* 0x244 */
> -   u32 idle_cnt4_ctrl; /* 0x248 */
> -   u8 res12[0x34]; /* 0x24c */
> -   u32 cnt64_ctrl; /* 0x280 */
> -   u32 cnt64_low;  /* 0x284 */
> -   u32 cnt64_high; /* 0x288 */
> -};
> +#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN9I)
> +#include 
> +#else
> +#include 
> +#endif
>
> -#endif /* __ASSEMBLY__ */
>  #endif /* _SUNXI_CPUCFG_H */
> diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h 
> b/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
> new file mode 100644
> index 00..af1a1d56c9
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
> @@ -0,0 +1,68 @@
> +/*
> + * Sunxi A31 CPUCFG register definition.
> + *
> + * (C) Copyright 2014 Hans de Goede  + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#ifndef _SUNXI_CPUCFG_SUN4I_H
> +#define _SUNXI_CPUCFG_SUN4I_H
> +
> +#include 
> +#include 
> +
> +#ifndef __ASSEMBLY__
> +
> +struct __packed sunxi_cpucfg_cpu {
> +   u32 rst;/* base + 0x0 */
> +   u32 ctrl;   /* base + 0x4 */
> +   u32 status; /* base + 0x8 */
> +   u8 res[0x34];   /* base + 0xc */
> +};
> +
> +struct __packed sunxi_cpucfg_reg {
> +   u8 res0[0x40];  /* 0x000 */
> +   struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */
> +   u8 res1[0x44];  

Re: [U-Boot] [linux-sunxi] [RFC PATCH 6/8] sunxi: add multi-cluster CPU PRCM register definition

[Chen-Yu Tsai]

On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng  wrote:
> A83T come with two clusters of CPU, for each cluster 1 the new registers
> are in the reserved spaces after the original cluster 0.
>
> Make the registers to have an array with length 2 (2 clusters), and
> change the current code to reference only cluster 0 registers.
>
> Signed-off-by: Icenowy Zheng 
> ---
>  arch/arm/cpu/armv7/sunxi/psci.c| 2 +-
>  arch/arm/include/asm/arch-sunxi/prcm.h | 8 
>  2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
> index b3a34de1aa..8caef6a85f 100644
> --- a/arch/arm/cpu/armv7/sunxi/psci.c
> +++ b/arch/arm/cpu/armv7/sunxi/psci.c
> @@ -144,7 +144,7 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)
> struct sunxi_prcm_reg *prcm =
> (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
>
> -   sunxi_power_switch(>cpu_pwr_clamp[cpu], >cpu_pwroff,
> +   sunxi_power_switch(>cpu_pwr_clamp[0][cpu], >cpu_pwroff[0],
>on, cpu);
>  }
>  #endif /* CONFIG_MACH_SUN7I */
> diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h 
> b/arch/arm/include/asm/arch-sunxi/prcm.h
> index ae3880b13b..c2a6e39ffc 100644
> --- a/arch/arm/include/asm/arch-sunxi/prcm.h
> +++ b/arch/arm/include/asm/arch-sunxi/prcm.h
> @@ -220,16 +220,16 @@ struct __packed sunxi_prcm_reg {
> u8 res5[0x3c];  /* 0x0b4 */
> u32 clk_outd;   /* 0x0f0 */
> u8 res6[0xc];   /* 0x0f4 */
> -   u32 cpu_pwroff; /* 0x100 */
> -   u8 res7[0xc];   /* 0x104 */
> +   u32 cpu_pwroff[2];  /* 0x100 */
> +   u8 res7[0x8];   /* 0x108 */
> u32 vdd_sys_pwroff; /* 0x110 */
> u8 res8[0x4];   /* 0x114 */
> u32 gpu_pwroff; /* 0x118 */
> u8 res9[0x4];   /* 0x11c */
> u32 vdd_pwr_reset;  /* 0x120 */
> u8 res10[0x1c]; /* 0x124 */
> -   u32 cpu_pwr_clamp[4];   /* 0x140 but first one is actually unused */
> -   u8 res11[0x30]; /* 0x150 */
> +   u32 cpu_pwr_clamp[2][4];/* 0x140 but first one is actually unused */

The comment needs to be fixed. It only applies to the single cluster SoCs.

Otherwise,

Reviewed-by: Chen-Yu Tsai 

> +   u8 res11[0x20]; /* 0x160 */
> u32 dram_pwr;   /* 0x180 */
> u8 res12[0xc];  /* 0x184 */
> u32 dram_tst;   /* 0x190 */
> --
> 2.12.2
>
> --
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Re: [U-Boot] [linux-sunxi] [RFC PATCH 8/8] sunxi: enable PSCI for A83T SoC

[Icenowy Zheng]

于 2017年6月7日 GMT+08:00 上午11:36:27, Chen-Yu Tsai  写到:
>On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng  wrote:
>> As we have now a basical implementation of PSCI for A83T, enable
>> non-secure boot support and PSCI on A83T now.
>>
>> Signed-off-by: Icenowy Zheng 
>> ---
>>  arch/arm/mach-sunxi/Kconfig | 4 
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm/mach-sunxi/Kconfig
>b/arch/arm/mach-sunxi/Kconfig
>> index 7ced838d6a..31d29de428 100644
>> --- a/arch/arm/mach-sunxi/Kconfig
>> +++ b/arch/arm/mach-sunxi/Kconfig
>> @@ -98,8 +98,12 @@ config MACH_SUN8I_A33
>>  config MACH_SUN8I_A83T
>> bool "sun8i (Allwinner A83T)"
>> select CPU_V7
>> +   select CPU_V7_HAS_NONSEC
>> +   select CPU_V7_HAS_VIRT
>> +   select ARCH_SUPPORT_PSCI
>> select SUNXI_GEN_SUN6I
>> select SUPPORT_SPL
>> +   select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
>
>The kernel does not work yet. Please have it boot to secure by default
>regardless of the kernel. We can have it boot non-secure once the
>kernel
>has been working for a reasonable amount of time.
>
>I don't want clueless users coming and asking why it suddenly stopped
>working. This should be an experimental feature.

Maybe you should send out the fix, and tag them to also apply to
stable tree.

GIC is really broken, UP systems only work by chance. We
shouldn't depend on this behavior.

>
>ChenYu
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Re: [U-Boot] [linux-sunxi] [RFC PATCH 8/8] sunxi: enable PSCI for A83T SoC

[Chen-Yu Tsai]

On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng  wrote:
> As we have now a basical implementation of PSCI for A83T, enable
> non-secure boot support and PSCI on A83T now.
>
> Signed-off-by: Icenowy Zheng 
> ---
>  arch/arm/mach-sunxi/Kconfig | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 7ced838d6a..31d29de428 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -98,8 +98,12 @@ config MACH_SUN8I_A33
>  config MACH_SUN8I_A83T
> bool "sun8i (Allwinner A83T)"
> select CPU_V7
> +   select CPU_V7_HAS_NONSEC
> +   select CPU_V7_HAS_VIRT
> +   select ARCH_SUPPORT_PSCI
> select SUNXI_GEN_SUN6I
> select SUPPORT_SPL
> +   select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT

The kernel does not work yet. Please have it boot to secure by default
regardless of the kernel. We can have it boot non-secure once the kernel
has been working for a reasonable amount of time.

I don't want clueless users coming and asking why it suddenly stopped
working. This should be an experimental feature.

ChenYu
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Re: [U-Boot] [PATCH v3 07/10] usb: dwc2: force to host mode if HNP/SRP not support

[rock-chips(daniel.meng)]

On 2017/6/6 23:02, Marek Vasut wrote:

On 06/06/2017 12:33 PM, Meng Dongyang wrote:

In current code, after running the command of "usb start", the controller
will keep in otg mode and can't switch to host mode if not support
SNP/SRP capability. So add the property of "hnp-srp-disable" in the DTS
to config the contrller work in force mode of host.

Signed-off-by: Meng Dongyang 
---

Changes in v3:
- revert change of macro definition in dwc2 driver
- support host mode without HNP/SRP capability through DTS

Changes in v2:
- Splited from patch [07/08] of v1

  drivers/usb/host/dwc2.c | 13 -
  1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 0e5df15..73a0290 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -43,6 +43,7 @@ struct dwc2_priv {
struct dwc2_core_regs *regs;
int root_hub_devnum;
bool ext_vbus;
+   bool hnp_srp_disable;
bool oc_disable;
  };
  
@@ -394,6 +395,9 @@ static void dwc_otg_core_init(struct dwc2_priv *priv)

usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
}
  #endif
+   if (priv->hnp_srp_disable)
+   usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
+
writel(usbcfg, >gusbcfg);
  
  	/* Program the GAHBCFG Register. */

@@ -423,7 +427,9 @@ static void dwc_otg_core_init(struct dwc2_priv *priv)
writel(ahbcfg, >gahbcfg);
  
  	/* Program the GUSBCFG register for HNP/SRP. */

-   setbits_le32(>gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
+   if (!priv->hnp_srp_disable)
+   setbits_le32(>gusbcfg,
+DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);

I guess you can prepare the mask and then do setbits...() once ?
Looks good otherwise.
I have attempted to move this config to the last writel of usbcfg and 
checked on our platform.
Do you think it is better?  Prepare a mask maybe looks a little strange 
since it only use with
writel() and the other setbits..() in this function use macro definition 
directly.

  #ifdef CONFIG_DWC2_IC_USB_CAP
setbits_le32(>gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
@@ -1244,6 +1250,11 @@ static int dwc2_usb_ofdata_to_platdata(struct udevice 
*dev)
if (prop)
priv->oc_disable = true;
  
+	prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),

+  "hnp-srp-disable", NULL);
+   if (prop)
+   priv->hnp_srp_disable = true;
+
return 0;
  }
  






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Re: [U-Boot] [PATCH 1/5] mmc: sh_sdhi: Fix Kconfig entry

[Jaehoon Chung]

Hi Marek,

On 06/05/2017 10:32 PM, Marek Vasut wrote:
> On 06/05/2017 03:11 PM, Jaehoon Chung wrote:
>> Hi,
> 
> Hi,
> 
>> On 2017년 06월 05일 20:57, Marek Vasut wrote:
>>> On 05/31/2017 07:07 AM, Nobuhiro Iwamatsu wrote:
 Hi!

 2017-05-31 11:06 GMT+09:00 Jaehoon Chung :
> On 05/31/2017 07:59 AM, Nobuhiro Iwamatsu wrote:
>> Hi, Jaehoon.
>>
>> Could you pickup this patch series to your mmc repository, and PR to 
>> u-boot?
>
> Sure, I will pick this patch series. After that, i will do PR..
> But i have sent the PR about a few days ago..but it doesn't accept yet..
> After accepting it, i will resend PR.

 I see. Thanks for your great work!
>>>
>>> Hi, any news ? RC1 is out and I don't see this in RC1 .
>>
>> When i had tested the buildman, there are build error with [PATCH 3/5]
>>
>>
>>   aarch64:  +   r8a7795_salvator-x
>> +board/renesas/salvator-x/salvator-x.c: In function 'board_mmc_init':
>> +board/renesas/salvator-x/salvator-x.c:196:7: error: 
>> 'SH_SDHI_QUIRK_64BIT_BUF' undeclared (first use in this function)
>> +   SH_SDHI_QUIRK_64BIT_BUF);
>> +   ^~~
>> +board/renesas/salvator-x/salvator-x.c:196:7: note: each undeclared 
>> identifier is reported only once for each function it appears in
>> +make[2]: *** [board/renesas/salvator-x/salvator-x.o] Error 1
>> +make[1]: *** [board/renesas/salvator-x] Error 2
>> +make[1]: *** wait: No child processes.  Stop.
>> +make: *** [sub-make] Error 2
>>
>> So i had sent the email about fixing it.
> 
> I didn't receive that email.
> 
>> i didn't check with latest u-boot.
>> but at that time, i could not apply it with building error.
> 
> Builds fine for me after applying all the patches on u-boot/master ,
> commit dd31be21bf .
> 
> I guess what you see is that if you apply only 1/5 , the build will
> choke on issue which is already present. The fix is simple really,
> apply the patches in the order 2,3,4,5,1 and you won't trigger the
> issue and your build will pass. In fact, patch 3 adds the missing macro
> and thus fixes the issue which patch 1 triggers. I don't think this
> requires me to resubmit the patches with no changes in them. Then you
> can send PR.

Applied to u-boot-mmc after ordering 2,3,4,5,1.
Will send PR. At that time, i will add you.

Best Regards,
Jaehoon Chung

> 

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Re: [U-Boot] [linux-sunxi] [RFC PATCH 3/8] sun8i: Add a macro to read the silicon revision

[Chen-Yu Tsai]

On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng  wrote:
> From: "tpear...@raptorengineering.com" 

Same thing with the author name.

>
> According to the user manuals released by Allwinner, the low 8-bit of
> the 0x24 register in "System Control" (marked SRAMC in U-Boot source as
> it controls some SRAMs' functionality since A10) is the silicon revision
> of the chip.
>
> This data is now important for A83T: according to the BSP source A83T
> have two revisions: Revision A (with revision ID 0) and Revision B (with
> revision ID 1); and revision B requires a SMP bringup workaround.
>
> Print the revision number when the SoC is A83T, as it does matter there.
>
> Signed-off-by: Timothy Pearson 
> [Icenowy: convert to macro so that it can be reused in PSCI code]
> Signed-off-by: Icenowy Zheng 
> ---
>  arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++
>  arch/arm/mach-sunxi/cpu_info.c  | 2 +-
>  2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
> b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> index 6aa5e91ada..a96680d8e8 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> @@ -205,6 +205,13 @@ void sunxi_board_init(void);
>  void sunxi_reset(void);
>  int sunxi_get_ss_bonding_id(void);
>  int sunxi_get_sid(unsigned int *sid);
> +
> +/*
> + * Implement it as a macro, because it's used both in PSCI source code
> + * and normal U-Boot source code.
> + */
> +#define sunxi_get_revision() (readl(SUNXI_SRAMC_BASE + 0x24) & 0xff)

Ideally, please add a macro for the register offset.

> +
>  #endif /* __ASSEMBLY__ */
>
>  #endif /* _SUNXI_CPU_SUN4I_H */
> diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
> index 25a5ec26a0..4236ab8f11 100644
> --- a/arch/arm/mach-sunxi/cpu_info.c
> +++ b/arch/arm/mach-sunxi/cpu_info.c
> @@ -84,7 +84,7 @@ int print_cpuinfo(void)
>  #elif defined CONFIG_MACH_SUN8I_A33
> printf("CPU:   Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id());
>  #elif defined CONFIG_MACH_SUN8I_A83T
> -   printf("CPU:   Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
> +   printf("CPU:   Allwinner A83T (SUN8I %04x rev. %x)\n", 
> sunxi_get_sram_id(), sunxi_get_revision());

Please wrap the line to under 80 characters.

Otherwise,

Reviewed-by: Chen-Yu Tsai 

>  #elif defined CONFIG_MACH_SUN8I_H3
> printf("CPU:   Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
>  #elif defined CONFIG_MACH_SUN8I_R40
> --
> 2.12.2
>
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Re: [U-Boot] [PATCH 3/6] rockchip: evb-rk3328: set uart2 and sdmmc io routing

[Kever Yang]

Simon,


On 06/01/2017 11:10 AM, Simon Glass wrote:

Hi Kever,

On 23 May 2017 at 20:35, Kever Yang  wrote:

Hi Simon,



On 05/20/2017 10:29 AM, Simon Glass wrote:

Hi Kever,

On 16 May 2017 at 21:44, Kever Yang  wrote:

In rk3328, some function pin may have more than one choice, and muxed
with more than one IO, for example, the UART2 controller IO,
TX and RX, have 3 choice(setting in com_iomux):
- M0 which mux with GPIO1A0/GPIO1A1
- M1 which mux with GPIO2A0/GPIO2A1
- usb2phy which mux with USB2.0 DP/DM pin.

We should set these IO routing in board file.

Signed-off-by: Kever Yang 
---

   board/rockchip/evb_rk3328/evb-rk3328.c | 12 
   1 file changed, 12 insertions(+)

diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c
b/board/rockchip/evb_rk3328/evb-rk3328.c
index a7895cb..d9dc782 100644
--- a/board/rockchip/evb_rk3328/evb-rk3328.c
+++ b/board/rockchip/evb_rk3328/evb-rk3328.c
@@ -5,7 +5,10 @@
*/

   #include 
+#include 
+#include 
   #include 
+#include 
   #include 
   #include 

@@ -13,6 +16,15 @@ DECLARE_GLOBAL_DATA_PTR;

   int board_init(void)
   {
+#define GRF_BASE   0xff10
+   struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
+
+   /* uart2 select m1, sdcard select m1*/
+   rk_clrsetreg(>com_iomux,
+IOMUX_SEL_UART2_MASK | IOMUX_SEL_SDMMC_MASK,
+IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
+IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
+
  return 0;
   }

This needs to be done via a call to some sort of driver. The above
hack is OK in SPL but not in U-Boot proper.


Yes, SPL also needs this. I thinks here should be the right place
before there is a SPL for rk3328.

But if you are booting from an SD card, how can you need a mux to
select it? Surely the boot ROM must set it up or you would not be able
to boot from MMC?


If we need to boot from SD card, then we need to follow the boot ROM 
setting,

and hardware also need to follow it.
There is another case, the default SD card pin is used for other 
function in hardware,

then we use the alternative pin mux, we can't boot from SD card in bootrom,
but we still can use SD card in later stage like U-Boot and kernel.

Thanks,
- Kever


When will there be SPL for rk3328?



See my comments elsewhere about using a misc driver with an IOCTL
interface to do this sort of thing. Although here I wonder why you
cannot use pinctrl?


This is different from traditional pinctrl, kernel also still not have
final solution on this, see [0], and some people think it should be
done in boot loader.

How about putting it in grf syscon driver?



Thanks,
- Kever
[0]
http://lists.infradead.org/pipermail/linux-rockchip/2016-August/011209.html


Regards,
Simon






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Re: [U-Boot] [linux-sunxi] [RFC PATCH 2/8] sunxi: add configuration of secure SRAM for A83T

[Chen-Yu Tsai]

On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng  wrote:
> A83T has some secure SRAM that can be used to place the PSCI code.
>
> Add the configuration of them.
>
> Signed-off-by: Icenowy Zheng 

Reviewed-by: Chen-Yu Tsai 
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Re: [U-Boot] [linux-sunxi] [RFC PATCH 1/8] sun8i: Add TZPC setup for A83T

[Chen-Yu Tsai]

On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng  wrote:
> From: "tpear...@raptorengineering.com" 

You should fix his name here.

>
> This patch enables non-secure access to all system peripherals
> controlled by the STMA, and additionally sets the secure RAM
> range to 64k in line with other sunxi devices.
>
> Signed-off-by: Timothy Pearson 
> Signed-off-by: Icenowy Zheng 
> ---
>  arch/arm/cpu/armv7/sunxi/Makefile  |  1 +
>  arch/arm/cpu/armv7/sunxi/tzpc.c| 10 ++
>  arch/arm/include/asm/arch-sunxi/tzpc.h |  6 ++
>  arch/arm/mach-sunxi/board.c|  2 +-
>  4 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
> b/arch/arm/cpu/armv7/sunxi/Makefile
> index b35b9df4a9..8c026ff052 100644
> --- a/arch/arm/cpu/armv7/sunxi/Makefile
> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
> @@ -11,6 +11,7 @@ obj-y += timer.o
>
>  obj-$(CONFIG_MACH_SUN6I)   += tzpc.o
>  obj-$(CONFIG_MACH_SUN8I_H3)+= tzpc.o
> +obj-$(CONFIG_MACH_SUN8I_A83T)  += tzpc.o
>
>  ifndef CONFIG_SPL_BUILD
>  obj-$(CONFIG_ARMV7_PSCI)   += psci.o
> diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c
> index 6c8a0fd9a2..50a5ff6b30 100644
> --- a/arch/arm/cpu/armv7/sunxi/tzpc.c
> +++ b/arch/arm/cpu/armv7/sunxi/tzpc.c
> @@ -18,6 +18,16 @@ void tzpc_init(void)
> writel(SUN6I_TZPC_DECPORT0_RTC, >decport0_set);
>  #endif
>
> +#ifdef SUN8I_A83T_TZPC_DECPORT0_ALL
> +   /* Set secure RAM size to defined value */
> +   writel(SUN8I_A83T_TZPC_R0SIZE_64K, >r0size);

As mentioned in the original review of this patch, this field is read only.
There is no need to write to this register.

> +
> +   /* Enable non-secure access to all peripherals */
> +   writel(SUN8I_A83T_TZPC_DECPORT0_ALL, >decport0_set);
> +   writel(SUN8I_A83T_TZPC_DECPORT1_ALL, >decport1_set);
> +   writel(SUN8I_A83T_TZPC_DECPORT2_ALL, >decport2_set);
> +#endif
> +
>  #ifdef CONFIG_MACH_SUN8I_H3
> /* Enable non-secure access to all peripherals */
> writel(SUN8I_H3_TZPC_DECPORT0_ALL, >decport0_set);
> diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h 
> b/arch/arm/include/asm/arch-sunxi/tzpc.h
> index 95c55cd4d1..5b85ee86f9 100644
> --- a/arch/arm/include/asm/arch-sunxi/tzpc.h
> +++ b/arch/arm/include/asm/arch-sunxi/tzpc.h
> @@ -25,6 +25,12 @@ struct sunxi_tzpc {
>
>  #define SUN6I_TZPC_DECPORT0_RTC(1 << 1)
>
> +#define SUN8I_A83T_TZPC_DECPORT0_ALL   0xbe
> +#define SUN8I_A83T_TZPC_DECPORT1_ALL   0x7f
> +#define SUN8I_A83T_TZPC_DECPORT2_ALL   0x10
> +/* The Secure RAM size, 0x10 means 64KiB */
> +#define SUN8I_A83T_TZPC_R0SIZE_64K 0x10

So this last one is not needed.

ChenYu

> +
>  #define SUN8I_H3_TZPC_DECPORT0_ALL  0xbe
>  #define SUN8I_H3_TZPC_DECPORT1_ALL  0xff
>  #define SUN8I_H3_TZPC_DECPORT2_ALL  0x7f
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> index 65b1ebd837..269555e77c 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -196,7 +196,7 @@ void s_init(void)
> "mcr p15, 0, r0, c1, c0, 1\n"
> ::: "r0");
>  #endif
> -#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
> +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A83T || defined 
> CONFIG_MACH_SUN8I_H3
> /* Enable non-secure access to some peripherals */
> tzpc_init();
>  #endif
> --
> 2.12.2
>
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Re: [U-Boot] [PATCH 08/13] rockchip: mmc: support rk3066 mmc

[Kever Yang]

Simon,


On 06/07/2017 05:10 AM, Simon Glass wrote:

Hi Pawel,

On 6 June 2017 at 12:51, Paweł Jarosz  wrote:

rk3066 and rk3288 mmc designware ip's are very similiar. They differ in
internal dma support and max driver frequency.

Signed-off-by: Paweł Jarosz 
---
  drivers/mmc/rockchip_dw_mmc.c | 31 +--
  1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 25a21e2..d94c395 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -22,8 +22,14 @@ DECLARE_GLOBAL_DATA_PTR;

  struct rockchip_mmc_plat {
  #if CONFIG_IS_ENABLED(OF_PLATDATA)
+
+#ifdef CONFIG_ROCKCHIP_RK3066
+   struct dtd_rockchip_rk2928_dw_mshc dtplat;
+#else
 struct dtd_rockchip_rk3288_dw_mshc dtplat;
  #endif
+
+#endif
 struct mmc_config cfg;
 struct mmc mmc;
  };
@@ -109,8 +115,11 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 int ret;

  #if CONFIG_IS_ENABLED(OF_PLATDATA)
+#ifdef CONFIG_ROCKCHIP_RK3066
+   struct dtd_rockchip_rk2928_dw_mshc *dtplat = >dtplat;
+#else
 struct dtd_rockchip_rk3288_dw_mshc *dtplat = >dtplat;
-
+#endif

I am not keen on this - it will get ugly. Can you please do this:

Create a new driver for rk3288 which just has the platdata stuff,
rockchip_dwmmc_ofdata_to_platdata() and the U_BOOT_DRIVER().
Everything else should remain in this file.

Then in a new patch, create a driver for rk3066 which uses the same
common elements from rockchip_dw_mmc.c


I think I have discuss this with you online or offline  for many times,
when OF_PLATADATA enabled, the dts is pre-compile by dtoc and then
there is structure like 'dtd_rockchip_rk2928_dw_mshc' which is from the dts
node compatible name, I propose to use the last compatible name in dtoc
instead of the first one, then we can get the same structure name and used
in drivers.

I still not enable the dwmmc when OF_PLATDATA enabled on rk3399 because
of the same reason.

I think we should fix this from the root cause, but not make different 
driver

for different SoCs.

Thanks,
- Kever



 host->name = dev->name;
 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
 host->buswidth = dtplat->bus_width;
@@ -118,7 +127,12 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 host->priv = dev;
 host->dev_index = 0;
 priv->fifo_depth = dtplat->fifo_depth;
+
+#ifdef CONFIG_ROCKCHIP_RK3066
+   priv->fifo_mode = 1;
+#else
 priv->fifo_mode = 0;
+#endif

What about the fifo_mode property in the DT?

If you have to hard-code this you should use a .data parameter in
rockchip_dwmmc_ids (e.g. RK2928, RK3288) and use that to determine the
mode. But hopefully the DT is enough.

For OF_PLATDATA however I suggest you have a different probe() which
either sets up this value and then calls rockchip_dwmmc_probe(), or
add it as a parameter to rockchip_dwmmc_probe().


 memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));

 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, >clk);
@@ -162,14 +176,27 @@ static int rockchip_dwmmc_bind(struct udevice *dev)
  }

  static const struct udevice_id rockchip_dwmmc_ids[] = {
+   { .compatible = "rockchip,rk2928-dw-mshc" },
 { .compatible = "rockchip,rk3288-dw-mshc" },
 { }
  };

+U_BOOT_DRIVER(rockchip_rk2928_dw_mshc) = {
+   .name   = "rockchip_rk2928_dw_mshc",
+   .id = UCLASS_MMC,
+   .of_match   = rockchip_dwmmc_ids,
+   .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
+   .ops= _dwmci_ops,
+   .bind   = rockchip_dwmmc_bind,
+   .probe  = rockchip_dwmmc_probe,
+   .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
+   .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
+};
+
  U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
 .name   = "rockchip_rk3288_dw_mshc",
 .id = UCLASS_MMC,
-   .of_match   = rockchip_dwmmc_ids,

I think you ne

 .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
 .ops= _dwmci_ops,
 .bind   = rockchip_dwmmc_bind,
--
2.7.4


Regards,
Simon
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Re: [U-Boot] [RFC PATCH 0/5] move boot0 hook in the beginning for armv7

[Simon Glass]

Hi Kever,

On 6 June 2017 at 20:41, Kever Yang  wrote:
> Simon,
>
>
>
> On 06/07/2017 05:08 AM, Simon Glass wrote:
>>
>> Hi Kever,
>>
>> On 31 May 2017 at 04:50, Kever Yang  wrote:
>>>
>>> I think the boot0 hook is suppose to add some data in the very beginning
>>> of the SPL image, am I right?
>>>
>>> Rockchip SoCs bootrom design is like this:
>>> - First 2KB or 4KB internal memory is for bootrom stack and heap;
>>> - Then the first 4-byte suppose to be a TAG like 'RK33';
>>> - The the following memory address end with '0004' is the first
>>>instruction load and running by bootrom;
>>>
>>> Example for RK3288:
>>> Before this patch set, the SPL_TEXT_BASE is ff704004, and image write to
>>> media device after mkimage like this:
>>>
>>> ff704000: 32334b52   RK32
>>> ff704010:    
>>> ff704020: ea0f e59ff014 e59ff014 e59ff014
>>> ff704030: e59ff014 e59ff014 e59ff014 e59ff014
>>>
>>> Where the first instruction from bootrom is '', which is a
>>> undefined instruction.
>>> The '_start' and 'reset' have to align to 0x20 for the requirement of
>>> VBAR, the memory offset '004'~'01c' are filled with ''.
>>>
>>> We can use the boot0 hook to fix this issue, after this patch set,
>>> the SPL_TEXT_BASE is ff704000 and image write to media device after
>>> mkimage like this:
>>>
>>> ff704000: 32334b52 ea1d e320f000 e320f000RK32.. ... .
>>> ff704010: e320f000 e320f000 e320f000 e320f000.. ... ... ... .
>>> ff704020: ea16 e59ff014 e59ff014 e59ff014
>>> ff704030: e59ff014 e59ff014 e59ff014 e59ff014
>>>
>>> The first instruction from bootrom is a 'b reset', and memory of
>>> '008'~'01c' are filled with 'nop' instruction.
>>>
>>> This patch set does not provide patch for socfpga, bcm and sunxi SoCs
>>> which also
>>> enable BOOT0_HOOK, so this is a RFC patch, please advice how to make it
>>> compatible with those three platforms.
>>>
>>>
>>>
>>> Kever Yang (5):
>>>armv7: move boot hook before '_start'
>>>rockchip: boot0: align to 0x20 for armv7 '_start'
>>>rockchip: enable BOOT0_HOOK for SoCs
>>>rockchip: configs: use aligned address for SPL_TEXT_BASE
>>>rockchip: mkimage: use spl_boot0 for all Rockchip SoCs
>>>
>>>   arch/arm/include/asm/arch-rockchip/boot0.h |  9 -
>>>   arch/arm/lib/vectors.S | 19 ++-
>>>   arch/arm/mach-rockchip/Kconfig |  3 +++
>>>   include/configs/rk3036_common.h|  2 +-
>>>   include/configs/rk3288_common.h|  2 +-
>>>   tools/rkcommon.c   |  8 
>>>   6 files changed, 27 insertions(+), 16 deletions(-)
>>>
>>> --
>>> 1.9.1
>>>
>> Do will still need this series now that (I think) we have a fix for
>> the return-to-brom feature in u-boot-rockchip/master?
>
>
> Could you point me out exactly which fix do you talking about?

These ones:

a079e52d35 rockchip: mkimage: set init_boot_size to avoid confusing the boot ROM
ee2c63912b rockchip: mkimage: force 2KB alignment for init_size
99c700c794 rockchip: mkimage: add support for verify_header/print_header

>
> This is not about return-to-brom, it's about the first instruction from
> Bootrom to SPL.
> So this is need for all Rockchip armv7 SoCs.

OK, how did we survive before? What has changed to make this series needed?

Regards,
Simon
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Re: [U-Boot] [PATCH 10/13] rockchip: rk3066: add sdram driver

[Kever Yang]

Simon, Pawel,


On 06/07/2017 05:10 AM, Simon Glass wrote:

On 6 June 2017 at 12:52, Paweł Jarosz  wrote:

Commit message?


Signed-off-by: Paweł Jarosz 
---
  arch/arm/mach-rockchip/rk3066/Makefile   |   1 +
  arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 +++
  2 files changed, 112 insertions(+)
  create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c


Acked-by: Simon Glass 


diff --git a/arch/arm/mach-rockchip/rk3066/Makefile 
b/arch/arm/mach-rockchip/rk3066/Makefile
index 4cf5df2..1d38518 100644
--- a/arch/arm/mach-rockchip/rk3066/Makefile
+++ b/arch/arm/mach-rockchip/rk3066/Makefile
@@ -6,6 +6,7 @@

  ifndef CONFIG_TPL_BUILD
  obj-y += clk_rk3066.o
+obj-y += sdram_rk3066.o
  obj-y += syscon_rk3066.o
  else
  obj-y += sdram_init.o
diff --git a/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c 
b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
new file mode 100644
index 000..a713ac4
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Adapted from the very similar rk3288 ddr init.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct dram_info {
+   struct ram_info info;
+   struct rk3188_pmu *pmu;
+};
+
+size_t sdram_size_mb(struct rk3188_pmu *pmu)

I wonder if most of this could go in a common function, or are the
registers / offsets different?


The definition of sys_reg for all the Rockchip SoC are the same, the only
difference may be some chip have dual channel while others only have one,
but the definition is not conflict.
The dram driver for rk3066, rk3188 and rk3288 are very similar.

Thanks,
- Kever



+{
+   u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
+   size_t chipsize_mb = 0;
+   size_t size_mb = 0;
+   u32 ch;
+   u32 sys_reg = readl(>sys_reg[2]);
+   u32 chans;
+
+   chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
+
+   for (ch = 0; ch < chans; ch++) {
+   rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
+   SYS_REG_RANK_MASK);
+   col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
+   bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
+   cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
+   SYS_REG_CS0_ROW_MASK);
+   cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
+   SYS_REG_CS1_ROW_MASK);
+   bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
+   SYS_REG_BW_MASK));
+   row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
+   SYS_REG_ROW_3_4_MASK;
+   chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
+
+   if (rank > 1)
+   chipsize_mb += chipsize_mb >>
+   (cs0_row - cs1_row);
+   if (row_3_4)
+   chipsize_mb = chipsize_mb * 3 / 4;
+   size_mb += chipsize_mb;
+   }
+
+   /* there can be no more than 2gb of memory */
+   size_mb = min(size_mb, 0x8000 >> 20);
+
+   return size_mb;
+}
+

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Re: [U-Boot] u-boot-flasher fails with current u-boot

[Simon Glass]

Hi Peter,

On 6 June 2017 at 17:36,   wrote:
> Recent changes to U-Boot have broken u-boot-flasher.I now see,
> after
> ./tegra-uboot-flasher flash jetson-tk1
> on the serial port:
>   >>> Selecting MMC device...
>   tegra_mmc_send_cmd_bounced: MMC Timeout
> Interrupt status0x0001
> Interrupt status enable 0x003b
> Interrupt signal enable 0x0002
> Present status  0x01fb02f6
>   mmc_init: -1, time 8042
>
> and nothing is flashed to the MMC.
>
> I can do
>  ./tegra-uboot-flasher exec jetson-tk1
> and everything works as expected.  The running-from-RAM u-boot can
> access the MMC.
>
> The patch in U-Boot that causes the problems (found by git-bisect) is
> 0e513e788f tegra: convert MMC to use driver model for operations

Oh dear. I cannot find my board but will see if I can repeat this on a beaver.

>
> --
> Dr Peter Chubb Tel: +61 2 9490 5852  http://ts.data61.csiro.au/
> Trustworthy Systems Group   Data61 (formerly NICTA)

Regards,
Simon
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[U-Boot] [PATCH v2] odroid: remove CONFIG_DM_I2C_COMPAT config

[Jaehoon Chung]

Remove the CONFIG_DM_I2C_COMPAT config.

Signed-off-by: Jaehoon Chung 
Reviewed-by: Simon Glass 
---
Changelog on V2:
- Rebased on latest u-boot-samsung
- Added Simon's Reviewed tag
- Fix the typo (COMPAT_DM_I2C_COMPAT -> CONFIG_DM_I2C_COMPAT)

 configs/odroid_defconfig | 2 +-
 include/configs/odroid.h | 5 -
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index ebfb910..22e86e2 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -38,7 +38,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_ISO_PARTITION=y
 CONFIG_OF_CONTROL=y
 CONFIG_DFU_MMC=y
-CONFIG_DM_I2C_COMPAT=y
+CONFIG_SYS_I2C_S3C24X0=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_SDHCI=y
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index afc7c5e..609a3d1 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -175,11 +175,6 @@
"scriptaddr=0x4200\0" \
"fdtaddr=4080\0"
 
-/* I2C */
-#define CONFIG_SYS_I2C_S3C24X0
-#define CONFIG_SYS_I2C_S3C24X0_SPEED   10
-#define CONFIG_SYS_I2C_S3C24X0_SLAVE   0
-
 /* GPT */
 #define CONFIG_RANDOM_UUID
 
-- 
2.10.2

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Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL

[Chee, Tien Fong]

On Sel, 2017-06-06 at 11:50 +0200, Marek Vasut wrote:
> On 06/06/2017 11:46 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2017-06-06 at 11:41 +0200, Marek Vasut wrote:
> > > 
> > > On 06/06/2017 11:36 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 06/06/2017 10:19 AM, Chee, Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > From: Tien Fong Chee 
> > > > > > > > 
> > > > > > > > This patch is for enabling FPGA driver support on SPL
> > > > > > > Why would we want that on Gen5 ? I believe this is only
> > > > > > > needed on
> > > > > > > Gen10.
> > > > > > > 
> > > > > > I already moved the fpga_manager driver into drivers/fpga/
> > > > > > on
> > > > > > patch
> > > > > > 6,
> > > > > > and fpga_manager drivers are required on SPL. Actually
> > > > > > fpga_manager
> > > > > > driver should be part of the drivers/fpga.
> > > > > I think I miss some fundamental piece of information . Why
> > > > > would
> > > > > I
> > > > > need
> > > > > anything from the FPGA framework in SPL on Gen5 ? It is not
> > > > > needed
> > > > > thus
> > > > > far. Is it because you shuffled some of the code around or
> > > > > what ?
> > > > > 
> > > > Because we need to know some status and mode type from FPGA
> > > > even we
> > > > did
> > > > not program FPGA in SPL.
> > > But we didn't have this option enabled before and everything
> > > worked
> > > on
> > > gen5, why do we need it now ?
> > > 
> > Because i already move them into fpga driver, because those
> > functions
> > should be part of fpga driver. So, this moving happen in patch 6.
> I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA
> framework ? Does the size of the Gen5 SPL change before and after
> this
> patchset ? If you did not check, please do.
Yeah, i confirm FPGA driver is availabled in SPL. A bit change in size,
1~2K more. I did the test on our devkits also.
> 
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Re: [U-Boot] [PATCH 2/2] power: regulator: lp87565: add regulator support

[Keerthy]

On Wednesday 07 June 2017 02:38 AM, Simon Glass wrote:
> Hi Keerthy,
> 
> On 1 June 2017 at 23:19, Keerthy  wrote:
>> The driver provides regulator set/get voltage
>> enable/disable functions for lp87565 family of PMICs.
>>
>> Signed-off-by: Keerthy 
>> ---
>>  drivers/power/regulator/Kconfig |   8 ++
>>  drivers/power/regulator/Makefile|   1 +
>>  drivers/power/regulator/lp87565_regulator.c | 199 
>> 
>>  3 files changed, 208 insertions(+)
>>  create mode 100644 drivers/power/regulator/lp87565_regulator.c
>>
>> diff --git a/drivers/power/regulator/Kconfig 
>> b/drivers/power/regulator/Kconfig
>> index ef057e0..203292f 100644
>> --- a/drivers/power/regulator/Kconfig
>> +++ b/drivers/power/regulator/Kconfig
>> @@ -149,3 +149,11 @@ config DM_REGULATOR_LP873X
>> This enables implementation of driver-model regulator uclass
>> features for REGULATOR LP873X and the family of LP873X PMICs.
>> The driver implements get/set api for: value and enable.
>> +
>> +config DM_REGULATOR_LP87565
>> +   bool "Enable driver for LP87565 PMIC regulators"
>> +depends on PMIC_LP87565
>> +   ---help---
>> +   This enables implementation of driver-model regulator uclass
>> +   features for REGULATOR LP87565 and the family of LP87565 PMICs.
>> +   The driver implements get/set api for value and enable.
> 
> What regulators are available? LDOs / bucks ?

Bucks. I will mention that in the description above.

> 
>> diff --git a/drivers/power/regulator/Makefile 
>> b/drivers/power/regulator/Makefile
>> index 3e01021..ce14d08 100644
>> --- a/drivers/power/regulator/Makefile
>> +++ b/drivers/power/regulator/Makefile
>> @@ -18,3 +18,4 @@ obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
>>  obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
>>  obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o
>>  obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
>> +obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
>> diff --git a/drivers/power/regulator/lp87565_regulator.c 
>> b/drivers/power/regulator/lp87565_regulator.c
>> new file mode 100644
>> index 000..f6a552e
>> --- /dev/null
>> +++ b/drivers/power/regulator/lp87565_regulator.c
>> @@ -0,0 +1,199 @@
>> +/*
>> + * (C) Copyright 2016
>> + * Texas Instruments Incorporated, 
>> + *
>> + * Keerthy 
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static const char lp87565_buck_ctrl1[LP87565_BUCK_NUM] = {0x2, 0x4, 0x6, 
>> 0x8, 0x2, 0x6};
>> +static const char lp87565_buck_vout[LP87565_BUCK_NUM] = {0xA, 0xC, 0xE, 
>> 0x10, 0xA, 0xE };
>> +
>> +static int lp87565_buck_enable(struct udevice *dev, int op, bool *enable)
>> +{
>> +   int ret;
>> +   unsigned int adr;
>> +   struct dm_regulator_uclass_platdata *uc_pdata;
>> +
>> +   uc_pdata = dev_get_uclass_platdata(dev);
>> +   adr = uc_pdata->ctrl_reg;
>> +
>> +   ret = pmic_reg_read(dev->parent, adr);
>> +   if (ret < 0)
>> +   return ret;
>> +
>> +   if (op == PMIC_OP_GET) {
>> +   ret &= LP87565_BUCK_MODE_MASK;
>> +
>> +   if (ret)
>> +   *enable = true;
>> +   else
>> +   *enable = false;
>> +
>> +   return 0;
>> +   } else if (op == PMIC_OP_SET) {
>> +   if (*enable)
>> +   ret |= LP87565_BUCK_MODE_MASK;
>> +   else
>> +   ret &= ~(LP87565_BUCK_MODE_MASK);
> 
> Drop ()

okay

> 
>> +   ret = pmic_reg_write(dev->parent, adr, ret);
>> +   if (ret)
>> +   return ret;
>> +   }
>> +
>> +   return 0;
>> +}
>> +
>> +static int lp87565_buck_volt2hex(int uV)
> 
> I'm a bit unsure about the word 'hex' here. Would it be better to use 'val'?

sure

> 
>> +{
>> +   if (uV > LP87565_BUCK_VOLT_MAX)
>> +   return -EINVAL;
>> +   else if (uV > 140)
>> +   return (uV - 142) / 2 + 0x9E;
>> +   else if (uV > 73)
>> +   return (uV - 735000) / 5000 + 0x18;
>> +   else if (uV >= 50)
>> +   return (uV - 50) / 1;
>> +   else
>> +   return -EINVAL;
>> +}
>> +
>> +static int lp87565_buck_hex2volt(int hex)
>> +{
>> +   if (hex > LP87565_BUCK_VOLT_MAX_HEX)
>> +   return -EINVAL;
>> +   else if (hex > 0x9D)
>> +   return 140 + (hex - 0x9D) * 2;
>> +   else if (hex > 0x17)
>> +   return 73 + (hex - 0x17) * 5000;
>> +   else if (hex >= 0x0)
>> +   return 50 + hex * 1;
>> +   else
>> +   return -EINVAL;
>> +}
>> +
>> +static int lp87565_buck_val(struct udevice 

Re: [U-Boot] [RFC PATCH 0/5] move boot0 hook in the beginning for armv7

[Kever Yang]

Simon,


On 06/07/2017 05:08 AM, Simon Glass wrote:

Hi Kever,

On 31 May 2017 at 04:50, Kever Yang  wrote:

I think the boot0 hook is suppose to add some data in the very beginning
of the SPL image, am I right?

Rockchip SoCs bootrom design is like this:
- First 2KB or 4KB internal memory is for bootrom stack and heap;
- Then the first 4-byte suppose to be a TAG like 'RK33';
- The the following memory address end with '0004' is the first
   instruction load and running by bootrom;

Example for RK3288:
Before this patch set, the SPL_TEXT_BASE is ff704004, and image write to
media device after mkimage like this:

ff704000: 32334b52   RK32
ff704010:    
ff704020: ea0f e59ff014 e59ff014 e59ff014
ff704030: e59ff014 e59ff014 e59ff014 e59ff014

Where the first instruction from bootrom is '', which is a
undefined instruction.
The '_start' and 'reset' have to align to 0x20 for the requirement of
VBAR, the memory offset '004'~'01c' are filled with ''.

We can use the boot0 hook to fix this issue, after this patch set,
the SPL_TEXT_BASE is ff704000 and image write to media device after
mkimage like this:

ff704000: 32334b52 ea1d e320f000 e320f000RK32.. ... .
ff704010: e320f000 e320f000 e320f000 e320f000.. ... ... ... .
ff704020: ea16 e59ff014 e59ff014 e59ff014
ff704030: e59ff014 e59ff014 e59ff014 e59ff014

The first instruction from bootrom is a 'b reset', and memory of
'008'~'01c' are filled with 'nop' instruction.

This patch set does not provide patch for socfpga, bcm and sunxi SoCs which also
enable BOOT0_HOOK, so this is a RFC patch, please advice how to make it
compatible with those three platforms.



Kever Yang (5):
   armv7: move boot hook before '_start'
   rockchip: boot0: align to 0x20 for armv7 '_start'
   rockchip: enable BOOT0_HOOK for SoCs
   rockchip: configs: use aligned address for SPL_TEXT_BASE
   rockchip: mkimage: use spl_boot0 for all Rockchip SoCs

  arch/arm/include/asm/arch-rockchip/boot0.h |  9 -
  arch/arm/lib/vectors.S | 19 ++-
  arch/arm/mach-rockchip/Kconfig |  3 +++
  include/configs/rk3036_common.h|  2 +-
  include/configs/rk3288_common.h|  2 +-
  tools/rkcommon.c   |  8 
  6 files changed, 27 insertions(+), 16 deletions(-)

--
1.9.1


Do will still need this series now that (I think) we have a fix for
the return-to-brom feature in u-boot-rockchip/master?


Could you point me out exactly which fix do you talking about?

This is not about return-to-brom, it's about the first instruction from 
Bootrom to SPL.

So this is need for all Rockchip armv7 SoCs.

Thanks,
- Kever

Regards,
Simon




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Re: [U-Boot] [PATCH 1/2] power: pmic: lp87565: Add the basic pmic support

[Keerthy]

On Wednesday 07 June 2017 02:38 AM, Simon Glass wrote:
> Hi,
> 
> On 1 June 2017 at 23:19, Keerthy  wrote:
>> Add support to bind the regulators/child nodes with the pmic.
>>
>> Signed-off-by: Keerthy 
>> ---
>>  drivers/power/pmic/Kconfig   |  7 
>>  drivers/power/pmic/Makefile  |  1 +
>>  drivers/power/pmic/lp87565.c | 85 
>> 
>>  include/power/lp87565.h  | 12 +++
>>  4 files changed, 105 insertions(+)
>>  create mode 100644 drivers/power/pmic/lp87565.c
>>  create mode 100644 include/power/lp87565.h
>>
>> diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
>> index 3f50c12..e3f9e4d 100644
>> --- a/drivers/power/pmic/Kconfig
>> +++ b/drivers/power/pmic/Kconfig
>> @@ -188,6 +188,13 @@ config PMIC_LP873X
>> The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
>> This driver binds the pmic children.
>>
>> +config PMIC_LP87565
>> +   bool "Enable driver for Texas Instruments LP87565 PMIC"
>> +   depends on DM_PMIC
>> +   ---help---
>> +   The LP87565 is a PMIC containing a bunch of SMPS.
>> +   This driver binds the pmic children.
>> +
>>  config POWER_MC34VR500
>> bool "Enable driver for Freescale MC34VR500 PMIC"
>> ---help---
>> diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
>> index f409e3a..f488799 100644
>> --- a/drivers/power/pmic/Makefile
>> +++ b/drivers/power/pmic/Makefile
>> @@ -21,6 +21,7 @@ obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
>>  obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
>>  obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
>>  obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
>> +obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
>>
>>  obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
>>  obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
>> diff --git a/drivers/power/pmic/lp87565.c b/drivers/power/pmic/lp87565.c
>> new file mode 100644
>> index 000..e82bb4a
>> --- /dev/null
>> +++ b/drivers/power/pmic/lp87565.c
>> @@ -0,0 +1,85 @@
>> +/*
>> + * (C) Copyright 2017 Texas Instruments Incorporated, 
>> + * Keerthy 
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static const struct pmic_child_info pmic_children_info[] = {
>> +   { .prefix = "buck", .driver = LP87565_BUCK_DRIVER },
>> +   { },
>> +};
>> +
>> +static int lp87565_write(struct udevice *dev, uint reg, const uint8_t *buff,
>> + int len)
>> +{
>> +   if (dm_i2c_write(dev, reg, buff, len)) {
>> +   error("write error to device: %p register: %#x!", dev, reg);
>> +   return -EIO;
>> +   }
>> +
>> +   return 0;
>> +}
>> +
>> +static int lp87565_read(struct udevice *dev, uint reg, uint8_t *buff, int 
>> len)
>> +{
>> +   if (dm_i2c_read(dev, reg, buff, len)) {
>> +   error("read error from device: %p register: %#x!", dev, reg);
>> +   return -EIO;
>> +   }
>> +
>> +   return 0;
>> +}
>> +
>> +static int lp87565_bind(struct udevice *dev)
>> +{
>> +   int regulators_node;
>> +   const void *blob = gd->fdt_blob;
>> +   int children;
>> +   int node = dev->of_offset;
>> +
>> +   regulators_node = fdt_subnode_offset(blob, node, "regulators");
> 
> Can you please update this to livetree? See rk8xx for an example.

Okay i believe using:

regulators_node = dev_read_subnode(dev, "regulators");

I will do that.

> 
>> +
>> +   if (regulators_node <= 0) {
>> +   printf("%s: %s reg subnode not found!", __func__, dev->name);
>> +   return -ENXIO;
>> +   }
>> +
>> +   children = pmic_bind_children(dev, regulators_node, 
>> pmic_children_info);
>> +   if (!children)
>> +   printf("%s: %s - no child found\n", __func__, dev->name);
>> +
>> +   /* Always return success for this device */
>> +   return 0;
>> +}
>> +
>> +static struct dm_pmic_ops lp87565_ops = {
>> +   .read = lp87565_read,
>> +   .write = lp87565_write,
>> +};
>> +
>> +static const struct udevice_id lp87565_ids[] = {
>> +   { .compatible = "ti,lp87565", .data = LP87565 },
>> +   { .compatible = "ti,lp87565-q1", .data = LP87565_Q1 },
>> +   { }
>> +};
>> +
>> +U_BOOT_DRIVER(pmic_lp87565) = {
>> +   .name = "lp87565_pmic",
>> +   .id = UCLASS_PMIC,
>> +   .of_match = lp87565_ids,
>> +   .bind = lp87565_bind,
>> +   .ops = _ops,
>> +};
>> diff --git a/include/power/lp87565.h b/include/power/lp87565.h
>> new file mode 100644
>> index 000..48e1386
>> --- /dev/null
>> +++ b/include/power/lp87565.h
>> @@ -0,0 +1,12 @@
>> +#define LP875650x0
>> +#define LP87565_Q1 0x1
>> +
>> +#define LP87565_BUCK_NUM   6
>> +
>> +/* Drivers name */
>> +#define LP87565_BUCK_DRIVER

Re: [U-Boot] [RFC PATCH 1/5] armv7: move boot hook before '_start'

[Kever Yang]

Hi Andre, Steve, Marek,

Could you help to check how to make it work with this patch on 
sunxi, bcm and socfpga platform?


Thanks,
- Kever
On 05/31/2017 06:50 PM, Kever Yang wrote:

The boot0 hook suppose to add some data before the SPL data,
let's move it at very begining and before '_start'.

Signed-off-by: Kever Yang 
---

  arch/arm/lib/vectors.S | 19 ++-
  1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index f53b1e9..b4cd825 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -35,6 +35,16 @@
  
  	.section ".vectors", "ax"
  
+#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK

+/*
+ * Various SoCs need something special and SoC-specific up front in
+ * order to boot, allow them to set that in their boot0.h file and then
+ * use it here.
+ */
+#include 
+
+#endif
+
  /*
   *
   *
@@ -60,15 +70,6 @@ _start:
ldr pc, _irq
ldr pc, _fiq
  
-#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK

-/*
- * Various SoCs need something special and SoC-specific up front in
- * order to boot, allow them to set that in their boot0.h file and then
- * use it here.
- */
-#include 
-#endif
-
  /*
   *
   *



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Re: [U-Boot] [ANN] U-Boot v2017.07-rc1 released

[Masahiro Yamada]

Hi Tom,


2017-06-06 9:52 GMT+09:00 Tom Rini :
> Hey all,
>
> So it's release day and I've put up v2017.07-rc1.  The merge window is
> now closed and I've updated git and the tarballs are also up now.
>
> As is often the case, my queue needs a bit of cleaning up still and as
> per the schedule, I plan to do -rc2 on the 19th of this month.  There's
> a few changes that should probably come in still that might be a bit
> disruptive but I think are mostly SoC-centric in their potential to
> disrupt so I'll likely still pull them in.
>
> I'm also expecting some "big" changes to come in that remove various
> boards/SoCs that haven't been active in a while and will help make
> our various migrations a bit easier.
>
> Thanks all!
>

I think v2017.07-rc1 is not tagged yet.





-- 
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Masahiro Yamada
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Re: [U-Boot] [PATCH v2 03/10] patman: Don't convert input data to unicode

[sjg]

The communication filter reads data in blocks and converts each block to
unicode (if necessary) one at a time. In the unlikely event that a unicode
character in the input spans a block this will not work. We get an error
like:

UnicodeDecodeError: 'utf8' codec can't decode bytes in position 1022-1023:
   unexpected end of data

There is no need to change the input to unicode, so the easiest fix is to
drop this feature.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 tools/patman/cros_subprocess.py | 4 
 1 file changed, 4 deletions(-)

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Re: [U-Boot] [PATCH v2 05/10] patman: Don't report unicode character

[sjg]

Unicode characters may appear in input patches so we should not warn about
them. Drop this warning.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 tools/patman/patchstream.py | 9 -
 1 file changed, 9 deletions(-)

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Re: [U-Boot] [PATCH v2 02/10] patman: Adjust handling of unicode email address

[sjg]

Don't mess with the email address when outputting them. Just make sure
they are encoded with utf-8.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Expand the patch to cover all cases
- Drop RFC tag
- Rewrite commit message

 tools/patman/gitutil.py |  2 ++
 tools/patman/series.py  | 10 +++---
 2 files changed, 9 insertions(+), 3 deletions(-)

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Re: [U-Boot] [PATCH v2 01/10] patman: encode CC list to UTF-8

[sjg]

From: Philipp Tomsich 

This change encodes the CC list to UTF-8 to avoid failures on
maintainer-addresses that include non-ASCII characters (observed on
Debian 7.11 with Python 2.7.3).

Without this, I get the following failure:
  Traceback (most recent call last):
File "tools/patman/patman", line 159, in 
  options.add_maintainers)
File "[snip]/u-boot/tools/patman/series.py", line 234, in MakeCcFile
  print(commit.patch, ', '.join(set(list)), file=fd)
  UnicodeEncodeError: 'ascii' codec can't encode character u'\xfc' in
position 81: ordinal not in range(128)
from Heiko's email address:
  [..., u'"Heiko St\xfcbner" ', ...]

While with this change added this encodes to:
  "=?UTF-8?q?Heiko=20St=C3=BCbner?= "

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 
Signed-off-by: Simon Glass 
---

Changes in v2: None

 tools/patman/series.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

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Re: [U-Boot] [PATCH v2 06/10] patman: Don't return the series in FixPatches()

[sjg]

There is no need for this function to return the same object that was
passed in. Drop the return value.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 tools/patman/patchstream.py | 1 -
 tools/patman/patman.py  | 4 ++--
 2 files changed, 2 insertions(+), 3 deletions(-)

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Re: [U-Boot] [PATCH v2 04/10] patman: Rename 'str' variable in EmailPatches()

[sjg]

This is not a good variable name in Python because 'str' is a type. It
shows up highlighted in some editors. Rename it.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 tools/patman/gitutil.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

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Re: [U-Boot] [PATCH] sandbox: Fix comparison of unsigned enum expression warning

[sjg]

On 13 May 2017 at 18:11, Tom Rini  wrote:
> In os_dirent_get_typename() we are checking that type falls within the
> known values of the enum os_dirent_t.  With clang-3.8 testing this value
> as being >= 0 results in a warning as it will always be true.  This
> assumes of course that we are only given valid data.  Given that we want
> to sanity check the input, we change this to check that it falls within
> the range of the first to the last entry in the given enum.
>
> Cc: Simon Glass 
> Signed-off-by: Tom Rini 
> ---
>  arch/sandbox/cpu/os.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Simon Glass 

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Re: [U-Boot] [PATCH] buildman: Fix bloat option when 'new' only drops functions

[sjg]

On 22 May 2017 at 11:48, Tom Rini  wrote:
> In the case where a new build only decreases sizes and does not increase
> any size we still want to report what functions have been dropped when
> doing a bloat comparison.
>
> Cc: Simon Glass 
> Signed-off-by: Tom Rini 
> ---
> This is important when doing Kconfig migrations and a given target has
> only decreased in size, we want to know what was dropped so we can see
> what needs to be re-enabled.
> ---
>  tools/buildman/builder.py | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Simon Glass 

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Re: [U-Boot] [PATCH v2 07/10] patman: Add unicode to test patches

[sjg]

Add some unicode to the test patches to make sure that patman does the
right thing.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 tools/patman/test.py | 9 +
 1 file changed, 9 insertions(+)

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Re: [U-Boot] [PATCH v2 09/10] patman: Rename 'list' variable in MakeCcFile()

[sjg]

This is not a good variable name in Python because 'list' is a type. It
shows up highlighted in some editors. Rename it.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 tools/patman/series.py | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

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Re: [U-Boot] [PATCH v2 08/10] patman: Add a maintainer test feature to MakeCcFile()

[sjg]

Allow the add_maintainers parameter to be a list of maintainers, thus
allowing us to simulate calling the script in tests without actually
needing it to work.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 tools/patman/series.py | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

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Re: [U-Boot] [PATCH v2 10/10] patman: Add a functional test

[sjg]

The existing test (patman --test) only covers basic checkpatch output.
We have had some problems with unicode processing and could use test
coverage for the various tags patman supports.

Add a new functional test which runs most of the patman flow on a few
test commits and checks that the results are correct.

See the documentation in the test for a description of what it does.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Add new clean-up patches and a functional test

 tools/patman/func_test.py  | 242 +
 tools/patman/patchstream.py|  13 ++
 tools/patman/patman.py |   6 +-
 tools/patman/test/-cover-letter.patch  |  23 ++
 .../test/0001-pci-Correct-cast-for-sandbox.patch   |  48 
 ...-cast-for-sandbox-in-fdtdec_setup_memory_.patch |  73 +++
 tools/patman/test/test01.txt   |  56 +
 7 files changed, 459 insertions(+), 2 deletions(-)
 create mode 100644 tools/patman/func_test.py
 create mode 100644 tools/patman/test/-cover-letter.patch
 create mode 100644 tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch
 create mode 100644
tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_memory_.patch
 create mode 100644 tools/patman/test/test01.txt

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Re: [U-Boot] spi: Drop atmel_dataflash_spi.c

[Yang, Wenyou]

On 2017/6/6 19:11, Tom Rini wrote:

On Tue, Jun 06, 2017 at 09:07:51AM +, wenyou.y...@microchip.com wrote:

Hi Tom,


On Mon, Jun 05, 2017 at 09:32:28PM +0200, Stelian Pop wrote:

Hi everybody,


The problem here is that you need to remove the boards in question
as well.  I see the baord maintainer was Cc'd on this email, so this
is a bit stronger of a poke, as I guess we need to drop these boards..

It looks like I'm still listed as the maintainer, although I haven't
been involved in u-boot development for years...

I no longer have access to any AT91 board, so if someone wants to take
over, it's ok to me. Otherwise, you can mark those boards as orphaned,
or remove them from the tree.

Thanks Stelian.  Wenyou, you've done some changes to some of these boards
recently, would you care to pick them up, or should I go ahead and remove them?

Please don't remove these boards.

We agree to drop atmel_dataflash_spi.c, and I will convert these
boards by using the new dataflash driver.

Please do the conversion and then we can drop the old file (otherwise
the build fails), and please send a patch updating the MAINTAINERS file
soon, thanks!

All right, thanks.




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Best Regards,
Wenyou Yang
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[U-Boot] [RFC PATCH 8/8] sunxi: enable PSCI for A83T SoC

[Icenowy Zheng]

As we have now a basical implementation of PSCI for A83T, enable
non-secure boot support and PSCI on A83T now.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/mach-sunxi/Kconfig | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 7ced838d6a..31d29de428 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -98,8 +98,12 @@ config MACH_SUN8I_A33
 config MACH_SUN8I_A83T
bool "sun8i (Allwinner A83T)"
select CPU_V7
+   select CPU_V7_HAS_NONSEC
+   select CPU_V7_HAS_VIRT
+   select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+   select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN8I_H3
bool "sun8i (Allwinner H3)"
-- 
2.12.2

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[U-Boot] [RFC PATCH 7/8] sunxi: Add basic PSCI implementation for multi-cluster SoCs

[Icenowy Zheng]

From: Chen-Yu Tsai 

Allwinner A80 and A83T SoCs have two clusters of CPU, each cluster
contains 4 cores. A80 is Cortex-A15 + Cortex-A7 configuration, while
A83T has two clusters of Cortex-A7.

This patch adds a basic version that allows bringing up the four cores
in the first cluster. The structure is based on existing sunxi PSCI code.

Signed-off-by: Chen-Yu Tsai 
[Icenowy: adapt for A83T]
Signed-off-by: Icenowy Zheng 
---
 arch/arm/cpu/armv7/sunxi/Makefile|   4 +
 arch/arm/cpu/armv7/sunxi/psci-mcpm.c | 258 +++
 2 files changed, 262 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci-mcpm.c

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index 8c026ff052..c789f686fd 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -14,8 +14,12 @@ obj-$(CONFIG_MACH_SUN8I_H3)  += tzpc.o
 obj-$(CONFIG_MACH_SUN8I_A83T)  += tzpc.o
 
 ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_MACH_SUN8I_A83T
+obj-$(CONFIG_ARMV7_PSCI)   += psci-mcpm.o
+else
 obj-$(CONFIG_ARMV7_PSCI)   += psci.o
 endif
+endif
 
 ifdef CONFIG_SPL_BUILD
 obj-y  += fel_utils.o
diff --git a/arch/arm/cpu/armv7/sunxi/psci-mcpm.c 
b/arch/arm/cpu/armv7/sunxi/psci-mcpm.c
new file mode 100644
index 00..ba8d669c7e
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/psci-mcpm.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright (C) 2016
+ * Author: Chen-Yu Tsai 
+ *
+ * Based on assembly code by Marc Zyngier ,
+ * which was based on code by Carl van Schaik .
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/*
+ * NOTE dense CPU IDs (0~3 for first cluster of 4 cores, 4~7 for the
+ * second cluster) are used throughout the PSCI code. Any MPIDR style
+ * values must be converted.
+ */
+
+/*
+ * Provide a dense CPU ID for 2-cluster systems. This must be coded in
+ * assembly as it gets called from psci_stack_setup, when the stack isn't
+ * available yet.
+ *
+ * Only r0 and r3 is usable. r8 - r12 are available if this function is
+ * only called from psci_stack_setup, which we cannot guarantee.
+ */
+u32 __secure __naked psci_get_cpu_id(void)
+{
+   asm volatile (
+   "mrcp15, 0, r3, c0, c0, 5   @ Get MPIDR\n"
+   "lsrr0, r3, #6\n"
+   "andr3, r3, #3\n"
+   "andr0, r0, #4\n"
+   "orrr0, r0, r3\n"
+   "bx lr\n"
+   );
+
+   /*
+* The last five lines are the compiler generated assembly code for
+*
+*  return (reg & 0x3) | (((reg >> 8) & 0x1) << 2);
+*
+* We can't guarantee that all compilers correctly use only r0 and
+* r3, so we use inline assembly here.
+*/
+}
+
+static void __secure cp15_write_cntp_tval(u32 tval)
+{
+   asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
+}
+
+static void __secure cp15_write_cntp_ctl(u32 val)
+{
+   asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+}
+
+static u32 __secure cp15_read_cntp_ctl(void)
+{
+   u32 val;
+
+   asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+
+   return val;
+}
+
+#define ONE_US (COUNTER_FREQUENCY / 100)
+
+/* Use a different name to avoid clashing with the non-secure function */
+static void __secure __udelay_sec(unsigned long us)
+{
+   u32 reg = ONE_US * us;
+
+   cp15_write_cntp_tval(reg);
+   isb();
+   cp15_write_cntp_ctl(3);
+
+   do {
+   isb();
+   reg = cp15_read_cntp_ctl();
+   } while (!(reg & BIT(2)));
+
+   cp15_write_cntp_ctl(0);
+   isb();
+}
+
+static void __secure clamp_release(u32 *clamp)
+{
+   writel(0xff, clamp);
+   __udelay_sec(10);
+   writel(0xfe, clamp);
+   __udelay_sec(10);
+   writel(0xf8, clamp);
+   __udelay_sec(10);
+   writel(0xf0, clamp);
+   __udelay_sec(10);
+   writel(0x00, clamp);
+}
+
+static void __secure clamp_set(u32 *clamp)
+{
+   writel(0xff, clamp);
+}
+
+static void __secure sunxi_core_power_switch(u32 *clamp, u32 *pwroff,
+bool on, int cpu)
+{
+   if (on) {
+   /* Release power clamp */
+   clamp_release(clamp);
+
+   __udelay_sec(20);
+
+   /* Clear power gating */
+   clrbits_le32(pwroff, BIT(cpu));
+   } else {
+   /* Set power gating */
+   setbits_le32(pwroff, BIT(cpu));
+
+   __udelay_sec(20);
+
+   /* Activate power clamp */
+   clamp_set(clamp);
+   }
+}
+
+static int __secure sunxi_cluster_is_a7(int cluster)
+{
+#ifdef CONFIG_MACH_SUN8I_A83T
+   return 1;
+#else
+   return (clustter == 0);
+#endif
+}
+
+static void __secure 

[U-Boot] [RFC PATCH 6/8] sunxi: add multi-cluster CPU PRCM register definition

[Icenowy Zheng]

A83T come with two clusters of CPU, for each cluster 1 the new registers
are in the reserved spaces after the original cluster 0.

Make the registers to have an array with length 2 (2 clusters), and
change the current code to reference only cluster 0 registers.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/cpu/armv7/sunxi/psci.c| 2 +-
 arch/arm/include/asm/arch-sunxi/prcm.h | 8 
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index b3a34de1aa..8caef6a85f 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -144,7 +144,7 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)
struct sunxi_prcm_reg *prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
-   sunxi_power_switch(>cpu_pwr_clamp[cpu], >cpu_pwroff,
+   sunxi_power_switch(>cpu_pwr_clamp[0][cpu], >cpu_pwroff[0],
   on, cpu);
 }
 #endif /* CONFIG_MACH_SUN7I */
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h 
b/arch/arm/include/asm/arch-sunxi/prcm.h
index ae3880b13b..c2a6e39ffc 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -220,16 +220,16 @@ struct __packed sunxi_prcm_reg {
u8 res5[0x3c];  /* 0x0b4 */
u32 clk_outd;   /* 0x0f0 */
u8 res6[0xc];   /* 0x0f4 */
-   u32 cpu_pwroff; /* 0x100 */
-   u8 res7[0xc];   /* 0x104 */
+   u32 cpu_pwroff[2];  /* 0x100 */
+   u8 res7[0x8];   /* 0x108 */
u32 vdd_sys_pwroff; /* 0x110 */
u8 res8[0x4];   /* 0x114 */
u32 gpu_pwroff; /* 0x118 */
u8 res9[0x4];   /* 0x11c */
u32 vdd_pwr_reset;  /* 0x120 */
u8 res10[0x1c]; /* 0x124 */
-   u32 cpu_pwr_clamp[4];   /* 0x140 but first one is actually unused */
-   u8 res11[0x30]; /* 0x150 */
+   u32 cpu_pwr_clamp[2][4];/* 0x140 but first one is actually unused */
+   u8 res11[0x20]; /* 0x160 */
u32 dram_pwr;   /* 0x180 */
u8 res12[0xc];  /* 0x184 */
u32 dram_tst;   /* 0x190 */
-- 
2.12.2

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[U-Boot] [RFC PATCH 4/8] sunxi: add SUNXI_R_CPUCFG_BASE for A83T SoC

[Icenowy Zheng]

A83T SoC has two part of CPUCFG configurations -- one part is at
0x0170, which contains most of the controls, and is like the one in
A80; the another part is at 0x01f01c00 (like other post-sun6i SoCs), but
contains now only a few registers.

Call it SUNXI_R_CPUCFG_BASE, like what the BSP Linux source code did.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index a96680d8e8..5c74714084 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -179,6 +179,8 @@ defined(CONFIG_MACH_SUN50I)
 !defined CONFIG_MACH_SUN8I_A83T && \
 !defined CONFIG_MACH_SUN8I_R40
 #define SUNXI_CPUCFG_BASE  0x01f01c00
+#elif defined CONFIG_MACH_SUN8I_A83T
+#define SUNXI_R_CPUCFG_BASE0x01f01c00
 #endif
 
 #define SUNXI_R_TWI_BASE   0x01f02400
-- 
2.12.2

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[U-Boot] [RFC PATCH 3/8] sun8i: Add a macro to read the silicon revision

[Icenowy Zheng]

From: "tpear...@raptorengineering.com" 

According to the user manuals released by Allwinner, the low 8-bit of
the 0x24 register in "System Control" (marked SRAMC in U-Boot source as
it controls some SRAMs' functionality since A10) is the silicon revision
of the chip.

This data is now important for A83T: according to the BSP source A83T
have two revisions: Revision A (with revision ID 0) and Revision B (with
revision ID 1); and revision B requires a SMP bringup workaround.

Print the revision number when the SoC is A83T, as it does matter there.

Signed-off-by: Timothy Pearson 
[Icenowy: convert to macro so that it can be reused in PSCI code]
Signed-off-by: Icenowy Zheng 
---
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++
 arch/arm/mach-sunxi/cpu_info.c  | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 6aa5e91ada..a96680d8e8 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -205,6 +205,13 @@ void sunxi_board_init(void);
 void sunxi_reset(void);
 int sunxi_get_ss_bonding_id(void);
 int sunxi_get_sid(unsigned int *sid);
+
+/*
+ * Implement it as a macro, because it's used both in PSCI source code
+ * and normal U-Boot source code.
+ */
+#define sunxi_get_revision() (readl(SUNXI_SRAMC_BASE + 0x24) & 0xff)
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _SUNXI_CPU_SUN4I_H */
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index 25a5ec26a0..4236ab8f11 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -84,7 +84,7 @@ int print_cpuinfo(void)
 #elif defined CONFIG_MACH_SUN8I_A33
printf("CPU:   Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN8I_A83T
-   printf("CPU:   Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
+   printf("CPU:   Allwinner A83T (SUN8I %04x rev. %x)\n", 
sunxi_get_sram_id(), sunxi_get_revision());
 #elif defined CONFIG_MACH_SUN8I_H3
printf("CPU:   Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN8I_R40
-- 
2.12.2

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[U-Boot] [RFC PATCH 5/8] sunxi: Add CPUCFG register definitions for A80/A83T SoCs

[Icenowy Zheng]

From: Chen-Yu Tsai 

The A80/A83T SoCs has a different CPUCFG register layout, likely due to
having 2 clusters. The A83T SoC has also a small extra CPUCFG part
located at single cluster SoCs' CPUCFG address (in CPUs domain).

Add a cpucfg header file for it, rename the original cpucfg.h to
cpucfg_sun4i.h and add a new cpucfg.h to automatically switch between
the two cpucfg header file.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Icenowy Zheng 
---
 arch/arm/include/asm/arch-sunxi/cpucfg.h   | 64 +++-
 arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h | 68 ++
 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h | 60 +++
 3 files changed, 134 insertions(+), 58 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h 
b/arch/arm/include/asm/arch-sunxi/cpucfg.h
index 297cdd28c0..cf60ff81b6 100644
--- a/arch/arm/include/asm/arch-sunxi/cpucfg.h
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
@@ -1,7 +1,5 @@
 /*
- * Sunxi A31 CPUCFG register definition.
- *
- * (C) Copyright 2014 Hans de Goede 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -9,60 +7,10 @@
 #ifndef _SUNXI_CPUCFG_H
 #define _SUNXI_CPUCFG_H
 
-#include 
-#include 
-
-#ifndef __ASSEMBLY__
-
-struct __packed sunxi_cpucfg_cpu {
-   u32 rst;/* base + 0x0 */
-   u32 ctrl;   /* base + 0x4 */
-   u32 status; /* base + 0x8 */
-   u8 res[0x34];   /* base + 0xc */
-};
-
-struct __packed sunxi_cpucfg_reg {
-   u8 res0[0x40];  /* 0x000 */
-   struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */
-   u8 res1[0x44];  /* 0x140 */
-   u32 gen_ctrl;   /* 0x184 */
-   u32 l2_status;  /* 0x188 */
-   u8 res2[0x4];   /* 0x18c */
-   u32 event_in;   /* 0x190 */
-   u8 res3[0xc];   /* 0x194 */
-   u32 super_standy_flag;  /* 0x1a0 */
-   u32 priv0;  /* 0x1a4 */
-   u32 priv1;  /* 0x1a8 */
-   u8 res4[0x4];   /* 0x1ac */
-   u32 cpu1_pwr_clamp; /* 0x1b0 sun7i only */
-   u32 cpu1_pwroff;/* 0x1b4 sun7i only */
-   u8 res5[0x2c];  /* 0x1b8 */
-   u32 dbg_ctrl1;  /* 0x1e4 */
-   u8 res6[0x18];  /* 0x1e8 */
-   u32 idle_cnt0_low;  /* 0x200 */
-   u32 idle_cnt0_high; /* 0x204 */
-   u32 idle_cnt0_ctrl; /* 0x208 */
-   u8 res8[0x4];   /* 0x20c */
-   u32 idle_cnt1_low;  /* 0x210 */
-   u32 idle_cnt1_high; /* 0x214 */
-   u32 idle_cnt1_ctrl; /* 0x218 */
-   u8 res9[0x4];   /* 0x21c */
-   u32 idle_cnt2_low;  /* 0x220 */
-   u32 idle_cnt2_high; /* 0x224 */
-   u32 idle_cnt2_ctrl; /* 0x228 */
-   u8 res10[0x4];  /* 0x22c */
-   u32 idle_cnt3_low;  /* 0x230 */
-   u32 idle_cnt3_high; /* 0x234 */
-   u32 idle_cnt3_ctrl; /* 0x238 */
-   u8 res11[0x4];  /* 0x23c */
-   u32 idle_cnt4_low;  /* 0x240 */
-   u32 idle_cnt4_high; /* 0x244 */
-   u32 idle_cnt4_ctrl; /* 0x248 */
-   u8 res12[0x34]; /* 0x24c */
-   u32 cnt64_ctrl; /* 0x280 */
-   u32 cnt64_low;  /* 0x284 */
-   u32 cnt64_high; /* 0x288 */
-};
+#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN9I)
+#include 
+#else
+#include 
+#endif
 
-#endif /* __ASSEMBLY__ */
 #endif /* _SUNXI_CPUCFG_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
new file mode 100644
index 00..af1a1d56c9
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
@@ -0,0 +1,68 @@
+/*
+ * Sunxi A31 CPUCFG register definition.
+ *
+ * (C) Copyright 2014 Hans de Goede 

[U-Boot] [RFC PATCH 1/8] sun8i: Add TZPC setup for A83T

[Icenowy Zheng]

From: "tpear...@raptorengineering.com" 

This patch enables non-secure access to all system peripherals
controlled by the STMA, and additionally sets the secure RAM
range to 64k in line with other sunxi devices.

Signed-off-by: Timothy Pearson 
Signed-off-by: Icenowy Zheng 
---
 arch/arm/cpu/armv7/sunxi/Makefile  |  1 +
 arch/arm/cpu/armv7/sunxi/tzpc.c| 10 ++
 arch/arm/include/asm/arch-sunxi/tzpc.h |  6 ++
 arch/arm/mach-sunxi/board.c|  2 +-
 4 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index b35b9df4a9..8c026ff052 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y += timer.o
 
 obj-$(CONFIG_MACH_SUN6I)   += tzpc.o
 obj-$(CONFIG_MACH_SUN8I_H3)+= tzpc.o
+obj-$(CONFIG_MACH_SUN8I_A83T)  += tzpc.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMV7_PSCI)   += psci.o
diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c
index 6c8a0fd9a2..50a5ff6b30 100644
--- a/arch/arm/cpu/armv7/sunxi/tzpc.c
+++ b/arch/arm/cpu/armv7/sunxi/tzpc.c
@@ -18,6 +18,16 @@ void tzpc_init(void)
writel(SUN6I_TZPC_DECPORT0_RTC, >decport0_set);
 #endif
 
+#ifdef SUN8I_A83T_TZPC_DECPORT0_ALL
+   /* Set secure RAM size to defined value */
+   writel(SUN8I_A83T_TZPC_R0SIZE_64K, >r0size);
+
+   /* Enable non-secure access to all peripherals */
+   writel(SUN8I_A83T_TZPC_DECPORT0_ALL, >decport0_set);
+   writel(SUN8I_A83T_TZPC_DECPORT1_ALL, >decport1_set);
+   writel(SUN8I_A83T_TZPC_DECPORT2_ALL, >decport2_set);
+#endif
+
 #ifdef CONFIG_MACH_SUN8I_H3
/* Enable non-secure access to all peripherals */
writel(SUN8I_H3_TZPC_DECPORT0_ALL, >decport0_set);
diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h 
b/arch/arm/include/asm/arch-sunxi/tzpc.h
index 95c55cd4d1..5b85ee86f9 100644
--- a/arch/arm/include/asm/arch-sunxi/tzpc.h
+++ b/arch/arm/include/asm/arch-sunxi/tzpc.h
@@ -25,6 +25,12 @@ struct sunxi_tzpc {
 
 #define SUN6I_TZPC_DECPORT0_RTC(1 << 1)
 
+#define SUN8I_A83T_TZPC_DECPORT0_ALL   0xbe
+#define SUN8I_A83T_TZPC_DECPORT1_ALL   0x7f
+#define SUN8I_A83T_TZPC_DECPORT2_ALL   0x10
+/* The Secure RAM size, 0x10 means 64KiB */
+#define SUN8I_A83T_TZPC_R0SIZE_64K 0x10
+
 #define SUN8I_H3_TZPC_DECPORT0_ALL  0xbe
 #define SUN8I_H3_TZPC_DECPORT1_ALL  0xff
 #define SUN8I_H3_TZPC_DECPORT2_ALL  0x7f
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 65b1ebd837..269555e77c 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -196,7 +196,7 @@ void s_init(void)
"mcr p15, 0, r0, c1, c0, 1\n"
::: "r0");
 #endif
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A83T || defined 
CONFIG_MACH_SUN8I_H3
/* Enable non-secure access to some peripherals */
tzpc_init();
 #endif
-- 
2.12.2

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[U-Boot] [RFC PATCH 2/8] sunxi: add configuration of secure SRAM for A83T

[Icenowy Zheng]

A83T has some secure SRAM that can be used to place the PSCI code.

Add the configuration of them.

Signed-off-by: Icenowy Zheng 
---
 include/configs/sun8i.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index 47f2813240..c6ba2a0c87 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -21,6 +21,7 @@
#define CONFIG_SUNXI_USB_PHYS   4
 #elif defined CONFIG_MACH_SUN8I_A83T
#define CONFIG_SUNXI_USB_PHYS   3
+   #define CONFIG_ARMV7_SECURE_BASESUNXI_SRAM_B_BASE
 #elif defined CONFIG_MACH_SUN8I_V3S
#define CONFIG_SUNXI_USB_PHYS   1
 #else
-- 
2.12.2

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[U-Boot] [RFC PATCH 0/8] Allwinner A83T PSCI SMP support

[Icenowy Zheng]

This is an experimental support for the PSCI SMP bringup of the first
cluster of Allwinner A83T SoC.

It's based on some code by Timothy Pearson for A83T (already quite old)
and Chen-Yu Tsai (which are originally for A80).

In order to ensure the Linux kernel to work properly in SMP environment,
some GIC workarounds implemented in [1] is needed.

[1] 
https://github.com/wens/linux/commit/c48654c1f737116e7a7660183c8c74fa91970528

Chen-Yu Tsai (2):
  sunxi: Add CPUCFG register definitions for A80/A83T SoCs
  sunxi: Add basic PSCI implementation for multi-cluster SoCs

Icenowy Zheng (4):
  sunxi: add configuration of secure SRAM for A83T
  sunxi: add SUNXI_R_CPUCFG_BASE for A83T SoC
  sunxi: add multi-cluster CPU PRCM register definition
  sunxi: enable PSCI for A83T SoC

tpear...@raptorengineering.com (2):
  sun8i: Add TZPC setup for A83T
  sun8i: Add a macro to read the silicon revision

 arch/arm/cpu/armv7/sunxi/Makefile  |   5 +
 arch/arm/cpu/armv7/sunxi/psci-mcpm.c   | 258 +
 arch/arm/cpu/armv7/sunxi/psci.c|   2 +-
 arch/arm/cpu/armv7/sunxi/tzpc.c|  10 +
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h|   9 +
 arch/arm/include/asm/arch-sunxi/cpucfg.h   |  64 +-
 arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h |  68 +++
 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h |  60 ++
 arch/arm/include/asm/arch-sunxi/prcm.h |   8 +-
 arch/arm/include/asm/arch-sunxi/tzpc.h |   6 +
 arch/arm/mach-sunxi/Kconfig|   4 +
 arch/arm/mach-sunxi/board.c|   2 +-
 arch/arm/mach-sunxi/cpu_info.c |   2 +-
 include/configs/sun8i.h|   1 +
 14 files changed, 434 insertions(+), 65 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci-mcpm.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h

-- 
2.12.2

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Re: [U-Boot] [PATCH v2 4/7] usb: dwc2-otg: make regs_otg (in platdata) a uintptr_t

[Simon Glass]

Hi,

On 6 June 2017 at 17:59, Dr. Philipp Tomsich
 wrote:
> Simon,
>
>> On 06 Jun 2017, at 23:09, Simon Glass  wrote:
>>
>> Hi Philipp,
>>
>> On 6 June 2017 at 07:42, Philipp Tomsich
>>  wrote:
>>> The regs_otg field in uintptr_t of the platform data structure for
>>> dwc2-otg has thus far been an unsigned int, but will eventually be
>>> casted into a void*.
>>>
>>> This raises the following error with GCC 6.3 and buildman:
>>>  ../drivers/usb/gadget/dwc2_udc_otg.c: In function 'dwc2_udc_probe':
>>>  ../drivers/usb/gadget/dwc2_udc_otg.c:821:8: warning: cast to pointer from 
>>> integer of different size [-Wint-to-pointer-cast]
>>>reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
>>>  ^
>>>
>>> This changes regs_otg to a uintptr_t to ensure that it is large enough
>>> to hold any valid pointer (and fix the associated warning).
>>>
>>> Signed-off-by: Philipp Tomsich 
>>>
>>> ---
>>>
>>> Changes in v2:
>>> - (new patch) fix a int-to-pointer cast warning for regs_otg in
>>>  dwc2-otg to fix a buildman failure for u-boot-rockchip/master@2b19b2f
>>>
>>> include/usb/dwc2_udc.h | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h
>>> index 7324d8a..1a370e0 100644
>>> --- a/include/usb/dwc2_udc.h
>>> +++ b/include/usb/dwc2_udc.h
>>> @@ -16,7 +16,7 @@ struct dwc2_plat_otg_data {
>>>int phy_of_node;
>>>int (*phy_control)(int on);
>>>unsigned intregs_phy;
>>> -   unsigned intregs_otg;
>>> +   uintptr_t   regs_otg;
>>
>> Can you use ulong instead?
>
> Sure, but can I first ask “why?”.
> I may reopen an old discussion with this… if so, forgive my ignorance:
>
> uintptr_t makes the most sense for this use case in the C99 (or later) type 
> system,
> as we want this field to hold an integer (i.e. the address from the physical 
> memory
> map for one of the register blocks) that will be casted into a pointer.
> The uintptr_t type will always the matching size in any and all programming 
> models;
> in contrast, ulong would be wrong for LLP64 (and LLP64 probably “doesn’t 
> matter”
> in the context of U-Boot anyway).
>
> What I always found odd, was that uintptr_t is optional according to ISO9899.
> I would thus not have been surprised if there’s a concern for portability 
> between
> compilers behind this, but then again … U-Boot makes extensive use of GCC
> extensions (such as inline assembly).
>
> So I am apparently missing something here.

I don't know of any deep reason except that long is defined to be able
to hold an address, and ulong makes sense since an address is
generally considered unsigned.

U-Boot by convention uses ulong for addresses. You can see this all
around the code base so I am really just arguing in favour of
consistency (and I suppose ulong is easier to type!)

Regards,
Simon
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Re: [U-Boot] [PATCH v2 4/7] usb: dwc2-otg: make regs_otg (in platdata) a uintptr_t

[Dr. Philipp Tomsich]

Simon,

> On 06 Jun 2017, at 23:09, Simon Glass  wrote:
> 
> Hi Philipp,
> 
> On 6 June 2017 at 07:42, Philipp Tomsich
>  wrote:
>> The regs_otg field in uintptr_t of the platform data structure for
>> dwc2-otg has thus far been an unsigned int, but will eventually be
>> casted into a void*.
>> 
>> This raises the following error with GCC 6.3 and buildman:
>>  ../drivers/usb/gadget/dwc2_udc_otg.c: In function 'dwc2_udc_probe':
>>  ../drivers/usb/gadget/dwc2_udc_otg.c:821:8: warning: cast to pointer from 
>> integer of different size [-Wint-to-pointer-cast]
>>reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
>>  ^
>> 
>> This changes regs_otg to a uintptr_t to ensure that it is large enough
>> to hold any valid pointer (and fix the associated warning).
>> 
>> Signed-off-by: Philipp Tomsich 
>> 
>> ---
>> 
>> Changes in v2:
>> - (new patch) fix a int-to-pointer cast warning for regs_otg in
>>  dwc2-otg to fix a buildman failure for u-boot-rockchip/master@2b19b2f
>> 
>> include/usb/dwc2_udc.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h
>> index 7324d8a..1a370e0 100644
>> --- a/include/usb/dwc2_udc.h
>> +++ b/include/usb/dwc2_udc.h
>> @@ -16,7 +16,7 @@ struct dwc2_plat_otg_data {
>>int phy_of_node;
>>int (*phy_control)(int on);
>>unsigned intregs_phy;
>> -   unsigned intregs_otg;
>> +   uintptr_t   regs_otg;
> 
> Can you use ulong instead?

Sure, but can I first ask “why?”.
I may reopen an old discussion with this… if so, forgive my ignorance:

uintptr_t makes the most sense for this use case in the C99 (or later) type 
system,
as we want this field to hold an integer (i.e. the address from the physical 
memory
map for one of the register blocks) that will be casted into a pointer. 
The uintptr_t type will always the matching size in any and all programming 
models;
in contrast, ulong would be wrong for LLP64 (and LLP64 probably “doesn’t matter”
in the context of U-Boot anyway).

What I always found odd, was that uintptr_t is optional according to ISO9899.
I would thus not have been surprised if there’s a concern for portability 
between
compilers behind this, but then again … U-Boot makes extensive use of GCC
extensions (such as inline assembly).

So I am apparently missing something here.

Cheers,
Philipp.

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Re: [U-Boot] [PATCH v2 00/10] patman: Fix unicode operation and add a functional test

[Simon Glass]

On 5 June 2017 at 16:50, Dr. Philipp Tomsich
 wrote:
> I have this on my tree since you sent it out and my last round of
> patch-submissions was already done with this version of patman.
> There were a few UTF-8 characters involved and all worked as
> expected.
>
> So you can consider it
> Tested-by: Philipp Tomsich 

Thanks - I've added your tag.

- Simon
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Re: [U-Boot] [PATCH 11/13] rockchip: serial: support rockchip rk3066

[Simon Glass]

Hi Pawel,

On 6 June 2017 at 12:53, Paweł Jarosz  wrote:
> update driver to support rk3066 serial
>
> Signed-off-by: Paweł Jarosz 
> ---
>  drivers/serial/serial_rockchip.c | 19 ++-
>  1 file changed, 18 insertions(+), 1 deletion(-)

Similar comments here to the mmc driver.

Regards,
Simon
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Re: [U-Boot] [PATCH 07/13] rockchip: rk3066: add mk808 board files

[Simon Glass]

On 6 June 2017 at 12:51, Paweł Jarosz  wrote:
> mk808 is a tv stick with two usb ports, micro sd card slot, hdmi and
> nand onboard.
>
> Signed-off-by: Paweł Jarosz 
> ---
>  arch/arm/dts/Makefile   |   1 +
>  arch/arm/dts/rk3066a-mk808.dts  | 172 
> 
>  board/rikomagic/mk808_rk3066/Kconfig|  15 +++
>  board/rikomagic/mk808_rk3066/MAINTAINERS|   6 +
>  board/rikomagic/mk808_rk3066/Makefile   |   7 ++
>  board/rikomagic/mk808_rk3066/mk808_rk3066.c |  10 ++
>  configs/mk808-rk3066_defconfig  |  54 +
>  include/configs/mk808_rk3066.h  |  15 +++
>  8 files changed, 280 insertions(+)
>  create mode 100644 arch/arm/dts/rk3066a-mk808.dts
>  create mode 100644 board/rikomagic/mk808_rk3066/Kconfig
>  create mode 100644 board/rikomagic/mk808_rk3066/MAINTAINERS
>  create mode 100644 board/rikomagic/mk808_rk3066/Makefile
>  create mode 100644 board/rikomagic/mk808_rk3066/mk808_rk3066.c
>  create mode 100644 configs/mk808-rk3066_defconfig
>  create mode 100644 include/configs/mk808_rk3066.h

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 08/13] rockchip: mmc: support rk3066 mmc

[Simon Glass]

Hi Pawel,

On 6 June 2017 at 12:51, Paweł Jarosz  wrote:
> rk3066 and rk3288 mmc designware ip's are very similiar. They differ in
> internal dma support and max driver frequency.
>
> Signed-off-by: Paweł Jarosz 
> ---
>  drivers/mmc/rockchip_dw_mmc.c | 31 +--
>  1 file changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
> index 25a21e2..d94c395 100644
> --- a/drivers/mmc/rockchip_dw_mmc.c
> +++ b/drivers/mmc/rockchip_dw_mmc.c
> @@ -22,8 +22,14 @@ DECLARE_GLOBAL_DATA_PTR;
>
>  struct rockchip_mmc_plat {
>  #if CONFIG_IS_ENABLED(OF_PLATDATA)
> +
> +#ifdef CONFIG_ROCKCHIP_RK3066
> +   struct dtd_rockchip_rk2928_dw_mshc dtplat;
> +#else
> struct dtd_rockchip_rk3288_dw_mshc dtplat;
>  #endif
> +
> +#endif
> struct mmc_config cfg;
> struct mmc mmc;
>  };
> @@ -109,8 +115,11 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
> int ret;
>
>  #if CONFIG_IS_ENABLED(OF_PLATDATA)
> +#ifdef CONFIG_ROCKCHIP_RK3066
> +   struct dtd_rockchip_rk2928_dw_mshc *dtplat = >dtplat;
> +#else
> struct dtd_rockchip_rk3288_dw_mshc *dtplat = >dtplat;
> -
> +#endif

I am not keen on this - it will get ugly. Can you please do this:

Create a new driver for rk3288 which just has the platdata stuff,
rockchip_dwmmc_ofdata_to_platdata() and the U_BOOT_DRIVER().
Everything else should remain in this file.

Then in a new patch, create a driver for rk3066 which uses the same
common elements from rockchip_dw_mmc.c

> host->name = dev->name;
> host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
> host->buswidth = dtplat->bus_width;
> @@ -118,7 +127,12 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
> host->priv = dev;
> host->dev_index = 0;
> priv->fifo_depth = dtplat->fifo_depth;
> +
> +#ifdef CONFIG_ROCKCHIP_RK3066
> +   priv->fifo_mode = 1;
> +#else
> priv->fifo_mode = 0;
> +#endif

What about the fifo_mode property in the DT?

If you have to hard-code this you should use a .data parameter in
rockchip_dwmmc_ids (e.g. RK2928, RK3288) and use that to determine the
mode. But hopefully the DT is enough.

For OF_PLATDATA however I suggest you have a different probe() which
either sets up this value and then calls rockchip_dwmmc_probe(), or
add it as a parameter to rockchip_dwmmc_probe().

> memcpy(priv->minmax, dtplat->clock_freq_min_max, 
> sizeof(priv->minmax));
>
> ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, >clk);
> @@ -162,14 +176,27 @@ static int rockchip_dwmmc_bind(struct udevice *dev)
>  }
>
>  static const struct udevice_id rockchip_dwmmc_ids[] = {
> +   { .compatible = "rockchip,rk2928-dw-mshc" },
> { .compatible = "rockchip,rk3288-dw-mshc" },
> { }
>  };
>
> +U_BOOT_DRIVER(rockchip_rk2928_dw_mshc) = {
> +   .name   = "rockchip_rk2928_dw_mshc",
> +   .id = UCLASS_MMC,
> +   .of_match   = rockchip_dwmmc_ids,
> +   .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
> +   .ops= _dwmci_ops,
> +   .bind   = rockchip_dwmmc_bind,
> +   .probe  = rockchip_dwmmc_probe,
> +   .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
> +   .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
> +};
> +
>  U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
> .name   = "rockchip_rk3288_dw_mshc",
> .id = UCLASS_MMC,
> -   .of_match   = rockchip_dwmmc_ids,
I think you ne
> .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
> .ops= _dwmci_ops,
> .bind   = rockchip_dwmmc_bind,
> --
> 2.7.4
>

Regards,
Simon
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Re: [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S

[Simon Glass]

Hi Pawel,

On 6 June 2017 at 12:53, Paweł Jarosz  wrote:
> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00 and
> executes it. Then waits for back to bootrom and loads another 32KB to sram
> which also executes. Sdram initialisation code needs to be in one of these two
> steps. Then bootloader loads another ~200KB of data at offset 0x6000
> and jumps to it.
>
> 32KB of data is a little low for tpl + spl part and ~200KB data is to low for
> u-boot part(for example to boot from mmc you need to disable usb support.
>
> My solution to size problem is to move sdram initialisation code to tpl stage,
> move spl part to third stage(reading 200KB data) and add support for loading
> u-boot by spl from ext2/4, fat partitions.
>
> But moving sdram initialisation code to tpl increases size of tpl above 1KB
> (first boot stage). Solution to this is to add code which will be below 1KB
> offset in tpl binary and do back to bootrom at very beginning of the tpl
> execution.

So do you mean that TPL starts and then loads more of itself? Why not
put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
not clear why.

>
> Adding this few lines of code here meets these conditions.
>
> Signed-off-by: Paweł Jarosz 
> ---
>  arch/arm/cpu/armv7/start.S | 13 +
>  1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> index f06fd28..73e03d9 100644
> --- a/arch/arm/cpu/armv7/start.S
> +++ b/arch/arm/cpu/armv7/start.S
> @@ -36,6 +36,19 @@
>  #endif
>
>  reset:
> +
> +#if defined(CONFIG_ROCKCHIP_RK3066) && defined(CONFIG_TPL_BUILD)
> +   ldr r3, =0x10080900
> +   ldr r0, [r3]
> +   cmp r0, #1
> +   movne   r0, #1
> +   strne   r0, [r3]
> +   beq out_of_bootrom
> +   bx  lr
> +out_of_bootrom:
> +   mov r0, #0
> +   str r0, [r3]
> +#endif
> /* Allow the board to save important registers */
> b   save_boot_params
>  save_boot_params_ret:
> --
> 2.7.4
>

Regards,
Simon
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Re: [U-Boot] dtb build issue on U-Boot

[Simon Glass]

+Masahiro

On 6 June 2017 at 05:45, Kever Yang  wrote:
>
> I notice that the dtb content in spl/u-boot-spl.bin and u-boot.bin not
>
> able to update after I modify the dts file and make again, I have to
>
> "make clean" first, and then the "make" can update the dtb content
>
> to output binary, which lead to bad efficiency when try to modify dts.
>
> I have try below command, the dtb file also not updated before "make clean".
>
> dtc -I dtb -O dts spl/u-boot-spl.dtb
>
> Is there any one can help fix this issue?

I have noticed this too, and also that changing a .dtsi file is not noticed.

Probably it is missing a dependency in the makefile.

Regards,
Simon
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Re: [U-Boot] [PATCH v2 4/7] usb: dwc2-otg: make regs_otg (in platdata) a uintptr_t

[Simon Glass]

Hi Philipp,

On 6 June 2017 at 07:42, Philipp Tomsich
 wrote:
> The regs_otg field in uintptr_t of the platform data structure for
> dwc2-otg has thus far been an unsigned int, but will eventually be
> casted into a void*.
>
> This raises the following error with GCC 6.3 and buildman:
>   ../drivers/usb/gadget/dwc2_udc_otg.c: In function 'dwc2_udc_probe':
>   ../drivers/usb/gadget/dwc2_udc_otg.c:821:8: warning: cast to pointer from 
> integer of different size [-Wint-to-pointer-cast]
> reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
>   ^
>
> This changes regs_otg to a uintptr_t to ensure that it is large enough
> to hold any valid pointer (and fix the associated warning).
>
> Signed-off-by: Philipp Tomsich 
>
> ---
>
> Changes in v2:
> - (new patch) fix a int-to-pointer cast warning for regs_otg in
>   dwc2-otg to fix a buildman failure for u-boot-rockchip/master@2b19b2f
>
>  include/usb/dwc2_udc.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h
> index 7324d8a..1a370e0 100644
> --- a/include/usb/dwc2_udc.h
> +++ b/include/usb/dwc2_udc.h
> @@ -16,7 +16,7 @@ struct dwc2_plat_otg_data {
> int phy_of_node;
> int (*phy_control)(int on);
> unsigned intregs_phy;
> -   unsigned intregs_otg;
> +   uintptr_t   regs_otg;

Can you use ulong instead?

> unsigned intusb_phy_ctrl;
> unsigned intusb_flags;
> unsigned intusb_gusbcfg;
> --
> 2.1.4
>

Regards,
Simon
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Re: [U-Boot] [PATCH 13/13] rockchip: rk3066: add sdram init code for tpl

[Simon Glass]

Hi Pawel,

On 6 June 2017 at 12:53, Paweł Jarosz  wrote:
> Add sdram initialisation code which will be ussed by tpl first boot stage.
> We need to implement sdram initialisation in tpl due to size issues on rk3066
> platform.
>
> Signed-off-by: Paweł Jarosz 
> ---
>  arch/arm/include/asm/arch-rockchip/ddr_rk3188.h |   5 +
>  arch/arm/mach-rockchip/rk3066/sdram_init.c  | 995 
> 
>  2 files changed, 1000 insertions(+)
>  create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_init.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h 
> b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
> index 3d7929f..74d11c6 100644
> --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
> @@ -10,6 +10,11 @@
>  #include 
>
>  /*
> + * RK3066 Tpl memory init.
> + */
> +void sdram_initialise(void);
> +
> +/*
>   * RK3188 Memory scheduler register map.
>   */
>  struct rk3188_msch {
> diff --git a/arch/arm/mach-rockchip/rk3066/sdram_init.c 
> b/arch/arm/mach-rockchip/rk3066/sdram_init.c
> new file mode 100644
> index 000..e7e506a
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/sdram_init.c
> @@ -0,0 +1,995 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + * Copyright 2014 Rockchip Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + *
> + * Adapted from the very similar rk3288 ddr init.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct pll_div {
> +   u32 nr;
> +   u32 nf;
> +   u32 no;
> +};
> +
> +enum {
> +   VCO_MAX_HZ  = 1416U * 100,
> +   VCO_MIN_HZ  = 300 * 100,
> +   OUTPUT_MAX_HZ   = 1416U * 100,
> +   OUTPUT_MIN_HZ   = 30 * 100,
> +   FREF_MAX_HZ = 1416U * 100,
> +   FREF_MIN_HZ = 30 * 1000,
> +};
> +
> +enum {
> +   /* PLL CON0 */
> +   PLL_OD_MASK = 0x0f,
> +
> +   /* PLL CON1 */
> +   PLL_NF_MASK = 0x1fff,
> +
> +   /* PLL CON2 */
> +   PLL_BWADJ_MASK  = 0x0fff,
> +
> +   /* PLL CON3 */
> +   PLL_RESET_SHIFT = 5,
> +
> +   /* GRF_SOC_STATUS0 */
> +   SOCSTS_DPLL_LOCK= 1 << 4,
> +   SOCSTS_APLL_LOCK= 1 << 5,
> +   SOCSTS_CPLL_LOCK= 1 << 6,
> +   SOCSTS_GPLL_LOCK= 1 << 7,
> +};
> +
> +#define CRU_BASE   0x2000
> +#define GRF_BASE   0x20008000
> +#define PMU_BASE   0x20004000
> +#define PCTL_BASE  0x2002
> +#define PUBL_BASE  0x2004
> +#define NOC_BASE   0x10128000

I'm assume we cannot use the DT / syscon because of space constraints?

> +
> +#define RK3066_PCTL_TIMING_DEFAULT { \

Do you need this? Why not just put these values below and avoid the indirection?

> +   .togcnt1u = 0x12c, \
> +   .tinit = 0xc8, \
> +   .trsth = 0x1f4, \
> +   .togcnt100n = 0x1e, \
> +   .trefi = 0x4e, \
> +   .tmrd = 0x4, \
> +   .trfc = 0x69, \
> +   .trp = 0x6, \
> +   .trtw = 0x3, \
> +   .tal = 0x0, \
> +   .tcl = 0x6, \
> +   .tcwl = 0x5, \
> +   .tras = 0xc, \
> +   .trc = 0x10, \
> +   .trcd = 0x6, \
> +   .trrd = 0x4, \
> +   .trtp = 0x4, \
> +   .twr = 0x5, \
> +   .twtr = 0x4, \
> +   .texsr = 0x200, \
> +   .txp = 0x3, \
> +   .txpdll = 0xa, \
> +   .tzqcs = 0x40, \
> +   .tzqcsi = 0x0, \
> +   .tdqs = 0x1, \
> +   .tcksre = 0x5, \
> +   .tcksrx = 0x5, \
> +   .tcke = 0x3, \
> +   .tmod = 0xc, \
> +   .trstl = 0x1e, \
> +   .tzqcl = 0x100, \
> +   .tmrr = 0x0, \
> +   .tckesr = 0x4, \
> +   .tdpd = 0x0 \
> +}
> +
> +#define RK3066_PHY_TIMING_DEFAULT { \
> +   .dtpr0 = 0x208c6690, \
> +   .dtpr1 = 0x690878, \
> +   .dtpr2 = 0x10022a00, \
> +   .mr = { 0x220, 0x40, 0x0,  0x0 } \
> +}
> +
> +#define RK3066_SDRAM_PARAMS_DEFAULT { \
> +   .noc_timing = 0x24716310, \
> +   .noc_activate = 0, \
> +   .ddrconfig = 2, \
> +   .ddr_freq = 3, \
> +   .dramtype = 3, \
> +   .stride = 9, \
> +   .odt = 0 \
> +}
> +
> +#ifndef RK3066_PCTL_TIMING
> +#define RK3066_PCTL_TIMING RK3066_PCTL_TIMING_DEFAULT
> +#endif
> +
> +#ifndef RK3066_PHY_TIMING
> +#define RK3066_PHY_TIMING  RK3066_PHY_TIMING_DEFAULT
> +#endif
> +
> +#ifndef RK3066_SDRAM_PARAMS
> +#define RK3066_SDRAM_PARAMSRK3066_SDRAM_PARAMS_DEFAULT
> +#endif
> +
> +struct chan_info {
> +   struct rk3288_ddr_pctl *pctl;
> +   struct rk3288_ddr_publ *publ;
> +   struct rk3188_msch *msch;
> +};
> +
> +struct dram_info {
> +   struct chan_info chan[1];
> +   struct ram_info info;
> +   struct rk3066_cru *cru;
> +   struct rk3066_grf *grf;
> +   struct rk3188_pmu *pmu;
> +};
> +
> +struct rk3066_sdram_params {
> + 

Re: [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support

[Simon Glass]

Hi Pawel,

On 6 June 2017 at 12:50, Paweł Jarosz  wrote:
> Add core skeleton for rk3066
>
> Signed-off-by: Paweł Jarosz 
> ---
>  arch/arm/mach-rockchip/Kconfig|  16 +++
>  arch/arm/mach-rockchip/Makefile   |   4 +
>  arch/arm/mach-rockchip/rk3066-board-spl.c | 173 +
>  arch/arm/mach-rockchip/rk3066-board-tpl.c |  46 +++
>  arch/arm/mach-rockchip/rk3066-board.c | 180 
> ++
>  arch/arm/mach-rockchip/rk3066/Kconfig |  34 +
>  arch/arm/mach-rockchip/rk3066/Makefile|  12 ++
>  arch/arm/mach-rockchip/rk3066/clk_rk3066.c|  33 +
>  arch/arm/mach-rockchip/rk3066/syscon_rk3066.c |  54 
>  include/configs/rk3066_common.h   | 125 ++
>  10 files changed, 677 insertions(+)
>  create mode 100644 arch/arm/mach-rockchip/rk3066-board-spl.c
>  create mode 100644 arch/arm/mach-rockchip/rk3066-board-tpl.c
>  create mode 100644 arch/arm/mach-rockchip/rk3066-board.c
>  create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig
>  create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile
>  create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c
>  create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
>  create mode 100644 include/configs/rk3066_common.h
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 6be2ab5..ad35e0a 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -11,6 +11,21 @@ config ROCKCHIP_RK3036
>   and video codec support. Peripherals include Gigabit Ethernet,
>   USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
>
> +config ROCKCHIP_RK3066
> +   bool "Support Rockchip RK3066"
> +   select CPU_V7
> +   select SUPPORT_SPL
> +   select SUPPORT_TPL
> +   select SPL
> +   select TPL
> +   select BOARD_LATE_INIT
> +   select ROCKCHIP_BROM_HELPER
> +   help
> + The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A7
> + including NEON and GPU, Mali-400 graphics, several DDR3 options
> + and video codec support. Peripherals include Gigabit Ethernet,
> + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
> +
>  config ROCKCHIP_RK3188
> bool "Support Rockchip RK3188"
> select CPU_V7
> @@ -91,6 +106,7 @@ config SPL_MMC_SUPPORT
> default y if !ROCKCHIP_SPL_BACK_TO_BROM
>
>  source "arch/arm/mach-rockchip/rk3036/Kconfig"
> +source "arch/arm/mach-rockchip/rk3066/Kconfig"
>  source "arch/arm/mach-rockchip/rk3188/Kconfig"
>  source "arch/arm/mach-rockchip/rk3288/Kconfig"
>  source "arch/arm/mach-rockchip/rk3328/Kconfig"
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 327b267..1ebba0c 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -7,15 +7,18 @@
>  obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
>
>  ifdef CONFIG_TPL_BUILD
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-tpl.o
>  obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
>  obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
>  else ifdef CONFIG_SPL_BUILD
>  obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-spl.o
>  obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
>  obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
>  obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
>  obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
>  else
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board.o
>  obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
>  obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
>  obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
> @@ -29,6 +32,7 @@ ifndef CONFIG_TPL_BUILD
>  obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
>  endif
>
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/
>  obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
>  obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
>  obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
> diff --git a/arch/arm/mach-rockchip/rk3066-board-spl.c 
> b/arch/arm/mach-rockchip/rk3066-board-spl.c
> new file mode 100644
> index 000..6f7bfb0
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066-board-spl.c
> @@ -0,0 +1,173 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 

That should go below spi.h

> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +u32 spl_boot_device(void)
> +{

This function seems to be common. Can you please (in a separate patch)
move it into a separate shared file and delete all the copies?

> +#if 

Re: [U-Boot] [PATCH 1/1] tools: conditionally disable python libfdt wrapper

[Simon Glass]

Hi Matt,

On 8 May 2017 at 10:38, Simon Glass  wrote:
> Hi Matt,
>
> On 1 May 2017 at 21:43, Matt Weber  wrote:
>> Not all host systems want the default swig to be
>> used when building the tools.  Allow for the
>> disabling of the wrapper to enable cross-compiling
>> of the tools on a host system with swig.
>>
>> Signed-off-by: Matthew Weber 
>> ---
>>
>> I'm open for suggestions on what updates to make to
>> enable the wrapper building to use prefix/destdir that
>> point python/swig in the right place to the sysroot/host
>> tools/libs for building of the tools.
>>
>> Example build failure when buildroot is trying to build
>> target/host uboot-tools and the host systems OS is detecting swig.
>> The intention would be the buildroot built host python/swig
>> should be used for the detect and as the tools assisting in the
>> build.
>> http://autobuild.buildroot.net/results/6d5/6d52ac8bb71012aea6fc4c679691b31a3366728b/build-end.log
>> ---
>>  tools/Makefile | 2 ++
>>  1 file changed, 2 insertions(+)
>
> Can you please take a look at u-boot-fdt/next ?
>
> That branch has the new approach for this feature. Can you try to get
> your path running on that branch and send v2?

This work is now in mainline. What do you think? Do you still need this patch?

Regards,
Simon
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Re: [U-Boot] [PATCH] rockchip: clk: rk3036: correct setting for pll integer mode

[Simon Glass]

On 6 June 2017 at 03:48, Kever Yang  wrote:
> According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
> interger mode, while the '0' means the frac mode.

Should that be 'integer' ?

>
> Signed-off-by: Kever Yang 
> ---
>
>  drivers/clk/rockchip/clk_rk3036.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Simon Glass 

>
> diff --git a/drivers/clk/rockchip/clk_rk3036.c 
> b/drivers/clk/rockchip/clk_rk3036.c
> index d866d0b..8fefa19 100644
> --- a/drivers/clk/rockchip/clk_rk3036.c
> +++ b/drivers/clk/rockchip/clk_rk3036.c
> @@ -62,7 +62,7 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum 
> rk_clk_id clk_id,
>output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
>
> /* use interger mode */

and here too

> -   rk_clrreg(>con1, 1 << PLL_DSMPD_SHIFT);
> +   rk_setreg(>con1, 1 << PLL_DSMPD_SHIFT);
>
> rk_clrsetreg(>con0,
>  PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
> --
> 1.9.1
>
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Re: [U-Boot] U-Boot for Intel 64bit Linux kernel?

[Simon Glass]

+Bin

Hi Paul,

On 6 June 2017 at 08:53, Paul Knopf  wrote:
> Does U-Boot support booting an Intel 64bit Linux kernel?
>

Yes, in various ways. See for example x86-fit-boot.txt (and README.x86).


> The bootloader itself doesn't need to be 64bit, but it needs (for me) to
> boot a 64bit kernel with the full memory address space available.

U-Boot normally runs in 32-bit mode on x86. There is experimental
64-bit x86 support (see chromebook_link64), but it is not ready for
use, unless you want to improve it :-)

>
> What about UEFI?

Yes, it supports booting as a UEFI payload. It also can run an an EFI
app (really just for debugging). It can also run EFI apps. See
README.efi

Regards,
Simon
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Re: [U-Boot] [PATCH 02/13] rockchip: rk3066: add rk3066 pinctrl driver

[Simon Glass]

On 6 June 2017 at 12:49, Paweł Jarosz  wrote:
> Add driver supporting pin multiplexing on rk3066 platform.
>
> Signed-off-by: Paweł Jarosz 
> ---
>  drivers/pinctrl/Kconfig   |   9 +
>  drivers/pinctrl/rockchip/Makefile |   1 +
>  drivers/pinctrl/rockchip/pinctrl_rk3066.c | 342 
> ++
>  3 files changed, 352 insertions(+)
>  create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3066.c

Can you please update the masks here as per the previous comment on grf?

Otherwise looks good.
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Re: [U-Boot] [PATCH 1/2] rockchip: video: rk_hdmi: fix implicit definition warnings

[Simon Glass]

On 6 June 2017 at 01:15, Philipp Tomsich
 wrote:
> When enabling CONFIG_DISPLAY_ROCKCHIP_HDMI, compile-time warning for
> the following implicitly defined functions are raised due to a missing
> include directive:
>
>   drivers/video/rockchip/rk_hdmi.c: In function 'rk_hdmi_probe':
>   drivers/video/rockchip/rk_hdmi.c:150:2: warning: implicit declaration of 
> function 'rk_setreg' [-Wimplicit-function-declaration]
> rk_setreg(>grf->soc_con6, 1 << 15);
> ^
>   drivers/video/rockchip/rk_hdmi.c:153:2: warning: implicit declaration of 
> function 'rk_clrsetreg' [-Wimplicit-function-declaration]
> rk_clrsetreg(>grf->soc_con6, 1 << 4,
> ^~~~
>
> This change fixes this by including  in rk_hdmi.c.
>
> Signed-off-by: Philipp Tomsich 
>
> ---
>
> Changes in v3:
> - adds an include-directive to the (pre-RK3399 enabled) rk_hdmi to
>   fix implicit definition warnings
>
> Changes in v2: None
>
>  drivers/video/rockchip/rk_hdmi.c | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 03/13] rockchip: rk3066: add sysreset driver

[Simon Glass]

On 6 June 2017 at 12:49, Paweł Jarosz  wrote:
> Add support for system reset for rk3066 socs.
>
> Signed-off-by: Paweł Jarosz 
> ---
>  drivers/sysreset/Makefile  |  1 +
>  drivers/sysreset/sysreset_rk3066.c | 62 
> ++
>  2 files changed, 63 insertions(+)
>  create mode 100644 drivers/sysreset/sysreset_rk3066.c
>

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v2 2/7] rockchip: pinctrl: rv1108: access of-offset via dev_of_offset(...)

[Simon Glass]

Hi,

On 6 June 2017 at 07:42, Philipp Tomsich
 wrote:
> After rebasing to u-boot-rockchip/master@2b19b2f, buildman fails for
> rv1108 with:
>   ../drivers/pinctrl/rockchip/pinctrl_rv1108.c: In function 
> 'rv1108_pinctrl_get_periph_id':
>   ../drivers/pinctrl/rockchip/pinctrl_rv1108.c:111:49: error: 'struct 
> udevice' has no member named 'of_offset'
> ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
>  ^
>
> This change access the of-offset of periph via the dev_of_offset()
> helper-function to fix this issue and (hopefully) to ensure it doesn't
> recur if there's more changes to the DM subsystem.
>
> Signed-off-by: Philipp Tomsich 
>
> ---
>
> Changes in v2:
> - (new patch) access of-offset of periph via dev_of_offset in the RV1108
>   pinctrl driver to fix a buildman failure for u-boot-rockchip/master@2b19b2f
>
>  drivers/pinctrl/rockchip/pinctrl_rv1108.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/rockchip/pinctrl_rv1108.c 
> b/drivers/pinctrl/rockchip/pinctrl_rv1108.c
> index d98ec81..bdf3910 100644
> --- a/drivers/pinctrl/rockchip/pinctrl_rv1108.c
> +++ b/drivers/pinctrl/rockchip/pinctrl_rv1108.c
> @@ -108,7 +108,7 @@ static int rv1108_pinctrl_get_periph_id(struct udevice 
> *dev,
> u32 cell[3];
> int ret;
>
> -   ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
> +   ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
>"interrupts", cell, ARRAY_SIZE(cell));

Could you use dev_read_u32_array() here instead? That is the new new
way :-) I added the dev_of_offset() as a transition mechanism but it
should not be used ideally.

> if (ret < 0)
> return -EINVAL;
> --
> 2.1.4
>

Regards,
Simon
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Re: [U-Boot] [PATCH 10/13] rockchip: rk3066: add sdram driver

[Simon Glass]

On 6 June 2017 at 12:52, Paweł Jarosz  wrote:

Commit message?

> Signed-off-by: Paweł Jarosz 
> ---
>  arch/arm/mach-rockchip/rk3066/Makefile   |   1 +
>  arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 
> +++
>  2 files changed, 112 insertions(+)
>  create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
>

Acked-by: Simon Glass 

> diff --git a/arch/arm/mach-rockchip/rk3066/Makefile 
> b/arch/arm/mach-rockchip/rk3066/Makefile
> index 4cf5df2..1d38518 100644
> --- a/arch/arm/mach-rockchip/rk3066/Makefile
> +++ b/arch/arm/mach-rockchip/rk3066/Makefile
> @@ -6,6 +6,7 @@
>
>  ifndef CONFIG_TPL_BUILD
>  obj-y += clk_rk3066.o
> +obj-y += sdram_rk3066.o
>  obj-y += syscon_rk3066.o
>  else
>  obj-y += sdram_init.o
> diff --git a/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c 
> b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
> new file mode 100644
> index 000..a713ac4
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
> @@ -0,0 +1,111 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + * Copyright 2014 Rockchip Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + *
> + * Adapted from the very similar rk3288 ddr init.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct dram_info {
> +   struct ram_info info;
> +   struct rk3188_pmu *pmu;
> +};
> +
> +size_t sdram_size_mb(struct rk3188_pmu *pmu)

I wonder if most of this could go in a common function, or are the
registers / offsets different?

> +{
> +   u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
> +   size_t chipsize_mb = 0;
> +   size_t size_mb = 0;
> +   u32 ch;
> +   u32 sys_reg = readl(>sys_reg[2]);
> +   u32 chans;
> +
> +   chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
> +
> +   for (ch = 0; ch < chans; ch++) {
> +   rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
> +   SYS_REG_RANK_MASK);
> +   col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & 
> SYS_REG_COL_MASK);
> +   bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & 
> SYS_REG_BK_MASK);
> +   cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
> +   SYS_REG_CS0_ROW_MASK);
> +   cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
> +   SYS_REG_CS1_ROW_MASK);
> +   bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
> +   SYS_REG_BW_MASK));
> +   row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
> +   SYS_REG_ROW_3_4_MASK;
> +   chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
> +
> +   if (rank > 1)
> +   chipsize_mb += chipsize_mb >>
> +   (cs0_row - cs1_row);
> +   if (row_3_4)
> +   chipsize_mb = chipsize_mb * 3 / 4;
> +   size_mb += chipsize_mb;
> +   }
> +
> +   /* there can be no more than 2gb of memory */
> +   size_mb = min(size_mb, 0x8000 >> 20);
> +
> +   return size_mb;
> +}
> +
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Re: [U-Boot] [PATCH 3/7] serial: mxc: Move cr1 and cr2 write to mxc_serial_setbrg

[Simon Glass]

On 5 June 2017 at 23:31, Jagan Teki  wrote:
> From: Jagan Teki 
>
> Control reg write should be part of setbrg for better
> buadrate generation, so move cr1 and cr2 write to
> mxc_serial_setbrg
>
> Signed-off-by: Jagan Teki 
> ---
>  drivers/serial/serial_mxc.c | 8 +++-
>  1 file changed, 3 insertions(+), 5 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 01/13] rockchip: rk3066: add grf header file

[Simon Glass]

Hi Pawel,

On 6 June 2017 at 12:48, Paweł Jarosz  wrote:
> grf is needed by various drivers for rk3066 soc.
>
> Signed-off-by: Paweł Jarosz 
> ---
>  arch/arm/include/asm/arch-rockchip/grf_rk3066.h | 621 
> 
>  1 file changed, 621 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3066.h
>
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3066.h 
> b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
> new file mode 100644
> index 000..96b4ca6
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
> @@ -0,0 +1,621 @@
> +/*
> + * Copyright (c) 2017 Paweł Jarosz 
> + *
> + * SPDX-License-Identifier:GPL-2.0
> + */
> +
> +#ifndef _ASM_ARCH_GRF_RK3066_H
> +#define _ASM_ARCH_GRF_RK3066_H
> +
> +struct rk3066_grf_gpio_lh {
> +   u32 l;
> +   u32 h;
> +};
> +
> +struct rk3066_grf {
> +   struct rk3066_grf_gpio_lh gpio_dir[7];
> +   struct rk3066_grf_gpio_lh gpio_do[7];
> +   struct rk3066_grf_gpio_lh gpio_en[7];
> +
> +   u32 gpio0a_iomux;
> +   u32 gpio0b_iomux;
> +   u32 gpio0c_iomux;
> +   u32 gpio0d_iomux;
> +
> +   u32 gpio1a_iomux;
> +   u32 gpio1b_iomux;
> +   u32 gpio1c_iomux;
> +   u32 gpio1d_iomux;
> +
> +   u32 gpio2a_iomux;
> +   u32 gpio2b_iomux;
> +   u32 gpio2c_iomux;
> +   u32 gpio2d_iomux;
> +
> +   u32 gpio3a_iomux;
> +   u32 gpio3b_iomux;
> +   u32 gpio3c_iomux;
> +   u32 gpio3d_iomux;
> +
> +   u32 gpio4a_iomux;
> +   u32 gpio4b_iomux;
> +   u32 gpio4c_iomux;
> +   u32 gpio4d_iomux;
> +
> +   u32 reserved0[5];
> +
> +   u32 gpio6b_iomux;
> +
> +   u32 reserved1[2];
> +
> +   struct rk3066_grf_gpio_lh gpio_pull[7];
> +
> +   u32 soc_con0;
> +   u32 soc_con1;
> +   u32 soc_con2;
> +
> +   u32 soc_status0;
> +
> +   u32 dmac1_con[3];
> +   u32 dmac2_con[4];
> +
> +   u32 uoc0_con[3];
> +   u32 uoc1_con[4];
> +   u32 ddrc_con;
> +   u32 ddrc_stat;
> +
> +   u32 reserved2[10];
> +
> +   u32 os_reg[4];
> +};
> +check_member(rk3066_grf, os_reg[3], 0x01d4);
> +
> +/* GRF_GPIO0A_IOMUX */
> +enum {
> +   GPIO0A6_SHIFT   = 12,
> +   GPIO0A6_MASK= 1,

Can you please use shifted masks for these values?

   GPIO0A6_MASK= 1 << GPIO0A6_SHIFT,

> +   GPIO0A6_GPIO= 0,
> +   GPIO0A6_HOST_DRV_VBUS,
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Re: [U-Boot] [PATCH 2/2] rockchip: defconfig: puma-rk3399: update defconfig with video-support

[Simon Glass]

On 6 June 2017 at 01:15, Philipp Tomsich
 wrote:
> With HDMI output for the RK3399 working, this update the RK3399-Q7
> (Puma) defconfig for the new functionality:
> 1. enables PMIC command (to check if the HDMI voltages are correct)
>   +CONFIG_CMD_PMIC=y
>   +CONFIG_CMD_REGULATOR=y
> 2. enables video-output (via HDMI)
>   +CONFIG_DM_VIDEO=y
>   +CONFIG_DISPLAY=y
>   +CONFIG_VIDEO_ROCKCHIP=y
>   +CONFIG_DISPLAY_ROCKCHIP_HDMI=y
> 3. turns on the 'dcache'-command (for a dcache flush) for our QA to
>fill the framebuffer using 'mw.l'
>   +CONFIG_CMD_CACHE=y
> 4. turns on the 'bmp'-command
>   +CONFIG_CMD_BMP=y
>
> Signed-off-by: Philipp Tomsich 
> Reviewed-by: Simon Glass 
>
> ---
>
> Changes in v3: None
> Changes in v2:
> - enable CMD_BMP in the puma-rk3399_defconfig (following a rebase to
>   the upstream master after CMD_BMP was migrate to Kconfig)
>
>  configs/puma-rk3399_defconfig | 8 
>  1 file changed, 8 insertions(+)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH v2 2/3] rockchip: dts: rk3399-puma: add DTS for the DDR3-1333 timing

[Simon Glass]

On 6 June 2017 at 12:44, Philipp Tomsich
 wrote:
> This adds the DDR3-1333 timing via its own DTS and wires it up.  This
> is not the default timing for the RK3399-Q7 and should be selected
> explicitly via the config (CONFIG_DEFAULT_DEVICE_TREE).
>
> Signed-off-by: Philipp Tomsich 
>
> ---
>
> Changes in v2:
> - added rk3399-puma-ddr1333 for DDR3-1333 timing (replacing the #ifdef
>   implementation)
>
>  arch/arm/dts/Makefile|  1 +
>  arch/arm/dts/rk3399-puma-ddr1333.dts | 11 +++
>  2 files changed, 12 insertions(+)
>  create mode 100644 arch/arm/dts/rk3399-puma-ddr1333.dts

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH v2 1/7] rockchip: clk: rv1108: rename dev_get_addr

[Simon Glass]

On 6 June 2017 at 07:42, Philipp Tomsich
 wrote:
> After rebasing to u-boot-rockchip/master@2b19b2f, buildman fails for
> rv1108 with:
>   ../drivers/clk/rockchip/clk_rv1108.c: In function 'rv1108_clk_probe':
>   ../drivers/clk/rockchip/clk_rv1108.c:191:22: warning: implicit declaration 
> of function 'dev_get_addr' [-Wimplicit-function-declaration]
> priv->cru = (struct rv1108_cru *)dev_get_addr(dev);
>
> This change tracks the dev_get_addr rename, which didn't make it into
> the rv1108 clk driver.
>
> Signed-off-by: Philipp Tomsich 
>
> ---
>
> Changes in v2:
> - (new patch) rename dev_get_addr in the RV1108 clk-driver to fix a
>   buildman failure for u-boot-rockchip/master@2b19b2f
>
>  drivers/clk/rockchip/clk_rv1108.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 6/7] serial: mxc: Code cleanup

[Simon Glass]

On 5 June 2017 at 23:31, Jagan Teki  wrote:
> From: Jagan Teki 
>
> - Remove space between #define to macro
> - Add tab between macro and value
>
> Signed-off-by: Jagan Teki 
> ---
>  drivers/serial/serial_mxc.c | 191 
> ++--
>  1 file changed, 94 insertions(+), 97 deletions(-)
>

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 05/13] rockchip: rk3066: add rk3066 platform devicetree file

[Simon Glass]

Hi Pawel,

On 6 June 2017 at 12:50, Paweł Jarosz  wrote:
> rk3066 peripherials include usb, i2c, pwm, gpio, sdio, sdmmc, emmc, spi,
> watchdog and uart
>
> Signed-off-by: Paweł Jarosz 
> ---
>  arch/arm/dts/rk3066a.dtsi | 699 
> ++
>  1 file changed, 699 insertions(+)
>  create mode 100644 arch/arm/dts/rk3066a.dtsi

How come this file has 'a' on the end?

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v2 1/3] rockchip: dts: rk3399-puma: refactor and rename (default) DDR3-1600 DTS

[Simon Glass]

On 6 June 2017 at 12:44, Philipp Tomsich
 wrote:
> To better support different RAM timings (DDR3-1333 and DDR3-1866 are
> assembly options for the RK3399-Q7), this refactors the DTS support
> and renames the default DTS variant from rk3399-puma to
> rk3399-puma-ddr1600:
> - changes the rk3399-puma DTS into a board-specific DTSI by removing
>   the inclusion of the DRAM timings
> - adds a new rk3399-puma-ddr1600.dts, which includes the (new) common
>   board DTSI and the DDR3-1600 timing DTSI
> - wires this up from arch/arm/dts/Makefile and configs/puma-rk3399_defconfig
>
> Signed-off-by: Philipp Tomsich 
>
> ---
>
> Changes in v2:
> - changed implementation from Kconfig and C preprocessor macros in the
>   DTS to using one DTS per DRAM timing that contains only two includes:
>   one for the common board-level definitions and one for the DRAM
>   timings
>
>  arch/arm/dts/Makefile  |  2 +-
>  arch/arm/dts/rk3399-puma-ddr1600.dts   | 11 +++
>  arch/arm/dts/{rk3399-puma.dts => rk3399-puma.dtsi} |  2 --
>  configs/puma-rk3399_defconfig  |  2 +-
>  4 files changed, 13 insertions(+), 4 deletions(-)
>  create mode 100644 arch/arm/dts/rk3399-puma-ddr1600.dts
>  rename arch/arm/dts/{rk3399-puma.dts => rk3399-puma.dtsi} (98%)
>

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH v2 3/3] rockchip: dts: rk3399-puma: add DTS for the DDR3-1866 timing

[Simon Glass]

On 6 June 2017 at 12:44, Philipp Tomsich
 wrote:
> This adds the DDR3-1866 timing via its own DTS and wires it up.  This
> (currently) is not the default timing for the RK3399-Q7 and should be
> selected explicitly via the config (CONFIG_DEFAULT_DEVICE_TREE).
>
> Signed-off-by: Philipp Tomsich 
>
> ---
>
> Changes in v2:
> - added rk3399-puma-ddr1866 DTS file for the DDR3-1866 implementation
>   (replacing the #ifdef implementation)
>
>  arch/arm/dts/Makefile|  1 +
>  arch/arm/dts/rk3399-puma-ddr1866.dts | 11 +++
>  2 files changed, 12 insertions(+)
>  create mode 100644 arch/arm/dts/rk3399-puma-ddr1866.dts
>

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 04/13] rockchip: rk3066: add clock driver for rk3066 soc

[Simon Glass]

On 6 June 2017 at 12:50, Paweł Jarosz  wrote:
> Add clock driver for rk3066 platform.
>
> Signed-off-by: Paweł Jarosz 
> ---
>  arch/arm/include/asm/arch-rockchip/cru_rk3066.h | 189 
>  drivers/clk/rockchip/Makefile   |   1 +
>  drivers/clk/rockchip/clk_rk3066.c   | 586 
> 
>  3 files changed, 776 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3066.h
>  create mode 100644 drivers/clk/rockchip/clk_rk3066.c

Again please can you update the masks?
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