date:20171210

Re: [U-Boot] [PATCH v5 00/11] mmc: fixes for HS200/UHS core support

2017-12-10 Thread Jaehoon Chung

Hi JJ,

On 12/01/2017 01:43 AM, Jean-Jacques Hiblot wrote:
> This series applies on top of "[PATCH v2 00/26] mmc: Add support for HS200
> and UHS modes"
> 
> It fixes a bug with old SD and MMC cards that support only the legacy mode.
> This series also adresses the problem of increased code size that broke some
> platform (openrd and omapl138_lcdk) by making more things optional.
> 
> It also addresses other comments made on the mailing list:
> * dump card and host capabilities in debug mode
> * use 1-bit if the DTS property 'bus-width' is not present.
> * recognize the "mmc-ddr-1_2v" and "mmc-hs200-1_2v" DTS properties
> * convert mmc_of_parse to livetree
> 

Applied to u-boot-mmc. Sorry for late. Thanks!

Best Regards,
Jaehoon Chung

>   
> Tested on DRA72
> 
> changes since v4:
> * use pr_warn() and pr_error() instead of custom macro to output log messages
> * add a new patch to lower the LOGLEVEL for the platform omapl138_lcdk
> * Fix typo in patch 'mmc: make optional the support for eMMC hardware
>   partitioning'
> 
> changes since v3:
> * Make UHS support optional. Disabled by default
> * Make HS200 support optional. Disabled by default
> * Make eMMC Hardware Partitioning optional. Enabled by default
> * Display most of the error messages only if MMC_VERBOSE is set (it's set by 
> default)
> 
> changes since v2:
> * use the device-oriented helpers like dev_read_u32_default() instead of using
>   the livetree API
> * Dump the host and card capabilities only in when debug is enabled. Also dump
>   the capabilities when 'mmc info' is executed if the verbose option is 
> enabled
> 
> changes since v1:
> * convert mmc_of_parse to livetree
> * squashed all changes to mmc_of_parse in a single patch
> 
> Jean-Jacques Hiblot (11):
>   mmc: dump card and host capabilities if debug is enabled
>   dm: mmc: update mmc_of_parse()
>   mmc: Fixed a problem with old sd or mmc that do not support High speed
>   mmc: all hosts support 1-bit bus width and legacy timings
>   mmc: fix for old MMCs (below version 4)
>   mmc: don't use malloc_cache_aligned()
>   mmc: convert most of printf() to pr_err() and pr_warn()
>   mmc: make UHS and HS200 optional
>   mmc: make optional the support for eMMC hardware partitioning
>   configs: openrd: removed support for eMMC hardware partitioning
>   configs: omapl138_lcdk: decrease the loglevel to reduce the size of
> the SPL
> 
>  cmd/mmc.c |   8 ++
>  configs/omapl138_lcdk_defconfig   |   1 +
>  configs/openrd_base_defconfig |   1 +
>  configs/openrd_client_defconfig   |   1 +
>  configs/openrd_ultimate_defconfig |   1 +
>  drivers/mmc/Kconfig   |  58 --
>  drivers/mmc/mmc-uclass.c  |  40 ++
>  drivers/mmc/mmc.c | 162 
> +-
>  include/mmc.h |  38 +++--
>  9 files changed, 246 insertions(+), 64 deletions(-)
> 

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[U-Boot] [RFC 3/5] sf: parse Serial Flash Discoverable Parameters (SFDP) tables

2017-12-10 Thread Prabhakar Kushwaha

This patch adds support to the JESD216 rev B standard and parses the
SFDP tables to dynamically initialize the 'struct spi_nor_flash_parameter'.

It has been ported from Linux commit "mtd: spi-nor: parse Serial Flash
Discoverable Parameters (SFDP) tables". It Also ports all modifications
done on top of the mentioned commit.

Signed-off-by: Prabhakar Kushwaha 
CC: Cyrille Pitchen 
CC: Marek Vasut 
---
 drivers/mtd/spi/sf_internal.h | 204 ++
 drivers/mtd/spi/spi_flash.c   | 389 ++
 2 files changed, 593 insertions(+)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 164b0ea..73fe207 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -12,6 +12,7 @@
 
 #include 
 #include 
+#include 
 
 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */
 enum spi_dual_flash {
@@ -82,6 +83,7 @@ enum spi_nor_option_flags {
 #define CMD_FLAG_STATUS0x70
 #define CMD_EN4B   0xB7
 #define CMD_EX4B   0xE9
+#define CMD_READ_SFDP  0x5a
 
 /* Bank addr access commands */
 #ifdef CONFIG_SPI_FLASH_BAR
@@ -155,9 +157,211 @@ struct spi_flash_info {
 * Use dedicated 4byte address op codes
 * to support memory size above 128Mib.
 */
+#define FLASH_SFDP BIT(9)   /* Parse SFDP tables */
 #define RD_FULL(RD_QUAD | RD_DUAL | RD_QUADIO | 
RD_DUALIO)
 };
 
+struct sfdp_parameter_header {
+   u8  id_lsb;
+   u8  minor;
+   u8  major;
+   u8  length; /* in double words */
+   u8  parameter_table_pointer[3]; /* byte address */
+   u8  id_msb;
+};
+
+#define SFDP_PARAM_HEADER_ID(p)(((p)->id_msb << 8) | (p)->id_lsb)
+#define SFDP_PARAM_HEADER_PTP(p) \
+   (((p)->parameter_table_pointer[2] << 16) | \
+((p)->parameter_table_pointer[1] <<  8) | \
+((p)->parameter_table_pointer[0] <<  0))
+
+#define SFDP_BFPT_ID   0xff00  /* Basic Flash Parameter Table */
+#define SFDP_SECTOR_MAP_ID 0xff81  /* Sector Map Table */
+
+#define SFDP_SIGNATURE 0x50444653U
+#define SFDP_JESD216_MAJOR 1
+#define SFDP_JESD216_MINOR 0
+#define SFDP_JESD216A_MINOR5
+#define SFDP_JESD216B_MINOR6
+
+struct sfdp_header {
+   u32 signature; /* Ox50444653U <=> "SFDP" */
+   u8  minor;
+   u8  major;
+   u8  nph; /* 0-base number of parameter headers */
+   u8  unused;
+
+   /* Basic Flash Parameter Table. */
+   struct sfdp_parameter_headerbfpt_header;
+};
+
+/* Basic Flash Parameter Table */
+
+/*
+ * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
+ * They are indexed from 1 but C arrays are indexed from 0.
+ */
+#define BFPT_DWORD(i)  ((i) - 1)
+#define BFPT_DWORD_MAX 16
+
+/* The first version of JESB216 defined only 9 DWORDs. */
+#define BFPT_DWORD_MAX_JESD216 9
+
+/* 1st DWORD. */
+#define BFPT_DWORD1_FAST_READ_1_1_2BIT(16)
+#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
+#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY   (0x0UL << 17)
+#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4   (0x1UL << 17)
+#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY   (0x2UL << 17)
+#define BFPT_DWORD1_DTRBIT(19)
+#define BFPT_DWORD1_FAST_READ_1_2_2BIT(20)
+#define BFPT_DWORD1_FAST_READ_1_4_4BIT(21)
+#define BFPT_DWORD1_FAST_READ_1_1_4BIT(22)
+
+/* 5th DWORD. */
+#define BFPT_DWORD5_FAST_READ_2_2_2BIT(0)
+#define BFPT_DWORD5_FAST_READ_4_4_4BIT(4)
+
+/* 11th DWORD. */
+#define BFPT_DWORD11_PAGE_SIZE_SHIFT   4
+#define BFPT_DWORD11_PAGE_SIZE_MASKGENMASK(7, 4)
+
+/* 15th DWORD. */
+
+/*
+ * (from JESD216 rev B)
+ * Quad Enable Requirements (QER):
+ * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
+ * reads based on instruction. DQ3/HOLD# functions are hold during
+ * instruction phase.
+ * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
+ * two data bytes where bit 1 of the second byte is one.
+ * [...]
+ * Writing only one byte to the status register has the side-effect of
+ * clearing status register 2, including the QE bit. The 100b code is
+ * used if writing one byte to the status register does not modify
+ * status register 2.
+ * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
+ * one data byte where bit 6 is one.
+ * [...]
+ * - 011b: QE is bit 7 of status register 2. It is set via Write

[U-Boot] [RFC 5/5] sf: fsl_quadspi: Configue LUT based on padding information

2017-12-10 Thread Prabhakar Kushwaha

Padding or number of line required for instruction, address and data
is pre-defined as per the selected read commond.

Configure LUT based on the selected read command under flag
SPI_XFER_BEGIN.

Signed-off-by: Prabhakar Kushwaha 
---
 drivers/spi/fsl_qspi.c | 55 --
 1 file changed, 53 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 7ec222a..bdaec44 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -52,7 +52,12 @@ DECLARE_GLOBAL_DATA_PTR;
 #define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */
 #define QSPI_CMD_RDSR  0x05/* Read status register */
 #define QSPI_CMD_WREN  0x06/* Write enable */
+#define QSPI_CMD_SLOW_READ 0x03/* Read data bytes (low frequency) */
 #define QSPI_CMD_FAST_READ 0x0b/* Read data bytes (high frequency) */
+#define QSPI_CMD_DUAL_OUTPUT_FAST_READ 0x3b
+#define QSPI_CMD_DUAL_IO_FAST_READ 0xbb
+#define QSPI_CMD_QUAD_OUTPUT_FAST_READ 0x6b
+#define QSPI_CMD_QUAD_IO_FAST_READ 0xeb
 #define QSPI_CMD_BE_4K 0x20/* 4K erase */
 #define QSPI_CMD_CHIP_ERASE0xc7/* Erase whole flash chip */
 #define QSPI_CMD_SE0xd8/* Sector erase (usually 64KiB) */
@@ -71,7 +76,12 @@ DECLARE_GLOBAL_DATA_PTR;
 #define QSPI_CMD_WRAR  0x71/* Write any device register */
 
 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
-#define QSPI_CMD_FAST_READ_4B  0x0c/* Read data bytes (high frequency) */
+#define QSPI_CMD_SLOW_READ_4B  0x13
+#define QSPI_CMD_FAST_READ_4B  0x0c
+#define QSPI_CMD_DUAL_OUTPUT_FAST_READ_4B  0x3c
+#define QSPI_CMD_DUAL_IO_FAST_READ_4B  0xbc
+#define QSPI_CMD_QUAD_OUTPUT_FAST_READ_4B  0x6c
+#define QSPI_CMD_QUAD_IO_FAST_READ_4B  0xec
 #define QSPI_CMD_PP_4B 0x12/* Page program (up to 256 bytes) */
 #define QSPI_CMD_SE_4B 0xdc/* Sector erase (usually 64KiB) */
 
@@ -762,10 +772,51 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int 
bitlen,
 {
u32 bytes = DIV_ROUND_UP(bitlen, 8);
static u32 wr_sfaddr;
-   u32 txbuf;
+   u32 txbuf, mode = priv->mode;
 
WATCHDOG_RESET();
 
+   if (dout && (flags & SPI_XFER_BEGIN)) {
+   switch (*(u8 *)dout) {
+   case QSPI_CMD_SLOW_READ:
+   case QSPI_CMD_SLOW_READ_4B:
+   case QSPI_CMD_FAST_READ:
+   case QSPI_CMD_FAST_READ_4B:
+   case QSPI_CMD_PP:
+   case QSPI_CMD_PP_4B:
+   /* TODO: 1_1_1 Padding */
+   break;
+
+   case QSPI_CMD_DUAL_OUTPUT_FAST_READ:
+   case QSPI_CMD_DUAL_OUTPUT_FAST_READ_4B:
+   if (mode & SPI_RX_DUAL) {
+   /* TODO: 1_1_2 Padding */
+   }
+   break;
+
+   case QSPI_CMD_DUAL_IO_FAST_READ:
+   case QSPI_CMD_DUAL_IO_FAST_READ_4B:
+   if (mode & SPI_RX_DUAL) {
+   /* TODO: 1_2_2 Padding */
+   }
+   break;
+
+   case QSPI_CMD_QUAD_OUTPUT_FAST_READ:
+   case QSPI_CMD_QUAD_OUTPUT_FAST_READ_4B:
+   if (mode & SPI_RX_QUAD) {
+   /* TODO: 1_1_4 Padding */
+   }
+   break;
+
+   case QSPI_CMD_QUAD_IO_FAST_READ:
+   case QSPI_CMD_QUAD_IO_FAST_READ_4B:
+   if (mode & SPI_RX_QUAD) {
+   /* TODO: 1_4_4 Padding */
+   }
+   break;
+   }
+   }
+
if (dout) {
if (flags & SPI_XFER_BEGIN) {
priv->cur_seqid = *(u8 *)dout;
-- 
2.7.4

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[U-Boot] [RFC 4/5] sf: fsl_qspi: Add support of fsl_qspi_set_mode

2017-12-10 Thread Prabhakar Kushwaha

SPI bus provide support dual and quad wire data transfers for tx and
rx. This information is parsed from device tree and passed to slave
device via set_mode of dm_spi_ops.

Implement set_mode i.e. fsl_qspi_set_mode to store mode information
in fsl_qspi_priv structure.

Signed-off-by: Prabhakar Kushwaha 
---
 drivers/spi/fsl_qspi.c | 30 +-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 0f3f7d9..7ec222a 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -120,6 +120,7 @@ struct fsl_qspi_platdata {
  * @cur_amba_base: Base address of QSPI memory mapping of current CS
  * @flash_num: Number of active slave devices
  * @num_chipselect: Number of QSPI chipselect signals
+ * @mode: I/O lines
  * @regs: Point to QSPI register structure for I/O access
  */
 struct fsl_qspi_priv {
@@ -133,6 +134,7 @@ struct fsl_qspi_priv {
u32 cur_amba_base;
u32 flash_num;
u32 num_chipselect;
+   u32 mode;
struct fsl_qspi_regs *regs;
 };
 
@@ -1212,7 +1214,33 @@ static int fsl_qspi_set_speed(struct udevice *bus, uint 
speed)
 
 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
 {
-   /* Nothing to do */
+   struct fsl_qspi_priv *priv = dev_get_priv(bus);
+
+   if (mode & SPI_RX_QUAD)
+   priv->mode |= SPI_RX_QUAD;
+   else if (mode & SPI_RX_DUAL)
+   priv->mode |= SPI_RX_DUAL;
+   else
+   priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL);
+
+   priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL);
+
+   debug("%s:  mode=%d rx: ", __func__, mode);
+
+   if (mode & SPI_RX_QUAD)
+   debug("quad, tx: ");
+   else if (mode & SPI_RX_DUAL)
+   debug("dual, tx: ");
+   else
+   debug("single, tx: ");
+
+   if (mode & SPI_TX_QUAD)
+   debug("quad\n");
+   else if (mode & SPI_TX_DUAL)
+   debug("dual\n");
+   else
+   debug("single\n");
+
return 0;
 }
 
-- 
2.7.4

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[U-Boot] [RFC 2/5] sf: add method to support memory size above 128Mib

2017-12-10 Thread Prabhakar Kushwaha

This patch add support of memories with size above 128Mib. It has
been ported from Linux commit "mtd: spi-nor: add a
stateless method to support memory size above 128Mib".

It convert 3byte opcode into 4byte opcode based upon
OPCODES_4B or Spansion flash. Also the commands are malloc'ed
at run time based on 3byte or 4byte address opcode requirement.

Signed-off-by: Prabhakar Kushwaha 
CC: Cyrille Pitchen 
CC: Marek Vasut 
CC: Vignesh R 
---
depends upon https://patchwork.ozlabs.org/patch/826919/

 drivers/mtd/spi/sf_internal.h |  28 -
 drivers/mtd/spi/spi_flash.c   | 136 --
 include/spi_flash.h   |   2 +
 3 files changed, 146 insertions(+), 20 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 06dee0a..164b0ea 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -27,7 +27,8 @@ enum spi_nor_option_flags {
 };
 
 #define SPI_FLASH_3B_ADDR_LEN  3
-#define SPI_FLASH_CMD_LEN  (1 + SPI_FLASH_3B_ADDR_LEN)
+#define SPI_FLASH_4B_ADDR_LEN  4
+#define SPI_FLASH_MAX_ADDR_WIDTH   4
 #define SPI_FLASH_16MB_BOUN0x100
 
 /* CFI Manufacture ID's */
@@ -57,13 +58,30 @@ enum spi_nor_option_flags {
 #define CMD_READ_DUAL_IO_FAST  0xbb
 #define CMD_READ_QUAD_OUTPUT_FAST  0x6b
 #define CMD_READ_QUAD_IO_FAST  0xeb
+
+/* 4B READ commands */
+#define CMD_READ_ARRAY_SLOW_4B 0x13
+#define CMD_READ_ARRAY_FAST_4B 0x0c
+#define CMD_READ_DUAL_OUTPUT_FAST_4B   0x3c
+#define CMD_READ_DUAL_IO_FAST_4B   0xbc
+#define CMD_READ_QUAD_OUTPUT_FAST_4B   0x6c
+#define CMD_READ_QUAD_IO_FAST_4B   0xec
+
+/* 4B Write commands */
+#define CMD_PAGE_PROGRAM_4B0x12
+
+/* 4B Erase commands */
+#define CMD_ERASE_4K_4B0x21
+#define CMD_ERASE_CHIP_4B  0x5c
+#define CMD_ERASE_64K_4B   0xdc
+
 #define CMD_READ_ID0x9f
 #define CMD_READ_STATUS0x05
 #define CMD_READ_STATUS1   0x35
 #define CMD_READ_CONFIG0x35
 #define CMD_FLAG_STATUS0x70
-#define CMD_EN4B   0xB7
-#define CMD_EX4B   0xE9
+#define CMD_EN4B   0xB7
+#define CMD_EX4B   0xE9
 
 /* Bank addr access commands */
 #ifdef CONFIG_SPI_FLASH_BAR
@@ -133,6 +151,10 @@ struct spi_flash_info {
 #define RD_DUALBIT(5)  /* use Dual Read */
 #define RD_QUADIO  BIT(6)  /* use Quad IO Read */
 #define RD_DUALIO  BIT(7)  /* use Dual IO Read */
+#define OPCODES_4B BIT(8)  /*
+* Use dedicated 4byte address op codes
+* to support memory size above 128Mib.
+*/
 #define RD_FULL(RD_QUAD | RD_DUAL | RD_QUADIO | 
RD_DUALIO)
 };
 
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 997e858..2e82a90 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -22,12 +22,28 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void spi_flash_addr(u32 addr, u8 *cmd)
+static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd)
 {
/* cmd[0] is actual command */
-   cmd[1] = addr >> 16;
-   cmd[2] = addr >> 8;
-   cmd[3] = addr >> 0;
+
+   switch (flash->addr_width) {
+   case SPI_FLASH_3B_ADDR_LEN:
+   cmd[1] = addr >> 16;
+   cmd[2] = addr >> 8;
+   cmd[3] = addr >> 0;
+   break;
+
+   case SPI_FLASH_4B_ADDR_LEN:
+   cmd[1] = addr >> 24;
+   cmd[2] = addr >> 16;
+   cmd[3] = addr >> 8;
+   cmd[4] = addr >> 0;
+   break;
+
+   default:
+   debug("SF: Wrong opcode size\n");
+   break;
+   }
 }
 
 static int read_sr(struct spi_flash *flash, u8 *rs)
@@ -74,6 +90,64 @@ static int write_sr(struct spi_flash *flash, u8 ws)
return 0;
 }
 
+static u8 spi_flash_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
+{
+   size_t i;
+
+   for (i = 0; i < size; i++)
+   if (table[i][0] == opcode)
+   return table[i][1];
+
+   /* No conversion found, keep input op code. */
+   return opcode;
+}
+
+static inline u8 spi_flash_convert_3to4_read(u8 opcode)
+{
+   static const u8 spi_flash_3to4_read[][2] = {
+   { CMD_READ_ARRAY_SLOW,  CMD_READ_ARRAY_SLOW_4B },
+   { CMD_READ_ARRAY_FAST,  CMD_READ_ARRAY_FAST_4B },
+   { CMD_READ_DUAL_OUTPUT_FAST,CMD_READ_DUAL_OUTPUT_FAST_4B },
+   { CMD_READ_DUAL_IO_FAST,CMD_READ_DUAL_IO_FAST_4B },
+

[U-Boot] [RFC 1/5] sf: Add support of 1-2-2, 1-4-4 IO READ protocols

2017-12-10 Thread Prabhakar Kushwaha

IO READ protocols transfers both address and data on multiple
data bits. 1-2-2(DUAL IO), 1-4-4(QUAD IO) transfer address on 2
data bits or 4 bits per rising edge of SCK respectively.

This patch update spi_nor_flash_parameter->spi_nor_read_command
array based on DUAL or QUAD IO flag enabled in flash_info for a flash.

Signed-off-by: Prabhakar Kushwaha 
---
 drivers/mtd/spi/spi_flash.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 51e28bf..4ff8d8b 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1071,8 +1071,12 @@ int spi_flash_scan(struct spi_flash *flash)
flash->read_cmd = CMD_READ_ARRAY_FAST;
if (spi->mode & SPI_RX_SLOW)
flash->read_cmd = CMD_READ_ARRAY_SLOW;
+   else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUADIO)
+   flash->read_cmd = CMD_READ_QUAD_IO_FAST;
else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD)
flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST;
+   else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUALIO)
+   flash->read_cmd = CMD_READ_DUAL_IO_FAST;
else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL)
flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST;
 
-- 
2.7.4

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[U-Boot] [RFC 0/5] sf: Update spi-nor framework

2017-12-10 Thread Prabhakar Kushwaha

SPI-NOR framework currently supports-
 - (1-1-1, 1-1-2, 1-1-4) read protocols
 - read latency(dummy bytes) are hardcoded with the assumption
 that the flash would support it.
 - No support of mode bits.
 - No support of flash size above 128Mib

This patch set add support of 1-2-2, 1-4-4 read protocols. 
It ports Linux commits "mtd: spi-nor: add a stateless method to support
memory size above 128Mib" and "mtd: spi-nor: parse Serial Flash
Discoverable Parameters (SFDP) tables". It enables 4byte address opcode
and run time flash parameters discovery including dummy cycle and mode
cycle.

Finally it update fsl-quadspi driver to store(set_mode) spi bus mode and
provision for run-time LUTs creation.

Note: This patch-set is only **compliation** tested. Sending RFC to get
early feed-back on the approach.

Prabhakar Kushwaha (5):
  sf: Add support of 1-2-2, 1-4-4 IO READ protocols
  sf: add method to support memory size above 128Mib
  sf: parse Serial Flash Discoverable Parameters (SFDP) tables
  sf: fsl_qspi: Add support of fsl_qspi_set_mode
  sf: fsl_quadspi: Configue LUT based on padding information

 drivers/mtd/spi/sf_internal.h   | 230 +++-
 drivers/mtd/spi/spi_flash.c | 574 +++-
 drivers/spi/fsl_qspi.c  |  85 +-
 include/spi_flash.h |   2 +
 5 files changed, 875 insertions(+), 18 deletions(-)

-- 
2.7.4

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Re: [U-Boot] [PATCH v4 2/4] net: designware: Pad small packets

2017-12-10 Thread Stefan Roese


On 09.12.2017 23:59, Florian Fainelli wrote:

Make sure that we pad small packets to a minimum length of 60 bytes
(without FCS). This is necessary to interface with Ethernet switches
that will reject RUNT frames unless padded correctly.

Signed-off-by: Florian Fainelli 


Reviewed-by: Stefan Roese 

Thanks,
Stefan
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[U-Boot] [PATCH v2] armv8: layerscape: sata: refine port register configuration

2017-12-10 Thread Yuantian Tang

Sata registers PP2C and PP3C are used to control the configuration
of the PHY control OOB timing for the COMINIT/COMWAKE parameters
respectively.
Calculate those parameters from port clock frequency. Overwrite those
registers with calculated values to get better OOB timing.

Signed-off-by: Tang Yuantian 
---
v2:
- refine the commit message and title

 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 6 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 497a4b541d..b52653929c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -328,6 +328,8 @@ int sata_init(void)
 #ifdef CONFIG_SYS_SATA2
ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+   out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 #endif
@@ -335,6 +337,8 @@ int sata_init(void)
 #ifdef CONFIG_SYS_SATA1
ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+   out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
@@ -355,6 +359,8 @@ int sata_init(void)
/* Disable SATA ECC */
out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x8000);
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+   out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 247f09e0f5..664d847e9c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -88,6 +88,8 @@ struct cpu_type {
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG0xa003fffe
+#define AHCI_PORT_PHY2_CFG 0x28184d1f
+#define AHCI_PORT_PHY3_CFG 0x0e081509
 #define AHCI_PORT_TRANS_CFG0x0829
 #define AHCI_PORT_AXICC_CFG0x3fff
 
-- 
2.14.1

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Re: [U-Boot] Updating ZFS for U-boot

2017-12-10 Thread Jorgen Lundman


The draft update for ZFS is ready, and is available here:
https://github.com/lundman/u-boot/commit/c2727e5004fe011d19156d728babdf968515b28d

I will refresh myself on U-boot commit procedures, and start the proper
method soon.

I did a question though, to be able to test file reading, I had to add the
code:

#ifdef CONFIG_SANDBOX
char *bufx = map_sysmem((phys_addr_t)(uint64_t)buf, movesize);

memmove(bufx, data->file_buf + file->offset + red
- data->file_start, movesize);
unmap_sysmem(bufx);
#else
memmove(buf, data->file_buf + file->offset + red
- data->file_start, movesize);
#endif

Should I keep that as #ifdef SANDBOX, or is there a preferred method?

I have tried to follow checkcommit.pl rules, and changed a few things to
"const" etc, to make it cleaner.

Example output:

Hit any key to stop autoboot:  0
=> host bind 0 ./raid1.raw
=> host bind 1 ./raid2.raw
=> host bind 2 ./raid3.raw
=> zfsls host 0:0 /@/
zfs: adding device 'host' dev 0
zfs: couldn't find a necessary member device of multi-device filesystem
zfs: couldn't find a necessary member device of multi-device filesystem
zfs: looking for devices...
zfs: adding device 'host' dev 1
zfs: adding device 'host' dev 2
zfs: device scan completed.
zfs fsname = '/' snapname='' filename = '/'
  hello.world
   file.txt


The device scan function ended up looking like:

for (
uclass_first_device(UCLASS_BLK, );
dev;
uclass_next_device()
) {
struct blk_desc *desc = dev_get_uclass_platdata(dev);
for (part = 0; part <= MAX_SEARCH_PARTITIONS; part++) {
snprintf(dev_str, sizeof(dev_str), "%u:%u", desc->devnum, part);
part = 
blk_get_device_part_str(blk_get_if_type_name(desc->if_type),
   dev_str,
   , _info, 1);
if (part < 0)
continue;


Hopefully that is acceptable.

Any other cleanups requested in the ZFS area?

Lund
-- 
Jorgen Lundman   | 
Unix Administrator   | +81 (0)90-5578-8500
Shibuya-ku, Tokyo| Japan

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Re: [U-Boot] [PATCH v3 15/18] efi_loader: output load options in helloworld

2017-12-10 Thread Florian Fainelli



On 12/09/2017 10:40 PM, Heinrich Schuchardt wrote:
> On 12/10/2017 12:09 AM, Florian Fainelli wrote:
>>
>>
>> On 11/26/2017 05:05 AM, Heinrich Schuchardt wrote:
>>> We need to test if we pass a valid image handle when loading
>>> and EFI application. This cannot be done in efi_selftest as
>>> it is not loaded as an image.
>>>
>>> So let's enhance helloworld a bit.
>>>
>>> Reviewed-by: Simon Glass 
>>> Signed-off-by: Heinrich Schuchardt 
>>
>> This particular patch/commit bbf75dd9345d0b1a7ec7a50016547eb7c759b7af
>> ("efi_loader: output load options in helloworld") was bisected and
>> causes the Lamobo_R1_defconfig build using the toolchain at [1] to fail
>> with:
>>
>> /home/fainelli/work/toolchains/stbgcc-6.3-1.1/bin/arm-linux-ld.bfd:
>> error: required section '.got' not found in the linker script
>> /home/fainelli/work/toolchains/stbgcc-6.3-1.1/bin/arm-linux-ld.bfd:
>> final link failed: Invalid operation
>> scripts/Makefile.lib:409: recipe for target
>> 'lib/efi_loader/helloworld_efi.so' failed
>> make[2]: *** [lib/efi_loader/helloworld_efi.so] Error 1
>> rm lib/efi_loader/helloworld.o
>> scripts/Makefile.build:425: recipe for target 'lib/efi_loader' failed
>> make[1]: *** [lib/efi_loader] Error 2
>>
>> [1]: https://github.com/Broadcom/stbgcc-6.3/releases/tag/stbgcc-6.3-1.1
>>
> 
> Isn't this fixed by
> http://git.denx.de/?p=u-boot.git;a=commit;h=3bb74f9800cdc4cf10a87f2725242c2565256654
> 
> "efi_loader helloworld.efi: Fix building with -Os" ?

Nope, my tree is at v2018.01-rc1-115-g335f7b1290ce which contains that
commit already.
-- 
Florian
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Re: [U-Boot] [PATCH v2 2/5] net: sun8i_emac: Support RX/TX delay chains

2017-12-10 Thread Simon Glass

Hi Joe,

On 7 December 2017 at 11:45, Joe Hershberger  wrote:
>
> On Wed, Dec 6, 2017 at 8:35 PM, Chen-Yu Tsai  wrote:
> > On Thu, Dec 7, 2017 at 4:20 AM, Joe Hershberger
> >  wrote:
> >> On Tue, Dec 5, 2017 at 8:34 PM, Chen-Yu Tsai  wrote:
> >>> On Wed, Dec 6, 2017 at 4:50 AM, Joe Hershberger  
> >>> wrote:
>  On Fri, Nov 24, 2017 at 11:08 PM, Chen-Yu Tsai  wrote:
> > The EMAC syscon has configurable RX/TX delay chains for use with RGMII
> > PHYs.
> >
> > This adds support for configuring them via device tree properties. The
> > property names and format were defined in Linux's dwmac-sun8i binding
> > that was merged at one point.
> 
>  I'm not seeing this in doc/device-tree-bindings/net/
> >>>
> >>> See 
> >>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> >>>
> >>> The bindings have been restored as of v4.15-rc1.
> >>>
> >>> We are following DT bindings as defined in the Linux kernel. Deviation
> >>> is kept to a minimum, and eliminated if possible. We still need to
> >>> migrate the driver to the new bindings for the internal PHY bits.
> >>> But that bit might still be changed during the 4.15 release cycle.
> >>
> >> That's good, but we want to have the currently supported bindings
> >> copied into the U-Boot tree under doc/device-tree-bindings/net/.
> >> Please include a patch that adds the bindings that your driver is
> >> using.
> >
> > Looks like this is a new requirement. Or it wasn't really enforced
> > before. Doesn't this make U-boot prone to having diverging device
> > tree bindings? It has already happened with the regulator bindings,
> > specifically the "regulator-name" property.
> >
> > And by "currently supported", are you referring to what the driver
> > expects, and not what the end result, i.e. the accepted bindings
> > in Linux, should be? This driver is still in a state of catchup.
> > The driver supports a previously merged then reverted set of
> > bindings. These bindings were then brought back and updated for
> > Linux v4.15 (unreleased yet, so may still change, again). So which
> > set of bindings should I submit here?
> >
> > And the goal _is_ to migrate the driver to what Linux is using, so
> > we can share the device tree files.
>
> I believe the goal is to have them match the current state of the
> driver as supported in U-Boot, and a higher-level goal of keeping the
> bindings + driver in sync with Linux for sharing.

Yes, they should match, and we should have the same binding file.

Also, please use dev_read_...() instead of fdtdec...() for all new
code since that supports live tree.

>
> Correct, Simon?
>
> Thanks,
> -Joe

Regards,
Simon
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Re: [U-Boot] [PATCH v2 07/19] fdt: Add compatible strings for Arria 10

2017-12-10 Thread Simon Glass

Hi,

On 25 September 2017 at 03:08, Marek Vasut  wrote:
> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
>> From: Tien Fong Chee 
>>
>> Add compatible strings for Intel Arria 10 SoCFPGA device.
>>
>> Signed-off-by: Tien Fong Chee 
>
> Applied, thanks
>
>> ---
>>  include/fdtdec.h | 2 ++
>>  lib/fdtdec.c | 2 ++
>>  2 files changed, 4 insertions(+)
>>
>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>> index 4a0947c..095ff36 100644
>> --- a/include/fdtdec.h
>> +++ b/include/fdtdec.h
>> @@ -157,6 +157,8 @@ enum fdt_compat_id {
>>   COMPAT_ALTERA_SOCFPGA_F2SDR0,   /* SoCFPGA fpga2SDRAM0 bridge 
>> */
>>   COMPAT_ALTERA_SOCFPGA_F2SDR1,   /* SoCFPGA fpga2SDRAM1 bridge 
>> */
>>   COMPAT_ALTERA_SOCFPGA_F2SDR2,   /* SoCFPGA fpga2SDRAM2 bridge 
>> */
>> + COMPAT_ALTERA_SOCFPGA_FPGA0,/* SOCFPGA FPGA manager */
>> + COMPAT_ALTERA_SOCFPGA_NOC,  /* SOCFPGA Arria 10 NOC */

We should not be adding new things here. There is a clear message at the top:

 * NOTE: This list is basically a TODO list for things that need to be
 * converted to driver model. So don't add new things here unless there is a
 * good reason why driver-model conversion is infeasible. Examples include
 * things which are used before driver model is available.

Can this be converted to driver model please? I'll see if I can remove
this array.

>>
>>   COMPAT_COUNT,
>>  };
>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>> index 107a892..03ff75e 100644
>> --- a/lib/fdtdec.c
>> +++ b/lib/fdtdec.c
>> @@ -70,6 +70,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
>>   COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
>>   COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
>>   COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
>> + COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
>> + COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
>>  };
>>
>>  const char *fdtdec_get_compatible(enum fdt_compat_id id)
>>
>
>
> --
> Best regards,
> Marek Vasut


Regards,
Simon
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Re: [U-Boot] [PATCH] net: sh-eth: Add to Kconfig and convert

2017-12-10 Thread Joe Hershberger

On Fri, Dec 1, 2017 at 1:08 AM, Nobuhiro Iwamatsu  wrote:
> This adds SH_ETHER to drivers/net/Kconfig and convert to Kconfig.
>
> Signed-off-by: Nobuhiro Iwamatsu 

Travis seems unhappy with this patch.

https://travis-ci.org/jhershbe/u-boot/jobs/314078906

Please have a look.
Thanks,
-Joe
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[U-Boot] [PATCH] gpio/hsdk: Depend on DM_GPIO instead of simple DM

2017-12-10 Thread Alexey Brodkin

This driver really is DM GPIO one and so we need to have a correct
dependency, because DM alone doesn't provide required for CMD_GPIO
call and we're seeing build failures like this:
-->8-
cmd/built-in.o: In function 'do_gpio':
.../cmd/gpio.c:188: undefined reference to 'gpio_request'
...
-->8-

Signed-off-by: Alexey Brodkin 
Cc: Eugeniy Paltsev 
Cc: Simon Glass 
---
 drivers/gpio/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 2acb33bb51bc..b4e859e40cfe 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -82,7 +82,7 @@ config IMX_RGPIO2P
 
 config HSDK_CREG_GPIO
bool "HSDK CREG GPIO griver"
-   depends on DM
+   depends on DM_GPIO
default n
help
  This driver supports CREG GPIOs on Synopsys HSDK SOC.
-- 
2.7.5

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[U-Boot] [PATCH] README: update the kernel coding style reference

2017-12-10 Thread Baruch Siach

The old CodingStyle document has been converted to ReST and moved
elsewhere. Link to the web version of this document instead.

Signed-off-by: Baruch Siach 
---
 README | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/README b/README
index 2df0e1f8a78e..93c7ea966589 100644
--- a/README
+++ b/README
@@ -5126,8 +5126,9 @@ Coding Standards:
 -
 
 All contributions to U-Boot should conform to the Linux kernel
-coding style; see the file "Documentation/CodingStyle" and the script
-"scripts/Lindent" in your Linux kernel source directory.
+coding style; see the kernel coding style guide at
+https://www.kernel.org/doc/html/latest/process/coding-style.html, and the
+script "scripts/Lindent" in your Linux kernel source directory.
 
 Source files originating from a different project (for example the
 MTD subsystem) are generally exempt from these guidelines and are not
-- 
2.15.1

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Re: [U-Boot] [PATCH 3/3] ARM: imx: cm_fx6: env: don't run boot scripts twice

2017-12-10 Thread Fabio Estevam

On Sat, Dec 9, 2017 at 1:37 PM,   wrote:
> From: Christopher Spinrath 
>
> Boot scripts located in the root directory of the first partition of
> USB, mmc, and SATA drives are executed twice: first by the distro boot
> command and then by the legacy boot command. This may have weird side
> effects if those scripts only change or extend the environment
> (including parts of the boot command itself).
>
> Removing the script execution from the legacy boot command has its own
> caveats. For instance, the distro boot command may execute the boot.scr
> on the mmc drive, then the boot.scr on the SATA drive, before the
> legacy boot command actually boots from the mmc drive. However, the
> current behavior would only execute the boot.scr once more before the
> actual boot, but it does not prevent the script located on the SATA
> drive from being executed, and thus, both scripts from being mixed up.
>
> Considering that the legacy boot command is only in place to boot old
> (standard) installations, let's go with the resolution having less
> custom code and remove the script execution from the legacy boot
> command.
>
> Signed-off-by: Christopher Spinrath 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH 2/3] ARM: imx: cm_fx6: env: support distro boot command

2017-12-10 Thread Fabio Estevam

On Sat, Dec 9, 2017 at 1:37 PM,   wrote:
> From: Christopher Spinrath 
>
> The current default environment of the cm_fx6 is not suitable for
> booting modern distributions.
>
> Instead of extending the custom environment, let's use the distro
> boot command, which has been developed for precisely this use case.
>
> If the distro boot command fails, fall back to the old behavior
> (except for USB drives where the old behaviour is completely covered
> by the distro boot command). That way it is still possible to create
> "rescue SD cards" for old installations (e.g. if one messes up the
> on-flash environment).
>
> Signed-off-by: Christopher Spinrath 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH 1/3] ARM: imx: cm_fx6: env: use standard variables

2017-12-10 Thread Fabio Estevam

On Sat, Dec 9, 2017 at 1:37 PM,   wrote:
> From: Christopher Spinrath 
>
> In preparation for supporting the distro boot command, introduce the
> standard variables for specifying load addresses, which are documented
> in README and doc/README.distro, and replace the custom variables
> used so far with them.
>
> Since the current address layout disregards an address for an initramfs,
> also switch to the load addresses used and proven by other imx6 boards
> (e.g. the wandboard and nitrogen6x), instead of going on with our own
> way.
>
> Signed-off-by: Christopher Spinrath 

Reviewed-by: Fabio Estevam 
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[U-Boot] [PATCH] arm64: mvebu: armada-8k: support SD card environment

2017-12-10 Thread Baruch Siach

Allow storing the environment on the Macchiatobin SD card. This is
useful for distribution of SD card software images. Currently, the
environment is always loaded from the SPI flash whose content might be
incompatible with SD card kernel loading.

Use the last 64KB of the 32MB boot partition as per the instructions in
the Macchiatobin wiki:

  
http://wiki.macchiatobin.net/tiki-index.php?page=Setup+alternative+boot+sources

Cc: Konstantin Porotchkin 
Signed-off-by: Baruch Siach 
---
 include/configs/mvebu_armada-8k.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/include/configs/mvebu_armada-8k.h 
b/include/configs/mvebu_armada-8k.h
index d85527434a0a..0457a72e353b 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -73,7 +73,12 @@
 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
 #define CONFIG_ENV_SPI_MODECONFIG_SF_DEFAULT_MODE
 
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 #define CONFIG_ENV_OFFSET  0x18 /* as Marvell U-Boot version */
+#elif defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_ENV_OFFSET  0x21f
+#endif
 #define CONFIG_ENV_SIZE(64 << 10) /* 64KiB */
 #define CONFIG_ENV_SECT_SIZE   (64 << 10) /* 64KiB sectors */
 
-- 
2.15.0

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Re: [U-Boot] [PATCH] efi_loader: Fix partition offsets

2017-12-10 Thread Mark Kettenis

> From: Alexander Graf 
> Date: Thu, 7 Dec 2017 11:27:15 +0100
> 
> On 07.12.17 08:00, Jonathan Gray wrote:
> > On Fri, Dec 01, 2017 at 04:10:33PM +0100, Alexander Graf wrote:
> >> Commit 884bcf6f65 (efi_loader: use proper device-paths for partitions) 
> >> tried
> >> to introduce the el torito scheme to all partition table types: Spawn
> >> individual disk objects for each partition on a disk.
> >>
> >> Unfortunately, that code ended up creating partitions with offset=0 which 
> >> meant
> >> that anyone accessing these objects gets data from the raw block device 
> >> instead
> >> of the partition.
> >>
> >> Furthermore, all the el torito logic to spawn devices for partitions was
> >> duplicated. So let's merge the two code paths and give partition disk 
> >> objects
> >> good offsets to work from, so that payloads can actually make use of them.
> >>
> >> Fixes: 884bcf6f65 (efi_loader: use proper device-paths for partitions)
> >> Reported-by: Yousaf Kaukab 
> >> Signed-off-by: Alexander Graf 
> > 
> > This once again broke being able to find a DEVICE_PATH_TYPE_MEDIA_DEVICE
> > node with the loaded image protocol on rpi_3 with mmc/usb.
> 
> Hooray :). Do you think you could somehow assemble a test that runs
> inside Travis-CI to make sure we catch your loader? I still need to do a
> better one for grub to ensure that that one's happy too.

Yes, I'd very much like to do that.  I suppose this should be a
qemu-based test in test/py/tests?  It is not clear to me how I run
those outside of Travis-CI.  Can you point me in the right direction?
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Re: [U-Boot] [PATCH v5 00/11] mmc: fixes for HS200/UHS core support

[U-Boot] [RFC 3/5] sf: parse Serial Flash Discoverable Parameters (SFDP) tables

[U-Boot] [RFC 5/5] sf: fsl_quadspi: Configue LUT based on padding information

[U-Boot] [RFC 4/5] sf: fsl_qspi: Add support of fsl_qspi_set_mode

[U-Boot] [RFC 2/5] sf: add method to support memory size above 128Mib

[U-Boot] [RFC 1/5] sf: Add support of 1-2-2, 1-4-4 IO READ protocols

[U-Boot] [RFC 0/5] sf: Update spi-nor framework

Re: [U-Boot] [PATCH v4 2/4] net: designware: Pad small packets

[U-Boot] [PATCH v2] armv8: layerscape: sata: refine port register configuration

Re: [U-Boot] Updating ZFS for U-boot

Re: [U-Boot] [PATCH v3 15/18] efi_loader: output load options in helloworld

Re: [U-Boot] [PATCH v2 2/5] net: sun8i_emac: Support RX/TX delay chains

Re: [U-Boot] [PATCH v2 07/19] fdt: Add compatible strings for Arria 10

Re: [U-Boot] [PATCH] net: sh-eth: Add to Kconfig and convert

[U-Boot] [PATCH] gpio/hsdk: Depend on DM_GPIO instead of simple DM

[U-Boot] [PATCH] README: update the kernel coding style reference

Re: [U-Boot] [PATCH 3/3] ARM: imx: cm_fx6: env: don't run boot scripts twice

Re: [U-Boot] [PATCH 2/3] ARM: imx: cm_fx6: env: support distro boot command

Re: [U-Boot] [PATCH 1/3] ARM: imx: cm_fx6: env: use standard variables

[U-Boot] [PATCH] arm64: mvebu: armada-8k: support SD card environment

Re: [U-Boot] [PATCH] efi_loader: Fix partition offsets

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