Re: [U-Boot] [PATCH v2 1/4] ARM: qemu-arm: Add support for AArch64

[Jonathan Gray]

On Thu, Jan 11, 2018 at 04:11:23PM +0200, Tuomas Tynkkynen wrote:
> This adds support for '-machine virt' on AArch64. This is rather simple:
> we just add TARGET_QEMU_ARM_xxBIT to select a few different Kconfig
> symbols, provide the ARMv8 memory map from the board file and add a new
> defconfig based on the 32-bit defconfig.

While nvme is in the defconfig it seems only ahci works with
distroboot automatically.

Booting off nvme requires manually running

=> nvme scan
=> setenv devtype nvme
=> run scan_dev_for_boot_part

Having it work automatically requires something like the below

diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 5c469a23fa..305e102cb8 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -195,6 +195,31 @@
BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
 #endif
 
+#ifdef CONFIG_NVME
+#define BOOTENV_RUN_NVME_INIT "run nvme_init; "
+#define BOOTENV_SET_NVME_NEED_INIT "setenv nvme_need_init; "
+#define BOOTENV_SHARED_NVME \
+   "nvme_init=" \
+   "if ${nvme_need_init}; then " \
+   "setenv nvme_need_init false; " \
+   "nvme scan; " \
+   "fi\0" \
+   \
+   "nvme_boot=" \
+   BOOTENV_RUN_NVME_INIT \
+   BOOTENV_SHARED_BLKDEV_BODY(nvme)
+#define BOOTENV_DEV_NVME   BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_NVME  BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_RUN_NVME_INIT
+#define BOOTENV_SET_NVME_NEED_INIT
+#define BOOTENV_SHARED_NVME
+#define BOOTENV_DEV_NVME \
+   BOOT_TARGET_DEVICES_references_NVME_without_CONFIG_NVME
+#define BOOTENV_DEV_NAME_NVME \
+   BOOT_TARGET_DEVICES_references_NVME_without_CONFIG_NVME
+#endif
+
 #ifdef CONFIG_IDE
 #define BOOTENV_SHARED_IDE BOOTENV_SHARED_BLKDEV(ide)
 #define BOOTENV_DEV_IDEBOOTENV_DEV_BLKDEV
@@ -324,6 +349,7 @@
 #define BOOTENV \
BOOTENV_SHARED_HOST \
BOOTENV_SHARED_MMC \
+   BOOTENV_SHARED_NVME \
BOOTENV_SHARED_PCI \
BOOTENV_SHARED_USB \
BOOTENV_SHARED_SATA \
@@ -390,6 +416,7 @@
BOOT_TARGET_DEVICES(BOOTENV_DEV)  \
\
"distro_bootcmd=" BOOTENV_SET_SCSI_NEED_INIT  \
+   BOOTENV_SET_NVME_NEED_INIT\
"for target in ${boot_targets}; do "  \
"run bootcmd_${target}; " \
"done\0"
diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h
index c8852cef34..8c65babb77 100644
--- a/include/configs/qemu-arm.h
+++ b/include/configs/qemu-arm.h
@@ -38,7 +38,8 @@
 #include 
 
 #define BOOT_TARGET_DEVICES(func) \
-   func(SCSI, scsi, 0)
+   func(SCSI, scsi, 0) \
+   func(NVME, nvme, 0)
 
 #include 
 
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Re: [U-Boot] [U-Boot, v2, 16/18] clk: rockchip: Add rk322x gamc clock support

[David.Wu]

Hi Philipp,

For the 'assigned-clocks' patches, i tested them well, and have 
implemented them at rk3328, rk3229, rk3288 and rk3368. The patches has 
been send for your review. Except for one thing, just like you said, we 
need to move "clk_set_defaults" further down and do it just before:

if (drv->probe) {
   ret = drv->probe(dev);
after ofdata_to_platdata called, or we might have a cru uninitialized 
problem.


在 2018/1/8 23:12, Dr. Philipp Tomsich 写道:

David,

As discussed last week (off-list), I implemented infrastructure-support for the
'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates’ 
properties
in the DTS … and validated on the RK3399.

For my work-in-progress tree, see the ‘assigned-clocks-wip’ branch at:
https://github.com/ptomsich/u-boot-rockchip/tree/assigned-clocks-wip

If this is sufficient to solve our clocking-issue on GMAC let me know. I plan to
have some additional time to finish this up for submission around the end of
the week.

@Jakob: This is the change I mentioned this morning that provides infrastructure
to allow setting PLLs via the DTS.  These changes are also on our internal GIT
in the ‘assigned-clocks-wip’ branch (which I manually mirror onto GitHub, so I
can test via Travis-CI).

Comments are welcome,
Phil.


On 4 Jan 2018, at 14:22, David.Wu  wrote:

Hi Philipp,

Could i just make the clock-driver respond to the requested frequency? I.e. 
50MHz will most likely always come from the internal sources
so when 50Mhz for rmii gets requested you just assume that we will use the 
internal source. And the 125MHz, we assume that we will use the externalsource.

在 2017/12/21 19:21, David.Wu 写道:

Hi Philipp,
在 2017/11/26 22:50, Philipp Tomsich 写道:


On Thu, 9 Nov 2017, David Wu wrote:


Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.

Signed-off-by: David Wu 
Acked-by: Philipp Tomsich 


Reviewed-by: Philipp Tomsich 

See below for requested changes.


---

Changes in v2:
- New patch

drivers/clk/rockchip/clk_rk322x.c | 13 +
1 file changed, 13 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk322x.c 
b/drivers/clk/rockchip/clk_rk322x.c
index e87267d..5fd27cd 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -239,6 +239,16 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, 
uint clk_general_rate,
 return DIV_TO_RATE(src_rate, div) / 2;
}

+static int rk322x_mac_set_clk(struct rk322x_cru *cru,
+  int periph, uint freq)
+{
+/* Assuming mac_clk is fed by an external clock */
+rk_clrsetreg(>cru_clksel_con[5], BIT(5),
+ BIT(5));


Please use a symbolic constant for BIT(5).

If this is the input/output selection for the MAC clk and covered by 'clock_in_out = 
"input";' in the DTS, then the DTS should be consulted before assuming a 
specific setting here.


Yes, I think so, but not do it now;
If it is "input", then actually do not need to set clk rate, as long as the 
direction of setting clk, clk rate rely on external clock input may originate from PHY.
If it is "output", then also need to set clk rate.
There has been the interface of setting clock rate currently, but not set the direction. 
Can we in the GMAC driver directly set cru registers of mac_clk direction through the dts 
property of "clk_in_out", otherwise need clk framework to provide a set of 
directional interface like setting the parent of mac_clk.

+
+return 0;
+}
+
static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
   int periph, uint freq)
{
@@ -352,6 +362,9 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong 
rate)
 case CLK_DDR:
 new_rate = rk322x_ddr_set_clk(priv->cru, rate);
 break;
+case SCLK_MAC:
+new_rate = rk322x_mac_set_clk(priv->cru, clk->id, rate);
+break;
 default:
 return -ENOENT;
 }














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[U-Boot] [PATCH v3 17/20] config: evb-rk3229: Enable rk gmac configs

[David Wu]

Add gmac config support for rk3229 evb.

Signed-off-by: David Wu 
---

Changes in v3:
- None

Changes in v2:
- New patch

 configs/evb-rk3229_defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index b226f66..39469b4 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -21,6 +21,7 @@ CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
@@ -31,6 +32,10 @@ CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_ROCKCHIP_RK322X=y
 CONFIG_RAM=y
-- 
2.7.4


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[U-Boot] [PATCH v3 20/20] clk: rockchip: clk_rk3368: Implement "assign-clock-parent"

[David Wu]

Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.

Signed-off-by: David Wu 
---

Changes in v3:
- New patch

Changes in v2: None

 arch/arm/include/asm/arch-rockchip/cru_rk3368.h |  7 ++
 drivers/clk/rockchip/clk_rk3368.c   | 91 +++--
 2 files changed, 91 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index 5f6a5fb..6a6fe47 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -95,6 +95,13 @@ enum {
CLK_SARADC_DIV_CON_WIDTH= 8,
 
/* CLKSEL43_CON */
+   GMAC_DIV_CON_SHIFT  = 0x0,
+   GMAC_DIV_CON_MASK   = GENMASK(4, 0),
+   GMAC_PLL_SHIFT  = 6,
+   GMAC_PLL_MASK   = GENMASK(7, 6),
+   GMAC_PLL_SELECT_NEW = (0x0 << GMAC_PLL_SHIFT),
+   GMAC_PLL_SELECT_CODEC   = (0x1 << GMAC_PLL_SHIFT),
+   GMAC_PLL_SELECT_GENERAL = (0x2 << GMAC_PLL_SHIFT),
GMAC_MUX_SEL_EXTCLK = BIT(8),
 
/* CLKSEL51_CON */
diff --git a/drivers/clk/rockchip/clk_rk3368.c 
b/drivers/clk/rockchip/clk_rk3368.c
index a831991..3364e6a 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -311,15 +311,43 @@ static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, 
ulong set_rate)
 #endif
 
 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
-static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,
-ulong clk_id, ulong set_rate)
+static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate)
 {
+   ulong ret;
+
/*
-* This models the 'assigned-clock-parents = <_gmac>' from
-* the DTS and switches to the 'ext_gmac' clock parent.
+* The gmac clock can be derived either from an external clock
+* or can be generated from internally by a divider from SCLK_MAC.
 */
-   rk_setreg(>clksel_con[43], GMAC_MUX_SEL_EXTCLK);
-   return set_rate;
+   if (readl(>clksel_con[43]) & GMAC_MUX_SEL_EXTCLK) {
+   /* An external clock will always generate the right rate... */
+   ret = set_rate;
+   } else {
+   u32 con = readl(>clksel_con[43]);
+   ulong pll_rate;
+   u8 div;
+
+   if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
+   GMAC_PLL_SELECT_GENERAL)
+   pll_rate = GPLL_HZ;
+   else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
+GMAC_PLL_SELECT_CODEC)
+   pll_rate = CPLL_HZ;
+   else
+   /* CPLL is not set */
+   return -EPERM;
+
+   div = DIV_ROUND_UP(pll_rate, set_rate) - 1;
+   if (div <= 0x1f)
+   rk_clrsetreg(>clksel_con[43], GMAC_DIV_CON_MASK,
+div << GMAC_DIV_CON_SHIFT);
+   else
+   debug("Unsupported div for gmac:%d\n", div);
+
+   return DIV_TO_RATE(pll_rate, div);
+   }
+
+   return ret;
 }
 #endif
 
@@ -479,7 +507,7 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong 
rate)
 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
case SCLK_MAC:
/* select the external clock */
-   ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate);
+   ret = rk3368_gmac_set_clk(priv->cru, rate);
break;
 #endif
case SCLK_SARADC:
@@ -492,9 +520,58 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong 
rate)
return ret;
 }
 
+static int rk3368_gmac_set_parent(struct clk *clk, struct clk *parent)
+{
+   struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+   struct rk3368_cru *cru = priv->cru;
+   const char *clock_output_name;
+   int ret;
+
+   /*
+* If the requested parent is in the same clock-controller and
+* the id is SCLK_MAC ("sclk_mac"), switch to the internal
+* clock.
+*/
+   if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
+   debug("%s: switching GAMC to SCLK_MAC\n", __func__);
+   rk_clrreg(>clksel_con[43], GMAC_MUX_SEL_EXTCLK);
+   return 0;
+   }
+
+   /*
+* Otherwise, we need to check the clock-output-names of the
+* requested parent to see if the requested id is "ext_gmac".
+*/
+   ret = dev_read_string_index(parent->dev, "clock-output-names",
+   parent->id, _output_name);
+   if (ret < 0)
+   return -ENODATA;
+
+   /* If this is "ext_gmac", switch to the external clock input */
+   if (!strcmp(clock_output_name, "ext_gmac")) {
+   debug("%s: switching GMAC to external clock\n", __func__);
+

[U-Boot] [PATCH v3 18/20] ARM: dts: rk3288: Remove unused LCDC clock assigned

[David Wu]

The LCDC assigned rate is 0, it will make boot error,
error log:"pll_para_config: the frequency can not be
 0 Hz". Remove them, and the lcdc driver will do the
correct clock rate setting.

Signed-off-by: David Wu 
---

Changes in v3:
- New patch

Changes in v2: None

 arch/arm/dts/rk3288.dtsi | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index da51878..2c8a616 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -604,19 +604,16 @@
u-boot,dm-pre-reloc;
#clock-cells = <1>;
#reset-cells = <1>;
-   assigned-clocks = < DCLK_VOP0>, < DCLK_VOP1>,
- < PLL_GPLL>, < PLL_CPLL>,
+   assigned-clocks = < PLL_GPLL>, < PLL_CPLL>,
  < PLL_NPLL>, < ACLK_CPU>,
  < HCLK_CPU>, < PCLK_CPU>,
  < ACLK_PERI>, < HCLK_PERI>,
  < PCLK_PERI>;
-   assigned-clock-rates = <0>, <0>,
-  <59400>, <4>,
+   assigned-clock-rates = <59400>, <4>,
   <5>, <3>,
   <15000>, <7500>,
   <3>, <15000>,
   <7500>;
-   assigned-clock-parents = < PLL_NPLL>, < PLL_GPLL>;
};
 
grf: syscon@ff77 {
-- 
2.7.4


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[U-Boot] [PATCH v3 12/20] rockchip: dts: rk3328-evb: Enable gmac2io for rk3328-evb

[David Wu]

Add rk3328-evb gmac support.

Signed-off-by: David Wu 
---

Changes in v3:
- None

Changes in v2:
- New patch

 arch/arm/dts/rk3328-evb.dts | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 3dd9d81..336c2d5 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -15,6 +15,13 @@
stdout-path = 
};
 
+   gmac_clkin: external-gmac-clock {
+   compatible = "fixed-clock";
+   clock-frequency = <12500>;
+   clock-output-names = "gmac_clkin";
+   #clock-cells = <0>;
+   };
+
vcc3v3_sdmmc: sdmmc-pwren {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
@@ -40,6 +47,13 @@
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
};
+
+   vcc_phy: vcc-phy-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc_phy";
+   regulator-always-on;
+   regulator-boot-on;
+   };
 };
 
  {
@@ -74,6 +88,22 @@
status = "okay";
 };
 
+ {
+   phy-supply = <_phy>;
+   phy-mode = "rgmii";
+   clock_in_out = "input";
+   snps,reset-gpio = < RK_PC2 GPIO_ACTIVE_LOW>;
+   snps,reset-active-low;
+   snps,reset-delays-us = <0 1 5>;
+   assigned-clocks = < SCLK_MAC2IO>, < SCLK_MAC2IO_EXT>;
+   assigned-clock-parents = <_clkin>, <_clkin>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   tx_delay = <0x26>;
+   rx_delay = <0x11>;
+   status = "okay";
+};
+
 _host0_ehci {
status = "okay";
 };
-- 
2.7.4


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[U-Boot] [PATCH v3 16/20] net: gmac_rockchip: Add support for the RK3228 GMAC

[David Wu]

The GMAC in the RK3228 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.

This adds the RK3368-specific logic necessary to reuse this driver.

Signed-off-by: David Wu 
---

Changes in v3:
- None

Changes in v2:
- New patch

 drivers/net/gmac_rockchip.c | 85 +
 1 file changed, 85 insertions(+)

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 551c230..683e820 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -69,6 +70,39 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice 
*dev)
return designware_eth_ofdata_to_platdata(dev);
 }
 
+static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+   struct rk322x_grf *grf;
+   int clk;
+   enum {
+   RK3228_GMAC_CLK_SEL_SHIFT = 8,
+   RK3228_GMAC_CLK_SEL_MASK  = GENMASK(9, 8),
+   RK3228_GMAC_CLK_SEL_125M  = 0 << 8,
+   RK3228_GMAC_CLK_SEL_25M   = 3 << 8,
+   RK3228_GMAC_CLK_SEL_2_5M  = 2 << 8,
+   };
+
+   switch (priv->phydev->speed) {
+   case 10:
+   clk = RK3228_GMAC_CLK_SEL_2_5M;
+   break;
+   case 100:
+   clk = RK3228_GMAC_CLK_SEL_25M;
+   break;
+   case 1000:
+   clk = RK3228_GMAC_CLK_SEL_125M;
+   break;
+   default:
+   debug("Unknown phy speed: %d\n", priv->phydev->speed);
+   return -EINVAL;
+   }
+
+   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   rk_clrsetreg(>mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
+
+   return 0;
+}
+
 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
struct rk3288_grf *grf;
@@ -221,6 +255,50 @@ static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
return 0;
 }
 
+static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+   struct rk322x_grf *grf;
+   enum {
+   RK3228_RMII_MODE_SHIFT = 10,
+   RK3228_RMII_MODE_MASK  = BIT(10),
+
+   RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
+   RK3228_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
+   RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+   RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+   RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+   RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+   RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+   RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+   RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+   };
+   enum {
+   RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+   RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+   RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+   RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+   };
+
+   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   rk_clrsetreg(>mac_con[1],
+RK3228_RMII_MODE_MASK |
+RK3228_GMAC_PHY_INTF_SEL_MASK |
+RK3228_RXCLK_DLY_ENA_GMAC_MASK |
+RK3228_TXCLK_DLY_ENA_GMAC_MASK,
+RK3228_GMAC_PHY_INTF_SEL_RGMII |
+RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
+RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+   rk_clrsetreg(>mac_con[0],
+RK3228_CLK_RX_DL_CFG_GMAC_MASK |
+RK3228_CLK_TX_DL_CFG_GMAC_MASK,
+pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
+pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
struct rk3288_grf *grf;
@@ -448,6 +526,11 @@ const struct eth_ops gmac_rockchip_eth_ops = {
.write_hwaddr   = designware_eth_write_hwaddr,
 };
 
+const struct rk_gmac_ops rk3228_gmac_ops = {
+   .fix_mac_speed = rk3228_gmac_fix_mac_speed,
+   .set_to_rgmii = rk3228_gmac_set_to_rgmii,
+};
+
 const struct rk_gmac_ops rk3288_gmac_ops = {
.fix_mac_speed = rk3288_gmac_fix_mac_speed,
.set_to_rgmii = rk3288_gmac_set_to_rgmii,
@@ -474,6 +557,8 @@ const struct rk_gmac_ops rv1108_gmac_ops = {
 };
 
 static const struct udevice_id rockchip_gmac_ids[] = {
+   { .compatible = "rockchip,rk3228-gmac",
+ .data = (ulong)_gmac_ops },
{ .compatible = "rockchip,rk3288-gmac",
  .data = (ulong)_gmac_ops },
{ .compatible = "rockchip,rk3328-gmac",
-- 
2.7.4


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[U-Boot] [PATCH v3 19/20] clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and "assign-clock-rate"

[David Wu]

The RK3288 CRU-node assigns rates to a number of clocks that are not
implemented in the RK3288 clock-driver (but which have been
sufficiently initialised from rkclk_init()): for these clocks, we
implement the gmac clock set parent, but simply ignore the
others' set_rate() operation and return 0 to signal success.

Signed-off-by: David Wu 
---

Changes in v3:
- New patch

Changes in v2: None

 drivers/clk/rockchip/clk_rk3288.c  | 106 ++---
 include/dt-bindings/clock/rk3288-cru.h |   1 +
 2 files changed, 99 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3288.c 
b/drivers/clk/rockchip/clk_rk3288.c
index b64c107..baa8122 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -295,15 +295,42 @@ static int pll_para_config(ulong freq_hz, struct pll_div 
*div, uint *ext_div)
return 0;
 }
 
-static int rockchip_mac_set_clk(struct rk3288_cru *cru,
- int periph, uint freq)
+static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
 {
-   /* Assuming mac_clk is fed by an external clock */
-   rk_clrsetreg(>cru_clksel_con[21],
-RMII_EXTCLK_MASK,
-RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
+   ulong ret;
 
-return 0;
+   /*
+* The gmac clock can be derived either from an external clock
+* or can be generated from internally by a divider from SCLK_MAC.
+*/
+   if (readl(>cru_clksel_con[21]) & RMII_EXTCLK_MASK) {
+   /* An external clock will always generate the right rate... */
+   ret = freq;
+   } else {
+   u32 con = readl(>cru_clksel_con[21]);
+   ulong pll_rate;
+   u8 div;
+
+   if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
+   EMAC_PLL_SELECT_GENERAL)
+   pll_rate = GPLL_HZ;
+   else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
+EMAC_PLL_SELECT_CODEC)
+   pll_rate = CPLL_HZ;
+   else
+   pll_rate = NPLL_HZ;
+
+   div = DIV_ROUND_UP(pll_rate, freq) - 1;
+   if (div <= 0x1f)
+   rk_clrsetreg(>cru_clksel_con[21], MAC_DIV_CON_MASK,
+div << MAC_DIV_CON_SHIFT);
+   else
+   debug("Unsupported div for gmac:%d\n", div);
+
+   return DIV_TO_RATE(pll_rate, div);
+   }
+
+   return ret;
 }
 
 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
@@ -744,7 +771,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong 
rate)
break;
 #ifndef CONFIG_SPL_BUILD
case SCLK_MAC:
-   new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
+   new_rate = rockchip_mac_set_clk(priv->cru, rate);
break;
case DCLK_VOP0:
case DCLK_VOP1:
@@ -797,6 +824,17 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong 
rate)
case SCLK_SARADC:
new_rate = rockchip_saradc_set_clk(priv->cru, rate);
break;
+   case PLL_GPLL:
+   case PLL_CPLL:
+   case PLL_NPLL:
+   case ACLK_CPU:
+   case HCLK_CPU:
+   case PCLK_CPU:
+   case ACLK_PERI:
+   case HCLK_PERI:
+   case PCLK_PERI:
+   case SCLK_UART0:
+   return 0;
default:
return -ENOENT;
}
@@ -804,9 +842,61 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong 
rate)
return new_rate;
 }
 
+static int rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
+{
+   struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
+   struct rk3288_cru *cru = priv->cru;
+   const char *clock_output_name;
+   int ret;
+
+   /*
+* If the requested parent is in the same clock-controller and
+* the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
+* clock.
+*/
+   if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
+   debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
+   rk_clrsetreg(>cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
+   return 0;
+   }
+
+   /*
+* Otherwise, we need to check the clock-output-names of the
+* requested parent to see if the requested id is "ext_gmac".
+*/
+   ret = dev_read_string_index(parent->dev, "clock-output-names",
+   parent->id, _output_name);
+   if (ret < 0)
+   return -ENODATA;
+
+   /* If this is "ext_gmac", switch to the external clock input */
+   if (!strcmp(clock_output_name, "ext_gmac")) {
+   debug("%s: switching GMAC to external clock\n", __func__);
+   rk_clrsetreg(>cru_clksel_con[21], RMII_EXTCLK_MASK,

[U-Boot] [PATCH v3 14/20] rockchip: pinctrl: Add rk322x gmac pinctrl support

[David Wu]

Set gmac pins iomux and rgmii tx pins to 12ma drive-strength,
clean others to 2ma.

Signed-off-by: David Wu 
---

Changes in v3:
- adhere to the established way of writing this to avoid future confusion
- use defined symbolic constants for drive-strength

Changes in v2:
- New patch

 drivers/pinctrl/rockchip/pinctrl_rk322x.c | 148 ++
 1 file changed, 148 insertions(+)

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c 
b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
index 28d9996..354fea2 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk322x.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
@@ -470,6 +470,56 @@ enum {
CON_IOMUX_PWM0SEL_MASK  = 1 << CON_IOMUX_PWM0SEL_SHIFT,
 };
 
+/* GRF_GPIO2B_E */
+enum {
+   GRF_GPIO2B0_E_SHIFT = 0,
+   GRF_GPIO2B0_E_MASK = 3 << GRF_GPIO2B0_E_SHIFT,
+   GRF_GPIO2B1_E_SHIFT = 2,
+   GRF_GPIO2B1_E_MASK = 3 << GRF_GPIO2B1_E_SHIFT,
+   GRF_GPIO2B3_E_SHIFT = 6,
+   GRF_GPIO2B3_E_MASK = 3 << GRF_GPIO2B3_E_SHIFT,
+   GRF_GPIO2B4_E_SHIFT = 8,
+   GRF_GPIO2B4_E_MASK = 3 << GRF_GPIO2B4_E_SHIFT,
+   GRF_GPIO2B5_E_SHIFT = 10,
+   GRF_GPIO2B5_E_MASK = 3 << GRF_GPIO2B5_E_SHIFT,
+   GRF_GPIO2B6_E_SHIFT = 12,
+   GRF_GPIO2B6_E_MASK = 3 << GRF_GPIO2B6_E_SHIFT,
+};
+
+/* GRF_GPIO2C_E */
+enum {
+   GRF_GPIO2C0_E_SHIFT = 0,
+   GRF_GPIO2C0_E_MASK = 3 << GRF_GPIO2C0_E_SHIFT,
+   GRF_GPIO2C1_E_SHIFT = 2,
+   GRF_GPIO2C1_E_MASK = 3 << GRF_GPIO2C1_E_SHIFT,
+   GRF_GPIO2C2_E_SHIFT = 4,
+   GRF_GPIO2C2_E_MASK = 3 << GRF_GPIO2C2_E_SHIFT,
+   GRF_GPIO2C3_E_SHIFT = 6,
+   GRF_GPIO2C3_E_MASK = 3 << GRF_GPIO2C3_E_SHIFT,
+   GRF_GPIO2C4_E_SHIFT = 8,
+   GRF_GPIO2C4_E_MASK = 3 << GRF_GPIO2C4_E_SHIFT,
+   GRF_GPIO2C5_E_SHIFT = 10,
+   GRF_GPIO2C5_E_MASK = 3 << GRF_GPIO2C5_E_SHIFT,
+   GRF_GPIO2C6_E_SHIFT = 12,
+   GRF_GPIO2C6_E_MASK = 3 << GRF_GPIO2C6_E_SHIFT,
+   GRF_GPIO2C7_E_SHIFT = 14,
+   GRF_GPIO2C7_E_MASK = 3 << GRF_GPIO2C7_E_SHIFT,
+};
+
+/* GRF_GPIO2D_E */
+enum {
+   GRF_GPIO2D1_E_SHIFT = 2,
+   GRF_GPIO2D1_E_MASK = 3 << GRF_GPIO2D1_E_SHIFT,
+};
+
+/* GPIO Bias drive strength settings */
+enum GPIO_BIAS {
+   GPIO_BIAS_2MA = 0,
+   GPIO_BIAS_4MA,
+   GPIO_BIAS_8MA,
+   GPIO_BIAS_12MA,
+};
+
 struct rk322x_pinctrl_priv {
struct rk322x_grf *grf;
 };
@@ -633,6 +683,95 @@ static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf 
*grf, int mmc_id)
}
 }
 
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id)
+{
+   switch (gmac_id) {
+   case PERIPH_ID_GMAC:
+   /* set rgmii pins mux */
+   rk_clrsetreg(>gpio2b_iomux,
+GPIO2B0_MASK |
+GPIO2B1_MASK |
+GPIO2B3_MASK |
+GPIO2B4_MASK |
+GPIO2B5_MASK |
+GPIO2B6_MASK,
+GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT |
+GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT |
+GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT |
+GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT |
+GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT |
+GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT);
+
+   rk_clrsetreg(>gpio2c_iomux,
+GPIO2C0_MASK |
+GPIO2C1_MASK |
+GPIO2C2_MASK |
+GPIO2C3_MASK |
+GPIO2C4_MASK |
+GPIO2C5_MASK |
+GPIO2C6_MASK |
+GPIO2C7_MASK,
+GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT |
+GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT |
+GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT |
+GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT |
+GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT |
+GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT |
+GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT |
+GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT);
+
+   rk_clrsetreg(>gpio2d_iomux,
+GPIO2D1_MASK,
+GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT);
+
+   /*
+* set rgmii tx pins to 12ma drive-strength,
+* clean others with 2ma.
+*/
+   rk_clrsetreg(>gpio2_e[1],
+GRF_GPIO2B0_E_MASK |
+GRF_GPIO2B1_E_MASK |
+GRF_GPIO2B3_E_MASK |
+GRF_GPIO2B4_E_MASK |
+GRF_GPIO2B5_E_MASK |
+

[U-Boot] [PATCH v3 11/20] rockchip: dts: rk3328: Add gmac2io support

[David Wu]

Add basic dts configuration for rk3328 gmac2io.

Signed-off-by: David Wu 
---

Changes in v3:
- None

Changes in v2:
- New patch

 arch/arm/dts/rk3328.dtsi | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 0bab1e3..5de1059 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -456,6 +456,25 @@
status = "disabled";
};
 
+   gmac2io: ethernet@ff54 {
+   compatible = "rockchip,rk3328-gmac";
+   reg = <0x0 0xff54 0x0 0x1>;
+   rockchip,grf = <>;
+   interrupts = ;
+   interrupt-names = "macirq";
+   clocks = < SCLK_MAC2IO>, < SCLK_MAC2IO_RX>,
+< SCLK_MAC2IO_TX>, < SCLK_MAC2IO_REF>,
+< SCLK_MAC2IO_REFOUT>, < ACLK_MAC2IO>,
+< PCLK_MAC2IO>;
+   clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+   resets = < SRST_GMAC2IO_A>;
+   reset-names = "stmmaceth";
+   status = "disabled";
+   };
+
usb_host0_ehci: usb@ff5c {
compatible = "generic-ehci";
reg = <0x0 0xff5c 0x0 0x1>;
-- 
2.7.4


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[U-Boot] [PATCH v3 15/20] clk: rockchip: Add rk322x gamc clock support

[David Wu]

Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.

Signed-off-by: David Wu 
---

Changes in v3:
- Add "set parent" for gmac
- Add internal mac clk div_sel for gmac

Changes in v2:
- New patch

 drivers/clk/rockchip/clk_rk322x.c | 107 ++
 1 file changed, 107 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk322x.c 
b/drivers/clk/rockchip/clk_rk322x.c
index c8a2413..4e6d2f0 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -239,6 +239,41 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, 
uint clk_general_rate,
return DIV_TO_RATE(src_rate, div) / 2;
 }
 
+static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
+{
+   ulong ret;
+
+   /*
+* The gmac clock can be derived either from an external clock
+* or can be generated from internally by a divider from SCLK_MAC.
+*/
+   if (readl(>cru_clksel_con[5]) & BIT(5)) {
+   /* An external clock will always generate the right rate... */
+   ret = freq;
+   } else {
+   u32 con = readl(>cru_clksel_con[5]);
+   ulong pll_rate;
+   u8 div;
+
+   if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
+   pll_rate = GPLL_HZ;
+   else
+   /* CPLL is not set */
+   return -EPERM;
+
+   div = DIV_ROUND_UP(pll_rate, freq) - 1;
+   if (div <= 0x1f)
+   rk_clrsetreg(>cru_clksel_con[5], CLK_MAC_DIV_MASK,
+div << CLK_MAC_DIV_SHIFT);
+   else
+   debug("Unsupported div for gmac:%d\n", div);
+
+   return DIV_TO_RATE(pll_rate, div);
+   }
+
+   return ret;
+}
+
 static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint 
clk_general_rate,
  int periph, uint freq)
 {
@@ -352,6 +387,11 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong 
rate)
case CLK_DDR:
new_rate = rk322x_ddr_set_clk(priv->cru, rate);
break;
+   case SCLK_MAC:
+   new_rate = rk322x_mac_set_clk(priv->cru, rate);
+   break;
+   case PLL_GPLL:
+   return 0;
default:
return -ENOENT;
}
@@ -359,9 +399,76 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong 
rate)
return new_rate;
 }
 
+static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent)
+{
+   struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+   struct rk322x_cru *cru = priv->cru;
+
+   /*
+* If the requested parent is in the same clock-controller and the id
+* is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
+*/
+   if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
+   debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
+   rk_clrsetreg(>cru_clksel_con[5], BIT(5), 0);
+   return 0;
+   }
+
+   /*
+* If the requested parent is in the same clock-controller and the id
+* is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
+*/
+   if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
+   debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
+   rk_clrsetreg(>cru_clksel_con[5], BIT(5), BIT(5));
+   return 0;
+   }
+
+   return -EINVAL;
+}
+
+static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent)
+{
+   struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+   const char *clock_output_name;
+   struct rk322x_cru *cru = priv->cru;
+   int ret;
+
+   ret = dev_read_string_index(parent->dev, "clock-output-names",
+   parent->id, _output_name);
+   if (ret < 0)
+   return -ENODATA;
+
+   if (!strcmp(clock_output_name, "ext_gmac")) {
+   debug("%s: switching gmac extclk to ext_gmac\n", __func__);
+   rk_clrsetreg(>cru_clksel_con[29], BIT(10), 0);
+   return 0;
+   } else if (!strcmp(clock_output_name, "phy_50m_out")) {
+   debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
+   rk_clrsetreg(>cru_clksel_con[29], BIT(10), BIT(10));
+   return 0;
+   }
+
+   return -EINVAL;
+}
+
+static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+   switch (clk->id) {
+   case SCLK_MAC:
+   return rk322x_gmac_set_parent(clk, parent);
+   case SCLK_MAC_EXTCLK:
+   return rk322x_gmac_extclk_set_parent(clk, parent);
+   }
+
+   debug("%s: unsupported clk %ld\n", __func__, clk->id);
+   return -ENOENT;
+}
+
 static 

[U-Boot] [PATCH v3 13/20] rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver

[David Wu]

Clean the iomux definitions at grf_rk322x.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
After that, define the uart2 iomux at rk322x-board file.

Signed-off-by: David Wu 
---

Changes in v3:
- Fix the wrong define for uart2 iomux

Changes in v2:
- New patch

 arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 455 
 arch/arm/mach-rockchip/rk322x-board-spl.c   |  22 +-
 arch/arm/mach-rockchip/rk322x-board.c   |  18 +
 drivers/pinctrl/rockchip/pinctrl_rk322x.c   | 453 +++
 4 files changed, 492 insertions(+), 456 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
index c0c0d84..52e5a0a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
@@ -88,461 +88,6 @@ struct rk322x_sgrf {
unsigned int busdmac_con[4];
 };
 
-/* GRF_GPIO0A_IOMUX */
-enum {
-   GPIO0A7_SHIFT   = 14,
-   GPIO0A7_MASK= 3 << GPIO0A7_SHIFT,
-   GPIO0A7_GPIO= 0,
-   GPIO0A7_I2C3_SDA,
-   GPIO0A7_HDMI_DDCSDA,
-
-   GPIO0A6_SHIFT   = 12,
-   GPIO0A6_MASK= 3 << GPIO0A6_SHIFT,
-   GPIO0A6_GPIO= 0,
-   GPIO0A6_I2C3_SCL,
-   GPIO0A6_HDMI_DDCSCL,
-
-   GPIO0A3_SHIFT   = 6,
-   GPIO0A3_MASK= 3 << GPIO0A3_SHIFT,
-   GPIO0A3_GPIO= 0,
-   GPIO0A3_I2C1_SDA,
-   GPIO0A3_SDIO_CMD,
-
-   GPIO0A2_SHIFT   = 4,
-   GPIO0A2_MASK= 3 << GPIO0A2_SHIFT,
-   GPIO0A2_GPIO= 0,
-   GPIO0A2_I2C1_SCL,
-
-   GPIO0A1_SHIFT   = 2,
-   GPIO0A1_MASK= 3 << GPIO0A1_SHIFT,
-   GPIO0A1_GPIO= 0,
-   GPIO0A1_I2C0_SDA,
-
-   GPIO0A0_SHIFT   = 0,
-   GPIO0A0_MASK= 3 << GPIO0A0_SHIFT,
-   GPIO0A0_GPIO= 0,
-   GPIO0A0_I2C0_SCL,
-};
-
-/* GRF_GPIO0B_IOMUX */
-enum {
-   GPIO0B7_SHIFT   = 14,
-   GPIO0B7_MASK= 3 << GPIO0B7_SHIFT,
-   GPIO0B7_GPIO= 0,
-   GPIO0B7_HDMI_HDP,
-
-   GPIO0B6_SHIFT   = 12,
-   GPIO0B6_MASK= 3 << GPIO0B6_SHIFT,
-   GPIO0B6_GPIO= 0,
-   GPIO0B6_I2S_SDI,
-   GPIO0B6_SPI_CSN0,
-
-   GPIO0B5_SHIFT   = 10,
-   GPIO0B5_MASK= 3 << GPIO0B5_SHIFT,
-   GPIO0B5_GPIO= 0,
-   GPIO0B5_I2S_SDO,
-   GPIO0B5_SPI_RXD,
-
-   GPIO0B3_SHIFT   = 6,
-   GPIO0B3_MASK= 3 << GPIO0B3_SHIFT,
-   GPIO0B3_GPIO= 0,
-   GPIO0B3_I2S1_LRCKRX,
-   GPIO0B3_SPI_TXD,
-
-   GPIO0B1_SHIFT   = 2,
-   GPIO0B1_MASK= 3 << GPIO0B1_SHIFT,
-   GPIO0B1_GPIO= 0,
-   GPIO0B1_I2S_SCLK,
-   GPIO0B1_SPI_CLK,
-
-   GPIO0B0_SHIFT   = 0,
-   GPIO0B0_MASK= 3,
-   GPIO0B0_GPIO= 0,
-   GPIO0B0_I2S_MCLK,
-};
-
-/* GRF_GPIO0C_IOMUX */
-enum {
-   GPIO0C4_SHIFT   = 8,
-   GPIO0C4_MASK= 3 << GPIO0C4_SHIFT,
-   GPIO0C4_GPIO= 0,
-   GPIO0C4_HDMI_CECSDA,
-
-   GPIO0C1_SHIFT   = 2,
-   GPIO0C1_MASK= 3 << GPIO0C1_SHIFT,
-   GPIO0C1_GPIO= 0,
-   GPIO0C1_UART0_RSTN,
-   GPIO0C1_CLK_OUT1,
-};
-
-/* GRF_GPIO0D_IOMUX */
-enum {
-   GPIO0D6_SHIFT   = 12,
-   GPIO0D6_MASK= 3 << GPIO0D6_SHIFT,
-   GPIO0D6_GPIO= 0,
-   GPIO0D6_SDIO_PWREN,
-   GPIO0D6_PWM11,
-
-
-   GPIO0D4_SHIFT   = 8,
-   GPIO0D4_MASK= 3 << GPIO0D4_SHIFT,
-   GPIO0D4_GPIO= 0,
-   GPIO0D4_PWM2,
-
-   GPIO0D3_SHIFT   = 6,
-   GPIO0D3_MASK= 3 << GPIO0D3_SHIFT,
-   GPIO0D3_GPIO= 0,
-   GPIO0D3_PWM1,
-
-   GPIO0D2_SHIFT   = 4,
-   GPIO0D2_MASK= 3 << GPIO0D2_SHIFT,
-   GPIO0D2_GPIO= 0,
-   GPIO0D2_PWM0,
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
-   GPIO1A7_SHIFT   = 14,
-   GPIO1A7_MASK= 1,
-   GPIO1A7_GPIO= 0,
-   GPIO1A7_SDMMC_WRPRT,
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
-   GPIO1B7_SHIFT   = 14,
-   GPIO1B7_MASK= 3 << GPIO1B7_SHIFT,
-   GPIO1B7_GPIO= 0,
-   GPIO1B7_SDMMC_CMD,
-
-   GPIO1B6_SHIFT   = 12,
-   GPIO1B6_MASK= 3 << GPIO1B6_SHIFT,
-   GPIO1B6_GPIO= 0,
-   GPIO1B6_SDMMC_PWREN,
-
-   GPIO1B4_SHIFT   = 8,
-   GPIO1B4_MASK= 3 << GPIO1B4_SHIFT,
-   GPIO1B4_GPIO= 0,
-   GPIO1B4_SPI_CSN1,
-   GPIO1B4_PWM12,
-
-   GPIO1B3_SHIFT   = 6,
-   GPIO1B3_MASK= 3 << GPIO1B3_SHIFT,
-   GPIO1B3_GPIO= 0,

[U-Boot] [PATCH v3 10/20] rockchip: configs: Enable GMAC configs for evb-rk3328

[David Wu]

Enable GMAC configs for evb-rk3328

Signed-off-by: David Wu 
---

Changes in v3:
- None

Changes in v2:
- New patch

 configs/evb-rk3328_defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 3b8b104..3d8c04d 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -17,6 +17,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
@@ -24,6 +25,10 @@ CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_ROCKCHIP_RK3328=y
 CONFIG_DM_PMIC=y
-- 
2.7.4


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[U-Boot] [PATCH v3 09/20] net: gmac_rockchip: Add rk3328 gmac support

[David Wu]

The GMAC2IO in the RK3328 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.

This adds the RK3328-specific logic necessary to reuse this driver.

Signed-off-by: David Wu 
---

Changes in v3:
- None

Changes in v2:
- New patch

 drivers/net/gmac_rockchip.c | 85 +
 1 file changed, 85 insertions(+)

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index cfffe29..551c230 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -94,6 +95,39 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
 }
 
+static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+   struct rk3328_grf_regs *grf;
+   int clk;
+   enum {
+   RK3328_GMAC_CLK_SEL_SHIFT = 11,
+   RK3328_GMAC_CLK_SEL_MASK  = GENMASK(12, 11),
+   RK3328_GMAC_CLK_SEL_125M  = 0 << 11,
+   RK3328_GMAC_CLK_SEL_25M   = 3 << 11,
+   RK3328_GMAC_CLK_SEL_2_5M  = 2 << 11,
+   };
+
+   switch (priv->phydev->speed) {
+   case 10:
+   clk = RK3328_GMAC_CLK_SEL_2_5M;
+   break;
+   case 100:
+   clk = RK3328_GMAC_CLK_SEL_25M;
+   break;
+   case 1000:
+   clk = RK3328_GMAC_CLK_SEL_125M;
+   break;
+   default:
+   debug("Unknown phy speed: %d\n", priv->phydev->speed);
+   return -EINVAL;
+   }
+
+   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   rk_clrsetreg(>mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
+
+   return 0;
+}
+
 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
struct rk3368_grf *grf;
@@ -207,6 +241,50 @@ static void rk3288_gmac_set_to_rgmii(struct 
gmac_rockchip_platdata *pdata)
 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
 }
 
+static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+   struct rk3328_grf_regs *grf;
+   enum {
+   RK3328_RMII_MODE_SHIFT = 9,
+   RK3328_RMII_MODE_MASK  = BIT(9),
+
+   RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
+   RK3328_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
+   RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+   RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+   RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+   RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+   RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+   RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+   RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+   };
+   enum {
+   RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+   RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+   RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+   RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+   };
+
+   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   rk_clrsetreg(>mac_con[1],
+RK3328_RMII_MODE_MASK |
+RK3328_GMAC_PHY_INTF_SEL_MASK |
+RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+RK3328_TXCLK_DLY_ENA_GMAC_MASK,
+RK3328_GMAC_PHY_INTF_SEL_RGMII |
+RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+   rk_clrsetreg(>mac_con[0],
+RK3328_CLK_RX_DL_CFG_GMAC_MASK |
+RK3328_CLK_TX_DL_CFG_GMAC_MASK,
+pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
+pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
struct rk3368_grf *grf;
@@ -375,6 +453,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = {
.set_to_rgmii = rk3288_gmac_set_to_rgmii,
 };
 
+const struct rk_gmac_ops rk3328_gmac_ops = {
+   .fix_mac_speed = rk3328_gmac_fix_mac_speed,
+   .set_to_rgmii = rk3328_gmac_set_to_rgmii,
+};
+
 const struct rk_gmac_ops rk3368_gmac_ops = {
.fix_mac_speed = rk3368_gmac_fix_mac_speed,
.set_to_rgmii = rk3368_gmac_set_to_rgmii,
@@ -393,6 +476,8 @@ const struct rk_gmac_ops rv1108_gmac_ops = {
 static const struct udevice_id rockchip_gmac_ids[] = {
{ .compatible = "rockchip,rk3288-gmac",
  .data = (ulong)_gmac_ops },
+   { .compatible = "rockchip,rk3328-gmac",
+ .data = (ulong)_gmac_ops },
{ .compatible = "rockchip,rk3368-gmac",
  .data = (ulong)_gmac_ops },
{ .compatible = "rockchip,rk3399-gmac",
-- 
2.7.4


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[U-Boot] [PATCH v3 08/20] clk: rockchip: Add rk3328 gamc clock support

[David Wu]

The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.

Signed-off-by: David Wu 
---

Changes in v3:
- Add "set parent" for gmac2io
- Add internal mac clk div_sel for gmac2io

Changes in v2:
- New patch

 drivers/clk/rockchip/clk_rk3328.c  | 178 +
 include/dt-bindings/clock/rk3328-cru.h |   6 +-
 2 files changed, 181 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3328.c 
b/drivers/clk/rockchip/clk_rk3328.c
index fa0c777..2ccc798 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -94,6 +95,14 @@ enum {
PCLK_DBG_DIV_SHIFT  = 0,
PCLK_DBG_DIV_MASK   = 0xF << PCLK_DBG_DIV_SHIFT,
 
+   /* CLKSEL_CON27 */
+   GMAC2IO_PLL_SEL_SHIFT   = 7,
+   GMAC2IO_PLL_SEL_MASK= 1 << GMAC2IO_PLL_SEL_SHIFT,
+   GMAC2IO_PLL_SEL_CPLL= 0,
+   GMAC2IO_PLL_SEL_GPLL= 1,
+   GMAC2IO_CLK_DIV_MASK= 0x1f,
+   GMAC2IO_CLK_DIV_SHIFT   = 0,
+
/* CLKSEL_CON28 */
ACLK_PERIHP_PLL_SEL_CPLL= 0,
ACLK_PERIHP_PLL_SEL_GPLL,
@@ -393,6 +402,44 @@ static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, 
ulong clk_id, uint hz)
return DIV_TO_RATE(GPLL_HZ, src_clk_div);
 }
 
+static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
+{
+   struct rk3328_grf_regs *grf;
+   ulong ret;
+
+   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+   /*
+* The RGMII CLK can be derived either from an external "clkin"
+* or can be generated from internally by a divider from SCLK_MAC.
+*/
+   if (readl(>mac_con[1]) & BIT(10) &&
+   readl(>soc_con[4]) & BIT(14)) {
+   /* An external clock will always generate the right rate... */
+   ret = rate;
+   } else {
+   u32 con = readl(>clksel_con[27]);
+   ulong pll_rate;
+   u8 div;
+
+   if ((con >> GMAC2IO_PLL_SEL_SHIFT) & GMAC2IO_PLL_SEL_GPLL)
+   pll_rate = GPLL_HZ;
+   else
+   pll_rate = CPLL_HZ;
+
+   div = DIV_ROUND_UP(pll_rate, rate) - 1;
+   if (div <= 0x1f)
+   rk_clrsetreg(>clksel_con[27], GMAC2IO_CLK_DIV_MASK,
+div << GMAC2IO_CLK_DIV_SHIFT);
+   else
+   debug("Unsupported div for gmac:%d\n", div);
+
+   return DIV_TO_RATE(pll_rate, div);
+   }
+
+   return ret;
+}
+
 static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
 {
u32 div, con, con_id;
@@ -558,12 +605,48 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong 
rate)
case SCLK_I2C3:
ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
break;
+   case SCLK_MAC2IO:
+   ret = rk3328_gmac2io_set_clk(priv->cru, rate);
+   break;
case SCLK_PWM:
ret = rk3328_pwm_set_clk(priv->cru, rate);
break;
case SCLK_SARADC:
ret = rk3328_saradc_set_clk(priv->cru, rate);
break;
+   case DCLK_LCDC:
+   case SCLK_PDM:
+   case SCLK_RTC32K:
+   case SCLK_UART0:
+   case SCLK_UART1:
+   case SCLK_UART2:
+   case SCLK_SDIO:
+   case SCLK_TSP:
+   case SCLK_WIFI:
+   case ACLK_BUS_PRE:
+   case HCLK_BUS_PRE:
+   case PCLK_BUS_PRE:
+   case ACLK_PERI_PRE:
+   case HCLK_PERI:
+   case PCLK_PERI:
+   case ACLK_VIO_PRE:
+   case HCLK_VIO_PRE:
+   case ACLK_RGA_PRE:
+   case SCLK_RGA:
+   case ACLK_VOP_PRE:
+   case ACLK_RKVDEC_PRE:
+   case ACLK_RKVENC:
+   case ACLK_VPU_PRE:
+   case SCLK_VDEC_CABAC:
+   case SCLK_VDEC_CORE:
+   case SCLK_VENC_CORE:
+   case SCLK_VENC_DSP:
+   case SCLK_EFUSE:
+   case PCLK_DDR:
+   case ACLK_GMAC:
+   case PCLK_GMAC:
+   case SCLK_USB3OTG_SUSPEND:
+   return 0;
default:
return -ENOENT;
}
@@ -571,9 +654,104 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong 
rate)
return ret;
 }
 
+static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
+{
+   struct rk3328_grf_regs *grf;
+   const char *clock_output_name;
+   int ret;
+
+   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+   /*
+* If the requested parent is in the same clock-controller and the id
+* is SCLK_MAC2IO_SRC ("clk_mac2io_src"), switch to the internal clock.
+*/
+   if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO_SRC)) {
+   debug("%s: switching RGMII to 

[U-Boot] [PATCH v3 06/20] rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver

[David Wu]

Clean the iomux definitions at grf_rk3328.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.

Signed-off-by: David Wu 
---

Changes in v3:
- None

Changes in v2:
- New patch

 arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 113 
 drivers/pinctrl/rockchip/pinctrl_rk3328.c   | 113 
 2 files changed, 113 insertions(+), 113 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
index f0a0781..0c37f2a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -131,118 +131,5 @@ struct rk3328_sgrf_regs {
 };
 check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
 
-enum {
-   /* GPIO0A_IOMUX */
-   GPIO0A5_SEL_SHIFT   = 10,
-   GPIO0A5_SEL_MASK= 3 << GPIO0A5_SEL_SHIFT,
-   GPIO0A5_I2C3_SCL= 2,
-
-   GPIO0A6_SEL_SHIFT   = 12,
-   GPIO0A6_SEL_MASK= 3 << GPIO0A6_SEL_SHIFT,
-   GPIO0A6_I2C3_SDA= 2,
-
-   GPIO0A7_SEL_SHIFT   = 14,
-   GPIO0A7_SEL_MASK= 3 << GPIO0A7_SEL_SHIFT,
-   GPIO0A7_EMMC_DATA0  = 2,
-
-   /* GPIO0D_IOMUX*/
-   GPIO0D6_SEL_SHIFT   = 12,
-   GPIO0D6_SEL_MASK= 3 << GPIO0D6_SEL_SHIFT,
-   GPIO0D6_GPIO= 0,
-   GPIO0D6_SDMMC0_PWRENM1  = 3,
-
-   /* GPIO1A_IOMUX */
-   GPIO1A0_SEL_SHIFT   = 0,
-   GPIO1A0_SEL_MASK= 0x3fff << GPIO1A0_SEL_SHIFT,
-   GPIO1A0_CARD_DATA_CLK_CMD_DETN  = 0x1555,
-
-   /* GPIO2A_IOMUX */
-   GPIO2A0_SEL_SHIFT   = 0,
-   GPIO2A0_SEL_MASK= 3 << GPIO2A0_SEL_SHIFT,
-   GPIO2A0_UART2_TX_M1 = 1,
-
-   GPIO2A1_SEL_SHIFT   = 2,
-   GPIO2A1_SEL_MASK= 3 << GPIO2A1_SEL_SHIFT,
-   GPIO2A1_UART2_RX_M1 = 1,
-
-   GPIO2A2_SEL_SHIFT   = 4,
-   GPIO2A2_SEL_MASK= 3 << GPIO2A2_SEL_SHIFT,
-   GPIO2A2_PWM_IR  = 1,
-
-   GPIO2A4_SEL_SHIFT   = 8,
-   GPIO2A4_SEL_MASK= 3 << GPIO2A4_SEL_SHIFT,
-   GPIO2A4_PWM_0   = 1,
-   GPIO2A4_I2C1_SDA,
-
-   GPIO2A5_SEL_SHIFT   = 10,
-   GPIO2A5_SEL_MASK= 3 << GPIO2A5_SEL_SHIFT,
-   GPIO2A5_PWM_1   = 1,
-   GPIO2A5_I2C1_SCL,
-
-   GPIO2A6_SEL_SHIFT   = 12,
-   GPIO2A6_SEL_MASK= 3 << GPIO2A6_SEL_SHIFT,
-   GPIO2A6_PWM_2   = 1,
-
-   GPIO2A7_SEL_SHIFT   = 14,
-   GPIO2A7_SEL_MASK= 3 << GPIO2A7_SEL_SHIFT,
-   GPIO2A7_GPIO= 0,
-   GPIO2A7_SDMMC0_PWRENM0,
-
-   /* GPIO2BL_IOMUX */
-   GPIO2BL0_SEL_SHIFT  = 0,
-   GPIO2BL0_SEL_MASK   = 0x3f << GPIO2BL0_SEL_SHIFT,
-   GPIO2BL0_SPI_CLK_TX_RX_M0   = 0x15,
-
-   GPIO2BL3_SEL_SHIFT  = 6,
-   GPIO2BL3_SEL_MASK   = 3 << GPIO2BL3_SEL_SHIFT,
-   GPIO2BL3_SPI_CSN0_M0= 1,
-
-   GPIO2BL4_SEL_SHIFT  = 8,
-   GPIO2BL4_SEL_MASK   = 3 << GPIO2BL4_SEL_SHIFT,
-   GPIO2BL4_SPI_CSN1_M0= 1,
-
-   GPIO2BL5_SEL_SHIFT  = 10,
-   GPIO2BL5_SEL_MASK   = 3 << GPIO2BL5_SEL_SHIFT,
-   GPIO2BL5_I2C2_SDA   = 1,
-
-   GPIO2BL6_SEL_SHIFT  = 12,
-   GPIO2BL6_SEL_MASK   = 3 << GPIO2BL6_SEL_SHIFT,
-   GPIO2BL6_I2C2_SCL   = 1,
-
-   /* GPIO2D_IOMUX */
-   GPIO2D0_SEL_SHIFT   = 0,
-   GPIO2D0_SEL_MASK= 3 << GPIO2D0_SEL_SHIFT,
-   GPIO2D0_I2C0_SCL= 1,
-
-   GPIO2D1_SEL_SHIFT   = 2,
-   GPIO2D1_SEL_MASK= 3 << GPIO2D1_SEL_SHIFT,
-   GPIO2D1_I2C0_SDA= 1,
-
-   GPIO2D4_SEL_SHIFT   = 8,
-   GPIO2D4_SEL_MASK= 0xff << GPIO2D4_SEL_SHIFT,
-   GPIO2D4_EMMC_DATA1234   = 0xaa,
-
-   /* GPIO3C_IOMUX */
-   GPIO3C0_SEL_SHIFT   = 0,
-   GPIO3C0_SEL_MASK= 0x3fff << GPIO3C0_SEL_SHIFT,
-   GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD   = 0x2aaa,
-
-   /* COM_IOMUX */
-   IOMUX_SEL_UART2_SHIFT   = 0,
-   IOMUX_SEL_UART2_MASK= 3 << IOMUX_SEL_UART2_SHIFT,
-   IOMUX_SEL_UART2_M0  = 0,
-   IOMUX_SEL_UART2_M1,
-
-   IOMUX_SEL_SPI_SHIFT = 4,
-   IOMUX_SEL_SPI_MASK  = 3 << IOMUX_SEL_SPI_SHIFT,
-   IOMUX_SEL_SPI_M0= 0,
-   IOMUX_SEL_SPI_M1,
-   IOMUX_SEL_SPI_M2,
-
-   IOMUX_SEL_SDMMC_SHIFT   = 7,
-   IOMUX_SEL_SDMMC_MASK= 1 << IOMUX_SEL_SDMMC_SHIFT,
-   IOMUX_SEL_SDMMC_M0  = 0,
-   IOMUX_SEL_SDMMC_M1,
-};
 
 #endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c 
b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index c74163e..3c2253f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -17,6 +17,119 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+enum {
+   /* GPIO0A_IOMUX */
+   GPIO0A5_SEL_SHIFT   = 10,
+   GPIO0A5_SEL_MASK  

[U-Boot] [PATCH v3 07/20] rockchip: pinctrl: Add rk3328 gmac pinctrl support

[David Wu]

Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2
and bit10 at com iomux register. After that, set rgmii m1 tx
pins to 12ma drive-strength, and clean others to 2ma.

Signed-off-by: David Wu 
---

Changes in v3:
- adhere to the established way of writing this to avoid future confusion
- use defined symbolic constants for drive-strength

Changes in v2:
- New patch

 arch/arm/include/asm/arch-rockchip/grf_rk3328.h |   1 -
 drivers/pinctrl/rockchip/pinctrl_rk3328.c   | 275 
 2 files changed, 275 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
index 0c37f2a..2776cef 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -131,5 +131,4 @@ struct rk3328_sgrf_regs {
 };
 check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
 
-
 #endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c 
b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index 3c2253f..fa2356a 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -31,6 +31,37 @@ enum {
GPIO0A7_SEL_MASK= 3 << GPIO0A7_SEL_SHIFT,
GPIO0A7_EMMC_DATA0  = 2,
 
+   /* GPIO0B_IOMUX*/
+   GPIO0B0_SEL_SHIFT   = 0,
+   GPIO0B0_SEL_MASK= 3 << GPIO0B0_SEL_SHIFT,
+   GPIO0B0_GAMC_CLKTXM0= 1,
+
+   GPIO0B4_SEL_SHIFT   = 8,
+   GPIO0B4_SEL_MASK= 3 << GPIO0B4_SEL_SHIFT,
+   GPIO0B4_GAMC_TXENM0 = 1,
+
+   /* GPIO0C_IOMUX*/
+   GPIO0C0_SEL_SHIFT   = 0,
+   GPIO0C0_SEL_MASK= 3 << GPIO0C0_SEL_SHIFT,
+   GPIO0C0_GAMC_TXD1M0 = 1,
+
+   GPIO0C1_SEL_SHIFT   = 2,
+   GPIO0C1_SEL_MASK= 3 << GPIO0C1_SEL_SHIFT,
+   GPIO0C1_GAMC_TXD0M0 = 1,
+
+   GPIO0C6_SEL_SHIFT   = 12,
+   GPIO0C6_SEL_MASK= 3 << GPIO0C6_SEL_SHIFT,
+   GPIO0C6_GAMC_TXD2M0 = 1,
+
+   GPIO0C7_SEL_SHIFT   = 14,
+   GPIO0C7_SEL_MASK= 3 << GPIO0C7_SEL_SHIFT,
+   GPIO0C7_GAMC_TXD3M0 = 1,
+
+   /* GPIO0D_IOMUX*/
+   GPIO0D0_SEL_SHIFT   = 0,
+   GPIO0D0_SEL_MASK= 3 << GPIO0D0_SEL_SHIFT,
+   GPIO0D0_GMAC_CLKM0  = 1,
+
GPIO0D6_SEL_SHIFT   = 12,
GPIO0D6_SEL_MASK= 3 << GPIO0D6_SEL_SHIFT,
GPIO0D6_GPIO= 0,
@@ -41,6 +72,69 @@ enum {
GPIO1A0_SEL_MASK= 0x3fff << GPIO1A0_SEL_SHIFT,
GPIO1A0_CARD_DATA_CLK_CMD_DETN  = 0x1555,
 
+   /* GPIO1B_IOMUX */
+   GPIO1B0_SEL_SHIFT   = 0,
+   GPIO1B0_SEL_MASK= 3 << GPIO1B0_SEL_SHIFT,
+   GPIO1B0_GMAC_TXD1M1 = 2,
+
+   GPIO1B1_SEL_SHIFT   = 2,
+   GPIO1B1_SEL_MASK= 3 << GPIO1B1_SEL_SHIFT,
+   GPIO1B1_GMAC_TXD0M1 = 2,
+
+   GPIO1B2_SEL_SHIFT   = 4,
+   GPIO1B2_SEL_MASK= 3 << GPIO1B2_SEL_SHIFT,
+   GPIO1B2_GMAC_RXD1M1 = 2,
+
+   GPIO1B3_SEL_SHIFT   = 6,
+   GPIO1B3_SEL_MASK= 3 << GPIO1B3_SEL_SHIFT,
+   GPIO1B3_GMAC_RXD0M1 = 2,
+
+   GPIO1B4_SEL_SHIFT   = 8,
+   GPIO1B4_SEL_MASK= 3 << GPIO1B4_SEL_SHIFT,
+   GPIO1B4_GMAC_TXCLKM1= 2,
+
+   GPIO1B5_SEL_SHIFT   = 10,
+   GPIO1B5_SEL_MASK= 3 << GPIO1B5_SEL_SHIFT,
+   GPIO1B5_GMAC_RXCLKM1= 2,
+
+   GPIO1B6_SEL_SHIFT   = 12,
+   GPIO1B6_SEL_MASK= 3 << GPIO1B6_SEL_SHIFT,
+   GPIO1B6_GMAC_RXD3M1 = 2,
+
+   GPIO1B7_SEL_SHIFT   = 14,
+   GPIO1B7_SEL_MASK= 3 << GPIO1B7_SEL_SHIFT,
+   GPIO1B7_GMAC_RXD2M1 = 2,
+
+   /* GPIO1C_IOMUX */
+   GPIO1C0_SEL_SHIFT   = 0,
+   GPIO1C0_SEL_MASK= 3 << GPIO1C0_SEL_SHIFT,
+   GPIO1C0_GMAC_TXD3M1 = 2,
+
+   GPIO1C1_SEL_SHIFT   = 2,
+   GPIO1C1_SEL_MASK= 3 << GPIO1C1_SEL_SHIFT,
+   GPIO1C1_GMAC_TXD2M1 = 2,
+
+   GPIO1C3_SEL_SHIFT   = 6,
+   GPIO1C3_SEL_MASK= 3 << GPIO1C3_SEL_SHIFT,
+   GPIO1C3_GMAC_MDIOM1 = 2,
+
+   GPIO1C5_SEL_SHIFT   = 10,
+   GPIO1C5_SEL_MASK= 3 << GPIO1C5_SEL_SHIFT,
+   GPIO1C5_GMAC_CLKM1  = 2,
+
+   GPIO1C6_SEL_SHIFT   = 12,
+   GPIO1C6_SEL_MASK= 3 << GPIO1C6_SEL_SHIFT,
+   GPIO1C6_GMAC_RXDVM1 = 2,
+
+   GPIO1C7_SEL_SHIFT   = 14,
+   GPIO1C7_SEL_MASK= 3 << GPIO1C7_SEL_SHIFT,
+   GPIO1C7_GMAC_MDCM1  = 2,
+
+   /* GPIO1D_IOMUX */
+   GPIO1D1_SEL_SHIFT   = 2,
+   GPIO1D1_SEL_MASK= 3 << GPIO1D1_SEL_SHIFT,
+   GPIO1D1_GMAC_TXENM1 = 2,
+
/* GPIO2A_IOMUX */
GPIO2A0_SEL_SHIFT   = 0,
GPIO2A0_SEL_MASK= 3 << GPIO2A0_SEL_SHIFT,
@@ -118,6 +212,11 @@ enum {
IOMUX_SEL_UART2_M0  = 0,
IOMUX_SEL_UART2_M1,
 
+   IOMUX_SEL_GMAC_SHIFT= 2,
+ 

[U-Boot] [PATCH v3 05/20] net: gmac_rockchip: Add support for the RV1108 GMAC

[David Wu]

The rv1108 GMAC only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops. At the same time, need to set the mac clock rate of
rmii with 50M, the clock rate of rgmii with 125M.

Signed-off-by: David Wu 
---

Changes in v3:
- return error if there was no set_to_rgmii ops at rgmii case
- return error if there was no set_to_rmii ops at rmii case
- set and check clock rate when gmac clock is internal pll.

Changes in v2:
- Add check whether the set rgmii/rmii function is a valid function pointer
- Clean the grf offset at gmac_rockchip.c
- Use current phy interface to set mac clock rate

 drivers/net/gmac_rockchip.c | 115 +---
 1 file changed, 109 insertions(+), 6 deletions(-)

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 586ccbf..cfffe29 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "designware.h"
@@ -31,12 +32,14 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 struct gmac_rockchip_platdata {
struct dw_eth_pdata dw_eth_pdata;
+   bool clock_input;
int tx_delay;
int rx_delay;
 };
 
 struct rk_gmac_ops {
int (*fix_mac_speed)(struct dw_eth_dev *priv);
+   void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
 };
 
@@ -44,6 +47,13 @@ struct rk_gmac_ops {
 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
 {
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+   const char *string;
+
+   string = dev_read_string(dev, "clock_in_out");
+   if (!strcmp(string, "input"))
+   pdata->clock_input = true;
+   else
+   pdata->clock_input = false;
 
/* Check the new naming-style first... */
pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
@@ -142,6 +152,41 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev 
*priv)
return 0;
 }
 
+static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
+{
+   struct rv1108_grf *grf;
+   int clk, speed;
+   enum {
+   RV1108_GMAC_SPEED_MASK  = BIT(2),
+   RV1108_GMAC_SPEED_10M   = 0 << 2,
+   RV1108_GMAC_SPEED_100M  = 1 << 2,
+   RV1108_GMAC_CLK_SEL_MASK= BIT(7),
+   RV1108_GMAC_CLK_SEL_2_5M= 0 << 7,
+   RV1108_GMAC_CLK_SEL_25M = 1 << 7,
+   };
+
+   switch (priv->phydev->speed) {
+   case 10:
+   clk = RV1108_GMAC_CLK_SEL_2_5M;
+   speed = RV1108_GMAC_SPEED_10M;
+   break;
+   case 100:
+   clk = RV1108_GMAC_CLK_SEL_25M;
+   speed = RV1108_GMAC_SPEED_100M;
+   break;
+   default:
+   debug("Unknown phy speed: %d\n", priv->phydev->speed);
+   return -EINVAL;
+   }
+
+   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   rk_clrsetreg(>gmac_con0,
+RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
+clk | speed);
+
+   return 0;
+}
+
 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
struct rk3288_grf *grf;
@@ -221,25 +266,76 @@ static void rk3399_gmac_set_to_rgmii(struct 
gmac_rockchip_platdata *pdata)
 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
 }
 
+static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+   struct rv1108_grf *grf;
+
+   enum {
+   RV1108_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
+   RV1108_GMAC_PHY_INTF_SEL_RMII  = 4 << 4,
+   };
+
+   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   rk_clrsetreg(>gmac_con0,
+RV1108_GMAC_PHY_INTF_SEL_MASK,
+RV1108_GMAC_PHY_INTF_SEL_RMII);
+}
+
 static int gmac_rockchip_probe(struct udevice *dev)
 {
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
struct rk_gmac_ops *ops =
(struct rk_gmac_ops *)dev_get_driver_data(dev);
+   struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+   struct eth_pdata *eth_pdata = _pdata->eth_pdata;
struct clk clk;
+   ulong rate;
int ret;
 
ret = clk_get_by_index(dev, 0, );
if (ret)
return ret;
 
-   /* Since mac_clk is fed by an external clock we can use 0 here */
-   ret = clk_set_rate(, 0);
-   if (ret)
-   return ret;
+   switch (eth_pdata->phy_interface) {
+   case PHY_INTERFACE_MODE_RGMII:
+   /*
+* If the gmac clock is from internal pll, need to set and
+* check the return value for gmac clock at RGMII mode. If
+* the gmac clock is from 

[U-Boot] [PATCH v3 02/20] rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb

[David Wu]

If the Ethernet address is not set, the network can't work,
enable the random address config for default use.

Signed-off-by: David Wu 
Acked-by: Philipp Tomsich 
Reviewed-by: Philipp Tomsich 
---

Changes in v3:
- None

Changes in v2:
- None

 configs/evb-rk3288_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index e944f97..6c67509 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -32,6 +32,7 @@ CONFIG_SPL_PARTITION_UUIDS=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
-- 
2.7.4


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[U-Boot] [PATCH v3 04/20] rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver

[David Wu]

If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the
conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h,
and move them into pinctrl-driver.

Signed-off-by: David Wu 
Reviewed-by: Philipp Tomsich 
---

Changes in v3:
- Fix the wrong define for uart2M0

Changes in v2:
- New patch

 arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 399 
 board/rockchip/evb_rv1108/evb_rv1108.c  |  17 +
 drivers/pinctrl/rockchip/pinctrl_rv1108.c   | 399 
 3 files changed, 416 insertions(+), 399 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h 
b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
index 428cf6a..76e742b 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
@@ -111,403 +111,4 @@ struct rv1108_grf {
 };
 
 check_member(rv1108_grf, chip_id, 0x0c00);
-
-/* GRF_GPIO1B_IOMUX */
-enum {
-   GPIO1B7_SHIFT   = 14,
-   GPIO1B7_MASK= 3 << GPIO1B7_SHIFT,
-   GPIO1B7_GPIO= 0,
-   GPIO1B7_LCDC_D12,
-   GPIO1B7_I2S_SDIO2_M0,
-   GPIO1B7_GMAC_RXDV,
-
-   GPIO1B6_SHIFT   = 12,
-   GPIO1B6_MASK= 3 << GPIO1B6_SHIFT,
-   GPIO1B6_GPIO= 0,
-   GPIO1B6_LCDC_D13,
-   GPIO1B6_I2S_LRCLKTX_M0,
-   GPIO1B6_GMAC_RXD1,
-
-   GPIO1B5_SHIFT   = 10,
-   GPIO1B5_MASK= 3 << GPIO1B5_SHIFT,
-   GPIO1B5_GPIO= 0,
-   GPIO1B5_LCDC_D14,
-   GPIO1B5_I2S_SDIO1_M0,
-   GPIO1B5_GMAC_RXD0,
-
-   GPIO1B4_SHIFT   = 8,
-   GPIO1B4_MASK= 3 << GPIO1B4_SHIFT,
-   GPIO1B4_GPIO= 0,
-   GPIO1B4_LCDC_D15,
-   GPIO1B4_I2S_MCLK_M0,
-   GPIO1B4_GMAC_TXEN,
-
-   GPIO1B3_SHIFT   = 6,
-   GPIO1B3_MASK= 3 << GPIO1B3_SHIFT,
-   GPIO1B3_GPIO= 0,
-   GPIO1B3_LCDC_D16,
-   GPIO1B3_I2S_SCLK_M0,
-   GPIO1B3_GMAC_TXD1,
-
-   GPIO1B2_SHIFT   = 4,
-   GPIO1B2_MASK= 3 << GPIO1B2_SHIFT,
-   GPIO1B2_GPIO= 0,
-   GPIO1B2_LCDC_D17,
-   GPIO1B2_I2S_SDIO_M0,
-   GPIO1B2_GMAC_TXD0,
-
-   GPIO1B1_SHIFT   = 2,
-   GPIO1B1_MASK= 3 << GPIO1B1_SHIFT,
-   GPIO1B1_GPIO= 0,
-   GPIO1B1_LCDC_D9,
-   GPIO1B1_PWM7,
-
-   GPIO1B0_SHIFT   = 0,
-   GPIO1B0_MASK= 3,
-   GPIO1B0_GPIO= 0,
-   GPIO1B0_LCDC_D8,
-   GPIO1B0_PWM6,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
-   GPIO1C7_SHIFT   = 14,
-   GPIO1C7_MASK= 3 << GPIO1C7_SHIFT,
-   GPIO1C7_GPIO= 0,
-   GPIO1C7_CIF_D5,
-   GPIO1C7_I2S_SDIO2_M1,
-
-   GPIO1C6_SHIFT   = 12,
-   GPIO1C6_MASK= 3 << GPIO1C6_SHIFT,
-   GPIO1C6_GPIO= 0,
-   GPIO1C6_CIF_D4,
-   GPIO1C6_I2S_LRCLKTX_M1,
-
-   GPIO1C5_SHIFT   = 10,
-   GPIO1C5_MASK= 3 << GPIO1C5_SHIFT,
-   GPIO1C5_GPIO= 0,
-   GPIO1C5_LCDC_CLK,
-   GPIO1C5_GMAC_CLK,
-
-   GPIO1C4_SHIFT   = 8,
-   GPIO1C4_MASK= 3 << GPIO1C4_SHIFT,
-   GPIO1C4_GPIO= 0,
-   GPIO1C4_LCDC_HSYNC,
-   GPIO1C4_GMAC_MDC,
-
-   GPIO1C3_SHIFT   = 6,
-   GPIO1C3_MASK= 3 << GPIO1C3_SHIFT,
-   GPIO1C3_GPIO= 0,
-   GPIO1C3_LCDC_VSYNC,
-   GPIO1C3_GMAC_MDIO,
-
-   GPIO1C2_SHIFT   = 4,
-   GPIO1C2_MASK= 3 << GPIO1C2_SHIFT,
-   GPIO1C2_GPIO= 0,
-   GPIO1C2_LCDC_EN,
-   GPIO1C2_I2S_SDIO3_M0,
-   GPIO1C2_GMAC_RXER,
-
-   GPIO1C1_SHIFT   = 2,
-   GPIO1C1_MASK= 3 << GPIO1C1_SHIFT,
-   GPIO1C1_GPIO= 0,
-   GPIO1C1_LCDC_D10,
-   GPIO1C1_I2S_SDI_M0,
-   GPIO1C1_PWM4,
-
-   GPIO1C0_SHIFT   = 0,
-   GPIO1C0_MASK= 3,
-   GPIO1C0_GPIO= 0,
-   GPIO1C0_LCDC_D11,
-   GPIO1C0_I2S_LRCLKRX_M0,
-};
-
-/* GRF_GPIO1D_OIMUX */
-enum {
-   GPIO1D7_SHIFT   = 14,
-   GPIO1D7_MASK= 3 << GPIO1D7_SHIFT,
-   GPIO1D7_GPIO= 0,
-   GPIO1D7_HDMI_CEC,
-   GPIO1D7_DSP_RTCK,
-
-   GPIO1D6_SHIFT   = 12,
-   GPIO1D6_MASK= 1 << GPIO1D6_SHIFT,
-   GPIO1D6_GPIO= 0,
-   GPIO1D6_HDMI_HPD_M0,
-
-   GPIO1D5_SHIFT   = 10,
-   GPIO1D5_MASK= 3 << GPIO1D5_SHIFT,
-   GPIO1D5_GPIO= 0,
-   GPIO1D5_UART2_RTSN,
-   GPIO1D5_HDMI_SDA_M0,
-
-   GPIO1D4_SHIFT   = 8,
-   GPIO1D4_MASK= 3 << GPIO1D4_SHIFT,
-   GPIO1D4_GPIO= 0,
-   GPIO1D4_UART2_CTSN,
-   GPIO1D4_HDMI_SCL_M0,
-
-   GPIO1D3_SHIFT   = 6,
-   

[U-Boot] [PATCH v3 01/20] rockchip: dts: rk3399-evb: Change the tx/rx delay value for transmission quality

[David Wu]

Give the mac controller the correct tx-delay and rx-delay value
for the rgmii mode transmission. If they are not matched, there
would be Ethernet packets lost, the net feature may not work.

Signed-off-by: David Wu 
Acked-by: Philipp Tomsich 
Reviewed-by: Philipp Tomsich 
---

Changes in v3:
- None

Changes in v2:
- None

 arch/arm/dts/rk3399-evb.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index f0567c9..ed0e00e 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -279,7 +279,7 @@
assigned-clock-parents = <_gmac>;
pinctrl-names = "default";
pinctrl-0 = <_pins>;
-   tx_delay = <0x10>;
-   rx_delay = <0x10>;
+   tx_delay = <0x28>;
+   rx_delay = <0x11>;
status = "okay";
 };
-- 
2.7.4


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[U-Boot] [PATCH v3 03/20] rockchip: grf_rv1108.h: Fix the grf offsets

[David Wu]

The last 4 grf registers offset of rv1108 are wrong, fix them
for correct usage.

Signed-off-by: David Wu 
Reviewed-by: Simon Glass 
---

Changes in v3:
- None

Changes in v2:
- New patch

 arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h 
b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
index c816a5b..428cf6a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
@@ -100,13 +100,17 @@ struct rv1108_grf {
u32 reserved14[2];
u32 dma_con0;
u32 dma_con1;
-   u32 reserved15[539];
+   u32 reserved15[59];
u32 uoc_status;
+   u32 reserved16[2];
u32 host_status;
+   u32 reserved17[59];
u32 gmac_con0;
+   u32 reserved18[191];
u32 chip_id;
 };
-check_member(rv1108_grf, chip_id, 0xf90);
+
+check_member(rv1108_grf, chip_id, 0x0c00);
 
 /* GRF_GPIO1B_IOMUX */
 enum {
-- 
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[U-Boot] [PATCH v3 00/20] Add gmac support for rk3399-evb rv1108-evb rk3328-evb and rk3229-evb

[David Wu]

This serie of patches add rmii interface support, and support more
socs's gmac function, such as rv1108, rk3328 and rk3229.

Implement the "assign-clock-parent" and "assign-clock-rate" for rk3328,
rk3228, rk3288 and rk3368.

This series of patches is based on Philipp's branch:
https://github.com/ptomsich/u-boot-rockchip/tree/assigned-clocks-wip

Changes in v3:
- Add "set parent" for gmac
- Add "set parent" for gmac2io
- Add internal mac clk div_sel for gmac
- Add internal mac clk div_sel for gmac2io
- Fix the wrong define for uart2 iomux
- Fix the wrong define for uart2M0
- New patch
- None
- adhere to the established way of writing this to avoid future confusion
- return error if there was no set_to_rgmii ops at rgmii case
- return error if there was no set_to_rmii ops at rmii case
- set and check clock rate when gmac clock is internal pll.
- use defined symbolic constants for drive-strength

Changes in v2:
- Add check whether the set rgmii/rmii function is a valid function pointer
- Clean the grf offset at gmac_rockchip.c
- New patch
- None
- Use current phy interface to set mac clock rate

David Wu (20):
  rockchip: dts: rk3399-evb: Change the tx/rx delay value for
transmission quality
  rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb
  rockchip: grf_rv1108.h: Fix the grf offsets
  rockchip: pinctrl: rv1108: Move the iomux definitions into
pinctrl-driver
  net: gmac_rockchip: Add support for the RV1108 GMAC
  rockchip: pinctrl: rk3328: Move the iomux definitions into
pinctrl-driver
  rockchip: pinctrl: Add rk3328 gmac pinctrl support
  clk: rockchip: Add rk3328 gamc clock support
  net: gmac_rockchip: Add rk3328 gmac support
  rockchip: configs: Enable GMAC configs for evb-rk3328
  rockchip: dts: rk3328: Add gmac2io support
  rockchip: dts: rk3328-evb: Enable gmac2io for rk3328-evb
  rockchip: pinctrl: rk322x: Move the iomux definitions into
pinctrl-driver
  rockchip: pinctrl: Add rk322x gmac pinctrl support
  clk: rockchip: Add rk322x gamc clock support
  net: gmac_rockchip: Add support for the RK3228 GMAC
  config: evb-rk3229: Enable rk gmac configs
  ARM: dts: rk3288: Remove unused LCDC clock assigned
  clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and
"assign-clock-rate"
  clk: rockchip: clk_rk3368: Implement "assign-clock-parent"

 arch/arm/dts/rk3288.dtsi|   7 +-
 arch/arm/dts/rk3328-evb.dts |  30 ++
 arch/arm/dts/rk3328.dtsi|  19 +
 arch/arm/dts/rk3399-evb.dts |   4 +-
 arch/arm/include/asm/arch-rockchip/cru_rk3368.h |   7 +
 arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 455 --
 arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 114 -
 arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 405 +---
 arch/arm/mach-rockchip/rk322x-board-spl.c   |  22 +-
 arch/arm/mach-rockchip/rk322x-board.c   |  18 +
 board/rockchip/evb_rv1108/evb_rv1108.c  |  17 +
 configs/evb-rk3229_defconfig|   5 +
 configs/evb-rk3288_defconfig|   1 +
 configs/evb-rk3328_defconfig|   5 +
 drivers/clk/rockchip/clk_rk322x.c   | 107 +
 drivers/clk/rockchip/clk_rk3288.c   | 106 -
 drivers/clk/rockchip/clk_rk3328.c   | 178 +++
 drivers/clk/rockchip/clk_rk3368.c   |  91 +++-
 drivers/net/gmac_rockchip.c | 285 ++-
 drivers/pinctrl/rockchip/pinctrl_rk322x.c   | 601 
 drivers/pinctrl/rockchip/pinctrl_rk3328.c   | 388 +++
 drivers/pinctrl/rockchip/pinctrl_rv1108.c   | 399 
 include/dt-bindings/clock/rk3288-cru.h  |   1 +
 include/dt-bindings/clock/rk3328-cru.h  |   6 +-
 24 files changed, 2270 insertions(+), 1001 deletions(-)

-- 
2.7.4


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Re: [U-Boot] [PATCH 2/2] configs: stm32: move config flag from defconfig to Kconfig

[Vikas Manocha]

Hi,

On 01/12/2018 12:23 AM, patrice.chot...@st.com wrote:
> From: Patrice Chotard 
> 
> Move system flags from defconfig to mach-stm32/Kconfig
> 
> Signed-off-by: Patrice Chotard 

Reviewed-by: Vikas Manocha 
One comment below 


> ---
>  arch/arm/mach-stm32/Kconfig   | 22 ++
>  configs/stm32f429-discovery_defconfig | 11 ---
>  configs/stm32f469-discovery_defconfig | 11 ---
>  configs/stm32f746-disco_defconfig | 11 ---
>  4 files changed, 22 insertions(+), 33 deletions(-)
> 
> diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
> index f4c93f1..5f7a2b5 100644
> --- a/arch/arm/mach-stm32/Kconfig
> +++ b/arch/arm/mach-stm32/Kconfig
> @@ -2,9 +2,31 @@ if STM32
>  
>  config STM32F4
>   bool "stm32f4 family"
> + select CLK
> + select DM_GPIO
> + select DM_RESET
> + select MISC
> + select PINCTRL
> + select PINCTRL_STM32
> + select RAM
> + select STM32_SDRAM
> + select STM32_RCC
> + select STM32_RESET
> + select STM32_SERIAL
>  
>  config STM32F7
>   bool "stm32f7 family"
> + select CLK
> + select DM_GPIO
> + select DM_RESET
> + select MISC
> + select PINCTRL
> + select PINCTRL_STM32
> + select RAM
> + select STM32_SDRAM
> + select STM32_RCC
> + select STM32_RESET
> + select STM32_SERIAL

Can you have one common selection(like STM32_SERIAL) like under 'if STM32'.

Cheers,
Vikas

>   select SUPPORT_SPL
>   select SPL
>   select SPL_CLK
> diff --git a/configs/stm32f429-discovery_defconfig 
> b/configs/stm32f429-discovery_defconfig
> index 6f7a12f..ec67aad 100644
> --- a/configs/stm32f429-discovery_defconfig
> +++ b/configs/stm32f429-discovery_defconfig
> @@ -19,16 +19,5 @@ CONFIG_CMD_TIMER=y
>  CONFIG_OF_CONTROL=y
>  CONFIG_OF_EMBED=y
>  CONFIG_ENV_IS_IN_FLASH=y
> -CONFIG_CLK=y
> -CONFIG_DM_GPIO=y
> -CONFIG_MISC=y
> -CONFIG_STM32_RCC=y
>  # CONFIG_MMC is not set
>  CONFIG_MTD_NOR_FLASH=y
> -CONFIG_PINCTRL=y
> -CONFIG_PINCTRL_STM32=y
> -CONFIG_RAM=y
> -CONFIG_STM32_SDRAM=y
> -CONFIG_DM_RESET=y
> -CONFIG_STM32_RESET=y
> -CONFIG_STM32_SERIAL=y
> diff --git a/configs/stm32f469-discovery_defconfig 
> b/configs/stm32f469-discovery_defconfig
> index 5b70aa9..8190b82 100644
> --- a/configs/stm32f469-discovery_defconfig
> +++ b/configs/stm32f469-discovery_defconfig
> @@ -26,17 +26,6 @@ CONFIG_CMD_FS_GENERIC=y
>  CONFIG_OF_CONTROL=y
>  CONFIG_OF_EMBED=y
>  # CONFIG_BLK is not set
> -CONFIG_CLK=y
> -CONFIG_DM_GPIO=y
> -CONFIG_MISC=y
> -CONFIG_STM32_RCC=y
>  CONFIG_DM_MMC=y
>  CONFIG_ARM_PL180_MMCI=y
>  CONFIG_MTD_NOR_FLASH=y
> -CONFIG_PINCTRL=y
> -CONFIG_PINCTRL_STM32=y
> -CONFIG_RAM=y
> -CONFIG_STM32_SDRAM=y
> -CONFIG_DM_RESET=y
> -CONFIG_STM32_RESET=y
> -CONFIG_STM32_SERIAL=y
> diff --git a/configs/stm32f746-disco_defconfig 
> b/configs/stm32f746-disco_defconfig
> index 69df866..f8fa198 100644
> --- a/configs/stm32f746-disco_defconfig
> +++ b/configs/stm32f746-disco_defconfig
> @@ -39,10 +39,6 @@ CONFIG_OF_CONTROL=y
>  CONFIG_NET_RANDOM_ETHADDR=y
>  CONFIG_NETCONSOLE=y
>  # CONFIG_BLK is not set
> -CONFIG_CLK=y
> -CONFIG_DM_GPIO=y
> -CONFIG_MISC=y
> -CONFIG_STM32_RCC=y
>  CONFIG_DM_MMC=y
>  # CONFIG_SPL_DM_MMC is not set
>  CONFIG_ARM_PL180_MMCI=y
> @@ -53,14 +49,7 @@ CONFIG_SPI_FLASH=y
>  CONFIG_SPI_FLASH_STMICRO=y
>  CONFIG_DM_ETH=y
>  CONFIG_ETH_DESIGNWARE=y
> -CONFIG_PINCTRL=y
>  # CONFIG_PINCTRL_FULL is not set
> -CONFIG_PINCTRL_STM32=y
> -CONFIG_RAM=y
> -CONFIG_STM32_SDRAM=y
> -CONFIG_DM_RESET=y
> -CONFIG_STM32_RESET=y
> -CONFIG_STM32_SERIAL=y
>  CONFIG_DM_SPI=y
>  CONFIG_STM32_QSPI=y
>  CONFIG_OF_LIBFDT_OVERLAY=y
> 
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Re: [U-Boot] [PATCH 1/2] serial: stm32: Rename serial_stm32x7.c to serial_stm32.c

[Vikas Manocha]

Hi,

On 01/12/2018 12:23 AM, patrice.chot...@st.com wrote:
> From: Patrice Chotard 
> 
> Now this driver is used across stm32f4, stm32f7 and stm32h7
> SoCs family, give it a generic name.
> 
> Signed-off-by: Patrice Chotard 

Reviewed-by: Vikas Manocha 

Cheers,
Vikas

> ---
>  arch/arm/mach-stm32/Kconfig | 2 +-
>  configs/stm32f429-discovery_defconfig   | 2 +-
>  configs/stm32f469-discovery_defconfig   | 2 +-
>  configs/stm32f746-disco_defconfig   | 2 +-
>  drivers/serial/Kconfig  | 2 +-
>  drivers/serial/Makefile | 2 +-
>  drivers/serial/{serial_stm32x7.c => serial_stm32.c} | 4 ++--
>  drivers/serial/{serial_stm32x7.h => serial_stm32.h} | 4 ++--
>  8 files changed, 10 insertions(+), 10 deletions(-)
>  rename drivers/serial/{serial_stm32x7.c => serial_stm32.c} (98%)
>  rename drivers/serial/{serial_stm32x7.h => serial_stm32.h} (97%)
> 
> diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
> index b618b60..f4c93f1 100644
> --- a/arch/arm/mach-stm32/Kconfig
> +++ b/arch/arm/mach-stm32/Kconfig
> @@ -38,7 +38,7 @@ config STM32H7
>   select STM32_SDRAM
>   select STM32_RCC
>   select STM32_RESET
> - select STM32X7_SERIAL
> + select STM32_SERIAL
>   select SYSCON
>  
>  source "arch/arm/mach-stm32/stm32f4/Kconfig"
> diff --git a/configs/stm32f429-discovery_defconfig 
> b/configs/stm32f429-discovery_defconfig
> index 52bd931..6f7a12f 100644
> --- a/configs/stm32f429-discovery_defconfig
> +++ b/configs/stm32f429-discovery_defconfig
> @@ -31,4 +31,4 @@ CONFIG_RAM=y
>  CONFIG_STM32_SDRAM=y
>  CONFIG_DM_RESET=y
>  CONFIG_STM32_RESET=y
> -CONFIG_STM32X7_SERIAL=y
> +CONFIG_STM32_SERIAL=y
> diff --git a/configs/stm32f469-discovery_defconfig 
> b/configs/stm32f469-discovery_defconfig
> index afffddf..5b70aa9 100644
> --- a/configs/stm32f469-discovery_defconfig
> +++ b/configs/stm32f469-discovery_defconfig
> @@ -39,4 +39,4 @@ CONFIG_RAM=y
>  CONFIG_STM32_SDRAM=y
>  CONFIG_DM_RESET=y
>  CONFIG_STM32_RESET=y
> -CONFIG_STM32X7_SERIAL=y
> +CONFIG_STM32_SERIAL=y
> diff --git a/configs/stm32f746-disco_defconfig 
> b/configs/stm32f746-disco_defconfig
> index 321321f..69df866 100644
> --- a/configs/stm32f746-disco_defconfig
> +++ b/configs/stm32f746-disco_defconfig
> @@ -60,7 +60,7 @@ CONFIG_RAM=y
>  CONFIG_STM32_SDRAM=y
>  CONFIG_DM_RESET=y
>  CONFIG_STM32_RESET=y
> -CONFIG_STM32X7_SERIAL=y
> +CONFIG_STM32_SERIAL=y
>  CONFIG_DM_SPI=y
>  CONFIG_STM32_QSPI=y
>  CONFIG_OF_LIBFDT_OVERLAY=y
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 122b8e7..7b20b47 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -529,7 +529,7 @@ config STI_ASC_SERIAL
> on STiH410 SoC. This is a basic implementation,  it supports
> following baudrate 9600, 19200, 38400, 57600 and 115200.
>  
> -config STM32X7_SERIAL
> +config STM32_SERIAL
>   bool "STMicroelectronics STM32 SoCs on-chip UART"
>   depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
>   help
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index 7adcee3..5ef603a 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -44,7 +44,7 @@ obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
>  obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
>  obj-$(CONFIG_STI_ASC_SERIAL) += serial_sti_asc.o
>  obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
> -obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
> +obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
>  obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
>  obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
>  obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
> diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32.c
> similarity index 98%
> rename from drivers/serial/serial_stm32x7.c
> rename to drivers/serial/serial_stm32.c
> index d1580e3..286b954 100644
> --- a/drivers/serial/serial_stm32x7.c
> +++ b/drivers/serial/serial_stm32.c
> @@ -11,7 +11,7 @@
>  #include 
>  #include 
>  #include 
> -#include "serial_stm32x7.h"
> +#include "serial_stm32.h"
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -148,7 +148,7 @@ static const struct dm_serial_ops stm32_serial_ops = {
>  };
>  
>  U_BOOT_DRIVER(serial_stm32) = {
> - .name = "serial_stm32x7",
> + .name = "serial_stm32",
>   .id = UCLASS_SERIAL,
>   .of_match = of_match_ptr(stm32_serial_id),
>   .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
> diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32.h
> similarity index 97%
> rename from drivers/serial/serial_stm32x7.h
> rename to drivers/serial/serial_stm32.h
> index f7dca39..d08ba1f 100644
> --- a/drivers/serial/serial_stm32x7.h
> +++ b/drivers/serial/serial_stm32.h
> @@ -5,8 +5,8 @@
>   * SPDX-License-Identifier:  GPL-2.0+
>   */
>  
> -#ifndef 

[U-Boot] [PATCH] powerpc: Drop unreferenced CONFIG_* defines

[Tuomas Tynkkynen]

The following config symbols are only defined once and never referenced
anywhere else:

CONFIG_CYRUS
CONFIG_IDS8313
CONFIG_MPC8308_P1M
CONFIG_MPC8308RDB
CONFIG_MPC8349EMDS
CONFIG_MPC8349ITXGP
CONFIG_SBC8349
CONFIG_SBC8548
CONFIG_SBC8641D
CONFIG_TQM834X
CONFIG_VE8313
CONFIG_XPEDITE5140
CONFIG_XPEDITE5200
CONFIG_XPEDITE550X

Most of them are config symbols named after the respective boards which
seems to have been a standard practice at some point.

Signed-off-by: Tuomas Tynkkynen 
---
 board/freescale/mpc8349itx/README |  1 -
 configs/MPC8349ITXGP_defconfig|  2 +-
 include/configs/MPC8308RDB.h  |  1 -
 include/configs/MPC8349EMDS.h |  1 -
 include/configs/TQM834x.h |  1 -
 include/configs/cyrus.h   |  2 --
 include/configs/ids8313.h |  1 -
 include/configs/mpc8308_p1m.h |  1 -
 include/configs/sbc8349.h |  1 -
 include/configs/sbc8548.h |  1 -
 include/configs/sbc8641d.h|  1 -
 include/configs/ve8313.h  |  1 -
 include/configs/xpedite517x.h |  1 -
 include/configs/xpedite520x.h |  1 -
 include/configs/xpedite550x.h |  1 -
 scripts/config_whitelist.txt  | 14 --
 16 files changed, 1 insertion(+), 30 deletions(-)

diff --git a/board/freescale/mpc8349itx/README 
b/board/freescale/mpc8349itx/README
index 48bbd50356..3012b83737 100644
--- a/board/freescale/mpc8349itx/README
+++ b/board/freescale/mpc8349itx/README
@@ -91,7 +91,6 @@ Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
CONFIG_MPC83xx  MPC83xx family
CONFIG_MPC8349  MPC8349 specific
CONFIG_MPC8349ITX   MPC8349E-mITX
-   CONFIG_MPC8349ITXGP MPC8349E-mITX-GP
 
 5. Compilation
 
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index 319141de1b..97dc8e7a80 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -3,7 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349ITX=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE00"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE00"
 CONFIG_BOOTDELAY=6
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs 
ip=mpc8349emitxgp:eth0:off console=ttyS0,115200"
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index bd0cb6fddc..d348ec9367 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -15,7 +15,6 @@
 #define CONFIG_E3001 /* E300 family */
 #define CONFIG_MPC830x 1 /* MPC830x family */
 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
-#define CONFIG_MPC8308RDB  1 /* MPC8308RDB board specific */
 
 #defineCONFIG_SYS_TEXT_BASE0xFE00
 
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 9b906a7c77..c7a5ee0aaf 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -19,7 +19,6 @@
 #define CONFIG_E3001   /* E300 Family */
 #define CONFIG_MPC834x 1   /* MPC834x family */
 #define CONFIG_MPC8349 1   /* MPC8349 specific */
-#define CONFIG_MPC8349EMDS 1   /* MPC8349EMDS board specific */
 
 #defineCONFIG_SYS_TEXT_BASE0xFE00
 
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 0c6bcae33c..9d27358031 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -18,7 +18,6 @@
 #define CONFIG_E3001   /* E300 Family */
 #define CONFIG_MPC834x 1   /* MPC834x specific */
 #define CONFIG_MPC8349 1   /* MPC8349 specific */
-#define CONFIG_TQM834X 1   /* TQM834X board specific */
 
 #defineCONFIG_SYS_TEXT_BASE0x8000
 
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index e413b5158c..3da91e80c8 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_CYRUS
-
 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
 #error Must call Cyrus CONFIG with a specific CPU enabled.
 #endif
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index b43c8c711e..12eb07d1f7 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -17,7 +17,6 @@
  */
 #define CONFIG_MPC831x
 #define CONFIG_MPC8313
-#define CONFIG_IDS8313
 
 #define CONFIG_FSL_ELBC
 
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index f97773146a..69c4309139 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -15,7 +15,6 @@
 #define CONFIG_E3001 /* E300 family */
 #define CONFIG_MPC830x 1 /* MPC830x family */
 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
-#define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */
 
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE   0xFC00
diff --git 

[U-Boot] [PATCH 1/1] dm: video: Correct color ANSI escape sequence support

[Heinrich Schuchardt]

Support increased intensity (bold).
Get RGB sequence in pixels right (swap blue and red).
Do not set reserved bits.
Use u32 instead of unsigned for color bit mask.

qemu-system-i386 -display sdl -vga virtio and
qemu-system-i386 -display sdl -vga cirrus
now display the same colors as
qemu-system-i386 -nographic

Testing is possible via

setenv efi_selftest test output
bootefi selftest

Signed-off-by: Heinrich Schuchardt 
---
 drivers/video/vidconsole-uclass.c | 53 ++-
 drivers/video/video-uclass.c  | 38 +---
 include/video.h   |  6 +++--
 3 files changed, 74 insertions(+), 23 deletions(-)

diff --git a/drivers/video/vidconsole-uclass.c 
b/drivers/video/vidconsole-uclass.c
index 5f63c12d6c..79c7f2113f 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -114,28 +114,35 @@ static const struct {
unsigned b;
 } colors[] = {
{ 0x00, 0x00, 0x00 },  /* black */
-   { 0xff, 0x00, 0x00 },  /* red */
-   { 0x00, 0xff, 0x00 },  /* green */
+   { 0xc0, 0x00, 0x00 },  /* red */
+   { 0x00, 0xc0, 0x00 },  /* green */
+   { 0xc0, 0x60, 0x00 },  /* brown */
+   { 0x00, 0x00, 0xc0 },  /* blue */
+   { 0xc0, 0x00, 0xc0 },  /* magenta */
+   { 0x00, 0xc0, 0xc0 },  /* cyan */
+   { 0xc0, 0xc0, 0xc0 },  /* light gray */
+   { 0x80, 0x80, 0x80 },  /* gray */
+   { 0xff, 0x00, 0x00 },  /* bright red */
+   { 0x00, 0xff, 0x00 },  /* bright green */
{ 0xff, 0xff, 0x00 },  /* yellow */
-   { 0x00, 0x00, 0xff },  /* blue */
-   { 0xff, 0x00, 0xff },  /* magenta */
-   { 0x00, 0xff, 0xff },  /* cyan */
+   { 0x00, 0x00, 0xff },  /* bright blue */
+   { 0xff, 0x00, 0xff },  /* bright magenta */
+   { 0x00, 0xff, 0xff },  /* bright cyan */
{ 0xff, 0xff, 0xff },  /* white */
 };
 
-static void set_color(struct video_priv *priv, unsigned idx, unsigned *c)
+static void set_color(struct video_priv *priv, unsigned int idx, u32 *c)
 {
switch (priv->bpix) {
case VIDEO_BPP16:
-   *c = ((colors[idx].r >> 3) << 0) |
-((colors[idx].g >> 2) << 5) |
-((colors[idx].b >> 3) << 11);
+   *c = ((colors[idx].r >> 3) << 11) |
+((colors[idx].g >> 2) <<  5) |
+((colors[idx].b >> 3) <<  0);
break;
case VIDEO_BPP32:
-   *c = 0xff00 |
-(colors[idx].r << 0) |
-(colors[idx].g << 8) |
-(colors[idx].b << 16);
+   *c = (colors[idx].r << 16) |
+(colors[idx].g <<  8) |
+(colors[idx].b <<  0);
break;
default:
/* unsupported, leave current color in place */
@@ -270,18 +277,30 @@ static void vidconsole_escape_char(struct udevice *dev, 
char ch)
s++;
 
switch (val) {
+   case 0:
+   /* all attributes off */
+   vid_priv->fg &= 7;
+   break;
+   case 1:
+   /* bold */
+   vid_priv->fg |= 8;
+   set_color(vid_priv, vid_priv->fg,
+ (unsigned int *)_priv->colour_fg);
+   break;
case 30 ... 37:
/* fg color */
-   set_color(vid_priv, val - 30,
- (unsigned *)_priv->colour_fg);
+   vid_priv->fg &= ~7;
+   vid_priv->fg |= val - 30;
+   set_color(vid_priv, vid_priv->fg,
+ _priv->colour_fg);
break;
case 40 ... 47:
/* bg color */
set_color(vid_priv, val - 40,
- (unsigned *)_priv->colour_bg);
+ _priv->colour_bg);
break;
default:
-   /* unknown/unsupported */
+   /* ignore unsupported SGR parameter */
break;
}
}
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index dcaceed42c..8dfb6b1902 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -91,14 +91,26 @@ void video_clear(struct udevice *dev)
 {
struct video_priv *priv = dev_get_uclass_priv(dev);
 
-   if (priv->bpix == VIDEO_BPP32) {
+   switch (priv->bpix) {
+   

Re: [U-Boot] On writing .ext4 image to MMC

[Adam Lee]

I was hoping to get this done in the bootloader otherwise I have to change
the rootfs ;)

On Fri, Jan 12, 2018 at 1:18 PM Michael Nazzareno Trimarchi <
mich...@amarulasolutions.com> wrote:

> Hi
>
> On 12 Jan. 2018 7:15 pm, "Adam Lee"  wrote:
>
> Hi Michael, I used gparted to fix the issue. I am just wondering if I can
> do all this in U-Boot.
> If there is no good solution, I will put one-time script in my rootfs to
> do this task.
>
>
> Sorry most of the system on first boot create a first instance of
> something like ssd for keys. I think that just use resize FS should do the
> trick. Why is should be done in bootloader?
>
> Michael
>
>
> Adam
>
> On Fri, Jan 12, 2018 at 10:18 AM Michael Nazzareno Trimarchi <
> mich...@amarulasolutions.com> wrote:
>
>> Hi
>>
>>
>> resize2fs from linux?
>>
>> Michael
>>
>> On Fri, Jan 12, 2018 at 4:15 PM, Adam Lee  wrote:
>> > Hello everyone,
>> >
>> > I am able to download a .ext4 image over tftp and write it to my SD
>> card.
>> > The system boots fine.
>> > One last thing I have to figure out is to expand this .ext4 file system
>> > that I just populated.
>> > If the image is 600MB, the partition size itself is 600MB, leaving no
>> room.
>> >
>> > Is there anything I can do to remedy this in U-Boot?
>> >
>> > Adam
>> > ___
>> > U-Boot mailing list
>> > U-Boot@lists.denx.de
>> > https://lists.denx.de/listinfo/u-boot
>>
>>
>>
>> --
>> | Michael Nazzareno Trimarchi Amarula Solutions BV |
>> | COO  -  Founder  Cruquiuskade 47
>>  |
>> | +31(0)851119172 <+31%2085%20111%209172>
>>  Amsterdam 1018 AM NL |
>> |  [`as] http://www.amarulasolutions.com   |
>>
>
>
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Re: [U-Boot] On writing .ext4 image to MMC

[Michael Nazzareno Trimarchi]

Hi

On 12 Jan. 2018 7:15 pm, "Adam Lee"  wrote:

Hi Michael, I used gparted to fix the issue. I am just wondering if I can
do all this in U-Boot.
If there is no good solution, I will put one-time script in my rootfs to do
this task.


Sorry most of the system on first boot create a first instance of something
like ssd for keys. I think that just use resize FS should do the trick. Why
is should be done in bootloader?

Michael


Adam

On Fri, Jan 12, 2018 at 10:18 AM Michael Nazzareno Trimarchi <
mich...@amarulasolutions.com> wrote:

> Hi
>
>
> resize2fs from linux?
>
> Michael
>
> On Fri, Jan 12, 2018 at 4:15 PM, Adam Lee  wrote:
> > Hello everyone,
> >
> > I am able to download a .ext4 image over tftp and write it to my SD card.
> > The system boots fine.
> > One last thing I have to figure out is to expand this .ext4 file system
> > that I just populated.
> > If the image is 600MB, the partition size itself is 600MB, leaving no
> room.
> >
> > Is there anything I can do to remedy this in U-Boot?
> >
> > Adam
> > ___
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > https://lists.denx.de/listinfo/u-boot
>
>
>
> --
> | Michael Nazzareno Trimarchi Amarula Solutions BV |
> | COO  -  Founder  Cruquiuskade 47
>  |
> | +31(0)851119172 <+31%2085%20111%209172>
>  Amsterdam 1018 AM NL |
> |  [`as] http://www.amarulasolutions.com   |
>
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Re: [U-Boot] On writing .ext4 image to MMC

[Adam Lee]

Hi Michael, I used gparted to fix the issue. I am just wondering if I can
do all this in U-Boot.
If there is no good solution, I will put one-time script in my rootfs to do
this task.

Adam

On Fri, Jan 12, 2018 at 10:18 AM Michael Nazzareno Trimarchi <
mich...@amarulasolutions.com> wrote:

> Hi
>
>
> resize2fs from linux?
>
> Michael
>
> On Fri, Jan 12, 2018 at 4:15 PM, Adam Lee  wrote:
> > Hello everyone,
> >
> > I am able to download a .ext4 image over tftp and write it to my SD card.
> > The system boots fine.
> > One last thing I have to figure out is to expand this .ext4 file system
> > that I just populated.
> > If the image is 600MB, the partition size itself is 600MB, leaving no
> room.
> >
> > Is there anything I can do to remedy this in U-Boot?
> >
> > Adam
> > ___
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > https://lists.denx.de/listinfo/u-boot
>
>
>
> --
> | Michael Nazzareno Trimarchi Amarula Solutions BV |
> | COO  -  Founder  Cruquiuskade 47 |
> | +31(0)851119172 <+31%2085%20111%209172>
>  Amsterdam 1018 AM NL |
> |  [`as] http://www.amarulasolutions.com   |
>
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Re: [U-Boot] [PATCH] imx: fix CAAM base for i.MX6UL

[Breno Matheus Lima]

Hi Anatolij,

2018-01-11 12:54 GMT-02:00 Fabio Estevam :
> Hi Anatolij,
>
> Thanks for the fix.
>
> On Thu, Jan 11, 2018 at 12:14 PM, Anatolij Gustschin  wrote:
>> HW accelerated "hash sha256 ..." command doesn't work on i.MX6UL, we get
>> "CAAM was not setup properly or it is faulty" error message.
>>
>> This is due to wrong CAAM base 0x0210, on i.MX6UL the CAAM base
>> address is 0x0214. Fix it.
>>
>> Note: with this patch applied the "hash sha256" commant still has some
>> issues on i.MX6UL ("Invalid KEY Command" or other errors). With data
>> cache off the "hash sha256" command works as expected.
>
> Breno, could you please take a look at this issue when possible ?

I managed to reproduce this issue on a mx6sabreauto, with data cache
off the "hash sha256" command works as expected.

I will take a look on this issue and let you know any progress.

Thanks,
Breno Lima
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[U-Boot] Pull request, u-boot-tegra/master

[Tom Warren]

Tom,

Please pull u-boot-tegra/master into U-Boot/master. Thanks!

All Tegra builds are OK, and Stephen's automated test system reports that
all tests pass.

The following changes since commit 373b9003410b44a1133060c2e63483b278fb476b:

  Merge git://git.denx.de/u-boot-sunxi (2018-01-11 14:14:19 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-tegra.git master

for you to fetch changes up to 5fed97af20da955625cc06563a725b49cebb99eb:

  Makefile: ensure DTB doesn't overflow into initial stack (2018-01-12
10:12:32 -0700)


Stephen Warren (14):
  ARM: tegra: don't use CONFIG_SPL_TEXT_BASE when no SPL
  ARM: tegra: remove SPL config for non-SPL SoCs
  ARMv8: Allow dynamic early stack pointer
  ARM: tegra: use CONFIG_SYS_INIT_SP_BSS_OFFSET
  ARMv8: add optional Linux kernel image header
  ARM: tegra: use LINUX_KERNEL_IMAGE_HEADER
  ARM: Tegra186: mem parsing fixes from downstream
  ARM: bootm: don't assume sp is in DRAM bank 0
  ARM: Tegra186: search for best RAM bank
  ARM: tegra: p2771-000: increase max DRAM bank count
  ARM: Tegra186: don't map memory not in RAM banks
  ARM: Tegra186: calculate load addresses at boot
  ARM: Tegra: p2771-: use calculate env var feature
  Makefile: ensure DTB doesn't overflow into initial stack

 Makefile   |  31 +++
 arch/arm/Kconfig   |  30 +++
 .../arm/cpu/armv8/linux-kernel-image-header-vars.h |  86 +++
 arch/arm/cpu/armv8/start.S |   4 +-
 arch/arm/cpu/armv8/u-boot.lds  |   4 +
 arch/arm/dts/tegra-u-boot.dtsi |  15 +-
 arch/arm/include/asm/boot0-linux-kernel-header.h   |  49 
 arch/arm/lib/bootm.c   |  15 +-
 arch/arm/lib/crt0_64.S |   3 +
 arch/arm/mach-tegra/Kconfig|   6 +
 arch/arm/mach-tegra/arm64-mmu.c|   3 +-
 arch/arm/mach-tegra/tegra186/Kconfig   |   3 +
 arch/arm/mach-tegra/tegra186/nvtboot_board.c   | 265
-
 arch/arm/mach-tegra/tegra186/nvtboot_mem.c | 144 ---
 arch/arm/mach-tegra/tegra210/Kconfig   |   3 +
 include/configs/p2771-.h   |  23 ++
 include/configs/tegra-common.h |   4 +
 include/configs/tegra186-common.h  |  10 -
 include/configs/tegra210-common.h  |  10 -
 19 files changed, 646 insertions(+), 62 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/linux-kernel-image-header-vars.h
 create mode 100644 arch/arm/include/asm/boot0-linux-kernel-header.h

Thanks,

Tom
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Re: [U-Boot] [PATCH v3] armv8: errata: Implement workaround for Cortex-A53 Erratum 855873

[York Sun]

On 01/12/2018 01:12 AM, Michal Simek wrote:
> On 11.1.2018 20:36, York Sun wrote:
>> On 12/27/2017 09:20 PM, Alison Wang wrote:
>>> 855873: An eviction might overtake a cache clean operation
>>> Workaround: The erratum can be avoided by upgrading cache clean by
>>> address operations to cache clean and invalidate operations. For
>>> Cortex-A53 r0p3 and later release, this can be achieved by setting
>>> CPUACTLR.ENDCCASCI to 1.
>>>
>>> This patch is to implement the workaround for this erratum.
>>>
>>> Signed-off-by: Alison Wang 
>>> ---
>>> Changes in v3:
>>> - Check the major revision of Cortex-A53.
>>>
>>> Changes in v2:
>>> - Check the revision of Cortex-A53 and apply the erratum to r0p3 and later 
>>> release.
>>> - Fix the mistake in the commit description.
>>>
>>
>> Applied to fsl-qoriq master. Thanks.
> 
> Just a note if this is just for a53 should we consider to place these
> Kconfigs to arch/arm/cpu/armv8/Kconfig?
> 

We were following Tom Rini's move in commit 8dda2e2f9. I am not against
moving ARMv8 related config options, if no single erratum applies to
both ARMv8 and legacy cores.

York
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Re: [U-Boot] [PATCH 3/9] optee: Make OPTEE_TZDRAM_BASE a mandatory define

[Tom Rini]

On Fri, Jan 12, 2018 at 02:52:18PM +, Bryan O'Donoghue wrote:

> This patch makes OTPEE_TZDRAM_BASE a mandatory parameter.
> Subsequent patches will ensure that the region between
> OTPEE_TZDRAM_BASE and (OTPEE_TZDRAM_BASE +
> CONFIG_OPTEE_TZDRAM_SIZE) match the information given in the OPTEE header
> before handing off control to the OPTEE image when booting OPTEE directly
> via bootm.
> 
> Signed-off-by: Bryan O'Donoghue 
> Cc: Harinarayan Bhatta 
> Cc: Andrew F. Davis 
> Cc: Tom Rini 
> Cc: Kever Yang 
> Cc: Philipp Tomsich 
> Cc: Peng Fan 
> ---
>  lib/optee/optee.c | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/lib/optee/optee.c b/lib/optee/optee.c
> index a6c856a..6e55027 100644
> --- a/lib/optee/optee.c
> +++ b/lib/optee/optee.c
> @@ -5,9 +5,14 @@
>   * SPDX-License-Identifier:  GPL-2.0+
>   */
>  
> +#include 
>  #include 
>  #include 
>  
> +#ifndef OPTEE_TZDRAM_BASE
> +#error "OPTEE_TZDRAM_BASE not defined"
> +#endif
> +
>  int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
>  unsigned long tzdram_len, unsigned long image_len)
>  {

I'm not a fan of adding #error's like this.  Since this is a static
value,it should be in Kconfig (with appropriate depends) or defined in a
consistent location (asm/arch/optee.h ?) and it should be obvious from
the code that uses the value that you need to have this value be
provided and how to determine what the valid and correct value is.
Thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] TCP and wget implementation v5.1

[Joe Hershberger]

Hi Duncan,

On Wed, Jan 10, 2018 at 8:18 PM, Duncan Hare  wrote:
> Date: Wed, 10 Jan 2018 17:54:07 -0800
> Subject: [PATCH] git_msg_1
>
> TCP and wget implementation.

Sounds like this should be the title of the series cover letter. I
thought we agreed that this should be sent as a series. That means
using patman to send all 3 matches to the list as once.

>
> This is the interface and Kconfig files for introducing TCP and wget
> into u-boot.
>
> Interfaces are in net.c and net.h, ping.c is modified to the new ip send
> interface, and UDP and TCP have shim procedures call map the protocol
> interface to the ip interface.
>
> The UDP interface is unchanged, and the existing UDP programs need no
> changes.
>
> All the code is new, and not copied from any source.
>
> This code should compile.
>
> Next step? git push?

Next step is to get sendmail setup and resend as a series using patman.

> And I do wish  I could get git send-mail configureg
> with yahoo.

https://help.yahoo.com/kb/SLN4724.html

>
> Signed-off-by: Duncan Hare 
>
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Re: [U-Boot] [PATCH V3] Convert CONFIG_SYS_DV_CLKMODE et al to Kconfig

[David Lechner]

On 01/12/2018 07:26 AM, Adam Ford wrote:

This converts the following to Kconfig:
CONFIG_SYS_DV_CLKMODE
CONFIG_SYS_DA850_PLL0_POSTDIV
CONFIG_SYS_DA850_PLL0_PLLDIV1
CONFIG_SYS_DA850_PLL0_PLLDIV2
CONFIG_SYS_DA850_PLL0_PLLDIV3
CONFIG_SYS_DA850_PLL0_PLLDIV4
CONFIG_SYS_DA850_PLL0_PLLDIV5
CONFIG_SYS_DA850_PLL0_PLLDIV7
CONFIG_SYS_DA850_PLL1_POSTDIV
CONFIG_SYS_DA850_PLL1_PLLDIV1
CONFIG_SYS_DA850_PLL1_PLLDIV2
CONFIG_SYS_DA850_PLL1_PLLDIV3

Signed-off-by: Adam Ford 
---


Reviewed-by: David Lechner 


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Re: [U-Boot] [PATCH v6 21/25] arm: imx: hab: Make authenticate_image() return zero on open boards

[Breno Matheus Lima]

Hi Bryan,

2018-01-12 10:40 GMT-02:00 Bryan O'Donoghue :
> The BootROM will not successfully process a HAB image passed by u-boot
> unless the board has been set into locked mode. Some of the existing usages
> of authenticate_image() expect and rely on unlocked boards doing the
> following
>
> 1. Not calling into the BootROM authenticate_image() callback
> 2. Returning a pass status for authenticate_image() calls anyway
>
> A previous patch removed the necessity to call into imx_hab_is_enabled()
> twice. This patch ensures the reliance on authenticate_image() returning
> zero is maintained.
>
> Signed-off-by: Bryan O'Donoghue 
> Suggested-by: Breno Matheus Lima 
> Cc: Stefano Babic 
> Cc: Fabio Estevam 
> Cc: Peng Fan 
> Cc: Albert Aribaud 
> Cc: Sven Ebenfeld 
> Cc: George McCollister 

Thanks for adding this patch on the series, I tested on an open
mx6ulevk board and it's working fine.

Tested-by: Breno Lima 
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[U-Boot] [PATCH] arm: zynq: Enable SPL_CLK only if SPL is enabled

[Ezequiel Garcia]

Setup proper dependency in Kconfig for SPL_CLK.
If SPL is not enabled, SPL_CLK shouldn't be selected.

Cc: Michal Simek 
Signed-off-by: Ezequiel Garcia 
---
 arch/arm/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index de323bf4b96e..4ff369c32524 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -760,7 +760,7 @@ config ARCH_ZYNQ
select DM_USB if USB
select BLK
select CLK
-   select SPL_CLK
+   select SPL_CLK if SPL
select CLK_ZYNQ
imply CMD_CLK
imply FAT_WRITE
-- 
2.15.1

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Re: [U-Boot] On writing .ext4 image to MMC

[Michael Nazzareno Trimarchi]

Hi


resize2fs from linux?

Michael

On Fri, Jan 12, 2018 at 4:15 PM, Adam Lee  wrote:
> Hello everyone,
>
> I am able to download a .ext4 image over tftp and write it to my SD card.
> The system boots fine.
> One last thing I have to figure out is to expand this .ext4 file system
> that I just populated.
> If the image is 600MB, the partition size itself is 600MB, leaving no room.
>
> Is there anything I can do to remedy this in U-Boot?
>
> Adam
> ___
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> https://lists.denx.de/listinfo/u-boot



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[U-Boot] On writing .ext4 image to MMC

[Adam Lee]

Hello everyone,

I am able to download a .ext4 image over tftp and write it to my SD card.
The system boots fine.
One last thing I have to figure out is to expand this .ext4 file system
that I just populated.
If the image is 600MB, the partition size itself is 600MB, leaving no room.

Is there anything I can do to remedy this in U-Boot?

Adam
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Re: [U-Boot] [U-Boot, v4, 07/11] spl: add support to booting with OP-TEE

[Bryan O'Donoghue]

On 12/01/18 11:27, Philipp Tomsich wrote:

OP-TEE is an open source trusted OS, in armv7, its loading and
running are like this:
loading:
- SPL load both OP-TEE and U-Boot
running:
- SPL run into OP-TEE in secure mode;
- OP-TEE run into U-Boot in non-secure mode;

More detail:
https://github.com/OP-TEE/optee_os
and search for 'boot arguments' for detail entry parameter in:
core/arch/arm/kernel/generic_entry_a32.S

Signed-off-by: Kever Yang 
---

Changes in v4:
- use NULL instead of '0'
- add fdt_addr as arg2 of entry

Changes in v3: None
Changes in v2:
- Using new image type for op-tee

  common/spl/Kconfig |  7 +++
  common/spl/Makefile|  1 +
  common/spl/spl.c   |  9 +
  common/spl/spl_optee.S | 13 +
  include/spl.h  | 13 +
  5 files changed, 43 insertions(+)
  create mode 100644 common/spl/spl_optee.S



Acked-by: Philipp Tomsich 
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Kever, Philipp

I have patches that define a IH_TYPE_OPTEE as a bootable OPTEE image 
(one that never returns to u-boot).


The image type allows bootm to identify the type of binary it is booting 
and perform image-specific checks.


On this patch though, do you guys really need a new image type for SPL ? 
Couldn't you use IH_TYPE_TEE in the same way ?


+#if CONFIG_IS_ENABLED(OPTEE)
+   case IH_TYPE_TEE:
+   debug("Jumping to U-Boot via OP-TEE\n");
+   spl_optee_entry(NULL, NULL, spl_image->fdt_addr,
+   (void *)spl_image.entry_point);
+   break;
+#endif

i.e. it appears to me as if you don't actually do anything 
image-specific with IH_OS_OP_TEE that couldn't be done with the existing 
IH_TYPE_TEE... as above you use spl_image->fdt_addr and 
spl_image.entry_point - as opposed to any header specific data from the 
binary you are booting..


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Re: [U-Boot] [PATCH v2 0/9] reduce the size of the mmc core

[Jaehoon Chung]

On 01/04/2018 11:23 PM, Jean-Jacques Hiblot wrote:
> 
> This series applies on u-boot/next
> 
> It aims at reducing the size taken by the mmc core in the SPL.
> Recent changes (for which I'm to blame) have bloated the mmc core and have
> broken platforms that were already tight on code space. This is achieved 
> mostly
> by compiling out parts of the initialization process that are not required 
> when
> the SD/MMC write operations are not used.
> 
> Using am335x_hs_evm_config and Linaro GCC 6.2-2016.11 toolchain, this series
> saves 624 bytes of sram (512 bytes of code and 112 bytes of rodata).
> This doesn't looks like much but it allows building the platform without
> removing features from its config file (tested with commit d2ac491
> ("am335x_hs_evm: Trim options in SPL to reduce binary size") reverted)
> 
> Changes in v2:
> - atmel_mci: fixed v1 bug by setting the block length before each transfer.
> - atmel_mci: removed loop to read/write dummy data as it is not needed anymore
> - compile out code for HS200 in mmc_get_capabilities()
> - fixed usage of CONFIG_IS_ENABLED() in the definition of mmc_blk_ops
> - default SPL_MMC_WRITE to 'n'
> - removed patch 'mmc: remove unneeded verification in mmc_set_card_speed()'
> 
> Jean-Jacques Hiblot (9):
>   common: do not compile common fastboot code when building the SPL
>   mmc: atmel: when sending a data command, use the provided block size
>   mmc: compile out more code if support for UHS and HS200 is not enabled
>   mmc: reworked version lookup in mmc_startup_v4
>   mmc: add a Kconfig option to enable the support for MMC write
> operations
>   mmc: read ssr only if MMC write support is enabled
>   mmc: compile out erase and write mmc commands if write operations are
> not enabled
>   mmc: don't read the size of eMMC enhanced user data area in SPL
>   mmc: remove hc_wp_grp_size from struct mmc if not needed

Applied to u-boot-mmc. Thanks!

Best Regards,
Jaehoon Chung

> 
>  cmd/mmc.c   | 10 +
>  cmd/mvebu/bubt.c|  2 +-
>  common/Makefile |  2 +
>  common/spl/Kconfig  |  9 +
>  drivers/mmc/Kconfig |  7 
>  drivers/mmc/Makefile|  4 +-
>  drivers/mmc/gen_atmel_mci.c | 42 +--
>  drivers/mmc/mmc-uclass.c|  2 +-
>  drivers/mmc/mmc.c   | 99 
> +++--
>  drivers/mmc/mmc_private.h   |  4 +-
>  include/mmc.h   |  8 
>  11 files changed, 121 insertions(+), 68 deletions(-)
> 

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[U-Boot] [PATCH 4/9] optee: Add optee_image_get_entry_point()

[Bryan O'Donoghue]

Add a helper function for extracting the least significant 32 bits from the
OPTEE entry point address, which will be good enough to load OPTEE binaries
up to (2^32)-1 bytes.

We may need to extend this out later on but for now (2^32)-1 should be
fine.

Signed-off-by: Bryan O'Donoghue 
Cc: Harinarayan Bhatta 
Cc: Andrew F. Davis 
Cc: Tom Rini 
Cc: Kever Yang 
Cc: Philipp Tomsich 
Cc: Peng Fan 
---
 include/tee/optee.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/include/tee/optee.h b/include/tee/optee.h
index 8943afb..eb328d3 100644
--- a/include/tee/optee.h
+++ b/include/tee/optee.h
@@ -29,6 +29,13 @@ struct optee_header {
uint32_t paged_size;
 };
 
+static inline uint32_t optee_image_get_entry_point(const image_header_t *hdr)
+{
+   struct optee_header *optee_hdr = (struct optee_header *)(hdr + 1);
+
+   return optee_hdr->init_load_addr_lo;
+}
+
 #if defined(CONFIG_OPTEE)
 int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
   unsigned long tzdram_len, unsigned long image_len);
-- 
2.7.4

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[U-Boot] [PATCH 3/9] optee: Make OPTEE_TZDRAM_BASE a mandatory define

[Bryan O'Donoghue]

This patch makes OTPEE_TZDRAM_BASE a mandatory parameter.
Subsequent patches will ensure that the region between
OTPEE_TZDRAM_BASE and (OTPEE_TZDRAM_BASE +
CONFIG_OPTEE_TZDRAM_SIZE) match the information given in the OPTEE header
before handing off control to the OPTEE image when booting OPTEE directly
via bootm.

Signed-off-by: Bryan O'Donoghue 
Cc: Harinarayan Bhatta 
Cc: Andrew F. Davis 
Cc: Tom Rini 
Cc: Kever Yang 
Cc: Philipp Tomsich 
Cc: Peng Fan 
---
 lib/optee/optee.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/lib/optee/optee.c b/lib/optee/optee.c
index a6c856a..6e55027 100644
--- a/lib/optee/optee.c
+++ b/lib/optee/optee.c
@@ -5,9 +5,14 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
+#include 
 #include 
 #include 
 
+#ifndef OPTEE_TZDRAM_BASE
+#error "OPTEE_TZDRAM_BASE not defined"
+#endif
+
 int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
   unsigned long tzdram_len, unsigned long image_len)
 {
-- 
2.7.4

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[U-Boot] [PATCH 9/9] bootm: optee: Add mechanism to validate an OPTEE image before boot

[Bryan O'Donoghue]

This patch makes it possible to verify the contents and location of an
OPTEE image in DRAM prior to handing off control to that image. If image
verification fails we won't try to boot any further.

Signed-off-by: Bryan O'Donoghue 
Cc: Harinarayan Bhatta 
Cc: Andrew F. Davis 
Cc: Tom Rini 
Cc: Kever Yang 
Cc: Philipp Tomsich 
Cc: Peng Fan 
---
 common/bootm.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/common/bootm.c b/common/bootm.c
index 9493a30..38c1b0a 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #if defined(CONFIG_CMD_USB)
 #include 
 #endif
@@ -201,6 +202,12 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int 
argc,
if (images.os.type == IH_TYPE_KERNEL_NOLOAD) {
images.os.load = images.os.image_start;
images.ep += images.os.load;
+   } else if (images.os.type == IH_TYPE_OPTEE) {
+   ret = optee_verify_bootm_image(images.os.image_start,
+  images.os.load,
+  images.os.image_len);
+   if (ret)
+   return ret;
}
 
images.os.start = map_to_sysmem(os_hdr);
@@ -275,7 +282,8 @@ static int bootm_find_other(cmd_tbl_t *cmdtp, int flag, int 
argc,
 {
if (((images.os.type == IH_TYPE_KERNEL) ||
 (images.os.type == IH_TYPE_KERNEL_NOLOAD) ||
-(images.os.type == IH_TYPE_MULTI)) &&
+(images.os.type == IH_TYPE_MULTI) ||
+(images.os.type == IH_TYPE_OPTEE)) &&
(images.os.os == IH_OS_LINUX ||
 images.os.os == IH_OS_VXWORKS))
return bootm_find_images(flag, argc, argv);
@@ -827,6 +835,7 @@ static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int 
flag, int argc,
switch (image_get_type(hdr)) {
case IH_TYPE_KERNEL:
case IH_TYPE_KERNEL_NOLOAD:
+   case IH_TYPE_OPTEE:
*os_data = image_get_data(hdr);
*os_len = image_get_data_size(hdr);
break;
-- 
2.7.4

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[U-Boot] [PATCH 8/9] optee: Improve error printout

[Bryan O'Donoghue]

When encountering an error in OPTEE verification print out the address of
the header and image.

Signed-off-by: Bryan O'Donoghue 
Cc: Harinarayan Bhatta 
Cc: Andrew F. Davis 
Cc: Tom Rini 
Cc: Kever Yang 
Cc: Philipp Tomsich 
Cc: Peng Fan 
---
 lib/optee/optee.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/lib/optee/optee.c b/lib/optee/optee.c
index 36358f1..8c4e7fe 100644
--- a/lib/optee/optee.c
+++ b/lib/optee/optee.c
@@ -56,10 +56,12 @@ int optee_verify_bootm_image(unsigned long image_addr,
 
return ret;
 error:
-   printf("OPTEE verification error tzdram 0x%08lx-0x%08lx "
-  "header 0x%08x-0x%08x size=0x%08lx arch=0x%08x"
-  "uimage params 0x%08lx-0x%08lx\n",
-  tzdram_start, tzdram_start + tzdram_len, hdr->init_load_addr_lo,
+   printf("OPTEE verification error:"
+  "\n\thdr=%p image=0x%08lx magic=0x%08x tzdram 0x%08lx-0x%08lx "
+  "\n\theader lo=0x%08x hi=0x%08x size=0x%08lx arch=0x%08x"
+  "\n\tuimage params 0x%08lx-0x%08lx\n",
+  hdr, image_addr, hdr->magic, tzdram_start,
+  tzdram_start + tzdram_len, hdr->init_load_addr_lo,
   hdr->init_load_addr_hi, image_len, hdr->arch, image_load_addr,
   image_load_addr + image_len);
 
-- 
2.7.4

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[U-Boot] [PATCH 6/9] tools: mkimage: add optee image type

[Bryan O'Donoghue]

This patch adds support for bootable OPTEE images to mkimage. Currently
there is a (Trusted Execution Environment) TEE image type, the TEE image
type is installed to a memory location with u-boot continuing to own the
boot process whereas the OPTEE image type defined here is a bootable image,
which typically wants to live at a defined location in memory. Defining a
new image type allows us to pull out the load address and entry point
defined in the OPTEE header and having a separate image type lays the
foundation for a subsequent patch to validate the OPTEE memory defined in a
board-port matches the link location specified in the OPTEE bootable
image.

example usage:

mkimage -A arm -T optee -C none -d ./out/arm-plat-imx/core/tee.bin
uTee.optee

Signed-off-by: Bryan O'Donoghue 
Cc: Harinarayan Bhatta 
Cc: Andrew F. Davis 
Cc: Tom Rini 
Cc: Kever Yang 
Cc: Philipp Tomsich 
Cc: Peng Fan 
---
 common/image.c|  1 +
 include/image.h   |  1 +
 tools/default_image.c | 25 +++--
 3 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/common/image.c b/common/image.c
index 4bcf6b3..381ef07 100644
--- a/common/image.c
+++ b/common/image.c
@@ -161,6 +161,7 @@ static const table_entry_t uimage_type[] = {
{   IH_TYPE_TEE,"tee","Trusted Execution 
Environment Image",},
{   IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" 
},
{   IH_TYPE_PMMC,"pmmc","TI Power Management 
Micro-Controller Firmware",},
+   {   IH_TYPE_OPTEE,   "optee", "OPTEE Boot Image",},
{   -1, "",   "",   },
 };
 
diff --git a/include/image.h b/include/image.h
index a128a62..9175624 100644
--- a/include/image.h
+++ b/include/image.h
@@ -271,6 +271,7 @@ enum {
IH_TYPE_TEE,/* Trusted Execution Environment OS Image */
IH_TYPE_FIRMWARE_IVT,   /* Firmware Image with HABv4 IVT */
IH_TYPE_PMMC,/* TI Power Management Micro-Controller 
Firmware */
+   IH_TYPE_OPTEE,  /* OPTEE Boot Image */
 
IH_TYPE_COUNT,  /* Number of image types */
 };
diff --git a/tools/default_image.c b/tools/default_image.c
index 4e5568e..5653933 100644
--- a/tools/default_image.c
+++ b/tools/default_image.c
@@ -18,6 +18,7 @@
 #include "mkimage.h"
 
 #include 
+#include 
 #include 
 
 static image_header_t header;
@@ -25,7 +26,8 @@ static image_header_t header;
 static int image_check_image_types(uint8_t type)
 {
if (((type > IH_TYPE_INVALID) && (type < IH_TYPE_FLATDT)) ||
-   (type == IH_TYPE_KERNEL_NOLOAD) || (type == IH_TYPE_FIRMWARE_IVT))
+   (type == IH_TYPE_KERNEL_NOLOAD) || (type == IH_TYPE_FIRMWARE_IVT) ||
+   (type == IH_TYPE_OPTEE))
return EXIT_SUCCESS;
else
return EXIT_FAILURE;
@@ -90,6 +92,8 @@ static void image_set_header(void *ptr, struct stat *sbuf, 
int ifd,
uint32_t checksum;
time_t time;
uint32_t imagesize;
+   uint32_t ep;
+   uint32_t addr;
 
image_header_t * hdr = (image_header_t *)ptr;
 
@@ -99,18 +103,27 @@ static void image_set_header(void *ptr, struct stat *sbuf, 
int ifd,
sbuf->st_size - sizeof(image_header_t));
 
time = imagetool_get_source_date(params, sbuf->st_mtime);
-   if (params->type == IH_TYPE_FIRMWARE_IVT)
+   ep = params->ep;
+   addr = params->addr;
+   imagesize = sbuf->st_size - sizeof(image_header_t);
+
+   switch (params->type) {
+   case IH_TYPE_FIRMWARE_IVT:
/* Add size of CSF minus IVT */
imagesize = sbuf->st_size - sizeof(image_header_t) + 0x1FE0;
-   else
-   imagesize = sbuf->st_size - sizeof(image_header_t);
+   break;
+   case IH_TYPE_OPTEE:
+   addr = optee_image_get_load_addr(hdr);
+   ep = optee_image_get_entry_point(hdr);
+   break;
+   }
 
/* Build new header */
image_set_magic(hdr, IH_MAGIC);
image_set_time(hdr, time);
image_set_size(hdr, imagesize);
-   image_set_load(hdr, params->addr);
-   image_set_ep(hdr, params->ep);
+   image_set_load(hdr, addr);
+   image_set_ep(hdr, ep);
image_set_dcrc(hdr, checksum);
image_set_os(hdr, params->os);
image_set_arch(hdr, params->arch);
-- 
2.7.4

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[U-Boot] [PATCH 5/9] optee: Add optee_image_get_load_addr()

[Bryan O'Donoghue]

This patch adds optee_image_get_load_addr() a helper function used to
calculate the load-address of an OPTEE image based on the lower
entry-point address given in the OPTEE header.

Signed-off-by: Bryan O'Donoghue 
Cc: Harinarayan Bhatta 
Cc: Andrew F. Davis 
Cc: Tom Rini 
Cc: Kever Yang 
Cc: Philipp Tomsich 
Cc: Peng Fan 
---
 include/tee/optee.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/include/tee/optee.h b/include/tee/optee.h
index eb328d3..e782cb0 100644
--- a/include/tee/optee.h
+++ b/include/tee/optee.h
@@ -36,6 +36,11 @@ static inline uint32_t optee_image_get_entry_point(const 
image_header_t *hdr)
return optee_hdr->init_load_addr_lo;
 }
 
+static inline uint32_t optee_image_get_load_addr(const image_header_t *hdr)
+{
+   return optee_image_get_entry_point(hdr) - sizeof(struct optee_header);
+}
+
 #if defined(CONFIG_OPTEE)
 int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
   unsigned long tzdram_len, unsigned long image_len);
-- 
2.7.4

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[U-Boot] [PATCH 7/9] optee: Add optee_verify_bootm_image()

[Bryan O'Donoghue]

This patch adds optee_verify_bootm_image() which will be subsequently used
to verify the parameters encoded in the OPTEE header match the memory
allocated to the OPTEE region, OPTEE header magic and version prior to
handing off control to the OPTEE image.

Signed-off-by: Bryan O'Donoghue 
Cc: Harinarayan Bhatta 
Cc: Andrew F. Davis 
Cc: Tom Rini 
Cc: Kever Yang 
Cc: Philipp Tomsich 
Cc: Peng Fan 
---
 include/tee/optee.h | 13 +
 lib/optee/optee.c   | 35 +++
 2 files changed, 44 insertions(+), 4 deletions(-)

diff --git a/include/tee/optee.h b/include/tee/optee.h
index e782cb0..4b9e94c 100644
--- a/include/tee/optee.h
+++ b/include/tee/optee.h
@@ -55,4 +55,17 @@ static inline int optee_verify_image(struct optee_header 
*hdr,
 
 #endif
 
+#if defined(CONFIG_OPTEE)
+int optee_verify_bootm_image(unsigned long image_addr,
+unsigned long image_load_addr,
+unsigned long image_len);
+#else
+static inline int optee_verify_bootm_image(unsigned long image_addr,
+  unsigned long image_load_addr,
+  unsigned long image_len)
+{
+   return -EPERM;
+}
+#endif
+
 #endif /* _OPTEE_H */
diff --git a/lib/optee/optee.c b/lib/optee/optee.c
index 6e55027..36358f1 100644
--- a/lib/optee/optee.c
+++ b/lib/optee/optee.c
@@ -29,12 +29,39 @@ int optee_verify_image(struct optee_header *hdr, unsigned 
long tzdram_start,
(tee_file_size > tzdram_len) ||
(tee_file_size != image_len) ||
((hdr->init_load_addr_lo + tee_file_size) > tzdram_end)) {
-   printf("OPTEE verification error tzdram 0x%08lx-0x%08lx "
-  "header lo=0x%08x hi=0x%08x size=0x%08x\n",
-  tzdram_start, tzdram_end, hdr->init_load_addr_lo,
-  hdr->init_load_addr_hi, tee_file_size);
return -EINVAL;
}
 
return 0;
 }
+
+int optee_verify_bootm_image(unsigned long image_addr,
+unsigned long image_load_addr,
+unsigned long image_len)
+{
+   struct optee_header *hdr = (struct optee_header *)image_addr;
+   unsigned long tzdram_start = OPTEE_TZDRAM_BASE;
+   unsigned long tzdram_len = CONFIG_OPTEE_TZDRAM_SIZE;
+
+   int ret;
+
+   ret = optee_verify_image(hdr, tzdram_start, tzdram_len, image_len);
+   if (ret)
+   goto error;
+
+   if (image_load_addr + sizeof(*hdr) != hdr->init_load_addr_lo) {
+   ret = -EINVAL;
+   goto error;
+   }
+
+   return ret;
+error:
+   printf("OPTEE verification error tzdram 0x%08lx-0x%08lx "
+  "header 0x%08x-0x%08x size=0x%08lx arch=0x%08x"
+  "uimage params 0x%08lx-0x%08lx\n",
+  tzdram_start, tzdram_start + tzdram_len, hdr->init_load_addr_lo,
+  hdr->init_load_addr_hi, image_len, hdr->arch, image_load_addr,
+  image_load_addr + image_len);
+
+   return ret;
+}
-- 
2.7.4

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[U-Boot] [PATCH 2/9] optee: Add CONFIG_OPTEE_TZDRAM_SIZE

[Bryan O'Donoghue]

OPTEE is currently linked to a specific area of memory called the TrustZone
DRAM. This patch adds a CONFIG entry for the default size of TrustZone DRAM
that a board-port can over-ride. The region that U-Boot sets aside for the
OPTEE run-time should be verified before attempting to hand off to the
OPTEE run-time. Each board-port should carefully ensure that the TZDRAM
size specified in the OPTEE build and the TZDRAM size specified in U-Boot
match-up.

Further patches will use TZDRAM size and other defines and variables to
carry out a degree of automated verification in U-Boot prior to trying to
boot an OPTEE image.

Signed-off-by: Bryan O'Donoghue 
Cc: Harinarayan Bhatta 
Cc: Andrew F. Davis 
Cc: Tom Rini 
Cc: Kever Yang 
Cc: Philipp Tomsich 
Cc: Peng Fan 
---
 lib/optee/Kconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/lib/optee/Kconfig b/lib/optee/Kconfig
index 2e406fe..41c0ab7 100644
--- a/lib/optee/Kconfig
+++ b/lib/optee/Kconfig
@@ -6,3 +6,11 @@ config OPTEE
   enable an OPTEE specific bootm command that will perform additional
   OPTEE specific checks before booting an OPTEE image created with
   mkimage.
+
+config OPTEE_TZDRAM_SIZE
+   hex "Amount of Trust-Zone RAM for the OPTEE image"
+   depends on OPTEE
+   default 0x300
+   help
+ The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE
+ runtime.
-- 
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[U-Boot] [PATCH 1/9] optee: Add lib entries for sharing OPTEE code across ports

[Bryan O'Donoghue]

This patch adds code to lib to enable sharing of useful OPTEE code between
board-ports and architectures. The code on lib/optee/optee.c comes from the
TI omap2 port. Eventually the OMAP2 code will be patched to include the
shared code. The intention here is to add more useful OPTEE specific code
as more functionality gets added.

Signed-off-by: Bryan O'Donoghue 
Cc: Harinarayan Bhatta 
Cc: Andrew F. Davis 
Cc: Tom Rini 
Cc: Kever Yang 
Cc: Philipp Tomsich 
Cc: Peng Fan 
---
 include/tee/optee.h | 16 
 lib/Kconfig |  1 +
 lib/Makefile|  1 +
 lib/optee/Kconfig   |  8 
 lib/optee/Makefile  |  7 +++
 lib/optee/optee.c   | 35 +++
 6 files changed, 68 insertions(+)
 create mode 100644 lib/optee/Kconfig
 create mode 100644 lib/optee/Makefile
 create mode 100644 lib/optee/optee.c

diff --git a/include/tee/optee.h b/include/tee/optee.h
index 9ab0d08..8943afb 100644
--- a/include/tee/optee.h
+++ b/include/tee/optee.h
@@ -10,6 +10,8 @@
 #ifndef_OPTEE_H
 #define _OPTEE_H
 
+#include 
+
 #define OPTEE_MAGIC 0x4554504f
 #define OPTEE_VERSION   1
 #define OPTEE_ARCH_ARM320
@@ -27,4 +29,18 @@ struct optee_header {
uint32_t paged_size;
 };
 
+#if defined(CONFIG_OPTEE)
+int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
+  unsigned long tzdram_len, unsigned long image_len);
+#else
+static inline int optee_verify_image(struct optee_header *hdr,
+unsigned long tzdram_start,
+unsigned long tzdram_len,
+unsigned long image_len)
+{
+   return -EPERM;
+}
+
+#endif
+
 #endif /* _OPTEE_H */
diff --git a/lib/Kconfig b/lib/Kconfig
index f447c53..5742fb7 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -278,5 +278,6 @@ endmenu
 
 source lib/efi/Kconfig
 source lib/efi_loader/Kconfig
+source lib/optee/Kconfig
 
 endmenu
diff --git a/lib/Makefile b/lib/Makefile
index 8cd779f..46813b6 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_FIT) += libfdt/
 obj-$(CONFIG_OF_LIVE) += of_live.o
 obj-$(CONFIG_CMD_DHRYSTONE) += dhry/
 obj-$(CONFIG_ARCH_AT91) += at91/
+obj-$(CONFIG_OPTEE) += optee/
 
 obj-$(CONFIG_AES) += aes.o
 obj-y += charset.o
diff --git a/lib/optee/Kconfig b/lib/optee/Kconfig
new file mode 100644
index 000..2e406fe
--- /dev/null
+++ b/lib/optee/Kconfig
@@ -0,0 +1,8 @@
+config OPTEE
+   bool "Support OPTEE images"
+   help
+ U-Boot can be configured to boot OPTEE images.
+ Selecting this option will enable shared OPTEE library code and
+  enable an OPTEE specific bootm command that will perform additional
+  OPTEE specific checks before booting an OPTEE image created with
+  mkimage.
diff --git a/lib/optee/Makefile b/lib/optee/Makefile
new file mode 100644
index 000..03e832f
--- /dev/null
+++ b/lib/optee/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2017 Linaro
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_OPTEE) += optee.o
diff --git a/lib/optee/optee.c b/lib/optee/optee.c
new file mode 100644
index 000..a6c856a
--- /dev/null
+++ b/lib/optee/optee.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2017 Linaro
+ * Bryan O'Donoghue 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
+  unsigned long tzdram_len, unsigned long image_len)
+{
+   unsigned long tzdram_end = tzdram_start + tzdram_len;
+   uint32_t tee_file_size;
+
+   tee_file_size = hdr->init_size + hdr->paged_size +
+   sizeof(struct optee_header);
+
+   if ((hdr->magic != OPTEE_MAGIC) ||
+   (hdr->version != OPTEE_VERSION) ||
+   (hdr->init_load_addr_hi > tzdram_end) ||
+   (hdr->init_load_addr_lo < tzdram_start) ||
+   (tee_file_size > tzdram_len) ||
+   (tee_file_size != image_len) ||
+   ((hdr->init_load_addr_lo + tee_file_size) > tzdram_end)) {
+   printf("OPTEE verification error tzdram 0x%08lx-0x%08lx "
+  "header lo=0x%08x hi=0x%08x size=0x%08x\n",
+  tzdram_start, tzdram_end, hdr->init_load_addr_lo,
+  hdr->init_load_addr_hi, tee_file_size);
+   return -EINVAL;
+   }
+
+   return 0;
+}
-- 
2.7.4

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[U-Boot] [PATCH 0/9] Add new OPTEE bootm support to u-boot

[Bryan O'Donoghue]

This series adds a new OPTEE bootable image type to u-boot, which is
directly bootable with the bootm command.

There is already a TEE image type but, in this case the TEE firmware is
loaded into RAM, jumped into and then back out of. This image type is a
directly bootable image as described here :
http://mrvan.github.io/optee-imx6ul

Instead of reusing the Linux bootable image type instead a new image type
is defined, which allows us to perform additional image verification, prior
to handing off control via bootm.

OPTEE images get linked to a specific address at compile time and must be
loaded to this address too. This series extends out mkimage with a new
image type that allows the OPTEE binary link location to be validated
against CONFIG_OPTEE_TZDRAM_BASE and CONFIG_OPTEE_TZDRAM_SIZE respectively
prior to proceeding through the bootm phase.

Once applied you can generate a bootable OPTEE image like this

mkimage -A arm -T optee -C none -d ./out/arm-plat-imx/core/tee.bin uTee.optee

That image can then be booted directly by bootm. bootm will verify the
header contents of the OPTEE binary against the DRAM area carved out in
u-boot. If the defined DRAM area does not match the link address specified
we refuse to boot.

Kever - I'd like to suggest that your OPTEE SPL image takes a different
image type IH_TYPE_OPTEE_SPL ? to indicate the different behavior your
image type has versus a directly bootable bootm image.

Bryan O'Donoghue (9):
  optee: Add lib entries for sharing OPTEE code across ports
  optee: Add CONFIG_OPTEE_TZDRAM_SIZE
  optee: Make OPTEE_TZDRAM_BASE a mandatory define
  optee: Add optee_image_get_entry_point()
  optee: Add optee_image_get_load_addr()
  tools: mkimage: add optee image type
  optee: Add optee_verify_bootm_image()
  optee: Improve error printout
  bootm: optee: Add mechanism to validate an OPTEE image before boot

 common/bootm.c| 11 +++-
 common/image.c|  1 +
 include/image.h   |  1 +
 include/tee/optee.h   | 41 ++
 lib/Kconfig   |  1 +
 lib/Makefile  |  1 +
 lib/optee/Kconfig | 16 
 lib/optee/Makefile|  7 ++
 lib/optee/optee.c | 69 +++
 tools/default_image.c | 25 ++-
 10 files changed, 166 insertions(+), 7 deletions(-)
 create mode 100644 lib/optee/Kconfig
 create mode 100644 lib/optee/Makefile
 create mode 100644 lib/optee/optee.c

-- 
2.7.4

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[U-Boot] [PATCH 5/5] arm: zynq: Add support for zc770-xm011-x16 configuration

[Michal Simek]

zc770-xm011 is x8 width configuration. This FMC card has also x16
variant which requires different ps7_init configuration. This patch adds
it.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynq-zc770-xm011-x16.dts  |   1 +
 .../zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c   | 782 +
 configs/zynq_zc770_xm011_x16_defconfig |  44 ++
 3 files changed, 827 insertions(+)
 create mode 12 arch/arm/dts/zynq-zc770-xm011-x16.dts
 create mode 100644 board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
 create mode 100644 configs/zynq_zc770_xm011_x16_defconfig

diff --git a/arch/arm/dts/zynq-zc770-xm011-x16.dts 
b/arch/arm/dts/zynq-zc770-xm011-x16.dts
new file mode 12
index ..5bd6af39a437
--- /dev/null
+++ b/arch/arm/dts/zynq-zc770-xm011-x16.dts
@@ -0,0 +1 @@
+zynq-zc770-xm011.dts
\ No newline at end of file
diff --git a/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c 
b/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
new file mode 100644
index ..f7ca84e58d10
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
@@ -0,0 +1,782 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0xF8000110, 0x0030U, 0x000FA220U),
+   EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+   EMIT_MASKWRITE(0xF8000100, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000100, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000100, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0001U),
+   EMIT_MASKWRITE(0xF8000100, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+   EMIT_MASKWRITE(0xF8000114, 0x0030U, 0x0012C220U),
+   EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x0002U),
+   EMIT_MASKWRITE(0xF8000104, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000104, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000104, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0002U),
+   EMIT_MASKWRITE(0xF8000104, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF8000124, 0xFFF3U, 0x0C23U),
+   EMIT_MASKWRITE(0xF8000118, 0x0030U, 0x001452C0U),
+   EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+   EMIT_MASKWRITE(0xF8000108, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000108, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000108, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0004U),
+   EMIT_MASKWRITE(0xF8000108, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF804, 0xU, 0x767BU),
+   EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+   EMIT_MASKWRITE(0xF8000148, 0x3F31U, 0x0A01U),
+   EMIT_MASKWRITE(0xF8000154, 0x3F33U, 0x1402U),
+   EMIT_MASKWRITE(0xF8000158, 0x3F33U, 0x0601U),
+   EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+   EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0xU),
+   EMIT_MASKWRITE(0xF8000168, 0x3F31U, 0x0501U),
+   EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+   EMIT_MASKWRITE(0xF80001C4, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+   EMIT_MASKWRITE(0xF8000304, 0x0001U, 0xU),
+   EMIT_MASKWRITE(0xF804, 0xU, 0x767BU),
+   EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF8006000, 0x0001U, 0x0080U),
+   EMIT_MASKWRITE(0xF8006004, 0x0007U, 0x1081U),
+   EMIT_MASKWRITE(0xF8006008, 0x03FFU, 0x03C0780FU),
+   EMIT_MASKWRITE(0xF800600C, 0x03FFU, 0x02001001U),
+   EMIT_MASKWRITE(0xF8006010, 0x03FFU, 0x00014001U),
+   EMIT_MASKWRITE(0xF8006014, 0x001FU, 0x0004159BU),
+   EMIT_MASKWRITE(0xF8006018, 0xF7FFU, 0x44E438D2U),
+   EMIT_MASKWRITE(0xF800601C, 0xU, 0x720238E5U),
+   EMIT_MASKWRITE(0xF8006020, 0x7FDCU, 0x27087290U),
+   EMIT_MASKWRITE(0xF8006024, 0x0FC3U, 0xU),
+   EMIT_MASKWRITE(0xF8006028, 0x3FFFU, 0x2007U),
+   EMIT_MASKWRITE(0xF800602C, 0xU, 0x0008U),
+   EMIT_MASKWRITE(0xF8006030, 0xU, 0x00040930U),
+   EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+   EMIT_MASKWRITE(0xF8006038, 0x0003U, 0xU),
+   EMIT_MASKWRITE(0xF800603C, 0x000FU, 0x0777U),
+   EMIT_MASKWRITE(0xF8006040, 0xU, 0xFFF0U),
+   EMIT_MASKWRITE(0xF8006044, 0x0FFFU, 0x0F66U),
+   EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+  

[U-Boot] [PATCH 4/5] arm: zynq: Add zc770-xm013 spl configuration

[Michal Simek]

Simplify ps7_init* initialization.

Signed-off-by: Michal Simek 
---

 board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c | 767 ++
 1 file changed, 767 insertions(+)
 create mode 100644 board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c

diff --git a/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c 
b/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
new file mode 100644
index ..7827daad9ac9
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
@@ -0,0 +1,767 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0xF8000110, 0x0030U, 0x000FA220U),
+   EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+   EMIT_MASKWRITE(0xF8000100, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000100, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000100, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0001U),
+   EMIT_MASKWRITE(0xF8000100, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+   EMIT_MASKWRITE(0xF8000114, 0x0030U, 0x0012C220U),
+   EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x0002U),
+   EMIT_MASKWRITE(0xF8000104, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000104, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000104, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0002U),
+   EMIT_MASKWRITE(0xF8000104, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF8000124, 0xFFF3U, 0x0C23U),
+   EMIT_MASKWRITE(0xF8000118, 0x0030U, 0x001452C0U),
+   EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+   EMIT_MASKWRITE(0xF8000108, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000108, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000108, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0004U),
+   EMIT_MASKWRITE(0xF8000108, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF804, 0xU, 0x767BU),
+   EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+   EMIT_MASKWRITE(0xF800013C, 0x0011U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100801U),
+   EMIT_MASKWRITE(0xF800014C, 0x3F31U, 0x0501U),
+   EMIT_MASKWRITE(0xF8000154, 0x3F33U, 0x1401U),
+   EMIT_MASKWRITE(0xF8000158, 0x3F33U, 0x0601U),
+   EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600702U),
+   EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0xU),
+   EMIT_MASKWRITE(0xF8000168, 0x3F31U, 0x0401U),
+   EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+   EMIT_MASKWRITE(0xF80001C4, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01DE408DU),
+   EMIT_MASKWRITE(0xF8000304, 0x0001U, 0xU),
+   EMIT_MASKWRITE(0xF804, 0xU, 0x767BU),
+   EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF8006000, 0x0001U, 0x0080U),
+   EMIT_MASKWRITE(0xF8006004, 0x0007U, 0x1081U),
+   EMIT_MASKWRITE(0xF8006008, 0x03FFU, 0x03C0780FU),
+   EMIT_MASKWRITE(0xF800600C, 0x03FFU, 0x02001001U),
+   EMIT_MASKWRITE(0xF8006010, 0x03FFU, 0x00014001U),
+   EMIT_MASKWRITE(0xF8006014, 0x001FU, 0x0004159BU),
+   EMIT_MASKWRITE(0xF8006018, 0xF7FFU, 0x44E438D2U),
+   EMIT_MASKWRITE(0xF800601C, 0xU, 0x720238E5U),
+   EMIT_MASKWRITE(0xF8006020, 0x7FDCU, 0x27087290U),
+   EMIT_MASKWRITE(0xF8006024, 0x0FC3U, 0xU),
+   EMIT_MASKWRITE(0xF8006028, 0x3FFFU, 0x2007U),
+   EMIT_MASKWRITE(0xF800602C, 0xU, 0x0008U),
+   EMIT_MASKWRITE(0xF8006030, 0xU, 0x00040930U),
+   EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+   EMIT_MASKWRITE(0xF8006038, 0x0003U, 0xU),
+   EMIT_MASKWRITE(0xF800603C, 0x000FU, 0x0777U),
+   EMIT_MASKWRITE(0xF8006040, 0xU, 0xFFF0U),
+   EMIT_MASKWRITE(0xF8006044, 0x0FFFU, 0x0F66U),
+   EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+   EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+   EMIT_MASKWRITE(0xF8006058, 0x0001U, 0xU),
+   EMIT_MASKWRITE(0xF800605C, 0xU, 0x5003U),
+   EMIT_MASKWRITE(0xF8006060, 0x17FFU, 0x003EU),
+   EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x0002U),
+   EMIT_MASKWRITE(0xF8006068, 0x03FFU, 0x00284141U),
+   EMIT_MASKWRITE(0xF800606C, 0xU, 0x1610U),
+   EMIT_MASKWRITE(0xF8006078, 0x03FFU, 0x00466111U),
+   

[U-Boot] [PATCH 3/5] arm: zynq: Add zc770-xm012 spl configuration

[Michal Simek]

Simplify ps7_init* initialization.

Signed-off-by: Michal Simek 
---

 board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c | 818 ++
 1 file changed, 818 insertions(+)
 create mode 100644 board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c

diff --git a/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c 
b/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
new file mode 100644
index ..4471e1b46f4b
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
@@ -0,0 +1,818 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0xF8000110, 0x0030U, 0x000FA220U),
+   EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+   EMIT_MASKWRITE(0xF8000100, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000100, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000100, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0001U),
+   EMIT_MASKWRITE(0xF8000100, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+   EMIT_MASKWRITE(0xF8000114, 0x0030U, 0x0012C220U),
+   EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x0002U),
+   EMIT_MASKWRITE(0xF8000104, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000104, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000104, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0002U),
+   EMIT_MASKWRITE(0xF8000104, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF8000124, 0xFFF3U, 0x0C23U),
+   EMIT_MASKWRITE(0xF8000118, 0x0030U, 0x001452C0U),
+   EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+   EMIT_MASKWRITE(0xF8000108, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000108, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000108, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0004U),
+   EMIT_MASKWRITE(0xF8000108, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF804, 0xU, 0x767BU),
+   EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+   EMIT_MASKWRITE(0xF8000148, 0x3F31U, 0x0A01U),
+   EMIT_MASKWRITE(0xF8000154, 0x3F33U, 0x1402U),
+   EMIT_MASKWRITE(0xF8000158, 0x3F33U, 0x0602U),
+   EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00100102U),
+   EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x004CU),
+   EMIT_MASKWRITE(0xF8000168, 0x3F31U, 0x0501U),
+   EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+   EMIT_MASKWRITE(0xF80001C4, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016E800DU),
+   EMIT_MASKWRITE(0xF8000304, 0x0001U, 0xU),
+   EMIT_MASKWRITE(0xF804, 0xU, 0x767BU),
+   EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF8006000, 0x0001U, 0x0080U),
+   EMIT_MASKWRITE(0xF8006004, 0x0007U, 0x1081U),
+   EMIT_MASKWRITE(0xF8006008, 0x03FFU, 0x03C0780FU),
+   EMIT_MASKWRITE(0xF800600C, 0x03FFU, 0x02001001U),
+   EMIT_MASKWRITE(0xF8006010, 0x03FFU, 0x00014001U),
+   EMIT_MASKWRITE(0xF8006014, 0x001FU, 0x0004159BU),
+   EMIT_MASKWRITE(0xF8006018, 0xF7FFU, 0x44E438D2U),
+   EMIT_MASKWRITE(0xF800601C, 0xU, 0x720238E5U),
+   EMIT_MASKWRITE(0xF8006020, 0x7FDCU, 0x27087290U),
+   EMIT_MASKWRITE(0xF8006024, 0x0FC3U, 0xU),
+   EMIT_MASKWRITE(0xF8006028, 0x3FFFU, 0x2007U),
+   EMIT_MASKWRITE(0xF800602C, 0xU, 0x0008U),
+   EMIT_MASKWRITE(0xF8006030, 0xU, 0x00040930U),
+   EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+   EMIT_MASKWRITE(0xF8006038, 0x0003U, 0xU),
+   EMIT_MASKWRITE(0xF800603C, 0x000FU, 0x0777U),
+   EMIT_MASKWRITE(0xF8006040, 0xU, 0xFFF0U),
+   EMIT_MASKWRITE(0xF8006044, 0x0FFFU, 0x0F66U),
+   EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+   EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+   EMIT_MASKWRITE(0xF8006058, 0x0001U, 0xU),
+   EMIT_MASKWRITE(0xF800605C, 0xU, 0x5003U),
+   EMIT_MASKWRITE(0xF8006060, 0x17FFU, 0x003EU),
+   EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x0002U),
+   EMIT_MASKWRITE(0xF8006068, 0x03FFU, 0x00284141U),
+   EMIT_MASKWRITE(0xF800606C, 0xU, 0x1610U),
+   EMIT_MASKWRITE(0xF8006078, 0x03FFU, 0x00466111U),
+   EMIT_MASKWRITE(0xF800607C, 0x000FU, 0x0003U),
+   EMIT_MASKWRITE(0xF80060A4, 0xU, 0x10200802U),
+   

[U-Boot] [PATCH 2/5] arm: zynq: Add zc770-xm011 spl configuration

[Michal Simek]

Simplify ps7_init* initialization.

Signed-off-by: Michal Simek 
---

 board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c | 776 ++
 1 file changed, 776 insertions(+)
 create mode 100644 board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c

diff --git a/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c 
b/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
new file mode 100644
index ..245bef356bf6
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
@@ -0,0 +1,776 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0xF8000110, 0x0030U, 0x000FA220U),
+   EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+   EMIT_MASKWRITE(0xF8000100, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000100, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000100, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0001U),
+   EMIT_MASKWRITE(0xF8000100, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+   EMIT_MASKWRITE(0xF8000114, 0x0030U, 0x0012C220U),
+   EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x0002U),
+   EMIT_MASKWRITE(0xF8000104, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000104, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000104, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0002U),
+   EMIT_MASKWRITE(0xF8000104, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF8000124, 0xFFF3U, 0x0C23U),
+   EMIT_MASKWRITE(0xF8000118, 0x0030U, 0x001452C0U),
+   EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+   EMIT_MASKWRITE(0xF8000108, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000108, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000108, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0004U),
+   EMIT_MASKWRITE(0xF8000108, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF804, 0xU, 0x767BU),
+   EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+   EMIT_MASKWRITE(0xF8000148, 0x3F31U, 0x0A01U),
+   EMIT_MASKWRITE(0xF8000154, 0x3F33U, 0x1402U),
+   EMIT_MASKWRITE(0xF8000158, 0x3F33U, 0x0601U),
+   EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+   EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0xU),
+   EMIT_MASKWRITE(0xF8000168, 0x3F31U, 0x0501U),
+   EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+   EMIT_MASKWRITE(0xF80001C4, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+   EMIT_MASKWRITE(0xF8000304, 0x0001U, 0xU),
+   EMIT_MASKWRITE(0xF804, 0xU, 0x767BU),
+   EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF8006000, 0x0001U, 0x0080U),
+   EMIT_MASKWRITE(0xF8006004, 0x0007U, 0x1081U),
+   EMIT_MASKWRITE(0xF8006008, 0x03FFU, 0x03C0780FU),
+   EMIT_MASKWRITE(0xF800600C, 0x03FFU, 0x02001001U),
+   EMIT_MASKWRITE(0xF8006010, 0x03FFU, 0x00014001U),
+   EMIT_MASKWRITE(0xF8006014, 0x001FU, 0x0004159BU),
+   EMIT_MASKWRITE(0xF8006018, 0xF7FFU, 0x44E438D2U),
+   EMIT_MASKWRITE(0xF800601C, 0xU, 0x720238E5U),
+   EMIT_MASKWRITE(0xF8006020, 0x7FDCU, 0x27087290U),
+   EMIT_MASKWRITE(0xF8006024, 0x0FC3U, 0xU),
+   EMIT_MASKWRITE(0xF8006028, 0x3FFFU, 0x2007U),
+   EMIT_MASKWRITE(0xF800602C, 0xU, 0x0008U),
+   EMIT_MASKWRITE(0xF8006030, 0xU, 0x00040930U),
+   EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+   EMIT_MASKWRITE(0xF8006038, 0x0003U, 0xU),
+   EMIT_MASKWRITE(0xF800603C, 0x000FU, 0x0777U),
+   EMIT_MASKWRITE(0xF8006040, 0xU, 0xFFF0U),
+   EMIT_MASKWRITE(0xF8006044, 0x0FFFU, 0x0F66U),
+   EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+   EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+   EMIT_MASKWRITE(0xF8006058, 0x0001U, 0xU),
+   EMIT_MASKWRITE(0xF800605C, 0xU, 0x5003U),
+   EMIT_MASKWRITE(0xF8006060, 0x17FFU, 0x003EU),
+   EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x0002U),
+   EMIT_MASKWRITE(0xF8006068, 0x03FFU, 0x00284141U),
+   EMIT_MASKWRITE(0xF800606C, 0xU, 0x1610U),
+   EMIT_MASKWRITE(0xF8006078, 0x03FFU, 0x00466111U),
+   EMIT_MASKWRITE(0xF800607C, 0x000FU, 0x0003U),
+   EMIT_MASKWRITE(0xF80060A4, 0xU, 0x10200802U),
+   

[U-Boot] [PATCH 1/5] arm: zynq: Add zc770-xm010 spl configuration

[Michal Simek]

Simplify ps7_init* initialization.

Signed-off-by: Michal Simek 
---

 board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c | 800 ++
 1 file changed, 800 insertions(+)
 create mode 100644 board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c

diff --git a/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c 
b/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
new file mode 100644
index ..3dd3785e4939
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
@@ -0,0 +1,800 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0xF8000110, 0x0030U, 0x000FA220U),
+   EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+   EMIT_MASKWRITE(0xF8000100, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000100, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000100, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0001U),
+   EMIT_MASKWRITE(0xF8000100, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+   EMIT_MASKWRITE(0xF8000114, 0x0030U, 0x0012C220U),
+   EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x0002U),
+   EMIT_MASKWRITE(0xF8000104, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000104, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000104, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0002U),
+   EMIT_MASKWRITE(0xF8000104, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF8000124, 0xFFF3U, 0x0C23U),
+   EMIT_MASKWRITE(0xF8000118, 0x0030U, 0x001452C0U),
+   EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+   EMIT_MASKWRITE(0xF8000108, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0xF8000108, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000108, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0xF800010C, 0x0004U),
+   EMIT_MASKWRITE(0xF8000108, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0xF804, 0xU, 0x767BU),
+   EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+   EMIT_MASKWRITE(0xF8000138, 0x0011U, 0x0001U),
+   EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+   EMIT_MASKWRITE(0xF800014C, 0x3F31U, 0x0501U),
+   EMIT_MASKWRITE(0xF8000150, 0x3F33U, 0x1401U),
+   EMIT_MASKWRITE(0xF8000154, 0x3F33U, 0x1402U),
+   EMIT_MASKWRITE(0xF8000158, 0x3F33U, 0x0602U),
+   EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+   EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0xU),
+   EMIT_MASKWRITE(0xF8000168, 0x3F31U, 0x0401U),
+   EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+   EMIT_MASKWRITE(0xF80001C4, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01ED844DU),
+   EMIT_MASKWRITE(0xF804, 0xU, 0x767BU),
+   EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+   EMIT_MASKWRITE(0xF8006000, 0x0001U, 0x0080U),
+   EMIT_MASKWRITE(0xF8006004, 0x0007U, 0x1081U),
+   EMIT_MASKWRITE(0xF8006008, 0x03FFU, 0x03C0780FU),
+   EMIT_MASKWRITE(0xF800600C, 0x03FFU, 0x02001001U),
+   EMIT_MASKWRITE(0xF8006010, 0x03FFU, 0x00014001U),
+   EMIT_MASKWRITE(0xF8006014, 0x001FU, 0x0004159BU),
+   EMIT_MASKWRITE(0xF8006018, 0xF7FFU, 0x44E438D2U),
+   EMIT_MASKWRITE(0xF800601C, 0xU, 0x720238E5U),
+   EMIT_MASKWRITE(0xF8006020, 0x7FDCU, 0x27087290U),
+   EMIT_MASKWRITE(0xF8006024, 0x0FC3U, 0xU),
+   EMIT_MASKWRITE(0xF8006028, 0x3FFFU, 0x2007U),
+   EMIT_MASKWRITE(0xF800602C, 0xU, 0x0008U),
+   EMIT_MASKWRITE(0xF8006030, 0xU, 0x00040930U),
+   EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+   EMIT_MASKWRITE(0xF8006038, 0x0003U, 0xU),
+   EMIT_MASKWRITE(0xF800603C, 0x000FU, 0x0777U),
+   EMIT_MASKWRITE(0xF8006040, 0xU, 0xFFF0U),
+   EMIT_MASKWRITE(0xF8006044, 0x0FFFU, 0x0F66U),
+   EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+   EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+   EMIT_MASKWRITE(0xF8006058, 0x0001U, 0xU),
+   EMIT_MASKWRITE(0xF800605C, 0xU, 0x5003U),
+   EMIT_MASKWRITE(0xF8006060, 0x17FFU, 0x003EU),
+   EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x0002U),
+   EMIT_MASKWRITE(0xF8006068, 0x03FFU, 0x00284141U),
+   EMIT_MASKWRITE(0xF800606C, 0xU, 0x1610U),
+   EMIT_MASKWRITE(0xF8006078, 0x03FFU, 0x00466111U),
+   

Re: [U-Boot] api: bootelf: go: flush cache before starting

[Emmanuel Vadot]

On Tue, 9 Jan 2018 15:59:23 -0500
Tom Rini  wrote:

> On Mon, Dec 04, 2017 at 07:33:45PM +0100, Emmanuel Vadot wrote:
> 
> > From: Warner Losh 
> > 
> > Some application might load some code at location that contain stale
> > cache entries. Before running a elf or raw binary, flush the caches
> > if they are enabled.
> > 
> > Reviewed-by: Tom Rini 
> > Signed-off-by: Emmanuel Vadot 
> > ---
> >  api/api.c  | 5 +
> >  cmd/boot.c | 4 
> >  cmd/elf.c  | 5 +
> >  3 files changed, 14 insertions(+)
> > 
> > diff --git a/api/api.c b/api/api.c
> > index 7eee2fc083..853a3f7b0a 100644
> > --- a/api/api.c
> > +++ b/api/api.c
> > @@ -290,6 +290,11 @@ static int API_dev_close(va_list ap)
> > if (!err)
> > di->state = DEV_STA_CLOSED;
> >  
> > +   if (dcache_status())
> > +   flush_dcache_all();
> > +   if (icache_status())
> > +   invalidate_icache_all();
> > +
> > return err;
> >  }
> >  
> > diff --git a/cmd/boot.c b/cmd/boot.c
> > index 72f2cf362d..b66ae67fcb 100644
> > --- a/cmd/boot.c
> > +++ b/cmd/boot.c
> > @@ -19,6 +19,10 @@ __attribute__((weak))
> >  unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
> >  char * const argv[])
> >  {
> > +   if (dcache_status())
> > +   flush_dcache_all();
> > +   if (icache_status())
> > +   invalidate_icache_all();
> > return entry (argc, argv);
> >  }
> >  
> > diff --git a/cmd/elf.c b/cmd/elf.c
> > index 5745a389da..5126c0e57d 100644
> > --- a/cmd/elf.c
> > +++ b/cmd/elf.c
> > @@ -109,6 +109,11 @@ static unsigned long do_bootelf_exec(ulong 
> > (*entry)(int, char * const[]),
> >  {
> > unsigned long ret;
> >  
> > +   if (dcache_status())
> > +   flush_dcache_all();
> > +   if (icache_status())
> > +   invalidate_icache_all();
> > +
> > /*
> >  * pass address parameter as argv[0] (aka command name),
> >  * and all remaining args
> 
> We do not have these flushes on all architectures, so as is travis-ci
> would fail, as does 'make tests'.  Thanks!

 Yes sorry,

 I have a v2 lying around for quite some time now, I'll send it soon.

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Re: [U-Boot] [PATCH 1/2] ARM: imx: cm_fx6: export board and soc info to env

[Stefano Babic]

On 09/01/2018 22:01, christopher.spinr...@rwth-aachen.de wrote:
> From: Christopher Spinrath 
> 
> Like many other i.MX6 based boards, there are multiple variants of
> the cm-fx6 module featuring different SoC variants. Furthermore, the
> module can be paired with multiple baseboards.
> 
> At the same time modern distribution like Fedora require U-Boot to
> select a proper devicetree which depends on the SoC variant and the
> baseboard.
> 
> Thus, export the SoC variant and the actual board to the environment
> following the conventions of other i.MX6 devices (e.g. the NXP boards)
> such that the environment can select a devicetree file to load.
> 
> For now, we only know for sure that the cm-fx6 module and the SB-fx6m
> baseboard amount to a Utilite Computer variant (depending on the SoC).
> Further combinations may be added in the future; e.g. CompuLab's
> evaluation board once someone can verify the identification string
> stored in its eeprom.
> 
> Signed-off-by: Christopher Spinrath 
> ---
>  arch/arm/mach-imx/mx6/Kconfig  |  1 +
>  board/compulab/cm_fx6/cm_fx6.c | 21 +
>  include/configs/cm_fx6.h   |  1 +
>  3 files changed, 23 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
> index 567a6a6bf5..057fca31ea 100644
> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -130,6 +130,7 @@ config TARGET_CM_FX6
>   bool "CM-FX6"
>   select SUPPORT_SPL
>   select MX6QDL
> + select BOARD_LATE_INIT
>   select DM
>   select DM_SERIAL
>   select DM_GPIO
> diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
> index 620c3f2d0d..673de03071 100644
> --- a/board/compulab/cm_fx6/cm_fx6.c
> +++ b/board/compulab/cm_fx6/cm_fx6.c
> @@ -621,6 +621,27 @@ int board_init(void)
>   return 0;
>  }
>  
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> + char baseboard_name[16];
> + int err;
> +
> + if (is_mx6dq())
> + env_set("board_rev", "MX6Q");
> + else if (is_mx6dl())
> + env_set("board_rev", "MX6DL");
> +
> + err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
> + if (err)
> + return 0;
> +
> + if (!strncmp("SB-FX6m", baseboard_name, 7))
> + env_set("board_name", "Utilite");
> +#endif
> + return 0;
> +}
> +
>  int checkboard(void)
>  {
>   puts("Board: CM-FX6\n");
> diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
> index ec3e6e6ca5..cb71ea8811 100644
> --- a/include/configs/cm_fx6.h
> +++ b/include/configs/cm_fx6.h
> @@ -67,6 +67,7 @@
>  #define CONFIG_ENV_OFFSET(768 * 1024)
>  
>  #ifndef CONFIG_SPL_BUILD
> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
>  #define CONFIG_EXTRA_ENV_SETTINGS \
>   "fdt_high=0x\0" \
>   "initrd_high=0x\0" \
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 2/3] mx6memcal: spl: Also take i.MX6ULL into account

[Stefano Babic]

On 03/01/2018 15:55, Fabio Estevam wrote:
> i.MX6ULL also does not support 64-bit DDR bus, so add it to the
> check logic.
> 
> Signed-off-by: Fabio Estevam 
> ---
>  board/freescale/mx6memcal/spl.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/board/freescale/mx6memcal/spl.c b/board/freescale/mx6memcal/spl.c
> index 8ee89ff..e8b992c 100644
> --- a/board/freescale/mx6memcal/spl.c
> +++ b/board/freescale/mx6memcal/spl.c
> @@ -419,6 +419,7 @@ void board_init_f(ulong dummy)
>   if (sysinfo.dsize != 1) {
>   if (is_cpu_type(MXC_CPU_MX6SX) ||
>   is_cpu_type(MXC_CPU_MX6UL) ||
> + is_cpu_type(MXC_CPU_MX6ULL) ||
>   is_cpu_type(MXC_CPU_MX6SL)) {
>   printf("cpu type 0x%x doesn't support 64-bit bus\n",
>  get_cpu_type());
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] [PATCH] drivers: pci: imx: fix enumeration logic error

[Stefano Babic]

On 04/01/2018 14:54, Koen Vandeputte wrote:
> By default, the subordinate is set equally to the secondary bus (1) when
> the RC boots, and does not alter afterwards.
> 
> This means that theoretically, the highest bus reachable downstream is
> bus 1.
> 
> Force the PCIe RC subordinate to 0xff, otherwise no downstream
> devices will be detected behind bus 1 if the booting OS does not allow
> enumerating a higher busnr than the subordinate value of the primary
> bus.
> 
> Signed-off-by: Koen Vandeputte 
> ---
>  drivers/pci/pcie_imx.c | 11 +++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
> index 2900c8d..9277af9 100644
> --- a/drivers/pci/pcie_imx.c
> +++ b/drivers/pci/pcie_imx.c
> @@ -612,6 +612,17 @@ static int imx_pcie_link_up(void)
>   imx_pcie_regions_setup();
>  
>   /*
> +  * By default, the subordinate is set equally to the secondary
> +  * bus (0x01) when the RC boots.
> +  * This means that theoretically, only bus 1 is reachable from the RC.
> +  * Force the PCIe RC subordinate to 0xff, otherwise no downstream
> +  * devices will be detected if the enumeration is applied strictly.
> +  */
> + tmp = readl(MX6_DBI_ADDR + 0x18);
> + tmp |= (0xff << 16);
> + writel(tmp, MX6_DBI_ADDR + 0x18);
> +
> + /*
>* FIXME: Force the PCIe RC to Gen1 operation
>* The RC must be forced into Gen1 mode before bringing the link
>* up, otherwise no downstream devices are detected. After the
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 3/3] mx6memcal: spl: Disambiguate the error message

[Stefano Babic]

On 03/01/2018 15:55, Fabio Estevam wrote:
> Currently mmdc_do_dqs_calibration() and mmdc_do_write_level_calibration()
> show the same error message, which is confusing for debugging.
> 
> Disambiguate the mmdc_do_dqs_calibration() error message.
> 
> Signed-off-by: Fabio Estevam 
> ---
>  board/freescale/mx6memcal/spl.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/board/freescale/mx6memcal/spl.c b/board/freescale/mx6memcal/spl.c
> index e8b992c..027da4f 100644
> --- a/board/freescale/mx6memcal/spl.c
> +++ b/board/freescale/mx6memcal/spl.c
> @@ -446,7 +446,7 @@ void board_init_f(ulong dummy)
>   } else {
>   errs = mmdc_do_dqs_calibration();
>   if (errs) {
> - printf("error %d from write level calibration\n", errs);
> + printf("error %d from dqs calibration\n", errs);
>   } else {
>   printf("completed successfully\n");
>   mmdc_read_calibration(, );
> 
Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH 2/2] ARM: imx: cm_fx6: env: try to determine dtb to use

[Stefano Babic]

On 09/01/2018 22:01, christopher.spinr...@rwth-aachen.de wrote:
> From: Christopher Spinrath 
> 
> Some distributions like Fedora expect U-Boot to select a proper
> devicetree. Since there are several variants of the cm-fx6 module
> featuring different SoC variants and the module can be paired with
> several baseboards, it is not viable to hardcode a filename.
> 
> Instead, follow the lead of other i.MX6 based devices and try to
> determine the devicetree to use with the help of the board name
> and the SoC variant exported by the board code, before calling the
> distro bootcommand.
> 
> For now, only for the Utilite Pro a proper devicetree filename is
> known but further variants of the Utilite Computer or other devices
> based on the cm-fx6 module may be added in the future.
> 
> Signed-off-by: Christopher Spinrath 
> ---
>  configs/cm_fx6_defconfig | 2 +-
>  include/configs/cm_fx6.h | 6 ++
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
> index 33e610ccb4..6b1c0a823c 100644
> --- a/configs/cm_fx6_defconfig
> +++ b/configs/cm_fx6_defconfig
> @@ -16,7 +16,7 @@ CONFIG_DISTRO_DEFAULTS=y
>  CONFIG_OF_BOARD_SETUP=y
>  CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
>  CONFIG_BOOTDELAY=3
> -CONFIG_BOOTCOMMAND="run distro_bootcmd; run legacy_bootcmd"
> +CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd"
>  CONFIG_SPL=y
>  CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
>  CONFIG_SPL_I2C_SUPPORT=y
> diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
> index cb71ea8811..da870b9baa 100644
> --- a/include/configs/cm_fx6.h
> +++ b/include/configs/cm_fx6.h
> @@ -76,6 +76,7 @@
>   "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
>   "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
>   "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
> + "fdtfile=undefined\0" \
>   "stdin=serial,usbkbd\0" \
>   "stdout=serial,vga\0" \
>   "stderr=serial,vga\0" \
> @@ -153,6 +154,11 @@
>   "fi;" \
>   "run setupnandboot;" \
>   "run nandboot;\0" \
> + "findfdt="\
> + "if test $board_name = Utilite && test $board_rev = MX6Q ; then 
> " \
> + "setenv fdtfile imx6q-utilite-pro.dtb; fi; " \
> + "if test $fdtfile = undefined; then " \
> + "echo WARNING: Could not determine dtb to use; fi; \0" \
>   BOOTENV
>  
>  #define CONFIG_PREBOOT   "usb start;sf probe"
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH] misc: mxc_ocotp: check fuse word before programming on i.MX7ULP

[Stefano Babic]

On 02/01/2018 08:51, Peng Fan wrote:
> On i.MX7ULP, the fuse words (except bank 0 and 1) only supports to
> write once, because they use ECC mode. Multiple writes may damage
> the ECC value and cause a wrong fuse value decoded when reading.
> This patch adds a checking before the fuse word programming, only
> can write when the word value is 0.
> 
> Signed-off-by: Ye Li 
> Signed-off-by: Peng Fan 
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH] imx: ventana: Rework CONFIG_CMD_EECONFIG code to not be included in SPL

[Stefano Babic]

On 03/01/2018 15:15, Tom Rini wrote:
> The command can only be used from full U-Boot, so do not build it into
> SPL.
> 
> Cc: Stefano Babic 
> Cc: Fabio Estevam 
> Cc: Tim Harvey 
> Signed-off-by: Tom Rini 
> ---
>  board/gateworks/gw_ventana/eeprom.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/board/gateworks/gw_ventana/eeprom.c 
> b/board/gateworks/gw_ventana/eeprom.c
> index 2c07a84fffcb..a435dd9fb7b7 100644
> --- a/board/gateworks/gw_ventana/eeprom.c
> +++ b/board/gateworks/gw_ventana/eeprom.c
> @@ -119,7 +119,7 @@ struct ventana_eeprom_config econfig[] = {
>   { /* Sentinel */ }
>  };
>  
> -#ifdef CONFIG_CMD_EECONFIG
> +#if defined(CONFIG_CMD_EECONFIG) && !defined(CONFIG_SPL_BUILD)
>  static struct ventana_eeprom_config *get_config(const char *name)
>  {
>   struct ventana_eeprom_config *cfg = econfig;
> @@ -135,7 +135,7 @@ static struct ventana_eeprom_config *get_config(const 
> char *name)
>  static u8 econfig_bytes[sizeof(ventana_info.config)];
>  static int econfig_init = -1;
>  
> -int do_econfig(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +static int do_econfig(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
> argv[])
>  {
>   struct ventana_eeprom_config *cfg;
>   struct ventana_board_info *info = _info;
> 
Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH 1/3] mx6memcal: Fix the UART ports for mx6sabresd/auto boards

[Stefano Babic]

On 03/01/2018 15:55, Fabio Estevam wrote:
> mx6sabresd board uses the following pins for console:
> 
> PAD_CSI0_DAT10__UART1_TX_DATA
> PAD_CSI0_DAT11__UART1_RX_DATA
> 
> ,so put it in the same config option as wandboard.
> 
> mx6sabreauto board uses the following pins for console:
> 
> PAD_KEY_COL0__UART4_TX_DATA
> PAD_KEY_ROW0__UART4_RX_DATA
> 
> So do not mention sabreauto board as part of the UART1_SD3_DAT6_7 option.
> 
> The config option for sabreauto can be added later when needed.
> 
> Signed-off-by: Fabio Estevam 
> ---
>  board/freescale/mx6memcal/Kconfig | 12 ++--
>  1 file changed, 2 insertions(+), 10 deletions(-)
> 
> diff --git a/board/freescale/mx6memcal/Kconfig 
> b/board/freescale/mx6memcal/Kconfig
> index 443804d..9987cba 100644
> --- a/board/freescale/mx6memcal/Kconfig
> +++ b/board/freescale/mx6memcal/Kconfig
> @@ -45,20 +45,12 @@ choice
> NXP SABRELite.
>  
>   config UART1_CSI0_DAT10_11
> - bool "UART1 on CSI0_DAT10/11 (Wand)"
> + bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)"
>   depends on SERIAL_CONSOLE_UART1
>   help
> Choose this configuration if you're using pads
> CSI0_DAT10 and DAT11 for a console on UART1 as
> -   is done on the i.MX6 Wand board.
> -
> - config UART1_SD3_DAT6_7
> - bool "UART1 on SD3_DAT6/7 (SabreSD, SabreAuto)"
> - depends on SERIAL_CONSOLE_UART1
> - help
> -   Choose this configuration if you're using pads
> -   SD3_DAT6 and DAT7 for a console on UART1 as is
> -   done on the NXP SABRESD or SABREAUTO designs.
> +   is done on the i.MX6 Wand board and i.MX6 SabreSD.
>  
>   config UART1_UART1
>   bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"
> 
Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH] imx: ventana: Rework CONFIG_CMD_GSC code to not be included in SPL

[Stefano Babic]

On 03/01/2018 15:16, Tom Rini wrote:
> The command can only be used from full U-Boot, so do not build it into
> SPL.
> 
> Cc: Stefano Babic 
> Cc: Fabio Estevam 
> Cc: Tim Harvey 
> Signed-off-by: Tom Rini 
> ---
>  board/gateworks/gw_ventana/gsc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/board/gateworks/gw_ventana/gsc.c 
> b/board/gateworks/gw_ventana/gsc.c
> index 68b1ddb532e0..f2a01b84deb2 100644
> --- a/board/gateworks/gw_ventana/gsc.c
> +++ b/board/gateworks/gw_ventana/gsc.c
> @@ -172,7 +172,7 @@ int gsc_boot_wd_disable(void)
>   return 1;
>  }
>  
> -#ifdef CONFIG_CMD_GSC
> +#if defined(CONFIG_CMD_GSC) && !defined(CONFIG_SPL_BUILD)
>  static int do_gsc_sleep(cmd_tbl_t *cmdtp, int flag, int argc,
>   char * const argv[])
>  {
> 
Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH] toradex: imx6: Rework PF0100 fuse programming commands to not be in SPL

[Stefano Babic]

On 03/01/2018 15:19, Tom Rini wrote:
> The code for programming the OTP fuses on the PMIC PF0100 can only be
> used in full U-Boot, so do not build / link it into SPL.
> 
> Cc: Max Krummenacher 
> Cc: Stefano Babic 
> Cc: Fabio Estevam 
> Signed-off-by: Tom Rini 
> ---
>  board/toradex/apalis_imx6/pf0100.c  | 9 ++---
>  board/toradex/apalis_imx6/pf0100.h  | 3 ---
>  board/toradex/colibri_imx6/pf0100.c | 8 +---
>  board/toradex/colibri_imx6/pf0100.h | 3 ---
>  4 files changed, 11 insertions(+), 12 deletions(-)
> 
> diff --git a/board/toradex/apalis_imx6/pf0100.c 
> b/board/toradex/apalis_imx6/pf0100.c
> index 5eaf9c0b1785..013801e62bae 100644
> --- a/board/toradex/apalis_imx6/pf0100.c
> +++ b/board/toradex/apalis_imx6/pf0100.c
> @@ -10,6 +10,7 @@
>  
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -23,7 +24,7 @@
>  /*#define DEBUG */
>  
>  /* use Apalis GPIO1 to switch on VPGM, ON: 1 */
> -static iomux_v3_cfg_t const pmic_prog_pads[] = {
> +static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
>   MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
>  #define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 4)
>  };
> @@ -161,7 +162,8 @@ unsigned pmic_init(void)
>   return programmed;
>  }
>  
> -int pf0100_prog(void)
> +#ifndef CONFIG_SPL_BUILD
> +static int pf0100_prog(void)
>  {
>   unsigned char bus = 1;
>   unsigned char val;
> @@ -208,7 +210,7 @@ int pf0100_prog(void)
>   return CMD_RET_SUCCESS;
>  }
>  
> -int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
> +static int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
>   char * const argv[])
>  {
>   int ret;
> @@ -226,3 +228,4 @@ U_BOOT_CMD(
>   "Program the OTP fuses on the PMIC PF0100",
>   ""
>  );
> +#endif
> diff --git a/board/toradex/apalis_imx6/pf0100.h 
> b/board/toradex/apalis_imx6/pf0100.h
> index c84cab8b158c..af1e88fbc9dd 100644
> --- a/board/toradex/apalis_imx6/pf0100.h
> +++ b/board/toradex/apalis_imx6/pf0100.h
> @@ -50,7 +50,4 @@
>  /* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
>  unsigned pmic_init(void);
>  
> -/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */
> -int pf0100_prog(void);
> -
>  #endif /* PF0100_H_ */
> diff --git a/board/toradex/colibri_imx6/pf0100.c 
> b/board/toradex/colibri_imx6/pf0100.c
> index 688928776068..62e64ab1d760 100644
> --- a/board/toradex/colibri_imx6/pf0100.c
> +++ b/board/toradex/colibri_imx6/pf0100.c
> @@ -23,7 +23,7 @@
>  /*#define DEBUG */
>  
>  /* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */
> -static iomux_v3_cfg_t const pmic_prog_pads[] = {
> +static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
>   MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
>  #define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3)
>  };
> @@ -144,7 +144,8 @@ unsigned pmic_init(void)
>   return programmed;
>  }
>  
> -int pf0100_prog(void)
> +#ifndef CONFIG_SPL_BUILD
> +static int pf0100_prog(void)
>  {
>   unsigned char bus = 1;
>   unsigned char val;
> @@ -191,7 +192,7 @@ int pf0100_prog(void)
>   return CMD_RET_SUCCESS;
>  }
>  
> -int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
> +static int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
>   char * const argv[])
>  {
>   int ret;
> @@ -209,3 +210,4 @@ U_BOOT_CMD(
>   "Program the OTP fuses on the PMIC PF0100",
>   ""
>  );
> +#endif
> diff --git a/board/toradex/colibri_imx6/pf0100.h 
> b/board/toradex/colibri_imx6/pf0100.h
> index c84cab8b158c..af1e88fbc9dd 100644
> --- a/board/toradex/colibri_imx6/pf0100.h
> +++ b/board/toradex/colibri_imx6/pf0100.h
> @@ -50,7 +50,4 @@
>  /* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
>  unsigned pmic_init(void);
>  
> -/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */
> -int pf0100_prog(void);
> -
>  #endif /* PF0100_H_ */
> 
Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH] arm: imx: Rework i.MX specific commands to be excluded from SPL

[Stefano Babic]

On 03/01/2018 14:52, Tom Rini wrote:
> The "clocks" and "bootaux" commands are only usable in full U-Boot, not
> SPL, so do not link them inside of SPL.  Rework a little of the bootaux
> related code to make use of __weak and declare parts of it static as
> it's local to the file.
> 
> Cc: Stefano Babic 
> Cc: Fabio Estevam 
> Signed-off-by: Tom Rini 
> ---
>  arch/arm/mach-imx/Makefile   |  2 ++
>  arch/arm/mach-imx/imx_bootaux.c  | 13 -
>  arch/arm/mach-imx/mx5/clock.c|  4 +++-
>  arch/arm/mach-imx/mx7/clock.c|  2 ++
>  arch/arm/mach-imx/mx7ulp/clock.c |  2 ++
>  5 files changed, 13 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index d77c10e17684..783b2c8602ba 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -28,7 +28,9 @@ obj-y   += cache.o init.o
>  obj-$(CONFIG_SATA) += sata.o
>  obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
>  obj-$(CONFIG_IMX_RDC) += rdc-sema.o
> +ifneq ($(CONFIG_SPL_BUILD),y)
>  obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
> +endif
>  obj-$(CONFIG_SECURE_BOOT)+= hab.o
>  endif
>  ifeq ($(SOC),$(filter $(SOC),mx7ulp))
> diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
> index 69026df7630f..b62dfbf6bf6c 100644
> --- a/arch/arm/mach-imx/imx_bootaux.c
> +++ b/arch/arm/mach-imx/imx_bootaux.c
> @@ -6,27 +6,22 @@
>  
>  #include 
>  #include 
> +#include 
>  
>  /* Allow for arch specific config before we boot */
> -static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
> +int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
>  {
>   /* please define platform specific arch_auxiliary_core_up() */
>   return CMD_RET_FAILURE;
>  }
>  
> -int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
> - __attribute__((weak, alias("__arch_auxiliary_core_up")));
> -
>  /* Allow for arch specific config before we boot */
> -static int __arch_auxiliary_core_check_up(u32 core_id)
> +int __weak arch_auxiliary_core_check_up(u32 core_id)
>  {
>   /* please define platform specific arch_auxiliary_core_check_up() */
>   return 0;
>  }
>  
> -int arch_auxiliary_core_check_up(u32 core_id)
> - __attribute__((weak, alias("__arch_auxiliary_core_check_up")));
> -
>  /*
>   * To i.MX6SX and i.MX7D, the image supported by bootaux needs
>   * the reset vector at the head for the image, with SP and PC
> @@ -40,7 +35,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
>   * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
>   * accessing the M4 TCMUL.
>   */
> -int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
> argv[])
>  {
>   ulong addr;
>   int ret, up;
> diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c
> index 610098c175e9..284f6d4cde3d 100644
> --- a/arch/arm/mach-imx/mx5/clock.c
> +++ b/arch/arm/mach-imx/mx5/clock.c
> @@ -911,10 +911,11 @@ void mxc_set_sata_internal_clock(void)
>  }
>  #endif
>  
> +#ifndef CONFIG_SPL_BUILD
>  /*
>   * Dump some core clockes.
>   */
> -int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
> argv[])
> +static int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * 
> const argv[])
>  {
>   u32 freq;
>  
> @@ -947,3 +948,4 @@ U_BOOT_CMD(
>   "display clocks",
>   ""
>  );
> +#endif
> diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
> index 8150faa1a313..c11042d6f5ed 100644
> --- a/arch/arm/mach-imx/mx7/clock.c
> +++ b/arch/arm/mach-imx/mx7/clock.c
> @@ -1096,6 +1096,7 @@ void epdc_clock_disable(void)
>  }
>  #endif
>  
> +#ifndef CONFIG_SPL_BUILD
>  /*
>   * Dump some core clockes.
>   */
> @@ -1131,3 +1132,4 @@ U_BOOT_CMD(
>   "display clocks",
>   ""
>  );
> +#endif
> diff --git a/arch/arm/mach-imx/mx7ulp/clock.c 
> b/arch/arm/mach-imx/mx7ulp/clock.c
> index 77b282addd6e..553d62149de6 100644
> --- a/arch/arm/mach-imx/mx7ulp/clock.c
> +++ b/arch/arm/mach-imx/mx7ulp/clock.c
> @@ -323,6 +323,7 @@ void hab_caam_clock_enable(unsigned char enable)
>  }
>  #endif
>  
> +#ifndef CONFIG_SPL_BUILD
>  /*
>   * Dump some core clockes.
>   */
> @@ -363,3 +364,4 @@ U_BOOT_CMD(
>   "display clocks",
>   ""
>  );
> +#endif
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH V2 2/2] imx: mx6ull-14x14-evk: enable DM QSPI driver

[Stefano Babic]

On 03/01/2018 01:52, Peng Fan wrote:
> To support QSPI DM driver
>  - Add spi0 alias for qspi node. Which is used for bus number 0.
>  - Modify the n25q256a@0 compatible property to "spi-flash".
>  - Modify spi4 (gpio_spi) node to spi5
>  - Define DM SPI/QSPI related config to enable QSPI
> 
> Signed-off-by: Peng Fan 
> ---
> 
> V2:
>  None
> 
>  arch/arm/dts/imx6ull-14x14-evk.dts|  5 +++--
>  arch/arm/dts/imx6ull.dtsi |  9 +
>  configs/mx6ull_14x14_evk_defconfig|  6 ++
>  configs/mx6ull_14x14_evk_plugin_defconfig |  6 ++
>  include/configs/mx6ullevk.h   | 10 ++
>  5 files changed, 30 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts 
> b/arch/arm/dts/imx6ull-14x14-evk.dts
> index 375bd4e..2a941bf 100644
> --- a/arch/arm/dts/imx6ull-14x14-evk.dts
> +++ b/arch/arm/dts/imx6ull-14x14-evk.dts
> @@ -67,7 +67,7 @@
>   };
>   };
>  
> - spi4 {
> + spi5 {
>   compatible = "spi-gpio";
>   pinctrl-names = "default";
>   pinctrl-0 = <_spi4>;
> @@ -455,7 +455,8 @@
>   flash0: n25q256a@0 {
>   #address-cells = <1>;
>   #size-cells = <1>;
> - compatible = "micron,n25q256a";
> + /* compatible = "micron,n25q256a"; */
> + compatible = "spi-flash";
>   spi-max-frequency = <2900>;
>   spi-nor,ddr-quad-read-dummy = <6>;
>   reg = <0>;
> diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi
> index 65950e8..ea882a7 100644
> --- a/arch/arm/dts/imx6ull.dtsi
> +++ b/arch/arm/dts/imx6ull.dtsi
> @@ -38,10 +38,11 @@
>   serial5 = 
>   serial6 = 
>   serial7 = 
> - spi0 = 
> - spi1 = 
> - spi2 = 
> - spi3 = 
> + spi0 = 
> + spi1 = 
> + spi2 = 
> + spi3 = 
> + spi4 = 
>   usbphy0 = 
>   usbphy1 = 
>   };
> diff --git a/configs/mx6ull_14x14_evk_defconfig 
> b/configs/mx6ull_14x14_evk_defconfig
> index 4960056..5305c12 100644
> --- a/configs/mx6ull_14x14_evk_defconfig
> +++ b/configs/mx6ull_14x14_evk_defconfig
> @@ -10,6 +10,7 @@ CONFIG_CMD_MEMTEST=y
>  CONFIG_CMD_GPIO=y
>  CONFIG_CMD_I2C=y
>  CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
>  CONFIG_CMD_DHCP=y
>  CONFIG_CMD_PING=y
>  CONFIG_CMD_CACHE=y
> @@ -24,7 +25,12 @@ CONFIG_DM_GPIO=y
>  CONFIG_DM_74X164=y
>  CONFIG_DM_I2C=y
>  CONFIG_DM_MMC=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_STMICRO=y
>  CONFIG_PINCTRL=y
>  CONFIG_PINCTRL_IMX6=y
>  CONFIG_DM_REGULATOR=y
>  CONFIG_DM_SPI=y
> +CONFIG_FSL_QSPI=y
> diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig 
> b/configs/mx6ull_14x14_evk_plugin_defconfig
> index d07be22..f1023b2 100644
> --- a/configs/mx6ull_14x14_evk_plugin_defconfig
> +++ b/configs/mx6ull_14x14_evk_plugin_defconfig
> @@ -11,6 +11,7 @@ CONFIG_CMD_MEMTEST=y
>  CONFIG_CMD_GPIO=y
>  CONFIG_CMD_I2C=y
>  CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
>  CONFIG_CMD_DHCP=y
>  CONFIG_CMD_PING=y
>  CONFIG_CMD_CACHE=y
> @@ -25,7 +26,12 @@ CONFIG_DM_GPIO=y
>  CONFIG_DM_74X164=y
>  CONFIG_DM_I2C=y
>  CONFIG_DM_MMC=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_STMICRO=y
>  CONFIG_PINCTRL=y
>  CONFIG_PINCTRL_IMX6=y
>  CONFIG_DM_REGULATOR=y
>  CONFIG_DM_SPI=y
> +CONFIG_FSL_QSPI=y
> diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
> index 8787df4..6a48742 100644
> --- a/include/configs/mx6ullevk.h
> +++ b/include/configs/mx6ullevk.h
> @@ -164,4 +164,14 @@
>  
>  #define CONFIG_SOFT_SPI
>  
> +#ifdef CONFIG_FSL_QSPI
> +#define CONFIG_SYS_FSL_QSPI_AHB
> +#define CONFIG_SF_DEFAULT_BUS0
> +#define CONFIG_SF_DEFAULT_CS 0
> +#define CONFIG_SF_DEFAULT_SPEED  4000
> +#define CONFIG_SF_DEFAULT_MODE   SPI_MODE_0
> +#define FSL_QSPI_FLASH_NUM   1
> +#define FSL_QSPI_FLASH_SIZE  SZ_32M
> +#endif
> +
>  #endif
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH V2 1/2] spi: fsl_qspi: support i.MX6UL/6ULLL/7D

[Stefano Babic]

On 03/01/2018 01:52, Peng Fan wrote:
> The QSPI module on i.MX7D is modified from i.MX6SX. The module used on
> i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size.
> 
> The endianness is not set at qspi driver initialization. So if we don't
> boot from QSPI, we will get wrong endianness when accessing from AHB
> address directly.
> 
> Add the compatible entry for 6ul/7d.
> 
> Signed-off-by: Peng Fan 
> ---
> 
> V2:
>  Add CONFIG_MX6ULL
> 
>  drivers/spi/fsl_qspi.c | 18 --
>  1 file changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
> index 0f3f7d9..2f5345f 100644
> --- a/drivers/spi/fsl_qspi.c
> +++ b/drivers/spi/fsl_qspi.c
> @@ -20,7 +20,8 @@
>  DECLARE_GLOBAL_DATA_PTR;
>  
>  #define RX_BUFFER_SIZE   0x80
> -#ifdef CONFIG_MX6SX
> +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
> + defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
>  #define TX_BUFFER_SIZE   0x200
>  #else
>  #define TX_BUFFER_SIZE   0x40
> @@ -268,7 +269,8 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
>INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
>PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
>  #endif
> -#ifdef CONFIG_MX6SX
> +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
> + defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
>   /*
>* To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
>* So, Use IDATSZ in IPCR to determine the size and here set 0.
> @@ -905,6 +907,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, 
> unsigned int cs,
>   qspi->slave.max_write_size = TX_BUFFER_SIZE;
>  
>   mcr_val = qspi_read32(qspi->priv.flags, >mcr);
> +
> + /* Set endianness to LE for i.mx */
> + if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
> + mcr_val = QSPI_MCR_END_CFD_LE;
> +
>   qspi_write32(qspi->priv.flags, >mcr,
>QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
>(mcr_val & QSPI_MCR_END_CFD_MASK));
> @@ -1023,6 +1030,11 @@ static int fsl_qspi_probe(struct udevice *bus)
>   }
>  
>   mcr_val = qspi_read32(priv->flags, >regs->mcr);
> +
> + /* Set endianness to LE for i.mx */
> + if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
> + mcr_val = QSPI_MCR_END_CFD_LE;
> +
>   qspi_write32(priv->flags, >regs->mcr,
>QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
>(mcr_val & QSPI_MCR_END_CFD_MASK));
> @@ -1227,6 +1239,8 @@ static const struct dm_spi_ops fsl_qspi_ops = {
>  static const struct udevice_id fsl_qspi_ids[] = {
>   { .compatible = "fsl,vf610-qspi" },
>   { .compatible = "fsl,imx6sx-qspi" },
> + { .compatible = "fsl,imx6ul-qspi" },
> + { .compatible = "fsl,imx7d-qspi" },
>   { }
>  };
>  
> 
Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH] mx6: ddr: Do not access MMDC_P1_BASE_ADDR on i.MX6ULL

[Stefano Babic]

On 02/01/2018 01:51, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> i.MX6ULL also does not have a MMDC_P1_BASE_ADDR, so do not try to
> access it.
> 
> Signed-off-by: Fabio Estevam 
> ---
>  arch/arm/mach-imx/mx6/ddr.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
> index 52a9a25..39dbd2f 100644
> --- a/arch/arm/mach-imx/mx6/ddr.c
> +++ b/arch/arm/mach-imx/mx6/ddr.c
> @@ -908,7 +908,7 @@ void mx6sdl_dram_iocfg(unsigned width,
>  #define MR(val, ba, cmd, cs1) \
>   ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
>  #define MMDC1(entry, value) do {   \
> - if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())\
> + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())\
>   mmdc1->entry = value; \
>   } while (0)
>  
> @@ -1215,7 +1215,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
>   u16 mem_speed = ddr3_cfg->mem_speed;
>  
>   mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
> - if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
> + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
>   mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
>  
>   /* Limit mem_speed for MX6D/MX6Q */
> 
Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH 1/7] ARM: imx: Introduce dts for i.MX6SX-SDB

[Stefano Babic]

On 02/01/2018 02:32, Peng Fan wrote:
> Introduce dts from Kernel commit
> commit 71ee203389f7cb1c("Merge tag 'scsi-fixes' of
> git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi")
> 
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> Cc: Fabio Estevam 
> ---


Applied (series, patch 4/7 in V2) to u-boot-imx, thanks !

Best regards,
Stefano Babic



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[U-Boot] [PATCH] arm: zynq: Fix types in ps7_spl_init

[Michal Simek]

The patch is fixing the following Warning:
arch/arm/mach-zynq/ps7_spl_init.c:133:24: warning: comparison between
signed and unsigned integer expressions [-Wsign-compare]
while (ioread(addr) < delay)
^

Signed-off-by: Michal Simek 
---

 arch/arm/mach-zynq/ps7_spl_init.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-zynq/ps7_spl_init.c 
b/arch/arm/mach-zynq/ps7_spl_init.c
index 6dc4e0364d8b..ba2dad759ca8 100644
--- a/arch/arm/mach-zynq/ps7_spl_init.c
+++ b/arch/arm/mach-zynq/ps7_spl_init.c
@@ -58,7 +58,7 @@ static void perf_start_clock(void)
 }
 
 /* Compute mask for given delay in miliseconds*/
-static int get_number_of_cycles_for_delay(unsigned int delay)
+static unsigned long get_number_of_cycles_for_delay(unsigned long delay)
 {
return (APU_FREQ / (2 * 1000)) * delay;
 }
@@ -92,7 +92,7 @@ int __weak ps7_config(unsigned long *ps7_config_init)
unsigned long mask;
unsigned int numargs;
int i;
-   int delay;
+   unsigned long delay;
 
for (;;) {
opcode = ptr[0];
-- 
1.9.1

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[U-Boot] [PATCH V3] Convert CONFIG_SYS_DV_CLKMODE et al to Kconfig

[Adam Ford]

This converts the following to Kconfig:
   CONFIG_SYS_DV_CLKMODE
   CONFIG_SYS_DA850_PLL0_POSTDIV
   CONFIG_SYS_DA850_PLL0_PLLDIV1
   CONFIG_SYS_DA850_PLL0_PLLDIV2
   CONFIG_SYS_DA850_PLL0_PLLDIV3
   CONFIG_SYS_DA850_PLL0_PLLDIV4
   CONFIG_SYS_DA850_PLL0_PLLDIV5
   CONFIG_SYS_DA850_PLL0_PLLDIV7
   CONFIG_SYS_DA850_PLL1_POSTDIV
   CONFIG_SYS_DA850_PLL1_PLLDIV1
   CONFIG_SYS_DA850_PLL1_PLLDIV2
   CONFIG_SYS_DA850_PLL1_PLLDIV3

Signed-off-by: Adam Ford 
---
Changes in V3:
Using the L138 Technical Reference manual, I changed the names to match
  the descriptions of the registers as listed in Table 8-2 and 8-3 of 
the
  PLL Control 0 and PLL Control 1 Registers.
V2:
Expand Kconfig help definitions to give a small explanation of options
V1:
This patch is a continuation of Convert CONFIG_SOC_DA8XX et al
This also showed warnings when used with the legoev3_defconfig, however
it seems like the ev3 board was defining things in the header it didn't need
since it doesn't seem to be building da850_lowlevel.c.  I don't have the
hardware to test that board.

 arch/arm/mach-davinci/Kconfig   | 85 -
 configs/omapl138_lcdk_defconfig |  1 +
 include/configs/calimain.h  | 13 ---
 include/configs/da850evm.h  | 13 ---
 include/configs/ipam390.h   | 13 ---
 include/configs/legoev3.h   | 13 ---
 include/configs/omapl138_lcdk.h | 13 ---
 scripts/config_whitelist.txt| 12 --
 8 files changed, 85 insertions(+), 78 deletions(-)

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index ae9c0fd..72e208f 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -24,7 +24,7 @@ config TARGET_EA20
 
 config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
-   select SOC_DA8XX
+   select SOC_DA850
select SUPPORT_SPL
 
 config TARGET_CALIMAIN
@@ -63,6 +63,89 @@ config SOC_DA8XX
 config MACH_DAVINCI_DA850_EVM
bool
 
+if SYS_DA850_PLL_INIT
+comment "DA850 PLL Initialization Parameters"
+
+config SYS_DV_CLKMODE
+   int "PLLCTL Clock Mode"
+   default 0 if SOC_DA850
+   help
+ Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
+
+config SYS_DA850_PLL0_POSTDIV
+   int "PLLC0 PLL Post-Divider"
+   default 1 if SOC_DA850
+   help
+ Value written to PLLC0 PLL Post-Divider Control Register
+
+config SYS_DA850_PLL0_PLLDIV1
+   hex "PLLC0 Divider 1"
+   default 0x8000 if SOC_DA850
+   help
+ Value written to PLLC0 Divider 1 register
+
+config SYS_DA850_PLL0_PLLDIV2
+   hex "PLLC0 Divider 2"
+   default 0x8001 if SOC_DA850
+   help
+ Value written to PLLC0 Divider 2 register
+
+config SYS_DA850_PLL0_PLLDIV3
+   hex "PLLC0 Divider 3"
+   default 0x8002 if SOC_DA850
+   help
+ Value written to PLLC0 Divider 3 register
+
+config SYS_DA850_PLL0_PLLDIV4
+   hex "PLLC0 Divider 4"
+   default 0x8003 if SOC_DA850
+   help
+ Value written to PLLC0 Divider 4 register
+
+config SYS_DA850_PLL0_PLLDIV5
+   hex "PLLC0 Divider 5"
+   default 0x8002 if SOC_DA850
+   help
+ Value written to PLLC0 Divider 5 register
+
+config SYS_DA850_PLL0_PLLDIV7
+   hex "PLLC0 Divider 7"
+   default 0x8005 if SOC_DA850
+   help
+ Value written to PLLC0 Divider 7 register
+
+config SYS_DA850_PLL1_POSTDIV
+   hex "PLLC1 PLL Post-Divider"
+   default 1 if SOC_DA850
+   help
+ Value written to PLLC1 PLL Post-Divider Control Register
+
+config SYS_DA850_PLL1_PLLDIV1
+   hex "PLLC1 Divider 2"
+   default 0x8000 if SOC_DA850
+   help
+ Value written to PLLC1 Divider 1 register
+
+config SYS_DA850_PLL1_PLLDIV2
+   hex "PLLC1 Divider 2"
+   default 0x8001 if SOC_DA850
+   help
+ Value written to PLLC1 Divider 2 register
+
+config SYS_DA850_PLL1_PLLDIV3
+   hex "PLLC1 Divider 3"
+   default 0x8002 if SOC_DA850
+   help
+ Value written to PLLC1 Divider 3 register
+
+config SYS_DA850_PLL1_PLLM
+   int "PLLC1 PLL Multiplier"
+   default 21 if SOC_DA850
+   help
+ Value written to PLLC1 PLL Multiplier Control Register
+
+endif
+
 source "board/Barix/ipam390/Kconfig"
 source "board/davinci/da8xxevm/Kconfig"
 source "board/davinci/ea20/Kconfig"
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 8d6b12f..2498126 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_OMAPL138_LCDK=y
+CONFIG_SYS_DA850_PLL1_PLLDIV3=0x8003
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index 7dfc1fa..8605487 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -39,20 +39,7 @@
 /*
 

Re: [U-Boot] [PATCH v1 2/2] x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parameters

[Andy Shevchenko]

On Fri, 2018-01-12 at 17:00 +0800, Bin Meng wrote:
> Hi Andy,
> 
> On Thu, Jan 11, 2018 at 1:40 AM, Andy Shevchenko
>  wrote:
> > New field acpi_rsdp_addr, which has been introduced in boot protocol
> > v2.14 [1], in boot parameters tells kernel the exact address of RDSP
> > ACPI table. Knowing it increases robustness of the kernel by
> > avoiding
> > in some cases traversal through a part of physical memory.
> > It will slightly reduce boot time by the same reason.
> > 
> > [1] See Linux kernel commit
> > 
> >   2f74cbf947f4 ("x86/boot: Add the ACPI RSDP address to struct
> > setup_header::acpi_rdsp_addr")
> 
> I don't see this commit id in my linux tree. Is this in some
> custodian's tree?

https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=2
f74cbf947f45fa082dda8eac1a1f1299a372f49

> > for the details.
> > 
> > Signed-off-by: Andy Shevchenko 
> > ---
> >  arch/x86/include/asm/bootparam.h |  1 +
> >  arch/x86/lib/acpi_table.c|  7 +++
> >  arch/x86/lib/acpi_table.h| 10 ++
> >  arch/x86/lib/zimage.c|  6 ++
> >  4 files changed, 24 insertions(+)
> >  create mode 100644 arch/x86/lib/acpi_table.h
> > 
> > diff --git a/arch/x86/include/asm/bootparam.h
> > b/arch/x86/include/asm/bootparam.h
> > index 48b138c6b0..90768a99ce 100644
> > --- a/arch/x86/include/asm/bootparam.h
> > +++ b/arch/x86/include/asm/bootparam.h
> > @@ -66,6 +66,7 @@ struct setup_header {
> > __u64   pref_address;
> > __u32   init_size;
> > __u32   handover_offset;
> > +   __u64   acpi_rsdp_addr;
> >  } __attribute__((packed));
> > 
> >  struct sys_desc_table {
> > diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
> > index 7b33cd371e..45bfc111ef 100644
> > --- a/arch/x86/lib/acpi_table.c
> > +++ b/arch/x86/lib/acpi_table.c
> > @@ -20,6 +20,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include "acpi_table.h"
> > 
> >  /*
> >   * IASL compiles the dsdt entries and writes the hex values
> > @@ -27,6 +28,11 @@
> >   */
> >  extern const unsigned char AmlCode[];
> > 
> > +/*
> > + * ACPI RSDP address to be used in boot parameters.
> > + */
> 
> nits: use single line comment format without the ending .

OK.

> 
> > +unsigned long acpi_rsdp_addr;
> > +
> >  static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct
> > acpi_rsdt *rsdt,
> > struct acpi_xsdt *xsdt)
> >  {
> > @@ -460,6 +466,7 @@ ulong write_acpi_tables(ulong start)
> > 
> > debug("current = %x\n", current);
> > 
> > +   acpi_rsdp_addr = (unsigned long)rsdp;
> > debug("ACPI: done\n");
> > 
> > /* Don't touch ACPI hardware on HW reduced platforms */
> > diff --git a/arch/x86/lib/acpi_table.h b/arch/x86/lib/acpi_table.h
> > new file mode 100644
> > index 00..cece5d1420
> > --- /dev/null
> > +++ b/arch/x86/lib/acpi_table.h
> > @@ -0,0 +1,10 @@
> > +/*
> > + * SPDX-License-Identifier:GPL-2.0
> > + */
> > +
> > +#ifndef _X86_LIB_ACPI_TABLES_H
> > +#define _X86_LIB_ACPI_TABLES_H
> > +
> > +extern unsigned long acpi_rsdp_addr;
> > +
> > +#endif
> > diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
> > index d224db4e07..eae26635b1 100644
> > --- a/arch/x86/lib/zimage.c
> > +++ b/arch/x86/lib/zimage.c
> > @@ -24,6 +24,7 @@
> >  #include 
> >  #endif
> >  #include 
> > +#include "acpi_table.h"
> > 
> >  DECLARE_GLOBAL_DATA_PTR;
> > 
> > @@ -255,6 +256,11 @@ int setup_zimage(struct boot_params
> > *setup_base, char *cmd_line, int auto_boot,
> > hdr->hardware_subarch = X86_SUBARCH_INTEL_MID;
> >  #endif
> > 
> > +#ifdef CONFIG_GENERATE_ACPI_TABLE
> > +   if (bootproto >= 0x020e)
> > +   hdr->acpi_rsdp_addr = acpi_rsdp_addr;
> > +#endif
> > +
> > setup_video(_base->screen_info);
> > 
> > return 0;
> > --
> 
> Other than the above nits,
> Reviewed-by: Bin Meng 
> 
> I can fix the nits when applying if you like.

If you have a chance to do it soon, please, do, otherwise I would send a
new version later (next week I suppose).

Thanks!

> 
> Regards,
> Bin

-- 
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Re: [U-Boot] [PATCH 1/2] ARM: imx: cm_fx6: export board and soc info to env

[Stefano Babic]

On 09/01/2018 22:51, Fabio Estevam wrote:
> Hi Christopher,
> 
> On Tue, Jan 9, 2018 at 7:01 PM,   wrote:
>> From: Christopher Spinrath 
>>
>> Like many other i.MX6 based boards, there are multiple variants of
>> the cm-fx6 module featuring different SoC variants. Furthermore, the
>> module can be paired with multiple baseboards.
>>
>> At the same time modern distribution like Fedora require U-Boot to
>> select a proper devicetree which depends on the SoC variant and the
>> baseboard.
>>
>> Thus, export the SoC variant and the actual board to the environment
>> following the conventions of other i.MX6 devices (e.g. the NXP boards)
>> such that the environment can select a devicetree file to load.
>>
>> For now, we only know for sure that the cm-fx6 module and the SB-fx6m
>> baseboard amount to a Utilite Computer variant (depending on the SoC).
>> Further combinations may be added in the future; e.g. CompuLab's
>> evaluation board once someone can verify the identification string
>> stored in its eeprom.
>>
>> Signed-off-by: Christopher Spinrath 
> 
> Patches look good.

Agree.

Reviewed-by: Stefano Babic 

> 
> Maybe you could combine both into a single one?
> 

Both have a good explanation uin the commit message. I will merge them
as they are.

Best regards,
Stefano


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[U-Boot] [PATCH v6 24/25] arm: imx: hab: Implement hab_rvt_failsafe

[Bryan O'Donoghue]

This patch implements the basic callback hooks for
hab_rvt_check_failsafe for BootROM code using the older BootROM address
layout - in my test case the i.MX7. Code based on new BootROM callbacks
will just do nothing and there's definitely a TODO to implement that extra
functionality on the alternative BootROM API.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index d1c5f69..1236717 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -70,6 +70,21 @@
((hab_rvt_exit_t *)HAB_RVT_EXIT)\
 )
 
+static inline void hab_rvt_failsafe_new(void)
+{
+}
+
+#define hab_rvt_failsafe_p \
+(  \
+   (is_mx6dqp()) ? \
+   ((hab_rvt_failsafe_t *)hab_rvt_failsafe_new) :  \
+   (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?   \
+   ((hab_rvt_failsafe_t *)hab_rvt_failsafe_new) :  \
+   (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?  \
+   ((hab_rvt_failsafe_t *)hab_rvt_failsafe_new) :  \
+   ((hab_rvt_failsafe_t *)HAB_RVT_FAILSAFE)\
+)
+
 static inline enum hab_status hab_rvt_check_target_new(enum hab_target target,
   const void *start,
   size_t bytes)
-- 
2.7.4

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[U-Boot] [PATCH v6 23/25] arm: imx: hab: Define rvt_failsafe()

[Bryan O'Donoghue]

The hab_rvt_failsafe() callback according to the HABv4 documentation:

"This function provides a safe path when image authentication has failed
and all possible boot paths have been exhausted. It is intended for use by
post-ROM boot stage components, via the ROM Vector Table."

Once invoked the part will drop down to its BootROM USB recovery mode.
Should it be the case that the part is in secure boot mode - only an
appropriately signed binary will be accepted by the ROM and subsequently
executed.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/include/asm/mach-imx/hab.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/mach-imx/hab.h 
b/arch/arm/include/asm/mach-imx/hab.h
index 5c13aff..a0cb19d 100644
--- a/arch/arm/include/asm/mach-imx/hab.h
+++ b/arch/arm/include/asm/mach-imx/hab.h
@@ -140,6 +140,7 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, 
ptrdiff_t,
void **, size_t *, hab_loader_callback_f_t);
 typedef enum hab_status hab_rvt_check_target_t(enum hab_target, const void *,
   size_t);
+typedef void hab_rvt_failsafe_t(void);
 typedef void hapi_clock_init_t(void);
 
 #define HAB_ENG_ANY0x00   /* Select first compatible engine */
@@ -170,6 +171,7 @@ typedef void hapi_clock_init_t(void);
 #define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
 #define HAB_RVT_REPORT_EVENT   (*(uint32_t *)(HAB_RVT_BASE + 0x20))
 #define HAB_RVT_REPORT_STATUS  (*(uint32_t *)(HAB_RVT_BASE + 0x24))
+#define HAB_RVT_FAILSAFE   (*(uint32_t *)(HAB_RVT_BASE + 0x28))
 
 #define HAB_RVT_REPORT_EVENT_NEW   (*(uint32_t *)0x00B8)
 #define HAB_RVT_REPORT_STATUS_NEW  (*(uint32_t *)0x00BC)
-- 
2.7.4

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[U-Boot] [PATCH v6 19/25] arm: imx: hab: Prefix authenticate_image with imx_hab

[Bryan O'Donoghue]

Tidy up the HAB namespace a bit by prefixing external functions with
imx_hab. All external facing functions past this point will be prefixed in
the same way to make the fact we are doing IMX HAB activities clear from
reading the code. authenticate_image() could mean anything
imx_hab_authenticate_image() is on the other hand very explicit.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/include/asm/mach-imx/hab.h | 4 ++--
 arch/arm/mach-imx/hab.c | 6 +++---
 arch/arm/mach-imx/spl.c | 5 +++--
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/hab.h 
b/arch/arm/include/asm/mach-imx/hab.h
index 14e1220..98bc1bd 100644
--- a/arch/arm/include/asm/mach-imx/hab.h
+++ b/arch/arm/include/asm/mach-imx/hab.h
@@ -185,7 +185,7 @@ typedef void hapi_clock_init_t(void);
 
 /* --- end of HAB API updates */
 
-int authenticate_image(uint32_t ddr_start, uint32_t image_size,
-  uint32_t ivt_offset);
+int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
+  uint32_t ivt_offset);
 
 #endif
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index ec85548..7c2f828 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -392,7 +392,7 @@ static int do_authenticate_image(cmd_tbl_t *cmdtp, int 
flag, int argc,
length = simple_strtoul(argv[2], NULL, 16);
ivt_offset = simple_strtoul(argv[3], NULL, 16);
 
-   rcode = authenticate_image(addr, length, ivt_offset);
+   rcode = imx_hab_authenticate_image(addr, length, ivt_offset);
if (rcode == 0)
rcode = CMD_RET_SUCCESS;
else
@@ -435,8 +435,8 @@ static bool is_hab_enabled(void)
return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
 }
 
-int authenticate_image(uint32_t ddr_start, uint32_t image_size,
-  uint32_t ivt_offset)
+int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
+  uint32_t ivt_offset)
 {
uint32_t load_addr = 0;
size_t bytes;
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index e5d0c35..a5478ce 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -196,8 +196,9 @@ __weak void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
/* HAB looks for the CSF at the end of the authenticated data therefore,
 * we need to subtract the size of the CSF from the actual filesize */
offset = spl_image->size - CONFIG_CSF_SIZE;
-   if (!authenticate_image(spl_image->load_addr,
-   offset + IVT_SIZE + CSF_PAD_SIZE, offset)) {
+   if (!imx_hab_authenticate_image(spl_image->load_addr,
+   offset + IVT_SIZE + CSF_PAD_SIZE,
+   offset)) {
image_entry();
} else {
puts("spl: ERROR:  image authentication unsuccessful\n");
-- 
2.7.4

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[U-Boot] [PATCH v6 15/25] arm: imx: hab: Implement hab_rvt_check_target

[Bryan O'Donoghue]

This patch implements the basic callback hooks for hab_rvt_check_target()
for BootROM code using the older BootROM address layout - in my test case
the i.MX7. Code based on new BootROM callbacks will just have HAB_SUCCESS
as a result code. Adding support for the new BootROM callbacks is a TODO.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 364bd6b..2a18ea2 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -70,6 +70,24 @@
((hab_rvt_exit_t *)HAB_RVT_EXIT)\
 )
 
+static inline enum hab_status hab_rvt_check_target_new(enum hab_target target,
+  const void *start,
+  size_t bytes)
+{
+   return HAB_SUCCESS;
+}
+
+#define hab_rvt_check_target_p \
+(  \
+   (is_mx6dqp()) ? \
+   ((hab_rvt_check_target_t *)hab_rvt_check_target_new) :  \
+   (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?   \
+   ((hab_rvt_check_target_t *)hab_rvt_check_target_new) :  \
+   (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?  \
+   ((hab_rvt_check_target_t *)hab_rvt_check_target_new) :  \
+   ((hab_rvt_check_target_t *)HAB_RVT_CHECK_TARGET)\
+)
+
 #define ALIGN_SIZE 0x1000
 #define MX6DQ_PU_IROM_MMU_EN_VAR   0x009024a8
 #define MX6DLS_PU_IROM_MMU_EN_VAR  0x00901dd0
-- 
2.7.4

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[U-Boot] [PATCH v6 06/25] arm: imx: hab: Move CSF_PAD_SIZE to hab.h

[Bryan O'Donoghue]

CSF_PAD_SIZE should be defined in hab.h, move it to that location now.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/include/asm/mach-imx/hab.h | 1 +
 arch/arm/mach-imx/hab.c | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/mach-imx/hab.h 
b/arch/arm/include/asm/mach-imx/hab.h
index 3c19d2e..91dda42 100644
--- a/arch/arm/include/asm/mach-imx/hab.h
+++ b/arch/arm/include/asm/mach-imx/hab.h
@@ -144,6 +144,7 @@ typedef void hapi_clock_init_t(void);
 #define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
 
 #define IVT_SIZE   0x20
+#define CSF_PAD_SIZE   0x2000
 
 /* --- end of HAB API updates */
 
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 6367562..039a017 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -71,7 +71,6 @@
 )
 
 #define ALIGN_SIZE 0x1000
-#define CSF_PAD_SIZE   0x2000
 #define MX6DQ_PU_IROM_MMU_EN_VAR   0x009024a8
 #define MX6DLS_PU_IROM_MMU_EN_VAR  0x00901dd0
 #define MX6SL_PU_IROM_MMU_EN_VAR   0x00900a18
-- 
2.7.4

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[U-Boot] [PATCH v6 13/25] arm: imx: hab: Print additional IVT elements during debug

[Bryan O'Donoghue]

This patch enables printout of the IVT entry, dcd and csf data fields.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 229c723..364bd6b 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -462,6 +462,8 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
 
 #ifdef DEBUG
printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr);
+   printf("ivt entry = 0x%08x, dcd = 0x%08x, csf = 0x%08x\n", ivt->entry,
+  ivt->dcd, ivt->csf);
puts("Dumping IVT\n");
print_buffer(ivt_addr, (void *)(ivt_addr), 4, 0x8, 0);
 
-- 
2.7.4

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[U-Boot] [PATCH v6 09/25] arm: imx: hab: Add IVT header verification

[Bryan O'Donoghue]

The IVT header contains a magic number, fixed length and one of two version
identifiers. Validate these settings before doing anything with a putative
IVT binary.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 36 ++--
 1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 2a40d06..998d253 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -80,6 +80,31 @@
 
 static bool is_hab_enabled(void);
 
+static int ivt_header_error(const char *err_str, struct ivt_header *ivt_hdr)
+{
+   printf("%s magic=0x%x length=0x%02x version=0x%x\n", err_str,
+  ivt_hdr->magic, ivt_hdr->length, ivt_hdr->version);
+
+   return 1;
+}
+
+static int verify_ivt_header(struct ivt_header *ivt_hdr)
+{
+   int result = 0;
+
+   if (ivt_hdr->magic != IVT_HEADER_MAGIC)
+   result = ivt_header_error("bad magic", ivt_hdr);
+
+   if (be16_to_cpu(ivt_hdr->length) != IVT_TOTAL_LENGTH)
+   result = ivt_header_error("bad length", ivt_hdr);
+
+   if (ivt_hdr->version != IVT_HEADER_V1 &&
+   ivt_hdr->version != IVT_HEADER_V2)
+   result = ivt_header_error("bad version", ivt_hdr);
+
+   return result;
+}
+
 #if !defined(CONFIG_SPL_BUILD)
 
 #define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
@@ -394,6 +419,8 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
hab_rvt_entry_t *hab_rvt_entry;
hab_rvt_exit_t *hab_rvt_exit;
+   struct ivt *ivt;
+   struct ivt_header *ivt_hdr;
 
hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
hab_rvt_entry = hab_rvt_entry_p;
@@ -416,6 +443,13 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
 
/* Calculate IVT address header */
ivt_addr = ddr_start + ivt_offset;
+   ivt = (struct ivt *)ivt_addr;
+   ivt_hdr = >hdr;
+
+   /* Verify IVT header bugging out on error */
+   if (verify_ivt_header(ivt_hdr))
+   goto hab_caam_clock_disable;
+
start = ddr_start;
bytes = image_size;
 #ifdef DEBUG
@@ -435,8 +469,6 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
printf("\tivt_offset = 0x%x\n", ivt_offset);
printf("\tstart = 0x%08lx\n", start);
printf("\tbytes = 0x%x\n", bytes);
-#else
-   (void)ivt_addr;
 #endif
/*
 * If the MMU is enabled, we have to notify the ROM
-- 
2.7.4

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[U-Boot] [PATCH v6 11/25] arm: imx: hab: Only call ROM once headers are verified

[Bryan O'Donoghue]

Previous patches added IVT header verification steps. We shouldn't call
hab_rvt_entry() until we have done the basic header verification steps.

This patch changes the time we make the hab_rvt_entry() call so that it
only takes place if we are happy with the IVT header sanity checks.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 39f8f2d..a8e3e79 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -436,11 +436,6 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
 
hab_caam_clock_enable(1);
 
-   if (hab_rvt_entry() != HAB_SUCCESS) {
-   puts("hab entry function fail\n");
-   goto hab_caam_clock_disable;
-   }
-
/* Calculate IVT address header */
ivt_addr = ddr_start + ivt_offset;
ivt = (struct ivt *)ivt_addr;
@@ -459,6 +454,12 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
 
start = ddr_start;
bytes = image_size;
+
+   if (hab_rvt_entry() != HAB_SUCCESS) {
+   puts("hab entry function fail\n");
+   goto hab_caam_clock_disable;
+   }
+
 #ifdef DEBUG
printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr);
puts("Dumping IVT\n");
-- 
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[U-Boot] [PATCH v6 20/25] arm: imx: hab: Rename is_hab_enabled imx_hab_is_enabled

[Bryan O'Donoghue]

Understanding if the HAB is enabled is something that we want to
interrogate and report on outside of the HAB layer. First step to that is
renaming the relevant function to match the previously introduced external
naming convention imx_hab_function()

The name imx_hab_is_hab_enabled() is a tautology. A more logical name is
imx_hab_is_enabled().

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 7c2f828..d917ac3 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -96,7 +96,7 @@ static inline enum hab_status hab_rvt_check_target_new(enum 
hab_target target,
(is_soc_type(MXC_SOC_MX7ULP) ? 0x8000 : \
 (is_soc_type(MXC_SOC_MX7) ? 0x200 : 0x2))
 
-static bool is_hab_enabled(void);
+static bool imx_hab_is_enabled(void);
 
 static int ivt_header_error(const char *err_str, struct ivt_header *ivt_hdr)
 {
@@ -334,7 +334,7 @@ static int get_hab_status(void)
hab_rvt_report_event = hab_rvt_report_event_p;
hab_rvt_report_status = hab_rvt_report_status_p;
 
-   if (is_hab_enabled())
+   if (imx_hab_is_enabled())
puts("\nSecure boot enabled\n");
else
puts("\nSecure boot disabled\n");
@@ -419,7 +419,7 @@ U_BOOT_CMD(
 
 #endif /* !defined(CONFIG_SPL_BUILD) */
 
-static bool is_hab_enabled(void)
+static bool imx_hab_is_enabled(void)
 {
struct imx_sec_config_fuse_t *fuse =
(struct imx_sec_config_fuse_t *)_sec_config_fuse;
@@ -456,7 +456,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
hab_rvt_exit = hab_rvt_exit_p;
hab_rvt_check_target = hab_rvt_check_target_p;
 
-   if (!is_hab_enabled()) {
+   if (!imx_hab_is_enabled()) {
puts("hab fuse not enabled\n");
return result;
}
-- 
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[U-Boot] [PATCH v6 16/25] arm: imx: hab: Add a hab_rvt_check_target to image auth

[Bryan O'Donoghue]

Add a hab_rvt_check_target() step to authenticate_image() as a sanity
check for the target memory region authenticate_image() will run over,
prior to making the BootROM authentication callback itself.

This check is recommended by the HAB documentation so it makes sense to
adhere to the guidance and perform that check as directed.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 2a18ea2..079423a 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -437,12 +437,15 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
hab_rvt_entry_t *hab_rvt_entry;
hab_rvt_exit_t *hab_rvt_exit;
+   hab_rvt_check_target_t *hab_rvt_check_target;
struct ivt *ivt;
struct ivt_header *ivt_hdr;
+   enum hab_status status;
 
hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
hab_rvt_entry = hab_rvt_entry_p;
hab_rvt_exit = hab_rvt_exit_p;
+   hab_rvt_check_target = hab_rvt_check_target_p;
 
if (!is_hab_enabled()) {
puts("hab fuse not enabled\n");
@@ -478,6 +481,12 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
goto hab_caam_clock_disable;
}
 
+   status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)ddr_start, bytes);
+   if (status != HAB_SUCCESS) {
+   printf("HAB check target 0x%08x-0x%08x fail\n",
+  ddr_start, ddr_start + bytes);
+   goto hab_caam_clock_disable;
+   }
 #ifdef DEBUG
printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr);
printf("ivt entry = 0x%08x, dcd = 0x%08x, csf = 0x%08x\n", ivt->entry,
-- 
2.7.4

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[U-Boot] [PATCH v6 25/25] arm: imx: hab: Add hab_failsafe console command

[Bryan O'Donoghue]

hab_failsafe when called puts the part into BootROM recovery mode.
This will allow u-boot scripts to script the dropping down into recovery
mode.

=> hab_failsafe

Shows the i.MX7 appear as "hiddev0,hidraw5: USB HID v1.10 Device [Freescale
SemiConductor Inc  SP Blank ULT1] " in a Linux dmesg thus allowing download
of a new image via the BootROM USB download protocol routine.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 1236717..5f19777 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -414,6 +414,22 @@ static int do_authenticate_image(cmd_tbl_t *cmdtp, int 
flag, int argc,
return rcode;
 }
 
+static int do_hab_failsafe(cmd_tbl_t *cmdtp, int flag, int argc,
+  char * const argv[])
+{
+   hab_rvt_failsafe_t *hab_rvt_failsafe;
+
+   if (argc != 1) {
+   cmd_usage(cmdtp);
+   return 1;
+   }
+
+   hab_rvt_failsafe = hab_rvt_failsafe_p;
+   hab_rvt_failsafe();
+
+   return 0;
+}
+
 U_BOOT_CMD(
hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
"display HAB status",
@@ -429,6 +445,11 @@ U_BOOT_CMD(
"ivt_offset - hex offset of IVT in the image"
  );
 
+U_BOOT_CMD(
+   hab_failsafe, CONFIG_SYS_MAXARGS, 1, do_hab_failsafe,
+   "run BootROM failsafe routine",
+   ""
+ );
 
 #endif /* !defined(CONFIG_SPL_BUILD) */
 
-- 
2.7.4

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[U-Boot] [PATCH v6 22/25] arm: imx: hab: Make imx_hab_is_enabled global

[Bryan O'Donoghue]

It will be helpful to boot commands to know if the HAB is enabled. Export
imx_hab_is_enabled() now to facilitate further work with this data-point in
a secure-boot context.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/include/asm/mach-imx/hab.h | 1 +
 arch/arm/mach-imx/hab.c | 4 +---
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/hab.h 
b/arch/arm/include/asm/mach-imx/hab.h
index 98bc1bd..5c13aff 100644
--- a/arch/arm/include/asm/mach-imx/hab.h
+++ b/arch/arm/include/asm/mach-imx/hab.h
@@ -187,5 +187,6 @@ typedef void hapi_clock_init_t(void);
 
 int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
   uint32_t ivt_offset);
+bool imx_hab_is_enabled(void);
 
 #endif
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 3b19a7e..d1c5f69 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -96,8 +96,6 @@ static inline enum hab_status hab_rvt_check_target_new(enum 
hab_target target,
(is_soc_type(MXC_SOC_MX7ULP) ? 0x8000 : \
 (is_soc_type(MXC_SOC_MX7) ? 0x200 : 0x2))
 
-static bool imx_hab_is_enabled(void);
-
 static int ivt_header_error(const char *err_str, struct ivt_header *ivt_hdr)
 {
printf("%s magic=0x%x length=0x%02x version=0x%x\n", err_str,
@@ -419,7 +417,7 @@ U_BOOT_CMD(
 
 #endif /* !defined(CONFIG_SPL_BUILD) */
 
-static bool imx_hab_is_enabled(void)
+bool imx_hab_is_enabled(void)
 {
struct imx_sec_config_fuse_t *fuse =
(struct imx_sec_config_fuse_t *)_sec_config_fuse;
-- 
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[U-Boot] [PATCH v6 12/25] arm: imx: hab: Print CSF based on IVT descriptor

[Bryan O'Donoghue]

The IVT gives the absolute address of the CSF. There is no requirement for
the CSF to be located adjacent to the IVT so lets use the address provided
in the IVT header instead of the hard-coded fixed CSF offset currently in
place.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index a8e3e79..229c723 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -466,8 +466,7 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
print_buffer(ivt_addr, (void *)(ivt_addr), 4, 0x8, 0);
 
puts("Dumping CSF Header\n");
-   print_buffer(ivt_addr + IVT_SIZE, (void *)(ivt_addr + IVT_SIZE), 4,
-0x10, 0);
+   print_buffer(ivt->csf, (void *)(ivt->csf), 4, 0x10, 0);
 
 #if  !defined(CONFIG_SPL_BUILD)
get_hab_status();
-- 
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[U-Boot] [PATCH v6 21/25] arm: imx: hab: Make authenticate_image() return zero on open boards

[Bryan O'Donoghue]

The BootROM will not successfully process a HAB image passed by u-boot
unless the board has been set into locked mode. Some of the existing usages
of authenticate_image() expect and rely on unlocked boards doing the
following

1. Not calling into the BootROM authenticate_image() callback
2. Returning a pass status for authenticate_image() calls anyway

A previous patch removed the necessity to call into imx_hab_is_enabled()
twice. This patch ensures the reliance on authenticate_image() returning
zero is maintained.

Signed-off-by: Bryan O'Donoghue 
Suggested-by: Breno Matheus Lima 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
---
 arch/arm/mach-imx/hab.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index d917ac3..3b19a7e 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -458,7 +458,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
 
if (!imx_hab_is_enabled()) {
puts("hab fuse not enabled\n");
-   return result;
+   return 0;
}
 
printf("\nAuthenticate image from DDR location 0x%x...\n",
-- 
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[U-Boot] [PATCH v6 14/25] arm: imx: hab: Define rvt_check_target()

[Bryan O'Donoghue]

The hab_rvt_check_target() callback according to the HABv4 documentation:

"This function reports whether or not a given target region is allowed for
 either peripheral configuration or image loading in memory. It is intended
 for use by post-ROM boot stage components, via the ROM Vector Table, in
 order to avoid configuring security-sensitive peripherals, or loading
 images over sensitive memory regions or outside recognized memory devices
 in the address map."

It is a useful function to support as a precursor to calling into
authenticate_image() to validate the target memory region is good.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/include/asm/mach-imx/hab.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/include/asm/mach-imx/hab.h 
b/arch/arm/include/asm/mach-imx/hab.h
index 28cde38..14e1220 100644
--- a/arch/arm/include/asm/mach-imx/hab.h
+++ b/arch/arm/include/asm/mach-imx/hab.h
@@ -113,6 +113,12 @@ enum hab_context {
HAB_CTX_MAX
 };
 
+enum hab_target {
+   HAB_TGT_MEMORY  = 0x0f,
+   HAB_TGT_PERIPHERAL  = 0xf0,
+   HAB_TGT_ANY = 0x55,
+};
+
 struct imx_sec_config_fuse_t {
int bank;
int word;
@@ -132,6 +138,8 @@ typedef enum hab_status hab_rvt_entry_t(void);
 typedef enum hab_status hab_rvt_exit_t(void);
 typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
void **, size_t *, hab_loader_callback_f_t);
+typedef enum hab_status hab_rvt_check_target_t(enum hab_target, const void *,
+  size_t);
 typedef void hapi_clock_init_t(void);
 
 #define HAB_ENG_ANY0x00   /* Select first compatible engine */
@@ -158,6 +166,7 @@ typedef void hapi_clock_init_t(void);
 
 #define HAB_RVT_ENTRY  (*(uint32_t *)(HAB_RVT_BASE + 0x04))
 #define HAB_RVT_EXIT   (*(uint32_t *)(HAB_RVT_BASE + 0x08))
+#define HAB_RVT_CHECK_TARGET   (*(uint32_t *)(HAB_RVT_BASE + 0x0C))
 #define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
 #define HAB_RVT_REPORT_EVENT   (*(uint32_t *)(HAB_RVT_BASE + 0x20))
 #define HAB_RVT_REPORT_STATUS  (*(uint32_t *)(HAB_RVT_BASE + 0x24))
-- 
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[U-Boot] [PATCH v6 18/25] arm: imx: hab: Make internal functions and data static

[Bryan O'Donoghue]

There is no need to export these functions and data structures externally.
Make them all static now.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 159 +---
 1 file changed, 84 insertions(+), 75 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 3ae88a4..ec85548 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -135,73 +135,81 @@ struct record {
bool any_rec_flag;
 };
 
-char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
-  "RSN = HAB_ENG_FAIL (0x30)\n",
-  "RSN = HAB_INV_ADDRESS (0x22)\n",
-  "RSN = HAB_INV_ASSERTION (0x0C)\n",
-  "RSN = HAB_INV_CALL (0x28)\n",
-  "RSN = HAB_INV_CERTIFICATE (0x21)\n",
-  "RSN = HAB_INV_COMMAND (0x06)\n",
-  "RSN = HAB_INV_CSF (0x11)\n",
-  "RSN = HAB_INV_DCD (0x27)\n",
-  "RSN = HAB_INV_INDEX (0x0F)\n",
-  "RSN = HAB_INV_IVT (0x05)\n",
-  "RSN = HAB_INV_KEY (0x1D)\n",
-  "RSN = HAB_INV_RETURN (0x1E)\n",
-  "RSN = HAB_INV_SIGNATURE (0x18)\n",
-  "RSN = HAB_INV_SIZE (0x17)\n",
-  "RSN = HAB_MEM_FAIL (0x2E)\n",
-  "RSN = HAB_OVR_COUNT (0x2B)\n",
-  "RSN = HAB_OVR_STORAGE (0x2D)\n",
-  "RSN = HAB_UNS_ALGORITHM (0x12)\n",
-  "RSN = HAB_UNS_COMMAND (0x03)\n",
-  "RSN = HAB_UNS_ENGINE (0x0A)\n",
-  "RSN = HAB_UNS_ITEM (0x24)\n",
-  "RSN = HAB_UNS_KEY (0x1B)\n",
-  "RSN = HAB_UNS_PROTOCOL (0x14)\n",
-  "RSN = HAB_UNS_STATE (0x09)\n",
-  "RSN = INVALID\n",
-  NULL};
-
-char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
-  "STS = HAB_FAILURE (0x33)\n",
-  "STS = HAB_WARNING (0x69)\n",
-  "STS = INVALID\n",
-  NULL};
-
-char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
-  "ENG = HAB_ENG_SCC (0x03)\n",
-  "ENG = HAB_ENG_RTIC (0x05)\n",
-  "ENG = HAB_ENG_SAHARA (0x06)\n",
-  "ENG = HAB_ENG_CSU (0x0A)\n",
-  "ENG = HAB_ENG_SRTC (0x0C)\n",
-  "ENG = HAB_ENG_DCP (0x1B)\n",
-  "ENG = HAB_ENG_CAAM (0x1D)\n",
-  "ENG = HAB_ENG_SNVS (0x1E)\n",
-  "ENG = HAB_ENG_OCOTP (0x21)\n",
-  "ENG = HAB_ENG_DTCP (0x22)\n",
-  "ENG = HAB_ENG_ROM (0x36)\n",
-  "ENG = HAB_ENG_HDCP (0x24)\n",
-  "ENG = HAB_ENG_RTL (0x77)\n",
-  "ENG = HAB_ENG_SW (0xFF)\n",
-  "ENG = INVALID\n",
-  NULL};
-
-char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
-  "CTX = HAB_CTX_FAB (0xFF)\n",
-  "CTX = HAB_CTX_ENTRY (0xE1)\n",
-  "CTX = HAB_CTX_TARGET (0x33)\n",
-  "CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
-  "CTX = HAB_CTX_DCD (0xDD)\n",
-  "CTX = HAB_CTX_CSF (0xCF)\n",
-  "CTX = HAB_CTX_COMMAND (0xC0)\n",
-  "CTX = HAB_CTX_AUT_DAT (0xDB)\n",
-  "CTX = HAB_CTX_ASSERT (0xA0)\n",
-  "CTX = HAB_CTX_EXIT (0xEE)\n",
-  "CTX = INVALID\n",
-  NULL};
-
-uint8_t hab_statuses[5] = {
+static char *rsn_str[] = {
+ "RSN = HAB_RSN_ANY (0x00)\n",
+ 

[U-Boot] [PATCH v6 07/25] arm: imx: hab: Fix authenticate_image input parameters

[Bryan O'Donoghue]

u-boot command "hab_auth_img" tells a user that it takes

- addr - image hex address
- offset - hex offset of IVT in the image

but in fact the callback hab_auth_img makes to authenticate_image treats
the second 'offset' parameter as an image length.

Furthermore existing code requires the IVT header to be appended to the end
of the image which is not actually a requirement of HABv4.

This patch fixes this situation by

1: Adding a new parameter to hab_auth_img
   - addr   : image hex address
   - length : total length of the image
   - offset : offset of IVT from addr

2: Updates the existing call into authenticate_image() in
   arch/arm/mach-imx/spl.c:jump_to_image_no_args() to pass
   addr, length and IVT offset respectively.

This allows then hab_auth_img to actually operate the way it was specified
in the help text and should still allow existing code to work.

It has the added advantage that the IVT header doesn't have to be appended
to an image given to HAB - it can be prepended for example.

Note prepending the IVT is what u-boot will do when making an IVT for the
BootROM. It should be possible for u-boot properly authenticate images
made by mkimage via HAB.

This patch is the first step in making that happen subsequent patches will
focus on removing hard-coded offsets to the IVT, which again is not
mandated to live at the end of a .imx image.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/include/asm/mach-imx/hab.h |  3 +-
 arch/arm/mach-imx/hab.c | 73 +++--
 arch/arm/mach-imx/spl.c | 35 +-
 3 files changed, 57 insertions(+), 54 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/hab.h 
b/arch/arm/include/asm/mach-imx/hab.h
index 91dda42..b2a8031 100644
--- a/arch/arm/include/asm/mach-imx/hab.h
+++ b/arch/arm/include/asm/mach-imx/hab.h
@@ -148,6 +148,7 @@ typedef void hapi_clock_init_t(void);
 
 /* --- end of HAB API updates */
 
-int authenticate_image(uint32_t ddr_start, uint32_t image_size);
+int authenticate_image(uint32_t ddr_start, uint32_t image_size,
+  uint32_t ivt_offset);
 
 #endif
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 039a017..2a40d06 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -78,37 +78,6 @@
(is_soc_type(MXC_SOC_MX7ULP) ? 0x8000 : \
 (is_soc_type(MXC_SOC_MX7) ? 0x200 : 0x2))
 
-/*
- * ++  0x0 (DDR_UIMAGE_START) -
- * |   Header   |  |
- * ++  0x40|
- * ||  |
- * ||  |
- * ||  |
- * ||  |
- * | Image Data |  |
- * .|  |
- * .|   > Stuff to be authenticated +
- * .|  ||
- * ||  ||
- * ||  ||
- * ++  ||
- * ||  ||
- * | Fill Data  |  ||
- * ||  ||
- * ++ Align to ALIGN_SIZE  ||
- * |IVT |  ||
- * ++ + IVT_SIZE  - |
- * ||   |
- * |  CSF DATA  | <-+
- * ||
- * ++
- * ||
- * | Fill Data  |
- * ||
- * ++ + CSF_PAD_SIZE
- */
-
 static bool is_hab_enabled(void);
 
 #if !defined(CONFIG_SPL_BUILD)
@@ -361,20 +330,22 @@ int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
 {
-   ulong   addr, ivt_offset;
+   ulong   addr, length, ivt_offset;
int rcode = 0;
 
-   if (argc < 3)
+   if (argc < 4)
return CMD_RET_USAGE;
 
addr = simple_strtoul(argv[1], NULL, 16);
-   

[U-Boot] [PATCH v6 03/25] arm: imx: hab: Optimise flow of authenticate_image on is_enabled fail

[Bryan O'Donoghue]

There is no need to call is_enabled() twice in authenticate_image - it does
nothing but add an additional layer of indentation.

We can check for is_enabled() at the start of the function and return the
result code directly.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 138 
 1 file changed, 69 insertions(+), 69 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 9fe6d43..6f86c02 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -428,91 +428,91 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size)
hab_rvt_entry = hab_rvt_entry_p;
hab_rvt_exit = hab_rvt_exit_p;
 
-   if (is_hab_enabled()) {
-   printf("\nAuthenticate image from DDR location 0x%x...\n",
-  ddr_start);
+   if (!is_hab_enabled()) {
+   puts("hab fuse not enabled\n");
+   return result;
+   }
 
-   hab_caam_clock_enable(1);
+   printf("\nAuthenticate image from DDR location 0x%x...\n",
+  ddr_start);
 
-   if (hab_rvt_entry() == HAB_SUCCESS) {
-   /* If not already aligned, Align to ALIGN_SIZE */
-   ivt_offset = (image_size + ALIGN_SIZE - 1) &
-   ~(ALIGN_SIZE - 1);
+   hab_caam_clock_enable(1);
 
-   start = ddr_start;
-   bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
+   if (hab_rvt_entry() == HAB_SUCCESS) {
+   /* If not already aligned, Align to ALIGN_SIZE */
+   ivt_offset = (image_size + ALIGN_SIZE - 1) &
+   ~(ALIGN_SIZE - 1);
+
+   start = ddr_start;
+   bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
 #ifdef DEBUG
-   printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
-  ivt_offset, ddr_start + ivt_offset);
-   puts("Dumping IVT\n");
-   print_buffer(ddr_start + ivt_offset,
-(void *)(ddr_start + ivt_offset),
-4, 0x8, 0);
-
-   puts("Dumping CSF Header\n");
-   print_buffer(ddr_start + ivt_offset+IVT_SIZE,
-(void *)(ddr_start + ivt_offset+IVT_SIZE),
-4, 0x10, 0);
+   printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
+  ivt_offset, ddr_start + ivt_offset);
+   puts("Dumping IVT\n");
+   print_buffer(ddr_start + ivt_offset,
+(void *)(ddr_start + ivt_offset),
+4, 0x8, 0);
+
+   puts("Dumping CSF Header\n");
+   print_buffer(ddr_start + ivt_offset + IVT_SIZE,
+(void *)(ddr_start + ivt_offset + IVT_SIZE),
+4, 0x10, 0);
 
 #if  !defined(CONFIG_SPL_BUILD)
-   get_hab_status();
+   get_hab_status();
 #endif
 
-   puts("\nCalling authenticate_image in ROM\n");
-   printf("\tivt_offset = 0x%x\n", ivt_offset);
-   printf("\tstart = 0x%08lx\n", start);
-   printf("\tbytes = 0x%x\n", bytes);
+   puts("\nCalling authenticate_image in ROM\n");
+   printf("\tivt_offset = 0x%x\n", ivt_offset);
+   printf("\tstart = 0x%08lx\n", start);
+   printf("\tbytes = 0x%x\n", bytes);
 #endif
-   /*
-* If the MMU is enabled, we have to notify the ROM
-* code, or it won't flush the caches when needed.
-* This is done, by setting the "pu_irom_mmu_enabled"
-* word to 1. You can find its address by looking in
-* the ROM map. This is critical for
-* authenticate_image(). If MMU is enabled, without
-* setting this bit, authentication will fail and may
-* crash.
-*/
-   /* Check MMU enabled */
-   if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
-   if (is_mx6dq()) {
-   /*
-* This won't work on Rev 1.0.0 of
- 

[U-Boot] [PATCH v6 17/25] arm: imx: hab: Print HAB event log only after calling ROM

[Bryan O'Donoghue]

The current flow of authenticate_image() will print the HAB event log even
if we reject an element of the IVT header before ever calling into the ROM.
This can be confusing.

This patch changes the flow of the code so that the HAB event log is only
printed out if we have called into the ROM and received some sort of status
code.

Signed-off-by: Bryan O'Donoghue 
Suggested-by: Cc: Breno Matheus Lima 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 079423a..3ae88a4 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -478,14 +478,14 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
 
if (hab_rvt_entry() != HAB_SUCCESS) {
puts("hab entry function fail\n");
-   goto hab_caam_clock_disable;
+   goto hab_exit_failure_print_status;
}
 
status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)ddr_start, bytes);
if (status != HAB_SUCCESS) {
printf("HAB check target 0x%08x-0x%08x fail\n",
   ddr_start, ddr_start + bytes);
-   goto hab_caam_clock_disable;
+   goto hab_exit_failure_print_status;
}
 #ifdef DEBUG
printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr);
@@ -543,12 +543,14 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
load_addr = 0;
}
 
-hab_caam_clock_disable:
-   hab_caam_clock_enable(0);
-
+hab_exit_failure_print_status:
 #if !defined(CONFIG_SPL_BUILD)
get_hab_status();
 #endif
+
+hab_caam_clock_disable:
+   hab_caam_clock_enable(0);
+
if (load_addr != 0)
result = 0;
 
-- 
2.7.4

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[U-Boot] [PATCH v6 05/25] arm: imx: hab: Move IVT_SIZE to hab.h

[Bryan O'Donoghue]

The size of the IVT header should be defined in hab.h move it there now.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/include/asm/mach-imx/hab.h | 2 ++
 arch/arm/mach-imx/hab.c | 1 -
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/mach-imx/hab.h 
b/arch/arm/include/asm/mach-imx/hab.h
index 1b7a5e4..3c19d2e 100644
--- a/arch/arm/include/asm/mach-imx/hab.h
+++ b/arch/arm/include/asm/mach-imx/hab.h
@@ -143,6 +143,8 @@ typedef void hapi_clock_init_t(void);
 #define HAB_CID_ROM 0 /**< ROM Caller ID */
 #define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
 
+#define IVT_SIZE   0x20
+
 /* --- end of HAB API updates */
 
 int authenticate_image(uint32_t ddr_start, uint32_t image_size);
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index f878b7b..6367562 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -70,7 +70,6 @@
((hab_rvt_exit_t *)HAB_RVT_EXIT)\
 )
 
-#define IVT_SIZE   0x20
 #define ALIGN_SIZE 0x1000
 #define CSF_PAD_SIZE   0x2000
 #define MX6DQ_PU_IROM_MMU_EN_VAR   0x009024a8
-- 
2.7.4

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[U-Boot] [PATCH v6 10/25] arm: imx: hab: Verify IVT self matches calculated address

[Bryan O'Donoghue]

The IVT is a self-describing structure which contains a self field. The
self field is the absolute physical base address the IVT ought to be at in
memory. Use the IVT self field to validate the calculated ivt_addr bugging
out if the two values differ.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 998d253..39f8f2d 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -450,6 +450,13 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size,
if (verify_ivt_header(ivt_hdr))
goto hab_caam_clock_disable;
 
+   /* Verify IVT body */
+   if (ivt->self != ivt_addr) {
+   printf("ivt->self 0x%08x pointer is 0x%08x\n",
+  ivt->self, ivt_addr);
+   goto hab_caam_clock_disable;
+   }
+
start = ddr_start;
bytes = image_size;
 #ifdef DEBUG
-- 
2.7.4

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[U-Boot] [PATCH v6 08/25] arm: imx: hab: Add IVT header definitions

[Bryan O'Donoghue]

The various i.MX BootROMs containing the High Assurance Boot (HAB) block
rely on a data structure called the Image Vector Table (IVT) to describe to
the BootROM where to locate various data-structures used by HAB during
authentication.

This patch adds a definition of the IVT header for use in later patches,
where we will break the current incorrect dependence on fixed offsets in
favour of an IVT described parsing of incoming binaries.

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/include/asm/mach-imx/hab.h | 28 
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/include/asm/mach-imx/hab.h 
b/arch/arm/include/asm/mach-imx/hab.h
index b2a8031..28cde38 100644
--- a/arch/arm/include/asm/mach-imx/hab.h
+++ b/arch/arm/include/asm/mach-imx/hab.h
@@ -10,6 +10,34 @@
 
 #include 
 
+/*
+ * IVT header definitions
+ * Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors,
+ * Rev. 0, 03/2017
+ * Section : 6.7.1.1
+ */
+#define IVT_HEADER_MAGIC   0xD1
+#define IVT_TOTAL_LENGTH   0x20
+#define IVT_HEADER_V1  0x40
+#define IVT_HEADER_V2  0x41
+
+struct ivt_header {
+   uint8_t magic;
+   uint16_tlength;
+   uint8_t version;
+} __attribute__((packed));
+
+struct ivt {
+   struct ivt_header hdr;  /* IVT header above */
+   uint32_t entry; /* Absolute address of first instruction */
+   uint32_t reserved1; /* Reserved should be zero */
+   uint32_t dcd;   /* Absolute address of the image DCD */
+   uint32_t boot;  /* Absolute address of the boot data */
+   uint32_t self;  /* Absolute address of the IVT */
+   uint32_t csf;   /* Absolute address of the CSF */
+   uint32_t reserved2; /* Reserved should be zero */
+};
+
 /*  start of HAB API updates */
 /* The following are taken from HAB4 SIS */
 
-- 
2.7.4

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[U-Boot] [PATCH v6 02/25] arm: imx: hab: Fix authenticate_image result code

[Bryan O'Donoghue]

authenticate_image returns 1 for success and 0 for failure. That result
code is mapped directly to the result code for the command line function
hab_auth_img - which means when hab_auth_img succeeds it is returning
CMD_RET_FAILURE (1) instead of CMD_RET_SUCCESS (0).

This patch fixes this behaviour by making authenticate_image() return 0 for
success and 1 for failure. Both users of authenticate_image() as a result
have some minimal churn. The upshot is once done when hab_auth_img is
called from the command line we set $? in the standard way for scripting
functions to act on.

Fixes: 36c1ca4d46ef ("imx: Support i.MX6 High Assurance Boot
authentication")

Signed-off-by: Bryan O'Donoghue 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Albert Aribaud 
Cc: Sven Ebenfeld 
Cc: George McCollister 
Cc: Breno Matheus Lima 
Tested-by: Breno Lima 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/hab.c | 9 ++---
 arch/arm/mach-imx/spl.c | 4 ++--
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 09892a6..9fe6d43 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -373,7 +373,10 @@ static int do_authenticate_image(cmd_tbl_t *cmdtp, int 
flag, int argc,
ivt_offset = simple_strtoul(argv[2], NULL, 16);
 
rcode = authenticate_image(addr, ivt_offset);
-
+   if (rcode == 0)
+   rcode = CMD_RET_SUCCESS;
+   else
+   rcode = CMD_RET_FAILURE;
return rcode;
 }
 
@@ -415,7 +418,7 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size)
uint32_t load_addr = 0;
size_t bytes;
ptrdiff_t ivt_offset = 0;
-   int result = 0;
+   int result = 1;
ulong start;
hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
hab_rvt_entry_t *hab_rvt_entry;
@@ -510,7 +513,7 @@ int authenticate_image(uint32_t ddr_start, uint32_t 
image_size)
}
 
if ((!is_hab_enabled()) || (load_addr != 0))
-   result = 1;
+   result = 0;
 
return result;
 }
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index d0d1b73..6e930b3 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -163,8 +163,8 @@ __weak void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
 
/* HAB looks for the CSF at the end of the authenticated data therefore,
 * we need to subtract the size of the CSF from the actual filesize */
-   if (authenticate_image(spl_image->load_addr,
-  spl_image->size - CONFIG_CSF_SIZE)) {
+   if (!authenticate_image(spl_image->load_addr,
+   spl_image->size - CONFIG_CSF_SIZE)) {
image_entry();
} else {
puts("spl: ERROR:  image authentication unsuccessful\n");
-- 
2.7.4

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