Re: [U-Boot] boot a bios/uefi with x86_64, without grub
forget my last question 'cos i have found the solution by adding a Startup.nsh juste beside the efi boot app : echo -off if exist .\u-boot-payload.efi then goto FOUNDTOOL endif if exist fs0:\u-boot-payload.efi then fs0: goto FOUNDTOOL endif if exist fs1:\u-boot-payload.efi then fs1: goto FOUNDTOOL endif if exist fs2:\u-boot-payload.efi then fs2: goto FOUNDTOOL endif echo u-boot-payload.efi.efi not found! goto END :FOUNDTOOL u-boot-payload.efi if NOT %lasterror% == 0 then echo Running u-boot for the upboard : NOK goto END endif echo Running u-boot for the upboard : OK :END 2018-08-01 8:43 GMT+02:00 Thierry Gayet : > hi, > > Well, all i want it to launch my u-boot-efi (payload mode) directly by the > bios/uefi. > > For now, for my tests, i have used an usbkey that have a partition with a > "EFI FAT 12/16/32" type. Inside, i have copying my uboot app efi inside > this directory. > > This is the way i am using for creating an UEFI bootable usbkey :-) My > u-boot doesn't start automatically but it stop with the efi shell. Inside > this efi shell i can start the uboot efi manually from the cli and it work > fine. > > Now that i have an uboot that can start, i am trying how to start it > directly on boot. > > Maybe i need to change its name ? or something else like this ? > > You was talking about some issues for the payload version ; do you have > more detail about that ? > > BR > > Thierry > > 2018-08-01 2:57 GMT+02:00 Bin Meng : > >> On Wed, Aug 1, 2018 at 2:32 AM, Thierry Gayet >> wrote: >> > hi bin, >> > >> > Thanks for your reply. >> > >> > Yes, you are totaly right because my uboot efi app didn't start due to >> my >> > architecture x86_64. >> > >> > Then i have try with a uboot efi payload (x86_64) and it start from efi >> > shell. >> > >> > I have tested with an usbkey using an EFI vfat partition formated as a >> vfat. >> > After that i have copyied my several filles from uboot efi payload >> x86_64 >> > and it start manually, not automatically. I don't know how to let it >> start >> > automaticaly ? any idea ? >> > >> >> I don't quite understand what you were doing. Please include some details. >> >> > Do you know what kind of issue there is on the uboot efi payload >> version ? >> > >> > Thanks in advance of you're reply. >> > >> >> Regards, >> Bin >> > > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] spi: kirkwood: Get drvdata in .ofdata_to_platdata
On Thu, Mar 15, 2018 at 5:03 PM, Jagan Teki wrote: > Get the is_errata_50mhz_ac in .ofdata_to_platdata, and > reuse it in .set_mode this can eventually initialized > dt code at once and adding room to add platdata. > > Signed-off-by: Jagan Teki > --- Applied to u-boot-spi/master ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: kirkwood: add orion-spi compatible string
On Tue, May 8, 2018 at 10:47 AM, Jagan Teki wrote:
> On Tue, May 8, 2018 at 4:24 AM, Chris Packham wrote:
>> This matches the compatible string used by the Linux kernel. This will
>> allow u-boot to use the same device tree files.
>>
>> Signed-off-by: Chris Packham
>> ---
>> This applies on top of Jagan's series
>> http://patchwork.ozlabs.org/project/uboot/list/?series=33927
>>
>> drivers/spi/kirkwood_spi.c | 8
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
>> index 036fc36b8329..6a5ab8a1cba4 100644
>> --- a/drivers/spi/kirkwood_spi.c
>> +++ b/drivers/spi/kirkwood_spi.c
>> @@ -226,6 +226,10 @@ static int mvebu_spi_ofdata_to_platdata(struct udevice
>> *bus)
>> return 0;
>> }
>>
>> +static const struct mvebu_spi_dev orion_spi_dev_data = {
>> + .is_errata_50mhz_ac = false,
>> +};
>> +
>> static const struct mvebu_spi_dev armada_xp_spi_dev_data = {
>> .is_errata_50mhz_ac = false,
>> };
>> @@ -239,6 +243,10 @@ static const struct mvebu_spi_dev
>> armada_380_spi_dev_data = {
>> };
>>
>> static const struct udevice_id mvebu_spi_ids[] = {
>> + {
>> + .compatible = "marvell,orion-spi",
>> + .data = (ulong)&orion_spi_dev_data
>
> Reviewed-by: Jagan Teki
Applied to u-boot-spi/master
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Re: [U-Boot] boot a bios/uefi with x86_64, without grub
hi, Well, all i want it to launch my u-boot-efi (payload mode) directly by the bios/uefi. For now, for my tests, i have used an usbkey that have a partition with a "EFI FAT 12/16/32" type. Inside, i have copying my uboot app efi inside this directory. This is the way i am using for creating an UEFI bootable usbkey :-) My u-boot doesn't start automatically but it stop with the efi shell. Inside this efi shell i can start the uboot efi manually from the cli and it work fine. Now that i have an uboot that can start, i am trying how to start it directly on boot. Maybe i need to change its name ? or something else like this ? You was talking about some issues for the payload version ; do you have more detail about that ? BR Thierry 2018-08-01 2:57 GMT+02:00 Bin Meng : > On Wed, Aug 1, 2018 at 2:32 AM, Thierry Gayet > wrote: > > hi bin, > > > > Thanks for your reply. > > > > Yes, you are totaly right because my uboot efi app didn't start due to my > > architecture x86_64. > > > > Then i have try with a uboot efi payload (x86_64) and it start from efi > > shell. > > > > I have tested with an usbkey using an EFI vfat partition formated as a > vfat. > > After that i have copyied my several filles from uboot efi payload x86_64 > > and it start manually, not automatically. I don't know how to let it > start > > automaticaly ? any idea ? > > > > I don't quite understand what you were doing. Please include some details. > > > Do you know what kind of issue there is on the uboot efi payload version > ? > > > > Thanks in advance of you're reply. > > > > Regards, > Bin > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] scsi: ceva: add ls1021a soc support.
On 1.8.2018 08:15, Peng Ma wrote:
> Add ahci compatible support for ls1021a soc.
>
> Signed-off-by: Peng Ma
> ---
> drivers/ata/sata_ceva.c | 24
> 1 files changed, 24 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
> index aa31515..e45679b 100644
> --- a/drivers/ata/sata_ceva.c
> +++ b/drivers/ata/sata_ceva.c
> @@ -82,13 +82,24 @@
> #define CEVA_TRANS_CFG 0x0829
> #define CEVA_AXICC_CFG 0x3fff
>
> +/* for ls1021a */
> +#define LS1021_AHCI_VEND_AXICC 0xC0
> +#define LS1021_CEVA_PHY2_CFG 0x28183414
> +#define LS1021_CEVA_PHY3_CFG 0x0e080e06
> +#define LS1021_CEVA_PHY4_CFG 0x064a080b
> +#define LS1021_CEVA_PHY5_CFG v
> +
> /* ecc addr-val pair */c
> #define ECC_DIS_ADDR_CH2 0x8000
> #define ECC_DIS_VAL_CH2 0x20140520
> +#define SATA_ECC_REG_ADDR0x20220520
> +#define SATA_ECC_DISABLE 0x0002
>
> enum ceva_soc {
> CEVA_1V84,
> CEVA_LS1012A,
> + CEVA_LS1021A,
> CEVA_LS1043A,
> };
>
> @@ -115,6 +126,18 @@ static int ceva_init_sata(struct ceva_sata_priv *priv)
> writel(tmp, base + AHCI_VEND_PTC);
> break;
>
> + case CEVA_LS1021A:
> + writel(SATA_ECC_DISABLE, SATA_ECC_REG_ADDR);
> + writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
> + writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
> + writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
> + writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
> + writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
> + writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
> + if (priv->flag & FLAG_COHERENT)
> + writel(CEVA_AXICC_CFG, base + LS1021_AHCI_VEND_AXICC);
> + break;
> +
> case CEVA_LS1012A:
> case CEVA_LS1043A:
> writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
> @@ -147,6 +170,7 @@ static int sata_ceva_probe(struct udevice *dev)
> static const struct udevice_id sata_ceva_ids[] = {
> { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
> { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
> + { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
> { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
> { }
> };
>
Acked-by: Michal Simek
Thanks,
Michal
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Re: [U-Boot] [PATCH v5 00/27] SPI-NAND support
On Wed, Aug 1, 2018 at 12:55 AM, Boris Brezillon wrote: > Hi Jagan, > > On Tue, 31 Jul 2018 20:03:47 +0530 > Jagan Teki wrote: > >> > Applied to u-boot-spi/master >> >> Look like we have some build issues [1]? > > Yep, I reproduced the issue. Looks like u-boot Makefile hierarchy is a > bit different from Linux one, and patch is breaking raw/parallel NAND > build. I fixed it up (see below diff). This diff should be merged in > patch 9, and you'll have to fix a few conflicts when rebasing. Here is > a branch [1] containing this fixup commit (placed just after the > offending one) in case you want to check the end result. Thanks, better send a patch v5.1 and point me where we need to apply with in the series so-that it can't break individual commits. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/4] scsi: ceva: add ls1021a soc support.
Add ahci compatible support for ls1021a soc.
Signed-off-by: Peng Ma
---
drivers/ata/sata_ceva.c | 24
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index aa31515..e45679b 100644
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@@ -82,13 +82,24 @@
#define CEVA_TRANS_CFG 0x0829
#define CEVA_AXICC_CFG 0x3fff
+/* for ls1021a */
+#define LS1021_AHCI_VEND_AXICC 0xC0
+#define LS1021_CEVA_PHY2_CFG 0x28183414
+#define LS1021_CEVA_PHY3_CFG 0x0e080e06
+#define LS1021_CEVA_PHY4_CFG 0x064a080b
+#define LS1021_CEVA_PHY5_CFG 0x2aa86470
+
/* ecc addr-val pair */
#define ECC_DIS_ADDR_CH2 0x8000
#define ECC_DIS_VAL_CH20x20140520
+#define SATA_ECC_REG_ADDR 0x20220520
+#define SATA_ECC_DISABLE 0x0002
enum ceva_soc {
CEVA_1V84,
CEVA_LS1012A,
+ CEVA_LS1021A,
CEVA_LS1043A,
};
@@ -115,6 +126,18 @@ static int ceva_init_sata(struct ceva_sata_priv *priv)
writel(tmp, base + AHCI_VEND_PTC);
break;
+ case CEVA_LS1021A:
+ writel(SATA_ECC_DISABLE, SATA_ECC_REG_ADDR);
+ writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
+ writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
+ writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
+ writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
+ writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
+ writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
+ if (priv->flag & FLAG_COHERENT)
+ writel(CEVA_AXICC_CFG, base + LS1021_AHCI_VEND_AXICC);
+ break;
+
case CEVA_LS1012A:
case CEVA_LS1043A:
writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
@@ -147,6 +170,7 @@ static int sata_ceva_probe(struct udevice *dev)
static const struct udevice_id sata_ceva_ids[] = {
{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
+ { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
{ .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
{ }
};
--
1.7.1
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[U-Boot] [PATCH 3/4] arm: ls1021atwr: enable DM support for sata
Enable related configs to support sata DM feature. Signed-off-by: Peng Ma --- configs/ls1021atwr_nor_defconfig |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index f4f7998..ffee644 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -50,3 +50,8 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_BLK=y CONFIG_DM_MMC=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/4] armv7: dts: fsl-ls1021a: add sata node support enable sata for ls1021a-qds and ls1021a-twr
Add sata node to support this feature.
Signed-off-by: Peng Ma
---
arch/arm/dts/ls1021a-qds.dtsi |4
arch/arm/dts/ls1021a-twr.dtsi |4
arch/arm/dts/ls1021a.dtsi |7 +++
3 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/ls1021a-qds.dtsi b/arch/arm/dts/ls1021a-qds.dtsi
index fb1af15..47c128f 100644
--- a/arch/arm/dts/ls1021a-qds.dtsi
+++ b/arch/arm/dts/ls1021a-qds.dtsi
@@ -212,3 +212,7 @@
&uart1 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi
index 63f2079..14e0cea 100644
--- a/arch/arm/dts/ls1021a-twr.dtsi
+++ b/arch/arm/dts/ls1021a-twr.dtsi
@@ -103,3 +103,7 @@
&uart1 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 5b3fc6a..dcc4ac7 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -404,5 +404,12 @@
ranges = <0x8100 0x0 0x 0x3402 0x0
0x0001 /* downstream I/O */
0x8200 0x0 0x3800 0x3800 0x0
0x0800>; /* non-prefetchable memory */
};
+
+ sata: sata@320 {
+ compatible = "fsl,ls1021a-ahci";
+ reg = <0x320 0x1>;
+ interrupts = <0 101 4>;
+ status = "disabled";
+ };
};
};
--
1.7.1
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[U-Boot] [PATCH 1/4] armv7: fsl: remove sata support
Remove the old implementation in order to enable DM for sata
Signed-off-by: Peng Ma
---
arch/arm/cpu/armv7/ls102xa/Makefile |1 -
arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c | 41 -
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 27 --
arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h | 10 -
board/freescale/ls1021aiot/ls1021aiot.c |5 ---
board/freescale/ls1021aqds/ls1021aqds.c |4 --
board/freescale/ls1021atwr/ls1021atwr.c |4 --
7 files changed, 0 insertions(+), 92 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
delete mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile
b/arch/arm/cpu/armv7/ls102xa/Makefile
index f8300c7..0c1596f 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -10,7 +10,6 @@ obj-y += timer.o
obj-y += fsl_epu.o
obj-y += soc.o
-obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
deleted file mode 100644
index c9fe752..000
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-#include
-#include
-#include
-#include
-#include
-
-/* port register default value */
-#define AHCI_PORT_PHY_1_CFG0xa003fffe
-#define AHCI_PORT_PHY_2_CFG0x28183414
-#define AHCI_PORT_PHY_3_CFG0x0e080e06
-#define AHCI_PORT_PHY_4_CFG0x064a080b
-#define AHCI_PORT_PHY_5_CFG0x2aa86470
-#define AHCI_PORT_TRANS_CFG0x0829
-
-#define SATA_ECC_REG_ADDR 0x20220520
-#define SATA_ECC_DISABLE 0x0002
-
-int ls1021a_sata_init(void)
-{
- struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
- out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
-#endif
-
- out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
- out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
- out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG);
- out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG);
- out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
-
- ahci_init((void __iomem *)AHCI_BASE_ADDR);
- scsi_scan(false);
-
- return 0;
-}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 13a282f..d6ba298 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -389,33 +389,6 @@ struct ccsr_serdes {
u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
};
-
-
-/* AHCI (sata) register map */
-struct ccsr_ahci {
- u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
- u32 pcfg; /* port config */
- u32 ppcfg; /* port phy1 config */
- u32 pp2c; /* port phy2 config */
- u32 pp3c; /* port phy3 config */
- u32 pp4c; /* port phy4 config */
- u32 pp5c; /* port phy5 config */
- u32 paxic; /* port AXI config */
- u32 axicc; /* AXI cache control */
- u32 axipc; /* AXI PROT control */
- u32 ptc;/* port Trans Config */
- u32 pts;/* port Trans Status */
- u32 plc;/* port link config */
- u32 plc1; /* port link config1 */
- u32 plc2; /* port link config2 */
- u32 pls;/* port link status */
- u32 pls1; /* port link status1 */
- u32 pcmdc; /* port CMD config */
- u32 ppcs; /* port phy control status */
- u32 pberr; /* port 0/1 BIST error */
- u32 cmds; /* port 0/1 CMD status error */
-};
-
#define RCPM_POWMGTCSR 0x130
#define RCPM_POWMGTCSR_SERDES_PW 0x8000
#define RCPM_POWMGTCSR_LPM20_REQ 0x0010
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
deleted file mode 100644
index 3acc5af..000
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-
-#ifndef __FSL_SATA_H_
-#define __FSL_SATA_H_
-
-int ls1021a_sata_init(void);
-#endif
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c
b/board/freescale/ls1021aiot/ls1021aiot.c
index a691dab..fb05b55 100644
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -11,7 +11,6 @@
#include
#include
-#include
#include
#include
#include
@@ -206,10 +205,6 @@ int board_init(void)
#ifdef CONFIG_BOA
Re: [U-Boot] xyz-modem: Change getc timeout loop waiting
Hi, On 08/01/2018 08:54 AM, Alexander Sverdlin wrote: Is the timeout a watchdog timeout or some communication freeze? I suppose, it reports false-positive timeout back to ymodem code. Because all it does is terminating communication gracefully (with 'C' and a bunch of CANs). If you are using omap_wdt then check the configured value of the timeout (WDT_HW_TIMEOUT). Time the y-modem loading, and if the reset happens just after that configured value, it would indicate that the watchdog is not kicked, for one reason or another. Tomas ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] efi_loader: don't allocate unusable RAM
On 07/31/2018 09:44 PM, Stephen Warren wrote:
> From: Stephen Warren
>
> Some boards define a maximum usable RAM top that's more restrictive than
> the ranges defined by U-Boot's memory bank definitions[1]. In this case,
> the unusable RAM isn't mapped in the page tables, and so the EFI code must
> not attempt to allocate RAM from outside the usable regions. Fix
> efi_find_free_memory() to detect when max_addr is unconstrained or out of
> range, and substitue a valid value.
>
In this case the board has to call efi_add_memory_map() to mark the
reserved region (cf. board/raspberrypi/rpi/rpi.c) or have to mark the
memory region as reserved in the device tree (see efi_carve_out_dt_rsv()).
Please, check if the tegra boards with which you had problems do so.
Best regards
Heinrich
> [1] For example, when some peripherals can't access RAM above 4GiB, it's
> simplest to force U-Boot's ram_top to a smaller value to avoid dealing
> with this issue more explicitly. However, the RAM bank definitions still
> describe the unusable RAM so that the booted OS has access to it, since
> the OS can typically deal with such restrictions in a more complex
> manner.
>
> Fixes: aa909462d018 "efi_loader: efi_allocate_pages is too restrictive"
> Cc: Heinrich Schuchardt
> Cc: Alexander Graf
> Signed-off-by: Stephen Warren
> ---
> lib/efi_loader/efi_memory.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
> index 967c3f733e4c..5064ff2ccbe8 100644
> --- a/lib/efi_loader/efi_memory.c
> +++ b/lib/efi_loader/efi_memory.c
> @@ -251,6 +251,9 @@ static uint64_t efi_find_free_memory(uint64_t len,
> uint64_t max_addr)
> {
> struct list_head *lhandle;
>
> + if ((max_addr == -1ULL) || (max_addr > gd->ram_top))
> + max_addr = gd->ram_top;
> +
> list_for_each(lhandle, &efi_mem) {
> struct efi_mem_list *lmem = list_entry(lhandle,
> struct efi_mem_list, link);
>
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Re: [U-Boot] xyz-modem: Change getc timeout loop waiting
Hi,
On 08/01/2018 03:15 AM, Alexander Sverdlin wrote:
This commit breaks YMODEM SPL->U-Boot boot on Beagle Bone,
transfer is aborted (because of timeout) after 497kb
(u-boot.img is around 570kb).
Reverting the commit repairs YMODEM boot.
Is the timeout a watchdog timeout or some communication freeze?
In case watchdog is correctly configured, kicking should still
happen.
Tomas
---
common/xyzModem.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/common/xyzModem.c b/common/xyzModem.c
index 5656aac..e0d87db 100644
--- a/common/xyzModem.c
+++ b/common/xyzModem.c
@@ -71,12 +71,12 @@ typedef int cyg_int32;
static int
CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c)
{
-#define DELAY 20
- unsigned long counter = 0;
- while (!tstc () && (counter < xyzModem_CHAR_TIMEOUT * 1000 / DELAY))
+
+ ulong now = get_timer(0);
+ while (!tstc ())
{
- udelay (DELAY);
- counter++;
+ if (get_timer(now) > xyzModem_CHAR_TIMEOUT)
+break;
}
if (tstc ())
{
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[U-Boot] [PATCH 2/2] sandbox: Enable bitrev library build
Turn on CONFIG_BITREVERSE for all sandbox builds. Signed-off-by: Bin Meng --- configs/sandbox64_defconfig| 1 + configs/sandbox_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_noblk_defconfig| 1 + configs/sandbox_spl_defconfig | 1 + 5 files changed, 5 insertions(+) diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 1fa85a8..dd3c128 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -189,6 +189,7 @@ CONFIG_WDT=y CONFIG_WDT_SANDBOX=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y +CONFIG_BITREVERSE=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 6130290..7408ee6 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -191,6 +191,7 @@ CONFIG_WDT=y CONFIG_WDT_SANDBOX=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y +CONFIG_BITREVERSE=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_TPM_V1=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index e922c4b..a492a21 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -167,6 +167,7 @@ CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y +CONFIG_BITREVERSE=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index 8bdd4ed..550bf20 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -168,6 +168,7 @@ CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y +CONFIG_BITREVERSE=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index fb6bb4b..d076472 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -187,6 +187,7 @@ CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y +CONFIG_BITREVERSE=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] lib: bitrev: Sync with Linux kernel v4.17
Signed-off-by: Bin Meng
---
include/linux/bitrev.h | 102 -
lib/bitrev.c | 28 --
2 files changed, 101 insertions(+), 29 deletions(-)
diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h
index cc5abd7..50fb0de 100644
--- a/include/linux/bitrev.h
+++ b/include/linux/bitrev.h
@@ -1,21 +1,105 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Based on bitrev from the Linux kernel, by Akinobu Mita
- */
-
+/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _LINUX_BITREV_H
#define _LINUX_BITREV_H
#include
-extern u8 const byte_rev_table[256];
+#ifdef CONFIG_HAVE_ARCH_BITREVERSE
+#include
+
+#define __bitrev32 __arch_bitrev32
+#define __bitrev16 __arch_bitrev16
+#define __bitrev8 __arch_bitrev8
-static inline u8 bitrev8(u8 byte)
+#else
+extern u8 const byte_rev_table[256];
+static inline u8 __bitrev8(u8 byte)
{
return byte_rev_table[byte];
}
-u16 bitrev16(u16 in);
-u32 bitrev32(u32 in);
+static inline u16 __bitrev16(u16 x)
+{
+ return (__bitrev8(x & 0xff) << 8) | __bitrev8(x >> 8);
+}
+
+static inline u32 __bitrev32(u32 x)
+{
+ return (__bitrev16(x & 0x) << 16) | __bitrev16(x >> 16);
+}
+
+#endif /* CONFIG_HAVE_ARCH_BITREVERSE */
+
+#define __bitrev8x4(x) (__bitrev32(swab32(x)))
+
+#define __constant_bitrev32(x) \
+({ \
+ u32 __x = x;\
+ __x = (__x >> 16) | (__x << 16);\
+ __x = ((__x & (u32)0xFF00FF00UL) >> 8) | ((__x & (u32)0x00FF00FFUL) <<
8); \
+ __x = ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) <<
4); \
+ __x = ((__x & (u32)0xUL) >> 2) | ((__x & (u32)0xUL) <<
2); \
+ __x = ((__x & (u32)0xUL) >> 1) | ((__x & (u32)0xUL) <<
1); \
+ __x;\
+})
+
+#define __constant_bitrev16(x) \
+({ \
+ u16 __x = x;\
+ __x = (__x >> 8) | (__x << 8); \
+ __x = ((__x & (u16)0xF0F0U) >> 4) | ((__x & (u16)0x0F0FU) << 4);
\
+ __x = ((__x & (u16)0xU) >> 2) | ((__x & (u16)0xU) << 2);
\
+ __x = ((__x & (u16)0xU) >> 1) | ((__x & (u16)0xU) << 1);
\
+ __x;\
+})
+
+#define __constant_bitrev8x4(x) \
+({ \
+ u32 __x = x;\
+ __x = ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) <<
4); \
+ __x = ((__x & (u32)0xUL) >> 2) | ((__x & (u32)0xUL) <<
2); \
+ __x = ((__x & (u32)0xUL) >> 1) | ((__x & (u32)0xUL) <<
1); \
+ __x;\
+})
+
+#define __constant_bitrev8(x) \
+({ \
+ u8 __x = x; \
+ __x = (__x >> 4) | (__x << 4); \
+ __x = ((__x & (u8)0xCCU) >> 2) | ((__x & (u8)0x33U) << 2); \
+ __x = ((__x & (u8)0xAAU) >> 1) | ((__x & (u8)0x55U) << 1); \
+ __x;\
+})
+
+#define bitrev32(x) \
+({ \
+ u32 __x = x;\
+ __builtin_constant_p(__x) ? \
+ __constant_bitrev32(__x) : \
+ __bitrev32(__x);\
+})
+
+#define bitrev16(x) \
+({ \
+ u16 __x = x;\
+ __builtin_constant_p(__x) ? \
+ __constant_bitrev16(__x) : \
+ __bitrev16(__x);\
+ })
+
+#define bitrev8x4(x) \
+({ \
+ u32 __x = x;\
+ __builtin_constant_p(__x) ? \
+ __constant_bitrev8x4(__x) : \
+ __bitrev8x4(__x); \
+ })
+#define bitrev8(x) \
+({ \
+ u8 __x = x; \
+ __builtin_constant_p(__x) ? \
+ __constant_bitrev8(__x) : \
+ __bitrev8(__x) ; \
+ })
#endif /* _LINUX_BITREV_H */
diff --git a/lib/bitrev.c b/lib/bitrev.c
index 4d494e1..beef6c8 100644
--- a/lib/bitrev.c
+++ b/lib/bitrev.c
@@ -1,13 +1,12 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * Based on bitrev from the Linux kernel, by Akinobu Mita
- */
-
-
+#ifndef CONFIG_HAVE_ARCH_BITREVERSE
#include
+#include
#include
+MODULE_AUTHOR("Akinobu Mita ");
+MODULE_DESCRIPTION("Bit ordering reversal functions");
+MODULE_LICENSE("GPL");
+
const u8 byte_rev_table[256] = {
0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
@@ -42,17 +41,6 @@ const u8 byte_rev_table[256] = {
0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
};
+EXPORT_SYMBOL_GPL(byte_rev_table);
[U-Boot] [PATCH 2/3,v2] scsi: ceva: add ls1043a soc support
Add ahci compatible support for ls1043a soc.
Signed-off-by: Peng Ma
---
v2:
-move compatible to orginal position
-rebase from master
drivers/ata/sata_ceva.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index 047cff7..327ffa5 100644
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@@ -88,6 +88,7 @@
enum ceva_soc {
CEVA_1V84,
CEVA_LS1012A,
+ CEVA_LS1043A,
};
struct ceva_sata_priv {
@@ -114,6 +115,7 @@ static int ceva_init_sata(struct ceva_sata_priv *priv)
break;
case CEVA_LS1012A:
+ case CEVA_LS1043A:
writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
@@ -144,6 +146,7 @@ static int sata_ceva_probe(struct udevice *dev)
static const struct udevice_id sata_ceva_ids[] = {
{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
+ { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
{ }
};
--
1.7.1
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[U-Boot] [PATCH 1/3, v2] armv8: dts: fsl-ls1043a: add sata node support
Add sata node to support ls1043a.
Signed-off-by: Peng Ma
---
v2:
-no changes
arch/arm/dts/fsl-ls1043a-qds.dtsi |4
arch/arm/dts/fsl-ls1043a.dtsi |8
2 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi
b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index addb9ab..3841aee 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -174,3 +174,7 @@
&lpuart0 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index a804f51..bb70992 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -287,5 +287,13 @@
ranges = <0x8100 0x0 0x 0x50 0x0002 0x0
0x0001 /* downstream I/O */
0x8200 0x0 0x4000 0x50 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
+
+ sata: sata@320 {
+ compatible = "fsl,ls1043a-ahci";
+ reg = <0x0 0x320 0x0 0x1>;
+ interrupts = <0 69 4>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
};
};
--
1.7.1
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[U-Boot] [PATCH 3/3, v2] arm64: ls1043aqds: enable DM support for sata
Enable related configs to support sata DM feature. Signed-off-by: Peng Ma --- v2: -no changes configs/ls1043aqds_defconfig |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 73f7f8a..5510509 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -48,3 +48,8 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_BLK=y CONFIG_DM_MMC=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device tree
> -Original Message- > From: Horia Geanta > Sent: Tuesday, July 31, 2018 9:49 PM > To: Laurentiu Tudor ; u-boot@lists.denx.de; > Prabhakar Kushwaha ; York Sun > > Cc: Bharat Bhushan > Subject: Re: [PATCH v6 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device > tree > > On 7/31/2018 5:53 PM, laurentiu.tu...@nxp.com wrote: > > From: Laurentiu Tudor > > > > Add support for SEC ICID configuration and apply it for ls1046a. > > Also add code to make the necessary device tree fixups. > > > > Signed-off-by: Laurentiu Tudor > Reviewed-by: Horia Geantă Reviewed-by: Bharat Bhushan Thanks -Bharat > > [snip] > > +#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \ > > + SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ > > + offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \ > > + CONFIG_SYS_FSL_SEC_ADDR, 0) > > + > RTIC nodes have a binding doc in Linux kernel: > Documentation/devicetree/bindings/crypto/fsl-sec4.txt > > Thus, in theory, "fsl,sec-v4.0-rtic-memory" could be used instead of NULL for > the compat string. > PPC code in arch/powerpc/include/asm/fsl_liodn.h does this. > > In practice, this won't make any difference until a RTIC kernel driver is > added. > > Regards, > Horia > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 7/8] armv8: ls1046a: setup fman ports ICIDs and device tree
> -Original Message-
> From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com]
> Sent: Tuesday, July 31, 2018 8:22 PM
> To: u-boot@lists.denx.de; Prabhakar Kushwaha
> ; York Sun
> Cc: Bharat Bhushan ; Horia Geanta
> ; Laurentiu Tudor
> Subject: [PATCH v6 7/8] armv8: ls1046a: setup fman ports ICIDs and device
> tree
>
> From: Laurentiu Tudor
>
> Add support for ICID setting of fman ports and the required device tree
> fixups.
>
> Signed-off-by: Laurentiu Tudor
Reviewed-by: Bharat Bhushan
Thanks
-Bharat
> ---
> arch/arm/cpu/armv8/fsl-layerscape/icid.c | 82 +++
> .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++
> .../asm/arch-fsl-layerscape/fsl_icid.h| 10 +++
> 3 files changed, 122 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> index ae3b8daa95..b1a950e7f9 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> @@ -10,6 +10,7 @@
> #include
> #include
> #include
> +#include
>
> static void set_icid(struct icid_id_table *tbl, int size) { @@ -19,10
> +20,27 @@
> static void set_icid(struct icid_id_table *tbl, int size)
> out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); }
>
> +#ifdef CONFIG_SYS_DPAA_FMAN
> +void set_fman_icids(struct fman_icid_id_table *tbl, int size) {
> + int i;
> + ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
> +
> + for (i = 0; i < size; i++) {
> + out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id
> - 1],
> + tbl[i].icid);
> + }
> +}
> +#endif
> +
> void set_icids(void)
> {
> /* setup general icid offsets */
> set_icid(icid_tbl, icid_tbl_sz);
> +
> +#ifdef CONFIG_SYS_DPAA_FMAN
> + set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz); #endif
> }
>
> int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int
> num_ids) @@ -75,6 +93,66 @@ int fdt_fixup_icid_tbl(void *blob, int
> smmu_ph,
> return 0;
> }
>
> +#ifdef CONFIG_SYS_DPAA_FMAN
> +int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
> +const int size)
> +{
> + int i;
> +
> + for (i = 0; i < size; i++) {
> + if (tbl[i].port_id == port_id)
> + return tbl[i].icid;
> + }
> +
> + return -1;
> +}
> +
> +void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
> + const char *compat)
> +{
> + int noff, len, icid;
> + const u32 *prop;
> +
> + noff = fdt_node_offset_by_compatible(blob, -1, compat);
> + while (noff > 0) {
> + prop = fdt_getprop(blob, noff, "cell-index", &len);
> + if (!prop) {
> + printf("WARNING missing cell-index for fman
> port\n");
> + continue;
> + }
> + if (len != 4) {
> + printf("WARNING bad cell-index size for fman
> port\n");
> + continue;
> + }
> +
> + icid = get_fman_port_icid(fdt32_to_cpu(*prop),
> + fman_icid_tbl, fman_icid_tbl_sz);
> + if (icid < 0) {
> + printf("WARNING unknown ICID for fman port
> %d\n",
> +*prop);
> + continue;
> + }
> +
> + fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *)&icid, 1);
> +
> + noff = fdt_node_offset_by_compatible(blob, noff, compat);
> + }
> +}
> +
> +void fdt_fixup_fman_icids(void *blob, int smmu_ph) {
> + static const char * const compats[] = {
> + "fsl,fman-v3-port-oh",
> + "fsl,fman-v3-port-rx",
> + "fsl,fman-v3-port-tx",
> + };
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(compats); i++)
> + fdt_fixup_fman_port_icid_by_compat(blob, smmu_ph,
> compats[i]); }
> +#endif
> +
> int fdt_get_smmu_phandle(void *blob)
> {
> int noff, smmu_ph;
> @@ -107,4 +185,8 @@ void fdt_fixup_icid(void *blob)
> return;
>
> fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz);
> +
> +#ifdef CONFIG_SYS_DPAA_FMAN
> + fdt_fixup_fman_icids(blob, smmu_ph);
> +#endif
> }
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> index 80e1ceadc0..30c7d8d28a 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> @@ -43,3 +43,33 @@ struct icid_id_table icid_tbl[] = { };
>
> int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
> +
> +#ifdef CONFIG_SYS_DPAA_FMAN
> +struct fman_icid_id_table fman_icid_tbl[] = {
> + /* port id, icid */
> + SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
> + SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END),
> + SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END),
> + SET_FMAN_ICID_ENTRY(0x05, FSL_
Re: [U-Boot] [PATCH v6 5/8] armv8: ls1046a: initial icid setup support
> -Original Message-
> From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com]
> Sent: Tuesday, July 31, 2018 8:22 PM
> To: u-boot@lists.denx.de; Prabhakar Kushwaha
> ; York Sun
> Cc: Bharat Bhushan ; Horia Geanta
> ; Laurentiu Tudor
> Subject: [PATCH v6 5/8] armv8: ls1046a: initial icid setup support
>
> From: Laurentiu Tudor
>
> Add infrastructure for ICID setup and device tree fixup on ARM platforms.
> This include basic ICID setup for several devices.
>
> Signed-off-by: Laurentiu Tudor
Reviewed-by: Bharat Bhushan
Thanks
-Bharat
> ---
> arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
> arch/arm/cpu/armv8/fsl-layerscape/icid.c | 110 ++
> .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 29 +
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +
> .../asm/arch-fsl-layerscape/fsl_icid.h| 80 +
> board/freescale/ls1046aqds/ls1046aqds.c | 3 +
> board/freescale/ls1046ardb/ls1046ardb.c | 3 +
> 7 files changed, 229 insertions(+)
> create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
> create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> index 1e9e4680fe..5d6f68aad6 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> @@ -37,6 +37,7 @@ endif
>
> ifneq ($(CONFIG_ARCH_LS1046A),)
> obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
> +obj-y += icid.o ls1046_ids.o
> endif
>
> ifneq ($(CONFIG_ARCH_LS1088A),)
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> new file mode 100644
> index 00..ae3b8daa95
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> @@ -0,0 +1,110 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +
> +static void set_icid(struct icid_id_table *tbl, int size) {
> + int i;
> +
> + for (i = 0; i < size; i++)
> + out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); }
> +
> +void set_icids(void)
> +{
> + /* setup general icid offsets */
> + set_icid(icid_tbl, icid_tbl_sz);
> +}
> +
> +int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int
> +num_ids) {
> + int i, ret;
> + u32 prop[8];
> +
> + /*
> + * Note: The "iommus" property definition mentions Stream IDs
> while
> + * this code handles ICIDs. The current implementation assumes that
> + * ICIDs and Stream IDs are equal.
> + */
> + for (i = 0; i < num_ids; i++) {
> + prop[i * 2] = cpu_to_fdt32(smmu_ph);
> + prop[i * 2 + 1] = cpu_to_fdt32(ids[i]);
> + }
> + ret = fdt_setprop(blob, off, "iommus",
> + prop, sizeof(u32) * num_ids * 2);
> + if (ret) {
> + printf("WARNING unable to set iommus: %s\n",
> fdt_strerror(ret));
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
> +struct icid_id_table *tbl, int size) {
> + int i, err, off;
> +
> + for (i = 0; i < size; i++) {
> + if (!tbl[i].compat)
> + continue;
> +
> + off = fdt_node_offset_by_compat_reg(blob,
> + tbl[i].compat,
> + tbl[i].compat_addr);
> + if (off > 0) {
> + err = fdt_set_iommu_prop(blob, off, smmu_ph,
> + &tbl[i].id, 1);
> + if (err)
> + return err;
> + } else {
> + printf("WARNING could not find node %s: %s.\n",
> +tbl[i].compat, fdt_strerror(off));
> + }
> + }
> +
> + return 0;
> +}
> +
> +int fdt_get_smmu_phandle(void *blob)
> +{
> + int noff, smmu_ph;
> +
> + noff = fdt_node_offset_by_compatible(blob, -1, "arm,mmu-500");
> + if (noff < 0) {
> + printf("WARNING failed to get smmu node: %s\n",
> +fdt_strerror(noff));
> + return noff;
> + }
> +
> + smmu_ph = fdt_get_phandle(blob, noff);
> + if (!smmu_ph) {
> + smmu_ph = fdt_create_phandle(blob, noff);
> + if (!smmu_ph) {
> + printf("WARNING failed to get smmu phandle\n");
> + return -1;
> + }
> + }
> +
> + return smmu_ph;
> +}
> +
> +void fdt_fixup_icid(void *blob)
> +{
> + int smmu_ph;
> +
> + smmu_ph = fdt_get_smmu_phandle(blob);
> + if (smmu_ph < 0)
> + return;
> +
> + fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz); }
>
Re: [U-Boot] [PATCH v6 6/8] armv8: ls1046a: add icid setup for qman portals
> -Original Message-
> From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com]
> Sent: Tuesday, July 31, 2018 8:22 PM
> To: u-boot@lists.denx.de; Prabhakar Kushwaha
> ; York Sun
> Cc: Bharat Bhushan ; Horia Geanta
> ; Laurentiu Tudor
> Subject: [PATCH v6 6/8] armv8: ls1046a: add icid setup for qman portals
>
> From: Laurentiu Tudor
>
> Add support for ICID setting of qman portals and the required device
> tree fixups. Also fix an endiness issue in portal setup code.
>
> Signed-off-by: Laurentiu Tudor
Reviewed-by: Bharat Bhushan
Thanks
-Bharat
> ---
> .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
> .../asm/arch-fsl-layerscape/fsl_portals.h | 24 +++
> drivers/misc/fsl_portals.c| 43 +++
> 3 files changed, 75 insertions(+), 8 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> index 1c528ab751..80e1ceadc0 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> @@ -6,6 +6,22 @@
> #include
> #include
> #include
> +#include
> +
> +#ifdef CONFIG_SYS_DPAA_QBMAN
> +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> +};
> +#endif
>
> struct icid_id_table icid_tbl[] = {
> #ifdef CONFIG_SYS_DPAA_QBMAN
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> new file mode 100644
> index 00..1577e935a6
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#ifndef _FSL_PORTALS_H_
> +#define _FSL_PORTALS_H_
> +
> +struct qportal_info {
> + u16 dicid; /* DQRR ICID */
> + u16 ficid; /* frame data ICID */
> + u16 icid;
> + u8 sdest;
> +};
> +
> +#define SET_QP_INFO(streamid, dest) \
> + { .dicid = (streamid), .ficid = (streamid), .icid = (streamid), \
> + .sdest = (dest) }
> +
> +extern struct qportal_info qp_info[];
> +void fdt_portal(void *blob, const char *compat, const char *container,
> + u64 addr, u32 size);
> +
> +#endif
> diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
> index 22faf16751..a524510707 100644
> --- a/drivers/misc/fsl_portals.c
> +++ b/drivers/misc/fsl_portals.c
> @@ -13,6 +13,9 @@
> #ifdef CONFIG_PPC
> #include
> #include
> +#else
> +#include
> +#include
> #endif
> #include
>
> @@ -45,6 +48,22 @@ void setup_qbman_portals(void)
> /* set frame liodn */
> out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) |
> fliodn);
> }
> +#else
> +#ifdef CONFIG_ARM
> + int i;
> +
> + for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
> + u8 sdest = qp_info[i].sdest;
> + u16 ficid = qp_info[i].ficid;
> + u16 dicid = qp_info[i].dicid;
> + u16 icid = qp_info[i].icid;
> +
> + out_be32(&qman->qcsp[i].qcsp_lio_cfg, (icid << 16) |
> + dicid);
> + /* set frame icid */
> + out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | ficid);
> + }
> +#endif
> #endif
>
> /* Change default state of BMan ISDR portals to all 1s */
> @@ -178,6 +197,10 @@ void fdt_fixup_qportals(void *blob)
> char compat[64];
> int compat_len;
>
> +#ifndef CONFIG_PPC
> + int smmu_ph = fdt_get_smmu_phandle(blob);
> +#endif
> +
> maj = (rev_1 >> 8) & 0xff;
> min = rev_1 & 0xff;
> ip_cfg = rev_2 & 0xff;
> @@ -188,7 +211,6 @@ void fdt_fixup_qportals(void *blob)
>
> off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
> while (off != -FDT_ERR_NOTFOUND) {
> -#ifdef CONFIG_PPC
> #ifdef CONFIG_FSL_CORENET
> u32 liodns[2];
> #endif
> @@ -198,12 +220,7 @@ void fdt_fixup_qportals(void *blob)
> if (!ci)
> goto err;
>
> - i = *ci;
> -#ifdef CONFIG_SYS_DPAA_FMAN
> - int j;
> -#endif
> -
> -#endif /* CONFIG_PPC */
> + i = fdt32_to_cpu(*ci);
> err = fdt_setprop(blob, off, "compatible", compat,
> compat_len);
> if (err < 0)
> goto err;
> @@ -235,7 +252,7 @@ void fdt_fixup_qportals(void *blob)
> #endif
>
>
Re: [U-Boot] [PATCH v6 4/8] armv8: fsl-layerscape: add missing debug stream ID
> -Original Message- > From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com] > Sent: Tuesday, July 31, 2018 8:22 PM > To: u-boot@lists.denx.de; Prabhakar Kushwaha > ; York Sun > Cc: Bharat Bhushan ; Horia Geanta > ; Laurentiu Tudor > Subject: [PATCH v6 4/8] armv8: fsl-layerscape: add missing debug stream ID > > From: Laurentiu Tudor > > Add a define with a value for the missing debug stream ID. > > Signed-off-by: Laurentiu Tudor Reviewed-by: Bharat Bhushan Thanks -Bharat > --- > arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h > b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h > index 61c6e533c6..1b02d484d9 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h > @@ -50,6 +50,7 @@ > #define FSL_QDMA_STREAM_ID 7 > #define FSL_EDMA_STREAM_ID 8 > #define FSL_ETR_STREAM_ID9 > +#define FSL_DEBUG_STREAM_ID 10 > > /* PCI - programmed in PEXn_LUT */ > #define FSL_PEX_STREAM_ID_START 11 > -- > 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 3/8] misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms
> -Original Message-
> From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com]
> Sent: Tuesday, July 31, 2018 8:22 PM
> To: u-boot@lists.denx.de; Prabhakar Kushwaha
> ; York Sun
> Cc: Bharat Bhushan ; Horia Geanta
> ; Laurentiu Tudor
> Subject: [PATCH v6 3/8] misc: fsl_portals: setup QMAN_BAR{E} also on ARM
> platforms
>
> From: Laurentiu Tudor
>
> QMAN_BAR{E} register setup was disabled on ARM platforms, however the
> register does need to be set. Enable the code also on ARMs and fix the
> CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the
> newly
> enabled code works.
>
> Signed-off-by: Laurentiu Tudor
Reviewed-by: Bharat Bhushan
Thanks
-Bharat
> ---
> arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +--
> drivers/misc/fsl_portals.c | 2 --
> 2 files changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> index 644a16dd30..d22ec70aa5 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> @@ -57,8 +57,7 @@
> #define CONFIG_SYS_BMAN_SWP_ISDR_REG0x3E80
> #define CONFIG_SYS_QMAN_NUM_PORTALS 10
> #define CONFIG_SYS_QMAN_MEM_BASE 0x5
> -#define CONFIG_SYS_QMAN_MEM_PHYS (0xfull + \
> -
> CONFIG_SYS_QMAN_MEM_BASE)
> +#define CONFIG_SYS_QMAN_MEM_PHYS
> CONFIG_SYS_QMAN_MEM_BASE
> #define CONFIG_SYS_QMAN_MEM_SIZE 0x0800
> #define CONFIG_SYS_QMAN_SP_CENA_SIZE0x1
> #define CONFIG_SYS_QMAN_SP_CINH_SIZE0x1
> diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
> index 7c22b8d209..22faf16751 100644
> --- a/drivers/misc/fsl_portals.c
> +++ b/drivers/misc/fsl_portals.c
> @@ -24,7 +24,6 @@ void setup_qbman_portals(void)
> CONFIG_SYS_BMAN_SWP_ISDR_REG;
> void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
> CONFIG_SYS_QMAN_SWP_ISDR_REG;
> -#ifdef CONFIG_PPC
> struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
>
> /* Set the Qman initiator BAR to match the LAW (for DQRR stashing)
> */
> @@ -32,7 +31,6 @@ void setup_qbman_portals(void)
> out_be32(&qman->qcsp_bare,
> (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
> #endif
> out_be32(&qman->qcsp_bar,
> (u32)CONFIG_SYS_QMAN_MEM_PHYS);
> -#endif
> #ifdef CONFIG_FSL_CORENET
> int i;
>
> --
> 2.17.1
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Re: [U-Boot] [PATCH v6 2/8] armv8: ls1046a: advertise QMan v3 in configuration
> -Original Message- > From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com] > Sent: Tuesday, July 31, 2018 8:22 PM > To: u-boot@lists.denx.de; Prabhakar Kushwaha > ; York Sun > Cc: Bharat Bhushan ; Horia Geanta > ; Laurentiu Tudor > Subject: [PATCH v6 2/8] armv8: ls1046a: advertise QMan v3 in configuration > > From: Laurentiu Tudor > > The QMan IP block in this SoC is version 3.2 so advertise this in the SoC > configuration header. > > Signed-off-by: Laurentiu Tudor Reviewed-by: Bharat Bhushan Thanks -Bharat > --- > arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h > b/arch/arm/include/asm/arch-fsl-layerscape/config.h > index 23faffd9fc..8a05148136 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h > @@ -257,6 +257,7 @@ > > #elif defined(CONFIG_ARCH_LS1046A) > #define CONFIG_SYS_FMAN_V3 > +#define CONFIG_SYS_FSL_QMAN_V3 > #define CONFIG_SYS_NUM_FMAN 1 > #define CONFIG_SYS_NUM_FM1_DTSEC 8 > #define CONFIG_SYS_NUM_FM1_10GEC 2 > -- > 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 1/8] armv8: fsl-layerscape: add missing register blocks base address defines
> -Original Message- > From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com] > Sent: Tuesday, July 31, 2018 8:22 PM > To: u-boot@lists.denx.de; Prabhakar Kushwaha > ; York Sun > Cc: Bharat Bhushan ; Horia Geanta > ; Laurentiu Tudor > Subject: [PATCH v6 1/8] armv8: fsl-layerscape: add missing register blocks > base address defines > > From: Laurentiu Tudor > > Add defines for the edma and qdma register block base addresses. > > Signed-off-by: Laurentiu Tudor Reviewed-by: Bharat Bhushan Thanks -Bharat > --- > arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h > b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h > index 5b4767e0fe..644a16dd30 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h > @@ -88,8 +88,12 @@ > > #define LPUART_BASE (CONFIG_SYS_IMMR + > 0x0195) > > +#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR > + 0x01c0) > + > #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR > + 0x0220) > > +#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR > + 0x0738) > + > #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x40ULL > #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x48ULL > #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x50ULL > -- > 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] scsi: ceva: add ls1043a soc support
Hi York:
It's My fault, I could misunderstood your suggest, I will send v2 patch to fix
this issue.
Thanks
Peng
-Original Message-
From: York Sun
Sent: 2018年8月1日 1:38
To: Peng Ma
Cc: albert.u.b...@aribaud.net; Mingkai Hu ; Pankaj Bansal
; Fabio Estevam ; Yinbo Zhu
; s...@chromium.org; bmeng...@gmail.com;
michal.si...@xilinx.com; Andy Tang ; u-boot@lists.denx.de
Subject: Re: [PATCH 2/3] scsi: ceva: add ls1043a soc support
On 07/09/2018 03:42 AM, peng...@nxp.com wrote:
> From: Peng Ma
>
> Add ahci compatible support for ls1043a soc.
>
> Signed-off-by: Peng Ma
> ---
> depend on:
> patchwork.ozlabs.org/patch/924896/
>
> drivers/ata/sata_ceva.c | 16 +---
> 1 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index
> 4c9ebe4..39269fe 100644
> --- a/drivers/ata/sata_ceva.c
> +++ b/drivers/ata/sata_ceva.c
> @@ -7,7 +7,6 @@
> #include
> #include
> #include
> -#include
>
> #include
>
> @@ -90,6 +89,7 @@
> enum ceva_soc {
> CEVA_1V84,
> CEVA_LS1012A,
> + CEVA_LS1043A,
> };
>
> struct ceva_sata_priv {
> @@ -98,6 +98,13 @@ struct ceva_sata_priv {
> ulong flag;
> };
>
> +static const struct udevice_id sata_ceva_ids[] = {
> + { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
> + { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
> + { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
> + { }
> +};
> +
> static int ceva_init_sata(struct ceva_sata_priv *priv) {
> ulong base = priv->base;
> @@ -116,6 +123,7 @@ static int ceva_init_sata(struct ceva_sata_priv *priv)
> break;
>
> case CEVA_LS1012A:
> + case CEVA_LS1043A:
> writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
> writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
> writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); @@ -143,12 +151,6
> @@
> static int sata_ceva_probe(struct udevice *dev)
> return ahci_probe_scsi(dev, priv->base); }
>
> -static const struct udevice_id sata_ceva_ids[] = {
> - { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
> - { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
> - { }
> -};
> -
Why do you move this structure?
York
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Re: [U-Boot] [PATCH 2/3] scsi: ceva: add ls1043a soc support
On 07/31/2018 07:36 PM, Peng Ma wrote:
>
>
> -Original Message-
> From: York Sun
> Sent: 2018年8月1日 1:38
> To: Peng Ma
> Cc: albert.u.b...@aribaud.net; Mingkai Hu ; Pankaj Bansal
> ; Fabio Estevam ; Yinbo Zhu
> ; s...@chromium.org; bmeng...@gmail.com;
> michal.si...@xilinx.com; Andy Tang ; u-boot@lists.denx.de
> Subject: Re: [PATCH 2/3] scsi: ceva: add ls1043a soc support
>
> On 07/09/2018 03:42 AM, peng...@nxp.com wrote:
>> From: Peng Ma
>>
>> Add ahci compatible support for ls1043a soc.
>>
>> Signed-off-by: Peng Ma
>> ---
>> depend on:
>> patchwork.ozlabs.org/patch/924896/
>>
>> drivers/ata/sata_ceva.c | 16 +---
>> 1 files changed, 9 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index
>> 4c9ebe4..39269fe 100644
>> --- a/drivers/ata/sata_ceva.c
>> +++ b/drivers/ata/sata_ceva.c
>> @@ -7,7 +7,6 @@
>> #include
>> #include
>> #include
>> -#include
>>
>> #include
>>
>> @@ -90,6 +89,7 @@
>> enum ceva_soc {
>> CEVA_1V84,
>> CEVA_LS1012A,
>> +CEVA_LS1043A,
>> };
>>
>> struct ceva_sata_priv {
>> @@ -98,6 +98,13 @@ struct ceva_sata_priv {
>> ulong flag;
>> };
>>
>> +static const struct udevice_id sata_ceva_ids[] = {
>> +{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
>> +{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
>> +{ .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
>> +{ }
>> +};
>> +
>> static int ceva_init_sata(struct ceva_sata_priv *priv) {
>> ulong base = priv->base;
>> @@ -116,6 +123,7 @@ static int ceva_init_sata(struct ceva_sata_priv *priv)
>> break;
>>
>> case CEVA_LS1012A:
>> +case CEVA_LS1043A:
>> writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
>> writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
>> writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); @@ -143,12 +151,6
>> @@
>> static int sata_ceva_probe(struct udevice *dev)
>> return ahci_probe_scsi(dev, priv->base); }
>>
>> -static const struct udevice_id sata_ceva_ids[] = {
>> -{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
>> -{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
>> -{ }
>> -};
>> -
>
> Why do you move this structure?
>
> York
>
> Replay:
> In our internal review, you suggested to me that compatible should put
> before, so I did that.
>
Hmm, I don't remember that for this patch. Checking my emails, I
commented on your internal patch set, but not on this change. Anyway, I
see your reason.
York
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[U-Boot] [PATCH 1/1] elf: Add support for PPC64 ELF V1 ABI in bootelf
This update adds PPC64 ELF V1 ABI support to bootelf for both the
program header and section header options. Elf64 support was already
present for the program header option, but it was not handling the
PPC64 ELF V1 ABI case. For the PPC64 ELF V1 ABI, the e_entry field of
the elf header must be treated as function descriptor pointer instead
of a function address. The first doubleword of the function descriptor
is the function's entry address.
Signed-off-by: Rob Bracero
---
:100644 100644 eafea38... 0c38bde... M cmd/elf.c
:100644 100644 6802428... 81f4019... M include/elf.h
cmd/elf.c | 75 ++-
include/elf.h | 3 +++
2 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/cmd/elf.c b/cmd/elf.c
index eafea38..0c38bde 100644
--- a/cmd/elf.c
+++ b/cmd/elf.c
@@ -57,6 +57,77 @@ static unsigned long load_elf64_image_phdr(unsigned long
addr)
++phdr;
}
+ if((ehdr->e_machine == EM_PPC64) && (ehdr->e_flags &
EF_PPC64_ELFV1_ABI))
+ {
+ /*
+* For the 64-bit PowerPC ELF V1 ABI, e_entry is a function
descriptor
+* pointer with the first double word being the address of the entry
+* point of the function.
+*/
+ uintptr_t addr = ehdr->e_entry;
+ return *(Elf64_Addr *)addr;
+ }
+
+ return ehdr->e_entry;
+}
+
+static unsigned long load_elf64_image_shdr(unsigned long addr)
+{
+ Elf64_Ehdr *ehdr; /* Elf header structure pointer */
+ Elf64_Shdr *shdr; /* Section header structure pointer */
+ unsigned char *strtab = 0; /* String table pointer */
+ unsigned char *image; /* Binary image pointer */
+ int i; /* Loop counter */
+
+ ehdr = (Elf64_Ehdr *)addr;
+
+ /* Find the section header string table for output info */
+ shdr = (Elf64_Shdr *)(addr + (ulong)ehdr->e_shoff +
+(ehdr->e_shstrndx * sizeof(Elf64_Shdr)));
+
+ if (shdr->sh_type == SHT_STRTAB)
+ strtab = (unsigned char *)(addr + (ulong)shdr->sh_offset);
+
+ /* Load each appropriate section */
+ for (i = 0; i < ehdr->e_shnum; ++i) {
+ shdr = (Elf64_Shdr *)(addr + (ulong)ehdr->e_shoff +
+(i * sizeof(Elf64_Shdr)));
+
+ if (!(shdr->sh_flags & SHF_ALLOC) ||
+ shdr->sh_addr == 0 || shdr->sh_size == 0) {
+ continue;
+ }
+
+ if (strtab) {
+ debug("%sing %s @ 0x%08lx (%ld bytes)\n",
+ (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
+ &strtab[shdr->sh_name],
+ (unsigned long)shdr->sh_addr,
+ (long)shdr->sh_size);
+ }
+
+ if (shdr->sh_type == SHT_NOBITS) {
+ memset((void *)(uintptr_t)shdr->sh_addr, 0,
+ shdr->sh_size);
+ } else {
+ image = (unsigned char *)addr + (ulong)shdr->sh_offset;
+ memcpy((void *)(uintptr_t)shdr->sh_addr,
+ (const void *)image, shdr->sh_size);
+ }
+ flush_cache((ulong)shdr->sh_addr, shdr->sh_size);
+ }
+
+ if((ehdr->e_machine == EM_PPC64) && (ehdr->e_flags &
EF_PPC64_ELFV1_ABI))
+ {
+ /*
+* For the 64-bit PowerPC ELF V1 ABI, e_entry is a function
descriptor
+* pointer with the first double word being the address of the entry
+* point of the function.
+*/
+ uintptr_t addr = ehdr->e_entry;
+ return *(Elf64_Addr *)addr;
+ }
+
return ehdr->e_entry;
}
@@ -107,7 +178,9 @@ static unsigned long load_elf_image_shdr(unsigned long addr)
int i; /* Loop counter */
ehdr = (Elf32_Ehdr *)addr;
-
+ if (ehdr->e_ident[EI_CLASS] == ELFCLASS64)
+ return load_elf64_image_shdr(addr);
+
/* Find the section header string table for output info */
shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
(ehdr->e_shstrndx * sizeof(Elf32_Shdr)));
diff --git a/include/elf.h b/include/elf.h
index 6802428..81f4019 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -593,6 +593,9 @@ unsigned long elf_hash(const unsigned char *name);
/* Values for Elf32/64_Ehdr.e_flags */
#define EF_PPC_EMB 0x8000 /* PowerPC embedded flag */
+#define EF_PPC64_ELFV1_ABI 0x0001
+#define EF_PPC64_ELFV2_ABI 0x0002
+
/* Cygnus local bits below */
#define EF_PPC_RELOCATABLE 0x0001 /* PowerPC -mrelocatable flag*/
#define EF_PPC_RELOCATABLE_LIB 0x8000 /* PowerPC -mrelocatable-lib
--
1.8.3.1
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Re: [U-Boot] [PATCH 2/3] scsi: ceva: add ls1043a soc support
-Original Message-
From: York Sun
Sent: 2018年8月1日 1:38
To: Peng Ma
Cc: albert.u.b...@aribaud.net; Mingkai Hu ; Pankaj Bansal
; Fabio Estevam ; Yinbo Zhu
; s...@chromium.org; bmeng...@gmail.com;
michal.si...@xilinx.com; Andy Tang ; u-boot@lists.denx.de
Subject: Re: [PATCH 2/3] scsi: ceva: add ls1043a soc support
On 07/09/2018 03:42 AM, peng...@nxp.com wrote:
> From: Peng Ma
>
> Add ahci compatible support for ls1043a soc.
>
> Signed-off-by: Peng Ma
> ---
> depend on:
> patchwork.ozlabs.org/patch/924896/
>
> drivers/ata/sata_ceva.c | 16 +---
> 1 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index
> 4c9ebe4..39269fe 100644
> --- a/drivers/ata/sata_ceva.c
> +++ b/drivers/ata/sata_ceva.c
> @@ -7,7 +7,6 @@
> #include
> #include
> #include
> -#include
>
> #include
>
> @@ -90,6 +89,7 @@
> enum ceva_soc {
> CEVA_1V84,
> CEVA_LS1012A,
> + CEVA_LS1043A,
> };
>
> struct ceva_sata_priv {
> @@ -98,6 +98,13 @@ struct ceva_sata_priv {
> ulong flag;
> };
>
> +static const struct udevice_id sata_ceva_ids[] = {
> + { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
> + { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
> + { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
> + { }
> +};
> +
> static int ceva_init_sata(struct ceva_sata_priv *priv) {
> ulong base = priv->base;
> @@ -116,6 +123,7 @@ static int ceva_init_sata(struct ceva_sata_priv *priv)
> break;
>
> case CEVA_LS1012A:
> + case CEVA_LS1043A:
> writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
> writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
> writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); @@ -143,12 +151,6
> @@
> static int sata_ceva_probe(struct udevice *dev)
> return ahci_probe_scsi(dev, priv->base); }
>
> -static const struct udevice_id sata_ceva_ids[] = {
> - { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
> - { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
> - { }
> -};
> -
Why do you move this structure?
York
Replay:
In our internal review, you suggested to me that compatible should put before,
so I did that.
Best regards
Peng Ma.
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Re: [U-Boot] boot a bios/uefi with x86_64, without grub
On Wed, Aug 1, 2018 at 2:32 AM, Thierry Gayet wrote: > hi bin, > > Thanks for your reply. > > Yes, you are totaly right because my uboot efi app didn't start due to my > architecture x86_64. > > Then i have try with a uboot efi payload (x86_64) and it start from efi > shell. > > I have tested with an usbkey using an EFI vfat partition formated as a vfat. > After that i have copyied my several filles from uboot efi payload x86_64 > and it start manually, not automatically. I don't know how to let it start > automaticaly ? any idea ? > I don't quite understand what you were doing. Please include some details. > Do you know what kind of issue there is on the uboot efi payload version ? > > Thanks in advance of you're reply. > Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] xyz-modem: Change getc timeout loop waiting
Hello!
On Mon, 21 Nov 2016 10:18:51 +0200
Tomas Melin wrote:
> This fixes the loop delay when using a hw watchdog.
>
> In case a watchdog is used that accesses CPU registers,
> the defined delay of 20us in a tight loop will cause a
> huge delay in the actual timeout seen. This is caused
> by the fact that udelay will inheritantly call WATCHDOG_RESET.
> Together with the omap wdt implementation, the seen timeout increases up to
> around 30s. This makes the loop very slow and causes long
> delays when using the modem.
>
> Instead, implement the 2 sec loop by using the timer interface to know
> when to break out of the timeout loop. Watchdog kicking is taken care of
> by getc().
>
> Signed-off-by: Tomas Melin
This commit breaks YMODEM SPL->U-Boot boot on Beagle Bone,
transfer is aborted (because of timeout) after 497kb
(u-boot.img is around 570kb).
Reverting the commit repairs YMODEM boot.
> ---
> common/xyzModem.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/common/xyzModem.c b/common/xyzModem.c
> index 5656aac..e0d87db 100644
> --- a/common/xyzModem.c
> +++ b/common/xyzModem.c
> @@ -71,12 +71,12 @@ typedef int cyg_int32;
> static int
> CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c)
> {
> -#define DELAY 20
> - unsigned long counter = 0;
> - while (!tstc () && (counter < xyzModem_CHAR_TIMEOUT * 1000 / DELAY))
> +
> + ulong now = get_timer(0);
> + while (!tstc ())
> {
> - udelay (DELAY);
> - counter++;
> + if (get_timer(now) > xyzModem_CHAR_TIMEOUT)
> +break;
> }
>if (tstc ())
> {
--
Alexander Sverdlin.
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[U-Boot] [PATCH 1/1] arm: zynq: Fix device tree for Avnet Picozed boards
This change adds the necessary /chosen/stdout-path to the device tree
for the Avnet Picozed boards. This node is mandatory for the SPL. Without
it the board resets in a loop without any output. The change also adds
the USB, QSPI and Ethernet MAC nodes of the corresponding devices present
on the board.
Signed-off-by: Andreas Galauner
---
arch/arm/dts/zynq-picozed.dts | 40 +--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynq-picozed.dts b/arch/arm/dts/zynq-picozed.dts
index dea6a422c3..db5bb8a6fe 100644
--- a/arch/arm/dts/zynq-picozed.dts
+++ b/arch/arm/dts/zynq-picozed.dts
@@ -14,13 +14,33 @@
aliases {
serial0 = &uart1;
spi0 = &qspi;
- mmc0 = &sdhci1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
};
memory@0 {
device_type = "memory";
reg = <0 0x4000>;
};
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <>;
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+ status = "okay";
};
&uart1 {
@@ -28,7 +48,17 @@
status = "okay";
};
-&qspi {
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
};
@@ -37,3 +67,9 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
--
2.18.0
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Re: [U-Boot] [PATCH] .travis.yml: Exclude openrd platforms
On Tue, Jul 31, 2018 at 07:56:38PM -0400, Tom Rini wrote: > The openrd platforms are currently orphaned, and are constantly on-edge > or overflowing their binary limit. Exclude them from travis for now. > > Cc: Vagrant Cascadian > Cc: Chris Packham > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] .travis.yml: Exclude kirkwood machines from the arm926ejs job
On Tue, Jul 31, 2018 at 02:49:22PM -0400, Tom Rini wrote: > We have a specific job for kirkwood platforms so exclude them from this > job. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ls1046ardb: Add qspi_spl variant to the MAINTAINERS file
On Tue, Jul 31, 2018 at 08:50:04AM -0400, Tom Rini wrote: > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] pico-pi: Add Otavio as maintainer
On Tue, Jul 31, 2018 at 08:49:33AM -0400, Tom Rini wrote: > Update the MAINTAINERS file to list Otavio Salvador as the maintainer > for this board. > > Cc: Otavio Salvador > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] dm: Fix CMD_DM enabling
On Tue, Jul 31, 2018 at 08:11:28AM +0200, Michal Simek wrote: > The patch "dm: Change CMD_DM enabling" > (sha1: 08a00cba06a7e608ae65e3d7ea225cf8c639429d) was incorrectly updated > and PICO_IMX7D is missing imply CMD_DM and WARP7 has it twice. > This patch is fixing it. > > Signed-off-by: Michal Simek Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] .travis.yml: Exclude openrd platforms
The openrd platforms are currently orphaned, and are constantly on-edge or overflowing their binary limit. Exclude them from travis for now. Cc: Vagrant Cascadian Cc: Chris Packham Signed-off-by: Tom Rini --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 9c53c4fe219d..d5862066570d 100644 --- a/.travis.yml +++ b/.travis.yml @@ -195,7 +195,7 @@ matrix: - BUILDMAN="sandbox x86" TOOLCHAIN="x86_64" - env: -- BUILDMAN="kirkwood" +- BUILDMAN="kirkwood -x openrd" - env: - BUILDMAN="mvebu" - env: -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] armv8: layerscape: Enable EHCI access for LS1012A
On 07/26/2018 07:38 PM, Ran Wang wrote: > Program Central Security Unit (CSU) to grant access > permission for USB 2.0 controller, otherwiase EHCI funciton will down. > > Signed-off-by: Ran Wang > --- > Change in v2: > - Add EL checking code to make sure related programming only happen > in EL3 > > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 + > arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 1 + > 2 files changed, 10 insertions(+) > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > index 6a56269..d8c3083 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > @@ -14,6 +14,7 @@ > #include > #include > #include > +#include Including this header has a problem. It declares and initializes ns_dev[], causing a compiling warning for soc.c. Please fix. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] efi_loader: don't allocate unusable RAM
On 31.07.18 22:20, Stephen Warren wrote: > On 07/31/2018 02:15 PM, Alexander Graf wrote: >> >> >>> Am 31.07.2018 um 22:04 schrieb Stephen Warren : >>> >>> On 07/31/2018 02:03 PM, Alexander Graf wrote: > Am 31.07.2018 um 21:44 schrieb Stephen Warren : > > From: Stephen Warren > > Some boards define a maximum usable RAM top that's more restrictive > than > the ranges defined by U-Boot's memory bank definitions[1]. In this > case, > the unusable RAM isn't mapped in the page tables, and so the EFI > code must > not attempt to allocate RAM from outside the usable regions. Fix > efi_find_free_memory() to detect when max_addr is unconstrained or > out of > range, and substitue a valid value. > > [1] For example, when some peripherals can't access RAM above 4GiB, > it's > simplest to force U-Boot's ram_top to a smaller value to avoid dealing > with this issue more explicitly. However, the RAM bank definitions > still > describe the unusable RAM so that the booted OS has access to it, > since > the OS can typically deal with such restrictions in a more complex > manner. That's what we have the efi bounce buffers for. Can't we just enable those for tegra? >>> >>> No, because that wouldn't help all the non-EFI code, or cause the RAM >>> to be mapped in the page tables due to the non-EFI code not needing it. >> >> The non-efi code can still rely on ram_top just fine, no? I was more >> thinking of enabling the bounce buffer config option as alternative to >> your patch. > > A lot more besides enabling that option would have to be done. The issue > here is that EFI is attempting to use RAM that's not in the page tables > and hence crashes. Enabling bounce buffers alone isn't going to help > that; we'd also have to rejig the U-Boot MMU code to set up page table > entries for the entire of the RAM banks rather than just the usable RAM, > and then we've have to develop some new way of preventing U-Boot from > mapping RAM that's part of the RAM banks but shouldn't be mapped because > e.g. it's part of the secure carveout that can't be mapped in the MMU in > order to ensure that the CPU never pre-fetches that RAM to avoid taking > security faults on the fetch. The fact that ram_top is lower than the > HW-defined RAM limit exists for reasons other than just preventing use > of RAM that some peripheral HW can't access, so bounce buffers will only > solve one of the causes, not everything. I see. The main problem I just see is exactly the rationale you described above: The EFI memory map will be used by the booted OS to indicate which regions are usable. If they really aren't, then we need to properly annotate that in the EFI memory map as well, because otherwise Linux may end up writing to carved out secure regions of RAM. Alex ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/8] armv8: ls1088a: fix sd boot config compile issue
On 07/17/2018 08:03 PM, Yinbo Zhu wrote:
> This patch is to fix sd boot config compile issue for ls1088a.
>
> Signed-off-by: Yinbo Zhu
> ---
> Change in v2:
> Changed this patch's order
>
> include/mmc.h |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/include/mmc.h b/include/mmc.h
> index 534c317..66e69b7 100644
> --- a/include/mmc.h
> +++ b/include/mmc.h
> @@ -604,7 +604,7 @@ struct mmc {
> u64 enh_user_start;
> u64 enh_user_size;
> #endif
> -#if !CONFIG_IS_ENABLED(BLK)
> +#if CONFIG_IS_ENABLED(BLK)
> struct blk_desc block_dev;
> #endif
> char op_cond_pending; /* 1 if we are waiting on an op_cond command */
>
NAK.
You can't simply reverse the logic. This code has been working for so
many platforms. Simply changing may fix your problem but definitely
breaks all others. Please find your root cause and fix properly.
York
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Re: [U-Boot] [PATCH] efi_loader: don't allocate unusable RAM
On 07/31/2018 02:15 PM, Alexander Graf wrote: Am 31.07.2018 um 22:04 schrieb Stephen Warren : On 07/31/2018 02:03 PM, Alexander Graf wrote: Am 31.07.2018 um 21:44 schrieb Stephen Warren : From: Stephen Warren Some boards define a maximum usable RAM top that's more restrictive than the ranges defined by U-Boot's memory bank definitions[1]. In this case, the unusable RAM isn't mapped in the page tables, and so the EFI code must not attempt to allocate RAM from outside the usable regions. Fix efi_find_free_memory() to detect when max_addr is unconstrained or out of range, and substitue a valid value. [1] For example, when some peripherals can't access RAM above 4GiB, it's simplest to force U-Boot's ram_top to a smaller value to avoid dealing with this issue more explicitly. However, the RAM bank definitions still describe the unusable RAM so that the booted OS has access to it, since the OS can typically deal with such restrictions in a more complex manner. That's what we have the efi bounce buffers for. Can't we just enable those for tegra? No, because that wouldn't help all the non-EFI code, or cause the RAM to be mapped in the page tables due to the non-EFI code not needing it. The non-efi code can still rely on ram_top just fine, no? I was more thinking of enabling the bounce buffer config option as alternative to your patch. A lot more besides enabling that option would have to be done. The issue here is that EFI is attempting to use RAM that's not in the page tables and hence crashes. Enabling bounce buffers alone isn't going to help that; we'd also have to rejig the U-Boot MMU code to set up page table entries for the entire of the RAM banks rather than just the usable RAM, and then we've have to develop some new way of preventing U-Boot from mapping RAM that's part of the RAM banks but shouldn't be mapped because e.g. it's part of the secure carveout that can't be mapped in the MMU in order to ensure that the CPU never pre-fetches that RAM to avoid taking security faults on the fetch. The fact that ram_top is lower than the HW-defined RAM limit exists for reasons other than just preventing use of RAM that some peripheral HW can't access, so bounce buffers will only solve one of the causes, not everything. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] efi_loader: don't allocate unusable RAM
> Am 31.07.2018 um 22:04 schrieb Stephen Warren : > > On 07/31/2018 02:03 PM, Alexander Graf wrote: >>> Am 31.07.2018 um 21:44 schrieb Stephen Warren : >>> >>> From: Stephen Warren >>> >>> Some boards define a maximum usable RAM top that's more restrictive than >>> the ranges defined by U-Boot's memory bank definitions[1]. In this case, >>> the unusable RAM isn't mapped in the page tables, and so the EFI code must >>> not attempt to allocate RAM from outside the usable regions. Fix >>> efi_find_free_memory() to detect when max_addr is unconstrained or out of >>> range, and substitue a valid value. >>> >>> [1] For example, when some peripherals can't access RAM above 4GiB, it's >>> simplest to force U-Boot's ram_top to a smaller value to avoid dealing >>> with this issue more explicitly. However, the RAM bank definitions still >>> describe the unusable RAM so that the booted OS has access to it, since >>> the OS can typically deal with such restrictions in a more complex >>> manner. >> That's what we have the efi bounce buffers for. Can't we just enable those >> for tegra? > > No, because that wouldn't help all the non-EFI code, or cause the RAM to be > mapped in the page tables due to the non-EFI code not needing it. The non-efi code can still rely on ram_top just fine, no? I was more thinking of enabling the bounce buffer config option as alternative to your patch. Alex ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] efi_loader: don't allocate unusable RAM
On 07/31/2018 02:03 PM, Alexander Graf wrote: Am 31.07.2018 um 21:44 schrieb Stephen Warren : From: Stephen Warren Some boards define a maximum usable RAM top that's more restrictive than the ranges defined by U-Boot's memory bank definitions[1]. In this case, the unusable RAM isn't mapped in the page tables, and so the EFI code must not attempt to allocate RAM from outside the usable regions. Fix efi_find_free_memory() to detect when max_addr is unconstrained or out of range, and substitue a valid value. [1] For example, when some peripherals can't access RAM above 4GiB, it's simplest to force U-Boot's ram_top to a smaller value to avoid dealing with this issue more explicitly. However, the RAM bank definitions still describe the unusable RAM so that the booted OS has access to it, since the OS can typically deal with such restrictions in a more complex manner. That's what we have the efi bounce buffers for. Can't we just enable those for tegra? No, because that wouldn't help all the non-EFI code, or cause the RAM to be mapped in the page tables due to the non-EFI code not needing it. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] efi_loader: don't allocate unusable RAM
> Am 31.07.2018 um 21:44 schrieb Stephen Warren :
>
> From: Stephen Warren
>
> Some boards define a maximum usable RAM top that's more restrictive than
> the ranges defined by U-Boot's memory bank definitions[1]. In this case,
> the unusable RAM isn't mapped in the page tables, and so the EFI code must
> not attempt to allocate RAM from outside the usable regions. Fix
> efi_find_free_memory() to detect when max_addr is unconstrained or out of
> range, and substitue a valid value.
>
> [1] For example, when some peripherals can't access RAM above 4GiB, it's
> simplest to force U-Boot's ram_top to a smaller value to avoid dealing
> with this issue more explicitly. However, the RAM bank definitions still
> describe the unusable RAM so that the booted OS has access to it, since
> the OS can typically deal with such restrictions in a more complex
> manner.
That's what we have the efi bounce buffers for. Can't we just enable those for
tegra?
Alex
>
> Fixes: aa909462d018 "efi_loader: efi_allocate_pages is too restrictive"
> Cc: Heinrich Schuchardt
> Cc: Alexander Graf
> Signed-off-by: Stephen Warren
> ---
> lib/efi_loader/efi_memory.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
> index 967c3f733e4c..5064ff2ccbe8 100644
> --- a/lib/efi_loader/efi_memory.c
> +++ b/lib/efi_loader/efi_memory.c
> @@ -251,6 +251,9 @@ static uint64_t efi_find_free_memory(uint64_t len,
> uint64_t max_addr)
> {
>struct list_head *lhandle;
>
> +if ((max_addr == -1ULL) || (max_addr > gd->ram_top))
> +max_addr = gd->ram_top;
> +
>list_for_each(lhandle, &efi_mem) {
>struct efi_mem_list *lmem = list_entry(lhandle,
>struct efi_mem_list, link);
> --
> 2.18.0
>
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Re: [U-Boot] [PATCH v5 00/27] SPI-NAND support
On Tue, 31 Jul 2018 21:25:53 +0200 Boris Brezillon wrote: > Hi Jagan, > > On Tue, 31 Jul 2018 20:03:47 +0530 > Jagan Teki wrote: > > > > Applied to u-boot-spi/master > > > > Look like we have some build issues [1]? > > Yep, I reproduced the issue. Looks like u-boot Makefile hierarchy is a > bit different from Linux one, and patch is breaking raw/parallel NAND > build. I fixed it up (see below diff). This diff should be merged in > patch 9, and you'll have to fix a few conflicts when rebasing. Here is > a branch [1] containing this fixup commit (placed just after the > offending one) in case you want to check the end result. > New diff, this time with all tree-wide s/drivers\/mtd\/nand/drivers\/mtd\/nand\/raw/ My branch has been updated accordingly. --->8--- diff --git a/MAINTAINERS b/MAINTAINERS index fe8423530c10..db3db2ec8a43 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -281,7 +281,7 @@ F: drivers/i2c/i2c-cdns.c F: drivers/i2c/muxes/pca954x.c F: drivers/i2c/zynq_i2c.c F: drivers/mmc/zynq_sdhci.c -F: drivers/mtd/nand/zynq_nand.c +F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c F: drivers/serial/serial_zynq.c @@ -305,7 +305,7 @@ F: drivers/i2c/i2c-cdns.c F: drivers/i2c/muxes/pca954x.c F: drivers/i2c/zynq_i2c.c F: drivers/mmc/zynq_sdhci.c -F: drivers/mtd/nand/zynq_nand.c +F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c F: drivers/serial/serial_zynq.c @@ -441,7 +441,7 @@ NAND FLASH #M:Scott Wood S: Orphaned (Since 2018-07) T: git git://git.denx.de/u-boot-nand-flash.git -F: drivers/mtd/nand/ +F: drivers/mtd/nand/raw/ NDS32 M: Macpaul Lin diff --git a/Makefile b/Makefile index 884b7d943cf7..a38146003d77 100644 --- a/Makefile +++ b/Makefile @@ -685,7 +685,7 @@ libs-y += drivers/dma/ libs-y += drivers/gpio/ libs-y += drivers/i2c/ libs-y += drivers/mtd/ -libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/ +libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/raw/ libs-y += drivers/mtd/onenand/ libs-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/ libs-y += drivers/mtd/spi/ diff --git a/README b/README index aee0f7371c42..fd5034ce91f2 100644 --- a/README +++ b/README @@ -3264,8 +3264,8 @@ Low Level (hardware related) configuration options: a 16 bit bus. Not all NAND drivers use this symbol. Example of drivers that use it: - - drivers/mtd/nand/ndfc.c - - drivers/mtd/nand/mxc_nand.c + - drivers/mtd/nand/raw/ndfc.c + - drivers/mtd/nand/raw/mxc_nand.c - CONFIG_SYS_NDFC_EBC0_CFG Sets the EBC0_CFG register for the NDFC. If not defined @@ -3382,7 +3382,7 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_NAND_NO_SUBPAGE_WRITE Option to disable subpage write in NAND driver driver that uses this: - drivers/mtd/nand/davinci_nand.c + drivers/mtd/nand/raw/davinci_nand.c Freescale QE/FMAN Firmware Support: --- diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 8ffb9a8d3c2c..1b871c62ced2 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -12,7 +12,7 @@ #include #include #include -#include <../drivers/mtd/nand/denali.h> +#include <../drivers/mtd/nand/raw/denali.h> #include "init.h" diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2af26a881af0..7bf7a2354221 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -479,7 +479,7 @@ config SPL_NAND_SUPPORT help Enable support for NAND (Negative AND) flash in SPL. NAND flash can be used to allow SPL to load U-Boot from supported devices. - This enables the drivers in drivers/mtd/nand as part of an SPL + This enables the drivers in drivers/mtd/nand/raw as part of an SPL build. config SPL_NET_SUPPORT diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index ba60a3a3c505..0016d4973905 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -2,7 +2,7 @@ /* * Copyright (C) 2011 OMICRON electronics GmbH * - * based on drivers/mtd/nand/nand_spl_load.c + * based on drivers/mtd/nand/raw/nand_spl_load.c * * Copyright (C) 2011 * Heiko Schocher, DENX Software Engineering, h...@denx.de. diff --git a/doc/README.SPL b/doc/README.SPL index 3ba313caa8f7..fc1ca1ad4f51 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -57,11 +57,11 @@ CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o) CONFIG_SPL_EXT_SUPPORT CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o) CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o) -CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o) +CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/raw/libnand.o) CONFIG_SPL_DRIVERS_MISC_SUPPORT (drivers/misc
[U-Boot] [PATCH] efi_loader: don't allocate unusable RAM
From: Stephen Warren
Some boards define a maximum usable RAM top that's more restrictive than
the ranges defined by U-Boot's memory bank definitions[1]. In this case,
the unusable RAM isn't mapped in the page tables, and so the EFI code must
not attempt to allocate RAM from outside the usable regions. Fix
efi_find_free_memory() to detect when max_addr is unconstrained or out of
range, and substitue a valid value.
[1] For example, when some peripherals can't access RAM above 4GiB, it's
simplest to force U-Boot's ram_top to a smaller value to avoid dealing
with this issue more explicitly. However, the RAM bank definitions still
describe the unusable RAM so that the booted OS has access to it, since
the OS can typically deal with such restrictions in a more complex
manner.
Fixes: aa909462d018 "efi_loader: efi_allocate_pages is too restrictive"
Cc: Heinrich Schuchardt
Cc: Alexander Graf
Signed-off-by: Stephen Warren
---
lib/efi_loader/efi_memory.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 967c3f733e4c..5064ff2ccbe8 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -251,6 +251,9 @@ static uint64_t efi_find_free_memory(uint64_t len, uint64_t
max_addr)
{
struct list_head *lhandle;
+ if ((max_addr == -1ULL) || (max_addr > gd->ram_top))
+ max_addr = gd->ram_top;
+
list_for_each(lhandle, &efi_mem) {
struct efi_mem_list *lmem = list_entry(lhandle,
struct efi_mem_list, link);
--
2.18.0
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Re: [U-Boot] [PATCH v5 00/27] SPI-NAND support
Hi Jagan, On Tue, 31 Jul 2018 20:03:47 +0530 Jagan Teki wrote: > > Applied to u-boot-spi/master > > Look like we have some build issues [1]? Yep, I reproduced the issue. Looks like u-boot Makefile hierarchy is a bit different from Linux one, and patch is breaking raw/parallel NAND build. I fixed it up (see below diff). This diff should be merged in patch 9, and you'll have to fix a few conflicts when rebasing. Here is a branch [1] containing this fixup commit (placed just after the offending one) in case you want to check the end result. Regards, Boris [1]https://github.com/bbrezillon/u-boot/commits/wip-spi --->8--- diff --git a/Makefile b/Makefile index 884b7d943cf7..a38146003d77 100644 --- a/Makefile +++ b/Makefile @@ -685,7 +685,7 @@ libs-y += drivers/dma/ libs-y += drivers/gpio/ libs-y += drivers/i2c/ libs-y += drivers/mtd/ -libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/ +libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/raw/ libs-y += drivers/mtd/onenand/ libs-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/ libs-y += drivers/mtd/spi/ diff --git a/drivers/Makefile b/drivers/Makefile index 276e5ee4d7ee..ccd1b648d058 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/ obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/ obj-$(CONFIG_$(SPL_TPL_)LED) += led/ obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += mmc/ -obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += mtd/nand/ +obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += mtd/nand/raw/ obj-$(CONFIG_$(SPL_TPL_)PHY) += phy/ obj-$(CONFIG_$(SPL_TPL_)PINCTRL) += pinctrl/ obj-$(CONFIG_$(SPL_TPL_)RAM) += ram/ diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 8b2d0e118d1c..69f40d15635d 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -1,3 +1,2 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_MTD_NAND) += raw/ ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Regression due to "efi_loader: efi_allocate_pages is too restrictive"
Commit aa909462d018 "efi_loader: efi_allocate_pages is too restrictive" causes a failure (synchronous abort) in the command "dhcp zImage" on board p2371-2180 (Jetson TX1). Reverting this commit alone solves the problem. According to the exception dump, elr/pc is in efi_allocate_pages(), which makes sense given the content of the patch. Do you have any ideas? Thanks. Failure log: U-Boot 2018.07-00378-gaa909462d018 (Jul 31 2018 - 13:06:57 -0600) TEGRA210 Model: NVIDIA P2371-2180 Board: NVIDIA P2371-2180 DRAM: 3.5 GiB MMC: sdhci@700b: 1, sdhci@700b0600: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment Failed (-5) In:serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Tegra210 (P2371-2180) # pci enum Tegra210 (P2371-2180) # dhcp zImage Warning: eth_rtl8169 using MAC address from ROM BOOTP broadcast 1 DHCP client bound to address 10.20.204.52 (2 ms) Using eth_rtl8169 device TFTP from server 10.20.204.51; our IP address is 10.20.204.52 Filename 'zImage'. Load address: 0x8008 Loading: "Synchronous Abort" handler, esr 0x9644 elr: 8015a8b0 lr : 8015a8a8 (reloc) elr: dff6f8b0 lr : dff6f8a8 x0 : x1 : 00017000 x2 : dda2dc20 x3 : 8000 x4 : x5 : x6 : 0015 x7 : dda1cf58 x8 : dda36030 x9 : 0008 x10: x11: dda1c774 x12: x13: dda1c768 x14: 0004 x15: x16: 2080 x17: 0001 x18: dda22dd0 x19: 0001 x20: dda1d048 x21: dff8dcae x22: dff97823 x23: dff9c000 x24: dffed000 x25: dffed5b4 x26: x27: dffef000 x28: dffef000 x29: dda1cff0 Resetting CPU ... ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] .travis.yml: Exclude kirkwood machines from the arm926ejs job
We have a specific job for kirkwood platforms so exclude them from this job. Signed-off-by: Tom Rini --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 7b0eb6e4f6b5..9c53c4fe219d 100644 --- a/.travis.yml +++ b/.travis.yml @@ -153,7 +153,7 @@ matrix: - BUILDMAN="arm11 arm7 arm920t arm946es" - env: - JOB="arm926ejs" - BUILDMAN="arm926ejs -x mx,siemens,atmel" + BUILDMAN="arm926ejs -x mx,siemens,atmel,kirkwood" - env: - BUILDMAN="atmel" - env: -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] openrd: Mark as Orphaned
After talking with Albert, mark these boards as orphaned as he no longer has one. Cc: Albert ARIBAUD Cc: Vagrant Cascadian Cc: Chris Packham Signed-off-by: Tom Rini --- board/Marvell/openrd/MAINTAINERS | 10 +++--- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/board/Marvell/openrd/MAINTAINERS b/board/Marvell/openrd/MAINTAINERS index 3789a04c8917..b24fff0a783e 100644 --- a/board/Marvell/openrd/MAINTAINERS +++ b/board/Marvell/openrd/MAINTAINERS @@ -1,12 +1,8 @@ -OPENRD BOARD -M: Albert ARIBAUD -S: Maintained +OPENRD / OPENRD_CLIENT BOARD +#M:Albert ARIBAUD +S: Orphaned (Since 2018-09) F: board/Marvell/openrd/ F: include/configs/openrd.h F: configs/openrd_base_defconfig - -OPENRD_CLIENT BOARD -M: Albert ARIBAUD -S: Maintained F: configs/openrd_client_defconfig F: configs/openrd_ultimate_defconfig -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARM: tegra: avoid more operations in non-secure world
From: Stephen Warren
A secure monitor that runs before U-Boot, and hence causes U-Boot to run
in non-secure world, must implement a few operations that U-Boot
otherwise implements when running in secure world. Fix U-Boot to skip
these operations when running in non-secure world. In particular:
- The secure monitor must provide the LP0 resume code and own LP0
configuration in order to maintain security, so must initialize all
the PMC scratch registers used by the boot ROM during LP0 resume.
Consequently, U-Boot should not attempt to clear those registers,
since the register accesses will fail or cause an error.
- The secure monitor owns system security, and so is responsible for
configuring security-related items such as the VPR.
Signed-off-by: Stephen Warren
---
arch/arm/mach-tegra/ap.c | 9 +++--
arch/arm/mach-tegra/gpu.c | 18 --
2 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c
index bf8001d9db09..84c20a48ad4d 100644
--- a/arch/arm/mach-tegra/ap.c
+++ b/arch/arm/mach-tegra/ap.c
@@ -155,8 +155,13 @@ static void init_pmc_scratch(void)
int i;
/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
- for (i = 0; i < 23; i++)
- writel(0, &pmc->pmc_scratch1+i);
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+ if (!tegra_cpu_is_non_secure())
+#endif
+ {
+ for (i = 0; i < 23; i++)
+ writel(0, &pmc->pmc_scratch1 + i);
+ }
/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
odmdata = get_odmdata();
diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c
index 2e203f735bf3..e047f678211d 100644
--- a/arch/arm/mach-tegra/gpu.c
+++ b/arch/arm/mach-tegra/gpu.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
@@ -18,12 +19,17 @@ void tegra_gpu_config(void)
{
struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
- /* Turn VPR off */
- writel(0, &mc->mc_video_protect_size_mb);
- writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
- &mc->mc_video_protect_reg_ctrl);
- /* read back to ensure the write went through */
- readl(&mc->mc_video_protect_reg_ctrl);
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+ if (!tegra_cpu_is_non_secure())
+#endif
+ {
+ /* Turn VPR off */
+ writel(0, &mc->mc_video_protect_size_mb);
+ writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
+ &mc->mc_video_protect_reg_ctrl);
+ /* read back to ensure the write went through */
+ readl(&mc->mc_video_protect_reg_ctrl);
+ }
debug("configured VPR\n");
--
2.18.0
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[U-Boot] [PATCH] ARM: tegra: align carveout size
From: Stephen Warren Align the size of the carveout region to 2M. This ensures that the size can be accurately represented by an LPAE page table that uses sections. This solves a bug (hang at boot time soon after printing the DRAM size) that only shows up when the following two commits are merged together: d32e86bde8a3 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported 6e584e633d10 ARM: tegra: avoid using secure carveout RAM Cc: Mark Kettenis Cc: Alexander Graf Signed-off-by: Stephen Warren --- This should be applied quickly since it fixes a regression that causes all boots to fail, which in turn causes test/py to reset and "reflash" the target board for each test, which causes the test to take eons. arch/arm/mach-tegra/board2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 5ecadf705e7e..421a71b3014d 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -252,7 +252,7 @@ static ulong carveout_size(void) #elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE) // BASE+SIZE might not == 4GB. If so, we want the carveout to cover // from BASE to 4GB, not BASE to BASE+SIZE. - return (0 - CONFIG_ARMV7_SECURE_BASE); + return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1); #else return 0; #endif -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Pull request: u-boot-sunxi/master
Hi Tom, Please pull this PR. thanks, Jagan. The following changes since commit 5a0007d481c0fcd2d422dd48b2a129dd8e8a272a: Prepare v2017.09-rc1 (2018-07-30 21:47:29 -0400) are available in the Git repository at: git://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to 89a897fc4d78e31332e5899e977d8bf3c82abafa: board: sun50i: h6: Add OrangePi One Plus initial support (2018-07-31 20:50:01 +0530) Icenowy Zheng (14): sunxi: change SUNXI_HIGH_SRAM option to SUNXI_SRAM_ADDRESS sunxi: add basic memory map definitions of H6 SoC sunxi: change RMR64's RVBAR address for H6 sunxi: change ATF position for H6 sunxi: add config for SPL at 0x2 on H6 sunxi: change GIC address on H6 sunxi: add clock code for H6 sunxi: use sun6i-style watchdog for H6 sunxi: add UART0 setup for H6 sunxi: add MMC support for H6 sunxi: add DRAM support to H6 sunxi: add support for Allwinner H6 SoC sunxi: add support for Pine H64 board video: sunxi: de2: fix SimpleFB node creation when DE2 not probed Jagan Teki (5): phy: sun4i-usb: Call phy_passby even for PHY#0 phy: sun4i-usb: Remove usb_clk_cfg set in probe phy: sun4i-usb: Update PHY#3 rst_mask only for H3_H5 configs: sunxi: Drop CONFIG_SUNXI_USB_PHYS board: sun50i: h6: Add OrangePi One Plus initial support Mylène Josserand (2): mtd: nand: nand_base: Convert EINVAL into ENOTSUPP mtd: nand: sunxi: Return on set_feature only when not ENOTSUPP Simon Baatz (1): sunxi: enable SATA on Banana Pi M2 Berry arch/arm/dts/Makefile | 3 + arch/arm/dts/sun50i-h6-orangepi-one-plus.dts | 150 + arch/arm/dts/sun50i-h6-pine-h64.dts | 185 ++ arch/arm/dts/sun50i-h6.dtsi | 288 + arch/arm/include/asm/arch-sunxi/boot0.h | 4 + arch/arm/include/asm/arch-sunxi/clock.h | 2 + arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 320 + arch/arm/include/asm/arch-sunxi/cpu.h | 2 + arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 73 +++ arch/arm/include/asm/arch-sunxi/dram.h| 2 + arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h | 297 + arch/arm/include/asm/arch-sunxi/gpio.h| 1 + arch/arm/include/asm/arch-sunxi/mmc.h | 2 +- arch/arm/include/asm/arch-sunxi/spl.h | 6 +- arch/arm/include/asm/arch-sunxi/timer.h | 2 +- arch/arm/mach-sunxi/Kconfig | 37 +- arch/arm/mach-sunxi/Makefile | 2 + arch/arm/mach-sunxi/board.c | 6 +- arch/arm/mach-sunxi/clock_sun50i_h6.c | 94 +++ arch/arm/mach-sunxi/cpu_info.c| 2 + arch/arm/mach-sunxi/dram_sun50i_h6.c | 755 ++ arch/arm/mach-sunxi/rmr_switch.S | 6 + board/sunxi/MAINTAINERS | 10 + board/sunxi/board.c | 7 + board/sunxi/mksunxi_fit_atf.sh| 10 +- common/spl/Kconfig| 2 +- configs/bananapi_m2_berry_defconfig | 3 + configs/orangepi_one_plus_defconfig | 14 + configs/pine_h64_defconfig| 15 + drivers/mmc/sunxi_mmc.c | 13 +- drivers/mtd/nand/nand_base.c | 4 +- drivers/mtd/nand/sunxi_nand.c | 2 +- drivers/phy/allwinner/phy-sun4i-usb.c | 10 +- drivers/video/sunxi/sunxi_de2.c | 3 + include/configs/sun4i.h | 2 - include/configs/sun50i.h | 7 +- include/configs/sun5i.h | 2 - include/configs/sun6i.h | 2 - include/configs/sun7i.h | 2 - include/configs/sun8i.h | 10 - include/configs/sunxi-common.h| 24 +- include/dt-bindings/clock/sun50i-h6-ccu.h | 125 include/dt-bindings/clock/sun50i-h6-r-ccu.h | 24 + include/dt-bindings/reset/sun50i-h6-ccu.h | 73 +++ include/dt-bindings/reset/sun50i-h6-r-ccu.h | 17 + scripts/config_whitelist.txt | 1 - 46 files changed, 2560 insertions(+), 61 deletions(-) create mode 100644 arch/arm/dts/sun50i-h6-orangepi-one-plus.dts create mode 100644 arch/arm/dts/sun50i-h6-pine-h64.dts create mode 100644 arch/arm/dts/sun50i-h6.dtsi create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h create mode 100644 arch/arm/mach-sunxi/clock_sun50i_h6.c create mode 100644 arch/arm/mach-sunxi/dram_sun50i_
Re: [U-Boot] [PATCH v1 9/9] ARM: Odroid XU3: Modify Odroid XU3 config to boot by default from SD card
Hi Lukasz, On 27 July 2018 at 15:26, Lukasz Majewski wrote: > On Fri, 27 Jul 2018 14:42:32 +0530 > Anand Moon wrote: > >> Hi Lukasz, >> >> On 27 July 2018 at 13:54, Lukasz Majewski wrote: >> > On Fri, 27 Jul 2018 08:34:15 +0530 >> > Anand Moon wrote: >> > >> >> Hi Lukasz, >> >> >> >> On 26 July 2018 at 21:23, Lukasz Majewski wrote: >> >> > Hi Anand, >> >> > >> >> >> Hi Lukasz, >> >> >> >> >> >> On 26 July 2018 at 03:55, Lukasz Majewski >> >> >> wrote: >> >> >> > This commit allows by default booting Odroid XU3 from the SD >> >> >> > card (when e.g. eMMC module is not present). >> >> >> > >> >> >> > Signed-off-by: Lukasz Majewski >> >> >> > >> >> >> > --- >> >> >> > >> >> >> > include/configs/odroid_xu3.h | 7 +-- >> >> >> > 1 file changed, 5 insertions(+), 2 deletions(-) >> >> >> > >> >> >> > diff --git a/include/configs/odroid_xu3.h >> >> >> > b/include/configs/odroid_xu3.h index >> >> >> > f495f6219ba9..818a06515cb2 100644 --- >> >> >> > a/include/configs/odroid_xu3.h +++ >> >> >> > b/include/configs/odroid_xu3.h @@ -94,6 +94,9 @@ >> >> >> > #undef CONFIG_SYS_BOARD >> >> >> > #define CONFIG_SYS_BOARD "odroid" >> >> >> > >> >> >> > +#undef CONFIG_SYS_MMC_ENV_DEV >> >> >> > +#define CONFIG_SYS_MMC_ENV_DEV 2 >> >> >> > + >> >> >> > /* Define new extra env settings, including DFU settings */ >> >> >> > #undef CONFIG_EXTRA_ENV_SETTINGS >> >> >> > #define CONFIG_EXTRA_ENV_SETTINGS \ >> >> >> > @@ -105,8 +108,8 @@ >> >> >> > "console=" CONFIG_DEFAULT_CONSOLE "\0"\ >> >> >> > "fdtfile=exynos5422-odroidxu3.dtb\0" \ >> >> >> > "boardname=odroidxu3\0" \ >> >> >> > - "mmcbootdev=0\0" \ >> >> >> > - "mmcrootdev=0\0" \ >> >> >> > + "mmcbootdev=2\0" \ >> >> >> > + "mmcrootdev=1\0" \ >> >> >> > "mmcbootpart=1\0" \ >> >> >> > "mmcrootpart=2\0" \ >> >> >> > "dfu_alt_system="CONFIG_DFU_ALT_SYSTEM \ >> >> >> > -- >> >> >> > 2.11.0 >> >> >> > >> >> >> >> >> >> This changes probably breaks the booting from eMMC on >> >> >> Odroid-XU4 >> >> > >> >> > I suppose, that XU4 is also equipped with SD card slot as XU3. >> >> > >> >> > Nonetheless, as I don't have eMMC card for mine XU3, the only >> >> > way to boot my device is SD card. >> >> > >> >> > If you believe that this may be a problem, then I can drop this >> >> > patch. >> >> > >> >> > Have you checked patches from 1-8? >> >> > Does it work for you? If yes, please send tested-by tag. >> >> > >> >> >> >> Yes you probably need to drop this patch, >> >> I had some tough time recovering my eMMC back to flash new u-boot. >> >> >> >> I have tested my eMMC with default boot.scr its boot good. >> >> Need to modify the boot.scr to boot into SD card. >> > >> > SD card has different layout than eMMC. >> > >> > Despite above - you just shall need to apply patch 9/9 to get the >> > board running from SD card. >> > >> >> Actually SD card are easy to modify and tune with just adding >> setenv mmcrootdev "1" to autoboot.cmd from sdcard. >> >> but with eMMC module it's bit difficult to make this work, > > Ach Ok, I see > > The problem is when you have both attached - the eMMC and SD card. > > In that case I always thought that one shall boot from eMMC and the SD > card shall be used as an extra storage space. > > Also, please keep in mind that IIRC the ROM first tries to boot from > eMMC, so you need BL1, u-boot placed there if it is present. > Can we create a different board initialization file to fine tune the odroid xu3 platform. for example Odroid U3 has # board/samsung/odroid/odroid.c where we can initialize for Odroid XU3 platform boards with following features. board_clock_init board_gpio_init exynos_power_init board_usb_init board_leds Best Regards -Anand ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] pico-pi: Add Otavio as maintainer
On Tue, Jul 31, 2018 at 9:49 AM, Tom Rini wrote: > Update the MAINTAINERS file to list Otavio Salvador as the maintainer > for this board. > > Cc: Otavio Salvador > Signed-off-by: Tom Rini Acked-by: Otavio Salvador -- Otavio Salvador O.S. Systems http://www.ossystems.com.brhttp://code.ossystems.com.br Mobile: +55 (53) 9 9981-7854 Mobile: +1 (347) 903-9750 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] scsi: ceva: add ls1043a soc support
On 07/09/2018 03:42 AM, peng...@nxp.com wrote:
> From: Peng Ma
>
> Add ahci compatible support for ls1043a soc.
>
> Signed-off-by: Peng Ma
> ---
> depend on:
> patchwork.ozlabs.org/patch/924896/
>
> drivers/ata/sata_ceva.c | 16 +---
> 1 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
> index 4c9ebe4..39269fe 100644
> --- a/drivers/ata/sata_ceva.c
> +++ b/drivers/ata/sata_ceva.c
> @@ -7,7 +7,6 @@
> #include
> #include
> #include
> -#include
>
> #include
>
> @@ -90,6 +89,7 @@
> enum ceva_soc {
> CEVA_1V84,
> CEVA_LS1012A,
> + CEVA_LS1043A,
> };
>
> struct ceva_sata_priv {
> @@ -98,6 +98,13 @@ struct ceva_sata_priv {
> ulong flag;
> };
>
> +static const struct udevice_id sata_ceva_ids[] = {
> + { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
> + { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
> + { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
> + { }
> +};
> +
> static int ceva_init_sata(struct ceva_sata_priv *priv)
> {
> ulong base = priv->base;
> @@ -116,6 +123,7 @@ static int ceva_init_sata(struct ceva_sata_priv *priv)
> break;
>
> case CEVA_LS1012A:
> + case CEVA_LS1043A:
> writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
> writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
> writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
> @@ -143,12 +151,6 @@ static int sata_ceva_probe(struct udevice *dev)
> return ahci_probe_scsi(dev, priv->base);
> }
>
> -static const struct udevice_id sata_ceva_ids[] = {
> - { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
> - { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
> - { }
> -};
> -
Why do you move this structure?
York
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Re: [U-Boot] [PATCH v2 1/8] Enable CONFIG_BLK and CONFIG_DM_MMC to Kconfig
On 07/26/2018 12:09 AM, Yinbo Zhu wrote: >> >> Thanks your feedback! And the patch 1 is applied then that it reported some >> compiled error, so add patch > >> 2 to fix compile error, and I will only put the patch 3 in front of patch 1, >> Do you think that's okay? > >> Every single patch must be successfully compiled. U-Boot must be functional, >> too. Otherwise, you will face > >> problem when you try to bisect an issue. > >> York > > Hi York > > I had updated the patch order, Could you give me a feedback? > http://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=71513&state=*&q=&archive=both&delegate= > This link doesn't work. It gives me other unrelated patches as well. Please send a new set. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/6] mvebu: select boot device at SoC level
Hi Baruch,
this patch needs to be rebased on git master as it does not apply.
Thanks
Dennis
El lun, 18-06-2018 a las 21:56 +0300, Baruch Siach escribió:
> Move the gdsys Controlcenter DC specific build time kwbimage.cfg
> generation code into the mach-mvebu/ directory to be shared by all
> 32bit
> mvebu platforms.
>
> Remove board specific kwbimage.cfg files, and use the generated one
> instead. These files are all identical, with two exceptions. Clearfog
> and Helios4 use the sdio boot device, whereas all others use spi.
> Update
> the defconfigs for the exceptional boards to generate the same
> kwbimage.cfg as before.
>
> Signed-off-by: Baruch Siach
> ---
> .../a38x => arch/arm/mach-mvebu}/.gitignore | 0
> arch/arm/mach-mvebu/Makefile | 30
> ++
> arch/arm/mach-mvebu/include/mach/config.h | 4 +--
> .../arm/mach-mvebu}/kwbimage.cfg.in | 0
> board/CZ.NIC/turris_omnia/kwbimage.cfg| 12 ---
> board/Marvell/db-88f6720/kwbimage.cfg | 12 ---
> board/Marvell/db-88f6820-amc/kwbimage.cfg | 12 ---
> board/Marvell/db-88f6820-gp/kwbimage.cfg | 12 ---
> board/Marvell/db-mv784mp-gp/kwbimage.cfg | 12 ---
> board/Synology/ds414/kwbimage.cfg | 12 ---
> board/gdsys/a38x/Makefile | 31 ---
>
> board/kobol/helios4/kwbimage.cfg | 13
> board/maxbcm/kwbimage.cfg | 12 ---
> board/solidrun/clearfog/kwbimage.cfg | 12 ---
> board/theadorable/kwbimage.cfg| 12 ---
> configs/clearfog_defconfig| 2 +-
> configs/helios4_defconfig | 2 +-
> 17 files changed, 34 insertions(+), 156 deletions(-)
> rename {board/gdsys/a38x => arch/arm/mach-mvebu}/.gitignore (100%)
> rename {board/gdsys/a38x => arch/arm/mach-mvebu}/kwbimage.cfg.in
> (100%)
> delete mode 100644 board/CZ.NIC/turris_omnia/kwbimage.cfg
> delete mode 100644 board/Marvell/db-88f6720/kwbimage.cfg
> delete mode 100644 board/Marvell/db-88f6820-amc/kwbimage.cfg
> delete mode 100644 board/Marvell/db-88f6820-gp/kwbimage.cfg
> delete mode 100644 board/Marvell/db-mv784mp-gp/kwbimage.cfg
> delete mode 100644 board/Synology/ds414/kwbimage.cfg
> delete mode 100644 board/kobol/helios4/kwbimage.cfg
> delete mode 100644 board/maxbcm/kwbimage.cfg
> delete mode 100644 board/solidrun/clearfog/kwbimage.cfg
> delete mode 100644 board/theadorable/kwbimage.cfg
>
> diff --git a/board/gdsys/a38x/.gitignore b/arch/arm/mach-
> mvebu/.gitignore
> similarity index 100%
> rename from board/gdsys/a38x/.gitignore
> rename to arch/arm/mach-mvebu/.gitignore
> diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-
> mvebu/Makefile
> index ade7b870646f..d907fac3752d 100644
> --- a/arch/arm/mach-mvebu/Makefile
> +++ b/arch/arm/mach-mvebu/Makefile
> @@ -25,6 +25,36 @@ obj-$(CONFIG_ARMADA_375) +=
> ../../../drivers/ddr/marvell/axp/xor.o
> obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
> obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
> obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
> +
> +extra-y += kwbimage.cfg
> +
> +KWB_REPLACE += BOOT_FROM
> +ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI),)
> + KWB_CFG_BOOT_FROM=spi
> +endif
> +ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC),)
> + KWB_CFG_BOOT_FROM=sdio
> +endif
> +
> +ifneq ($(CONFIG_SECURED_MODE_IMAGE),)
> +KWB_REPLACE += CSK_INDEX
> +KWB_CFG_CSK_INDEX = $(CONFIG_SECURED_MODE_CSK_INDEX)
> +
> +KWB_REPLACE += SEC_BOOT_DEV
> +KWB_CFG_SEC_BOOT_DEV=$(patsubst "%",%, \
> + $(if $(findstring
> BOOT_SPI_NOR_FLASH,$(CONFIG_SPL_BOOT_DEVICE)),0x34) \
> + $(if $(findstring
> BOOT_SDIO_MMC_CARD,$(CONFIG_SPL_BOOT_DEVICE)),0x31) \
> + )
> +
> +KWB_REPLACE += SEC_FUSE_DUMP
> +KWB_CFG_SEC_FUSE_DUMP = a38x
> +endif
> +
> +$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
> + include/config/auto.conf
> + $(Q)sed -ne '$(foreach V,$(KWB_REPLACE),s/^#@$(V)/$(V)
> $(KWB_CFG_$(V))/;)p' \
> + <$< >$(dir $<)$(@F)
> +
> endif # CONFIG_SPL_BUILD
> obj-y+= gpio.o
> obj-y+= mbus.o
> diff --git a/arch/arm/mach-mvebu/include/mach/config.h
> b/arch/arm/mach-mvebu/include/mach/config.h
> index 2acfd3314a68..9f51411e43f1 100644
> --- a/arch/arm/mach-mvebu/include/mach/config.h
> +++ b/arch/arm/mach-mvebu/include/mach/config.h
> @@ -32,12 +32,12 @@
> #endif
>
> /*
> - * By default kwbimage.cfg from board specific folder is used
> + * By default the generated mvebu kwbimage.cfg is used
> * If for some board, different configuration file need to be used,
> * CONFIG_SYS_KWD_CONFIG should be defined in board specific header
> file
> */
> #ifndef CONFIG_SYS_KWD_CONFIG
> -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.c
> fg
> +#define CONFIG_SYS_KWD_CONFIG arch/arm/mach-
> mvebu/kwbimage.cfg
> #endif /* CONFIG_SYS_KWD_CONFIG */
>
> /* Add target to build it au
[U-Boot] Please pull u-boot-mpc85xx master
Tom, The following changes since commit 2547e91dc15e5203e15d4ebde9172174743b14a7: tegra: Indicate that binman makes all three output files (2018-07-26 15:49:40 -0400) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git for you to fetch changes up to 9dcb9d763d328da903194d0f14f97d9620a6f52d: Revert "powerpc/T104xRDB: Fix endian access issue on EHCI intinalization" (2018-07-31 10:19:42 -0700) Ran Wang (2): Revert "powerpc/p1_p2_rdb_pc: Fix endian access issue on EHCI intinalization" Revert "powerpc/T104xRDB: Fix endian access issue on EHCI intinalization" include/configs/T104xRDB.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - 2 files changed, 2 deletions(-) Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-mpc85xx master
Scratch that. I realized I didn't fix the commit messages. Will push another one. York On 07/31/2018 10:12 AM, York Sun wrote: > Tom, > > The following changes since commit 2547e91dc15e5203e15d4ebde9172174743b14a7: > > tegra: Indicate that binman makes all three output files (2018-07-26 > 15:49:40 -0400) > > are available in the git repository at: > > git://git.denx.de/u-boot-mpc85xx.git > > for you to fetch changes up to 7c176ce687bb35ccdcec123768d235db08674891: > > Revert "powerpc/T104xRDB: Fix endian access issue on EHCI > intinalization" (2018-07-27 08:52:13 -0700) > > > Ran Wang (2): > Revert "powerpc/p1_p2_rdb_pc: Fix endian access issue on EHCI > intinalization" > Revert "powerpc/T104xRDB: Fix endian access issue on EHCI > intinalization" > > include/configs/T104xRDB.h | 1 - > include/configs/p1_p2_rdb_pc.h | 1 - > 2 files changed, 2 deletions(-) > > Travis build passed, log > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftravis-ci.org%2Fyorksun%2Fu-boot%2Fbuilds%2F409003975&data=02%7C01%7Cyork.sun%40nxp.com%7C14c12c421deb4d8a7b3308d5f708daba%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636686539764348347&sdata=Viuv5jhwUr4rrCTUOSimz7xlMXGLlKQV%2F%2FLOD1kkojQ%3D&reserved=0 > > Thanks. > > York > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.denx.de%2Flistinfo%2Fu-boot&data=02%7C01%7Cyork.sun%40nxp.com%7C14c12c421deb4d8a7b3308d5f708daba%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636686539764348347&sdata=egsorvmJRUfElsGVoNsb%2Fa4cBABDYv02gnzv4LbImV8%3D&reserved=0 > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] Revert "powerpc/T104xRDB: Fix endian access issue on EHCI intinalization"
On 06/13/2018 07:46 PM, Ran Wang wrote:
> There was an EHCI endian accessor issue. Now it's fixed by
> commit 9829ce2ff25c ("usb: ehci: Fix accessors for big-endian platforms and
> descriptors")
> Revert commit e6a727fffec7b2002e ("powerpc/T104xRDB: Fix endian access issue
> on EHCI intinalization")
> due to it fix that issue in a wrong way. Actually, on T104x platform,
> USB EHCI register use little endian.
>
> Signed-off-by: Ran Wang
> ---
Applied to mpc85xx, awaiting upstream. Thanks.
York
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Re: [U-Boot] [PATCH 1/2] Revert "powerpc/p1_p2_rdb_pc: Fix endian access issue on EHCI intinalization"
On 06/13/2018 07:46 PM, Ran Wang wrote:
> There was an EHCI endian accessor issue. Now it's fixed by
> commit 9829ce2ff25c ("usb: ehci: Fix accessors for big-endian platforms and
> descriptors").
> Revert commit 0f2296bab141 ("powerpc/p1_p2_rdb_pc: Fix endian access issue on
> EHCI intinalization")
> due to it fix that issue in a wrong way. Actually, on P1 P2 platforms,
> USB EHCI register use little endian.
>
> Signed-off-by: Ran Wang
> ---
Applied to mpc85xx, awaiting upstream. Thanks.
York
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[U-Boot] Please pull u-boot-mpc85xx master
Tom, The following changes since commit 2547e91dc15e5203e15d4ebde9172174743b14a7: tegra: Indicate that binman makes all three output files (2018-07-26 15:49:40 -0400) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git for you to fetch changes up to 7c176ce687bb35ccdcec123768d235db08674891: Revert "powerpc/T104xRDB: Fix endian access issue on EHCI intinalization" (2018-07-27 08:52:13 -0700) Ran Wang (2): Revert "powerpc/p1_p2_rdb_pc: Fix endian access issue on EHCI intinalization" Revert "powerpc/T104xRDB: Fix endian access issue on EHCI intinalization" include/configs/T104xRDB.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - 2 files changed, 2 deletions(-) Travis build passed, log https://travis-ci.org/yorksun/u-boot/builds/409003975 Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Latest u-boot-spi.git master branch build breaks
On Tue, Jul 31, 2018 at 10:15 PM, Stephen Warren wrote:
> On 07/31/2018 10:34 AM, Jagan Teki wrote:
>>
>> On Tue, Jul 31, 2018 at 9:51 PM, Stephen Warren
>> wrote:
>>>
>>> Jagan,
>>>
>>> The following Tegra/sandbox builds fail with the latest u-boot-spi.git
>>> master branch:
>>>
>>> sandbox:
drivers/mtd/spi/spi_flash_ids.c:113:2: error: expected ‘}’ before ‘{’
token
{"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL
|
WR_QPP) },
^
>>
>>
>> Yeah, just know i found, fixed the same. thanks for the notice.
>
>
> The Tegra link problems too?
>
> BTW, your email address in doc/git-emailrc (at least in u-boot.git master
> branch) bounces.
in doc/git-mailrc? about this jt...@openedev.com mail? It's already
updated to jag...@openedev.com
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Re: [U-Boot] Latest u-boot-spi.git master branch build breaks
On 07/31/2018 10:34 AM, Jagan Teki wrote:
On Tue, Jul 31, 2018 at 9:51 PM, Stephen Warren wrote:
Jagan,
The following Tegra/sandbox builds fail with the latest u-boot-spi.git
master branch:
sandbox:
drivers/mtd/spi/spi_flash_ids.c:113:2: error: expected ‘}’ before ‘{’
token
{"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL |
WR_QPP) },
^
Yeah, just know i found, fixed the same. thanks for the notice.
The Tegra link problems too?
BTW, your email address in doc/git-emailrc (at least in u-boot.git
master branch) bounces.
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Re: [U-Boot] Latest u-boot-spi.git master branch build breaks
On Tue, Jul 31, 2018 at 9:51 PM, Stephen Warren wrote:
> Jagan,
>
> The following Tegra/sandbox builds fail with the latest u-boot-spi.git
> master branch:
>
> sandbox:
>>
>> drivers/mtd/spi/spi_flash_ids.c:113:2: error: expected ‘}’ before ‘{’
>> token
>> {"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL |
>> WR_QPP) },
>> ^
Yeah, just know i found, fixed the same. thanks for the notice.
Jagan.
--
Jagan Teki
Senior Linux Kernel Engineer | Amarula Solutions
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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[U-Boot] Latest u-boot-spi.git master branch build breaks
Jagan,
The following Tegra/sandbox builds fail with the latest u-boot-spi.git
master branch:
sandbox:
drivers/mtd/spi/spi_flash_ids.c:113:2: error: expected ‘}’ before ‘{’ token
{"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL |
WR_QPP) },
^
plutux:
medcom-wide:
harmony:
tec:
colibri_t20:
seaboard:
cmd/built-in.o: In function `set_dev':
cmd/nand.c:118: undefined reference to `get_nand_dev_by_index'
cmd/nand.c:121: undefined reference to `nand_curr_device'
(and many other link errors)
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Re: [U-Boot] [PATCH v6 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device tree
On 7/31/2018 5:53 PM, laurentiu.tu...@nxp.com wrote: > From: Laurentiu Tudor > > Add support for SEC ICID configuration and apply it for ls1046a. > Also add code to make the necessary device tree fixups. > > Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geantă [snip] > +#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \ > + SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ > + offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \ > + CONFIG_SYS_FSL_SEC_ADDR, 0) > + RTIC nodes have a binding doc in Linux kernel: Documentation/devicetree/bindings/crypto/fsl-sec4.txt Thus, in theory, "fsl,sec-v4.0-rtic-memory" could be used instead of NULL for the compat string. PPC code in arch/powerpc/include/asm/fsl_liodn.h does this. In practice, this won't make any difference until a RTIC kernel driver is added. Regards, Horia ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] board: freescale: ls1012ardb: Add command to switch QSPI bank
Hi York, > -Original Message- > From: York Sun > Sent: Tuesday, July 31, 2018 8:37 PM > To: Calvin Johnson ; Scott Wood > ; Calvin Johnson > Cc: Jagdish Gediya ; U-Boot Mailing List b...@lists.denx.de> > Subject: Re: [U-Boot] [PATCH] board: freescale: ls1012ardb: Add command to > switch QSPI bank > > On 04/19/2018 06:53 PM, Calvin Johnson wrote: > >> > >>> would be better. What this patch currently does can be done with > >>> simple env vars, like : > >>> > >>> setenv boot_bank_1 'i2c mw 0x24 0x7 0xfc; i2c mw 0x24 0x3 0xf5' > >>> setenv boot_bank_2 'i2c mw 0x24 0x7 0xfc; i2c mw 0x24 0x3 0xf4' > >> > >> ...if the user knows to env reset those variables after the update > >> (versus something that shows up in help), and if they don't get > >> corrupted in a multi- user board farm environment, etc. > > > > Make sense. Thanks! > > > > Calvin, > > Do you want to stay with env, or still want this patch, or standardize the > command? Ideally, a fully standardized generic command interface supporting all similar platforms with multiple banks as well as other boot sources such as NAND and MMC, is the best option. This patch looks good as an interim solution. Regards Calvin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] board: sun50i: h6: Add OrangePi One Plus initial support
On Mon, Jul 30, 2018 at 2:31 PM, Maxime Ripard wrote: > On Sun, Jul 29, 2018 at 12:03:31AM +0530, Jagan Teki wrote: >> OrangePi One Plus is Allwinner H6 based open-source SBC, >> which support: >> - Allwinner H6 Quad-core 64-bit ARM Cortex-A53 >> - GPU Mali-T720 >> - 1GB LPDDR3 RAM >> - AXP805 PMIC >> - 1Gbps GMAC via RTL8211 >> - USB 2.0 Host, OTG >> - HDMI port >> - 5V/2A DC power supply >> >> Signed-off-by: Jagan Teki > > Acked-by: Maxime Ripard Applied to u-boot-sunxi/master ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] mtd: nand: nand_base: Convert EINVAL into ENOTSUPP
On Fri, Jul 13, 2018 at 9:40 PM, Mylène Josserand wrote: > Convert the EINVAL error into ENOTSUPP when the GET/SET_FEATURES > is not supported. > > Signed-off-by: Mylène Josserand > --- Applied both. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] board: freescale: ls1012ardb: Add command to switch QSPI bank
On 04/19/2018 06:53 PM, Calvin Johnson wrote: >> >>> would be better. What this patch currently does can be done with >>> simple env vars, like : >>> >>> setenv boot_bank_1 'i2c mw 0x24 0x7 0xfc; i2c mw 0x24 0x3 0xf5' >>> setenv boot_bank_2 'i2c mw 0x24 0x7 0xfc; i2c mw 0x24 0x3 0xf4' >> >> ...if the user knows to env reset those variables after the update (versus >> something that shows up in help), and if they don't get corrupted in a multi- >> user board farm environment, etc. > > Make sense. Thanks! > Calvin, Do you want to stay with env, or still want this patch, or standardize the command? York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] boot a bios/uefi with x86_64, without grub
Hi Thierry, On Tue, Jul 31, 2018 at 6:18 PM, Thierry Gayet wrote: > Hi, > > I am working with a board called "up board" ( > http://www.aaeon.com/en/p/up-board-computer-board-for-professional-makers) > from aaeon. > > This card is as tiny as a credit card or a raspberry pi running with a > x86_64 processor. > > It buildin an UEFI BIOS and a MMC memory (no sdcard, no ssd, no sata, no > rom). > > I know this is not really adapt to an embedded usage but i would like to > let my u-boot bootloader loading my gnu/linux kernel (using the bootefi > command) then my linux rootfs (generated by yocto) : > > (UEFI / BIOS) -> (uboot uefi) -> (GNU/Linux kernel) --> (linux rootfs) > > I do not want to use grub or grub uefi if possible. > > My idea is to make a uefi partition on the eMMC memory. > > I am looking for an uboot configuration i can use to compile my bootloader. > > I have make tests with the u-boot-app.efi that i have compiled and set into > an efi paritiion ; i am booting into an usb key first. This is not working > and always stop at the uefi shell... > > Maybe my u-boot-app.efi need to be signed ? No. Since you mentioned the x86 processor is 64-bit, it's hightly possible that you have a 64-bit EFI BIOS. That means you cannot use u-boot-app.efi with this EFI BIOS since u-boot-app.efi is 32-bit. > > Is there a documentation that describe all steps required ? > > Any help welcome in order to solve my use case. Thanks in advance. > You will need try efi-x86_payload64, and boot from there. Note currently there are issues to boot Linux kernel from the U-Boot payload. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device tree
From: Laurentiu Tudor
Add support for SEC ICID configuration and apply it for ls1046a.
Also add code to make the necessary device tree fixups.
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 14 +++
.../asm/arch-fsl-layerscape/fsl_icid.h| 25 +++
.../asm/arch-fsl-layerscape/immap_lsch2.h | 8 ++
3 files changed, 47 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 30c7d8d28a..2da9adab5b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -40,6 +40,20 @@ struct icid_id_table icid_tbl[] = {
SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
SET_ETR_ICID(FSL_ETR_STREAM_ID),
SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+ SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+ SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 7),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 8),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 9),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 10),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 11),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 12),
+ SET_SEC_DECO_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 13),
+#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 5be50a17ab..a70c866651 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -8,6 +8,7 @@
#include
#include
+#include
struct icid_id_table {
const char *compat;
@@ -82,6 +83,30 @@ void fdt_fixup_icid(void *blob);
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
{ .port_id = (_port_id), .icid = (streamid) }
+#define SET_SEC_QI_ICID(streamid) \
+ SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
+ (((streamid) << 16) | (streamid)), \
+ offsetof(ccsr_sec_t, qilcr_ls) + \
+ CONFIG_SYS_FSL_SEC_ADDR, \
+ CONFIG_SYS_FSL_SEC_ADDR)
+
+#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
+ SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
+ (((streamid) << 16) | (streamid)), \
+ offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
+ CONFIG_SYS_FSL_SEC_ADDR, \
+ FSL_SEC_JR##jr_num##_BASE_ADDR)
+
+#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
+ SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
+ offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
+ CONFIG_SYS_FSL_SEC_ADDR, 0)
+
+#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
+ SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
+ offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
+ CONFIG_SYS_FSL_SEC_ADDR, 0)
+
extern struct icid_id_table icid_tbl[];
extern struct fman_icid_id_table fman_icid_tbl[];
extern int icid_tbl_sz;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d22ec70aa5..be0a6ae363 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -200,10 +200,18 @@ struct sys_info {
#define CONFIG_SYS_FSL_SEC_OFFSET 0x70ull
#define CONFIG_SYS_FSL_JR0_OFFSET 0x71ull
+#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
+#define FSL_SEC_JR1_OFFSET 0x72ull
+#define FSL_SEC_JR2_OFFSET 0x73ull
+#define FSL_SEC_JR3_OFFSET 0x74ull
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
+#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
+#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
+#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
/* Device Configuration and Pin Control */
#define DCFG_DCSR_PORCR1 0x0
--
2.17.1
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[U-Boot] [PATCH v6 7/8] armv8: ls1046a: setup fman ports ICIDs and device tree
From: Laurentiu Tudor
Add support for ICID setting of fman ports and the required device
tree fixups.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 82 +++
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++
.../asm/arch-fsl-layerscape/fsl_icid.h| 10 +++
3 files changed, 122 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index ae3b8daa95..b1a950e7f9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
static void set_icid(struct icid_id_table *tbl, int size)
{
@@ -19,10 +20,27 @@ static void set_icid(struct icid_id_table *tbl, int size)
out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
}
+#ifdef CONFIG_SYS_DPAA_FMAN
+void set_fman_icids(struct fman_icid_id_table *tbl, int size)
+{
+ int i;
+ ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+
+ for (i = 0; i < size; i++) {
+ out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1],
+tbl[i].icid);
+ }
+}
+#endif
+
void set_icids(void)
{
/* setup general icid offsets */
set_icid(icid_tbl, icid_tbl_sz);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
+#endif
}
int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids)
@@ -75,6 +93,66 @@ int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
return 0;
}
+#ifdef CONFIG_SYS_DPAA_FMAN
+int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
+ const int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++) {
+ if (tbl[i].port_id == port_id)
+ return tbl[i].icid;
+ }
+
+ return -1;
+}
+
+void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
+ const char *compat)
+{
+ int noff, len, icid;
+ const u32 *prop;
+
+ noff = fdt_node_offset_by_compatible(blob, -1, compat);
+ while (noff > 0) {
+ prop = fdt_getprop(blob, noff, "cell-index", &len);
+ if (!prop) {
+ printf("WARNING missing cell-index for fman port\n");
+ continue;
+ }
+ if (len != 4) {
+ printf("WARNING bad cell-index size for fman port\n");
+ continue;
+ }
+
+ icid = get_fman_port_icid(fdt32_to_cpu(*prop),
+ fman_icid_tbl, fman_icid_tbl_sz);
+ if (icid < 0) {
+ printf("WARNING unknown ICID for fman port %d\n",
+ *prop);
+ continue;
+ }
+
+ fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *)&icid, 1);
+
+ noff = fdt_node_offset_by_compatible(blob, noff, compat);
+ }
+}
+
+void fdt_fixup_fman_icids(void *blob, int smmu_ph)
+{
+ static const char * const compats[] = {
+ "fsl,fman-v3-port-oh",
+ "fsl,fman-v3-port-rx",
+ "fsl,fman-v3-port-tx",
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(compats); i++)
+ fdt_fixup_fman_port_icid_by_compat(blob, smmu_ph, compats[i]);
+}
+#endif
+
int fdt_get_smmu_phandle(void *blob)
{
int noff, smmu_ph;
@@ -107,4 +185,8 @@ void fdt_fixup_icid(void *blob)
return;
fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_icids(blob, smmu_ph);
+#endif
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 80e1ceadc0..30c7d8d28a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -43,3 +43,33 @@ struct icid_id_table icid_tbl[] = {
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct fman_icid_id_table fman_icid_tbl[] = {
+ /* port id, icid */
+ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STR
[U-Boot] [PATCH v6 6/8] armv8: ls1046a: add icid setup for qman portals
From: Laurentiu Tudor
Add support for ICID setting of qman portals and the required device
tree fixups. Also fix an endiness issue in portal setup code.
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
.../asm/arch-fsl-layerscape/fsl_portals.h | 24 +++
drivers/misc/fsl_portals.c| 43 +++
3 files changed, 75 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 1c528ab751..80e1ceadc0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -6,6 +6,22 @@
#include
#include
#include
+#include
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+};
+#endif
struct icid_id_table icid_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
new file mode 100644
index 00..1577e935a6
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef _FSL_PORTALS_H_
+#define _FSL_PORTALS_H_
+
+struct qportal_info {
+ u16 dicid; /* DQRR ICID */
+ u16 ficid; /* frame data ICID */
+ u16 icid;
+ u8 sdest;
+};
+
+#define SET_QP_INFO(streamid, dest) \
+ { .dicid = (streamid), .ficid = (streamid), .icid = (streamid), \
+ .sdest = (dest) }
+
+extern struct qportal_info qp_info[];
+void fdt_portal(void *blob, const char *compat, const char *container,
+ u64 addr, u32 size);
+
+#endif
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index 22faf16751..a524510707 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c
@@ -13,6 +13,9 @@
#ifdef CONFIG_PPC
#include
#include
+#else
+#include
+#include
#endif
#include
@@ -45,6 +48,22 @@ void setup_qbman_portals(void)
/* set frame liodn */
out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
}
+#else
+#ifdef CONFIG_ARM
+ int i;
+
+ for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+ u8 sdest = qp_info[i].sdest;
+ u16 ficid = qp_info[i].ficid;
+ u16 dicid = qp_info[i].dicid;
+ u16 icid = qp_info[i].icid;
+
+ out_be32(&qman->qcsp[i].qcsp_lio_cfg, (icid << 16) |
+ dicid);
+ /* set frame icid */
+ out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | ficid);
+ }
+#endif
#endif
/* Change default state of BMan ISDR portals to all 1s */
@@ -178,6 +197,10 @@ void fdt_fixup_qportals(void *blob)
char compat[64];
int compat_len;
+#ifndef CONFIG_PPC
+ int smmu_ph = fdt_get_smmu_phandle(blob);
+#endif
+
maj = (rev_1 >> 8) & 0xff;
min = rev_1 & 0xff;
ip_cfg = rev_2 & 0xff;
@@ -188,7 +211,6 @@ void fdt_fixup_qportals(void *blob)
off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
while (off != -FDT_ERR_NOTFOUND) {
-#ifdef CONFIG_PPC
#ifdef CONFIG_FSL_CORENET
u32 liodns[2];
#endif
@@ -198,12 +220,7 @@ void fdt_fixup_qportals(void *blob)
if (!ci)
goto err;
- i = *ci;
-#ifdef CONFIG_SYS_DPAA_FMAN
- int j;
-#endif
-
-#endif /* CONFIG_PPC */
+ i = fdt32_to_cpu(*ci);
err = fdt_setprop(blob, off, "compatible", compat, compat_len);
if (err < 0)
goto err;
@@ -235,7 +252,7 @@ void fdt_fixup_qportals(void *blob)
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
- for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
+ for (int j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
char name[] = "fman@0";
name[sizeof(name) - 2] = '0' + j;
@@ -251,6 +268,16 @@ void fdt_fixup_qportals(void *blob)
if (err < 0)
goto err;
#endif
+#else
+ if (smmu_ph >= 0) {
+ u32 icids[3];
+
+ icids[0] = qp_info[i].icid;
+ icids[1] = qp_inf
[U-Boot] [PATCH v6 4/8] armv8: fsl-layerscape: add missing debug stream ID
From: Laurentiu Tudor Add a define with a value for the missing debug stream ID. Signed-off-by: Laurentiu Tudor --- arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h index 61c6e533c6..1b02d484d9 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -50,6 +50,7 @@ #define FSL_QDMA_STREAM_ID 7 #define FSL_EDMA_STREAM_ID 8 #define FSL_ETR_STREAM_ID 9 +#define FSL_DEBUG_STREAM_ID10 /* PCI - programmed in PEXn_LUT */ #define FSL_PEX_STREAM_ID_START11 -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 5/8] armv8: ls1046a: initial icid setup support
From: Laurentiu Tudor
Add infrastructure for ICID setup and device tree fixup on ARM
platforms. This include basic ICID setup for several devices.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 110 ++
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 29 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +
.../asm/arch-fsl-layerscape/fsl_icid.h| 80 +
board/freescale/ls1046aqds/ls1046aqds.c | 3 +
board/freescale/ls1046ardb/ls1046ardb.c | 3 +
7 files changed, 229 insertions(+)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 1e9e4680fe..5d6f68aad6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -37,6 +37,7 @@ endif
ifneq ($(CONFIG_ARCH_LS1046A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
+obj-y += icid.o ls1046_ids.o
endif
ifneq ($(CONFIG_ARCH_LS1088A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
new file mode 100644
index 00..ae3b8daa95
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+static void set_icid(struct icid_id_table *tbl, int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++)
+ out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
+}
+
+void set_icids(void)
+{
+ /* setup general icid offsets */
+ set_icid(icid_tbl, icid_tbl_sz);
+}
+
+int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids)
+{
+ int i, ret;
+ u32 prop[8];
+
+ /*
+* Note: The "iommus" property definition mentions Stream IDs while
+* this code handles ICIDs. The current implementation assumes that
+* ICIDs and Stream IDs are equal.
+*/
+ for (i = 0; i < num_ids; i++) {
+ prop[i * 2] = cpu_to_fdt32(smmu_ph);
+ prop[i * 2 + 1] = cpu_to_fdt32(ids[i]);
+ }
+ ret = fdt_setprop(blob, off, "iommus",
+ prop, sizeof(u32) * num_ids * 2);
+ if (ret) {
+ printf("WARNING unable to set iommus: %s\n", fdt_strerror(ret));
+ return ret;
+ }
+
+ return 0;
+}
+
+int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
+ struct icid_id_table *tbl, int size)
+{
+ int i, err, off;
+
+ for (i = 0; i < size; i++) {
+ if (!tbl[i].compat)
+ continue;
+
+ off = fdt_node_offset_by_compat_reg(blob,
+ tbl[i].compat,
+ tbl[i].compat_addr);
+ if (off > 0) {
+ err = fdt_set_iommu_prop(blob, off, smmu_ph,
+&tbl[i].id, 1);
+ if (err)
+ return err;
+ } else {
+ printf("WARNING could not find node %s: %s.\n",
+ tbl[i].compat, fdt_strerror(off));
+ }
+ }
+
+ return 0;
+}
+
+int fdt_get_smmu_phandle(void *blob)
+{
+ int noff, smmu_ph;
+
+ noff = fdt_node_offset_by_compatible(blob, -1, "arm,mmu-500");
+ if (noff < 0) {
+ printf("WARNING failed to get smmu node: %s\n",
+ fdt_strerror(noff));
+ return noff;
+ }
+
+ smmu_ph = fdt_get_phandle(blob, noff);
+ if (!smmu_ph) {
+ smmu_ph = fdt_create_phandle(blob, noff);
+ if (!smmu_ph) {
+ printf("WARNING failed to get smmu phandle\n");
+ return -1;
+ }
+ }
+
+ return smmu_ph;
+}
+
+void fdt_fixup_icid(void *blob)
+{
+ int smmu_ph;
+
+ smmu_ph = fdt_get_smmu_phandle(blob);
+ if (smmu_ph < 0)
+ return;
+
+ fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz);
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
new file mode 100644
index 00..1c528ab751
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include
+#include
+
+struct icid_id_table icid_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START),
+ SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1),
+#endif
+
+
[U-Boot] [PATCH v6 2/8] armv8: ls1046a: advertise QMan v3 in configuration
From: Laurentiu Tudor The QMan IP block in this SoC is version 3.2 so advertise this in the SoC configuration header. Signed-off-by: Laurentiu Tudor --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 23faffd9fc..8a05148136 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -257,6 +257,7 @@ #elif defined(CONFIG_ARCH_LS1046A) #define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FSL_QMAN_V3 #define CONFIG_SYS_NUM_FMAN1 #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 3/8] misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms
From: Laurentiu Tudor
QMAN_BAR{E} register setup was disabled on ARM platforms, however the
register does need to be set. Enable the code also on ARMs and fix the
CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly
enabled code works.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +--
drivers/misc/fsl_portals.c | 2 --
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 644a16dd30..d22ec70aa5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -57,8 +57,7 @@
#define CONFIG_SYS_BMAN_SWP_ISDR_REG0x3E80
#define CONFIG_SYS_QMAN_NUM_PORTALS10
#define CONFIG_SYS_QMAN_MEM_BASE 0x5
-#define CONFIG_SYS_QMAN_MEM_PHYS (0xfull + \
- CONFIG_SYS_QMAN_MEM_BASE)
+#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_MEM_SIZE 0x0800
#define CONFIG_SYS_QMAN_SP_CENA_SIZE0x1
#define CONFIG_SYS_QMAN_SP_CINH_SIZE0x1
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index 7c22b8d209..22faf16751 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c
@@ -24,7 +24,6 @@ void setup_qbman_portals(void)
CONFIG_SYS_BMAN_SWP_ISDR_REG;
void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
CONFIG_SYS_QMAN_SWP_ISDR_REG;
-#ifdef CONFIG_PPC
struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
@@ -32,7 +31,6 @@ void setup_qbman_portals(void)
out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
#endif
out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
-#endif
#ifdef CONFIG_FSL_CORENET
int i;
--
2.17.1
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[U-Boot] [PATCH v6 1/8] armv8: fsl-layerscape: add missing register blocks base address defines
From: Laurentiu Tudor Add defines for the edma and qdma register block base addresses. Signed-off-by: Laurentiu Tudor --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 5b4767e0fe..644a16dd30 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -88,8 +88,12 @@ #define LPUART_BASE(CONFIG_SYS_IMMR + 0x0195) +#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c0) + #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x0220) +#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x0738) + #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x40ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x48ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x50ULL -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 0/8] NXP LS1046A SMMU enabling patches
From: Laurentiu Tudor
This patch series adds the required devices setup and device tree
fixups for SMMU enablement on NXP LS1046A chips. The approach taken
tries to mimic the implementation of PAMU LIODN setup on booke powerpc.
First 4 patches contain some fixes and add some missing bits & pieces.
Last 4 patches add the actual infrastructure for ICID setup, qman
portals, fman ICID and SEC configuration.
Changes in v6:
- distinct ICIDs for all SEC blocks (Horia, Bharat)
Changes in v5:
- use distinct ICID for SEC JRs (Horia, Bharat)
- moved an #include in the file it's used (Horia)
- fix broken compilation of multiple targets due to removal of SEC
related config (Horia)
- add a missing #include in qds board file
- drop few uses of CONFIG_SYS_FMAN_V3 and consistently use
CONFIG_SYS_DPAA_FMAN everywhere
Changes in v4:
- added missing SEC ICID config
- updated macro params to match arguments
- supplemental comments
Changes in v3:
- cleaner QMAN_BAR setup
- moved SoC specific bits from generic ICID arch setup to board code
Changes in v2:
- drop CONFIG_SYS_ prefix from newly introduced defines in patch [1/8]
Laurentiu Tudor (8):
armv8: fsl-layerscape: add missing register blocks base address
defines
armv8: ls1046a: advertise QMan v3 in configuration
misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms
armv8: fsl-layerscape: add missing debug stream ID
armv8: ls1046a: initial icid setup support
armv8: ls1046a: add icid setup for qman portals
armv8: ls1046a: setup fman ports ICIDs and device tree
armv8: ls1046a: setup SEC ICIDs and fix up device tree
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 192 ++
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 89
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +
.../include/asm/arch-fsl-layerscape/config.h | 1 +
.../asm/arch-fsl-layerscape/fsl_icid.h| 115 +++
.../asm/arch-fsl-layerscape/fsl_portals.h | 24 +++
.../asm/arch-fsl-layerscape/immap_lsch2.h | 15 +-
.../asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 +
board/freescale/ls1046aqds/ls1046aqds.c | 3 +
board/freescale/ls1046ardb/ls1046ardb.c | 3 +
drivers/misc/fsl_portals.c| 45 +++-
12 files changed, 480 insertions(+), 12 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
--
2.17.1
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Re: [U-Boot] [PATCH v5 00/27] SPI-NAND support
On Tue, Jul 31, 2018 at 12:59 PM, Jagan Teki wrote:
> On Mon, Jul 30, 2018 at 9:16 PM, Miquel Raynal
> wrote:
>> During the last months, Boris Brezillon shared his work to support
>> serial flashes within Linux. First, he delivered (and merged) a new
>> layer called spi-mem. He also initiated in Linux MTD subsystem the move
>> of all 'raw' NAND related code to a raw/ subdirectory, adding at the
>> same time a NAND core that would be shared with all NAND devices. Then,
>> he contributed a generic SPI-NAND driver, making use of this NAND core,
>> as well as some vendor code to drive a few chips.
>>
>> On top of this work, I added an 'mtd' U-Boot command to handle all sort
>> of MTD devices. This should become the default command instead of having
>> one per flash flavor ('sf', 'nand', 'spi-nand' ?).
>>
>> The series has been tested on an Ocelot board PCB123 (VSC7514),
>> featuring a Macronix SPI NAND chip.
>>
>> TL;DR: the series contains:
>> - A few patches from Linux to resynchronize some areas of the MTD layer.
>> - Various fixes and re-organization of the MTD subsystem.
>> - The introduction of the SPI-mem interface.
>> - The addition of the generic SPI-NAND driver (and its bindings).
>> - Several SPI NAND chip drivers (Macronix, Micron, Winbond).
>> - A new 'mtd' command.
>> - Support for spi-nand devices in mtdparts.
>>
>> To test your SPI-NAND device with U-Boot simply follow these lines:
>>
>>> setenv mtdparts mtdparts=spi-nand0:1m(foo),-(bar)
>>> setenv mtdids spi-nand0=spi-nand0
>>> mtdparts # show the spi-nand device partitions
>>> ubi part bar # create a static UBI volume in the bar partition
>>
>> Thanks,
>> Miquèl
>>
>> Changes since v4:
>> -
>> * Added Jagan's Acked-by tags to every patch related to the
>> SPI-mem/SPI-NAND addition.
>> * Rebased on top of master.
>>
>> Changes since v3:
>> -
>> * Fixed the debug messages in spi-mem to print either Rx or Tx data.
>> * Fixed a Kconfig error that prevented to build mtdparts with plain
>> defconfig.
>> * Fixed a compilation error due to the above error that prevented one
>> file to be compiled.
>> * Adapted the mtd command to probe MTD partitions also.
>> * Declared mtd_probe_devices() in a header so mtdparts or UBI could
>> use it too (to probe all devices and MTD partitions in a clean way).
>> * As I worked on mtdparts, I found annoying and completely useless the
>> fact that we need to prefix the environment variable with
>> "mtdparts=". Canceled this obligation.
>> * Added one patch to allow spi-nand devices to be recognized by mtdparts
>> (this is purely useless but needed to be done in order to use this
>> command).
>> * Removed useless definitions of MTD device types in UBI code.
>> * Wrote a generic mtdparts environment variable parser, used by the mtd
>> command.
>> * Used the mtd_probe_devices() function from get_mtd_info() in
>> cmd/mtdparts.c to be sure the desired partition really does not exist
>> (otherwise it will be probed and then found).
>>
>> Changes since v2:
>> -
>> * Rebased on u-boot master branch.
>> * Removed extra-parenthesis in
>> "mtd: Fallback to ->_read/write() when ->_read/write_oob() is missing"
>> * s/fiels/files/ in "mtd: move NAND fiels into a raw/ subdirectory"
>> * Do not describe generic SPI device properties in SPI NAND bindings.
>> * Changes in the mtd command:
>> * Printing more information in 'mtd list' (device type, device
>> characteristics)
>> * Switch to do_div() instead of '(u32)value64b % value32b' which only
>> worked because value32b was a power of 2.
>> * Removed erase.chip option.
>> * By default, erase/read/write happen on the full MTD device while a
>> dump will only work on a single page.
>>
>> Changes since v1:
>> -
>> * Fixed the nand_memorg structure of the MX35LF2GE4AB chip.
>> * Added Reviewed-by tags from Jagan.
>> * Backported and squashed two patches fixing things in the SPI NAND core
>> received on the Linux ML.
>> * Backported more changes in mtdcore.c from Linux.
>> * Added a patch to add a fallback on mtd->_read/_write() in mtdcore.c
>> when mtd->_read/write_oob() is not supported.
>> * Removed the DT changes, useless as the DTs are not available in
>> mainline yet.
>> * Addressed Boris/Stefan comments on the 'mtd' command.
>> * Added support for multi-pages OOB read/write.
>>
>>
>> Boris Brezillon (7):
>> mtd: Fallback to ->_read/write_oob() when ->_read/write() is missing
>> mtd: Add sanity checks in mtd_write/read_oob()
>> mtd: nand: Add core infrastructure to deal with NAND devices
>> mtd: nand: Pass mode information to nand_page_io_req
>> spi: Extend the core to ease integration of SPI memory controllers
>> mtd: spinand: Add initial support for the MX35LF1GE4AB chip
>> dt-bindings: Add bindings for SPI NAND devices
>>
>> Brian Norris (1):
>> mtd: add get/set of_node/flash_node helpers
>>
>> Ezequiel Garcia (1):
>> mtd: Uninl
Re: [U-Boot] [PATCH] dm: Fix CMD_DM enabling
On Tue, Jul 31, 2018 at 1:11 AM, Michal Simek wrote: > The patch "dm: Change CMD_DM enabling" > (sha1: 08a00cba06a7e608ae65e3d7ea225cf8c639429d) was incorrectly updated > and PICO_IMX7D is missing imply CMD_DM and WARP7 has it twice. > This patch is fixing it. > > Signed-off-by: Michal Simek Reviewed-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 1/2] dm: serial: Replace setparity by setconfig
Hi Simon
On 07/31/2018 01:52 PM, Simon Glass wrote:
> Hi Patrice,
>
> On 30 July 2018 at 09:23, Patrice Chotard wrote:
>> From: Patrick Delaunay
>>
>> Replace setparity by more generic setconfig ops
>> to allow uart parity, bits word length and stop bits
>> number change.
>>
>> Adds SERIAL_GET_PARITY/BITS/STOP macros.
>>
>> Signed-off-by: Patrick Delaunay
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> drivers/serial/serial-uclass.c | 14 ++
>> include/serial.h | 42
>> +++---
>> 2 files changed, 53 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
>> index 321d23ee93bf..9f523751ce17 100644
>> --- a/drivers/serial/serial-uclass.c
>> +++ b/drivers/serial/serial-uclass.c
>> @@ -287,6 +287,18 @@ void serial_setbrg(void)
>> ops->setbrg(gd->cur_serial_dev, gd->baudrate);
>> }
>>
>> +void serial_setconfig(u8 config)
>> +{
>> + struct dm_serial_ops *ops;
>> +
>> + if (!gd->cur_serial_dev)
>> + return;
>> +
>> + ops = serial_get_ops(gd->cur_serial_dev);
>> + if (ops->setconfig)
>> + ops->setconfig(gd->cur_serial_dev, config);
>> +}
>> +
>> void serial_stdio_init(void)
>> {
>> }
>> @@ -398,6 +410,8 @@ static int serial_post_probe(struct udevice *dev)
>> ops->pending += gd->reloc_off;
>> if (ops->clear)
>> ops->clear += gd->reloc_off;
>> + if (ops->setconfig)
>> + ops->setconfig += gd->reloc_off;
>> #if CONFIG_POST & CONFIG_SYS_POST_UART
>> if (ops->loop)
>> ops->loop += gd->reloc_off
>> diff --git a/include/serial.h b/include/serial.h
>> index b9ef6d91c9c5..61c1362e9e32 100644
>> --- a/include/serial.h
>> +++ b/include/serial.h
>> @@ -73,6 +73,39 @@ enum serial_par {
>> SERIAL_PAR_EVEN
>> };
>>
>> +#define SERIAL_PAR_MASK0x03
>> +#define SERIAL_PAR_SHIFT 0
>> +#define SERIAL_GET_PARITY(config) \
>> + ((config & SERIAL_PAR_MASK) >> SERIAL_PAR_SHIFT)
>> +
>> +enum serial_bits {
>> + SERIAL_5_BITS,
>> + SERIAL_6_BITS,
>> + SERIAL_7_BITS,
>> + SERIAL_8_BITS
>> +};
>> +
>> +#define SERIAL_BITS_MASK 0x0C
>> +#define SERIAL_BITS_SHIFT 2
>
> For consistency:
>
> #define SERIAL_BITS_SHIFT 2
> #define SERIAL_BITS_MASK (0x3 << SERIAL_BITS_SHIFT)
Ok
>
>> +#define SERIAL_GET_BITS(config) \
>> + ((config & SERIAL_BITS_MASK) >> SERIAL_BITS_SHIFT)
>> +
>> +enum serial_stop {
>> + SERIAL_HALF_STOP, /* 0.5 stop bit */
>> + SERIAL_ONE_STOP,/* 1 stop bit */
>> + SERIAL_ONE_HALF_STOP, /* 1.5 stop bit */
>> + SERIAL_TWO_STOP /* 2 stop bit */
>> +};
>> +
>> +#define SERIAL_STOP_MASK 0x30
>> +#define SERIAL_STOP_SHIFT 4
>
> same here
ok
>
>> +#define SERIAL_GET_STOP(config) \
>> + ((config & SERIAL_STOP_MASK) >> SERIAL_STOP_SHIFT)
>> +
>> +#define SERIAL_DEFAULT_CONFIG SERIAL_PAR_NONE << SERIAL_PAR_SHIFT | \
>> + SERIAL_8_BITS << SERIAL_BITS_SHIFT | \
>> + SERIAL_ONE_STOP << SERIAL_STOP_SHIFT
>> +
>> /**
>>* struct struct dm_serial_ops - Driver model serial operations
>>*
>> @@ -150,15 +183,18 @@ struct dm_serial_ops {
>> int (*loop)(struct udevice *dev, int on);
>> #endif
>> /**
>> -* setparity() - Set up the parity
>> +* setconfig() - Set up the uart configuration
>> +* (parity, 5/6/7/8 bits word length, stop bits)
>> *
>> -* Set up a new parity for this device.
>> +* Set up a new config for this device.
>> *
>> * @dev: Device pointer
>> * @parity: parity to use
>> +* @bits: bits number to use
>> +* @stop: stop bits number to use
>> * @return 0 if OK, -ve on error
>> */
>> - int (*setparity)(struct udevice *dev, enum serial_par parity);
>> + int (*setconfig)(struct udevice *dev, u8 serial_config);
>
> Please make this uint instead of u8. There is no point in using u8
> since the compiler will use a register anyway. It can only make code
> size worse, if the compile add masking, etc.
ok
>
>> };
>>
>> /**
>> --
>> 1.9.1
>>
>
> Also you need a serial_setconfig() function call in the uclass so
> people can call it.
I already add serial_setconfig() function call in serial-uclass at the
beginning of this patch ;-)
>
> Perhaps that could have separate parameters for each setting, so that
> the caller does not have to make up a mask? I'm not sure if that is
> better or not.
Don't know what is better, currently only STM32 platforms will use it,
internally we already use this API.
>
> Also we need to call this from sandbox code for testing purposes,
Ok i will add a test for this.
Thanks
Patrice
>
> Regards,
> Simon
>
__
Re: [U-Boot] [PATCH 1/3] arm: exynos4: fix warning of dts
On Tue, Jul 31, 2018 at 04:12:42PM +0900, Minkyu Kang wrote: > remove this warning: avoid_unnecessary_addr_size > > Signed-off-by: Minkyu Kang > --- > arch/arm/dts/exynos4210-pinctrl-uboot.dtsi | 4 > arch/arm/dts/exynos4210-universal_c210.dts | 2 -- > arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi | 4 > 3 files changed, 10 deletions(-) Here and the rest of the series, have you sent the non -uboot.dtsi portions upstream so that we'll not get them back when we re-sync with Linux? Thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ls1046ardb: Add qspi_spl variant to the MAINTAINERS file
Signed-off-by: Tom Rini --- board/freescale/ls1046ardb/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS index 79a2290974f4..e4312c7cb2fd 100644 --- a/board/freescale/ls1046ardb/MAINTAINERS +++ b/board/freescale/ls1046ardb/MAINTAINERS @@ -5,6 +5,7 @@ F: board/freescale/ls1046ardb/ F: board/freescale/ls1046ardb/ls1046ardb.c F: include/configs/ls1046ardb.h F: configs/ls1046ardb_qspi_defconfig +F: configs/ls1046ardb_qspi_spl_config F: configs/ls1046ardb_sdcard_defconfig F: configs/ls1046ardb_emmc_defconfig -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] pico-pi: Add Otavio as maintainer
Update the MAINTAINERS file to list Otavio Salvador as the maintainer for this board. Cc: Otavio Salvador Signed-off-by: Tom Rini --- board/technexion/pico-imx7d/MAINTAINERS | 5 + 1 file changed, 5 insertions(+) diff --git a/board/technexion/pico-imx7d/MAINTAINERS b/board/technexion/pico-imx7d/MAINTAINERS index 3ab1aa6381c3..0755bd836663 100644 --- a/board/technexion/pico-imx7d/MAINTAINERS +++ b/board/technexion/pico-imx7d/MAINTAINERS @@ -4,3 +4,8 @@ S: Maintained F: board/technexion/pico-imx7d/ F: include/configs/pico-imx7d.h F: configs/pico-imx7d_defconfig + +Technexion PICO-PI-IMX7 +M: Otavio Salvador +S: Maintained +F: configs/pico-pi-imx7d_defconfig -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-dm
On Mon, Jul 30, 2018 at 02:10:44PM -0600, Simon Glass wrote: > Hi Tom, > > Here are the binman changes, with the rename of the 'pos' property to > 'offset'. > > > The following changes since commit 0e8a8a311020d317fcfcf594e8e3fb1598134593: > > Merge git://git.denx.de/u-boot-fsl-qoriq (2018-07-27 13:09:30 -0400) > > are available in the Git repository at: > > git://git.denx.de/u-boot-dm.git > > for you to fetch changes up to e824c2422356cc9656d714335fc9b7907c3dace7: > > binman: Adjust _GetPropTree() parameters (2018-07-30 10:28:07 -0600) > NAK, this seems to be introducing some failures: binman: Section '/binman/image1': Symbol '_binman_u_boot_any_prop_pos' in entry '/binman/image1/u-boot-spl': No such property 'pos' /home/trini/work/u-boot/u-boot/Makefile:1240: recipe for target 'u-boot-tegra.bin' failed make[1]: *** [u-boot-tegra.bin] Error 1 make[1]: Leaving directory '/tmp/colibri_t30' Makefile:148: recipe for target 'sub-make' failed make: *** [sub-make] Error 2 -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] common: fdt: Make fdt_del_subnodes/fdt_del_partition static
These functions are only called in this file that's why make them static
to keep static analysers happy.
Signed-off-by: Michal Simek
---
common/fdt_support.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 1bdd03fddab1..34d2bd59c485 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -725,7 +725,7 @@ struct reg_cell {
unsigned int r1;
};
-int fdt_del_subnodes(const void *blob, int parent_offset)
+static int fdt_del_subnodes(const void *blob, int parent_offset)
{
int off, ndepth;
int ret;
@@ -750,7 +750,7 @@ int fdt_del_subnodes(const void *blob, int parent_offset)
return 0;
}
-int fdt_del_partitions(void *blob, int parent_offset)
+static int fdt_del_partitions(void *blob, int parent_offset)
{
const void *prop;
int ndepth = 0;
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 4/4] misc: Add gdsys_ioep driver
Add driver for the IHS IO endpoint on IHS FPGAs.
Signed-off-by: Mario Six
---
v3 -> v4:
* Fixed style violations
* Added full documentation
* Added binding file
* Made res/ret variable names consistent
* Improved error checking and error debug output
v2 -> v3:
No changes
v1 -> v2:
* Switched to regmap usage (instead of fpgamap)
---
.../devicetree/bindings/misc/gdsys,io-endpoint.txt | 20 ++
drivers/misc/Kconfig | 5 +
drivers/misc/Makefile | 1 +
drivers/misc/gdsys_ioep.c | 209 +
drivers/misc/gdsys_ioep.h | 137 ++
5 files changed, 372 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt
create mode 100644 drivers/misc/gdsys_ioep.c
create mode 100644 drivers/misc/gdsys_ioep.h
diff --git a/Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt
b/Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt
new file mode 100644
index 000..db2ff8ca128
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt
@@ -0,0 +1,20 @@
+gdsys IO endpoint of IHS FPGA devices
+
+The IO endpoint of IHS FPGA devices is a packet-based transmission interface
+that allows interconnected gdsys devices to send and receive data over the
+FPGA's main ethernet connection.
+
+Required properties:
+- compatible: must be "gdsys,io-endpoint"
+- reg: describes the address and length of the endpoint's register map (within
+ the FPGA's register space)
+
+Example:
+
+fpga0_ep0 {
+ compatible = "gdsys,io-endpoint";
+ reg = <0x020 0x10
+ 0x320 0x10
+ 0x340 0x10
+ 0x360 0x10>;
+};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index a479e4eec56..89854a4941b 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -284,4 +284,9 @@ config MPC83XX_SERDES
help
Support for serdes found on MPC83xx SoCs.
+config GDSYS_IOEP
+ bool "Enable gdsys IOEP driver"
+ depends on MISC
+ help
+ Support gdsys FPGA's IO endpoint driver.
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 5d2336d915f..b0ef97b6b31 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o
obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
+obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
diff --git a/drivers/misc/gdsys_ioep.c b/drivers/misc/gdsys_ioep.c
new file mode 100644
index 000..7f17095cc58
--- /dev/null
+++ b/drivers/misc/gdsys_ioep.c
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario@gdsys.cc
+ *
+ * based on the cmd_ioloop driver/command, which is
+ *
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eib...@gdsys.cc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+#include "gdsys_ioep.h"
+
+/**
+ * struct gdsys_ioep_priv - Private data structure for IOEP devices
+ * @map: Register map to be used for the device
+ * @state: Flag to keep the current status of the RX control (enabled/disabled)
+ */
+struct gdsys_ioep_priv {
+ struct regmap *map;
+ bool state;
+};
+
+/**
+ * enum last_spec - Convenience enum for read data sanity check
+ * @READ_DATA_IS_LAST: The data to be read should be the final data of the
+ *current packet
+ * @READ_DATA_IS_NOT_LAST: The data to be read should not be the final data of
+ *the current packet
+ */
+enum last_spec {
+ READ_DATA_IS_LAST,
+ READ_DATA_IS_NOT_LAST,
+};
+
+static int gdsys_ioep_set_receive(struct udevice *dev, bool val)
+{
+ struct gdsys_ioep_priv *priv = dev_get_priv(dev);
+ u16 state;
+
+ priv->state = !priv->state;
+
+ if (val)
+ state = CTRL_PROC_RECEIVE_ENABLE;
+ else
+ state = ~CTRL_PROC_RECEIVE_ENABLE;
+
+ gdsys_ioep_set(priv->map, tx_control, state);
+
+ if (val) {
+ /* Set device address to dummy 1 */
+ gdsys_ioep_set(priv->map, device_address, 1);
+ }
+
+ return !priv->state;
+}
+
+static int gdsys_ioep_send(struct udevice *dev, int offset,
+ const void *buf, int size)
+{
+ struct gdsys_ioep_priv *priv = dev_get_priv(dev);
+ int k;
+ u16 *p = (u16 *)buf;
+
+ for (k = 0; k < size; ++k)
+ gdsys_ioep_set(priv->map, transmit_data, *(p++));
+
+ gdsys_ioep_set(priv->map, tx_control, CTRL_PROC_RECEIVE_ENABLE |
+ CTRL_FLUSH_TRANSMIT_BUFFER);
+
+ return 0;
+}
+
+/**
+ * receive_byte_buffer() - Read data from a IOEP device
+ * @dev: The IOEP device to r
[U-Boot] [PATCH v4 3/4] test: Add tests for misc uclass
Add a set of tests for the misc uclass.
Signed-off-by: Mario Six
---
v3 -> v4:
New in v4
---
arch/sandbox/dts/test.dts | 4 ++
drivers/misc/Makefile | 2 +-
drivers/misc/misc_sandbox.c | 133
test/dm/Makefile| 1 +
test/dm/misc.c | 83 +++
5 files changed, 222 insertions(+), 1 deletion(-)
create mode 100644 drivers/misc/misc_sandbox.c
create mode 100644 test/dm/misc.c
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 137679abea9..c41375ac225 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -283,6 +283,10 @@
mbox-names = "other", "test";
};
+ misc-test {
+ compatible = "sandbox,misc_sandbox";
+ };
+
mmc2 {
compatible = "sandbox,mmc";
};
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index e2c2b763b7a..5d2336d915f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -39,7 +39,7 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
endif
endif
-obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
+obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
diff --git a/drivers/misc/misc_sandbox.c b/drivers/misc/misc_sandbox.c
new file mode 100644
index 000..e4164f76fba
--- /dev/null
+++ b/drivers/misc/misc_sandbox.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario@gdsys.cc
+ */
+
+#include
+#include
+#include
+
+struct misc_sandbox_priv {
+ u8 mem[128];
+ ulong last_ioctl;
+ bool enabled;
+};
+
+int misc_sandbox_read(struct udevice *dev, int offset, void *buf, int size)
+{
+ struct misc_sandbox_priv *priv = dev_get_priv(dev);
+
+ memcpy(buf, priv->mem + offset, size);
+
+ return 0;
+}
+
+int misc_sandbox_write(struct udevice *dev, int offset, const void *buf,
+ int size)
+{
+ struct misc_sandbox_priv *priv = dev_get_priv(dev);
+
+ memcpy(priv->mem + offset, buf, size);
+
+ return 0;
+}
+
+int misc_sandbox_ioctl(struct udevice *dev, unsigned long request, void *buf)
+{
+ struct misc_sandbox_priv *priv = dev_get_priv(dev);
+
+ priv->last_ioctl = request;
+
+ return 0;
+}
+
+int misc_sandbox_call(struct udevice *dev, int msgid, void *tx_msg,
+ int tx_size, void *rx_msg, int rx_size)
+{
+ struct misc_sandbox_priv *priv = dev_get_priv(dev);
+
+ if (msgid == 0) {
+ int num = *(int *)tx_msg;
+
+ switch (num) {
+ case 0:
+ strncpy(rx_msg, "Zero", rx_size);
+ break;
+ case 1:
+ strncpy(rx_msg, "One", rx_size);
+ break;
+ case 2:
+ strncpy(rx_msg, "Two", rx_size);
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ if (msgid == 1) {
+ int num = *(int *)tx_msg;
+
+ switch (num) {
+ case 0:
+ strncpy(rx_msg, "Forty", rx_size);
+ break;
+ case 1:
+ strncpy(rx_msg, "Forty-one", rx_size);
+ break;
+ case 2:
+ strncpy(rx_msg, "Forty-two", rx_size);
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ if (msgid == 2)
+ memcpy(rx_msg, &priv->last_ioctl, sizeof(priv->last_ioctl));
+
+ if (msgid == 3)
+ memcpy(rx_msg, &priv->enabled, sizeof(priv->enabled));
+
+ return 0;
+}
+
+int misc_sandbox_set_enabled(struct udevice *dev, bool val)
+{
+ struct misc_sandbox_priv *priv = dev_get_priv(dev);
+
+ priv->enabled = !priv->enabled;
+
+ return 0;
+}
+
+static const struct misc_ops misc_sandbox_ops = {
+ .read = misc_sandbox_read,
+ .write = misc_sandbox_write,
+ .ioctl = misc_sandbox_ioctl,
+ .call = misc_sandbox_call,
+ .set_enabled = misc_sandbox_set_enabled,
+};
+
+int misc_sandbox_probe(struct udevice *dev)
+{
+ struct misc_sandbox_priv *priv = dev_get_priv(dev);
+
+ priv->enabled = true;
+
+ return 0;
+}
+
+static const struct udevice_id misc_sandbox_ids[] = {
+ { .compatible = "sandbox,misc_sandbox" },
+ { }
+};
+
+U_BOOT_DRIVER(misc_sandbox) = {
+ .name = "misc_sandbox",
+ .id = UCLASS_MISC,
+ .ops= &misc_sandbox_ops,
+ .of_match = misc_sandbox_ids,
+ .probe = misc_sandbox_probe,
+ .priv_auto_alloc
[U-Boot] [PATCH v4 2/4] misc: uclass: Add enable/disable function
Add generic enable/disable function to the misc uclass.
Reviewed-by: Simon Glass
Signed-off-by: Mario Six
---
v3 -> v4:
No changes
v2 -> v3:
* Now return old state from misc_set_enabled
v1 -> v2:
* Merged the two functions into one function
* Explained the semantics of enabling/disabling more throughly
---
drivers/misc/misc-uclass.c | 10 ++
include/misc.h | 27 +++
2 files changed, 37 insertions(+)
diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c
index 0dc62d00344..f240cda5c05 100644
--- a/drivers/misc/misc-uclass.c
+++ b/drivers/misc/misc-uclass.c
@@ -55,6 +55,16 @@ int misc_call(struct udevice *dev, int msgid, void *tx_msg,
int tx_size,
return ops->call(dev, msgid, tx_msg, tx_size, rx_msg, rx_size);
}
+int misc_set_enabled(struct udevice *dev, bool val)
+{
+ const struct misc_ops *ops = device_get_ops(dev);
+
+ if (!ops->set_enabled)
+ return -ENOSYS;
+
+ return ops->set_enabled(dev, val);
+}
+
UCLASS_DRIVER(misc) = {
.id = UCLASS_MISC,
.name = "misc",
diff --git a/include/misc.h b/include/misc.h
index ce2f05dfd4c..50515852b25 100644
--- a/include/misc.h
+++ b/include/misc.h
@@ -60,6 +60,23 @@ int misc_call(struct udevice *dev, int msgid, void *tx_msg,
int tx_size,
void *rx_msg, int rx_size);
/**
+ * misc_set_enabled() - Enable or disable a device.
+ * @dev: the device to enable or disable.
+ * @val: the flag that tells the driver to either enable or disable the device.
+ *
+ * The semantics of "disable" and "enable" should be understood here as
+ * activating or deactivating the device's primary function, hence a "disabled"
+ * device should be dormant, but still answer to commands and queries.
+ *
+ * A probed device may start in a disabled or enabled state, depending on the
+ * driver and hardware.
+ *
+ * Return: -ve on error, 0 if the previous state was "disabled", 1 if the
+ *previous state was "enabled"
+ */
+int misc_set_enabled(struct udevice *dev, bool val);
+
+/*
* struct misc_ops - Driver model Misc operations
*
* The uclass interface is implemented by all miscellaneous devices which
@@ -112,6 +129,16 @@ struct misc_ops {
*/
int (*call)(struct udevice *dev, int msgid, void *tx_msg, int tx_size,
void *rx_msg, int rx_size);
+ /**
+* Enable or disable a device, optional.
+* @dev: the device to enable.
+* @val: the flag that tells the driver to either enable or disable the
+* device.
+*
+* Return: -ve on error, 0 if the previous state was "disabled", 1 if
+* the previous state was "enabled"
+*/
+ int (*set_enabled)(struct udevice *dev, bool val);
};
#endif /* _MISC_H_ */
--
2.11.0
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[U-Boot] [PATCH v4 1/4] misc: docs: Fix comments in misc.h
The comments in misc.h are not in kernel-doc format. Correct the format.
Signed-off-by: Mario Six
---
v3 -> v4:
No changes
v2 -> v3:
New in v3
---
include/misc.h | 84 ++
1 file changed, 44 insertions(+), 40 deletions(-)
diff --git a/include/misc.h b/include/misc.h
index 68f8e64d61a..ce2f05dfd4c 100644
--- a/include/misc.h
+++ b/include/misc.h
@@ -6,38 +6,47 @@
#ifndef _MISC_H_
#define _MISC_H_
-/*
- * Read the device to buffer, optional.
- *
+/**
+ * misc_read() - Read the device to buffer, optional.
* @dev: the device
* @offset: offset to read the device
* @buf: pointer to data buffer
* @size: data size in bytes to read the device
- * @return: 0 if OK, -ve on error
+ *
+ * Return: 0 if OK, -ve on error
*/
int misc_read(struct udevice *dev, int offset, void *buf, int size);
-/*
- * Write buffer to the device, optional.
- *
+
+/**
+ * misc_write() - Write buffer to the device, optional.
* @dev: the device
* @offset: offset to write the device
* @buf: pointer to data buffer
* @size: data size in bytes to write the device
- * @return: 0 if OK, -ve on error
+ *
+ * Return: 0 if OK, -ve on error
*/
int misc_write(struct udevice *dev, int offset, void *buf, int size);
-/*
- * Assert command to the device, optional.
- *
+
+/**
+ * misc_ioctl() - Assert command to the device, optional.
* @dev: the device
* @request: command to be sent to the device
* @buf: pointer to buffer related to the request
- * @return: 0 if OK, -ve on error
+ *
+ * Return: 0 if OK, -ve on error
*/
int misc_ioctl(struct udevice *dev, unsigned long request, void *buf);
-/*
- * Send a message to the device and wait for a response.
+/**
+ * misc_call() - Send a message to the device and wait for a response.
+ * @dev: the device.
+ * @msgid: the message ID/number to send.
+ * @tx_msg: the request/transmit message payload.
+ * @tx_size: the size of the buffer pointed at by tx_msg.
+ * @rx_msg: the buffer to receive the response message payload. May be NULL if
+ * the caller only cares about the error code.
+ * @rx_size: the size of the buffer pointed at by rx_msg.
*
* The caller provides the message type/ID and payload to be sent.
* The callee constructs any message header required, transmits it to the
@@ -45,66 +54,61 @@ int misc_ioctl(struct udevice *dev, unsigned long request,
void *buf);
* strips any message header from the response, and returns the error code
* (or a parsed version of it) and the response message payload.
*
- * @dev: the device.
- * @msgid: the message ID/number to send.
- * tx_msg: the request/transmit message payload.
- * tx_size: the size of the buffer pointed at by tx_msg.
- * rx_msg: the buffer to receive the response message payload. May be NULL if
- * the caller only cares about the error code.
- * rx_size: the size of the buffer pointed at by rx_msg.
- * @return the response message size if OK, -ve on error
+ * Return: the response message size if OK, -ve on error
*/
int misc_call(struct udevice *dev, int msgid, void *tx_msg, int tx_size,
void *rx_msg, int rx_size);
-/*
+/**
* struct misc_ops - Driver model Misc operations
*
* The uclass interface is implemented by all miscellaneous devices which
* use driver model.
*/
struct misc_ops {
- /*
+ /**
* Read the device to buffer, optional.
-*
* @dev: the device
* @offset: offset to read the device
* @buf: pointer to data buffer
* @size: data size in bytes to read the device
-* @return: 0 if OK, -ve on error
+*
+* Return: 0 if OK, -ve on error
*/
int (*read)(struct udevice *dev, int offset, void *buf, int size);
- /*
+
+ /**
* Write buffer to the device, optional.
-*
* @dev: the device
* @offset: offset to write the device
* @buf: pointer to data buffer
* @size: data size in bytes to write the device
-* @return: 0 if OK, -ve on error
+*
+* Return: 0 if OK, -ve on error
*/
int (*write)(struct udevice *dev, int offset, const void *buf,
int size);
- /*
+ /**
* Assert command to the device, optional.
-*
* @dev: the device
* @request: command to be sent to the device
* @buf: pointer to buffer related to the request
-* @return: 0 if OK, -ve on error
+*
+* Return: 0 if OK, -ve on error
*/
int (*ioctl)(struct udevice *dev, unsigned long request, void *buf);
- /*
+
+ /**
* Send a message to the device and wait for a response.
-*
* @dev: the device
* @msgid: the message ID/number to send
-* tx_msg: the request/transmit message payload
-* tx_size: the size of the buffer pointed at by tx_msg
-* rx_msg: the buffer to receive the respons
Re: [U-Boot] [ANN] U-Boot v2018.09-rc1 released
On Tue, Jul 31, 2018 at 12:48:03PM +0200, Michal Simek wrote: > Hi Tom, > > On 31.7.2018 03:49, Tom Rini wrote: > > Hey all, > > > > So it's release day and I've put up v2018.09-rc1. The merge window is > > now closed and I've updated git and the tarballs are also up now. > > > > That said, there's a few things that I expect to come in and I hope > > soon. There's the SPI-NAND series. There's EFI support to Sandbox. > > And there may be at least some amount of the FAT improvement series. > > > > There's also some amount of cleaning up of my patch queue that's still > > needed. > > > > I will follow the usual rule of an -rc every other Monday > > and we're looking at release on September 10th, 2018. > > > > Thanks all! > > FYI: Just wanted to let you know that tag name and tag description is > correct but the Makefile patch subject you have created contains 2017 > year instead of 2018. Bah. I'm just glad I only typo the year once every few years. Thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] smbios: fix checkstyle warning
On 30 July 2018 at 05:22, Christian Gmeiner wrote: > Fixes the following checkstyle warning: > > WARNING: Missing a blank line after declarations > + int tmp = smbios_write_funcs[i]((ulong *)&addr, handle++); > + max_struct_size = max(max_struct_size, tmp); > > Signed-off-by: Christian Gmeiner > --- > lib/smbios.c | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] sata: fix sata_Probe return value check
On 27 July 2018 at 17:45, Troy Kisky wrote: > > sata_probe returns 1 for failure, so don't checkout for < 0 > > fixes: f19f1ecb6025 dm: sata: Support driver model with the 'sata' command > > Signed-off-by: Troy Kisky > Thanks! Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 2/2] serial: stm32: Replace setparity by setconfig
Hi Patrice, On 30 July 2018 at 09:23, Patrice Chotard wrote: > Replace stm32_serial_setparity by stm32_serial_setconfig > which allows to set serial bits number, parity and stop > bits number. > Only parity setting is implemented. > > Signed-off-by: Patrick Delaunay > Signed-off-by: Patrice Chotard > --- > > drivers/serial/serial_stm32.c | 21 +++-- > 1 file changed, 15 insertions(+), 6 deletions(-) Looks OK, apart from changes requested in the first patch. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
