Re: [U-Boot] [PATCH] gpio: xilinx: Add support for using label property
On 5.8.2018 09:56, Stefan Herbrechtsmeier wrote:
> Am 02.08.2018 um 13:31 schrieb Michal Simek:
>> Add support for reading label property from DT and set up bank name
>> based on that. If label property is not present full device node name is
>> used.
>>
>> Signed-off-by: Michal Simek
>> ---
>>
>> drivers/gpio/xilinx_gpio.c | 14 --
>> drivers/gpio/zynq_gpio.c | 14 --
>> 2 files changed, 24 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c
>> index cccfa7561739..da50d1634570 100644
>> --- a/drivers/gpio/xilinx_gpio.c
>> +++ b/drivers/gpio/xilinx_gpio.c
>> @@ -224,8 +224,18 @@ static int xilinx_gpio_probe(struct udevice *dev)
>> {
>> struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
>> struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
>> -
>> - uc_priv->bank_name = dev->name;
>> + const void *label_ptr;
>> + void *label_c;
>> + int size;
>> +
>> + label_ptr = dev_read_prop(dev, "label", &size);
>> + if (label_ptr) {
>> + label_c = calloc(1, size);
>> + memcpy(label_c, label_ptr, size);
>> + uc_priv->bank_name = label_c;
>
> This could be simplified by the function strdup.
I have sent v2 with this change. Let's make it clean.
Thanks,
Michal
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2] gpio: xilinx: Add support for using label property
Add support for reading label property from DT and set up bank name
based on that. If label property is not present full device node name is
used.
Signed-off-by: Michal Simek
---
Changes in v2:
- Use strdup
drivers/gpio/xilinx_gpio.c | 10 +-
drivers/gpio/zynq_gpio.c | 10 +-
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c
index fc460c343efe..2389abee3777 100644
--- a/drivers/gpio/xilinx_gpio.c
+++ b/drivers/gpio/xilinx_gpio.c
@@ -241,8 +241,16 @@ static int xilinx_gpio_probe(struct udevice *dev)
struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ const void *label_ptr;
- uc_priv->bank_name = dev->name;
+ label_ptr = dev_read_prop(dev, "label", NULL);
+ if (label_ptr) {
+ uc_priv->bank_name = strdup(label_ptr);
+ if (!uc_priv->bank_name)
+ return -ENOMEM;
+ } else {
+ uc_priv->bank_name = dev->name;
+ }
uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];
diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index 6fbaafb3fa3c..55a5cba0688e 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -336,8 +336,16 @@ static int zynq_gpio_probe(struct udevice *dev)
{
struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ const void *label_ptr;
- uc_priv->bank_name = dev->name;
+ label_ptr = dev_read_prop(dev, "label", NULL);
+ if (label_ptr) {
+ uc_priv->bank_name = strdup(label_ptr);
+ if (!uc_priv->bank_name)
+ return -ENOMEM;
+ } else {
+ uc_priv->bank_name = dev->name;
+ }
if (platdata->p_data)
uc_priv->gpio_count = platdata->p_data->ngpio;
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] gpio: xilinx: Return 0 from xilinx_gpio_set_value
.set_value functions have no specified return value and gpio_uclass is not working with it too. But this patch is returning 0 to be in sync with others DM gpio drivers. Reported-by: Stefan Herbrechtsmeier Signed-off-by: Michal Simek --- drivers/gpio/xilinx_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c index 2584b4b3e648..2389abee3777 100644 --- a/drivers/gpio/xilinx_gpio.c +++ b/drivers/gpio/xilinx_gpio.c @@ -81,7 +81,7 @@ static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset, priv->output_val[bank] = val; - return val; + return 0; }; static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] boot partition access at HS200 speed in eMMC
Hi, +JJ, Jaehoon Chung I had CCd them in my original mail but they seem to have been dropped in the U-boot list. On Thursday 02 August 2018 03:14 PM, Faiz Abbas wrote: > Hi Everyone, > > After the following patch from JJ, U-boot shifts to a lower speed mode > from HS200 when accessing a boot partition. > > 01298da31d mmc: Change mode when switching to a boot partition > > I have looked through the JESD84-B51 spec for eMMC card and don't see it > say anywhere that boot0 partition cannot be accessed in HS200 modes. > > In practice, I have seen timeouts sometimes when I try to write to the > boot partition in HS200 mode on a dra7xx-evm in U-boot but not > consistently (one would expect if such a thing was forbidden by the spec > then it wouldn't work at all). > > Can anyone point to a documentation that says that boot partition cannot > be accessed in HS200 mode? Has anyone else observed failures before this > patch? > > I was able to access the boot0 partition in kernel in HS200 mode (log > below). Unless there is code to fallback to a lower speed in kernel also > (which doesn't seem to be the case from a simple searching of the code), > this should prove that boot partitions can be accessed in HS200 speed mode. > > Here is the log: > https://pastebin.ubuntu.com/p/W3SB4N3rfn/ > > Thanks, > Faiz > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Two CRC32 implementation in U-Boot, why?
On Wed, Aug 1, 2018 at 9:50 PM, Heinrich Schuchardt wrote: > > > On 08/01/2018 02:13 PM, Bin Meng wrote: >> Hi, >> >> Currently it seems that we have two CRC32 implementation in U-Boot. >> Two headers files are provided. >> >> 1. include/linux/crc32.h >> The implementation is drivers/mtd/ubi/crc32.c. >> Codes that use this implementation include: >> >> drivers/mtd/ubi/* >> drivers/mtd/ubispl/* >> fs/ubifs/* >> >> 2. include/u-boot/crc.h >> The implementation is lib/crc32.c >> Codes that use this implementation include: >> >> fs/btrfs/hash.c >> tools/* >> common/hash.c >> common/image.c >> common/image-fit.c >> lib/efi_loader/efi_boottime.c >> >> It looks that include/linux/crc32.h was originally imported from Linux >> kernel's include/linux/crc32.h, but the implementation in Linux >> kernel's lib/crc32.c was not imported to U-Boot's lib/crc32.c but to >> drivers/mtd/ubi/crc32.c. Why? >> >> Somehow U-Boot lib/crc32.c uses another different implementation from zlib. >> >> This is a mess. For example if I include both headers in one C file, >> it won't compile. >> >> Can we clean this up? > > Thanks for pointing this out. > > The drivers/mtd/ubi/crc32.c is based on an elder version of Linux. > > When looking at the function signatures I am not happy with > include/u-boot/crc.h > uint32_t crc32 (uint32_t, const unsigned char *, uint) > The last parameter should be size_t. Otherwise the CRC may be wrong on > 64bit systems. > > The two crc32 implementations do not have the same result on a > low-endian system: > > crc32_le(0, 'U-Boot', 6) = a289ac17 > crc32(0, 'U-Boot', 6) = 134b0db4. > > According to the comments in in include/linux/crc32.h the result of > crc32_le is in bit reversed order. > > Conflicting definitions could be avoided by removing #define crc32() in > include/linux/crc32.h and adjusting the ubi code accordingly. > I would like to see one CRC32 implementation to support all use cases in U-Boot. Allowing two different implementation just confuses people. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARM: omap3: evm: Enable CONFIG_BLK and misc. cleanup
This commit enables CONFIG_BLK and removes USB_STORAGE which is awaiting proper implementation for current U-Boot interfaces. Additionally the console selection is now handled by Kconfig and no longer needs to be in the config header. CONFIG_SYS_MALLOC_F_LEN=0x2000 was added to sync with other boards. CONFIG_SPL_BLK and CONFIG_SPL_DM_MMC are disabled because they currently do not allow the OMAP3-EVM (OMAP34XX) to actually boot. Signed-off-by: Derald D. Woods --- configs/omap3_evm_defconfig | 9 +++-- include/configs/omap3_evm.h | 3 --- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index cd517b418d..c53f439618 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_TEXT_BASE=0x8010 +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_OMAP3_EVM=y CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="omap3-evm" @@ -38,6 +39,10 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SPL_DM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x8200 +CONFIG_BLK=y +# CONFIG_SPL_BLK is not set +CONFIG_DM_MMC=y +# CONFIG_SPL_DM_MMC is not set CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y @@ -48,15 +53,15 @@ CONFIG_NETDEVICES=y CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x2C00 CONFIG_SMC911X_32_BIT=y +CONFIG_CONS_INDEX=1 CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_OMAP3=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_OMAP2PLUS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 34418309cb..6e5c3005ce 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -33,9 +33,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG -/* Override OMAP3 serial console configuration */ -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 - /* NAND */ #if defined(CONFIG_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Unable to boot evb-ast2500
Hello, I am attempting to boot evb-ast2500 in Qemu before flashing it to a system. It doesn't get past the DRAM step, due to getting stuck endlessly looping in some libfdt code. With some debugging turned on, I get this: OF: translating address: 0040781e OF: parent translation for: OF: one level translation: 0040781e OF: parent translation for: OF: one level translation: 0040781e OF: translating address: 00206e1e U-Boot 2018.09-rc1-00096-gbb694d4e898b-dirty (Aug 06 2018 - 12:27:22 +0930) Model: Aspeed BMC DRAM: OF: translating address: 6e1e OF: translating address: 00026e1e OF: translating address: 0050781e OF: parent translation for: OF: one level translation: 0050781e OF: parent translation for: OF: one level translation: 0050781e Watchdog timer expired. And then the watchdog causes the system to reboot. The build is master as of gbb694d4e898b, with the addition of some #define DEBUG. I don't think this is a qemu issue. If it is, I can work on fixing qemu, but I need some help on understanding what u-boot is doing. There's a big pause before the U-Boot banner, and again after showing 'DRAM: 'before getting any of the OF messages. If I get gdb to show me a backtrace at this point: #0 0x0001e858 in __fswab32 (x=) at include/linux/byteorder/swab.h:114 #1 fdt_offset_ptr (fdt=fdt@entry=0x39370, offset=offset@entry=6444, len=len@entry=4) at lib/libfdt/../../scripts/dtc/libfdt/fdt.c:86 #2 0x0001e9b4 in fdt_next_tag (fdt=fdt@entry=0x39370, startoffset=startoffset@entry=6440, nextoffset=0x1e726d44, nextoffset@entry=0x1e726d3c) at lib/libfdt/../../scripts/dtc/libfdt/fdt.c:120 #3 0x0001eae4 in fdt_next_node (fdt=fdt@entry=0x39370, offset=6440, depth=0x1e726d5c, depth@entry=0x1e726d54) at lib/libfdt/../../scripts/dtc/libfdt/fdt.c:176 #4 0x000205cc in fdt_supernode_atdepth_offset (fdt=0x39370, nodeoffset=14748, supernodedepth=0, nodedepth=0x0 <_start>) at lib/libfdt/fdt_ro.c:443 #5 0x00011608 in ofnode_get_parent (node=..., node@entry=...) at include/dm/ofnode.h:94 #6 0x000113dc in regmap_init_mem (node=..., mapp=0x0 <_start>, mapp@entry=0x1e726dbc) at drivers/core/regmap.c:63 #7 0x14e0 in ast2500_sdrammc_ofdata_to_platdata (dev=0x1e7273c4) at include/dm/read.h:38 #8 0xfc88 in device_probe (dev=dev@entry=0x1e7273c4) at drivers/core/device.c:399 #9 0x000108c0 in uclass_get_device_tail (dev=0x1e7273c4, ret=, devp=0x1e726e0c) at drivers/core/uclass.c:397 #10 0x00010900 in uclass_get_device (id=id@entry=UCLASS_RAM, index=index@entry=0, devp=0x1e726e0c, devp@entry=0x1e726e04) at drivers/core/uclass.c:413 #11 0x1ab0 in dram_init () at arch/arm/mach-aspeed/ast2500-board.c:69 #12 0x0001b834 in initcall_run_list (init_sequence=init_sequence@entry=0x29344 ) at lib/initcall.c:30 #13 0x854c in board_init_f (boot_flags=) at common/board_f.c:900 #14 0x0664 in _main () at arch/arm/lib/crt0.S:86 Cheers, Joel -- To reproduce in qemu, build qemu master for ARM: git://git.qemu-project.org/qemu && cd qemu ./configure --target-list=arm-softmmu make build a 32MB image from u-boot.bin: dd if=/dev/zero of=test.img bs=1M count=32 dd if=u-boot.bin of=test.img conv=notrunc boot it: arm-softmmu/qemu-system-arm -M ast2500-evb -m 512 -nographic -drive file=test.img,format=raw,if=mtd -serial stdio -monitor pty ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V2 1/4] power-domain: add dummy functions when CONFIG_POWER_DOMAIN not defined
Hi Simon, Jaehoon Would you pick up this patchset? https://patchwork.ozlabs.org/patch/949962/ https://patchwork.ozlabs.org/patch/949963/ https://patchwork.ozlabs.org/patch/949964/ https://patchwork.ozlabs.org/patch/949965/ Thanks, Peng. > -Original Message- > From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass > Sent: 2018年7月30日 21:27 > To: Peng Fan > Cc: Jaehoon Chung ; U-Boot Mailing List > ; dl-linux-imx > Subject: Re: [PATCH V2 1/4] power-domain: add dummy functions when > CONFIG_POWER_DOMAIN not defined > > On 26 July 2018 at 20:20, Peng Fan wrote: > > Add dummy functions when CONFIG_POWER_DOMAIN not defined. > > > > Signed-off-by: Peng Fan > > --- > > > > V2: Use CONFIG_IS_ENABLED > > > > include/power-domain.h | 28 > > 1 file changed, 28 insertions(+) > > Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V2] drivers: regulator: fixed: add u-boot, off-on-delay-us
Hi, Would anyone pick up this patch? Thanks, Peng. > -Original Message- > From: Tom Rini [mailto:tr...@konsulko.com] > Sent: 2018年7月27日 1:06 > To: Peng Fan > Cc: s...@chromium.org; yamada.masah...@socionext.com; > u-boot@lists.denx.de > Subject: Re: [PATCH V2] drivers: regulator: fixed: add u-boot,off-on-delay-us > > On Thu, Jul 26, 2018 at 01:59:20PM +, Peng Fan wrote: > > > > -Original Message- > > > From: Peng Fan > > > Sent: 2018年7月26日 19:47 > > > To: s...@chromium.org; tr...@konsulko.com > > > Cc: yamada.masah...@socionext.com; u-boot@lists.denx.de; Peng Fan > > > > > > Subject: [PATCH V2] drivers: regulator: fixed: add > > > u-boot,off-on-delay-us > > > > > > Add u-boot,off-on-delay-us for fixed regulator. > > > > > > Depends on board design, the gpio regulator sometimes connects with > > > a big capacitance. When need to off, then on the regulator, if there > > > is no enough delay, the voltage does not drop to 0, so introduce this > > > property > to handle such case. > > > > > > Signed-off-by: Peng Fan > > > Reviewed-by: Simon Glass > > > Cc: Masahiro Yamada > > > --- > > > > > > V2: > > > Moved device tree bindings to new directory. > > > Simon, I keep you reviewed by tag. Thanks. > > > > Sorry, this patchset should be V3 version. > > > > Tom, should I resend a v3 out? Or you could apply this one? > > Barring further comments from people, you can just keep this version. > FWIW, I think that if people register with patchwork they can manage the state > of their own patches and that always helps keep me from failing to notice > something / grab the wrong version :) Thanks! > > -- > Tom ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 27/32] serial: lpuart: Enable RX and TX FIFO
From: Ye Li
Enable the RX and TX FIFO in LPUART driver to avoid the input lost
during u-boot boot up.
Signed-off-by: Ye Li
Acked-by: Peng Fan
---
drivers/serial/serial_lpuart.c | 33 ++---
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index c14a8105c9..b28f7cf68d 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -40,6 +40,12 @@
#define CTRL_TE(1 << 19)
#define CTRL_RE(1 << 18)
+#define FIFO_RXFLUSH BIT(14)
+#define FIFO_TXFLUSH BIT(15)
+#define FIFO_TXSIZE_MASK 0x70
+#define FIFO_TXSIZE_OFF4
+#define FIFO_RXSIZE_MASK 0x7
+#define FIFO_RXSIZE_OFF0
#define FIFO_TXFE 0x80
#ifdef CONFIG_ARCH_IMX8
#define FIFO_RXFE 0x08
@@ -47,7 +53,7 @@
#define FIFO_RXFE 0x40
#endif
-#define WATER_TXWATER_OFF 1
+#define WATER_TXWATER_OFF 0
#define WATER_RXWATER_OFF 16
DECLARE_GLOBAL_DATA_PTR;
@@ -318,15 +324,28 @@ static int _lpuart32_serial_tstc(struct
lpuart_serial_platdata *plat)
static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)
{
struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
- u32 ctrl;
+ u32 val, tx_fifo_size;
- lpuart_read32(plat->flags, &base->ctrl, &ctrl);
- ctrl &= ~CTRL_RE;
- ctrl &= ~CTRL_TE;
- lpuart_write32(plat->flags, &base->ctrl, ctrl);
+ lpuart_read32(plat->flags, &base->ctrl, &val);
+ val &= ~CTRL_RE;
+ val &= ~CTRL_TE;
+ lpuart_write32(plat->flags, &base->ctrl, val);
lpuart_write32(plat->flags, &base->modir, 0);
- lpuart_write32(plat->flags, &base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
+
+ lpuart_read32(plat->flags, &base->fifo, &val);
+ tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
+ /* Set the TX water to half of FIFO size */
+ if (tx_fifo_size > 1)
+ tx_fifo_size = tx_fifo_size >> 1;
+
+ /* Set RX water to 0, to be triggered by any receive data */
+ lpuart_write32(plat->flags, &base->water,
+ (tx_fifo_size << WATER_TXWATER_OFF));
+
+ /* Enable TX and RX FIFO */
+ val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
+ lpuart_write32(plat->flags, &base->fifo, val);
lpuart_write32(plat->flags, &base->match, 0);
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 31/32] arm: dts: introduce dtsi for i.MX8QXP
Introduce dtsi for i.MX8QXP, since there is other variants i.MX8DX(P),
so add them there, because i.MX8QXP includes the dtsi of them.
Signed-off-by: Peng Fan
---
arch/arm/dts/fsl-imx8-ca35.dtsi | 66 ++
arch/arm/dts/fsl-imx8dx.dtsi| 444
arch/arm/dts/fsl-imx8dxp.dtsi | 11 +
arch/arm/dts/fsl-imx8qxp.dtsi | 51 +
4 files changed, 572 insertions(+)
create mode 100644 arch/arm/dts/fsl-imx8-ca35.dtsi
create mode 100644 arch/arm/dts/fsl-imx8dx.dtsi
create mode 100644 arch/arm/dts/fsl-imx8dxp.dtsi
create mode 100644 arch/arm/dts/fsl-imx8qxp.dtsi
diff --git a/arch/arm/dts/fsl-imx8-ca35.dtsi b/arch/arm/dts/fsl-imx8-ca35.dtsi
new file mode 100644
index 00..28bc32c8b7
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8-ca35.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include
+
+/{
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ /* We have 1 clusters having 4 Cortex-A35 cores */
+ A35_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+
+ A35_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+
+ A35_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+
+ A35_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+
+ A35_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = ;
+ interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc401>;
+ cpu_off = <0xc402>;
+ cpu_on= <0xc403>;
+ };
+};
diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
new file mode 100644
index 00..e84f7cf000
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8dx.dtsi
@@ -0,0 +1,444 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include "fsl-imx8-ca35.dtsi"
+#include
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ model = "Freescale i.MX8DX";
+ compatible = "fsl,imx8dx", "fsl,imx8qxp";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &lpuart0;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x 0x8000 0 0x4000>;
+ /* DRAM space - 1, size : 1 GB DRAM */
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+* reserved-memory layout
+* 0x8800_ ~ 0x8FFF_ is reserved for M4
+* Shouldn't be used at A core and Linux side.
+*
+*/
+ decoder_boot: decoder_boot@0x8400 {
+ no-map;
+ reg = <0 0x8400 0 0x200>;
+ };
+ encoder_boot: encoder_boot@0x8600 {
+ no-map;
+ reg = <0 0x8600 0 0x200>;
+ };
+ rpmsg_reserved: rpmsg@0x9000 {
+ no-map;
+ reg = <0 0x9000 0 0x40>;
+ };
+ decoder_rpc: decoder_rpc@0x9040 {
+ no-map;
+ reg = <0 0x9040 0 0x100>;
+ };
+ encoder_rpc: encoder_rpc@0x9140 {
+ no-map;
+ reg = <0 0x9140 0 0x100>;
+ };
[U-Boot] [PATCH V3 28/32] serial: lpuart: support uclass clk api
Modify most APIs to use udevice as the first param, then
it will be easy to get the clk reference by using udevice pointer.
Use uclass api to get lpuart clk when CONFIG_CLK enabled.
Signed-off-by: Peng Fan
---
drivers/serial/serial_lpuart.c | 78 --
1 file changed, 59 insertions(+), 19 deletions(-)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index b28f7cf68d..3887c3d1c8 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -104,6 +105,27 @@ u32 __weak get_lpuart_clk(void)
return CONFIG_SYS_CLK_FREQ;
}
+ulong get_lpuart_clk_rate(struct udevice *dev)
+{
+ struct clk per_clk;
+ ulong rate;
+ int ret;
+
+ ret = clk_get_by_name(dev, "per", &per_clk);
+ if (ret) {
+ dev_err(dev, "Failed to get per clk: %d\n", ret);
+ return ret;
+ }
+
+ rate = clk_get_rate(&per_clk);
+ if ((long)rate <= 0) {
+ dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
+ return ret;
+ }
+
+ return rate;
+}
+
static bool is_lpuart32(struct udevice *dev)
{
struct lpuart_serial_platdata *plat = dev->platdata;
@@ -111,13 +133,19 @@ static bool is_lpuart32(struct udevice *dev)
return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
}
-static void _lpuart_serial_setbrg(struct lpuart_serial_platdata *plat,
+static void _lpuart_serial_setbrg(struct udevice *dev,
int baudrate)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl *base = plat->reg;
- u32 clk = get_lpuart_clk();
+ u32 clk;
u16 sbr;
+ if (IS_ENABLED(CONFIG_CLK))
+ clk = get_lpuart_clk_rate(dev);
+ else
+ clk = get_lpuart_clk();
+
sbr = (u16)(clk / (16 * baudrate));
/* place adjustment later - n/32 BRFA */
@@ -162,8 +190,9 @@ static int _lpuart_serial_tstc(struct
lpuart_serial_platdata *plat)
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
-static int _lpuart_serial_init(struct lpuart_serial_platdata *plat)
+static int _lpuart_serial_init(struct udevice *dev)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
u8 ctrl;
@@ -182,19 +211,25 @@ static int _lpuart_serial_init(struct
lpuart_serial_platdata *plat)
__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
/* provide data bits, parity, stop bit, etc */
- _lpuart_serial_setbrg(plat, gd->baudrate);
+ _lpuart_serial_setbrg(dev, gd->baudrate);
__raw_writeb(UC2_RE | UC2_TE, &base->uc2);
return 0;
}
-static void _lpuart32_serial_setbrg_7ulp(struct lpuart_serial_platdata *plat,
+static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
int baudrate)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl_reg32 *base = plat->reg;
u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
- u32 clk = get_lpuart_clk();
+ u32 clk;
+
+ if (IS_ENABLED(CONFIG_CLK))
+ clk = get_lpuart_clk_rate(dev);
+ else
+ clk = get_lpuart_clk();
baud_diff = baudrate;
osr = 0;
@@ -248,13 +283,19 @@ static void _lpuart32_serial_setbrg_7ulp(struct
lpuart_serial_platdata *plat,
out_le32(&base->baud, tmp);
}
-static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat,
+static void _lpuart32_serial_setbrg(struct udevice *dev,
int baudrate)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl_reg32 *base = plat->reg;
- u32 clk = get_lpuart_clk();
+ u32 clk;
u32 sbr;
+ if (IS_ENABLED(CONFIG_CLK))
+ clk = get_lpuart_clk_rate(dev);
+ else
+ clk = get_lpuart_clk();
+
sbr = (clk / (16 * baudrate));
/* place adjustment later - n/32 BRFA */
@@ -321,8 +362,9 @@ static int _lpuart32_serial_tstc(struct
lpuart_serial_platdata *plat)
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
-static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)
+static int _lpuart32_serial_init(struct udevice *dev)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
u32 val, tx_fifo_size;
@@ -350,10 +392,10 @@ static int _lpuart32_serial_init(struct
lpuart_serial_platdata *plat)
lpuart_write32(plat->flag
Re: [U-Boot] [PATCH 3/9] common: include always
2018-08-04 0:01 GMT+09:00 Tom Rini :
> On Thu, Aug 02, 2018 at 10:56:11AM -0600, Simon Glass wrote:
>> +Tom
>>
>> Hi Masahiro,
>>
>> On 30 July 2018 at 19:41, Masahiro Yamada
>> wrote:
>> > 2018-07-26 22:59 GMT+09:00 Philipp Tomsich
>> > :
>> >> With the ram-size variable changed to u64, we'll need appropriate
>> >> macros for printing u64 values correctly either in 32bit builds
>> >> (i.e. ILP32 models) or in 64bit builds (i.e. LP64 models). Best to
>> >> make the PRIx64 macro available everywhere.
>> >>
>> >> This include inttypes.h from common.h to make the various macros for
>> >> formatted printing available to everyone.
>> >>
>> >> Signed-off-by: Philipp Tomsich
>> >> ---
>> >
>> >
>> > NACK.
>> >
>> >
>> > PRIx64 is evil crap. I would make the code super ugly.
>> > Do not use it.
>> >
>> >
>> > The right thing to do is use the same typedefs
>> > for all architectures.
>> >
>> > typedef unsigned char u8;
>> > typedef unsigned short u16;
>> > typedef unsigned intu32;
>> > typedef unsigned long long u64;
>> >
>> > This works for both ILP32 and LP64.
>> >
>> >
>> > Use '%llx' for printing u64 variables _always_.
>> >
>> >
>> >
>> > This is what Linux exactly does.
>> >
>> >
>> >
>> > In fact, Linux defined fixed-width types differently
>> > for different architectures in old days.
>> >
>> >
>> > After long time effort, Linux unified
>> > the fixed-width types for the kernel space.
>> >
>> > https://github.com/torvalds/linux/blob/master/include/uapi/asm-generic/int-ll64.h
>> >
>> >
>> >
>> > See Linux commit:
>> >
>> > commit 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf
>> > Author: Geert Uytterhoeven
>> > Date: Thu Jan 23 15:53:43 2014 -0800
>> >
>> > asm/types.h: Remove include/asm-generic/int-l64.h
>> >
>> >
>> >
>> >
>> >
>> > And, I fixed ARM Trusted Firmware in the same way:
>> >
>> > https://github.com/ARM-software/arm-trusted-firmware/commit/0a2d5b43c81ed6132761023bf43755f13122ddf0
>> >
>> >
>> >
>> >
>> >
>> > U-Boot is still doing wrong,
>> > and core developers in U-Boot do not understand this, unfortunately.
>>
>> While this works in many cases we do seem to have problems with some
>> toolchains. Perhaps things are better now as my problems were a a few
>> years back.
Please pin-point the pre-built toolchains with which
you had problems.
In other words, please show a compiler that has:
sizeof(int) != 4
or
sizeof(long long) != 8
>> Things like size_t with %z caused problems too. I remember
>> m68k producing warnings when I tried this.
This is true, but
the typedefs of uint{8,16,32,64}_t
and the typedef of size_t are
_different_ problems.
Please do not mix them up to exaggerate things.
Most 32 bit architectures use "unsigned int" size_t,
and all 64 bit architectures use "unsigned long" size_t
as stated in
https://github.com/torvalds/linux/blob/v4.17/include/uapi/asm-generic/posix_types.h#L63
Linux kernel hard-codes size_t and ssize_t, thus
people are supposed to use a compiler with proper size_t define.
Such compilers are provided in
https://mirrors.edge.kernel.org/pub/tools/crosstool/
If you are not happy about hard-coding size_t,
you can do like this:
typedef __SIZE_TYPE__ size_t;
typedef __typeof(__builtin_choose_expr(__builtin_types_compatible_p(size_t,
unsigned long), (long)0, (int)0)) ssize_t;
>> I am certainly interested in converting over to this other approach. I
>> am also OK with the PRi stuff, since it only affects a relatively
>> small number of cases.
Whether the code is right or not
should not be judged by the number of use cases.
> It would certainly be worth giving things another try with current
> compilers.
>
> --
> Tom
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
>
--
Best Regards
Masahiro Yamada
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 29/32] fsl_esdhc: Update usdhc driver to support i.MX8
From: Ye Li
Add CONFIG_ARCH_IMX8 to use the 64bits support in usdhc driver.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
Cc: Jaehoon Chung
---
drivers/mmc/fsl_esdhc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 4528345c67..1b062ff06d 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -257,7 +257,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
dma_addr_t addr;
#endif
uint wml_value;
@@ -271,7 +271,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -301,7 +301,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -367,7 +367,7 @@ static void check_and_invalidate_dcache_range
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 21/32] imx8: add dummy clock
This driver is mostly used to avoid build error.
We use uclass clk driver to clk related operations.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8/clock.h | 27 +++
arch/arm/mach-imx/imx8/clock.c | 21 +
2 files changed, 48 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8/clock.h
create mode 100644 arch/arm/mach-imx/imx8/clock.c
diff --git a/arch/arm/include/asm/arch-imx8/clock.h
b/arch/arm/include/asm/arch-imx8/clock.h
new file mode 100644
index 00..bea157171f
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/clock.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8_CLOCK_H__
+#define __ASM_ARCH_IMX8_CLOCK_H__
+
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_UART_CLK,
+ MXC_CSPI_CLK,
+ MXC_AXI_CLK,
+ MXC_DDR_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_I2C_CLK,
+ MXC_FEC_CLK,
+};
+
+u32 mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_IMX8_CLOCK_H__ */
diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c
new file mode 100644
index 00..d747e1332f
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/clock.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ default:
+ printf("Unsupported mxc_clock %d\n", clk);
+ break;
+ }
+
+ return 0;
+}
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 32/32] imx: add i.MX8QXP MEK board support
Add i.MX8QXP MEK board support
Enabled pinctrl/clk/power domain/mmc/i2c driver.
Added README file.
Signed-off-by: Peng Fan
Cc: Stefano Babic
Cc: Fabio Estevam
Cc: Anatolij Gustschin
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/fsl-imx8qxp-mek.dts | 136 ++
arch/arm/mach-imx/imx8/Kconfig| 13 +++
board/freescale/imx8qxp_mek/Kconfig | 14 +++
board/freescale/imx8qxp_mek/MAINTAINERS | 6 ++
board/freescale/imx8qxp_mek/Makefile | 7 ++
board/freescale/imx8qxp_mek/README| 72 ++
board/freescale/imx8qxp_mek/imx8qxp_mek.c | 152 +
board/freescale/mx8mq_evk/README | 81 +++
configs/imx8qxp_mek_defconfig | 37 +++
include/configs/imx8qxp_mek.h | 157 ++
11 files changed, 677 insertions(+)
create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts
create mode 100644 board/freescale/imx8qxp_mek/Kconfig
create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS
create mode 100644 board/freescale/imx8qxp_mek/Makefile
create mode 100644 board/freescale/imx8qxp_mek/README
create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c
create mode 100644 board/freescale/mx8mq_evk/README
create mode 100644 configs/imx8qxp_mek_defconfig
create mode 100644 include/configs/imx8qxp_mek.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 09adf5eab1..a32a7a3668 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -444,6 +444,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
+
dtb-$(CONFIG_RCAR_GEN3) += \
r8a7795-h3ulcb.dtb \
r8a7795-salvator-x.dtb \
diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts
new file mode 100644
index 00..5443ef7e4e
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-mek.dts
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qxp.dtsi"
+
+/ {
+ model = "Freescale i.MX8QXP MEK";
+ compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
+
+ chosen {
+ bootargs = "console=ttyLP0,115200
earlycon=lpuart32,0x5a06,115200";
+ stdout-path = &lpuart0;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ reg_usdhc2_vmmc: usdhc2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "SD1_SPWR";
+ regulator-min-microvolt = <300>;
+ regulator-max-microvolt = <300>;
+ gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay = <3480>;
+ enable-active-high;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx8qxp-mek {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0
0x064c
+ SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD
0x000514a0
+ >;
+ };
+
+ pinctrl_ioexp_rst: ioexp_rst_grp {
+ fsl,pins = <
+ SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x0621
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi1cgrp {
+ fsl,pins = <
+ SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x0621
+ SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x0621
+ >;
+ };
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ SC_P_UART0_RX_ADMA_UART0_RX 0x0620
+ SC_P_UART0_TX_ADMA_UART0_TX 0x0620
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK
0x0641
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD
0x0021
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0
0x0021
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1
0x0021
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2
0x0021
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3
0x0021
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4
0x0021
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5
0x0021
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6
0x0021
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7
[U-Boot] [PATCH V3 25/32] clk: imx: add clk driver for i.MX8QXP
Add clk driver for i.MX8QXP, support clk
enable/disable/get_rate/set_rate operations.
Signed-off-by: Peng Fan
Cc: Stefano Babic
---
drivers/clk/Kconfig| 1 +
drivers/clk/Makefile | 1 +
drivers/clk/imx/Kconfig| 6 ++
drivers/clk/imx/Makefile | 5 ++
drivers/clk/imx/clk-imx8.c | 212 +
5 files changed, 225 insertions(+)
create mode 100644 drivers/clk/imx/Kconfig
create mode 100644 drivers/clk/imx/Makefile
create mode 100644 drivers/clk/imx/clk-imx8.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 18bf8a6d28..c2f2a99b40 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -86,6 +86,7 @@ config CLK_STM32MP1
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/uniphier/Kconfig"
source "drivers/clk/exynos/Kconfig"
+source "drivers/clk/imx/Kconfig"
source "drivers/clk/at91/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/mvebu/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 146283c723..2a3c83b597 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
obj-y += tegra/
+obj-y += imx/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MESON) += clk_meson.o
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
new file mode 100644
index 00..a6fb58d6cf
--- /dev/null
+++ b/drivers/clk/imx/Kconfig
@@ -0,0 +1,6 @@
+config CLK_IMX8
+ bool "Clock support for i.MX8"
+ depends on ARCH_IMX8
+ select CLK
+ help
+ This enables support clock driver for i.MX8 platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
new file mode 100644
index 00..5505ae52e2
--- /dev/null
+++ b/drivers/clk/imx/Makefile
@@ -0,0 +1,5 @@
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
new file mode 100644
index 00..ba87ad6964
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8.c
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static ulong imx8_clk_get_rate(struct clk *clk)
+{
+ sc_pm_clk_t pm_clk;
+ ulong rate;
+ u16 resource;
+ int ret;
+
+ debug("%s(#%ld)\n", __func__, clk->id);
+
+ switch (clk->id) {
+ case IMX8QXP_A35_DIV:
+ resource = SC_R_A35;
+ pm_clk = SC_PM_CLK_CPU;
+ break;
+ case IMX8QXP_SDHC0_IPG_CLK:
+ case IMX8QXP_SDHC0_CLK:
+ case IMX8QXP_SDHC0_DIV:
+ resource = SC_R_SDHC_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_SDHC1_IPG_CLK:
+ case IMX8QXP_SDHC1_CLK:
+ case IMX8QXP_SDHC1_DIV:
+ resource = SC_R_SDHC_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART0_IPG_CLK:
+ case IMX8QXP_UART0_CLK:
+ resource = SC_R_UART_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ default:
+ dev_err(dev, "%s(Invalid #%ld)\n", __func__, clk->id);
+ return -EINVAL;
+ };
+
+ ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
+ (sc_pm_clock_rate_t *)&rate);
+ if (ret)
+ printf("%s err %d\n", __func__, ret);
+
+ return rate;
+}
+
+static ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ sc_pm_clk_t pm_clk;
+ u32 new_rate = rate;
+ u16 resource;
+ int ret;
+
+ debug("%s(#%ld), rate: %lu\n", __func__, clk->id, rate);
+
+ switch (clk->id) {
+ case IMX8QXP_UART0_CLK:
+ resource = SC_R_UART_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART1_CLK:
+ resource = SC_R_UART_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART2_CLK:
+ resource = SC_R_UART_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART3_CLK:
+ resource = SC_R_UART_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_SDHC0_IPG_CLK:
+ case IMX8QXP_SDHC0_CLK:
+ case IMX8QXP_SDHC0_DIV:
+ resource = SC_R_SDHC_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_SDHC1_SEL:
+ case IMX8QXP_SDHC0_SEL:
+ return 0;
+ case IMX8QXP_SDHC1_IPG_CLK:
+ case IMX8QXP_SDHC1_CLK:
+ case IMX8QXP_SDHC1_DIV:
+ resource = SC_R_SDHC_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ default:
+ printf("%s %ld\n", __func__, clk->id);
+
[U-Boot] [PATCH V3 24/32] power: Add power domain driver for i.MX8
Add the power domain DM driver for i.MX8, that it depends on the DTB
power domain trees to generate the power domain provider devices. Users
needs add power domain trees with property "compatible = "nxp,imx8-pd";"
When power on one PD device, the driver will power on its ancestor PD
devices in power domain tree.
When power off on PD device, the driver will check its child PD devices
first, only all child PD devices are off, then power off the current PD
device. Then the driver checks sibling PD devices. If sibling PD devices
are off, then it will power off parent PD device.
There is no counter maintained in this driver, but a state to hold current
on/off state. So the request and free functions are empty.
The power domain implementation in i.MX8 DTB set the "#power-domain-cells"
to 0, so there is no ID binding with each PD device. We don't use "id"
variable in struct power_domain. At same time, we have to set of_xlate to
empty to bypass standard of_xlate in uclass driver.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx8/power-domain.h | 15 ++
drivers/power/domain/Kconfig | 6 +
drivers/power/domain/Makefile | 1 +
drivers/power/domain/imx8-power-domain.c | 312 ++
4 files changed, 334 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8/power-domain.h
create mode 100644 drivers/power/domain/imx8-power-domain.c
diff --git a/arch/arm/include/asm/arch-imx8/power-domain.h
b/arch/arm/include/asm/arch-imx8/power-domain.h
new file mode 100644
index 00..1396008877
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/power-domain.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H
+#define _ASM_ARCH_IMX8_POWER_DOMAIN_H
+
+#include
+
+struct imx8_power_domain_platdata {
+ sc_rsrc_t resource_id;
+};
+
+#endif
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 7cfa761498..2a72642a26 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -31,4 +31,10 @@ config TEGRA186_POWER_DOMAIN
Enable support for manipulating Tegra's on-SoC power domains via IPC
requests to the BPMP (Boot and Power Management Processor).
+config IMX8_POWER_DOMAIN
+ bool "Enable i.MX8 power domain driver"
+depends on ARCH_IMX8
+help
+ Enable support for manipulating NXP i.MX8 on-SoC power domains via
IPC
+ requests to the SCU.
endmenu
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 020eee2378..1ef4844c0b 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
+obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain.o
diff --git a/drivers/power/domain/imx8-power-domain.c
b/drivers/power/domain/imx8-power-domain.c
new file mode 100644
index 00..be91d626ad
--- /dev/null
+++ b/drivers/power/domain/imx8-power-domain.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct imx8_power_domain_priv {
+ bool state_on;
+};
+
+static int imx8_power_domain_request(struct power_domain *power_domain)
+{
+ debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+ return 0;
+}
+
+static int imx8_power_domain_free(struct power_domain *power_domain)
+{
+ debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+ return 0;
+}
+
+static int imx8_power_domain_on(struct power_domain *power_domain)
+{
+ struct udevice *dev = power_domain->dev;
+ struct imx8_power_domain_platdata *pdata;
+ struct imx8_power_domain_priv *ppriv;
+ sc_err_t ret;
+
+ struct power_domain parent_domain;
+ struct udevice *parent = dev_get_parent(dev);
+
+ /* Need to power on parent node first */
+ if (device_get_uclass_id(parent) == UCLASS_POWER_DOMAIN) {
+ parent_domain.dev = parent;
+ imx8_power_domain_on(&parent_domain);
+ }
+
+ pdata = (struct imx8_power_domain_platdata *)dev_get_platdata(dev);
+ ppriv = (struct imx8_power_domain_priv *)dev_get_priv(dev);
+
+ debug("%s(power_domain=%s) resource_id %d\n", __func__, dev->name,
+ pdata->resource_id);
+
+ /* Already powered on */
+ if (ppriv->state_on)
+ return 0;
+
+ if (pdata->resource_id != SC_R_LAST) {
+ ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id,
+ SC_PM_PW_MODE_O
[U-Boot] [PATCH V3 17/32] imx8: implement mmc_get_env_dev
Implement mmc_get_env_dev for i.MX8.
Signed-off-by: Peng Fan
Cc: Stefano Babic
---
arch/arm/mach-imx/imx8/cpu.c | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 90b6ea4211..0cacaa895c 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -176,3 +176,35 @@ enum boot_device get_boot_device(void)
return boot_dev;
}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return CONFIG_SYS_MMC_ENV_DEV;
+}
+
+int mmc_get_env_dev(void)
+{
+ sc_rsrc_t dev_rsrc;
+ int devno;
+
+ sc_misc_get_boot_dev(-1, &dev_rsrc);
+
+ switch (dev_rsrc) {
+ case SC_R_SDHC_0:
+ devno = 0;
+ break;
+ case SC_R_SDHC_1:
+ devno = 1;
+ break;
+ case SC_R_SDHC_2:
+ devno = 2;
+ break;
+ default:
+ /* If not boot from sd/mmc, use default value */
+ return CONFIG_SYS_MMC_ENV_DEV;
+ }
+
+ return board_mmc_get_env_dev(devno);
+}
+#endif
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 26/32] serial_lpuart: Update lpuart driver to support i.MX8
Add i.MX8 compatible string and cpu type support to lpuart driver,
to use little endian 32 bits configurations.
Also, accroding to RM, the Receive FIFO Enable (RXFE) field in LPUART
FIFO register is bit 3, so the definition should change to 0x08 not 0x40
for i.MX8, otherwise the Receive FIFO is not disabled.
Signed-off-by: Peng Fan
---
drivers/serial/serial_lpuart.c | 15 ---
include/fsl_lpuart.h | 2 +-
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 1212b72676..c14a8105c9 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -41,7 +41,11 @@
#define CTRL_RE(1 << 18)
#define FIFO_TXFE 0x80
+#ifdef CONFIG_ARCH_IMX8
+#define FIFO_RXFE 0x08
+#else
#define FIFO_RXFE 0x40
+#endif
#define WATER_TXWATER_OFF 1
#define WATER_RXWATER_OFF 16
@@ -54,7 +58,8 @@ DECLARE_GLOBAL_DATA_PTR;
enum lpuart_devtype {
DEV_VF610 = 1,
DEV_LS1021A,
- DEV_MX7ULP
+ DEV_MX7ULP,
+ DEV_IMX8
};
struct lpuart_serial_platdata {
@@ -325,7 +330,7 @@ static int _lpuart32_serial_init(struct
lpuart_serial_platdata *plat)
lpuart_write32(plat->flags, &base->match, 0);
- if (plat->devtype == DEV_MX7ULP) {
+ if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) {
_lpuart32_serial_setbrg_7ulp(plat, gd->baudrate);
} else {
/* provide data bits, parity, stop bit, etc */
@@ -342,7 +347,7 @@ static int lpuart_serial_setbrg(struct udevice *dev, int
baudrate)
struct lpuart_serial_platdata *plat = dev->platdata;
if (is_lpuart32(dev)) {
- if (plat->devtype == DEV_MX7ULP)
+ if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8)
_lpuart32_serial_setbrg_7ulp(plat, baudrate);
else
_lpuart32_serial_setbrg(plat, baudrate);
@@ -427,6 +432,8 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice
*dev)
plat->devtype = DEV_MX7ULP;
else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
plat->devtype = DEV_VF610;
+ else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
+ plat->devtype = DEV_IMX8;
return 0;
}
@@ -444,6 +451,8 @@ static const struct udevice_id lpuart_serial_ids[] = {
{ .compatible = "fsl,imx7ulp-lpuart",
.data = LPUART_FLAG_REGMAP_32BIT_REG },
{ .compatible = "fsl,vf610-lpuart"},
+ { .compatible = "fsl,imx8qm-lpuart",
+ .data = LPUART_FLAG_REGMAP_32BIT_REG },
{ }
};
diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h
index 02ebfefc74..fc517d4b7f 100644
--- a/include/fsl_lpuart.h
+++ b/include/fsl_lpuart.h
@@ -4,7 +4,7 @@
*
*/
-#ifdef CONFIG_ARCH_MX7ULP
+#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8)
struct lpuart_fsl_reg32 {
u32 verid;
u32 param;
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 30/32] mmc: fsl_esdhc: add uclass clk support
When CONIFG_CLK is enabled, use uclass clk api to handle
the clock.
Signed-off-by: Peng Fan
Cc: Jaehoon Chung
Cc: Stefano Babic
---
drivers/mmc/fsl_esdhc.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 1b062ff06d..70243b99d2 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -121,6 +122,7 @@ struct esdhc_soc_data {
struct fsl_esdhc_priv {
struct fsl_esdhc *esdhc_regs;
unsigned int sdhc_clk;
+ struct clk per_clk;
unsigned int clock;
unsigned int mode;
unsigned int bus_width;
@@ -1462,10 +1464,22 @@ static int fsl_esdhc_probe(struct udevice *dev)
init_clk_usdhc(dev->seq);
- priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
- if (priv->sdhc_clk <= 0) {
- dev_err(dev, "Unable to get clk for %s\n", dev->name);
- return -EINVAL;
+ if (IS_ENABLED(CONFIG_CLK)) {
+ /* Assigned clock already set clock */
+ ret = clk_get_by_name(dev, "per", &priv->per_clk);
+ if (ret)
+ printf("Failed to get per_clk\n");
+ ret = clk_enable(&priv->per_clk);
+ if (ret)
+ printf("Failed to enable per_clk\n");
+
+ priv->sdhc_clk = clk_get_rate(&priv->per_clk);
+ } else {
+ priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+ if (priv->sdhc_clk <= 0) {
+ dev_err(dev, "Unable to get clk for %s\n", dev->name);
+ return -EINVAL;
+ }
}
ret = fsl_esdhc_init(priv, plat);
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 19/32] imx8: add arch_cpu_init arch_cpu_init_dm
Add arch_cpu_init(_dm) mainly to open the channel between ACore and SCU.
Signed-off-by: Peng Fan
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx8/sys_proto.h | 9 ++
arch/arm/mach-imx/imx8/cpu.c | 51 ++
2 files changed, 60 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h
b/arch/arm/include/asm/arch-imx8/sys_proto.h
index f9a3016132..73ffaba7d5 100644
--- a/arch/arm/include/asm/arch-imx8/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -6,5 +6,14 @@
#include
#include
+struct pass_over_info_t {
+ u16 barker;
+ u16 len;
+ u32 g_bt_cfg_shadow;
+ u32 card_address_mode;
+ u32 bad_block_count_met;
+ u32 g_ap_mu;
+};
+
enum boot_device get_boot_device(void);
int print_bootinfo(void);
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 389f422be7..be5a8ee8ca 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -95,6 +95,57 @@ int print_cpuinfo(void)
}
#endif
+#define BT_PASSOVER_TAG0x504F
+struct pass_over_info_t *get_pass_over_info(void)
+{
+ struct pass_over_info_t *p =
+ (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
+
+ if (p->barker != BT_PASSOVER_TAG ||
+ p->len != sizeof(struct pass_over_info_t))
+ return NULL;
+
+ return p;
+}
+
+int arch_cpu_init(void)
+{
+ struct pass_over_info_t *pass_over = get_pass_over_info();
+
+ if (pass_over && pass_over->g_ap_mu == 0) {
+ /*
+* When ap_mu is 0, means the u-boot is boot
+* from first container
+*/
+ sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
+ }
+
+ return 0;
+}
+
+int arch_cpu_init_dm(void)
+{
+ struct udevice *devp;
+ int node, ret;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
+ ret = device_bind_driver_to_node(gd->dm_root, "imx8_scu", "imx8_scu",
+offset_to_ofnode(node), &devp);
+
+ if (ret) {
+ printf("could not find scu %d\n", ret);
+ return ret;
+ }
+
+ ret = device_probe(devp);
+ if (ret) {
+ printf("scu probe failed %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
int print_bootinfo(void)
{
enum boot_device bt_dev = get_boot_device();
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 22/32] gpio: mxc_gpio: add support for i.MX8
Add i.MX8 support, there are 8 GPIO banks.
Signed-off-by: Peng Fan
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx8/gpio.h | 21 +
drivers/gpio/mxc_gpio.c | 30 +-
2 files changed, 42 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx8/gpio.h
diff --git a/arch/arm/include/asm/arch-imx8/gpio.h
b/arch/arm/include/asm/arch-imx8/gpio.h
new file mode 100644
index 00..24cfde3c29
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/gpio.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8_GPIO_H
+#define __ASM_ARCH_IMX8_GPIO_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+/* GPIO registers */
+struct gpio_regs {
+ u32 gpio_dr;/* data */
+ u32 gpio_dir; /* direction */
+ u32 gpio_psr; /* pad satus */
+};
+#endif
+
+/* IMX8 the GPIO index is from 0 not 1 */
+#define IMX_GPIO_NR(port, index) (((port) * 32) + ((index) & 31))
+
+#endif /* __ASM_ARCH_IMX8_GPIO_H */
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index d8e72ada19..b820160ae7 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -40,21 +40,27 @@ static unsigned long gpio_ports[] = {
[2] = GPIO3_BASE_ADDR,
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+ defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \
+ defined(CONFIG_ARCH_IMX8)
[3] = GPIO4_BASE_ADDR,
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+ defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \
+ defined(CONFIG_ARCH_IMX8)
[4] = GPIO5_BASE_ADDR,
#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M))
[5] = GPIO6_BASE_ADDR,
#endif
#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
+ defined(CONFIG_ARCH_IMX8)
#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
[6] = GPIO7_BASE_ADDR,
#endif
#endif
+#if defined(CONFIG_ARCH_IMX8)
+ [7] = GPIO8_BASE_ADDR,
+#endif
};
static int mxc_gpio_direction(unsigned int gpio,
@@ -347,19 +353,22 @@ static const struct mxc_gpio_plat mxc_plat[] = {
{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
#ifndef CONFIG_MX8M
{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
#endif
#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
#endif
+#if defined(CONFIG_ARCH_IMX8)
+ { 7, (struct gpio_regs *)GPIO8_BASE_ADDR },
+#endif
};
U_BOOT_DEVICES(mxc_gpios) = {
@@ -368,19 +377,22 @@ U_BOOT_DEVICES(mxc_gpios) = {
{ "gpio_mxc", &mxc_plat[2] },
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
{ "gpio_mxc", &mxc_plat[3] },
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
{ "gpio_mxc", &mxc_plat[4] },
#ifndef CONFIG_MX8M
{ "gpio_mxc", &mxc_plat[5] },
#endif
#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
{ "gpio_mxc", &mxc_plat[6] },
#endif
+#if defined(CONFIG_ARCH_IMX8)
+ { "gpio_mxc", &mxc_plat[7] },
+#endif
};
#endif
#endif
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 10/32] imx: boot_mode: Add FLEXSPI boot entry
i.MX8 support FLEXSPI boot support. So add FLEXSPI boot entry.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h
b/arch/arm/include/asm/mach-imx/boot_mode.h
index 8766e9d180..3a483b6afa 100644
--- a/arch/arm/include/asm/mach-imx/boot_mode.h
+++ b/arch/arm/include/asm/mach-imx/boot_mode.h
@@ -25,6 +25,7 @@ enum boot_device {
MMC4_BOOT,
NAND_BOOT,
QSPI_BOOT,
+ FLEXSPI_BOOT,
USB_BOOT,
UNKNOWN_BOOT,
BOOT_DEV_NUM = UNKNOWN_BOOT,
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 16/32] imx8: add boot device detection
Add get_boot_device to detect boot device.
Add print_bootinfo to print the boot device info.
Signed-off-by: Peng Fan
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx8/sys_proto.h | 10
arch/arm/mach-imx/imx8/cpu.c | 85 ++
2 files changed, 95 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8/sys_proto.h
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h
b/arch/arm/include/asm/arch-imx8/sys_proto.h
new file mode 100644
index 00..f9a3016132
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include
+
+enum boot_device get_boot_device(void);
+int print_bootinfo(void);
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 0b841e291d..90b6ea4211 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -11,8 +11,10 @@
#include
#include
#include
+#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -91,3 +93,86 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+int print_bootinfo(void)
+{
+ enum boot_device bt_dev = get_boot_device();
+
+ puts("Boot: ");
+ switch (bt_dev) {
+ case SD1_BOOT:
+ puts("SD0\n");
+ break;
+ case SD2_BOOT:
+ puts("SD1\n");
+ break;
+ case SD3_BOOT:
+ puts("SD2\n");
+ break;
+ case MMC1_BOOT:
+ puts("MMC0\n");
+ break;
+ case MMC2_BOOT:
+ puts("MMC1\n");
+ break;
+ case MMC3_BOOT:
+ puts("MMC2\n");
+ break;
+ case FLEXSPI_BOOT:
+ puts("FLEXSPI\n");
+ break;
+ case SATA_BOOT:
+ puts("SATA\n");
+ break;
+ case NAND_BOOT:
+ puts("NAND\n");
+ break;
+ case USB_BOOT:
+ puts("USB\n");
+ break;
+ default:
+ printf("Unknown device %u\n", bt_dev);
+ break;
+ }
+
+ return 0;
+}
+
+enum boot_device get_boot_device(void)
+{
+ enum boot_device boot_dev = SD1_BOOT;
+
+ sc_rsrc_t dev_rsrc;
+
+ sc_misc_get_boot_dev(-1, &dev_rsrc);
+
+ switch (dev_rsrc) {
+ case SC_R_SDHC_0:
+ boot_dev = MMC1_BOOT;
+ break;
+ case SC_R_SDHC_1:
+ boot_dev = SD2_BOOT;
+ break;
+ case SC_R_SDHC_2:
+ boot_dev = SD3_BOOT;
+ break;
+ case SC_R_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case SC_R_FSPI_0:
+ boot_dev = FLEXSPI_BOOT;
+ break;
+ case SC_R_SATA_0:
+ boot_dev = SATA_BOOT;
+ break;
+ case SC_R_USB_0:
+ case SC_R_USB_1:
+ case SC_R_USB_2:
+ boot_dev = USB_BOOT;
+ break;
+ default:
+ break;
+ }
+
+ return boot_dev;
+}
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 23/32] pinctrl: Add pinctrl driver for i.MX8
Add pinctrl driver for i.MX8. The pads configuration is controlled
by SCU, so need to ask SCU to configure pads through scfw API.
Add pinctrl-scu to invoke sc_pad_set to configue pads.
Add a new flag IMX8_USE_SCU to differentiate i.MX8 from other platforms
which could directly configure pads from Acore side.
Add CONFIG_PINCTRL_IMX8 as the built gate.
Signed-off-by: Peng Fan
---
drivers/pinctrl/nxp/Kconfig| 18
drivers/pinctrl/nxp/Makefile | 2 +
drivers/pinctrl/nxp/pinctrl-imx.c | 209 -
drivers/pinctrl/nxp/pinctrl-imx.h | 16 +++
drivers/pinctrl/nxp/pinctrl-imx8.c | 40 +++
drivers/pinctrl/nxp/pinctrl-scu.c | 66
6 files changed, 258 insertions(+), 93 deletions(-)
create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8.c
create mode 100644 drivers/pinctrl/nxp/pinctrl-scu.c
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index b668359a0b..449ad47ebc 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -1,6 +1,9 @@
config PINCTRL_IMX
bool
+config PINCTRL_IMX_SCU
+ bool
+
config PINCTRL_IMX5
bool "IMX5 pinctrl driver"
depends on ARCH_MX5 && PINCTRL_FULL
@@ -56,3 +59,18 @@ config PINCTRL_IMX7ULP
is different from the linux one, this is a simple implementation,
only parses the 'fsl,pins' property and configure related
registers.
+
+config PINCTRL_IMX8
+ bool "IMX8 pinctrl driver"
+ depends on ARCH_IMX8 && PINCTRL_FULL
+ select DEVRES
+ select PINCTRL_IMX
+ select PINCTRL_IMX_SCU
+ help
+ Say Y here to enable the imx8 pinctrl driver
+
+ This provides a simple pinctrl driver for i.MX8 SoC familiy.
+ This feature depends on device tree configuration. This driver
+ is different from the linux one, this is a simple implementation,
+ only parses the 'fsl,pins' property and configure related
+ registers.
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index c763948376..310b3b3a2e 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o
obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o
obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
+obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
+obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c
b/drivers/pinctrl/nxp/pinctrl-imx.c
index 36e1e8983c..04ea82aba5 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx.c
@@ -28,7 +28,9 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
dev_dbg(dev, "%s: %s\n", __func__, config->name);
- if (info->flags & SHARE_MUX_CONF_REG)
+ if (info->flags & IMX8_USE_SCU)
+ pin_size = SHARE_IMX8_PIN_SIZE;
+ else if (info->flags & SHARE_MUX_CONF_REG)
pin_size = SHARE_FSL_PIN_SIZE;
else
pin_size = FSL_PIN_SIZE;
@@ -58,112 +60,127 @@ static int imx_pinctrl_set_state(struct udevice *dev,
struct udevice *config)
npins = size / pin_size;
- /*
-* Refer to linux documentation for details:
-* Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
-*/
- for (i = 0; i < npins; i++) {
- mux_reg = pin_data[j++];
-
- if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
- mux_reg = -1;
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- conf_reg = mux_reg;
- } else {
- conf_reg = pin_data[j++];
- if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
- conf_reg = -1;
- }
+ if (info->flags & IMX8_USE_SCU) {
+ imx_pinctrl_scu_conf_pins(info, pin_data, npins);
+ } else {
+ /*
+* Refer to linux documentation for details:
+* Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+*/
+ for (i = 0; i < npins; i++) {
+ mux_reg = pin_data[j++];
- if ((mux_reg == -1) || (conf_reg == -1)) {
- dev_err(dev, "Error mux_reg or conf_reg\n");
- devm_kfree(dev, pin_data);
- return -EINVAL;
- }
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
- input_reg = pin_data[j++];
- mux_mode = pin_data[j++];
- input_val = pin_data[j++];
- config_val = pin_data[j++];
+ if (info->flags & SHARE_MUX_CONF_REG) {
+
[U-Boot] [PATCH V3 11/32] imx8: add imx-regs header file
Add imx-regs header file to include the register base definition Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/imx-regs.h | 46 +++ 1 file changed, 46 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/imx-regs.h diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h new file mode 100644 index 00..af0fb5154b --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_REGS_H__ +#define __ASM_ARCH_IMX8_REGS_H__ + +#define LPUART_BASE0x5A06 + +#define GPT1_BASE_ADDR 0x5D14 +#define SCU_LPUART_BASE0x3322 +#define GPIO1_BASE_ADDR0x5D08 +#define GPIO2_BASE_ADDR0x5D09 +#define GPIO3_BASE_ADDR0x5D0A +#define GPIO4_BASE_ADDR0x5D0B +#define GPIO5_BASE_ADDR0x5D0C +#define GPIO6_BASE_ADDR0x5D0D +#define GPIO7_BASE_ADDR0x5D0E +#define GPIO8_BASE_ADDR0x5D0F +#define LPI2C1_BASE_ADDR 0x5A80 +#define LPI2C2_BASE_ADDR 0x5A81 +#define LPI2C3_BASE_ADDR 0x5A82 +#define LPI2C4_BASE_ADDR 0x5A83 +#define LPI2C5_BASE_ADDR 0x5A84 + +#ifdef CONFIG_IMX8QXP +#define LVDS0_PHYCTRL_BASE 0x56221000 +#define LVDS1_PHYCTRL_BASE 0x56241000 +#define MIPI0_SS_BASE 0x5622 +#define MIPI1_SS_BASE 0x5624 +#endif + +#define APBH_DMA_ARB_BASE_ADDR 0x5B81 +#define APBH_DMA_ARB_END_ADDR 0x5B81 +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR + +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + +#define PASS_OVER_INFO_ADDR0x0010fe00 + +#define USB_BASE_ADDR 0x5b0d +#define USB_PHY0_BASE_ADDR 0x5b10 + +#endif /* __ASM_ARCH_IMX8_REGS_H__ */ -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 14/32] armv8: add cpu core helper functions
Add helper functions to identify different armv8 variants.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/armv8/cpu.h | 26 ++
1 file changed, 26 insertions(+)
create mode 100644 arch/arm/include/asm/armv8/cpu.h
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h
new file mode 100644
index 00..40d54dc85a
--- /dev/null
+++ b/arch/arm/include/asm/armv8/cpu.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define MIDR_PARTNUM_CORTEX_A350xD04
+#define MIDR_PARTNUM_CORTEX_A530xD03
+#define MIDR_PARTNUM_CORTEX_A720xD08
+#define MIDR_PARTNUM_SHIFT 0x4
+#define MIDR_PARTNUM_MASK (0xFFF << 0x4)
+
+static inline unsigned int read_midr(void)
+{
+ unsigned long val;
+
+ asm volatile("mrs %0, midr_el1" : "=r" (val));
+
+ return val;
+}
+
+#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
+MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35)
+#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
+MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53)
+#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
+MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 15/32] imx8: add basic cpu support
Add basic cpu support, including cpu revision, cpu type,
cpu core detection.
Signed-off-by: Peng Fan
Cc: Stefano Babic
---
arch/arm/mach-imx/imx8/Makefile | 7
arch/arm/mach-imx/imx8/cpu.c| 93 +
2 files changed, 100 insertions(+)
create mode 100644 arch/arm/mach-imx/imx8/Makefile
create mode 100644 arch/arm/mach-imx/imx8/cpu.c
diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile
new file mode 100644
index 00..57876139a1
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
new file mode 100644
index 00..0b841e291d
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_cpu_rev(void)
+{
+ u32 id = 0, rev = 0;
+ int ret;
+
+ ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
+ if (ret)
+ return 0;
+
+ rev = (id >> 5) & 0xf;
+ id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
+
+ return (id << 12) | rev;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+const char *get_imx8_type(u32 imxtype)
+{
+ switch (imxtype) {
+ case MXC_CPU_IMX8QXP:
+ return "8QXP";
+ default:
+ return "??";
+ }
+}
+
+const char *get_imx8_rev(u32 rev)
+{
+ switch (rev) {
+ case CHIP_REV_A:
+ return "A";
+ case CHIP_REV_B:
+ return "B";
+ default:
+ return "?";
+ }
+}
+
+const char *get_core_name(void)
+{
+ if (is_cortex_a35())
+ return "A35";
+ else
+ return "?";
+}
+
+int print_cpuinfo(void)
+{
+ struct udevice *dev;
+ struct clk cpu_clk;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_CPU, 0, &dev);
+ if (ret)
+ return 0;
+
+ ret = clk_get_by_index(dev, 0, &cpu_clk);
+ if (ret) {
+ dev_err(dev, "failed to clk\n");
+ return 0;
+ }
+
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+
+ printf("CPU: Freescale i.MX%s rev%s %s at %ld MHz\n",
+ get_imx8_type((cpurev & 0xFF000) >> 12),
+ get_imx8_rev((cpurev & 0xFFF)),
+ get_core_name(),
+ clk_get_rate(&cpu_clk) / 100);
+
+ return 0;
+}
+#endif
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 13/32] imx: add i.MX8 cpu type
Add i.MX8 cpu type and is_imx8/is_imx8qxp help macros. Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/include/asm/arch-imx/cpu.h | 5 + arch/arm/include/asm/mach-imx/sys_proto.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 62df1b9ad2..cf6303c3f5 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -25,12 +25,14 @@ #define MXC_CPU_MX7S 0x71 /* dummy ID */ #define MXC_CPU_MX7D 0x72 #define MXC_CPU_MX8MQ 0x82 +#define MXC_CPU_IMX8QXP0x92 /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_SOC_MX60x60 #define MXC_SOC_MX70x70 #define MXC_SOC_MX8M 0x80 +#define MXC_SOC_IMX8 0x90 /* dummy */ #define MXC_SOC_MX7ULP 0xE0 /* dummy */ #define CHIP_REV_1_00x10 @@ -41,6 +43,9 @@ #define CHIP_REV_2_50x25 #define CHIP_REV_3_00x30 +#define CHIP_REV_A 0x0 +#define CHIP_REV_B 0x1 + #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 #define BOARD_VER_OFFSET0x8 diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index d1d6cbc462..f8890b57da 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -27,6 +27,7 @@ #define is_mx6() (is_soc_type(MXC_SOC_MX6)) #define is_mx7() (is_soc_type(MXC_SOC_MX7)) #define is_mx8m() (is_soc_type(MXC_SOC_MX8M)) +#define is_imx8() (is_soc_type(MXC_SOC_IMX8)) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) @@ -41,6 +42,8 @@ #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) +#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) + #ifdef CONFIG_MX6 #define IMX6_SRC_GPR10_BMODE BIT(28) -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 18/32] imx8: add mmu and dram related functiions
Add mmu memmap, some memory regions are reserved by M4, Arm Trusted
Firmware, so need to get memreg using SCFW API and setup the memmap.
Add dram_init, dram_init_banksize, get_effective_memsize functions,
according to the memreg.
Signed-off-by: Peng Fan
Cc: Stefano Babic
---
arch/arm/mach-imx/imx8/cpu.c | 283 +++
1 file changed, 283 insertions(+)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 0cacaa895c..389f422be7 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -208,3 +209,285 @@ int mmc_get_env_dev(void)
return board_mmc_get_env_dev(devno);
}
#endif
+
+#define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
+
+static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
+ sc_faddr_t *addr_end)
+{
+ sc_faddr_t start, end;
+ int ret;
+ bool owned;
+
+ owned = sc_rm_is_memreg_owned(-1, mr);
+ if (owned) {
+ ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
+ if (ret) {
+ printf("Memreg get info failed, %d\n", ret);
+ return -EINVAL;
+ }
+ debug("0x%llx -- 0x%llx\n", start, end);
+ *addr_start = start;
+ *addr_end = end;
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ sc_rm_mr_t mr;
+ sc_faddr_t start, end, end1;
+ int err;
+
+ end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
+
+ for (mr = 0; mr < 64; mr++) {
+ err = get_owned_memreg(mr, &start, &end);
+ if (!err) {
+ start = roundup(start, MEMSTART_ALIGNMENT);
+ /* Too small memory region, not use it */
+ if (start > end)
+ continue;
+
+ /* Find the memory region runs the u-boot */
+ if (start >= PHYS_SDRAM_1 && start <= end1 &&
+ (start <= CONFIG_SYS_TEXT_BASE &&
+ end >= CONFIG_SYS_TEXT_BASE)) {
+ if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
+ PHYS_SDRAM_1_SIZE))
+ return (end - PHYS_SDRAM_1 + 1);
+ else
+ return PHYS_SDRAM_1_SIZE;
+ }
+ }
+ }
+
+ return PHYS_SDRAM_1_SIZE;
+}
+
+int dram_init(void)
+{
+ sc_rm_mr_t mr;
+ sc_faddr_t start, end, end1, end2;
+ int err;
+
+ end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
+ end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
+ for (mr = 0; mr < 64; mr++) {
+ err = get_owned_memreg(mr, &start, &end);
+ if (!err) {
+ start = roundup(start, MEMSTART_ALIGNMENT);
+ /* Too small memory region, not use it */
+ if (start > end)
+ continue;
+
+ if (start >= PHYS_SDRAM_1 && start <= end1) {
+ if ((end + 1) <= end1)
+ gd->ram_size += end - start + 1;
+ else
+ gd->ram_size += end1 - start;
+ } else if (start >= PHYS_SDRAM_2 && start <= end2) {
+ if ((end + 1) <= end2)
+ gd->ram_size += end - start + 1;
+ else
+ gd->ram_size += end2 - start;
+ }
+ }
+ }
+
+ /* If error, set to the default value */
+ if (!gd->ram_size) {
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ gd->ram_size += PHYS_SDRAM_2_SIZE;
+ }
+ return 0;
+}
+
+static void dram_bank_sort(int current_bank)
+{
+ phys_addr_t start;
+ phys_size_t size;
+
+ while (current_bank > 0) {
+ if (gd->bd->bi_dram[current_bank - 1].start >
+ gd->bd->bi_dram[current_bank].start) {
+ start = gd->bd->bi_dram[current_bank - 1].start;
+ size = gd->bd->bi_dram[current_bank - 1].size;
+
+ gd->bd->bi_dram[current_bank - 1].start =
+ gd->bd->bi_dram[current_bank].start;
+ gd->bd->bi_dram[current_bank - 1].size =
+ gd->bd->bi_dram[current_bank].size;
+
+ gd->bd->bi_dram[current_bank].start = start;
+ gd->bd->bi_dram[current_bank].size = size;
+
[U-Boot] [PATCH V3 12/32] imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined
Include i.MX8QXP pin header when CONFIG_IMX8QXP defined, if no SoC macro defined, report error. Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/imx8-pins.h | 15 +++ 1 file changed, 15 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/imx8-pins.h diff --git a/arch/arm/include/asm/arch-imx8/imx8-pins.h b/arch/arm/include/asm/arch-imx8/imx8-pins.h new file mode 100644 index 00..dcced1010b --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8-pins.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_PINS_H__ +#define __ASM_ARCH_IMX8_PINS_H__ + +#if defined(CONFIG_IMX8QXP) +#include +#else +#error "No pin header" +#endif + +#endif /* __ASM_ARCH_IMX8_PINS_H__ */ -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 20/32] imx8: add iomux configuration api
Add iomux configuration api.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8/iomux.h | 40 +++
arch/arm/mach-imx/imx8/Makefile| 2 +-
arch/arm/mach-imx/imx8/iomux.c | 43 ++
3 files changed, 84 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h
create mode 100644 arch/arm/mach-imx/imx8/iomux.c
diff --git a/arch/arm/include/asm/arch-imx8/iomux.h
b/arch/arm/include/asm/arch-imx8/iomux.h
new file mode 100644
index 00..bedd01bfd8
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/iomux.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8_IOMUX_H__
+#define __ASM_ARCH_IMX8_IOMUX_H__
+
+/*
+ * We use 64bits value for iomux settings.
+ * High 32bits are used for padring register value,
+ * low 16bits are used for pin index.
+ */
+typedef u64 iomux_cfg_t;
+
+#define PADRING_IFMUX_EN_SHIFT 31
+#define PADRING_IFMUX_EN_MASK BIT(31)
+#define PADRING_GP_EN_SHIFT30
+#define PADRING_GP_EN_MASK BIT(30)
+#define PADRING_IFMUX_SHIFT27
+#define PADRING_IFMUX_MASK GENMASK(29, 27)
+#define PADRING_CONFIG_SHIFT 25
+#define PADRING_LPCONFIG_SHIFT 23
+#define PADRING_PULL_SHIFT 5
+#define PADRING_DSE_SHIFT 0
+
+#define MUX_PAD_CTRL_SHIFT 32
+#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x << MUX_PAD_CTRL_SHIFT)
+#define MUX_PAD_CTRL(x)((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+#define MUX_MODE_SHIFT (PADRING_IFMUX_SHIFT + MUX_PAD_CTRL_SHIFT)
+#define MUX_MODE_MASK ((iomux_cfg_t)0x7 << MUX_MODE_SHIFT)
+#define PIN_ID_MASK((iomux_cfg_t)0x)
+
+/* Valid mux alt0 to alt7 */
+#define MUX_MODE_ALT(x)(((iomux_cfg_t)(x) << MUX_MODE_SHIFT) &
\
+MUX_MODE_MASK)
+
+void imx8_iomux_setup_pad(iomux_cfg_t pad);
+void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count);
+#endif /* __ASM_ARCH_IMX8_IOMUX_H__ */
diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile
index 57876139a1..31ad169ccf 100644
--- a/arch/arm/mach-imx/imx8/Makefile
+++ b/arch/arm/mach-imx/imx8/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += cpu.o
+obj-y += cpu.o iomux.o
diff --git a/arch/arm/mach-imx/imx8/iomux.c b/arch/arm/mach-imx/imx8/iomux.c
new file mode 100644
index 00..0ade85fb8f
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/iomux.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * configures a single pad in the iomuxer
+ */
+void imx8_iomux_setup_pad(iomux_cfg_t pad)
+{
+ sc_pad_t pin_id = pad & PIN_ID_MASK;
+ int ret;
+
+ u32 val = (u32)((pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT);
+
+ val |= PADRING_IFMUX_EN_MASK;
+ val |= PADRING_GP_EN_MASK;
+
+ ret = sc_pad_set(-1, pin_id, val);
+ if (ret)
+ printf("sc_pad_set failed!, pin: %u, val: 0x%x\n", pin_id, val);
+
+ debug("iomux: pin %d, val = 0x%x\n", pin_id, val);
+}
+
+/* configures a list of pads within declared with IOMUX_PADS macro */
+void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count)
+{
+ iomux_cfg_t const *p = pad_list;
+ int i;
+
+ for (i = 0; i < count; i++) {
+ imx8_iomux_setup_pad(*p);
+ p++;
+ }
+}
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 09/32] arm: global_data: add scu_dev for i.MX8
Add scu_dev for i.MX8, this will be used as a handle
to communite with SCU from A35.
Signed-off-by: Peng Fan
Cc: Stefano Babic
---
arch/arm/include/asm/global_data.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index 287a7bd5b1..c3ee5f0c7b 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -74,6 +74,10 @@ struct arch_global_data {
#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR)
unsigned long mem2_clk;
#endif
+
+#ifdef CONFIG_ARCH_IMX8
+ struct udevice *scu_dev;
+#endif
};
#include
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 08/32] misc: imx8: add scfw api impementation
Add clk/misc/pad/pm/rm scfw api implementaion for different
drivers to invoke. The low level code is using misc_call
to invoke imx8_scu driver.
Signed-off-by: Peng Fan
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx8/sci/sci.h | 31 +-
drivers/misc/imx8/Makefile | 2 +-
drivers/misc/imx8/clk.c | 93 ++
drivers/misc/imx8/misc.c | 88 +
drivers/misc/imx8/pad.c | 39 +
drivers/misc/imx8/pm.c | 38 +
drivers/misc/imx8/rm.c | 97
7 files changed, 386 insertions(+), 2 deletions(-)
create mode 100644 drivers/misc/imx8/clk.c
create mode 100644 drivers/misc/imx8/misc.c
create mode 100644 drivers/misc/imx8/pad.c
create mode 100644 drivers/misc/imx8/pm.c
create mode 100644 drivers/misc/imx8/rm.c
diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h
b/arch/arm/include/asm/arch-imx8/sci/sci.h
index b7280aee05..4704ba9699 100644
--- a/arch/arm/include/asm/arch-imx8/sci/sci.h
+++ b/arch/arm/include/asm/arch-imx8/sci/sci.h
@@ -46,7 +46,8 @@ static inline int sc_err_to_linux(sc_err_t err)
ret = -EIO;
break;
default:
- panic("Invalid sc_err_t value\n");
+ ret = 0;
+ break;
}
debug("%s %d %d\n", __func__, err, ret);
@@ -54,4 +55,32 @@ static inline int sc_err_to_linux(sc_err_t err)
return ret;
}
+/* PM API*/
+int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_pm_power_mode_t mode);
+int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+sc_pm_clock_rate_t *rate);
+int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+sc_pm_clock_rate_t *rate);
+int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+sc_pm_clock_rate_t *rate);
+int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+sc_pm_clock_rate_t *rate);
+int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+ sc_bool_t enable, sc_bool_t autog);
+
+/* MISC API */
+int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
+ u32 *val);
+void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev);
+void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
+
+/* RM API */
+sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
+int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start,
+ sc_faddr_t *addr_end);
+sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
+
+/* PAD API */
+int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val);
#endif
diff --git a/drivers/misc/imx8/Makefile b/drivers/misc/imx8/Makefile
index 3395340d22..4fc08ade50 100644
--- a/drivers/misc/imx8/Makefile
+++ b/drivers/misc/imx8/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
-obj-y += scu.o
+obj-y += pm.o clk.o misc.o pad.o rm.o scu.o
diff --git a/drivers/misc/imx8/clk.c b/drivers/misc/imx8/clk.c
new file mode 100644
index 00..13ac650d76
--- /dev/null
+++ b/drivers/misc/imx8/clk.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ *
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+sc_pm_clock_rate_t *rate)
+{
+ struct udevice *dev = gd->arch.scu_dev;
+ int size = sizeof(struct sc_rpc_msg_s);
+ struct sc_rpc_msg_s msg;
+ int ret;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (u8)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (u8)PM_FUNC_SET_CLOCK_RATE;
+ RPC_U32(&msg, 0U) = *(u32 *)rate;
+ RPC_U16(&msg, 4U) = (u16)resource;
+ RPC_U8(&msg, 6U) = (u8)clk;
+ RPC_SIZE(&msg) = 3U;
+
+ ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+ if (ret)
+ printf("%s: rate:%u resource:%u: clk:%u res:%d\n",
+ __func__, *rate, resource, clk, RPC_R8(&msg));
+
+ *rate = RPC_U32(&msg, 0U);
+
+ return ret;
+}
+
+int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+sc_pm_clock_rate_t *rate)
+{
+ struct udevice *dev = gd->arch.scu_dev;
+ int size = sizeof(struct sc_rpc_msg_s);
+ struct sc_rpc_msg_s msg;
+ int ret;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (u8)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (u8)PM_FUNC_GET_CLOCK_RATE;
+ RPC_U16(&msg, 0U) = (u16)resource;
+ RPC_U8(&msg, 2U) = (u8)clk;
+ RPC_SIZE(&msg) = 2U;
+
+ ret = misc_call(dev, SC_FAL
[U-Boot] [PATCH V3 06/32] arm: build mach-imx for i.MX8
Build mach-imx for i.MX8 Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index cac58bdc4d..40c8f6fe13 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -104,7 +104,7 @@ ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610)) libs-y += arch/arm/mach-imx/ endif endif -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 05/32] imx: add Kconfig entry for i.MX8QXP
Add Kconfig entry for i.MX8QXP Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/Kconfig | 8 arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/imx8/Kconfig | 13 + 3 files changed, 22 insertions(+) create mode 100644 arch/arm/mach-imx/imx8/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a047552ed3..958db8788d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -662,6 +662,12 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. +config ARCH_IMX8 + bool "NXP i.MX8 platform" + select ARM64 + select DM + select OF_CONTROL + config ARCH_MX8M bool "NXP i.MX8M platform" select ARM64 @@ -1397,6 +1403,8 @@ source "arch/arm/mach-imx/mx7/Kconfig" source "arch/arm/mach-imx/mx7ulp/Kconfig" +source "arch/arm/mach-imx/imx8/Kconfig" + source "arch/arm/mach-imx/mx8m/Kconfig" source "arch/arm/mach-imx/mxs/Kconfig" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 733c308670..375789efb2 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -141,3 +141,4 @@ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ obj-$(CONFIG_MX8M) += mx8m/ +obj-$(CONFIG_ARCH_IMX8) += imx8/ diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig new file mode 100644 index 00..28910c1509 --- /dev/null +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -0,0 +1,13 @@ +if ARCH_IMX8 + +config IMX8 + bool + +config IMX8QXP + select IMX8 + bool + +config SYS_SOC + default "imx8" + +endif -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V3 07/32] misc: add i.MX8 misc driver
Add i.MX8 MISC driver to handle the communication between
A35 Core and SCU.
Signed-off-by: Peng Fan
---
drivers/misc/Makefile | 1 +
drivers/misc/imx8/Makefile | 3 +
drivers/misc/imx8/scu.c| 247 +
3 files changed, 251 insertions(+)
create mode 100644 drivers/misc/imx8/Makefile
create mode 100644 drivers/misc/imx8/scu.c
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 4ce9d213f0..57d34dbd9a 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_FSL_IIM) += fsl_iim.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
+obj-$(CONFIG_IMX8) += imx8/
obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
diff --git a/drivers/misc/imx8/Makefile b/drivers/misc/imx8/Makefile
new file mode 100644
index 00..3395340d22
--- /dev/null
+++ b/drivers/misc/imx8/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += scu.o
diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c
new file mode 100644
index 00..3cc6b719e3
--- /dev/null
+++ b/drivers/misc/imx8/scu.c
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ *
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mu_type {
+ u32 tr[4];
+ u32 rr[4];
+ u32 sr;
+ u32 cr;
+};
+
+struct imx8_scu {
+ struct mu_type *base;
+ struct udevice *clk;
+ struct udevice *pinclk;
+};
+
+#define MU_CR_GIE_MASK 0xF000u
+#define MU_CR_RIE_MASK 0xF00u
+#define MU_CR_GIR_MASK 0xFu
+#define MU_CR_TIE_MASK 0xF0u
+#define MU_CR_F_MASK 0x7u
+#define MU_SR_TE0_MASK BIT(23)
+#define MU_SR_RF0_MASK BIT(27)
+#define MU_TR_COUNT4
+#define MU_RR_COUNT4
+static inline void mu_hal_init(struct mu_type *base)
+{
+ /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
+ clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK |
+MU_CR_TIE_MASK | MU_CR_GIR_MASK | MU_CR_F_MASK);
+}
+
+static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
+{
+ u32 mask = MU_SR_TE0_MASK >> reg_index;
+ u32 val;
+ int ret;
+
+ assert(reg_index < MU_TR_COUNT);
+
+ /* Wait TX register to be empty. */
+ ret = readl_poll_timeout(&base->sr, val, val & mask, 1);
+ if (ret < 0) {
+ printf("%s timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ writel(msg, &base->tr[reg_index]);
+
+ return 0;
+}
+
+static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg)
+{
+ u32 mask = MU_SR_RF0_MASK >> reg_index;
+ u32 val;
+ int ret;
+
+ assert(reg_index < MU_TR_COUNT);
+
+ /* Wait RX register to be full. */
+ ret = readl_poll_timeout(&base->sr, val, val & mask, 1);
+ if (ret < 0) {
+ printf("%s timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ *msg = readl(&base->rr[reg_index]);
+
+ return 0;
+}
+
+static void sc_ipc_read(struct mu_type *base, void *data)
+{
+ struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
+ u8 count = 0;
+
+ /* Check parms */
+ if (!base || !msg)
+ return;
+
+ /* Read first word */
+ mu_hal_receivemsg(base, 0, (u32 *)msg);
+ count++;
+
+ /* Check size */
+ if (msg->size > SC_RPC_MAX_MSG) {
+ *((u32 *)msg) = 0;
+ return;
+ }
+
+ /* Read remaining words */
+ while (count < msg->size) {
+ mu_hal_receivemsg(base, count % MU_RR_COUNT,
+ &msg->DATA.u32[count - 1]);
+ count++;
+ }
+}
+
+static void sc_ipc_write(struct mu_type *base, void *data)
+{
+ struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
+ u8 count = 0;
+
+ /* Check parms */
+ if (!base || !msg)
+ return;
+
+ /* Check size */
+ if (msg->size > SC_RPC_MAX_MSG)
+ return;
+
+ /* Write first word */
+ mu_hal_sendmsg(base, 0, *((u32 *)msg));
+ count++;
+
+ /* Write remaining words */
+ while (count < msg->size) {
+ mu_hal_sendmsg(base, count % MU_TR_COUNT,
+ msg->DATA.u32[count - 1]);
+ count++;
+ }
+}
+
+/*
+ * Note the function prototype use msgid as the 2nd parameter, here
+ * we take it as no_resp.
+ */
+static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
+int tx_size, void *rx_msg, int rx_size)
+{
+ struct imx8_scu *priv = dev_get_priv(dev);
+ s
[U-Boot] [PATCH V3 04/32] imx8: add scfw macro definition
Add SCFW macro definition.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8/sci/rpc.h | 158
arch/arm/include/asm/arch-imx8/sci/sci.h | 57 ++
arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h | 30 +++
arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h | 57 ++
arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h | 44 +
arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h | 69 +++
arch/arm/include/asm/arch-imx8/sci/types.h| 220 ++
7 files changed, 635 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8/sci/rpc.h
create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h
create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
create mode 100644 arch/arm/include/asm/arch-imx8/sci/types.h
diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h
b/arch/arm/include/asm/arch-imx8/sci/rpc.h
new file mode 100644
index 00..746c2fa24d
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2018 NXP
+ *
+ */
+
+#ifndef SC_RPC_H
+#define SC_RPC_H
+
+/* Note: Check SCFW API Released DOC before you want to modify something */
+#define SC_RPC_VERSION 1U
+
+#define SC_RPC_MAX_MSG 8U
+
+#define RPC_VER(MSG)((MSG)->version)
+#define RPC_SIZE(MSG) ((MSG)->size)
+#define RPC_SVC(MSG)((MSG)->svc)
+#define RPC_FUNC(MSG) ((MSG)->func)
+#define RPC_R8(MSG) ((MSG)->func)
+#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U])
+#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U])
+#define RPC_I8(MSG, IDX)((MSG)->DATA.i8[(IDX)])
+#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U])
+#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U])
+#define RPC_U8(MSG, IDX)((MSG)->DATA.u8[(IDX)])
+
+#define SC_RPC_SVC_UNKNOWN 0U
+#define SC_RPC_SVC_RETURN 1U
+#define SC_RPC_SVC_PM 2U
+#define SC_RPC_SVC_RM 3U
+#define SC_RPC_SVC_TIMER5U
+#define SC_RPC_SVC_PAD 6U
+#define SC_RPC_SVC_MISC 7U
+#define SC_RPC_SVC_IRQ 8U
+#define SC_RPC_SVC_ABORT9U
+
+/* Types */
+
+struct sc_rpc_msg_s {
+ u8 version;
+ u8 size;
+ u8 svc;
+ u8 func;
+ union {
+ s32 i32[(SC_RPC_MAX_MSG - 1U)];
+ s16 i16[(SC_RPC_MAX_MSG - 1U) * 2U];
+ s8 i8[(SC_RPC_MAX_MSG - 1U) * 4U];
+ u32 u32[(SC_RPC_MAX_MSG - 1U)];
+ u16 u16[(SC_RPC_MAX_MSG - 1U) * 2U];
+ u8 u8[(SC_RPC_MAX_MSG - 1U) * 4U];
+ } DATA;
+};
+
+/* PM RPC */
+#define PM_FUNC_UNKNOWN0
+#define PM_FUNC_SET_SYS_POWER_MODE 19U
+#define PM_FUNC_SET_PARTITION_POWER_MODE 1U
+#define PM_FUNC_GET_SYS_POWER_MODE 2U
+#define PM_FUNC_SET_RESOURCE_POWER_MODE3U
+#define PM_FUNC_GET_RESOURCE_POWER_MODE4U
+#define PM_FUNC_REQ_LOW_POWER_MODE 16U
+#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U
+#define PM_FUNC_SET_CPU_RESUME_ADDR17U
+#define PM_FUNC_SET_CPU_RESUME 21U
+#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U
+#define PM_FUNC_SET_CLOCK_RATE 5U
+#define PM_FUNC_GET_CLOCK_RATE 6U
+#define PM_FUNC_CLOCK_ENABLE 7U
+#define PM_FUNC_SET_CLOCK_PARENT 14U
+#define PM_FUNC_GET_CLOCK_PARENT 15U
+#define PM_FUNC_RESET 13U
+#define PM_FUNC_RESET_REASON 10U
+#define PM_FUNC_BOOT 8U
+#define PM_FUNC_REBOOT 9U
+#define PM_FUNC_REBOOT_PARTITION 12U
+#define PM_FUNC_CPU_START 11U
+
+/* MISC RPC */
+#define MISC_FUNC_UNKNOWN 0
+#define MISC_FUNC_SET_CONTROL 1U
+#define MISC_FUNC_GET_CONTROL 2U
+#define MISC_FUNC_SET_MAX_DMA_GROUP4U
+#define MISC_FUNC_SET_DMA_GROUP5U
+#define MISC_FUNC_SECO_IMAGE_LOAD 8U
+#define MISC_FUNC_SECO_AUTHENTICATE9U
+#define MISC_FUNC_SECO_FUSE_WRITE 20U
+#define MISC_FUNC_SECO_ENABLE_DEBUG21U
+#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U
+#define MISC_FUNC_SECO_RETURN_LIFECYCLE23U
+#define MISC_FUNC_SECO_BUILD_INFO 24U
+#define MISC_FUNC_DEBUG_OUT10U
+#define MISC_FUNC_WAVEFORM_CAPTURE 6U
+#define MISC_FUNC_BUILD_INFO 15U
+#define MISC_FUNC_UNIQUE_ID19U
+#define MISC_FUNC_SET_ARI 3U
+#define
[U-Boot] [PATCH V3 03/32] dt-bindings: soc: add i.MX8QXP pm and rsrc definition
Add i.MX8QXP power and resource definition Signed-off-by: Peng Fan Cc: Stefano Babic --- include/dt-bindings/soc/imx8_pd.h | 188 + include/dt-bindings/soc/imx_rsrc.h | 557 + 2 files changed, 745 insertions(+) create mode 100644 include/dt-bindings/soc/imx8_pd.h create mode 100644 include/dt-bindings/soc/imx_rsrc.h diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h new file mode 100644 index 00..682b608eef --- /dev/null +++ b/include/dt-bindings/soc/imx8_pd.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __DT_BINDINGS_IMX8_PD_H +#define __DT_BINDINGS_IMX8_PD_H + +/*! + * These defines are used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +#define PD_DC_0 dc0_power_domain +#define PD_DC_0_PLL_0 dc0_pll0 +#define PD_DC_0_PLL_1 dc0_pll1 +#define PD_LVDS0lvds0_power_domain +#define PD_LVDS0_I2C0 lvds0_i2c0 +#define PD_LVDS0_I2C1 lvds0_i2c1 +#define PD_LVDS0_PWMlvds0_pwm +#define PD_LVDS0_PWMlvds0_pwm +#define PD_LVDS0_GPIO lvds0_gpio +#define PD_DC_1 dc1_power_domain +#define PD_DC_1_PLL_0 dc1_pll0 +#define PD_DC_1_PLL_1 dc1_pll1 +#define PD_LVDS1lvds1_power_domain +#define PD_LVDS1_I2C0 lvds1_i2c0 +#define PD_LVDS1_I2C1 lvds1_i2c1 +#define PD_LVDS1_PWMlvds1_pwm +#define PD_LVDS1_GPIO lvds1_gpio + +#define PD_DMA dma_power_domain +#define PD_DMA_SPI_0dma_spi0 +#define PD_DMA_SPI_1dma_spi1 +#define PD_DMA_SPI_2dma_spi2 +#define PD_DMA_SPI_3dma_spi3 +#define PD_DMA_UART0dma_lpuart0 +#define PD_DMA_UART1dma_lpuart1 +#define PD_DMA_UART2dma_lpuart2 +#define PD_DMA_UART3dma_lpuart3 +#define PD_DMA_UART4dma_lpuart4 +#define PD_DMA_EMVSIM_0 dma_emvsim0 +#define PD_DMA_EMVSIM_1 dma_emvsim1 +#define PD_DMA_I2C_0dma_lpi2c0 +#define PD_DMA_I2C_1dma_lpi2c1 +#define PD_DMA_I2C_2dma_lpi2c2 +#define PD_DMA_I2C_3dma_lpi2c3 +#define PD_DMA_I2C_4dma_lpi2c4 +#define PD_DMA_ADC_0dma_adc0 +#define PD_DMA_ADC_1dma_adc1 +#define PD_DMA_FTM_0dma_ftm0 +#define PD_DMA_FTM_1dma_ftm1 +#define PD_DMA_CAN_0dma_flexcan0 +#define PD_DMA_CAN_1dma_flexcan1 +#define PD_DMA_CAN_2dma_flexcan2 +#define PD_DMA_PWM_0dma_pwm0 +#define PD_DMA_LCD_0dma_lcd0 + +#define PD_HSIO hsio_power_domain +#define PD_HSIO_PCIE_A hsio_pcie0 +#define PD_HSIO_PCIE_B hsio_pcie1 +#define PD_HSIO_SATA_0 hsio_sata0 +#define PD_HSIO_GPIOhsio_gpio + +#define PD_LCD_0lcd0_power_domain +#define PD_LCD_0_I2C_0 lcd0_i2c0 +#define PD_LCD_0_I2C_1 lcd0_i2c1 +#define PD_LCD_PWM_0lcd0_pwm0 + +#define PD_LSIO lsio_power_domain +#define PD_LSIO_GPIO_0 lsio_gpio0 +#define PD_LSIO_GPIO_1 lsio_gpio1 +#define PD_LSIO_GPIO_2 lsio_gpio2 +#define PD_LSIO_GPIO_3 lsio_gpio3 +#define PD_LSIO_GPIO_4 lsio_gpio4 +#define PD_LSIO_GPIO_5 lsio_gpio5 +#define PD_LSIO_GPIO_6 lsio_gpio6 +#define PD_LSIO_GPIO_7 lsio_gpio7 +#define PD_LSIO_GPT_0 lsio_gpt0 +#define PD_LSIO_GPT_1 lsio_gpt1 +#define PD_LSIO_GPT_2 lsio_gpt2 +#define PD_LSIO_GPT_3 lsio_gpt3 +#define PD_LSIO_GPT_4 lsio_gpt4 +#define PD_LSIO_KPP lsio_kpp +#define PD_LSIO_FSPI_0 lsio_fspi0 +#define PD_LSIO_FSPI_1 lsio_fspi1 +#define PD_LSIO_PWM_0 lsio_pwm0 +#define PD_LSIO_PWM_1 lsio_pwm1 +#define PD_LSIO_PWM_2 lsio_pwm2 +#define PD_LSIO_PWM_3 lsio_pwm3 +#define PD_LSIO_PWM_4 lsio_pwm4 +#define PD_LSIO_PWM_5 lsio_pwm5 +#define PD_LSIO_PWM_6 lsio_pwm6 +#define PD_LSIO_PWM_7 lsio_pwm7 + +#define PD_CONN connectivity_power_domain +#define PD_CONN_SDHC_0 conn_sdhc0 +#define PD_CONN_SDHC_1 conn_sdhc1 +#define PD_CONN_SDHC_2 conn_sdhc2 +#define PD_CONN_ENET_0 conn_enet0 +#define PD_CONN_ENET_1 conn_enet1 +#define PD_
[U-Boot] [PATCH V3 02/32] dt-bindings: clock: dt-bindings: pinctrl: add i.MX8QXP clocks definition
Add i.MX8QXP clocks definition Signed-off-by: Peng Fan --- include/dt-bindings/clock/imx8qxp-clock.h | 583 ++ 1 file changed, 583 insertions(+) create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h new file mode 100644 index 00..d0334ea398 --- /dev/null +++ b/include/dt-bindings/clock/imx8qxp-clock.h @@ -0,0 +1,583 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H +#define __DT_BINDINGS_CLOCK_IMX8QXP_H + +#define IMX8QXP_CLK_DUMMY 0 + +#define IMX8QXP_UART0_IPG_CLK 1 +#define IMX8QXP_UART0_DIV 2 +#define IMX8QXP_UART0_CLK 3 + +#define IMX8QXP_IPG_DMA_CLK_ROOT 4 + +/* GPU Clocks. */ +#define IMX8QXP_GPU0_CORE_DIV 5 +#define IMX8QXP_GPU0_CORE_CLK 6 +#define IMX8QXP_GPU0_SHADER_DIV7 +#define IMX8QXP_GPU0_SHADER_CLK8 + +#define IMX8QXP_24MHZ 9 +#define IMX8QXP_GPT_3M 10 +#define IMX8QXP_32KHZ 11 + +/* LSIO SS */ +#define IMX8QXP_LSIO_MEM_CLK 12 +#define IMX8QXP_LSIO_BUS_CLK 13 +#define IMX8QXP_LSIO_PWM0_DIV 14 +#define IMX8QXP_LSIO_PWM0_IPG_S_CLK15 +#define IMX8QXP_LSIO_PWM0_IPG_SLV_CLK 16 +#define IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK 17 +#define IMX8QXP_LSIO_PWM0_HF_CLK 18 +#define IMX8QXP_LSIO_PWM0_CLK 19 +#define IMX8QXP_LSIO_PWM1_DIV 20 +#define IMX8QXP_LSIO_PWM1_IPG_S_CLK21 +#define IMX8QXP_LSIO_PWM1_IPG_SLV_CLK 22 +#define IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK 23 +#define IMX8QXP_LSIO_PWM1_HF_CLK 24 +#define IMX8QXP_LSIO_PWM1_CLK 25 +#define IMX8QXP_LSIO_PWM2_DIV 26 +#define IMX8QXP_LSIO_PWM2_IPG_S_CLK27 +#define IMX8QXP_LSIO_PWM2_IPG_SLV_CLK 28 +#define IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK 29 +#define IMX8QXP_LSIO_PWM2_HF_CLK 30 +#define IMX8QXP_LSIO_PWM2_CLK 31 +#define IMX8QXP_LSIO_PWM3_DIV 32 +#define IMX8QXP_LSIO_PWM3_IPG_S_CLK33 +#define IMX8QXP_LSIO_PWM3_IPG_SLV_CLK 34 +#define IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK 35 +#define IMX8QXP_LSIO_PWM3_HF_CLK 36 +#define IMX8QXP_LSIO_PWM3_CLK 37 +#define IMX8QXP_LSIO_PWM4_DIV 38 +#define IMX8QXP_LSIO_PWM4_IPG_S_CLK39 +#define IMX8QXP_LSIO_PWM4_IPG_SLV_CLK 40 +#define IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK 42 +#define IMX8QXP_LSIO_PWM4_HF_CLK 43 +#define IMX8QXP_LSIO_PWM4_CLK 44 +#define IMX8QXP_LSIO_PWM5_DIV 45 +#define IMX8QXP_LSIO_PWM5_IPG_S_CLK46 +#define IMX8QXP_LSIO_PWM5_IPG_SLV_CLK 47 +#define IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK 48 +#define IMX8QXP_LSIO_PWM5_HF_CLK 49 +#define IMX8QXP_LSIO_PWM5_CLK 50 +#define IMX8QXP_LSIO_PWM6_DIV 51 +#define IMX8QXP_LSIO_PWM6_IPG_S_CLK52 +#define IMX8QXP_LSIO_PWM6_IPG_SLV_CLK 53 +#define IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK 54 +#define IMX8QXP_LSIO_PWM6_HF_CLK 55 +#define IMX8QXP_LSIO_PWM6_CLK 56 +#define IMX8QXP_LSIO_PWM7_DIV 57 +#define IMX8QXP_LSIO_PWM7_IPG_S_CLK58 +#define IMX8QXP_LSIO_PWM7_IPG_SLV_CLK 59 +#define IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK 60 +#define IMX8QXP_LSIO_PWM7_HF_CLK 61 +#define IMX8QXP_LSIO_PWM7_CLK 62 +#define IMX8QXP_LSIO_GPT0_DIV 63 +#define IMX8QXP_LSIO_GPT0_IPG_S_CLK64 +#define IMX8QXP_LSIO_GPT0_IPG_SLV_CL
[U-Boot] [PATCH V3 01/32] dt-bindings: pinctrl: add i.MX8QXP pads definition
Add i.MX8QXP pads definition Signed-off-by: Peng Fan Cc: Stefano Babic --- include/dt-bindings/pinctrl/pads-imx8qxp.h | 757 + 1 file changed, 757 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h new file mode 100644 index 00..41f4fe564c --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h @@ -0,0 +1,757 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _SC_PADS_H +#define _SC_PADS_H + +#define SC_P_PCIE_CTRL0_PERST_B 0 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */ +#define SC_P_PCIE_CTRL0_WAKE_B 2 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /* */ +#define SC_P_USB_SS3_TC0 4 /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 5 /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 6 /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 7 /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO8 /* */ +#define SC_P_EMMC0_CLK 9 /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ +#define SC_P_EMMC0_CMD 10/* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */ +#define SC_P_EMMC0_DATA0 11/* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */ +#define SC_P_EMMC0_DATA1 12/* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */ +#define SC_P_EMMC0_DATA2 13/* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */ +#define SC_P_EMMC0_DATA3 14/* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15/* */ +#define SC_P_EMMC0_DATA4 16/* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */ +#define SC_P_EMMC0_DATA5 17/* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */ +#define SC_P_EMMC0_DATA6 18/* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */ +#define SC_P_EMMC0_DATA7 19/* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */ +#define SC_P_EMMC0_STROBE20/* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */ +#define SC_P_EMMC0_RESET_B 21/* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22/* */ +#define SC_P_USDHC1_RESET_B 23/* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */ +#define SC_P_USDHC1_VSELECT 24/* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */ +#define SC_P_CTL_NAND_RE_P_N 25/* */ +#define SC_P_USDHC1_WP 26/* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */ +#define SC_P_USDHC1_CD_B 27/* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_CTL_NAND_DQS_P_N28/* */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29/* */ +#define SC_P_USDHC1_CLK 30/* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */ +#define SC_P_USDHC1_CMD 31/* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */ +#define SC_P_USDHC1_DATA032/* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */ +#define SC_P_USDHC1_DATA133/* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */ +#define SC_P_USDHC1_DATA234/* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */ +#define SC_P_USDHC1_DATA335/* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36/* */ +#define SC_P_ENET0_RGMII_TXC 37/* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */ +#define SC_P_ENET0_RGMII_TX_CTL 38/* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */ +#define SC_P_ENET0_RGMII_TXD039
[U-Boot] [PATCH V3 00/32] i.MX: Add i.MX8QXP support
This patchset is to upstream i.MX8QXP and mek board support, with some drivers update to support i.MX8QXP. The information about the processor could be found https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X The architecture of i.MX8QXP is different from i.MX6/7/8M, inside i.MX8QXP, there is a dedicated processor(SCU) used for power/clock/pin/ pad/resource management/thermal and etc. V3: patch 7: use CONFIG_IMX8 patch 29: use CONFIG_IMX8 patch 32: Added README with scfw_tcm.bin link added misc: remove sc_rpc_msg_t typedef, use struct sc_rpc_msg_s in patchset. V2: In this V2 patchset, the SCFW API is replaced by uclass driver implementation, but the api name is not changed from scfw api. The related macro definitions are kept in different api.h file following SCFW API file structure. Impelemnted scu misc driver to handle the low level communication between Acore and SCU. Implemented rm/pm/pad/misc protocol code to invoke misc_call for different functionality. The dm clk/pinctrl/power and others will invokde the protocol api to communicate with SCU. The arch/arm/mach-imx/imx8/clock.c currently is only a dummy file to avoid build break for mxc_get_clock. The i2c patch and common power domain patches are removed from this patchset. The imx8 name still kept, this is because NXP marketing requires to use this name for i.MX branding. Peng Fan (30): dt-bindings: pinctrl: add i.MX8QXP pads definition dt-bindings: clock: dt-bindings: pinctrl: add i.MX8QXP clocks definition dt-bindings: soc: add i.MX8QXP pm and rsrc definition imx8: add scfw macro definition imx: add Kconfig entry for i.MX8QXP arm: build mach-imx for i.MX8 misc: add i.MX8 misc driver misc: imx8: add scfw api impementation arm: global_data: add scu_dev for i.MX8 imx: boot_mode: Add FLEXSPI boot entry imx8: add imx-regs header file imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined imx: add i.MX8 cpu type armv8: add cpu core helper functions imx8: add basic cpu support imx8: add boot device detection imx8: implement mmc_get_env_dev imx8: add mmu and dram related functiions imx8: add arch_cpu_init arch_cpu_init_dm imx8: add iomux configuration api imx8: add dummy clock gpio: mxc_gpio: add support for i.MX8 pinctrl: Add pinctrl driver for i.MX8 power: Add power domain driver for i.MX8 clk: imx: add clk driver for i.MX8QXP serial_lpuart: Update lpuart driver to support i.MX8 serial: lpuart: support uclass clk api mmc: fsl_esdhc: add uclass clk support arm: dts: introduce dtsi for i.MX8QXP imx: add i.MX8QXP MEK board support Ye Li (2): serial: lpuart: Enable RX and TX FIFO fsl_esdhc: Update usdhc driver to support i.MX8 arch/arm/Kconfig | 8 + arch/arm/Makefile | 2 +- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8-ca35.dtsi | 66 ++ arch/arm/dts/fsl-imx8dx.dtsi | 444 + arch/arm/dts/fsl-imx8dxp.dtsi | 11 + arch/arm/dts/fsl-imx8qxp-mek.dts | 136 arch/arm/dts/fsl-imx8qxp.dtsi | 51 ++ arch/arm/include/asm/arch-imx/cpu.h | 5 + arch/arm/include/asm/arch-imx8/clock.h| 27 + arch/arm/include/asm/arch-imx8/gpio.h | 21 + arch/arm/include/asm/arch-imx8/imx-regs.h | 46 ++ arch/arm/include/asm/arch-imx8/imx8-pins.h| 15 + arch/arm/include/asm/arch-imx8/iomux.h| 40 ++ arch/arm/include/asm/arch-imx8/power-domain.h | 15 + arch/arm/include/asm/arch-imx8/sci/rpc.h | 158 + arch/arm/include/asm/arch-imx8/sci/sci.h | 86 +++ arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h | 30 + arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h | 57 ++ arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h | 44 ++ arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h | 69 ++ arch/arm/include/asm/arch-imx8/sci/types.h| 220 +++ arch/arm/include/asm/arch-imx8/sys_proto.h| 19 + arch/arm/include/asm/armv8/cpu.h | 26 + arch/arm/include/asm/global_data.h| 4 + arch/arm/include/asm/mach-imx/boot_mode.h | 1 + arch/arm/include/asm/mach-imx/sys_proto.h | 3 + arch/arm/mach-imx/Makefile| 1 + arch/arm/mach-imx/imx8/Kconfig| 26 + arch/arm/mach-imx/imx8/Makefile | 7 + arch/arm/mach-imx/imx8/clock.c| 21 + arch/arm/mach-imx/imx8/cpu.c | 544 arch/arm/mach-imx/imx8/iomux.c| 43 ++ board/freescale/imx8qxp_mek/Kconfig | 14 + board/freescale/imx8qxp_mek/MAINTAINERS | 6
[U-Boot] [PATCH 3/5] arm: socfpga: cyclone5: handle debug uart
If CONFIG_DEBUG_UART is enabled, correctly initialize
the debug uart before console is initialized to debug
early boot problems in SPL.
This also changes a printf in reset_manager_gen5 to
a debug to prevent calling into debug uart before it
is initialized.
Signed-off-by: Simon Goldschmidt
---
arch/arm/mach-socfpga/reset_manager_gen5.c | 5 +++--
arch/arm/mach-socfpga/spl_gen5.c | 6 ++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c
b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 25baef79bc..3dfa09b742 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -89,8 +89,9 @@ void socfpga_bridges_reset(int enable)
/* Check signal from FPGA. */
if (!fpgamgr_test_fpga_ready()) {
/* FPGA not ready, do nothing. We allow system to boot
-* without FPGA ready. So, return 0 instead of error. */
- printf("%s: FPGA not ready, aborting.\n", __func__);
+* without FPGA ready.
+*/
+ debug("%s: FPGA not ready, aborting.\n", __func__);
return;
}
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 0d5526656d..0e685f6ee5 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
@@ -153,6 +154,11 @@ void board_init_f(ulong dummy)
/* unfreeze / thaw all IO banks */
sys_mgr_frzctrl_thaw_req();
+#ifdef CONFIG_DEBUG_UART
+ socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
+ debug_uart_init();
+#endif
+
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 5/5] malloc_simple: calloc: don't call memset if malloc failed
malloc_simple() can return 0 if out of memory. Don't call memset from calloc() in this case but rely on the caller checking the return value. Signed-off-by: Simon Goldschmidt --- common/malloc_simple.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/malloc_simple.c b/common/malloc_simple.c index c14f8b59c1..871b5444bd 100644 --- a/common/malloc_simple.c +++ b/common/malloc_simple.c @@ -57,7 +57,8 @@ void *calloc(size_t nmemb, size_t elem_size) void *ptr; ptr = malloc(size); - memset(ptr, '\0', size); + if (ptr) + memset(ptr, '\0', size); return ptr; } -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/5] board_init.c: fix simple malloc by storing malloc_limit
board_init_f_init_reserve() sets gd->malloc_base but does not set gd->malloc_limit. This results in malloc_simple() failing, so let's set this here. Signed-off-by: Simon Goldschmidt --- common/init/board_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/common/init/board_init.c b/common/init/board_init.c index 526fee35ff..a9b21a7111 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -123,6 +123,7 @@ void board_init_f_init_reserve(ulong base) #if CONFIG_VAL(SYS_MALLOC_F_LEN) /* go down one 'early malloc arena' */ gd->malloc_base = base; + gd->malloc_limit = CONFIG_VAL(SYS_MALLOC_F_LEN); /* next alloc will be higher by one 'early malloc arena' size */ base += CONFIG_VAL(SYS_MALLOC_F_LEN); #endif -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/5] arm: socfpga: fix device trees to work with DM serial
Device trees need to have the serial console device available
before relocation and require a stdout-path in chosen at least
for SPL to have a console.
Signed-off-by: Simon Goldschmidt
---
arch/arm/dts/socfpga.dtsi | 1 +
arch/arm/dts/socfpga_arria5_socdk.dts | 1 +
arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 1 +
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 1 +
arch/arm/dts/socfpga_cyclone5_de10_nano.dts| 1 +
arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 1 +
arch/arm/dts/socfpga_cyclone5_is1.dts | 1 +
arch/arm/dts/socfpga_cyclone5_socdk.dts| 1 +
arch/arm/dts/socfpga_cyclone5_sockit.dts | 1 +
arch/arm/dts/socfpga_cyclone5_socrates.dts | 6 ++
arch/arm/dts/socfpga_cyclone5_sr1500.dts | 1 +
arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 1 +
12 files changed, 17 insertions(+)
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 314449478d..0e5445cd1b 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -738,6 +738,7 @@
reg-io-width = <4>;
clocks = <&l4_sp_clk>;
clock-frequency = <1>;
+ u-boot,dm-pre-reloc;
};
uart1: serial1@ffc03000 {
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts
b/arch/arm/dts/socfpga_arria5_socdk.dts
index 449ba9cbb9..128f0c9762 100644
--- a/arch/arm/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
memory {
diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
index aeb327dd5b..8e01a27320 100644
--- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
aliases {
diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
index f4a98e4bb0..16b86ce631 100644
--- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
aliases {
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
index 7da2d8b043..9d40ce912e 100644
--- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
@@ -13,6 +13,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
aliases {
diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
index e6fadb4fc9..d7dd809162 100644
--- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
aliases {
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts
b/arch/arm/dts/socfpga_cyclone5_is1.dts
index aa1ce2c3e2..e6306fb285 100644
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
memory {
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts
b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 55c70abb02..b24c39e1a3 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
memory {
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts
b/arch/arm/dts/socfpga_cyclone5_sockit.dts
index 08d8356d80..734e682ed2 100644
--- a/arch/arm/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
aliases {
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts
b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 0d452ae300..7f9b48a839 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
aliases {
@@ -84,3 +85,8 @@
disable-over-current;
status = "okay";
};
+
[U-Boot] [PATCH 1/5] arm: socfpga: fix SPL on gen5 after moving to DM serial
There were some NULL pointers dereferenced because DM was used
too early without correct initialization.
This fixes commit 73172753f4f3 ("ARM: socfpga: Convert to DM serial")
Signed-off-by: Simon Goldschmidt
---
arch/arm/mach-socfpga/spl_gen5.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index d6fe7d35af..0d5526656d 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -86,6 +86,7 @@ void board_init_f(ulong dummy)
const struct cm_config *cm_default_cfg = cm_get_default_config();
unsigned long sdram_size;
unsigned long reg;
+ int ret;
/*
* First C code to run. Clear fake OCRAM ECC first as SBE
@@ -152,6 +153,12 @@ void board_init_f(ulong dummy)
/* unfreeze / thaw all IO banks */
sys_mgr_frzctrl_thaw_req();
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
/* enable console uart printing */
preloader_console_init();
@@ -177,7 +184,4 @@ void board_init_f(ulong dummy)
}
socfpga_bridges_reset(1);
-
- /* Configure simple malloc base pointer into RAM. */
- gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
}
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/5] Get socfpga gen5 SPL working again.
Socfpga gen5 SPL has been broken since moving to DM serial with v2018.07.. Also, U-Boot console output has been broken since then. This series fixes this and makes some related small improvements. Simon Goldschmidt (5): arm: socfpga: fix SPL on gen5 after moving to DM serial arm: socfpga: fix device trees to work with DM serial arm: socfpga: cyclone5: handle debug uart board_init.c: fix simple malloc by storing malloc_limit malloc_simple: calloc: don't call memset if malloc failed arch/arm/dts/socfpga.dtsi | 1 + arch/arm/dts/socfpga_arria5_socdk.dts | 1 + arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 1 + arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 1 + arch/arm/dts/socfpga_cyclone5_de10_nano.dts| 1 + arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 1 + arch/arm/dts/socfpga_cyclone5_is1.dts | 1 + arch/arm/dts/socfpga_cyclone5_socdk.dts| 1 + arch/arm/dts/socfpga_cyclone5_sockit.dts | 1 + arch/arm/dts/socfpga_cyclone5_socrates.dts | 6 ++ arch/arm/dts/socfpga_cyclone5_sr1500.dts | 1 + arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 1 + arch/arm/mach-socfpga/reset_manager_gen5.c | 5 +++-- arch/arm/mach-socfpga/spl_gen5.c | 16 +--- common/init/board_init.c | 1 + common/malloc_simple.c | 3 ++- 16 files changed, 36 insertions(+), 6 deletions(-) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/2] tpm: sandbox: fix wrong assignment with a simplification
The recv variable in sandbox_tpm2_fill_buf() is a pointer on a pointer
of a char array. It means accessing *recv is the char array pointer
itself while **recv is the first character of that array. There is no
need for such indirection here, so simplify the code.
Simplifying things will make the last assignment right: "*recv = NULL"
is now correct. The issue has been found by the following Coverity
Scan report:
CID 183371: Incorrect expression (UNUSED_VALUE)
Assigning value "4UL" to "*recv" here, but that stored value is overwritten
before it can be used.
232 *recv += sizeof(rc);
233
234 /* Add trailing \0 */
235 *recv = NULL;
While at simplifying things, use '\0' instead of NULL when adding an
empty char at the end of the buffer.
Reported-by: Tom Rini
Signed-off-by: Miquel Raynal
---
drivers/tpm/tpm2_tis_sandbox.c | 52 +-
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/tpm/tpm2_tis_sandbox.c b/drivers/tpm/tpm2_tis_sandbox.c
index b15ec732ad..f282ea6adf 100644
--- a/drivers/tpm/tpm2_tis_sandbox.c
+++ b/drivers/tpm/tpm2_tis_sandbox.c
@@ -215,24 +215,24 @@ static int sandbox_tpm2_check_readyness(struct udevice
*dev, int command)
return 0;
}
-static int sandbox_tpm2_fill_buf(u8 **recv, size_t *recv_len, u16 tag, u32 rc)
+static int sandbox_tpm2_fill_buf(u8 *recv, size_t *recv_len, u16 tag, u32 rc)
{
*recv_len = sizeof(tag) + sizeof(u32) + sizeof(rc);
/* Write tag */
- put_unaligned_be16(tag, *recv);
- *recv += sizeof(tag);
+ put_unaligned_be16(tag, recv);
+ recv += sizeof(tag);
/* Write length */
- put_unaligned_be32(*recv_len, *recv);
- *recv += sizeof(u32);
+ put_unaligned_be32(*recv_len, recv);
+ recv += sizeof(u32);
/* Write return code */
- put_unaligned_be32(rc, *recv);
- *recv += sizeof(rc);
+ put_unaligned_be32(rc, recv);
+ recv += sizeof(rc);
/* Add trailing \0 */
- *recv = NULL;
+ *recv = '\0';
return 0;
}
@@ -287,7 +287,7 @@ static int sandbox_tpm2_xfer(struct udevice *dev, const u8
*sendbuf,
printf("TPM2: Unmatching length, received: %ld, expected: %d\n",
send_size, length);
rc = TPM2_RC_SIZE;
- sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ sandbox_tpm2_fill_buf(recv, recv_len, tag, rc);
return 0;
}
@@ -295,13 +295,13 @@ static int sandbox_tpm2_xfer(struct udevice *dev, const
u8 *sendbuf,
sent += sizeof(command);
rc = sandbox_tpm2_check_readyness(dev, command);
if (rc) {
- sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ sandbox_tpm2_fill_buf(recv, recv_len, tag, rc);
return 0;
}
rc = sandbox_tpm2_check_session(dev, command, tag, &sent, &hierarchy);
if (rc) {
- sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ sandbox_tpm2_fill_buf(recv, recv_len, tag, rc);
return 0;
}
@@ -319,7 +319,7 @@ static int sandbox_tpm2_xfer(struct udevice *dev, const u8
*sendbuf,
tpm->startup_done = true;
- sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ sandbox_tpm2_fill_buf(recv, recv_len, tag, rc);
break;
case TPM2_CC_SELF_TEST:
@@ -335,7 +335,7 @@ static int sandbox_tpm2_xfer(struct udevice *dev, const u8
*sendbuf,
tpm->tests_done = true;
- sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ sandbox_tpm2_fill_buf(recv, recv_len, tag, rc);
break;
case TPM2_CC_CLEAR:
@@ -358,7 +358,7 @@ static int sandbox_tpm2_xfer(struct udevice *dev, const u8
*sendbuf,
tpm->pcr[i][j] = 0;
}
- sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ sandbox_tpm2_fill_buf(recv, recv_len, tag, rc);
break;
case TPM2_CC_HIERCHANGEAUTH:
@@ -372,7 +372,7 @@ static int sandbox_tpm2_xfer(struct udevice *dev, const u8
*sendbuf,
sent += new_pw_sz;
}
- sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ sandbox_tpm2_fill_buf(recv, recv_len, tag, rc);
break;
case TPM2_CC_GET_CAPABILITY:
@@ -392,7 +392,7 @@ static int sandbox_tpm2_xfer(struct udevice *dev, const u8
*sendbuf,
if (!property_count ||
property + property_count > TPM2_PROPERTY_NB) {
rc = TPM2_RC_HANDLE;
- return sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ return sandbox_tpm2_fill_buf(recv, recv_len, tag, rc);
}
/* Write tag */
@@ -445,7 +445,7 @@ static in
[U-Boot] [PATCH 1/2] tpm: sandbox: fix wrong check on pcr_map
The second check on pcr_map in sandbox_tpm2_xfer() is wrong. It should
check for pcr_map not being empty. Instead, it is a pure copy/paste of
the first check which is redundant.
This has been found thanks to a Coverity Scan report:
CID 183370: Memory - illegal accesses (UNINIT)
Using uninitialized value "pcr_index".
put_unaligned_be32(tpm->pcr_extensions[pcr_index], recv);
This is because pcr_index is initialized only if the user input is
correct, ie. at least one valid bit is set in pcr_map.
Fix the second check and also initialize pcr_index to 0 (which is
harmless in case of error) to make Coverity Scan happy.
Reported-by: Tom Rini
Signed-off-by: Miquel Raynal
---
drivers/tpm/tpm2_tis_sandbox.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/tpm/tpm2_tis_sandbox.c b/drivers/tpm/tpm2_tis_sandbox.c
index 66f6c9ba82..b15ec732ad 100644
--- a/drivers/tpm/tpm2_tis_sandbox.c
+++ b/drivers/tpm/tpm2_tis_sandbox.c
@@ -272,7 +272,7 @@ static int sandbox_tpm2_xfer(struct udevice *dev, const u8
*sendbuf,
u32 capability, property, property_count;
/* TPM2_PCR_Read/Extend variables */
- int pcr_index;
+ int pcr_index = 0;
u64 pcr_map = 0;
u32 selections, pcr_nb;
u16 alg;
@@ -483,8 +483,8 @@ static int sandbox_tpm2_xfer(struct udevice *dev, const u8
*sendbuf,
return sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
}
- if (pcr_map >> SANDBOX_TPM_PCR_NB) {
- printf("Wrong PCR map.\n");
+ if (!pcr_map) {
+ printf("Empty PCR map.\n");
rc = TPM2_RC_VALUE;
return sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
}
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-spi/master
On Sat, Aug 04, 2018 at 09:43:24PM +0530, Jagan Teki wrote: > Hi Tom, > > Please pull this PR. > > thanks, > Jagan. > > The following changes since commit a839c3641e4de98981695056eeeb2ec17ba1a4ab: > > ARM: tegra: align carveout size (2018-08-01 20:06:10 -0400) > > are available in the Git repository at: > > git://git.denx.de/u-boot-spi.git master > > for you to fetch changes up to 7f25d8179776226a8ecfbaad3d3a88e9acd89f28: > > arm: sunxi: Allwinner A10 SPI driver (2018-08-03 11:14:08 +0530) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-sunxi/master
On Tue, Jul 31, 2018 at 11:41:50PM +0530, Jagan Teki wrote: > Hi Tom, > > Please pull this PR. > > thanks, > Jagan. > > The following changes since commit 5a0007d481c0fcd2d422dd48b2a129dd8e8a272a: > > Prepare v2017.09-rc1 (2018-07-30 21:47:29 -0400) > > are available in the Git repository at: > > git://git.denx.de/u-boot-sunxi.git master > > for you to fetch changes up to 89a897fc4d78e31332e5899e977d8bf3c82abafa: > > board: sun50i: h6: Add OrangePi One Plus initial support (2018-07-31 > 20:50:01 +0530) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] m68k: ColdFire mcf5441x, add eSDHC support
This patch adds mcf5441x eSDHC support for the mcf5441x family.
Signed-off-by: Angelo Dureghello
---
arch/m68k/cpu/mcf5445x/cpu_init.c | 10 ++
arch/m68k/cpu/mcf5445x/speed.c | 2 ++
arch/m68k/include/asm/global_data.h | 3 +++
3 files changed, 15 insertions(+)
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c
b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 0b86020204..7632d9262c 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -173,6 +173,15 @@ void cpu_init_f(void)
/* Lowest slew rate for UART0,1,2 */
out_8(&gpio->srcr_uart, 0x00);
+
+#ifdef CONFIG_FSL_ESDHC
+ /* eSDHC pin as faster speed */
+ out_8(&gpio->srcr_sdhc, 0x03);
+
+ /* All esdhc pins as SD */
+ out_8(&gpio->par_sdhch, 0xff);
+ out_8(&gpio->par_sdhcl, 0xff);
+#endif
#endif /* CONFIG_MCF5441x */
#ifdef CONFIG_MCF5445x
@@ -534,4 +543,5 @@ void cfspi_release_bus(uint bus, uint cs)
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
#endif
}
+
#endif
diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c
index 5214730a0f..e15e32ebde 100644
--- a/arch/m68k/cpu/mcf5445x/speed.c
+++ b/arch/m68k/cpu/mcf5445x/speed.c
@@ -120,6 +120,8 @@ void setup_5441x_clocks(void)
temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
gd->bus_clk = vco / temp; /* bus clock */
+ temp = ((pdr & PLL_DR_OUTDIV3_BITS) >> 10) + 1;
+ gd->arch.sdhc_clk = vco / temp;
}
#endif
diff --git a/arch/m68k/include/asm/global_data.h
b/arch/m68k/include/asm/global_data.h
index aa0be8191a..188055e9d3 100644
--- a/arch/m68k/include/asm/global_data.h
+++ b/arch/m68k/include/asm/global_data.h
@@ -18,6 +18,9 @@ struct arch_global_data {
unsigned long vco_clk;
unsigned long flb_clk;
#endif
+#ifdef CONFIG_MCF5441x
+ unsigned long sdhc_clk;
+#endif
};
#include
--
2.18.0
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] m68k: fix multiple memory accesses on swap operations
On a
u32 val = __sw32(*addr);
multiple memory accesses are not welcome, since "addr" may
be an IO peripheral register address.
This patch changes __sw16/32 to perform a single memory
access for the source value.
Signed-off-by: Angelo Dureghello
---
arch/m68k/include/asm/byteorder.h | 34 ++-
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/arch/m68k/include/asm/byteorder.h
b/arch/m68k/include/asm/byteorder.h
index eb03b6a053..9179622250 100644
--- a/arch/m68k/include/asm/byteorder.h
+++ b/arch/m68k/include/asm/byteorder.h
@@ -10,21 +10,28 @@
#include
#ifdef __GNUC__
-#define __sw16(x) \
- ((__u16)( \
- (((__u16)(x) & (__u16)0x00ffU) << 8) | \
- (((__u16)(x) & (__u16)0xff00U) >> 8) ))
-#define __sw32(x) \
- ((__u32)( \
- (((__u32)(x)) << 24) | \
- (((__u32)(x) & (__u32)0xff00UL) << 8) | \
- (((__u32)(x) & (__u32)0x00ffUL) >> 8) | \
- (((__u32)(x)) >> 24) ))
+
+static inline __u32 __sw32(__u32 x)
+{
+ __u32 v = x;
+
+ return v << 24 |
+ (v & (__u32)0xff00UL) << 8 |
+ (v & (__u32)0x00ffUL) >> 8 |
+ v >> 24;
+}
+
+static inline __u16 __sw16(__u16 x)
+{
+ __u16 v = x;
+
+ return (v & (__u16)0x00ffU) << 8 |
+ (v & (__u16)0xff00U) >> 8;
+}
static __inline__ unsigned ld_le16(const volatile unsigned short *addr)
{
- unsigned result = *addr;
- return __sw16(result);
+ return __sw16(*addr);
}
static __inline__ void st_le16(volatile unsigned short *addr,
@@ -35,8 +42,7 @@ static __inline__ void st_le16(volatile unsigned short *addr,
static __inline__ unsigned ld_le32(const volatile unsigned *addr)
{
- unsigned result = *addr;
- return __sw32(result);
+ return __sw32(*addr);
}
static __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
--
2.18.0
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC 1/1] efi_loader: relocate pointer to tables
> From: Heinrich Schuchardt
> Date: Sat, 4 Aug 2018 23:16:06 +0200
>
> When applying a virtual memory map we have to update the pointer to the
> list of configuration tables.
>
> Fixes: 4182a129ef73 ("efi_loader: allocate configuration table array")
> Reported-by: Mark Kettenis
> Signed-off-by: Heinrich Schuchardt
> ---
> Hello Mark,
>
> could you, please, test if this solves the problem.
Works on my Orange Pi PC2.
So FWIW,
Tested-by: Mark Kettenis
Thanks,
Mark
> Best regards
>
> Heinrich
> ---
> lib/efi_loader/efi_runtime.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
> index 06958f23fa..45b7809dec 100644
> --- a/lib/efi_loader/efi_runtime.c
> +++ b/lib/efi_loader/efi_runtime.c
> @@ -360,6 +360,7 @@ static efi_status_t EFIAPI efi_set_virtual_address_map(
> efi_physical_addr_t map_start = map->physical_start;
> efi_physical_addr_t map_len = map->num_pages << EFI_PAGE_SHIFT;
> efi_physical_addr_t map_end = map_start + map_len;
> + u64 off = map->virtual_start - map_start;
>
> /* Adjust all mmio pointers in this region */
> list_for_each(lhandle, &efi_runtime_mmio) {
> @@ -370,11 +371,17 @@ static efi_status_t EFIAPI efi_set_virtual_address_map(
> link);
> if ((map_start <= lmmio->paddr) &&
> (map_end >= lmmio->paddr)) {
> - u64 off = map->virtual_start - map_start;
> uintptr_t new_addr = lmmio->paddr + off;
> *lmmio->ptr = (void *)new_addr;
> }
> }
> + if ((map_start <= (uintptr_t)systab.tables) &&
> + (map_end >= (uintptr_t)systab.tables)) {
> + char *ptr = (char *)systab.tables;
> +
> + ptr += off;
> + systab.tables = (struct efi_configuration_table *)ptr;
> + }
> }
>
> /* Move the actual runtime code over */
> --
> 2.18.0
>
>
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] drivers: esdhc: add support for coldfire mcf5441x family
Signed-off-by: Angelo Dureghello
---
drivers/mmc/fsl_esdhc.c | 21 -
include/fsl_esdhc.h | 1 +
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 4528345c67..e376926c53 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -26,6 +26,12 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_MCF5441x
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO
+#endif
+#endif
+
#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
IRQSTATEN_CINT | \
IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE
| \
@@ -399,7 +405,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc,
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
return 0;
#endif
-
esdhc_write32(®s->irqstat, -1);
sync();
@@ -987,8 +992,12 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv,
struct mmc *mmc)
/* Disable the BRR and BWR bits in IRQSTAT */
esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
+#ifdef CONFIG_MCF5441x
+ esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
+#else
/* Put the PROCTL reg back to the default */
esdhc_write32(®s->proctl, PROCTL_INIT);
+#endif
/* Set timout to the maximum value */
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
@@ -1014,7 +1023,6 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
return dm_gpio_get_value(&priv->cd_gpio);
#endif
#endif
-
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
udelay(1000);
@@ -1112,11 +1120,16 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
+
+#ifdef CONFIG_MCF5441x
+ /* ColdFire, using SDHC_DATA[3] for card detection */
+ esdhc_write32(®s->proctl, esdhc_read32(®s->proctl) | PROCTL_D3CD);
+#endif
+
cfg = &plat->cfg;
#ifndef CONFIG_DM_MMC
memset(cfg, '\0', sizeof(*cfg));
#endif
-
voltage_caps = 0;
caps = esdhc_read32(®s->hostcapblt);
@@ -1129,7 +1142,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
caps = caps | ESDHC_HOSTCAPBLT_VS33;
#endif
-
if (caps & ESDHC_HOSTCAPBLT_VS18)
voltage_caps |= MMC_VDD_165_195;
if (caps & ESDHC_HOSTCAPBLT_VS30)
@@ -1150,7 +1162,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
printf("voltage not supported by controller\n");
return -1;
}
-
if (priv->bus_width == 8)
cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
else if (priv->bus_width == 4)
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index acd8dd06f8..8dbd5249a7 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -106,6 +106,7 @@
#define PROCTL_INIT0x0020
#define PROCTL_DTW_4 0x0002
#define PROCTL_DTW_8 0x0004
+#define PROCTL_D3CD0x0008
#define CMDARG 0x0002e008
--
2.18.0
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] gpio: xilinx: Add support for using label property
Am 02.08.2018 um 13:31 schrieb Michal Simek:
Add support for reading label property from DT and set up bank name
based on that. If label property is not present full device node name is
used.
Signed-off-by: Michal Simek
---
drivers/gpio/xilinx_gpio.c | 14 --
drivers/gpio/zynq_gpio.c | 14 --
2 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c
index cccfa7561739..da50d1634570 100644
--- a/drivers/gpio/xilinx_gpio.c
+++ b/drivers/gpio/xilinx_gpio.c
@@ -224,8 +224,18 @@ static int xilinx_gpio_probe(struct udevice *dev)
{
struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-
- uc_priv->bank_name = dev->name;
+ const void *label_ptr;
+ void *label_c;
+ int size;
+
+ label_ptr = dev_read_prop(dev, "label", &size);
+ if (label_ptr) {
+ label_c = calloc(1, size);
+ memcpy(label_c, label_ptr, size);
+ uc_priv->bank_name = label_c;
This could be simplified by the function strdup.
+ } else {
+ uc_priv->bank_name = dev->name;
+ }
uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];
diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index 6fbaafb3fa3c..aa8d51e2f709 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -336,8 +336,18 @@ static int zynq_gpio_probe(struct udevice *dev)
{
struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-
- uc_priv->bank_name = dev->name;
+ const void *label_ptr;
+ void *label_c;
+ int size;
+
+ label_ptr = dev_read_prop(dev, "label", &size);
+ if (label_ptr) {
+ label_c = calloc(1, size);
+ memcpy(label_c, label_ptr, size);
+ uc_priv->bank_name = label_c;
+ } else {
+ uc_priv->bank_name = dev->name;
+ }
if (platdata->p_data)
uc_priv->gpio_count = platdata->p_data->ngpio;
Reviewed-by: Stefan Herbrechtsmeier
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] gpio: xilinx: Not read output values via regs
Am 02.08.2018 um 14:54 schrieb Michal Simek:
Reading registers for finding out output value is not working because
input value is read instead in case of tristate.
Reported-by: Stefan Herbrechtsmeier
Signed-off-by: Michal Simek
---
Changes in v2:
- Rebased on the top of reviewed patches
- Change logic in xilinx_gpio_get_value()
drivers/gpio/xilinx_gpio.c | 36
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c
index da50d1634570..4b4bf651642c 100644
--- a/drivers/gpio/xilinx_gpio.c
+++ b/drivers/gpio/xilinx_gpio.c
@@ -25,6 +25,11 @@ struct xilinx_gpio_platdata {
int bank_max[XILINX_GPIO_MAX_BANK];
int bank_input[XILINX_GPIO_MAX_BANK];
int bank_output[XILINX_GPIO_MAX_BANK];
+ u32 dout_default[XILINX_GPIO_MAX_BANK];
+};
+
+struct xilinx_gpio_privdata {
+ u32 output_val[XILINX_GPIO_MAX_BANK];
};
static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
@@ -54,6 +59,7 @@ static int xilinx_gpio_set_value(struct udevice *dev,
unsigned offset,
int value)
{
struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
int val, ret;
u32 bank, pin;
@@ -61,10 +67,10 @@ static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
if (ret)
return ret;
- val = readl(&platdata->regs->gpiodata + bank * 2);
+ val = priv->output_val[bank];
- debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x\n",
- __func__, (ulong)platdata->regs, value, offset, bank, pin);
+ debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
+ __func__, (ulong)platdata->regs, value, offset, bank, pin, val);
if (value)
val = val | (1 << pin);
@@ -73,12 +79,15 @@ static int xilinx_gpio_set_value(struct udevice *dev,
unsigned offset,
writel(val, &platdata->regs->gpiodata + bank * 2);
+ priv->output_val[bank] = val;
+
return val;
The return value is wrong. But this isn't related to this patch.
};
static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
{
struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
int val, ret;
u32 bank, pin;
@@ -89,7 +98,14 @@ static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
(ulong)platdata->regs, offset, bank, pin);
- val = readl(&platdata->regs->gpiodata + bank * 2);
+ if (platdata->bank_output[bank]) {
+ debug("%s: Read saved output value\n", __func__);
+ val = priv->output_val[bank];
+ } else {
+ debug("%s: Read input value from reg\n", __func__);
+ val = readl(&platdata->regs->gpiodata + bank * 2);
+ }
+
val = !!(val & (1 << pin));
return val;
@@ -223,6 +239,7 @@ static const struct dm_gpio_ops xilinx_gpio_ops = {
static int xilinx_gpio_probe(struct udevice *dev)
{
struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
const void *label_ptr;
void *label_c;
@@ -239,6 +256,11 @@ static int xilinx_gpio_probe(struct udevice *dev)
uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];
+ priv->output_val[0] = platdata->dout_default[0];
+
+ if (platdata->bank_max[1])
+ priv->output_val[1] = platdata->dout_default[1];
+
return 0;
}
@@ -255,6 +277,9 @@ static int xilinx_gpio_ofdata_to_platdata(struct udevice *dev)
"xlnx,all-inputs", 0);
platdata->bank_output[0] = dev_read_u32_default(dev,
"xlnx,all-outputs", 0);
+ platdata->dout_default[0] = dev_read_u32_default(dev,
+"xlnx,dout-default",
+0);
is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
if (is_dual) {
@@ -264,6 +289,8 @@ static int xilinx_gpio_ofdata_to_platdata(struct udevice
*dev)
"xlnx,all-inputs-2", 0);
platdata->bank_output[1] = dev_read_u32_default(dev,
"xlnx,all-outputs-2", 0);
+ platdata->dout_default[1] = dev_read_u32_default(dev,
+ "xlnx,dout-default-2", 0);
}
return 0;
@@ -282,4 +309,5 @@ U_BOOT_DRIVER(xilinx_gpio) = {
.ofdata_to_platdata = xilinx_gp
