[U-Boot] [PATCH v4 1/2] armv8: layerscape: move ns_dev[] define from h to c file.
Since more c files will include ns_access.h, this move will fix some
compiling warnings and make it sense.
Signed-off-by: Ran Wang
---
Change in v4:
- Apply same move for ls102xa
Change in v3:
- New file
.../include/asm/arch-fsl-layerscape/ns_access.h| 80 --
arch/arm/include/asm/arch-ls102xa/ns_access.h | 84 ---
board/freescale/common/ns_access.c | 167 +
3 files changed, 167 insertions(+), 164 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index 8ecff4d..2bbfab7 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -87,84 +87,4 @@ enum csu_cslx_ind {
CSU_CSLX_DSCR = 121,
};
-static struct csu_ns_dev ns_dev[] = {
-{CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
-{CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
-{CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
-{CSU_CSLX_IFC_MEM, CSU_ALL_RW},
-{CSU_CSLX_OCRAM, CSU_ALL_RW},
-{CSU_CSLX_GIC, CSU_ALL_RW},
-{CSU_CSLX_PCIE1, CSU_ALL_RW},
-{CSU_CSLX_OCRAM2, CSU_ALL_RW},
-{CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
-{CSU_CSLX_PCIE2, CSU_ALL_RW},
-{CSU_CSLX_SATA, CSU_ALL_RW},
-{CSU_CSLX_USB1, CSU_ALL_RW},
-{CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
-{CSU_CSLX_PCIE3, CSU_ALL_RW},
-{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
-{CSU_CSLX_USB3, CSU_ALL_RW},
-{CSU_CSLX_USB2, CSU_ALL_RW},
-{CSU_CSLX_PFE, CSU_ALL_RW},
-{CSU_CSLX_SERDES, CSU_ALL_RW},
-{CSU_CSLX_QDMA, CSU_ALL_RW},
-{CSU_CSLX_LPUART2, CSU_ALL_RW},
-{CSU_CSLX_LPUART1, CSU_ALL_RW},
-{CSU_CSLX_LPUART4, CSU_ALL_RW},
-{CSU_CSLX_LPUART3, CSU_ALL_RW},
-{CSU_CSLX_LPUART6, CSU_ALL_RW},
-{CSU_CSLX_LPUART5, CSU_ALL_RW},
-{CSU_CSLX_DSPI1, CSU_ALL_RW},
-{CSU_CSLX_QSPI, CSU_ALL_RW},
-{CSU_CSLX_ESDHC, CSU_ALL_RW},
-{CSU_CSLX_IFC, CSU_ALL_RW},
-{CSU_CSLX_I2C1, CSU_ALL_RW},
-{CSU_CSLX_I2C3, CSU_ALL_RW},
-{CSU_CSLX_I2C2, CSU_ALL_RW},
-{CSU_CSLX_DUART2, CSU_ALL_RW},
-{CSU_CSLX_DUART1, CSU_ALL_RW},
-{CSU_CSLX_WDT2, CSU_ALL_RW},
-{CSU_CSLX_WDT1, CSU_ALL_RW},
-{CSU_CSLX_EDMA, CSU_ALL_RW},
-{CSU_CSLX_SYS_CNT, CSU_ALL_RW},
-{CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
-{CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
-{CSU_CSLX_DDR, CSU_ALL_RW},
-{CSU_CSLX_QUICC, CSU_ALL_RW},
-{CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
-{CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
-{CSU_CSLX_SFP, CSU_ALL_RW},
-{CSU_CSLX_TMU, CSU_ALL_RW},
-{CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
-{CSU_CSLX_SCFG, CSU_ALL_RW},
-{CSU_CSLX_FM, CSU_ALL_RW},
-{CSU_CSLX_SEC5_5, CSU_ALL_RW},
-{CSU_CSLX_BM, CSU_ALL_RW},
-{CSU_CSLX_QM, CSU_ALL_RW},
-{CSU_CSLX_GPIO2, CSU_ALL_RW},
-{CSU_CSLX_GPIO1, CSU_ALL_RW},
-{CSU_CSLX_GPIO4, CSU_ALL_RW},
-{CSU_CSLX_GPIO3, CSU_ALL_RW},
-{CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
-{CSU_CSLX_CSU, CSU_ALL_RW},
-{CSU_CSLX_IIC4, CSU_ALL_RW},
-{CSU_CSLX_WDT4, CSU_ALL_RW},
-{CSU_CSLX_WDT3, CSU_ALL_RW},
-{CSU_CSLX_ESDHC2, CSU_ALL_RW},
-{CSU_CSLX_WDT5, CSU_ALL_RW},
-{CSU_CSLX_SAI2, CSU_ALL_RW},
-{CSU_CSLX_SAI1, CSU_ALL_RW},
-{CSU_CSLX_SAI4, CSU_ALL_RW},
-{CSU_CSLX_SAI3, CSU_ALL_RW},
-{CSU_CSLX_FTM2, CSU_ALL_RW},
-{CSU_CSLX_FTM1, CSU_ALL_RW},
-{CSU_CSLX_FTM4, CSU_ALL_RW},
-{CSU_CSLX_FTM3, CSU_ALL_RW},
-{CSU_CSLX_FTM6, CSU_ALL_RW},
-{CSU_CSLX_FTM5, CSU_ALL_RW},
-{CSU_CSLX_FTM8, CSU_ALL_RW},
-{CSU_CSLX_FTM7, CSU_ALL_RW},
-{CSU_CSLX_DSCR, CSU_ALL_RW},
-};
-
#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h
b/arch/arm/include/asm/arch-ls102xa/ns_access.h
index f414b73..b6daf32 100644
--- a/arch/arm/include/asm/arch-ls102xa/ns_access.h
+++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h
@@ -91,88 +91,4 @@ enum csu_cslx_ind {
CSU_CSLX_MAX,
};
-static struct csu_ns_dev ns_dev[] = {
- { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
- { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
- { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
- { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
- { CSU_CSLX_OCRAM, CSU_ALL_RW },
- { CSU_CSLX_GIC, CSU_ALL_RW },
- { CSU_CSLX_PCIE1, CSU_ALL_RW },
- { CSU_CSLX_OCRAM2, CSU_ALL_RW },
- { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
- { CSU_CSLX_PCIE2, CSU_ALL_RW },
- { CSU_CSLX_SATA, CSU_ALL_RW },
- { CSU_CSLX_USB3, CSU_ALL_RW },
- { CSU_CSLX_SERDES, CSU_ALL_RW },
- { CSU_CSLX_QDMA, CSU_ALL_RW },
- { CSU_CSLX_LPUART2, CSU_ALL_RW },
- { CSU_CSLX_LPUART1, CSU_ALL_RW },
- { CSU_CSLX_LPUART4, CSU_ALL_RW },
- { CSU_CSLX_LP
[U-Boot] [PATCH v4 2/2] armv8: layerscape: Enable EHCI access for LS1012A
Program Central Security Unit (CSU) to grant access
permission for USB 2.0 controller, otherwiase EHCI funciton will down.
Signed-off-by: Ran Wang
---
Change in v4:
- None
Change in v3:
- None
Change in v2:
- Add EL checking code to make sure related programming only happen
in EL3
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 +
arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8028d52..4ef6eb6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
#include
#endif
@@ -614,6 +615,14 @@ void fsl_lsch2_early_init_f(void)
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
}
+ /*
+* Program Central Security Unit (CSU) to grant access
+* permission for USB 2.0 controller
+*/
+#if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
+ if (current_el() == 3)
+ set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
+#endif
/* Erratum */
erratum_a008850_early(); /* part 1 of 2 */
erratum_a009929();
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index 2bbfab7..a265106 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -39,6 +39,7 @@ enum csu_cslx_ind {
CSU_CSLX_ESDHC,
CSU_CSLX_IFC = 45,
CSU_CSLX_I2C1,
+ CSU_CSLX_USB_2,
CSU_CSLX_I2C3 = 48,
CSU_CSLX_I2C2,
CSU_CSLX_DUART2 = 50,
--
2.7.4
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Re: [U-Boot] [PATCH v2] spi: Add SPI driver for MT76xx SoCs
On Fri, Aug 10, 2018 at 12:26 PM, Stefan Roese wrote: > This patch adds the SPI driver for the MediaTek MT7688 SoC (and > derivates). Its been tested on the LinkIt Smart 7688 and the Gardena > Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart > Gateway additionally with an SPI NAND on CS1. > > Note that the SPI controller only supports a max transfer size of 32 > bytes. This driver implementes a workaround to enable bigger xfer > sizes to speed up the transfer especially for the SPI NAND support. > > Signed-off-by: Stefan Roese > Cc: Jagan Teki > --- > v2: > - Add some macros instead of hardcoded numbers > - Move compatible DT struct down in the file Reviewed-by: Jagan Teki ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 00/18] spi: mpc8xxx: DM conversion
Hello Mario, Le 26/04/2018 à 10:36, Mario Six a écrit : Hi Joakim, On Thu, Apr 26, 2018 at 10:23 AM, Joakim Tjernlund wrote: On Thu, 2018-04-26 at 11:35 +0530, Jagan Teki wrote: CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe. On Thu, Apr 26, 2018 at 11:24 AM, Mario Six wrote: Hi Jagan, On Thu, Apr 26, 2018 at 7:30 AM, Jagan Teki wrote: On Thu, Apr 19, 2018 at 6:06 PM, Mario Six wrote: This is v2 of a patch series that adds support for DM to the MPC8XXX SPI driver, cleans up the driver code, fixes a few minor problems. Some TODOs are left over for later, such as proper SPI speed setting, and support for SPI mode setting. These would be enhancements to the original functionality, and can come later. The legacy functionality is removed in this version, so old boards in the tree might end up with broken SPI functionality. Mario Six (18): spi: mpc8xxx: Use short type names spi: mpc8xxx: Fix comments spi: mpc8xxx: Rename camel-case variables spi: mpc8xxx: Fix space after cast spi: mpc8xxx: Fix function names in strings spi: mpc8xxx: Replace defines with enums spi: mpc8xxx: Use IO accessors spi: mpc8xxx: Simplify if spi: mpc8xxx: Get rid of is_read spi: mpc8xxx: Simplify logic a bit spi: mpc8xxx: Reduce scope of loop variables spi: mpc8xxx: Make code more readable spi: mpc8xxx: Rename variable spi: mpc8xxx: Document LEN setting better spi: mpc8xxx: Re-order transfer setup spi: mpc8xxx: Fix if check spi: mpc8xxx: Use get_timer spi: mpc8xxx: Convert to DM Boards with - configs/MPC8349EMDS_defconfig - configs/ids8313_defconfig are using this driver, so Kim, Heiko please convert enable DM_SPI for the same. Use below tree for respective changes and update on top of this. http://git.denx.de/?p=u-boot-spi.git;a=shortlog;h=refs/heads/next I have a few series in the making that will enable DM on the MPC83xx platform (I'm doing a respin on the first right now). If there is still interests in the boards, I could push it to the MPC83xx repository (but mind that the work required per board is quite extensive). Also, MPC8349EMDS is de facto abandoned, and I don't have access to the hardware, so I can't really maintain it. It's up to you, look like this board maintained by Kim is not available with freescale e-mail (or may be changed) if none can't maintain, it better to drop the board. we use custom 832x boards so please don't remove 83xx from u-boot. I'm not planning to do that; on the contrary: I'm trying to update the platform to fully support DM (I hope to get a fully converted board in after the next release). The problem is that we only use MPC8308 SoCs, so I can only vouche for the correctness of that specific SoC. Everything else is a bit up in the air, since I'm changing code blindly pretty much. I have a MPC8321 board so I may test it on it if it helps. In the meantime, I was thinking about using your converted driver and see if I can adapt it to support MPC8xx as well, instead of converting the mpc8xx_spi driver to DM, however I've not been able to find your patches in the master tree allthough they are flagged as accepted in patchwork. Are they on another branch somewhere ? Thanks Christophe Best regards, Mario ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/5 v2] mips: Add arch/mips/include/asm/atomic.h
This is needed for the UBIFS support. The file is a copy of
arch/xtensa/include/asm/atomic.h
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
v2:
- No change
arch/mips/include/asm/atomic.h | 54 ++
1 file changed, 54 insertions(+)
create mode 100644 arch/mips/include/asm/atomic.h
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
new file mode 100644
index 00..7551bf6e6c
--- /dev/null
+++ b/arch/mips/include/asm/atomic.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef _MIPS_ATOMIC_H
+#define _MIPS_ATOMIC_H
+
+#include
+
+typedef struct { volatile int counter; } atomic_t;
+
+#define ATOMIC_INIT(i) { (i) }
+
+#define atomic_read(v) ((v)->counter)
+#define atomic_set(v, i) ((v)->counter = (i))
+
+static inline void atomic_add(int i, atomic_t *v)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ v->counter += i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ v->counter -= i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_inc(atomic_t *v)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ ++v->counter;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_dec(atomic_t *v)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ --v->counter;
+ local_irq_restore(flags);
+}
+
+#endif
--
2.18.0
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[U-Boot] [PATCH 5/5 v2] mips: mt76xx: Add sysreset support
This patch adds the necessary sysreset DT node and enables the required
drivers via Kconfig.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
v2:
- New patch
arch/mips/Kconfig | 1 +
arch/mips/dts/mt7628a.dtsi | 7 +++
2 files changed, 8 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b7c5fa3114..4234b924c4 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -100,6 +100,7 @@ config ARCH_MT7620
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_LITTLE_ENDIAN
+ select SYSRESET
config MACH_PIC32
bool "Support Microchip PIC32"
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi
index d00f528e1f..d525f019fe 100644
--- a/arch/mips/dts/mt7628a.dtsi
+++ b/arch/mips/dts/mt7628a.dtsi
@@ -41,6 +41,13 @@
reg = <0x0 0x100>;
};
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&sysc>;
+ offset = <0x34>;
+ mask = <0x1>;
+ };
+
intc: interrupt-controller@200 {
compatible = "ralink,rt2880-intc";
reg = <0x200 0x100>;
--
2.18.0
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[U-Boot] [PATCH 3/5 v2] mips: Add LinkIt Smart 7688 support
The LinkIt Smart 7688 modules have a MT7688 SoC with 128 MiB of RAM
and 32 MiB of flash (SPI NOR).
The mt7628a.dtsi file is imported from Linux v4.17.
This patch also includes 2 targets. One is the target that can be
programmed into the SPI NOR flash and a 2nd target "xxx-ram" is
added to support loading and booting via an already running U-Boot
version. This allows easy development and testing without the
need to flash the image each time.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
v2:
- Kconfig entries added with this patch now
arch/mips/dts/linkit-smart-7688.dts | 46
arch/mips/dts/mt7628a.dtsi| 135 ++
arch/mips/mach-mt7620/Kconfig | 13 +++
board/seeed/linkit-smart-7688/Kconfig | 12 ++
board/seeed/linkit-smart-7688/MAINTAINERS | 8 ++
board/seeed/linkit-smart-7688/Makefile| 3 +
board/seeed/linkit-smart-7688/board.c | 22
configs/linkit-smart-7688-ram_defconfig | 58 ++
configs/linkit-smart-7688_defconfig | 62 ++
include/configs/linkit-smart-7688.h | 52 +
10 files changed, 411 insertions(+)
create mode 100644 arch/mips/dts/linkit-smart-7688.dts
create mode 100644 arch/mips/dts/mt7628a.dtsi
create mode 100644 board/seeed/linkit-smart-7688/Kconfig
create mode 100644 board/seeed/linkit-smart-7688/MAINTAINERS
create mode 100644 board/seeed/linkit-smart-7688/Makefile
create mode 100644 board/seeed/linkit-smart-7688/board.c
create mode 100644 configs/linkit-smart-7688-ram_defconfig
create mode 100644 configs/linkit-smart-7688_defconfig
create mode 100644 include/configs/linkit-smart-7688.h
diff --git a/arch/mips/dts/linkit-smart-7688.dts
b/arch/mips/dts/linkit-smart-7688.dts
new file mode 100644
index 00..df4bf907c6
--- /dev/null
+++ b/arch/mips/dts/linkit-smart-7688.dts
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Stefan Roese
+ */
+
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+
+/ {
+ compatible = "seeed,linkit-smart-7688", "ralink,mt7628a-soc";
+ model = "LinkIt-Smart-7688";
+
+ aliases {
+ serial0 = &uart2;
+ spi0 = &spi0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0800>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600";
+ stdout-path = &uart2;
+ };
+};
+
+&uart2 {
+ status = "okay";
+ clock-frequency = <4000>;
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <2>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash", "jedec,spi-nor";
+ spi-max-frequency = <2500>;
+ reg = <0>;
+ };
+};
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi
new file mode 100644
index 00..d00f528e1f
--- /dev/null
+++ b/arch/mips/dts/mt7628a.dtsi
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,mt7628a-soc";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mti,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ resetc: reset-controller {
+ compatible = "ralink,rt2880-reset";
+ #reset-cells = <1>;
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@1000 {
+ compatible = "palmbus", "simple-bus";
+ reg = <0x1000 0x20>;
+ ranges = <0x0 0x1000 0x1F>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc: system-controller@0 {
+ compatible = "ralink,mt7620a-sysc", "syscon";
+ reg = <0x0 0x100>;
+ };
+
+ intc: interrupt-controller@200 {
+ compatible = "ralink,rt2880-intc";
+ reg = <0x200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ resets = <&resetc 9>;
+ reset-names = "intc";
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+
+ ralink,intc-registers = <0x9c 0xa0
+0x6c 0xa4
+0x80 0x78>;
+ };
+
+ memory-controller@300 {
+ compatible = "ralink,mt7620a-memc";
+
[U-Boot] [PATCH 1/5 v2] mips: Add basic MediaTek MT7620/88 support
This patch adds basic support for the MediaTek MT7620/88 SoCs. Parts of the code is copied from the MediaTek GitHub repository: https://github.com/MediaTek-Labs/linkit-smart-uboot.git Support for the LinkIt Smart 7688 module and the Gardena Smart Gateway both based on the MT7688 will be added in further patches. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- v2: - Sort Kconfig symbols alphabetically - Use MIPS_TUNE_24KC - Use imply for SPI support - Dont' add LinkIt module support yet (is added with the board support) - Move SKIP_LOWLEVEL_INIT from Kconfig to config header - Use DT to get the base address of the system controller (for display_cpuinfo) - Remove _machine_restart - a separate driver is provided in a new patch - Remove cachop_op() and cal_invalidate_dcache_range and use the generic invalidate_dcache_range function instead Daniel I tried to change to CPU_HAS PREFETCH, but this did not work smoothly. It seems this option is very old and outdated. Perhaps I can revisit this again, once this patchset has settled a bit. arch/mips/Kconfig | 15 ++ arch/mips/Makefile| 1 + arch/mips/mach-mt7620/Kconfig | 113 + arch/mips/mach-mt7620/Makefile| 8 + arch/mips/mach-mt7620/cpu.c | 72 ++ arch/mips/mach-mt7620/ddr_calibrate.c | 307 +++ arch/mips/mach-mt7620/lowlevel_init.S | 337 ++ arch/mips/mach-mt7620/mt76xx.h| 38 +++ 8 files changed, 891 insertions(+) create mode 100644 arch/mips/mach-mt7620/Kconfig create mode 100644 arch/mips/mach-mt7620/Makefile create mode 100644 arch/mips/mach-mt7620/cpu.c create mode 100644 arch/mips/mach-mt7620/ddr_calibrate.c create mode 100644 arch/mips/mach-mt7620/lowlevel_init.S create mode 100644 arch/mips/mach-mt7620/mt76xx.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 31b622ff51..b7c5fa3114 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -87,6 +87,20 @@ config ARCH_BMIPS select SYSRESET imply CMD_DM +config ARCH_MT7620 + bool "Support MT7620/7688 SoCs" + select DISPLAY_CPUINFO + select DM + select DM_SERIAL + imply DM_SPI + imply DM_SPI_FLASH + select MIPS_TUNE_24KC + select OF_CONTROL + select ROM_EXCEPTION_VECTORS + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_LITTLE_ENDIAN + config MACH_PIC32 bool "Support Microchip PIC32" select DM @@ -141,6 +155,7 @@ source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-pic32/Kconfig" +source "arch/mips/mach-mt7620/Kconfig" if MIPS diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 5deec9a202..cc8ea5d7d4 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -15,6 +15,7 @@ machine-$(CONFIG_SOC_AU1X00) += au1x00 machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_ARCH_BMIPS) += bmips machine-$(CONFIG_MACH_PIC32) += pic32 +machine-$(CONFIG_ARCH_MT7620) += mt7620 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig new file mode 100644 index 00..396fbd0141 --- /dev/null +++ b/arch/mips/mach-mt7620/Kconfig @@ -0,0 +1,113 @@ +menu "MediaTek MIPS platforms" + depends on ARCH_MT7620 + +config SYS_MALLOC_F_LEN + default 0x1000 + +config SYS_SOC + default "mt7620" if SOC_MT7620 + +choice + prompt "MediaTek MIPS SoC select" + +config SOC_MT7620 + bool "MT7620/8" + select MIPS_L1_CACHE_SHIFT_5 + help + This supports MediaTek MIPS MT7620 family. + +endchoice + +choice + prompt "Board select" + +endchoice + +choice + prompt "Boot mode" + +config BOOT_RAM + bool "RAM boot" + depends on SUPPORTS_BOOT_RAM + help + This builds an image that is linked to a RAM address. It can be used + for booting from CFE via TFTP using an ELF image, but it can also be + booted from RAM by other bootloaders using a BIN image. + +config BOOT_ROM + bool "ROM boot" + depends on SUPPORTS_BOOT_RAM + help + This builds an image that is linked to a ROM address. It can be + used as main bootloader image which is programmed onto the onboard + flash storage (SPI NOR). + +endchoice + +choice + prompt "DDR2 size" + +config ONBOARD_DDR2_SIZE_256MBIT + bool "256MBit (32MByte) total size" + depends on BOOT_ROM + help + Use 256MBit (32MByte) of DDR total size + +config ONBOARD_DDR2_SIZE_512MBIT + bool "512MBit (64MByte) total size" + depends on BOOT_ROM + help + Use 512MBit (64MByte) of DDR total size + +config ONBOARD_DDR2_SIZE_1024MBIT + bool "1024MBit (128MByte) total size" + depends on BOOT_ROM + help + Use 1024
[U-Boot] [PATCH 4/5 v2] mips: Add Gardena Smart-Gateway board support
The Gardena Smart-Gateway boards have a MT7688 SoC with 128 MiB of RAM
and 8 MiB of flash (SPI NOR) and additional 128MiB SPI NAND storage.
This patch also includes 2 targets. One is the target that can be
programmed into the SPI NOR flash and a 2nd target "xxx-ram" is
added to support loading and booting via an already running U-Boot
version. This allows easy development and testing without the
need to flash the image each time.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
v2:
- No change
.../mips/dts/gardena-smart-gateway-mt7688.dts | 54 +++
arch/mips/mach-mt7620/Kconfig | 9 +++
board/gardena/smart-gateway-mt7688/Kconfig| 12
.../gardena/smart-gateway-mt7688/MAINTAINERS | 8 +++
board/gardena/smart-gateway-mt7688/Makefile | 3 +
board/gardena/smart-gateway-mt7688/board.c| 18 +
...gardena-smart-gateway-mt7688-ram_defconfig | 68 +++
.../gardena-smart-gateway-mt7688_defconfig| 67 ++
.../configs/gardena-smart-gateway-mt7688.h| 56 +++
9 files changed, 295 insertions(+)
create mode 100644 arch/mips/dts/gardena-smart-gateway-mt7688.dts
create mode 100644 board/gardena/smart-gateway-mt7688/Kconfig
create mode 100644 board/gardena/smart-gateway-mt7688/MAINTAINERS
create mode 100644 board/gardena/smart-gateway-mt7688/Makefile
create mode 100644 board/gardena/smart-gateway-mt7688/board.c
create mode 100644 configs/gardena-smart-gateway-mt7688-ram_defconfig
create mode 100644 configs/gardena-smart-gateway-mt7688_defconfig
create mode 100644 include/configs/gardena-smart-gateway-mt7688.h
diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts
b/arch/mips/dts/gardena-smart-gateway-mt7688.dts
new file mode 100644
index 00..6b2600a446
--- /dev/null
+++ b/arch/mips/dts/gardena-smart-gateway-mt7688.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Stefan Roese
+ */
+
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+
+/ {
+ compatible = "gardena,smart-gateway-mt7688", "ralink,mt7628a-soc";
+ model = "Gardena smart-Gateway-MT7688";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0800>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600";
+ stdout-path = &uart0;
+ };
+};
+
+&uart0 {
+ status = "okay";
+ clock-frequency = <4000>;
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <2>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash", "jedec,spi-nor";
+ spi-max-frequency = <2500>;
+ reg = <0>;
+ };
+
+ spi-nand@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <2500>;
+ reg = <1>;
+ };
+};
diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig
index ef1211d172..13a7bd2cc0 100644
--- a/arch/mips/mach-mt7620/Kconfig
+++ b/arch/mips/mach-mt7620/Kconfig
@@ -21,6 +21,14 @@ endchoice
choice
prompt "Board select"
+config BOARD_GARDENA_SMART_GATEWAY_MT7688
+ bool "Gardena Smart Gateway"
+ depends on SOC_MT7620
+ select SUPPORTS_BOOT_RAM
+ help
+ Gardena Smart Gateway boards have a MT7688 SoC with 128 MiB of RAM
+ and 8 MiB of flash (SPI NOR) and additional SPI NAND storage.
+
config BOARD_LINKIT_SMART_7688
bool "LinkIt Smart 7688"
depends on SOC_MT7620
@@ -121,6 +129,7 @@ endchoice
config SUPPORTS_BOOT_RAM
bool
+source "board/gardena/smart-gateway-mt7688/Kconfig"
source "board/seeed/linkit-smart-7688/Kconfig"
endmenu
diff --git a/board/gardena/smart-gateway-mt7688/Kconfig
b/board/gardena/smart-gateway-mt7688/Kconfig
new file mode 100644
index 00..3653f8aadb
--- /dev/null
+++ b/board/gardena/smart-gateway-mt7688/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_GARDENA_SMART_GATEWAY_MT7688
+
+config SYS_BOARD
+ default "smart-gateway-mt7688"
+
+config SYS_VENDOR
+ default "gardena"
+
+config SYS_CONFIG_NAME
+ default "gardena-smart-gateway-mt7688"
+
+endif
diff --git a/board/gardena/smart-gateway-mt7688/MAINTAINERS
b/board/gardena/smart-gateway-mt7688/MAINTAINERS
new file mode 100644
index 00..bbb491c1ce
--- /dev/null
+++ b/board/gardena/smart-gateway-mt7688/MAINTAINERS
@@ -0,0 +1,8 @@
+GARDENA_SMART_GATEWAY_MT7688 BOARD
+M: Stefan Roese
+S: Maintained
+F: board/gardena/smart-gateway-mt7688
+F: include/configs/gardena-smart-gateway-mt7688.h
+F: configs/gardena-smart-gateway-mt7688_defconfig
+F: configs/gardena-smart-gateway-mt7688-ram_defconfig
+F: arch/mips/dts/gardena-smart-gateway-mt7688.dts
diff --git a/board/gardena/smart-gateway-mt7688/
[U-Boot] [PATCH v5 1/8] dm: mmc: use block layer in mmc driver
At present the MMC subsystem maintains its own list
of MMC devices. This cannot work with driver model
when CONFIG_BLK is enabled, use blk_dread to
replace previous mmc read interface,
use mmc_get_blk_desc to get the mmc device property
Signed-off-by: Yinbo Zhu
---
Change in v5:
use block layer in mmc driver
arch/arm/cpu/armv8/fsl-layerscape/ppa.c |5 ++---
drivers/mmc/mmc_legacy.c| 10 +-
drivers/net/fm/fm.c |2 +-
drivers/qe/qe.c |2 +-
4 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
index a31c4d9..95875d3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -99,7 +99,7 @@ int ppa_init(void)
cnt = DIV_ROUND_UP(fdt_header_len, 512);
debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n",
__func__, dev, blk, cnt);
- ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, fitp);
+ ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, fitp);
if (ret != cnt) {
free(fitp);
printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
@@ -149,8 +149,7 @@ int ppa_init(void)
cnt = DIV_ROUND_UP(fw_length, 512);
debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n",
__func__, dev, blk, cnt);
- ret = mmc->block_dev.block_read(&mmc->block_dev,
- blk, cnt, ppa_fit_addr);
+ ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ppa_fit_addr);
if (ret != cnt) {
free(ppa_fit_addr);
printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c
index 66a7cda..29d94e9 100644
--- a/drivers/mmc/mmc_legacy.c
+++ b/drivers/mmc/mmc_legacy.c
@@ -42,7 +42,7 @@ struct mmc *find_mmc_device(int dev_num)
list_for_each(entry, &mmc_devices) {
m = list_entry(entry, struct mmc, link);
- if (m->block_dev.devnum == dev_num)
+ if (mmc_get_blk_desc(m)->devnum == dev_num)
return m;
}
@@ -60,7 +60,7 @@ int mmc_get_next_devnum(void)
struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
{
- return &mmc->block_dev;
+ return mmc_get_blk_desc(mmc);
}
int get_mmc_num(void)
@@ -113,7 +113,7 @@ void print_mmc_devices(char separator)
else
mmc_type = NULL;
- printf("%s: %d", m->cfg->name, m->block_dev.devnum);
+ printf("%s: %d", m->cfg->name, mmc_get_blk_desc(m)->devnum);
if (mmc_type)
printf(" (%s)", mmc_type);
@@ -218,7 +218,7 @@ static int mmc_select_hwpartp(struct blk_desc *desc, int
hwpart)
if (!mmc)
return -ENODEV;
- if (mmc->block_dev.hwpart == hwpart)
+ if (mmc_get_blk_desc(mmc)->hwpart == hwpart)
return 0;
if (mmc->part_config == MMCPART_NOAVAILABLE)
@@ -242,7 +242,7 @@ static int mmc_get_dev(int dev, struct blk_desc **descp)
if (ret)
return ret;
- *descp = &mmc->block_dev;
+ *descp = mmc_get_blk_desc(mmc);
return 0;
}
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 3327073..c5cf188 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -402,7 +402,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
- (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+ (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
addr);
}
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 7654df8..7010bbc 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -218,7 +218,7 @@ void u_qe_init(void)
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
- (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+ (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
addr);
}
#endif
--
1.7.1
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[U-Boot] [PATCH v5 2/8] armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support
This patch adds esdhc clock support for ls1088a and ls2088a.
Signed-off-by: Yinbo Zhu
---
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index 653c6dd..bc268e2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -192,6 +192,16 @@ int get_dspi_freq(ulong dummy)
return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
}
+#ifdef CONFIG_FSL_ESDHC
+int get_sdhc_freq(ulong dummy)
+{
+ if (!gd->arch.sdhc_clk)
+ get_clocks();
+
+ return gd->arch.sdhc_clk;
+}
+#endif
+
int get_serial_clock(void)
{
return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
@@ -202,6 +212,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
switch (clk) {
case MXC_I2C_CLK:
return get_i2c_freq(0);
+#if defined(CONFIG_FSL_ESDHC)
+ case MXC_ESDHC_CLK:
+ return get_sdhc_freq(0);
+#endif
case MXC_DSPI_CLK:
return get_dspi_freq(0);
default:
--
1.7.1
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[U-Boot] [PATCH v5 3/8] Enable CONFIG_BLK and CONFIG_DM_MMC to Kconfig
This enables the folowing to Kconfig: CONFIG_BLK CONFIG_DM_MMC Signed-off-by: Yinbo Zhu --- configs/ls1021atwr_nor_SECURE_BOOT_defconfig |2 ++ configs/ls1021atwr_nor_defconfig |2 ++ configs/ls1021atwr_nor_lpuart_defconfig|2 ++ configs/ls1021atwr_qspi_defconfig |2 ++ .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig|2 ++ configs/ls1021atwr_sdcard_ifc_defconfig|2 ++ configs/ls1021atwr_sdcard_qspi_defconfig |2 ++ configs/ls1043aqds_defconfig |2 ++ configs/ls1043aqds_lpuart_defconfig|2 ++ configs/ls1043aqds_nand_defconfig |2 ++ configs/ls1043aqds_nor_ddr3_defconfig |2 ++ configs/ls1043aqds_qspi_defconfig |2 ++ configs/ls1043aqds_sdcard_ifc_defconfig|2 ++ configs/ls1043aqds_sdcard_qspi_defconfig |2 ++ configs/ls1043ardb_SECURE_BOOT_defconfig |2 ++ configs/ls1043ardb_defconfig |2 ++ configs/ls1043ardb_nand_SECURE_BOOT_defconfig |2 ++ configs/ls1043ardb_nand_defconfig |2 ++ configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig|2 ++ configs/ls1043ardb_sdcard_defconfig|2 ++ configs/ls1046aqds_SECURE_BOOT_defconfig |2 ++ configs/ls1046aqds_defconfig |2 ++ configs/ls1046aqds_lpuart_defconfig|2 ++ configs/ls1046aqds_nand_defconfig |2 ++ configs/ls1046aqds_qspi_defconfig |2 ++ configs/ls1046aqds_sdcard_ifc_defconfig|2 ++ configs/ls1046aqds_sdcard_qspi_defconfig |2 ++ configs/ls1046ardb_emmc_defconfig |2 ++ configs/ls1046ardb_qspi_SECURE_BOOT_defconfig |2 ++ configs/ls1046ardb_qspi_defconfig |2 ++ configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig|2 ++ configs/ls1046ardb_sdcard_defconfig|2 ++ configs/ls1088aqds_defconfig |2 ++ configs/ls1088aqds_qspi_SECURE_BOOT_defconfig |2 ++ configs/ls1088aqds_qspi_defconfig |2 ++ configs/ls1088aqds_sdcard_ifc_defconfig|2 ++ configs/ls1088aqds_sdcard_qspi_defconfig |2 ++ configs/ls1088ardb_qspi_SECURE_BOOT_defconfig |2 ++ configs/ls1088ardb_qspi_defconfig |2 ++ .../ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig |2 ++ configs/ls1088ardb_sdcard_qspi_defconfig |2 ++ configs/ls2080a_emu_defconfig |2 ++ configs/ls2080a_simu_defconfig |2 ++ configs/ls2080aqds_SECURE_BOOT_defconfig |2 ++ configs/ls2080aqds_defconfig |2 ++ configs/ls2080aqds_nand_defconfig |2 ++ configs/ls2080aqds_qspi_defconfig |2 ++ configs/ls2080aqds_sdcard_defconfig|2 ++ configs/ls2080ardb_SECURE_BOOT_defconfig |2 ++ configs/ls2080ardb_defconfig |2 ++ configs/ls2080ardb_nand_defconfig |2 ++ configs/ls2088ardb_qspi_SECURE_BOOT_defconfig |2 ++ configs/ls2088ardb_qspi_defconfig |2 ++ 53 files changed, 106 insertions(+), 0 deletions(-) diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 17a202d..4d85983 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -48,3 +48,5 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index a18426e..f4f7998 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -48,3 +48,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 83ffa19..037f56c 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -49,3 +49,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 46d8dbb..084bd27 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -55,3 +55,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index b
[U-Boot] [PATCH v5 7/8] armv8: ls1046a: add eSDHC node
This patch is to add eSDHC node for ls1046a.
Signed-off-by: Yinbo Zhu
---
arch/arm/dts/fsl-ls1046a.dtsi |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 4acbaf7..7687d12 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -70,6 +70,14 @@
status = "disabled";
};
+ esdhc: esdhc@156 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x156 0x0 0x1>;
+ interrupts = <0 62 0x4>;
+ big-endian;
+ bus-width = <4>;
+ };
+
ifc: ifc@153 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x153 0x0 0x1>;
--
1.7.1
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[U-Boot] [PATCH v5 5/8] armv8: ls1088a: add eSDHC node
This patch is to add eSDHC node for ls1088a.
Signed-off-by: Yinbo Zhu
---
arch/arm/dts/fsl-ls1088a.dtsi |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 077caf3..72d755a 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -74,6 +74,15 @@
reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <4>;
};
+
+ esdhc: esdhc@214 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x214 0x0 0x1>;
+ interrupts = <0 28 0x4>; /* Level high type */
+ little-endian;
+ bus-width = <4>;
+ };
+
ifc: ifc@153 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x224 0x0 0x2>;
--
1.7.1
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[U-Boot] [PATCH v5 6/8] armv8: ls1043a: add eSDHC node
This patch is to add eSDHC node for ls1043a.
Signed-off-by: Yinbo Zhu
---
arch/arm/dts/fsl-ls1043a.dtsi |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index ff40122..a804f51 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -70,6 +70,14 @@
status = "disabled";
};
+ esdhc: esdhc@156 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x156 0x0 0x1>;
+ interrupts = <0 62 0x4>;
+ big-endian;
+ bus-width = <4>;
+ };
+
ifc: ifc@153 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x153 0x0 0x1>;
--
1.7.1
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[U-Boot] [PATCH v5 4/8] armv8: ls2088a: add eSDHC node
This patch is to add eSDHC node for ls2088a.
Signed-off-by: Yinbo Zhu
---
arch/arm/dts/fsl-ls2080a.dtsi |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index b0f8517..2d537ae 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -75,6 +75,14 @@
num-cs = <4>;
};
+ esdhc: esdhc@0 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x214 0x0 0x1>;
+ interrupts = <0 28 0x4>; /* Level high type */
+ little-endian;
+ bus-width = <4>;
+ };
+
usb0: usb3@310 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x310 0x0 0x1>;
--
1.7.1
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[U-Boot] [PATCH v5 8/8] armv7: ls1021a: enable esdhc
This patch is to enable eSDHC for ls1021a.
Signed-off-by: Yinbo Zhu
---
arch/arm/dts/ls1021a.dtsi |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 5b3fc6a..59c97d5 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -96,7 +96,6 @@
sdhci,auto-cmd12;
big-endian;
bus-width = <4>;
- status = "disabled";
};
scfg: scfg@157 {
--
1.7.1
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Re: [U-Boot] [PATCH v2 00/18] spi: mpc8xxx: DM conversion
Hi Christophe, On Fri, Aug 10, 2018 at 9:35 AM Christophe LEROY wrote: > > Hello Mario, > > Le 26/04/2018 à 10:36, Mario Six a écrit : > > Hi Joakim, > > > > On Thu, Apr 26, 2018 at 10:23 AM, Joakim Tjernlund > > wrote: > >> On Thu, 2018-04-26 at 11:35 +0530, Jagan Teki wrote: > >>> CAUTION: This email originated from outside of the organization. Do not > >>> click links or open attachments unless you recognize the sender and know > >>> the content is safe. > >>> > >>> > >>> On Thu, Apr 26, 2018 at 11:24 AM, Mario Six wrote: > Hi Jagan, > > On Thu, Apr 26, 2018 at 7:30 AM, Jagan Teki > wrote: > > On Thu, Apr 19, 2018 at 6:06 PM, Mario Six wrote: > >> This is v2 of a patch series that adds support for DM to the MPC8XXX > >> SPI > >> driver, cleans up the driver code, fixes a few minor problems. > >> > >> Some TODOs are left over for later, such as proper SPI speed setting, > >> and support for SPI mode setting. These would be enhancements to the > >> original functionality, and can come later. > >> > >> The legacy functionality is removed in this version, so old boards in > >> the tree might end up with broken SPI functionality. > >> > >> Mario Six (18): > >>spi: mpc8xxx: Use short type names > >>spi: mpc8xxx: Fix comments > >>spi: mpc8xxx: Rename camel-case variables > >>spi: mpc8xxx: Fix space after cast > >>spi: mpc8xxx: Fix function names in strings > >>spi: mpc8xxx: Replace defines with enums > >>spi: mpc8xxx: Use IO accessors > >>spi: mpc8xxx: Simplify if > >>spi: mpc8xxx: Get rid of is_read > >>spi: mpc8xxx: Simplify logic a bit > >>spi: mpc8xxx: Reduce scope of loop variables > >>spi: mpc8xxx: Make code more readable > >>spi: mpc8xxx: Rename variable > >>spi: mpc8xxx: Document LEN setting better > >>spi: mpc8xxx: Re-order transfer setup > >>spi: mpc8xxx: Fix if check > >>spi: mpc8xxx: Use get_timer > >>spi: mpc8xxx: Convert to DM > > > > Boards with > > - configs/MPC8349EMDS_defconfig > > - configs/ids8313_defconfig > > > > are using this driver, so Kim, Heiko please convert enable DM_SPI for > > the same. > > > > Use below tree for respective changes and update on top of this. > > http://git.denx.de/?p=u-boot-spi.git;a=shortlog;h=refs/heads/next > > > > I have a few series in the making that will enable DM on the MPC83xx > platform > (I'm doing a respin on the first right now). If there is still interests > in the > boards, I could push it to the MPC83xx repository (but mind that the work > required per board is quite extensive). > > Also, MPC8349EMDS is de facto abandoned, and I don't have access to the > hardware, so I can't really maintain it. > >>> > >>> It's up to you, look like this board maintained by Kim is not > >>> available with freescale e-mail (or may be changed) if none can't > >>> maintain, it better to drop the board. > >> > >> we use custom 832x boards so please don't remove 83xx from u-boot. > >> > > > > I'm not planning to do that; on the contrary: I'm trying to update the > > platform > > to fully support DM (I hope to get a fully converted board in after the next > > release). > > > > The problem is that we only use MPC8308 SoCs, so I can only vouche for the > > correctness of that specific SoC. Everything else is a bit up in the air, > > since > > I'm changing code blindly pretty much. > > I have a MPC8321 board so I may test it on it if it helps. > That would be very much appreciated! Thanks. > In the meantime, I was thinking about using your converted driver and > see if I can adapt it to support MPC8xx as well, instead of converting > the mpc8xx_spi driver to DM, however I've not been able to find your > patches in the master tree allthough they are flagged as accepted in > patchwork. > > Are they on another branch somewhere ? > Hmm, indeed. I thought they would be in the SPI custodian repository, but apparently they are not? @Jagan: Were those patches forgotten somehow? > Thanks > Christophe > Best regards, Mario ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 00/18] spi: mpc8xxx: DM conversion
On Fri, Aug 10, 2018 at 1:27 PM, Mario Six wrote: > Hi Christophe, > > On Fri, Aug 10, 2018 at 9:35 AM Christophe LEROY > wrote: >> >> Hello Mario, >> >> Le 26/04/2018 à 10:36, Mario Six a écrit : >> > Hi Joakim, >> > >> > On Thu, Apr 26, 2018 at 10:23 AM, Joakim Tjernlund >> > wrote: >> >> On Thu, 2018-04-26 at 11:35 +0530, Jagan Teki wrote: >> >>> CAUTION: This email originated from outside of the organization. Do not >> >>> click links or open attachments unless you recognize the sender and know >> >>> the content is safe. >> >>> >> >>> >> >>> On Thu, Apr 26, 2018 at 11:24 AM, Mario Six wrote: >> Hi Jagan, >> >> On Thu, Apr 26, 2018 at 7:30 AM, Jagan Teki >> wrote: >> > On Thu, Apr 19, 2018 at 6:06 PM, Mario Six wrote: >> >> This is v2 of a patch series that adds support for DM to the MPC8XXX >> >> SPI >> >> driver, cleans up the driver code, fixes a few minor problems. >> >> >> >> Some TODOs are left over for later, such as proper SPI speed setting, >> >> and support for SPI mode setting. These would be enhancements to the >> >> original functionality, and can come later. >> >> >> >> The legacy functionality is removed in this version, so old boards in >> >> the tree might end up with broken SPI functionality. >> >> >> >> Mario Six (18): >> >>spi: mpc8xxx: Use short type names >> >>spi: mpc8xxx: Fix comments >> >>spi: mpc8xxx: Rename camel-case variables >> >>spi: mpc8xxx: Fix space after cast >> >>spi: mpc8xxx: Fix function names in strings >> >>spi: mpc8xxx: Replace defines with enums >> >>spi: mpc8xxx: Use IO accessors >> >>spi: mpc8xxx: Simplify if >> >>spi: mpc8xxx: Get rid of is_read >> >>spi: mpc8xxx: Simplify logic a bit >> >>spi: mpc8xxx: Reduce scope of loop variables >> >>spi: mpc8xxx: Make code more readable >> >>spi: mpc8xxx: Rename variable >> >>spi: mpc8xxx: Document LEN setting better >> >>spi: mpc8xxx: Re-order transfer setup >> >>spi: mpc8xxx: Fix if check >> >>spi: mpc8xxx: Use get_timer >> >>spi: mpc8xxx: Convert to DM >> > >> > Boards with >> > - configs/MPC8349EMDS_defconfig >> > - configs/ids8313_defconfig >> > >> > are using this driver, so Kim, Heiko please convert enable DM_SPI for >> > the same. >> > >> > Use below tree for respective changes and update on top of this. >> > http://git.denx.de/?p=u-boot-spi.git;a=shortlog;h=refs/heads/next >> > >> >> I have a few series in the making that will enable DM on the MPC83xx >> platform >> (I'm doing a respin on the first right now). If there is still >> interests in the >> boards, I could push it to the MPC83xx repository (but mind that the >> work >> required per board is quite extensive). >> >> Also, MPC8349EMDS is de facto abandoned, and I don't have access to the >> hardware, so I can't really maintain it. >> >>> >> >>> It's up to you, look like this board maintained by Kim is not >> >>> available with freescale e-mail (or may be changed) if none can't >> >>> maintain, it better to drop the board. >> >> >> >> we use custom 832x boards so please don't remove 83xx from u-boot. >> >> >> > >> > I'm not planning to do that; on the contrary: I'm trying to update the >> > platform >> > to fully support DM (I hope to get a fully converted board in after the >> > next >> > release). >> > >> > The problem is that we only use MPC8308 SoCs, so I can only vouche for the >> > correctness of that specific SoC. Everything else is a bit up in the air, >> > since >> > I'm changing code blindly pretty much. >> >> I have a MPC8321 board so I may test it on it if it helps. >> > > That would be very much appreciated! Thanks. > >> In the meantime, I was thinking about using your converted driver and >> see if I can adapt it to support MPC8xx as well, instead of converting >> the mpc8xx_spi driver to DM, however I've not been able to find your >> patches in the master tree allthough they are flagged as accepted in >> patchwork. >> >> Are they on another branch somewhere ? >> > Hmm, indeed. I thought they would be in the SPI custodian repository, but > apparently they are not? > > @Jagan: Were those patches forgotten somehow? http://git.denx.de/?p=u-boot-spi.git;a=shortlog;h=refs/heads/spi-dm-migrate If all the boards which are using this driver enabled DM_SPI, then I will pick the same. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [UBOOT PATCH 0/2] dm: core: Scan "/firmware" node by default
Hi Simon, On 10.8.2018 10:45, Rajan Vaja wrote: > All Linux firmware drivers are put under "/firmware" node > and it has support to populate "/firmware" node by default. > > u-boot and Linux can share same DTB. In this case, driver > probe for devices under "/firmware" will not be invoked > as "/firmware" does not have its own "compatible" property. > > This patch series scans "/firmware" node by default like "/clocks". > To avoid duplication of code, first patch moves, node scan code > into separate function. > > Rajan Vaja (2): > dm: core: Move "/clock" node scan into function > dm: core: Scan "/firmware" node by default > > drivers/core/root.c | 35 ++- > 1 file changed, 22 insertions(+), 13 deletions(-) > This patch is done based on acked binding https://lkml.org/lkml/2018/8/3/683 and https://lkml.org/lkml/2018/8/3/684 where clock driver is child of firmware node. Can you please look at these 2 patches? Thanks, Michal ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/6] x86: coreboot: Add generic coreboot payload support
Currently building U-Boot as the coreboot payload requires user
to change the build configuration for a specific board during
menuconfig process. This uses the board's native device tree
to configure the hardware. For example, the device tree provides
PCI address range for the PCI host controller and U-Boot will
re-program all PCI devices' BAR to be within this range. In order
to make sure we don't mess up the hardware, we should guarantee
the range matches what coreboot programs the chipset.
But we really should make the coreboot payload support easier.
Just like EFI payload, we can create a generic coreboot payload
for all x86 boards as well. The payload is configured to include
as many generic drivers as possible. All stuff that touches low
level initialization are not allowed as such is the coreboot's
responsibility. Platform specific drivers (like gpio, spi, etc)
are not included.
Signed-off-by: Bin Meng
---
arch/x86/cpu/coreboot/Kconfig | 20 +--
arch/x86/cpu/coreboot/coreboot.c | 9 +++--
arch/x86/dts/Makefile | 1 +
arch/x86/dts/coreboot.dts | 41 ++
board/coreboot/coreboot/Kconfig| 28 +++
board/coreboot/coreboot/Makefile | 2 +-
board/coreboot/coreboot/coreboot.c | 17 +
.../coreboot/{coreboot_start.S => start.S} | 0
configs/coreboot_defconfig | 18 --
doc/README.x86 | 15
include/configs/coreboot.h | 32 +
11 files changed, 116 insertions(+), 67 deletions(-)
create mode 100644 arch/x86/dts/coreboot.dts
create mode 100644 board/coreboot/coreboot/coreboot.c
rename board/coreboot/coreboot/{coreboot_start.S => start.S} (100%)
create mode 100644 include/configs/coreboot.h
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index 392c258..93f61f2 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -3,26 +3,26 @@ if TARGET_COREBOOT
config SYS_COREBOOT
bool
default y
+ imply SYS_NS16550
+ imply SCSI
+ imply SCSI_AHCI
imply AHCI_PCI
- imply E1000
- imply ICH_SPI
imply MMC
imply MMC_PCI
imply MMC_SDHCI
imply MMC_SDHCI_SDMA
- imply SCSI
- imply SCSI_AHCI
- imply SPI_FLASH
- imply SYS_NS16550
imply USB
imply USB_EHCI_HCD
imply USB_XHCI_HCD
+ imply USB_STORAGE
+ imply USB_KEYBOARD
imply VIDEO_COREBOOT
+ imply E1000
+ imply ETH_DESIGNWARE
+ imply PCH_GBE
+ imply RTL8169
imply CMD_CBFS
imply FS_CBFS
-
-config CBMEM_CONSOLE
- bool
- default y
+ imply CBMEM_CONSOLE
endif
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 69025c1..a6fd3a8 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -7,6 +7,7 @@
#include
#include
+#include
#include
#include
#include
@@ -75,12 +76,10 @@ int last_stage_init(void)
if (gd->flags & GD_FLG_COLD_BOOT)
timestamp_add_to_bootstage();
- board_final_cleanup();
+ /* start usb so that usb keyboard can be used as input device */
+ usb_init();
- return 0;
-}
+ board_final_cleanup();
-int misc_init_r(void)
-{
return 0;
}
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 37e4fdc..c62540f 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -6,6 +6,7 @@ dtb-y += bayleybay.dtb \
chromebox_panther.dtb \
chromebook_samus.dtb \
conga-qeval20-qa3-e3845.dtb \
+ coreboot.dtb \
cougarcanyon2.dtb \
crownbay.dtb \
dfi-bt700-q7x-151.dtb \
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
new file mode 100644
index 000..a94f781
--- /dev/null
+++ b/arch/x86/dts/coreboot.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng
+ *
+ * Generic coreboot payload device tree for x86 targets
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+ model = "coreboot x86 payload";
+ compatible = "coreboot,x86-payload";
+
+ aliases {
+ serial0 = &serial;
+ };
+
+ config {
+ silent_console = <0>;
+ };
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ pci {
+ compatible = "pci-x86";
+ u-boot,dm-pre-reloc;
+ };
+
+ coreboot-fb {
+ compatible = "coreboot-fb";
+ };
+};
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
index cfa1d50
[U-Boot] [PATCH 2/6] x86: Remove support for Advantech SOM-6896
Now that we have generic coreboot payload support, remove the
dedicated support for Advantech SOM-6896.
Signed-off-by: Bin Meng
---
arch/x86/dts/Makefile | 1 -
arch/x86/dts/broadwell_som-6896.dts | 52 -
include/configs/som-6896.h | 28
3 files changed, 81 deletions(-)
delete mode 100644 arch/x86/dts/broadwell_som-6896.dts
delete mode 100644 include/configs/som-6896.h
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index c62540f..fa717bc 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -18,7 +18,6 @@ dtb-y += bayleybay.dtb \
qemu-x86_i440fx.dtb \
qemu-x86_q35.dtb \
theadorable-x86-dfi-bt700.dtb \
- broadwell_som-6896.dtb \
baytrail_som-db5800-som-6867.dtb
targets += $(dtb-y)
diff --git a/arch/x86/dts/broadwell_som-6896.dts
b/arch/x86/dts/broadwell_som-6896.dts
deleted file mode 100644
index ec691f1..000
--- a/arch/x86/dts/broadwell_som-6896.dts
+++ /dev/null
@@ -1,52 +0,0 @@
-/dts-v1/;
-
-/include/ "skeleton.dtsi"
-/include/ "serial.dtsi"
-/include/ "reset.dtsi"
-/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
-/include/ "coreboot_fb.dtsi"
-
-/ {
- model = "Advantech SOM-6896";
- compatible = "advantech,som-6896", "intel,broadwell";
-
- aliases {
- spi0 = &spi;
- };
-
- config {
- silent_console = <0>;
- };
-
- chosen {
- stdout-path = "/serial";
- };
-
- pci {
- compatible = "pci-x86";
- #address-cells = <3>;
- #size-cells = <2>;
- u-boot,dm-pre-reloc;
- ranges = <0x0200 0x0 0xe000 0xe000 0 0x1000
- 0x4200 0x0 0xd000 0xd000 0 0x1000
- 0x0100 0x0 0x2000 0x2000 0 0xe000>;
-
- pch@1f,0 {
- reg = <0xf800 0 0 0 0>;
- compatible = "intel,pch9";
-
- spi: spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich9-spi";
- spi-flash@0 {
- reg = <0>;
- compatible = "winbond,w25q128",
"spi-flash";
- memory-map = <0xff00 0x0100>;
- };
- };
- };
- };
-
-};
diff --git a/include/configs/som-6896.h b/include/configs/som-6896.h
deleted file mode 100644
index f0e8d61..000
--- a/include/configs/som-6896.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration settings for the SOM-6896
- *
- * Copyright (C) 2015 NovaTech LLC
- * George McCollister
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include
-
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-
-#define CONFIG_MISC_INIT_R
-
-#define VIDEO_IO_OFFSET0
-#define CONFIG_X86EMU_RAW_IO
-
-#define CONFIG_STD_DEVICES_SETTINGS"stdin=serial,usbkbd\0" \
- "stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
-
-#define CONFIG_ENV_SECT_SIZE 0x1000
-#define CONFIG_ENV_OFFSET 0x00ff
-
-#endif /* __CONFIG_H */
--
2.7.4
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[U-Boot] [PATCH 3/6] x86: dts: Remove coreboot_fb.dtsi
There is no need to keep a separate coreboot_fb.dtsi since now we
have a generic coreboot payload dts.
While we are here, this also remove the out-of-date description in
the documentation regarding to coreboot framebuffer driver with
U-Boot loaded as a payload from coreboot. As the testing result with
QEMU 2.5.0 shows, the driver just works like a charm.
Signed-off-by: Bin Meng
---
arch/x86/dts/bayleybay.dts | 1 -
arch/x86/dts/chromebook_link.dts | 1 -
arch/x86/dts/chromebook_samus.dts | 1 -
arch/x86/dts/chromebox_panther.dts | 1 -
arch/x86/dts/coreboot_fb.dtsi | 5 -
arch/x86/dts/minnowmax.dts | 1 -
doc/README.x86 | 7 ---
7 files changed, 17 deletions(-)
delete mode 100644 arch/x86/dts/coreboot_fb.dtsi
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 9683c52..291dc07 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -15,7 +15,6 @@
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
-/include/ "coreboot_fb.dtsi"
/ {
model = "Intel Bayley Bay";
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 115a088..f9f0979 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -8,7 +8,6 @@
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
-/include/ "coreboot_fb.dtsi"
/ {
model = "Google Link";
diff --git a/arch/x86/dts/chromebook_samus.dts
b/arch/x86/dts/chromebook_samus.dts
index 9c48c9a..b58936b 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -8,7 +8,6 @@
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
-/include/ "coreboot_fb.dtsi"
/ {
model = "Google Samus";
diff --git a/arch/x86/dts/chromebox_panther.dts
b/arch/x86/dts/chromebox_panther.dts
index a72a85e..f56e482 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -5,7 +5,6 @@
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
-/include/ "coreboot_fb.dtsi"
/ {
model = "Google Panther";
diff --git a/arch/x86/dts/coreboot_fb.dtsi b/arch/x86/dts/coreboot_fb.dtsi
deleted file mode 100644
index 7d72f18..000
--- a/arch/x86/dts/coreboot_fb.dtsi
+++ /dev/null
@@ -1,5 +0,0 @@
-/ {
- coreboot-fb {
- compatible = "coreboot-fb";
- };
-};
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 02ab4c1..6c65fb9 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -14,7 +14,6 @@
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
-/include/ "coreboot_fb.dtsi"
/ {
model = "Intel Minnowboard Max";
diff --git a/doc/README.x86 b/doc/README.x86
index 6015ca4..8cc4672 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -412,17 +412,10 @@ To enable video you must enable these options in coreboot:
- Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
- Keep VESA framebuffer
-And include coreboot_fb.dtsi in your board's device tree source file, like:
-
- /include/ "coreboot_fb.dtsi"
-
At present it seems that for Minnowboard Max, coreboot does not pass through
the video information correctly (it always says the resolution is 0x0). This
works correctly for link though.
-Note: coreboot framebuffer driver does not work on QEMU. The reason is unknown
-at this point. Patches are welcome if you figure out anything wrong.
-
Test with QEMU for bare mode
QEMU is a fancy emulator that can enable us to test U-Boot without access to
--
2.7.4
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[U-Boot] [PATCH 6/6] x86: efi: payload: Add default TSC frequency in the device tree
It was observed sometimes U-Boot as the EFI payload fails to boot on
QEMU. This is because TSC calibration fails with no valid frequency.
This adds default TSC frequency in the device tree.
Signed-off-by: Bin Meng
---
arch/x86/dts/efi-x86_payload.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/x86/dts/efi-x86_payload.dts b/arch/x86/dts/efi-x86_payload.dts
index 19f2530..5ccb986 100644
--- a/arch/x86/dts/efi-x86_payload.dts
+++ b/arch/x86/dts/efi-x86_payload.dts
@@ -30,6 +30,10 @@
stdout-path = "/serial";
};
+ tsc-timer {
+ clock-frequency = <10>;
+ };
+
pci {
compatible = "pci-x86";
u-boot,dm-pre-reloc;
--
2.7.4
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[U-Boot] [PATCH 4/6] x86: tsc: Try hardware calibration first
At present if TSC frequency is provided in the device tree, it takes
precedence over hardware calibration result. This swaps the order to
try hardware calibration first and uses device tree as last resort.
This can be helpful when a generic dts (eg: coreboot/efi payload) is
supposed to work on as many hardware as possible, including emulators
like QEMU where TSC hardware calibration sometimes fails.
Signed-off-by: Bin Meng
---
drivers/timer/tsc_timer.c | 27 ---
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 747f190..6473de2 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -341,16 +341,12 @@ static int tsc_timer_get_count(struct udevice *dev, u64
*count)
return 0;
}
-static void tsc_timer_ensure_setup(void)
+static void tsc_timer_ensure_setup(bool stop)
{
if (gd->arch.tsc_base)
return;
gd->arch.tsc_base = rdtsc();
- /*
-* If there is no clock frequency specified in the device tree,
-* calibrate it by ourselves.
-*/
if (!gd->arch.clock_rate) {
unsigned long fast_calibrate;
@@ -366,7 +362,10 @@ static void tsc_timer_ensure_setup(void)
if (fast_calibrate)
goto done;
- panic("TSC frequency is ZERO");
+ if (stop)
+ panic("TSC frequency is ZERO");
+ else
+ return;
done:
gd->arch.clock_rate = fast_calibrate * 100;
@@ -377,11 +376,17 @@ static int tsc_timer_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- if (!uc_priv->clock_rate) {
- tsc_timer_ensure_setup();
- uc_priv->clock_rate = gd->arch.clock_rate;
+ /* Try hardware calibration first */
+ tsc_timer_ensure_setup(false);
+ if (!gd->arch.clock_rate) {
+ /*
+* Use the clock frequency specified in the
+* device tree as last resort
+*/
+ if (!uc_priv->clock_rate)
+ panic("TSC frequency is ZERO");
} else {
- gd->arch.tsc_base = rdtsc();
+ uc_priv->clock_rate = gd->arch.clock_rate;
}
return 0;
@@ -394,7 +399,7 @@ unsigned long notrace timer_early_get_rate(void)
* clock rate can only be calibrated via some hardware ways. Specifying
* it in the device tree won't work for the early timer.
*/
- tsc_timer_ensure_setup();
+ tsc_timer_ensure_setup(true);
return gd->arch.clock_rate;
}
--
2.7.4
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[U-Boot] [PATCH 5/6] x86: coreboot: Add default TSC frequency in the device tree
It was observed sometimes U-Boot as the coreboot payload fails to
boot on QEMU. This is because TSC calibration fails with no valid
frequency. This adds default TSC frequency in the device tree.
Signed-off-by: Bin Meng
---
arch/x86/dts/coreboot.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
index a94f781..e212f3d 100644
--- a/arch/x86/dts/coreboot.dts
+++ b/arch/x86/dts/coreboot.dts
@@ -30,6 +30,10 @@
stdout-path = "/serial";
};
+ tsc-timer {
+ clock-frequency = <10>;
+ };
+
pci {
compatible = "pci-x86";
u-boot,dm-pre-reloc;
--
2.7.4
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[U-Boot] [PATCH] Convert CONFIG_SYS_I2C_DAVINCI to Kconfig
This converts the following to Kconfig: CONFIG_SYS_I2C_DAVINCI Signed-off-by: Adam Ford diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig index abb2295951..31e0529e40 100644 --- a/configs/da850_am18xxevm_defconfig +++ b/configs/da850_am18xxevm_defconfig @@ -38,6 +38,7 @@ CONFIG_DM=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y +CONFIG_SYS_I2C_DAVINCI=y CONFIG_MTD_DEVICE=y CONFIG_MTD_PARTITIONS=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 4242728e6a..ea56d01344 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -40,6 +40,7 @@ CONFIG_DM_GPIO=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y +CONFIG_SYS_I2C_DAVINCI=y CONFIG_MTD_DEVICE=y CONFIG_MTD_PARTITIONS=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 9d6c47df50..b5f17c2575 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -38,6 +38,7 @@ CONFIG_DM=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y +CONFIG_SYS_I2C_DAVINCI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig index ace5fc51d4..76f2d97786 100644 --- a/configs/ea20_defconfig +++ b/configs/ea20_defconfig @@ -30,6 +30,7 @@ CONFIG_CMD_DIAG=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DA8XX_GPIO=y +CONFIG_SYS_I2C_DAVINCI=y # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_DAVINCI=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index c5bb84a8d6..0b9fcd2cd9 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -34,6 +34,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y # CONFIG_MMC is not set CONFIG_NAND=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index a86eeb8b14..78b0060457 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -27,6 +27,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y # CONFIG_MMC is not set CONFIG_NAND=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 911618c17a..813483b40f 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -34,6 +34,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y # CONFIG_BLK is not set +CONFIG_SYS_I2C_DAVINCI=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index 174af79960..015eb54ec1 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -27,6 +27,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y # CONFIG_BLK is not set +CONFIG_SYS_I2C_DAVINCI=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 942e44e7a9..ee24a558b7 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -34,6 +34,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y # CONFIG_MMC is not set CONFIG_NAND=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 12be37f0b7..4af27ed30f 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -27,6 +27,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y # CONFIG_MMC is not set CONFIG_NAND=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 5381e9f7cc..4150af1d9c 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -34,6 +34,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y # CONFIG_MMC is not set CONFIG_NAND=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 0381a7240c..f9f38ee62f 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -26,6 +26,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y # CONFIG_MMC is not set CONFIG_NAND=y diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig index 8ee2d223fd..c9a7eb6e10 100644 --- a/configs/legoev3_defconfig +++ b/configs/legoev3_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_SPI=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_DIAG=y +CONFIG_SYS_I2C_DAVINCI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SYS_NS16550=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 4a97269dd4..b16e
Re: [U-Boot] [PATCH] efi_loader: fix a parameter check at CreateEvent()
On 08/10/2018 08:36 AM, AKASHI Takahiro wrote:
> The commit 21b3edfc9644 ("efi_loader: check parameters of CreateEvent")
> enforces a strict parameter check at CreateEvent(). On the other hand,
> UEFI specification version 2.7, section 7.1, says:
>
> The EVT_NOTIFY_WAIT and EVT_NOTIFY_SIGNAL flags are exclusive. If
> neither flag is specified, the caller does not require any notification
> concerning the event and the NotifyTpl, NotifyFunction, and
> NotifyContext parameters are ignored.
>
> So the check should be mitigated so as to comply with the specification.
> Without this patch, EDK2's Shell.efi won't be started.
>
> Fixes: 21b3edfc9644 ("efi_loader: check parameters of CreateEvent")
> Signed-off-by: AKASHI Takahiro
> ---
> lib/efi_loader/efi_boottime.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
> index ac8f484507bd..f3fba3190981 100644
> --- a/lib/efi_loader/efi_boottime.c
> +++ b/lib/efi_loader/efi_boottime.c
> @@ -627,7 +627,8 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t
> notify_tpl,
> return EFI_INVALID_PARAMETER;
> }
>
> - if (is_valid_tpl(notify_tpl) != EFI_SUCCESS)
> + if ((type & (EVT_NOTIFY_WAIT | EVT_NOTIFY_SIGNAL)) &&
> + (is_valid_tpl(notify_tpl) != EFI_SUCCESS))
> return EFI_INVALID_PARAMETER;
>
> evt = calloc(1, sizeof(struct efi_event));
>
@Alex:
Please, add this to the pull request for rc2.
Reviewed-by: Heinrich Schuchardt
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Re: [U-Boot] [PATCH] spi: davinci: Full dm conversion
On Fri, Aug 10, 2018 at 12:14 AM Jagan Teki wrote:
>
> On Wed, Aug 8, 2018 at 6:47 PM, Adam Ford wrote:
> > On Tue, Aug 7, 2018 at 1:29 AM Jagan Teki
> > wrote:
> >>
> >> davinci_spi now support dt along with platform data,
> >> respective boards need to switch into dm for the same.
> >>
> >> Cc: Adam Ford
> >> Cc: Vitaly Andrianov
> >> Cc: Stefano Babic
> >> Cc: Peter Howard
> >> Cc: Tom Rini
> >> Signed-off-by: Jagan Teki
> >> ---
> >> drivers/spi/Kconfig| 12 +-
> >> drivers/spi/davinci_spi.c | 289 +++--
> >> include/dm/platform_data/spi_davinci.h | 15 ++
> >> 3 files changed, 97 insertions(+), 219 deletions(-)
> >> create mode 100644 include/dm/platform_data/spi_davinci.h
> >>
> >> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> >> index d046e919b4..18ebff0231 100644
> >> --- a/drivers/spi/Kconfig
> >> +++ b/drivers/spi/Kconfig
> >> @@ -80,6 +80,12 @@ config CADENCE_QSPI
> >> used to access the SPI NOR flash on platforms embedding this
> >> Cadence IP core.
> >>
> >> +config DAVINCI_SPI
> >> + bool "Davinci & Keystone SPI driver"
> >> + depends on ARCH_DAVINCI || ARCH_KEYSTONE
> >> + help
> >> + Enable the Davinci SPI driver
> >> +
> >> config DESIGNWARE_SPI
> >> bool "Designware SPI driver"
> >> help
> >> @@ -281,12 +287,6 @@ config FSL_QSPI
> >> used to access the SPI NOR flash on platforms embedding this
> >> Freescale IP core.
> >>
> >> -config DAVINCI_SPI
> >> - bool "Davinci & Keystone SPI driver"
> >> - depends on ARCH_DAVINCI || ARCH_KEYSTONE
> >> - help
> >> - Enable the Davinci SPI driver
> >> -
> >> config SH_SPI
> >> bool "SuperH SPI driver"
> >> help
> >> diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
> >> index a822858323..5007e6c618 100644
> >> --- a/drivers/spi/davinci_spi.c
> >> +++ b/drivers/spi/davinci_spi.c
> >> @@ -14,6 +14,7 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >>
> >> /* SPIGCR0 */
> >> #define SPIGCR0_SPIENA_MASK0x1
> >> @@ -118,9 +119,6 @@ struct davinci_spi_regs {
> >>
> >> /* davinci spi slave */
> >> struct davinci_spi_slave {
> >> -#ifndef CONFIG_DM_SPI
> >> - struct spi_slave slave;
> >> -#endif
> >> struct davinci_spi_regs *regs;
> >> unsigned int freq; /* current SPI bus frequency */
> >> unsigned int mode; /* current SPI mode used */
> >> @@ -240,11 +238,43 @@ static int davinci_spi_read_write(struct
> >> davinci_spi_slave *ds, unsigned
> >> return 0;
> >> }
> >>
> >> +static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
> >> +{
> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
> >>
> >> -static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
> >> + debug("%s speed %u\n", __func__, max_hz);
> >> + if (max_hz > CONFIG_SYS_SPI_CLK / 2)
> >> + return -EINVAL;
> >> +
> >> + ds->freq = max_hz;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int davinci_spi_set_mode(struct udevice *bus, uint mode)
> >> +{
> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
> >> +
> >> + debug("%s mode %u\n", __func__, mode);
> >> + ds->mode = mode;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int davinci_spi_claim_bus(struct udevice *dev)
> >> {
> >> + struct dm_spi_slave_platdata *slave_plat =
> >> + dev_get_parent_platdata(dev);
> >> + struct udevice *bus = dev->parent;
> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
> >> unsigned int mode = 0, scalar;
> >>
> >> + if (slave_plat->cs >= ds->num_cs) {
> >> + printf("Invalid SPI chipselect\n");
> >> + return -EINVAL;
> >> + }
> >> + ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
> >> +
> >> /* Enable the SPI hardware */
> >> writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
> >> udelay(1000);
> >> @@ -254,7 +284,7 @@ static int __davinci_spi_claim_bus(struct
> >> davinci_spi_slave *ds, int cs)
> >> writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
> >>
> >> /* CS, CLK, SIMO and SOMI are functional pins */
> >> - writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
> >> + writel(((1 << slave_plat->cs) | SPIPC0_CLKFUN_MASK |
> >> SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
> >>
> >> /* setup format */
> >> @@ -292,20 +322,32 @@ static int __davinci_spi_claim_bus(struct
> >> davinci_spi_slave *ds, int cs)
> >> return 0;
> >> }
> >>
> >> -static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
> >> +static int davinci_spi_release_bus(struct udevice *dev)
> >> {
> >> + struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
> >> +
> >> /* Disable the SPI hardware */
> >> writel(SPIGCR0_SPIRST_MAS
[U-Boot] [PATCH] configs: da850evm: Remove DM_I2C_COMPAT
Since using DM_I2C_COMPAT throws a warning during compilation, and it isn't really needed any longer, so this patch removes this feature and shrinks the code a bit. from: textdata bss dec hex filename 343326 13388 123448 480162 753a2 u-boot to: textdata bss dec hex filename 342924 13380 123440 479744 75200 u-boot Signed-off-by: Adam Ford diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index ea56d01344..56d87334a7 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -39,7 +39,6 @@ CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_MTD_DEVICE=y CONFIG_MTD_PARTITIONS=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 5/6] serial: ns16550: fix debug uart putc called before init
On 08/10/2018 07:22 AM, Simon Goldschmidt wrote:
> On 10.08.2018 00:41, Marek Vasut wrote:
>> On 08/10/2018 12:35 AM, Andy Shevchenko wrote:
>>> On Fri, Aug 10, 2018 at 12:45 AM, Marek Vasut wrote:
On 08/09/2018 11:13 PM, Adam Ford wrote:
> On Thu, Aug 9, 2018 at 2:08 PM Simon Goldschmidt
> wrote:
>> If _debug_uart_putc() is called before _debug_uart_init(), the
>> ns16550 debug uart driver hangs in a tight loop waiting for the
>> tx FIFO to get empty.
>>
>> As this can happen via a printf sneaking in before the port calls
>> debug_uart_init(), let's rather ignore characters before the debug
>> uart is initialized.
>>
>> This is done by reading the baudrate divisor and aborting if is zero.
>> static inline void _debug_uart_putc(int ch)
>> {
>> struct NS16550 *com_port = (struct NS16550
>> *)CONFIG_DEBUG_UART_BASE;
>> + while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) {
>> + if (!NS16550_read_baud_divisor(com_port))
> Unless there is a change that the read_baud_divisor will change while
> we're waiting for the character, could we move this check before the
> while statement? This would reduce the check for the divisor to 1x
> and the while statement would only have one comparison to do. I
> realize it's rather trivial, but the way I see it, there is no reason
> to do the while statement at all if the read_baud_divisor fails and
> there if there is a baud divisor, we should only need to check it
> once.
This looks like a massive hack -- what about having a flag which says
that the debug uart was/was not inited somewhere ?
>>> Agree, why not to cache divisor value, for example, instead of doing
>>> slow I/O?
>> But why do we care about the divisor at all ?
>
> Because if the divisor is zero, the UART is disabled.
>
>> The real problem I believe
>> is that someone can call debug UART print/read functions before it is
>> inited.
>>
> I know this is a hack. I did it like that because I need something like
> this to get debug uart to work on socfpga gen5 (there always is a printf
> before debug uart init is possible).
>
> A generic solution for all debug uarts would be better of course, but
> given the point in SPL runtime, we might have to add a field to 'gd' for
> that, or does a global variable work at that point already?
GD field might be needed indeed.
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] pci: Support parsing PCI controller DT subnodes
On 08/10/2018 05:42 AM, Bin Meng wrote: > Hi Marek, > > On Thu, Aug 9, 2018 at 6:25 PM, Marek Vasut wrote: >> On 08/09/2018 11:41 AM, Bin Meng wrote: >> >> [...] >> >>> Sorry this is a hack to current U-Boot implementation, not fix. >> >> I am waiting for a better solution or suggestion ... >> >>> The fix should be adding "ehci-pci" compatible string in the >>> r8a7794.dtsi. >> >> Wrong. The DT is perfectly valid as is. >> > > I did not say r8a7794.dtsi is invalid. Being valid does not mean it > works everywhere. Being valid only means its syntax follows the DTS > language and does not cause any build error. Adding a "compatible" > string to a DT node is also perfectly valid. See "Binding Guidelines" > in devicetree-specification-v0.2.pdf [1] Hacking up DT to work around bugs in an OS implementation makes it OS specific and this is incorrect. It is the OS that should be fixed, in this case U-Boot. >>> >>> It's not a bug of U-Boot implementation. U-Boot DM was designed this >>> way. >> >> Then the design is flawed. (and btw. the U-Boot DM was not designed that >> way, you can take my word for it :-) ) >> > > Then please propose something that that is not flawed. But this patch > is not a fix to the design, but a hack. You are mixing two things in this answer, so it makes no sense. Anyway, let me just stop you here, DM was not designed in such a way, period. >>> If you are in U-Boot, you must follow U-Boot's rule. And I don't >>> see current DM is a wrong design. >> >> Wrong, U-Boot is given some hardware to run on and a matching >> description, DT. If both are valid and U-Boot cannot operate on them, >> then U-Boot is broken and must be fixed. >> >> You cannot claim that just because U-Boot behaves in some way, a >> perfectly good hardware and/or it's description is wrong and needs to be >> adjusted. That makes no sense. >> > > Again, who said current dts is *invalid*? You keep saying "valid", > "valid"... Can you explain why adding a perfectly OK "compatible" > string suddenly makes the DT invalid? Adding a compatible to DT may or may not make it invalid. Yet, the DT at hand is valid already, so adding extra crap into it just to work around buggy or incomplete implementation of PCI DT parsing is not an option. >> Just assume the DT is in ROM, it's set in stone and it cannot be >> changed. Then the entire discussion below becomes pointless and we can >> focus on fixing U-Boot such that it'd be able to parse the DT properly. >> > > Sometimes we have to update DT as not every working DT is born from day 1. This DT at hand is working and valid. It cannot and will not be updated only because U-Boot PCI implementation is lacking. Keep in mind that the DT may even be stored in ROM and can not be modified. > 4.1 Binding Guidelines > 4.1.1 General Principles > When creating a new devicetree representation for a device, a binding > should be created that fully describes the required properties and > value of the device. This set of properties shall be sufficiently > descriptive to provide device drivers with needed attributes of the > device. Some recommended practices include: > 1. Define a *compatible* string using the conventions described in > section 2.3.1 > ... Yes, "recommended" . The compatible string is not a hard requirement. >>> >>> OK, since you mentioned "recommended", let me paste the bullet 2 from >>> the same spec: >>> >>> Some recommended practices include: >>> 1. Define a compatible string using the conventions described in section >>> 2.3.1. >>> 2. Use the standard properties (defined in sections 2.3 and 2.4) as >>> applicable for the new device. This usage typically includes the *reg* >>> and interrupts properties at a minimum. >>> 3. Use the conventions specified in section 4 (Device Bindings) if the >>> new device fits into one the DTSpec defined device classes >>> ... >>> >>> Bullet 2 says: This usage *typically* includes the *reg* and >>> interrupts properties at a minimum. That means "reg" is not mandatory. >>> >>> And now let's see this patch: >>> >>> df = ofnode_get_addr_size(node, "reg", &size); >>> >>> Who says a node must have a "reg" property? Using this as a sign to >>> attach to DT is definitely wrong. >> >> If there is no "reg" property, then you won't get a node associated with >> the driver instance and that's perfectly fine. Without the "reg" prop, >> you cannot figure out which PCI device/function the node describes, so >> how could you possibly associate the node with a driver instance ? You >> cannot. >> > > This is a hack. I said many times if you add a "compatible" string DM > create the device node for you. I explained many times that the DT will not be updated to work around lacking implementation of PCI DT parsing in U-Boot. The DT is perfectly fine as-is. I also explained already that the PCI ID or clas
Re: [U-Boot] [PATCH v5 1/8] dm: mmc: use block layer in mmc driver
Hi Yinbo,
> -Original Message-
> From: Yinbo Zhu [mailto:yinbo@nxp.com]
> Sent: Friday, August 10, 2018 3:52 PM
> To: Yinbo Zhu ; york...@freescale.com;
> u-boot@lists.denx.de
> Cc: Y.b. Lu ; Xiaobo Xie ; Andy
> Tang ; Peng Ma
> Subject: [PATCH v5 1/8] dm: mmc: use block layer in mmc driver
>
> At present the MMC subsystem maintains its own list of MMC devices. This
> cannot work with driver model when CONFIG_BLK is enabled, use blk_dread to
> replace previous mmc read interface, use mmc_get_blk_desc to get the mmc
> device property
>
> Signed-off-by: Yinbo Zhu
> ---
> Change in v5:
> use block layer in mmc driver
>
> arch/arm/cpu/armv8/fsl-layerscape/ppa.c |5 ++---
> drivers/mmc/mmc_legacy.c| 10 +-
> drivers/net/fm/fm.c |2 +-
> drivers/qe/qe.c |2 +-
> 4 files changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> index a31c4d9..95875d3 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> @@ -99,7 +99,7 @@ int ppa_init(void)
> cnt = DIV_ROUND_UP(fdt_header_len, 512);
> debug("%s: MMC read PPA FIT header: dev # %u, block # %u,
> count %u\n",
> __func__, dev, blk, cnt);
> - ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, fitp);
> + ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, fitp);
> if (ret != cnt) {
> free(fitp);
> printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
> @@
> -149,8 +149,7 @@ int ppa_init(void)
> cnt = DIV_ROUND_UP(fw_length, 512);
> debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n",
> __func__, dev, blk, cnt);
> - ret = mmc->block_dev.block_read(&mmc->block_dev,
> - blk, cnt, ppa_fit_addr);
> + ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ppa_fit_addr);
> if (ret != cnt) {
> free(ppa_fit_addr);
> printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
> diff
> --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c index
> 66a7cda..29d94e9 100644
> --- a/drivers/mmc/mmc_legacy.c
> +++ b/drivers/mmc/mmc_legacy.c
[Y.b. Lu] Please don't apply this change to mmc_legacy.c which is for operation
where CONFIG_BLK is never enabled.
> @@ -42,7 +42,7 @@ struct mmc *find_mmc_device(int dev_num)
> list_for_each(entry, &mmc_devices) {
> m = list_entry(entry, struct mmc, link);
>
> - if (m->block_dev.devnum == dev_num)
> + if (mmc_get_blk_desc(m)->devnum == dev_num)
> return m;
> }
>
> @@ -60,7 +60,7 @@ int mmc_get_next_devnum(void)
>
> struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) {
> - return &mmc->block_dev;
> + return mmc_get_blk_desc(mmc);
> }
>
> int get_mmc_num(void)
> @@ -113,7 +113,7 @@ void print_mmc_devices(char separator)
> else
> mmc_type = NULL;
>
> - printf("%s: %d", m->cfg->name, m->block_dev.devnum);
> + printf("%s: %d", m->cfg->name, mmc_get_blk_desc(m)->devnum);
> if (mmc_type)
> printf(" (%s)", mmc_type);
>
> @@ -218,7 +218,7 @@ static int mmc_select_hwpartp(struct blk_desc *desc,
> int hwpart)
> if (!mmc)
> return -ENODEV;
>
> - if (mmc->block_dev.hwpart == hwpart)
> + if (mmc_get_blk_desc(mmc)->hwpart == hwpart)
> return 0;
>
> if (mmc->part_config == MMCPART_NOAVAILABLE) @@ -242,7 +242,7
> @@ static int mmc_get_dev(int dev, struct blk_desc **descp)
> if (ret)
> return ret;
>
> - *descp = &mmc->block_dev;
> + *descp = mmc_get_blk_desc(mmc);
>
> return 0;
> }
> diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 3327073..c5cf188
> 100644
> --- a/drivers/net/fm/fm.c
> +++ b/drivers/net/fm/fm.c
> @@ -402,7 +402,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
> printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
> dev, blk, cnt);
> mmc_init(mmc);
> - (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
> + (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
> addr);
> }
> #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
> diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 7654df8..7010bbc 100644
> --- a/drivers/qe/qe.c
> +++ b/drivers/qe/qe.c
> @@ -218,7 +218,7 @@ void u_qe_init(void)
> printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
> dev, blk, cnt);
> mmc_init(mmc);
> - (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
> + (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
>
Re: [U-Boot] [PATCH v5 3/8] Enable CONFIG_BLK and CONFIG_DM_MMC to Kconfig
Hi Yinbo, Better to apply this patch as the final one of this patch-set, after these dts node patches. Otherwise, mmc couldn't work at this commit on all boards. Best regards, Yangbo Lu > -Original Message- > From: Yinbo Zhu [mailto:yinbo@nxp.com] > Sent: Friday, August 10, 2018 3:52 PM > To: Yinbo Zhu ; york...@freescale.com; > u-boot@lists.denx.de > Cc: Y.b. Lu ; Xiaobo Xie ; Andy > Tang ; Peng Ma > Subject: [PATCH v5 3/8] Enable CONFIG_BLK and CONFIG_DM_MMC to > Kconfig > > This enables the folowing to Kconfig: > CONFIG_BLK > CONFIG_DM_MMC > > Signed-off-by: Yinbo Zhu > --- > configs/ls1021atwr_nor_SECURE_BOOT_defconfig |2 ++ > configs/ls1021atwr_nor_defconfig |2 ++ > configs/ls1021atwr_nor_lpuart_defconfig|2 ++ > configs/ls1021atwr_qspi_defconfig |2 ++ > .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig|2 ++ > configs/ls1021atwr_sdcard_ifc_defconfig|2 ++ > configs/ls1021atwr_sdcard_qspi_defconfig |2 ++ > configs/ls1043aqds_defconfig |2 ++ > configs/ls1043aqds_lpuart_defconfig|2 ++ > configs/ls1043aqds_nand_defconfig |2 ++ > configs/ls1043aqds_nor_ddr3_defconfig |2 ++ > configs/ls1043aqds_qspi_defconfig |2 ++ > configs/ls1043aqds_sdcard_ifc_defconfig|2 ++ > configs/ls1043aqds_sdcard_qspi_defconfig |2 ++ > configs/ls1043ardb_SECURE_BOOT_defconfig |2 ++ > configs/ls1043ardb_defconfig |2 ++ > configs/ls1043ardb_nand_SECURE_BOOT_defconfig |2 ++ > configs/ls1043ardb_nand_defconfig |2 ++ > configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig|2 ++ > configs/ls1043ardb_sdcard_defconfig|2 ++ > configs/ls1046aqds_SECURE_BOOT_defconfig |2 ++ > configs/ls1046aqds_defconfig |2 ++ > configs/ls1046aqds_lpuart_defconfig|2 ++ > configs/ls1046aqds_nand_defconfig |2 ++ > configs/ls1046aqds_qspi_defconfig |2 ++ > configs/ls1046aqds_sdcard_ifc_defconfig|2 ++ > configs/ls1046aqds_sdcard_qspi_defconfig |2 ++ > configs/ls1046ardb_emmc_defconfig |2 ++ > configs/ls1046ardb_qspi_SECURE_BOOT_defconfig |2 ++ > configs/ls1046ardb_qspi_defconfig |2 ++ > configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig|2 ++ > configs/ls1046ardb_sdcard_defconfig|2 ++ > configs/ls1088aqds_defconfig |2 ++ > configs/ls1088aqds_qspi_SECURE_BOOT_defconfig |2 ++ > configs/ls1088aqds_qspi_defconfig |2 ++ > configs/ls1088aqds_sdcard_ifc_defconfig|2 ++ > configs/ls1088aqds_sdcard_qspi_defconfig |2 ++ > configs/ls1088ardb_qspi_SECURE_BOOT_defconfig |2 ++ > configs/ls1088ardb_qspi_defconfig |2 ++ > .../ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig |2 ++ > configs/ls1088ardb_sdcard_qspi_defconfig |2 ++ > configs/ls2080a_emu_defconfig |2 ++ > configs/ls2080a_simu_defconfig |2 ++ > configs/ls2080aqds_SECURE_BOOT_defconfig |2 ++ > configs/ls2080aqds_defconfig |2 ++ > configs/ls2080aqds_nand_defconfig |2 ++ > configs/ls2080aqds_qspi_defconfig |2 ++ > configs/ls2080aqds_sdcard_defconfig|2 ++ > configs/ls2080ardb_SECURE_BOOT_defconfig |2 ++ > configs/ls2080ardb_defconfig |2 ++ > configs/ls2080ardb_nand_defconfig |2 ++ > configs/ls2088ardb_qspi_SECURE_BOOT_defconfig |2 ++ > configs/ls2088ardb_qspi_defconfig |2 ++ > 53 files changed, 106 insertions(+), 0 deletions(-) > > diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig > b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig > index 17a202d..4d85983 100644 > --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig > +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig > @@ -48,3 +48,5 @@ CONFIG_VIDEO=y > # CONFIG_VIDEO_SW_CURSOR is not set > CONFIG_RSA=y > CONFIG_SPL_RSA=y > +CONFIG_BLK=y > +CONFIG_DM_MMC=y > diff --git a/configs/ls1021atwr_nor_defconfig > b/configs/ls1021atwr_nor_defconfig > index a18426e..f4f7998 100644 > --- a/configs/ls1021atwr_nor_defconfig > +++ b/configs/ls1021atwr_nor_defconfig > @@ -48,3 +48,5 @@ CONFIG_USB_STORAGE=y > CONFIG_VIDEO_FSL_DCU_FB=y > CONFIG_VIDEO=y > # CONFIG_VIDEO_SW_CURSOR is not set > +CONFIG_BLK=y > +CONFIG_DM_MMC=y > diff --git a/configs/ls1021atwr_nor_lpuart_defconfig > b/configs/ls1021atwr_nor_lpuart_defconfig > index 83ffa19..037f56c 100644 > --- a/configs/ls1021atwr_nor_lpuart_defconfig >
Re: [U-Boot] [PATCH 5/6] serial: ns16550: fix debug uart putc called before init
On 10.08.2018 11:51, Marek Vasut wrote:
On 08/10/2018 07:22 AM, Simon Goldschmidt wrote:
On 10.08.2018 00:41, Marek Vasut wrote:
On 08/10/2018 12:35 AM, Andy Shevchenko wrote:
On Fri, Aug 10, 2018 at 12:45 AM, Marek Vasut wrote:
On 08/09/2018 11:13 PM, Adam Ford wrote:
On Thu, Aug 9, 2018 at 2:08 PM Simon Goldschmidt
wrote:
If _debug_uart_putc() is called before _debug_uart_init(), the
ns16550 debug uart driver hangs in a tight loop waiting for the
tx FIFO to get empty.
As this can happen via a printf sneaking in before the port calls
debug_uart_init(), let's rather ignore characters before the debug
uart is initialized.
This is done by reading the baudrate divisor and aborting if is zero.
static inline void _debug_uart_putc(int ch)
{
struct NS16550 *com_port = (struct NS16550
*)CONFIG_DEBUG_UART_BASE;
+ while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) {
+ if (!NS16550_read_baud_divisor(com_port))
Unless there is a change that the read_baud_divisor will change while
we're waiting for the character, could we move this check before the
while statement? This would reduce the check for the divisor to 1x
and the while statement would only have one comparison to do. I
realize it's rather trivial, but the way I see it, there is no reason
to do the while statement at all if the read_baud_divisor fails and
there if there is a baud divisor, we should only need to check it
once.
This looks like a massive hack -- what about having a flag which says
that the debug uart was/was not inited somewhere ?
Agree, why not to cache divisor value, for example, instead of doing
slow I/O?
But why do we care about the divisor at all ?
Because if the divisor is zero, the UART is disabled.
The real problem I believe
is that someone can call debug UART print/read functions before it is
inited.
I know this is a hack. I did it like that because I need something like
this to get debug uart to work on socfpga gen5 (there always is a printf
before debug uart init is possible).
A generic solution for all debug uarts would be better of course, but
given the point in SPL runtime, we might have to add a field to 'gd' for
that, or does a global variable work at that point already?
GD field might be needed indeed.
Right. I'll drop this patch in the next version of the series and
instead I'll try to work out something that works for all debug uarts
drivers using a gd field.
Thanks,
Simon
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[U-Boot] [PATCH] common: fdt: set the value of MEMORY_BANKS_MAX to 8
set the value of MEMORY_BANKS_MAX to 8.
Odroid-XU4 fails to boot with following message
fdt_fixup_memory_banks: num banks 8 exceeds hardcoded limit 4.
Recompile with higher MEMORY_BANKS_MAX?
ERROR: arch-specific fdt fixup failed
- must RESET the board to recover.
Fixes: commit 2a1f4f1758b5 (Revert "fdt_support: Use CONFIG_NR_DRAM_BANKS if
defined")
CC: Ramon Fried
CC: Simon Glass
Signed-off-by: Anand Moon
---
common/fdt_support.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 34d2bd59c4..ad87f31ab3 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -409,7 +409,7 @@ static int fdt_pack_reg(const void *fdt, void *buf, u64
*address, u64 *size,
return p - (char *)buf;
}
-#define MEMORY_BANKS_MAX 4
+#define MEMORY_BANKS_MAX 8
int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
{
int err, nodeoffset;
--
2.17.1
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Re: [U-Boot] [PATCH 5/6] serial: ns16550: fix debug uart putc called before init
On 08/10/2018 01:37 PM, Simon Goldschmidt wrote:
> On 10.08.2018 11:51, Marek Vasut wrote:
>> On 08/10/2018 07:22 AM, Simon Goldschmidt wrote:
>>> On 10.08.2018 00:41, Marek Vasut wrote:
On 08/10/2018 12:35 AM, Andy Shevchenko wrote:
> On Fri, Aug 10, 2018 at 12:45 AM, Marek Vasut wrote:
>> On 08/09/2018 11:13 PM, Adam Ford wrote:
>>> On Thu, Aug 9, 2018 at 2:08 PM Simon Goldschmidt
>>> wrote:
If _debug_uart_putc() is called before _debug_uart_init(), the
ns16550 debug uart driver hangs in a tight loop waiting for the
tx FIFO to get empty.
As this can happen via a printf sneaking in before the port calls
debug_uart_init(), let's rather ignore characters before the debug
uart is initialized.
This is done by reading the baudrate divisor and aborting if is
zero.
static inline void _debug_uart_putc(int ch)
{
struct NS16550 *com_port = (struct NS16550
*)CONFIG_DEBUG_UART_BASE;
+ while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) {
+ if (!NS16550_read_baud_divisor(com_port))
>>> Unless there is a change that the read_baud_divisor will change
>>> while
>>> we're waiting for the character, could we move this check before the
>>> while statement? This would reduce the check for the divisor to 1x
>>> and the while statement would only have one comparison to do. I
>>> realize it's rather trivial, but the way I see it, there is no
>>> reason
>>> to do the while statement at all if the read_baud_divisor fails and
>>> there if there is a baud divisor, we should only need to check it
>>> once.
>> This looks like a massive hack -- what about having a flag which says
>> that the debug uart was/was not inited somewhere ?
> Agree, why not to cache divisor value, for example, instead of doing
> slow I/O?
But why do we care about the divisor at all ?
>>> Because if the divisor is zero, the UART is disabled.
>>>
The real problem I believe
is that someone can call debug UART print/read functions before it is
inited.
>>> I know this is a hack. I did it like that because I need something like
>>> this to get debug uart to work on socfpga gen5 (there always is a printf
>>> before debug uart init is possible).
>>>
>>> A generic solution for all debug uarts would be better of course, but
>>> given the point in SPL runtime, we might have to add a field to 'gd' for
>>> that, or does a global variable work at that point already?
>> GD field might be needed indeed.
>>
> Right. I'll drop this patch in the next version of the series and
> instead I'll try to work out something that works for all debug uarts
> drivers using a gd field.
Thanks, much appreciated :)
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] pci: Support parsing PCI controller DT subnodes
On Wed, Aug 08, 2018 at 09:37:25PM +0200, Marek Vasut wrote:
> On 08/08/2018 05:32 PM, Bin Meng wrote:
> > Hi Marek,
> >
> > On Wed, Aug 8, 2018 at 10:33 PM, Marek Vasut wrote:
> >> On 08/08/2018 03:39 PM, Bin Meng wrote:
> >>> Hi Marek,
> >>>
> >>> On Wed, Aug 8, 2018 at 9:24 PM, Marek Vasut wrote:
> On 08/08/2018 03:14 PM, Bin Meng wrote:
> > Hi Marek,
> >
> > On Wed, Aug 8, 2018 at 9:03 PM, Marek Vasut
> > wrote:
> >> The PCI controller can have DT subnodes describing extra properties
> >> of particular PCI devices, ie. a PHY attached to an EHCI controller
> >> on a PCI bus. This patch parses those DT subnodes and assigns a node
> >> to the PCI device instance, so that the driver can extract details
> >> from that node and ie. configure the PHY using the PHY subsystem.
> >>
> >> Signed-off-by: Marek Vasut
> >> Cc: Simon Glass
> >> ---
> >> drivers/pci/pci-uclass.c | 14 ++
> >> 1 file changed, 14 insertions(+)
> >>
> >> diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
> >> index 46e9c71bdf..306bea0dbf 100644
> >> --- a/drivers/pci/pci-uclass.c
> >> +++ b/drivers/pci/pci-uclass.c
> >> @@ -662,6 +662,8 @@ static int pci_find_and_bind_driver(struct udevice
> >> *parent,
> >> for (id = entry->match;
> >> id->vendor || id->subvendor || id->class_mask;
> >> id++) {
> >> + ofnode node;
> >> +
> >> if (!pci_match_one_id(id, find_id))
> >> continue;
> >>
> >> @@ -691,6 +693,18 @@ static int pci_find_and_bind_driver(struct
> >> udevice *parent,
> >> goto error;
> >> debug("%s: Match found: %s\n", __func__,
> >> drv->name);
> >> dev->driver_data = find_id->driver_data;
> >> +
> >> + dev_for_each_subnode(node, parent) {
> >> + phys_addr_t df, size;
> >> + df = ofnode_get_addr_size(node, "reg",
> >> &size);
> >> +
> >> + if (PCI_FUNC(df) == PCI_FUNC(bdf) &&
> >> + PCI_DEV(df) == PCI_DEV(bdf)) {
> >> + dev->node = node;
> >> + break;
> >> + }
> >
> > The function pci_find_and_bind_driver() is supposed to bind devices
> > that are NOT in the device tree. Adding device tree access in this
> > routine is quite odd. You can add the EHCI controller that need such
> > PHY subnodes in the device tree and there is no need to modify
> > anything I believe. If you are looking for an example, please check
> > pciuart0 in arch/x86/dts/crownbay.dts.
>
> Well this does not work for me, the EHCI PCI doesn't get a DT node
> assigned, check r8a7794.dtsi for the PCI devices I use.
>
> >>>
> >>> I think that's because you don't specify a "compatible" string for
> >>> these two EHCI PCI nodes.
> >>
> >> That's perfectly fine, why should I specify it ? Linux has no problem
> >> with it either.
> >>
> >
> > Without a "compatible" string, DM does not bind any device in the
> > device tree to a driver, hence no device node created. This is not
> > Linux.
>
> DT is NOT Linux specific, it is OS-agnostic, DT describes hardware and
> hardware only. If U-Boot cannot parse DT correctly, U-Boot is broken and
> must be fixed.
>
> This is a fix. If there is a better fix, I am open to it.
DT should but isn't always OS agnostic. DTS files that reside in the
Linux Kernel are in practice is Linux-centric with the expectation that
even if you could solve a given problem with valid DTS changes you make
whatever is parsing it do additional logic instead. That,
approximately, is what your patch is doing. If you added some HW
description information to the dtsi file everything would work as
expected as your DTS is describing the hardware and U-Boot is reading
that description and figuring out what to do with it.
The problem here is that in Linux, something that sees the compatible
renesas,pci-r8a7794 or renesas,pci-rcar-gen2 is doing whatever else
needs to be done. Or something else? Please explain how what you want
to have work here in U-Boot is working in the Linux kernel. Thanks!
--
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Re: [U-Boot] [PATCH] pci: Support parsing PCI controller DT subnodes
On 08/10/2018 02:01 PM, Tom Rini wrote:
> On Wed, Aug 08, 2018 at 09:37:25PM +0200, Marek Vasut wrote:
>> On 08/08/2018 05:32 PM, Bin Meng wrote:
>>> Hi Marek,
>>>
>>> On Wed, Aug 8, 2018 at 10:33 PM, Marek Vasut wrote:
On 08/08/2018 03:39 PM, Bin Meng wrote:
> Hi Marek,
>
> On Wed, Aug 8, 2018 at 9:24 PM, Marek Vasut wrote:
>> On 08/08/2018 03:14 PM, Bin Meng wrote:
>>> Hi Marek,
>>>
>>> On Wed, Aug 8, 2018 at 9:03 PM, Marek Vasut
>>> wrote:
The PCI controller can have DT subnodes describing extra properties
of particular PCI devices, ie. a PHY attached to an EHCI controller
on a PCI bus. This patch parses those DT subnodes and assigns a node
to the PCI device instance, so that the driver can extract details
from that node and ie. configure the PHY using the PHY subsystem.
Signed-off-by: Marek Vasut
Cc: Simon Glass
---
drivers/pci/pci-uclass.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 46e9c71bdf..306bea0dbf 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -662,6 +662,8 @@ static int pci_find_and_bind_driver(struct udevice
*parent,
for (id = entry->match;
id->vendor || id->subvendor || id->class_mask;
id++) {
+ ofnode node;
+
if (!pci_match_one_id(id, find_id))
continue;
@@ -691,6 +693,18 @@ static int pci_find_and_bind_driver(struct
udevice *parent,
goto error;
debug("%s: Match found: %s\n", __func__,
drv->name);
dev->driver_data = find_id->driver_data;
+
+ dev_for_each_subnode(node, parent) {
+ phys_addr_t df, size;
+ df = ofnode_get_addr_size(node, "reg",
&size);
+
+ if (PCI_FUNC(df) == PCI_FUNC(bdf) &&
+ PCI_DEV(df) == PCI_DEV(bdf)) {
+ dev->node = node;
+ break;
+ }
>>>
>>> The function pci_find_and_bind_driver() is supposed to bind devices
>>> that are NOT in the device tree. Adding device tree access in this
>>> routine is quite odd. You can add the EHCI controller that need such
>>> PHY subnodes in the device tree and there is no need to modify
>>> anything I believe. If you are looking for an example, please check
>>> pciuart0 in arch/x86/dts/crownbay.dts.
>>
>> Well this does not work for me, the EHCI PCI doesn't get a DT node
>> assigned, check r8a7794.dtsi for the PCI devices I use.
>>
>
> I think that's because you don't specify a "compatible" string for
> these two EHCI PCI nodes.
That's perfectly fine, why should I specify it ? Linux has no problem
with it either.
>>>
>>> Without a "compatible" string, DM does not bind any device in the
>>> device tree to a driver, hence no device node created. This is not
>>> Linux.
>>
>> DT is NOT Linux specific, it is OS-agnostic, DT describes hardware and
>> hardware only. If U-Boot cannot parse DT correctly, U-Boot is broken and
>> must be fixed.
>>
>> This is a fix. If there is a better fix, I am open to it.
>
> DT should but isn't always OS agnostic. DTS files that reside in the
> Linux Kernel are in practice is Linux-centric with the expectation that
> even if you could solve a given problem with valid DTS changes you make
> whatever is parsing it do additional logic instead. That,
> approximately, is what your patch is doing. If you added some HW
> description information to the dtsi file everything would work as
> expected as your DTS is describing the hardware and U-Boot is reading
> that description and figuring out what to do with it.
Yes, you need additional logic to match the PCI controller subnode in DT
with PCI device BFD, that's expected. You do NOT need extra compatibles,
the PCI bus gives you enough information to match a driver on them. In
fact, adding a compatible can interfere with this matching.
> The problem here is that in Linux, something that sees the compatible
> renesas,pci-r8a7794 or renesas,pci-rcar-gen2 is doing whatever else
> needs to be done. Or something else? Please explain how what you want
> to have work here in U-Boot is working in the Linux kernel. Thanks!
This has nothing to do with a specific controller. iMX6 does the same
thing, see ie arch
Re: [U-Boot] [PATCH 1/6] arm: socfpga: fix SPL on gen5 after moving to DM serial
On 09.08.2018 23:42, Marek Vasut wrote:
On 08/09/2018 09:04 PM, Simon Goldschmidt wrote:
There were NULL pointers dereferenced because DM was used
too early without correct initialization:
- malloc_simple returned NULL when called from preloader_console_init()
because gd->malloc_limit was 0
- uclass_add dereferenced gd->uclass_root members which were NULL because
dm_init (or one of its relatives) has not been called.
All this is fixed by calling spl_early_init before calling
preloader_console_init.
This fixes commit 73172753f4f3 ("ARM: socfpga: Convert to DM serial")
Signed-off-by: Simon Goldschmidt
---
v2:
- Don't remove gd->malloc_base assignment at the end of board_init_f()
(moved to an extra patch)
arch/arm/mach-socfpga/spl_gen5.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index d6fe7d35af..9bdfaa3c1e 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -86,6 +86,7 @@ void board_init_f(ulong dummy)
const struct cm_config *cm_default_cfg = cm_get_default_config();
unsigned long sdram_size;
unsigned long reg;
+ int ret;
/*
* First C code to run. Clear fake OCRAM ECC first as SBE
@@ -152,6 +153,12 @@ void board_init_f(ulong dummy)
/* unfreeze / thaw all IO banks */
sys_mgr_frzctrl_thaw_req();
+ ret = spl_early_init();
Uh, but isn't this called from common/spl/spl.c ? I suspect the SoCFPGA
SPL is a bit weird.
Ehrm, I copied this from spl_s10.c, but other boards seem to do this,
too. Honestly, I don't know how any SPL can use DM serial without this
being called. Maybe other SPLs initialize the serial port later (not in
board_init_f).
common/spl/spl.c calls spl_init(), which also calls the part that
spl_early_init() calls.
I can only take other SPLs as reference and from reading all the code, I
think this should be good.
Simon
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
/* enable console uart printing */
preloader_console_init();
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Re: [U-Boot] [PATCH 1/6] arm: socfpga: fix SPL on gen5 after moving to DM serial
On 08/10/2018 02:39 PM, Simon Goldschmidt wrote:
> On 09.08.2018 23:42, Marek Vasut wrote:
>> On 08/09/2018 09:04 PM, Simon Goldschmidt wrote:
>>> There were NULL pointers dereferenced because DM was used
>>> too early without correct initialization:
>>> - malloc_simple returned NULL when called from preloader_console_init()
>>> because gd->malloc_limit was 0
>>> - uclass_add dereferenced gd->uclass_root members which were NULL
>>> because
>>> dm_init (or one of its relatives) has not been called.
>>>
>>> All this is fixed by calling spl_early_init before calling
>>> preloader_console_init.
>>>
>>> This fixes commit 73172753f4f3 ("ARM: socfpga: Convert to DM serial")
>>>
>>> Signed-off-by: Simon Goldschmidt
>>> ---
>>> v2:
>>> - Don't remove gd->malloc_base assignment at the end of board_init_f()
>>> (moved to an extra patch)
>>>
>>> arch/arm/mach-socfpga/spl_gen5.c | 7 +++
>>> 1 file changed, 7 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-socfpga/spl_gen5.c
>>> b/arch/arm/mach-socfpga/spl_gen5.c
>>> index d6fe7d35af..9bdfaa3c1e 100644
>>> --- a/arch/arm/mach-socfpga/spl_gen5.c
>>> +++ b/arch/arm/mach-socfpga/spl_gen5.c
>>> @@ -86,6 +86,7 @@ void board_init_f(ulong dummy)
>>> const struct cm_config *cm_default_cfg = cm_get_default_config();
>>> unsigned long sdram_size;
>>> unsigned long reg;
>>> + int ret;
>>> /*
>>> * First C code to run. Clear fake OCRAM ECC first as SBE
>>> @@ -152,6 +153,12 @@ void board_init_f(ulong dummy)
>>> /* unfreeze / thaw all IO banks */
>>> sys_mgr_frzctrl_thaw_req();
>>> + ret = spl_early_init();
>> Uh, but isn't this called from common/spl/spl.c ? I suspect the SoCFPGA
>> SPL is a bit weird.
>
> Ehrm, I copied this from spl_s10.c, but other boards seem to do this,
> too. Honestly, I don't know how any SPL can use DM serial without this
> being called. Maybe other SPLs initialize the serial port later (not in
> board_init_f).
I mean, spl_early_init() is called in common/spl/spl.c , which is common
code. Maybe the socfpga SPL is structured in a really weird way (I think
it is).
> common/spl/spl.c calls spl_init(), which also calls the part that
> spl_early_init() calls.
>
> I can only take other SPLs as reference and from reading all the code, I
> think this should be good.
Right
> Simon
>
>>
>>> + if (ret) {
>>> + debug("spl_early_init() failed: %d\n", ret);
>>> + hang();
>>> + }
>>> +
>>> /* enable console uart printing */
>>> preloader_console_init();
>>>
>>
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] spi: davinci: Full dm conversion
On Fri, Aug 10, 2018 at 3:50 PM, Adam Ford wrote:
> On Fri, Aug 10, 2018 at 12:14 AM Jagan Teki
> wrote:
>>
>> On Wed, Aug 8, 2018 at 6:47 PM, Adam Ford wrote:
>> > On Tue, Aug 7, 2018 at 1:29 AM Jagan Teki
>> > wrote:
>> >>
>> >> davinci_spi now support dt along with platform data,
>> >> respective boards need to switch into dm for the same.
>> >>
>> >> Cc: Adam Ford
>> >> Cc: Vitaly Andrianov
>> >> Cc: Stefano Babic
>> >> Cc: Peter Howard
>> >> Cc: Tom Rini
>> >> Signed-off-by: Jagan Teki
>> >> ---
>> >> drivers/spi/Kconfig| 12 +-
>> >> drivers/spi/davinci_spi.c | 289 +++--
>> >> include/dm/platform_data/spi_davinci.h | 15 ++
>> >> 3 files changed, 97 insertions(+), 219 deletions(-)
>> >> create mode 100644 include/dm/platform_data/spi_davinci.h
>> >>
>> >> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>> >> index d046e919b4..18ebff0231 100644
>> >> --- a/drivers/spi/Kconfig
>> >> +++ b/drivers/spi/Kconfig
>> >> @@ -80,6 +80,12 @@ config CADENCE_QSPI
>> >> used to access the SPI NOR flash on platforms embedding this
>> >> Cadence IP core.
>> >>
>> >> +config DAVINCI_SPI
>> >> + bool "Davinci & Keystone SPI driver"
>> >> + depends on ARCH_DAVINCI || ARCH_KEYSTONE
>> >> + help
>> >> + Enable the Davinci SPI driver
>> >> +
>> >> config DESIGNWARE_SPI
>> >> bool "Designware SPI driver"
>> >> help
>> >> @@ -281,12 +287,6 @@ config FSL_QSPI
>> >> used to access the SPI NOR flash on platforms embedding this
>> >> Freescale IP core.
>> >>
>> >> -config DAVINCI_SPI
>> >> - bool "Davinci & Keystone SPI driver"
>> >> - depends on ARCH_DAVINCI || ARCH_KEYSTONE
>> >> - help
>> >> - Enable the Davinci SPI driver
>> >> -
>> >> config SH_SPI
>> >> bool "SuperH SPI driver"
>> >> help
>> >> diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
>> >> index a822858323..5007e6c618 100644
>> >> --- a/drivers/spi/davinci_spi.c
>> >> +++ b/drivers/spi/davinci_spi.c
>> >> @@ -14,6 +14,7 @@
>> >> #include
>> >> #include
>> >> #include
>> >> +#include
>> >>
>> >> /* SPIGCR0 */
>> >> #define SPIGCR0_SPIENA_MASK0x1
>> >> @@ -118,9 +119,6 @@ struct davinci_spi_regs {
>> >>
>> >> /* davinci spi slave */
>> >> struct davinci_spi_slave {
>> >> -#ifndef CONFIG_DM_SPI
>> >> - struct spi_slave slave;
>> >> -#endif
>> >> struct davinci_spi_regs *regs;
>> >> unsigned int freq; /* current SPI bus frequency */
>> >> unsigned int mode; /* current SPI mode used */
>> >> @@ -240,11 +238,43 @@ static int davinci_spi_read_write(struct
>> >> davinci_spi_slave *ds, unsigned
>> >> return 0;
>> >> }
>> >>
>> >> +static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
>> >> +{
>> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
>> >>
>> >> -static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
>> >> + debug("%s speed %u\n", __func__, max_hz);
>> >> + if (max_hz > CONFIG_SYS_SPI_CLK / 2)
>> >> + return -EINVAL;
>> >> +
>> >> + ds->freq = max_hz;
>> >> +
>> >> + return 0;
>> >> +}
>> >> +
>> >> +static int davinci_spi_set_mode(struct udevice *bus, uint mode)
>> >> +{
>> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
>> >> +
>> >> + debug("%s mode %u\n", __func__, mode);
>> >> + ds->mode = mode;
>> >> +
>> >> + return 0;
>> >> +}
>> >> +
>> >> +static int davinci_spi_claim_bus(struct udevice *dev)
>> >> {
>> >> + struct dm_spi_slave_platdata *slave_plat =
>> >> + dev_get_parent_platdata(dev);
>> >> + struct udevice *bus = dev->parent;
>> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
>> >> unsigned int mode = 0, scalar;
>> >>
>> >> + if (slave_plat->cs >= ds->num_cs) {
>> >> + printf("Invalid SPI chipselect\n");
>> >> + return -EINVAL;
>> >> + }
>> >> + ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
>> >> +
>> >> /* Enable the SPI hardware */
>> >> writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
>> >> udelay(1000);
>> >> @@ -254,7 +284,7 @@ static int __davinci_spi_claim_bus(struct
>> >> davinci_spi_slave *ds, int cs)
>> >> writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK,
>> >> &ds->regs->gcr1);
>> >>
>> >> /* CS, CLK, SIMO and SOMI are functional pins */
>> >> - writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
>> >> + writel(((1 << slave_plat->cs) | SPIPC0_CLKFUN_MASK |
>> >> SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
>> >>
>> >> /* setup format */
>> >> @@ -292,20 +322,32 @@ static int __davinci_spi_claim_bus(struct
>> >> davinci_spi_slave *ds, int cs)
>> >> return 0;
>> >> }
>> >>
>> >> -static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
>> >> +static int davinci_spi_re
Re: [U-Boot] [PATCH 2/6] x86: Remove support for Advantech SOM-6896
I don't have time to test the generic coreboot support on this board
right now but sounds fine to me.
Thanks,
George McCollister
On Fri, Aug 10, 2018 at 4:39 AM, Bin Meng wrote:
> Now that we have generic coreboot payload support, remove the
> dedicated support for Advantech SOM-6896.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/dts/Makefile | 1 -
> arch/x86/dts/broadwell_som-6896.dts | 52
> -
> include/configs/som-6896.h | 28
> 3 files changed, 81 deletions(-)
> delete mode 100644 arch/x86/dts/broadwell_som-6896.dts
> delete mode 100644 include/configs/som-6896.h
>
> diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
> index c62540f..fa717bc 100644
> --- a/arch/x86/dts/Makefile
> +++ b/arch/x86/dts/Makefile
> @@ -18,7 +18,6 @@ dtb-y += bayleybay.dtb \
> qemu-x86_i440fx.dtb \
> qemu-x86_q35.dtb \
> theadorable-x86-dfi-bt700.dtb \
> - broadwell_som-6896.dtb \
> baytrail_som-db5800-som-6867.dtb
>
> targets += $(dtb-y)
> diff --git a/arch/x86/dts/broadwell_som-6896.dts
> b/arch/x86/dts/broadwell_som-6896.dts
> deleted file mode 100644
> index ec691f1..000
> --- a/arch/x86/dts/broadwell_som-6896.dts
> +++ /dev/null
> @@ -1,52 +0,0 @@
> -/dts-v1/;
> -
> -/include/ "skeleton.dtsi"
> -/include/ "serial.dtsi"
> -/include/ "reset.dtsi"
> -/include/ "rtc.dtsi"
> -/include/ "tsc_timer.dtsi"
> -/include/ "coreboot_fb.dtsi"
> -
> -/ {
> - model = "Advantech SOM-6896";
> - compatible = "advantech,som-6896", "intel,broadwell";
> -
> - aliases {
> - spi0 = &spi;
> - };
> -
> - config {
> - silent_console = <0>;
> - };
> -
> - chosen {
> - stdout-path = "/serial";
> - };
> -
> - pci {
> - compatible = "pci-x86";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - u-boot,dm-pre-reloc;
> - ranges = <0x0200 0x0 0xe000 0xe000 0 0x1000
> - 0x4200 0x0 0xd000 0xd000 0 0x1000
> - 0x0100 0x0 0x2000 0x2000 0 0xe000>;
> -
> - pch@1f,0 {
> - reg = <0xf800 0 0 0 0>;
> - compatible = "intel,pch9";
> -
> - spi: spi {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "intel,ich9-spi";
> - spi-flash@0 {
> - reg = <0>;
> - compatible = "winbond,w25q128",
> "spi-flash";
> - memory-map = <0xff00 0x0100>;
> - };
> - };
> - };
> - };
> -
> -};
> diff --git a/include/configs/som-6896.h b/include/configs/som-6896.h
> deleted file mode 100644
> index f0e8d61..000
> --- a/include/configs/som-6896.h
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Configuration settings for the SOM-6896
> - *
> - * Copyright (C) 2015 NovaTech LLC
> - * George McCollister
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -#include
> -
> -#define CONFIG_SYS_MONITOR_LEN (1 << 20)
> -
> -#define CONFIG_MISC_INIT_R
> -
> -#define VIDEO_IO_OFFSET0
> -#define CONFIG_X86EMU_RAW_IO
> -
> -#define CONFIG_STD_DEVICES_SETTINGS"stdin=serial,usbkbd\0" \
> - "stdout=serial,vidconsole\0" \
> - "stderr=serial,vidconsole\0"
> -
> -#define CONFIG_ENV_SECT_SIZE 0x1000
> -#define CONFIG_ENV_OFFSET 0x00ff
> -
> -#endif /* __CONFIG_H */
> --
> 2.7.4
>
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[U-Boot] [PATCH 0/2] Convert fdtdec_setup_memory_banksize() to use livetree
Hi,
As requested while reviewing
452bc121027d ("fdt: fix fdtdec_setup_memory_banksize()")
heres a patch set converting fdtdec_setup_memory_banksize() to use livetree.
Thanks,
Jens
Jens Wiklander (2):
ofnode: add ofnode_by_prop_value()
fdt: fdtdec_setup_memory_banksize() use livetree
drivers/core/of_access.c | 27 +++
drivers/core/ofnode.c| 14
include/dm/of_access.h | 16 ++
include/dm/ofnode.h | 14
lib/fdtdec.c | 46 ++--
5 files changed, 92 insertions(+), 25 deletions(-)
--
2.17.1
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[U-Boot] [PATCH 2/2] fdt: fdtdec_setup_memory_banksize() use livetree
Converts fdtdec_setup_memory_banksize() to use ofnode functions instead.
Signed-off-by: Jens Wiklander
---
lib/fdtdec.c | 46 +-
1 file changed, 21 insertions(+), 25 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index a208589c48ae..fef2f88f9d10 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -1182,43 +1183,34 @@ int fdtdec_setup_mem_size_base(void)
#if defined(CONFIG_NR_DRAM_BANKS)
-static int get_next_memory_node(const void *blob, int startoffset)
+static ofnode get_next_memory_node(ofnode mem)
{
- int mem = -1;
-
do {
- mem = fdt_node_offset_by_prop_value(gd->fdt_blob, mem,
- "device_type", "memory", 7);
- } while (!fdtdec_get_is_enabled(blob, mem));
+ mem = ofnode_by_prop_value(mem, "device_type", "memory", 7);
+ } while (ofnode_valid(mem) && !ofnode_is_available(mem));
return mem;
}
int fdtdec_setup_memory_banksize(void)
{
- int bank, ret, mem, reg = 0;
- struct fdt_resource res;
+ int bank, reg = 0;
+ struct resource res;
+ ofnode mem;
- mem = get_next_memory_node(gd->fdt_blob, -1);
- if (mem < 0) {
- debug("%s: Missing /memory node\n", __func__);
- return -EINVAL;
- }
+ mem = get_next_memory_node(ofnode_null());
+ if (!ofnode_valid(mem))
+ goto missing_node;
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res);
- if (ret == -FDT_ERR_NOTFOUND) {
+ while (ofnode_read_resource(mem, reg++, &res)) {
reg = 0;
- mem = get_next_memory_node(gd->fdt_blob, mem);
- if (mem == -FDT_ERR_NOTFOUND)
- break;
-
- ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++,
&res);
- if (ret == -FDT_ERR_NOTFOUND)
- break;
- }
- if (ret != 0) {
- return -EINVAL;
+ mem = get_next_memory_node(mem);
+ if (!ofnode_valid(mem)) {
+ if (bank)
+ return 0;
+ goto missing_node;
+ }
}
gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
@@ -1232,6 +1224,10 @@ int fdtdec_setup_memory_banksize(void)
}
return 0;
+
+missing_node:
+ debug("%s: Missing /memory node\n", __func__);
+ return -EINVAL;
}
#endif
--
2.17.1
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[U-Boot] [PATCH 1/2] ofnode: add ofnode_by_prop_value()
Adds ofnode_by_prop_value() to search for nodes with a given property
and value, an ofnode version of fdt_node_offset_by_prop_value().
Signed-off-by: Jens Wiklander
---
drivers/core/of_access.c | 27 +++
drivers/core/ofnode.c| 14 ++
include/dm/of_access.h | 16
include/dm/ofnode.h | 14 ++
4 files changed, 71 insertions(+)
diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index 0729dfcdb3b8..14c020a687b7 100644
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c
@@ -376,6 +376,33 @@ struct device_node *of_find_compatible_node(struct
device_node *from,
return np;
}
+static int of_device_has_prop_value(const struct device_node *device,
+ const char *propname, const void *propval,
+ int proplen)
+{
+ struct property *prop = of_find_property(device, propname, NULL);
+
+ if (!prop || !prop->value || prop->length != proplen)
+ return 0;
+ return !memcmp(prop->value, propval, proplen);
+}
+
+struct device_node *of_find_node_by_prop_value(struct device_node *from,
+ const char *propname,
+ const void *propval, int proplen)
+{
+ struct device_node *np;
+
+ for_each_of_allnodes_from(from, np) {
+ if (of_device_has_prop_value(np, propname, propval, proplen) &&
+ of_node_get(np))
+ break;
+ }
+ of_node_put(from);
+
+ return np;
+}
+
struct device_node *of_find_node_by_phandle(phandle handle)
{
struct device_node *np;
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 0cfb0fbabb00..a7e192772324 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -777,3 +777,17 @@ ofnode ofnode_by_compatible(ofnode from, const char
*compat)
gd->fdt_blob, ofnode_to_offset(from), compat));
}
}
+
+ofnode ofnode_by_prop_value(ofnode from, const char *propname,
+ const void *propval, int proplen)
+{
+ if (of_live_active()) {
+ return np_to_ofnode(of_find_node_by_prop_value(
+ (struct device_node *)ofnode_to_np(from), propname,
+ propval, proplen));
+ } else {
+ return offset_to_ofnode(fdt_node_offset_by_prop_value(
+ gd->fdt_blob, ofnode_to_offset(from),
+ propname, propval, proplen));
+ }
+}
diff --git a/include/dm/of_access.h b/include/dm/of_access.h
index dd1abb8e97b4..5ed1a0cdb427 100644
--- a/include/dm/of_access.h
+++ b/include/dm/of_access.h
@@ -193,6 +193,22 @@ static inline struct device_node
*of_find_node_by_path(const char *path)
struct device_node *of_find_compatible_node(struct device_node *from,
const char *type, const char *compatible);
+/**
+ * of_find_node_by_prop_value() - find a node with a given property value
+ *
+ * Find a node based on a property value.
+ * @from: Node to start searching from or NULL. the node you pass will not be
+ * searched, only the next one will; typically, you pass what the previous
+ * call returned.
+ * @propname: property name to check
+ * @propval: property value to search for
+ * @proplen: length of the value in propval
+ * @return node pointer or NULL if not found
+ */
+struct device_node *of_find_node_by_prop_value(struct device_node *from,
+ const char *propname,
+ const void *propval,
+ int proplen);
/**
* of_find_node_by_phandle() - Find a node given a phandle
*
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index ab36b74c4ca4..c06d77849c73 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -702,6 +702,20 @@ int ofnode_read_resource_byname(ofnode node, const char
*name,
*/
ofnode ofnode_by_compatible(ofnode from, const char *compat);
+/**
+ * ofnode_by_prop_value() - Find the next node with given property value
+ *
+ * Find the next node after @from that has a @propname with a value
+ * @propval and a length @proplen.
+ *
+ * @from: ofnode to start from (use ofnode_null() to start at the
+ * beginning) @propname: property name to check @propval: property value to
+ * search for @proplen: length of the value in propval @return ofnode
+ * found, or ofnode_null() if none
+ */
+ofnode ofnode_by_prop_value(ofnode from, const char *propname,
+ const void *propval, int proplen);
+
/**
* ofnode_for_each_subnode() - iterate over all subnodes of a parent
*
--
2.17.1
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Re: [U-Boot] [PATCH 1/6] arm: socfpga: fix SPL on gen5 after moving to DM serial
On 10.08.2018 14:41, Marek Vasut wrote:
On 08/10/2018 02:39 PM, Simon Goldschmidt wrote:
On 09.08.2018 23:42, Marek Vasut wrote:
On 08/09/2018 09:04 PM, Simon Goldschmidt wrote:
There were NULL pointers dereferenced because DM was used
too early without correct initialization:
- malloc_simple returned NULL when called from preloader_console_init()
because gd->malloc_limit was 0
- uclass_add dereferenced gd->uclass_root members which were NULL
because
dm_init (or one of its relatives) has not been called.
All this is fixed by calling spl_early_init before calling
preloader_console_init.
This fixes commit 73172753f4f3 ("ARM: socfpga: Convert to DM serial")
Signed-off-by: Simon Goldschmidt
---
v2:
- Don't remove gd->malloc_base assignment at the end of board_init_f()
(moved to an extra patch)
arch/arm/mach-socfpga/spl_gen5.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-socfpga/spl_gen5.c
b/arch/arm/mach-socfpga/spl_gen5.c
index d6fe7d35af..9bdfaa3c1e 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -86,6 +86,7 @@ void board_init_f(ulong dummy)
const struct cm_config *cm_default_cfg = cm_get_default_config();
unsigned long sdram_size;
unsigned long reg;
+ int ret;
/*
* First C code to run. Clear fake OCRAM ECC first as SBE
@@ -152,6 +153,12 @@ void board_init_f(ulong dummy)
/* unfreeze / thaw all IO banks */
sys_mgr_frzctrl_thaw_req();
+ ret = spl_early_init();
Uh, but isn't this called from common/spl/spl.c ? I suspect the SoCFPGA
SPL is a bit weird.
Ehrm, I copied this from spl_s10.c, but other boards seem to do this,
too. Honestly, I don't know how any SPL can use DM serial without this
being called. Maybe other SPLs initialize the serial port later (not in
board_init_f).
I mean, spl_early_init() is called in common/spl/spl.c , which is common
code. Maybe the socfpga SPL is structured in a really weird way (I think
it is).
Not exactly: common/spl/spl.c calls spl_common_init(), just like
spl_early_init() does. Given the names, I think spl_early_init() is
meant to be called early, e.g. from board_init_f() ;-)
Oh, I just saw spl_common_init() emits a debug print "spl_early_init()",
so that might have tricked you...?
common/spl/spl.c calls spl_init(), which also calls the part that
spl_early_init() calls.
I can only take other SPLs as reference and from reading all the code, I
think this should be good.
Right
So is this change OK for v2018.09 once I fix the dts thing? Given that
v2018.07 is broken for socfpga gen5, it would be good to merge it
before. I can prepare a v3 of the series with only minimal changes in
the socfpga files and resend the rest as detached patches.
Simon
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
/* enable console uart printing */
preloader_console_init();
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Re: [U-Boot] [PATCH] arm: socfpga: make socfpga_socrates_defconfig boot from QSPI
On 09.08.2018 23:57, Marek Vasut wrote: On 08/09/2018 09:17 PM, Simon Goldschmidt wrote: [..] BTW, the DIP switches even allow the SoCrates to boot from fpga, which is what I'm currently working on. In this case, it seems like we need a separate config at least, but the dts can still be the same. Presumably because the SPL needs different link address ? The linker address of course needs to be changed. Preventing the cpu accessing the FPGA OnChip RAM was a bit more tricky to debug, but it seems I have it working now. I guess we need a Kconfig option to enable the bridge reset changes and select the correct link address. I'll prepare a patch for that. Should I base it on top of my gen5 fixes series? Additionally, to add the binary into an fpga, we need a hex file, maybe these can be automatically generated by mach-socfpga's Makefile when creating the SPL... Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] serial: omap: Introduce DM specific omap serial
Add driver model support for OMAP_SERIAL while reusing
the functions in ns16550.c
Signed-off-by: Lokesh Vutla
---
Based on the conclusion on the thread[1], added a separate driver for
omap uart.
[1] https://patchwork.ozlabs.org/patch/944756/
drivers/serial/Kconfig | 9 +++
drivers/serial/Makefile | 1 +
drivers/serial/ns16550.c | 42
drivers/serial/serial_omap.c | 121 +++
4 files changed, 131 insertions(+), 42 deletions(-)
create mode 100644 drivers/serial/serial_omap.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 766e5ced03..0aa2338135 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -625,6 +625,15 @@ config MSM_SERIAL
for example APQ8016 and MSM8916.
Single baudrate is supported in current implementation (115200).
+config OMAP_SERIAL
+ bool "Support for OMAP specific UART"
+ depends on DM_SERIAL
+ default y if (ARCH_OMAP2PLUS || SOC_DA8XX)
+ select SYS_NS16550
+ help
+ If you have an TI based SoC and want to use the on-chip serial
+ port, say Y to this option. If unsure say N.
+
config OWL_SERIAL
bool "Actions Semi OWL UART"
depends on DM_SERIAL && ARCH_OWL
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 9fa81d855d..03dc29ee2e 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
obj-$(CONFIG_OWL_SERIAL) += serial_owl.o
+obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 9c80090aa7..1858465ec9 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -279,42 +279,6 @@ DEBUG_UART_FUNCS
#endif
-#ifdef CONFIG_DEBUG_UART_OMAP
-
-#include
-
-static inline void _debug_uart_init(void)
-{
- struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
- int baud_divisor;
-
- baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
- CONFIG_BAUDRATE);
- serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
- serial_dout(&com_port->mdr1, 0x7);
- serial_dout(&com_port->mcr, UART_MCRVAL);
- serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
-
- serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
- serial_dout(&com_port->dll, baud_divisor & 0xff);
- serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
- serial_dout(&com_port->lcr, UART_LCRVAL);
- serial_dout(&com_port->mdr1, 0x0);
-}
-
-static inline void _debug_uart_putc(int ch)
-{
- struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
-
- while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
- ;
- serial_dout(&com_port->thr, ch);
-}
-
-DEBUG_UART_FUNCS
-
-#endif
-
#ifdef CONFIG_DM_SERIAL
static int ns16550_serial_putc(struct udevice *dev, const char ch)
{
@@ -489,12 +453,6 @@ static const struct udevice_id ns16550_serial_ids[] = {
{ .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 },
{ .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 },
{ .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
- { .compatible = "ti,omap2-uart",.data = PORT_NS16550 },
- { .compatible = "ti,omap3-uart",.data = PORT_NS16550 },
- { .compatible = "ti,omap4-uart",.data = PORT_NS16550 },
- { .compatible = "ti,am3352-uart", .data = PORT_NS16550 },
- { .compatible = "ti,am4372-uart", .data = PORT_NS16550 },
- { .compatible = "ti,dra742-uart", .data = PORT_NS16550 },
{}
};
#endif /* OF_CONTROL && !OF_PLATDATA */
diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
new file mode 100644
index 00..5d408deda9
--- /dev/null
+++ b/drivers/serial/serial_omap.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments' OMAP serial driver
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#ifdef CONFIG_DEBUG_UART_OMAP
+
+#include
+
+static inline void _debug_uart_init(void)
+{
+ struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
+ int baud_divisor;
+
+ baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
+ CONFIG_BAUDRATE);
+ serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
+ serial_dout(&com_port->mdr1, 0x7);
+ serial_dout(&com_port->mcr, UART_MCRVAL);
+ serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
+
+ serial_dout(&com_port-
Re: [U-Boot] [PATCH 1/6] arm: socfpga: fix SPL on gen5 after moving to DM serial
On 08/10/2018 02:55 PM, Simon Goldschmidt wrote:
> On 10.08.2018 14:41, Marek Vasut wrote:
>> On 08/10/2018 02:39 PM, Simon Goldschmidt wrote:
>>> On 09.08.2018 23:42, Marek Vasut wrote:
On 08/09/2018 09:04 PM, Simon Goldschmidt wrote:
> There were NULL pointers dereferenced because DM was used
> too early without correct initialization:
> - malloc_simple returned NULL when called from
> preloader_console_init()
> because gd->malloc_limit was 0
> - uclass_add dereferenced gd->uclass_root members which were NULL
> because
> dm_init (or one of its relatives) has not been called.
>
> All this is fixed by calling spl_early_init before calling
> preloader_console_init.
>
> This fixes commit 73172753f4f3 ("ARM: socfpga: Convert to DM serial")
>
> Signed-off-by: Simon Goldschmidt
> ---
> v2:
> - Don't remove gd->malloc_base assignment at the end of board_init_f()
> (moved to an extra patch)
>
> arch/arm/mach-socfpga/spl_gen5.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/spl_gen5.c
> b/arch/arm/mach-socfpga/spl_gen5.c
> index d6fe7d35af..9bdfaa3c1e 100644
> --- a/arch/arm/mach-socfpga/spl_gen5.c
> +++ b/arch/arm/mach-socfpga/spl_gen5.c
> @@ -86,6 +86,7 @@ void board_init_f(ulong dummy)
> const struct cm_config *cm_default_cfg =
> cm_get_default_config();
> unsigned long sdram_size;
> unsigned long reg;
> + int ret;
> /*
> * First C code to run. Clear fake OCRAM ECC first as SBE
> @@ -152,6 +153,12 @@ void board_init_f(ulong dummy)
> /* unfreeze / thaw all IO banks */
> sys_mgr_frzctrl_thaw_req();
> + ret = spl_early_init();
Uh, but isn't this called from common/spl/spl.c ? I suspect the SoCFPGA
SPL is a bit weird.
>>> Ehrm, I copied this from spl_s10.c, but other boards seem to do this,
>>> too. Honestly, I don't know how any SPL can use DM serial without this
>>> being called. Maybe other SPLs initialize the serial port later (not in
>>> board_init_f).
>> I mean, spl_early_init() is called in common/spl/spl.c , which is common
>> code. Maybe the socfpga SPL is structured in a really weird way (I think
>> it is).
>
> Not exactly: common/spl/spl.c calls spl_common_init(), just like
> spl_early_init() does. Given the names, I think spl_early_init() is
> meant to be called early, e.g. from board_init_f() ;-)
>
> Oh, I just saw spl_common_init() emits a debug print "spl_early_init()",
> so that might have tricked you...?
Ah, yes, I think so.
>>> common/spl/spl.c calls spl_init(), which also calls the part that
>>> spl_early_init() calls.
>>>
>>> I can only take other SPLs as reference and from reading all the code, I
>>> think this should be good.
>> Right
>
> So is this change OK for v2018.09 once I fix the dts thing? Given that
> v2018.07 is broken for socfpga gen5, it would be good to merge it
> before. I can prepare a v3 of the series with only minimal changes in
> the socfpga files and resend the rest as detached patches.
Looks good, yes.
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] serial: omap: Introduce DM specific omap serial
On Fri, Aug 10, 2018 at 06:36:20PM +0530, Lokesh Vutla wrote:
> Add driver model support for OMAP_SERIAL while reusing
> the functions in ns16550.c
>
> Signed-off-by: Lokesh Vutla
> ---
>
> Based on the conclusion on the thread[1], added a separate driver for
> omap uart.
>
> [1] https://patchwork.ozlabs.org/patch/944756/
>
> drivers/serial/Kconfig | 9 +++
> drivers/serial/Makefile | 1 +
> drivers/serial/ns16550.c | 42
> drivers/serial/serial_omap.c | 121 +++
> 4 files changed, 131 insertions(+), 42 deletions(-)
> create mode 100644 drivers/serial/serial_omap.c
For the record, I don't like this, but I'm not naking it, and I guess
this is what we'll need moving forward. FWIW, the alternative (patching
the dtsi files in the kernel) looks like:
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 9cd62bc2ca35..dab6bc9607bb 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -346,6 +346,7 @@
ti,hwmods = "uart1";
clock-frequency = <4800>;
reg = <0x44e09000 0x2000>;
+ reg-shift = <2>;
interrupts = <72>;
status = "disabled";
dmas = <&edma 26 0>, <&edma 27 0>;
@@ -357,6 +358,7 @@
ti,hwmods = "uart2";
clock-frequency = <4800>;
reg = <0x48022000 0x2000>;
+ reg-shift = <2>;
interrupts = <73>;
status = "disabled";
dmas = <&edma 28 0>, <&edma 29 0>;
@@ -368,6 +370,7 @@
ti,hwmods = "uart3";
clock-frequency = <4800>;
reg = <0x48024000 0x2000>;
+ reg-shift = <2>;
interrupts = <74>;
status = "disabled";
dmas = <&edma 30 0>, <&edma 31 0>;
@@ -379,6 +382,7 @@
ti,hwmods = "uart4";
clock-frequency = <4800>;
reg = <0x481a6000 0x2000>;
+ reg-shift = <2>;
interrupts = <44>;
status = "disabled";
};
@@ -388,6 +392,7 @@
ti,hwmods = "uart5";
clock-frequency = <4800>;
reg = <0x481a8000 0x2000>;
+ reg-shift = <2>;
interrupts = <45>;
status = "disabled";
};
@@ -397,6 +402,7 @@
ti,hwmods = "uart6";
clock-frequency = <4800>;
reg = <0x481aa000 0x2000>;
+ reg-shift = <2>;
interrupts = <46>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index ca294914bbb1..1eceeba076d8 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -56,6 +56,7 @@
ti,hwmods = "uart4";
status = "disabled";
reg = <0x4809e000 0x400>;
+ reg-shift = <2>;
interrupts = <84>;
dmas = <&sdma 55 &sdma 54>;
dma-names = "tx", "rx";
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index f0cbd86312dc..0f0f203a0fdd 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -300,6 +300,7 @@
uart0: serial@44e09000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x44e09000 0x2000>;
+ reg-shift = <2>;
interrupts = ;
ti,hwmods = "uart1";
};
@@ -307,6 +308,7 @@
uart1: serial@48022000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x48022000 0x2000>;
+ reg-shift = <2>;
interrupts = ;
ti,hwmods = "uart2";
status = "disabled";
@@ -315,6 +317,7 @@
uart2: serial@48024000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x48024000 0x2000>;
+ reg-shift = <2>;
interrupts = ;
ti,hwmods = "uart3";
status = "disabled";
@@ -323,6 +326,7 @@
uart3: serial@481a6000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x481a6000 0x2000>;
+
Re: [U-Boot] [PATCH] spi: davinci: Full dm conversion
On Wed, Aug 8, 2018 at 6:47 PM, Adam Ford wrote:
> On Tue, Aug 7, 2018 at 1:29 AM Jagan Teki wrote:
>>
>> davinci_spi now support dt along with platform data,
>> respective boards need to switch into dm for the same.
>>
>> Cc: Adam Ford
>> Cc: Vitaly Andrianov
>> Cc: Stefano Babic
>> Cc: Peter Howard
>> Cc: Tom Rini
>> Signed-off-by: Jagan Teki
>> ---
>> drivers/spi/Kconfig| 12 +-
>> drivers/spi/davinci_spi.c | 289 +++--
>> include/dm/platform_data/spi_davinci.h | 15 ++
>> 3 files changed, 97 insertions(+), 219 deletions(-)
>> create mode 100644 include/dm/platform_data/spi_davinci.h
>>
>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>> index d046e919b4..18ebff0231 100644
>> --- a/drivers/spi/Kconfig
>> +++ b/drivers/spi/Kconfig
>> @@ -80,6 +80,12 @@ config CADENCE_QSPI
>> used to access the SPI NOR flash on platforms embedding this
>> Cadence IP core.
>>
>> +config DAVINCI_SPI
>> + bool "Davinci & Keystone SPI driver"
>> + depends on ARCH_DAVINCI || ARCH_KEYSTONE
>> + help
>> + Enable the Davinci SPI driver
>> +
>> config DESIGNWARE_SPI
>> bool "Designware SPI driver"
>> help
>> @@ -281,12 +287,6 @@ config FSL_QSPI
>> used to access the SPI NOR flash on platforms embedding this
>> Freescale IP core.
>>
>> -config DAVINCI_SPI
>> - bool "Davinci & Keystone SPI driver"
>> - depends on ARCH_DAVINCI || ARCH_KEYSTONE
>> - help
>> - Enable the Davinci SPI driver
>> -
>> config SH_SPI
>> bool "SuperH SPI driver"
>> help
>> diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
>> index a822858323..5007e6c618 100644
>> --- a/drivers/spi/davinci_spi.c
>> +++ b/drivers/spi/davinci_spi.c
>> @@ -14,6 +14,7 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> /* SPIGCR0 */
>> #define SPIGCR0_SPIENA_MASK0x1
>> @@ -118,9 +119,6 @@ struct davinci_spi_regs {
>>
>> /* davinci spi slave */
>> struct davinci_spi_slave {
>> -#ifndef CONFIG_DM_SPI
>> - struct spi_slave slave;
>> -#endif
>> struct davinci_spi_regs *regs;
>> unsigned int freq; /* current SPI bus frequency */
>> unsigned int mode; /* current SPI mode used */
>> @@ -240,11 +238,43 @@ static int davinci_spi_read_write(struct
>> davinci_spi_slave *ds, unsigned
>> return 0;
>> }
>>
>> +static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
>> +{
>> + struct davinci_spi_slave *ds = dev_get_priv(bus);
>>
>> -static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
>> + debug("%s speed %u\n", __func__, max_hz);
>> + if (max_hz > CONFIG_SYS_SPI_CLK / 2)
>> + return -EINVAL;
>> +
>> + ds->freq = max_hz;
>> +
>> + return 0;
>> +}
>> +
>> +static int davinci_spi_set_mode(struct udevice *bus, uint mode)
>> +{
>> + struct davinci_spi_slave *ds = dev_get_priv(bus);
>> +
>> + debug("%s mode %u\n", __func__, mode);
>> + ds->mode = mode;
>> +
>> + return 0;
>> +}
>> +
>> +static int davinci_spi_claim_bus(struct udevice *dev)
>> {
>> + struct dm_spi_slave_platdata *slave_plat =
>> + dev_get_parent_platdata(dev);
>> + struct udevice *bus = dev->parent;
>> + struct davinci_spi_slave *ds = dev_get_priv(bus);
>> unsigned int mode = 0, scalar;
>>
>> + if (slave_plat->cs >= ds->num_cs) {
>> + printf("Invalid SPI chipselect\n");
>> + return -EINVAL;
>> + }
>> + ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
>> +
>> /* Enable the SPI hardware */
>> writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
>> udelay(1000);
>> @@ -254,7 +284,7 @@ static int __davinci_spi_claim_bus(struct
>> davinci_spi_slave *ds, int cs)
>> writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
>>
>> /* CS, CLK, SIMO and SOMI are functional pins */
>> - writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
>> + writel(((1 << slave_plat->cs) | SPIPC0_CLKFUN_MASK |
>> SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
>>
>> /* setup format */
>> @@ -292,20 +322,32 @@ static int __davinci_spi_claim_bus(struct
>> davinci_spi_slave *ds, int cs)
>> return 0;
>> }
>>
>> -static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
>> +static int davinci_spi_release_bus(struct udevice *dev)
>> {
>> + struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
>> +
>> /* Disable the SPI hardware */
>> writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
>>
>> return 0;
>> }
>>
>> -static int __davinci_spi_xfer(struct davinci_spi_slave *ds,
>> - unsigned int bitlen, const void *dout, void *din,
>> - unsigned long flags)
>> +static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen,
>> + cons
Re: [U-Boot] [PATCH] spi: davinci: Full dm conversion
On Fri, Aug 10, 2018 at 8:38 AM Jagan Teki wrote:
>
> On Wed, Aug 8, 2018 at 6:47 PM, Adam Ford wrote:
> > On Tue, Aug 7, 2018 at 1:29 AM Jagan Teki
> > wrote:
> >>
> >> davinci_spi now support dt along with platform data,
> >> respective boards need to switch into dm for the same.
> >>
> >> Cc: Adam Ford
> >> Cc: Vitaly Andrianov
> >> Cc: Stefano Babic
> >> Cc: Peter Howard
> >> Cc: Tom Rini
> >> Signed-off-by: Jagan Teki
> >> ---
> >> drivers/spi/Kconfig| 12 +-
> >> drivers/spi/davinci_spi.c | 289 +++--
> >> include/dm/platform_data/spi_davinci.h | 15 ++
> >> 3 files changed, 97 insertions(+), 219 deletions(-)
> >> create mode 100644 include/dm/platform_data/spi_davinci.h
> >>
> >> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> >> index d046e919b4..18ebff0231 100644
> >> --- a/drivers/spi/Kconfig
> >> +++ b/drivers/spi/Kconfig
> >> @@ -80,6 +80,12 @@ config CADENCE_QSPI
> >> used to access the SPI NOR flash on platforms embedding this
> >> Cadence IP core.
> >>
> >> +config DAVINCI_SPI
> >> + bool "Davinci & Keystone SPI driver"
> >> + depends on ARCH_DAVINCI || ARCH_KEYSTONE
> >> + help
> >> + Enable the Davinci SPI driver
> >> +
> >> config DESIGNWARE_SPI
> >> bool "Designware SPI driver"
> >> help
> >> @@ -281,12 +287,6 @@ config FSL_QSPI
> >> used to access the SPI NOR flash on platforms embedding this
> >> Freescale IP core.
> >>
> >> -config DAVINCI_SPI
> >> - bool "Davinci & Keystone SPI driver"
> >> - depends on ARCH_DAVINCI || ARCH_KEYSTONE
> >> - help
> >> - Enable the Davinci SPI driver
> >> -
> >> config SH_SPI
> >> bool "SuperH SPI driver"
> >> help
> >> diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
> >> index a822858323..5007e6c618 100644
> >> --- a/drivers/spi/davinci_spi.c
> >> +++ b/drivers/spi/davinci_spi.c
> >> @@ -14,6 +14,7 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >>
> >> /* SPIGCR0 */
> >> #define SPIGCR0_SPIENA_MASK0x1
> >> @@ -118,9 +119,6 @@ struct davinci_spi_regs {
> >>
> >> /* davinci spi slave */
> >> struct davinci_spi_slave {
> >> -#ifndef CONFIG_DM_SPI
> >> - struct spi_slave slave;
> >> -#endif
> >> struct davinci_spi_regs *regs;
> >> unsigned int freq; /* current SPI bus frequency */
> >> unsigned int mode; /* current SPI mode used */
> >> @@ -240,11 +238,43 @@ static int davinci_spi_read_write(struct
> >> davinci_spi_slave *ds, unsigned
> >> return 0;
> >> }
> >>
> >> +static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
> >> +{
> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
> >>
> >> -static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
> >> + debug("%s speed %u\n", __func__, max_hz);
> >> + if (max_hz > CONFIG_SYS_SPI_CLK / 2)
> >> + return -EINVAL;
> >> +
> >> + ds->freq = max_hz;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int davinci_spi_set_mode(struct udevice *bus, uint mode)
> >> +{
> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
> >> +
> >> + debug("%s mode %u\n", __func__, mode);
> >> + ds->mode = mode;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int davinci_spi_claim_bus(struct udevice *dev)
> >> {
> >> + struct dm_spi_slave_platdata *slave_plat =
> >> + dev_get_parent_platdata(dev);
> >> + struct udevice *bus = dev->parent;
> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
> >> unsigned int mode = 0, scalar;
> >>
> >> + if (slave_plat->cs >= ds->num_cs) {
> >> + printf("Invalid SPI chipselect\n");
> >> + return -EINVAL;
> >> + }
> >> + ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
> >> +
> >> /* Enable the SPI hardware */
> >> writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
> >> udelay(1000);
> >> @@ -254,7 +284,7 @@ static int __davinci_spi_claim_bus(struct
> >> davinci_spi_slave *ds, int cs)
> >> writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
> >>
> >> /* CS, CLK, SIMO and SOMI are functional pins */
> >> - writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
> >> + writel(((1 << slave_plat->cs) | SPIPC0_CLKFUN_MASK |
> >> SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
> >>
> >> /* setup format */
> >> @@ -292,20 +322,32 @@ static int __davinci_spi_claim_bus(struct
> >> davinci_spi_slave *ds, int cs)
> >> return 0;
> >> }
> >>
> >> -static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
> >> +static int davinci_spi_release_bus(struct udevice *dev)
> >> {
> >> + struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
> >> +
> >> /* Disable the SPI hardware */
> >> writel(SPIGCR0_SPIRST_MASK
Re: [U-Boot] [PATCH] common: fdt: set the value of MEMORY_BANKS_MAX to 8
On Fri, Aug 10, 2018 at 2:54 PM Anand Moon wrote:
> set the value of MEMORY_BANKS_MAX to 8.
> Odroid-XU4 fails to boot with following message
>
> fdt_fixup_memory_banks: num banks 8 exceeds hardcoded limit 4.
> Recompile with higher MEMORY_BANKS_MAX?
> ERROR: arch-specific fdt fixup failed
> - must RESET the board to recover.
>
> Fixes: commit 2a1f4f1758b5 (Revert "fdt_support: Use CONFIG_NR_DRAM_BANKS
> if defined")
>
> CC: Ramon Fried
> CC: Simon Glass
> Signed-off-by: Anand Moon
> ---
> common/fdt_support.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/common/fdt_support.c b/common/fdt_support.c
> index 34d2bd59c4..ad87f31ab3 100644
> --- a/common/fdt_support.c
> +++ b/common/fdt_support.c
> @@ -409,7 +409,7 @@ static int fdt_pack_reg(const void *fdt, void *buf,
> u64 *address, u64 *size,
> return p - (char *)buf;
> }
>
> I think it's better to check if MEMORY_BANKS was defined and only if not
to define it to 4.
Then users can define MEMORY_BANKS at include/configs/h
Simon, what do you say ?
-#define MEMORY_BANKS_MAX 4
> +#define MEMORY_BANKS_MAX 8
> int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
> {
> int err, nodeoffset;
> --
> 2.17.1
>
>
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Re: [U-Boot] [PATCH] arm: socfpga: make socfpga_socrates_defconfig boot from QSPI
On 08/10/2018 02:56 PM, Simon Goldschmidt wrote: > On 09.08.2018 23:57, Marek Vasut wrote: >> On 08/09/2018 09:17 PM, Simon Goldschmidt wrote: >>> [..] >>> BTW, the DIP switches even allow the SoCrates to boot from fpga, which >>> is what I'm currently working on. In this case, it seems like we need >>> a separate config at least, but the dts can still be the same. >> Presumably because the SPL needs different link address ? > > The linker address of course needs to be changed. Preventing the cpu > accessing the FPGA OnChip RAM was a bit more tricky to debug, but it > seems I have it working now. > > I guess we need a Kconfig option to enable the bridge reset changes and > select the correct link address. I'll prepare a patch for that. Should I > base it on top of my gen5 fixes series? Arent you gonna repost that series anyway ? Just wrap it in I think. > Additionally, to add the binary into an fpga, we need a hex file, maybe > these can be automatically generated by mach-socfpga's Makefile when > creating the SPL... Don't we have a hex file target already ? Maybe you do want some socrates_fpga custom defconfig for this setup. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/1] avb2.0: add get_size_of_partition()
Implement get_size_of_partition() operation,
which is required by the latest upstream libavb [1].
[1] https://android.googlesource.com/platform/external/avb/+/android-p-preview-5
Signed-off-by: Igor Opaniuk
---
Changes for v3:
- reword commit message, added avblib repository link, that stick to specific
tag
- fix get_size_of_partition() function description.
Changes for v2:
- change the return code for the case when out_size_num_bytes is NULL
(s/AVB_IO_RESULT_ERROR_IO/AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE/g)
common/avb_verify.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 20e35ad..82ddebc 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -700,6 +700,37 @@ static AvbIOResult get_unique_guid_for_partition(AvbOps
*ops,
}
/**
+ * get_size_of_partition() - gets the size of a partition identified
+ * by a string name
+ *
+ * @ops: contains AVB ops handlers
+ * @partition: partition name (NUL-terminated UTF-8 string)
+ * @out_size_num_bytes: returns the value of a partition size
+ *
+ * @return:
+ * AVB_IO_RESULT_OK, on success (GUID found)
+ * AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE, out_size_num_bytes is NULL
+ * AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION, if partition was not found
+ */
+static AvbIOResult get_size_of_partition(AvbOps *ops,
+const char *partition,
+u64 *out_size_num_bytes)
+{
+ struct mmc_part *part;
+
+ if (!out_size_num_bytes)
+ return AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE;
+
+ part = get_partition(ops, partition);
+ if (!part)
+ return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+
+ *out_size_num_bytes = part->info.blksz * part->info.size;
+
+ return AVB_IO_RESULT_OK;
+}
+
+/**
*
* AVB2.0 AvbOps alloc/initialisation/free
*
@@ -722,7 +753,7 @@ AvbOps *avb_ops_alloc(int boot_device)
ops_data->ops.read_is_device_unlocked = read_is_device_unlocked;
ops_data->ops.get_unique_guid_for_partition =
get_unique_guid_for_partition;
-
+ ops_data->ops.get_size_of_partition = get_size_of_partition;
ops_data->mmc_dev = boot_device;
return &ops_data->ops;
--
2.7.4
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Re: [U-Boot] [PATCH v3 1/1] avb2.0: add get_size_of_partition()
On 08/10/2018 08:59 AM, Igor Opaniuk wrote:
> Implement get_size_of_partition() operation,
> which is required by the latest upstream libavb [1].
>
> [1]
> https://android.googlesource.com/platform/external/avb/+/android-p-preview-5
>
> Signed-off-by: Igor Opaniuk
Sam reviewed v1, not sure enough changed to drop his review tag, anyway
for me:
Acked-by: Andrew F. Davis
> ---
>
> Changes for v3:
> - reword commit message, added avblib repository link, that stick to specific
> tag
> - fix get_size_of_partition() function description.
>
> Changes for v2:
> - change the return code for the case when out_size_num_bytes is NULL
> (s/AVB_IO_RESULT_ERROR_IO/AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE/g)
>
> common/avb_verify.c | 33 -
> 1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/common/avb_verify.c b/common/avb_verify.c
> index 20e35ad..82ddebc 100644
> --- a/common/avb_verify.c
> +++ b/common/avb_verify.c
> @@ -700,6 +700,37 @@ static AvbIOResult get_unique_guid_for_partition(AvbOps
> *ops,
> }
>
> /**
> + * get_size_of_partition() - gets the size of a partition identified
> + * by a string name
> + *
> + * @ops: contains AVB ops handlers
> + * @partition: partition name (NUL-terminated UTF-8 string)
> + * @out_size_num_bytes: returns the value of a partition size
> + *
> + * @return:
> + * AVB_IO_RESULT_OK, on success (GUID found)
> + * AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE, out_size_num_bytes is NULL
> + * AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION, if partition was not found
> + */
> +static AvbIOResult get_size_of_partition(AvbOps *ops,
> + const char *partition,
> + u64 *out_size_num_bytes)
> +{
> + struct mmc_part *part;
> +
> + if (!out_size_num_bytes)
> + return AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE;
> +
> + part = get_partition(ops, partition);
> + if (!part)
> + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
> +
> + *out_size_num_bytes = part->info.blksz * part->info.size;
> +
> + return AVB_IO_RESULT_OK;
> +}
> +
> +/**
> *
>
> * AVB2.0 AvbOps alloc/initialisation/free
> *
>
> @@ -722,7 +753,7 @@ AvbOps *avb_ops_alloc(int boot_device)
> ops_data->ops.read_is_device_unlocked = read_is_device_unlocked;
> ops_data->ops.get_unique_guid_for_partition =
> get_unique_guid_for_partition;
> -
> + ops_data->ops.get_size_of_partition = get_size_of_partition;
> ops_data->mmc_dev = boot_device;
>
> return &ops_data->ops;
>
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Re: [U-Boot] [PATCH v3 1/1] avb2.0: add get_size_of_partition()
Sam,
Could you please double-check this patch and confirm that your tag can
be still applied?
Thanks!
On 10 August 2018 at 17:06, Andrew F. Davis wrote:
> On 08/10/2018 08:59 AM, Igor Opaniuk wrote:
>> Implement get_size_of_partition() operation,
>> which is required by the latest upstream libavb [1].
>>
>> [1]
>> https://android.googlesource.com/platform/external/avb/+/android-p-preview-5
>>
>> Signed-off-by: Igor Opaniuk
>
>
> Sam reviewed v1, not sure enough changed to drop his review tag, anyway
> for me:
>
> Acked-by: Andrew F. Davis
>
>> ---
>>
>> Changes for v3:
>> - reword commit message, added avblib repository link, that stick to specific
>> tag
>> - fix get_size_of_partition() function description.
>>
>> Changes for v2:
>> - change the return code for the case when out_size_num_bytes is NULL
>> (s/AVB_IO_RESULT_ERROR_IO/AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE/g)
>>
>> common/avb_verify.c | 33 -
>> 1 file changed, 32 insertions(+), 1 deletion(-)
>>
>> diff --git a/common/avb_verify.c b/common/avb_verify.c
>> index 20e35ad..82ddebc 100644
>> --- a/common/avb_verify.c
>> +++ b/common/avb_verify.c
>> @@ -700,6 +700,37 @@ static AvbIOResult get_unique_guid_for_partition(AvbOps
>> *ops,
>> }
>>
>> /**
>> + * get_size_of_partition() - gets the size of a partition identified
>> + * by a string name
>> + *
>> + * @ops: contains AVB ops handlers
>> + * @partition: partition name (NUL-terminated UTF-8 string)
>> + * @out_size_num_bytes: returns the value of a partition size
>> + *
>> + * @return:
>> + * AVB_IO_RESULT_OK, on success (GUID found)
>> + * AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE, out_size_num_bytes is NULL
>> + * AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION, if partition was not found
>> + */
>> +static AvbIOResult get_size_of_partition(AvbOps *ops,
>> + const char *partition,
>> + u64 *out_size_num_bytes)
>> +{
>> + struct mmc_part *part;
>> +
>> + if (!out_size_num_bytes)
>> + return AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE;
>> +
>> + part = get_partition(ops, partition);
>> + if (!part)
>> + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
>> +
>> + *out_size_num_bytes = part->info.blksz * part->info.size;
>> +
>> + return AVB_IO_RESULT_OK;
>> +}
>> +
>> +/**
>> *
>>
>> * AVB2.0 AvbOps alloc/initialisation/free
>> *
>>
>> @@ -722,7 +753,7 @@ AvbOps *avb_ops_alloc(int boot_device)
>> ops_data->ops.read_is_device_unlocked = read_is_device_unlocked;
>> ops_data->ops.get_unique_guid_for_partition =
>> get_unique_guid_for_partition;
>> -
>> + ops_data->ops.get_size_of_partition = get_size_of_partition;
>> ops_data->mmc_dev = boot_device;
>>
>> return &ops_data->ops;
>>
--
Regards,
Igor Opaniuk
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Re: [U-Boot] [PATCH V3 07/32] misc: add i.MX8 misc driver
Hi Peng, On Fri, 10 Aug 2018 02:30:09 + Peng Fan peng@nxp.com wrote: ... > > Thanks for working on this! I think we should rename this driver to imx-mu > > and > > unify it, so that it can be used on i.MX7 and i.MX6SX, if needed. > > > Thanks for reviewing the patcset. Communicating with SCU needs > dedicated mu designed for SCU, and the scfw requires all the 4 channels > being used. It will introduce too much complexity to develop a generic mu > driver support generic mu and scu mu. I would not do that. OK. ... > > > + gd->arch.scu_dev = dev; > > > > Can we avoid using the dev pointer in global data? > > I could not find a better solution to make other components could > easily refer the scu dev. Do you have any suggestions? No. I think we will have to stick with the scu_dev in global data, now I see that it is needed just after relocation and before initr_dm(), so we can't get it just after relocation via dm functions. > Do you have time to review the remaining patches in the patchset? I'm working on ENET and I2C/USB/LVDS support for i.MX8QXP MEK based on this patch series and will try to review remaining patches over the weekend. Thanks, Anatolij ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] serial: omap: Introduce DM specific omap serial
On Fri, Aug 10, 2018 at 8:07 AM Lokesh Vutla wrote:
>
> Add driver model support for OMAP_SERIAL while reusing
> the functions in ns16550.c
>
> Signed-off-by: Lokesh Vutla
> ---
>
> Based on the conclusion on the thread[1], added a separate driver for
> omap uart.
>
> [1] https://patchwork.ozlabs.org/patch/944756/
>
> drivers/serial/Kconfig | 9 +++
> drivers/serial/Makefile | 1 +
> drivers/serial/ns16550.c | 42
> drivers/serial/serial_omap.c | 121 +++
> 4 files changed, 131 insertions(+), 42 deletions(-)
> create mode 100644 drivers/serial/serial_omap.c
>
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 766e5ced03..0aa2338135 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -625,6 +625,15 @@ config MSM_SERIAL
> for example APQ8016 and MSM8916.
> Single baudrate is supported in current implementation (115200).
>
> +config OMAP_SERIAL
> + bool "Support for OMAP specific UART"
> + depends on DM_SERIAL
> + default y if (ARCH_OMAP2PLUS || SOC_DA8XX)
> + select SYS_NS16550
> + help
> + If you have an TI based SoC and want to use the on-chip serial
> + port, say Y to this option. If unsure say N.
> +
> config OWL_SERIAL
> bool "Actions Semi OWL UART"
> depends on DM_SERIAL && ARCH_OWL
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index 9fa81d855d..03dc29ee2e 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -65,6 +65,7 @@ obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
> obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
> obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
> obj-$(CONFIG_OWL_SERIAL) += serial_owl.o
> +obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
>
> ifndef CONFIG_SPL_BUILD
> obj-$(CONFIG_USB_TTY) += usbtty.o
> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> index 9c80090aa7..1858465ec9 100644
> --- a/drivers/serial/ns16550.c
> +++ b/drivers/serial/ns16550.c
> @@ -279,42 +279,6 @@ DEBUG_UART_FUNCS
>
> #endif
>
> -#ifdef CONFIG_DEBUG_UART_OMAP
> -
> -#include
> -
> -static inline void _debug_uart_init(void)
> -{
> - struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
> - int baud_divisor;
> -
> - baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
> - CONFIG_BAUDRATE);
> - serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
> - serial_dout(&com_port->mdr1, 0x7);
> - serial_dout(&com_port->mcr, UART_MCRVAL);
> - serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
> -
> - serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
> - serial_dout(&com_port->dll, baud_divisor & 0xff);
> - serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
> - serial_dout(&com_port->lcr, UART_LCRVAL);
> - serial_dout(&com_port->mdr1, 0x0);
> -}
> -
> -static inline void _debug_uart_putc(int ch)
> -{
> - struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
> -
> - while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
> - ;
> - serial_dout(&com_port->thr, ch);
> -}
> -
> -DEBUG_UART_FUNCS
> -
> -#endif
> -
> #ifdef CONFIG_DM_SERIAL
> static int ns16550_serial_putc(struct udevice *dev, const char ch)
> {
> @@ -489,12 +453,6 @@ static const struct udevice_id ns16550_serial_ids[] = {
> { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 },
> { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 },
> { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
> - { .compatible = "ti,omap2-uart",.data = PORT_NS16550 },
> - { .compatible = "ti,omap3-uart",.data = PORT_NS16550 },
> - { .compatible = "ti,omap4-uart",.data = PORT_NS16550 },
> - { .compatible = "ti,am3352-uart", .data = PORT_NS16550 },
> - { .compatible = "ti,am4372-uart", .data = PORT_NS16550 },
> - { .compatible = "ti,dra742-uart", .data = PORT_NS16550 },
> {}
> };
I am not trying to rock the boat, but I am wondering if it's necessary
to completely migrate the driver for OMAP. I was thinking about the
possibility of creating a structure which includes the PORT_NS16550 as
well as reg-shift and point .data entry to that new structure. This
way, .compatible = "ti,omapX-uart" would also bring with it the
'reg-shift' for all board using that driver compatible flag. For the
other boards that don't need it, it can default to something else.
It limits the number of different drivers that do the same thing, and
it allows the DTS and DTSI files to remain in sync with the kernel.
Just a thought.
adam
> #endif /* OF_CONTROL && !OF_PLATDATA */
> diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
> new file mode 100644
> index 00..5d408deda9
> -
Re: [U-Boot] [PATCH V3 08/32] misc: imx8: add scfw api impementation
On Mon, 6 Aug 2018 10:50:23 +0800
Peng Fan peng@nxp.com wrote:
> Add clk/misc/pad/pm/rm scfw api implementaion for different
> drivers to invoke. The low level code is using misc_call
> to invoke imx8_scu driver.
>
> Signed-off-by: Peng Fan
> Cc: Stefano Babic
> ---
> arch/arm/include/asm/arch-imx8/sci/sci.h | 31 +-
> drivers/misc/imx8/Makefile | 2 +-
> drivers/misc/imx8/clk.c | 93 ++
> drivers/misc/imx8/misc.c | 88 +
> drivers/misc/imx8/pad.c | 39 +
> drivers/misc/imx8/pm.c | 38 +
> drivers/misc/imx8/rm.c | 97
>
> 7 files changed, 386 insertions(+), 2 deletions(-)
> create mode 100644 drivers/misc/imx8/clk.c
> create mode 100644 drivers/misc/imx8/misc.c
> create mode 100644 drivers/misc/imx8/pad.c
> create mode 100644 drivers/misc/imx8/pm.c
> create mode 100644 drivers/misc/imx8/rm.c
What about adding a single file (scu-api.c ?) with all API functions?
> diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h
> b/arch/arm/include/asm/arch-imx8/sci/sci.h
> index b7280aee05..4704ba9699 100644
> --- a/arch/arm/include/asm/arch-imx8/sci/sci.h
> +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h
> @@ -46,7 +46,8 @@ static inline int sc_err_to_linux(sc_err_t err)
> ret = -EIO;
> break;
> default:
> - panic("Invalid sc_err_t value\n");
> + ret = 0;
> + break;
> }
Please move this to patch 4/32 that adds sci.h file.
--
Anatolij
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Re: [U-Boot] [PATCH v1] arm: at91: wdt: Convert watchdog driver to dm
On Thu, Jul 26, 2018 at 02:56:27PM -0700, Prasanthi Chellakumar wrote: > Convert the Watchdog driver for AT91SAM9x processors to support > the driver model and device tree > > Signed-off-by: Prasanthi Chellakumar > --- > arch/arm/mach-at91/include/mach/at91_wdt.h | 12 +++- > drivers/watchdog/Kconfig | 7 ++ > drivers/watchdog/Makefile | 2 +- > drivers/watchdog/at91sam9_wdt.c| 105 > + > 4 files changed, 95 insertions(+), 31 deletions(-) Thanks for doing the conversion. It's fine to rename the config option to match the rest of the WDT drivers but you need to update all of the existing users now too, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 3/4] configs: stm32mp15: Enable USB relative flags
Enable config USB relative flags in order to enable USB EHCI, DWC2 gadget, download and mass_storage support. Signed-off-by: Patrice Chotard --- configs/stm32mp15_basic_defconfig | 16 1 file changed, 16 insertions(+) diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index c72a440dff1d..e955a4279c33 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -23,6 +23,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y @@ -31,6 +33,8 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_DM_MMC=y CONFIG_STM32_SDMMC2=y +CONFIG_PHY=y +CONFIG_PHY_STM32_USBPHYC=y # CONFIG_PINCTRL_FULL is not set # CONFIG_SPL_PINCTRL_FULL is not set CONFIG_DM_PMIC=y @@ -42,3 +46,15 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_STM32_VREFBUF=y CONFIG_DM_REGULATOR_STPMU1=y CONFIG_STM32_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" +CONFIG_USB_GADGET_VENDOR_NUM=0x0483 +CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 0/4] Add USB EHCI and gadget support for STM32MP1
This series : - Adds DT nodes to add usb gadget support for stm32mp157-ev1 board - Adds DT nodes to add EHCI support for stm32mp157-ev1 board - Enables all USB relative flags needed for USB EHCI, DWC2 gadget and mass storage support - Update stm32mp1 board by populating board_usb_init() to initialize USB gadget driver Patrice Chotard (4): ARM: dts: stm32mp1: Add usb gadget support for stm32mp157c-ev1 board ARM: dts: stm32mp1: Add EHCI support for stm32mp157c-ev1 board configs: stm32mp15: Enable USB relative flags board: st: stm32mp1: Add usb gadget support arch/arm/dts/stm32mp157-pinctrl.dtsi | 6 ++ arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 5 + arch/arm/dts/stm32mp157c-ev1.dts | 15 +++ arch/arm/dts/stm32mp157c.dtsi| 36 +++ board/st/stm32mp1/stm32mp1.c | 168 +++ configs/stm32mp15_basic_defconfig| 16 +++ 6 files changed, 246 insertions(+) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 4/4] board: st: stm32mp1: Add usb gadget support
Enable USB gadget support using DWC2 driver
Populate board_usb_init() to initialize clocks,
phy, reset and data needed for DWC2 IP.
Signed-off-by: Patrice Chotard
---
board/st/stm32mp1/stm32mp1.c | 168 +++
1 file changed, 168 insertions(+)
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index cc39fa6df9c3..a36ea228c7f4 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -4,13 +4,181 @@
*/
#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
#include
+#include
+#include
+#include
/*
* Get a global data pointer
*/
DECLARE_GLOBAL_DATA_PTR;
+#define STM32MP_GUSBCFG 0x40002407
+
+#define STM32MP_GGPIO 0x38
+#define STM32MP_GGPIO_VBUS_SENSING BIT(21)
+
+static struct dwc2_plat_otg_data stm32mp_otg_data = {
+ .usb_gusbcfg = STM32MP_GUSBCFG,
+};
+
+static struct reset_ctl usbotg_reset;
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ struct fdtdec_phandle_args args;
+ struct udevice *dev;
+ const void *blob = gd->fdt_blob;
+ struct clk clk;
+ struct phy phy;
+ int node;
+ int phy_provider;
+ int ret;
+
+ /* find the usb otg node */
+ node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
+ if (node < 0) {
+ debug("Not found usb_otg device\n");
+ return -ENODEV;
+ }
+
+ if (!fdtdec_get_is_enabled(blob, node)) {
+ debug("stm32 usbotg is disabled in the device tree\n");
+ return -ENODEV;
+ }
+
+ /* Enable clock */
+ ret = fdtdec_parse_phandle_with_args(blob, node, "clocks",
+"#clock-cells", 0, 0, &args);
+ if (ret) {
+ debug("usbotg has no clocks defined in the device tree\n");
+ return ret;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev);
+ if (ret)
+ return ret;
+
+ if (args.args_count != 1) {
+ debug("Can't find clock ID in the device tree\n");
+ return -ENODATA;
+ }
+
+ clk.dev = dev;
+ clk.id = args.args[0];
+
+ ret = clk_enable(&clk);
+ if (ret) {
+ debug("Failed to enable usbotg clock\n");
+ return ret;
+ }
+
+ /* Reset */
+ ret = fdtdec_parse_phandle_with_args(blob, node, "resets",
+"#reset-cells", 0, 0, &args);
+ if (ret) {
+ debug("usbotg has no resets defined in the device tree\n");
+ goto clk_err;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_RESET, args.node, &dev);
+ if (ret || args.args_count != 1)
+ goto clk_err;
+
+ usbotg_reset.dev = dev;
+ usbotg_reset.id = args.args[0];
+
+ reset_assert(&usbotg_reset);
+ udelay(2);
+ reset_deassert(&usbotg_reset);
+
+ /* Get USB PHY */
+ ret = fdtdec_parse_phandle_with_args(blob, node, "phys",
+"#phy-cells", 0, 0, &args);
+ if (!ret) {
+ phy_provider = fdt_parent_offset(blob, args.node);
+ ret = uclass_get_device_by_of_offset(UCLASS_PHY,
+phy_provider, &dev);
+ if (ret)
+ goto clk_err;
+
+ phy.dev = dev;
+ phy.id = fdtdec_get_uint(blob, args.node, "reg", -1);
+
+ ret = generic_phy_power_on(&phy);
+ if (ret) {
+ debug("unable to power on the phy\n");
+ goto clk_err;
+ }
+
+ ret = generic_phy_init(&phy);
+ if (ret) {
+ debug("failed to init usb phy\n");
+ goto phy_power_err;
+ }
+ }
+
+ /* Parse and store data needed for gadget */
+ stm32mp_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+ if (stm32mp_otg_data.regs_otg == FDT_ADDR_T_NONE) {
+ debug("usbotg: can't get base address\n");
+ ret = -ENODATA;
+ goto phy_init_err;
+ }
+
+ stm32mp_otg_data.rx_fifo_sz = fdtdec_get_int(blob, node,
+"g-rx-fifo-size", 0);
+ stm32mp_otg_data.np_tx_fifo_sz = fdtdec_get_int(blob, node,
+ "g-np-tx-fifo-size", 0);
+ stm32mp_otg_data.tx_fifo_sz = fdtdec_get_int(blob, node,
+"g-tx-fifo-size", 0);
+ /* Enable voltage level detector */
+ if (!(fdtdec_parse_phandle_with_args(blob, node, "usb33d-supply",
+NULL, 0, 0, &args))) {
+ if (!uclass_get_device_by_of_offset(UCLASS_REGULATOR,
+
[U-Boot] [PATCH v1 2/4] ARM: dts: stm32mp1: Add EHCI support for stm32mp157c-ev1 board
Add DT nodes to enable EHCI support
Signed-off-by: Patrice Chotard
---
arch/arm/dts/stm32mp157c-ev1.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index e2128af93fe5..902a42bee290 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -96,6 +96,13 @@
};
};
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ phy-names = "usb";
+ vbus-supply = <&vbus_sw>;
+ status = "okay";
+};
+
&usbotg_hs {
pinctrl-names = "default";
pinctrl-0 = <&usbotg_hs_pins_a>;
--
1.9.1
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[U-Boot] [PATCH v1 1/4] ARM: dts: stm32mp1: Add usb gadget support for stm32mp157c-ev1 board
Add DT nodes to enable DWC2 gadget support
Signed-off-by: Patrice Chotard
---
arch/arm/dts/stm32mp157-pinctrl.dtsi | 6 ++
arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 5 +
arch/arm/dts/stm32mp157c-ev1.dts | 8 +++
arch/arm/dts/stm32mp157c.dtsi| 36
4 files changed, 55 insertions(+)
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi
b/arch/arm/dts/stm32mp157-pinctrl.dtsi
index c69c397964af..85da5926551c 100644
--- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
@@ -321,6 +321,12 @@
bias-disable;
};
};
+
+ usbotg_hs_pins_a: usbotg_hs-0 {
+ pins {
+ pinmux = ; /* OTG_ID */
+ };
+ };
};
pinctrl_z: pin-controller-z@54004000 {
diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
index 2f4de3a066c0..30b173478c6c 100644
--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
@@ -25,6 +25,10 @@
regulator-always-on;
};
+&usbotg_hs {
+ g-tx-fifo-size = <576>;
+};
+
/* SPL part **/
&qspi {
u-boot,dm-spl;
@@ -60,3 +64,4 @@
&flash0 {
u-boot,dm-spl;
};
+
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index d6934f74e076..e2128af93fe5 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -96,6 +96,14 @@
};
};
+&usbotg_hs {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
&usbphyc {
status = "okay";
};
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index 8df9f09dc6c3..44190394e7af 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -106,6 +106,26 @@
};
};
+ pm_domain {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32mp157c-pd";
+
+ pd_core_ret: core-ret-power-domain@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ #power-domain-cells = <0>;
+ label = "CORE-RETENTION";
+
+ pd_core: core-power-domain@2 {
+ reg = <2>;
+ #power-domain-cells = <0>;
+ label = "CORE";
+ };
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -622,6 +642,22 @@
status = "disabled";
};
+ usbotg_hs: usb-otg@4900 {
+ compatible = "st,stm32mp1-hsotg", "snps,dwc2";
+ reg = <0x4900 0x1>;
+ clocks = <&rcc USBO_K>;
+ clock-names = "otg";
+ resets = <&rcc USBO_R>;
+ reset-names = "dwc2";
+ interrupts = ;
+ g-rx-fifo-size = <256>;
+ g-np-tx-fifo-size = <32>;
+ g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
+ dr_mode = "otg";
+ power-domains = <&pd_core>;
+ status = "disabled";
+ };
+
rcc: rcc@5000 {
compatible = "st,stm32mp1-rcc", "syscon";
reg = <0x5000 0x1000>;
--
1.9.1
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Re: [U-Boot] [PATCH] spi: davinci: Full dm conversion
On Fri, Aug 10, 2018 at 7:11 PM, Adam Ford wrote:
> On Fri, Aug 10, 2018 at 8:38 AM Jagan Teki wrote:
>>
>> On Wed, Aug 8, 2018 at 6:47 PM, Adam Ford wrote:
>> > On Tue, Aug 7, 2018 at 1:29 AM Jagan Teki
>> > wrote:
>> >>
>> >> davinci_spi now support dt along with platform data,
>> >> respective boards need to switch into dm for the same.
[snip]
>> >
>> > Looking at other drivers, I wonder if this should be
>> > +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
>> >
>> >
>> >> static int davinci_ofdata_to_platadata(struct udevice *bus)
>> >> {
>> >> - struct davinci_spi_slave *ds = dev_get_priv(bus);
>> >> - const void *blob = gd->fdt_blob;
>> >> - int node = dev_of_offset(bus);
>> >> + struct davinci_spi_platdata *plat = bus->platdata;
>> >> + fdt_addr_t addr;
>> >>
>> >> - ds->regs = devfdt_map_physmem(bus, sizeof(struct
>> >> davinci_spi_regs));
>> >> - if (!ds->regs) {
>> >> - printf("%s: could not map device address\n", __func__);
>> >> + addr = devfdt_get_addr(bus);
>> >> + if (addr == FDT_ADDR_T_NONE)
>> >> return -EINVAL;
>> >> - }
>> >> - ds->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
>> >> +
>> >> + plat->regs = (struct davinci_spi_regs *)addr;
>> >> + plat->num_cs = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
>> >> "num-cs", 4);
>> >>
>> >> return 0;
>> >> }
>> >>
>> >> -static const struct dm_spi_ops davinci_spi_ops = {
>> >> - .claim_bus = davinci_spi_claim_bus,
>> >> - .release_bus= davinci_spi_release_bus,
>> >> - .xfer = davinci_spi_xfer,
>> >> - .set_speed = davinci_spi_set_speed,
>> >> - .set_mode = davinci_spi_set_mode,
>> >> -};
>> >> -
>> >> static const struct udevice_id davinci_spi_ids[] = {
>> >> { .compatible = "ti,keystone-spi" },
>> >> { .compatible = "ti,dm6441-spi" },
>> >> { .compatible = "ti,da830-spi" },
>> >> { }
>> >> };
>> >> +#endif
>> >>
>> >> U_BOOT_DRIVER(davinci_spi) = {
>> >> .name = "davinci_spi",
>> >> .id = UCLASS_SPI,
>> >> +#if CONFIG_IS_ENABLED(OF_CONTROL)
>> >
>> > Like above, should this be:
>> > +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
>> >
>> > With limited SPL resources, I cannot build OF_CONTROL in SPL and
>> > disabling OF_CONTROL in SPL doesn't build either.
>> > With the modification, I can build with OF_PLATDATA enabled.
>> >
>> >> .of_match = davinci_spi_ids,
>> >> - .ops = &davinci_spi_ops,
>> >> .ofdata_to_platdata = davinci_ofdata_to_platadata,
>> >> - .priv_auto_alloc_size = sizeof(struct davinci_spi_slave),
>> >> +.platdata_auto_alloc_size = sizeof(struct davinci_spi_platdata),
>> >> +#endif
>> >> .probe = davinci_spi_probe,
>> >> + .ops = &davinci_spi_ops,
>> >> + .priv_auto_alloc_size = sizeof(struct davinci_spi_slave),
>> >> };
>> >> -#endif
>> >
>> >
>> > With the above changes, I can build U-Boot, but I cannot boot with
>> > DM_SPL enabled.
>>
>> For SPL have you initialize pladata some where in board code?
>
> I didn't do that yet, which is probably what part of the problem is.
> I hadn't gotten around to trying to figure out what the correct method
> is. Do you have an example I can follow?
Sample.
static const struct davinci_spi_platdata davinci_spi_data = {
.regs = (struct davinci_spi_regs *)BASE,
.num_cs = 4,
};
U_BOOT_DEVICE(davinci_spi) = {
"davinci_spi",
&davinci_spi_data,
};
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[U-Boot] [PATCH 2/3] dt: bcm6838: add pinctrl
Add pinctrl node and related syscon node for broadcom bcm6838 SoC.
Signed-off-by: Philippe Reynes
---
arch/mips/dts/brcm,bcm6838.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm6838.dtsi b/arch/mips/dts/brcm,bcm6838.dtsi
index d365d0f..f276a6a 100644
--- a/arch/mips/dts/brcm,bcm6838.dtsi
+++ b/arch/mips/dts/brcm,bcm6838.dtsi
@@ -55,6 +55,18 @@
u-boot,dm-pre-reloc;
};
+ gpio_test_port: syscon@14e00294 {
+ compatible = "syscon";
+ reg = <0x14e00294 0x1c>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "brcm,bcm6838-pinctrl";
+ regmap = <&gpio_test_port>;
+ pins-count = <74>;
+ functions-count = <8>;
+ };
+
uart0: serial@14e00500 {
compatible = "brcm,bcm6345-uart";
reg = <0x14e00500 0x18>;
--
2.7.4
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[U-Boot] [PATCH 3/3] bcm968380gerg: enable pinctrl
Signed-off-by: Philippe Reynes --- configs/bcm968380gerg_ram_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/bcm968380gerg_ram_defconfig b/configs/bcm968380gerg_ram_defconfig index 3354a5e..7c83d43 100644 --- a/configs/bcm968380gerg_ram_defconfig +++ b/configs/bcm968380gerg_ram_defconfig @@ -38,6 +38,7 @@ CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY=y CONFIG_BCM6368_USBH_PHY=y +CONFIG_PINCTRL=y CONFIG_POWER_DOMAIN=y CONFIG_BCM6328_POWER_DOMAIN=y CONFIG_DM_RESET=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/3] pinctrl: bcm6838: add pinctrl support
Add pinctrl support for broadcom bcm6838 SoC.
Signed-off-by: Philippe Reynes
---
.../pinctrl/bcm6838-pinctrl.txt| 35 +
drivers/pinctrl/broadcom/Kconfig | 8 ++
drivers/pinctrl/broadcom/Makefile | 1 +
drivers/pinctrl/broadcom/pinctrl-bcm6838.c | 159 +
4 files changed, 203 insertions(+)
create mode 100644 doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt
create mode 100644 drivers/pinctrl/broadcom/pinctrl-bcm6838.c
diff --git a/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt
b/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt
new file mode 100644
index 000..e13d4e7
--- /dev/null
+++ b/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt
@@ -0,0 +1,35 @@
+* broadcom bcm6838 pinctrl
+
+Required properties for the pinctrl driver:
+- compatible: "brcm,bcm6838-pinctrl"
+- regmap: specify the gpio test port syscon
+- pins-count: the number of pin
+- functions-count: the number of function
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+Example:
+
+ gpio_test_port: syscon@14e00294 {
+ compatible = "syscon";
+ reg = <0x14e00294 0x1c>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "brcm,bcm6838-pinctrl";
+ regmap = <&gpio_test_port>;
+ pins-count = <74>;
+ functions-count = <8>;
+
+ usb0: usb0 {
+ usb0_pwrflt {
+ pins = "69";
+ function = "1";
+ };
+ usb0_pwron {
+ pins = "70";
+ function = "1";
+ };
+ };
+ };
diff --git a/drivers/pinctrl/broadcom/Kconfig b/drivers/pinctrl/broadcom/Kconfig
index 4056782..b01b725 100644
--- a/drivers/pinctrl/broadcom/Kconfig
+++ b/drivers/pinctrl/broadcom/Kconfig
@@ -5,3 +5,11 @@ config PINCTRL_BCM283X
help
Support pin multiplexing and pin configuration control on
Broadcom's 283x family of SoCs.
+
+config PINCTRL_BCM6838
+ depends on ARCH_BMIPS && PINCTRL_FULL && OF_CONTROL
+ default y
+ bool "Broadcom 6838 family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Broadcom's 6838 family of SoCs.
diff --git a/drivers/pinctrl/broadcom/Makefile
b/drivers/pinctrl/broadcom/Makefile
index 99c7c23..f94f3ce 100644
--- a/drivers/pinctrl/broadcom/Makefile
+++ b/drivers/pinctrl/broadcom/Makefile
@@ -5,3 +5,4 @@
# https://spdx.org/licenses
obj-$(CONFIG_PINCTRL_BCM283X) += pinctrl-bcm283x.o
+obj-$(CONFIG_PINCTRL_BCM6838) += pinctrl-bcm6838.o
diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm6838.c
b/drivers/pinctrl/broadcom/pinctrl-bcm6838.c
new file mode 100644
index 000..2b8d849
--- /dev/null
+++ b/drivers/pinctrl/broadcom/pinctrl-bcm6838.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include
+#include
+#include
+#include
+#include
+
+#define BCM6838_CMD_LOAD_MUX0x21
+
+#define BCM6838_FUNC_OFFS 12
+#define BCM6838_FUNC_MASK (0x37 << BCM6838_FUNC_OFFS)
+#define BCM6838_PIN_OFFS 0
+#define BCM6838_PIN_MASK(0xfff << BCM6838_PIN_OFFS)
+
+#define BCM6838_MAX_PIN_NAME_LEN 8
+static char bcm6838_pin_name[BCM6838_MAX_PIN_NAME_LEN];
+
+#define BCM6838_MAX_FUNC_NAME_LEN8
+static char bcm6838_func_name[BCM6838_MAX_FUNC_NAME_LEN];
+
+struct bcm6838_test_port_hw {
+ unsigned long port_blk_data1;
+ unsigned long port_blk_data2;
+ unsigned long port_command;
+};
+
+static const struct bcm6838_test_port_hw bcm6838_hw = {
+ .port_blk_data1 = 0x10,
+ .port_blk_data2 = 0x14,
+ .port_command = 0x18
+};
+
+struct bcm6838_pinctrl_priv {
+ const struct bcm6838_test_port_hw *hw;
+ struct regmap *regmap;
+ u32 pins_count;
+ u32 functions_count;
+};
+
+int bcm6838_pinctrl_get_pins_count(struct udevice *dev)
+{
+ struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->pins_count;
+}
+
+const char *bcm6838_pinctrl_get_pin_name(struct udevice *dev,
+unsigned int selector)
+{
+ snprintf(bcm6838_pin_name, BCM6838_MAX_PIN_NAME_LEN, "%u", selector);
+ return bcm6838_pin_name;
+}
+
+int bcm6838_pinctrl_get_functions_count(struct udevice *dev)
+{
+ struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->functions_count;
+}
+
+const char *bcm6838_pinctrl_get_function_name(struct udevice *dev,
+
Re: [U-Boot] [PATCH] spi: davinci: Full dm conversion
On Fri, Aug 10, 2018 at 7:42 AM Jagan Teki wrote:
>
> On Fri, Aug 10, 2018 at 3:50 PM, Adam Ford wrote:
> > On Fri, Aug 10, 2018 at 12:14 AM Jagan Teki
> > wrote:
> >>
> >> On Wed, Aug 8, 2018 at 6:47 PM, Adam Ford wrote:
> >> > On Tue, Aug 7, 2018 at 1:29 AM Jagan Teki
> >> > wrote:
> >> >>
> >> >> davinci_spi now support dt along with platform data,
> >> >> respective boards need to switch into dm for the same.
> >> >>
> >> >> Cc: Adam Ford
> >> >> Cc: Vitaly Andrianov
> >> >> Cc: Stefano Babic
> >> >> Cc: Peter Howard
> >> >> Cc: Tom Rini
> >> >> Signed-off-by: Jagan Teki
> >> >> ---
> >> >> drivers/spi/Kconfig| 12 +-
> >> >> drivers/spi/davinci_spi.c | 289 +++--
> >> >> include/dm/platform_data/spi_davinci.h | 15 ++
> >> >> 3 files changed, 97 insertions(+), 219 deletions(-)
> >> >> create mode 100644 include/dm/platform_data/spi_davinci.h
> >> >>
> >> >> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> >> >> index d046e919b4..18ebff0231 100644
> >> >> --- a/drivers/spi/Kconfig
> >> >> +++ b/drivers/spi/Kconfig
> >> >> @@ -80,6 +80,12 @@ config CADENCE_QSPI
> >> >> used to access the SPI NOR flash on platforms embedding this
> >> >> Cadence IP core.
> >> >>
> >> >> +config DAVINCI_SPI
> >> >> + bool "Davinci & Keystone SPI driver"
> >> >> + depends on ARCH_DAVINCI || ARCH_KEYSTONE
> >> >> + help
> >> >> + Enable the Davinci SPI driver
> >> >> +
> >> >> config DESIGNWARE_SPI
> >> >> bool "Designware SPI driver"
> >> >> help
> >> >> @@ -281,12 +287,6 @@ config FSL_QSPI
> >> >> used to access the SPI NOR flash on platforms embedding this
> >> >> Freescale IP core.
> >> >>
> >> >> -config DAVINCI_SPI
> >> >> - bool "Davinci & Keystone SPI driver"
> >> >> - depends on ARCH_DAVINCI || ARCH_KEYSTONE
> >> >> - help
> >> >> - Enable the Davinci SPI driver
> >> >> -
> >> >> config SH_SPI
> >> >> bool "SuperH SPI driver"
> >> >> help
> >> >> diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
> >> >> index a822858323..5007e6c618 100644
> >> >> --- a/drivers/spi/davinci_spi.c
> >> >> +++ b/drivers/spi/davinci_spi.c
> >> >> @@ -14,6 +14,7 @@
> >> >> #include
> >> >> #include
> >> >> #include
> >> >> +#include
> >> >>
> >> >> /* SPIGCR0 */
> >> >> #define SPIGCR0_SPIENA_MASK0x1
> >> >> @@ -118,9 +119,6 @@ struct davinci_spi_regs {
> >> >>
> >> >> /* davinci spi slave */
> >> >> struct davinci_spi_slave {
> >> >> -#ifndef CONFIG_DM_SPI
> >> >> - struct spi_slave slave;
> >> >> -#endif
> >> >> struct davinci_spi_regs *regs;
> >> >> unsigned int freq; /* current SPI bus frequency */
> >> >> unsigned int mode; /* current SPI mode used */
> >> >> @@ -240,11 +238,43 @@ static int davinci_spi_read_write(struct
> >> >> davinci_spi_slave *ds, unsigned
> >> >> return 0;
> >> >> }
> >> >>
> >> >> +static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
> >> >> +{
> >> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
> >> >>
> >> >> -static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int
> >> >> cs)
> >> >> + debug("%s speed %u\n", __func__, max_hz);
> >> >> + if (max_hz > CONFIG_SYS_SPI_CLK / 2)
> >> >> + return -EINVAL;
> >> >> +
> >> >> + ds->freq = max_hz;
> >> >> +
> >> >> + return 0;
> >> >> +}
> >> >> +
> >> >> +static int davinci_spi_set_mode(struct udevice *bus, uint mode)
> >> >> +{
> >> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
> >> >> +
> >> >> + debug("%s mode %u\n", __func__, mode);
> >> >> + ds->mode = mode;
> >> >> +
> >> >> + return 0;
> >> >> +}
> >> >> +
> >> >> +static int davinci_spi_claim_bus(struct udevice *dev)
> >> >> {
> >> >> + struct dm_spi_slave_platdata *slave_plat =
> >> >> + dev_get_parent_platdata(dev);
> >> >> + struct udevice *bus = dev->parent;
> >> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
> >> >> unsigned int mode = 0, scalar;
> >> >>
> >> >> + if (slave_plat->cs >= ds->num_cs) {
> >> >> + printf("Invalid SPI chipselect\n");
> >> >> + return -EINVAL;
> >> >> + }
> >> >> + ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
> >> >> +
> >> >> /* Enable the SPI hardware */
> >> >> writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
> >> >> udelay(1000);
> >> >> @@ -254,7 +284,7 @@ static int __davinci_spi_claim_bus(struct
> >> >> davinci_spi_slave *ds, int cs)
> >> >> writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK,
> >> >> &ds->regs->gcr1);
> >> >>
> >> >> /* CS, CLK, SIMO and SOMI are functional pins */
> >> >> - writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
> >> >> + writel(((1 << slave_plat->cs) | SPIPC0_CLKFUN_MASK |
> >> >> SPIPC0_DOFUN_MASK | SPIPC
Re: [U-Boot] [PATCH] arm: socfpga: make socfpga_socrates_defconfig boot from QSPI
On 10.08.2018 15:15, Marek Vasut wrote: On 08/10/2018 02:56 PM, Simon Goldschmidt wrote: On 09.08.2018 23:57, Marek Vasut wrote: On 08/09/2018 09:17 PM, Simon Goldschmidt wrote: [..] BTW, the DIP switches even allow the SoCrates to boot from fpga, which is what I'm currently working on. In this case, it seems like we need a separate config at least, but the dts can still be the same. Presumably because the SPL needs different link address ? The linker address of course needs to be changed. Preventing the cpu accessing the FPGA OnChip RAM was a bit more tricky to debug, but it seems I have it working now. I guess we need a Kconfig option to enable the bridge reset changes and select the correct link address. I'll prepare a patch for that. Should I base it on top of my gen5 fixes series? Arent you gonna repost that series anyway ? Just wrap it in I think. OK then. After getting SPL to run from FPGA, I then had problems with running U-Boot from FPGA. I do that because U-Boot allows us to boot empty boards via network by only downloading an FPGA image (in combination with fallback boot from FPGA). Turns out the problem is the same: bridges into FPGA get disabled. Now I can deduplicate the code, but is this the right thing to do at all? Can't we expect for the SPL to have run an correctly initialize the low level hardware? On the other hand, it's a bit strange that after relocation, U-Boot tries to access pre-relocation memory anyway (gd->env_addr points to the fpga bridge). Maybe a better fix would be to relocate that pointer? In its original port, Altera has put all data into SRAM instead of fpga's OCRAM, so while code wouldn't work, data access to pre-relocation pointers would still work after the bridges got disabled... Which option would you prefer? Additionally, to add the binary into an fpga, we need a hex file, maybe these can be automatically generated by mach-socfpga's Makefile when creating the SPL... Don't we have a hex file target already ? Maybe you do want some socrates_fpga custom defconfig for this setup. Never stumbled accross that one, yet. Let me check. Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: socfpga: make socfpga_socrates_defconfig boot from QSPI
On 08/10/2018 10:11 PM, Simon Goldschmidt wrote: > On 10.08.2018 15:15, Marek Vasut wrote: >> On 08/10/2018 02:56 PM, Simon Goldschmidt wrote: >>> On 09.08.2018 23:57, Marek Vasut wrote: On 08/09/2018 09:17 PM, Simon Goldschmidt wrote: > [..] > BTW, the DIP switches even allow the SoCrates to boot from fpga, which > is what I'm currently working on. In this case, it seems like we need > a separate config at least, but the dts can still be the same. Presumably because the SPL needs different link address ? >>> The linker address of course needs to be changed. Preventing the cpu >>> accessing the FPGA OnChip RAM was a bit more tricky to debug, but it >>> seems I have it working now. >>> >>> I guess we need a Kconfig option to enable the bridge reset changes and >>> select the correct link address. I'll prepare a patch for that. Should I >>> base it on top of my gen5 fixes series? >> Arent you gonna repost that series anyway ? Just wrap it in I think. > > OK then. > > After getting SPL to run from FPGA, I then had problems with running > U-Boot from FPGA. I do that because U-Boot allows us to boot empty > boards via network by only downloading an FPGA image (in combination > with fallback boot from FPGA). You can boot from network in SPL too. > Turns out the problem is the same: bridges into FPGA get disabled. Now I > can deduplicate the code, but is this the right thing to do at all? > Can't we expect for the SPL to have run an correctly initialize the low > level hardware? Deduplication is always good. I don't quite understand this question though. > On the other hand, it's a bit strange that after relocation, U-Boot > tries to access pre-relocation memory anyway (gd->env_addr points to the > fpga bridge). Maybe a better fix would be to relocate that pointer? In > its original port, Altera has put all data into SRAM instead of fpga's > OCRAM, so while code wouldn't work, data access to pre-relocation > pointers would still work after the bridges got disabled... > > Which option would you prefer? I wonder why the in-ram env isn't relocated. But do you really need any of that ? See above about using TFTP in SPL . >>> Additionally, to add the binary into an fpga, we need a hex file, maybe >>> these can be automatically generated by mach-socfpga's Makefile when >>> creating the SPL... >> Don't we have a hex file target already ? Maybe you do want some >> socrates_fpga custom defconfig for this setup. > > Never stumbled accross that one, yet. Let me check. > > > Simon > -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARM: da850evm: Enable USE_TINY_PRINTF
The SPL space is limited. In order to try to enable DM in SPL, we need more space. This reduces the size of SPL by ~2.7K before: textdata bss dec hex filename 207601216 80 220565628 spl/u-boot-spl after: textdata bss dec hex filename 179471216 80 192434b2b spl/u-boot-spl Signed-off-by: Adam Ford diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 4242728e6a..46d0644254 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -53,3 +53,4 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y # CONFIG_FAT_WRITE is not set +CONFIG_USE_TINY_PRINTF=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARM: da850evm: Enable SPL_SYS_MALLOC_SIMPLE
The SPL space is limited. In order to try to enable DM in SPL, we need more space. When combined wtih TINY_PRINTF, this reduces the size of SPL by 6.5k Original: textdata bss dec hex filename 207601216 80 220565628 spl/u-boot-spl Tiny Printf textdata bss dec hex filename 179471216 80 192434b2b spl/u-boot-spl Malloc Simple + Tiny Printf textdata bss dec hex filename 15187 176 28 153913c1f spl/u-boot-spl Signed-off-by: Adam Ford diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 46d0644254..24e02a7004 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -17,6 +17,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 40/53] spi: Add Allwinner A31 SPI driver
> Add Allwinner sun6i SPI driver for A31, H3/H5 an A64. > > Cc: Fahad Sadah > Signed-off-by: Jagan Teki > --- > drivers/spi/Kconfig | 6 + > drivers/spi/Makefile| 1 + > drivers/spi/sun6i_spi.c | 475 > 3 files changed, 482 insertions(+) > create mode 100644 drivers/spi/sun6i_spi.c Hi there, Sorry for my delay in responding to your previous email - my FTDI broke and I've just acquired a new one. u-boot-sunxi/clk on my Orange Pi R1 can find and read from the SPI NOR flash, and can find the USB ethernet adaptor :D Thanks for this! Tested-by: Fahad Sadah Regards, Fahad Sadah ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PULL] u-boot-usb/master
On Thu, Aug 09, 2018 at 09:29:58AM +0200, Marek Vasut wrote: > The following changes since commit b1aad8dbe28415695b290726199681ced969c118: > > zynqmp: Add avnet_ultra96_rev1_defconfig to the lits of boards > (2018-08-07 11:36:39 -0400) > > are available in the Git repository at: > > git://git.denx.de/u-boot-usb.git master > > for you to fetch changes up to 28a5c88043c80a38040abde957fbe1755b796912: > > dfu: Provide more verbose error message (2018-08-08 22:22:08 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/9] Support 4GB of memory on 32bit systems
On Thu, Jul 26, 2018 at 03:59:42PM +0200, Philipp Tomsich wrote: > Even on 32bit systems a full 4GB of DRAM may be installed and reported > by the DRAM controller. Whether these 4GB are larger available > depends on the size/configuration of address decoding windows and > architectural features. > > This increases the fields holding the RAM size to have at least 33bits > (i.e. we use a u64) and fixes the fallout from the change: some casts, > the usage of min() and a few printf formats have to be adjusted. > > > Philipp Tomsich (9): > dm: allow 4GB of DRAM on 32bit systems > rockchip: support 4GB DRAM on 32bit systems > common: include always > MIPS: use PRIx64 macros for printing ram size > rockchip: rk3368: change type of ram-size field for a > min()-calculation > ram: stm32mp1: use PRIx64 macros for printing ram size > board: keymile: add explicit cast to truncate the 64bit ram size field > board: cm_fx6: use PRIx64 macros for printing ram size > mpc85xx: add casts for ram size in min() calculation. > > arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 +- > arch/arm/mach-rockchip/sdram_common.c | 8 > arch/arm/mach-stm32mp/dram_init.c | 2 +- > arch/mips/mach-bmips/dram.c | 2 +- > arch/powerpc/cpu/mpc85xx/cpu.c| 6 -- > board/compulab/cm_fx6/cm_fx6.c| 3 ++- > board/keymile/km_arm/km_arm.c | 6 -- > drivers/ram/rockchip/dmc-rk3368.c | 2 +- > drivers/ram/stm32mp1/stm32mp1_ram.c | 2 +- > include/asm-generic/global_data.h | 2 +- > include/common.h | 1 + > include/ram.h | 9 - > 12 files changed, 29 insertions(+), 16 deletions(-) Please rework this on top of https://patchwork.ozlabs.org/user/todo/uboot/?series=59452 thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v4,1/5] stm32mp1: add gpio led support
On Fri, Jul 27, 2018 at 04:37:05PM +0200, Patrick Delaunay wrote: > This patch add the 4 LED available on the ED1 board and activated > gpio led driver. > > Reviewed-by: Simon Glass > Signed-off-by: Patrick Delaunay Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v4, 2/5] Revert "dm: led: auto probe() LEDs with "default-state""
On Fri, Jul 27, 2018 at 04:37:06PM +0200, Patrick Delaunay wrote: > This reverts commit bc882f5d5c7b4d6ed5e927bf838863af43c786e7. > because this patch adds the probe of LED driver during the > binding phasis. It is not allowed in driver model because > the drivers (clock, pincontrol) needed by the LED driver can > be also probed before the binding of all the device and > it is a source of problems. > > Signed-off-by: Patrick Delaunay Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v4, 4/5] stm32mp1: use new function led default state
On Fri, Jul 27, 2018 at 04:37:08PM +0200, Patrick Delaunay wrote: > Initialize the led with the default state defined in device tree. > > Reviewed-by: Simon Glass > > Signed-off-by: Patrick Delaunay Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/1] doc: add structure to Sphinx generated docs
On Sun, Jul 29, 2018 at 01:45:47PM +0200, Heinrich Schuchardt wrote: > Create separate html pages for linker lists, the serial subsystem, > and the EFI subsystem. > > Add a table of content. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] sata: fix sata_Probe return value check
On Fri, Jul 27, 2018 at 04:45:26PM -0700, Troy Kisky wrote: > sata_probe returns 1 for failure, so don't checkout for < 0 > > fixes: f19f1ecb6025 dm: sata: Support driver model with the 'sata' command > > Signed-off-by: Troy Kisky > Reviewed-by: Simon Glass > > diff --git a/cmd/sata.c b/cmd/sata.c > index cc12afb07e..4f0c6e0137 100644 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v4, 5/5] sandbox: led: use new function to configure default state
On Fri, Jul 27, 2018 at 04:37:09PM +0200, Patrick Delaunay wrote: > Initialize the led with the default state defined in device tree > in board_init and solve issue with test for led default state. > > Reviewed-by: Simon Glass > > > Signed-off-by: Patrick Delaunay Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 1/2] env: Don't show "Failed" error message
On Mon, Jul 30, 2018 at 07:19:26PM +0300, Sam Protsenko wrote: > "Failed" error message from env_load() only clutters the log with > unnecessary details, as we already have all needed warnings by that > time. Example: > > Loading Environment from FAT... MMC: no card present > ** Bad device mmc 0 ** > Failed (-5) > > Let's only print it in case when DEBUG is defined to keep log clear. > > Signed-off-by: Sam Protsenko Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 2/2] disk: part: Don't show redundant error message
On Mon, Jul 30, 2018 at 07:19:27PM +0300, Sam Protsenko wrote: > Underlying API should already print some meaningful error message, so > this one is just brings more noise. E.g. we can see log like this: > > MMC: no card present > ** Bad device mmc 0 ** > > Obviously, second error message is unwanted. Let's only print it in case > when DEBUG is defined to keep log short and clear. > > Signed-off-by: Sam Protsenko Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v4, 3/5] dm: led: move default state support in led uclass
On Fri, Jul 27, 2018 at 04:37:07PM +0200, Patrick Delaunay wrote: > This patch save common LED property "default-state" value > in post bind of LED uclass. > The configuration for this default state is only performed when > led_default_state() is called; > It can be called in your board_init() > or it could added in init_sequence_r[] in future. > > Signed-off-by: Patrick Delaunay Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,1/1] drivers: serial: document on_baudrate()
On Sun, Jul 29, 2018 at 10:41:02AM +0200, Heinrich Schuchardt wrote: > Add parameter description. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] travis: give every job a name
On Mon, Jul 30, 2018 at 10:19:43AM -0600, Stephen Warren wrote: > From: Stephen Warren > > Travis CI now supports giving jobs an explicit name. Do this for all jobs. > This allows more direct control over jobs names than the previous > automatic or implicit naming based on the environment variables or script > text. > > Signed-off-by: Stephen Warren Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/1] doc: README.iscsi: make compatible with restructured text
On Sun, Jul 29, 2018 at 01:50:50PM +0200, Heinrich Schuchardt wrote: > The Sphinx documentation system uses restructured text. > Make the README.iscsi file compatible. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v2,2/2] db410c: Fixup DRAM
On Tue, Jul 31, 2018 at 12:29:58PM +0300, Ramon Fried wrote: > Call the MSM DRAM detection and fixup function to support > dynamic detection of onboard memory. > > Signed-off-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,1/2] smbios: fix checkstyle error
On Mon, Jul 30, 2018 at 01:22:06PM +0200, Christian Gmeiner wrote: > Fixes the following chechpatch -f error: > > ERROR: "(foo*)" should be "(foo *)" > + strncpy((char*)t->uuid, serial_str, sizeof(t->uuid)); > > Signed-off-by: Christian Gmeiner > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/2] doc: FIT image: clarify usage of "compression" property
On Mon, Jul 30, 2018 at 12:53:18PM +0200, Simon Goldschmidt wrote: > Compressed images should have their compression property > set to "none" if U-Boot should leave them compressed. > > This is especially the case for compressed ramdisks that > should be uncompressed by the kernel only. > > Signed-off-by: Simon Goldschmidt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,1/1] README: U_BOOT_ENV_CALLBACK functions
On Sun, Jul 29, 2018 at 11:08:14AM +0200, Heinrich Schuchardt wrote: > Describe the interface of environment variable callback functions. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] omap3_logic: Fix CONS_INDEX
On Sat, Jul 28, 2018 at 02:03:21PM -0500, Adam Ford wrote:
> The console index for SPL should be 1 not 3 in order to see text during
> SPL.
>
> Fixes 6f6b7cfa89e5 ("Convert all of CONFIG_CONS_INDEX to Kconfig")
>
> Signed-off-by: Adam Ford
>
> diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
> index ed9f454a5d..0420493a0e 100644
Applied to u-boot/master, thanks!
--
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Re: [U-Boot] [U-Boot, 1/1] elf: Add support for PPC64 ELF V1 ABI in bootelf
On Tue, Jul 31, 2018 at 10:57:42PM -0400, Rob Bracero wrote: > This update adds PPC64 ELF V1 ABI support to bootelf for both the > program header and section header options. Elf64 support was already > present for the program header option, but it was not handling the > PPC64 ELF V1 ABI case. For the PPC64 ELF V1 ABI, the e_entry field of > the elf header must be treated as function descriptor pointer instead > of a function address. The first doubleword of the function descriptor > is the function's entry address. > > Signed-off-by: Rob Bracero Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 1/2] snapdragon: Add DRAM detection & FDT fixup
On Tue, Jul 31, 2018 at 12:29:57PM +0300, Ramon Fried wrote: > Fixup the Linux FDT with the detection of onboard DRAM as > provided by SBL (Secondary boot loader) by reading > the shared-memory region. > > Signed-off-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] configs: omap3_logic: Disable NAND ID during SPL
On Sun, Jul 29, 2018 at 08:16:49PM -0500, Adam Ford wrote: > For these boards, the GPMC timings are more determined by > processor speed/type than the NAND/PoP memory. This code > is never invoked, so disable the config option, so it doesn't > take the time to compile it in. > > Signed-off-by: Adam Ford > > diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig > index ed9f454a5d..77dfdfc0e5 100644 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,2/2] smbios: fix checkstyle warning
On Mon, Jul 30, 2018 at 01:22:07PM +0200, Christian Gmeiner wrote: > Fixes the following checkstyle warning: > > WARNING: Missing a blank line after declarations > + int tmp = smbios_write_funcs[i]((ulong *)&addr, handle++); > + max_struct_size = max(max_struct_size, tmp); > > Signed-off-by: Christian Gmeiner > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
