[U-Boot] MIPS (mt7688): EBase change in U-Boot breaks Linux
Hi! I've been hunting for a problem for quite some time, where Linux hangs / crashes in userspace at some point on my MT7688 based systems. I found that this problem can be avoided (worked around) by not giving Linux the full memory (by using DT memory node fixup or mem= kernel cmdline). When reducing this memory by the memory used by U-Boot (stack pointer minus some KiB value as this is the "lowest" memory used by U-Boot), then Linux runs just fine. My first idea here was, that this issue is cache related (most likely I-cache). But all tests and debugging in this area did not fix this issue (even running with caches disabled). Finally I found that this line in U-Boot makes Linux break: arch/mips/lib/traps.c: void trap_init(ulong reloc_addr) unsigned long ebase = gd->irq_sp; ... write_c0_ebase(ebase); This sets EBase to something like 0x87e9b000 on my system (128MiB). And Linux then re-uses this value and copies the exceptions handlers to this address, overwriting random code and leading to an unstable system. So my questions now is, how should this be handled on the MT7688 platform instead? One way would be to set EBase back to the original value (0x8000) before booting into Linux. Another solution would be to add some Linux code like board_ebase_setup() to the MT7688 Linux port. Since I'm still no real MIPS expert yet, I would really like to get some advise here on how to best solve this issue. Maybe I missed something. Comments? Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] poplar: fix boot failure caused by serial driver change
Hi Shawn,
Thanks, that fixes the problem!
Reviewed-by: Igor Opaniuk
Tested-by: Igor Opaniuk
On Wed, 12 Dec 2018 at 09:25, Shawn Guo wrote:
>
> Commit 4687919684e0 ("serial: Remove DM_FLAG_PRE_RELOC flag in various
> drivers") essentially drops flag DM_FLAG_PRE_RELOC from serial_pl01x
> driver for Poplar platform, because the platform falls into the
> following strategy category made by the commit.
>
> Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
> drivers that support both statically declared devices and
> configuration from device tree
>
> Before the commit lands, Poplar platform works by statically declaring
> pl011 serial device via U_BOOT_DEVICE() with DM_FLAG_PRE_RELOC flag set
> in the driver. But since Poplar also supports device configuration from
> device tree, the commit practically drops the flag for Poplar, and hence
> breaks the platform from booting.
>
> This patch changes platform code and device tree to initiate pl011
> serial device from device tree rather than static declaration, so that
> above strategy about DM_FLAG_PRE_RELOC applies to Poplar, and therefore
> the reported boot failure gets fixed.
>
> Reported-by: Igor Opaniuk
> Fixes: 4687919684e0 ("serial: Remove DM_FLAG_PRE_RELOC flag in various
> drivers")
> Cc: Bin Meng
> Cc: Simon Glass
> Signed-off-by: Shawn Guo
> ---
> arch/arm/dts/hi3798cv200-u-boot.dtsi | 10 ++
> board/hisilicon/poplar/poplar.c | 2 ++
> 2 files changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/dts/hi3798cv200-u-boot.dtsi
> b/arch/arm/dts/hi3798cv200-u-boot.dtsi
> index 709ae1cbc9f3..7844c5208c5d 100644
> --- a/arch/arm/dts/hi3798cv200-u-boot.dtsi
> +++ b/arch/arm/dts/hi3798cv200-u-boot.dtsi
> @@ -17,12 +17,6 @@
> };
>
> &uart0 {
> - status = "disabled";
> + clock = <7500>;
> + status = "okay";
> };
> -
> -/{
> - chosen {
> - stdout-path = "";
> - };
> -};
> -
> diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c
> index 9e8eac78388b..8adc750962a1 100644
> --- a/board/hisilicon/poplar/poplar.c
> +++ b/board/hisilicon/poplar/poplar.c
> @@ -35,6 +35,7 @@ static struct mm_region poplar_mem_map[] = {
>
> struct mm_region *mem_map = poplar_mem_map;
>
> +#if !CONFIG_IS_ENABLED(OF_CONTROL)
> static const struct pl01x_serial_platdata serial_platdata = {
> .base = REG_BASE_UART0,
> .type = TYPE_PL010,
> @@ -45,6 +46,7 @@ U_BOOT_DEVICE(poplar_serial) = {
> .name = "serial_pl01x",
> .platdata = &serial_platdata,
> };
> +#endif
>
> int checkboard(void)
> {
> --
> 2.18.0
>
--
Regards,
Igor Opaniuk
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Re: [U-Boot] [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific Kconfig option
Hi Bin Bin Meng 於 2018年12月11日 週二 下午3:17寫道： > > Hi Rick, > > On Tue, Dec 11, 2018 at 3:06 PM Rick Chen wrote: > > > > > > Subject: [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific Kconfig > > > > option > > > > > > > > There is no need to expose RISCV_NDS to the Kconfig menu as it is an > > > > ax25-specific option. > > > > > > > > Hi Bin > > > > Can you explain why there is no need to expose RISCV_NDS here ? > > > > This is specific to AX25, and there is no need to appear in the > Kconfig menu when people are building U-Boot for some other RISC-V > platforms. Also even if you select Y in the Kconfig menu for this > option for platforms other than AX25, it just does not help since all > its logic is within arch/riscv/cpu/ax25. > AX25 can not select RISCV_NDS by default, it may cause build fail problem. I still prefer to enable it by make menuconfig. Can you drop this patch ? Thanks Rick > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] rockchip: rk3288-evb: dts: remove 'vmmc' from emmc node
On 12/11/2018 02:20 AM, Tom Rini wrote: > On Sat, Dec 08, 2018 at 12:27:42PM +0800, Kever Yang wrote: >> Hi Tom, >> >> >> On 12/07/2018 10:13 PM, Tom Rini wrote: >>> On Fri, Dec 07, 2018 at 02:24:22PM +0100, Philipp Tomsich wrote: Kever, > On 07.12.2018, at 02:39, Kever Yang wrote: > > Hi Philipp, > > On 12/06/2018 09:50 PM, Philipp Tomsich wrote: >> +Tom >> >>> On 05.12.2018, at 03:25, Kever Yang wrote: >>> >>> The U-Boot eMMC does not need to care about the power for Rockchip >>> SoC, because if the board is using eMMC, the power will default on >>> (for bootrom), and we do not do power management for it like kernel, >>> so the 'vmmc', 'vqmmc' is only useful for SD in U-Boot. >>> >>> This make U-Boot can boot into kernel even if the pmic driver is >>> broken. >> If the PMIC driver is broken, we should fix the PMIC driver. >> I would feel more comfortable w/o this statement. >> >>> The rk3288-evb dts may be used in many boards using rockchip reference >>> schematic but with little change, so we hope it can be more robust to >>> boot into next stage. >> Again, this is not how the DTS should be used. I believe that Heiko, >> Fabio and >> I had already highlighted this in comments to the earlier thread. > Not sure if you have read my previous mail for answer all your > comments, > > I do agree DTS should represent the hardware, but please note that the DTS > is no kind of standard, and people always choose what they need and add > those part in there dts, but not always add all the property and > everyone use the same model. I would say there are many boards does not > have this > 'vmmc-supply’ in there emmc node. That is exactly the reason why I bumped the decision up the stairs (to Tom and/or Simon): what you are saying makes sense to me (viewed through your eyes and from your specific usecase), but it directly contradicts how the DTS usage is intended. In other words: Tom (as the top-level decision maker) or Simon (who owns the device-model and therefore will also have an opinion on DTS usage) should make the final call. >>> My answer is that I would strongly suspect that over in linux "we have N >>> different close-enough boards using this one DTS" isn't acceptable. You >>> make a dtsi and include it from the board and things that aren't common >>> don't go into the dtsi. And yes, when starting off everyone (myself >>> included) copies the reference platform dts and then changes it as >>> needed, and sometimes misses a thing or two. But no, I don't think we >>> want a wrong dts and I'm pretty sure the kernel really wouldn't want >>> wrong dts files and the general goal is that excluding the -u-boot.dtsi >>> files, ours are copies of the kernel. >> I don't think this is a "wrong dts" after my patch, these two nodes are >> not mark >> as required property in kernel, so many dts emmc node does not have it. >> I check the latest kernel dtsi in arch/arm/boot/dts/rk3288-evb.dtsi [1], >> the emmc node do not have 'vmmc' and 'vqmmc' while the SD node have, which >> just like description in my commit message. > OK. So this would fall into the category of "sync with upstream dts" > then, right? That is what we want. OK, Got it, 'sync with upstream dts' is a good and acceptable commit message rather than the real reason why we need the patch. Philipp, Do you need me to send out a patch with update the commit message? Thanks, - Kever >> Well, I don't know why U-Boot project is so difficult to accept a >> reasonable patch now, I don't >> want to make you unhappy, but make 'every board must have its own dts' >> in U-Boot to make >> every developer to join U-Boot does not make sense to me. The kernel >> need different >> dts for different board because they need to use/control those different >> feature, but U-Boot >> is not the case, U-Boot should work if the storage driver works. > Well, here's the thing. If you want U-Boot to then load and pass the > correct DTB to the kernel, we need per-board tweaks to the code anyhow > to find and load that DTB (see the various "findfdt" environment scripts > for example). If you want to rework things so that you have a "generic" > type board under U-Boot that's more clearly not tied to any specific > board but instead runs on many, that might help clear things up too. > Hope this helps! > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] net: explicitly assign errno to return code in case of network failure
Am Di., 27. Nov. 2018 um 21:06 Uhr schrieb Christian Gmeiner : > > Am Mi., 21. Nov. 2018 um 15:57 Uhr schrieb Thomas RIENOESSL > : > > > > When dealing with two ethernet ports and having "netretry" set > > to "once", it could occur that the connection (e.g. an ARP > > request) failed, hence the status of the netloop was > > "NETLOOP_FAIL". Due to the setting of "netretry", the network > > logic would then switch to the other network interface, > > assigning "ret" with the return value of "net_start_again()". > > If this call succeeded we would return 0 (i.e. success) to > > the caller when in reality the network action failed. > > > > Change-Id: I58b935b0f6c7a300d1dd0058803f7d3c9455b0dc > > Signed-off-by: Thomas RIENOESSL > > Looks good - Gerrit change id should be removed before pushing this > patch. > > Reviewed-by: Christian Gmeiner > ping -- greets -- Christian Gmeiner, MSc https://christian-gmeiner.info ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] mtd: Get rid of board_mtdparts_default()
Hi Ladislav,
On Tue, 11 Dec 2018 23:55:26 +0100
Ladislav Michl wrote:
> Hi Boris,
>
> On Mon, Dec 10, 2018 at 04:38:50PM +0100, Boris Brezillon wrote:
> > The only implementer of this function has been patched to use
> > CONFIG_MTD{IDS,PARTS}_DEFAULT instead. Let's get rid of this function
> > and the associated CONFIG_SYS_MTDPARTS_RUNTIME option.
>
> the only implementer of this fuction did so for a good reason. What is
> a motivation to remove it?
Simplifying the code (see this discussion [1] which led me to send
this patchset).
>
> The requirement is to be able to use single u-boot binary on all igep2
> boards ever produced. These comes with various NAND and OneNAND chips
> and I was not able to come with single static partition configuration
> to support them all.
That's actually the question I asked Enric in [1]. Can you list all
the memory organization you have (for NAND and OneNAND chips)? I mean,
the SPL part size depends on the NAND/OneNAND erase block size, and
board vendors try to use similar flashes when they source different
parts (same page size, same block size, ...). Assuming this is the
case, you should always have the same layout for OneNAND/NAND devices,
hence my proposal to define those parts statically.
> Hence runtime detection. That code could be used
> on all OMAP3 boards as BootROM reads up to first four sectors searching
> for SPL (MLO).
Note that, for the nand side of things, you can also automate that using
a u-boot script:
nand info; setexpr splsize ${nand_erasesize} * 4; setenv mtdparts
mtdparts=omap2-nand:0x${splsize}(SPL),-(UBI)
Shouldn't be hard to patch the onenand cmd to also expose writesize,
erasesize and oobsize.
Regards,
Boris
[1]https://www.mail-archive.com/u-boot@lists.denx.de/msg304933.html
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Re: [U-Boot] [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific Kconfig option
Hi Rick, On Wed, Dec 12, 2018 at 5:02 PM Rick Chen wrote: > > Hi Bin > > Bin Meng 於 2018年12月11日 週二 下午3:17寫道： > > > > Hi Rick, > > > > On Tue, Dec 11, 2018 at 3:06 PM Rick Chen wrote: > > > > > > > > Subject: [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific Kconfig > > > > > option > > > > > > > > > > There is no need to expose RISCV_NDS to the Kconfig menu as it is an > > > > > ax25-specific option. > > > > > > > > > > > Hi Bin > > > > > > Can you explain why there is no need to expose RISCV_NDS here ? > > > > > > > This is specific to AX25, and there is no need to appear in the > > Kconfig menu when people are building U-Boot for some other RISC-V > > platforms. Also even if you select Y in the Kconfig menu for this > > option for platforms other than AX25, it just does not help since all > > its logic is within arch/riscv/cpu/ax25. > > > > AX25 can not select RISCV_NDS by default, it may cause build fail problem. > I still prefer to enable it by make menuconfig. > Can you drop this patch ? > I prefer not to drop this patch since it's not supposed to be exposed to other platforms. Do you mean the build fail problem is custom CSR numbers like mcache_ctl? Can we use hardcoded CSR number instead? Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH u-boot-marvell v3 09/10] board: turris_mox: Support 1 GB version of Turris Mox
Hi Marek,
On 12.12.18 03:23, Marek Behun wrote:
Hi, I have found the bug causing this issue.
Good.
If I understand the algorithm in get_ram_size correctly, it does
approximately this. Suppose A, B, C, D, E, F are different constatnts.
X(i) is a value at address 1<
I have to admit that I didn't fully try to understand this issue you
describe above (sorry, lack of time). If you have found a bug and do
have a fix for it, then please submit a patch. Please add all
developers (e.g. Patrick Delaunay etc) who did some work on this code
to Cc, as changes here might be critical.
I have to confess that I do not like how this function is written at
all. It does not, for example, solve correctly the case when a device
has 768 MiB of RAM from two chips (512 + 256). Given 1024 MiB as
argument, it would return 1024 MiB, but the system only has 768 MiB.
This maybe is never an issue with devices that run u-boot, but still.
If you have a nice and easy implementation to also support such
memory configurations, that would be perfect of course. But I really
think that such non-power-of-2 memory configurations are rather uncommon
for U-Boot and most likely don't need to be supported by this function.
Such configuration usually are a result of using multiple DIMM's (or
SODIMM's) which can be equipped with various sized memories. And here
the memory size can be read from the DIMM itself. So no need to support
this in get_ram_size().
Thanks,
Stefan
Marek
On Tue, 11 Dec 2018 16:06:42 +0100
Stefan Roese wrote:
On 11.12.18 15:53, Marek Behún wrote:
On Tue, 11 Dec 2018 15:28:11 +0100
Stefan Roese wrote:
Hi Marek,
On 11.12.18 14:59, Marek Behún wrote:
get_ram_size does not work correctly on Mox. On a 512 MiB board it
detects 1024 MiB of RAM, because on the 512 MiB RAM chip the
topmost address bit is simply ignored and the RAM wraps - on
0x2000-0x4000 CPU sees the same data as on
0x0-0x2000.
That's what get_ram_size() does: It does detect such aliases when
the same memory is mapped at multiple areas (power of 2). Did you
give it a try with a max value of 1024 MiB? It should return
512 on such boards.
I checked it and it returned 1024 MiB.
I did
printf("%08x %08x\n",
get_ram_size(0, 512<<20),
get_ram_size(0, 1024<<20));
on a 512 MiB board and
0x2000 0x4000
was printed.
Very strange. Could you please debug this issue? get_ram_size()
should be able to work in such situations.
Thanks,
Stefan
ATF does not run RAM size determining code either, it just gets
RAM size from a register, this register is written before ATF by
BootROM and we have done it so that there is always 1 GB so that
we could use same secure firmware image for all Moxes. I tried to
change this register in secure firmware, but this lead to
Synchornous Abort events in U-Boot.
Maybe we could move the dram_init funcitons from arm64-common.c to
specific board files, or maybe we could declare them __weak in
arm64-common.c and turris_mox can then redefine them.
Would that be OK with you?
Please fist check if get_ram_size() can't be used.
Thanks,
Stefan
Marek
On Thu, 29 Nov 2018 14:07:59 +0100
Stefan Roese wrote:
On 20.11.18 13:04, Marek Behún wrote:
Depending on the data in the OTP memory, differentiate between
the 512 MiB and 1 GiB versions of Turris Mox and report these
RAM sizes in dram_init and dram_init_banksize.
Signed-off-by: Marek Behún
---
arch/arm/mach-mvebu/arm64-common.c | 7 ++-
board/CZ.NIC/turris_mox/turris_mox.c | 27
+++ 2 files changed, 33 insertions(+), 1
deletion(-)
diff --git a/arch/arm/mach-mvebu/arm64-common.c
b/arch/arm/mach-mvebu/arm64-common.c index
f47273fde9..5e6ac9fc4a 100644 ---
a/arch/arm/mach-mvebu/arm64-common.c +++
b/arch/arm/mach-mvebu/arm64-common.c @@ -43,8 +43,12 @@ const
struct mbus_dram_target_info *mvebu_mbus_dram_info(void) return
NULL; }
-/* DRAM init code ... */
+/*
+ * DRAM init code ...
+ * Turris Mox defines this itself, depending on data in burned
eFuses
+ */
+#ifndef CONFIG_TARGET_TURRIS_MOX
int dram_init_banksize(void)
{
fdtdec_setup_memory_banksize();
@@ -59,6 +63,7 @@ int dram_init(void)
return 0;
}
+#endif /* !CONFIG_TARGET_TURRIS_MOX */
2 Problems with this:
a)
This does not apply any more with the latest changes in mainline.
b)
I really don't like #ifdef's here in this common code. Can you
not get rid of this somehow? Isn't the turris_mox also using ATF
and will read the RAM size from there?
U-Boot still has the good old get_ram_size() function, which can
easily auto-detect 512MiB vs 1GiB when run with 1GiB as
parameter.
Thanks,
Stefan
int arch_cpu_init(void)
{
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c
b/board/CZ.NIC/turris_mox/turris_mox.c index
89b3cd2ce0..9aa2fc004d 100644 ---
a/board/CZ.NIC/turris_mox/turris_mox.c +++
b/board/CZ.NIC/turris_mox/turris_mox.c @@ -14,6 +14,7 @@
Re: [U-Boot] [PATCH v2] rockchip: rk3288-evb: dts: remove 'vmmc' from emmc node
> On 12.12.2018, at 10:05, Kever Yang wrote: > > > > On 12/11/2018 02:20 AM, Tom Rini wrote: >> On Sat, Dec 08, 2018 at 12:27:42PM +0800, Kever Yang wrote: >>> Hi Tom, >>> >>> >>> On 12/07/2018 10:13 PM, Tom Rini wrote: On Fri, Dec 07, 2018 at 02:24:22PM +0100, Philipp Tomsich wrote: > Kever, > >> On 07.12.2018, at 02:39, Kever Yang wrote: >> >> Hi Philipp, >> >> On 12/06/2018 09:50 PM, Philipp Tomsich wrote: >>> +Tom >>> On 05.12.2018, at 03:25, Kever Yang wrote: The U-Boot eMMC does not need to care about the power for Rockchip SoC, because if the board is using eMMC, the power will default on (for bootrom), and we do not do power management for it like kernel, so the 'vmmc', 'vqmmc' is only useful for SD in U-Boot. This make U-Boot can boot into kernel even if the pmic driver is broken. >>> If the PMIC driver is broken, we should fix the PMIC driver. >>> I would feel more comfortable w/o this statement. >>> The rk3288-evb dts may be used in many boards using rockchip reference schematic but with little change, so we hope it can be more robust to boot into next stage. >>> Again, this is not how the DTS should be used. I believe that Heiko, >>> Fabio and >>> I had already highlighted this in comments to the earlier thread. >>Not sure if you have read my previous mail for answer all your >> comments, >> >> I do agree DTS should represent the hardware, but please note that the >> DTS >> is no kind of standard, and people always choose what they need and add >> those part in there dts, but not always add all the property and >> everyone use the same model. I would say there are many boards does not >> have this >> 'vmmc-supply’ in there emmc node. > That is exactly the reason why I bumped the decision up the stairs (to > Tom and/or > Simon): what you are saying makes sense to me (viewed through your eyes > and > from your specific usecase), but it directly contradicts how the DTS > usage is intended. > > In other words: Tom (as the top-level decision maker) or Simon (who owns > the > device-model and therefore will also have an opinion on DTS usage) should > make > the final call. My answer is that I would strongly suspect that over in linux "we have N different close-enough boards using this one DTS" isn't acceptable. You make a dtsi and include it from the board and things that aren't common don't go into the dtsi. And yes, when starting off everyone (myself included) copies the reference platform dts and then changes it as needed, and sometimes misses a thing or two. But no, I don't think we want a wrong dts and I'm pretty sure the kernel really wouldn't want wrong dts files and the general goal is that excluding the -u-boot.dtsi files, ours are copies of the kernel. >>> I don't think this is a "wrong dts" after my patch, these two nodes are >>> not mark >>> as required property in kernel, so many dts emmc node does not have it. >>> I check the latest kernel dtsi in arch/arm/boot/dts/rk3288-evb.dtsi [1], >>> the emmc node do not have 'vmmc' and 'vqmmc' while the SD node have, which >>> just like description in my commit message. >> OK. So this would fall into the category of "sync with upstream dts" >> then, right? That is what we want. > > OK, Got it, 'sync with upstream dts' is a good and acceptable commit > message > rather than the real reason why we need the patch. > > Philipp, > Do you need me to send out a patch with update the commit message? If you do it, you’ll save me work and the history on the list is 1:1 identical with what I apply … If you absolutely don’t have time, I’ll change the commit message as I process this for my end-of-week pull-request. Thanks, Philipp. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 00/25] riscv: Adding RISC-V CPU and timer driver
Thanks for folding my timer patches in your series. I agree with Lukas comment on "riscv: Update supports_extension() to use desc from cpu driver". Please don't access misa in S-mode. Otherwise entire series looks good to me. Reviewed-by: Anup Patel Regards, Anup ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/7] Remove defines for SPI default speed and mode
On Wed, Dec 12, 2018 at 8:51 AM Petr Vorel wrote: > > Hi Patrick, > > FYI this patchset breaks some machines: > https://travis-ci.org/pevik/u-boot/builds/466192406 I might be wrong, but I think that build log indicates an error on a line that should not exist any more after applying this series and the one the OP says it's based on: http://patchwork.ozlabs.org/project/uboot/list/?series=76834 Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific Kconfig option
Bin Meng 於 2018年12月12日 週三 下午5:37寫道： > > Hi Rick, > > On Wed, Dec 12, 2018 at 5:02 PM Rick Chen wrote: > > > > Hi Bin > > > > Bin Meng 於 2018年12月11日 週二 下午3:17寫道： > > > > > > Hi Rick, > > > > > > On Tue, Dec 11, 2018 at 3:06 PM Rick Chen wrote: > > > > > > > > > > Subject: [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific > > > > > > Kconfig option > > > > > > > > > > > > There is no need to expose RISCV_NDS to the Kconfig menu as it is an > > > > > > ax25-specific option. > > > > > > > > > > > > > > Hi Bin > > > > > > > > Can you explain why there is no need to expose RISCV_NDS here ? > > > > > > > > > > This is specific to AX25, and there is no need to appear in the > > > Kconfig menu when people are building U-Boot for some other RISC-V > > > platforms. Also even if you select Y in the Kconfig menu for this > > > option for platforms other than AX25, it just does not help since all > > > its logic is within arch/riscv/cpu/ax25. > > > > > > > AX25 can not select RISCV_NDS by default, it may cause build fail problem. > > I still prefer to enable it by make menuconfig. > > Can you drop this patch ? > > > > I prefer not to drop this patch since it's not supposed to be exposed > to other platforms. > > Do you mean the build fail problem is custom CSR numbers like > mcache_ctl? Can we use hardcoded CSR number instead? > Thanks for your suggestion about hardcoded CSR number. But actually I hope the mcache_ctl will be disabled by default in this stage. Because some drivers of ae350 (like spi, smc flash driver, mac driver) still have some access problems when cache is enable. I am fixing it now. But mmc driver is ready when cache is enable. That is why I prefer enable cache by make menuconfig. It will be easy to switch cache enable or disable by make menuconfig without modifying Kconfig. How do you think about it ? B.R Rick > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 16/25] riscv: Update supports_extension() to use desc from cpu driver
Hi Bin,
On Wed, 2018-12-12 at 15:02 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Wed, Dec 12, 2018 at 7:40 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Tue, 2018-12-11 at 01:34 -0800, Bin Meng wrote:
> > > This updates supports_extension() implementation to use the desc
> > > string from the cpu driver whenever possible, which avoids the
> > > reading of misa CSR for S-mode U-Boot.
> > >
> > > Signed-off-by: Bin Meng
> > >
> > > ---
> > >
> > > Changes in v3:
> > > - new patch to update supports_extension() to use desc from cpu
> > > driver
> > >
> > > Changes in v2: None
> > >
> > > arch/riscv/cpu/cpu.c | 16
> > > 1 file changed, 16 insertions(+)
> > >
> > > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > > index d3c59da..704ae70 100644
> > > --- a/arch/riscv/cpu/cpu.c
> > > +++ b/arch/riscv/cpu/cpu.c
> > > @@ -5,8 +5,10 @@
> > >
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > > +#include
> > >
> > > /*
> > > * prior_stage_fdt_address must be stored in the data section
> > > since
> > > it is used
> > > @@ -16,7 +18,21 @@ phys_addr_t prior_stage_fdt_address
> > > __attribute__((section(".data")));
> > >
> > > static inline bool supports_extension(char ext)
> > > {
> > > +#ifdef CONFIG_CPU
> > > + struct udevice *dev;
> > > + char desc[32];
> > > +
> > > + uclass_find_first_device(UCLASS_CPU, &dev);
> > > + if (!cpu_get_desc(dev, desc, sizeof(desc))) {
> > > + /* skip the first 4 characters (rv32|rv64) */
> > > + if (strchr(desc + 4, ext))
> > > + return true;
> > > + }
> > > +
> > > + return false;
> > > +#else
> > > return csr_read(misa) & (1 << (ext - 'a'));
> >
> > This should not be used in supervisor mode, so that we don't need a
> > patched BBL. I think it is better to use #elif
> > defined(CONFIG_RISCV_MMODE) here.
> >
>
> OK, will do in v4.
>
> > There should also be a warning message to the user if
> > supports_extension() does not have a way to determine the available
> > extensions (supervisor-mode and no CONFIG_CPU or CONFIG_CPU, but no
> > device found). This would help to prevent difficult-to-debug errors
> > caused by part of the initialization missing.
> >
>
> Will add a warning message for S-mode without CPU. I don't think we
> should warn CONFIG_CPU but no device found case as it has already
> been
> covered in riscv_cpu_probe().
>
You are right, I missed that.
Thanks,
Lukas
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Re: [U-Boot] MIPS (mt7688): EBase change in U-Boot breaks Linux
Hi Stefan, Is your Linux Kernel compile with CONFIG_CPU_MIPSR2_IRQ_VI? Because we had similar issue with two of our boards(Ocelot and Luton). In our case the problem was that that Linux Kernel didn't reserve memory for the addresses pointed by ebase register and then later the kernel used this address overwriting the interupt vector, that lead to random crash. The 12/12/2018 09:18, Stefan Roese wrote: > Hi! > > I've been hunting for a problem for quite some time, where Linux > hangs / crashes in userspace at some point on my MT7688 based > systems. I found that this problem can be avoided (worked around) > by not giving Linux the full memory (by using DT memory node fixup > or mem= kernel cmdline). When reducing this memory by the memory > used by U-Boot (stack pointer minus some KiB value as this is the > "lowest" memory used by U-Boot), then Linux runs just fine. > > My first idea here was, that this issue is cache related (most > likely I-cache). But all tests and debugging in this area did not > fix this issue (even running with caches disabled). > > Finally I found that this line in U-Boot makes Linux break: > > arch/mips/lib/traps.c: > > void trap_init(ulong reloc_addr) > unsigned long ebase = gd->irq_sp; > ... > write_c0_ebase(ebase); > > This sets EBase to something like 0x87e9b000 on my system (128MiB). > And Linux then re-uses this value and copies the exceptions handlers > to this address, overwriting random code and leading to an unstable > system. > > So my questions now is, how should this be handled on the MT7688 > platform instead? One way would be to set EBase back to the > original value (0x8000) before booting into Linux. Another > solution would be to add some Linux code like board_ebase_setup() > to the MT7688 Linux port. > > Since I'm still no real MIPS expert yet, I would really like to get > some advise here on how to best solve this issue. Maybe I missed > something. Comments? > > Thanks, > Stefan > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot -- /Horatiu ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] qemu-arm: Add persistent environment support
On Wed, 12 Dec 2018 at 13:07, Takahiro Akashi wrote: > > On Wed, Dec 12, 2018 at 12:14:27PM +0530, Sumit Garg wrote: > > On Wed, 12 Dec 2018 at 07:09, Takahiro Akashi > > wrote: > > > > > > On Tue, Dec 11, 2018 at 06:04:05PM +0530, Sumit Garg wrote: > > > > On Mon, 26 Nov 2018 at 16:51, Sumit Garg wrote: > > > > > > > > > > Currently on qemu-arm platforms environment is kept in RAM. Instead > > > > > use pflash device 1 to provide persistent environment support across > > > > > device reset. > > > > > > > > > > Also (optionally) provide support for persistent environment across > > > > > qemu machine OFF/ON using following instructions: > > > > > > > > > > - Create envstore.img using qemu-img: > > > > > qemu-img create -f raw envstore.img 64M > > > > > - Add a pflash drive parameter to the command line: > > > > > -drive if=pflash,format=raw,index=1,file=envstore.img > > > > > > > > > > Signed-off-by: Sumit Garg > > > > > --- > > > > > configs/qemu_arm64_defconfig | 7 +++ > > > > > configs/qemu_arm_defconfig | 7 +++ > > > > > doc/README.qemu-arm | 6 ++ > > > > > include/configs/qemu-arm.h | 8 +++- > > > > > 4 files changed, 27 insertions(+), 1 deletion(-) > > > > > > > > > > > > > Gentle reminder. Please let me know if you have any further comments. > > > > > > Another use case is atf + u-boot (although I don't know people are > > > interested in it). Put bl1.bin in flash0(0x0-0x400) and put > > > fip.bin in flash1(0x400-0x800). Please note that, with secure=on, > > > flash0 is in secure and flash1 is in non-secure. > > > > I don't think current u-boot with "CONFIG_SYS_TEXT_BASE=0x" > > (flash0 address) could work in atf + u-boot configuration with bl33 > > address as NS_IMAGE_OFFSET=0x6000 [1] (RAM address). Alternatively > > we could use PRELOADED_BL33_BASE to specify flash address but that > > certainly won't be flash0 start address. > > I was able to run atf + u-boot with some tweaks on some CONFIG_* > and even successfully ran linux kernel with bootefi. > But I don't want to go into details now. > > > Also from TF-A doc for qemu [2] it seems to support UEFI/edk2 boot. > > > > IMHO, there should be separate u-boot ram defconfig to work with atf + > > u-boot configuration. Also we may choose a different flash address for > > environment for this target. > > My point is, again, > > > > [1] > > https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/qemu/include/platform_def.h#L168 > > [2] > > https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/qemu.rst > > > > -Sumit > > > > > While I admit that your patch is workable, my point is that there are > > > different use cases and it may not be a good idea to put one configuration > > > in qemu-arm.h. > > here. So do you suggest here to move following config options to Kconfig? 1. CONFIG_ENV_ADDR 2. CONFIG_ENV_SIZE 3. CONFIG_ENV_OFFSET If yes, I think this could be explored. -Sumit > It's time that we need get opinions from maintainers or anybody else. > > Thanks, > -Takahiro Akashi > > > > Thanks, > > > -Takahiro Akashi > > > > > > > > > > -Sumit > > > > > > > > > diff --git a/configs/qemu_arm64_defconfig > > > > > b/configs/qemu_arm64_defconfig > > > > > index f4502c9..0f13716 100644 > > > > > --- a/configs/qemu_arm64_defconfig > > > > > +++ b/configs/qemu_arm64_defconfig > > > > > @@ -29,3 +29,10 @@ CONFIG_USB=y > > > > > CONFIG_DM_USB=y > > > > > CONFIG_USB_EHCI_HCD=y > > > > > CONFIG_USB_EHCI_PCI=y > > > > > +CONFIG_ENV_IS_IN_FLASH=y > > > > > +CONFIG_MTD=y > > > > > +CONFIG_MTD_NOR_FLASH=y > > > > > +CONFIG_FLASH_CFI_DRIVER=y > > > > > +CONFIG_CFI_FLASH=y > > > > > +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y > > > > > +CONFIG_SYS_FLASH_CFI=y > > > > > diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig > > > > > index acebdc5..b75363e 100644 > > > > > --- a/configs/qemu_arm_defconfig > > > > > +++ b/configs/qemu_arm_defconfig > > > > > @@ -29,3 +29,10 @@ CONFIG_USB=y > > > > > CONFIG_DM_USB=y > > > > > CONFIG_USB_EHCI_HCD=y > > > > > CONFIG_USB_EHCI_PCI=y > > > > > +CONFIG_ENV_IS_IN_FLASH=y > > > > > +CONFIG_MTD=y > > > > > +CONFIG_MTD_NOR_FLASH=y > > > > > +CONFIG_FLASH_CFI_DRIVER=y > > > > > +CONFIG_CFI_FLASH=y > > > > > +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y > > > > > +CONFIG_SYS_FLASH_CFI=y > > > > > diff --git a/doc/README.qemu-arm b/doc/README.qemu-arm > > > > > index 2601656..e67bc13 100644 > > > > > --- a/doc/README.qemu-arm > > > > > +++ b/doc/README.qemu-arm > > > > > @@ -47,6 +47,12 @@ The minimal QEMU command line to get U-Boot up and > > > > > running is: > > > > > Note that for some odd reason qemu-system-aarch64 needs to be > > > > > explicitly > > > > > told to use a 64-bit CPU or it will boot in 32-bit mode. > > > > > > > > > > +Additional persistent U-boot environment support can be added as > > > > > follows: > > > > > +- Create envstore.img using qemu-img: > > > > > +qemu-img create -f raw envstore.i
Re: [U-Boot] Uboot File not found in MMC
Hi Thanks for the reply. The ext2 partition is not set as bootable. Is it needed to set this partition as bootable for uboot to detect files in this partition. Thanks, Kasiviswanathan.V -Original Message- From: Kever Yang Sent: Tuesday, December 04, 2018 12:39 PM To: Venkatakrishnan, Kasiviswanathan ; u-boot@lists.denx.de Subject: Re: [U-Boot] Uboot File not found in MMC Hi Does the boot partition marks as 'bootable' in partition table? Thanks, - Kever On 12/01/2018 12:16 PM, kasiviswanathan.venkatakrish...@us.fujitsu.com wrote: > Hi all, > > We are using U-Boot of version 2015.01 in one of our PPC boards. The > development board has few FPGA's and its corresponding images are > downloaded into the /boot partition from the linux prompt which is of ext2 > type. > > If we download new files to the /boot partition i.e when we update the > FPGA images and reboot U-Boot is not able to identify the updated > files from the /boot partition. But when we do a listing of the files in > U-Boot it is shown as available. > > We tried to change the partition type of /boot from ext2 to ext4 but > still U-Boot is not able to find the files. > > Is there any fix available for this issue ? > > Thanks in advance. > > Thanks, > Kasiviswanathan.V > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://urldefense.proofpoint.com/v2/url?u=https-3A__lists.denx.de_lis > tinfo_u-2Dboot&d=DwIDaQ&c=09aR81AqZjK9FqV5BSCPBw&r=rxo4w3inOZ4mlsfSo0GdJxeb7sluHpXYMAzJwNCqnLtOS1A8UCYdjP5tOXx4gEEN&m=13s7h1mWN6KN85K-AEHgPH3VZNo-z1Aqvi4HzRWQgEQ&s=Qfg4wBlhL4xd2U1Gcggo-__kaWA9fgu5vOUu-7w4Leo&e= ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] fsl-ls2088ardb: dts: enabling SATA node
Signed-off-by: Pankit Garg
---
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
index c8bf9a0..b6d4f0f 100644
--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
@@ -56,3 +56,7 @@
reg = <1>;
};
};
+
+&sata {
+ status = "okay";
+};
--
1.9.1
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[U-Boot] [PATCH] fsl-ls2088ardb: dts: enabling SATA node
Signed-off-by: Pankit Garg
---
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
index c8bf9a0..b6d4f0f 100644
--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
@@ -56,3 +56,7 @@
reg = <1>;
};
};
+
+&sata {
+ status = "okay";
+};
--
1.9.1
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Re: [U-Boot] [PATCH 09/13] serial: Remove DM_FLAG_PRE_RELOC flag in various drivers
Hi Igor, On Mon, Dec 10, 2018 at 07:26:23PM +0200, Igor Opaniuk wrote: > Hi Bin, > > This particular commit leads to a constant Poplar board restart (git > bisect pointed to it). > U-boot is built with the default poplar_config from the latest master > (btw, is uses r), and U-boot is used as default BL33 image (setup: > vanilla ATF + vanilla OP-TEE(BL32, S-EL1 payload) + U-boot). Thanks for reporting the issue. I looked into it and came up with a fix for review [1]. Would you give it a try to see if it fixes the problem? Shawn [1] https://lists.denx.de/pipermail/u-boot/2018-December/351741.html ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/7] Remove defines for SPI default speed and mode
Hi Patrick, FYI this patchset breaks some machines: https://travis-ci.org/pevik/u-boot/builds/466192406 Kind regards, Petr ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] mtd: Get rid of board_mtdparts_default()
Hello Boris,
On Wed, Dec 12, 2018 at 10:32:51AM +0100, Boris Brezillon wrote:
> Hi Ladislav,
>
> On Tue, 11 Dec 2018 23:55:26 +0100
> Ladislav Michl wrote:
>
> > Hi Boris,
> >
> > On Mon, Dec 10, 2018 at 04:38:50PM +0100, Boris Brezillon wrote:
> > > The only implementer of this function has been patched to use
> > > CONFIG_MTD{IDS,PARTS}_DEFAULT instead. Let's get rid of this function
> > > and the associated CONFIG_SYS_MTDPARTS_RUNTIME option.
> >
> > the only implementer of this fuction did so for a good reason. What is
> > a motivation to remove it?
>
> Simplifying the code (see this discussion [1] which led me to send
> this patchset).
Thank you, makes sense.
> > The requirement is to be able to use single u-boot binary on all igep2
> > boards ever produced. These comes with various NAND and OneNAND chips
> > and I was not able to come with single static partition configuration
> > to support them all.
>
> That's actually the question I asked Enric in [1]. Can you list all
> the memory organization you have (for NAND and OneNAND chips)? I mean,
> the SPL part size depends on the NAND/OneNAND erase block size, and
> board vendors try to use similar flashes when they source different
> parts (same page size, same block size, ...). Assuming this is the
> case, you should always have the same layout for OneNAND/NAND devices,
> hence my proposal to define those parts statically.
First, thanks to Enric for pinging me, otherwise I would probably miss this
completely.
Now problem is that IGEPv2 comes with quite many configurations, some of
them are even customized, so static configuration is a show stopper
mainly as I do not know what devices are in field.
Another issue is how ubispl code works: It expects struct ubispl_info
filled with (among others) peb_offset of ubi partition. ubispl code counts
in terms of eraseblocks regardless of their size. So we would need to touch
this number when using static mtdparts.
> > Hence runtime detection. That code could be used
> > on all OMAP3 boards as BootROM reads up to first four sectors searching
> > for SPL (MLO).
>
> Note that, for the nand side of things, you can also automate that using
> a u-boot script:
>
> nand info; setexpr splsize ${nand_erasesize} * 4; setenv mtdparts
> mtdparts=omap2-nand:0x${splsize}(SPL),-(UBI)
That seems as a way to go!
> Shouldn't be hard to patch the onenand cmd to also expose writesize,
> erasesize and oobsize.
Side note: I never fully understand why is OneNAND using separate set of
commands.
Could you hold merging your paches until I implement above idea and test
it on a few boards? I know u-boot is now using two months merge window,
which is unfortunate, so I'll try to do it as soon as possible, but I do
not think I'll finish it till end of week.
> Regards,
>
> Boris
>
> [1]https://www.mail-archive.com/u-boot@lists.denx.de/msg304933.html
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Re: [U-Boot] MIPS (mt7688): EBase change in U-Boot breaks Linux
Hi Horatiu Vultur, On 12.12.18 12:21, Horatiu Vultur wrote: Is your Linux Kernel compile with CONFIG_CPU_MIPSR2_IRQ_VI? Because we had similar issue with two of our boards(Ocelot and Luton). No, its not configured for this MT7688 / RAMIPS SoC. Enabling this option does fix this issue. Many thanks for the suggestion. BTW: Should CPU_MIPSR2_IRQ_EI probably also be set? In our case the problem was that that Linux Kernel didn't reserve memory for the addresses pointed by ebase register and then later the kernel used this address overwriting the interupt vector, that lead to random crash. Exactly what we've observed here. It took quite some debugging to finally find the root-cause for this. Thanks, Stefan The 12/12/2018 09:18, Stefan Roese wrote: Hi! I've been hunting for a problem for quite some time, where Linux hangs / crashes in userspace at some point on my MT7688 based systems. I found that this problem can be avoided (worked around) by not giving Linux the full memory (by using DT memory node fixup or mem= kernel cmdline). When reducing this memory by the memory used by U-Boot (stack pointer minus some KiB value as this is the "lowest" memory used by U-Boot), then Linux runs just fine. My first idea here was, that this issue is cache related (most likely I-cache). But all tests and debugging in this area did not fix this issue (even running with caches disabled). Finally I found that this line in U-Boot makes Linux break: arch/mips/lib/traps.c: void trap_init(ulong reloc_addr) unsigned long ebase = gd->irq_sp; ... write_c0_ebase(ebase); This sets EBase to something like 0x87e9b000 on my system (128MiB). And Linux then re-uses this value and copies the exceptions handlers to this address, overwriting random code and leading to an unstable system. So my questions now is, how should this be handled on the MT7688 platform instead? One way would be to set EBase back to the original value (0x8000) before booting into Linux. Another solution would be to add some Linux code like board_ebase_setup() to the MT7688 Linux port. Since I'm still no real MIPS expert yet, I would really like to get some advise here on how to best solve this issue. Maybe I missed something. Comments? Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] armv8: fsl-layerscape: properly configure qdma ICID
From: Laurentiu Tudor The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor --- arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h| 6 +- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index a3f473fe28..f375fe7115 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -55,7 +55,11 @@ void fdt_fixup_icid(void *blob); CONFIG_SYS_FSL_ESDHC_ADDR) #define SET_QDMA_ICID(compat, streamid) \ - SET_SCFG_ICID(compat, streamid, dma_icid,\ + SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ + QDMA_BASE_ADDR), \ + SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ QDMA_BASE_ADDR) #define SET_EDMA_ICID(streamid) \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 4d0f16f21c..b4b7c3492e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -94,6 +94,7 @@ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x0220) #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x0738) +#define QMAN_CQSIDR_REG0x20a80 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x40ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x48ULL -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH] usb: composite: Fix max packet size for USB3.0
For USB3.0 the max packetsize for GET_DESCRIPTOR should be
sent as exponent value for 2. This means for 512, max packet
size should be filled with 9(2^9=512). Also, fill the USB
version field with 3.0 if speed is negotiated to Superspeed.
This fixes the issue of DFU gadget download failure with
superspeed. With out this patch, the max packet size is
overflowed to zero as the bMaxPacketsize is of u8 and hence
host is not able to detect this device.
Signed-off-by: Siva Durga Prasad Paladugu
---
drivers/usb/gadget/composite.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 5106cc5..c7e7623 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -735,8 +735,21 @@ composite_setup(struct usb_gadget *gadget, const struct
usb_ctrlrequest *ctrl)
case USB_DT_DEVICE:
cdev->desc.bNumConfigurations =
count_configs(cdev, USB_DT_DEVICE);
- cdev->desc.bMaxPacketSize0 =
- cdev->gadget->ep0->maxpacket;
+
+ /*
+* If the speed is Super speed, then the supported
+* max packet size is 512 and it should be sent as
+* exponent of 2. So, 9(2^9=512) should be filled in
+* bMaxPacketSize0. Also fill USB version as 3.0
+* if speed is Super speed.
+*/
+ if (cdev->gadget->speed == USB_SPEED_SUPER) {
+ cdev->desc.bMaxPacketSize0 = 9;
+ cdev->desc.bcdUSB = cpu_to_le16(0x0300);
+ } else {
+ cdev->desc.bMaxPacketSize0 =
+ cdev->gadget->ep0->maxpacket;
+ }
value = min(w_length, (u16) sizeof cdev->desc);
memcpy(req->buf, &cdev->desc, value);
break;
--
2.7.4
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Re: [U-Boot] [PATCH v4 16/25] riscv: Update supports_extension() to use desc from cpu driver
Hi Bin,
On Tue, 2018-12-11 at 23:11 -0800, Bin Meng wrote:
> This updates supports_extension() implementation to use the desc
> string from the cpu driver whenever possible, which avoids the
> reading of misa CSR for S-mode U-Boot.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v4:
> - print warnings for S-mode without CONFIG_CPU
>
> Changes in v3:
> - new patch to update supports_extension() to use desc from cpu
> driver
>
> Changes in v2: None
>
> arch/riscv/cpu/cpu.c | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index d3c59da..a2ebaf3 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -5,8 +5,10 @@
>
> #include
> #include
> +#include
> #include
> #include
> +#include
>
> /*
> * prior_stage_fdt_address must be stored in the data section since
> it is used
> @@ -16,7 +18,27 @@ phys_addr_t prior_stage_fdt_address
> __attribute__((section(".data")));
>
> static inline bool supports_extension(char ext)
> {
> +#ifdef CONFIG_CPU
> + struct udevice *dev;
> + char desc[32];
> +
> + uclass_find_first_device(UCLASS_CPU, &dev);
Sorry, I missed this before. Can you add error handling here to catch
uclass_find_first_device returning an error or not finding a device? It
would probably also make sense to print a warning message to the user
in this case.
Other than that, this patch and the series look good!
Reviewed-by: Lukas Auer
Thanks,
Lukas
> + if (!cpu_get_desc(dev, desc, sizeof(desc))) {
> + /* skip the first 4 characters (rv32|rv64) */
> + if (strchr(desc + 4, ext))
> + return true;
> + }
> +
> + return false;
> +#else /* !CONFIG_CPU */
> +#ifdef CONFIG_RISCV_MMODE
> return csr_read(misa) & (1 << (ext - 'a'));
> +#else /* !CONFIG_RISCV_MMODE */
> +#warning "There is no way to determine the available extensions in
> S-mode."
> +#warning "Please convert your board to use the RISC-V CPU driver."
> + return false;
> +#endif /* CONFIG_RISCV_MMODE */
> +#endif /* CONFIG_CPU */
> }
>
> static int riscv_cpu_probe(void)
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Re: [U-Boot] policy regarding unused code
Tom, Rick, On 11/12/2018 19:17, Tom Rini wrote: On Tue, Dec 11, 2018 at 06:01:23PM +0100, Jean-Jacques Hiblot wrote: On 11/12/2018 17:35, Tom Rini wrote: On Tue, Dec 11, 2018 at 04:46:01PM +0100, Jean-Jacques Hiblot wrote: On 11/12/2018 16:25, Jean-Jacques Hiblot wrote: Hi Tom, Is there such a policy described somewhere ? There are quite a pieces of code that are not used/compiled because no config enables it. A random pick among many others: - CONFIG_FPGA_LATTICE - CONFIG_MESON_SPIFC - CONFIG_POWER_BATTERY_TRATS2 - CONFIG_UPDATE_TFTP Here a more complete list of suspects (there may be options that do not even exist) Suspect means that the variable is probably referenced in a Makefile but not in configs/ nor in include/configs This is not a small list and a lot of them we probably want to keep. ['CONFIG_MX8M', 'CONFIG_POWER_PMIC_MAX77693', 'CONFIG_TPM2_TIS_SANDBOX', 'CONFIG_TPM_ST33ZP24_SPI', 'CONFIG_USB_SL811HS', 'CONFIG_RAM_SUPPORT', 'CONFIG_BCM2835_WDT', 'CONFIG_ENV_IS_IN_SATA', 'CONFIG_IO64', 'CONFIG_NAND_SUPPORT', 'CONFIG_NOR_SUPPORT', 'CONFIG_RISCV_ISA_A', 'CONFIG_I2C_MUX_GPIO', 'CONFIG_POWER_FG_MAX17042', 'CONFIG_DNET', 'CONFIG_CMD_SH_ZIMAGEBOOT', 'CONFIG_USE_DEFAULT_ENV_FILE', 'CONFIG_CMD_IOTRACE', 'CONFIG_ALI152X', 'CONFIG_M5271', 'CONFIG_CPU_MPC83XX', 'CONFIG_NXP_TDA19988', 'CONFIG_IMX', 'CONFIG_ADI_GPIO2', 'CONFIG_BUILD_ENVCRC', 'CONFIG_FTMAC110', 'CONFIG_CMD_CONITRACE', 'CONFIG_USB_DAVINCI', 'CONFIG_TARGET_XTFPGA', 'CONFIG_DLVISION_10G', 'CONFIG_CMD_KGDB', 'CONFIG_USB_SDP_SUPPORT', 'CONFIG_MESON_GX_VPU_POWER_DOMAIN', 'CONFIG_FSL_DMA', 'CONFIG_IHS_VIDEO_OUT', 'CONFIG_CMD_ZFS', 'CONFIG_P2020DS', 'CONFIG_RTC_DS1388', 'CONFIG_POWER_MUIC_MAX8997', 'CONFIG_TPM2_TIS_SPI', 'CONFIG_TEST_FDTDEC', 'CONFIG_AIS_CONFIG_FILE', 'CONFIG_GDSYS_SOC', 'CONFIG_CMD_DTIMG', 'CONFIG_DFU_SUPPORT', 'CONFIG_SYS_JFFS2_SORT_FRAGMENTS', 'CONFIG_ATF', 'CONFIG_BLOBLIST', 'CONFIG_NAND_SPEAR', 'CONFIG_MPC8XXX_GPIO', 'CONFIG_ULP_WATCHDOG', 'CONFIG_RTC_MK48T59', 'CONFIG_CMD_FITUPD', 'CONFIG_MODVERSIONS', 'CONFIG_CPU_SH3', 'CONFIG_CMD_BEDBUG', 'CONFIG_AT91_USB_CLK', 'CONFIG_CMD_UNIVERSE', 'CONFIG_DEBUG_UART_UNIPHIER', 'CONFIG_CMD_DISPLAY', 'CONFIG_ETH_SANDBOX_RAW', 'CONFIG_SANDBOX', 'CONFIG_CPU_SH2', 'CONFIG_SATA_SUPPORT', 'CONFIG_IOCON', 'CONFIG_MESON_SPIFC', 'CONFIG_NS8382X', 'CONFIG_SOC_DM355', 'CONFIG_BOARD_GAZERBEAM', 'CONFIG_CMD_AVB', 'CONFIG_MW_EEPROM', 'CONFIG_SHA1_CHECK_UB_IMG', 'CONFIG_IHS_FPGA', 'CONFIG_USE_PLUGIN', 'CONFIG_VIDEO_SIMPLE', 'CONFIG_CLK_VEXPRESS_OSC', 'CONFIG_MIPS_TUNE_14KC', 'CONFIG_MPC83XX_SDRAM', 'CONFIG_XIP_SUPPORT', 'CONFIG_MIPS_TUNE_34KC', 'CONFIG_ALTERA_UART', 'CONFIG_LOAD_FIT', 'CONFIG_RTC_DS1339', 'CONFIG_ENV_SUPPORT', 'CONFIG_DEFAULT_ENV_FILE', 'CONFIG_TPM_ST33ZP24_I2C', 'CONFIG_PCH_SUPPORT', 'CONFIG_UBOOT_PAD_TO', 'CONFIG_LYNXKDI', 'CONFIG_CMD_SMC', 'CONFIG_BOOTCOUNT_AT91', 'CONFIG_OF_PLATDATA', 'CONFIG_CONSOLE_TRUETYPE_NIMBUS', 'CONFIG_S6E8AX0', 'CONFIG_FPGA_ACEX1K', 'CONFIG_MVEBU_EFUSE', 'CONFIG_CONSOLE_TRUETYPE_RUFSCRIPT', 'CONFIG_XILINX_MICROBLAZE0_HW_VER', 'CONFIG_CONSOLE_TRUETYPE_ANKACODER', 'CONFIG_RTC_M41T60', 'CONFIG_CMD_ZIP', 'CONFIG_USB_SUPPORT', 'CONFIG_SPI_FLASH_SUPPORT', 'CONFIG_FLASH_PIC32', 'CONFIG_SAVEENV', 'CONFIG_FPGA_STRATIX_II', 'CONFIG_TEE', 'CONFIG_PIC32_SPI', 'CONFIG_FAT_SUPPORT', 'CONFIG_SERIAL_SUPPORT', 'CONFIG_RTC_DS174x', 'CONFIG_RTC_RS5C372A', 'CONFIG_DM_DEBUG', 'CONFIG_DISPLAY_ROCKCHIP_LVDS', 'CONFIG_CMD_ZYNQ_RSA', 'CONFIG_VEXPRESS_CONFIG', 'CONFIG_SPI_SUPPORT', 'CONFIG_POWER_BATTERY_TRATS2', 'CONFIG_CS8900', 'CONFIG_DRIVERS_MISC_SUPPORT', 'CONFIG_YMODEM_SUPPORT', 'CONFIG_MPC83XX_SERDES', 'CONFIG_NAND_KB9202', 'CONFIG_PL022_SPI', 'CONFIG_RTC_PCF2127', 'CONFIG_ARMV8_PSCI', 'CONFIG_KALLSYMS', 'CONFIG_LAN91C96', 'CONFIG_SHELL', 'CONFIG_SOC_DM646X', 'CONFIG_HASH_SUPPORT', 'CONFIG_ARMADA_39X', 'CONFIG_CMD_STRINGS', 'CONFIG_ARCH_RV32I', 'CONFIG_RTC_M48T35A', 'CONFIG_DATAFLASH_MMC_SELECT', 'CONFIG_UPDATE_TFTP', 'CONFIG_CPU_SA1100', 'CONFIG_NAND_PLAT', 'CONFIG_GPIO_SUPPORT', 'CONFIG_RTC_DS1306', 'CONFIG_LOG_TEST', 'CONFIG_IHS_AXI', 'CONFIG_XWAY_SWAP_BYTES', 'CONFIG_CPU_SH4', 'CONFIG_RTC_MAX6900', 'CONFIG_TEGRA210_QSPI', 'CONFIG_SYS_I2C_VERSATILE', 'CONFIG_PCI_SUPPORT', 'CONFIG_SPI_LOAD', 'CONFIG_NAND_FSL_UPM', 'CONFIG_RTC_DS1556', 'CONFIG_DRIVER_AX88180', 'CONFIG_E1000_SPI', 'CONFIG_ONENAND_U_BOOT', 'CONFIG_CMD_TERMINAL', 'CONFIG_MODULES', 'CONFIG_ONENAND_SUPPORT', 'CONFIG_SH_SDHI', 'CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED', 'CONFIG_BUILD', 'CONFIG_VIDEO_ARM_MALIDP', 'CONFIG_POWER_BATTERY_TRATS', 'CONFIG_DRIVER_SMC911X', 'CONFIG_UBI', 'CONFIG_MMC_SDHCI_SPEAR', 'CONFIG_USB_OHCI_DA8XX', 'CONFIG_UDP_FUNCTION_FASTBOOT', 'CONFIG_EXT_SUPPORT', 'CONFIG_USB_EHCI_FARADAY', 'CONFIG_TARGET_AXS103', 'CONFIG_PHY_MSCC', 'CONFIG_FTPCI100', 'CONFIG_PCIE_INTEL_FPGA', 'CONFIG_IO', 'CONFIG_SECURED_MODE_CSK_INDEX', 'CONFIG_SYSRESET_MCP83XX', 'CONFIG_BOOTROM_SUPPORT', 'CONFIG_POWER_MUIC_MAX77693', 'CONFIG_MMC_SUPPORT', 'CONFIG_LOGICORE_DP_TX', 'CONFIG_GDSYS_IOEP', 'CONFIG_XILINX_M
Re: [U-Boot] [PATCH] poplar: fix boot failure caused by serial driver change
Hi Shawn,
On Wed, Dec 12, 2018 at 3:25 PM Shawn Guo wrote:
>
> Commit 4687919684e0 ("serial: Remove DM_FLAG_PRE_RELOC flag in various
> drivers") essentially drops flag DM_FLAG_PRE_RELOC from serial_pl01x
> driver for Poplar platform, because the platform falls into the
> following strategy category made by the commit.
>
> Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
> drivers that support both statically declared devices and
> configuration from device tree
>
> Before the commit lands, Poplar platform works by statically declaring
> pl011 serial device via U_BOOT_DEVICE() with DM_FLAG_PRE_RELOC flag set
> in the driver. But since Poplar also supports device configuration from
> device tree, the commit practically drops the flag for Poplar, and hence
> breaks the platform from booting.
>
> This patch changes platform code and device tree to initiate pl011
> serial device from device tree rather than static declaration, so that
> above strategy about DM_FLAG_PRE_RELOC applies to Poplar, and therefore
> the reported boot failure gets fixed.
>
> Reported-by: Igor Opaniuk
> Fixes: 4687919684e0 ("serial: Remove DM_FLAG_PRE_RELOC flag in various
> drivers")
> Cc: Bin Meng
> Cc: Simon Glass
> Signed-off-by: Shawn Guo
> ---
> arch/arm/dts/hi3798cv200-u-boot.dtsi | 10 ++
> board/hisilicon/poplar/poplar.c | 2 ++
> 2 files changed, 4 insertions(+), 8 deletions(-)
>
Thanks for the fix! It looks good to me.
Reviewed-by: Bin Meng
Regards,
Bin
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Re: [U-Boot] [RFC PATCH] usb: composite: Fix max packet size for USB3.0
On 12/12/2018 12:49 PM, Siva Durga Prasad Paladugu wrote:
> For USB3.0 the max packetsize for GET_DESCRIPTOR should be
> sent as exponent value for 2. This means for 512, max packet
> size should be filled with 9(2^9=512). Also, fill the USB
> version field with 3.0 if speed is negotiated to Superspeed.
> This fixes the issue of DFU gadget download failure with
> superspeed. With out this patch, the max packet size is
> overflowed to zero as the bMaxPacketsize is of u8 and hence
> host is not able to detect this device.
>
> Signed-off-by: Siva Durga Prasad Paladugu
CCing Bin, I'd like his AB/RB.
> ---
> drivers/usb/gadget/composite.c | 17 +++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
> index 5106cc5..c7e7623 100644
> --- a/drivers/usb/gadget/composite.c
> +++ b/drivers/usb/gadget/composite.c
> @@ -735,8 +735,21 @@ composite_setup(struct usb_gadget *gadget, const struct
> usb_ctrlrequest *ctrl)
> case USB_DT_DEVICE:
> cdev->desc.bNumConfigurations =
> count_configs(cdev, USB_DT_DEVICE);
> - cdev->desc.bMaxPacketSize0 =
> - cdev->gadget->ep0->maxpacket;
> +
> + /*
> + * If the speed is Super speed, then the supported
> + * max packet size is 512 and it should be sent as
> + * exponent of 2. So, 9(2^9=512) should be filled in
> + * bMaxPacketSize0. Also fill USB version as 3.0
> + * if speed is Super speed.
> + */
> + if (cdev->gadget->speed == USB_SPEED_SUPER) {
> + cdev->desc.bMaxPacketSize0 = 9;
> + cdev->desc.bcdUSB = cpu_to_le16(0x0300);
> + } else {
> + cdev->desc.bMaxPacketSize0 =
> + cdev->gadget->ep0->maxpacket;
> + }
> value = min(w_length, (u16) sizeof cdev->desc);
> memcpy(req->buf, &cdev->desc, value);
> break;
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [RFC PATCH] usb: composite: Fix max packet size for USB3.0
On Wed, Dec 12, 2018 at 8:54 PM Marek Vasut wrote: > > On 12/12/2018 12:49 PM, Siva Durga Prasad Paladugu wrote: > > For USB3.0 the max packetsize for GET_DESCRIPTOR should be nits: USB 3.0, packet size > > sent as exponent value for 2. This means for 512, max packet > > size should be filled with 9(2^9=512). Also, fill the USB > > version field with 3.0 if speed is negotiated to Superspeed. > > This fixes the issue of DFU gadget download failure with > > superspeed. With out this patch, the max packet size is nits: Without > > overflowed to zero as the bMaxPacketsize is of u8 and hence > > host is not able to detect this device. > > > > Signed-off-by: Siva Durga Prasad Paladugu > > CCing Bin, I'd like his AB/RB. > > > --- > > drivers/usb/gadget/composite.c | 17 +++-- > > 1 file changed, 15 insertions(+), 2 deletions(-) > > Reviewed-by: Bin Meng Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] m53menlo: fix splashfile location
After merging the boot partition into the root partition, the splashfile resides in the /boot subdirectory: update the default environment to reflect that. Signed-off-by: Olaf Mandel --- include/configs/m53menlo.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index f8a0188d93..1729a54c25 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -202,7 +202,7 @@ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"\ "netdev=eth0\0" \ "splashsource=mmc_fs\0" \ - "splashfile=usplash.bmp.gz\0" \ + "splashfile=boot/usplash.bmp.gz\0" \ "splashimage=0x8800\0" \ "splashpos=m,m\0" \ "addcons=" \ -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] m53menlo: fix addmtd cmd in default environment
The original definition added the string mtdparts= to the Linux Kernel
args twice: mtdparts=mtdparts=. Fix that.
Signed-off-by: Olaf Mandel
---
include/configs/m53menlo.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 3fca28da6b..f8a0188d93 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -212,7 +212,7 @@
"setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off\0" \
- "addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=" \
"setenv bootargs ${bootargs} ${miscargs}\0" \
"addargs=run addcons addmisc addmtd\0" \
--
2.11.0
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Re: [U-Boot] [PATCH] Drivers: USB: MUSB: Remove legacy CONFIG_USB_DA8XX
On Tue, Dec 11, 2018 at 3:51 AM Jean-Jacques Hiblot wrote:
>
>
> On 11/12/2018 10:47, Jean-Jacques Hiblot wrote:
> >
> > On 10/12/2018 20:01, Marek Vasut wrote:
> >> On 12/10/2018 05:35 PM, Adam Ford wrote:
> >>> There don't appear to be any boards enabling CONFIG_USB_DA8XX,
> >>> and there is a newer version of the MUSB driver, so let's remove
> >>> the legacy version of it.
> >>>
> >>> Signed-off-by: Adam Ford
> >> CCing Jean, I'd like his A-B/R-B.
> >> Looks good to me, so I'll pick it once I have it, thanks!
> >
> > This is good to see some code removal
>
> This could even go a bit further and remove:
>
> - drivers/usb/host/ohci-da8xx.c
>
> - arch/arm/mach-davinci/include/mach/da8xx-usb.h
>
I want to investigate these a bit. I might have a use for these two
files on the da850evm yet. I know the musb was replaced by musb-new,
so my hope is to make the legacy musb drivers go away first. In my
ideal word, I'd like to keep the da850-evm around for a bit longer, at
least until Logic PD discontinues the L138 and AM1808 system on
module. If I can reuse these drivers to bring back USB host
functionality, I'd like to keep them.
adam
>
> >
> > Thanks
> >
> >
> > Reviewed-by: Jean-Jacques Hiblot
> >
> >
> >>
> >>> diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
> >>> index 7e6be03f4a..2508b6ed0d 100644
> >>> --- a/drivers/usb/musb/Kconfig
> >>> +++ b/drivers/usb/musb/Kconfig
> >>> @@ -15,10 +15,6 @@ config USB_OMAP3
> >>> bool "Legacy MUSB OMAP3 / OMAP4"
> >>> depends on ARCH_OMAP2PLUS
> >>> -config USB_DA8XX
> >>> -bool "Legacy MUSB DA8xx/OMAP-L1x"
> >>> -depends on ARCH_DAVINCI
> >>> -
> >>> config USB_AM35X
> >>> bool"Legacy MUSB AM35x"
> >>> depends on ARCH_OMAP2PLUS && !USB_OMAP3
> >>> diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
> >>> index 1242ce1c8c..744f2cfaa2 100644
> >>> --- a/drivers/usb/musb/Makefile
> >>> +++ b/drivers/usb/musb/Makefile
> >>> @@ -6,5 +6,4 @@
> >>> obj-$(CONFIG_USB_MUSB_HCD) += musb_hcd.o musb_core.o
> >>> obj-$(CONFIG_USB_MUSB_UDC) += musb_udc.o musb_core.o
> >>> obj-$(CONFIG_USB_OMAP3) += omap3.o
> >>> -obj-$(CONFIG_USB_DA8XX) += da8xx.o
> >>> obj-$(CONFIG_USB_AM35X) += am35x.o
> >>> diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
> >>> deleted file mode 100644
> >>> index a652a7c3c1..00
> >>> --- a/drivers/usb/musb/da8xx.c
> >>> +++ /dev/null
> >>> @@ -1,127 +0,0 @@
> >>> -// SPDX-License-Identifier: GPL-2.0+
> >>> -/*
> >>> - * da8xx.c - TI's DA8xx platform specific usb wrapper functions.
> >>> - *
> >>> - * Author: Ajay Kumar Gupta
> >>> - *
> >>> - * Based on drivers/usb/musb/davinci.c
> >>> - *
> >>> - * Copyright (C) 2009 Texas Instruments Incorporated
> >>> - */
> >>> -#include
> >>> -
> >>> -#include "musb_core.h"
> >>> -#include
> >>> -
> >>> -/* MUSB platform configuration */
> >>> -struct musb_config musb_cfg = {
> >>> -.regs= (struct musb_regs *)DA8XX_USB_OTG_CORE_BASE,
> >>> -.timeout= DA8XX_USB_OTG_TIMEOUT,
> >>> -.musb_speed= 0,
> >>> -};
> >>> -
> >>> -/*
> >>> - * This function enables VBUS by driving the GPIO Bank4 Pin 15 high.
> >>> - */
> >>> -static void enable_vbus(void)
> >>> -{
> >>> -u32 value;
> >>> -
> >>> -/* configure GPIO bank4 pin 15 in output direction */
> >>> -value = readl(&davinci_gpio_bank45->dir);
> >>> -writel((value & (~DA8XX_USB_VBUS_GPIO)),
> >>> &davinci_gpio_bank45->dir);
> >>> -
> >>> -/* set GPIO bank4 pin 15 high to drive VBUS */
> >>> -value = readl(&davinci_gpio_bank45->set_data);
> >>> -writel((value | DA8XX_USB_VBUS_GPIO),
> >>> &davinci_gpio_bank45->set_data);
> >>> -}
> >>> -
> >>> -/*
> >>> - * Enable the usb0 phy. This initialization procedure is explained in
> >>> - * the DA8xx USB user guide document.
> >>> - */
> >>> -static u8 phy_on(void)
> >>> -{
> >>> -u32 timeout;
> >>> -u32 cfgchip2;
> >>> -
> >>> -cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
> >>> -
> >>> -cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN |
> >>> CFGCHIP2_OTGPWRDN |
> >>> - CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ);
> >>> -cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN |
> >>> CFGCHIP2_PHY_PLLON |
> >>> -CFGCHIP2_REFFREQ_24MHZ;
> >>> -
> >>> -writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
> >>> -
> >>> -/* wait until the usb phy pll locks */
> >>> -timeout = musb_cfg.timeout;
> >>> -while (timeout--)
> >>> -if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD)
> >>> -return 1;
> >>> -
> >>> -/* USB phy was not turned on */
> >>> -return 0;
> >>> -}
> >>> -
> >>> -/*
> >>> - * Disable the usb phy
> >>> - */
> >>> -static void phy_off(void)
> >>> -{
> >>> -u32 cfgchip2;
> >>> -
> >>> -/*
> >>> - * Power down the on-chip PHY.
> >>> - */
> >>> -cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
> >>> -cfgchip2 &= ~CFGCHIP2_PHY_PLLON;
> >>> -cfgchip2 |= CFG
[U-Boot] [PATCH v2 0/6] Add support for MIPS Creator CI20
A new round. For this new round: * Replaced infinite while loop with wait_for_bit. * Added a MAINTAINERS file. If anyone wants to co-maintain this, please let me know. This is based on top of yesterday's master (ee168783ae8) and has been tested by SD-card booting both U-Boot and Linux. Booting Linux via TFTP was also tested. Toolchain used to test: $ mips-linux-gcc -v Using built-in specs. COLLECT_GCC=mips-linux-gcc COLLECT_LTO_WRAPPER=/home/zeta/.buildman-toolchains/gcc-7.3.0-nolibc/mips-linux/bin/../libexec/gcc/mips-linux/7.3.0/lto-wrapper Target: mips-linux Configured with: /home/arnd/git/gcc/configure --target=mips-linux --enable-targets=all --prefix=/opt/crosstool/gcc-7.3.0-nolibc/mips-linux --enable-languages=c --without-headers --disable-bootstrap --disable-nls --disable-threads --disable-shared --disable-libmudflap --disable-libssp --disable-libgomp --disable-decimal-float --disable-libquadmath --disable-libatomic --disable-libcc1 --disable-libmpx --enable-checking=release Thread model: single gcc version 7.3.0 (GCC) SPL size: $ size spl/u-boot-spl textdata bss dec hex filename 9252 752 736 1074029f4 spl/u-boot-spl I've pushed a branch to https://github.com/ezequielgarcia/u-boot/tree/ci20-v2 and made sure travis passed. Note that Paul's contributions are recorded using his imgtec.com mail although it's no longer valid, and that we will rely on mailmap to map it to mips.com. It would be terrific to fit this on the next release. Thanks! Paul Burton (6): misc: Add JZ47xx efuse driver gpio: Add JZ47xx GPIO driver mmc: Add JZ47xx SD/MMC controller driver mips: Add SPL header mips: jz47xx: Add JZ4780 SoC support mips: jz47xx: Add Creator CI20 platform arch/mips/Kconfig | 7 + arch/mips/Makefile| 1 + arch/mips/dts/Makefile| 1 + arch/mips/dts/ci20.dts| 120 arch/mips/dts/jz4780.dtsi | 162 ++ arch/mips/include/asm/spl.h | 35 ++ arch/mips/mach-jz47xx/Kconfig | 26 + arch/mips/mach-jz47xx/Makefile| 7 + arch/mips/mach-jz47xx/include/mach/jz4780.h | 104 .../mach-jz47xx/include/mach/jz4780_dram.h| 457 +++ arch/mips/mach-jz47xx/jz4780/Makefile | 5 + arch/mips/mach-jz47xx/jz4780/jz4780.c | 142 + arch/mips/mach-jz47xx/jz4780/pll.c| 528 ++ arch/mips/mach-jz47xx/jz4780/sdram.c | 271 + arch/mips/mach-jz47xx/jz4780/timer.c | 238 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds | 52 ++ arch/mips/mach-jz47xx/start.S | 99 board/imgtec/ci20/Kconfig | 15 + board/imgtec/ci20/MAINTAINERS | 6 + board/imgtec/ci20/Makefile| 5 + board/imgtec/ci20/README | 10 + board/imgtec/ci20/ci20.c | 365 configs/ci20_defconfig| 47 ++ drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-jz47xx.c| 78 +++ drivers/misc/Kconfig | 6 + drivers/misc/Makefile | 1 + drivers/misc/jz4780_efuse.c | 104 drivers/mmc/Kconfig | 6 + drivers/mmc/Makefile | 1 + drivers/mmc/jz_mmc. | 0 drivers/mmc/jz_mmc.c | 489 include/configs/ci20.h| 74 +++ include/dt-bindings/clock/jz4780-cgu.h| 88 +++ 35 files changed, 3558 insertions(+) create mode 100644 arch/mips/dts/ci20.dts create mode 100644 arch/mips/dts/jz4780.dtsi create mode 100644 arch/mips/include/asm/spl.h create mode 100644 arch/mips/mach-jz47xx/Kconfig create mode 100644 arch/mips/mach-jz47xx/Makefile create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780.h create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h create mode 100644 arch/mips/mach-jz47xx/jz4780/Makefile create mode 100644 arch/mips/mach-jz47xx/jz4780/jz4780.c create mode 100644 arch/mips/mach-jz47xx/jz4780/pll.c create mode 100644 arch/mips/mach-jz47xx/jz4780/sdram.c create mode 100644 arch/mips/mach-jz47xx/jz4780/timer.c create mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds create mode 100644 arch/mips/mach-jz47xx/start.S create mode 100644 board/imgtec/ci20/Kconfig create mode 100644 board/imgtec/ci20/MAINTAINERS create mode 100644 board/imgtec/ci20/Makefile create mode 100644 board/imgtec/ci20/README create mode 100644 board/imgtec/ci20/ci20.c create mode 100644 configs/ci20_defconfig create mode 100644 drivers/gpio/gpio-jz47xx.c create mode 100644 drivers/misc/jz4780_efuse.c create mode 100644 drivers/mmc/jz_mmc.
[U-Boot] [PATCH v2 1/6] misc: Add JZ47xx efuse driver
From: Paul Burton
Add driver for the efuse block in the JZ47xx SOC.
Cc: Daniel Schwierzeck
Signed-off-by: Paul Burton
Signed-off-by: Marek Vasut
Signed-off-by: Ezequiel Garcia
Reviewed-by: Marek Vasut
---
drivers/misc/Kconfig| 6 +++
drivers/misc/Makefile | 1 +
drivers/misc/jz4780_efuse.c | 104
3 files changed, 111 insertions(+)
create mode 100644 drivers/misc/jz4780_efuse.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 48febc47d263..704c8dd1955f 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -120,6 +120,12 @@ config FSL_SEC_MON
Security Monitor can be transitioned on any security failures,
like software violations or hardware security violations.
+config JZ4780_EFUSE
+ bool "Ingenic JZ4780 eFUSE support"
+ depends on ARCH_JZ47XX
+ help
+ This selects support for the eFUSE on Ingenic JZ4780 SoCs.
+
config MXC_OCOTP
bool "Enable MXC OCOTP Driver"
help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 302d44159274..6bdf5054f475 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -62,3 +62,4 @@ obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o
obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
+obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
diff --git a/drivers/misc/jz4780_efuse.c b/drivers/misc/jz4780_efuse.c
new file mode 100644
index ..7b327f54b15c
--- /dev/null
+++ b/drivers/misc/jz4780_efuse.c
@@ -0,0 +1,104 @@
+/*
+ * JZ4780 EFUSE driver
+ *
+ * Copyright (c) 2014 Imagination Technologies
+ * Author: Alex Smith
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define EFUSE_EFUCTRL 0xd0
+#define EFUSE_EFUCFG 0xd4
+#define EFUSE_EFUSTATE 0xd8
+#define EFUSE_EFUDATA(n) (0xdc + ((n) * 4))
+
+#define EFUSE_EFUCTRL_RD_ENBIT(0)
+#define EFUSE_EFUCTRL_LEN_BIT 16
+#define EFUSE_EFUCTRL_LEN_MASK 0x1f
+#define EFUSE_EFUCTRL_ADDR_BIT 21
+#define EFUSE_EFUCTRL_ADDR_MASK0x1ff
+#define EFUSE_EFUCTRL_CS BIT(30)
+
+#define EFUSE_EFUCFG_RD_STROBE_BIT 16
+#define EFUSE_EFUCFG_RD_STROBE_MASK0xf
+#define EFUSE_EFUCFG_RD_ADJ_BIT20
+#define EFUSE_EFUCFG_RD_ADJ_MASK 0xf
+
+#define EFUSE_EFUSTATE_RD_DONE BIT(0)
+
+static void jz4780_efuse_read_chunk(size_t addr, size_t count, u8 *buf)
+{
+ void __iomem *regs = (void __iomem *)NEMC_BASE;
+ size_t i;
+ u32 val;
+ int ret;
+
+ val = EFUSE_EFUCTRL_RD_EN |
+ ((count - 1) << EFUSE_EFUCTRL_LEN_BIT) |
+ (addr << EFUSE_EFUCTRL_ADDR_BIT) |
+ ((addr > 0x200) ? EFUSE_EFUCTRL_CS : 0);
+ writel(val, regs + EFUSE_EFUCTRL);
+
+ ret = wait_for_bit_le32(regs + EFUSE_EFUSTATE,
+ EFUSE_EFUSTATE_RD_DONE, true, 1, false);
+ if (ret)
+ return;
+
+ if ((count % 4) == 0) {
+ for (i = 0; i < count / 4; i++) {
+ val = readl(regs + EFUSE_EFUDATA(i));
+ put_unaligned(val, (u32 *)(buf + (i * 4)));
+ }
+ } else {
+ val = readl(regs + EFUSE_EFUDATA(0));
+ if (count > 2)
+ buf[2] = (val >> 16) & 0xff;
+ if (count > 1)
+ buf[1] = (val >> 8) & 0xff;
+ buf[0] = val & 0xff;
+ }
+}
+
+static inline int jz4780_efuse_chunk_size(size_t count)
+{
+ if (count >= 32)
+ return 32;
+ else if ((count / 4) > 0)
+ return (count / 4) * 4;
+ else
+ return count % 4;
+}
+
+void jz4780_efuse_read(size_t addr, size_t count, u8 *buf)
+{
+ size_t chunk;
+
+ while (count > 0) {
+ chunk = jz4780_efuse_chunk_size(count);
+ jz4780_efuse_read_chunk(addr, chunk, buf);
+ addr += chunk;
+ buf += chunk;
+ count -= chunk;
+ }
+}
+
+void jz4780_efuse_init(u32 ahb2_rate)
+{
+ void __iomem *regs = (void __iomem *)NEMC_BASE;
+ u32 rd_adj, rd_strobe, tmp;
+
+ rd_adj = (((6500 * (ahb2_rate / 100)) / 100) + 0xf) / 2;
+ tmp = (((35000 * (ahb2_rate / 100)) / 100) - 4) - rd_adj;
+ rd_strobe = ((tmp + 0xf) / 2 < 7) ? 7 : (tmp + 0xf) / 2;
+
+ tmp = (rd_adj << EFUSE_EFUCFG_RD_ADJ_BIT) |
+ (rd_strobe << EFUSE_EFUCFG_RD_STROBE_BIT);
+ writel(tmp, regs + EFUSE_EFUCFG);
+}
--
2.20.0.rc2
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[U-Boot] [PATCH v2 2/6] gpio: Add JZ47xx GPIO driver
From: Paul Burton
Add primitive GPIO controller driver for the JZ47xx SoC.
Cc: Daniel Schwierzeck
Signed-off-by: Paul Burton
Signed-off-by: Marek Vasut
Reviewed-by: Marek Vasut
---
drivers/gpio/Kconfig | 7
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-jz47xx.c | 78 ++
3 files changed, 86 insertions(+)
create mode 100644 drivers/gpio/gpio-jz47xx.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 35344e57c6c6..46c161c99ce9 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -322,4 +322,11 @@ config MT7621_GPIO
help
Say yes here to support MediaTek MT7621 compatible GPIOs.
+config JZ47XX_GPIO
+ bool "Ingenic JZ47xx GPIO driver"
+ depends on ARCH_JZ47XX
+ default y
+ help
+ Supports GPIO access on Ingenic JZ47xx SoCs.
+
endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 7ed9a4ec4221..92310e9ba934 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -59,3 +59,4 @@ obj-$(CONFIG_MSM_GPIO)+= msm_gpio.o
obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
+obj-$(CONFIG_JZ47XX_GPIO) += gpio-jz47xx.o
diff --git a/drivers/gpio/gpio-jz47xx.c b/drivers/gpio/gpio-jz47xx.c
new file mode 100644
index ..565108192306
--- /dev/null
+++ b/drivers/gpio/gpio-jz47xx.c
@@ -0,0 +1,78 @@
+/*
+ * Ingenic JZ47xx GPIO
+ *
+ * Copyright (C) 2018 Marek Vasut
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+int gpio_get_value(unsigned gpio)
+{
+ void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+ int port = gpio / 32;
+ int pin = gpio % 32;
+
+ return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin);
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+ int port = gpio / 32;
+ int pin = gpio % 32;
+
+ if (value)
+ writel(BIT(pin), gpio_regs + GPIO_PXPAT0S(port));
+ else
+ writel(BIT(pin), gpio_regs + GPIO_PXPAT0C(port));
+
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+ int port = gpio / 32;
+ int pin = gpio % 32;
+
+ writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
+ writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
+ writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port));
+
+ return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+ int port = gpio / 32;
+ int pin = gpio % 32;
+
+ writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
+ writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
+ writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port));
+
+ gpio_set_value(gpio, value);
+
+ return 0;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ int port = gpio / 32;
+
+ if (port >= 6)
+ return -EINVAL;
+
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
--
2.20.0.rc2
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[U-Boot] [PATCH v2 6/6] mips: jz47xx: Add Creator CI20 platform
From: Paul Burton
Add support for the Creator CI20 platform based on the JZ4780 SoC.
Cc: Daniel Schwierzeck
Signed-off-by: Paul Burton
Signed-off-by: Marek Vasut
Signed-off-by: Ezequiel Garcia
Reviewed-by: Marek Vasut
---
arch/mips/dts/Makefile| 1 +
arch/mips/dts/ci20.dts| 120 +++
arch/mips/mach-jz47xx/Kconfig | 11 +
board/imgtec/ci20/Kconfig | 15 ++
board/imgtec/ci20/MAINTAINERS | 6 +
board/imgtec/ci20/Makefile| 5 +
board/imgtec/ci20/README | 10 +
board/imgtec/ci20/ci20.c | 365 ++
configs/ci20_defconfig| 47 +
include/configs/ci20.h| 74 +++
10 files changed, 654 insertions(+)
create mode 100644 arch/mips/dts/ci20.dts
create mode 100644 board/imgtec/ci20/Kconfig
create mode 100644 board/imgtec/ci20/MAINTAINERS
create mode 100644 board/imgtec/ci20/Makefile
create mode 100644 board/imgtec/ci20/README
create mode 100644 board/imgtec/ci20/ci20.c
create mode 100644 configs/ci20_defconfig
create mode 100644 include/configs/ci20.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index b447141f8717..647d2bf0d53b 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -16,6 +16,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f...@st1704.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
+dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
targets += $(dtb-y)
diff --git a/arch/mips/dts/ci20.dts b/arch/mips/dts/ci20.dts
new file mode 100644
index ..934d9e96d24d
--- /dev/null
+++ b/arch/mips/dts/ci20.dts
@@ -0,0 +1,120 @@
+/dts-v1/;
+
+#include "jz4780.dtsi"
+
+/ {
+ compatible = "img,ci20", "ingenic,jz4780";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ };
+
+ chosen {
+ stdout-path = "serial4:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x1000
+ 0x3000 0x3000>;
+ };
+};
+
+&ext {
+ clock-frequency = <4800>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&nemc {
+ status = "okay";
+
+ nandc: nand-controller@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ingenic,bch-controller = <&bch>;
+
+ ingenic,nemc-tAS = <10>;
+ ingenic,nemc-tAH = <5>;
+ ingenic,nemc-tBP = <10>;
+ ingenic,nemc-tAW = <15>;
+ ingenic,nemc-tSTRV = <100>;
+
+ nand@1 {
+ reg = <1>;
+
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x0 0x0 0x80>;
+ };
+
+ partition@0x80 {
+ label = "u-boot";
+ reg = <0x0 0x80 0x0 0x20>;
+ };
+
+ partition@0xa0 {
+ label = "u-boot-env";
+ reg = <0x0 0xa0 0x0 0x20>;
+ };
+
+ partition@0xc0 {
+ label = "boot";
+ reg = <0x0 0xc0 0x0 0x400>;
+ };
+
+ partition@0x8c0 {
+ label = "system";
+ reg = <0x0 0x4c0 0x1 0xfb40>;
+ };
+ };
+ };
+ };
+};
+
+&bch {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ max-frequency = <5000>;
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ max-frequency = <5000>;
+ status = "okay";
+};
diff --git a/arch/mips/mach-jz47xx/Kconfig b/arch/mips/mach-jz47xx/Kconfig
index cd6944cfc252..dcaac0162866 100644
--- a/arch/mips/mach-jz47xx/Kconfig
+++ b/arc
[U-Boot] [PATCH v2 4/6] mips: Add SPL header
From: Paul Burton
Add header with SPL boot mode and type definitions.
Cc: Daniel Schwierzeck
Signed-off-by: Paul Burton
Signed-off-by: Marek Vasut
Reviewed-by: Marek Vasut
---
arch/mips/include/asm/spl.h | 35 +++
1 file changed, 35 insertions(+)
create mode 100644 arch/mips/include/asm/spl.h
diff --git a/arch/mips/include/asm/spl.h b/arch/mips/include/asm/spl.h
new file mode 100644
index ..01baab606606
--- /dev/null
+++ b/arch/mips/include/asm/spl.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments,
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef_ASM_SPL_H_
+#define_ASM_SPL_H_
+
+enum {
+ BOOT_DEVICE_RAM,
+ BOOT_DEVICE_MMC1,
+ BOOT_DEVICE_MMC2,
+ BOOT_DEVICE_MMC2_2,
+ BOOT_DEVICE_NAND,
+ BOOT_DEVICE_ONENAND,
+ BOOT_DEVICE_NOR,
+ BOOT_DEVICE_UART,
+ BOOT_DEVICE_SPI,
+ BOOT_DEVICE_USB,
+ BOOT_DEVICE_SATA,
+ BOOT_DEVICE_I2C,
+ BOOT_DEVICE_BOARD,
+ BOOT_DEVICE_NONE
+};
+
+/* Linker symbols. */
+extern char __bss_start[];
+extern ulong __bss_end;
+
+#ifndef CONFIG_DM
+extern gd_t gdata;
+#endif
+
+#endif
--
2.20.0.rc2
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[U-Boot] [PATCH v2 3/6] mmc: Add JZ47xx SD/MMC controller driver
From: Paul Burton Add driver for the JZ47xx MSC controller. Cc: Daniel Schwierzeck Signed-off-by: Paul Burton Signed-off-by: Marek Vasut Signed-off-by: Ezequiel Garcia Reviewed-by: Marek Vasut --- drivers/mmc/Kconfig | 6 + drivers/mmc/Makefile | 1 + drivers/mmc/jz_mmc. | 0 drivers/mmc/jz_mmc.c | 489 +++ 4 files changed, 496 insertions(+) create mode 100644 drivers/mmc/jz_mmc. create mode 100644 drivers/mmc/jz_mmc.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index fbd13964a084..496b2cba6405 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -332,6 +332,12 @@ config MMC_BCM2835 If unsure, say N. +config JZ47XX_MMC + bool "Ingenic JZ47xx SD/MMC Host Controller support" + depends on ARCH_JZ47XX + help + This selects support for the SD Card Controller on Ingenic JZ47xx SoCs. + config MMC_SANDBOX bool "Sandbox MMC support" depends on SANDBOX diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 801a26d82192..7892c468f05c 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_SH_SDHI) += sh_sdhi.o obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o +obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o # SDHCI obj-$(CONFIG_MMC_SDHCI)+= sdhci.o diff --git a/drivers/mmc/jz_mmc. b/drivers/mmc/jz_mmc. new file mode 100644 index ..e69de29bb2d1 diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c new file mode 100644 index ..2e92fa16e6c8 --- /dev/null +++ b/drivers/mmc/jz_mmc.c @@ -0,0 +1,489 @@ +/* + * Ingenic JZ MMC driver + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Registers */ +#define MSC_STRPCL 0x000 +#define MSC_STAT 0x004 +#define MSC_CLKRT 0x008 +#define MSC_CMDAT 0x00c +#define MSC_RESTO 0x010 +#define MSC_RDTO 0x014 +#define MSC_BLKLEN 0x018 +#define MSC_NOB0x01c +#define MSC_SNOB 0x020 +#define MSC_IMASK 0x024 +#define MSC_IREG 0x028 +#define MSC_CMD0x02c +#define MSC_ARG0x030 +#define MSC_RES0x034 +#define MSC_RXFIFO 0x038 +#define MSC_TXFIFO 0x03c +#define MSC_LPM0x040 +#define MSC_DMAC 0x044 +#define MSC_DMANDA 0x048 +#define MSC_DMADA 0x04c +#define MSC_DMALEN 0x050 +#define MSC_DMACMD 0x054 +#define MSC_CTRL2 0x058 +#define MSC_RTCNT 0x05c +#define MSC_DBG0x0fc + +/* MSC Clock and Control Register (MSC_STRPCL) */ +#define MSC_STRPCL_EXIT_MULTIPLE BIT(7) +#define MSC_STRPCL_EXIT_TRANSFER BIT(6) +#define MSC_STRPCL_START_READWAIT BIT(5) +#define MSC_STRPCL_STOP_READWAIT BIT(4) +#define MSC_STRPCL_RESET BIT(3) +#define MSC_STRPCL_START_OPBIT(2) +#define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0) +#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1) + +/* MSC Status Register (MSC_STAT) */ +#define MSC_STAT_AUTO_CMD_DONE BIT(31) +#define MSC_STAT_IS_RESETTING BIT(15) +#define MSC_STAT_SDIO_INT_ACTIVE BIT(14) +#define MSC_STAT_PRG_DONE BIT(13) +#define MSC_STAT_DATA_TRAN_DONEBIT(12) +#define MSC_STAT_END_CMD_RES BIT(11) +#define MSC_STAT_DATA_FIFO_AFULL BIT(10) +#define MSC_STAT_IS_READWAIT BIT(9) +#define MSC_STAT_CLK_ENBIT(8) +#define MSC_STAT_DATA_FIFO_FULLBIT(7) +#define MSC_STAT_DATA_FIFO_EMPTY BIT(6) +#define MSC_STAT_CRC_RES_ERR BIT(5) +#define MSC_STAT_CRC_READ_ERRORBIT(4) +#define MSC_STAT_CRC_WRITE_ERROR BIT(2) +#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4) +#define MSC_STAT_TIME_OUT_RES BIT(1) +#define MSC_STAT_TIME_OUT_READ BIT(0) + +/* MSC Bus Clock Control Register (MSC_CLKRT) */ +#define MSC_CLKRT_CLK_RATE_MASK0x7 + +/* MSC Command Sequence Control Register (MSC_CMDAT) */ +#define MSC_CMDAT_IO_ABORT BIT(11) +#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9) +#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9) +#define MSC_CMDAT_DMA_EN BIT(8) +#define MSC_CMDAT_INIT BIT(7) +#define MSC_CMDAT_BUSY BIT(6) +#define MSC_CMDAT_STREAM_BLOCK BIT(5) +#d
[U-Boot] [PATCH v2 5/6] mips: jz47xx: Add JZ4780 SoC support
From: Paul Burton
Add initial support for the Ingenic JZ47xx MIPS SoC.
Cc: Daniel Schwierzeck
Signed-off-by: Paul Burton
Signed-off-by: Marek Vasut
Signed-off-by: Ezequiel Garcia
Reviewed-by: Marek Vasut
---
arch/mips/Kconfig | 7 +
arch/mips/Makefile| 1 +
arch/mips/dts/jz4780.dtsi | 162 ++
arch/mips/mach-jz47xx/Kconfig | 15 +
arch/mips/mach-jz47xx/Makefile| 7 +
arch/mips/mach-jz47xx/include/mach/jz4780.h | 104
.../mach-jz47xx/include/mach/jz4780_dram.h| 457 +++
arch/mips/mach-jz47xx/jz4780/Makefile | 5 +
arch/mips/mach-jz47xx/jz4780/jz4780.c | 142 +
arch/mips/mach-jz47xx/jz4780/pll.c| 528 ++
arch/mips/mach-jz47xx/jz4780/sdram.c | 271 +
arch/mips/mach-jz47xx/jz4780/timer.c | 238
arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds | 52 ++
arch/mips/mach-jz47xx/start.S | 99
include/dt-bindings/clock/jz4780-cgu.h| 88 +++
15 files changed, 2176 insertions(+)
create mode 100644 arch/mips/dts/jz4780.dtsi
create mode 100644 arch/mips/mach-jz47xx/Kconfig
create mode 100644 arch/mips/mach-jz47xx/Makefile
create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780.h
create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
create mode 100644 arch/mips/mach-jz47xx/jz4780/Makefile
create mode 100644 arch/mips/mach-jz47xx/jz4780/jz4780.c
create mode 100644 arch/mips/mach-jz47xx/jz4780/pll.c
create mode 100644 arch/mips/mach-jz47xx/jz4780/sdram.c
create mode 100644 arch/mips/mach-jz47xx/jz4780/timer.c
create mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
create mode 100644 arch/mips/mach-jz47xx/start.S
create mode 100644 include/dt-bindings/clock/jz4780-cgu.h
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1b1b1d7d0031..44b25460b8cc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -88,6 +88,12 @@ config ARCH_MT7620
select SUPPORTS_LITTLE_ENDIAN
select SYSRESET
+config ARCH_JZ47XX
+ bool "Support Ingenic JZ47xx"
+ select SUPPORT_SPL
+ select OF_CONTROL
+ select DM
+
config MACH_PIC32
bool "Support Microchip PIC32"
select DM
@@ -139,6 +145,7 @@ source "board/micronas/vct/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
source "arch/mips/mach-bmips/Kconfig"
+source "arch/mips/mach-jz47xx/Kconfig"
source "arch/mips/mach-pic32/Kconfig"
source "arch/mips/mach-mt7620/Kconfig"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 802244a06e5d..a294e9b1e8b9 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -13,6 +13,7 @@ libs-y += arch/mips/lib/
machine-$(CONFIG_ARCH_ATH79) += ath79
machine-$(CONFIG_ARCH_BMIPS) += bmips
+machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
machine-$(CONFIG_MACH_PIC32) += pic32
machine-$(CONFIG_ARCH_MT7620) += mt7620
diff --git a/arch/mips/dts/jz4780.dtsi b/arch/mips/dts/jz4780.dtsi
new file mode 100644
index ..e34f8d359036
--- /dev/null
+++ b/arch/mips/dts/jz4780.dtsi
@@ -0,0 +1,162 @@
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ingenic,jz4780";
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ intc: interrupt-controller@10001000 {
+ compatible = "ingenic,jz4780-intc";
+ reg = <0x10001000 0x50>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ ext: ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ rtc: rtc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ cgu: jz4780-cgu@1000 {
+ compatible = "ingenic,jz4780-cgu";
+ reg = <0x1000 0x100>;
+
+ clocks = <&ext>, <&rtc>;
+ clock-names = "ext", "rtc";
+
+ #clock-cells = <1>;
+ };
+
+ mmc0: mmc@1345 {
+ compatible = "ingenic,jz4780-mmc";
+ reg = <0x1345 0x1000>;
+
+ status = "disabled";
+
+ clocks = <&cgu JZ4780_CLK_MSC0>;
+ clock-names = "mmc";
+ };
+
+ mmc1: mmc@1346 {
+ compatible = "ingenic,jz4780-mmc";
+ reg = <0x1346 0x1000>;
+
+ clocks = <&cgu JZ4780_CLK_MSC1>;
+ clock-names = "mmc";
+
+ status = "disabled";
+ };
+
+ uart0: serial@1003 {
+ compatible = "ingenic,jz4780-uart";
+
[U-Boot] [PATCH v5 00/25] riscv: Adding RISC-V CPU and timer driver
This adds DM drivers to support RISC-V CPU and timer, plus some bug fixes. This series is available at u-boot-x86/riscv-working for testing. Changes in v5: - Introduced another Kconfig option for the cache ops on AX25 CPU, so that it remains selectable in Kconfig menu, but only visible to AX25 platform. - check if dev is valid, otherwise print a warning Changes in v4: - print warnings for S-mode without CONFIG_CPU Changes in v3: - remove 'select RISCV_CLINT' in Kconfig - do not mention the spec version number v1.10 - adjust riscv_get_time() API signature to have a return value - check return value of syscon_get_first_range() - probe cpus in the pre-relocation stage too - new patch to remove non-DM version of print_cpuinfo() - add sedeleg (0x102) and sideleg (0x103) CSRs - new patch to update supports_extension() to use desc from cpu driver - only initialize mcounteren CSR for S-mode - only touch satp in M-mode U-Boot - move the implementation to arch_cpu_init_dm() - new patch to save boot hart id to the global data - new patch to change to use boot_hart from global data - new patch to remove ae350.dts Changes in v2: - Use 'Hz' instead of 'HZ' - add DM_FLAG_PRE_RELOC flag to the simple-bus driver - pass NULL as the timer device to device_bind_with_driver_data() - remove the probe to syscon driver in the timer probe, to make the driver generic, and rely on platform codes to provide the API riscv_get_time(). - incorporated and reworked Anup's S-mode timer patch @ http://patchwork.ozlabs.org/patch/1006663/ - rename the driver name to sifive_clint - save the clint base address to arch specific global data to support pre-relocation stage - remove the probe routine - add riscv_clear_ipi() API - incorporated and reworked Anup's S-mode timer patch @ http://patchwork.ozlabs.org/patch/1006663/ - add CMD_CPU as well - move to arch/riscv/cpu/cpu.c - new patch to add indirect stringification to csr_xxx ops - use csr_set() to set MSTATUS_FS - only enabling the cycle, time, and instret counters - change to use satp - rebase on u-boot/master - drop the patch "riscv: Pass correct exception code to _exit_trap()" - drop the patch "riscv: Refactor handle_trap() a little for future extension" - drop the patch "riscv: Allow U-Boot to run on hart 0 only", and leave the SMP support to Lukas's future patch series Anup Patel (2): riscv: Introduce a Kconfig option for machine mode riscv: Implement riscv_get_time() API using rdtime instruction Bin Meng (22): dm: cpu: Add timebase frequency to the platdata riscv: qemu: Create a simple-bus driver for the soc node cpu: Add a RISC-V CPU driver timer: Add generic driver for RISC-V privileged architecture defined timer riscv: ax25: Hide the ax25-specific Kconfig option riscv: Add a SYSCON driver for SiFive's Core Local Interruptor riscv: qemu: Add platform-specific Kconfig options riscv: Enlarge the default SYS_MALLOC_F_LEN riscv: Probe cpus during boot riscv: Remove non-DM version of print_cpuinfo() riscv: Add CSR numbers riscv: Add exception codes for xcause register riscv: Update supports_extension() to use desc from cpu driver riscv: Add indirect stringification to csr_xxx ops riscv: Do some basic architecture level cpu initialization riscv: Move trap handler codes to mtrap.S riscv: Fix context restore before returning from trap handler riscv: Return to previous privilege level after trap handling riscv: Adjust the _exit_trap() position to come before handle_trap() riscv: Save boot hart id to the global data riscv: bootm: Change to use boot_hart from global data riscv: Remove ae350.dts Lukas Auer (1): riscv: add Kconfig entries for the code model arch/riscv/Kconfig | 60 - arch/riscv/Makefile | 9 +- arch/riscv/cpu/Makefile | 2 +- arch/riscv/cpu/ax25/Kconfig | 17 ++- arch/riscv/cpu/ax25/cache.c | 12 +- arch/riscv/cpu/cpu.c | 98 ++- arch/riscv/cpu/mtrap.S | 103 +++ arch/riscv/cpu/qemu/Kconfig | 12 ++ arch/riscv/cpu/qemu/cpu.c| 14 +++ arch/riscv/cpu/start.S | 93 +- arch/riscv/dts/ae350.dts | 229 - arch/riscv/include/asm/csr.h | 16 +-- arch/riscv/include/asm/encoding.h| 236 +++ arch/riscv/include/asm/global_data.h | 4 + arch/riscv/include/asm/syscon.h | 19 +++ arch/riscv/lib/Makefile | 2 + arch/riscv/lib/asm-offsets.c | 19 +++ arch/riscv/lib/bootm.c | 2 +- arch/riscv/lib/interrupts.c | 62 + arch/riscv/lib/rdtime.c | 38 ++ arch/riscv/lib/sifive_clint.c| 84 + board/AndesTech/ax25-ae350/Kconfig | 4 + board/emulation/qemu-riscv/Kconfig | 1 + drivers/cpu/Kconfig | 6 + drivers/cpu/Makefile
[U-Boot] [PATCH v5 02/25] dm: cpu: Add timebase frequency to the platdata
This adds a timebase_freq member to the 'struct cpu_platdata', to
hold the "timebase-frequency" value in the cpu or /cpus node.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Use 'Hz' instead of 'HZ'
include/cpu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/cpu.h b/include/cpu.h
index 367c5f4..28dd48f 100644
--- a/include/cpu.h
+++ b/include/cpu.h
@@ -14,6 +14,8 @@
* @device_id: Driver-defined device identifier
* @family:DMTF CPU Family identifier
* @id:DMTF CPU Processor identifier
+ * @timebase_freq: the current frequency at which the cpu timer timebase
+ *registers are updated (in Hz)
*
* This can be accessed with dev_get_parent_platdata() for any UCLASS_CPU
* device.
@@ -24,6 +26,7 @@ struct cpu_platdata {
ulong device_id;
u16 family;
u32 id[2];
+ u32 timebase_freq;
};
/* CPU features - mostly just a placeholder for now */
--
2.7.4
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[U-Boot] [PATCH v5 03/25] riscv: qemu: Create a simple-bus driver for the soc node
To enumerate devices on the /soc/ node, create a "simple-bus"
driver to match "riscv-virtio-soc".
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- add DM_FLAG_PRE_RELOC flag to the simple-bus driver
arch/riscv/cpu/qemu/cpu.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c
index 25d97d0..ad2950c 100644
--- a/arch/riscv/cpu/qemu/cpu.c
+++ b/arch/riscv/cpu/qemu/cpu.c
@@ -4,6 +4,7 @@
*/
#include
+#include
/*
* cleanup_before_linux() is called just before we call linux
@@ -19,3 +20,16 @@ int cleanup_before_linux(void)
return 0;
}
+
+/* To enumerate devices on the /soc/ node, create a "simple-bus" driver */
+static const struct udevice_id riscv_virtio_soc_ids[] = {
+ { .compatible = "riscv-virtio-soc" },
+ { }
+};
+
+U_BOOT_DRIVER(riscv_virtio_soc) = {
+ .name = "riscv_virtio_soc",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = riscv_virtio_soc_ids,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.7.4
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[U-Boot] [PATCH v5 01/25] riscv: add Kconfig entries for the code model
From: Lukas Auer RISC-V has two code models, medium low (medlow) and medium any (medany). Medlow limits addressable memory to a single 2 GiB range between the absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory to any single 2 GiB address range. By default, medlow is selected for U-Boot on both 32-bit and 64-bit systems. The -mcmodel compiler flag is selected according to the Kconfig configuration. Signed-off-by: Lukas Auer [bmeng: adjust to make medlow the default code model for U-Boot] Signed-off-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/riscv/Kconfig | 18 ++ arch/riscv/Makefile | 9 - 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 732a357..6d85ac9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -44,6 +44,24 @@ config ARCH_RV64I endchoice +choice + prompt "Code Model" + default CMODEL_MEDLOW + +config CMODEL_MEDLOW + bool "medium low code model" + help + U-Boot and its statically defined symbols must lie within a single 2 GiB + address range and must lie between absolute addresses -2 GiB and +2 GiB. + +config CMODEL_MEDANY + bool "medium any code model" + help + U-Boot and its statically defined symbols must be within any single 2 GiB + address range. + +endchoice + config RISCV_ISA_C bool "Emit compressed instructions" default y diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 55d7c65..0b80eb8 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -17,8 +17,15 @@ endif ifeq ($(CONFIG_RISCV_ISA_C),y) ARCH_C = c endif +ifeq ($(CONFIG_CMODEL_MEDLOW),y) + CMODEL = medlow +endif +ifeq ($(CONFIG_CMODEL_MEDANY),y) + CMODEL = medany +endif -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) +ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ +-mcmodel=$(CMODEL) PLATFORM_CPPFLAGS += $(ARCH_FLAGS) CFLAGS_EFI += $(ARCH_FLAGS) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 10/25] riscv: qemu: Add platform-specific Kconfig options
Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Anup Patel --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: - add CMD_CPU as well arch/riscv/Kconfig | 1 + arch/riscv/cpu/qemu/Kconfig| 11 +++ board/emulation/qemu-riscv/Kconfig | 1 + 3 files changed, 13 insertions(+) create mode 100644 arch/riscv/cpu/qemu/Kconfig diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7dc6e3f..39ca2d8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -22,6 +22,7 @@ source "board/emulation/qemu-riscv/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" +source "arch/riscv/cpu/qemu/Kconfig" # architecture-specific options below diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/qemu/Kconfig new file mode 100644 index 000..2e953e1 --- /dev/null +++ b/arch/riscv/cpu/qemu/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng + +config QEMU_RISCV + bool + imply CPU + imply CPU_RISCV + imply RISCV_TIMER + imply SIFIVE_CLINT if RISCV_MMODE + imply CMD_CPU diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 56bb533..ed005e5 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -18,6 +18,7 @@ config SYS_TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select QEMU_RISCV imply SYS_NS16550 imply VIRTIO_MMIO imply VIRTIO_NET -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 20/25] riscv: Fix context restore before returning from trap handler
sp cannot be loaded before restoring other registers. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Anup Patel --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/riscv/cpu/mtrap.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index a5ad558..da307e4 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -77,7 +77,6 @@ trap_entry: #endif csrs MODE_PREFIX(status), t0 LREG x1, 1 * REGBYTES(sp) - LREG x2, 2 * REGBYTES(sp) LREG x3, 3 * REGBYTES(sp) LREG x4, 4 * REGBYTES(sp) LREG x5, 5 * REGBYTES(sp) @@ -107,5 +106,6 @@ trap_entry: LREG x29, 29 * REGBYTES(sp) LREG x30, 30 * REGBYTES(sp) LREG x31, 31 * REGBYTES(sp) + LREG x2, 2 * REGBYTES(sp) addi sp, sp, 32 * REGBYTES MODE_PREFIX(ret) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 21/25] riscv: Return to previous privilege level after trap handling
At present the trap handler returns to hardcoded M-mode/S-mode. Change to returning to previous privilege level instead. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Anup Patel --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/riscv/cpu/mtrap.S | 8 1 file changed, 8 deletions(-) diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index da307e4..407ecfa 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -68,14 +68,6 @@ trap_entry: jal handle_trap csrw MODE_PREFIX(epc), a0 -#ifdef CONFIG_RISCV_SMODE - /* Remain in S-mode after sret */ - li t0, SSTATUS_SPP -#else - /* Remain in M-mode after mret */ - li t0, MSTATUS_MPP -#endif - csrs MODE_PREFIX(status), t0 LREG x1, 1 * REGBYTES(sp) LREG x3, 3 * REGBYTES(sp) LREG x4, 4 * REGBYTES(sp) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 18/25] riscv: Do some basic architecture level cpu initialization
In arch_cpu_init_dm() do some basic architecture level cpu
initialization, like FPU enable, etc.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- only initialize mcounteren CSR for S-mode
- only touch satp in M-mode U-Boot
- move the implementation to arch_cpu_init_dm()
Changes in v2:
- use csr_set() to set MSTATUS_FS
- only enabling the cycle, time, and instret counters
- change to use satp
arch/riscv/cpu/cpu.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index fc7c9b3..e662140 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
/*
@@ -61,7 +62,31 @@ static int riscv_cpu_probe(void)
int arch_cpu_init_dm(void)
{
- return riscv_cpu_probe();
+ int ret;
+
+ ret = riscv_cpu_probe();
+ if (ret)
+ return ret;
+
+ /* Enable FPU */
+ if (supports_extension('d') || supports_extension('f')) {
+ csr_set(MODE_PREFIX(status), MSTATUS_FS);
+ csr_write(fcsr, 0);
+ }
+
+ if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
+ /*
+* Enable perf counters for cycle, time,
+* and instret counters only
+*/
+ csr_write(mcounteren, GENMASK(2, 0));
+
+ /* Disable paging */
+ if (supports_extension('s'))
+ csr_write(satp, 0);
+ }
+
+ return 0;
}
int arch_early_init_r(void)
--
2.7.4
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[U-Boot] [PATCH v5 05/25] timer: Add generic driver for RISC-V privileged architecture defined timer
RISC-V privileged architecture v1.10 defines a real-time counter,
exposed as a memory-mapped machine-mode register - mtime. mtime must
run at constant frequency, and the platform must provide a mechanism
for determining the timebase of mtime. The mtime register has a
64-bit precision on all RV32, RV64, and RV128 systems.
Different platform may have different implementation of the mtime
block hence an API riscv_get_time() is required by this driver for
platform codes to hide such implementation details. For example,
on some platforms mtime is provided by the CLINT module, while on
some other platforms a simple 'rdtime' can be used to get the timer
counter.
With this timer driver the U-Boot timer functionalities like delay
works correctly now.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- remove 'select RISCV_CLINT' in Kconfig
- do not mention the spec version number v1.10
- adjust riscv_get_time() API signature to have a return value
Changes in v2:
- remove the probe to syscon driver in the timer probe, to make the
driver generic, and rely on platform codes to provide the API
riscv_get_time().
drivers/timer/Kconfig | 7 ++
drivers/timer/Makefile | 1 +
drivers/timer/riscv_timer.c | 56 +
3 files changed, 64 insertions(+)
create mode 100644 drivers/timer/riscv_timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index b0e6f32..df37a79 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -126,6 +126,13 @@ config OMAP_TIMER
help
Select this to enable an timer for Omap devices.
+config RISCV_TIMER
+ bool "RISC-V timer support"
+ depends on TIMER && RISCV
+ help
+ Select this to enable support for the timer as defined
+ by the RISC-V privileged architecture spec.
+
config ROCKCHIP_TIMER
bool "Rockchip timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index c4fbab2..d0bf218 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
+obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_SANDBOX_TIMER)+= sandbox_timer.o
obj-$(CONFIG_STI_TIMER)+= sti-timer.o
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
new file mode 100644
index 000..9f9f070
--- /dev/null
+++ b/drivers/timer/riscv_timer.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng
+ *
+ * RISC-V privileged architecture defined generic timer driver
+ *
+ * This driver relies on RISC-V platform codes to provide the essential API
+ * riscv_get_time() which is supposed to return the timer counter as defined
+ * by the RISC-V privileged architecture spec.
+ *
+ * This driver can be used in both M-mode and S-mode U-Boot.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * riscv_get_time() - get the timer counter
+ *
+ * Platform codes should provide this API in order to make this driver
function.
+ *
+ * @time: the 64-bit timer count as defined by the RISC-V privileged
+ * architecture spec.
+ * @return:0 on success, -ve on error.
+ */
+extern int riscv_get_time(u64 *time);
+
+static int riscv_timer_get_count(struct udevice *dev, u64 *count)
+{
+ return riscv_get_time(count);
+}
+
+static int riscv_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ /* clock frequency was passed from the cpu driver as driver data */
+ uc_priv->clock_rate = dev->driver_data;
+
+ return 0;
+}
+
+static const struct timer_ops riscv_timer_ops = {
+ .get_count = riscv_timer_get_count,
+};
+
+U_BOOT_DRIVER(riscv_timer) = {
+ .name = "riscv_timer",
+ .id = UCLASS_TIMER,
+ .probe = riscv_timer_probe,
+ .ops = &riscv_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.7.4
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[U-Boot] [PATCH v5 13/25] riscv: Remove non-DM version of print_cpuinfo()
With DM CPU driver, the non-DM version of print_cpuinfo() is no
longer needed.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- new patch to remove non-DM version of print_cpuinfo()
Changes in v2: None
arch/riscv/cpu/cpu.c | 37 -
1 file changed, 37 deletions(-)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 8286a0c..d3c59da 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -14,48 +14,11 @@
*/
phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
-enum {
- ISA_INVALID = 0,
- ISA_32BIT,
- ISA_64BIT,
- ISA_128BIT
-};
-
-static const char * const isa_bits[] = {
- [ISA_INVALID] = NULL,
- [ISA_32BIT] = "32",
- [ISA_64BIT] = "64",
- [ISA_128BIT] = "128"
-};
-
static inline bool supports_extension(char ext)
{
return csr_read(misa) & (1 << (ext - 'a'));
}
-int print_cpuinfo(void)
-{
- char name[32];
- char *s = name;
- int bit;
-
- s += sprintf(name, "rv");
- bit = csr_read(misa) >> (sizeof(long) * 8 - 2);
- s += sprintf(s, isa_bits[bit]);
-
- supports_extension('i') ? *s++ = 'i' : 'r';
- supports_extension('m') ? *s++ = 'm' : 'i';
- supports_extension('a') ? *s++ = 'a' : 's';
- supports_extension('f') ? *s++ = 'f' : 'c';
- supports_extension('d') ? *s++ = 'd' : '-';
- supports_extension('c') ? *s++ = 'c' : 'v';
- *s++ = '\0';
-
- printf("CPU: %s\n", name);
-
- return 0;
-}
-
static int riscv_cpu_probe(void)
{
#ifdef CONFIG_CPU
--
2.7.4
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[U-Boot] [PATCH v5 06/25] riscv: ax25: Hide the ax25-specific Kconfig option
There is no need to expose RISCV_NDS to the Kconfig menu as it is
an ax25-specific option. Introduce a dedicated Kconfig option for
the cache ops of ax25 platform and use that to guard the cache ops.
Signed-off-by: Bin Meng
---
Changes in v5:
- Introduced another Kconfig option for the cache ops on AX25 CPU,
so that it remains selectable in Kconfig menu, but only visible
to AX25 platform.
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/riscv/cpu/ax25/Kconfig| 17 -
arch/riscv/cpu/ax25/cache.c| 12 ++--
board/AndesTech/ax25-ae350/Kconfig | 4
3 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6c7022f..e9dbca2 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -1,7 +1,14 @@
config RISCV_NDS
- bool "AndeStar V5 ISA support"
- default n
+ bool
help
- Say Y here if you plan to run U-Boot on AndeStar v5
- platforms and use some specific features which are
- provided by Andes Technology AndeStar V5 Families.
+ Run U-Boot on AndeStar V5 platforms and use some specific features
+ which are provided by Andes Technology AndeStar V5 families.
+
+if RISCV_NDS
+
+config RISCV_NDS_CACHE
+ bool "AndeStar V5 families specific cache support"
+ help
+ Provide Andes Technology AndeStar V5 families specific cache support.
+
+endif
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 6600ac2..8d6ae17 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -9,7 +9,7 @@
void icache_enable(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x1\n\t"
@@ -22,7 +22,7 @@ void icache_enable(void)
void icache_disable(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence.i\n\t"
"csrr t1, mcache_ctl\n\t"
@@ -36,7 +36,7 @@ void icache_disable(void)
void dcache_enable(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x2\n\t"
@@ -49,7 +49,7 @@ void dcache_enable(void)
void dcache_disable(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence\n\t"
"csrr t1, mcache_ctl\n\t"
@@ -64,7 +64,7 @@ int icache_status(void)
{
int ret = 0;
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi %0, t1, 0x01\n\t"
@@ -81,7 +81,7 @@ int dcache_status(void)
{
int ret = 0;
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi %0, t1, 0x02\n\t"
diff --git a/board/AndesTech/ax25-ae350/Kconfig
b/board/AndesTech/ax25-ae350/Kconfig
index bb69ea3..44cb302 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -21,4 +21,8 @@ config ENV_SIZE
config ENV_OFFSET
default 0x14 if ENV_IS_IN_SPI_FLASH
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select RISCV_NDS
+
endif
--
2.7.4
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[U-Boot] [PATCH v5 09/25] riscv: Implement riscv_get_time() API using rdtime instruction
From: Anup Patel
This adds an implementation of riscv_get_time() API that is using
rdtime instruction.
This is the case for S-mode U-Boot, and is useful for processors
that support rdtime in M-mode too.
Signed-off-by: Anup Patel
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- incorporated and reworked Anup's S-mode timer patch
@ http://patchwork.ozlabs.org/patch/1006663/
arch/riscv/Kconfig | 8
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/rdtime.c | 38 ++
3 files changed, 47 insertions(+)
create mode 100644 arch/riscv/lib/rdtime.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f513f52..7dc6e3f 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -104,4 +104,12 @@ config SIFIVE_CLINT
The SiFive CLINT block holds memory-mapped control and status
registers
associated with software and timer interrupts.
+config RISCV_RDTIME
+ bool
+ default y if RISCV_SMODE
+ help
+ The provides the riscv_get_time() API that is implemented using the
+ standard rdtime instruction. This is the case for S-mode U-Boot, and
+ is useful for processors that support rdtime in M-mode too.
+
endmenu
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index b13c876..edfa616 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -9,6 +9,7 @@
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
+obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
obj-y += interrupts.o
obj-y += reset.o
diff --git a/arch/riscv/lib/rdtime.c b/arch/riscv/lib/rdtime.c
new file mode 100644
index 000..e128d7f
--- /dev/null
+++ b/arch/riscv/lib/rdtime.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Anup Patel
+ * Copyright (C) 2018, Bin Meng
+ *
+ * The riscv_get_time() API implementation that is using the
+ * standard rdtime instruction.
+ */
+
+#include
+
+/* Implement the API required by RISC-V timer driver */
+int riscv_get_time(u64 *time)
+{
+#ifdef CONFIG_64BIT
+ u64 n;
+
+ __asm__ __volatile__ (
+ "rdtime %0"
+ : "=r" (n));
+
+ *time = n;
+#else
+ u32 lo, hi, tmp;
+
+ __asm__ __volatile__ (
+ "1:\n"
+ "rdtimeh %0\n"
+ "rdtime %1\n"
+ "rdtimeh %2\n"
+ "bne %0, %2, 1b"
+ : "=&r" (hi), "=&r" (lo), "=&r" (tmp));
+
+ *time = ((u64)hi << 32) | lo;
+#endif
+
+ return 0;
+}
--
2.7.4
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[U-Boot] [PATCH v5 08/25] riscv: Add a SYSCON driver for SiFive's Core Local Interruptor
This adds U-Boot syscon driver for SiFive's Core Local Interruptor
(CLINT). The CLINT block holds memory-mapped control and status
registers associated with software and timer interrupts.
This driver implements the riscv_get_time() API as required by
the generic RISC-V timer driver, as well as some other APIs that
are needed for handling IPI.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- check return value of syscon_get_first_range()
Changes in v2:
- rename the driver name to sifive_clint
- save the clint base address to arch specific global data to support
pre-relocation stage
- remove the probe routine
- add riscv_clear_ipi() API
arch/riscv/Kconfig | 9
arch/riscv/include/asm/global_data.h | 3 ++
arch/riscv/include/asm/syscon.h | 19
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/sifive_clint.c| 84
5 files changed, 116 insertions(+)
create mode 100644 arch/riscv/include/asm/syscon.h
create mode 100644 arch/riscv/lib/sifive_clint.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 55c60e4..f513f52 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -95,4 +95,13 @@ config 32BIT
config 64BIT
bool
+config SIFIVE_CLINT
+ bool
+ depends on RISCV_MMODE
+ select REGMAP
+ select SYSCON
+ help
+ The SiFive CLINT block holds memory-mapped control and status
registers
+ associated with software and timer interrupts.
+
endmenu
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
index 4d5d623..46fcfab 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -12,6 +12,9 @@
/* Architecture-specific global data */
struct arch_global_data {
+#ifdef CONFIG_SIFIVE_CLINT
+ void __iomem *clint;/* clint base address */
+#endif
};
#include
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
new file mode 100644
index 000..d311ee6
--- /dev/null
+++ b/arch/riscv/include/asm/syscon.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng
+ */
+
+#ifndef _ASM_SYSCON_H
+#define _ASM_SYSCON_H
+
+/*
+ * System controllers in a RISC-V system
+ *
+ * So far only SiFive's Core Local Interruptor (CLINT) is defined.
+ */
+enum {
+ RISCV_NONE,
+ RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
+};
+
+#endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index b58db89..b13c876 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -9,6 +9,7 @@
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
+obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
obj-y += interrupts.o
obj-y += reset.o
obj-y += setjmp.o
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
new file mode 100644
index 000..d24e0d5
--- /dev/null
+++ b/arch/riscv/lib/sifive_clint.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng
+ *
+ * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
+ * The CLINT block holds memory-mapped control and status registers
+ * associated with software and timer interrupts.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* MSIP registers */
+#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4)
+/* mtime compare register */
+#define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8)
+/* mtime register */
+#define MTIME_REG(base)((ulong)(base) + 0xbff8)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLINT_BASE_GET(void) \
+ do {\
+ long *ret; \
+ \
+ if (!gd->arch.clint) { \
+ ret = syscon_get_first_range(RISCV_SYSCON_CLINT); \
+ if (IS_ERR(ret))\
+ return PTR_ERR(ret);\
+ gd->arch.clint = ret; \
+ } \
+ } while (0)
+
+int riscv_get_time(u64 *time)
+{
+ CLINT_BASE_GET();
+
+ *time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
+
+ return 0;
+}
+
+int riscv_set_timecmp(int hart, u64 cmp)
+{
+ CLINT_BASE_GET();
+
+ writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
+
+ return 0;
+}
+
+int riscv_send_ipi(int hart)
+{
+ CLINT_BASE_GET();
+
+ writel(1, (void __iome
[U-Boot] [PATCH v5 23/25] riscv: Save boot hart id to the global data
At present the hart id passed via a0 in the U-Boot entry is saved
to s0 at the beginning but does not preserve later. Save it to the
global data structure so that it can be used later.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- new patch to save boot hart id to the global data
Changes in v2: None
arch/riscv/cpu/start.S | 4
arch/riscv/include/asm/global_data.h | 1 +
arch/riscv/lib/asm-offsets.c | 19 +++
3 files changed, 24 insertions(+)
create mode 100644 arch/riscv/lib/asm-offsets.c
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 47c3bf0..81ea52b 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_32BIT
#define LREG lw
@@ -70,6 +71,9 @@ call_board_init_f_0:
jal board_init_f_init_reserve
+ /* save the boot hart id to global_data */
+ SREGs0, GD_BOOT_HART(gp)
+
mv a0, zero/* a0 <-- boot_flags = 0 */
la t5, board_init_f
jr t5 /* jump to board_init_f() */
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
index 46fcfab..a3a342c 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -12,6 +12,7 @@
/* Architecture-specific global data */
struct arch_global_data {
+ long boot_hart; /* boot hart id */
#ifdef CONFIG_SIFIVE_CLINT
void __iomem *clint;/* clint base address */
#endif
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
new file mode 100644
index 000..e0b71f5
--- /dev/null
+++ b/arch/riscv/lib/asm-offsets.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng
+ *
+ * From arch/x86/lib/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ */
+
+#include
+#include
+
+int main(void)
+{
+ DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+
+ return 0;
+}
--
2.7.4
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[U-Boot] [PATCH v5 22/25] riscv: Adjust the _exit_trap() position to come before handle_trap()
With this change, we can avoid a forward declaration.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- rebase on u-boot/master
- drop the patch "riscv: Pass correct exception code to _exit_trap()"
- drop the patch "riscv: Refactor handle_trap() a little for future extension"
- drop the patch "riscv: Allow U-Boot to run on hart 0 only", and
leave the SMP support to Lukas's future patch series
arch/riscv/lib/interrupts.c | 62 ++---
1 file changed, 30 insertions(+), 32 deletions(-)
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 3aff006..e185933 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -12,7 +12,36 @@
#include
#include
-static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs);
+static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
+{
+ static const char * const exception_code[] = {
+ "Instruction address misaligned",
+ "Instruction access fault",
+ "Illegal instruction",
+ "Breakpoint",
+ "Load address misaligned",
+ "Load access fault",
+ "Store/AMO address misaligned",
+ "Store/AMO access fault",
+ "Environment call from U-mode",
+ "Environment call from S-mode",
+ "Reserved",
+ "Environment call from M-mode",
+ "Instruction page fault",
+ "Load page fault",
+ "Reserved",
+ "Store/AMO page fault",
+ };
+
+ if (code < ARRAY_SIZE(exception_code)) {
+ printf("exception code: %ld , %s , epc %lx , ra %lx\n",
+ code, exception_code[code], epc, regs->ra);
+ } else {
+ printf("Reserved\n");
+ }
+
+ hang();
+}
int interrupt_init(void)
{
@@ -72,34 +101,3 @@ __attribute__((weak)) void external_interrupt(struct
pt_regs *regs)
__attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
{
}
-
-static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
-{
- static const char * const exception_code[] = {
- "Instruction address misaligned",
- "Instruction access fault",
- "Illegal instruction",
- "Breakpoint",
- "Load address misaligned",
- "Load access fault",
- "Store/AMO address misaligned",
- "Store/AMO access fault",
- "Environment call from U-mode",
- "Environment call from S-mode",
- "Reserved",
- "Environment call from M-mode",
- "Instruction page fault",
- "Load page fault",
- "Reserved",
- "Store/AMO page fault",
- };
-
- if (code < ARRAY_SIZE(exception_code)) {
- printf("exception code: %ld , %s , epc %lx , ra %lx\n",
- code, exception_code[code], epc, regs->ra);
- } else {
- printf("Reserved\n");
- }
-
- hang();
-}
--
2.7.4
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[U-Boot] [PATCH v5 14/25] riscv: Add CSR numbers
The standard RISC-V ISA sets aside a 12-bit encoding space for up to 4096 CSRs. This adds all known CSR numbers as defined in the RISC-V Privileged Architecture Version 1.10. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Anup Patel --- Changes in v5: None Changes in v4: None Changes in v3: - add sedeleg (0x102) and sideleg (0x103) CSRs Changes in v2: None arch/riscv/include/asm/encoding.h | 221 ++ 1 file changed, 221 insertions(+) diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 97cf906..05e1ce3 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -152,6 +152,227 @@ #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) +/* CSR numbers */ +#define CSR_FFLAGS 0x1 +#define CSR_FRM0x2 +#define CSR_FCSR 0x3 + +#define CSR_SSTATUS0x100 +#define CSR_SEDELEG0x102 +#define CSR_SIDELEG0x103 +#define CSR_SIE0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP0x144 +#define CSR_SATP 0x180 + +#define CSR_MSTATUS0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG0x302 +#define CSR_MIDELEG0x303 +#define CSR_MIE0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT100x32a +#define CSR_MHPMEVENT110x32b +#define CSR_MHPMEVENT120x32c +#define CSR_MHPMEVENT130x32d +#define CSR_MHPMEVENT140x32e +#define CSR_MHPMEVENT150x32f +#define CSR_MHPMEVENT160x330 +#define CSR_MHPMEVENT170x331 +#define CSR_MHPMEVENT180x332 +#define CSR_MHPMEVENT190x333 +#define CSR_MHPMEVENT200x334 +#define CSR_MHPMEVENT210x335 +#define CSR_MHPMEVENT220x336 +#define CSR_MHPMEVENT230x337 +#define CSR_MHPMEVENT240x338 +#define CSR_MHPMEVENT250x339 +#define CSR_MHPMEVENT260x33a +#define CSR_MHPMEVENT270x33b +#define CSR_MHPMEVENT280x33c +#define CSR_MHPMEVENT290x33d +#define CSR_MHPMEVENT300x33e +#define CSR_MHPMEVENT310x33f +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP0x344 +#define CSR_PMPCFG00x3a0 +#define CSR_PMPCFG10x3a1 +#define CSR_PMPCFG20x3a2 +#define CSR_PMPCFG30x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf + +#define CSR_TSELECT0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC0x7b1 +#define CSR_DSCRATCH 0x7b2 + +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOU
[U-Boot] [PATCH v5 16/25] riscv: Update supports_extension() to use desc from cpu driver
This updates supports_extension() implementation to use the desc
string from the cpu driver whenever possible, which avoids the
reading of misa CSR for S-mode U-Boot.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5:
- check if dev is valid, otherwise print a warning
Changes in v4:
- print warnings for S-mode without CONFIG_CPU
Changes in v3:
- new patch to update supports_extension() to use desc from cpu driver
Changes in v2: None
arch/riscv/cpu/cpu.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index d3c59da..fc7c9b3 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -5,8 +5,10 @@
#include
#include
+#include
#include
#include
+#include
/*
* prior_stage_fdt_address must be stored in the data section since it is used
@@ -16,7 +18,31 @@ phys_addr_t prior_stage_fdt_address
__attribute__((section(".data")));
static inline bool supports_extension(char ext)
{
+#ifdef CONFIG_CPU
+ struct udevice *dev;
+ char desc[32];
+
+ uclass_find_first_device(UCLASS_CPU, &dev);
+ if (!dev) {
+ debug("unable to find the RISC-V cpu device\n");
+ return false;
+ }
+ if (!cpu_get_desc(dev, desc, sizeof(desc))) {
+ /* skip the first 4 characters (rv32|rv64) */
+ if (strchr(desc + 4, ext))
+ return true;
+ }
+
+ return false;
+#else /* !CONFIG_CPU */
+#ifdef CONFIG_RISCV_MMODE
return csr_read(misa) & (1 << (ext - 'a'));
+#else /* !CONFIG_RISCV_MMODE */
+#warning "There is no way to determine the available extensions in S-mode."
+#warning "Please convert your board to use the RISC-V CPU driver."
+ return false;
+#endif /* CONFIG_RISCV_MMODE */
+#endif /* CONFIG_CPU */
}
static int riscv_cpu_probe(void)
--
2.7.4
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[U-Boot] [PATCH v5 04/25] cpu: Add a RISC-V CPU driver
This adds a driver for RISC-V CPU. Note the driver will bind
a RISC-V timer driver if "timebase-frequency" property is
present in the device tree.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- pass NULL as the timer device to device_bind_with_driver_data()
drivers/cpu/Kconfig | 6 +++
drivers/cpu/Makefile| 1 +
drivers/cpu/riscv_cpu.c | 116
3 files changed, 123 insertions(+)
create mode 100644 drivers/cpu/riscv_cpu.c
diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
index d405200..3d5729f 100644
--- a/drivers/cpu/Kconfig
+++ b/drivers/cpu/Kconfig
@@ -13,3 +13,9 @@ config CPU_MPC83XX
select CLK_MPC83XX
help
Support CPU cores for SoCs of the MPC83xx series.
+
+config CPU_RISCV
+ bool "Enable RISC-V CPU driver"
+ depends on CPU && RISCV
+ help
+ Support CPU cores for RISC-V architecture.
diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
index 858b037..be0300c 100644
--- a/drivers/cpu/Makefile
+++ b/drivers/cpu/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_CPU) += cpu-uclass.o
obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
+obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
obj-$(CONFIG_SANDBOX) += cpu_sandbox.o
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
new file mode 100644
index 000..5e15df5
--- /dev/null
+++ b/drivers/cpu/riscv_cpu.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size)
+{
+ const char *isa;
+
+ isa = dev_read_string(dev, "riscv,isa");
+ if (size < (strlen(isa) + 1))
+ return -ENOSPC;
+
+ strcpy(buf, isa);
+
+ return 0;
+}
+
+static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
+{
+ const char *mmu;
+
+ dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
+
+ mmu = dev_read_string(dev, "mmu-type");
+ if (!mmu)
+ info->features |= BIT(CPU_FEAT_MMU);
+
+ return 0;
+}
+
+static int riscv_cpu_get_count(struct udevice *dev)
+{
+ ofnode node;
+ int num = 0;
+
+ ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+ const char *device_type;
+
+ device_type = ofnode_read_string(node, "device_type");
+ if (!device_type)
+ continue;
+ if (strcmp(device_type, "cpu") == 0)
+ num++;
+ }
+
+ return num;
+}
+
+static int riscv_cpu_bind(struct udevice *dev)
+{
+ struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ struct driver *drv;
+ int ret;
+
+ /* save the hart id */
+ plat->cpu_id = dev_read_addr(dev);
+
+ /* first examine the property in current cpu node */
+ ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
+ /* if not found, then look at the parent /cpus node */
+ if (ret)
+ dev_read_u32(dev->parent, "timebase-frequency",
+&plat->timebase_freq);
+
+ /*
+* Bind riscv-timer driver on hart 0
+*
+* We only instantiate one timer device which is enough for U-Boot.
+* Pass the "timebase-frequency" value as the driver data for the
+* timer device.
+*
+* Return value is not checked since it's possible that the timer
+* driver is not included.
+*/
+ if (!plat->cpu_id && plat->timebase_freq) {
+ drv = lists_driver_lookup_name("riscv_timer");
+ if (!drv) {
+ debug("Cannot find the timer driver, not included?\n");
+ return 0;
+ }
+
+ device_bind_with_driver_data(dev, drv, "riscv_timer",
+plat->timebase_freq, ofnode_null(),
+NULL);
+ }
+
+ return 0;
+}
+
+static const struct cpu_ops riscv_cpu_ops = {
+ .get_desc = riscv_cpu_get_desc,
+ .get_info = riscv_cpu_get_info,
+ .get_count = riscv_cpu_get_count,
+};
+
+static const struct udevice_id riscv_cpu_ids[] = {
+ { .compatible = "riscv" },
+ { }
+};
+
+U_BOOT_DRIVER(riscv_cpu) = {
+ .name = "riscv_cpu",
+ .id = UCLASS_CPU,
+ .of_match = riscv_cpu_ids,
+ .bind = riscv_cpu_bind,
+ .ops = &riscv_cpu_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.7.4
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[U-Boot] [PATCH v5 07/25] riscv: Introduce a Kconfig option for machine mode
From: Anup Patel So far we have a Kconfig option for supervisor mode. This adds an option for the machine mode. Signed-off-by: Anup Patel Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: - incorporated and reworked Anup's S-mode timer patch @ http://patchwork.ozlabs.org/patch/1006663/ arch/riscv/Kconfig | 21 - 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6d85ac9..55c60e4 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -62,6 +62,22 @@ config CMODEL_MEDANY endchoice +choice + prompt "Run Mode" + default RISCV_MMODE + +config RISCV_MMODE + bool "Machine" + help + Choose this option to build U-Boot for RISC-V M-Mode. + +config RISCV_SMODE + bool "Supervisor" + help + Choose this option to build U-Boot for RISC-V S-Mode. + +endchoice + config RISCV_ISA_C bool "Emit compressed instructions" default y @@ -73,11 +89,6 @@ config RISCV_ISA_C config RISCV_ISA_A def_bool y -config RISCV_SMODE - bool "Run in S-Mode" - help - Enable this option to build U-Boot for RISC-V S-Mode - config 32BIT bool -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 24/25] riscv: bootm: Change to use boot_hart from global data
Avoid reading mhartid CSR directly, instead use the one we saved
in the global data structure before.
With this patch, BBL no longer needs to be hacked to provide the
mhartid CSR emulation for S-mode U-Boot.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- new patch to change to use boot_hart from global data
Changes in v2: None
arch/riscv/lib/bootm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 124aeef..60b32cc 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -93,7 +93,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
if (!fake) {
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
- kernel(csr_read(mhartid), images->ft_addr);
+ kernel(gd->arch.boot_hart, images->ft_addr);
}
}
--
2.7.4
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[U-Boot] [PATCH v5 12/25] riscv: Probe cpus during boot
This calls cpu_probe_all() to probe all available cpus.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- probe cpus in the pre-relocation stage too
Changes in v2:
- move to arch/riscv/cpu/cpu.c
arch/riscv/cpu/cpu.c| 26 ++
arch/riscv/cpu/qemu/Kconfig | 1 +
2 files changed, 27 insertions(+)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index d9f820c..8286a0c 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -4,6 +4,8 @@
*/
#include
+#include
+#include
#include
/*
@@ -53,3 +55,27 @@ int print_cpuinfo(void)
return 0;
}
+
+static int riscv_cpu_probe(void)
+{
+#ifdef CONFIG_CPU
+ int ret;
+
+ /* probe cpus so that RISC-V timer can be bound */
+ ret = cpu_probe_all();
+ if (ret)
+ return log_msg_ret("RISC-V cpus probe failed\n", ret);
+#endif
+
+ return 0;
+}
+
+int arch_cpu_init_dm(void)
+{
+ return riscv_cpu_probe();
+}
+
+int arch_early_init_r(void)
+{
+ return riscv_cpu_probe();
+}
diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/qemu/Kconfig
index 2e953e1..f48751e 100644
--- a/arch/riscv/cpu/qemu/Kconfig
+++ b/arch/riscv/cpu/qemu/Kconfig
@@ -4,6 +4,7 @@
config QEMU_RISCV
bool
+ select ARCH_EARLY_INIT_R
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
--
2.7.4
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[U-Boot] [PATCH v5 15/25] riscv: Add exception codes for xcause register
This adds all exception codes in encoding.h. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Anup Patel --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/riscv/include/asm/encoding.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 05e1ce3..772668c 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -85,6 +85,21 @@ #define IRQ_COP12 #define IRQ_HOST 13 +#define CAUSE_MISALIGNED_FETCH 0 +#define CAUSE_FETCH_ACCESS 1 +#define CAUSE_ILLEGAL_INSTRUCTION 2 +#define CAUSE_BREAKPOINT 3 +#define CAUSE_MISALIGNED_LOAD 4 +#define CAUSE_LOAD_ACCESS 5 +#define CAUSE_MISALIGNED_STORE 6 +#define CAUSE_STORE_ACCESS 7 +#define CAUSE_USER_ECALL 8 +#define CAUSE_SUPERVISOR_ECALL 9 +#define CAUSE_MACHINE_ECALL11 +#define CAUSE_FETCH_PAGE_FAULT 12 +#define CAUSE_LOAD_PAGE_FAULT 13 +#define CAUSE_STORE_PAGE_FAULT 15 + #define DEFAULT_RSTVEC 0x1000 #define DEFAULT_NMIVEC 0x1004 #define DEFAULT_MTVEC 0x1010 -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 17/25] riscv: Add indirect stringification to csr_xxx ops
With current csr_xxx ops, we cannot pass a macro to parameter
'csr', hence we need add another level to allow the parameter
to be a macro itself, aka indirect stringification.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- new patch to add indirect stringification to csr_xxx ops
arch/riscv/include/asm/csr.h | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 29624fd..86136f5 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -61,10 +61,12 @@
#ifndef __ASSEMBLY__
+#define xcsr(csr) #csr
+
#define csr_swap(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
- __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \
+ __asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1" \
: "=r" (__v) : "rK" (__v) \
: "memory"); \
__v;\
@@ -73,7 +75,7 @@
#define csr_read(csr) \
({ \
register unsigned long __v; \
- __asm__ __volatile__ ("csrr %0, " #csr \
+ __asm__ __volatile__ ("csrr %0, " xcsr(csr) \
: "=r" (__v) :\
: "memory"); \
__v;\
@@ -82,7 +84,7 @@
#define csr_write(csr, val)\
({ \
unsigned long __v = (unsigned long)(val); \
- __asm__ __volatile__ ("csrw " #csr ", %0" \
+ __asm__ __volatile__ ("csrw " xcsr(csr) ", %0" \
: : "rK" (__v)\
: "memory"); \
})
@@ -90,7 +92,7 @@
#define csr_read_set(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
- __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \
+ __asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1" \
: "=r" (__v) : "rK" (__v) \
: "memory"); \
__v;\
@@ -99,7 +101,7 @@
#define csr_set(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
- __asm__ __volatile__ ("csrs " #csr ", %0" \
+ __asm__ __volatile__ ("csrs " xcsr(csr) ", %0" \
: : "rK" (__v)\
: "memory"); \
})
@@ -107,7 +109,7 @@
#define csr_read_clear(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
- __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \
+ __asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1" \
: "=r" (__v) : "rK" (__v) \
: "memory"); \
__v;\
@@ -116,7 +118,7 @@
#define csr_clear(csr, val)\
({ \
unsigned long __v = (unsigned long)(val); \
- __asm__ __volatile__ ("csrc " #csr ", %0" \
+ __asm__ __volatile__ ("csrc " xcsr(csr) ", %0" \
: : "rK" (__v)\
: "memory"); \
})
--
2.7.4
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[U-Boot] [PATCH V2] Drivers: USB: MUSB: Remove legacy CONFIG_USB_DA8XX
There don't appear to be any boards enabling CONFIG_USB_DA8XX,
and there is a newer version of the MUSB driver, so let's remove
the legacy version of it.
Signed-off-by: Adam Ford
Reviewed-by: Jean-Jacques Hiblot
---
V2: Rebase on u-boot-usb master after applying patch to remove
CONFIG_USB_DAVINCI
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 7e6be03f4a..2508b6ed0d 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -15,10 +15,6 @@ config USB_OMAP3
bool "Legacy MUSB OMAP3 / OMAP4"
depends on ARCH_OMAP2PLUS
-config USB_DA8XX
- bool "Legacy MUSB DA8xx/OMAP-L1x"
- depends on ARCH_DAVINCI
-
config USB_AM35X
bool"Legacy MUSB AM35x"
depends on ARCH_OMAP2PLUS && !USB_OMAP3
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index 1242ce1c8c..744f2cfaa2 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -6,5 +6,4 @@
obj-$(CONFIG_USB_MUSB_HCD) += musb_hcd.o musb_core.o
obj-$(CONFIG_USB_MUSB_UDC) += musb_udc.o musb_core.o
obj-$(CONFIG_USB_OMAP3) += omap3.o
-obj-$(CONFIG_USB_DA8XX) += da8xx.o
obj-$(CONFIG_USB_AM35X) += am35x.o
diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
deleted file mode 100644
index a652a7c3c1..00
--- a/drivers/usb/musb/da8xx.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * da8xx.c - TI's DA8xx platform specific usb wrapper functions.
- *
- * Author: Ajay Kumar Gupta
- *
- * Based on drivers/usb/musb/davinci.c
- *
- * Copyright (C) 2009 Texas Instruments Incorporated
- */
-#include
-
-#include "musb_core.h"
-#include
-
-/* MUSB platform configuration */
-struct musb_config musb_cfg = {
- .regs = (struct musb_regs *)DA8XX_USB_OTG_CORE_BASE,
- .timeout= DA8XX_USB_OTG_TIMEOUT,
- .musb_speed = 0,
-};
-
-/*
- * This function enables VBUS by driving the GPIO Bank4 Pin 15 high.
- */
-static void enable_vbus(void)
-{
- u32 value;
-
- /* configure GPIO bank4 pin 15 in output direction */
- value = readl(&davinci_gpio_bank45->dir);
- writel((value & (~DA8XX_USB_VBUS_GPIO)), &davinci_gpio_bank45->dir);
-
- /* set GPIO bank4 pin 15 high to drive VBUS */
- value = readl(&davinci_gpio_bank45->set_data);
- writel((value | DA8XX_USB_VBUS_GPIO), &davinci_gpio_bank45->set_data);
-}
-
-/*
- * Enable the usb0 phy. This initialization procedure is explained in
- * the DA8xx USB user guide document.
- */
-static u8 phy_on(void)
-{
- u32 timeout;
- u32 cfgchip2;
-
- cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
-
- cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN |
- CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ);
- cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON |
- CFGCHIP2_REFFREQ_24MHZ;
-
- writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
-
- /* wait until the usb phy pll locks */
- timeout = musb_cfg.timeout;
- while (timeout--)
- if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD)
- return 1;
-
- /* USB phy was not turned on */
- return 0;
-}
-
-/*
- * Disable the usb phy
- */
-static void phy_off(void)
-{
- u32 cfgchip2;
-
- /*
-* Power down the on-chip PHY.
-*/
- cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
- cfgchip2 &= ~CFGCHIP2_PHY_PLLON;
- cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
- writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
-}
-
-/*
- * This function performs DA8xx platform specific initialization for usb0.
- */
-int musb_platform_init(void)
-{
- u32 revision;
-
- /* enable psc for usb2.0 */
- lpsc_on(33);
-
- /* enable usb vbus */
- enable_vbus();
-
- /* reset the controller */
- writel(0x1, &da8xx_usb_regs->control);
- udelay(5000);
-
- /* start the on-chip usb phy and its pll */
- if (phy_on() == 0)
- return -1;
-
- /* Returns zero if e.g. not clocked */
- revision = readl(&da8xx_usb_regs->revision);
- if (revision == 0)
- return -1;
-
- /* Disable all interrupts */
- writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
- DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_set);
- return 0;
-}
-
-/*
- * This function performs DA8xx platform specific deinitialization for usb0.
- */
-void musb_platform_deinit(void)
-{
- /* Turn of the phy */
- phy_off();
-
- /* flush any interrupts */
- writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
- DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_clr);
- writel(0, &da8xx_usb_regs->eoi);
-}
--
2.17.1
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[U-Boot] [PATCH v5 19/25] riscv: Move trap handler codes to mtrap.S
Currently the M-mode trap handler codes are in start.S. For future extension, move them to a separate file mtrap.S. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Anup Patel --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/riscv/cpu/Makefile | 2 +- arch/riscv/cpu/mtrap.S | 111 arch/riscv/cpu/start.S | 89 -- 3 files changed, 112 insertions(+), 90 deletions(-) create mode 100644 arch/riscv/cpu/mtrap.S diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile index 2cc6757..6bf6f91 100644 --- a/arch/riscv/cpu/Makefile +++ b/arch/riscv/cpu/Makefile @@ -4,4 +4,4 @@ extra-y = start.o -obj-y += cpu.o +obj-y += cpu.o mtrap.o diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S new file mode 100644 index 000..a5ad558 --- /dev/null +++ b/arch/riscv/cpu/mtrap.S @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * M-mode Trap Handler Code for RISC-V Core + * + * Copyright (c) 2017 Microsemi Corporation. + * Copyright (c) 2017 Padmarao Begari + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + * + * Copyright (C) 2018, Bin Meng + */ + +#include +#include + +#ifdef CONFIG_32BIT +#define LREG lw +#define SREG sw +#define REGBYTES 4 +#else +#define LREG ld +#define SREG sd +#define REGBYTES 8 +#endif + + .text + + /* trap entry */ + .align 2 + .global trap_entry +trap_entry: + addi sp, sp, -32 * REGBYTES + SREG x1, 1 * REGBYTES(sp) + SREG x2, 2 * REGBYTES(sp) + SREG x3, 3 * REGBYTES(sp) + SREG x4, 4 * REGBYTES(sp) + SREG x5, 5 * REGBYTES(sp) + SREG x6, 6 * REGBYTES(sp) + SREG x7, 7 * REGBYTES(sp) + SREG x8, 8 * REGBYTES(sp) + SREG x9, 9 * REGBYTES(sp) + SREG x10, 10 * REGBYTES(sp) + SREG x11, 11 * REGBYTES(sp) + SREG x12, 12 * REGBYTES(sp) + SREG x13, 13 * REGBYTES(sp) + SREG x14, 14 * REGBYTES(sp) + SREG x15, 15 * REGBYTES(sp) + SREG x16, 16 * REGBYTES(sp) + SREG x17, 17 * REGBYTES(sp) + SREG x18, 18 * REGBYTES(sp) + SREG x19, 19 * REGBYTES(sp) + SREG x20, 20 * REGBYTES(sp) + SREG x21, 21 * REGBYTES(sp) + SREG x22, 22 * REGBYTES(sp) + SREG x23, 23 * REGBYTES(sp) + SREG x24, 24 * REGBYTES(sp) + SREG x25, 25 * REGBYTES(sp) + SREG x26, 26 * REGBYTES(sp) + SREG x27, 27 * REGBYTES(sp) + SREG x28, 28 * REGBYTES(sp) + SREG x29, 29 * REGBYTES(sp) + SREG x30, 30 * REGBYTES(sp) + SREG x31, 31 * REGBYTES(sp) + csrr a0, MODE_PREFIX(cause) + csrr a1, MODE_PREFIX(epc) + mv a2, sp + jal handle_trap + csrw MODE_PREFIX(epc), a0 + +#ifdef CONFIG_RISCV_SMODE + /* Remain in S-mode after sret */ + li t0, SSTATUS_SPP +#else + /* Remain in M-mode after mret */ + li t0, MSTATUS_MPP +#endif + csrs MODE_PREFIX(status), t0 + LREG x1, 1 * REGBYTES(sp) + LREG x2, 2 * REGBYTES(sp) + LREG x3, 3 * REGBYTES(sp) + LREG x4, 4 * REGBYTES(sp) + LREG x5, 5 * REGBYTES(sp) + LREG x6, 6 * REGBYTES(sp) + LREG x7, 7 * REGBYTES(sp) + LREG x8, 8 * REGBYTES(sp) + LREG x9, 9 * REGBYTES(sp) + LREG x10, 10 * REGBYTES(sp) + LREG x11, 11 * REGBYTES(sp) + LREG x12, 12 * REGBYTES(sp) + LREG x13, 13 * REGBYTES(sp) + LREG x14, 14 * REGBYTES(sp) + LREG x15, 15 * REGBYTES(sp) + LREG x16, 16 * REGBYTES(sp) + LREG x17, 17 * REGBYTES(sp) + LREG x18, 18 * REGBYTES(sp) + LREG x19, 19 * REGBYTES(sp) + LREG x20, 20 * REGBYTES(sp) + LREG x21, 21 * REGBYTES(sp) + LREG x22, 22 * REGBYTES(sp) + LREG x23, 23 * REGBYTES(sp) + LREG x24, 24 * REGBYTES(sp) + LREG x25, 25 * REGBYTES(sp) + LREG x26, 26 * REGBYTES(sp) + LREG x27, 27 * REGBYTES(sp) + LREG x28, 28 * REGBYTES(sp) + LREG x29, 29 * REGBYTES(sp) + LREG x30, 30 * REGBYTES(sp) + LREG x31, 31 * REGBYTES(sp) + addi sp, sp, 32 * REGBYTES + MODE_PREFIX(ret) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 64246a4..47c3bf0 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -198,92 +198,3 @@ call_board_init_r: * jump to it ... */ jr t4 /* jump to board_init_r() */ - -/* - * trap entry - */ -.align 2 -trap_entry: - addisp, sp, -32*REGBYTES - SREGx1, 1*REGBYTES(sp) - SREGx2, 2*REGBYTES(sp) - SREGx3, 3*REGBYTES(sp) - SREGx4, 4*REGBYTES(sp) - SREGx5, 5*REGBYTES(sp) - SREGx6, 6*REGBYTES(sp) - SREGx7, 7*REGBYTES(sp) - SREGx8, 8*REGBYTES(sp) - SREGx9, 9*REGBYTES(sp) - SREGx10,
[U-Boot] [PATCH v5 11/25] riscv: Enlarge the default SYS_MALLOC_F_LEN
Increase the heap size for the pre-relocation stage, so that CPU driver can be loaded. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Anup Patel --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/riscv/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 39ca2d8..c45e4d7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -113,4 +113,7 @@ config RISCV_RDTIME standard rdtime instruction. This is the case for S-mode U-Boot, and is useful for processors that support rdtime in M-mode too. +config SYS_MALLOC_F_LEN + default 0x1000 + endmenu -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 25/25] riscv: Remove ae350.dts
This is not used by any board. Remove it.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
Reviewed-by: Anup Patel
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- new patch to remove ae350.dts
Changes in v2: None
arch/riscv/dts/ae350.dts | 229 ---
1 file changed, 229 deletions(-)
delete mode 100644 arch/riscv/dts/ae350.dts
diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts
deleted file mode 100644
index e48c298..000
--- a/arch/riscv/dts/ae350.dts
+++ /dev/null
@@ -1,229 +0,0 @@
-/dts-v1/;
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "andestech,ax25";
- model = "andestech,ax25";
-
- aliases {
- uart0 = &serial0;
- spi0 = &spi;
- };
-
- chosen {
- bootargs = "console=ttyS0,38400n8 debug loglevel=7";
- stdout-path = "uart0:38400n8";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- timebase-frequency = <6000>;
- CPU0: cpu@0 {
- device_type = "cpu";
- reg = <0>;
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imafdc";
- mmu-type = "riscv,sv39";
- clock-frequency = <6000>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <32>;
- CPU0_intc: interrupt-controller {
- #interrupt-cells = <1>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- };
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x 0x0 0x4000>;
- };
-
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "andestech,riscv-ae350-soc";
- ranges;
-
- plic0: interrupt-controller@e400 {
- compatible = "riscv,plic0";
- #address-cells = <2>;
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0x0 0xe400 0x0 0x200>;
- riscv,ndev=<71>;
- interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
- };
-
- plic1: interrupt-controller@e640 {
- compatible = "riscv,plic1";
- #address-cells = <2>;
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0x0 0xe640 0x0 0x40>;
- riscv,ndev=<1>;
- interrupts-extended = <&CPU0_intc 3>;
- };
-
- plmt0@e600 {
- compatible = "riscv,plmt0";
- interrupts-extended = <&CPU0_intc 7>;
- reg = <0x0 0xe600 0x0 0x10>;
- };
- };
-
- spiclk: virt_100mhz {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <1>;
- };
-
- timer0: timer@f040 {
- compatible = "andestech,atcpit100";
- reg = <0x0 0xf040 0x0 0x1000>;
- clock-frequency = <6000>;
- interrupts = <3 4>;
- interrupt-parent = <&plic0>;
- };
-
- serial0: serial@f030 {
- compatible = "andestech,uart16550", "ns16550a";
- reg = <0x0 0xf030 0x0 0x1000>;
- interrupts = <9 4>;
- clock-frequency = <19660800>;
- reg-shift = <2>;
- reg-offset = <32>;
- no-loopback-test = <1>;
- interrupt-parent = <&plic0>;
- };
-
- mac0: mac@e010 {
- compatible = "andestech,atmac100";
- reg = <0x0 0xe010 0x0 0x1000>;
- interrupts = <19 4>;
- interrupt-parent = <&plic0>;
- };
-
- mmc0: mmc@f0e0 {
- compatible = "andestech,atfsdc010";
- max-frequency = <1>;
- clock-freq-min-max = <40 1>;
- fifo-depth = <0x10>;
- reg = <0x0 0xf0e0 0x0 0x1000>;
- interrupts = <18 4>;
- cap-sd-highspeed;
- interrupt-parent = <&plic0>;
- };
-
- dma0: dma@f0c0 {
- compatible = "andestech,atcdmac300";
- reg = <0x0 0xf0c0 0x0 0x1000>;
- interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
- dma-channels = <8>;
- interrupt-parent = <&plic0>;
- };
-
- lcd0: lcd@e020 {
- compatible = "andestech,atflcdc100";
- reg = <0x0 0xe020 0x0 0x1000>;
Re: [U-Boot] [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific Kconfig option
Hi Rick, On Wed, Dec 12, 2018 at 5:56 PM Rick Chen wrote: > > Bin Meng 於 2018年12月12日 週三 下午5:37寫道： > > > > Hi Rick, > > > > On Wed, Dec 12, 2018 at 5:02 PM Rick Chen wrote: > > > > > > Hi Bin > > > > > > Bin Meng 於 2018年12月11日 週二 下午3:17寫道： > > > > > > > > Hi Rick, > > > > > > > > On Tue, Dec 11, 2018 at 3:06 PM Rick Chen wrote: > > > > > > > > > > > > Subject: [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific > > > > > > > Kconfig option > > > > > > > > > > > > > > There is no need to expose RISCV_NDS to the Kconfig menu as it is > > > > > > > an > > > > > > > ax25-specific option. > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > Can you explain why there is no need to expose RISCV_NDS here ? > > > > > > > > > > > > > This is specific to AX25, and there is no need to appear in the > > > > Kconfig menu when people are building U-Boot for some other RISC-V > > > > platforms. Also even if you select Y in the Kconfig menu for this > > > > option for platforms other than AX25, it just does not help since all > > > > its logic is within arch/riscv/cpu/ax25. > > > > > > > > > > AX25 can not select RISCV_NDS by default, it may cause build fail problem. > > > I still prefer to enable it by make menuconfig. > > > Can you drop this patch ? > > > > > > > I prefer not to drop this patch since it's not supposed to be exposed > > to other platforms. > > > > Do you mean the build fail problem is custom CSR numbers like > > mcache_ctl? Can we use hardcoded CSR number instead? > > > > Thanks for your suggestion about hardcoded CSR number. > > But actually I hope the mcache_ctl will be disabled by default in this stage. > Because some drivers of ae350 (like spi, smc flash driver, mac driver) > still have some access problems when cache is enable. > I am fixing it now. > But mmc driver is ready when cache is enable. > That is why I prefer enable cache by make menuconfig. > It will be easy to switch cache enable or disable by make menuconfig > without modifying Kconfig. > > How do you think about it ? > Please check the v5 patch [1] which should satisfy your requirement. [1] http://patchwork.ozlabs.org/patch/1011983/ Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 16/25] riscv: Update supports_extension() to use desc from cpu driver
Hi Lukas,
On Wed, Dec 12, 2018 at 7:53 PM Auer, Lukas
wrote:
>
> Hi Bin,
>
> On Tue, 2018-12-11 at 23:11 -0800, Bin Meng wrote:
> > This updates supports_extension() implementation to use the desc
> > string from the cpu driver whenever possible, which avoids the
> > reading of misa CSR for S-mode U-Boot.
> >
> > Signed-off-by: Bin Meng
> >
> > ---
> >
> > Changes in v4:
> > - print warnings for S-mode without CONFIG_CPU
> >
> > Changes in v3:
> > - new patch to update supports_extension() to use desc from cpu
> > driver
> >
> > Changes in v2: None
> >
> > arch/riscv/cpu/cpu.c | 22 ++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > index d3c59da..a2ebaf3 100644
> > --- a/arch/riscv/cpu/cpu.c
> > +++ b/arch/riscv/cpu/cpu.c
> > @@ -5,8 +5,10 @@
> >
> > #include
> > #include
> > +#include
> > #include
> > #include
> > +#include
> >
> > /*
> > * prior_stage_fdt_address must be stored in the data section since
> > it is used
> > @@ -16,7 +18,27 @@ phys_addr_t prior_stage_fdt_address
> > __attribute__((section(".data")));
> >
> > static inline bool supports_extension(char ext)
> > {
> > +#ifdef CONFIG_CPU
> > + struct udevice *dev;
> > + char desc[32];
> > +
> > + uclass_find_first_device(UCLASS_CPU, &dev);
>
> Sorry, I missed this before. Can you add error handling here to catch
> uclass_find_first_device returning an error or not finding a device? It
> would probably also make sense to print a warning message to the user
> in this case.
>
Added the error check in v5. Note only checking not finding a device
(dev == NULL) is enough as if uclass_find_first_device() returns an
error code, dev is NULL too.
> Other than that, this patch and the series look good!
> Reviewed-by: Lukas Auer
>
Regards,
Bin
___
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[U-Boot] [PATCH V2] Drivers: USB: Remove Legacy CONFIG_USB_DAVINCI
This patch removes CONFIG_USB_DAVINCI. It's a legacy option
that isn't defined anywhere, and there is a newer MUSB driver.
Signed-off-by: Adam Ford
Reviewed-by: Jean-Jacques Hiblot
---
V2: Rebase on origin/master
Remove drivers/usb/musb/davinci.c
Remove drivers/usb/musb/davinci.h
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index dd42f69a6b..7e6be03f4a 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -11,9 +11,6 @@ config USB_MUSB_HCD
config USB_MUSB_UDC
bool "Legacy USB Device Controller"
-config USB_DAVINCI
- bool "Legacy MUSB DaVinci"
-
config USB_OMAP3
bool "Legacy MUSB OMAP3 / OMAP4"
depends on ARCH_OMAP2PLUS
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index bdb3cd87f6..1242ce1c8c 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -5,7 +5,6 @@
obj-$(CONFIG_USB_MUSB_HCD) += musb_hcd.o musb_core.o
obj-$(CONFIG_USB_MUSB_UDC) += musb_udc.o musb_core.o
-obj-$(CONFIG_USB_DAVINCI) += davinci.o
obj-$(CONFIG_USB_OMAP3) += omap3.o
obj-$(CONFIG_USB_DA8XX) += da8xx.o
obj-$(CONFIG_USB_AM35X) += am35x.o
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
deleted file mode 100644
index 46cdb5ad1f..00
--- a/drivers/usb/musb/davinci.c
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * TI's Davinci platform specific USB wrapper functions.
- *
- * Copyright (c) 2008 Texas Instruments
- *
- * Author: Thomas Abraham t-abra...@ti.com, Texas Instruments
- */
-
-#include
-#include
-#include "davinci.h"
-#include
-
-#if !defined(CONFIG_DV_USBPHY_CTL)
-#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN)
-#endif
-
-/* MUSB platform configuration */
-struct musb_config musb_cfg = {
- .regs = (struct musb_regs *)MENTOR_USB0_BASE,
- .timeout= DAVINCI_USB_TIMEOUT,
- .musb_speed = 0,
-};
-
-/* MUSB module register overlay */
-struct davinci_usb_regs *dregs;
-
-/*
- * Enable the USB phy
- */
-static u8 phy_on(void)
-{
- u32 timeout;
-#ifdef DAVINCI_DM365EVM
- u32 val;
-#endif
- /* Wait until the USB phy is turned on */
-#ifdef DAVINCI_DM365EVM
- writel(USBPHY_PHY24MHZ | USBPHY_SESNDEN |
- USBPHY_VBDTCTEN, USBPHY_CTL_PADDR);
-#else
- writel(CONFIG_DV_USBPHY_CTL, USBPHY_CTL_PADDR);
-#endif
- timeout = musb_cfg.timeout;
-
-#ifdef DAVINCI_DM365EVM
- /* Set the ownership of GIO33 to USB */
- val = readl(PINMUX4);
- val &= ~(PINMUX4_USBDRVBUS_BITCLEAR);
- val |= PINMUX4_USBDRVBUS_BITSET;
- writel(val, PINMUX4);
-#endif
- while (timeout--)
- if (readl(USBPHY_CTL_PADDR) & USBPHY_PHYCLKGD)
- return 1;
-
- /* USB phy was not turned on */
- return 0;
-}
-
-/*
- * Disable the USB phy
- */
-static void phy_off(void)
-{
- /* powerdown the on-chip PHY and its oscillator */
- writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, USBPHY_CTL_PADDR);
-}
-
-void __enable_vbus(void)
-{
- /*
-* nothing to do, vbus is handled through the cpu.
-* Define this function in board code, if it is
-* different on your board.
-*/
-}
-void enable_vbus(void)
- __attribute__((weak, alias("__enable_vbus")));
-
-/*
- * This function performs Davinci platform specific initialization for usb0.
- */
-int musb_platform_init(void)
-{
- u32 revision;
-
- /* enable USB VBUS */
- enable_vbus();
-
- /* start the on-chip USB phy and its pll */
- if (!phy_on())
- return -1;
-
- /* reset the controller */
- dregs = (struct davinci_usb_regs *)DAVINCI_USB0_BASE;
- writel(1, &dregs->ctrlr);
- udelay(5000);
-
- /* Returns zero if e.g. not clocked */
- revision = readl(&dregs->version);
- if (!revision)
- return -1;
-
- /* Disable all interrupts */
- writel(DAVINCI_USB_USBINT_MASK | DAVINCI_USB_RXINT_MASK |
- DAVINCI_USB_TXINT_MASK , &dregs->intmsksetr);
- return 0;
-}
-
-/*
- * This function performs Davinci platform specific deinitialization for usb0.
- */
-void musb_platform_deinit(void)
-{
- /* Turn of the phy */
- phy_off();
-
- /* flush any interrupts */
- writel(DAVINCI_USB_USBINT_MASK | DAVINCI_USB_TXINT_MASK |
- DAVINCI_USB_RXINT_MASK , &dregs->intclrr);
-}
diff --git a/drivers/usb/musb/davinci.h b/drivers/usb/musb/davinci.h
deleted file mode 100644
index 29bb08c307..00
--- a/drivers/usb/musb/davinci.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * TI's Davinci platform specific USB wrapper functions.
- *
- * Copyright (c) 2008 Texas Instruments
- *
- * Author: Thomas Abraham t-abra...@ti.com, Texas Instruments
- */
-
-#ifndef __DAVINCI_USB_H__
-#define __DAVINCI_USB_H__
-
-#include
-#include "musb_core.h"
-
-/* B
Re: [U-Boot] [PATCH] Drivers: USB: MUSB: Remove legacy CONFIG_USB_DA8XX
On 12/12/2018 14:55, Adam Ford wrote:
On Tue, Dec 11, 2018 at 3:51 AM Jean-Jacques Hiblot wrote:
On 11/12/2018 10:47, Jean-Jacques Hiblot wrote:
On 10/12/2018 20:01, Marek Vasut wrote:
On 12/10/2018 05:35 PM, Adam Ford wrote:
There don't appear to be any boards enabling CONFIG_USB_DA8XX,
and there is a newer version of the MUSB driver, so let's remove
the legacy version of it.
Signed-off-by: Adam Ford
CCing Jean, I'd like his A-B/R-B.
Looks good to me, so I'll pick it once I have it, thanks!
This is good to see some code removal
This could even go a bit further and remove:
- drivers/usb/host/ohci-da8xx.c
- arch/arm/mach-davinci/include/mach/da8xx-usb.h
I want to investigate these a bit. I might have a use for these two
files on the da850evm yet. I know the musb was replaced by musb-new,
so my hope is to make the legacy musb drivers go away first. In my
ideal word, I'd like to keep the da850-evm around for a bit longer, at
least until Logic PD discontinues the L138 and AM1808 system on
module. If I can reuse these drivers to bring back USB host
functionality, I'd like to keep them.
It's fine by me. I just thought that those files might have been overlooked.
JJ
adam
Thanks
Reviewed-by: Jean-Jacques Hiblot
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 7e6be03f4a..2508b6ed0d 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -15,10 +15,6 @@ config USB_OMAP3
bool "Legacy MUSB OMAP3 / OMAP4"
depends on ARCH_OMAP2PLUS
-config USB_DA8XX
-bool "Legacy MUSB DA8xx/OMAP-L1x"
-depends on ARCH_DAVINCI
-
config USB_AM35X
bool"Legacy MUSB AM35x"
depends on ARCH_OMAP2PLUS && !USB_OMAP3
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index 1242ce1c8c..744f2cfaa2 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -6,5 +6,4 @@
obj-$(CONFIG_USB_MUSB_HCD) += musb_hcd.o musb_core.o
obj-$(CONFIG_USB_MUSB_UDC) += musb_udc.o musb_core.o
obj-$(CONFIG_USB_OMAP3) += omap3.o
-obj-$(CONFIG_USB_DA8XX) += da8xx.o
obj-$(CONFIG_USB_AM35X) += am35x.o
diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
deleted file mode 100644
index a652a7c3c1..00
--- a/drivers/usb/musb/da8xx.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * da8xx.c - TI's DA8xx platform specific usb wrapper functions.
- *
- * Author: Ajay Kumar Gupta
- *
- * Based on drivers/usb/musb/davinci.c
- *
- * Copyright (C) 2009 Texas Instruments Incorporated
- */
-#include
-
-#include "musb_core.h"
-#include
-
-/* MUSB platform configuration */
-struct musb_config musb_cfg = {
-.regs= (struct musb_regs *)DA8XX_USB_OTG_CORE_BASE,
-.timeout= DA8XX_USB_OTG_TIMEOUT,
-.musb_speed= 0,
-};
-
-/*
- * This function enables VBUS by driving the GPIO Bank4 Pin 15 high.
- */
-static void enable_vbus(void)
-{
-u32 value;
-
-/* configure GPIO bank4 pin 15 in output direction */
-value = readl(&davinci_gpio_bank45->dir);
-writel((value & (~DA8XX_USB_VBUS_GPIO)),
&davinci_gpio_bank45->dir);
-
-/* set GPIO bank4 pin 15 high to drive VBUS */
-value = readl(&davinci_gpio_bank45->set_data);
-writel((value | DA8XX_USB_VBUS_GPIO),
&davinci_gpio_bank45->set_data);
-}
-
-/*
- * Enable the usb0 phy. This initialization procedure is explained in
- * the DA8xx USB user guide document.
- */
-static u8 phy_on(void)
-{
-u32 timeout;
-u32 cfgchip2;
-
-cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
-
-cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN |
CFGCHIP2_OTGPWRDN |
- CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ);
-cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN |
CFGCHIP2_PHY_PLLON |
-CFGCHIP2_REFFREQ_24MHZ;
-
-writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
-
-/* wait until the usb phy pll locks */
-timeout = musb_cfg.timeout;
-while (timeout--)
-if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD)
-return 1;
-
-/* USB phy was not turned on */
-return 0;
-}
-
-/*
- * Disable the usb phy
- */
-static void phy_off(void)
-{
-u32 cfgchip2;
-
-/*
- * Power down the on-chip PHY.
- */
-cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
-cfgchip2 &= ~CFGCHIP2_PHY_PLLON;
-cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
-writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
-}
-
-/*
- * This function performs DA8xx platform specific initialization
for usb0.
- */
-int musb_platform_init(void)
-{
-u32 revision;
-
-/* enable psc for usb2.0 */
-lpsc_on(33);
-
-/* enable usb vbus */
-enable_vbus();
-
-/* reset the controller */
-writel(0x1, &da8xx_usb_regs->control);
-udelay(5000);
-
-/* start the on-chip usb phy and its pll */
-if (phy_on() == 0)
-return -1;
-
-/* Returns zero if e.g. not clocked */
-revision = readl(&da8xx_usb_regs->revision);
-if (revisi
Re: [U-Boot] [PATCH V2] Drivers: USB: Remove Legacy CONFIG_USB_DAVINCI
On 12/12/2018 03:17 PM, Adam Ford wrote: > This patch removes CONFIG_USB_DAVINCI. It's a legacy option > that isn't defined anywhere, and there is a newer MUSB driver. > > Signed-off-by: Adam Ford > Reviewed-by: Jean-Jacques Hiblot Applied after fixing the tags, please use usb: musb: next time. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V2] Drivers: USB: MUSB: Remove legacy CONFIG_USB_DA8XX
On 12/12/2018 03:17 PM, Adam Ford wrote: > There don't appear to be any boards enabling CONFIG_USB_DA8XX, > and there is a newer version of the MUSB driver, so let's remove > the legacy version of it. > > Signed-off-by: Adam Ford > Reviewed-by: Jean-Jacques Hiblot > Applied after fixing the tags, please use usb: musb: next time. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] fs: cbfs: remove wrong header validation
Hi Bin,
Finally I have some time to look deeper into this issue.
>
> On Thu, Sep 20, 2018 at 10:47 PM Christian Gmeiner
> wrote:
> >
> > Coreboot does not contain such a check:
> > https://github.com/coreboot/coreboot/blob/eeb4e20b2f6d786c92fe3efb30817e90389a2bfe/src/commonlib/cbfs.c#L64
> >
> > Before this change cbfsinit failed with 'Bad CBFS file'. After this change
> > all cbfs commands
> > are working as expected.
> >
> > Signed-off-by: Christian Gmeiner
> > ---
> > fs/cbfs/cbfs.c | 6 +-
> > 1 file changed, 1 insertion(+), 5 deletions(-)
> >
> > diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c
> > index 0dce639b49..2a581f0c18 100644
> > --- a/fs/cbfs/cbfs.c
> > +++ b/fs/cbfs/cbfs.c
> > @@ -96,11 +96,7 @@ static int file_cbfs_next_file(u8 *start, u32 size, u32
> > align,
> > }
> >
> > swap_file_header(&header, fileHeader);
> > - if (header.offset < sizeof(struct cbfs_fileheader) ||
> > - header.offset > header.len) {
> > - file_cbfs_result = CBFS_BAD_FILE;
> > - return -1;
> > - }
>
> It looks to me the existing codes were doing some sanity checks. Can
> you elaborate why this is failing on your board? In your coreboot
> reference, I don't see exactly how U-Boot codes are connected to the
> coreboot one.
>
This has nothing to do with my board at all - I can easily reproduce
this issue under qemu:
qemu-system-i386 -bios build/coreboot.rom -hda /dev/zero -serial
stdio -display none
WARNING: Image format was not specified for '/dev/zero' and probing guessed raw.
Automatically detecting the format is dangerous for raw
images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
coreboot-4.8-2510-g303a4bfd4a Wed Dec 12 02:20:54 UTC 2018 bootblock starting...
CBFS: 'Master Header Locator' located CBFS at [1fa0200:200)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size 3c04
coreboot-4.8-2510-g303a4bfd4a Wed Dec 12 02:20:54 UTC 2018 romstage starting...
CBMEM:
IMD: root @ 07fff000 254 entries.
IMD: root @ 07ffec00 62 entries.
CBFS: 'Master Header Locator' located CBFS at [1fa0200:200)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 3d00 size acb2
Decompressing stage fallback/ramstage @ 0x07fbcfc0 (128664 bytes)
Loading module at 07fbd000 with entry 07fbd000. filesize: 0x15750
memsize: 0x1f658
Processing 1257 relocs. Offset value of 0x071bd000
coreboot-4.8-2510-g303a4bfd4a Wed Dec 12 02:20:54 UTC 2018 ramstage starting...
Enumerating buses...
CPU_CLUSTER: 0 enabled
DOMAIN: enabled
QEMU: firmware config interface detected
QEMU: max_cpus is 1
CPU: APIC: 00 enabled
scan_bus: scanning of bus CPU_CLUSTER: 0 took 0 usecs
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/1237] enabled
PCI: 00:01.0 [8086/7000] enabled
PCI: 00:01.1 [8086/7010] enabled
PCI: 00:01.3 [8086/7113] enabled
PCI: 00:02.0 [1234/] enabled
PCI: 00:03.0 [8086/100e] enabled
scan_bus: scanning of bus PCI: 00:01.0 took 0 usecs
scan_bus: scanning of bus PCI: 00:01.3 took 0 usecs
scan_bus: scanning of bus DOMAIN: took 0 usecs
scan_bus: scanning of bus Root Device took 0 usecs
done
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN:
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
QEMU: 11 files in fw_cfg
QEMU: bootorder [size=0]
QEMU: etc/acpi/rsdp [size=36]
QEMU: etc/acpi/tables [size=131072]
QEMU: etc/boot-fail-wait [size=4]
QEMU: etc/e820 [size=20]
QEMU: etc/smbios/smbios-anchor [size=31]
QEMU: etc/smbios/smbios-tables [size=320]
QEMU: etc/system-states [size=6]
QEMU: etc/table-loader [size=4096]
QEMU: etc/tpm/log [size=0]
QEMU: genroms/kvmvapic.bin [size=9216]
QEMU: e820/ram: 0x +0x0800
QEMU: reserve ioports 0x0510-0x0511 [firmware-config]
QEMU: reserve ioports 0x5658-0x5658 [vmware-port]
QEMU: reserve ioports 0xae00-0xae0f [pci-hotplug]
QEMU: reserve ioports 0xaf00-0xaf1f [cpu-hotplug]
QEMU: reserve ioports 0xafe0-0xafe3 [piix4-gpe0]
Done reading resources.
Setting resources...
PCI: 00:01.1 20 <- [0x005840 - 0x00584f] size 0x0010 gran 0x04 io
PCI: 00:02.0 10 <- [0x00fd00 - 0x00fdff] size 0x0100 gran
0x18 prefmem
PCI: 00:02.0 18 <- [0x00fe07 - 0x00fe070fff] size 0x1000 gran 0x0c mem
PCI: 00:02.0 30 <- [0x00fe06 - 0x00fe06] size 0x0001 gran 0x10 romem
PCI: 00:03.0 10 <- [0x00fe04 - 0x00fe05] size 0x0002 gran 0x11 mem
PCI: 00:03.0 14 <- [0x005800 - 0x00583f] size 0x0040 gran 0x06 io
PCI: 00:03.0 30 <- [0x00fe00 - 0x00fe03] size 0x0004 gran 0x12 romem
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 00
PCI: 00:01.0 cmd <- 00
PCI: 00:01.1 cmd <- 01
PCI: 00:01.3 cmd <- 00
PCI: 00:02.0 cmd <- 03
PCI: 00:03.0 cmd <- 03
done.
I
Re: [U-Boot] policy regarding unused code
I suspect this splits into three categories:
- Dead symbols and code to drop.
- Typos/thinkos
- Mistake in your grep? I see CONFIG_VIRTIO_SANDBOX is used today for
example.
what did you run to get that list of CONFIG_* symbols? years ago, i
This is small python script that I wrote (see code below).
What it does (roughly):
- scan all Makefile and*.mk file to create a set of variables starting
with CONFIG_
- create the set of all used CONFIG_* variables by scanning
moveconfig.db. This can be created with tools/moveconfig.py -b. (you
need patch 'tools: moveconfig: Add an option to build a fuller database
of options').
- subtract set#2 from set#1
JJ
From: Jean-Jacques Hiblot
Date: Wed, 12 Dec 2018 16:15:21 +0100
Subject: [PATCH] simple tool to find unused options
Signed-off-by: Jean-Jacques Hiblot
---
tools/find_unused_config_options.py | 78
+
1 file changed, 78 insertions(+)
create mode 100755 tools/find_unused_config_options.py
diff --git a/tools/find_unused_config_options.py
b/tools/find_unused_config_options.py
new file mode 100755
index 000..85c859a
--- /dev/null
+++ b/tools/find_unused_config_options.py
@@ -0,0 +1,78 @@
+#! /usr/bin/env python
+
+import re
+import os
+
+def get_var_from_moveconfig_db():
+ options = set()
+ search = re.compile("\s*CONFIG_([^=]*)=.*")
+ with open("moveconfig.db", "r") as f:
+ for l in f.readlines():
+ m = search.match(l)
+ if m:
+ options.add(m.group(1))
+ return options
+
+def get_makefiles(start):
+ Makefiles = []
+ for (dirpath, dirnames, filenames) in os.walk(start):
+ Makefiles.extend([ os.path.join(dirpath,f) for f in
filenames if f == "Makefile" or f.endswith(".mk")])
+ return Makefiles
+
+def get_C_files(start):
+ c_files = []
+ for (dirpath, dirnames, filenames) in os.walk(start):
+ Makefiles.extend([ os.path.join(dirpath,f) for f in
filenames if f.endswith(".c") or f.endswith(".h")])
+ return c_files
+
+def get_CONFIG_var_from_Makefile(makefile):
+ simple_options = set()
+ spl_tpl_options = set()
+
+ search = re.compile("\$\(CONFIG_(.*)\)")
+ with open(makefile, "r") as f:
+ for l in f.readlines():
+ m = search.search(l)
+ if m:
+ option = m.group(1)
+ s = set()
+ if option.startswith("$(SPL_)"):
+ s.add(option.replace("$(SPL_)",""))
+ s.add(option.replace("$(SPL_)","SPL_"))
+ elif option.startswith("$(SPL_TPL_)"):
+ s.add(option.replace("$(SPL_TPL_)",""))
+ s.add(option.replace("$(SPL_TPL_)","SPL_"))
+ s.add(option.replace("$(SPL_TPL_)","TPL_"))
+ else:
+ simple_options.add(option.split(')')[0].split(':')[0])
+ for opt in s:
+ spl_tpl_options.add(opt.split(')')[0].split(':')[0])
+
+ return simple_options, spl_tpl_options
+
+
+makefiles = get_makefiles('./')
+simple_options = set()
+spl_tpl_options = set()
+for f in makefiles:
+ a, b = get_CONFIG_var_from_Makefile(f)
+ simple_options |= a
+ spl_tpl_options |= b
+
+var_in_makefiles = simple_options
+# add the SPL_TPL variables (but filter out those that are never
referenced in the code)
+for option in spl_tpl_options:
+ ### filter out variable that are not reference at all
+ if os.system("git grep 'CONFIG_{}' > /dev/null".format(option))
== 0:
+ var_in_makefiles.add(option)
+
+var_in_cfg = get_var_from_moveconfig_db()
+
+whitelist = set(["SPL_BUILD","TPL_BUILD", "SHELL"])
+suspects = var_in_makefiles - var_in_cfg - whitelist
+
+print(" ---")
+print ("used in makefile but NOT referenced in defconfigs")
+for option in suspects:
+ print('CONFIG_'+option)
+
--
2.7.4
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Re: [U-Boot] [PATCH v5 06/25] riscv: ax25: Hide the ax25-specific Kconfig option
On Wed, 2018-12-12 at 06:12 -0800, Bin Meng wrote: > There is no need to expose RISCV_NDS to the Kconfig menu as it is > an ax25-specific option. Introduce a dedicated Kconfig option for > the cache ops of ax25 platform and use that to guard the cache ops. > > Signed-off-by: Bin Meng > > --- > > Changes in v5: > - Introduced another Kconfig option for the cache ops on AX25 CPU, > so that it remains selectable in Kconfig menu, but only visible > to AX25 platform. > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > arch/riscv/cpu/ax25/Kconfig| 17 - > arch/riscv/cpu/ax25/cache.c| 12 ++-- > board/AndesTech/ax25-ae350/Kconfig | 4 > 3 files changed, 22 insertions(+), 11 deletions(-) > Reviewed-by: Lukas Auer ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 16/25] riscv: Update supports_extension() to use desc from cpu driver
Hi Bin,
On Wed, 2018-12-12 at 22:11 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Wed, Dec 12, 2018 at 7:53 PM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Tue, 2018-12-11 at 23:11 -0800, Bin Meng wrote:
> > > This updates supports_extension() implementation to use the desc
> > > string from the cpu driver whenever possible, which avoids the
> > > reading of misa CSR for S-mode U-Boot.
> > >
> > > Signed-off-by: Bin Meng
> > >
> > > ---
> > >
> > > Changes in v4:
> > > - print warnings for S-mode without CONFIG_CPU
> > >
> > > Changes in v3:
> > > - new patch to update supports_extension() to use desc from cpu
> > > driver
> > >
> > > Changes in v2: None
> > >
> > > arch/riscv/cpu/cpu.c | 22 ++
> > > 1 file changed, 22 insertions(+)
> > >
> > > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > > index d3c59da..a2ebaf3 100644
> > > --- a/arch/riscv/cpu/cpu.c
> > > +++ b/arch/riscv/cpu/cpu.c
> > > @@ -5,8 +5,10 @@
> > >
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > > +#include
> > >
> > > /*
> > > * prior_stage_fdt_address must be stored in the data section
> > > since
> > > it is used
> > > @@ -16,7 +18,27 @@ phys_addr_t prior_stage_fdt_address
> > > __attribute__((section(".data")));
> > >
> > > static inline bool supports_extension(char ext)
> > > {
> > > +#ifdef CONFIG_CPU
> > > + struct udevice *dev;
> > > + char desc[32];
> > > +
> > > + uclass_find_first_device(UCLASS_CPU, &dev);
> >
> > Sorry, I missed this before. Can you add error handling here to
> > catch
> > uclass_find_first_device returning an error or not finding a
> > device? It
> > would probably also make sense to print a warning message to the
> > user
> > in this case.
> >
>
> Added the error check in v5. Note only checking not finding a device
> (dev == NULL) is enough as if uclass_find_first_device() returns an
> error code, dev is NULL too.
>
Thanks! The series looks good now!
Lukas
> > Other than that, this patch and the series look good!
> > Reviewed-by: Lukas Auer
> >
>
> Regards,
> Bin
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Re: [U-Boot] [PATCH] m53menlo: fix addmtd cmd in default environment
On 12/12/2018 02:43 PM, Olaf Mandel wrote:
> The original definition added the string mtdparts= to the Linux Kernel
> args twice: mtdparts=mtdparts=. Fix that.
>
> Signed-off-by: Olaf Mandel
Subject should have "arm: mx5: m53menlo: " tags, otherwise
Reviewed-by: Marek Vasut
> ---
> include/configs/m53menlo.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
> index 3fca28da6b..f8a0188d93 100644
> --- a/include/configs/m53menlo.h
> +++ b/include/configs/m53menlo.h
> @@ -212,7 +212,7 @@
> "setenv bootargs ${bootargs} " \
> "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
> ":${hostname}:${netdev}:off\0" \
> - "addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \
> + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
> "addmisc=" \
> "setenv bootargs ${bootargs} ${miscargs}\0" \
> "addargs=run addcons addmisc addmtd\0" \
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] m53menlo: fix splashfile location
On 12/12/2018 02:42 PM, Olaf Mandel wrote: > After merging the boot partition into the root partition, the splashfile > resides in the /boot subdirectory: update the default environment to > reflect that. > > Signed-off-by: Olaf Mandel Subject should have "arm: mx5: m53menlo: " tags, otherwise Reviewed-by: Marek Vasut > --- > include/configs/m53menlo.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h > index f8a0188d93..1729a54c25 100644 > --- a/include/configs/m53menlo.h > +++ b/include/configs/m53menlo.h > @@ -202,7 +202,7 @@ > "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"\ > "netdev=eth0\0" \ > "splashsource=mmc_fs\0" \ > - "splashfile=usplash.bmp.gz\0" \ > + "splashfile=boot/usplash.bmp.gz\0" \ > "splashimage=0x8800\0" \ > "splashpos=m,m\0" \ > "addcons=" \ > -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/7] cmd: part: Add 'number' sub-command
This sub-command serves for getting the partition index from
partition name. Also it can be used to test the existence of specified
partition.
Signed-off-by: Ruslan Trofymenko
Reviewed-by: Alistair Strachan
Reviewed-by: Sam Protsenko
Reviewed-by: Simon Glass
---
Changes in v2: None
cmd/part.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/cmd/part.c b/cmd/part.c
index bfb6488..653e13c 100644
--- a/cmd/part.c
+++ b/cmd/part.c
@@ -24,6 +24,7 @@
enum cmd_part_info {
CMD_PART_INFO_START = 0,
CMD_PART_INFO_SIZE,
+ CMD_PART_INFO_NUMBER
};
static int do_part_uuid(int argc, char * const argv[])
@@ -149,6 +150,9 @@ static int do_part_info(int argc, char * const argv[], enum
cmd_part_info param)
case CMD_PART_INFO_SIZE:
snprintf(buf, sizeof(buf), LBAF, info.size);
break;
+ case CMD_PART_INFO_NUMBER:
+ snprintf(buf, sizeof(buf), "%d", part);
+ break;
default:
printf("** Unknown cmd_part_info value: %d\n", param);
return 1;
@@ -172,6 +176,11 @@ static int do_part_size(int argc, char * const argv[])
return do_part_info(argc, argv, CMD_PART_INFO_SIZE);
}
+static int do_part_number(int argc, char * const argv[])
+{
+ return do_part_info(argc, argv, CMD_PART_INFO_NUMBER);
+}
+
static int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2)
@@ -185,6 +194,8 @@ static int do_part(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
return do_part_start(argc - 2, argv + 2);
else if (!strcmp(argv[1], "size"))
return do_part_size(argc - 2, argv + 2);
+ else if (!strcmp(argv[1], "number"))
+ return do_part_number(argc - 2, argv + 2);
return CMD_RET_USAGE;
}
@@ -206,5 +217,8 @@ U_BOOT_CMD(
" part can be either partition number or partition name\n"
"part size\n"
"- set environment variable to the size of the partition (in
blocks)\n"
- " part can be either partition number or partition name"
+ " part can be either partition number or partition name\n"
+ "part number\n"
+ "- set environment variable to the partition number using the
partition name\n"
+ " part must be specified as partition name"
);
--
2.7.4
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[U-Boot] [PATCH v2 0/7] android: Implement A/B boot process
This patch series adds support for Android A/B boot process [1]. Main steps of A/B boot process are: - A/B metadata integrity check - looking for the current slot (where the system should be booting from) - getting the name of the current boot partition (boot_a or boot_b) and loading the corresponding Android boot image - getting the name of the current system partition (system_a or system_b) and passing of its full name via kernel command line (like 'root=/dev/mmcblk1p11') - passing current slot via kernel command line (like 'androidboot.slot_suffix=_a') and via A/B metadata (e.g. via misc partition) - A/B metadata processing: setting the boot success flag for current slot, handling the retry counter, etc A/B metadata is organized according to Android reference [2] and stored on 'misc' partition. On the first A/B boot process, when 'misc' partition doesn't contain required data, default A/B metadata will be created and stored in 'misc' partition. In the end of the Android boot, 'update_verifier' and 'update_engine' services are processing the A/B metadata through the Boot Control HAL. To confirm the boot was successful using current slot, "boot success" flag must be set on Android side. To enable Android A/B support in U-Boot: 1. Set the following config options: CONFIG_ANDROID_AB=y CONFIG_CMD_AB_SELECT=y 2. Change the disk layout so that it has sloted boot partitions. E.g. instead of 'boot' and 'system' partitions there should be 'boot_a', 'boot_b', 'system_a' and 'system_b' partitions. To be able to actually test this patch series, the A/B features must be implemented and enabled in Android as well (see [1] for details). Documentation and corresponding test for A/B boot is present here. The last patch in this series integrates A/B boot support on AM57xx based boards (though it's not enabled by default). Future users of A/B boot feature can use it as a reference. This series is a part of previous submission [3] by Alex Deymo. It contains only A/B feature that was stripped out from there with some modifications for using with "bootm" command preferred in upstream. Changes in v2: * 'android_ab_select' command is renamed to 'ab_select' command and moved to separate 'Android support commands' menu * For am57xx boards slotted sections (e.g. system_a and system_b) are added to the default sections if CONFIG_CMD_AB_SELECT flag is defined * Returned function error codes are clarified (errno using) * Some types constants and files are renamed * Assertion condition is clarified in test case * 'debug' calls are changed to 'log_debug' * The Guide is clarified by the results of changes [1] https://source.android.com/devices/tech/ota/ab/ab_implement [2] bootable/recovery/bootloader_message/include/bootloader_message/bootloader_message.h [3] https://lists.denx.de/pipermail/u-boot/2017-April/285841.html Ruslan Trofymenko (7): cmd: part: Add 'number' sub-command disk: part: Extend API to get partition info common: Implement A/B metadata cmd: Add 'ab_select' command test/py: Add base test case for A/B updates doc: android: Add simple guide for A/B updates env: am57xx: Implement A/B boot process cmd/Kconfig | 15 +++ cmd/Makefile | 1 + cmd/ab_select.c | 52 cmd/part.c| 16 ++- common/Kconfig| 10 ++ common/Makefile | 1 + common/android_ab.c | 277 ++ configs/sandbox_defconfig | 2 + disk/part.c | 68 +++ doc/README.android-ab | 67 ++ include/android_ab.h | 34 ++ include/android_bl_msg.h | 169 ++ include/environment/ti/boot.h | 58 - include/part.h| 21 test/py/tests/test_ab.py | 74 +++ 15 files changed, 858 insertions(+), 7 deletions(-) create mode 100644 cmd/ab_select.c create mode 100644 common/android_ab.c create mode 100644 doc/README.android-ab create mode 100644 include/android_ab.h create mode 100644 include/android_bl_msg.h create mode 100644 test/py/tests/test_ab.py -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 5/7] test/py: Add base test case for A/B updates
Add sandbox test for 'ab_select' command.
Test: ./test/py/test.py --bd sandbox --build -k test_ab
Signed-off-by: Ruslan Trofymenko
Reviewed-by: Alistair Strachan
Reviewed-by: Sam Protsenko
---
Changes in v2:
* Сhanges related to command renaming
* Assertion condition was clarified. Full command output is controlled.
configs/sandbox_defconfig | 2 ++
test/py/tests/test_ab.py | 74 +++
2 files changed, 76 insertions(+)
create mode 100644 test/py/tests/test_ab.py
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 5b65c61..b6a642e 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -21,6 +21,7 @@ CONFIG_PRE_CON_BUF_ADDR=0x10
CONFIG_LOG_MAX_LEVEL=6
CONFIG_LOG_ERROR_RETURN=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ANDROID_AB=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
@@ -49,6 +50,7 @@ CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_AXI=y
+CONFIG_CMD_AB_SELECT=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
CONFIG_CMD_RARP=y
diff --git a/test/py/tests/test_ab.py b/test/py/tests/test_ab.py
new file mode 100644
index 000..b90ca87
--- /dev/null
+++ b/test/py/tests/test_ab.py
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0
+# (C) Copyright 2018 Texas Instruments,
+
+# Test A/B update commands.
+
+import os
+import pytest
+import u_boot_utils
+
+class ABTestDiskImage(object):
+"""Disk Image used by the A/B tests."""
+
+def __init__(self, u_boot_console):
+"""Initialize a new ABTestDiskImage object.
+
+Args:
+u_boot_console: A U-Boot console.
+
+Returns:
+Nothing.
+"""
+
+filename = 'test_ab_disk_image.bin'
+
+persistent = u_boot_console.config.persistent_data_dir + '/' + filename
+self.path = u_boot_console.config.result_dir + '/' + filename
+
+with u_boot_utils.persistent_file_helper(u_boot_console.log,
persistent):
+if os.path.exists(persistent):
+u_boot_console.log.action('Disk image file ' + persistent +
+' already exists')
+else:
+u_boot_console.log.action('Generating ' + persistent)
+fd = os.open(persistent, os.O_RDWR | os.O_CREAT)
+os.ftruncate(fd, 524288)
+os.close(fd)
+cmd = ('sgdisk', persistent)
+u_boot_utils.run_and_log(u_boot_console, cmd)
+
+cmd = ('sgdisk', '--new=1:64:512', '-c 1:misc', persistent)
+u_boot_utils.run_and_log(u_boot_console, cmd)
+cmd = ('sgdisk', '-l', persistent)
+u_boot_utils.run_and_log(u_boot_console, cmd)
+
+cmd = ('cp', persistent, self.path)
+u_boot_utils.run_and_log(u_boot_console, cmd)
+
+di = None
+@pytest.fixture(scope='function')
+def ab_disk_image(u_boot_console):
+global di
+if not di:
+di = ABTestDiskImage(u_boot_console)
+return di
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('android_ab')
+@pytest.mark.buildconfigspec('cmd_ab_select')
+@pytest.mark.requiredtool('sgdisk')
+def test_ab(ab_disk_image, u_boot_console):
+"""Test the 'ab_select' command."""
+
+u_boot_console.run_command('host bind 0 ' + ab_disk_image.path)
+
+output = u_boot_console.run_command('ab_select slot_name host 0#misc')
+assert 're-initializing A/B metadata' in output
+assert 'Attempting slot a, tries remaining 7' in output
+output = u_boot_console.run_command('printenv slot_name')
+assert 'slot_name=a' in output
+
+output = u_boot_console.run_command('ab_select slot_name host 0:1')
+assert 'Attempting slot b, tries remaining 7' in output
+output = u_boot_console.run_command('printenv slot_name')
+assert 'slot_name=b' in output
--
2.7.4
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[U-Boot] [PATCH v2 3/7] common: Implement A/B metadata
This patch determines the A/B-specific bootloader message structure
that is the basis for implementation of recovery and A/B update
functions. A/B metadata is stored in this structure and used to decide
which slot should we use to boot the device. Also some basic functions
for A/B metadata manipulation are implemented (like slot selection).
The patch was extracted from commits [1], [2] with some coding style
fixes.
[1]
https://android-review.googlesource.com/c/platform/external/u-boot/+/729878/2
[2]
https://android-review.googlesource.com/c/platform/external/u-boot/+/729880/2
Signed-off-by: Ruslan Trofymenko
Reviewed-by: Sam Protsenko
---
Changes in v2:
* Function return codes are clarified
* Some types and constants are renamed (for compactness)
* android_bootloader_message.h is renamed to android_bl_msg.h
* 'debug' calls are changed to 'log_debug'
* Order of headers is changed
* android_bl_msg.h was synced with AOSP master counterpart
common/Kconfig | 10 ++
common/Makefile | 1 +
common/android_ab.c | 277 +++
include/android_ab.h | 34 ++
include/android_bl_msg.h | 169 +
5 files changed, 491 insertions(+)
create mode 100644 common/android_ab.c
create mode 100644 include/android_ab.h
create mode 100644 include/android_bl_msg.h
diff --git a/common/Kconfig b/common/Kconfig
index 57bd16d..0ff4679 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -748,6 +748,16 @@ config UPDATE_TFTP_MSEC_MAX
default 100
depends on UPDATE_TFTP
+config ANDROID_AB
+ bool "Android A/B updates"
+ default n
+ help
+ If enabled, adds support for the new Android A/B update model. This
+ allows the bootloader to select which slot to boot from based on the
+ information provided by userspace via the Android boot_ctrl HAL. This
+ allows a bootloader to try a new version of the system but roll back
+ to previous version if the new one didn't boot all the way.
+
endmenu
menu "Blob list"
diff --git a/common/Makefile b/common/Makefile
index 65d89dc..acc3851 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -104,6 +104,7 @@ endif
endif
obj-y += image.o
+obj-$(CONFIG_ANDROID_AB) += android_ab.o
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o
obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o
diff --git a/common/android_ab.c b/common/android_ab.c
new file mode 100644
index 000..dda2263
--- /dev/null
+++ b/common/android_ab.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2017 The Android Open Source Project
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * Compute the CRC-32 of the bootloader control struct.
+ *
+ * Only the bytes up to the crc32_le field are considered for the CRC-32
+ * calculation.
+ */
+static uint32_t ab_control_compute_crc(struct andr_bl_control *abc)
+{
+ return crc32(0, (void *)abc, offsetof(typeof(*abc), crc32_le));
+}
+
+/**
+ * Initialize andr_bl_control to the default value.
+ *
+ * It allows us to boot all slots in order from the first one. This value
+ * should be used when the bootloader message is corrupted, but not when
+ * a valid message indicates that all slots are unbootable.
+ */
+static void ab_control_default(struct andr_bl_control *abc)
+{
+ int i;
+ const struct andr_slot_metadata metadata = {
+ .priority = 15,
+ .tries_remaining = 7,
+ .successful_boot = 0,
+ .verity_corrupted = 0,
+ .reserved = 0
+ };
+
+ memcpy(abc->slot_suffix, "a\0\0\0", 4);
+ abc->magic = ANDROID_BOOT_CTRL_MAGIC;
+ abc->version = ANDROID_BOOT_CTRL_VERSION;
+ abc->nb_slot = ANDROID_NUM_SLOTS;
+ memset(abc->reserved0, 0, sizeof(abc->reserved0));
+ for (i = 0; i < abc->nb_slot; ++i)
+ abc->slot_info[i] = metadata;
+
+ memset(abc->reserved1, 0, sizeof(abc->reserved1));
+ abc->crc32_le = ab_control_compute_crc(abc);
+}
+
+/**
+ * Load the boot_control struct from disk into newly allocated memory.
+ *
+ * This function allocates and returns an integer number of disk blocks,
+ * based on the block size of the passed device to help performing a
+ * read-modify-write operation on the boot_control struct.
+ * The boot_control struct offset (2 KiB) must be a multiple of the device
+ * block size, for simplicity.
+ *
+ * @param[in] dev_desc Device where to read the boot_control struct from
+ * @param[in] part_info Partition in 'dev_desc' where to read from, normally
+ * the "misc" partition should be used
+ * @param[out] pointer to pointer to andr_bl_control data
+ * @return 0 on success and a negative on error
+ */
+static int ab_control_create_from_disk(struct blk_desc *dev_desc,
+ const disk_parti
[U-Boot] [PATCH v2 2/7] disk: part: Extend API to get partition info
This patch adds part_get_info_by_dev_and_name_or_num() function which
allows us to get partition info from its number or name. Partition of
interest is specified by string like "device_num:partition_number" or
"device_num#partition_name".
The patch was extracted from [1].
[1]
https://android-review.googlesource.com/c/platform/external/u-boot/+/729880/2
Signed-off-by: Ruslan Trofymenko
Reviewed-by: Alistair Strachan
Reviewed-by: Sam Protsenko
---
Changes in v2:
* Error codes are changed to -EINVAL instead of -1
disk/part.c| 68 ++
include/part.h | 21 ++
2 files changed, 89 insertions(+)
diff --git a/disk/part.c b/disk/part.c
index f30f9e9..7b739ad 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -675,6 +675,74 @@ int part_get_info_by_name(struct blk_desc *dev_desc, const
char *name,
return part_get_info_by_name_type(dev_desc, name, info, PART_TYPE_ALL);
}
+/**
+ * Get partition info from device number and partition name.
+ *
+ * Parse a device number and partition name string in the form of
+ * "device_num#partition_name", for example "0#misc". If the partition
+ * is found, sets dev_desc and part_info accordingly with the information
+ * of the partition with the given partition_name.
+ *
+ * @param[in] dev_iface Device interface
+ * @param[in] dev_part_str Input string argument, like "0#misc"
+ * @param[out] dev_desc Place to store the device description pointer
+ * @param[out] part_info Place to store the partition information
+ * @return 0 on success, or a negative on error
+ */
+static int part_get_info_by_dev_and_name(const char *dev_iface,
+const char *dev_part_str,
+struct blk_desc **dev_desc,
+disk_partition_t *part_info)
+{
+ char *ep;
+ const char *part_str;
+ int dev_num;
+
+ part_str = strchr(dev_part_str, '#');
+ if (!part_str || part_str == dev_part_str)
+ return -EINVAL;
+
+ dev_num = simple_strtoul(dev_part_str, &ep, 16);
+ if (ep != part_str) {
+ /* Not all the first part before the # was parsed. */
+ return -EINVAL;
+ }
+ part_str++;
+
+ *dev_desc = blk_get_dev(dev_iface, dev_num);
+ if (!*dev_desc) {
+ printf("Could not find %s %d\n", dev_iface, dev_num);
+ return -EINVAL;
+ }
+ if (part_get_info_by_name(*dev_desc, part_str, part_info) < 0) {
+ printf("Could not find \"%s\" partition\n", part_str);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+int part_get_info_by_dev_and_name_or_num(const char *dev_iface,
+const char *dev_part_str,
+struct blk_desc **dev_desc,
+disk_partition_t *part_info)
+{
+ /* Split the part_name if passed as "$dev_num#part_name". */
+ if (!part_get_info_by_dev_and_name(dev_iface, dev_part_str,
+ dev_desc, part_info))
+ return 0;
+ /*
+* Couldn't lookup by name, try looking up the partition description
+* directly.
+*/
+ if (blk_get_device_part_str(dev_iface, dev_part_str,
+ dev_desc, part_info, 1) < 0) {
+ printf("Couldn't find partition %s %s\n",
+ dev_iface, dev_part_str);
+ return -EINVAL;
+ }
+ return 0;
+}
+
void part_set_generic_name(const struct blk_desc *dev_desc,
int part_num, char *name)
{
diff --git a/include/part.h b/include/part.h
index 0750aee..9d57b65 100644
--- a/include/part.h
+++ b/include/part.h
@@ -202,6 +202,27 @@ int part_get_info_by_name(struct blk_desc *dev_desc,
const char *name, disk_partition_t *info);
/**
+ * Get partition info from dev number + part name, or dev number + part number.
+ *
+ * Parse a device number and partition description (either name or number)
+ * in the form of device number plus partition name separated by a "#"
+ * (like "device_num#partition_name") or a device number plus a partition
number
+ * separated by a ":". For example both "0#misc" and "0:1" can be valid
+ * partition descriptions for a given interface. If the partition is found,
sets
+ * dev_desc and part_info accordingly with the information of the partition.
+ *
+ * @param[in] dev_ifaceDevice interface
+ * @param[in] dev_part_str Input partition description, like "0#misc" or "0:1"
+ * @param[out] dev_descPlace to store the device description pointer
+ * @param[out] part_info Place to store the partition information
+ * @return 0 on success, or a negative on error
+ */
+int part_get_info_by_dev_and_name_or_num(const char *dev_iface,
+const char *dev_p
[U-Boot] [PATCH v2 6/7] doc: android: Add simple guide for A/B updates
Add a short documentation for A/B enablement and 'ab_select' command usage. Signed-off-by: Ruslan Trofymenko Reviewed-by: Alistair Strachan Reviewed-by: Sam Protsenko --- Changes in v2: * Сhanges related to command renaming (android_ab_select -> ab_select) doc/README.android-ab | 67 +++ 1 file changed, 67 insertions(+) create mode 100644 doc/README.android-ab diff --git a/doc/README.android-ab b/doc/README.android-ab new file mode 100644 index 000..9f37ed5 --- /dev/null +++ b/doc/README.android-ab @@ -0,0 +1,67 @@ +Android A/B updates +=== + +Overview + + +A/B system updates ensures modern approach for system update. This feature +allows one to use two sets (or more) of partitions referred to as slots +(normally slot A and slot B). The system runs from the current slot while the +partitions in the unused slot can be updated [1]. + +A/B enablement +-- + +The A/B updates support can be activated by specifying next options in +your board configuration file: + +CONFIG_ANDROID_AB=y +CONFIG_CMD_AB_SELECT=y + +The disk space on target device must be partitioned in a way so that each +partition which needs to be updated has two or more instances. The name of +each instance must be formed by adding suffixes: _a, _b, _c, etc. +For example: boot_a, boot_b, system_a, system_b, vendor_a, vendor_b. + +As a result you can use 'ab_select' command to ensure A/B boot process in your +boot script. This command analyzes and processes A/B metadata stored on a +special partition (e.g. "misc") and determines which slot should be used for +booting up. + +Command usage +- + +ab_select + +for example: + +=> ab_select slot_name mmc 1:4 + +or + +=> ab_select slot_name mmc 1#misc + +Result: + +=> printenv slot_name +slot_name=a + +Based on this slot information, the current boot partition should be defined, +and next kernel command line parameters should be generated: + + - androidboot.slot_suffix= + - root= + +For example: + +androidboot.slot_suffix=_a root=/dev/mmcblk1p12 + +A/B metadata is organized according to AOSP reference [2]. On the first system +start with A/B enabled, when 'misc' partition doesn't contain required data, +the default A/B metadata will be created and written to 'misc' partition. + +References +-- + +[1] https://source.android.com/devices/tech/ota/ab +[2] bootable/recovery/bootloader_message/include/bootloader_message/bootloader_message.h -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 7/7] env: am57xx: Implement A/B boot process
Add support for A/B boot process on AM57xx based boards:
1. Define 'slot_suffix' variable (using 'ab_select' command)
2. Extend 'emmc_android_boot' boot command (add commands for A/B boot
process)
'ab_select' command is used to decide which slot should be used for
booting up. A/B metadata resides in 'misc' partition.
To activate the A/B boot process, the following config options must be
set:
CONFIG_ANDROID_AB=y
CONFIG_CMD_AB_SELECT=y
For successful A/B boot, the corresponding A/B infrastructure must be
involved on Android side [1] (including mounting system as root), and
disk must be partitioned accordingly.
When A/B boot is enabled, there are some known limitations currently
exist (not related to A/B patches, need to be implemented later):
1. The 'Verified Boot' sequence is not supported
2. dev path to system partition (system_a or system_b) is passed via
'bootargs' as 'root=' argument like 'root=/dev/mmcblk1p12', but
further we'll need to rework it with respect to dm-verity
requirements [2]
In case when A/B partitions are not present in system (and A/B boot is
enabled), boot up process will be terminated and next message will be
shown:
"boot_a(b) partition not found"
[1] https://source.android.com/devices/tech/ota/ab
[2] https://source.android.com/devices/tech/ota/ab/ab_implement#kernel
Signed-off-by: Ruslan Trofymenko
Reviewed-by: Alistair Strachan
Reviewed-by: Sam Protsenko
---
Changes in v2:
* Сhanges related to command renaming (android_ab_select -> ab_select)
* Slotted sections (e.g. system_a and system_b) are added to the
default sections if CONFIG_CMD_AB_SELECT flag is defined
* Rebased on top of master
* system partitions sizes increased to 1024 MiB (to be consistent with
recent changes to boot.h file)
include/environment/ti/boot.h | 58 ++-
1 file changed, 52 insertions(+), 6 deletions(-)
diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
index 5891009..e3ba689 100644
--- a/include/environment/ti/boot.h
+++ b/include/environment/ti/boot.h
@@ -23,6 +23,18 @@
#define VBMETA_PART""
#endif
+#if defined(CONFIG_CMD_AB_SELECT)
+#define COMMON_PARTS \
+ "name=boot_a,size=10M,uuid=${uuid_gpt_boot_a};" \
+ "name=boot_b,size=10M,uuid=${uuid_gpt_boot_b};" \
+ "name=system_a,size=1024M,uuid=${uuid_gpt_system_a};" \
+ "name=system_b,size=1024M,uuid=${uuid_gpt_system_b};"
+#else
+#define COMMON_PARTS \
+ "name=boot,size=10M,uuid=${uuid_gpt_boot};" \
+ "name=system,size=1024M,uuid=${uuid_gpt_system};"
+#endif
+
#ifndef PARTS_DEFAULT
/* Define the default GPT table for eMMC */
#define PARTS_DEFAULT \
@@ -40,8 +52,7 @@
"name=efs,size=16M,uuid=${uuid_gpt_efs};" \
"name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \
"name=recovery,size=40M,uuid=${uuid_gpt_recovery};" \
- "name=boot,size=10M,uuid=${uuid_gpt_boot};" \
- "name=system,size=768M,uuid=${uuid_gpt_system};" \
+ COMMON_PARTS \
"name=vendor,size=256M,uuid=${uuid_gpt_vendor};" \
"name=cache,size=256M,uuid=${uuid_gpt_cache};" \
"name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \
@@ -63,6 +74,35 @@
#define AVB_VERIFY_CMD ""
#endif
+#define CONTROL_PARTITION "misc"
+
+#if defined(CONFIG_CMD_AB_SELECT)
+#define AB_SELECT \
+ "if part number mmc 1 " CONTROL_PARTITION " control_part_number; " \
+ "then " \
+ "echo " CONTROL_PARTITION \
+ " partition number:${control_part_number};" \
+ "ab_select slot_name mmc ${mmcdev}:${control_part_number};" \
+ "else " \
+ "echo " CONTROL_PARTITION " partition not found;" \
+ "exit;" \
+ "fi;" \
+ "setenv slot_suffix _${slot_name};" \
+ "if part number mmc ${mmcdev} system${slot_suffix} " \
+ "system_part_number; then " \
+ "setenv bootargs_ab " \
+ "ro root=/dev/mmcblk${mmcdev}p${system_part_number} " \
+ "rootwait init=/init skip_initramfs " \
+ "androidboot.slot_suffix=${slot_suffix};" \
+ "echo A/B cmdline addition: ${bootargs_ab};" \
+ "setenv bootargs ${bootargs} ${bootargs_ab};" \
+ "else " \
+ "echo system${slot_suffix} partition not found;" \
+ "fi;"
+#else
+#define AB_SELECT ""
+#endif
+
#define DEFAULT_COMMON_BOOT_TI_ARGS \
"console=" CONSOLEDEV ",115200n8\0" \
"fdtfile=undefined\0" \
@@ -91,10 +131,16 @@
"mmc dev $mmcdev; " \
"mmc rescan; " \
AVB_VERIFY_CHECK \
- "part start mmc ${mmcdev} boot boot_start; " \
- "part size mmc ${mmcdev} boot boot_size; " \
- "mmc read ${loadaddr} ${boot_start} ${boot_size}; " \
- "bootm ${loadaddr}#${fdtfile};\0 "
+ AB_SELECT \
+ "if
[U-Boot] [PATCH v2 4/7] cmd: Add 'ab_select' command
For A/B system update support the Android boot process requires to send
'androidboot.slot_suffix' parameter as a command line argument. This
patch implementes 'ab_select' command which allows us to obtain current
slot by processing the A/B metadata.
The patch was extracted from commit [1] with one modification: the
separator for specifying the name of metadata partition was changed
from ';' to '#', because ';' is used for commands separation.
[1]
https://android-review.googlesource.com/c/platform/external/u-boot/+/729880/2
Signed-off-by: Ruslan Trofymenko
Reviewed-by: Alistair Strachan
Reviewed-by: Sam Protsenko
---
Changes in v2:
* 'android_ab_select' command is renamed to 'ab_select' command
* command is moved to the separate 'Android support commands' menu
cmd/Kconfig | 15 +++
cmd/Makefile| 1 +
cmd/ab_select.c | 52
3 files changed, 68 insertions(+)
create mode 100644 cmd/ab_select.c
diff --git a/cmd/Kconfig b/cmd/Kconfig
index ea1a325..ed60e1e 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1123,6 +1123,21 @@ config CMD_SETEXPR
endmenu
+menu "Android support commands"
+
+config CMD_AB_SELECT
+ bool "ab_select"
+ default n
+ depends on ANDROID_AB
+ help
+ On Android devices with more than one boot slot (multiple copies of
+ the kernel and system images) this provides a command to select which
+ slot should be used to boot from and register the boot attempt. This
+ is used by the new A/B update model where one slot is updated in the
+ background while running from the other slot.
+
+endmenu
+
if NET
menuconfig CMD_NET
diff --git a/cmd/Makefile b/cmd/Makefile
index 4998643..1d345c1 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -12,6 +12,7 @@ obj-y += version.o
# command
obj-$(CONFIG_CMD_AES) += aes.o
+obj-$(CONFIG_CMD_AB_SELECT) += ab_select.o
obj-$(CONFIG_CMD_ADC) += adc.o
obj-$(CONFIG_CMD_ARMFLASH) += armflash.o
obj-y += blk_common.o
diff --git a/cmd/ab_select.c b/cmd/ab_select.c
new file mode 100644
index 000..2a9e524
--- /dev/null
+++ b/cmd/ab_select.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2017 The Android Open Source Project
+ */
+
+#include
+#include
+
+static int do_ab_select(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int ret;
+ struct blk_desc *dev_desc;
+ disk_partition_t part_info;
+ char slot[2];
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ /* Lookup the "misc" partition from argv[2] and argv[3] */
+ if (part_get_info_by_dev_and_name_or_num(argv[2], argv[3],
+&dev_desc, &part_info) < 0) {
+ return CMD_RET_FAILURE;
+ }
+
+ ret = ab_select_slot(dev_desc, &part_info);
+ if (ret < 0) {
+ printf("Android boot failed, error %d.\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ /* Android standard slot names are 'a', 'b', ... */
+ slot[0] = ANDROID_BOOT_SLOT_NAME(ret);
+ slot[1] = '\0';
+ env_set(argv[1], slot);
+ printf("ANDROID: Booting slot: %s\n", slot);
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(ab_select, 4, 0, do_ab_select,
+ "Select the slot used to boot from and register the boot attempt.",
+ " \n"
+ "- Load the slot metadata from the partition 'part' on\n"
+ " device type 'interface' instance 'dev' and store the active\n"
+ " slot in the 'slot_var_name' variable. This also updates the\n"
+ " Android slot metadata with a boot attempt, which can cause\n"
+ " successive calls to this function to return a different
result\n"
+ " if the returned slot runs out of boot attempts.\n"
+ "- If 'part_name' is passed, preceded with a # instead of :,
the\n"
+ " partition name whose label is 'part_name' will be looked up
in\n"
+ " the partition table. This is commonly the \"misc\"
partition.\n"
+);
--
2.7.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/6] Add support for MIPS Creator CI20
Hi Ezequiel, Am 12.12.18 um 14:58 schrieb Ezequiel Garcia: > A new round. > > For this new round: > > * Replaced infinite while loop with wait_for_bit. > * Added a MAINTAINERS file. If anyone wants to co-maintain this, >please let me know. > > This is based on top of yesterday's master (ee168783ae8) and has > been tested by SD-card booting both U-Boot and Linux. Booting > Linux via TFTP was also tested. > > Toolchain used to test: > > $ mips-linux-gcc -v > Using built-in specs. > COLLECT_GCC=mips-linux-gcc > COLLECT_LTO_WRAPPER=/home/zeta/.buildman-toolchains/gcc-7.3.0-nolibc/mips-linux/bin/../libexec/gcc/mips-linux/7.3.0/lto-wrapper > Target: mips-linux > Configured with: /home/arnd/git/gcc/configure --target=mips-linux > --enable-targets=all --prefix=/opt/crosstool/gcc-7.3.0-nolibc/mips-linux > --enable-languages=c --without-headers --disable-bootstrap --disable-nls > --disable-threads --disable-shared --disable-libmudflap --disable-libssp > --disable-libgomp --disable-decimal-float --disable-libquadmath > --disable-libatomic --disable-libcc1 --disable-libmpx > --enable-checking=release > Thread model: single > gcc version 7.3.0 (GCC) > > SPL size: > > $ size spl/u-boot-spl >text data bss dec hex filename >9252 752 736 1074029f4 spl/u-boot-spl > > I've pushed a branch to https://github.com/ezequielgarcia/u-boot/tree/ci20-v2 > and made sure travis passed. > Thanks for working on this but the problem with the original patch series was that it was not fully driver model compatible and that stuff like watchdog, reset and pin-muxing was open-coded instead of using the proper frameworks. As the ship is sailing towards having only driver model and device tree in U-Boot proper, it doesn't make sense to accept new SoC/boards with legacy code especially if there is no active maintainer who would do the conversion work. And with the upcoming dead lines for DM conversions, boards with legacy code will be removed when not converted. This is also one of the reasons why the Ingenic SoC support we already had in mainline was removed. And readding parts of the removed code doesn't make sense either because the patch series is based on that old Ingenic SoC code. I wanted to work on Marek's patch series to fix those issues because it's quite some work which I couldn't expect from Marek ;) But I got stuck with EJTAG because halting the CPU didn't work. Then I hadn't time anymore. I'm little busy right now so I can't do a detailed review. But the issues which should be addressed at first are: - fix all SPDX license identifiers - convert GPIO driver to DM - add a DM watchdog driver - implement machine reset with the generic watchdog reset (see BMIPS for an example) - don't use SoC specific start.S and u-boot-spl.lds, the generic code is now configurable enough and non-generic things could be done in a lowlevel_init.S - reduce the hundreds of definitions of register addresses to the ones really needed in assembly or SPL. This stuff should come from device tree - define the remaining register base addresses as physical addresses and establish a mapping with ioremap_nocache() -- - Daniel ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 00/16] SF: Migrate to Linux SPI NOR framework
U-Boot SPI NOR support (sf layer) is quite outdated as it does not support 4 byte addressing opcodes, SFDP table parsing and different types of quad mode enable sequences. Many newer flashes no longer support BANK registers used by sf layer to a access >16MB space. Also, many SPI controllers have special MMIO interfaces which provide accelerated read/write access but require knowledge of flash parameters to make use of it. Recent spi-mem layer provides a way to support such flashes but sf layer isn't using that. This patch series syncs SPI NOR framework from Linux v4.19. It also adds spi-mem support on top. So, we gain 4byte addressing support and SFDP support. This makes migrating to U-Boot MTD framework easier. Tested with few Spansion, micron and macronix flashes with TI's dra7xx, k2g, am43xx EVMs. I dont have access to flashes from other vendors. So, I would greatly appreciate testing on other platforms. Complete series with dependencies here[1] For clean build on some platforms, depends on CONFIG_SPI_FLASH migration to defconfigs [2] [1] https://github.com/r-vignesh/u-boot.git branch: spi-nor-mig-patch-v1 [2] https://patchwork.ozlabs.org/patch/1007485/ Patch 12-15 are compile tested. Change log: Since RFC v2: Fix issues reported by Simon Goldschmidt wrt 4 use of byte addressing opcode Fix issues in compiling SFDP code Re organize file names and Makefile to simply spi-nor-tiny inclusion Remove SPI_FLASH_BAR and SF_DUAL_FLASH as these are no longer used RFC v2: https://patchwork.ozlabs.org/cover/1007589/ Since RFC v1: Add lightweight SPI flash stack for boards with SPL size constraints Provide non DM version of spi-mem Fix build issues on different platforms as reported by travis-ci on v1 RFC v1: https://patchwork.ozlabs.org/cover/1004689/ Vignesh R (16): spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes spi-mem: Claim SPI bus before spi mem access spi: Add non DM version of SPI_MEM sh: bitops: add hweight*() macros mtd: spi: Port SPI NOR framework from Linux mtd: spi: Switch to new SPI NOR framework mtd: spi: Remove unused files mtd: spi: Add lightweight SPI flash stack for SPL sf_mtd: Simply mtd operations configs: Get rid of SPI_FLASH_BAR configs: Remove SF_DUAL_FLASH axm_defconfig: Enable simple malloc in SPL taurus_defconfig: Enable simple malloc in SPL da850_am18xxevm: Enable tiny printf turris_omnia_defconfig: Enable tiny printf MAINTAINERS: Add an entry for SPI NOR MAINTAINERS |8 + arch/arm/mach-omap2/am33xx/Kconfig|1 - arch/sh/include/asm/bitops.h |4 + common/spl/Kconfig| 21 +- configs/alt_defconfig |1 - configs/am57xx_evm_defconfig |1 - configs/am57xx_hs_evm_defconfig |1 - configs/ap121_defconfig |1 - configs/ap143_defconfig |1 - configs/avnet_ultra96_rev1_defconfig |1 - configs/axm_defconfig |1 + configs/axs101_defconfig |1 - configs/axs103_defconfig |1 - configs/bg0900_defconfig |1 - configs/blanche_defconfig |1 - configs/cl-som-am57x_defconfig|1 - configs/clearfog_defconfig|1 - configs/cm_t43_defconfig |1 - configs/da850_am18xxevm_defconfig |1 + configs/db-88f6820-amc_defconfig |1 - configs/display5_defconfig|1 - configs/display5_factory_defconfig|1 - configs/dra7xx_evm_defconfig |1 - configs/dra7xx_hs_evm_defconfig |1 - configs/ds109_defconfig |1 - configs/ds414_defconfig |1 - configs/evb-rv1108_defconfig |1 - configs/gose_defconfig|1 - configs/helios4_defconfig |1 - configs/k2g_evm_defconfig |1 - configs/k2g_hs_evm_defconfig |1 - configs/koelsch_defconfig |1 - configs/lager_defconfig |1 - configs/maxbcm_defconfig |1 - configs/mt7629_rfb_defconfig |1 - configs/mx6sxsabreauto_defconfig |1 - configs/mx6sxsabresd_defconfig|1 - configs/mx6ul_14x14_evk_defconfig |1 - configs/mx6ul_9x9_evk_defconfig |1 - configs/mx6ull_14x14_evk_defconfig|1 - configs/mx6ull_14x14_evk_plugin_defconfig |1 - configs/mx7dsabresd_qspi_defconfig|1 - configs/porter_defconfig |1 - configs/r8a77970_eagle_defconfig |1 - configs/silk_defconfig|1 - conf
[U-Boot] [PATCH 01/16] spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes
SPI controllers support all types of SPI modes including dual/quad bus
widths. Therefore remove constraint wrt SPI mode from spi-mem layer.
Signed-off-by: Vignesh R
---
drivers/spi/spi-mem.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index af9aef009a73..1da20b8de5c4 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -323,15 +323,6 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
return -EIO;
#else
- /* U-Boot does not support parallel SPI data lanes */
- if ((op->cmd.buswidth != 1) ||
- (op->addr.nbytes && op->addr.buswidth != 1) ||
- (op->dummy.nbytes && op->dummy.buswidth != 1) ||
- (op->data.nbytes && op->data.buswidth != 1)) {
- printf("Dual/Quad raw SPI transfers not supported\n");
- return -ENOTSUPP;
- }
-
if (op->data.nbytes) {
if (op->data.dir == SPI_MEM_DATA_IN)
rx_buf = op->data.buf.in;
--
2.19.2
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[U-Boot] [PATCH 04/16] sh: bitops: add hweight*() macros
Add hweight*() macros required for moving to new SF layer Signed-off-by: Vignesh R --- arch/sh/include/asm/bitops.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h index 8cb8385d76db..765f28f116bc 100644 --- a/arch/sh/include/asm/bitops.h +++ b/arch/sh/include/asm/bitops.h @@ -153,6 +153,10 @@ static inline int ffs (int x) } #define PLATFORM_FFS +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + #endif /* __KERNEL__ */ #endif /* __ASM_SH_BITOPS_H */ -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 03/16] spi: Add non DM version of SPI_MEM
Add non DM version of SPI_MEM to support easy migration to new SPI NOR
framework. This can be removed once DM_SPI conversion is complete.
Signed-off-by: Vignesh R
---
drivers/spi/Kconfig| 4 +-
drivers/spi/Makefile | 1 +
drivers/spi/spi-mem-nodm.c | 89 ++
3 files changed, 92 insertions(+), 2 deletions(-)
create mode 100644 drivers/spi/spi-mem-nodm.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a7bb5b35c294..5ee855fc5319 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -16,8 +16,6 @@ config DM_SPI
typically use driver-private data instead of extending the
spi_slave structure.
-if DM_SPI
-
config SPI_MEM
bool "SPI memory extension"
help
@@ -25,6 +23,8 @@ config SPI_MEM
This extension is meant to simplify interaction with SPI memories
by providing an high-level interface to send memory-like commands.
+if DM_SPI
+
config ALTERA_SPI
bool "Altera SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 392a92579578..32ba3b61f70d 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SOFT_SPI) += soft_spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem.o
else
obj-y += spi.o
+obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o
endif
diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c
new file mode 100644
index ..4d91761f56d3
--- /dev/null
+++ b/drivers/spi/spi-mem-nodm.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include
+#include
+
+int spi_mem_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ unsigned int pos = 0;
+ const u8 *tx_buf = NULL;
+ u8 *rx_buf = NULL;
+ u8 *op_buf;
+ int op_len;
+ u32 flag;
+ int ret;
+ int i;
+
+ if (op->data.nbytes) {
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ rx_buf = op->data.buf.in;
+ else
+ tx_buf = op->data.buf.out;
+ }
+
+ op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ op_buf = calloc(1, op_len);
+
+ ret = spi_claim_bus(slave);
+ if (ret < 0)
+ return ret;
+
+ op_buf[pos++] = op->cmd.opcode;
+
+ if (op->addr.nbytes) {
+ for (i = 0; i < op->addr.nbytes; i++)
+ op_buf[pos + i] = op->addr.val >>
+ (8 * (op->addr.nbytes - i - 1));
+
+ pos += op->addr.nbytes;
+ }
+
+ if (op->dummy.nbytes)
+ memset(op_buf + pos, 0xff, op->dummy.nbytes);
+
+ /* 1st transfer: opcode + address + dummy cycles */
+ flag = SPI_XFER_BEGIN;
+ /* Make sure to set END bit if no tx or rx data messages follow */
+ if (!tx_buf && !rx_buf)
+ flag |= SPI_XFER_END;
+
+ ret = spi_xfer(slave, op_len * 8, op_buf, NULL, flag);
+ if (ret)
+ return ret;
+
+ /* 2nd transfer: rx or tx data path */
+ if (tx_buf || rx_buf) {
+ ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf,
+ rx_buf, SPI_XFER_END);
+ if (ret)
+ return ret;
+ }
+
+ spi_release_bus(slave);
+
+ for (i = 0; i < pos; i++)
+ debug("%02x ", op_buf[i]);
+ debug("| [%dB %s] ",
+ tx_buf || rx_buf ? op->data.nbytes : 0,
+ tx_buf || rx_buf ? (tx_buf ? "out" : "in") : "-");
+ for (i = 0; i < op->data.nbytes; i++)
+ debug("%02x ", tx_buf ? tx_buf[i] : rx_buf[i]);
+ debug("[ret %d]\n", ret);
+
+ free(op_buf);
+
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+int spi_mem_adjust_op_size(struct spi_slave *slave,
+ struct spi_mem_op *op)
+{
+ return 0;
+}
--
2.19.2
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[U-Boot] [PATCH 02/16] spi-mem: Claim SPI bus before spi mem access
It is necessary to call spi_claim_bus() before starting any SPI transactions and this restriction would also apply when calling spi-mem operationss. Therefore claim and release bus before requesting transfer via exec_op. Signed-off-by: Vignesh R --- drivers/spi/spi-mem.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 1da20b8de5c4..4c1463118ab2 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -231,7 +231,13 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) mutex_lock(&ctlr->bus_lock_mutex); mutex_lock(&ctlr->io_mutex); #endif + ret = spi_claim_bus(slave); + if (ret < 0) + return ret; + ret = ops->mem_ops->exec_op(slave, op); + + spi_release_bus(slave); #ifndef __UBOOT__ mutex_unlock(&ctlr->io_mutex); mutex_unlock(&ctlr->bus_lock_mutex); -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 06/16] mtd: spi: Switch to new SPI NOR framework
Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/defintions
Signed-off-by: Vignesh R
---
common/spl/Kconfig | 12 +-
drivers/mtd/spi/Kconfig| 15 ++-
drivers/mtd/spi/Makefile | 4 +-
drivers/mtd/spi/sandbox.c | 36 +++---
drivers/mtd/spi/sf_dataflash.c | 11 +-
drivers/mtd/spi/sf_internal.h | 228 +++--
drivers/mtd/spi/sf_probe.c | 33 +++--
drivers/mtd/spi/spi-nor-core.c | 59 +
drivers/spi/stm32_qspi.c | 4 +-
include/spi_flash.h| 105 ---
10 files changed, 137 insertions(+), 370 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 0ddbffc7d1c6..ba6d4d71fbc6 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -727,13 +727,23 @@ config SPL_SPI_FLASH_SUPPORT
lines). This enables the drivers in drivers/mtd/spi as part of an
SPL build. This normally requires SPL_SPI_SUPPORT.
+if SPL_SPI_FLASH_SUPPORT
+
+config SPL_SPI_FLASH_SFDP_SUPPORT
+ bool "SFDP table parsing support for SPI NOR flashes"
+ help
+Enable support for parsing and auto discovery of parameters for
+SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
+tables as per JESD216 standard in SPL.
+
config SPL_SPI_LOAD
bool "Support loading from SPI flash"
- depends on SPL_SPI_FLASH_SUPPORT
help
Enable support for loading next stage, U-Boot or otherwise, from
SPI NOR in U-Boot SPL.
+endif # SPL_SPI_FLASH_SUPPORT
+
config SPL_SPI_SUPPORT
bool "Support SPI drivers"
help
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 76d5a1d11527..8bd6db6ff4d3 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -27,6 +27,8 @@ config SPI_FLASH_SANDBOX
config SPI_FLASH
bool "Legacy SPI Flash Interface support"
+ depends on SPI
+ select SPI_MEM
help
Enable the legacy SPI flash support. This will include basic
standard support for things like probing, read / write, and
@@ -34,9 +36,17 @@ config SPI_FLASH
If unsure, say N
+if SPI_FLASH
+
+config SPI_FLASH_SFDP_SUPPORT
+ bool "SFDP table parsing support for SPI NOR flashes"
+ help
+Enable support for parsing and auto discovery of parameters for
+SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
+tables as per JESD216 standard.
+
config SPI_FLASH_BAR
bool "SPI flash Bank/Extended address register support"
- depends on SPI_FLASH
help
Enable the SPI flash Bank/Extended address register support.
Bank/Extended address registers are used to access the flash
@@ -44,13 +54,10 @@ config SPI_FLASH_BAR
config SF_DUAL_FLASH
bool "SPI DUAL flash memory support"
- depends on SPI_FLASH
help
Enable this option to support two flash memories connected to a single
controller. Currently Xilinx Zynq qspi supports this.
-if SPI_FLASH
-
config SPI_FLASH_ATMEL
bool "Atmel SPI flash support"
help
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index b4c7e1c98bd5..70058d3df2b9 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -9,7 +9,7 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
endif
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o spi_flash_ids.o sf.o
-obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
+obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor-core.o
+obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o
obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 7b9891cb981c..084c66e9840b 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -92,7 +92,7 @@ struct sandbox_spi_flash {
/* The current flash status (see STAT_XXX defines above) */
u16 status;
/* Data describing the flash we're emulating */
- const struct spi_flash_info *data;
+ const struct flash_info *data;
/* The file on disk to serv up data from */
int fd;
};
@@ -122,7 +122,7 @@ static int sandbox_sf_probe(struct udevice *dev)
/* spec = idcode:file */
struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
size_t len, idname_len;
- const struct spi_flash_info *data;
+ const struct flash_info *data;
struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
struct sandbox_state *state = state_get_current();
struct dm_spi_slave_platdata *slave_plat;
@@ -155,7 +155,7 @@ static int sandbox_sf_probe(struct udevice *dev)
idname_len = strlen(spec);
debug("%s: device='%s'\n", __func__, spec);
- for (data = spi_f
[U-Boot] [PATCH 05/16] mtd: spi: Port SPI NOR framework from Linux
Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different types of
quad mode enable sequences. Many newer flashes no longer support BANK
registers used by sf layer to a access >16MB space.
Also, many SPI controllers have special MMIO interfaces which provide
accelerated read/write access but require knowledge of flash parameters
to make use of it. Recent spi-mem layer provides a way to support such
flashes but sf layer isn't using that.
So sync SPI NOR framework from Linux v4.19 and add spi-mem support on top.
in order to gain 4 byte addressing support, SFDP support and a way to
support SPI controllers with MMIO flash interface.
Signed-off-by: Vignesh R
---
drivers/mtd/spi/spi-nor-core.c | 2647
include/linux/mtd/cfi.h| 32 +
include/linux/mtd/spi-nor.h| 421 +
3 files changed, 3100 insertions(+)
create mode 100644 drivers/mtd/spi/spi-nor-core.c
create mode 100644 include/linux/mtd/cfi.h
create mode 100644 include/linux/mtd/spi-nor.h
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
new file mode 100644
index ..4563cd74c2e8
--- /dev/null
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -0,0 +1,2647 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Based on m25p80.c, by Mike Lavender (m...@steroidmicros.com), with
+ * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
+ *
+ * Copyright (C) 2005, Intec Automation Inc.
+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
+ *
+ * Synced from Linux v4.19
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+/* Define max times to check status register before we give up. */
+
+/*
+ * For everything but full-chip erase; probably could be much smaller, but kept
+ * around for safety for now
+ */
+
+#define HZ CONFIG_SYS_HZ
+
+#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
+
+#define SPI_NOR_MAX_ID_LEN 6
+#define SPI_NOR_MAX_ADDR_WIDTH 4
+
+struct flash_info {
+ char*name;
+
+ /*
+* This array stores the ID bytes.
+* The first three bytes are the JEDIC ID.
+* JEDEC ID zero means "no ID" (mostly older chips).
+*/
+ u8 id[SPI_NOR_MAX_ID_LEN];
+ u8 id_len;
+
+ /* The size listed here is what works with SPINOR_OP_SE, which isn't
+* necessarily called a "sector" by the vendor.
+*/
+ unsigned intsector_size;
+ u16 n_sectors;
+
+ u16 page_size;
+ u16 addr_width;
+
+ u16 flags;
+#define SECT_4KBIT(0) /* SPINOR_OP_BE_4K works
uniformly */
+#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
+#define SST_WRITE BIT(2) /* use SST byte programming */
+#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
+#define SECT_4K_PMCBIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly
*/
+#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
+#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
+#define USE_FSRBIT(7) /* use flag status register */
+#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
+#define SPI_NOR_HAS_TB BIT(9) /*
+* Flash SR has Top/Bottom (TB) protect
+* bit. Must be used with
+* SPI_NOR_HAS_LOCK.
+*/
+#defineSPI_S3ANBIT(10) /*
+* Xilinx Spartan 3AN In-System Flash
+* (MFR cannot be used for probing
+* because it has the same value as
+* ATMEL flashes)
+*/
+#define SPI_NOR_4B_OPCODES BIT(11) /*
+* Use dedicated 4byte address op codes
+* to support memory size above 128Mib.
+*/
+#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
+#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
+#define USE_CLSR BIT(14) /* use CLSR command */
+
+ int (*quad_enable)(struct spi_nor *nor);
+};
+
+#define JEDEC_MFR(info)((info)->id[0])
+
+static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
+ *op, void *buf)
+{
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ op->data.buf.in = buf;
+ else
+ op->data.buf.out = buf;
+ return spi_mem_exec_op(nor->spi, op);
+}
+
+static int spi_nor
[U-Boot] [PATCH 07/16] mtd: spi: Remove unused files
spi_flash and spi_flash_ids are no longer needed after SPI NOR
migration. Remove them.
Signed-off-by: Vignesh R
---
drivers/mtd/spi/spi_flash.c | 1337 ---
drivers/mtd/spi/spi_flash_ids.c | 211 -
2 files changed, 1548 deletions(-)
delete mode 100644 drivers/mtd/spi/spi_flash.c
delete mode 100644 drivers/mtd/spi/spi_flash_ids.c
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
deleted file mode 100644
index 0c2392f28a43..
--- a/drivers/mtd/spi/spi_flash.c
+++ /dev/null
@@ -1,1337 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SPI Flash Core
- *
- * Copyright (C) 2015 Jagan Teki
- * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
- * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
- * Copyright (C) 2008 Atmel Corporation
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include "sf_internal.h"
-
-static void spi_flash_addr(u32 addr, u8 *cmd)
-{
- /* cmd[0] is actual command */
- cmd[1] = addr >> 16;
- cmd[2] = addr >> 8;
- cmd[3] = addr >> 0;
-}
-
-static int read_sr(struct spi_flash *flash, u8 *rs)
-{
- int ret;
- u8 cmd;
-
- cmd = CMD_READ_STATUS;
- ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
- if (ret < 0) {
- debug("SF: fail to read status register\n");
- return ret;
- }
-
- return 0;
-}
-
-static int read_fsr(struct spi_flash *flash, u8 *fsr)
-{
- int ret;
- const u8 cmd = CMD_FLAG_STATUS;
-
- ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1);
- if (ret < 0) {
- debug("SF: fail to read flag status register\n");
- return ret;
- }
-
- return 0;
-}
-
-static int write_sr(struct spi_flash *flash, u8 ws)
-{
- u8 cmd;
- int ret;
-
- cmd = CMD_WRITE_STATUS;
- ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
- if (ret < 0) {
- debug("SF: fail to write status register\n");
- return ret;
- }
-
- return 0;
-}
-
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
-static int read_cr(struct spi_flash *flash, u8 *rc)
-{
- int ret;
- u8 cmd;
-
- cmd = CMD_READ_CONFIG;
- ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
- if (ret < 0) {
- debug("SF: fail to read config register\n");
- return ret;
- }
-
- return 0;
-}
-
-static int write_cr(struct spi_flash *flash, u8 wc)
-{
- u8 data[2];
- u8 cmd;
- int ret;
-
- ret = read_sr(flash, &data[0]);
- if (ret < 0)
- return ret;
-
- cmd = CMD_WRITE_STATUS;
- data[1] = wc;
- ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
- if (ret) {
- debug("SF: fail to write config register\n");
- return ret;
- }
-
- return 0;
-}
-#endif
-
-int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash)
-{
- u8 status;
- int ret;
-
- ret = read_sr(flash, &status);
- if (ret)
- return ret;
-
- return (status >> 2) & 7;
-}
-
-#ifdef CONFIG_SPI_FLASH_BAR
-/*
- * This "clean_bar" is necessary in a situation when one was accessing
- * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
- *
- * After it the BA24 bit shall be cleared to allow access to correct
- * memory region after SW reset (by calling "reset" command).
- *
- * Otherwise, the BA24 bit may be left set and then after reset, the
- * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
- */
-static int clean_bar(struct spi_flash *flash)
-{
- u8 cmd, bank_sel = 0;
-
- if (flash->bank_curr == 0)
- return 0;
- cmd = flash->bank_write_cmd;
- flash->bank_curr = 0;
-
- return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
-}
-
-static int write_bar(struct spi_flash *flash, u32 offset)
-{
- u8 cmd, bank_sel;
- int ret;
-
- bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
- if (bank_sel == flash->bank_curr)
- goto bar_end;
-
- cmd = flash->bank_write_cmd;
- ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
- if (ret < 0) {
- debug("SF: fail to write bank register\n");
- return ret;
- }
-
-bar_end:
- flash->bank_curr = bank_sel;
- return flash->bank_curr;
-}
-
-static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
-{
- u8 curr_bank = 0;
- int ret;
-
- if (flash->size <= SPI_FLASH_16MB_BOUN)
- goto bar_end;
-
- switch (JEDEC_MFR(info)) {
- case SPI_FLASH_CFI_MFR_SPANSION:
- flash->bank_read_cmd = CMD_BANKADDR_BRRD;
- flash->bank_write_cmd = CMD_BANKADDR_BRWR;
- break;
- default:
-
[U-Boot] [PATCH 09/16] sf_mtd: Simply mtd operations
Now that there is new SPI NOR framework, simplify mtd device
registration and read/write/erase operations.
Signed-off-by: Vignesh R
---
drivers/mtd/spi/sf_internal.h | 2 +-
drivers/mtd/spi/sf_mtd.c | 52 ++-
drivers/mtd/spi/sf_probe.c| 5 ++--
3 files changed, 24 insertions(+), 35 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 7e7d400cdbdf..8b445bb0b506 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -99,6 +99,6 @@ int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);
#ifdef CONFIG_SPI_FLASH_MTD
int spi_flash_mtd_register(struct spi_flash *flash);
-void spi_flash_mtd_unregister(void);
+void spi_flash_mtd_unregister(struct spi_flash *flash);
#endif
#endif /* _SF_INTERNAL_H_ */
diff --git a/drivers/mtd/spi/sf_mtd.c b/drivers/mtd/spi/sf_mtd.c
index 68c36002bee2..65185b7c57dc 100644
--- a/drivers/mtd/spi/sf_mtd.c
+++ b/drivers/mtd/spi/sf_mtd.c
@@ -9,21 +9,19 @@
#include
#include
-static struct mtd_info sf_mtd_info;
static bool sf_mtd_registered;
static char sf_mtd_name[8];
static int spi_flash_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
{
- struct spi_flash *flash = mtd->priv;
int err;
- if (!flash)
+ if (!mtd || !mtd->priv)
return -ENODEV;
instr->state = MTD_ERASING;
- err = spi_flash_erase(flash, instr->addr, instr->len);
+ err = mtd->_erase(mtd, instr);
if (err) {
instr->state = MTD_ERASE_FAILED;
instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
@@ -39,13 +37,12 @@ static int spi_flash_mtd_erase(struct mtd_info *mtd, struct
erase_info *instr)
static int spi_flash_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
- struct spi_flash *flash = mtd->priv;
int err;
- if (!flash)
+ if (!mtd || !mtd->priv)
return -ENODEV;
- err = spi_flash_read(flash, from, len, buf);
+ err = mtd->_read(mtd, from, len, retlen, buf);
if (!err)
*retlen = len;
@@ -55,13 +52,12 @@ static int spi_flash_mtd_read(struct mtd_info *mtd, loff_t
from, size_t len,
static int spi_flash_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
size_t *retlen, const u_char *buf)
{
- struct spi_flash *flash = mtd->priv;
int err;
- if (!flash)
+ if (!mtd || !mtd->priv)
return -ENODEV;
- err = spi_flash_write(flash, to, len, buf);
+ err = mtd->_write(mtd, to, len, retlen, buf);
if (!err)
*retlen = len;
@@ -83,10 +79,11 @@ static int spi_flash_mtd_number(void)
int spi_flash_mtd_register(struct spi_flash *flash)
{
+ struct mtd_info *mtd = &flash->mtd;
int ret;
if (sf_mtd_registered) {
- ret = del_mtd_device(&sf_mtd_info);
+ ret = del_mtd_device(mtd);
if (ret)
return ret;
@@ -94,42 +91,33 @@ int spi_flash_mtd_register(struct spi_flash *flash)
}
sf_mtd_registered = false;
- memset(&sf_mtd_info, 0, sizeof(sf_mtd_info));
sprintf(sf_mtd_name, "nor%d", spi_flash_mtd_number());
- sf_mtd_info.name = sf_mtd_name;
- sf_mtd_info.type = MTD_NORFLASH;
- sf_mtd_info.flags = MTD_CAP_NORFLASH;
- sf_mtd_info.writesize = 1;
- sf_mtd_info.writebufsize = flash->page_size;
-
- sf_mtd_info._erase = spi_flash_mtd_erase;
- sf_mtd_info._read = spi_flash_mtd_read;
- sf_mtd_info._write = spi_flash_mtd_write;
- sf_mtd_info._sync = spi_flash_mtd_sync;
-
- sf_mtd_info.size = flash->size;
- sf_mtd_info.priv = flash;
+ mtd->name = sf_mtd_name;
+ mtd->_erase = spi_flash_mtd_erase;
+ mtd->_read = spi_flash_mtd_read;
+ mtd->_write = spi_flash_mtd_write;
+ mtd->_sync = spi_flash_mtd_sync;
/* Only uniform flash devices for now */
- sf_mtd_info.numeraseregions = 0;
- sf_mtd_info.erasesize = flash->sector_size;
+ mtd->numeraseregions = 0;
- ret = add_mtd_device(&sf_mtd_info);
+ ret = add_mtd_device(mtd);
if (!ret)
sf_mtd_registered = true;
return ret;
}
-void spi_flash_mtd_unregister(void)
+void spi_flash_mtd_unregister(struct spi_flash *flash)
{
+ struct mtd_info *mtd = &flash->mtd;
int ret;
if (!sf_mtd_registered)
return;
- ret = del_mtd_device(&sf_mtd_info);
+ ret = del_mtd_device(mtd);
if (!ret) {
sf_mtd_registered = false;
return;
@@ -141,7 +129,7 @@ void spi_flash_mtd_unregister(void)
* use-after-free bug. Still, things should be fixed to prevent the
* spi_flash object from being destroyed when del_mtd_device() fails.
*/
- sf_mtd_info.priv = NULL;
+ mtd->priv = NULL;
[U-Boot] [PATCH 08/16] mtd: spi: Add lightweight SPI flash stack for SPL
Add a tiny SPI flash stack that just supports reading data/images from
SPI flash. This is useful for boards that have SPL size constraints and
would need to use SPI flash framework just to read images/data from
flash. There is approximately 1.5 to 2KB savings with this.
Based on prior work of reducing spi flash id table by
Simon Goldschmidt
Signed-off-by: Vignesh R
---
common/spl/Kconfig | 9 +
drivers/mtd/spi/Makefile | 10 +-
drivers/mtd/spi/sf_internal.h | 2 +
drivers/mtd/spi/spi-nor-core.c | 266 +--
drivers/mtd/spi/spi-nor-ids.c | 294
drivers/mtd/spi/spi-nor-tiny.c | 810 +
6 files changed, 1128 insertions(+), 263 deletions(-)
create mode 100644 drivers/mtd/spi/spi-nor-ids.c
create mode 100644 drivers/mtd/spi/spi-nor-tiny.c
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index ba6d4d71fbc6..7433c049332d 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -729,8 +729,17 @@ config SPL_SPI_FLASH_SUPPORT
if SPL_SPI_FLASH_SUPPORT
+config SPL_SPI_FLASH_TINY
+ bool "Enable low footprint SPL SPI Flash support"
+ help
+Enable lightweight SPL SPI Flash support that supports just reading
+data/images from flash. No support to write/erase flash. Enable
+this if you have SPL size limitations and don't need full
+fledged SPI flash support.
+
config SPL_SPI_FLASH_SFDP_SUPPORT
bool "SFDP table parsing support for SPI NOR flashes"
+ depends on !SPL_SPI_FLASH_TINY
help
Enable support for parsing and auto discovery of parameters for
SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 70058d3df2b9..f99f6cb16e29 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -4,12 +4,20 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
+spi-nor-y := sf_probe.o spi-nor-ids.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
+ifeq ($(CONFIG_SPL_SPI_FLASH_TINY),y)
+spi-nor-y += spi-nor-tiny.o
+else
+spi-nor-y += spi-nor-core.o
+endif
+else
+spi-nor-y += spi-nor-core.o
endif
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor-core.o
+obj-$(CONFIG_SPI_FLASH) += spi-nor.o
obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o
obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 55619f5aea5c..7e7d400cdbdf 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -16,7 +16,9 @@
#define SPI_NOR_MAX_ADDR_WIDTH 4
struct flash_info {
+#if !CONFIG_IS_ENABLED(SPI_FLASH_TINY)
char*name;
+#endif
/*
* This array stores the ID bytes.
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 97bf205c2d2d..879da2ee74e1 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -824,284 +824,26 @@ static int spi_nor_is_locked(struct mtd_info *mtd,
loff_t ofs, uint64_t len)
return ret;
}
-/* Used when the "_ext_id" is two bytes at most */
-#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
- .id = { \
- ((_jedec_id) >> 16) & 0xff, \
- ((_jedec_id) >> 8) & 0xff, \
- (_jedec_id) & 0xff, \
- ((_ext_id) >> 8) & 0xff,\
- (_ext_id) & 0xff, \
- }, \
- .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),
\
- .sector_size = (_sector_size), \
- .n_sectors = (_n_sectors), \
- .page_size = 256, \
- .flags = (_flags),
-
-#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
- .id = { \
- ((_jedec_id) >> 16) & 0xff, \
- ((_jedec_id) >> 8) & 0xff, \
- (_jedec_id) & 0xff, \
- ((_ext_id) >> 16) & 0xff, \
- ((_ext_id) >> 8) & 0xff,\
- (_ext_id) & 0xff, \
- }, \
- .id_len = 6,\
- .sector_size = (_sector_size),
[U-Boot] [PATCH 10/16] configs: Get rid of SPI_FLASH_BAR
Now that we have new SPI NOR framework in place that supports 4 byte addressing mode by default, get rid of CONFIG_SPI_FLASH_BAR Signed-off-by: Vignesh R --- arch/arm/mach-omap2/am33xx/Kconfig | 1 - configs/alt_defconfig| 1 - configs/am57xx_evm_defconfig | 1 - configs/am57xx_hs_evm_defconfig | 1 - configs/ap121_defconfig | 1 - configs/ap143_defconfig | 1 - configs/avnet_ultra96_rev1_defconfig | 1 - configs/axs101_defconfig | 1 - configs/axs103_defconfig | 1 - configs/bg0900_defconfig | 1 - configs/blanche_defconfig| 1 - configs/cl-som-am57x_defconfig | 1 - configs/clearfog_defconfig | 1 - configs/cm_t43_defconfig | 1 - configs/db-88f6820-amc_defconfig | 1 - configs/display5_defconfig | 1 - configs/display5_factory_defconfig | 1 - configs/dra7xx_evm_defconfig | 1 - configs/dra7xx_hs_evm_defconfig | 1 - configs/ds109_defconfig | 1 - configs/ds414_defconfig | 1 - configs/evb-rv1108_defconfig | 1 - configs/gose_defconfig | 1 - configs/helios4_defconfig| 1 - configs/k2g_evm_defconfig| 1 - configs/k2g_hs_evm_defconfig | 1 - configs/koelsch_defconfig| 1 - configs/lager_defconfig | 1 - configs/maxbcm_defconfig | 1 - configs/mt7629_rfb_defconfig | 1 - configs/mx6sxsabreauto_defconfig | 1 - configs/mx6sxsabresd_defconfig | 1 - configs/mx6ul_14x14_evk_defconfig| 1 - configs/mx6ul_9x9_evk_defconfig | 1 - configs/mx6ull_14x14_evk_defconfig | 1 - configs/mx6ull_14x14_evk_plugin_defconfig| 1 - configs/mx7dsabresd_qspi_defconfig | 1 - configs/porter_defconfig | 1 - configs/r8a77970_eagle_defconfig | 1 - configs/silk_defconfig | 1 - configs/socfpga_arria5_defconfig | 1 - configs/socfpga_cyclone5_defconfig | 1 - configs/socfpga_is1_defconfig| 1 - configs/socfpga_sockit_defconfig | 1 - configs/socfpga_socrates_defconfig | 1 - configs/socfpga_sr1500_defconfig | 1 - configs/socfpga_stratix10_defconfig | 1 - configs/stout_defconfig | 1 - configs/topic_miami_defconfig| 1 - configs/topic_miamilite_defconfig| 1 - configs/topic_miamiplus_defconfig| 1 - configs/xilinx_versal_virt_defconfig | 1 - configs/xilinx_zynqmp_mini_qspi_defconfig| 1 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu102_rev1_0_defconfig| 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - configs/zynq_cc108_defconfig | 1 - configs/zynq_cse_qspi_defconfig | 1 - configs/zynq_dlc20_rev1_0_defconfig | 1 - configs/zynq_microzed_defconfig | 1 - configs/zynq_minized_defconfig | 1 - configs/zynq_z_turn_defconfig| 1 - configs/zynq_zc702_defconfig | 1 - configs/zynq_zc706_defconfig | 1 - configs/zynq_zc770_xm010_defconfig | 1 - configs/zynq_zc770_xm013_defconfig | 1 - configs/zynq_zed_defconfig | 1 - configs/zynq_zybo_defconfig | 1 - configs/zynq_zybo_z7_defconfig | 1 - doc/SPI/README.ti_qspi_dra_test | 1 - drivers/mtd/spi/Kconfig | 7 --- include/configs/T102xQDS.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/
[U-Boot] [PATCH 14/16] da850_am18xxevm: Enable tiny printf
Enable tiny printf to reduce SPL size Signed-off-by: Vignesh R --- configs/da850_am18xxevm_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig index 58745fec8267..5fecfccba50c 100644 --- a/configs/da850_am18xxevm_defconfig +++ b/configs/da850_am18xxevm_defconfig @@ -57,3 +57,4 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y # CONFIG_FAT_WRITE is not set +CONFIG_USE_TINY_PRINTF=y -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 12/16] axm_defconfig: Enable simple malloc in SPL
Enable CONFIG_SPL_SYS_MALLOC_SIMPLE in SPL to reduce SPL size Signed-off-by: Vignesh R --- configs/axm_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/axm_defconfig b/configs/axm_defconfig index 89d6b6f2012c..16c093b37b83 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -44,3 +44,4 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
