Re: [U-Boot] [PATCH 0/3] Ethernet support for QEMU sifive_u machine
Hi Anup, On Mon, Dec 24, 2018 at 3:23 PM Anup Patel wrote: > > On Mon, Dec 24, 2018 at 12:45 PM Bin Meng wrote: > > > > Hi Anup, > > > > On Mon, Dec 24, 2018 at 2:42 PM Anup Patel wrote: > > > > > > On Mon, Dec 24, 2018 at 12:01 PM Bin Meng wrote: > > > > > > > > Hi Anup, > > > > > > > > On Mon, Dec 24, 2018 at 1:41 PM Anup Patel wrote: > > > > > > > > > > On Mon, Dec 24, 2018 at 6:59 AM Bin Meng wrote: > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > On Wed, Dec 19, 2018 at 5:05 PM Bin Meng wrote: > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > On Wed, Dec 19, 2018 at 2:32 PM Anup Patel > > > > > > > wrote: > > > > > > > > > > > > > > > > On Wed, Dec 19, 2018 at 11:02 AM Bin Meng > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > > > > > On Wed, Dec 19, 2018 at 12:41 PM Anup Patel > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 4:06 PM Bin Meng > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 6:33 PM Anup Patel > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 3:21 PM Bin Meng > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > > > > > > > > > > > > > On Mon, Dec 17, 2018 at 7:51 PM Anup Patel > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > This patchset enables Cadance MACB ethernet driver > > > > > > > > > > > > > > for > > > > > > > > > > > > > > QEMU sifive_u machine. The Cadance MACB ethernet > > > > > > > > > > > > > > driver > > > > > > > > > > > > > > works fine for QEMU sifive_u machince in both > > > > > > > > > > > > > > M-mode and > > > > > > > > > > > > > > S-mode with some minor fixes. > > > > > > > > > > > > > > > > > > > > > > > > > > > > The patches are based upon latest RISC-V U-Boot tree > > > > > > > > > > > > > > (git://git.denx.de/u-boot-riscv.git) at commit id > > > > > > > > > > > > > > 9deb8d2fcd13d4a40a4e63c396fe4376af46efac > > > > > > > > > > > > > > > > > > > > > > > > > > > > To try on QEMU, please ensure following patches are > > > > > > > > > > > > > > applied to QEMU sources: > > > > > > > > > > > > > > https://patchwork.kernel.org/patch/10729579/ > > > > > > > > > > > > > > https://patchwork.kernel.org/patch/10729581/ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > What "-device " parameter should I tell QEMU to > > > > > > > > > > > > > instantiate the MACB? > > > > > > > > > > > > > "-device ?" does not give me anything that looks like > > > > > > > > > > > > > MACB. Without a > > > > > > > > > > > > > proper "-device " parameter, I can boot U-Boot on > > > > > > > > > > > > > QEMU sifive_u and > > > > > > > > > > > > > see U-Boot driver is probed, but a simple 'ping' test > > > > > > > > > > > > > does not work. > > > > > > > > > > > > > > > > > > > > > > > > Try the following: > > > > > > > > > > > > # setenv ipaddr 10.0.2.1 > > > > > > > > > > > > # ping 10.0.2.2 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, I have set up all the required network parameters. > > > > > > > > > > > > > > > > > > > > > > > The above works for me on QEMU. > > > > > > > > > > > > > > > > > > > > > > My understanding is that we need enable QEMU network via > > > > > > > > > > > "-netdev " > > > > > > > > > > > (either usr, or tap), with a corresponding "-device". I > > > > > > > > > > > don't know how > > > > > > > > > > > to set it up. What's your command line to test this? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > "-netdev" or "-device" parameters are not mandatory. By > > > > > > > > > > default, virtual > > > > > > > > > > NICs are in NAT mode. The QEMU NAT gateway is at IP address > > > > > > > > > > 10.0.2.2. We can always ping the NAT gateway when virtual > > > > > > > > > > NIC is in > > > > > > > > > > NAT mode. > > > > > > > > > > > > > > > > > > > > Here's how I compile for M-mode: > > > > > > > > > > # ARCH=riscv > > > > > > > > > > # CROSS_COMPILE=riscv64-unknown-linux-gnu- > > > > > > > > > > # make qemu-riscv64_defconfig > > > > > > > > > > # make > > > > > > > > > > > > > > > > > > > > My U-boot log is as follows: > > > > > > > > > > > > > > > > > > > > anup@anup-ubuntu64:~/Work/riscv-test/u-boot$ > > > > > > > > > > qemu-system-riscv64 -M > > > > > > > > > > sifive_u -m 256M -display none -serial stdio -kernel > > > > > > > > > > ./u-boot > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > U-Boot 2019.01-rc1-00948-ge6b3cdafd0 (Dec 19 2018 - > > > > > > > > > > 10:05:50 +0530) > > > > > > > > > > > > > > > > > > > > CPU: rv64imafdcsu > > > > > > > > > > Model: ucbbar,spike-bare,qemu > > > > > > > > > > DRAM: 256 MiB > > > > > > > > > > In:uart@10013000 > > > > > > > > > > Out:
Re: [U-Boot] [PATCH 0/3] Ethernet support for QEMU sifive_u machine
On Mon, Dec 24, 2018 at 12:45 PM Bin Meng wrote: > > Hi Anup, > > On Mon, Dec 24, 2018 at 2:42 PM Anup Patel wrote: > > > > On Mon, Dec 24, 2018 at 12:01 PM Bin Meng wrote: > > > > > > Hi Anup, > > > > > > On Mon, Dec 24, 2018 at 1:41 PM Anup Patel wrote: > > > > > > > > On Mon, Dec 24, 2018 at 6:59 AM Bin Meng wrote: > > > > > > > > > > Hi Anup, > > > > > > > > > > On Wed, Dec 19, 2018 at 5:05 PM Bin Meng wrote: > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > On Wed, Dec 19, 2018 at 2:32 PM Anup Patel > > > > > > wrote: > > > > > > > > > > > > > > On Wed, Dec 19, 2018 at 11:02 AM Bin Meng > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > > > On Wed, Dec 19, 2018 at 12:41 PM Anup Patel > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 4:06 PM Bin Meng > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 6:33 PM Anup Patel > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 3:21 PM Bin Meng > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > > > > > > > > > > > On Mon, Dec 17, 2018 at 7:51 PM Anup Patel > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > This patchset enables Cadance MACB ethernet driver for > > > > > > > > > > > > > QEMU sifive_u machine. The Cadance MACB ethernet > > > > > > > > > > > > > driver > > > > > > > > > > > > > works fine for QEMU sifive_u machince in both M-mode > > > > > > > > > > > > > and > > > > > > > > > > > > > S-mode with some minor fixes. > > > > > > > > > > > > > > > > > > > > > > > > > > The patches are based upon latest RISC-V U-Boot tree > > > > > > > > > > > > > (git://git.denx.de/u-boot-riscv.git) at commit id > > > > > > > > > > > > > 9deb8d2fcd13d4a40a4e63c396fe4376af46efac > > > > > > > > > > > > > > > > > > > > > > > > > > To try on QEMU, please ensure following patches are > > > > > > > > > > > > > applied to QEMU sources: > > > > > > > > > > > > > https://patchwork.kernel.org/patch/10729579/ > > > > > > > > > > > > > https://patchwork.kernel.org/patch/10729581/ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > What "-device " parameter should I tell QEMU to > > > > > > > > > > > > instantiate the MACB? > > > > > > > > > > > > "-device ?" does not give me anything that looks like > > > > > > > > > > > > MACB. Without a > > > > > > > > > > > > proper "-device " parameter, I can boot U-Boot on QEMU > > > > > > > > > > > > sifive_u and > > > > > > > > > > > > see U-Boot driver is probed, but a simple 'ping' test > > > > > > > > > > > > does not work. > > > > > > > > > > > > > > > > > > > > > > Try the following: > > > > > > > > > > > # setenv ipaddr 10.0.2.1 > > > > > > > > > > > # ping 10.0.2.2 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, I have set up all the required network parameters. > > > > > > > > > > > > > > > > > > > > > The above works for me on QEMU. > > > > > > > > > > > > > > > > > > > > My understanding is that we need enable QEMU network via > > > > > > > > > > "-netdev " > > > > > > > > > > (either usr, or tap), with a corresponding "-device". I > > > > > > > > > > don't know how > > > > > > > > > > to set it up. What's your command line to test this? > > > > > > > > > > > > > > > > > > > > > > > > > > > > "-netdev" or "-device" parameters are not mandatory. By > > > > > > > > > default, virtual > > > > > > > > > NICs are in NAT mode. The QEMU NAT gateway is at IP address > > > > > > > > > 10.0.2.2. We can always ping the NAT gateway when virtual NIC > > > > > > > > > is in > > > > > > > > > NAT mode. > > > > > > > > > > > > > > > > > > Here's how I compile for M-mode: > > > > > > > > > # ARCH=riscv > > > > > > > > > # CROSS_COMPILE=riscv64-unknown-linux-gnu- > > > > > > > > > # make qemu-riscv64_defconfig > > > > > > > > > # make > > > > > > > > > > > > > > > > > > My U-boot log is as follows: > > > > > > > > > > > > > > > > > > anup@anup-ubuntu64:~/Work/riscv-test/u-boot$ > > > > > > > > > qemu-system-riscv64 -M > > > > > > > > > sifive_u -m 256M -display none -serial stdio -kernel ./u-boot > > > > > > > > > > > > > > > > > > > > > > > > > > > U-Boot 2019.01-rc1-00948-ge6b3cdafd0 (Dec 19 2018 - 10:05:50 > > > > > > > > > +0530) > > > > > > > > > > > > > > > > > > CPU: rv64imafdcsu > > > > > > > > > Model: ucbbar,spike-bare,qemu > > > > > > > > > DRAM: 256 MiB > > > > > > > > > In:uart@10013000 > > > > > > > > > Out: uart@10013000 > > > > > > > > > Err: uart@10013000 > > > > > > > > > Net: > > > > > > > > > Warning: ethernet@100900fc (eth0) using random MAC address - > > > > > > > > > f6:1f:8c:13:83:c0 > > > > > > > > > eth0: ethernet@100900fc > > > > > > > > > Hit any key to stop autoboot: 0 > > > > > > > > > > > > > > > > > > Device 0: unknown device > >
Re: [U-Boot] [PATCH 0/3] Ethernet support for QEMU sifive_u machine
Hi Anup, On Mon, Dec 24, 2018 at 2:42 PM Anup Patel wrote: > > On Mon, Dec 24, 2018 at 12:01 PM Bin Meng wrote: > > > > Hi Anup, > > > > On Mon, Dec 24, 2018 at 1:41 PM Anup Patel wrote: > > > > > > On Mon, Dec 24, 2018 at 6:59 AM Bin Meng wrote: > > > > > > > > Hi Anup, > > > > > > > > On Wed, Dec 19, 2018 at 5:05 PM Bin Meng wrote: > > > > > > > > > > Hi Anup, > > > > > > > > > > On Wed, Dec 19, 2018 at 2:32 PM Anup Patel > > > > > wrote: > > > > > > > > > > > > On Wed, Dec 19, 2018 at 11:02 AM Bin Meng > > > > > > wrote: > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > On Wed, Dec 19, 2018 at 12:41 PM Anup Patel > > > > > > > wrote: > > > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 4:06 PM Bin Meng > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 6:33 PM Anup Patel > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 3:21 PM Bin Meng > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > > > > > > > > > On Mon, Dec 17, 2018 at 7:51 PM Anup Patel > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > This patchset enables Cadance MACB ethernet driver for > > > > > > > > > > > > QEMU sifive_u machine. The Cadance MACB ethernet driver > > > > > > > > > > > > works fine for QEMU sifive_u machince in both M-mode and > > > > > > > > > > > > S-mode with some minor fixes. > > > > > > > > > > > > > > > > > > > > > > > > The patches are based upon latest RISC-V U-Boot tree > > > > > > > > > > > > (git://git.denx.de/u-boot-riscv.git) at commit id > > > > > > > > > > > > 9deb8d2fcd13d4a40a4e63c396fe4376af46efac > > > > > > > > > > > > > > > > > > > > > > > > To try on QEMU, please ensure following patches are > > > > > > > > > > > > applied to QEMU sources: > > > > > > > > > > > > https://patchwork.kernel.org/patch/10729579/ > > > > > > > > > > > > https://patchwork.kernel.org/patch/10729581/ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > What "-device " parameter should I tell QEMU to > > > > > > > > > > > instantiate the MACB? > > > > > > > > > > > "-device ?" does not give me anything that looks like > > > > > > > > > > > MACB. Without a > > > > > > > > > > > proper "-device " parameter, I can boot U-Boot on QEMU > > > > > > > > > > > sifive_u and > > > > > > > > > > > see U-Boot driver is probed, but a simple 'ping' test > > > > > > > > > > > does not work. > > > > > > > > > > > > > > > > > > > > Try the following: > > > > > > > > > > # setenv ipaddr 10.0.2.1 > > > > > > > > > > # ping 10.0.2.2 > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, I have set up all the required network parameters. > > > > > > > > > > > > > > > > > > > The above works for me on QEMU. > > > > > > > > > > > > > > > > > > My understanding is that we need enable QEMU network via > > > > > > > > > "-netdev " > > > > > > > > > (either usr, or tap), with a corresponding "-device". I don't > > > > > > > > > know how > > > > > > > > > to set it up. What's your command line to test this? > > > > > > > > > > > > > > > > > > > > > > > > > "-netdev" or "-device" parameters are not mandatory. By > > > > > > > > default, virtual > > > > > > > > NICs are in NAT mode. The QEMU NAT gateway is at IP address > > > > > > > > 10.0.2.2. We can always ping the NAT gateway when virtual NIC > > > > > > > > is in > > > > > > > > NAT mode. > > > > > > > > > > > > > > > > Here's how I compile for M-mode: > > > > > > > > # ARCH=riscv > > > > > > > > # CROSS_COMPILE=riscv64-unknown-linux-gnu- > > > > > > > > # make qemu-riscv64_defconfig > > > > > > > > # make > > > > > > > > > > > > > > > > My U-boot log is as follows: > > > > > > > > > > > > > > > > anup@anup-ubuntu64:~/Work/riscv-test/u-boot$ > > > > > > > > qemu-system-riscv64 -M > > > > > > > > sifive_u -m 256M -display none -serial stdio -kernel ./u-boot > > > > > > > > > > > > > > > > > > > > > > > > U-Boot 2019.01-rc1-00948-ge6b3cdafd0 (Dec 19 2018 - 10:05:50 > > > > > > > > +0530) > > > > > > > > > > > > > > > > CPU: rv64imafdcsu > > > > > > > > Model: ucbbar,spike-bare,qemu > > > > > > > > DRAM: 256 MiB > > > > > > > > In:uart@10013000 > > > > > > > > Out: uart@10013000 > > > > > > > > Err: uart@10013000 > > > > > > > > Net: > > > > > > > > Warning: ethernet@100900fc (eth0) using random MAC address - > > > > > > > > f6:1f:8c:13:83:c0 > > > > > > > > eth0: ethernet@100900fc > > > > > > > > Hit any key to stop autoboot: 0 > > > > > > > > > > > > > > > > Device 0: unknown device > > > > > > > > ethernet@100900fc: PHY present at 0 > > > > > > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > > > > > > BOOTP broadcast 1 > > > > > > > > DHCP client bound to address 10.0.2.15 (2 ms) > > > > > > > > Using ethernet@100900fc device > > > > > > > > TFTP from server 10.0.2.2; our IP address is 10.0.2.15 > > > >
Re: [U-Boot] [PATCH 0/3] Ethernet support for QEMU sifive_u machine
On Mon, Dec 24, 2018 at 12:01 PM Bin Meng wrote: > > Hi Anup, > > On Mon, Dec 24, 2018 at 1:41 PM Anup Patel wrote: > > > > On Mon, Dec 24, 2018 at 6:59 AM Bin Meng wrote: > > > > > > Hi Anup, > > > > > > On Wed, Dec 19, 2018 at 5:05 PM Bin Meng wrote: > > > > > > > > Hi Anup, > > > > > > > > On Wed, Dec 19, 2018 at 2:32 PM Anup Patel wrote: > > > > > > > > > > On Wed, Dec 19, 2018 at 11:02 AM Bin Meng wrote: > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > On Wed, Dec 19, 2018 at 12:41 PM Anup Patel > > > > > > wrote: > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 4:06 PM Bin Meng > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 6:33 PM Anup Patel > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 3:21 PM Bin Meng > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > > > > > > > On Mon, Dec 17, 2018 at 7:51 PM Anup Patel > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > This patchset enables Cadance MACB ethernet driver for > > > > > > > > > > > QEMU sifive_u machine. The Cadance MACB ethernet driver > > > > > > > > > > > works fine for QEMU sifive_u machince in both M-mode and > > > > > > > > > > > S-mode with some minor fixes. > > > > > > > > > > > > > > > > > > > > > > The patches are based upon latest RISC-V U-Boot tree > > > > > > > > > > > (git://git.denx.de/u-boot-riscv.git) at commit id > > > > > > > > > > > 9deb8d2fcd13d4a40a4e63c396fe4376af46efac > > > > > > > > > > > > > > > > > > > > > > To try on QEMU, please ensure following patches are > > > > > > > > > > > applied to QEMU sources: > > > > > > > > > > > https://patchwork.kernel.org/patch/10729579/ > > > > > > > > > > > https://patchwork.kernel.org/patch/10729581/ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > What "-device " parameter should I tell QEMU to instantiate > > > > > > > > > > the MACB? > > > > > > > > > > "-device ?" does not give me anything that looks like MACB. > > > > > > > > > > Without a > > > > > > > > > > proper "-device " parameter, I can boot U-Boot on QEMU > > > > > > > > > > sifive_u and > > > > > > > > > > see U-Boot driver is probed, but a simple 'ping' test does > > > > > > > > > > not work. > > > > > > > > > > > > > > > > > > Try the following: > > > > > > > > > # setenv ipaddr 10.0.2.1 > > > > > > > > > # ping 10.0.2.2 > > > > > > > > > > > > > > > > > > > > > > > > > Yes, I have set up all the required network parameters. > > > > > > > > > > > > > > > > > The above works for me on QEMU. > > > > > > > > > > > > > > > > My understanding is that we need enable QEMU network via > > > > > > > > "-netdev " > > > > > > > > (either usr, or tap), with a corresponding "-device". I don't > > > > > > > > know how > > > > > > > > to set it up. What's your command line to test this? > > > > > > > > > > > > > > > > > > > > > > "-netdev" or "-device" parameters are not mandatory. By default, > > > > > > > virtual > > > > > > > NICs are in NAT mode. The QEMU NAT gateway is at IP address > > > > > > > 10.0.2.2. We can always ping the NAT gateway when virtual NIC is > > > > > > > in > > > > > > > NAT mode. > > > > > > > > > > > > > > Here's how I compile for M-mode: > > > > > > > # ARCH=riscv > > > > > > > # CROSS_COMPILE=riscv64-unknown-linux-gnu- > > > > > > > # make qemu-riscv64_defconfig > > > > > > > # make > > > > > > > > > > > > > > My U-boot log is as follows: > > > > > > > > > > > > > > anup@anup-ubuntu64:~/Work/riscv-test/u-boot$ qemu-system-riscv64 > > > > > > > -M > > > > > > > sifive_u -m 256M -display none -serial stdio -kernel ./u-boot > > > > > > > > > > > > > > > > > > > > > U-Boot 2019.01-rc1-00948-ge6b3cdafd0 (Dec 19 2018 - 10:05:50 > > > > > > > +0530) > > > > > > > > > > > > > > CPU: rv64imafdcsu > > > > > > > Model: ucbbar,spike-bare,qemu > > > > > > > DRAM: 256 MiB > > > > > > > In:uart@10013000 > > > > > > > Out: uart@10013000 > > > > > > > Err: uart@10013000 > > > > > > > Net: > > > > > > > Warning: ethernet@100900fc (eth0) using random MAC address - > > > > > > > f6:1f:8c:13:83:c0 > > > > > > > eth0: ethernet@100900fc > > > > > > > Hit any key to stop autoboot: 0 > > > > > > > > > > > > > > Device 0: unknown device > > > > > > > ethernet@100900fc: PHY present at 0 > > > > > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > > > > > BOOTP broadcast 1 > > > > > > > DHCP client bound to address 10.0.2.15 (2 ms) > > > > > > > Using ethernet@100900fc device > > > > > > > TFTP from server 10.0.2.2; our IP address is 10.0.2.15 > > > > > > > Filename 'boot.scr.uimg'. > > > > > > > Load address: 0x8210 > > > > > > > Loading: * > > > > > > > TFTP error: 'Access violation' (2) > > > > > > > Not retrying... > > > > > > > ethernet@100900fc: PHY present at 0 > > > > > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > > > > > BOOTP
Re: [U-Boot] [PATCH 0/3] Ethernet support for QEMU sifive_u machine
Hi Anup, On Mon, Dec 24, 2018 at 1:41 PM Anup Patel wrote: > > On Mon, Dec 24, 2018 at 6:59 AM Bin Meng wrote: > > > > Hi Anup, > > > > On Wed, Dec 19, 2018 at 5:05 PM Bin Meng wrote: > > > > > > Hi Anup, > > > > > > On Wed, Dec 19, 2018 at 2:32 PM Anup Patel wrote: > > > > > > > > On Wed, Dec 19, 2018 at 11:02 AM Bin Meng wrote: > > > > > > > > > > Hi Anup, > > > > > > > > > > On Wed, Dec 19, 2018 at 12:41 PM Anup Patel > > > > > wrote: > > > > > > > > > > > > On Tue, Dec 18, 2018 at 4:06 PM Bin Meng wrote: > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 6:33 PM Anup Patel > > > > > > > wrote: > > > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 3:21 PM Bin Meng > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > > > > > On Mon, Dec 17, 2018 at 7:51 PM Anup Patel > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > This patchset enables Cadance MACB ethernet driver for > > > > > > > > > > QEMU sifive_u machine. The Cadance MACB ethernet driver > > > > > > > > > > works fine for QEMU sifive_u machince in both M-mode and > > > > > > > > > > S-mode with some minor fixes. > > > > > > > > > > > > > > > > > > > > The patches are based upon latest RISC-V U-Boot tree > > > > > > > > > > (git://git.denx.de/u-boot-riscv.git) at commit id > > > > > > > > > > 9deb8d2fcd13d4a40a4e63c396fe4376af46efac > > > > > > > > > > > > > > > > > > > > To try on QEMU, please ensure following patches are > > > > > > > > > > applied to QEMU sources: > > > > > > > > > > https://patchwork.kernel.org/patch/10729579/ > > > > > > > > > > https://patchwork.kernel.org/patch/10729581/ > > > > > > > > > > > > > > > > > > > > > > > > > > > > What "-device " parameter should I tell QEMU to instantiate > > > > > > > > > the MACB? > > > > > > > > > "-device ?" does not give me anything that looks like MACB. > > > > > > > > > Without a > > > > > > > > > proper "-device " parameter, I can boot U-Boot on QEMU > > > > > > > > > sifive_u and > > > > > > > > > see U-Boot driver is probed, but a simple 'ping' test does > > > > > > > > > not work. > > > > > > > > > > > > > > > > Try the following: > > > > > > > > # setenv ipaddr 10.0.2.1 > > > > > > > > # ping 10.0.2.2 > > > > > > > > > > > > > > > > > > > > > > Yes, I have set up all the required network parameters. > > > > > > > > > > > > > > > The above works for me on QEMU. > > > > > > > > > > > > > > My understanding is that we need enable QEMU network via "-netdev > > > > > > > " > > > > > > > (either usr, or tap), with a corresponding "-device". I don't > > > > > > > know how > > > > > > > to set it up. What's your command line to test this? > > > > > > > > > > > > > > > > > > > "-netdev" or "-device" parameters are not mandatory. By default, > > > > > > virtual > > > > > > NICs are in NAT mode. The QEMU NAT gateway is at IP address > > > > > > 10.0.2.2. We can always ping the NAT gateway when virtual NIC is in > > > > > > NAT mode. > > > > > > > > > > > > Here's how I compile for M-mode: > > > > > > # ARCH=riscv > > > > > > # CROSS_COMPILE=riscv64-unknown-linux-gnu- > > > > > > # make qemu-riscv64_defconfig > > > > > > # make > > > > > > > > > > > > My U-boot log is as follows: > > > > > > > > > > > > anup@anup-ubuntu64:~/Work/riscv-test/u-boot$ qemu-system-riscv64 -M > > > > > > sifive_u -m 256M -display none -serial stdio -kernel ./u-boot > > > > > > > > > > > > > > > > > > U-Boot 2019.01-rc1-00948-ge6b3cdafd0 (Dec 19 2018 - 10:05:50 +0530) > > > > > > > > > > > > CPU: rv64imafdcsu > > > > > > Model: ucbbar,spike-bare,qemu > > > > > > DRAM: 256 MiB > > > > > > In:uart@10013000 > > > > > > Out: uart@10013000 > > > > > > Err: uart@10013000 > > > > > > Net: > > > > > > Warning: ethernet@100900fc (eth0) using random MAC address - > > > > > > f6:1f:8c:13:83:c0 > > > > > > eth0: ethernet@100900fc > > > > > > Hit any key to stop autoboot: 0 > > > > > > > > > > > > Device 0: unknown device > > > > > > ethernet@100900fc: PHY present at 0 > > > > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > > > > BOOTP broadcast 1 > > > > > > DHCP client bound to address 10.0.2.15 (2 ms) > > > > > > Using ethernet@100900fc device > > > > > > TFTP from server 10.0.2.2; our IP address is 10.0.2.15 > > > > > > Filename 'boot.scr.uimg'. > > > > > > Load address: 0x8210 > > > > > > Loading: * > > > > > > TFTP error: 'Access violation' (2) > > > > > > Not retrying... > > > > > > ethernet@100900fc: PHY present at 0 > > > > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > > > > BOOTP broadcast 1 > > > > > > DHCP client bound to address 10.0.2.15 (1 ms) > > > > > > Using ethernet@100900fc device > > > > > > TFTP from server 10.0.2.2; our IP address is 10.0.2.15 > > > > > > Filename 'boot.scr.uimg'. > > > > > > Load address: 0x8100 > > > > > > Loading: * > > > > > > TFTP error: 'Access violation' (2) > > > > > > Not retrying... > > > > > >
Re: [U-Boot] [PATCH 0/3] Ethernet support for QEMU sifive_u machine
On Mon, Dec 24, 2018 at 6:59 AM Bin Meng wrote: > > Hi Anup, > > On Wed, Dec 19, 2018 at 5:05 PM Bin Meng wrote: > > > > Hi Anup, > > > > On Wed, Dec 19, 2018 at 2:32 PM Anup Patel wrote: > > > > > > On Wed, Dec 19, 2018 at 11:02 AM Bin Meng wrote: > > > > > > > > Hi Anup, > > > > > > > > On Wed, Dec 19, 2018 at 12:41 PM Anup Patel wrote: > > > > > > > > > > On Tue, Dec 18, 2018 at 4:06 PM Bin Meng wrote: > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > On Tue, Dec 18, 2018 at 6:33 PM Anup Patel > > > > > > wrote: > > > > > > > > > > > > > > On Tue, Dec 18, 2018 at 3:21 PM Bin Meng > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > > > On Mon, Dec 17, 2018 at 7:51 PM Anup Patel > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > This patchset enables Cadance MACB ethernet driver for > > > > > > > > > QEMU sifive_u machine. The Cadance MACB ethernet driver > > > > > > > > > works fine for QEMU sifive_u machince in both M-mode and > > > > > > > > > S-mode with some minor fixes. > > > > > > > > > > > > > > > > > > The patches are based upon latest RISC-V U-Boot tree > > > > > > > > > (git://git.denx.de/u-boot-riscv.git) at commit id > > > > > > > > > 9deb8d2fcd13d4a40a4e63c396fe4376af46efac > > > > > > > > > > > > > > > > > > To try on QEMU, please ensure following patches are > > > > > > > > > applied to QEMU sources: > > > > > > > > > https://patchwork.kernel.org/patch/10729579/ > > > > > > > > > https://patchwork.kernel.org/patch/10729581/ > > > > > > > > > > > > > > > > > > > > > > > > > What "-device " parameter should I tell QEMU to instantiate the > > > > > > > > MACB? > > > > > > > > "-device ?" does not give me anything that looks like MACB. > > > > > > > > Without a > > > > > > > > proper "-device " parameter, I can boot U-Boot on QEMU sifive_u > > > > > > > > and > > > > > > > > see U-Boot driver is probed, but a simple 'ping' test does not > > > > > > > > work. > > > > > > > > > > > > > > Try the following: > > > > > > > # setenv ipaddr 10.0.2.1 > > > > > > > # ping 10.0.2.2 > > > > > > > > > > > > > > > > > > > Yes, I have set up all the required network parameters. > > > > > > > > > > > > > The above works for me on QEMU. > > > > > > > > > > > > My understanding is that we need enable QEMU network via "-netdev " > > > > > > (either usr, or tap), with a corresponding "-device". I don't know > > > > > > how > > > > > > to set it up. What's your command line to test this? > > > > > > > > > > > > > > > > "-netdev" or "-device" parameters are not mandatory. By default, > > > > > virtual > > > > > NICs are in NAT mode. The QEMU NAT gateway is at IP address > > > > > 10.0.2.2. We can always ping the NAT gateway when virtual NIC is in > > > > > NAT mode. > > > > > > > > > > Here's how I compile for M-mode: > > > > > # ARCH=riscv > > > > > # CROSS_COMPILE=riscv64-unknown-linux-gnu- > > > > > # make qemu-riscv64_defconfig > > > > > # make > > > > > > > > > > My U-boot log is as follows: > > > > > > > > > > anup@anup-ubuntu64:~/Work/riscv-test/u-boot$ qemu-system-riscv64 -M > > > > > sifive_u -m 256M -display none -serial stdio -kernel ./u-boot > > > > > > > > > > > > > > > U-Boot 2019.01-rc1-00948-ge6b3cdafd0 (Dec 19 2018 - 10:05:50 +0530) > > > > > > > > > > CPU: rv64imafdcsu > > > > > Model: ucbbar,spike-bare,qemu > > > > > DRAM: 256 MiB > > > > > In:uart@10013000 > > > > > Out: uart@10013000 > > > > > Err: uart@10013000 > > > > > Net: > > > > > Warning: ethernet@100900fc (eth0) using random MAC address - > > > > > f6:1f:8c:13:83:c0 > > > > > eth0: ethernet@100900fc > > > > > Hit any key to stop autoboot: 0 > > > > > > > > > > Device 0: unknown device > > > > > ethernet@100900fc: PHY present at 0 > > > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > > > BOOTP broadcast 1 > > > > > DHCP client bound to address 10.0.2.15 (2 ms) > > > > > Using ethernet@100900fc device > > > > > TFTP from server 10.0.2.2; our IP address is 10.0.2.15 > > > > > Filename 'boot.scr.uimg'. > > > > > Load address: 0x8210 > > > > > Loading: * > > > > > TFTP error: 'Access violation' (2) > > > > > Not retrying... > > > > > ethernet@100900fc: PHY present at 0 > > > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > > > BOOTP broadcast 1 > > > > > DHCP client bound to address 10.0.2.15 (1 ms) > > > > > Using ethernet@100900fc device > > > > > TFTP from server 10.0.2.2; our IP address is 10.0.2.15 > > > > > Filename 'boot.scr.uimg'. > > > > > Load address: 0x8100 > > > > > Loading: * > > > > > TFTP error: 'Access violation' (2) > > > > > Not retrying... > > > > > => ping 10.0.2.2 > > > > > ethernet@100900fc: PHY present at 0 > > > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > > > Using ethernet@100900fc device > > > > > host 10.0.2.2 is alive > > > > > => > > > > > ethernet@100900fc: PHY present at 0 > > > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1)
[U-Boot] [PATCH 10/10] imx: support i.MX8QM MEK board
Add i.MX8QM MEK board support.
Included a basic dts, enabled SPL FIT
Boot log as below:
U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)
Normal Boot
Trying to boot from MMC2_2
U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)
CPU: NXP i.MX8QM RevB A53 at 142933 MHz
Model: Freescale i.MX8QM MEK
Board: iMX8QM MEK
Build: SCFW 9330215b
Boot: SD1
DRAM: 6 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment
In:serial@5a06
Out: serial@5a06
Err: serial@5a06
Net:
Error: ethernet@5b04 address not set.
eth-1: ethernet@5b04
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan
---
arch/arm/dts/Makefile | 4 +-
arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 112 +++
arch/arm/dts/fsl-imx8qm-mek.dts | 184
arch/arm/mach-imx/imx8/Kconfig | 6 ++
board/freescale/imx8qm_mek/Kconfig | 14 +++
board/freescale/imx8qm_mek/MAINTAINERS | 6 ++
board/freescale/imx8qm_mek/Makefile | 8 ++
board/freescale/imx8qm_mek/README | 57 ++
board/freescale/imx8qm_mek/imx8qm_mek.c | 157 +++
board/freescale/imx8qm_mek/imximage.cfg | 19
board/freescale/imx8qm_mek/spl.c| 75 +
configs/imx8qm_mek_defconfig| 75 +
include/configs/imx8qm_mek.h| 176 ++
13 files changed, 892 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
create mode 100644 arch/arm/dts/fsl-imx8qm-mek.dts
create mode 100644 board/freescale/imx8qm_mek/Kconfig
create mode 100644 board/freescale/imx8qm_mek/MAINTAINERS
create mode 100644 board/freescale/imx8qm_mek/Makefile
create mode 100644 board/freescale/imx8qm_mek/README
create mode 100644 board/freescale/imx8qm_mek/imx8qm_mek.c
create mode 100644 board/freescale/imx8qm_mek/imximage.cfg
create mode 100644 board/freescale/imx8qm_mek/spl.c
create mode 100644 configs/imx8qm_mek_defconfig
create mode 100644 include/configs/imx8qm_mek.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ad494ec3ef..80009b2c49 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -463,7 +463,9 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
-dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
+dtb-$(CONFIG_ARCH_IMX8) += \
+ fsl-imx8qxp-mek.dtb \
+ fsl-imx8qm-mek.dtb \
dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
new file mode 100644
index 00..5d50eb028e
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_lsio {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio0 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio1 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio2 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio3 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio4 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio5 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio6 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio7 {
+ u-boot,dm-spl;
+};
+
+_conn {
+ u-boot,dm-spl;
+};
+
+_conn_sdch0 {
+ u-boot,dm-spl;
+};
+
+_conn_sdch1 {
+ u-boot,dm-spl;
+};
+
+_conn_sdch2 {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qm-mek.dts b/arch/arm/dts/fsl-imx8qm-mek.dts
new file mode 100644
index 00..63908ba6bf
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-mek.dts
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qm.dtsi"
+#include "fsl-imx8qm-mek-u-boot.dtsi"
+
+/ {
+ model = "Freescale i.MX8QM MEK";
+ compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+ chosen {
+ bootargs = "console=ttyLP0,115200
earlycon=lpuart32,0x5a06,115200";
+ stdout-path =
+ };
+
+ reg_usdhc2_vmmc: usdhc2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "sw-3p3-sd1";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 7 GPIO_ACTIVE_HIGH>;
+ off-on-delay = <4800>;
+ enable-active-high;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_hog>;
+
+
[U-Boot] [PATCH] mmc: support hs400 enhanced strobe mode
eMMC 5.1+ supports HS400 Enhances Strobe mode without the need for
tuning procedure.
The flow is as following:
- set HS_TIMIMG (Highspeed)
- Host change freq to <= 52Mhz
- set the bus width to Enhanced strobe and DDR8Bit(CMD6),
EXT_CSD[183] = 0x86 instead of 0x80
- set HS_TIMING to 0x3 (HS400)
- Host change freq to <= 200Mhz
- Host select HS400 enhanced strobe complete
Signed-off-by: Peng Fan
---
drivers/mmc/Kconfig | 12
drivers/mmc/mmc-uclass.c | 15 +
drivers/mmc/mmc.c| 79 +++-
include/mmc.h| 15 +
4 files changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index fbd13964a0..41fcd9335c 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -111,6 +111,18 @@ config SPL_MMC_UHS_SUPPORT
cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus
frequency can go up to 208MHz (SDR104)
+config MMC_HS400_ES_SUPPORT
+ bool "enable HS400 Enhanced Strobe support"
+ help
+ The HS400 Enhanced Strobe mode is support by some eMMC. The bus
frequency is up to
+ 200MHz. This mode does not tune the IO.
+
+config SPL_MMC_HS400_ES_SUPPORT
+ bool "enable HS400 Enhanced Strobe support in SPL"
+ help
+ The HS400 Enhanced Strobe mode is support by some eMMC. The bus
frequency is up to
+ 200MHz. This mode does not tune the IO.
+
config MMC_HS400_SUPPORT
bool "enable HS400 support"
select MMC_HS200_SUPPORT
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 76225b7939..d81725437f 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -120,6 +120,21 @@ int mmc_execute_tuning(struct mmc *mmc, uint opcode)
}
#endif
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+void dm_mmc_set_enhanced_strobe(struct udevice *dev)
+{
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+ if (ops->set_enhanced_strobe)
+ ops->set_enhanced_strobe(dev);
+}
+
+void mmc_set_enhanced_strobe(struct mmc *mmc)
+{
+ dm_mmc_set_enhanced_strobe(mmc->dev);
+}
+#endif
+
int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg)
{
int val;
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f5c821e308..6d8ac69662 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -148,6 +148,7 @@ const char *mmc_mode_name(enum bus_mode mode)
[MMC_DDR_52] = "MMC DDR52 (52MHz)",
[MMC_HS_200] = "HS200 (200MHz)",
[MMC_HS_400] = "HS400 (200MHz)",
+ [MMC_HS_400_ES] = "HS400ES (200MHz)",
};
if (mode >= MMC_MODES_END)
@@ -173,6 +174,7 @@ static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode
mode)
[UHS_SDR104] = 20800,
[MMC_HS_200] = 2,
[MMC_HS_400] = 2,
+ [MMC_HS_400_ES] = 2,
};
if (mode == MMC_LEGACY)
@@ -776,6 +778,11 @@ static int mmc_set_card_speed(struct mmc *mmc, enum
bus_mode mode)
case MMC_HS_400:
speed_bits = EXT_CSD_TIMING_HS400;
break;
+#endif
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+ case MMC_HS_400_ES:
+ speed_bits = EXT_CSD_TIMING_HS400;
+ break;
#endif
case MMC_LEGACY:
speed_bits = EXT_CSD_TIMING_LEGACY;
@@ -832,7 +839,8 @@ static int mmc_get_capabilities(struct mmc *mmc)
mmc->card_caps |= MMC_MODE_HS200;
}
#endif
-#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+#if (IS_ENABLED(CONFIG_MMC_HS400_SUPPORT) || \
+ IS_ENABLED(CONFIG_MMC_HS400_ES_SUPPORT))
if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
EXT_CSD_CARD_TYPE_HS400_1_8V)) {
mmc->card_caps |= MMC_MODE_HS400;
@@ -846,6 +854,13 @@ static int mmc_get_capabilities(struct mmc *mmc)
if (cardtype & EXT_CSD_CARD_TYPE_26)
mmc->card_caps |= MMC_MODE_HS;
+#if IS_ENABLED(CONFIG_MMC_HS400_ES_SUPPORT)
+ if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
+ (mmc->card_caps & MMC_MODE_HS400)) {
+ mmc->card_caps |= MMC_MODE_HS400_ES;
+ }
+#endif
+
return 0;
}
#endif
@@ -1751,6 +1766,7 @@ static int mmc_set_lowest_voltage(struct mmc *mmc, enum
bus_mode mode,
u32 card_mask = 0;
switch (mode) {
+ case MMC_HS_400_ES:
case MMC_HS_400:
case MMC_HS_200:
if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
@@ -1793,6 +1809,12 @@ static inline int mmc_set_lowest_voltage(struct mmc
*mmc, enum bus_mode mode,
#endif
static const struct mode_width_tuning mmc_modes_by_pref[] = {
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+ {
+ .mode = MMC_HS_400_ES,
+ .widths = MMC_MODE_8BIT,
+ },
+#endif
#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
{
.mode
[U-Boot] [PATCH 08/10] imx8: imx8-pins: add i.MX8QM
Add i.MX8QM entry Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8/imx8-pins.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8/imx8-pins.h b/arch/arm/include/asm/arch-imx8/imx8-pins.h index dcced1010b..2130298163 100644 --- a/arch/arm/include/asm/arch-imx8/imx8-pins.h +++ b/arch/arm/include/asm/arch-imx8/imx8-pins.h @@ -8,6 +8,8 @@ #if defined(CONFIG_IMX8QXP) #include +#elif defined(CONFIG_IMX8QM) +#include #else #error "No pin header" #endif -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 09/10] misc: imx8: scu: add i.MX8QM support
According to IMX8QXP/8QM config option, choose the clk/iomuxc
compatible.
Signed-off-by: Peng Fan
---
drivers/misc/imx8/scu.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c
index 1b9c49c99c..9ec00457b8 100644
--- a/drivers/misc/imx8/scu.c
+++ b/drivers/misc/imx8/scu.c
@@ -219,11 +219,21 @@ static int imx8_scu_bind(struct udevice *dev)
int ret;
struct udevice *child;
int node;
+ char *clk_compatible, *iomuxc_compatible;
+
+ if (IS_ENABLED(CONFIG_IMX8QXP)) {
+ clk_compatible = "fsl,imx8qxp-clk";
+ iomuxc_compatible = "fsl,imx8qxp-iomuxc";
+ } else if (IS_ENABLED(CONFIG_IMX8QM)) {
+ clk_compatible = "fsl,imx8qm-clk";
+ iomuxc_compatible = "fsl,imx8qm-iomuxc";
+ } else {
+ return -EINVAL;
+ }
debug("%s(dev=%p)\n", __func__, dev);
- node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
-"fsl,imx8qxp-clk");
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, clk_compatible);
if (node < 0)
panic("No clk node found\n");
@@ -234,7 +244,7 @@ static int imx8_scu_bind(struct udevice *dev)
plat->clk = child;
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
-"fsl,imx8qxp-iomuxc");
+iomuxc_compatible);
if (node < 0)
panic("No iomuxc node found\n");
--
2.14.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 06/10] clk: imx8: split code into common and soc specific part
To make it easy to add new clk driver for i.MX8, split
the code into common part and SoC specific part.
Make the get/set/enable non static and introduce a num_clks for
soc_clk_dump, because the arrays are moved to clk-imx8qxp.c.
Signed-off-by: Peng Fan
---
drivers/clk/imx/Makefile | 4 +
drivers/clk/imx/clk-imx8.c| 297 ++--
drivers/clk/imx/clk-imx8.h| 19 +++
drivers/clk/imx/clk-imx8qxp.c | 311 ++
4 files changed, 342 insertions(+), 289 deletions(-)
create mode 100644 drivers/clk/imx/clk-imx8.h
create mode 100644 drivers/clk/imx/clk-imx8qxp.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 5505ae52e2..d07d91b88f 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -3,3 +3,7 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
+
+ifdef CONFIG_CLK_IMX8
+obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
+endif
diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
index d03fcc2fdd..c69a9ed867 100644
--- a/drivers/clk/imx/clk-imx8.c
+++ b/drivers/clk/imx/clk-imx8.c
@@ -13,302 +13,21 @@
#include
#include
-struct imx8_clks {
- ulong id;
- const char *name;
-};
-
-#if CONFIG_IS_ENABLED(CMD_CLK)
-static struct imx8_clks imx8_clk_names[] = {
- { IMX8QXP_A35_DIV, "A35_DIV" },
- { IMX8QXP_I2C0_CLK, "I2C0" },
- { IMX8QXP_I2C1_CLK, "I2C1" },
- { IMX8QXP_I2C2_CLK, "I2C2" },
- { IMX8QXP_I2C3_CLK, "I2C3" },
- { IMX8QXP_UART0_CLK, "UART0" },
- { IMX8QXP_UART1_CLK, "UART1" },
- { IMX8QXP_UART2_CLK, "UART2" },
- { IMX8QXP_UART3_CLK, "UART3" },
- { IMX8QXP_SDHC0_CLK, "SDHC0" },
- { IMX8QXP_SDHC1_CLK, "SDHC1" },
- { IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" },
- { IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" },
- { IMX8QXP_ENET0_REF_DIV, "ENET0_REF" },
- { IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" },
- { IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" },
- { IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" },
- { IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
- { IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
-};
-#endif
+#include "clk-imx8.h"
-static ulong imx8_clk_get_rate(struct clk *clk)
+__weak ulong imx8_clk_get_rate(struct clk *clk)
{
- sc_pm_clk_t pm_clk;
- ulong rate;
- u16 resource;
- int ret;
-
- debug("%s(#%lu)\n", __func__, clk->id);
-
- switch (clk->id) {
- case IMX8QXP_A35_DIV:
- resource = SC_R_A35;
- pm_clk = SC_PM_CLK_CPU;
- break;
- case IMX8QXP_I2C0_CLK:
- resource = SC_R_I2C_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_I2C1_CLK:
- resource = SC_R_I2C_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_I2C2_CLK:
- resource = SC_R_I2C_2;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_I2C3_CLK:
- resource = SC_R_I2C_3;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_SDHC0_IPG_CLK:
- case IMX8QXP_SDHC0_CLK:
- case IMX8QXP_SDHC0_DIV:
- resource = SC_R_SDHC_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_SDHC1_IPG_CLK:
- case IMX8QXP_SDHC1_CLK:
- case IMX8QXP_SDHC1_DIV:
- resource = SC_R_SDHC_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART0_IPG_CLK:
- case IMX8QXP_UART0_CLK:
- resource = SC_R_UART_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART1_CLK:
- resource = SC_R_UART_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART2_CLK:
- resource = SC_R_UART_2;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART3_CLK:
- resource = SC_R_UART_3;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_ENET0_IPG_CLK:
- case IMX8QXP_ENET0_AHB_CLK:
- case IMX8QXP_ENET0_REF_DIV:
- case IMX8QXP_ENET0_PTP_CLK:
- resource = SC_R_ENET_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_ENET1_IPG_CLK:
- case IMX8QXP_ENET1_AHB_CLK:
- case IMX8QXP_ENET1_REF_DIV:
- case IMX8QXP_ENET1_PTP_CLK:
- resource = SC_R_ENET_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- default:
- if (clk->id < IMX8QXP_UART0_IPG_CLK ||
- clk->id >= IMX8QXP_CLK_END) {
- printf("%s(Invalid clk ID #%lu)\n",
- __func__, clk->id);
- return -EINVAL;
- }
- return -ENOTSUPP;
- };
-
- ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
-
[U-Boot] [PATCH 07/10] clk: imx8: add i.MX8QM clk driver
Add i.MX8QM clk driver, SDHC/FEC/UART/I2C supported.
Signed-off-by: Peng Fan
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx8.c | 1 +
drivers/clk/imx/clk-imx8qm.c | 307 +++
3 files changed, 309 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8qm.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index d07d91b88f..eb379c188a 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
ifdef CONFIG_CLK_IMX8
obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
+obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
endif
diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
index c69a9ed867..a755e26501 100644
--- a/drivers/clk/imx/clk-imx8.c
+++ b/drivers/clk/imx/clk-imx8.c
@@ -101,6 +101,7 @@ static int imx8_clk_probe(struct udevice *dev)
static const struct udevice_id imx8_clk_ids[] = {
{ .compatible = "fsl,imx8qxp-clk" },
+ { .compatible = "fsl,imx8qm-clk" },
{ },
};
diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c
new file mode 100644
index 00..6b5561e178
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8qm.c
@@ -0,0 +1,307 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-imx8.h"
+
+#if CONFIG_IS_ENABLED(CMD_CLK)
+struct imx8_clks imx8_clk_names[] = {
+ { IMX8QM_A53_DIV, "A53_DIV" },
+ { IMX8QM_UART0_CLK, "UART0" },
+ { IMX8QM_UART1_CLK, "UART1" },
+ { IMX8QM_UART2_CLK, "UART2" },
+ { IMX8QM_UART3_CLK, "UART3" },
+ { IMX8QM_SDHC0_CLK, "SDHC0" },
+ { IMX8QM_SDHC1_CLK, "SDHC1" },
+ { IMX8QM_SDHC2_CLK, "SDHC2" },
+ { IMX8QM_ENET0_AHB_CLK, "ENET0_AHB" },
+ { IMX8QM_ENET0_IPG_CLK, "ENET0_IPG" },
+ { IMX8QM_ENET0_REF_DIV, "ENET0_REF" },
+ { IMX8QM_ENET0_PTP_CLK, "ENET0_PTP" },
+ { IMX8QM_ENET1_AHB_CLK, "ENET1_AHB" },
+ { IMX8QM_ENET1_IPG_CLK, "ENET1_IPG" },
+ { IMX8QM_ENET1_REF_DIV, "ENET1_REF" },
+ { IMX8QM_ENET1_PTP_CLK, "ENET1_PTP" },
+};
+
+int num_clks = ARRAY_SIZE(imx8_clk_names);
+#endif
+
+ulong imx8_clk_get_rate(struct clk *clk)
+{
+ sc_pm_clk_t pm_clk;
+ ulong rate;
+ u16 resource;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ switch (clk->id) {
+ case IMX8QM_A53_DIV:
+ resource = SC_R_A53;
+ pm_clk = SC_PM_CLK_CPU;
+ break;
+ case IMX8QM_I2C0_CLK:
+ resource = SC_R_I2C_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_I2C1_CLK:
+ resource = SC_R_I2C_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_I2C2_CLK:
+ resource = SC_R_I2C_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_I2C3_CLK:
+ resource = SC_R_I2C_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_SDHC0_IPG_CLK:
+ case IMX8QM_SDHC0_CLK:
+ case IMX8QM_SDHC0_DIV:
+ resource = SC_R_SDHC_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_SDHC1_IPG_CLK:
+ case IMX8QM_SDHC1_CLK:
+ case IMX8QM_SDHC1_DIV:
+ resource = SC_R_SDHC_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART0_IPG_CLK:
+ case IMX8QM_UART0_CLK:
+ resource = SC_R_UART_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART1_CLK:
+ resource = SC_R_UART_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART2_CLK:
+ resource = SC_R_UART_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART3_CLK:
+ resource = SC_R_UART_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_ENET0_IPG_CLK:
+ case IMX8QM_ENET0_AHB_CLK:
+ case IMX8QM_ENET0_REF_DIV:
+ case IMX8QM_ENET0_PTP_CLK:
+ resource = SC_R_ENET_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_ENET1_IPG_CLK:
+ case IMX8QM_ENET1_AHB_CLK:
+ case IMX8QM_ENET1_REF_DIV:
+ case IMX8QM_ENET1_PTP_CLK:
+ resource = SC_R_ENET_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ default:
+ if (clk->id < IMX8QM_UART0_IPG_CLK ||
+ clk->id >= IMX8QM_CLK_END) {
+ printf("%s(Invalid clk ID #%lu)\n",
+ __func__, clk->id);
+ return -EINVAL;
+ }
+ return -ENOTSUPP;
+ };
+
+ ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
+
[U-Boot] [PATCH 05/10] imx8: add cpu support
Add cpu type and Kconfig entry
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx/cpu.h | 1 +
arch/arm/mach-imx/imx8/Kconfig | 5 +
arch/arm/mach-imx/imx8/cpu.c| 3 +++
3 files changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm/arch-imx/cpu.h
index 667badbc06..d4a83eef72 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -26,6 +26,7 @@
#define MXC_CPU_MX7D 0x72
#define MXC_CPU_IMX8MQ 0x82
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
+#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP0x92 /* dummy ID */
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index f76a139684..4336a8c236 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -10,6 +10,11 @@ config MU_BASE_SPL
SPL runs in EL3 mode, it use MU0_A to communicate with SCU.
So we could not reuse the one in dts which is for normal U-Boot.
+config IMX8QM
+ select IMX8
+ select SUPPORT_SPL
+ bool
+
config IMX8QXP
select IMX8
select SUPPORT_SPL
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 7599afe720..303cdc3c9a 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -537,6 +537,8 @@ const char *get_imx8_type(u32 imxtype)
case MXC_CPU_IMX8QXP:
case MXC_CPU_IMX8QXP_A0:
return "QXP";
+ case MXC_CPU_IMX8QM:
+ return "QM";
default:
return "??";
}
@@ -608,6 +610,7 @@ static const struct cpu_ops cpu_imx8_ops = {
static const struct udevice_id cpu_imx8_ids[] = {
{ .compatible = "arm,cortex-a35" },
+ { .compatible = "arm,cortex-a53" },
{ }
};
--
2.14.1
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[U-Boot] [PATCH 03/10] dt-bindings: clock: dt-bindings: pinctrl: add i.MX8QM clocks definition
Add i.MX8QM clocks definition Signed-off-by: Peng Fan --- include/dt-bindings/clock/imx8qm-clock.h | 846 +++ 1 file changed, 846 insertions(+) create mode 100644 include/dt-bindings/clock/imx8qm-clock.h diff --git a/include/dt-bindings/clock/imx8qm-clock.h b/include/dt-bindings/clock/imx8qm-clock.h new file mode 100644 index 00..58de976e63 --- /dev/null +++ b/include/dt-bindings/clock/imx8qm-clock.h @@ -0,0 +1,846 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QM_H +#define __DT_BINDINGS_CLOCK_IMX8QM_H + +#define IMX8QM_CLK_DUMMY 0 + +#define IMX8QM_A53_DIV 1 +#define IMX8QM_A53_CLK 2 +#define IMX8QM_A72_DIV 3 +#define IMX8QM_A72_CLK 4 + +/* SC Clocks. */ +#define IMX8QM_SC_I2C_DIV 5 +#define IMX8QM_SC_I2C_CLK 6 +#define IMX8QM_SC_PID0_DIV 7 +#define IMX8QM_SC_PID0_CLK 8 +#define IMX8QM_SC_PIT_DIV 9 +#define IMX8QM_SC_PIT_CLK 10 +#define IMX8QM_SC_TPM_DIV 11 +#define IMX8QM_SC_TPM_CLK 12 +#define IMX8QM_SC_UART_DIV 13 +#define IMX8QM_SC_UART_CLK 14 + +/* LSIO */ +#define IMX8QM_PWM0_DIV15 +#define IMX8QM_PWM0_CLK16 +#define IMX8QM_PWM1_DIV17 +#define IMX8QM_PWM1_CLK18 +#define IMX8QM_PWM2_DIV19 +#define IMX8QM_PWM2_CLK20 +#define IMX8QM_PWM3_DIV21 +#define IMX8QM_PWM3_CLK22 +#define IMX8QM_PWM4_DIV23 +#define IMX8QM_PWM4_CLK24 +#define IMX8QM_PWM5_DIV26 +#define IMX8QM_PWM5_CLK27 +#define IMX8QM_PWM6_DIV28 +#define IMX8QM_PWM6_CLK29 +#define IMX8QM_PWM7_DIV30 +#define IMX8QM_PWM7_CLK31 +#define IMX8QM_FSPI0_DIV 32 +#define IMX8QM_FSPI0_CLK 33 +#define IMX8QM_FSPI1_DIV 34 +#define IMX8QM_FSPI1_CLK 35 +#define IMX8QM_GPT0_DIV36 +#define IMX8QM_GPT0_CLK37 +#define IMX8QM_GPT1_DIV38 +#define IMX8QM_GPT1_CLK39 +#define IMX8QM_GPT2_DIV40 +#define IMX8QM_GPT2_CLK41 +#define IMX8QM_GPT3_DIV42 +#define IMX8QM_GPT3_CLK43 +#define IMX8QM_GPT4_DIV44 +#define IMX8QM_GPT4_CLK45 + +/* Connectivity */ +#define IMX8QM_APBHDMA_CLK 46 +#define IMX8QM_GPMI_APB_CLK47 +#define IMX8QM_GPMI_APB_BCH_CLK48 +#define IMX8QM_GPMI_BCH_IO_DIV 49 +#define IMX8QM_GPMI_BCH_IO_CLK 50 +#define IMX8QM_GPMI_BCH_DIV51 +#define IMX8QM_GPMI_BCH_CLK52 +#define IMX8QM_SDHC0_IPG_CLK 53 +#define IMX8QM_SDHC0_DIV 54 +#define IMX8QM_SDHC0_CLK 55 +#define IMX8QM_SDHC1_IPG_CLK 56 +#define IMX8QM_SDHC1_DIV 57 +#define IMX8QM_SDHC1_CLK 58 +#define IMX8QM_SDHC2_IPG_CLK 59 +#define IMX8QM_SDHC2_DIV 60 +#define IMX8QM_SDHC2_CLK 61 +#define IMX8QM_USB2_OH_AHB_CLK 62 +#define IMX8QM_USB2_OH_IPG_S_CLK 63 +#define
[U-Boot] [PATCH 04/10] arm: dts: introduce dtsi for i.MX8QM
Introduce basic dtsi for i.MX8QM, only support SDHC/FEC/LPUART.
Signed-off-by: Peng Fan
---
arch/arm/dts/fsl-imx8qm.dtsi | 400 +++
1 file changed, 400 insertions(+)
create mode 100644 arch/arm/dts/fsl-imx8qm.dtsi
diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
new file mode 100644
index 00..b39c40bd98
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -0,0 +1,400 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include "fsl-imx8-ca53.dtsi"
+#include
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "fsl,imx8qm";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 =
+ ethernet1 =
+ serial0 =
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x 0x8000 0 0x4000>;
+ /* DRAM space - 1, size : 1 GB DRAM */
+ };
+
+ gic: interrupt-controller@51a0 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x51a0 0 0x1>, /* GIC Dist */
+ <0x0 0x51b0 0 0xC>, /* GICR */
+ <0x0 0x5200 0 0x2000>, /* GICC */
+ <0x0 0x5201 0 0x1000>, /* GICH */
+ <0x0 0x5202 0 0x2>; /* GICV */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = ;
+ interrupt-parent = <>;
+ };
+
+ mu: mu@5d1c {
+ compatible = "fsl,imx8-mu";
+ reg = <0x0 0x5d1c 0x0 0x1>;
+ interrupts = ;
+ interrupt-parent = <>;
+ fsl,scu_ap_mu_id = <0>;
+ status = "okay";
+
+ clk: clk {
+ compatible = "fsl,imx8qm-clk";
+ #clock-cells = <1>;
+ };
+
+ iomuxc: iomuxc {
+ compatible = "fsl,imx8qm-iomuxc";
+ };
+ };
+
+ imx8qm-pm {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_lsio: PD_LSIO {
+ compatible = "nxp,imx8-pd";
+ reg = ;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_lsio_gpio0: PD_LSIO_GPIO_0 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <_lsio>;
+ };
+ pd_lsio_gpio1: PD_LSIO_GPIO_1 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <_lsio>;
+ };
+ pd_lsio_gpio2: PD_LSIO_GPIO_2 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <_lsio>;
+ };
+ pd_lsio_gpio3: PD_LSIO_GPIO_3 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <_lsio>;
+ };
+ pd_lsio_gpio4: PD_LSIO_GPIO_4 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <_lsio>;
+ };
+ pd_lsio_gpio5: PD_LSIO_GPIO_5{
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <_lsio>;
+ };
+ pd_lsio_gpio6:PD_LSIO_GPIO_6 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <_lsio>;
+ };
+ pd_lsio_gpio7: PD_LSIO_GPIO_7 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <_lsio>;
+ };
+ };
+
+ pd_conn: PD_CONN {
+ compatible = "nxp,imx8-pd";
+ reg = ;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_conn_sdch0: PD_CONN_SDHC_0 {
+ reg = ;
+ #power-domain-cells = <0>;
+
[U-Boot] [PATCH 02/10] dt-bindings: pinctrl: add i.MX8QM pads definition
Add i.MX8QM pads definition Signed-off-by: Peng Fan --- include/dt-bindings/pinctrl/pads-imx8qm.h | 961 ++ 1 file changed, 961 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pads-imx8qm.h diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h new file mode 100644 index 00..e980fd55ed --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8qm.h @@ -0,0 +1,961 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +#define SC_P_SIM0_CLK0 /* DMA.SIM0.CLK, LSIO.GPIO0.IO00 */ +#define SC_P_SIM0_RST1 /* DMA.SIM0.RST, LSIO.GPIO0.IO01 */ +#define SC_P_SIM0_IO 2 /* DMA.SIM0.IO, LSIO.GPIO0.IO02 */ +#define SC_P_SIM0_PD 3 /* DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */ +#define SC_P_SIM0_POWER_EN 4 /* DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */ +#define SC_P_SIM0_GPIO0_00 5 /* DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /* */ +#define SC_P_M40_I2C0_SCL7 /* M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */ +#define SC_P_M40_I2C0_SDA8 /* M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */ +#define SC_P_M40_GPIO0_009 /* M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */ +#define SC_P_M40_GPIO0_0110/* M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */ +#define SC_P_M41_I2C0_SCL11/* M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */ +#define SC_P_M41_I2C0_SDA12/* M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */ +#define SC_P_M41_GPIO0_0013/* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */ +#define SC_P_M41_GPIO0_0114/* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */ +#define SC_P_GPT0_CLK15/* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */ +#define SC_P_GPT0_CAPTURE16/* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */ +#define SC_P_GPT0_COMPARE17/* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */ +#define SC_P_GPT1_CLK18/* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */ +#define SC_P_GPT1_CAPTURE19/* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */ +#define SC_P_GPT1_COMPARE20/* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */ +#define SC_P_UART0_RX21/* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */ +#define SC_P_UART0_TX22/* DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */ +#define SC_P_UART0_RTS_B 23/* DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */ +#define SC_P_UART0_CTS_B 24/* DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */ +#define SC_P_UART1_TX25/* DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */ +#define SC_P_UART1_RX26/* DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */ +#define SC_P_UART1_RTS_B 27/* DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */ +#define SC_P_UART1_CTS_B 28/* DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH29/* */ +#define SC_P_SCU_PMIC_MEMC_ON30/* SCU.GPIO0.IOXX_PMIC_MEMC_ON */ +#define SC_P_SCU_WDOG_OUT31/* SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SDA32/* SCU.PMIC_I2C.SDA */ +#define SC_P_PMIC_I2C_SCL33/* SCU.PMIC_I2C.SCL */ +#define SC_P_PMIC_EARLY_WARNING 34/* SCU.PMIC_EARLY_WARNING */ +#define SC_P_PMIC_INT_B 35/* SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_0036/* SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */ +#define SC_P_SCU_GPIO0_0137/* SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */ +#define SC_P_SCU_GPIO0_0238/* SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */ +#define SC_P_SCU_GPIO0_0339/* SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */ +#define SC_P_SCU_GPIO0_0440
[U-Boot] [PATCH 01/10] pinctrl: imx8: add i.MX8QM compatible
Add i.MX8QM compatible
Signed-off-by: Peng Fan
---
drivers/pinctrl/nxp/pinctrl-imx8.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c
b/drivers/pinctrl/nxp/pinctrl-imx8.c
index 0738da0ebe..c1b0ca438a 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx8.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx8.c
@@ -25,6 +25,7 @@ static int imx8_pinctrl_probe(struct udevice *dev)
static const struct udevice_id imx8_pinctrl_match[] = {
{ .compatible = "fsl,imx8qxp-iomuxc", .data =
(ulong)_pinctrl_soc_info },
+ { .compatible = "fsl,imx8qm-iomuxc", .data =
(ulong)_pinctrl_soc_info },
{ /* sentinel */ }
};
--
2.14.1
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Re: [U-Boot] [PATCH] Add support for initializing MMC
On Sat, 2018-12-22 at 13:51 -0700, Simon Glass wrote: > Hi Tien, > > On Fri, 21 Dec 2018 at 10:50, Chee, Tien Fong om> wrote: > > > > > > On Fri, 2018-12-21 at 10:16 -0700, Simon Glass wrote: > > > > > > Hi, > > > > > > On Fri, 21 Dec 2018 at 01:25, Chee, Tien Fong > > el.c > > > om> wrote: > > > > > > > > > > > > > > > > On Fri, 2018-12-14 at 14:53 +0800, tien.fong.c...@intel.com > > > > wrote: > > > > > > > > > > > > > > > From: Tien Fong Chee > > > > > > > > > > Firmware loader would encounter problem if the MMC is > > > > > accessed > > > > > before > > > > > initializing it. This patch would adding the support of > > > > > initializing > > > > > MMC before the MMC is accessed by firmware loader. > > > > > > > > > > Signed-off-by: Tien Fong Chee > > > > > --- > > > > > drivers/misc/fs_loader.c | 31 > > > > > +++ > > > > > 1 files changed, 31 insertions(+), 0 deletions(-) > > > > > > > > > Any comment for this patch? > > > This should not be needed with CONFIG_DM_MMC enabled as it should > > > be > > > enough to probe the mmc device. Is that right? > > No, CONFIG_DM_MMC is required, otherwise compiler would tell you > > error. > > This whole mechanism is always developed in DM context. > > What's your concern? You want me to add CONFIG_DM_MMC or replace > > with > > CONFIG_MMC? or You want to improve the document? > Well, mmc_blk_probe() calls mmc_init() on the device. So instead of > the code you have, would it be possible to probe the blk device? You > can use device_find_first_child() for that. Perhaps write a function > in blk.h which probes the first block device for a parent? Yeah, sure. Let me find out more info. > > Regards, > Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/3] Ethernet support for QEMU sifive_u machine
Hi Anup, On Wed, Dec 19, 2018 at 5:05 PM Bin Meng wrote: > > Hi Anup, > > On Wed, Dec 19, 2018 at 2:32 PM Anup Patel wrote: > > > > On Wed, Dec 19, 2018 at 11:02 AM Bin Meng wrote: > > > > > > Hi Anup, > > > > > > On Wed, Dec 19, 2018 at 12:41 PM Anup Patel wrote: > > > > > > > > On Tue, Dec 18, 2018 at 4:06 PM Bin Meng wrote: > > > > > > > > > > Hi Anup, > > > > > > > > > > On Tue, Dec 18, 2018 at 6:33 PM Anup Patel > > > > > wrote: > > > > > > > > > > > > On Tue, Dec 18, 2018 at 3:21 PM Bin Meng wrote: > > > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > > > On Mon, Dec 17, 2018 at 7:51 PM Anup Patel > > > > > > > wrote: > > > > > > > > > > > > > > > > This patchset enables Cadance MACB ethernet driver for > > > > > > > > QEMU sifive_u machine. The Cadance MACB ethernet driver > > > > > > > > works fine for QEMU sifive_u machince in both M-mode and > > > > > > > > S-mode with some minor fixes. > > > > > > > > > > > > > > > > The patches are based upon latest RISC-V U-Boot tree > > > > > > > > (git://git.denx.de/u-boot-riscv.git) at commit id > > > > > > > > 9deb8d2fcd13d4a40a4e63c396fe4376af46efac > > > > > > > > > > > > > > > > To try on QEMU, please ensure following patches are > > > > > > > > applied to QEMU sources: > > > > > > > > https://patchwork.kernel.org/patch/10729579/ > > > > > > > > https://patchwork.kernel.org/patch/10729581/ > > > > > > > > > > > > > > > > > > > > > > What "-device " parameter should I tell QEMU to instantiate the > > > > > > > MACB? > > > > > > > "-device ?" does not give me anything that looks like MACB. > > > > > > > Without a > > > > > > > proper "-device " parameter, I can boot U-Boot on QEMU sifive_u > > > > > > > and > > > > > > > see U-Boot driver is probed, but a simple 'ping' test does not > > > > > > > work. > > > > > > > > > > > > Try the following: > > > > > > # setenv ipaddr 10.0.2.1 > > > > > > # ping 10.0.2.2 > > > > > > > > > > > > > > > > Yes, I have set up all the required network parameters. > > > > > > > > > > > The above works for me on QEMU. > > > > > > > > > > My understanding is that we need enable QEMU network via "-netdev " > > > > > (either usr, or tap), with a corresponding "-device". I don't know how > > > > > to set it up. What's your command line to test this? > > > > > > > > > > > > > "-netdev" or "-device" parameters are not mandatory. By default, virtual > > > > NICs are in NAT mode. The QEMU NAT gateway is at IP address > > > > 10.0.2.2. We can always ping the NAT gateway when virtual NIC is in > > > > NAT mode. > > > > > > > > Here's how I compile for M-mode: > > > > # ARCH=riscv > > > > # CROSS_COMPILE=riscv64-unknown-linux-gnu- > > > > # make qemu-riscv64_defconfig > > > > # make > > > > > > > > My U-boot log is as follows: > > > > > > > > anup@anup-ubuntu64:~/Work/riscv-test/u-boot$ qemu-system-riscv64 -M > > > > sifive_u -m 256M -display none -serial stdio -kernel ./u-boot > > > > > > > > > > > > U-Boot 2019.01-rc1-00948-ge6b3cdafd0 (Dec 19 2018 - 10:05:50 +0530) > > > > > > > > CPU: rv64imafdcsu > > > > Model: ucbbar,spike-bare,qemu > > > > DRAM: 256 MiB > > > > In:uart@10013000 > > > > Out: uart@10013000 > > > > Err: uart@10013000 > > > > Net: > > > > Warning: ethernet@100900fc (eth0) using random MAC address - > > > > f6:1f:8c:13:83:c0 > > > > eth0: ethernet@100900fc > > > > Hit any key to stop autoboot: 0 > > > > > > > > Device 0: unknown device > > > > ethernet@100900fc: PHY present at 0 > > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > > BOOTP broadcast 1 > > > > DHCP client bound to address 10.0.2.15 (2 ms) > > > > Using ethernet@100900fc device > > > > TFTP from server 10.0.2.2; our IP address is 10.0.2.15 > > > > Filename 'boot.scr.uimg'. > > > > Load address: 0x8210 > > > > Loading: * > > > > TFTP error: 'Access violation' (2) > > > > Not retrying... > > > > ethernet@100900fc: PHY present at 0 > > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > > BOOTP broadcast 1 > > > > DHCP client bound to address 10.0.2.15 (1 ms) > > > > Using ethernet@100900fc device > > > > TFTP from server 10.0.2.2; our IP address is 10.0.2.15 > > > > Filename 'boot.scr.uimg'. > > > > Load address: 0x8100 > > > > Loading: * > > > > TFTP error: 'Access violation' (2) > > > > Not retrying... > > > > => ping 10.0.2.2 > > > > ethernet@100900fc: PHY present at 0 > > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > > Using ethernet@100900fc device > > > > host 10.0.2.2 is alive > > > > => > > > > ethernet@100900fc: PHY present at 0 > > > > ethernet@100900fc: link up, 100Mbps full-duplex (lpa: 0xcde1) > > > > Using ethernet@100900fc device > > > > host 10.0.2.2 is alive > > > > => qemu-system-riscv64: terminating on signal 2 > > > > > > > > > > I have always been using "qemu-system-riscv64 -nographic -M sifive_u > > > -kernel u-boot" to test U-Boot on qemu risc-v. > > > With above command, I can "ping 10.0.2.2" and get the exact the same >
[U-Boot] [PATCHv2] zynq: Kconfig: extend the bootstrap malloc() pool
Most of the memory is being consumed by device binding code, more space needed for other data structures. Z-turn board has already hit the limit, others may follow soon. Signed-off-by: Anton Gerasimov --- arch/arm/mach-zynq/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index a599ed63ee..21dfebf5c0 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -55,7 +55,7 @@ config SYS_CONFIG_NAME will be used for board configuration. config SYS_MALLOC_F_LEN - default 0x600 + default 0x800 config SYS_MALLOC_LEN default 0x140 -- 2.19.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-spi/master
On Mon, Dec 24, 2018 at 02:49:30AM +0530, Jagan Teki wrote: > Hi Tom, > > Please pull this as part of v2019.01 release. > > thanks, > Jagan. > > The following changes since commit 562a63e86bc7b308a328a7bbdf0db237855c39a8: > > Merge git://git.denx.de/u-boot-marvell (2018-12-21 13:38:09 -0500) > > are available in the Git repository at: > > git://git.denx.de/u-boot-spi.git master > > for you to fetch changes up to 532741dfbfebe917bf6c7c05ed7bab55105ce2a4: > > dm: MIGRATION: Update migration plan for SPI/SPI_FLASH (2018-12-24 02:05:25 > +0530) > > > Jagan Teki (1): > dm: MIGRATION: Update migration plan for SPI/SPI_FLASH WARNING: 'convertion' may be misspelled - perhaps 'conversion'? #30: FILE: Makefile:960: + @echo >&2 "Please update the board before v2019.04 for no dm convertion" Please fix since you're doing v2 anyhow, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] dm: usb: gadget: Fix boot breakage on sunxi platforms
On Fri, Dec 21, 2018 at 2:20 PM Jean-Jacques Hiblot wrote:
>
Better to have proper commit head that tells the real issue.
> Fixes commit 013116243950 ("dm: usb: create a new UCLASS ID for USB gadget
> devices")
>
> The UCLASS_DRIVER for id UCLASS_USB_GADGET_GENERIC needs to be declared
> even for platforms that do not enable DM_USB_GADGET. Otherwise the driver
> for their usb peripheral controller fails to bind.
Sorry this is unclear, you are trying to skip DM_USB_GADGET code even
though UCLASS_USB_GADGET_GENERIC id used. does it make sense?
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Re: [U-Boot] Pull request: u-boot-spi/master
Tom, Forgot to include once patch, please ignore this will send v2. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] A20-olinuxino-micro hangs in U-boot if powered from MINI-USB only.
Hi all, I'm observing that the said A20-onlinuxino-micro board hangs in U-boot in probing USB2 (see example below) in case it is powered by connecting its mini-usb connector to a computer. The problem does not happen if 12V power connector is also empoyed. (Note: the example attached below is for RC1, but RC2 is no different) I can't say if such problem was also present in previous version of u-boot or not. Thank you, Regards, Nikolai U-Boot 2019.01-rc1 (Dec 13 2018 - 15:11:11 +0300) Allwinner Technology CPU: Allwinner A20 (SUN7I) Model: Olimex A20-Olinuxino Micro I2C: ready DRAM: 1 GiB MMC: SUNXI SD/MMC: 0, SUNXI SD/MMC: 1 Loading Environment from FAT... MMC: no card present In:serial Out: serial Err: serial Net: eth0: ethernet@1c5 starting USB... USB0: USB EHCI 1.00 USB1: USB OHCI 1.0 USB2: ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] SPL variant of sunxi nand module
Hi again, The following commit (titled "use PIO instead of DMA") apparently broke actual reading of nand pages in SPL at least for A20: http://git.denx.de/?p=u-boot.git;a=commit;h=6ddbb1e936c78cdef1e7395039fa7020c5c75326 Instead of reading page contents, non-dma (current) version just feeds zeroes here. Tested on A20-olinuxino-micro with a Hynix 4GB nand chip. It'd be nice to somehow fix it back eventually :) Other than that, nand boot seems usable (with added necessary chip id). Thank you, Regards, Nikolai 24.12.2018 0:00, I wrote: 23.12.2018 21:58, I wrote: [...] Regarding the sunxi_nand_spl.c module, I can not find any mention if it implies NAND_ECC_HW, NAND_ECC_HW_SYNDROME, or rather some other mode, or if these modes are irrelevant in this case? So far I'm observing that sunxi_nand_spl module refuses to load erased nand pages (50 in the example below), which is correct, but it "successfully" loads filled nand pages as totally zeroed out, which is supposedly incorrect. This is in contrast with sunxi_nand module, that loads filled pages correctly, at least in my simple tests. So while detection in sunxi_nand_spl seems fine, reading seems not. I think digging deeper without some additional advice is a bit beyond my capabilities, although most probably some very tiny bits are missing... Thank you, Regards, Nikolai U-Boot SPL 2019.01-rc2 (Dec 23 2018 - 23:23:57 +0300) CPU: 91200Hz, AXI/AHB/APB: 3/2/2 DRAM: 1024 MiB >>SPL: board_init_r() Trying to boot from NAND spl: nand - using hw ecc [zh]nand_spl_load_image(50, 40)=-22 [zh]Read dump of page 768 (nand offs 60, page_size 8192): 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, [zh]Read dump of page 768 (nand offs 60, page_size 8192): 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, = U-Boot 2019.01-rc2 (Dec 23 2018 - 22:30:35 +0300) Allwinner Technology CPU: Allwinner A20 (SUN7I) Model: Olimex A20-Olinuxino Micro I2C: ready DRAM: 1 GiB NAND: nand_base: device found, Manufacturer ID: 0xad, Chip ID: 0xd7 nand_base: Hynix H27UBG8T2BTR-BC 32G 3.3V 8-bit nand_base: Hynix H27UBG8T2BTR-BC 32G 3.3V 8-bit nand_base: 4096 MiB, MLC, erase size: 2048 KiB, page size: 8192, OOB size: 640 Using ECC step 1024, strength 40, mode 2 4096 MiB In: serial Out: serial Err: serial SCSI: SATA link 0 timeout. AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode flags: ncq stag pm led clo only pmp pio slum part ccc apst Net: Can't get reset: -524 eth0: ethernet@1c5 Hit any key to stop autoboot: 0 => nand read 0x4500 0x40 0x1000 NAND read: device 0 offset 0x40, size 0x1000 Scanning device for bad blocks Bad eraseblock 0 at 0x001fe000 Bad eraseblock 1 at 0x003fe000 4096 bytes read: OK => md.b 0x4500 100 4500: b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 = Can not guess browsing through the code, it looks too different from sunxi_nand.c to compare. Thank you, Regards, Nikolai On the other hand, normal U-boot variant reads correct data from nand, but I'm not yet sure if it uses correct parameters and specifically, if they match those of SPL version. Need to add yet more debugging output. Thank you, Regards, Nikolai Michael Now the detection routine in sunxi_nand_spl apparently comes up with a value of ecc_strength=4 instead... Why is that? n - 1 using an index, if the code that I have is aligned so Michael Thank you, Regards, Nikolai Thank you, Regards, Nikolai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Pull request: u-boot-spi/master
Hi Tom, Please pull this as part of v2019.01 release. thanks, Jagan. The following changes since commit 562a63e86bc7b308a328a7bbdf0db237855c39a8: Merge git://git.denx.de/u-boot-marvell (2018-12-21 13:38:09 -0500) are available in the Git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 532741dfbfebe917bf6c7c05ed7bab55105ce2a4: dm: MIGRATION: Update migration plan for SPI/SPI_FLASH (2018-12-24 02:05:25 +0530) Jagan Teki (1): dm: MIGRATION: Update migration plan for SPI/SPI_FLASH Stefan Mavrodiev (1): spi: sun4i: Add rx_buf NULL pointer check Makefile | 9 + doc/driver-model/MIGRATION.txt | 10 +++--- drivers/spi/sun4i_spi.c| 3 ++- 3 files changed, 18 insertions(+), 4 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: cadence_qspi: remap iomem registers instead of just mapping
On Thu, Dec 20, 2018 at 6:28 PM Ramon Fried wrote: > > Some architectures(MIPS) requires real mapping of IOMEM, > other just define it as identity mapping. fix it. Hope it wouldn't break anything, will push after release? > > Signed-off-by: Ramon Fried Reviewed-by: Jagan Teki ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] SPL variant of sunxi nand module
23.12.2018 21:58, I wrote: [...] Regarding the sunxi_nand_spl.c module, I can not find any mention if it implies NAND_ECC_HW, NAND_ECC_HW_SYNDROME, or rather some other mode, or if these modes are irrelevant in this case? So far I'm observing that sunxi_nand_spl module refuses to load erased nand pages (50 in the example below), which is correct, but it "successfully" loads filled nand pages as totally zeroed out, which is supposedly incorrect. This is in contrast with sunxi_nand module, that loads filled pages correctly, at least in my simple tests. So while detection in sunxi_nand_spl seems fine, reading seems not. I think digging deeper without some additional advice is a bit beyond my capabilities, although most probably some very tiny bits are missing... Thank you, Regards, Nikolai U-Boot SPL 2019.01-rc2 (Dec 23 2018 - 23:23:57 +0300) CPU: 91200Hz, AXI/AHB/APB: 3/2/2 DRAM: 1024 MiB >>SPL: board_init_r() Trying to boot from NAND spl: nand - using hw ecc [zh]nand_spl_load_image(50, 40)=-22 [zh]Read dump of page 768 (nand offs 60, page_size 8192): 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, [zh]Read dump of page 768 (nand offs 60, page_size 8192): 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, = U-Boot 2019.01-rc2 (Dec 23 2018 - 22:30:35 +0300) Allwinner Technology CPU: Allwinner A20 (SUN7I) Model: Olimex A20-Olinuxino Micro I2C: ready DRAM: 1 GiB NAND: nand_base: device found, Manufacturer ID: 0xad, Chip ID: 0xd7 nand_base: Hynix H27UBG8T2BTR-BC 32G 3.3V 8-bit nand_base: Hynix H27UBG8T2BTR-BC 32G 3.3V 8-bit nand_base: 4096 MiB, MLC, erase size: 2048 KiB, page size: 8192, OOB size: 640 Using ECC step 1024, strength 40, mode 2 4096 MiB In:serial Out: serial Err: serial SCSI: SATA link 0 timeout. AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode flags: ncq stag pm led clo only pmp pio slum part ccc apst Net: Can't get reset: -524 eth0: ethernet@1c5 Hit any key to stop autoboot: 0 => nand read 0x4500 0x40 0x1000 NAND read: device 0 offset 0x40, size 0x1000 Scanning device for bad blocks Bad eraseblock 0 at 0x001fe000 Bad eraseblock 1 at 0x003fe000 4096 bytes read: OK => md.b 0x4500 100 4500: b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 = Can not guess browsing through the code, it looks too different from sunxi_nand.c to compare. Thank you, Regards, Nikolai On the other hand, normal U-boot variant reads correct data from nand, but I'm not yet sure if it uses correct parameters and specifically, if they match those of SPL version. Need to add yet more debugging output. Thank you, Regards, Nikolai Michael Now the detection routine in sunxi_nand_spl apparently comes up with a value of ecc_strength=4 instead... Why is that? n - 1 using an index, if the code that I have is aligned so Michael Thank you, Regards, Nikolai Thank you, Regards, Nikolai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: soft_spi: Fix null ptr when probing soft_spi.
On Wed, Dec 19, 2018 at 8:40 PM Horatiu Vultur
wrote:
>
> When probing soft_spi the result of dev_get_parent_priv(dev) in probe
> function is null ptr because the spi is on the ahb bus which has
> per_child_auto_alloc_size set to 0. Therefore it would generate an Ooops
> messages when accessing spi_slave structure.
>
> The fix consist of delaying the read of dm_spi_slave_platdata until a
> child under the spi is probed, to be able to read SPI mode. Therefore
> implement .child_pre_probe in which updates soft_spi_platdata based on
> child dm_spi_slave_platdata.
>
> Signed-off-by: Horatiu Vultur
> ---
> drivers/spi/soft_spi.c | 24 +---
> 1 file changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
> index b06883f..e28591b 100644
> --- a/drivers/spi/soft_spi.c
> +++ b/drivers/spi/soft_spi.c
> @@ -210,18 +210,13 @@ static int soft_spi_ofdata_to_platdata(struct udevice
> *dev)
>
> static int soft_spi_probe(struct udevice *dev)
> {
> - struct spi_slave *slave = dev_get_parent_priv(dev);
> struct soft_spi_platdata *plat = dev->platdata;
> - int cs_flags, clk_flags;
> int ret;
>
> - cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
> - clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
> -
> if (gpio_request_by_name(dev, "cs-gpios", 0, >cs,
> -GPIOD_IS_OUT | cs_flags) ||
> +GPIOD_IS_OUT) ||
> gpio_request_by_name(dev, "gpio-sck", 0, >sclk,
> -GPIOD_IS_OUT | clk_flags))
> +GPIOD_IS_OUT))
> return -EINVAL;
>
> ret = gpio_request_by_name(dev, "gpio-mosi", 0, >mosi,
> @@ -241,6 +236,20 @@ static int soft_spi_probe(struct udevice *dev)
> return 0;
> }
>
> +static int soft_spi_child_pre_probe(struct udevice *dev)
> +{
> + struct udevice *bus = dev_get_parent(dev);
> + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
> + struct soft_spi_platdata *plat = bus->platdata;
> +
> + if (!(slave->mode & SPI_CS_HIGH))
> + plat->cs.flags |= GPIOD_ACTIVE_LOW;
> + if (slave->mode & SPI_CPOL)
> + plat->sclk.flags |= GPIOD_ACTIVE_LOW;
Can't we update the flags during .set_mode? it set_mode would trigger
during initial probe time and modes were updated as part of that.
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Re: [U-Boot] SPL variant of sunxi nand module
Hi again, 23.12.2018 21:11, I wrote: [...] Indeed, its an index, and therefore it appears SPL's detection actually gives correct values! Nevertheless, SPL reads all zeroes from nand. Regarding the sunxi_nand_spl.c module, I can not find any mention if it implies NAND_ECC_HW, NAND_ECC_HW_SYNDROME, or rather some other mode, or if these modes are irrelevant in this case? Can not guess browsing through the code, it looks too different from sunxi_nand.c to compare. Thank you, Regards, Nikolai On the other hand, normal U-boot variant reads correct data from nand, but I'm not yet sure if it uses correct parameters and specifically, if they match those of SPL version. Need to add yet more debugging output. Thank you, Regards, Nikolai Michael Now the detection routine in sunxi_nand_spl apparently comes up with a value of ecc_strength=4 instead... Why is that? n - 1 using an index, if the code that I have is aligned so Michael Thank you, Regards, Nikolai Thank you, Regards, Nikolai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] SPL variant of sunxi nand module
Hi Michael, 23.12.2018 18:54, Michael Nazzareno Trimarchi: [...] Considering ecc_size=1024, ecc_strength=4 good(b). Considering addr_cycles=5, page_size=8192 accepted. I'm almost 100% sure that correct config would be page_size=8192, ecc_size=1024, ecc_strength=40 (from nand chip identification structure for regular linux kernel) That is an index on an array. Am I wrong? so the max is 74 Indeed, its an index, and therefore it appears SPL's detection actually gives correct values! Nevertheless, SPL reads all zeroes from nand. On the other hand, normal U-boot variant reads correct data from nand, but I'm not yet sure if it uses correct parameters and specifically, if they match those of SPL version. Need to add yet more debugging output. Thank you, Regards, Nikolai Michael Now the detection routine in sunxi_nand_spl apparently comes up with a value of ecc_strength=4 instead... Why is that? n - 1 using an index, if the code that I have is aligned so Michael Thank you, Regards, Nikolai Thank you, Regards, Nikolai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] Yet another old Hynix chip id.
Hi all,
Could some kind soul please add this id attached below?
Maybe even for 2019.01 if possible?
Otherwise nand is totally unaccessible in u-boot on some older
A20-olinuxino-micro board with this bloody old Hynix chip.
Thank you,
Regards,
Nikolai
==
--- a/u-boot/drivers/mtd/nand/raw/nand_ids.c
+++ b/u-boot/drivers/mtd/nand/raw/nand_ids.c
@@ -61,6 +61,10 @@
{"SDTNRGAMA 64G 3.3V 8-bit",
{ .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} },
SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40,
SZ_1K) },
+ {"H27UBG8T2BTR-BC 32G 3.3V 8-bit",
+ { .id = {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3} },
+ SZ_8K, SZ_4K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
+ NAND_ECC_INFO(40, SZ_1K), 0 },
{"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
==
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Re: [U-Boot] Please pull u-boot-marvell/master
On Fri, Dec 21, 2018 at 04:31:20PM +0100, Stefan Roese wrote: > Hi Tom, > > please pull the following minor, local changes and fixes: > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PULL] u-boot-socfpga/master
On Fri, Dec 21, 2018 at 01:42:50PM +0100, Marek Vasut wrote: > The following changes since commit 1f2e948d6d53f77a2ddb2dde3531b0d5bc2815ad: > > Prepare v2019.01-rc2 (2018-12-17 20:25:24 -0500) > > are available in the Git repository at: > > git://git.denx.de/u-boot-socfpga.git master > > for you to fetch changes up to bd5581716d0407272cfde624b484e530665b0a2f: > > arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration > (2018-12-20 17:12:25 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PULL u-boot] Please pull u-boot-amlogic-20181219
On Wed, Dec 19, 2018 at 04:26:24PM +0100, Neil Armstrong wrote: > Hi Tom, > > Here is single U-Boot DT fixup for the S400 board. > > Thanks, > Neil > > The following changes since commit 1f2e948d6d53f77a2ddb2dde3531b0d5bc2815ad: > > Prepare v2019.01-rc2 (2018-12-17 20:25:24 -0500) > > are available in the Git repository at: > > git://git.denx.de/u-boot-amlogic.git tags/u-boot-amlogic-20181219 > > for you to fetch changes up to 53904dc7c13841497835090a8057930d4a84c4de: > > arm: dts: s400: Fix status for eMMC and SDIO ports (2018-12-19 16:20:50 > +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PULL] MIPS updates for v2019.01
On Wed, Dec 19, 2018 at 03:52:09PM +0100, Daniel Schwierzeck wrote: > Hi Tom, > > though it's a little big for rc2, it's beside some bugfixes almost only new > code which is isolated to drivers and MIPS. The patches were on the list for > several weeks/months but the review process took a bit longer. > > Please consider pulling, thanks. > > https://travis-ci.org/danielschwierzeck/u-boot/builds/470042933 > > > The following changes since commit 1f2e948d6d53f77a2ddb2dde3531b0d5bc2815ad: > > Prepare v2019.01-rc2 (2018-12-17 20:25:24 -0500) > > are available in the Git repository at: > > git://git.denx.de/u-boot-mips.git tags/mips-updates-for-2019.11 > > for you to fetch changes up to 25c7de2255128743fcbe436b6f3b17a70d0cdd82: > > mips: jz47xx: Add Creator CI20 platform (2018-12-19 15:23:02 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Uboot send pull request
On Tue, Dec 18, 2018 at 06:09:33PM +0800, ub...@andestech.com wrote: > Hi Tom, > > Please pull some riscv update: > 1. Add DM drivers to support RISC-V CPU and timer, plus some bug fixes. > 2. Support SiFive UART > 3. Rename ax25-ae350 defconfig > > https://travis-ci.org/rickchen36/u-boot-riscv/builds/469364551 > > Thanks > > Rick > > > The following changes since commit 1f2e948d6d53f77a2ddb2dde3531b0d5bc2815ad: > > Prepare v2019.01-rc2 (2018-12-17 20:25:24 -0500) > > are available in the Git repository at: > > git://git.denx.de/u-boot-riscv.git > > for you to fetch changes up to 368ff57805b03bebf99e97e703ce07aec721bc71: > > doc: README.ae350: Sync for ax25-ae350 rename (2018-12-18 13:26:02 +0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] SPL variant of sunxi nand module
Hi On Sun, Dec 23, 2018 at 4:46 PM Nikolai Zhubr wrote: > > Hi again, > > 23.12.2018 16:29, I wrote: > > > U-Boot SPL 2019.01-rc2 (Dec 20 2018 - 16:30:46 +0300) > > > CPU: 91200Hz, AXI/AHB/APB: 3/2/2 > > > DRAM: 1024 MiB > > > Trying to boot from NAND > > > > Ok, discovered a special SPL-only sunxi_nand_spl variant, added some > debugging, so the detection is visible: > > In nand_detect_config(), start detection... > Considering addr_cycles=5, page_size=2048 > Considering ecc_size=1024, ecc_strength=0 failed(a). > Considering addr_cycles=5, page_size=2048 rejected. > Considering addr_cycles=5, page_size=4096 > Considering ecc_size=1024, ecc_strength=3 failed(a). > Considering addr_cycles=5, page_size=4096 rejected. > Considering addr_cycles=5, page_size=8192 > Considering ecc_size=1024, ecc_strength=4 good(b). > Considering addr_cycles=5, page_size=8192 accepted. > > I'm almost 100% sure that correct config would be page_size=8192, > ecc_size=1024, ecc_strength=40 (from nand chip identification structure > for regular linux kernel) That is an index on an array. Am I wrong? so the max is 74 Michael > > Now the detection routine in sunxi_nand_spl apparently comes up with a > value of ecc_strength=4 instead... Why is that? n - 1 using an index, if the code that I have is aligned so Michael > > > Thank you, > > Regards, > Nikolai > > > > > > > > Thank you, > > > > Regards, > > Nikolai > > ___ > > U-Boot mailing list > > U-Boot@lists.denx.de > > https://lists.denx.de/listinfo/u-boot > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot -- | Michael Nazzareno Trimarchi Amarula Solutions BV | | COO - Founder Cruquiuskade 47 | | +31(0)851119172 Amsterdam 1018 AM NL | | [`as] http://www.amarulasolutions.com | ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] SPL variant of sunxi nand module
Hi again, 23.12.2018 16:29, I wrote: > U-Boot SPL 2019.01-rc2 (Dec 20 2018 - 16:30:46 +0300) > CPU: 91200Hz, AXI/AHB/APB: 3/2/2 > DRAM: 1024 MiB > Trying to boot from NAND Ok, discovered a special SPL-only sunxi_nand_spl variant, added some debugging, so the detection is visible: In nand_detect_config(), start detection... Considering addr_cycles=5, page_size=2048 Considering ecc_size=1024, ecc_strength=0 failed(a). Considering addr_cycles=5, page_size=2048 rejected. Considering addr_cycles=5, page_size=4096 Considering ecc_size=1024, ecc_strength=3 failed(a). Considering addr_cycles=5, page_size=4096 rejected. Considering addr_cycles=5, page_size=8192 Considering ecc_size=1024, ecc_strength=4 good(b). Considering addr_cycles=5, page_size=8192 accepted. I'm almost 100% sure that correct config would be page_size=8192, ecc_size=1024, ecc_strength=40 (from nand chip identification structure for regular linux kernel) Now the detection routine in sunxi_nand_spl apparently comes up with a value of ecc_strength=4 instead... Why is that? Thank you, Regards, Nikolai Thank you, Regards, Nikolai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] fs: cbfs: remove wrong header validation
Hi Andre, On Sat, Dec 22, 2018 at 7:07 PM Andre Heider wrote: > > Hi Bin, > > this patch reminds me of one I sent some time ago: > http://patchwork.ozlabs.org/patch/873666/ > > I forgot about it, so didn't follow up on the comments, but iirc this > fixed a 'Bad CBFS file' error for me too. Does that work for you? > I checked your patch. It can "fix" the problem, but the approach your patch used is not 100% correct. Please check my series instead. [snip] Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] SPL variant of sunxi nand module
Hi all, While fighting with this A20-olinuxino nand boot process I've initially found that some essential nand-related parameters are apparently missing by default, preventing reasonable nand operation, so I started debugging this gradually. > U-Boot SPL 2019.01-rc2 (Dec 20 2018 - 16:30:46 +0300) > CPU: 91200Hz, AXI/AHB/APB: 3/2/2 > DRAM: 1024 MiB > Trying to boot from NAND Now I've discovered that SPL-build variant of sunxi_nand module is missing the sunxi_nand_init() whatsoever. Apparently it is on purpose, because: #ifndef CONFIG_SPL_BUILD sunxi_nand_init(); #endif And I cannot simply un-ifdef sunxi_nand_init() here, because the SPL build would fail with undefined symbol then, but I'm wondering, where are all values (like ECC strength and such) are expected to come from instead? Is SPL nand loader is supposed to be usable at all currently? Thank you, Regards, Nikolai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
