Re: [U-Boot] [PATCH v2] imx: Use a convenient default value for SYS_MALLOC_F_LEN

[Peng Fan]

> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: 2019年5月4日 1:05
> To: sba...@denx.de
> Cc: dl-uboot-imx ; u-boot@lists.denx.de;
> pjtex...@koncepto.io; lukas.a...@aisec.fraunhofer.de;
> offougajo...@gmail.com; tr...@konsulko.com; Fabio Estevam
> 
> Subject: [PATCH v2] imx: Use a convenient default value for
> SYS_MALLOC_F_LEN
> 
> Commit 3a7c45f6a772 ("simple-bus: add DM_FLAG_PRE_RELOC flag to
> simple-bus driver") causes some i.MX boards that were converted to DM, such
> as warp7, to fail to boot.
> 
> As explained by Lukas Auer:
> 
> "With the patch, U-Boot probes the drivers for devices under simple-bus
> device tree nodes in the pre-relocation device model. The default value of
> CONFIG_SYS_MALLOC_F_LEN (0x400) leaves U-Boot with not enough
> memory to do this, causing it to hang."
> 
> Fix this problem by providing a convenient default value for
> CONFIG_SYS_MALLOC_F_LEN.
> 
> Reported-by: Pierre-Jean Texier 
> Suggested-by: Lukas Auer 
> Signed-off-by: Fabio Estevam 
> ---
> Changes since v1:
> - Move the default setting to the main Kconfig and make it depend on i.MX
> 
>  Kconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Kconfig b/Kconfig
> index 7a5491bd67..fd4ff42c17 100644
> --- a/Kconfig
> +++ b/Kconfig
> @@ -138,6 +138,8 @@ config SYS_MALLOC_F_LEN
>   depends on SYS_MALLOC_F
>   default 0x1000 if AM33XX
>   default 0x2800 if SANDBOX
> + default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \
> +ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5)
>   default 0x400
>   help
> Before relocation, memory is very limited on many platforms. Still,

Reviewed-by: Peng Fan 

> --
> 2.17.1

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Re: [U-Boot] [PATCH] arm: socfpga: control reboot from SRAM via env callback

[Marek Vasut]

On 5/4/19 9:10 PM, Simon Goldschmidt wrote:
> Am 04.05.2019 um 20:43 schrieb Marek Vasut:
>> On 5/3/19 10:53 PM, Simon Goldschmidt wrote:
>>>
>>>
>>> Marek Vasut mailto:ma...@denx.de>> schrieb am Fr., 3.
>>> Mai 2019, 22:42:
>>>
>>>  On 5/3/19 10:39 PM, Simon Goldschmidt wrote:
>>>  >
>>>  >
>>>  > On 03.05.19 22:35, Marek Vasut wrote:
>>>  >> On 5/3/19 10:30 PM, Simon Goldschmidt wrote:
>>>  >>>
>>>  >>>
>>>  >>> On 03.05.19 22:28, Marek Vasut wrote:
>>>   On 5/3/19 10:08 PM, Simon Goldschmidt wrote:
>>>  > This moves the code that enables the Boot ROM to just jump
>>> to SRAM
>>>  > instead
>>>  > of loading SPL from the original boot source on warm reboot.
>>>  >
>>>  > Instead of always enabling this, an environment callback
>>> for the
>>>  > env var
>>>  > "socfpga_reboot_from_sram" is used. This way, the
>>> behaviour can be
>>>  > enabled
>>>  > at runtime and via saved environment.
>>>  >
>>>  > Signed-off-by: Simon Goldschmidt
>>>  >>  >
>>>  
>>>   Would that be like a default "reset" command action ?
>>>   This probably shouldn't be socfpga specific then.
>>>  >>>
>>>  >>> No, it's a thing that lives on and influences even the soft
>>>  reset issued
>>>  >>> by linux "reboot" command. This is something *very* socfpga
>>>  specific.
>>>  >>
>>>  >> Hmmm, so isn't this a policy to be configured on the Linux end ?
>>>  >
>>>  > Might be, but it affects U-Boot's 'reset' command as well. And
>>> I guess
>>>  > it's set up in U-Boot this early to ensure it always works.
>>>
>>>  Drat, that's right. So there has to be some way to agree on how the
>>>  reset works between the kernel and U-Boot ?
>>>
>>>  > If it were for me, we could drop writing this magic
>>> altogether. I just
>>>  > figured some boards might require it to be written somewhere,
>>> and came
>>>  > up with a patch that might save those boards with the way it was
>>>  before.
>>>
>>>  Isn't this magic actually used by bootrom ?
>>>
>>>
>>> Right. It tells the boot rom to jump to ocram on next reboot instead of
>>> loading spl from qspi or mmc. But if that's required or not a good idea
>>> at all depends on many factors. Some of them board related, some U-Boot
>>> related and some Linux related (depending on the hardware and drivers
>>> used).
>>
>> Should that be runtime configurable then ?
> 
> Since it might depend on Linux putting the qspi chip into a state where
> it's not accessible by the boot ROM. That might change without
> rebuilding U-Boot.

If Linux switches the chip into some weird mode the bootrom cannot cope
with, it's a reset routing problem. This cannot be fixed in software.

> On the other hand, this is probably more of a U-Boot build time config.
> I could make it a Kconfig option as well...
> 
> Regards,
> Simon


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v3] Convert CONFIG_SUPPORT_EMMC_BOOT to Kconfig

[Tom Rini]

On Wed, May 01, 2019 at 07:58:27AM +, Alex Kiernan wrote:

> This converts the following to Kconfig:
>CONFIG_SUPPORT_EMMC_BOOT
> 
> As requested by Michal Simek , these boards
> have no eMMC so CONFIG_SUPPORT_EMMC_BOOT has not been migrated:
> 
>   xilinx_zynqmp_zc1275_revB
>   xilinx_zynqmp_zc1751_xm018_dc4
>   xilinx_zynqmp_zc1751_xm019_dc5
>   xilinx_zynqmp_zcu100_revC
>   xilinx_zynqmp_zcu102_rev1_0
>   xilinx_zynqmp_zcu102_revA
>   xilinx_zynqmp_zcu102_revB
>   xilinx_zynqmp_zcu104_revA
>   xilinx_zynqmp_zcu104_revC
>   xilinx_zynqmp_zcu106_revA
>   xilinx_zynqmp_zcu111_revA
> 
> Signed-off-by: Alex Kiernan 
> Acked-by: Lukasz Majewski 
> Acked-by: Patrick Delaunay 
> Acked-by: Ramon Fried 
> Reviewed-by: Andy Shevchenko 
> Tested-by: Sébastien Szymanski 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH 3/5] nand: davinci: remove dead code for dm644x

[Tom Rini]

On Mon, Apr 29, 2019 at 06:37:10PM +0200, Bartosz Golaszewski wrote:

> From: Bartosz Golaszewski 
> 
> The support for DaVinci DM* SoCs has been dropped. The code that used
> to be relevant to dm644x is no longer needed. Remove it.
> 
> Signed-off-by: Bartosz Golaszewski 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 2/5] arm: davinci: remove dead code for PHYs used by DaVinci DM* boards

[Tom Rini]

On Mon, Apr 29, 2019 at 06:37:09PM +0200, Bartosz Golaszewski wrote:

> From: Bartosz Golaszewski 
> 
> The support for DaVinci DM* boards has been dropped a while ago. The
> code for all those PHYs is no longer used and they have their own
> proper PHY drivers in drivers/net/phy anyway. Remove all dead code.
> 
> Signed-off-by: Bartosz Golaszewski 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH 4/5] usb: musb_hcd: remove unnecessary ifdefs for dm* SoCs

[Tom Rini]

On Mon, Apr 29, 2019 at 06:37:11PM +0200, Bartosz Golaszewski wrote:

> From: Bartosz Golaszewski 
> 
> The support for DaVinci DM* SoCs has been dropped. The ifdefs in the
> musb_hcd driver are no longer needed. Remove them.
> 
> Signed-off-by: Bartosz Golaszewski 
> Acked-by: Marek Vasut 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH 5/5] arm: davinci: remove leftover code for dm* SoCs

[Tom Rini]

On Mon, Apr 29, 2019 at 06:37:12PM +0200, Bartosz Golaszewski wrote:

> From: Bartosz Golaszewski 
> 
> The support for DaVinci DM* SoCs has been dropped a while ago. There's
> still a lot of leftover code in mach-davinci though. Entirely remove
> certain files and modify the common code to no longer reference
> unsupported chips.
> 
> Note: all DaVinci platforms supported in u-boot now define SOC_DA8XX
> but not all define SOC_DA850 (e.g. omapl138). We can safely remove
> all ifdefs for the former, but let's leave the ones for the latter.
> 
> Signed-off-by: Bartosz Golaszewski 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH 1/5] net: davinci_emac: drop support for unused PHYs

[Tom Rini]

On Mon, Apr 29, 2019 at 06:37:08PM +0200, Bartosz Golaszewski wrote:

> From: Bartosz Golaszewski 
> 
> The boards with SoCs from the DaVinci DM* family used to come with
> different PHYs that needed special support implemented in mach-davinci.
> 
> Since the support for these chips has long been removed, we can now
> drop this unnused code from the emac driver.
> 
> Signed-off-by: Bartosz Golaszewski 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH] delete Kbuild "select" of long-dead SPL_DISABLE_OF_CONTROL

[Tom Rini]

On Sun, Apr 14, 2019 at 06:20:55AM -0400, Robert P. J. Day wrote:

> >From way back in 2015:
> 
>   commit dffb86e468c8e02ba77283989aefef214d904dc5
>   Author: Masahiro Yamada 
>   Date:   Wed Aug 12 07:31:54 2015 +0900
> 
> of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROL
> 
> As we discussed a couple of times, negative CONFIG options make our
> life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ...
> and here is another one.
> 
> Now, there are three boards enabling OF_CONTROL on SPL:
>  - socfpga_arria5_defconfig
>  - socfpga_cyclone5_defconfig
>  - socfpga_socrates_defconfig
> 
> This commit adds CONFIG_SPL_OF_CONTROL for them and deletes
> CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert
> the logic.
> 
> Signed-off-by: Masahiro Yamada 
> Reviewed-by: Tom Rini 
> Reviewed-by: Simon Glass 
> Reviewed-by: Masahiro Yamada 

Applied to u-boot/master, thanks!

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[U-Boot] [PATCH 0/3] implement RegisterProtocolNotify()

[Heinrich Schuchardt]

Provide the missing implementation of the RegisterProtocolNotify() boot
service.

Provide a unit test for RegisterProtocolNotify().

Fix a problem with events of type EVT_NOTIFY_SIGNAL.

Heinrich Schuchardt (3):
  efi_loader: EVT_NOTIFY_SIGNAL events
  efi_loader: implement RegisterProtocolNotify()
  efi_selftest: unit test for RegisterProtocolNotify()

 include/efi_loader.h  |  19 ++
 lib/efi_loader/efi_boottime.c |  85 +--
 lib/efi_selftest/Makefile |   1 +
 .../efi_selftest_register_notify.c| 231 ++
 4 files changed, 321 insertions(+), 15 deletions(-)
 create mode 100644 lib/efi_selftest/efi_selftest_register_notify.c

--
2.20.1

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[U-Boot] [PATCH 3/3] efi_selftest: unit test for RegisterProtocolNotify()

[Heinrich Schuchardt]

Provide a unit test for the RegisterProtocolNotify() boot service.

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_selftest/Makefile |   1 +
 .../efi_selftest_register_notify.c| 231 ++
 2 files changed, 232 insertions(+)
 create mode 100644 lib/efi_selftest/efi_selftest_register_notify.c

diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index 4945691e67..c69ad7a9c0 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -27,6 +27,7 @@ efi_selftest_gop.o \
 efi_selftest_loaded_image.o \
 efi_selftest_manageprotocols.o \
 efi_selftest_memory.o \
+efi_selftest_register_notify.o \
 efi_selftest_rtc.o \
 efi_selftest_snp.o \
 efi_selftest_textinput.o \
diff --git a/lib/efi_selftest/efi_selftest_register_notify.c 
b/lib/efi_selftest/efi_selftest_register_notify.c
new file mode 100644
index 00..ee0ef395de
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_register_notify.c
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_register_notify
+ *
+ * Copyright (c) 2019 Heinrich Schuchardt 
+ *
+ * This unit test checks the following protocol services:
+ * InstallProtocolInterface, UninstallProtocolInterface,
+ * RegisterProtocolNotify, CreateEvent, CloseEvent.
+ */
+
+#include 
+
+/*
+ * The test currently does not actually call the interface function.
+ * So this is just a dummy structure.
+ */
+struct interface {
+   void (EFIAPI * inc)(void);
+};
+
+struct context {
+   void *registration_key;
+   efi_uintn_t notify_count;
+   efi_uintn_t handle_count;
+   efi_handle_t *handles;
+};
+
+static struct efi_boot_services *boottime;
+static efi_guid_t guid1 =
+   EFI_GUID(0x2e7ca819, 0x21d3, 0x0a3a,
+0xf7, 0x91, 0x82, 0x1f, 0x7a, 0x83, 0x67, 0xaf);
+static efi_guid_t guid2 =
+   EFI_GUID(0xf909f2bb, 0x90a8, 0x0d77,
+0x94, 0x0c, 0x3e, 0xa8, 0xea, 0x38, 0xd6, 0x6f);
+static struct context context;
+static struct efi_event *event;
+
+/*
+ * Notification function, increments the notification count if parameter
+ * context is provided.
+ *
+ * @event  notified event
+ * @contextpointer to the notification count
+ */
+static void EFIAPI notify(struct efi_event *event, void *context)
+{
+   struct context *cp = context;
+   efi_status_t ret;
+
+   cp->notify_count++;
+
+   ret = boottime->locate_handle_buffer(BY_REGISTER_NOTIFY, NULL,
+cp->registration_key,
+>handle_count,
+>handles);
+   if (ret != EFI_SUCCESS)
+   cp->handle_count = 0;
+}
+
+/*
+ * Setup unit test.
+ *
+ * @handle:handle of the loaded image
+ * @systable:  system table
+ */
+static int setup(const efi_handle_t img_handle,
+const struct efi_system_table *systable)
+{
+   efi_status_t ret;
+
+   boottime = systable->boottime;
+
+   ret = boottime->create_event(EVT_NOTIFY_SIGNAL,
+TPL_CALLBACK, notify, ,
+);
+   if (ret != EFI_SUCCESS) {
+   efi_st_error("could not create event\n");
+   return EFI_ST_FAILURE;
+   }
+
+   ret = boottime->register_protocol_notify(, event,
+_key);
+   if (ret != EFI_SUCCESS) {
+   efi_st_error("could not register event\n");
+   return EFI_ST_FAILURE;
+   }
+
+   return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ */
+static int teardown(void)
+{
+   efi_status_t ret;
+
+   if (event) {
+   ret = boottime->close_event(event);
+   event = NULL;
+   if (ret != EFI_SUCCESS) {
+   efi_st_error("could not close event\n");
+   return EFI_ST_FAILURE;
+   }
+   }
+
+   return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ */
+static int execute(void)
+{
+   efi_status_t ret;
+   efi_handle_t handle1 = NULL, handle2 = NULL;
+   struct interface interface1, interface2;
+
+   ret = boottime->install_protocol_interface(, ,
+  EFI_NATIVE_INTERFACE,
+  );
+   if (ret != EFI_SUCCESS) {
+   efi_st_error("could not install interface\n");
+   return EFI_ST_FAILURE;
+   }
+   if (!context.notify_count) {
+   efi_st_error("install was not notified\n");
+   return EFI_ST_FAILURE;
+   }
+   if (context.notify_count > 1) {
+   efi_st_error("install was notified too often\n");
+   return EFI_ST_FAILURE;
+   }
+   if (context.handle_count != 1) {
+   efi_st_error("LocateHandle failed\n");
+   return EFI_ST_FAILURE;
+   }
+   ret = 

[U-Boot] [PATCH 1/3] efi_loader: EVT_NOTIFY_SIGNAL events

[Heinrich Schuchardt]

The notification function of events of type EVT_NOTIFY_SIGNAL should always
be queued when SignalEvent() is called.

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_boottime.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 7aa2b4e16e..a3d206bd51 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -239,7 +239,7 @@ void efi_signal_event(struct efi_event *event, bool 
check_tpl)
if (evt->is_queued)
efi_queue_event(evt, check_tpl);
}
-   } else if (!event->is_signaled) {
+   } else {
event->is_signaled = true;
if (event->type & EVT_NOTIFY_SIGNAL)
efi_queue_event(event, check_tpl);
--
2.20.1

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[U-Boot] [PATCH 2/3] efi_loader: implement RegisterProtocolNotify()

[Heinrich Schuchardt]

The RegisterProtocolNotify() boot service registers an event to be
notified upon the installation of a protocol interface with the
specified GUID.

Add the missing implementation.

Signed-off-by: Heinrich Schuchardt 
---
 include/efi_loader.h  | 19 
 lib/efi_loader/efi_boottime.c | 83 +--
 2 files changed, 88 insertions(+), 14 deletions(-)

diff --git a/include/efi_loader.h b/include/efi_loader.h
index d73c89ac26..ef18d872d7 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -274,6 +274,25 @@ extern struct list_head efi_obj_list;
 /* List of all events */
 extern struct list_head efi_events;

+/**
+ * efi_register_notify_event - event registered by RegisterProtocolNotify()
+ *
+ * The address of this structure serves as registration value.
+ *
+ * @link:  link to list of all registered events
+ * @event: registered event. The same event may registered for
+ * multiple GUIDs.
+ * @protocol:  protocol for which the event is registered
+ */
+struct efi_register_notify_event {
+   struct list_head link;
+   struct efi_event *event;
+   efi_guid_t protocol;
+};
+
+/* List of all events registered by RegisterProtocolNotify() */
+extern struct list_head efi_register_notify_events;
+
 /* Initialize efi execution environment */
 efi_status_t efi_init_obj_list(void);
 /* Called by bootefi to initialize root node */
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index a3d206bd51..9a6e1947a6 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -27,6 +27,9 @@ LIST_HEAD(efi_obj_list);
 /* List of all events */
 LIST_HEAD(efi_events);

+/* List of all events registered by RegisterProtocolNotify() */
+LIST_HEAD(efi_register_notify_events);
+
 /* Handle of the currently executing image */
 static efi_handle_t current_image;

@@ -908,9 +911,21 @@ static efi_status_t EFIAPI efi_signal_event_ext(struct 
efi_event *event)
  */
 static efi_status_t EFIAPI efi_close_event(struct efi_event *event)
 {
+   struct efi_register_notify_event *item, *next;
+
EFI_ENTRY("%p", event);
if (efi_is_event(event) != EFI_SUCCESS)
return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+   /* Remove protocol notify registrations for the event */
+   list_for_each_entry_safe(item, next, _register_notify_events,
+link) {
+   if (event == item->event) {
+   list_del(>link);
+   free(item);
+   }
+   }
+
list_del(>link);
free(event);
return EFI_EXIT(EFI_SUCCESS);
@@ -1014,6 +1029,7 @@ efi_status_t efi_add_protocol(const efi_handle_t handle,
struct efi_object *efiobj;
struct efi_handler *handler;
efi_status_t ret;
+   struct efi_register_notify_event *event;

efiobj = efi_search_obj(handle);
if (!efiobj)
@@ -1028,6 +1044,13 @@ efi_status_t efi_add_protocol(const efi_handle_t handle,
handler->protocol_interface = protocol_interface;
INIT_LIST_HEAD(>open_infos);
list_add_tail(>link, >protocols);
+
+   /* Notify registered events */
+   list_for_each_entry(event, _register_notify_events, link) {
+   if (!guidcmp(protocol, >protocol))
+   efi_signal_event(event->event, true);
+   }
+
if (!guidcmp(_guid_device_path, protocol))
EFI_PRINT("installed device path '%pD'\n", protocol_interface);
return EFI_SUCCESS;
@@ -1291,8 +1314,30 @@ static efi_status_t EFIAPI efi_register_protocol_notify(
struct efi_event *event,
void **registration)
 {
+   struct efi_register_notify_event *item;
+   efi_status_t ret = EFI_SUCCESS;
+
EFI_ENTRY("%pUl, %p, %p", protocol, event, registration);
-   return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+
+   if (!protocol || !event || !registration) {
+   ret = EFI_INVALID_PARAMETER;
+   goto out;
+   }
+
+   item = calloc(1, sizeof(struct efi_register_notify_event));
+   if (!item) {
+   ret = EFI_OUT_OF_RESOURCES;
+   goto out;
+   }
+
+   item->event = event;
+   memcpy(>protocol, protocol, sizeof(efi_guid_t));
+
+   list_add_tail(>link, _register_notify_events);
+
+   *registration = item;
+out:
+   return EFI_EXIT(ret);
 }

 /**
@@ -1307,8 +1352,7 @@ static efi_status_t EFIAPI efi_register_protocol_notify(
  * Return: 0 if the handle implements the protocol
  */
 static int efi_search(enum efi_locate_search_type search_type,
- const efi_guid_t *protocol, void *search_key,
- efi_handle_t handle)
+ const efi_guid_t *protocol, efi_handle_t handle)
 {
efi_status_t ret;

@@ -1316,8 +1360,6 @@ static int 

Re: [U-Boot] [PATCH v3 2/2] arm64: zynqmp: add tool to convert PMU config object .c to binary

[Michal Simek]

Hi,

pá 3. 5. 2019 v 23:15 odesílatel Luca Ceresoli 
napsal:

> Hi Michal,
>
> On 04/05/19 00:31, Michal Simek wrote:
> > Hi,
> >
> > On 15. 04. 19 9:47, Luca Ceresoli wrote:
> >> The recently-added ZYNQMP_LOAD_PM_CFG_OBJ_FILE option allows SPL to
> load a
> >> PMUFW configuration object from a binary blob. However the configuration
> >> object is produced by Xilinx proprietary tools as a C source file and no
> >> tool exists to easily convert it to a binary blob in an embedded Linux
> >> build system for U-Boot to use.
> >>
> >> Add a simple Python script to do the conversion.
> >>
> >> It is definitely not a complete C language parser, but it is enough to
> >> parse the known patterns generated by Xilinx tools, including:
> >>
> >>  - defines
> >>  - literal integers, optionally with a 'U' suffix
> >>  - bitwise OR between them
> >>
> >> Signed-off-by: Luca Ceresoli 
> >> ---
> >>  arch/arm/mach-zynqmp/pm_cfg_obj_convert.py | 302 +
> >>  1 file changed, 302 insertions(+)
> >>  create mode 100755 arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
> >>
> >> diff --git a/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
> b/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
> >> new file mode 100755
> >> index ..5aea15860319
> >> --- /dev/null
> >> +++ b/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
> >> @@ -0,0 +1,302 @@
> >> +#!/usr/bin/env python3
> >> +# SPDX-License-Identifier: GPL-2.0+
> >> +# Copyright (C) 2019 Luca Ceresoli 
> >> +
> >> +import sys
> >> +import re
> >> +import struct
> >> +import logging
> >> +import argparse
> >> +
> >> +parser = argparse.ArgumentParser(
> >> +description='Convert a PMU configuration object from C source to a
> binary blob.',
> >> +allow_abbrev=False)
> >> +parser.add_argument('-D', '--debug', action="store_true")
> >> +parser.add_argument(
> >> +"in_file", metavar='INPUT_FILE',
> >> +help='PMU configuration object (C source as produced by Xilinx
> XSDK)')
> >> +parser.add_argument(
> >> +"out_file", metavar='OUTPUT_FILE',
> >> +help='PMU configuration object binary blob')
> >> +args = parser.parse_args()
> >> +
> >> +logging.basicConfig(format='%(levelname)s:%(message)s',
> >> +level=(logging.DEBUG if args.debug else
> logging.WARNING))
> >> +
> >> +pm_define = {
> >> +'PM_CAP_ACCESS'   : 0x1,
> >> +'PM_CAP_CONTEXT'  : 0x2,
> >> +'PM_CAP_WAKEUP'   : 0x4,
> >> +
> >> +'NODE_UNKNOWN':  0,
> >> +'NODE_APU':  1,
> >> +'NODE_APU_0'  :  2,
> >> +'NODE_APU_1'  :  3,
> >> +'NODE_APU_2'  :  4,
> >> +'NODE_APU_3'  :  5,
> >> +'NODE_RPU':  6,
> >> +'NODE_RPU_0'  :  7,
> >> +'NODE_RPU_1'  :  8,
> >> +'NODE_PLD':  9,
> >> +'NODE_FPD': 10,
> >> +'NODE_OCM_BANK_0' : 11,
> >> +'NODE_OCM_BANK_1' : 12,
> >> +'NODE_OCM_BANK_2' : 13,
> >> +'NODE_OCM_BANK_3' : 14,
> >> +'NODE_TCM_0_A': 15,
> >> +'NODE_TCM_0_B': 16,
> >> +'NODE_TCM_1_A': 17,
> >> +'NODE_TCM_1_B': 18,
> >> +'NODE_L2' : 19,
> >> +'NODE_GPU_PP_0'   : 20,
> >> +'NODE_GPU_PP_1'   : 21,
> >> +'NODE_USB_0'  : 22,
> >> +'NODE_USB_1'  : 23,
> >> +'NODE_TTC_0'  : 24,
> >> +'NODE_TTC_1'  : 25,
> >> +'NODE_TTC_2'  : 26,
> >> +'NODE_TTC_3'  : 27,
> >> +'NODE_SATA'   : 28,
> >> +'NODE_ETH_0'  : 29,
> >> +'NODE_ETH_1'  : 30,
> >> +'NODE_ETH_2'  : 31,
> >> +'NODE_ETH_3'  : 32,
> >> +'NODE_UART_0' : 33,
> >> +'NODE_UART_1' : 34,
> >> +'NODE_SPI_0'  : 35,
> >> +'NODE_SPI_1'  : 36,
> >> +'NODE_I2C_0'  : 37,
> >> +'NODE_I2C_1'  : 38,
> >> +'NODE_SD_0'   : 39,
> >> +'NODE_SD_1'   : 40,
> >> +'NODE_DP' : 41,
> >> +'NODE_GDMA'   : 42,
> >> +'NODE_ADMA'   : 43,
> >> +'NODE_NAND'   : 44,
> >> +'NODE_QSPI'   : 45,
> >> +'NODE_GPIO'   : 46,
> >> +'NODE_CAN_0'  : 47,
> >> +'NODE_CAN_1'  : 48,
> >> +'NODE_EXTERN' : 49,
> >> +'NODE_APLL'   : 50,
> >> +'NODE_VPLL'   : 51,
> >> +'NODE_DPLL'   : 52,
> >> +'NODE_RPLL'   : 53,
> >> +'NODE_IOPLL'  : 54,
> >> +'NODE_DDR': 55,
> >> +'NODE_IPI_APU': 56,
> >> +'NODE_IPI_RPU_0'  : 57,
> >> +'NODE_GPU': 58,
> >> +'NODE_PCIE'   : 59,
> >> +'NODE_PCAP'   : 60,
> >> +'NODE_RTC': 61,
> >> +'NODE_LPD': 62,
> >> +'NODE_VCU': 63,
> >> +'NODE_IPI_RPU_1'  : 64,
> >> +'NODE_IPI_PL_0'   : 65,
> >> +'NODE_IPI_PL_1'   : 66,
> >> +'NODE_IPI_PL_2'   : 67,
> >> +'NODE_IPI_PL_3'   : 68,
> >> +'NODE_PL' : 69,
> >> +'NODE_ID_MA'  : 70,
> >> +
> >> +'XILPM_RESET_PCIE_CFG' : 1000,
> >> +'XILPM_RESET_PCIE_BRIDGE'  : 1001,
> >> +'XILPM_RESET_PCIE_CTRL': 1002,
> >> +

Re: [U-Boot] [PATCH] spl: kconfig: separate sysreset and firmware drivers from misc

[Simon Goldschmidt]

Am 04.05.2019 um 22:16 schrieb Marek Behun:

On Sat,  4 May 2019 22:03:56 +0200
Simon Goldschmidt  wrote:


diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h
index 018f54428b..7cffdc3d51 100644
--- a/include/configs/turris_omnia.h
+++ b/include/configs/turris_omnia.h
@@ -52,6 +52,8 @@
  #define CONFIG_SPL_STACK  (0x4000 + ((192 - 16) << 10))
  #define CONFIG_SPL_BOOTROM_SAVE   (CONFIG_SPL_STACK + 4)
  #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_DRIVERS_FIRMWARE_SUPPORT
+#define CONFIG_SPL_SYSRESET_SUPPORT


These are not required for Turris Omnia, only
CONFIG_SPL_DRIVERS_MISC_SUPPORT for ATSHA204A.


I would have suspected that not all of these are required for all boards 
I changed. However, I'd rather have this patch as it is (it adds kconfig 
symbols but shouldn't change the binaries) and the various board 
maintainers can then reduce their configuration as fits as a follow-up.


Regards,
Simon
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Re: [U-Boot] [PATCH] spl: kconfig: separate sysreset and firmware drivers from misc

[Marek Behun]

On Sat,  4 May 2019 22:03:56 +0200
Simon Goldschmidt  wrote:

> diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h
> index 018f54428b..7cffdc3d51 100644
> --- a/include/configs/turris_omnia.h
> +++ b/include/configs/turris_omnia.h
> @@ -52,6 +52,8 @@
>  #define CONFIG_SPL_STACK (0x4000 + ((192 - 16) << 10))
>  #define CONFIG_SPL_BOOTROM_SAVE  (CONFIG_SPL_STACK + 4)
>  #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> +#define CONFIG_SPL_DRIVERS_FIRMWARE_SUPPORT
> +#define CONFIG_SPL_SYSRESET_SUPPORT

These are not required for Turris Omnia, only
CONFIG_SPL_DRIVERS_MISC_SUPPORT for ATSHA204A.

Marek
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[U-Boot] [PATCH] spl: kconfig: separate sysreset and firmware drivers from misc

[Simon Goldschmidt]

This adds separate kconfig options for drivers/sysreset and
drivers/firmware.

Up to now, CONFIG_SPL_DRIVERS_MISC_SUPPORT added drivers/misc to SPL
build but also added drivers/firmware and drivers/sysreset at the same
time.

Since that is confusing, this patch adds CONFIG_SPL_SYSRESET_SUPPORT for
drivers/sysreset and CONFIG_SPL_DRIVERS_FIRMWARE_SUPPORT for
drivers/firmware (and accordingly for the TPL options).

To keep the binaries unchanged, this patch enables the 2 new options
on all boards where DRIVERS_MISC_SUPPORT has been enabled before.

Signed-off-by: Simon Goldschmidt 
---

 arch/arm/mach-rockchip/Kconfig|  4 +++
 arch/arm/mach-rockchip/rk3288/Kconfig |  8 ++
 arch/arm/mach-stm32/Kconfig   |  2 ++
 arch/arm/mach-stm32mp/Kconfig |  2 ++
 common/spl/Kconfig| 28 +++
 configs/B4420QDS_NAND_defconfig   |  2 ++
 configs/B4860QDS_NAND_defconfig   |  2 ++
 configs/C29XPCIE_NAND_defconfig   |  2 ++
 configs/P1010RDB-PA_36BIT_NAND_defconfig  |  4 +++
 configs/P1010RDB-PA_36BIT_SDCARD_defconfig|  2 ++
 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig  |  2 ++
 configs/P1010RDB-PA_NAND_defconfig|  4 +++
 configs/P1010RDB-PA_SDCARD_defconfig  |  2 ++
 configs/P1010RDB-PA_SPIFLASH_defconfig|  2 ++
 configs/P1010RDB-PB_36BIT_NAND_defconfig  |  4 +++
 configs/P1010RDB-PB_36BIT_SDCARD_defconfig|  2 ++
 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig  |  2 ++
 configs/P1010RDB-PB_NAND_defconfig|  4 +++
 configs/P1010RDB-PB_SDCARD_defconfig  |  2 ++
 configs/P1010RDB-PB_SPIFLASH_defconfig|  2 ++
 configs/T1023RDB_NAND_defconfig   |  2 ++
 configs/T1023RDB_SDCARD_defconfig |  2 ++
 configs/T1023RDB_SPIFLASH_defconfig   |  2 ++
 configs/T1024QDS_NAND_defconfig   |  2 ++
 configs/T1024QDS_SDCARD_defconfig |  2 ++
 configs/T1024QDS_SPIFLASH_defconfig   |  2 ++
 configs/T1024RDB_NAND_defconfig   |  2 ++
 configs/T1024RDB_SDCARD_defconfig |  2 ++
 configs/T1024RDB_SPIFLASH_defconfig   |  2 ++
 configs/T1040D4RDB_NAND_defconfig |  2 ++
 configs/T1040D4RDB_SDCARD_defconfig   |  2 ++
 configs/T1040D4RDB_SPIFLASH_defconfig |  2 ++
 configs/T1040RDB_NAND_defconfig   |  2 ++
 configs/T1040RDB_SDCARD_defconfig |  2 ++
 configs/T1040RDB_SPIFLASH_defconfig   |  2 ++
 configs/T1042D4RDB_NAND_defconfig |  2 ++
 configs/T1042D4RDB_SDCARD_defconfig   |  2 ++
 configs/T1042D4RDB_SPIFLASH_defconfig |  2 ++
 .../T1042RDB_PI_NAND_SECURE_BOOT_defconfig|  2 ++
 configs/T1042RDB_PI_NAND_defconfig|  2 ++
 configs/T1042RDB_PI_SDCARD_defconfig  |  2 ++
 configs/T1042RDB_PI_SPIFLASH_defconfig|  2 ++
 configs/T2080QDS_NAND_defconfig   |  2 ++
 configs/T2080QDS_SDCARD_defconfig |  2 ++
 configs/T2080QDS_SPIFLASH_defconfig   |  2 ++
 configs/T2080RDB_NAND_defconfig   |  2 ++
 configs/T2080RDB_SDCARD_defconfig |  2 ++
 configs/T2080RDB_SPIFLASH_defconfig   |  2 ++
 configs/T2081QDS_NAND_defconfig   |  2 ++
 configs/T2081QDS_SDCARD_defconfig |  2 ++
 configs/T2081QDS_SPIFLASH_defconfig   |  2 ++
 configs/T4160QDS_NAND_defconfig   |  2 ++
 configs/T4160QDS_SDCARD_defconfig |  2 ++
 configs/T4240QDS_NAND_defconfig   |  2 ++
 configs/T4240QDS_SDCARD_defconfig |  2 ++
 configs/T4240RDB_SDCARD_defconfig |  2 ++
 configs/am335x_guardian_defconfig |  2 ++
 configs/am43xx_evm_defconfig  |  2 ++
 configs/am65x_evm_a53_defconfig   |  2 ++
 configs/am65x_evm_r5_defconfig|  2 ++
 configs/am65x_hs_evm_a53_defconfig|  2 ++
 configs/am65x_hs_evm_r5_defconfig |  2 ++
 configs/chromebook_link64_defconfig   |  2 ++
 configs/imx8qm_mek_defconfig  |  2 ++
 configs/imx8qxp_mek_defconfig |  2 ++
 configs/lion-rk3368_defconfig |  4 +++
 configs/ls1021aqds_nand_defconfig |  2 ++
 configs/ls1021aqds_sdcard_ifc_defconfig   |  2 ++
 configs/ls1021aqds_sdcard_qspi_defconfig  |  2 ++
 ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig |  2 ++
 configs/ls1043aqds_nand_defconfig |  2 ++
 configs/ls1043aqds_sdcard_ifc_defconfig   |  2 ++
 configs/ls1043aqds_sdcard_qspi_defconfig  |  2 ++
 configs/ls1043ardb_nand_SECURE_BOOT_defconfig |  2 ++
 configs/ls1043ardb_nand_defconfig |  2 ++
 .../ls1043ardb_sdcard_SECURE_BOOT_defconfig   |  2 ++
 configs/ls1043ardb_sdcard_defconfig   |  2 ++
 configs/ls1046aqds_sdcard_ifc_defconfig   |  2 ++
 configs/ls1046aqds_sdcard_qspi_defconfig  |  2 ++
 configs/ls1046ardb_emmc_defconfig 

Re: [U-Boot] [PATCH] arm: socfpga: control reboot from SRAM via env callback

[Simon Goldschmidt]

Am 04.05.2019 um 20:43 schrieb Marek Vasut:

On 5/3/19 10:53 PM, Simon Goldschmidt wrote:



Marek Vasut mailto:ma...@denx.de>> schrieb am Fr., 3.
Mai 2019, 22:42:

 On 5/3/19 10:39 PM, Simon Goldschmidt wrote:
 >
 >
 > On 03.05.19 22:35, Marek Vasut wrote:
 >> On 5/3/19 10:30 PM, Simon Goldschmidt wrote:
 >>>
 >>>
 >>> On 03.05.19 22:28, Marek Vasut wrote:
  On 5/3/19 10:08 PM, Simon Goldschmidt wrote:
 > This moves the code that enables the Boot ROM to just jump to SRAM
 > instead
 > of loading SPL from the original boot source on warm reboot.
 >
 > Instead of always enabling this, an environment callback for the
 > env var
 > "socfpga_reboot_from_sram" is used. This way, the behaviour can be
 > enabled
 > at runtime and via saved environment.
 >
 > Signed-off-by: Simon Goldschmidt
 mailto:simon.k.r.goldschm...@gmail.com>>
 
  Would that be like a default "reset" command action ?
  This probably shouldn't be socfpga specific then.
 >>>
 >>> No, it's a thing that lives on and influences even the soft
 reset issued
 >>> by linux "reboot" command. This is something *very* socfpga
 specific.
 >>
 >> Hmmm, so isn't this a policy to be configured on the Linux end ?
 >
 > Might be, but it affects U-Boot's 'reset' command as well. And I guess
 > it's set up in U-Boot this early to ensure it always works.

 Drat, that's right. So there has to be some way to agree on how the
 reset works between the kernel and U-Boot ?

 > If it were for me, we could drop writing this magic altogether. I just
 > figured some boards might require it to be written somewhere, and came
 > up with a patch that might save those boards with the way it was
 before.

 Isn't this magic actually used by bootrom ?


Right. It tells the boot rom to jump to ocram on next reboot instead of
loading spl from qspi or mmc. But if that's required or not a good idea
at all depends on many factors. Some of them board related, some U-Boot
related and some Linux related (depending on the hardware and drivers used).


Should that be runtime configurable then ?


Since it might depend on Linux putting the qspi chip into a state where 
it's not accessible by the boot ROM. That might change without 
rebuilding U-Boot.


On the other hand, this is probably more of a U-Boot build time config. 
I could make it a Kconfig option as well...


Regards,
Simon
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[U-Boot] Pull request v2: u-boot-sunxi/master

[Jagan Teki]

Hi Tom,

Please pull this PR.

Summary:
- H6 Beelink GS1 board (Clément)
- Olimex A64-Teres-I board (Jonas)
- sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej)
- EPHY clock changes (Jagan)
- EMAC enablement on Cubietruck Plus, BPI-M3 (Chen-Yu Tsai)

Changes for v2:
- Skip _relaxed MMIO changes

The following changes since commit 1f4ae66eaab29bfb5d1eb44996f7826c9cd01ed1:

  Merge tag 'arc-for-2019.07' of git://git.denx.de/u-boot-arc (2019-04-18 
12:12:16 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-sunxi.git master

for you to fetch changes up to 4488e3031bb96fe362f04fec4a75cd621cb8b4d3:

  sunxi: Enable EMAC on the Bananapi M3 (2019-05-03 15:06:12 +0530)


Chen-Yu Tsai (2):
  sunxi: Enable EMAC on the Cubietruck Plus
  sunxi: Enable EMAC on the Bananapi M3

Clément Péron (1):
  arm: dts: h6: Add Beelink GS1 initial support

Jagan Teki (6):
  clk: Get the CLK by index without device
  clk: Use clk_get_by_index_tail()
  test/dm: clk: Add clk_get_by_index[_nodev] test
  reset: Get the RESET by index without device
  test/dm: reset: Add reset_get_by_index[_nodev] test
  net: sun8i_emac: Add EPHY CLK and RESET support

Jonas Smedegaard (1):
  sun50i: a64: Add Olimex A64-Teres-I board initial support

Ondrej Jirman (1):
  sunxi: Fix build when CONFIG_CMD_PXE or CONFIG_CMD_DHCP are disabled

 arch/arm/dts/Makefile   |   4 +-
 arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi |  41 +
 arch/arm/dts/sun50i-a64-teres-i.dts | 270 
 arch/arm/dts/sun50i-h6-beelink-gs1.dts  | 184 +++
 board/sunxi/MAINTAINERS |  12 ++
 configs/Cubietruck_plus_defconfig   |   2 +
 configs/Sinovoip_BPI_M3_defconfig   |   4 +-
 configs/beelink_gs1_defconfig   |  15 ++
 configs/teres_i_defconfig   |  22 +++
 drivers/clk/clk-uclass.c|  75 ++--
 drivers/net/sun8i_emac.c|  74 ++--
 drivers/reset/reset-uclass.c|  53 --
 include/clk.h   |  15 ++
 include/configs/sunxi-common.h  |  16 +-
 include/reset.h |  16 ++
 test/dm/clk.c   |  21 +++
 test/dm/reset.c |  23 +++
 17 files changed, 791 insertions(+), 56 deletions(-)
 create mode 100644 arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi
 create mode 100644 arch/arm/dts/sun50i-a64-teres-i.dts
 create mode 100644 arch/arm/dts/sun50i-h6-beelink-gs1.dts
 create mode 100644 configs/beelink_gs1_defconfig
 create mode 100644 configs/teres_i_defconfig
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Re: [U-Boot] [PATCH] arm: socfpga: control reboot from SRAM via env callback

[Marek Vasut]

On 5/3/19 10:53 PM, Simon Goldschmidt wrote:
> 
> 
> Marek Vasut mailto:ma...@denx.de>> schrieb am Fr., 3.
> Mai 2019, 22:42:
> 
> On 5/3/19 10:39 PM, Simon Goldschmidt wrote:
> >
> >
> > On 03.05.19 22:35, Marek Vasut wrote:
> >> On 5/3/19 10:30 PM, Simon Goldschmidt wrote:
> >>>
> >>>
> >>> On 03.05.19 22:28, Marek Vasut wrote:
>  On 5/3/19 10:08 PM, Simon Goldschmidt wrote:
> > This moves the code that enables the Boot ROM to just jump to SRAM
> > instead
> > of loading SPL from the original boot source on warm reboot.
> >
> > Instead of always enabling this, an environment callback for the
> > env var
> > "socfpga_reboot_from_sram" is used. This way, the behaviour can be
> > enabled
> > at runtime and via saved environment.
> >
> > Signed-off-by: Simon Goldschmidt
>  >
> 
>  Would that be like a default "reset" command action ?
>  This probably shouldn't be socfpga specific then.
> >>>
> >>> No, it's a thing that lives on and influences even the soft
> reset issued
> >>> by linux "reboot" command. This is something *very* socfpga
> specific.
> >>
> >> Hmmm, so isn't this a policy to be configured on the Linux end ?
> >
> > Might be, but it affects U-Boot's 'reset' command as well. And I guess
> > it's set up in U-Boot this early to ensure it always works.
> 
> Drat, that's right. So there has to be some way to agree on how the
> reset works between the kernel and U-Boot ?
> 
> > If it were for me, we could drop writing this magic altogether. I just
> > figured some boards might require it to be written somewhere, and came
> > up with a patch that might save those boards with the way it was
> before.
> 
> Isn't this magic actually used by bootrom ?
> 
> 
> Right. It tells the boot rom to jump to ocram on next reboot instead of
> loading spl from qspi or mmc. But if that's required or not a good idea
> at all depends on many factors. Some of them board related, some U-Boot
> related and some Linux related (depending on the hardware and drivers used).

Should that be runtime configurable then ?

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] cmd: reset: add parameters to specify reboot_mode

[Simon Goldschmidt]

Am 03.05.2019 um 23:10 schrieb Simon Glass:

Hi Simon,

On Fri, 3 May 2019 at 14:43, Marek Vasut  wrote:


On 5/3/19 10:40 PM, Simon Goldschmidt wrote:



On 03.05.19 22:37, Marek Vasut wrote:

On 5/3/19 10:33 PM, Simon Goldschmidt wrote:



On 03.05.19 22:27, Marek Vasut wrote:

On 5/3/19 10:25 PM, Simon Goldschmidt wrote:

This patch adds parameter support for the 'reset' command to specify
the reboot mode (cold vs. warm).

Checking these parameters is implemented in the DM implementation.

Signed-off-by: Simon Goldschmidt 
---

cmd/boot.c |  4 ++--
drivers/sysreset/sysreset-uclass.c | 17 -
2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/cmd/boot.c b/cmd/boot.c
index 9150fce80b..c3f33a9ca3 100644
--- a/cmd/boot.c
+++ b/cmd/boot.c
@@ -56,9 +56,9 @@ U_BOOT_CMD(
#endif
  U_BOOT_CMD(
-reset, 1, 0,do_reset,
+reset, 2, 0,do_reset,
"Perform RESET of the CPU",
-""
+"[] - type of reboot"
);
  #ifdef CONFIG_CMD_POWEROFF
diff --git a/drivers/sysreset/sysreset-uclass.c
b/drivers/sysreset/sysreset-uclass.c
index ad831c703a..fbda3f44f2 100644
--- a/drivers/sysreset/sysreset-uclass.c
+++ b/drivers/sysreset/sysreset-uclass.c
@@ -111,9 +111,24 @@ void reset_cpu(ulong addr)
  int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
argv[])
{
+enum sysreset_t reboot_mode = SYSRESET_COLD;
+
+if (argc > 1 && argv[1]) {
+switch (*argv[1]) {
+case 'w':
+reboot_mode = SYSRESET_WARM;
+printf("warm ");
+break;
+case 'c':
+reboot_mode = SYSRESET_COLD;
+printf("cold ");
+break;


Please can we have a pytest for this command?


There's 'test_sandbox_exit.py' that seems to test that the "reset" 
command exits sandbox process. How would I test differing between "warm" 
and "cold" exit?


Regards,
Simon



Regards,
Simon



This looks like a platform or driver specific stuff ?


Ouch, I just saw the extra printf might have to be removed in a v2...

Anyway, except for that, I don't think it's platform or driver specific.
It's just a way to make the cmd 'reset' take arguments that map to enum
sysreset_t.


Cold vs. Warm reset is socfpga specific. The reset driver should
probably somehow register supported reset modes (warm/cold) with the
reset core code.


But it's a thing the UCLASS_SYSRESET already exposes. I haven't added
the enum values for that, I merely exposed them to the cmd "API". I
can't see anything socfpga specific about it.


Ah, then socfpga just maps to that "API" very well, nice. I wasn't aware
of it.

--
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Marek Vasut


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Re: [U-Boot] [PATCH v5 2/2] dlmalloc: fix malloc range at end of ram

[Simon Goldschmidt]

Tom,

Am 26.04.2019 um 13:00 schrieb Marek Vasut:

On 4/26/19 12:19 PM, Simon Goldschmidt wrote:

On Fri, Apr 26, 2019 at 11:56 AM Marek Vasut  wrote:


On 4/26/19 11:36 AM, Simon Goldschmidt wrote:

On Fri, Apr 26, 2019 at 11:32 AM Marek Vasut  wrote:


On 4/26/19 8:19 AM, Simon Goldschmidt wrote:

Marek Vasut  schrieb am Fr., 26. Apr. 2019, 00:22:


On 4/25/19 9:22 PM, Simon Goldschmidt wrote:

If the malloc range passed to mem_malloc_init() is at the end of address
range and 'start + size' overflows to 0, following allocations fail as
mem_malloc_end is zero (which looks like uninitialized).

Fix this by subtracting 1 of 'start + size' overflows to zero.

Signed-off-by: Simon Goldschmidt 


Since there's no way this fits without breaking smartweb, I'd rather 
drop this for now in order to get 1/2 accepted.


Regards,
Simon


---

Changes in v5:
- this patch was 1/2 in v4 but is now 2/2 as the 2nd patch of v4 has
   already been accepted
- rearrange the code to make it only 8 bytes plus in code size for arm
   (which fixes smartweb SPL overflowing)

  common/dlmalloc.c | 6 +-
  1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 6f12a18d54..38859ecbd4 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -601,8 +601,12 @@ void *sbrk(ptrdiff_t increment)
  void mem_malloc_init(ulong start, ulong size)
  {
   mem_malloc_start = start;
- mem_malloc_end = start + size;
   mem_malloc_brk = start;
+ mem_malloc_end = start + size;
+ if (size > mem_malloc_end) {
+ /* overflow: malloc area is at end of address range */
+ mem_malloc_end--;


Does this mean a memory wrap-around happened ?
I don't think decrementing malloc area size by 1 is a proper solution.
You can have it overflow by 2 and decrementing by 1 won't help.



No, not a real overflow. Instead, as I tried to described in the commit
message, mem_malloc_end gets 0 if the range is at the end of addr range,
e.g. malloc start is 0x and malloc size is 0x1. Subtracting 1
will be enough here. It reduces the available mall of aize, but I don't
think that should be a problem.


That's a wrap-around . What happens with your example if malloc_size is
0x10001 ? Hint: It fails ...


Yes it fails. But in contrast, that's an invalid configuration, while
my patch makes
a valid configuration work. I don't know if we want to fix all invalid
configurations.


Yes ? Should be easy, just clamp() size to (size, (BIT(32) - 1) -
mem_malloc_start) or similar for 64bit systems.


I'm not convinced we should. This range is normally generated using
something like:
SIZE=2048
START=RAM_END - SIZE


Normally ... on SoCFPGA . Other ARM32 platforms can have OCRAM mapped
somewhere in the middle of the address space. Take R-Car Gen2, which has
it at 0xe630 + 64k or something like that.

And, to make things worse, you cannot detect these overflows at compile
time, since the DRAM layout, which is passed to malloc init can come
from DT.

Thus, you might want to sanitize the input, properly.


I don't want to be overprotective here. I don't think there's much point
in fixing the out-of-ram-range check if it produces an overflow but not
fix it if it's in the middle of an address space.

Again, this patch simply fixes the case for something like this:
RAM_SIZE=0x1
RAM_START=0x
so RAM_END=0

We can use clamp as you suggested, but what would it be good for
if it only fixes an out-of-range heap if an overflow occurs?


It's better than nothing. Further refinements welcome.


You could as well enter a range without RAM, that would fail as well.


That info is available in gd , but I wonder whether this is the right
place to check for it.


Indeed, that would seem misplaced here.

Regards,
Simon




A different approach to fix my valid end-of-ram configuration would be to set
the end to "start + size - 1" and to change all the checks using it. But that
would probably lead to more code size problems in various SPL...

Regards,
Simon




I got this when experimenting with full heap in socfpga. Due to other
patches not being accepted, this is not an issue currebtly, but can easily
become one on the future.

Regrds,
Simon



+ }

   debug("using memory %#lx-%#lx for malloc()\n", mem_malloc_start,
 mem_malloc_end);




--
Best regards,
Marek Vasut






--
Best regards,
Marek Vasut



--
Best regards,
Marek Vasut





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[U-Boot] [PATCH 1/1] efi_selftest: remove redundant function efi_st_memcmp()

[Heinrich Schuchardt]

Function memcmp() is available in efi_freestanding.c. So we do not remove a
further implementation.

Replace all usages of efi_st_memcmp() by memcmp().

Signed-off-by: Heinrich Schuchardt 
---
 include/efi_selftest.h  | 11 ---
 lib/efi_selftest/efi_selftest_block_device.c|  6 +++---
 lib/efi_selftest/efi_selftest_config_table.c| 12 ++--
 lib/efi_selftest/efi_selftest_loaded_image.c|  5 ++---
 lib/efi_selftest/efi_selftest_loadimage.c   |  7 +++
 lib/efi_selftest/efi_selftest_manageprotocols.c |  8 
 lib/efi_selftest/efi_selftest_memory.c  |  4 ++--
 lib/efi_selftest/efi_selftest_snp.c |  7 +++
 lib/efi_selftest/efi_selftest_startimage_exit.c |  2 +-
 lib/efi_selftest/efi_selftest_util.c| 14 --
 lib/efi_selftest/efi_selftest_variables.c   | 10 +-
 11 files changed, 29 insertions(+), 57 deletions(-)

diff --git a/include/efi_selftest.h b/include/efi_selftest.h
index dd42e49023..eaee188de7 100644
--- a/include/efi_selftest.h
+++ b/include/efi_selftest.h
@@ -92,17 +92,6 @@ u16 *efi_st_translate_char(u16 code);
  */
 u16 *efi_st_translate_code(u16 code);

-/*
- * Compare memory.
- * We cannot use lib/string.c due to different CFLAGS values.
- *
- * @buf1:  first buffer
- * @buf2:  second buffer
- * @length:number of bytes to compare
- * @return:0 if both buffers contain the same bytes
- */
-int efi_st_memcmp(const void *buf1, const void *buf2, size_t length);
-
 /*
  * Compare an u16 string to a char string.
  *
diff --git a/lib/efi_selftest/efi_selftest_block_device.c 
b/lib/efi_selftest/efi_selftest_block_device.c
index 29ac0ce651..644c5ade21 100644
--- a/lib/efi_selftest/efi_selftest_block_device.c
+++ b/lib/efi_selftest/efi_selftest_block_device.c
@@ -337,7 +337,7 @@ static int execute(void)
}
if (len >= dp_size(dp_partition))
continue;
-   if (efi_st_memcmp(dp, dp_partition, len))
+   if (memcmp(dp, dp_partition, len))
continue;
handle_partition = handles[i];
break;
@@ -409,7 +409,7 @@ static int execute(void)
 (unsigned int)buf_size);
return EFI_ST_FAILURE;
}
-   if (efi_st_memcmp(buf, "ello world!", 11)) {
+   if (memcmp(buf, "ello world!", 11)) {
efi_st_error("Unexpected file content\n");
return EFI_ST_FAILURE;
}
@@ -480,7 +480,7 @@ static int execute(void)
 (unsigned int)buf_size);
return EFI_ST_FAILURE;
}
-   if (efi_st_memcmp(buf, "U-Boot", 7)) {
+   if (memcmp(buf, "U-Boot", 7)) {
efi_st_error("Unexpected file content %s\n", buf);
return EFI_ST_FAILURE;
}
diff --git a/lib/efi_selftest/efi_selftest_config_table.c 
b/lib/efi_selftest/efi_selftest_config_table.c
index 0bc5da6b0c..4467f492ac 100644
--- a/lib/efi_selftest/efi_selftest_config_table.c
+++ b/lib/efi_selftest/efi_selftest_config_table.c
@@ -153,8 +153,8 @@ static int execute(void)
}
table = NULL;
for (i = 0; i < sys_table->nr_tables; ++i) {
-   if (!efi_st_memcmp(_table->tables[i].guid, _guid,
-  sizeof(efi_guid_t)))
+   if (!memcmp(_table->tables[i].guid, _guid,
+   sizeof(efi_guid_t)))
table = sys_table->tables[i].table;
}
if (!table) {
@@ -192,8 +192,8 @@ static int execute(void)
table = NULL;
tabcnt = 0;
for (i = 0; i < sys_table->nr_tables; ++i) {
-   if (!efi_st_memcmp(_table->tables[i].guid, _guid,
-  sizeof(efi_guid_t))) {
+   if (!memcmp(_table->tables[i].guid, _guid,
+   sizeof(efi_guid_t))) {
table = sys_table->tables[i].table;
++tabcnt;
}
@@ -235,8 +235,8 @@ static int execute(void)
}
table = NULL;
for (i = 0; i < sys_table->nr_tables; ++i) {
-   if (!efi_st_memcmp(_table->tables[i].guid, _guid,
-  sizeof(efi_guid_t))) {
+   if (!memcmp(_table->tables[i].guid, _guid,
+   sizeof(efi_guid_t))) {
table = sys_table->tables[i].table;
}
}
diff --git a/lib/efi_selftest/efi_selftest_loaded_image.c 
b/lib/efi_selftest/efi_selftest_loaded_image.c
index ea2b380a77..5889ab1261 100644
--- a/lib/efi_selftest/efi_selftest_loaded_image.c
+++ b/lib/efi_selftest/efi_selftest_loaded_image.c
@@ -60,9 +60,8 @@ static int execute(void)
efi_st_printf("%u protocols installed on image handle\n",
  (unsigned int)protocol_buffer_count);
for (i = 0; i < protocol_buffer_count; ++i) {
-

[U-Boot] [PATCH 4/9] serial: sh: Add RZ/A1 support

[Marek Vasut]

Add support for RZ/A1 SoC specifics.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Nobuhiro Iwamatsu 
---
 drivers/serial/serial_sh.c | 3 +++
 drivers/serial/serial_sh.h | 3 ++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index e6fe5c7c67..8f52f9dce4 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -62,6 +62,9 @@ static void sh_serial_init_generic(struct uart_port *port)
sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
sci_in(port, SCFCR);
sci_out(port, SCFCR, 0);
+#if defined(CONFIG_RZA1)
+   sci_out(port, SCSPTR, 0x0003);
+#endif
 }
 
 static void
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 887dd19ff5..8aa80d4a37 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -195,7 +195,7 @@ struct uart_port {
 #  define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
 # endif
 # define SCSCR_INIT(port)  0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7269)
+#elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_RZA1)
 # define SCSPTR0 0xe8007020 /* 16 bit SCIF */
 # define SCSPTR1 0xe8007820 /* 16 bit SCIF */
 # define SCSPTR2 0xe8008020 /* 16 bit SCIF */
@@ -205,6 +205,7 @@ struct uart_port {
 # define SCSPTR6 0xe800a020 /* 16 bit SCIF */
 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */
 # define SCSCR_INIT(port)  0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+# define SCIF_ORER 0x0001  /* overrun error bit */
 #elif defined(CONFIG_CPU_SH7619)
 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
-- 
2.20.1

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[U-Boot] [PATCH 8/9] ARM: dts: renesas: Add RZ/A1 platform code

[Marek Vasut]

From: Chris Brandt 

Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC.
Distinguishing feature of this SoC is that it has up to
10 MiB of on-SoC static RAM (SRAM).

The DTs are imported from Linux 5.0.11, commit d5a2675b207d .

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/Kconfig  |   2 +-
 arch/arm/dts/r7s72100.dtsi| 705 ++
 arch/arm/mach-rmobile/Kconfig |   5 +
 arch/arm/mach-rmobile/Kconfig.rza1|  21 +
 arch/arm/mach-rmobile/cpu_info.c  |   8 +
 arch/arm/mach-rmobile/include/mach/rmobile.h  |   1 +
 include/dt-bindings/clock/r7s72100-clock.h| 112 +++
 .../dt-bindings/pinctrl/r7s72100-pinctrl.h|  18 +
 8 files changed, 871 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/r7s72100.dtsi
 create mode 100644 arch/arm/mach-rmobile/Kconfig.rza1
 create mode 100644 include/dt-bindings/clock/r7s72100-clock.h
 create mode 100644 include/dt-bindings/pinctrl/r7s72100-pinctrl.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49f01f1ff1..70a14eef48 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -785,7 +785,7 @@ config ARCH_QEMU
 
 config ARCH_RMOBILE
bool "Renesas ARM SoCs"
-   select BOARD_EARLY_INIT_F
+   select BOARD_EARLY_INIT_F if !RZA1
select DM
select DM_SERIAL
imply CMD_DM
diff --git a/arch/arm/dts/r7s72100.dtsi b/arch/arm/dts/r7s72100.dtsi
new file mode 100644
index 00..2211f88ede
--- /dev/null
+++ b/arch/arm/dts/r7s72100.dtsi
@@ -0,0 +1,705 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r7s72100 SoC
+ *
+ * Copyright (C) 2013-14 Renesas Solutions Corp.
+ * Copyright (C) 2014 Wolfram Sang, Sang Engineering 

+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r7s72100";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   aliases {
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   i2c3 = 
+   spi0 = 
+   spi1 = 
+   spi2 = 
+   spi3 = 
+   spi4 = 
+   };
+
+   /* Fixed factor clocks */
+   b_clk: b {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <_clocks R7S72100_CLK_PLL>;
+   clock-mult = <1>;
+   clock-div = <3>;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0>;
+   clock-frequency = <4>;
+   clocks = <_clocks R7S72100_CLK_I>;
+   next-level-cache = <>;
+   };
+   };
+
+   /* External clocks */
+   extal_clk: extal {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   /* If clk present, value must be set by board */
+   clock-frequency = <0>;
+   };
+
+   p0_clk: p0 {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <_clocks R7S72100_CLK_PLL>;
+   clock-mult = <1>;
+   clock-div = <12>;
+   };
+
+   p1_clk: p1 {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <_clocks R7S72100_CLK_PLL>;
+   clock-mult = <1>;
+   clock-div = <6>;
+   };
+
+   pmu {
+   compatible = "arm,cortex-a9-pmu";
+   interrupts-extended = < GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
+   };
+
+   rtc_x1_clk: rtc_x1 {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   /* If clk present, value must be set by board to 32678 */
+   clock-frequency = <0>;
+   };
+
+   rtc_x3_clk: rtc_x3 {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   /* If clk present, value must be set by board to 400 */
+   clock-frequency = <0>;
+   };
+
+   soc {
+   compatible = "simple-bus";
+   interrupt-parent = <>;
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   L2: cache-controller@3000 {
+   compatible = "arm,pl310-cache";
+   reg = <0x3000 0x1000>;
+   interrupts = ;
+   arm,early-bresp-disable;
+   arm,full-line-zero-disable;
+   cache-unified;
+   cache-level = <2>;
+   };
+
+   scif0: serial@e8007000 {
+   compatible = "renesas,scif-r7s72100", "renesas,scif";
+   

[U-Boot] [PATCH 7/9] spi: rpc: Add support for operation without clock framework

[Marek Vasut]

Add ifdeffery to allow operation without the clock framework
enabled. This is required on RZ/A1, as it does not have clock
driver yet.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Jagan Teki 
Cc: Nobuhiro Iwamatsu 
---
 drivers/spi/Kconfig   |  2 +-
 drivers/spi/renesas_rpc_spi.c | 12 
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index fb794adae7..9138425d40 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -173,7 +173,7 @@ config PL022_SPI
 
 config RENESAS_RPC_SPI
bool "Renesas RPC SPI driver"
-   depends on RCAR_GEN3
+   depends on RCAR_GEN3 || RZA1
imply SPI_FLASH_BAR
help
  Enable the Renesas RPC SPI driver, used to access SPI NOR flash
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index bec9095ff4..bb2e7748fe 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -409,27 +409,30 @@ static int rpc_spi_probe(struct udevice *dev)
 
priv->regs = plat->regs;
priv->extr = plat->extr;
-
+#if CONFIG_IS_ENABLED(CLK)
clk_enable(>clk);
-
+#endif
return 0;
 }
 
 static int rpc_spi_ofdata_to_platdata(struct udevice *bus)
 {
struct rpc_spi_platdata *plat = dev_get_platdata(bus);
-   struct rpc_spi_priv *priv = dev_get_priv(bus);
-   int ret;
 
plat->regs = dev_read_addr_index(bus, 0);
plat->extr = dev_read_addr_index(bus, 1);
 
+#if CONFIG_IS_ENABLED(CLK)
+   struct rpc_spi_priv *priv = dev_get_priv(bus);
+   int ret;
+
ret = clk_get_by_index(bus, 0, >clk);
if (ret < 0) {
printf("%s: Could not get clock for %s: %d\n",
   __func__, bus->name, ret);
return ret;
}
+#endif
 
plat->freq = dev_read_u32_default(bus, "spi-max-freq", 5000);
 
@@ -448,6 +451,7 @@ static const struct udevice_id rpc_spi_ids[] = {
{ .compatible = "renesas,rpc-r8a77965" },
{ .compatible = "renesas,rpc-r8a77970" },
{ .compatible = "renesas,rpc-r8a77995" },
+   { .compatible = "renesas,rpc-r7s72100" },
{ }
 };
 
-- 
2.20.1

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[U-Boot] [PATCH] usb: Convert CONFIG_USB_R8A66597_HCD to Kconfig

[Marek Vasut]

This converts the following to Kconfig:
   CONFIG_USB_R8A66597_HCD

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 drivers/usb/host/Kconfig | 16 
 scripts/config_whitelist.txt |  1 -
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 1c2212f547..4e72157e07 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -287,3 +287,19 @@ config USB_DWC2_BUFFER_SIZE
  because larger transactions could be split in smaller ones.
 
 endif # USB_DWC2
+
+config USB_R8A66597_HCD
+   bool "Renesas R8A66597 USB 2.0 host controller support"
+   select USB_HOST
+   ---help---
+ Enables support for the on-chip Renesas R8A66597 USB 2.0 controller,
+ present in various RZ and SH SoCs.
+
+if USB_R8A66597_HCD
+config RZA_USB
+   bool "Renesas RZ/A1 extras"
+   default y if RZA1
+   ---help---
+ Enables support for RZ/A1 SoC extras in the R8A66597 USB host driver.
+
+endif # USB_R8A66597_HCD
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index e48c40d34b..5a0cf7c4fc 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4534,7 +4534,6 @@ CONFIG_USB_OTG
 CONFIG_USB_OTG_BLACKLIST_HUB
 CONFIG_USB_PHY_TYPE
 CONFIG_USB_PXA25X_SMALL
-CONFIG_USB_R8A66597_HCD
 CONFIG_USB_SERIALNO
 CONFIG_USB_TI_CPPI_DMA
 CONFIG_USB_TTY
-- 
2.20.1

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[U-Boot] [PATCH 6/9] net: sh_eth: Add support for operation without clock framework

[Marek Vasut]

Add ifdeffery to allow operation without the clock framework
enabled. This is required on RZ/A1, as it does not have clock
driver yet.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Joe Hershberger 
Cc: Nobuhiro Iwamatsu 
---
 drivers/net/sh_eth.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index a2577e1e8f..8e54e7cc7a 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -806,9 +806,11 @@ static int sh_ether_probe(struct udevice *udev)
 
priv->iobase = pdata->iobase;
 
+#if CONFIG_IS_ENABLED(CLK)
ret = clk_get_by_index(udev, 0, >clk);
if (ret < 0)
return ret;
+#endif
 
ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, 
_args);
if (!ret) {
@@ -843,9 +845,11 @@ static int sh_ether_probe(struct udevice *udev)
eth->port_info[eth->port].iobase =
(void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
 
+#if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(>clk);
if (ret)
goto err_mdio_register;
+#endif
 
ret = sh_eth_phy_config(udev);
if (ret) {
@@ -856,7 +860,9 @@ static int sh_ether_probe(struct udevice *udev)
return 0;
 
 err_phy_config:
+#if CONFIG_IS_ENABLED(CLK)
clk_disable(>clk);
+#endif
 err_mdio_register:
mdio_free(mdiodev);
return ret;
@@ -868,7 +874,9 @@ static int sh_ether_remove(struct udevice *udev)
struct sh_eth_dev *eth = >shdev;
struct sh_eth_info *port_info = >port_info[eth->port];
 
+#if CONFIG_IS_ENABLED(CLK)
clk_disable(>clk);
+#endif
free(port_info->phydev);
mdio_unregister(priv->bus);
mdio_free(priv->bus);
@@ -917,6 +925,7 @@ int sh_ether_ofdata_to_platdata(struct udevice *dev)
 }
 
 static const struct udevice_id sh_ether_ids[] = {
+   { .compatible = "renesas,ether-r7s72100" },
{ .compatible = "renesas,ether-r8a7790" },
{ .compatible = "renesas,ether-r8a7791" },
{ .compatible = "renesas,ether-r8a7793" },
-- 
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[U-Boot] [PATCH 3/9] timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver

[Marek Vasut]

Add OSTM timer driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Nobuhiro Iwamatsu 
---
 drivers/timer/Kconfig  |  7 +++
 drivers/timer/Makefile |  1 +
 drivers/timer/ostm_timer.c | 92 ++
 3 files changed, 100 insertions(+)
 create mode 100644 drivers/timer/ostm_timer.c

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index df37a798bd..5f4bc6edb6 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -110,6 +110,13 @@ config MPC83XX_TIMER
  Select this to enable support for the timer found on
  devices based on the MPC83xx family of SoCs.
 
+config RENESAS_OSTM_TIMER
+   bool "Renesas RZ/A1 R7S72100 OSTM Timer"
+   depends on TIMER
+   help
+ Enables support for the Renesas OSTM Timer driver.
+ This timer is present on Renesas RZ/A1 R7S72100 SoCs.
+
 config X86_TSC_TIMER_EARLY_FREQ
int "x86 TSC timer frequency in MHz when used as the early timer"
depends on X86_TSC_TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index d0bf218b11..fa35bea6c5 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER)   += cadence-ttc.o
 obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
 obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
 obj-$(CONFIG_OMAP_TIMER)   += omap-timer.o
+obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
 obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
 obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
 obj-$(CONFIG_SANDBOX_TIMER)+= sandbox_timer.o
diff --git a/drivers/timer/ostm_timer.c b/drivers/timer/ostm_timer.c
new file mode 100644
index 00..f0e25093ca
--- /dev/null
+++ b/drivers/timer/ostm_timer.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas RZ/A1 R7S72100 OSTM Timer driver
+ *
+ * Copyright (C) 2019 Marek Vasut 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define OSTM_CMP   0x00
+#define OSTM_CNT   0x04
+#define OSTM_TE0x10
+#define OSTM_TS0x14
+#define OSTM_TT0x18
+#define OSTM_CTL   0x20
+#define OSTM_CTL_D BIT(1)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ostm_priv {
+   fdt_addr_t  regs;
+};
+
+static int ostm_get_count(struct udevice *dev, u64 *count)
+{
+   struct ostm_priv *priv = dev_get_priv(dev);
+
+   *count = timer_conv_64(readl(priv->regs + OSTM_CNT));
+
+   return 0;
+}
+
+static int ostm_probe(struct udevice *dev)
+{
+   struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+   struct ostm_priv *priv = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(CLK)
+   struct clk clk;
+   int ret;
+
+   ret = clk_get_by_index(dev, 0, );
+   if (ret)
+   return ret;
+
+   uc_priv->clock_rate = clk_get_rate();
+
+   clk_free();
+#else
+   uc_priv->clock_rate = CONFIG_SYS_CLK_FREQ / 2;
+#endif
+
+   readb(priv->regs + OSTM_CTL);
+   writeb(OSTM_CTL_D, priv->regs + OSTM_CTL);
+
+   setbits_8(priv->regs + OSTM_TT, BIT(0));
+   writel(0x, priv->regs + OSTM_CMP);
+   setbits_8(priv->regs + OSTM_TS, BIT(0));
+
+   return 0;
+}
+
+static int ostm_ofdata_to_platdata(struct udevice *dev)
+{
+   struct ostm_priv *priv = dev_get_priv(dev);
+
+   priv->regs = dev_read_addr(dev);
+
+   return 0;
+}
+
+static const struct timer_ops ostm_ops = {
+   .get_count  = ostm_get_count,
+};
+
+static const struct udevice_id ostm_ids[] = {
+   { .compatible = "renesas,ostm" },
+   {}
+};
+
+U_BOOT_DRIVER(ostm_timer) = {
+   .name   = "ostm-timer",
+   .id = UCLASS_TIMER,
+   .ops= _ops,
+   .probe  = ostm_probe,
+   .of_match   = ostm_ids,
+   .ofdata_to_platdata = ostm_ofdata_to_platdata,
+   .priv_auto_alloc_size = sizeof(struct ostm_priv),
+};
-- 
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[U-Boot] [PATCH 9/9] ARM: dts: renesas: Add RZ/A1 GR-Peach board

[Marek Vasut]

From: Chris Brandt 

Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach,
which is a cheap development platform with RZ/A1H SoC. The
DTs are imported from Linux 5.0.11, commit d5a2675b207d .

Currently supported are UART, ethernet and RPC SPI. The board
can be booted from RPC SPI by writing the u-boot.bin binary
to the beginning of the SPI NOR, e.g. using the "sf" command.
The board can also be booted via JTAG by setting text base to
0x2002, loading u-boot.bin there via JTAG and executing it
from that address.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/dts/Makefile |   3 +
 arch/arm/dts/r7s72100-gr-peach-u-boot.dts |  78 +
 arch/arm/dts/r7s72100-gr-peach.dts| 134 ++
 arch/arm/mach-rmobile/Kconfig.rza1|   7 ++
 board/renesas/grpeach/Kconfig |  12 ++
 board/renesas/grpeach/MAINTAINERS |   6 +
 board/renesas/grpeach/Makefile|   8 ++
 board/renesas/grpeach/grpeach.c   |  52 +
 board/renesas/grpeach/lowlevel_init.S | 107 +
 configs/grpeach_defconfig |  53 +
 include/configs/grpeach.h |  53 +
 11 files changed, 513 insertions(+)
 create mode 100644 arch/arm/dts/r7s72100-gr-peach-u-boot.dts
 create mode 100644 arch/arm/dts/r7s72100-gr-peach.dts
 create mode 100644 board/renesas/grpeach/Kconfig
 create mode 100644 board/renesas/grpeach/MAINTAINERS
 create mode 100644 board/renesas/grpeach/Makefile
 create mode 100644 board/renesas/grpeach/grpeach.c
 create mode 100644 board/renesas/grpeach/lowlevel_init.S
 create mode 100644 configs/grpeach_defconfig
 create mode 100644 include/configs/grpeach.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8e082f2840..a199f3f988 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -603,6 +603,9 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a77990-ebisu-u-boot.dtb \
r8a77995-draak-u-boot.dtb
 
+dtb-$(CONFIG_RZA1) += \
+   r7s72100-gr-peach-u-boot.dtb
+
 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
keystone-k2e-evm.dtb \
diff --git a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts 
b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
new file mode 100644
index 00..28247d19d7
--- /dev/null
+++ b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the GR Peach board
+ *
+ * Copyright (C) 2019 Marek Vasut 
+ */
+
+#include "r7s72100-gr-peach.dts"
+
+/ {
+   aliases {
+   spi0 = 
+   };
+
+   soc {
+   u-boot,dm-pre-reloc;
+   };
+
+   leds {
+   led1 {
+   label = "peach:bottom:red";
+   };
+
+   led-red {
+   label = "peach:tri:red";
+   gpios = < 13 GPIO_ACTIVE_HIGH>;
+   };
+
+   led-green {
+   label = "peach:tri:green";
+   gpios = < 14 GPIO_ACTIVE_HIGH>;
+   };
+
+   led-blue {
+   label = "peach:tri:blue";
+   gpios = < 15 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   rpc: rpc@0xee20 {
+   compatible = "renesas,rpc-r7s72100", "renesas,rpc";
+   reg = <0x3fefa000 0x100>, <0x1800 0x0800>;
+   bank-width = <2>;
+   num-cs = <1>;
+   status = "okay";
+   spi-max-frequency = <5000>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   flash0: spi-flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "jedec,spi-nor";
+   spi-max-frequency = <5000>;
+   spi-tx-bus-width = <1>;
+   spi-rx-bus-width = <1>;
+   reg = <0>;
+   status = "okay";
+   };
+   };
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   clock = <>; /* ToDo: Replace by DM clock driver */
+};
+
+_pins {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/r7s72100-gr-peach.dts 
b/arch/arm/dts/r7s72100-gr-peach.dts
new file mode 100644
index 00..fe1a4aa4d7
--- /dev/null
+++ b/arch/arm/dts/r7s72100-gr-peach.dts
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the GR-Peach board
+ *
+ * Copyright (C) 2017 Jacopo Mondi 
+ * Copyright (C) 2016 Renesas Electronics
+ */
+
+/dts-v1/;
+#include "r7s72100.dtsi"
+#include 
+#include 
+
+/ {
+   model = "GR-Peach";
+   compatible = "renesas,gr-peach", "renesas,r7s72100";
+
+   aliases {
+   serial0 = 
+   };
+
+   

[U-Boot] [PATCH 5/9] net: sh_eth: Add RZ/A1 support

[Marek Vasut]

Add support for RZ/A1 SoC specifics.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Joe Hershberger 
Cc: Nobuhiro Iwamatsu 
---
 drivers/net/sh_eth.h | 56 
 1 file changed, 56 insertions(+)

diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index d8b4bda3ef..e1bbd4913f 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -228,6 +228,60 @@ static const u16 
sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
[RMII_MII] =  0x0790,
 };
 
+static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
+   [EDSR]  = 0x,
+   [EDMR]  = 0x0400,
+   [EDTRR] = 0x0408,
+   [EDRRR] = 0x0410,
+   [EESR]  = 0x0428,
+   [EESIPR]= 0x0430,
+   [TDLAR] = 0x0010,
+   [TDFAR] = 0x0014,
+   [TDFXR] = 0x0018,
+   [TDFFR] = 0x001c,
+   [RDLAR] = 0x0030,
+   [RDFAR] = 0x0034,
+   [RDFXR] = 0x0038,
+   [RDFFR] = 0x003c,
+   [TRSCER]= 0x0438,
+   [RMFCR] = 0x0440,
+   [TFTR]  = 0x0448,
+   [FDR]   = 0x0450,
+   [RMCR]  = 0x0458,
+   [RPADIR]= 0x0460,
+   [FCFTR] = 0x0468,
+   [CSMR] = 0x04E4,
+
+   [ECMR]  = 0x0500,
+   [ECSR]  = 0x0510,
+   [ECSIPR]= 0x0518,
+   [PIR]   = 0x0520,
+   [PSR]   = 0x0528,
+   [PIPR]  = 0x052c,
+   [RFLR]  = 0x0508,
+   [APR]   = 0x0554,
+   [MPR]   = 0x0558,
+   [PFTCR] = 0x055c,
+   [PFRCR] = 0x0560,
+   [TPAUSER]   = 0x0564,
+   [GECMR] = 0x05b0,
+   [BCULR] = 0x05b4,
+   [MAHR]  = 0x05c0,
+   [MALR]  = 0x05c8,
+   [TROCR] = 0x0700,
+   [CDCR]  = 0x0708,
+   [LCCR]  = 0x0710,
+   [CEFCR] = 0x0740,
+   [FRECR] = 0x0748,
+   [TSFRCR]= 0x0750,
+   [TLFRCR]= 0x0758,
+   [RFCR]  = 0x0760,
+   [CERCR] = 0x0768,
+   [CEECR] = 0x0770,
+   [MAFCR] = 0x0778,
+   [RMII_MII] =  0x0790,
+};
+
 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
[ECMR]  = 0x0100,
[RFLR]  = 0x0108,
@@ -603,6 +657,8 @@ static inline unsigned long sh_eth_reg_addr(struct 
sh_eth_info *port,
const u16 *reg_offset = sh_eth_offset_gigabit;
 #elif defined(SH_ETH_TYPE_ETHER)
const u16 *reg_offset = sh_eth_offset_fast_sh4;
+#elif defined(SH_ETH_TYPE_RZ)
+   const u16 *reg_offset = sh_eth_offset_rz;
 #else
 #error
 #endif
-- 
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[U-Boot] [PATCH 1/9] gpio: renesas: Add RZ/A1 R7S72100 GPIO driver

[Marek Vasut]

Add GPIO driver for RZ/A1 SoC. The IP is very different from the
R-Car Gen2/Gen3 one already present in the tree, hence a custom
driver.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Nobuhiro Iwamatsu 
---
 drivers/gpio/Kconfig |   6 ++
 drivers/gpio/Makefile|   1 +
 drivers/gpio/gpio-rza1.c | 134 +++
 3 files changed, 141 insertions(+)
 create mode 100644 drivers/gpio/gpio-rza1.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b3e4ecc50e..4e2095dcd6 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -169,6 +169,12 @@ config RCAR_GPIO
help
  This driver supports the GPIO banks on Renesas RCar SoCs.
 
+config RZA1_GPIO
+   bool "Renesas RZ/A1 GPIO driver"
+   depends on DM_GPIO && RZA1
+   help
+ This driver supports the GPIO banks on Renesas RZ/A1 R7S72100 SoCs.
+
 config ROCKCHIP_GPIO
bool "Rockchip GPIO driver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 3be325044f..7337153e0e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PCA953X) += pca953x.o
 obj-$(CONFIG_PCA9698)  += pca9698.o
 obj-$(CONFIG_ROCKCHIP_GPIO)+= rk_gpio.o
 obj-$(CONFIG_RCAR_GPIO)+= gpio-rcar.o
+obj-$(CONFIG_RZA1_GPIO)+= gpio-rza1.o
 obj-$(CONFIG_S5P)  += s5p_gpio.o
 obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o
 obj-$(CONFIG_SPEAR_GPIO)   += spear_gpio.o
diff --git a/drivers/gpio/gpio-rza1.c b/drivers/gpio/gpio-rza1.c
new file mode 100644
index 00..ce2453e2ba
--- /dev/null
+++ b/drivers/gpio/gpio-rza1.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marek Vasut 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define P(bank)(0x + (bank) * 4)
+#define PSR(bank)  (0x0100 + (bank) * 4)
+#define PPR(bank)  (0x0200 + (bank) * 4)
+#define PM(bank)   (0x0300 + (bank) * 4)
+#define PMC(bank)  (0x0400 + (bank) * 4)
+#define PFC(bank)  (0x0500 + (bank) * 4)
+#define PFCE(bank) (0x0600 + (bank) * 4)
+#define PNOT(bank) (0x0700 + (bank) * 4)
+#define PMSR(bank) (0x0800 + (bank) * 4)
+#define PMCSR(bank)(0x0900 + (bank) * 4)
+#define PFCAE(bank)(0x0A00 + (bank) * 4)
+#define PIBC(bank) (0x4000 + (bank) * 4)
+#define PBDC(bank) (0x4100 + (bank) * 4)
+#define PIPC(bank) (0x4200 + (bank) * 4)
+
+#define RZA1_MAX_GPIO_PER_BANK 16
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct r7s72100_gpio_priv {
+   void __iomem*regs;
+   int bank;
+};
+
+static int r7s72100_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+   struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
+
+   return !!(readw(priv->regs + PPR(priv->bank)) & BIT(offset));
+}
+
+static int r7s72100_gpio_set_value(struct udevice *dev, unsigned line,
+  int value)
+{
+   struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
+
+   writel(BIT(line + 16) | (value ? BIT(line) : 0),
+  priv->regs + PSR(priv->bank));
+
+   return 0;
+}
+
+static void r7s72100_gpio_set_direction(struct udevice *dev, unsigned line,
+   bool output)
+{
+   struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
+
+   writel(BIT(line + 16), priv->regs + PMCSR(priv->bank));
+   writel(BIT(line + 16) | (output ? 0 : BIT(line)),
+  priv->regs + PMSR(priv->bank));
+
+   clrsetbits_le16(priv->regs + PIBC(priv->bank), BIT(line),
+   output ? 0 : BIT(line));
+}
+
+static int r7s72100_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+   r7s72100_gpio_set_direction(dev, offset, false);
+   return 0;
+}
+
+static int r7s72100_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+   /* write GPIO value to output before selecting output mode of pin */
+   r7s72100_gpio_set_value(dev, offset, value);
+   r7s72100_gpio_set_direction(dev, offset, true);
+
+   return 0;
+}
+
+static int r7s72100_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+   struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
+
+   if (readw(priv->regs + PM(priv->bank)) & BIT(offset))
+   return GPIOF_INPUT;
+   else
+   return GPIOF_OUTPUT;
+}
+
+static const struct dm_gpio_ops r7s72100_gpio_ops = {
+   .direction_input= r7s72100_gpio_direction_input,
+   .direction_output   = r7s72100_gpio_direction_output,
+   .get_value  = r7s72100_gpio_get_value,
+   .set_value  = r7s72100_gpio_set_value,
+   .get_function   = r7s72100_gpio_get_function,
+};
+
+static int 

[U-Boot] [PATCH 2/9] pinctrl: renesas: Add RZ/A1 R7S72100 pin control driver

[Marek Vasut]

Add pin control driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Nobuhiro Iwamatsu 
---
 drivers/pinctrl/renesas/Kconfig|  12 ++
 drivers/pinctrl/renesas/Makefile   |   1 +
 drivers/pinctrl/renesas/pfc-r7s72100.c | 146 +
 3 files changed, 159 insertions(+)
 create mode 100644 drivers/pinctrl/renesas/pfc-r7s72100.c

diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 152414ce31..0ffd7fcfd4 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -3,6 +3,7 @@ if ARCH_RMOBILE
 config PINCTRL_PFC
bool "Renesas pin control drivers"
depends on DM && ARCH_RMOBILE
+   default n if CPU_RZA1
help
  Enable support for clock present on Renesas RCar SoCs.
 
@@ -116,4 +117,15 @@ config PINCTRL_PFC_R8A77995
  the GPIO definitions and pin control functions for each available
  multiplex function.
 
+config PINCTRL_PFC_R7S72100
+   bool "Renesas RZ/A1 R7S72100 pin control driver"
+   depends on CPU_RZA1
+   default y if CPU_RZA1
+   help
+ Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
 endif
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 596b0023a3..e8703f681e 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
+obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
diff --git a/drivers/pinctrl/renesas/pfc-r7s72100.c 
b/drivers/pinctrl/renesas/pfc-r7s72100.c
new file mode 100644
index 00..7e4530d684
--- /dev/null
+++ b/drivers/pinctrl/renesas/pfc-r7s72100.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * R7S72100 processor support
+ *
+ * Copyright (C) 2019 Marek Vasut 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define P(bank)(0x + (bank) * 4)
+#define PSR(bank)  (0x0100 + (bank) * 4)
+#define PPR(bank)  (0x0200 + (bank) * 4)
+#define PM(bank)   (0x0300 + (bank) * 4)
+#define PMC(bank)  (0x0400 + (bank) * 4)
+#define PFC(bank)  (0x0500 + (bank) * 4)
+#define PFCE(bank) (0x0600 + (bank) * 4)
+#define PNOT(bank) (0x0700 + (bank) * 4)
+#define PMSR(bank) (0x0800 + (bank) * 4)
+#define PMCSR(bank)(0x0900 + (bank) * 4)
+#define PFCAE(bank)(0x0A00 + (bank) * 4)
+#define PIBC(bank) (0x4000 + (bank) * 4)
+#define PBDC(bank) (0x4100 + (bank) * 4)
+#define PIPC(bank) (0x4200 + (bank) * 4)
+
+#define RZA1_PINS_PER_PORT 16
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct r7s72100_pfc_platdata {
+   void __iomem*base;
+};
+
+static void r7s72100_pfc_set_function(struct udevice *dev, u16 bank, u16 line,
+ u16 func, u16 inbuf, u16 bidir)
+{
+   struct r7s72100_pfc_platdata *plat = dev_get_platdata(dev);
+
+   clrsetbits_le16(plat->base + PFCAE(bank), BIT(line),
+   (func & BIT(2)) ? BIT(line) : 0);
+   clrsetbits_le16(plat->base + PFCE(bank), BIT(line),
+   (func & BIT(1)) ? BIT(line) : 0);
+   clrsetbits_le16(plat->base + PFC(bank), BIT(line),
+   (func & BIT(0)) ? BIT(line) : 0);
+
+   clrsetbits_le16(plat->base + PIBC(bank), BIT(line),
+   inbuf ? BIT(line) : 0);
+   clrsetbits_le16(plat->base + PBDC(bank), BIT(line),
+   bidir ? BIT(line) : 0);
+
+   setbits_le32(plat->base + PMCSR(bank), BIT(line + 16) | BIT(line));
+
+   setbits_le16(plat->base + PIPC(bank), BIT(line));
+}
+
+static int r7s72100_pfc_set_state(struct udevice *dev, struct udevice *config)
+{
+   const void *blob = gd->fdt_blob;
+   int node = dev_of_offset(config);
+   u32 cells[32];
+   u16 bank, line, func;
+   int i, count, bidir;
+
+   count = fdtdec_get_int_array_count(blob, node, "pinmux",
+  cells, ARRAY_SIZE(cells));
+   if (count < 0) {
+   printf("%s: bad pinmux array %d\n", __func__, count);
+   return -EINVAL;
+   }
+
+   if (count > ARRAY_SIZE(cells)) {
+   printf("%s: unsupported pinmux array count %d\n",
+  __func__, count);
+   return -EINVAL;
+   }
+
+   for (i = 0 ; i < count; i++) {
+  

[U-Boot] [PATCH 5/5] sh: 7785: Remove CPU support

[Marek Vasut]

There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Nobuhiro Iwamatsu 
Cc: Vladimir Zapolskiy 
Cc: Yoshihiro Shimoda 
---
 arch/sh/include/asm/cpu_sh4.h|   2 -
 arch/sh/include/asm/cpu_sh7785.h | 119 ---
 doc/README.sh|   1 -
 drivers/serial/serial_sh.c   |   1 -
 drivers/serial/serial_sh.h   |   6 +-
 scripts/config_whitelist.txt |   1 -
 6 files changed, 1 insertion(+), 129 deletions(-)
 delete mode 100644 arch/sh/include/asm/cpu_sh7785.h

diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h
index 977b648dd4..5fc9c962d8 100644
--- a/arch/sh/include/asm/cpu_sh4.h
+++ b/arch/sh/include/asm/cpu_sh4.h
@@ -42,8 +42,6 @@
 # include 
 #elif defined (CONFIG_CPU_SH7780)
 # include 
-#elif defined (CONFIG_CPU_SH7785)
-# include 
 #else
 # error "Unknown SH4 variant"
 #endif
diff --git a/arch/sh/include/asm/cpu_sh7785.h b/arch/sh/include/asm/cpu_sh7785.h
deleted file mode 100644
index b0388957f9..00
--- a/arch/sh/include/asm/cpu_sh7785.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-#ifndef_ASM_CPU_SH7785_H_
-#define_ASM_CPU_SH7785_H_
-
-/*
- * Copyright (c) 2007,2008 Nobuhiro Iwamatsu 
- * Copyright (c) 2008 Yusuke Goda 
- * Copyright (c) 2008 Yoshihiro Shimoda 
- */
-
-#defineCACHE_OC_NUM_WAYS   1
-#defineCCR_CACHE_INIT  0x090b
-
-/* Exceptions  */
-#defineTRA 0xFF20
-#defineEXPEVT  0xFF24
-#defineINTEVT  0xFF28
-
-/* Cache Controller */
-#defineCCR 0xFF1C
-#defineQACR0   0xFF38
-#defineQACR1   0xFF3C
-#defineRAMCR   0xFF74
-
-/* Watchdog Timer and Reset */
-#defineWTCNT   WDTCNT
-#defineWDTST   0xFFCC
-#defineWDTCSR  0xFFCC0004
-#defineWDTBST  0xFFCC0008
-#defineWDTCNT  0xFFCC0010
-#defineWDTBCNT 0xFFCC0018
-
-/* Timer Unit */
-#define TMU_BASE   0xFFD8
-
-/* Serial CommunicationInterface with FIFO */
-#defineSCIF1_BASE  0xffeb
-
-/* LBSC */
-#define MMSELR 0xfc400020
-#define LBSC_BASE  0xff80
-#define BCR(LBSC_BASE + 0x1000)
-#define CS0BCR (LBSC_BASE + 0x2000)
-#define CS1BCR (LBSC_BASE + 0x2010)
-#define CS2BCR (LBSC_BASE + 0x2020)
-#define CS3BCR (LBSC_BASE + 0x2030)
-#define CS4BCR (LBSC_BASE + 0x2040)
-#define CS5BCR (LBSC_BASE + 0x2050)
-#define CS6BCR (LBSC_BASE + 0x2060)
-#define CS0WCR (LBSC_BASE + 0x2008)
-#define CS1WCR (LBSC_BASE + 0x2018)
-#define CS2WCR (LBSC_BASE + 0x2028)
-#define CS3WCR (LBSC_BASE + 0x2038)
-#define CS4WCR (LBSC_BASE + 0x2048)
-#define CS5WCR (LBSC_BASE + 0x2058)
-#define CS6WCR (LBSC_BASE + 0x2068)
-#define CS5PCR (LBSC_BASE + 0x2070)
-#define CS6PCR (LBSC_BASE + 0x2080)
-
-/* PCI Controller */
-#defineSH7780_PCIECR   0xFE08
-#defineSH7780_PCIVID   0xFE04
-#defineSH7780_PCIDID   0xFE040002
-#defineSH7780_PCICMD   0xFE040004
-#defineSH7780_PCISTATUS0xFE040006
-#defineSH7780_PCIRID   0xFE040008
-#defineSH7780_PCIPIF   0xFE040009
-#defineSH7780_PCISUB   0xFE04000A
-#defineSH7780_PCIBCC   0xFE04000B
-#defineSH7780_PCICLS   0xFE04000C
-#defineSH7780_PCILTM   0xFE04000D
-#defineSH7780_PCIHDR   0xFE04000E
-#defineSH7780_PCIBIST  0xFE04000F
-#defineSH7780_PCIIBAR  0xFE040010
-#defineSH7780_PCIMBAR0 0xFE040014
-#defineSH7780_PCIMBAR1 0xFE040018
-#defineSH7780_PCISVID  0xFE04002C
-#defineSH7780_PCISID   0xFE04002E
-#defineSH7780_PCICP0xFE040034
-#defineSH7780_PCIINTLINE   0xFE04003C
-#defineSH7780_PCIINTPIN0xFE04003D
-#defineSH7780_PCIMINGNT0xFE04003E
-#defineSH7780_PCIMAXLAT0xFE04003F
-#defineSH7780_PCICID   0xFE040040
-#defineSH7780_PCINIP   0xFE040041
-#defineSH7780_PCIPMC   0xFE040042
-#defineSH7780_PCIPMCSR 0xFE040044
-#defineSH7780_PCIPMCSRBSE  0xFE040046
-#defineSH7780_PCI_CDD  0xFE040047
-#defineSH7780_PCICR0xFE040100
-#defineSH7780_PCILSR0  0xFE040104
-#defineSH7780_PCILSR1  0xFE040108
-#defineSH7780_PCILAR0  0xFE04010C
-#defineSH7780_PCILAR1  0xFE040110
-#defineSH7780_PCIIR0xFE040114
-#defineSH7780_PCIIMR   0xFE040118
-#defineSH7780_PCIAIR   0xFE04011C
-#define

[U-Boot] [PATCH 4/5] sh: sh7785lcr: Remove the board

[Marek Vasut]

Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Nobuhiro Iwamatsu 
Cc: Vladimir Zapolskiy 
Cc: Yoshihiro Shimoda 
---
 arch/sh/Kconfig  |   5 -
 board/renesas/sh7785lcr/Kconfig  |  12 -
 board/renesas/sh7785lcr/MAINTAINERS  |   7 -
 board/renesas/sh7785lcr/Makefile |   7 -
 board/renesas/sh7785lcr/README.sh7785lcr | 123 
 board/renesas/sh7785lcr/lowlevel_init.S  | 361 ---
 board/renesas/sh7785lcr/rtl8169.h|  43 ---
 board/renesas/sh7785lcr/rtl8169_mac.c| 330 -
 board/renesas/sh7785lcr/selfcheck.c  | 150 --
 board/renesas/sh7785lcr/sh7785lcr.c  |  63 
 configs/sh7785lcr_32bit_defconfig|  40 ---
 configs/sh7785lcr_defconfig  |  39 ---
 include/configs/sh7785lcr.h  | 128 
 13 files changed, 1308 deletions(-)
 delete mode 100644 board/renesas/sh7785lcr/Kconfig
 delete mode 100644 board/renesas/sh7785lcr/MAINTAINERS
 delete mode 100644 board/renesas/sh7785lcr/Makefile
 delete mode 100644 board/renesas/sh7785lcr/README.sh7785lcr
 delete mode 100644 board/renesas/sh7785lcr/lowlevel_init.S
 delete mode 100644 board/renesas/sh7785lcr/rtl8169.h
 delete mode 100644 board/renesas/sh7785lcr/rtl8169_mac.c
 delete mode 100644 board/renesas/sh7785lcr/selfcheck.c
 delete mode 100644 board/renesas/sh7785lcr/sh7785lcr.c
 delete mode 100644 configs/sh7785lcr_32bit_defconfig
 delete mode 100644 configs/sh7785lcr_defconfig
 delete mode 100644 include/configs/sh7785lcr.h

diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index ff7932bacb..a5772da87a 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -107,10 +107,6 @@ config TARGET_SH7763RDP
bool "SH7763RDP"
select CPU_SH4
 
-config TARGET_SH7785LCR
-   bool "SH7785LCR"
-   select CPU_SH4A
-
 endchoice
 
 config SYS_ARCH
@@ -141,7 +137,6 @@ source "board/renesas/sh7752evb/Kconfig"
 source "board/renesas/sh7753evb/Kconfig"
 source "board/renesas/sh7757lcr/Kconfig"
 source "board/renesas/sh7763rdp/Kconfig"
-source "board/renesas/sh7785lcr/Kconfig"
 source "board/shmin/Kconfig"
 
 endmenu
diff --git a/board/renesas/sh7785lcr/Kconfig b/board/renesas/sh7785lcr/Kconfig
deleted file mode 100644
index e204c76ef5..00
--- a/board/renesas/sh7785lcr/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_SH7785LCR
-
-config SYS_BOARD
-   default "sh7785lcr"
-
-config SYS_VENDOR
-   default "renesas"
-
-config SYS_CONFIG_NAME
-   default "sh7785lcr"
-
-endif
diff --git a/board/renesas/sh7785lcr/MAINTAINERS 
b/board/renesas/sh7785lcr/MAINTAINERS
deleted file mode 100644
index 17578e036a..00
--- a/board/renesas/sh7785lcr/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-SH7785LCR BOARD
-#M:-
-S: Maintained
-F: board/renesas/sh7785lcr/
-F: include/configs/sh7785lcr.h
-F: configs/sh7785lcr_defconfig
-F: configs/sh7785lcr_32bit_defconfig
diff --git a/board/renesas/sh7785lcr/Makefile b/board/renesas/sh7785lcr/Makefile
deleted file mode 100644
index ba00657d7e..00
--- a/board/renesas/sh7785lcr/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2008  Yoshihiro Shimoda 
-#
-
-obj-y  := sh7785lcr.o selfcheck.o rtl8169_mac.o
-extra-y+= lowlevel_init.o
diff --git a/board/renesas/sh7785lcr/README.sh7785lcr 
b/board/renesas/sh7785lcr/README.sh7785lcr
deleted file mode 100644
index 56455fc162..00
--- a/board/renesas/sh7785lcr/README.sh7785lcr
+++ /dev/null
@@ -1,123 +0,0 @@
-
-Renesas Technology R0P7785LC0011RL board
-
-
-This board specification:
-=
-
-The R0P7785LC0011RL(board config name:sh7785lcr) has the following device:
-
- - SH7785 (SH-4A)
- - DDR2-SDRAM 512MB
- - NOR Flash 64MB
- - 2D Graphic controller
- - SATA controller
- - Ethernet controller
- - USB host/peripheral controller
- - SD controller
- - I2C controller
- - RTC
-
-This board has 2 physical memory maps. It can be changed with DIP switch(S2-5).
-
- phys address  | S2-5 = OFF| S2-5 = ON
- ---+---+---
- 0x - 0x03ff(CS0)  | NOR Flash | NOR Flash
- 0x0400 - 0x05ff(CS1)  | PLD   | PLD
- 0x0600 - 0x07ff(CS1)  | reserved  | I2C
- 0x0800 - 0x0bff(CS2)  | USB   | DDR SDRAM
- 0x0c00 - 0x0fff(CS3)  | SD| DDR SDRAM
- 0x1000 - 0x13ff(CS4)  | SM107 | SM107
- 0x1400 - 0x17ff(CS5)  | I2C   | USB
- 0x1800 - 0x1bff(CS6)  | reserved  | SD
- 0x4000 - 0x5fff   | DDR SDRAM | (cannot use)
-
-
-configuration for This board:
-=
-
-You can choose configuration as follows:
-
- - make sh7785lcr_config
- - make 

[U-Boot] [PATCH 2/5] sh: ecovec: Remove the board

[Marek Vasut]

Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Nobuhiro Iwamatsu 
Cc: Vladimir Zapolskiy 
Cc: Yoshihiro Shimoda 
---
 arch/sh/Kconfig  |   5 -
 board/renesas/ecovec/Kconfig |  12 --
 board/renesas/ecovec/MAINTAINERS |   7 -
 board/renesas/ecovec/Makefile|   8 --
 board/renesas/ecovec/ecovec.c|  98 --
 board/renesas/ecovec/lowlevel_init.S | 196 ---
 configs/ecovec_defconfig |  40 --
 include/configs/ecovec.h | 133 --
 scripts/config_whitelist.txt |   1 -
 9 files changed, 500 deletions(-)
 delete mode 100644 board/renesas/ecovec/Kconfig
 delete mode 100644 board/renesas/ecovec/MAINTAINERS
 delete mode 100644 board/renesas/ecovec/Makefile
 delete mode 100644 board/renesas/ecovec/ecovec.c
 delete mode 100644 board/renesas/ecovec/lowlevel_init.S
 delete mode 100644 configs/ecovec_defconfig
 delete mode 100644 include/configs/ecovec.h

diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index d20761e66c..ff7932bacb 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -75,10 +75,6 @@ config TARGET_AP325RXA
bool "Renesas AP-325RXA"
select CPU_SH4
 
-config TARGET_ECOVEC
-   bool "EcoVec"
-   select CPU_SH4A
-
 config TARGET_MIGOR
bool "Migo-R"
select CPU_SH4
@@ -135,7 +131,6 @@ source "board/ms7722se/Kconfig"
 source "board/ms7750se/Kconfig"
 source "board/renesas/MigoR/Kconfig"
 source "board/renesas/ap325rxa/Kconfig"
-source "board/renesas/ecovec/Kconfig"
 source "board/renesas/r0p7734/Kconfig"
 source "board/renesas/r2dplus/Kconfig"
 source "board/renesas/r7780mp/Kconfig"
diff --git a/board/renesas/ecovec/Kconfig b/board/renesas/ecovec/Kconfig
deleted file mode 100644
index 08cde83356..00
--- a/board/renesas/ecovec/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ECOVEC
-
-config SYS_BOARD
-   default "ecovec"
-
-config SYS_VENDOR
-   default "renesas"
-
-config SYS_CONFIG_NAME
-   default "ecovec"
-
-endif
diff --git a/board/renesas/ecovec/MAINTAINERS b/board/renesas/ecovec/MAINTAINERS
deleted file mode 100644
index 439b528de9..00
--- a/board/renesas/ecovec/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-ECOVEC BOARD
-M: Nobuhiro Iwamatsu 
-M: Nobuhiro Iwamatsu 
-S: Maintained
-F: board/renesas/ecovec/
-F: include/configs/ecovec.h
-F: configs/ecovec_defconfig
diff --git a/board/renesas/ecovec/Makefile b/board/renesas/ecovec/Makefile
deleted file mode 100644
index aae3f70813..00
--- a/board/renesas/ecovec/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Nobuhiro Iwamatsu 
-# Copyright (C) 2011 Nobuhiro Iwamatsu 
-#
-
-obj-y := ecovec.o
-extra-y += lowlevel_init.o
diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c
deleted file mode 100644
index 6b6c5dc559..00
--- a/board/renesas/ecovec/ecovec.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2009, 2011 Renesas Solutions Corp.
- * Copyright (C) 2009 Kuninori Morimoto 
- * Copyright (C) 2011 Nobuhiro Iwamatsu 
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-/* USB power management register */
-#define UPONCR0 0xA40501D4
-
-int checkboard(void)
-{
-   puts("BOARD: ecovec\n");
-   return 0;
-}
-
-static void debug_led(u8 led)
-{
-   /* PDGR[0-4] is debug LED */
-   outb((inb(PGDR) & ~0x0F) | (led & 0x0F), PGDR);
-}
-
-int board_late_init(void)
-{
-   u8 mac[6];
-   char env_mac[18];
-
-   udelay(1000);
-
-   /* SH-Eth (PLCR, PNCR, PXCR, PSELx )*/
-   outw(inw(PLCR) & ~0xFFF0, PLCR);
-   outw(inw(PNCR) & ~0x000F, PNCR);
-   outw(inw(PXCR) & ~0x0FC0, PXCR);
-   outw((inw(PSELB) & ~0x030F) | 0x020A, PSELB);
-   outw((inw(PSELC) & ~0x0307) | 0x0207, PSELC);
-   outw((inw(PSELE) & ~0x00c0) | 0x0080, PSELE);
-
-   debug_led(1 << 3);
-
-   outl(inl(MSTPCR2) & ~0x1000, MSTPCR2);
-
-   i2c_set_bus_num(1); /* Use I2C 1 */
-
-   /* Read MAC address */
-   i2c_read(0x50, 0x10, 0, mac, 6);
-
-   /* Set MAC address */
-   sprintf(env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
-   mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-   env_set("ethaddr", env_mac);
-
-   debug_led(0x0F);
-
-   return 0;
-}
-
-int board_init(void)
-{
-
-   /* LED (PTG) */
-   outw((inw(PGCR) & ~0xFF) | 0x55, PGCR);
-   outw((inw(HIZCRA) & ~0x02), HIZCRA);
-
-   debug_led(1 << 0);
-
-   /* SCIF0 (PTF, PTM) */
-   outw(inw(PFCR) & ~0x30, PFCR);
-   outw(inw(PMCR) & ~0x0C, PMCR);
-   outw((inw(PSELA) & ~0x40) | 0x40, PSELA);
-
-   debug_led(1 << 1);
-
-   /* RMII (PTA) */
-   outw((inw(PACR) & ~0x0C) | 0x04, PACR);
-   outb((inb(PADR) & ~0x02) | 

[U-Boot] [PATCH 3/5] sh: 7724: Remove CPU support

[Marek Vasut]

There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Nobuhiro Iwamatsu 
Cc: Vladimir Zapolskiy 
Cc: Yoshihiro Shimoda 
---
 arch/sh/include/asm/cpu_sh4.h|   2 -
 arch/sh/include/asm/cpu_sh7724.h | 209 ---
 drivers/net/sh_eth.c |   2 +-
 drivers/net/sh_eth.h |   3 -
 drivers/serial/serial_sh.h   |  15 +--
 scripts/config_whitelist.txt |   1 -
 6 files changed, 4 insertions(+), 228 deletions(-)
 delete mode 100644 arch/sh/include/asm/cpu_sh7724.h

diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h
index b558d6935c..977b648dd4 100644
--- a/arch/sh/include/asm/cpu_sh4.h
+++ b/arch/sh/include/asm/cpu_sh4.h
@@ -30,8 +30,6 @@
 # include 
 #elif defined (CONFIG_CPU_SH7723)
 # include 
-#elif defined (CONFIG_CPU_SH7724)
-# include 
 #elif defined (CONFIG_CPU_SH7734)
 # include 
 #elif defined (CONFIG_CPU_SH7752)
diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h
deleted file mode 100644
index 7b217959ed..00
--- a/arch/sh/include/asm/cpu_sh7724.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008, 2011 Renesas Solutions Corp.
- *
- * SH7724 Internal I/O register
- */
-
-#ifndef _ASM_CPU_SH7724_H_
-#define _ASM_CPU_SH7724_H_
-
-#define CACHE_OC_NUM_WAYS  4
-#define CCR_CACHE_INIT 0x090d
-
-/* EXP */
-#define TRA0xFF20
-#define EXPEVT 0xFF24
-#define INTEVT 0xFF28
-
-/* MMU */
-#define PTEH   0xFF00
-#define PTEL   0xFF04
-#define TTB0xFF08
-#define TEA0xFF0C
-#define MMUCR  0xFF10
-#define PASCR  0xFF70
-#define IRMCR  0xFF78
-
-/* CACHE */
-#define CCR0xFF1C
-#define RAMCR  0xFF74
-
-/* INTC */
-
-/* BSC */
-#define MMSELR 0xFF800020
-#define CMNCR  0xFEC1
-#defineCS0BCR  0xFEC10004
-#define CS2BCR 0xFEC10008
-#define CS4BCR 0xFEC10010
-#define CS5ABCR0xFEC10014
-#define CS5BBCR0xFEC10018
-#define CS6ABCR0xFEC1001C
-#define CS6BBCR0xFEC10020
-#define CS0WCR 0xFEC10024
-#define CS2WCR 0xFEC10028
-#define CS4WCR 0xFEC10030
-#define CS5AWCR0xFEC10034
-#define CS5BWCR0xFEC10038
-#define CS6AWCR0xFEC1003C
-#define CS6BWCR0xFEC10040
-#define RBWTCNT0xFEC10054
-
-/* SBSC */
-#define SBSC_SDCR  0xFE48
-#define SBSC_SDWCR 0xFE4C
-#define SBSC_SDPCR 0xFE400010
-#define SBSC_RTCSR 0xFE400014
-#define SBSC_RTCNT 0xFE400018
-#define SBSC_RTCOR 0xFE40001C
-#define SBSC_RFCR  0xFE400020
-
-/* DSBC */
-#define DBKIND 0xFD08
-#define DBSTATE0xFD0C
-#define DBEN   0xFD10
-#define DBCMDCNT   0xFD14
-#define DBCKECNT   0xFD18
-#define DBCONF 0xFD20
-#define DBTR0  0xFD30
-#define DBTR1  0xFD34
-#define DBTR2  0xFD38
-#define DBTR3  0xFD3C
-#define DBRFPDN0   0xFD40
-#define DBRFPDN1   0xFD44
-#define DBRFPDN2   0xFD48
-#define DBRFSTS0xFD4C
-#define DBMRCNT0xFD60
-#define DBPDCNT0   0xFD000108
-
-/* DMAC */
-
-/* CPG */
-#define FRQCRA 0xA415
-#define FRQCRB 0xA4150004
-#define FRQCR  FRQCRA
-#define VCLKCR  0xA4150004
-#define SCLKACR 0xA4150008
-#define SCLKBCR 0xA415000C
-#define IRDACLKCR   0xA4150018
-#define PLLCR   0xA4150024
-#define DLLFRQ  0xA4150050
-
-/* LOW POWER MODE */
-#define STBCR   0xA4150020
-#define MSTPCR0 0xA4150030
-#define MSTPCR1 0xA4150034
-#define MSTPCR2 0xA4150038
-
-/* RWDT */
-#define RWTCNT  0xA452
-#define RWTCSR  0xA4520004
-#define WTCNT  RWTCNT
-
-/* TMU */
-#define TMU_BASE   0xFFD8
-
-/* TPU */
-
-/* CMT */
-#define CMSTR   0xA44A
-#define CMCSR   0xA44A0060
-#define CMCNT   0xA44A0064
-#define CMCOR   0xA44A0068
-
-/* MSIOF */
-
-/* SCIF */
-#define SCIF0_BASE  0xFFE0
-#define SCIF1_BASE  0xFFE1
-#define SCIF2_BASE  0xFFE2
-#define SCIF3_BASE  0xa4e3
-#define SCIF4_BASE  0xa4e4
-#define SCIF5_BASE  0xa4e5
-
-/* RTC */
-/* IrDA */
-/* KEYSC */
-/* USB */
-/* IIC */
-/* FLCTL */
-/* VPU */
-/* VIO(CEU) */
-/* VIO(VEU) */
-/* VIO(BEU) */
-/* 2DG */
-/* LCDC */
-/* VOU */
-/* TSIF */
-/* SIU */
-/* ATAPI */
-
-/* PFC */
-#define PACR0xA4050100
-#define PBCR0xA4050102
-#define PCCR0xA4050104
-#define PDCR0xA4050106
-#define PECR0xA4050108
-#define PFCR0xA405010A
-#define PGCR0xA405010C
-#define PHCR0xA405010E
-#define PJCR0xA4050110
-#define PKCR0xA4050112
-#define PLCR

[U-Boot] [PATCH 1/5] sh: sh7757lcr: Fix copy-paste error in README

[Marek Vasut]

Update the README to use the correct defconfig.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Nobuhiro Iwamatsu 
Cc: Vladimir Zapolskiy 
Cc: Yoshihiro Shimoda 
---
 board/renesas/sh7757lcr/README.sh7757lcr | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/renesas/sh7757lcr/README.sh7757lcr 
b/board/renesas/sh7757lcr/README.sh7757lcr
index 3e9c1c1a1e..9453839d2c 100644
--- a/board/renesas/sh7757lcr/README.sh7757lcr
+++ b/board/renesas/sh7757lcr/README.sh7757lcr
@@ -20,7 +20,7 @@ configuration for This board:
 
 You can select the configuration as follows:
 
- - make sh7785lcr_config
+ - make sh7757lcr_config
 
 
 This board specific command:
-- 
2.20.1

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[U-Boot] [PATCH] env: spi: Fix incorrect entry description

[Marek Vasut]

Fix the max frequency entry description, it's incorrect.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Jagan Teki 
Cc: Tom Rini 
---
 env/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/env/Kconfig b/env/Kconfig
index 78300660c7..70858d3b40 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -351,14 +351,14 @@ config ENV_SPI_CS
  Value of the SPI chip select for environment.
 
 config USE_ENV_SPI_MAX_HZ
-   bool "SPI flash bus for environment"
+   bool "SPI flash max frequency for environment"
depends on ENV_IS_IN_SPI_FLASH
help
  Force the SPI max work clock for environment.
  If not defined, use CONFIG_SF_DEFAULT_SPEED.
 
 config ENV_SPI_MAX_HZ
-   int "Value of SPI flash max work for environment"
+   int "Value of SPI flash max frequency for environment"
depends on USE_ENV_SPI_MAX_HZ
help
  Value of the SPI max work clock for environment.
-- 
2.20.1

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Re: [U-Boot] [PULL] u-boot-socfpga/master

[Tom Rini]

On Fri, May 03, 2019 at 05:10:53PM +0200, Marek Vasut wrote:

> The following changes since commit 6aebc0d11a10f48a54146c5e71bbef15a1a458fc:
> 
>   Revert "fs: btrfs: fix false negatives in ROOT_ITEM search"
> (2019-04-27 11:35:44 -0400)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-socfpga.git master
> 
> for you to fetch changes up to 7110259f550ce2c300f6f2c1760576c180705f4e:
> 
>   dts: arm: socfpga: fix socfpga_de10_nano console (2019-04-29 20:33:23
> +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PULL] u-boot-usb/master

[Tom Rini]

On Fri, May 03, 2019 at 05:15:30PM +0200, Marek Vasut wrote:

> The following changes since commit b4ee6daad7a2604ca9466b2ba48de86cc27d381f:
> 
>   Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx
> (2019-05-01 07:25:51 -0400)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-usb.git master
> 
> for you to fetch changes up to ff83e4c368f0155617e813d275d88192f05131e1:
> 
>   ARM: davinci: Remove unused functions from header (2019-05-03 17:14:49
> +0200)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] Please pull u-boot-marvell/master

[Tom Rini]

On Fri, May 03, 2019 at 01:49:51PM +0200, Stefan Roese wrote:

> Hi Tom,
> 
> please pull the following Marvell related patches:
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v3 1/2] arm64: zynqmp: spl: install a PMU firmware config object at runtime

[Luca Ceresoli]

Hi Michal,

thanks for your review. See my replies below.

On 04/05/19 00:38, Michal Simek wrote:
> On 15. 04. 19 9:47, Luca Ceresoli wrote:
>> Optionally allow U-Boot to load at the PMU firmware configuration object
>> into the Power Management Unit (PMU) on Xilinx ZynqMP.
>>
>> The configuration object is required by the PMU FW to enable most SoC
>> peripherals. So far the only way to boot using U-Boot SPL was to hard-code
>> the configuration object in the PMU firmware. Allow a different boot
>> process, where the PMU FW is equal for any ZynqMP chip and its
>> configuration is passed at runtime by U-Boot SPL.
>>
>> All the code for Inter-processor communication with the PMU is isolated in
>> a new file (pmu_ipc.c). The code is inspired by the same feature as
>> implemented in the Xilinx First Stage Bootloader (FSBL) and Arm Trusted
>> Firmware:
>>
>>  * 
>> https://github.com/Xilinx/embeddedsw/blob/fb647e6b4c00f5154eba52a88b948195b6f1dc2b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_misc_drivers.c#L295
>>  * 
>> https://github.com/ARM-software/arm-trusted-firmware/blob/c48d02bade88b07fa7f43aa44e5217f68e5d047f/plat/xilinx/zynqmp/pm_service/pm_api_sys.c#L357
>>
>> SPL logs on the console before loading the configuration object:
>>
>>   U-Boot SPL 2018.01 (Mar 20 2019 - 08:12:21)
>>   Loading PMUFW cfg obj (2008 bytes)
>>   EL Level:  EL3
>>   ...
>>
>> Signed-off-by: Luca Ceresoli 
>>
>> ---
>>
>> Changes RFC v2 -> v3:
>>  - don't compile pm_cfg_obj.c from source, load it from a binary file
>>(suggested by Michal)
>>  - move IPC code to arch/arm/mach-zynqmp/ and sys_proto.h (Michal)
>>
>> Changes RFC v1 -> RFC v2:
>>  - Load the cfg_obj in SPL, not U-Boot proper: this required a complete
>>reimplementation since we cannot rely on ATF now
>>  - Update and refine the Kconfig option help
>> ---
>>  arch/arm/mach-zynqmp/Kconfig  |  17 +++
>>  arch/arm/mach-zynqmp/Makefile |   4 +
>>  arch/arm/mach-zynqmp/include/mach/sys_proto.h |   4 +
>>  arch/arm/mach-zynqmp/pmu_ipc.c| 112 ++
>>  board/xilinx/zynqmp/Makefile  |  12 ++
>>  board/xilinx/zynqmp/pm_cfg_obj.S  |  17 +++
>>  board/xilinx/zynqmp/zynqmp.c  |   8 ++
>>  7 files changed, 174 insertions(+)
>>  create mode 100644 arch/arm/mach-zynqmp/pmu_ipc.c
>>  create mode 100644 board/xilinx/zynqmp/pm_cfg_obj.S
>>
>> diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
>> index 9bb5a5c20201..b88d1d313839 100644
>> --- a/arch/arm/mach-zynqmp/Kconfig
>> +++ b/arch/arm/mach-zynqmp/Kconfig
>> @@ -65,6 +65,23 @@ config PMUFW_INIT_FILE
>>Include external PMUFW (Platform Management Unit FirmWare) to
>>a Xilinx bootable image (boot.bin).
>>  
>> +config ZYNQMP_LOAD_PM_CFG_OBJ_FILE
>> +string "PMU firmware configuration object to load at runtime"
>> +help
>> +
> 
> remove this empty line.

OK.

>> diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h 
>> b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
>> index 385c8825f2f6..e2b9a79ed539 100644
>> --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
>> +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
>> @@ -72,4 +72,8 @@ int chip_id(unsigned char id);
>>  void tcm_init(u8 mode);
>>  #endif
>>  
>> +#if defined(CONFIG_SPL_BUILD) && defined(ZYNQMP_LOAD_PM_CFG_OBJ)
>> +void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
>> +#endif
> 
> nit: you can remove that if/endif to open a way to also pass different
> configuration object from full u-boot.

Good idea. Less #ifdefs is always good as well.

>> diff --git a/arch/arm/mach-zynqmp/pmu_ipc.c b/arch/arm/mach-zynqmp/pmu_ipc.c
>> new file mode 100644
>> index ..5feb8568f8de
>> --- /dev/null
>> +++ b/arch/arm/mach-zynqmp/pmu_ipc.c
>> @@ -0,0 +1,112 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Inter-Processor Communication with the Platform Management Unit (PMU)
>> + * firmware.
>> + *
>> + * (C) Copyright 2019 Luca Ceresoli
>> + * Luca Ceresoli 
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/* IPI bitmasks, register base and register offsets */
>> +#define IPI_BIT_MASK_APU  0x1
>> +#define IPI_BIT_MASK_PMU0 0x1
>> +#define IPI_REG_BASE_APU  0xFF30
>> +#define IPI_REG_BASE_PMU0 0xFF33
>> +#define IPI_REG_OFFSET_TRIG   0x00
>> +#define IPI_REG_OFFSET_OBR0x04
>> +
>> +/* IPI mailbox buffer offsets */
>> +#define IPI_BUF_BASE_APU   0xFF990400
>> +#define IPI_BUF_OFFSET_TARGET_PMU  0x1C0
>> +#define IPI_BUF_OFFSET_REQ 0x00
>> +#define IPI_BUF_OFFSET_RESP0x20
>> +
>> +#define PMUFW_PAYLOAD_ARG_CNT  8
>> +
>> +/* PMUFW commands */
>> +#define PMUFW_CMD_SET_CONFIGURATION2
>> +
>> +static void pmu_ipc_send_request(const u32 *req, size_t req_len)
>> +{
>> +u32 *mbx = IPI_BUF_BASE_APU +
>> +   IPI_BUF_OFFSET_TARGET_PMU +
>> +   IPI_BUF_OFFSET_REQ;
>> +size_t 

Re: [U-Boot] RISC-V: Crashes with OpenSBI+U-Boot on the qemu "virt" machine

[David Abdurachmanov]

On Sat, May 4, 2019 at 7:20 PM Anup Patel  wrote:
>
> On Sat, May 4, 2019 at 8:38 PM Karsten Merker  wrote:
> >
> > On Sat, May 04, 2019 at 09:24:15AM +0530, Anup Patel wrote:
> >
> > [U-Boot+OpenSBI crash with more than 2GB RAM in qemu-system-riscv64]
> > > I tried again with image header changes applied to u-boot and
> > > Linux kernel but still not able to reproduce the issues.
> > >
> > > Either you might have more local changes or debian toolchain
> > > is causing issue for u-boot.
> >
> > Hello,
> >
> > I hadn't made any local changes besides the ones described in my
> > original email, i.e. the application of the booti patches.  To
> > check for a toolchain-related problem I have rebuilt everything
> > with both the gcc8-based and the gcc7-based buildroot toolchains,
> > but the problem remained in all cases, regardless of whether I
> > used the branch with the booti patch or the plain v2019.07-rc1
> > tag, so the problem is definitely not specific to the Debian
> > toolchain.  As a new qemu release has happend just a few days
> > ago, I have now tried to upgrade qemu from the previous release
> > version 3.1.0 to the freshly released version 4.0.0, and indeed
> > with qemu 4.0.0 both the 2GB problem and the hang of init in SMP
> > configurations with OpenSBI+U-Boot are gone.  Which qemu version
> > had you been using in your tests?
>
> I am using QEMU 4.0.0-rc2.
>

If you want to use SMP with U-Boot you need to use QEMU 4.0.0 +
Kernel 5.1 + U-Boot v2019.07-rc1. At least that's what I recall.

david
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Re: [U-Boot] RISC-V: Crashes with OpenSBI+U-Boot on the qemu "virt" machine

[Anup Patel]

On Sat, May 4, 2019 at 8:38 PM Karsten Merker  wrote:
>
> On Sat, May 04, 2019 at 09:24:15AM +0530, Anup Patel wrote:
>
> [U-Boot+OpenSBI crash with more than 2GB RAM in qemu-system-riscv64]
> > I tried again with image header changes applied to u-boot and
> > Linux kernel but still not able to reproduce the issues.
> >
> > Either you might have more local changes or debian toolchain
> > is causing issue for u-boot.
>
> Hello,
>
> I hadn't made any local changes besides the ones described in my
> original email, i.e. the application of the booti patches.  To
> check for a toolchain-related problem I have rebuilt everything
> with both the gcc8-based and the gcc7-based buildroot toolchains,
> but the problem remained in all cases, regardless of whether I
> used the branch with the booti patch or the plain v2019.07-rc1
> tag, so the problem is definitely not specific to the Debian
> toolchain.  As a new qemu release has happend just a few days
> ago, I have now tried to upgrade qemu from the previous release
> version 3.1.0 to the freshly released version 4.0.0, and indeed
> with qemu 4.0.0 both the 2GB problem and the hang of init in SMP
> configurations with OpenSBI+U-Boot are gone.  Which qemu version
> had you been using in your tests?

I am using QEMU 4.0.0-rc2.

Like mentioned in previous email, BBL has limitation that it allows
full memory access to S-mode software. This means S-mode software
can actually corrupt BBL too. This is not possible in OpenSBI because
we use PMP configuration to protect firmware and critical memory
regions.

With QEMU 3.x, OpenSBI+U-Boot is failing for you because there
were bugs in QEMU PMP checks.

>
> What makes this interesting is that I'm running qemu 3.1.0 with
> BBL and Linux in a 4-core SMP configuration and with 8GB of RAM
> since months and never had any problems with it, so
> OpenSBI+U-Boot seems to do something differently from BBL.

That's because BBL is buggy. It allows complete RAM access to
S-mode software so QEMU PMP checks did not matter.

Regards,
Anup
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[U-Boot] [PATCH 1/1] efi_loader: correct parameter check in LocateHandle()

[Heinrich Schuchardt]

If LocateHandle() does not find an entry EFI_NOT_FOUND has to be returned
even if BufferSize is NULL.

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_boottime.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 51e0bb2fd5..7aa2b4e16e 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1365,28 +1365,28 @@ static efi_status_t efi_locate_handle(
return EFI_INVALID_PARAMETER;
}

-   /*
-* efi_locate_handle_buffer uses this function for
-* the calculation of the necessary buffer size.
-* So do not require a buffer for buffersize == 0.
-*/
-   if (!buffer_size || (*buffer_size && !buffer))
-   return EFI_INVALID_PARAMETER;
-
/* Count how much space we need */
list_for_each_entry(efiobj, _obj_list, link) {
if (!efi_search(search_type, protocol, search_key, efiobj))
size += sizeof(void *);
}

+   if (size == 0)
+   return EFI_NOT_FOUND;
+
+   if (!buffer_size)
+   return EFI_INVALID_PARAMETER;
+
if (*buffer_size < size) {
*buffer_size = size;
return EFI_BUFFER_TOO_SMALL;
}

*buffer_size = size;
-   if (size == 0)
-   return EFI_NOT_FOUND;
+
+   /* The buffer size is sufficient but there is not buffer */
+   if (!buffer)
+   return EFI_INVALID_PARAMETER;

/* Then fill the array */
list_for_each_entry(efiobj, _obj_list, link) {
--
2.20.1

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[U-Boot] [PULL] u-boot-mips

[Daniel Schwierzeck]

Hi Tom,

please pull MIPS updates for 2019.07

https://travis-ci.org/danielschwierzeck/u-boot/builds/527853668


The following changes since commit b4ee6daad7a2604ca9466b2ba48de86cc27d381f:

  Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx (2019-05-01 
07:25:51 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-mips.git tags/mips-pull-2019-05-03

for you to fetch changes up to 5c629b1b69f780540e6e3bcc57d29438749f97c5:

  net: mscc: ocelot: Update DTS for Luton pcb90 (2019-05-03 16:46:36 +0200)


- mscc: small fixes, enhance network support for Serval, Luton amd
Ocelot
- mt7620: rename arch to more generic name mtmips
- mips: pass initrd addresses via DT as physical addresses


Horatiu Vultur (13):
  mips: mscc: serval: Fix reset
  board: mscc: serval: Fix board detect
  net: Add MSCC Serval network driver.
  board: mscc: serval: Update MSCC Serval boards
  net: mscc: serval: Add ethernet nodes for Serval
  configs: mscc_serval: Add network support
  arch: mips: Update initrd_start and initrd_end
  net: mscc: ocelot: Update network driver for pcb120
  board: mscc: ocelot: Update MSCC Ocelot board.
  net: mscc: ocelot: Update DTS for Ocelot pcb120.
  net: mscc: luton: Update network driver for pcb90
  board: mscc: luton: Update MSCC Luton board
  net: mscc: ocelot: Update DTS for Luton pcb90

Robert P. J. Day (1):
  MSCC: delete obsolete reference to MSCC_BITBANG_SPI_GPIO

Weijie Gao (1):
  mips: rename mach-mt7620 to mach-mtmips

 MAINTAINERS|   1 +
 arch/mips/Kconfig  |   6 +-
 arch/mips/Makefile |   2 +-
 arch/mips/dts/Makefile |   2 +-
 arch/mips/dts/luton_pcb090.dts | 228 +--
 arch/mips/dts/luton_pcb091.dts | 132 ++--
 arch/mips/dts/mscc,luton.dtsi  | 126 +---
 arch/mips/dts/mscc,ocelot.dtsi | 109 ++--
 arch/mips/dts/mscc,serval.dtsi |  58 ++
 arch/mips/dts/ocelot_pcb120.dts|  75 +++
 arch/mips/dts/ocelot_pcb123.dts|  44 +-
 arch/mips/dts/serval_pcb105.dts|  44 ++
 arch/mips/dts/serval_pcb106.dts|  44 ++
 arch/mips/lib/bootm.c  |   2 +
 arch/mips/mach-mscc/Kconfig|   1 -
 arch/mips/mach-mscc/include/mach/ddr.h |  55 +-
 .../include/mach/ocelot/ocelot_devcpu_gcb.h|   1 +
 arch/mips/mach-mscc/reset.c|   2 +-
 arch/mips/{mach-mt7620 => mach-mtmips}/Kconfig |  14 +-
 arch/mips/{mach-mt7620 => mach-mtmips}/Makefile|   0
 arch/mips/{mach-mt7620 => mach-mtmips}/cpu.c   |   0
 .../{mach-mt7620 => mach-mtmips}/ddr_calibrate.c   |   0
 .../{mach-mt7620 => mach-mtmips}/lowlevel_init.S   |   0
 arch/mips/{mach-mt7620 => mach-mtmips}/mt76xx.h|   0
 board/mscc/luton/luton.c   |  13 +-
 board/mscc/ocelot/ocelot.c |  15 +
 board/mscc/serval/serval.c |  14 +-
 configs/gardena-smart-gateway-mt7688-ram_defconfig |   2 +-
 configs/gardena-smart-gateway-mt7688_defconfig |   2 +-
 configs/linkit-smart-7688-ram_defconfig|   2 +-
 configs/linkit-smart-7688_defconfig|   2 +-
 configs/mscc_serval_defconfig  |   6 +-
 drivers/gpio/Kconfig   |   2 +-
 drivers/net/Kconfig|   2 +-
 drivers/net/mscc_eswitch/Kconfig   |   7 +
 drivers/net/mscc_eswitch/Makefile  |   5 +-
 drivers/net/mscc_eswitch/luton_switch.c| 415 +++-
 drivers/net/mscc_eswitch/ocelot_switch.c   | 434 ++---
 drivers/net/mscc_eswitch/serval_switch.c   | 703 +
 drivers/spi/Kconfig|   2 +-
 drivers/watchdog/Kconfig   |   2 +-
 include/dt-bindings/mscc/luton_data.h  |  17 +
 include/dt-bindings/mscc/ocelot_data.h |  19 +
 include/dt-bindings/mscc/serval_data.h |  19 +
 44 files changed, 2043 insertions(+), 586 deletions(-)
 rename arch/mips/{mach-mt7620 => mach-mtmips}/Kconfig (93%)
 rename arch/mips/{mach-mt7620 => mach-mtmips}/Makefile (100%)
 rename arch/mips/{mach-mt7620 => mach-mtmips}/cpu.c (100%)
 rename arch/mips/{mach-mt7620 => mach-mtmips}/ddr_calibrate.c (100%)
 rename arch/mips/{mach-mt7620 => mach-mtmips}/lowlevel_init.S (100%)
 rename arch/mips/{mach-mt7620 => mach-mtmips}/mt76xx.h (100%)
 create mode 100644 drivers/net/mscc_eswitch/serval_switch.c
 create mode 100644 include/dt-bindings/mscc/luton_data.h
 create mode 100644 

Re: [U-Boot] [PATCH, RESEND] mips: rename mach-mt7620 to mach-mtmips

[Daniel Schwierzeck]

Am 30.04.19 um 05:13 schrieb Weijie Gao:
> Currently mach-mt7620 contains only support for mt7628. To avoid confusion,
> rename mach-mt7620 to mach-mtmips, which means MediaTek MIPS platforms.
> MT7620 and MT7628 should be distinguished by SOC_MT7620 and SOC_MT7628
> because they do not share the same lowlevel codes.
> 
> Dependencies of four drivers are changed to SOC_MT7628 as these drivers
> are only used by MT7628.
> 
> Cc: Daniel Schwierzeck 
> Reviewed-by: Stefan Roese 
> Signed-off-by: Weijie Gao 
> ---
>  arch/mips/Kconfig  |  6 +++---
>  arch/mips/Makefile |  2 +-
>  arch/mips/dts/Makefile |  2 +-
>  arch/mips/{mach-mt7620 => mach-mtmips}/Kconfig | 14 +++---
>  arch/mips/{mach-mt7620 => mach-mtmips}/Makefile|  0
>  arch/mips/{mach-mt7620 => mach-mtmips}/cpu.c   |  0
>  .../{mach-mt7620 => mach-mtmips}/ddr_calibrate.c   |  0
>  .../{mach-mt7620 => mach-mtmips}/lowlevel_init.S   |  0
>  arch/mips/{mach-mt7620 => mach-mtmips}/mt76xx.h|  0
>  configs/gardena-smart-gateway-mt7688-ram_defconfig |  2 +-
>  configs/gardena-smart-gateway-mt7688_defconfig |  2 +-
>  configs/linkit-smart-7688-ram_defconfig|  2 +-
>  configs/linkit-smart-7688_defconfig|  2 +-
>  drivers/gpio/Kconfig   |  2 +-
>  drivers/net/Kconfig|  2 +-
>  drivers/spi/Kconfig|  2 +-
>  drivers/watchdog/Kconfig   |  2 +-
>  17 files changed, 20 insertions(+), 20 deletions(-)
>  rename arch/mips/{mach-mt7620 => mach-mtmips}/Kconfig (93%)
>  rename arch/mips/{mach-mt7620 => mach-mtmips}/Makefile (100%)
>  rename arch/mips/{mach-mt7620 => mach-mtmips}/cpu.c (100%)
>  rename arch/mips/{mach-mt7620 => mach-mtmips}/ddr_calibrate.c (100%)
>  rename arch/mips/{mach-mt7620 => mach-mtmips}/lowlevel_init.S (100%)
>  rename arch/mips/{mach-mt7620 => mach-mtmips}/mt76xx.h (100%)
> 

applied to u-boot-mips, thanks.

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Re: [U-Boot] [PATCH 0/3] Update Luton network driver

[Daniel Schwierzeck]

Am 01.05.19 um 13:16 schrieb Horatiu Vultur:
> Update Luton network driver to add support for all the ports
> on pcb90. The existing support is only for first 12 ports, with
> this patch adds support for another 12 ports.
> 
> This patch series is based on u-boot-mips/master.
> 
> Horatiu Vultur (3):
>   net: mscc: luton: Update network driver for pcb90
>   board: mscc: luton: Update MSCC Luton board
>   net: mscc: ocelot: Update DTS for Luton pcb90
> 
>  arch/mips/dts/luton_pcb090.dts  | 228 ++
>  arch/mips/dts/luton_pcb091.dts  | 132 ++
>  arch/mips/dts/mscc,luton.dtsi   | 126 ++
>  board/mscc/luton/luton.c|  13 +-
>  drivers/net/mscc_eswitch/Makefile   |   2 +-
>  drivers/net/mscc_eswitch/luton_switch.c | 415 
> 
>  include/dt-bindings/mscc/luton_data.h   |  17 ++
>  7 files changed, 576 insertions(+), 357 deletions(-)
>  create mode 100644 include/dt-bindings/mscc/luton_data.h
> 

series applied to u-boot-mips, thanks.

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[U-Boot] [PATCH 4/4] efi_loader: unload applications upon Exit()

[Heinrich Schuchardt]

Implement unloading of images in the Exit() boot services:

* unload images that are not yet started,
* unload started applications,
* unload drivers returning an error.

Signed-off-by: Heinrich Schuchardt 
---
 include/efi_loader.h  |  1 +
 lib/efi_loader/efi_boottime.c | 34 ++-
 lib/efi_loader/efi_image_loader.c |  2 ++
 3 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/include/efi_loader.h b/include/efi_loader.h
index c2a449e5b6..d73c89ac26 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -237,6 +237,7 @@ struct efi_loaded_image_obj {
struct jmp_buf_data exit_jmp;
EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
 struct efi_system_table *st);
+   u16 image_type;
 };

 /**
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index bbcd66caa6..51e0bb2fd5 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 

 DECLARE_GLOBAL_DATA_PTR;
@@ -2798,7 +2799,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t 
image_handle,
 *   image protocol.
 */
efi_status_t ret;
-   void *info;
+   struct efi_loaded_image *loaded_image_protocol;
struct efi_loaded_image_obj *image_obj =
(struct efi_loaded_image_obj *)image_handle;

@@ -2806,13 +2807,33 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t 
image_handle,
  exit_data_size, exit_data);

/* Check parameters */
-   if (image_handle != current_image)
+   if (image_handle != current_image) {
+   ret = EFI_INVALID_PARAMETER;
goto out;
+   }
ret = EFI_CALL(efi_open_protocol(image_handle, _guid_loaded_image,
-, NULL, NULL,
+(void **)_image_protocol,
+NULL, NULL,
 EFI_OPEN_PROTOCOL_GET_PROTOCOL));
-   if (ret != EFI_SUCCESS)
+   if (ret != EFI_SUCCESS) {
+   ret = EFI_INVALID_PARAMETER;
goto out;
+   }
+
+   /* Unloading of unstarted images */
+   switch (image_obj->header.type) {
+   case EFI_OBJECT_TYPE_STARTED_IMAGE:
+   break;
+   case EFI_OBJECT_TYPE_LOADED_IMAGE:
+   efi_delete_image(image_obj, loaded_image_protocol);
+   ret = EFI_SUCCESS;
+   goto out;
+   default:
+   /* Handle does not refer to loaded image */
+   ret = EFI_INVALID_PARAMETER;
+   goto out;
+   }
+   image_obj->header.type = EFI_OBJECT_TYPE_LOADED_IMAGE;

/* Exit data is only foreseen in case of failure. */
if (exit_status != EFI_SUCCESS) {
@@ -2822,6 +2843,9 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t 
image_handle,
if (ret != EFI_SUCCESS)
EFI_PRINT("%s: out of memory\n", __func__);
}
+   if (image_obj->image_type == IMAGE_SUBSYSTEM_EFI_APPLICATION ||
+   exit_status != EFI_SUCCESS)
+   efi_delete_image(image_obj, loaded_image_protocol);

/* Make sure entry/exit counts for EFI world cross-overs match */
EFI_EXIT(exit_status);
@@ -2837,7 +2861,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t 
image_handle,

panic("EFI application exited");
 out:
-   return EFI_EXIT(EFI_INVALID_PARAMETER);
+   return EFI_EXIT(ret);
 }

 /**
diff --git a/lib/efi_loader/efi_image_loader.c 
b/lib/efi_loader/efi_image_loader.c
index f8092b6202..13541cfa7a 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -273,6 +273,7 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj 
*handle, void *efi,
IMAGE_OPTIONAL_HEADER64 *opt = >OptionalHeader;
image_base = opt->ImageBase;
efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
+   handle->image_type = opt->Subsystem;
efi_reloc = efi_alloc(virt_size,
  loaded_image_info->image_code_type);
if (!efi_reloc) {
@@ -288,6 +289,7 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj 
*handle, void *efi,
IMAGE_OPTIONAL_HEADER32 *opt = >OptionalHeader;
image_base = opt->ImageBase;
efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
+   handle->image_type = opt->Subsystem;
efi_reloc = efi_alloc(virt_size,
  loaded_image_info->image_code_type);
if (!efi_reloc) {
--
2.20.1

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[U-Boot] [PATCH 3/4] efi_loader: implement UnloadImage()

[Heinrich Schuchardt]

Implement the UnloadImage() boot service

Signed-off-by: Heinrich Schuchardt 
---
 include/efi_api.h |  2 +-
 lib/efi_loader/efi_boottime.c | 55 ---
 2 files changed, 52 insertions(+), 5 deletions(-)

diff --git a/include/efi_api.h b/include/efi_api.h
index 4ebb4a5f59..54c6232079 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -348,7 +348,7 @@ struct efi_loaded_image {
aligned_u64 image_size;
unsigned int image_code_type;
unsigned int image_data_type;
-   unsigned long unload;
+   efi_status_t (EFIAPI *unload)(efi_handle_t image_handle);
 };

 #define EFI_DEVICE_PATH_PROTOCOL_GUID \
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 2992af269a..bbcd66caa6 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -2669,6 +2669,20 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t 
image_handle,
return EFI_CALL(systab.boottime->exit(image_handle, ret, 0, NULL));
 }

+/**
+ * efi_delete_image() - delete loaded image from memory)
+ *
+ * @image_obj: handle of the loaded image
+ * @loaded_image_protocol: loaded image protocol
+ */
+static void efi_delete_image(struct efi_loaded_image_obj *image_obj,
+struct efi_loaded_image *loaded_image_protocol)
+{
+   efi_free_pages((uintptr_t)loaded_image_protocol->image_base,
+  efi_size_in_pages(loaded_image_protocol->image_size));
+   efi_delete_handle(_obj->header);
+}
+
 /**
  * efi_unload_image() - unload an EFI image
  * @image_handle: handle of the image to be unloaded
@@ -2682,14 +2696,47 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t 
image_handle,
  */
 efi_status_t EFIAPI efi_unload_image(efi_handle_t image_handle)
 {
+   efi_status_t ret = EFI_SUCCESS;
struct efi_object *efiobj;
+   struct efi_loaded_image *loaded_image_protocol;

EFI_ENTRY("%p", image_handle);
-   efiobj = efi_search_obj(image_handle);
-   if (efiobj)
-   list_del(>link);

-   return EFI_EXIT(EFI_SUCCESS);
+   efiobj = efi_search_obj(image_handle);
+   if (!efiobj) {
+   ret = EFI_INVALID_PARAMETER;
+   goto out;
+   }
+   /* Find the loaded image protocol */
+   ret = EFI_CALL(efi_open_protocol(image_handle, _guid_loaded_image,
+(void **)_image_protocol,
+NULL, NULL,
+EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+   if (ret != EFI_SUCCESS) {
+   ret = EFI_INVALID_PARAMETER;
+   goto out;
+   }
+   switch (efiobj->type) {
+   case EFI_OBJECT_TYPE_STARTED_IMAGE:
+   /* Call the unload function */
+   if (!loaded_image_protocol->unload) {
+   ret = EFI_UNSUPPORTED;
+   goto out;
+   }
+   ret = EFI_CALL(loaded_image_protocol->unload(image_handle));
+   if (ret != EFI_SUCCESS)
+   goto out;
+   break;
+   case EFI_OBJECT_TYPE_LOADED_IMAGE:
+   break;
+   default:
+   ret = EFI_INVALID_PARAMETER;
+   goto out;
+   }
+   efi_delete_image((struct efi_loaded_image_obj *)efiobj,
+loaded_image_protocol);
+out:
+   return EFI_EXIT(ret);
 }

 /**
--
2.20.1

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[U-Boot] [PATCH 2/4] efi_loader: move efi_unload_image() down in source

[Heinrich Schuchardt]

Move efi_unload_image() down in source to avoid forward declaration in
following page.

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_boottime.c | 46 +--
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index dc444fccf6..2992af269a 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1744,29 +1744,6 @@ error:
return EFI_EXIT(ret);
 }

-/**
- * efi_unload_image() - unload an EFI image
- * @image_handle: handle of the image to be unloaded
- *
- * This function implements the UnloadImage service.
- *
- * See the Unified Extensible Firmware Interface (UEFI) specification for
- * details.
- *
- * Return: status code
- */
-efi_status_t EFIAPI efi_unload_image(efi_handle_t image_handle)
-{
-   struct efi_object *efiobj;
-
-   EFI_ENTRY("%p", image_handle);
-   efiobj = efi_search_obj(image_handle);
-   if (efiobj)
-   list_del(>link);
-
-   return EFI_EXIT(EFI_SUCCESS);
-}
-
 /**
  * efi_exit_caches() - fix up caches for EFI payloads if necessary
  */
@@ -2692,6 +2669,29 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t 
image_handle,
return EFI_CALL(systab.boottime->exit(image_handle, ret, 0, NULL));
 }

+/**
+ * efi_unload_image() - unload an EFI image
+ * @image_handle: handle of the image to be unloaded
+ *
+ * This function implements the UnloadImage service.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * Return: status code
+ */
+efi_status_t EFIAPI efi_unload_image(efi_handle_t image_handle)
+{
+   struct efi_object *efiobj;
+
+   EFI_ENTRY("%p", image_handle);
+   efiobj = efi_search_obj(image_handle);
+   if (efiobj)
+   list_del(>link);
+
+   return EFI_EXIT(EFI_SUCCESS);
+}
+
 /**
  * efi_update_exit_data() - fill exit data parameters of StartImage()
  *
--
2.20.1

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[U-Boot] [PATCH 1/4] efi_loader: mark started images

[Heinrich Schuchardt]

In UnloadImage() we need to know if an image is already started.

Add a field to the handle structure identifying loaded and started images.

Signed-off-by: Heinrich Schuchardt 
---
 include/efi_loader.h  | 13 +
 lib/efi_loader/efi_boottime.c |  2 ++
 2 files changed, 15 insertions(+)

diff --git a/include/efi_loader.h b/include/efi_loader.h
index 3fd9901d66..c2a449e5b6 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -182,6 +182,18 @@ struct efi_handler {
struct list_head open_infos;
 };

+/**
+ * enum efi_object_type - type of EFI object
+ *
+ * In UnloadImage we must be able to identify if the handle relates to a
+ * started image.
+ */
+enum efi_object_type {
+   EFI_OBJECT_TYPE_UNDEFINED = 0,
+   EFI_OBJECT_TYPE_LOADED_IMAGE,
+   EFI_OBJECT_TYPE_STARTED_IMAGE,
+};
+
 /**
  * struct efi_object - dereferenced EFI handle
  *
@@ -204,6 +216,7 @@ struct efi_object {
struct list_head link;
/* The list of protocols */
struct list_head protocols;
+   enum efi_object_type type;
 };

 /**
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 3ed08e7c37..dc444fccf6 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1554,6 +1554,7 @@ efi_status_t efi_setup_loaded_image(struct 
efi_device_path *device_path,
free(info);
return EFI_OUT_OF_RESOURCES;
}
+   obj->header.type = EFI_OBJECT_TYPE_LOADED_IMAGE;

/* Add internal object to object list */
efi_add_handle(>header);
@@ -2678,6 +2679,7 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t 
image_handle,
}

current_image = image_handle;
+   image_obj->header.type = EFI_OBJECT_TYPE_STARTED_IMAGE;
EFI_PRINT("Jumping into 0x%p\n", image_obj->entry);
ret = EFI_CALL(image_obj->entry(image_handle, ));

--
2.20.1

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[U-Boot] [PATCH 0/4] efi_loader implent unloading of images

[Heinrich Schuchardt]

The patch series implements the UnloadImage() boot service and the
unloading of images in Exit().

Heinrich Schuchardt (4):
  efi_loader: mark started images
  efi_loader: move efi_unload_image() down in source
  efi_loader: implement UnloadImage()
  efi_loader: unload applications upon Exit()

 include/efi_api.h |   2 +-
 include/efi_loader.h  |  14 
 lib/efi_loader/efi_boottime.c | 129 +++---
 lib/efi_loader/efi_image_loader.c |   2 +
 4 files changed, 118 insertions(+), 29 deletions(-)

--
2.20.1

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[U-Boot] [PATCH 1/1] efi_loader: allowable event types in CreateEventEx()

[Heinrich Schuchardt]

CreateEventEx() does allow the following event types:

* EVT_SIGNAL_EXIT_BOOT_SERVICES
* EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_boottime.c | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 602b0da9f0..8965dabb2b 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -665,10 +665,26 @@ efi_status_t EFIAPI efi_create_event_ex(uint32_t type, 
efi_uintn_t notify_tpl,
efi_guid_t *event_group,
struct efi_event **event)
 {
+   efi_status_t ret;
+
EFI_ENTRY("%d, 0x%zx, %p, %p, %pUl", type, notify_tpl, notify_function,
  notify_context, event_group);
-   return EFI_EXIT(efi_create_event(type, notify_tpl, notify_function,
-notify_context, event_group, event));
+
+   /*
+* The allowable input parameters are the same as in CreateEvent()
+* except for the following two disallowed event types.
+*/
+   switch (type) {
+   case EVT_SIGNAL_EXIT_BOOT_SERVICES:
+   case EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE:
+   ret = EFI_INVALID_PARAMETER;
+   goto out;
+   }
+
+   ret = efi_create_event(type, notify_tpl, notify_function,
+  notify_context, event_group, event);
+out:
+   return EFI_EXIT(ret);
 }

 /**
--
2.20.1

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Re: [U-Boot] [PATCH] fdt_shrink_to_minimum: do not mark fdt space reserved unconditionally

[Lokesh Vutla]

On 04/05/19 12:49 AM, Simon Goldschmidt wrote:
> This function merely relocates the fdt blob, so don't let it alter
> it by adding reservations that didn't exist before.
> 
> Instead, if the memory used for the fdt blob has been reserved
> before calling this function, ensure the relocated memory is
> marked as reserved instead.
> 
> Reported-by: Keerthy 
> Reported-by: Lokesh Vutla 
> Signed-off-by: Simon Goldschmidt 

Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh

> ---
> 
>  common/fdt_support.c | 12 
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/common/fdt_support.c b/common/fdt_support.c
> index ab08a0114f..4e7cf6ebe9 100644
> --- a/common/fdt_support.c
> +++ b/common/fdt_support.c
> @@ -597,6 +597,7 @@ int fdt_shrink_to_minimum(void *blob, uint extrasize)
>   uint64_t addr, size;
>   int total, ret;
>   uint actualsize;
> + int fdt_memrsv = 0;
>  
>   if (!blob)
>   return 0;
> @@ -606,6 +607,7 @@ int fdt_shrink_to_minimum(void *blob, uint extrasize)
>   fdt_get_mem_rsv(blob, i, , );
>   if (addr == (uintptr_t)blob) {
>   fdt_del_mem_rsv(blob, i);
> + fdt_memrsv = 1;
>   break;
>   }
>   }
> @@ -627,10 +629,12 @@ int fdt_shrink_to_minimum(void *blob, uint extrasize)
>   /* Change the fdt header to reflect the correct size */
>   fdt_set_totalsize(blob, actualsize);
>  
> - /* Add the new reservation */
> - ret = fdt_add_mem_rsv(blob, map_to_sysmem(blob), actualsize);
> - if (ret < 0)
> - return ret;
> + if (fdt_memrsv) {
> + /* Add the new reservation */
> + ret = fdt_add_mem_rsv(blob, map_to_sysmem(blob), actualsize);
> + if (ret < 0)
> + return ret;
> + }
>  
>   return actualsize;
>  }
> 
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Re: [U-Boot] [PATCH v3 2/2] arm64: zynqmp: add tool to convert PMU config object .c to binary

[Luca Ceresoli]

Hi Michal,

On 04/05/19 00:31, Michal Simek wrote:
> Hi,
> 
> On 15. 04. 19 9:47, Luca Ceresoli wrote:
>> The recently-added ZYNQMP_LOAD_PM_CFG_OBJ_FILE option allows SPL to load a
>> PMUFW configuration object from a binary blob. However the configuration
>> object is produced by Xilinx proprietary tools as a C source file and no
>> tool exists to easily convert it to a binary blob in an embedded Linux
>> build system for U-Boot to use.
>>
>> Add a simple Python script to do the conversion.
>>
>> It is definitely not a complete C language parser, but it is enough to
>> parse the known patterns generated by Xilinx tools, including:
>>
>>  - defines
>>  - literal integers, optionally with a 'U' suffix
>>  - bitwise OR between them
>>
>> Signed-off-by: Luca Ceresoli 
>> ---
>>  arch/arm/mach-zynqmp/pm_cfg_obj_convert.py | 302 +
>>  1 file changed, 302 insertions(+)
>>  create mode 100755 arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
>>
>> diff --git a/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py 
>> b/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
>> new file mode 100755
>> index ..5aea15860319
>> --- /dev/null
>> +++ b/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
>> @@ -0,0 +1,302 @@
>> +#!/usr/bin/env python3
>> +# SPDX-License-Identifier: GPL-2.0+
>> +# Copyright (C) 2019 Luca Ceresoli 
>> +
>> +import sys
>> +import re
>> +import struct
>> +import logging
>> +import argparse
>> +
>> +parser = argparse.ArgumentParser(
>> +description='Convert a PMU configuration object from C source to a 
>> binary blob.',
>> +allow_abbrev=False)
>> +parser.add_argument('-D', '--debug', action="store_true")
>> +parser.add_argument(
>> +"in_file", metavar='INPUT_FILE',
>> +help='PMU configuration object (C source as produced by Xilinx XSDK)')
>> +parser.add_argument(
>> +"out_file", metavar='OUTPUT_FILE',
>> +help='PMU configuration object binary blob')
>> +args = parser.parse_args()
>> +
>> +logging.basicConfig(format='%(levelname)s:%(message)s',
>> +level=(logging.DEBUG if args.debug else 
>> logging.WARNING))
>> +
>> +pm_define = {
>> +'PM_CAP_ACCESS'   : 0x1,
>> +'PM_CAP_CONTEXT'  : 0x2,
>> +'PM_CAP_WAKEUP'   : 0x4,
>> +
>> +'NODE_UNKNOWN':  0,
>> +'NODE_APU':  1,
>> +'NODE_APU_0'  :  2,
>> +'NODE_APU_1'  :  3,
>> +'NODE_APU_2'  :  4,
>> +'NODE_APU_3'  :  5,
>> +'NODE_RPU':  6,
>> +'NODE_RPU_0'  :  7,
>> +'NODE_RPU_1'  :  8,
>> +'NODE_PLD':  9,
>> +'NODE_FPD': 10,
>> +'NODE_OCM_BANK_0' : 11,
>> +'NODE_OCM_BANK_1' : 12,
>> +'NODE_OCM_BANK_2' : 13,
>> +'NODE_OCM_BANK_3' : 14,
>> +'NODE_TCM_0_A': 15,
>> +'NODE_TCM_0_B': 16,
>> +'NODE_TCM_1_A': 17,
>> +'NODE_TCM_1_B': 18,
>> +'NODE_L2' : 19,
>> +'NODE_GPU_PP_0'   : 20,
>> +'NODE_GPU_PP_1'   : 21,
>> +'NODE_USB_0'  : 22,
>> +'NODE_USB_1'  : 23,
>> +'NODE_TTC_0'  : 24,
>> +'NODE_TTC_1'  : 25,
>> +'NODE_TTC_2'  : 26,
>> +'NODE_TTC_3'  : 27,
>> +'NODE_SATA'   : 28,
>> +'NODE_ETH_0'  : 29,
>> +'NODE_ETH_1'  : 30,
>> +'NODE_ETH_2'  : 31,
>> +'NODE_ETH_3'  : 32,
>> +'NODE_UART_0' : 33,
>> +'NODE_UART_1' : 34,
>> +'NODE_SPI_0'  : 35,
>> +'NODE_SPI_1'  : 36,
>> +'NODE_I2C_0'  : 37,
>> +'NODE_I2C_1'  : 38,
>> +'NODE_SD_0'   : 39,
>> +'NODE_SD_1'   : 40,
>> +'NODE_DP' : 41,
>> +'NODE_GDMA'   : 42,
>> +'NODE_ADMA'   : 43,
>> +'NODE_NAND'   : 44,
>> +'NODE_QSPI'   : 45,
>> +'NODE_GPIO'   : 46,
>> +'NODE_CAN_0'  : 47,
>> +'NODE_CAN_1'  : 48,
>> +'NODE_EXTERN' : 49,
>> +'NODE_APLL'   : 50,
>> +'NODE_VPLL'   : 51,
>> +'NODE_DPLL'   : 52,
>> +'NODE_RPLL'   : 53,
>> +'NODE_IOPLL'  : 54,
>> +'NODE_DDR': 55,
>> +'NODE_IPI_APU': 56,
>> +'NODE_IPI_RPU_0'  : 57,
>> +'NODE_GPU': 58,
>> +'NODE_PCIE'   : 59,
>> +'NODE_PCAP'   : 60,
>> +'NODE_RTC': 61,
>> +'NODE_LPD': 62,
>> +'NODE_VCU': 63,
>> +'NODE_IPI_RPU_1'  : 64,
>> +'NODE_IPI_PL_0'   : 65,
>> +'NODE_IPI_PL_1'   : 66,
>> +'NODE_IPI_PL_2'   : 67,
>> +'NODE_IPI_PL_3'   : 68,
>> +'NODE_PL' : 69,
>> +'NODE_ID_MA'  : 70,
>> +
>> +'XILPM_RESET_PCIE_CFG' : 1000,
>> +'XILPM_RESET_PCIE_BRIDGE'  : 1001,
>> +'XILPM_RESET_PCIE_CTRL': 1002,
>> +'XILPM_RESET_DP'   : 1003,
>> +'XILPM_RESET_SWDT_CRF' : 1004,
>> +'XILPM_RESET_AFI_FM5'  : 1005,
>> +'XILPM_RESET_AFI_FM4'  : 1006,
>> +'XILPM_RESET_AFI_FM3'  : 1007,
>> +'XILPM_RESET_AFI_FM2'  : 1008,
>> +'XILPM_RESET_AFI_FM1'  : 1009,
>> +