Re: [U-Boot] [PATCH] armv8: ls1028ardb: enable DisplayPort Power support

[Wen He]

> -Original Message-
> From: Wen He 
> Sent: 2019年7月23日 10:06
> To: Andy Tang ; u-boot@lists.denx.de
> Cc: Wen He 
> Subject: [PATCH] armv8: ls1028ardb: enable DisplayPort Power support
> 
> Enable DP_PWR signal to power the DP to HDMI converter cable.
> 
> Signed-off-by: Wen He 
> ---
>  include/configs/ls1028a_common.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/configs/ls1028a_common.h
> b/include/configs/ls1028a_common.h
> index 41ce4a054c..25fc548c99 100644
> --- a/include/configs/ls1028a_common.h
> +++ b/include/configs/ls1028a_common.h
> @@ -135,6 +135,7 @@
>   "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
>   " bootm $load_addr#$board\0" \
>   "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
> + "i2c mw 0x66 0x54 0x0;" \
>   "sf probe 0:0 && sf read $load_addr 0x94 0x3 " \
>   "&& hdp load $load_addr 0x2000\0"   \
>   "sd_bootcmd=echo Trying load from SD ...;" \ @@ -145,6 +146,7 @@
>   " && esbc_validate ${kernelheader_addr_r};" \
>   "bootm $load_addr#$board\0" \
>   "sd_hdploadcmd=echo Trying load HDP firmware from SD..;"\
> + "i2c mw 0x66 0x54 0x0;" \
>   "mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
>   "&& hdp load $load_addr 0x2000\0"   \
>   "emmc_bootcmd=echo Trying load from EMMC ..;"   \
> @@ -155,6 +157,7 @@
>   " && esbc_validate ${kernelheader_addr_r};" \
>   "bootm $load_addr#$board\0" \
>   "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;"
> \
> + "i2c mw 0x66 0x54 0x0;" \
>   "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 "   \
>   "&& hdp load $load_addr 0x2000\0"
> 

Sorry, Should be move this function to platform initialization, will send v2 
version. 

Best Regards,
Wen

> --
> 2.17.1

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[U-Boot] [v2] armv8: ls1028ardb: enable DisplayPort Power support

[Wen He]

Enable DP_PWR signal to power the DP to HDMI converter cable.

Signed-off-by: Wen He 
---
 board/freescale/ls1028a/ls1028a.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/board/freescale/ls1028a/ls1028a.c 
b/board/freescale/ls1028a/ls1028a.c
index ece91660bf..7d34f92eb5 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -75,6 +75,19 @@ int board_init(void)
u8 val = I2C_MUX_CH_DEFAULT;
 
i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
+#endif
+
+#if defined(CONFIG_TARGET_LS1028ARDB)
+   u8 reg;
+
+   reg = QIXIS_READ(brdcfg[4]);
+   /* Field| Function
+* 3 | DisplayPort Power Enable (net DP_PWR_EN):
+* DPPWR | 0= DP_PWR is enabled.
+*/
+   reg &= ~(0x08);
+   QIXIS_WRITE(brdcfg[4], reg);
+
 #endif
return 0;
 }
-- 
2.17.1

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Re: [U-Boot] [PATCH 1/4] net: mdio-uclass: name MDIO according to device-name property if preset

[Bin Meng]

Hi Alex,

On Tue, Jul 23, 2019 at 2:51 PM Alex Marginean  wrote:
>
> On 7/23/2019 9:38 AM, Bin Meng wrote:
> > On Wed, Jul 17, 2019 at 11:11 PM Alex Marginean
> >  wrote:
> >>
> >> Use the optional property device-name to name the MDIO bus.  This works
> >> around limitations with using the DT node name on devices such as
> >> Armada-8040, which integrates two cp100 cores, both featuring MDIOs at the
> >> same relative offsets and with the same DT node names.
> >> The concept was originally proposed by Marvell as a custom property called
> >> mdio-name specific to Marvell driver.  This patch uses the more generic
> >
> > I was wondering whether such optional custom property name is accepted
> > by the Linux devicetree committee or yet? The general goal is to use
> > exact the same DT as kernel uses, at least for ARM, and that is what I
> > learned from this ML.
>
> I didn't ask, my guess is they would not.  The property is not actually
> describing HW, plus Linux wouldn't need this name anyway.  As far as I
> know MDIOs in Linux are not addressable directly using user-space tools
> and for the purpose of probing devices and matching ethernet/PHY/MDIO
> this property is not useful.  U-Boot on the other hand has the mdio cmd
> which requires unique names and also benefits from friendly names for
> MDIO buses.
> There are other potential solutions for the unique name problem, like
> creating something out of the full DT path of the device, or resolve
> absolute base address and use that.  These aren't as easy to use though.

Thanks for the clarification. Good enough for now :)

Regards,
Bin
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[U-Boot] [PATCH V2 1/4] imx: add module fuse support

[Peng Fan]

There are different parts from one SoC. Take i.MX6ULL for example,
some part might not have ENET, some might have; some might not have
USB, some might have. The information could be got from OCOTP,
to make one image support the different parts, we need runtime
disable linux kernel dts node and uboot driver probe if the
corresponding module not exists in the part.

Signed-off-by: Peng Fan 
---

V2:
 None

 arch/arm/include/asm/mach-imx/module_fuse.h | 127 +++
 arch/arm/include/asm/mach-imx/sys_proto.h   |   1 +
 arch/arm/mach-imx/Kconfig   |   7 +
 arch/arm/mach-imx/mx6/Makefile  |   1 +
 arch/arm/mach-imx/mx6/module_fuse.c | 322 
 5 files changed, 458 insertions(+)
 create mode 100644 arch/arm/include/asm/mach-imx/module_fuse.h
 create mode 100644 arch/arm/mach-imx/mx6/module_fuse.c

diff --git a/arch/arm/include/asm/mach-imx/module_fuse.h 
b/arch/arm/include/asm/mach-imx/module_fuse.h
new file mode 100644
index 00..6b93f0402e
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/module_fuse.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __MODULE_FUSE_H__
+#define __MODULE_FUSE_H__
+
+enum fuse_module_type {
+   MODULE_TSC,
+   MODULE_ADC1,
+   MODULE_ADC2,
+   MODULE_SIM1,
+   MODULE_SIM2,
+   MODULE_FLEXCAN1,
+   MODULE_FLEXCAN2,
+   MODULE_SPDIF,
+   MODULE_EIM,
+   MODULE_SD1,
+   MODULE_SD2,
+   MODULE_SD3,
+   MODULE_SD4,
+   MODULE_QSPI1,
+   MODULE_QSPI2,
+   MODULE_GPMI,
+   MODULE_APBHDMA,
+   MODULE_LCDIF,
+   MODULE_PXP,
+   MODULE_CSI,
+   MODULE_ENET1,
+   MODULE_ENET2,
+   MODULE_CAAM,
+   MODULE_USB_OTG1,
+   MODULE_USB_OTG2,
+   MODULE_SAI2,
+   MODULE_SAI3,
+   MODULE_BEE,
+   MODULE_UART1,
+   MODULE_UART2,
+   MODULE_UART3,
+   MODULE_UART4,
+   MODULE_UART5,
+   MODULE_UART6,
+   MODULE_UART7,
+   MODULE_UART8,
+   MODULE_PWM5,
+   MODULE_PWM6,
+   MODULE_PWM7,
+   MODULE_PWM8,
+   MODULE_ECSPI1,
+   MODULE_ECSPI2,
+   MODULE_ECSPI3,
+   MODULE_ECSPI4,
+   MODULE_ECSPI5,
+   MODULE_I2C1,
+   MODULE_I2C2,
+   MODULE_I2C3,
+   MODULE_I2C4,
+   MODULE_GPT1,
+   MODULE_GPT2,
+   MODULE_EPIT1,
+   MODULE_EPIT2,
+   MODULE_EPDC,
+   MODULE_ESAI,
+   MODULE_DCP,
+   MODULE_DCP_CRYPTO,
+};
+
+struct fuse_entry_desc {
+   enum fuse_module_type module;
+   const char *node_path;
+   u32 fuse_word_offset;
+   u32 fuse_bit_offset;
+   u32 status;
+};
+
+#if !IS_ENABLED(CONFIG_IMX_MODULE_FUSE)
+static inline u32 check_module_fused(enum fuse_module_type module)
+{
+   return 0;
+};
+
+static inline u32 esdhc_fused(u32 base_addr)
+{
+   return 0;
+};
+
+static inline u32 ecspi_fused(u32 base_addr)
+{
+   return 0;
+};
+
+static inline u32 uart_fused(u32 base_addr)
+{
+   return 0;
+};
+
+static inline u32 usb_fused(u32 base_addr)
+{
+   return 0;
+};
+
+static inline u32 qspi_fused(u32 base_addr)
+{
+   return 0;
+};
+
+static inline u32 i2c_fused(u32 base_addr)
+{
+   return 0;
+};
+
+static inline u32 enet_fused(u32 base_addr)
+{
+   return 0;
+};
+#else
+u32 check_module_fused(enum fuse_module_type module);
+u32 esdhc_fused(u32 base_addr);
+u32 ecspi_fused(u32 base_addr);
+u32 uart_fused(u32 base_addr);
+u32 usb_fused(u32 base_addr);
+u32 qspi_fused(u32 base_addr);
+u32 i2c_fused(u32 base_addr);
+u32 enet_fused(u32 base_addr);
+#endif
+#endif /* __MODULE_FUSE_H__ */
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h 
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 4925dd7894..6ebe5b5479 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -9,6 +9,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include "../arch-imx/cpu.h"
 
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index aeb5493488..a5b6f51ef0 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -27,6 +27,13 @@ config IMX_BOOTAUX
help
  bootaux [addr] to boot auxiliary core.
 
+config IMX_MODULE_FUSE
+   bool "i.MX Module Fuse"
+   depends on ARCH_MX6
+   help
+ i.MX module fuse to runtime disable some driver, including
+ Linux OS device node.
+
 config USE_IMXIMG_PLUGIN
bool "Use imximage plugin code"
depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX7ULP
diff --git a/arch/arm/mach-imx/mx6/Makefile b/arch/arm/mach-imx/mx6/Makefile
index 81e2913d14..7ea8f91e4f 100644
--- a/arch/arm/mach-imx/mx6/Makefile
+++ b/arch/arm/mach-imx/mx6/Makefile
@@ -6,6 +6,7 @@
 # (C) Copyright 2011 Freescale Semiconductor, Inc.
 
 obj-y  := soc.o clock.o
+obj-$(CONFIG_IMX_MODULE_FUSE) += module_fuse.o
 obj-$(CONFIG_SPL_BUILD) += ddr.o
 obj-$(CONFIG_MP) += mp.o
 obj-$(CONFIG_MX6UL_LI

[U-Boot] [PATCH V2 3/4] usb: mx6: add fuse check

[Peng Fan]

Add fuse check for USB. If the fuse indicates the module
will not work in the SoC, let's fail the initialization.

Signed-off-by: Peng Fan 
---

V2:
 Update commit and debug info

 drivers/usb/host/ehci-mx6.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index e9e6ed596d..60b4d1ceb3 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -353,6 +353,14 @@ int ehci_hcd_init(int index, enum usb_init_type init,
if (index > 3)
return -EINVAL;
 
+   if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
+   if (usb_fused((u32)ehci)) {
+   printf("SoC fuse indicates USB@0x%x is unavailable.\n",
+  (u32)ehci);
+   return  -ENODEV;
+   }
+   }
+
ret = ehci_mx6_common_init(ehci, index);
if (ret)
return ret;
@@ -549,6 +557,14 @@ static int ehci_usb_probe(struct udevice *dev)
struct ehci_hcor *hcor;
int ret;
 
+   if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
+   if (usb_fused((u32)ehci)) {
+   printf("SoC fuse indicates USB@0x%x is unavailable.\n",
+  (u32)ehci);
+   return -ENODEV;
+   }
+   }
+
priv->ehci = ehci;
priv->portnr = dev->seq;
priv->init_type = type;
-- 
2.16.4

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[U-Boot] [PATCH V2 2/4] i2c: mxc: add fuse check

[Peng Fan]

Add fuse check for I2C. If the fuse indicates the module
will not work in the SoC, let's fail the initialization.

Signed-off-by: Peng Fan 
---

V2:
 Update commit and debug info

 drivers/i2c/mxc_i2c.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 23119cce65..c5c1190af1 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -740,6 +741,14 @@ void bus_i2c_init(int index, int speed, int unused,
return;
}
 
+   if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
+   if (i2c_fused((u32)mxc_i2c_buses[index].base)) {
+   printf("SoC fuse indicates I2C@0x%x is unavailable.\n",
+  (u32)mxc_i2c_buses[index].base);
+   return;
+   }
+   }
+
/*
 * Warning: Be careful to allow the assignment to a static
 * variable here. This function could be called while U-Boot is
@@ -885,6 +894,14 @@ static int mxc_i2c_probe(struct udevice *bus)
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
 
+   if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
+   if (i2c_fused(addr)) {
+   printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
+  addr);
+   return -ENODEV;
+   }
+   }
+
i2c_bus->base = addr;
i2c_bus->index = bus->seq;
i2c_bus->bus = bus;
-- 
2.16.4

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[U-Boot] [PATCH V2 4/4] net: fec: add fuse check

[Peng Fan]

Add fuse check for fec. If the fuse indicates the module
will not work in the SoC, let's fail the initialization.

Signed-off-by: Peng Fan 
---

V2:
 Update commit and debug info

 drivers/net/fec_mxc.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 96e3ad9a1a..c666874b98 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1185,6 +1185,13 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int 
phy_id, uint32_t addr)
 #endif
int ret;
 
+   if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
+   if (enet_fused(addr)) {
+   printf("SoC fuse indicates Ethernet@0x%x is 
unavailable.\n", addr);
+   return -ENODEV;
+   }
+   }
+
 #ifdef CONFIG_FEC_MXC_MDIO_BASE
/*
 * The i.MX28 has two ethernet interfaces, but they are not equal.
@@ -1323,6 +1330,13 @@ static int fecmxc_probe(struct udevice *dev)
uint32_t start;
int ret;
 
+   if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
+   if (enet_fused((u32)priv->eth)) {
+   printf("SoC fuse indicates Ethernet@0x%x is 
unavailable.\n", (u32)priv->eth);
+   return -ENODEV;
+   }
+   }
+
if (IS_ENABLED(CONFIG_IMX8)) {
ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
if (ret < 0) {
-- 
2.16.4

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[U-Boot] [PULL] u-boot-stm32/master for v2019.10-rc1: u-boot-stm32-20190723

[Patrick DELAUNAY]

Hi Tom

please pull the STM32 related patches for v2019.10-rc1 = u-boot-stm32-20190723

Travis CI status:
https://travis-ci.org/patrickdelaunay/u-boot/builds/562084625
the warnings are not related to the patchsets.

Thanks,
Patrick

The following changes since commit 0de815356474912ef5bef9a69f0327a5a93bb2c2:

  Merge branch '2019-07-17-master-imports' (2019-07-18 11:31:37 -0400)

are available in the git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git 
tags/u-boot-stm32-20190723

for you to fetch changes up to 1f99eaff08f699472860c82480344e824a737d57:

  rtc: Add rtc driver for stm32mp1 (2019-07-22 11:04:52 +0200)


- add rtc driver for stm32mp1
- add remoteproc driver for stm32mp1
- use kernel qspi compatible string for stm32


Fabien Dessenne (6):
  dm: core: Introduce xxx_translate_dma_address()
  remoteproc: fix function headers
  remoteproc: add device_to_virt ops
  remoteproc: add elf file load support
  remoteproc: Introduce STM32 Cortex-M4 remoteproc driver
  MAINTAINERS: Add stm32 remoteproc driver

Patrice Chotard (4):
  ARM: dts: stm32: Use kernel qspi compatible string for stm32f7-uboot.dtsi
  ARM: dts: stm32: Use kernel qspi compatible string for 
stm32f469-disco-uboot.dtsi
  spi: stm32_qspi: Remove "st, stm32-qspi" compatible string
  doc: device-tree-bindings: alignment with v5.2-rc6 for spi-stm32-qspi.txt

Patrick Delaunay (3):
  configs: stm32mp15: enable stm32 remoteproc
  clk: stm32mp1: Add RTC clock entry
  rtc: Add rtc driver for stm32mp1

 MAINTAINERS |   1 +
 arch/arm/dts/stm32f469-disco-u-boot.dtsi|   2 +-
 arch/arm/dts/stm32f7-u-boot.dtsi|   2 +-
 arch/sandbox/dts/test.dts   |   4 +
 common/fdt_support.c|   6 ++
 configs/stm32mp15_basic_defconfig   |   3 +
 configs/stm32mp15_optee_defconfig   |   3 +
 configs/stm32mp15_trusted_defconfig |   3 +
 doc/device-tree-bindings/spi/spi-stm32-qspi.txt |  71 +-
 drivers/clk/clk_stm32mp1.c  |   9 +++
 drivers/core/of_addr.c  |   4 +
 drivers/core/ofnode.c   |   8 ++
 drivers/core/read.c |   5 ++
 drivers/remoteproc/Kconfig  |  10 +++
 drivers/remoteproc/Makefile |   3 +-
 drivers/remoteproc/rproc-elf-loader.c   | 106 
++
 drivers/remoteproc/sandbox_testproc.c   |  19 +
 drivers/remoteproc/stm32_copro.c| 257 
+++
 drivers/rtc/Kconfig |   6 ++
 drivers/rtc/Makefile|   1 +
 drivers/rtc/stm32_rtc.c | 323 

 drivers/spi/stm32_qspi.c|   1 -
 include/dm/of_addr.h|  18 +
 include/dm/ofnode.h |  16 +++-
 include/dm/read.h   |  20 -
 include/fdt_support.h   |  24 ++
 include/remoteproc.h| 146 
++--
 test/dm/remoteproc.c| 122 
++
 test/dm/test-fdt.c  |  12 +++
 29 files changed, 1127 insertions(+), 78 deletions(-)
 create mode 100644 drivers/remoteproc/rproc-elf-loader.c
 create mode 100644 drivers/remoteproc/stm32_copro.c
 create mode 100644 drivers/rtc/stm32_rtc.c
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[U-Boot] [PATCH] armv8: ls1028aqds: define ARCH_MISC_INIT to handle mux

[Pankaj Bansal]

define ARCH_MISC_INIT for LS1028AQDS platform to handle board
related mux.

Signed-off-by: Pankaj Bansal 
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 51d4acedac..3b171cf643 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1290,6 +1290,7 @@ config TARGET_LS1028AQDS
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
+   select ARCH_MISC_INIT
help
  Support for Freescale LS1028AQDS platform
  The LS1028A Development System (QDS) is a high-performance
-- 
2.17.1

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Re: [U-Boot] [PATCH V2 4/4] net: fec: add fuse check

[Joe Hershberger]

On Tue, Jul 23, 2019 at 2:21 AM Peng Fan  wrote:
>
> Add fuse check for fec. If the fuse indicates the module
> will not work in the SoC, let's fail the initialization.
>
> Signed-off-by: Peng Fan 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH v3 0/9] NXP LS1021A-TSN Board

[Joe Hershberger]

On Tue, Jul 23, 2019 at 1:08 AM Vladimir Oltean  wrote:
>
> Hi Joe,
>
> On Tue, 23 Jul 2019 at 03:15, Joe Hershberger  wrote:
> >
> > On Thu, Jul 18, 2019 at 4:33 PM Vladimir Oltean  wrote:
> > >
> > > This patchset adds initial support for the NXP LS1021A-TSN board,
> > > an evaluation platform built in partnership with VVDN/Argonboards
> > > for some IEEE 802.1 TSN features.
> > >
> > > It features a cleaned-up U-Boot board support taken from OpenIL,
> > > as well as an eTSEC migration to DM_ETH.  I picked up Bin Meng's
> > > patch that converts the LS1021A-TWR (different board, same SoC):
> > > https://lists.denx.de/pipermail/u-boot/2018-May/330096.html
> > > verified it on the LS1021A-TSN board I am submitting, and made a
> > > few adjustments where necessary.
> > >
> > > TODO items:
> > > - Make the eTSEC driver support fixed-link interfaces (necessary
> > >   for the enet2 <-> sja1105 internal port)
> > > - Add driver for SJA1105 switch
> > > - Potentially migrate the eTSEC MDIO bus driver to DM_MDIO and
> > >   expose the TBI PHY to mdio commands (useful for debugging),
> > >   once https://lists.denx.de/pipermail/u-boot/2019-June/371563.html
> > >   is merged.
> >
> > This series is merged at this point... are you wanting to do that
> > migration now or do it sometime later?
> >
>
> I think I would rather have these 9 patches merged first, now that
> they got reviewed, instead of reworking them again.

Sounds good.
Thanks,
-Joe

>
> > >
> > > Bin Meng (1):
> > >   arm: ls1021atwr: Convert to use driver model TSEC driver
> > >
> > > Jianchao Wang (1):
> > >   Add support for the NXP LS1021A-TSN board
> > >
> > > Vladimir Oltean (7):
> > >   net: tsec: Refactor the readout of the tbi-handle property
> > >   net: tsec: Fix offset of MDIO registers for DM_ETH
> > >   net: tsec: Reverse Christmas tree notation
> > >   net: tsec: Make errors visible
> > >   net: tsec: Common handling of MAC station address for DM_ETH
> > >   net: tsec: Change compatible strings to match Linux
> > >   configs: ls1021atwr: Fix distro_bootcmd for QSPI boot
> > >
> > >  arch/arm/Kconfig  |  14 +
> > >  arch/arm/cpu/armv7/ls102xa/cpu.c  |   2 +-
> > >  arch/arm/cpu/armv7/ls102xa/fdt.c  |  10 +
> > >  arch/arm/dts/Makefile |   2 +-
> > >  arch/arm/dts/ls1021a-tsn.dts  |  77 ++
> > >  arch/arm/dts/ls1021a-twr.dtsi |  32 +++
> > >  arch/arm/dts/ls1021a.dtsi |  30 +-
> > >  board/freescale/ls1021atsn/Kconfig|  18 ++
> > >  board/freescale/ls1021atsn/MAINTAINERS|   8 +
> > >  board/freescale/ls1021atsn/Makefile   |   3 +
> > >  board/freescale/ls1021atsn/README.rst |  97 +++
> > >  board/freescale/ls1021atsn/ls1021atsn.c   | 260 ++
> > >  board/freescale/ls1021atsn/ls102xa_pbi.cfg|  15 +
> > >  board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg |   8 +
> > >  board/freescale/ls1021atwr/ls1021atwr.c   |  38 ---
> > >  configs/ls1021atsn_qspi_defconfig |  79 ++
> > >  configs/ls1021atsn_sdcard_defconfig   |  91 ++
> > >  configs/ls1021atwr_nor_SECURE_BOOT_defconfig  |   2 +
> > >  configs/ls1021atwr_nor_defconfig  |   2 +
> > >  configs/ls1021atwr_nor_lpuart_defconfig   |   2 +
> > >  configs/ls1021atwr_qspi_defconfig |   2 +
> > >  ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig |   2 +
> > >  configs/ls1021atwr_sdcard_ifc_defconfig   |   2 +
> > >  configs/ls1021atwr_sdcard_qspi_defconfig  |   2 +
> > >  doc/device-tree-bindings/net/fsl-tsec-phy.txt |   4 +-
> > >  drivers/net/tsec.c|  59 ++--
> > >  include/configs/ls1021atsn.h  | 250 +
> > >  include/configs/ls1021atwr.h  |  30 +-
> > >  include/tsec.h|   4 +-
> > >  29 files changed, 1038 insertions(+), 107 deletions(-)
> > >  create mode 100644 arch/arm/dts/ls1021a-tsn.dts
> > >  create mode 100644 board/freescale/ls1021atsn/Kconfig
> > >  create mode 100644 board/freescale/ls1021atsn/MAINTAINERS
> > >  create mode 100644 board/freescale/ls1021atsn/Makefile
> > >  create mode 100644 board/freescale/ls1021atsn/README.rst
> > >  create mode 100644 board/freescale/ls1021atsn/ls1021atsn.c
> > >  create mode 100644 board/freescale/ls1021atsn/ls102xa_pbi.cfg
> > >  create mode 100644 board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg
> > >  create mode 100644 configs/ls1021atsn_qspi_defconfig
> > >  create mode 100644 configs/ls1021atsn_sdcard_defconfig
> > >  create mode 100644 include/configs/ls1021atsn.h
> > >
> > > --
> > > 2.17.1
> > >
> > > ___
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> > > https://lists.denx.de/listinfo/u-boot
>
> Regards,
> -Vladimir
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Re: [U-Boot] [PATCH 3/3] board: amlogic: add support for Odroid-N2

[Neil Armstrong]

Hi Anand,

On 22/07/2019 19:08, Anand Moon wrote:
> Hi Neil,
> 
> On Mon, 22 Jul 2019 at 16:00, Neil Armstrong  wrote:
>>
>> ODROID-N2 is a single board computer manufactured by Hardkernel Co. Ltd
>> with the following specifications:
>>
>>  - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
>>  - 4GB DDR4 SDRAM
>>  - Gigabit Ethernet
>>  - HDMI 2.1 4K/60Hz display
>>  - 40-pin GPIO header
>>  - 4 x USB 3.0 Host, 1 x USB OTG
>>  - eMMC, microSD
>>  - Infrared receiver
>>
>> The board directory is W400, the name of the Amlogic Reference Design
>> of Amlogic G12B with Gigabit boards, which will be used for similar
>> boards.
>>
>> Signed-off-by: Neil Armstrong 
>> ---
>>  board/amlogic/w400/MAINTAINERS  |   6 ++
>>  board/amlogic/w400/Makefile |   6 ++
>>  board/amlogic/w400/README.odroid-n2 | 130 
>>  board/amlogic/w400/README.w400  | 130 
>>  board/amlogic/w400/w400.c   |  18 
>>  configs/odroid-n2_defconfig |  56 
>>  6 files changed, 346 insertions(+)
>>  create mode 100644 board/amlogic/w400/MAINTAINERS
>>  create mode 100644 board/amlogic/w400/Makefile
>>  create mode 100644 board/amlogic/w400/README.odroid-n2
>>  create mode 100644 board/amlogic/w400/README.w400
>>  create mode 100644 board/amlogic/w400/w400.c
>>  create mode 100644 configs/odroid-n2_defconfig
>>
[..]

>> +
>> + > wget 
>> https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
>> + > wget 
>> https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
>> + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
>> + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
>> + > export 
>> PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
>> +
> 
> Should we checkout odroidn2-v2015.01 from Hardkernel repository.

Yes, you are right it's a typo !

> 
> 
>> + > DIR=odroid-c2
>> + > git clone --depth 1 \
>> +   https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \
>> +   $DIR
>> +

[..]

Thanks,
Neil
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Re: [U-Boot] [PATCH 1/3] ARM: dts: add support for Odroid-N2

[Neil Armstrong]

Hi Anand,

On 22/07/2019 19:07, Anand Moon wrote:
> Hi Neil,
> 
> On Mon, 22 Jul 2019 at 15:50, Neil Armstrong  wrote:
>>
>> Import HardKernel Odroid-N2 DT from Linux 5.3-rc1, commit 5f9e832c1370
>> ("Linus 5.3-rc1") based on an Amlogic G12B S922X SoC.
>>
>> Signed-off-by: Neil Armstrong 
>> ---
>>  arch/arm/dts/Makefile |   3 +-
>>  arch/arm/dts/meson-g12b-odroid-n2.dts | 386 ++
>>  arch/arm/dts/meson-g12b.dtsi  |  82 
>>  .../dt-bindings/sound/meson-g12a-tohdmitx.h   |  13 +
>>  4 files changed, 483 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/arm/dts/meson-g12b-odroid-n2.dts
>>  create mode 100644 arch/arm/dts/meson-g12b.dtsi
>>  create mode 100644 include/dt-bindings/sound/meson-g12a-tohdmitx.h
>>
> 
> I am getting following error while building this on mainline u-boot.

I forgot to explicit in the cover letter, but you'll need 
https://patchwork.ozlabs.org/patch/1134772/
before this serie.

Neil

> 
>   CHK include/config/uboot.release
>   UPD include/config/uboot.release
>   CHK include/generated/version_autogenerated.h
>   UPD include/generated/version_autogenerated.h
>   CHK include/generated/timestamp_autogenerated.h
>   UPD include/generated/timestamp_autogenerated.h
>   CHK include/generated/generic-asm-offsets.h
>   CHK include/generated/asm-offsets.h
>   HOSTCC  tools/mkenvimage.o
>   HOSTLD  tools/mkenvimage
>   HOSTCC  tools/dumpimage.o
>   HOSTLD  tools/dumpimage
>   HOSTCC  tools/mkimage.o
>   HOSTLD  tools/mkimage
>   CC  arch/arm/cpu/armv8/fwcall.o
>   LD  arch/arm/cpu/armv8/built-in.o
>   CC  cmd/version.o
>   LD  cmd/built-in.o
>   CC  common/main.o
>   LD  common/built-in.o
>   CC  lib/efi_loader/helloworld.o
>   CC  lib/efi_loader/efi_reloc.o
>   CC  lib/efi_loader/efi_freestanding.o
>   LD  lib/efi_loader/helloworld_efi.so
>   OBJCOPY lib/efi_loader/helloworld.efi
>   CC  lib/smbios.o
>   CC  lib/display_options.o
>   LD  lib/built-in.o
>   LD  u-boot
>   OBJCOPY u-boot.srec
>   OBJCOPY u-boot-nodtb.bin
> start=$(aarch64-linux-gnu-nm u-boot | grep __rel_dyn_start | cut -f 1
> -d ' '); end=$(aarch64-linux-gnu-nm u-boot | grep __rel_dyn_end | cut
> -f 1 -d ' '); tools/relocate-rela u-boot-nodtb.bin 0x0100 $start
> $end
>   DTC arch/arm/dts/meson-g12b-odroid-n2.dtb
> Error: arch/arm/dts/.meson-g12b-odroid-n2.dtb.pre.tmp:226.1-5 Label or
> path arb not found
> Error: arch/arm/dts/.meson-g12b-odroid-n2.dtb.pre.tmp:244.1-12 Label
> or path clkc_audio not found
> Error: arch/arm/dts/.meson-g12b-odroid-n2.dtb.pre.tmp:248.1-10 Label
> or path ext_mdio not found
> Error: arch/arm/dts/.meson-g12b-odroid-n2.dtb.pre.tmp:264.1-8 Label or
> path ethmac not found
> Error: arch/arm/dts/.meson-g12b-odroid-n2.dtb.pre.tmp:273.1-9 Label or
> path frddr_a not found
> Error: arch/arm/dts/.meson-g12b-odroid-n2.dtb.pre.tmp:277.1-9 Label or
> path frddr_b not found
> Error: arch/arm/dts/.meson-g12b-odroid-n2.dtb.pre.tmp:281.1-9 Label or
> path frddr_c not found
> Error: arch/arm/dts/.meson-g12b-odroid-n2.dtb.pre.tmp:313.1-4 Label or
> path ir not found
> Error: arch/arm/dts/.meson-g12b-odroid-n2.dtb.pre.tmp:320.1-11 Label
> or path sd_emmc_b not found
> Error: arch/arm/dts/.meson-g12b-odroid-n2.dtb.pre.tmp:338.1-11 Label
> or path sd_emmc_c not found
> Error: arch/arm/dts/.meson-g12b-odroid-n2.dtb.pre.tmp:356.1-9 Label or
> path tdmif_b not found
> Error: arch/arm/dts/.meson-g12b-odroid-n2.dtb.pre.tmp:360.1-10 Label
> or path tdmout_b not found
> Error: arch/arm/dts/.meson-g12b-odroid-n2.dtb.pre.tmp:364.1-10 Label
> or path tohdmitx not found
> FATAL ERROR: Syntax error parsing input tree
> make[2]: *** [scripts/Makefile.lib:308:
> arch/arm/dts/meson-g12b-odroid-n2.dtb] Error 1
> make[1]: *** [dts/Makefile:38: arch-dtbs] Error 2
> make: *** [Makefile:1045: dts/dt.dtb] Error 2
> 
> 

[..]
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Re: [U-Boot] [PATCH] mmc: relocate code comment

[Peng Fan]

> Subject: [PATCH] mmc: relocate code comment
> 
> The comment about init op being NULL used to be next to the NULL check
> code. Commit 8ca51e51c182 ("dm: mmc: Add a way to use driver model for
> MMC operations") separated the comment from the code. Put them back
> together.
> 
> Fixes: 8ca51e51c182 ("dm: mmc: Add a way to use driver model for MMC
> operations")
> Signed-off-by: Baruch Siach 
> ---
>  drivers/mmc/mmc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index
> c9aa13b409ac..eecc7d687e32 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -2819,12 +2819,12 @@ int mmc_start_init(struct mmc *mmc)
>MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
> 
>  #if !defined(CONFIG_MMC_BROKEN_CD)
> - /* we pretend there's no card when init is NULL */
>   no_card = mmc_getcd(mmc) == 0;
>  #else
>   no_card = 0;
>  #endif
>  #if !CONFIG_IS_ENABLED(DM_MMC)
> + /* we pretend there's no card when init is NULL */
>   no_card = no_card || (mmc->cfg->ops->init == NULL);  #endif
>   if (no_card) {

Reviewed-by: Peng Fan 

> --
> 2.20.1

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Re: [U-Boot] [PATCH] mmd: sdhci: fix non GPIO card detect

[Peng Fan]

+ Faiz

> Subject: [PATCH] mmd: sdhci: fix non GPIO card detect
> 
> Some SD cards do not assert the SDHCI_CARD_PRESENT bit. Only the
> SDHCI_CARD_DETECT_PIN_LEVEL is enabled. Consider that enough for card
> detect indication.
> 
> This fixes SD card access from SPL, since DM_GPIO is not available in SPL
> code.
> 
> Fixes: da18c62b6e6a ("mmc: sdhci: Implement SDHCI card detect")
> Cc: T Karthik Reddy 
> Cc: Michal Simek 
> Signed-off-by: Baruch Siach 
> ---
>  drivers/mmc/sdhci.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index
> 2779bca93f08..17a28181fcca 100644
> --- a/drivers/mmc/sdhci.c
> +++ b/drivers/mmc/sdhci.c
> @@ -683,7 +683,7 @@ int sdhci_get_cd(struct udevice *dev)
>   }
>  #endif
>   value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
> -SDHCI_CARD_PRESENT);
> +(SDHCI_CARD_PRESENT | SDHCI_CARD_DETECT_PIN_LEVEL));

Faiz, are you fine with this change?

Thanks,
Peng.


>   if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
>   return !value;
>   else
> --
> 2.20.1

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Re: [U-Boot] [PATCH] mmc: sdhci: fix chip detect gpio property name

[Peng Fan]

> Subject: [PATCH] mmc: sdhci: fix chip detect gpio property name
> 
> The standard property name for chip-detect gpio is "cd-gpios". All in-tree DT
> files use only this name.
> 
> Fixes: 451931ea700 ("mmc: sdhci: Read cd-gpio from devicetree")
> Cc: T Karthik Reddy 
> Cc: Michal Simek 
> Signed-off-by: Baruch Siach 
> ---
>  drivers/mmc/sdhci.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index
> 0a0770cc2035..2779bca93f08 100644
> --- a/drivers/mmc/sdhci.c
> +++ b/drivers/mmc/sdhci.c
> @@ -623,7 +623,7 @@ static int sdhci_init(struct mmc *mmc)  #if
> CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
>   struct udevice *dev = mmc->dev;
> 
> - gpio_request_by_name(dev, "cd-gpio", 0,
> + gpio_request_by_name(dev, "cd-gpios", 0,
>&host->cd_gpio, GPIOD_IS_IN);
>  #endif
> 

Reviewed-by: Peng Fan 
> --
> 2.20.1

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Re: [U-Boot] [PATCH 1/2] rockchip: Fix TPL build without CONFIG_TPL_SERIAL_SUPPORT【请注意，邮件由u-boot-boun...@lists.denx.de代发】

[Kever Yang]

On 2019/7/21 上午11:30, Kever Yang wrote:

Hi Chris,


On 2019/7/19 下午9:23, Chris Webb wrote:

If CONFIG_DEBUG_UART is set but CONFIG_TPL_SERIAL_SUPPORT is not, the
serial output should be available in SPL and full U-Boot, but not built
in TPL. However, the rockchip tpl.c instead fails to compile with
undefined references to the debug UART.

Instead, initialise the debug UART and print the TPL banner only if both
CONFIG_DEBUG_UART and CONFIG_TPL_SERIAL_SUPPORT are set.

Signed-off-by: 



Applied to u-boot-rockchip, thanks!

Reviewed-by: Kever Yang 

Thanks,
 - Kever

---
  arch/arm/mach-rockchip/tpl.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
index 0ff2a197ed..5df88bddeb 100644
--- a/arch/arm/mach-rockchip/tpl.c
+++ b/arch/arm/mach-rockchip/tpl.c
@@ -44,7 +44,7 @@ void board_init_f(ulong dummy)
  struct udevice *dev;
  int ret;
  -#ifdef CONFIG_DEBUG_UART
+#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT)
  /*
   * Debug UART can be used from here if required:
   *




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Re: [U-Boot] [PATCH] rockchip: sdhci: Fix sdhci mmc driver probe abort

[Kever Yang]

On 2019/7/19 下午11:04, Jagan Teki wrote:

On Fri, Jul 19, 2019 at 3:38 PM Kever Yang  wrote:

This patch fix mmc driver abort caused by below patch:
3d296365e4 mmc: sdhci: Add support for sdhci-caps-mask

After the patch sdhci_setup_cfg() access to host->mmc->dev,
so we have to do init before make the call to the function()

Signed-off-by: Kever Yang 
---

Tested-by: Jagan Teki  # Rockpro64,
NanoPi-NE04/M4, NanoPC-T4, OrangePI



Applied to u-boot-rockchip, thanks!


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Re: [U-Boot] [PATCH 2/2] rockchip: TPL banner should depend on CONFIG_TPL_BANNER_PRINT【请注意，邮件由u-boot-boun...@lists.denx.de代发】

[Kever Yang]

On 2019/7/21 上午11:30, Kever Yang wrote:

Hi Chris,


On 2019/7/19 下午9:23, Chris Webb wrote:

The generic code in common/spl/spl.c allows TPL/SPL banners to be
silenced by unsetting CONFIG_TPL_BANNER_PRINT or CONFIG_SPL_BANNER_PRINT
respectively. However, arch/arm/mach-rockchip/tpl.c prints this banner
unconditionally.

Fix the rockchip-specific tpl.c so that the TPL banner depends on
CONFIG_TPL_BANNER_PRINT in the same way as the generic code.

Signed-off-by: 




Applied to u-boot-rockchip, thanks!


Reviewed-by: Kever Yang 

Thanks,
 - Kever


---
  arch/arm/mach-rockchip/tpl.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
index 5df88bddeb..55f6e922d0 100644
--- a/arch/arm/mach-rockchip/tpl.c
+++ b/arch/arm/mach-rockchip/tpl.c
@@ -54,8 +54,10 @@ void board_init_f(ulong dummy)
   * printascii("string");
   */
  debug_uart_init();
+#ifdef CONFIG_TPL_BANNER_PRINT
  printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
  U_BOOT_TIME ")\n");
+#endif
  #endif
  ret = spl_early_init();
  if (ret) {




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Re: [U-Boot] [PATCH v3 1/2] rockchip: make_fit_atf.py: Eliminate pyelftools dependency【请注意，邮件由u-boot-boun...@lists.denx.de代发】

[Kever Yang]

On 2019/7/17 下午6:47, Kever Yang wrote:


On 2019/7/17 上午3:52, Chris Webb wrote:

make_fit_aft.py depends on the non-standard library pyelftools to pull
out PT_LOAD segments from ELF files. However, this is as easy to do
manually, without imposing the extra dependency on users.

Structures in the ELF file are unpacked into variables named to exactly
match the ELF spec to ensure the destructuring code is reasonably
self-documenting.

Signed-off-by: Chris Webb 



Reviewed-by: Kever Yang 


Applied to u-boot-rockchip, thanks!


Thanks,
 - Kever

---
  arch/arm/mach-rockchip/make_fit_atf.py | 75 +++---
  1 file changed, 32 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mach-rockchip/make_fit_atf.py 
b/arch/arm/mach-rockchip/make_fit_atf.py

index db0ae96ca8..b9a1988298 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -13,16 +13,7 @@ import os
  import sys
  import getopt
  import logging
-
-# pip install pyelftools
-from elftools.elf.elffile import ELFFile
-
-ELF_SEG_P_TYPE = 'p_type'
-ELF_SEG_P_PADDR = 'p_paddr'
-ELF_SEG_P_VADDR = 'p_vaddr'
-ELF_SEG_P_OFFSET = 'p_offset'
-ELF_SEG_P_FILESZ = 'p_filesz'
-ELF_SEG_P_MEMSZ = 'p_memsz'
+import struct
    DT_HEADER = """
  /*
@@ -118,33 +109,19 @@ def append_conf_node(file, dtbs, segments):
  file.write('\n')
    def generate_atf_fit_dts_uboot(fit_file, uboot_file_name):
-    num_load_seg = 0
-    p_paddr = 0x
-    with open(uboot_file_name, 'rb') as uboot_file:
-    uboot = ELFFile(uboot_file)
-    for i in range(uboot.num_segments()):
-    seg = uboot.get_segment(i)
-    if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-    p_paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-    num_load_seg = num_load_seg + 1
-
-    assert (p_paddr != 0x and num_load_seg == 1)
-
+    segments = unpack_elf(uboot_file_name)
+    if len(segments) != 1:
+    raise ValueError("Invalid u-boot ELF image '%s'" % 
uboot_file_name)

+    index, entry, p_paddr, data = segments[0]
  fit_file.write(DT_UBOOT % p_paddr)
    def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, 
dtbs_file_name):

-    with open(bl31_file_name, 'rb') as bl31_file:
-    bl31 = ELFFile(bl31_file)
-    elf_entry = bl31.header['e_entry']
-    segments = bl31.num_segments()
-    for i in range(segments):
-    seg = bl31.get_segment(i)
-    if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-    paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-    append_bl31_node(fit_file, i + 1, paddr, elf_entry)
+    segments = unpack_elf(bl31_file_name)
+    for index, entry, paddr, data in segments:
+    append_bl31_node(fit_file, index + 1, paddr, entry)
  append_fdt_node(fit_file, dtbs_file_name)
  fit_file.write(DT_IMAGES_NODE_END)
-    append_conf_node(fit_file, dtbs_file_name, segments)
+    append_conf_node(fit_file, dtbs_file_name, len(segments))
    def generate_atf_fit_dts(fit_file_name, bl31_file_name, 
uboot_file_name, dtbs_file_name):

  # Generate FIT script for ATF image.
@@ -162,17 +139,29 @@ def generate_atf_fit_dts(fit_file_name, 
bl31_file_name, uboot_file_name, dtbs_fi

  fit_file.close()
    def generate_atf_binary(bl31_file_name):
-    with open(bl31_file_name, 'rb') as bl31_file:
-    bl31 = ELFFile(bl31_file)
-
-    num = bl31.num_segments()
-    for i in range(num):
-    seg = bl31.get_segment(i)
-    if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-    paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-    file_name = 'bl31_0x%08x.bin' % paddr
-    with open(file_name, "wb") as atf:
-    atf.write(seg.data())
+    for index, entry, paddr, data in unpack_elf(bl31_file_name):
+    file_name = 'bl31_0x%08x.bin' % paddr
+    with open(file_name, "wb") as atf:
+    atf.write(data)
+
+def unpack_elf(filename):
+    with open(filename, 'rb') as file:
+    elf = file.read()
+    if elf[0:7] != b'\x7fELF\x02\x01\x01' or elf[18:20] != b'\xb7\x00':
+    raise ValueError("Invalid arm64 ELF file '%s'" % filename)
+
+    e_entry, e_phoff = struct.unpack_from('<2Q', elf, 0x18)
+    e_phentsize, e_phnum = struct.unpack_from('<2H', elf, 0x36)
+    segments = []
+
+    for index in range(e_phnum):
+    offset = e_phoff + e_phentsize * index
+    p_type, p_flags, p_offset = struct.unpack_from('offset)

+    if p_type == 1: # PT_LOAD
+    p_paddr, p_filesz = struct.unpack_from('<2Q', elf, 
offset + 0x18)

+    p_data = elf[p_offset:p_offset + p_filesz]
+    segments.append((index, e_entry, p_paddr, p_data))
+    return segments
    def main():
  uboot_elf = "./u-boot"



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Re: [U-Boot] [PATCH v3 2/2] rockchip: Remove obsolete references to pyelftools【请注意，邮件由u-boot-boun...@lists.denx.de代发】 pyelftools

[Kever Yang]

On 2019/7/17 下午6:39, Kever Yang wrote:


On 2019/7/17 上午3:53, Chris Webb wrote:

make_fit_atf.py no longer requires pyelftools, and nothing else in the
rockchip build requires it either, so remove references to installing it
from the documentation.

Signed-off-by: Chris Webb 



Reviewed-by: Kever Yang 


Applied to u-boot-rockchip, thanks!


Thanks,
 - Kever

---
  board/rockchip/evb_rk3399/README | 6 --
  doc/README.rockchip  | 4 
  2 files changed, 10 deletions(-)

diff --git a/board/rockchip/evb_rk3399/README 
b/board/rockchip/evb_rk3399/README

index 6469821987..ea3258cf37 100644
--- a/board/rockchip/evb_rk3399/README
+++ b/board/rockchip/evb_rk3399/README
@@ -35,12 +35,6 @@ Get the Source and prebuild binary
    > git clone https://github.com/rockchip-linux/rkbin.git
    > git clone https://github.com/rockchip-linux/rkdeveloptool.git
  -Get some prerequisites
-==
-
-You need the Python elftools.elf.elffile library for make_fit_atf.py 
to work:

-
-  > sudo apt-get install python-pyelftools
    Compile ATF
  ===
diff --git a/doc/README.rockchip b/doc/README.rockchip
index 02e2497b15..8ccbb87264 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -123,10 +123,6 @@ For example:
   Option 2: Package the image with SPL:
  -   - We need the Python elftools.elf.elffile library for 
make_fit_atf.py to work

-
- => sudo apt-get install python-pyelftools
-
 - Export cross compiler path for aarch64
   - Compile ATF



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Re: [U-Boot] [RFC PATCH 01/11] fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL

[Bin Meng]

On Mon, Jul 22, 2019 at 2:00 AM Lukas Auer
 wrote:
>
> The current preprocessor logic prevents CONFIG_OF_PRIOR_STAGE from being
> used in U-Boot SPL. Change the logic to also make it available in U-Boot
> SPL.
>
> Signed-off-by: Lukas Auer 
> ---
>
>  include/fdtdec.h | 2 +-
>  lib/fdtdec.c | 6 ++
>  2 files changed, 3 insertions(+), 5 deletions(-)
>

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Re: [U-Boot] [RFC PATCH 03/11] spl: fit: use U-Boot device tree when FIT image has no device tree

[Bin Meng]

On Mon, Jul 22, 2019 at 2:00 AM Lukas Auer
 wrote:
>
> As part of the SPL FIT boot flow, the device tree is appended to U-Boot
> proper. The device tree is used to record information on the loadables
> to make them available to the SPL framework and U-Boot proper. Depending
> on the U-Boot device tree provider, the FIT image might not include a
> device tree. Information on the loadables is missing in this case.
>
> When booting via firmware bundled with the FIT image, U-Boot SPL loads
> the firmware binary and U-Boot proper before starting the firmware. The
> firmware, in turn, is responsible for starting U-Boot proper.
> Information on the memory location of the U-Boot proper loadable must be
> available to the SPL framework so that it can be passed to the firmware
> binary. To support this use case when no device tree is found in the FIT
> image, fall back to the U-Boot device tree in this situation.
>
> At the same time, update the comment to remove the note that the
> destination address must be aligned to ARCH_DMA_MINALIGN. Alignment is
> only required as an intermediate step when reading external data. This
> is automatically handled by spl_fit_append_fdt(). After reading the
> external data, it is copied to the specified address, which does not
> have to be aligned to ARCH_DMA_MINALIGN.
>
> Signed-off-by: Lukas Auer 
> ---
>
>  common/spl/spl_fit.c | 37 -
>  1 file changed, 24 insertions(+), 13 deletions(-)
>

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Re: [U-Boot] [RFC PATCH 02/11] Makefile: support building SPL FIT images without device trees

[Bin Meng]

On Mon, Jul 22, 2019 at 2:00 AM Lukas Auer
 wrote:
>
> When building a U-Boot FIT image, the device trees specified by the
> board are unconditionally built for inclusion in the FIT image. However,
> not all device tree providers, such as CONFIG_OF_PRIOR_STAGE, require a
> device tree to be built and bundled with the U-Boot binary. They rely on
> other mechanisms to provide the device tree to U-Boot. Compilation on
> boards with these device tree providers fails, because they do not
> specify a device tree.
>
> Change the makefile rules to conditionally build the device trees if
> either CONFIG_OF_SEPARATE or CONFIG_OF_EMBED is selected as device tree
> provider.
>
> Signed-off-by: Lukas Auer 
> ---
>
>  Makefile | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>

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Re: [U-Boot] [RFC PATCH 04/11] riscv: add run mode configuration for SPL

[Bin Meng]

On Mon, Jul 22, 2019 at 2:00 AM Lukas Auer
 wrote:
>
> U-Boot SPL can be run in a different privilege mode from U-Boot proper.
> Add new configuration entries for SPL to allow the run mode to be
> configured independently of U-Boot proper.
>
> Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE
> configuration symbols to also cover the SPL equivalents. Ensure that
> files compatible with only one privilege mode are not included in builds
> targeting an incompatible privilege mode.
>
> Signed-off-by: Lukas Auer 
> ---
>
>  arch/riscv/Kconfig| 33 ++-
>  arch/riscv/cpu/ax25/Kconfig   |  6 +++---
>  arch/riscv/cpu/cpu.c  |  6 +++---
>  arch/riscv/cpu/generic/Kconfig|  2 +-
>  arch/riscv/cpu/start.S|  6 +++---
>  arch/riscv/include/asm/encoding.h |  2 +-
>  arch/riscv/lib/Makefile   |  7 +--
>  7 files changed, 44 insertions(+), 18 deletions(-)
>

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Re: [U-Boot] [RFC PATCH 05/11] spl: support booting via RISC-V OpenSBI

[Bin Meng]

On Mon, Jul 22, 2019 at 2:00 AM Lukas Auer
 wrote:
>
> RISC-V OpenSBI is an open-source implementation of the RISC-V Supervisor
> Binary Interface (SBI) specification. It is required by Linux and U-Boot
> running in supervisor mode. This patch adds support for booting via the
> OpenSBI FW_DYNAMIC firmware.
>
> In this configuration, U-Boot SPL starts in machine mode. After loading
> OpenSBI and U-Boot proper, it will start OpenSBI. All necessary
> parameters are generated by U-Boot SPL and passed to OpenSBI. U-Boot
> proper is started in supervisor mode by OpenSBI. Support for OpenSBI is
> enabled with CONFIG_SPL_OPENSBI. An additional configuration entry,
> CONFIG_SPL_OPENSBI_LOAD_ADDR, is used to specify the load address of the
> OpenSBI firmware binary. It is not used directly in U-Boot and instead
> is intended to make the value available to scripts such as FIT
> configuration generators.
>
> The header file include/opensbi.h is based on header files from the
> OpenSBI project. They are recent, as of commit bae54f764570 ("firmware:
> Add fw_dynamic firmware").
>
> Signed-off-by: Lukas Auer 
> ---
>
>  common/image.c   |  1 +
>  common/spl/Kconfig   | 17 
>  common/spl/Makefile  |  1 +
>  common/spl/spl.c |  6 +++
>  common/spl/spl_opensbi.c | 85 
>  include/image.h  |  1 +
>  include/opensbi.h| 40 +++
>  include/spl.h|  5 +++
>  8 files changed, 156 insertions(+)
>  create mode 100644 common/spl/spl_opensbi.c
>  create mode 100644 include/opensbi.h
>

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Re: [U-Boot] [RFC PATCH 06/11] riscv: add SPL support

[Bin Meng]

On Mon, Jul 22, 2019 at 2:00 AM Lukas Auer
 wrote:
>
> U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly
> jumping to the image and via OpenSBI firmware. In the first case, both
> U-Boot SPL and proper must be compiled to run in the same privilege
> mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine
> mode and U-Boot proper for supervisor mode.
>
> To be able to use SPL, boards have to provide a supported SPL boot
> device.
>
> Signed-off-by: Lukas Auer 
> ---
>
>  arch/Kconfig   |  6 +++
>  arch/riscv/Kconfig |  3 ++
>  arch/riscv/cpu/generic/Kconfig |  3 ++
>  arch/riscv/cpu/start.S | 23 +-
>  arch/riscv/cpu/u-boot-spl.lds  | 82 ++
>  arch/riscv/include/asm/spl.h   | 31 +
>  arch/riscv/lib/Makefile|  1 +
>  arch/riscv/lib/spl.c   | 48 
>  8 files changed, 196 insertions(+), 1 deletion(-)
>  create mode 100644 arch/riscv/cpu/u-boot-spl.lds
>  create mode 100644 arch/riscv/include/asm/spl.h
>  create mode 100644 arch/riscv/lib/spl.c
>

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Re: [U-Boot] [RFC PATCH 08/11] riscv: add a generic FIT generator script

[Bin Meng]

On Mon, Jul 22, 2019 at 2:01 AM Lukas Auer
 wrote:
>
> Add a generic FIT generator script for RISC-V to generate images
> containing U-Boot, OpenSBI FW_DYNAMIC firmware, and optionally one or
> more device trees. The location of the OpenSBI firmware binary can be
> specified with the OPENSBI environment variable. By default, it is
> assumed to be "fw_dynamic.bin" and located in the U-Boot top-level.
> Device trees are passed as arguments to the generator script. A separate
> configuration entry is created for each device tree.
>
> The load addresses of U-Boot and OpenSBI are parsed from the U-Boot
> configuration. They can be overwritten with the UBOOT_LOAD_ADDR and
> OPENSBI_LOAD_ADDR environment variables.
>
> The script is based on the i.MX (arch/arm/mach-imx/mkimage_fit_atf.sh)
> and Allwinner sunxi (board/sunxi/mksunxi_fit_atf.sh) FIT generator
> scripts.
>
> Signed-off-by: Lukas Auer 
> ---
>
>  arch/riscv/lib/mkimage_fit_opensbi.sh | 100 ++
>  1 file changed, 100 insertions(+)
>  create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh
>

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Re: [U-Boot] [RFC PATCH 07/11] riscv: support SPL stack and global data relocation

[Bin Meng]

On Mon, Jul 22, 2019 at 2:00 AM Lukas Auer
 wrote:
>
> To support relocation of the stack and global data on RISC-V, the
> secondary harts must be notified of the change using IPIs. We can reuse
> the hart relocation code for this purpose. It uses global data to store
> the new stack pointer and global data pointer for the secondary harts.
> This means that we cannot update the global data pointer of the main
> hart in spl_relocate_stack_gd(), because the secondary harts have not
> yet been relocated at this point. It is updated after the secondary
> harts have been notified.
>
> Signed-off-by: Lukas Auer 
> ---
>
>  arch/riscv/cpu/start.S | 35 ++-
>  common/spl/spl.c   |  2 +-
>  2 files changed, 35 insertions(+), 2 deletions(-)
>

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Re: [U-Boot] [RFC PATCH 11/11] doc: update QEMU RISC-V documentation

[Bin Meng]

On Mon, Jul 22, 2019 at 2:01 AM Lukas Auer
 wrote:
>
> The available defconfigs for RISC-V QEMU have changed. We now have
> configurations to compile U-Boot to run in supervisor mode and for
> U-Boot SPL. Update the QEMU RISC-V documentation to reflect these
> changes.
>
> Signed-off-by: Lukas Auer 
> ---
>
>  doc/README.qemu-riscv | 56 ++-
>  1 file changed, 55 insertions(+), 1 deletion(-)
>

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Re: [U-Boot] [RFC PATCH 10/11] riscv: qemu: add SPL configuration

[Bin Meng]

On Mon, Jul 22, 2019 at 2:01 AM Lukas Auer
 wrote:
>
> Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL
> enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The
> configurations are meant to help the development of SPL on RISC-V.
>
> The configurations enable RAM as the only SPL boot device. Images must
> be loaded at address 0x8020. In the default boot flow, U-Boot SPL
> starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot
> proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is
> then started in supervisor mode by OpenSBI.
>
> Signed-off-by: Lukas Auer 
> ---
>
>  board/emulation/qemu-riscv/Kconfig  | 10 ++
>  board/emulation/qemu-riscv/MAINTAINERS  |  2 ++
>  board/emulation/qemu-riscv/qemu-riscv.c | 17 +
>  configs/qemu-riscv32_spl_defconfig  | 11 +++
>  configs/qemu-riscv64_spl_defconfig  | 12 
>  include/configs/qemu-riscv.h| 14 ++
>  6 files changed, 66 insertions(+)
>  create mode 100644 configs/qemu-riscv32_spl_defconfig
>  create mode 100644 configs/qemu-riscv64_spl_defconfig
>

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Re: [U-Boot] [RFC PATCH 09/11] riscv: set default FIT generator script and build target for SPL builds

[Bin Meng]

On Mon, Jul 22, 2019 at 2:01 AM Lukas Auer
 wrote:
>
> Now that we have a generic FIT generator script for RISC-V, set it as
> the default. To also build the FIT image by default, set the default
> build target to "u-boot.itb" if CONFIG_SPL_LOAD_FIT is enabled.
>
> Signed-off-by: Lukas Auer 
> ---
>
>  Kconfig | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>

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Re: [U-Boot] [PATCH] mmd: sdhci: fix non GPIO card detect

[Faiz Abbas]

Hi,

On 23/07/19 1:30 PM, Peng Fan wrote:
> + Faiz
> 
>> Subject: [PATCH] mmd: sdhci: fix non GPIO card detect
>>
>> Some SD cards do not assert the SDHCI_CARD_PRESENT bit. Only the
>> SDHCI_CARD_DETECT_PIN_LEVEL is enabled. Consider that enough for card
>> detect indication.
>>
>> This fixes SD card access from SPL, since DM_GPIO is not available in SPL
>> code.
>>
>> Fixes: da18c62b6e6a ("mmc: sdhci: Implement SDHCI card detect")
>> Cc: T Karthik Reddy 
>> Cc: Michal Simek 
>> Signed-off-by: Baruch Siach 
>> ---
>>  drivers/mmc/sdhci.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index
>> 2779bca93f08..17a28181fcca 100644
>> --- a/drivers/mmc/sdhci.c
>> +++ b/drivers/mmc/sdhci.c
>> @@ -683,7 +683,7 @@ int sdhci_get_cd(struct udevice *dev)
>>  }
>>  #endif
>>  value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
>> -   SDHCI_CARD_PRESENT);
>> +   (SDHCI_CARD_PRESENT | SDHCI_CARD_DETECT_PIN_LEVEL));
> 
> Faiz, are you fine with this change?
> 

Not really. The spec is pretty clear that DETECT_PIN_LEVEL is not to be
trusted. Also how does the CARD_PRESENT assertion depend on the SD card
you use? Are you normally muxing the SDCD line to the IP (for hardware
to detect) or are you connecting it as a gpio which software must detect?

Thanks,
Faiz
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Re: [U-Boot] [PATCH] mmd: sdhci: fix non GPIO card detect

[Baruch Siach]

Hi Faiz,

On Tue, Jul 23, 2019 at 02:27:28PM +0530, Faiz Abbas wrote:
> On 23/07/19 1:30 PM, Peng Fan wrote:
> > + Faiz
> > 
> >> Subject: [PATCH] mmd: sdhci: fix non GPIO card detect
> >>
> >> Some SD cards do not assert the SDHCI_CARD_PRESENT bit. Only the
> >> SDHCI_CARD_DETECT_PIN_LEVEL is enabled. Consider that enough for card
> >> detect indication.
> >>
> >> This fixes SD card access from SPL, since DM_GPIO is not available in SPL
> >> code.
> >>
> >> Fixes: da18c62b6e6a ("mmc: sdhci: Implement SDHCI card detect")
> >> Cc: T Karthik Reddy 
> >> Cc: Michal Simek 
> >> Signed-off-by: Baruch Siach 
> >> ---
> >>  drivers/mmc/sdhci.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index
> >> 2779bca93f08..17a28181fcca 100644
> >> --- a/drivers/mmc/sdhci.c
> >> +++ b/drivers/mmc/sdhci.c
> >> @@ -683,7 +683,7 @@ int sdhci_get_cd(struct udevice *dev)
> >>}
> >>  #endif
> >>value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
> >> - SDHCI_CARD_PRESENT);
> >> + (SDHCI_CARD_PRESENT | SDHCI_CARD_DETECT_PIN_LEVEL));
> > 
> > Faiz, are you fine with this change?
> 
> Not really. The spec is pretty clear that DETECT_PIN_LEVEL is not to be
> trusted. Also how does the CARD_PRESENT assertion depend on the SD card
> you use? Are you normally muxing the SDCD line to the IP (for hardware
> to detect) or are you connecting it as a gpio which software must detect?

I tested SanDisk 8GB SD card, class 10, UHS1, on Armada 388 based SolidRun 
Clearfog Base. The SDHCI_PRESENT_STATE register consistently reads 0x01f6, 
that is, CARD_PRESENT is disabled, DETECT_PIN_LEVEL is enabled.

The SD card-detect GPIO is present at the hardware level, but it is not 
accessible from SPL code because there is currently no SPL_DM_GPIO. The main 
U-Boot image detects the SD card correctly (once the other MMC patches I 
posted are applied).

Without this patch boot from SD card is broken. What is the right fix then?

baruch

-- 
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Re: [U-Boot] Remote code execution vulnerabilities in U-Boot's NFS and other IP parsing code

[Simon Goldschmidt]

On Tue, Jul 23, 2019 at 1:09 AM Fermín Serna  wrote:
>
> Hello,
>
> Find attached more information about 13 vulnerabilities we found at
> U-Boot and its NFS and networking code. Also, find attached a proposed
> quick patch that should serve as a first initial one and should
> probably go through iterations of code review.
>
> Please note, these vulnerabilities are not patched yet at the source
> repository. Tom Rini (U-boot's master custodian) requested the
> attached report to be published at this mailing list. At this time,
> and because of this email, we consider these vulnerabilities public.

Would you mind sending the patch again as plain text mail so it can undergo a
proper review process on this list?

Regards,
Simon

>
> For reference, MITRE has issued CVEs for the vulnerabilities:
> CVE-2019-14192, CVE-2019-14193, CVE-2019-14194, CVE-2019-14195,
> CVE-2019-14196, CVE-2019-14197, CVE-2019-14198, CVE-2019-14199,
> CVE-2019-14200, CVE-2019-14201, CVE-2019-14202, CVE-2019-14203 and
> CVE-2019-14204
>
> Best regards,
> --
> Fermin
> Semmle Security Research Team
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[U-Boot] [PATCH] mmc: sti_sdhci: Fix sdhci_setup_cfg() call.

[Patrice Chotard]

host->mmc and host->mmc->dev must be set before calling
sdhci_setup_cfg() to avoid hang during mmc initialization.

Thanks to commit 3d296365e4e8
("mmc: sdhci: Add support for sdhci-caps-mask") which put
this issue into evidence.

Signed-off-by: Patrice Chotard 
---

 drivers/mmc/sti_sdhci.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c
index 8ed47e113d..c7f1947edd 100644
--- a/drivers/mmc/sti_sdhci.c
+++ b/drivers/mmc/sti_sdhci.c
@@ -97,14 +97,14 @@ static int sti_sdhci_probe(struct udevice *dev)
   SDHCI_QUIRK_NO_HISPD_BIT;
 
host->host_caps = MMC_MODE_DDR_52MHz;
+   host->mmc = &plat->mmc;
+   host->mmc->dev = dev;
 
ret = sdhci_setup_cfg(&plat->cfg, host, 5000, 40);
if (ret)
return ret;
 
-   host->mmc = &plat->mmc;
host->mmc->priv = host;
-   host->mmc->dev = dev;
upriv->mmc = host->mmc;
 
return sdhci_probe(dev);
-- 
2.17.1

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Re: [U-Boot] [PATCH] mmd: sdhci: fix non GPIO card detect

[Faiz Abbas]

Hi Baruch,

On 23/07/19 2:39 PM, Baruch Siach wrote:
> Hi Faiz,
> 
> On Tue, Jul 23, 2019 at 02:27:28PM +0530, Faiz Abbas wrote:
>> On 23/07/19 1:30 PM, Peng Fan wrote:
>>> + Faiz
>>>
 Subject: [PATCH] mmd: sdhci: fix non GPIO card detect

 Some SD cards do not assert the SDHCI_CARD_PRESENT bit. Only the
 SDHCI_CARD_DETECT_PIN_LEVEL is enabled. Consider that enough for card
 detect indication.

 This fixes SD card access from SPL, since DM_GPIO is not available in SPL
 code.

 Fixes: da18c62b6e6a ("mmc: sdhci: Implement SDHCI card detect")
 Cc: T Karthik Reddy 
 Cc: Michal Simek 
 Signed-off-by: Baruch Siach 
 ---
  drivers/mmc/sdhci.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index
 2779bca93f08..17a28181fcca 100644
 --- a/drivers/mmc/sdhci.c
 +++ b/drivers/mmc/sdhci.c
 @@ -683,7 +683,7 @@ int sdhci_get_cd(struct udevice *dev)
}
  #endif
value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 - SDHCI_CARD_PRESENT);
 + (SDHCI_CARD_PRESENT | SDHCI_CARD_DETECT_PIN_LEVEL));
>>>
>>> Faiz, are you fine with this change?
>>
>> Not really. The spec is pretty clear that DETECT_PIN_LEVEL is not to be
>> trusted. Also how does the CARD_PRESENT assertion depend on the SD card
>> you use? Are you normally muxing the SDCD line to the IP (for hardware
>> to detect) or are you connecting it as a gpio which software must detect?
> 
> I tested SanDisk 8GB SD card, class 10, UHS1, on Armada 388 based SolidRun 
> Clearfog Base. The SDHCI_PRESENT_STATE register consistently reads 
> 0x01f6, 
> that is, CARD_PRESENT is disabled, DETECT_PIN_LEVEL is enabled.
> 
> The SD card-detect GPIO is present at the hardware level, but it is not 
> accessible from SPL code because there is currently no SPL_DM_GPIO. The main 
> U-Boot image detects the SD card correctly (once the other MMC patches I 
> posted are applied).
> 
> Without this patch boot from SD card is broken. What is the right fix then?
> 

There are two choices to implement card detect:

1. Mux the card detect line from the SD card cage directly to the host
controller and expect PRESENT state register to indicate whether card is
present or not.

2. Mux the card detect line as a GPIO and use software
(dm_gpio_get_value() call) to detect whether card is present or not. In
that case, PRESENT_STATE[16,17,18] are completely useless because there
is no card detect line going into the IP.

It seems that you are using #2. What confuses me is how any cards are
able to assert CARD_DETECT.

Thanks,
Faiz
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[U-Boot] [PATCH v2] rtc: ds3232/ds3231: Add support to generate 32KHz output for driver module

[Chuanhua Han]

This patch add an implementation of the rtc_enable_32khz_output() that
uses the driver model i2c APIs.

Signed-off-by: Chuanhua Han 
---
Change in v2:
- Add RTC_ENABLE_32KHZ_OUTPUT option so this code compiles only 
in that cases where it is really useful.

 drivers/rtc/Kconfig  | 10 ++
 drivers/rtc/ds3231.c | 21 +
 include/rtc.h|  6 ++
 3 files changed, 37 insertions(+)

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index fd0009b..040d241 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -31,6 +31,12 @@ config TPL_DM_RTC
  drivers to perform the actual functions. See rtc.h for a
  description of the API.
 
+config RTC_ENABLE_32KHZ_OUTPUT
+   bool "Enable RTC 32Khz output"
+   help
+  Some real-time clocks support the output of 32kHz square waves (such 
as ds3231),
+  the config symbol choose Real Time Clock device 32Khz output feature.
+
 config RTC_PCF2127
bool "Enable PCF2127 driver"
depends on DM_RTC
@@ -41,6 +47,10 @@ config RTC_PCF2127
  has a selectable I2C-bus or SPI-bus, a backup battery switch-over 
circuit, a
  programmable watchdog function, a timestamp function, and many other 
features.
 
+config DS3231_BUS_NUM
+   hex "I2C bus of the DS3231 device"
+   default 0
+
 config RTC_DS1307
bool "Enable DS1307 driver"
depends on DM_RTC
diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c
index 79b026a..dbd77a6 100644
--- a/drivers/rtc/ds3231.c
+++ b/drivers/rtc/ds3231.c
@@ -148,11 +148,13 @@ void rtc_reset (void)
 /*
  * Enable 32KHz output
  */
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
 void rtc_enable_32khz_output(void)
 {
rtc_write(RTC_STAT_REG_ADDR,
  RTC_STAT_BIT_BB32KHZ | RTC_STAT_BIT_EN32KHZ);
 }
+#endif
 
 /*
  * Helper functions
@@ -251,6 +253,25 @@ static int ds3231_probe(struct udevice *dev)
return 0;
 }
 
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
+void rtc_enable_32khz_output(void)
+{
+   int ret;
+   struct udevice *dev;
+
+#ifdef CONFIG_DS3231_BUS_NUM
+   ret = i2c_get_chip_for_busnum(CONFIG_DS3231_BUS_NUM,
+ CONFIG_SYS_I2C_RTC_ADDR, 1, &dev);
+#else
+   ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_RTC_ADDR, 1, &dev);
+#endif
+   if (!ret)
+   dm_i2c_reg_write(dev, RTC_STAT_REG_ADDR,
+RTC_STAT_BIT_BB32KHZ |
+RTC_STAT_BIT_EN32KHZ);
+}
+#endif
+
 static const struct rtc_ops ds3231_rtc_ops = {
.get = ds3231_rtc_get,
.set = ds3231_rtc_set,
diff --git a/include/rtc.h b/include/rtc.h
index b255bdc..df7de09 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -166,11 +166,17 @@ int rtc_read32(struct udevice *dev, unsigned int reg, u32 
*valuep);
  */
 int rtc_write32(struct udevice *dev, unsigned int reg, u32 value);
 
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
+void rtc_enable_32khz_output(void);
+#endif
+
 #else
 int rtc_get (struct rtc_time *);
 int rtc_set (struct rtc_time *);
 void rtc_reset (void);
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
 void rtc_enable_32khz_output(void);
+#endif
 
 /**
  * rtc_read8() - Read an 8-bit register
-- 
2.9.5

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Re: [U-Boot] [PATCH 18/35] rockchip: rk3288-phycore: move phycore_init() to its own board file

[Wadim Egorov]

Hi Kever,

this is fine for me. You can drop the phycore_init() code completely. No
need to carry this around in our board code.
The SOM was redesigned and is equipped with an STM8 connected to the
RK818. The required setup we did before in the SPL is now done by the ST
controller. I know there are only a few SOMs without the STM8 out in the
wild. So if you remove it it will affect only a few people who probably
already have both boards.

Thanks,
Wadim

On 22.07.19 13:59, Kever Yang wrote:
> phycore_init() is use for phycore board only, it should be move back
> to phycore-rk3288.c
>
> Signed-off-by: Kever Yang 
> ---
>
>  arch/arm/mach-rockchip/rk3288-board-spl.c| 39 
>  arch/arm/mach-rockchip/rk3288/Kconfig|  1 +
>  board/phytec/phycore_rk3288/phycore-rk3288.c | 47 
>  3 files changed, 48 insertions(+), 39 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
> b/arch/arm/mach-rockchip/rk3288-board-spl.c
> index 6db5369a10..13cd86079b 100644
> --- a/arch/arm/mach-rockchip/rk3288-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
> @@ -25,8 +25,6 @@
>  #include 
>  #include 
>  #include 
> -#include 
> -#include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -81,32 +79,6 @@ fallback:
>   return BOOT_DEVICE_MMC1;
>  }
>  
> -#if !defined(CONFIG_SPL_OF_PLATDATA)
> -static int phycore_init(void)
> -{
> - struct udevice *pmic;
> - int ret;
> -
> - ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
> - if (ret)
> - return ret;
> -
> -#if defined(CONFIG_SPL_POWER_SUPPORT)
> - /* Increase USB input current to 2A */
> - ret = rk818_spl_configure_usb_input_current(pmic, 2000);
> - if (ret)
> - return ret;
> -
> - /* Close charger when USB lower then 3.26V */
> - ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 326);
> - if (ret)
> - return ret;
> -#endif
> -
> - return 0;
> -}
> -#endif
> -
>  __weak int arch_cpu_init(void)
>  {
>   return 0;
> @@ -175,17 +147,6 @@ void board_init_f(ulong dummy)
>   return;
>   }
>  
> -#if !defined(CONFIG_SPL_OF_PLATDATA)
> - if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
> - ret = phycore_init();
> - if (ret) {
> - debug("Failed to set up phycore power settings: %d\n",
> -   ret);
> - return;
> - }
> - }
> -#endif
> -
>  #if !defined(CONFIG_SUPPORT_TPL)
>   debug("\nspl:init dram\n");
>   ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig 
> b/arch/arm/mach-rockchip/rk3288/Kconfig
> index 6e3ab1d06b..87d0786ba8 100644
> --- a/arch/arm/mach-rockchip/rk3288/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3288/Kconfig
> @@ -85,6 +85,7 @@ config TARGET_MIQI_RK3288
>  config TARGET_PHYCORE_RK3288
>   bool "phyCORE-RK3288"
>  select BOARD_LATE_INIT
> + select SPL_BOARD_INIT if SPL
>   help
> Add basic support for the PCM-947 carrier board, a RK3288 based
> development board made by PHYTEC. This board works in a combination
> diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c 
> b/board/phytec/phycore_rk3288/phycore-rk3288.c
> index ffe1833b06..fbf1511978 100644
> --- a/board/phytec/phycore_rk3288/phycore-rk3288.c
> +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c
> @@ -8,10 +8,13 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
>  #include "som.h"
> +#include 
> +#include 
>  
>  static int valid_rk3288_som(struct rk3288_som *som)
>  {
> @@ -68,3 +71,47 @@ int rk_board_late_init(void)
>  
>   return 0;
>  }
> +
> +#ifdef CONFIG_SPL_BUILD
> +#if !defined(CONFIG_SPL_OF_PLATDATA)
> +static int phycore_init(void)
> +{
> + struct udevice *pmic;
> + int ret;
> +
> + ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
> + if (ret)
> + return ret;
> +
> +#if defined(CONFIG_SPL_POWER_SUPPORT)
> + /* Increase USB input current to 2A */
> + ret = rk818_spl_configure_usb_input_current(pmic, 2000);
> + if (ret)
> + return ret;
> +
> + /* Close charger when USB lower then 3.26V */
> + ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 326);
> + if (ret)
> + return ret;
> +#endif
> +
> + return 0;
> +}
> +#endif
> +
> +void spl_board_init(void)
> +{
> +#if !defined(CONFIG_SPL_OF_PLATDATA)
> + int ret;
> +
> + if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
> + ret = phycore_init();
> + if (ret) {
> + debug("Failed to set up phycore power settings: %d\n",
> +   ret);
> + return;
> + }
> + }
> +#endif
> +}
> +#endif
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Re: [U-Boot] [PATCH] mmd: sdhci: fix non GPIO card detect

[Baruch Siach]

Hi Faiz,

On Tue, Jul 23, 2019 at 03:35:31PM +0530, Faiz Abbas wrote:
> On 23/07/19 2:39 PM, Baruch Siach wrote:
> > On Tue, Jul 23, 2019 at 02:27:28PM +0530, Faiz Abbas wrote:
> >> On 23/07/19 1:30 PM, Peng Fan wrote:
> >>> + Faiz
> >>>
>  Subject: [PATCH] mmd: sdhci: fix non GPIO card detect
> 
>  Some SD cards do not assert the SDHCI_CARD_PRESENT bit. Only the
>  SDHCI_CARD_DETECT_PIN_LEVEL is enabled. Consider that enough for card
>  detect indication.
> 
>  This fixes SD card access from SPL, since DM_GPIO is not available in SPL
>  code.
> 
>  Fixes: da18c62b6e6a ("mmc: sdhci: Implement SDHCI card detect")
>  Cc: T Karthik Reddy 
>  Cc: Michal Simek 
>  Signed-off-by: Baruch Siach 
>  ---
>   drivers/mmc/sdhci.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
>  diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index
>  2779bca93f08..17a28181fcca 100644
>  --- a/drivers/mmc/sdhci.c
>  +++ b/drivers/mmc/sdhci.c
>  @@ -683,7 +683,7 @@ int sdhci_get_cd(struct udevice *dev)
>   }
>   #endif
>   value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
>  -   SDHCI_CARD_PRESENT);
>  +   (SDHCI_CARD_PRESENT | SDHCI_CARD_DETECT_PIN_LEVEL));
> >>>
> >>> Faiz, are you fine with this change?
> >>
> >> Not really. The spec is pretty clear that DETECT_PIN_LEVEL is not to be
> >> trusted. Also how does the CARD_PRESENT assertion depend on the SD card
> >> you use? Are you normally muxing the SDCD line to the IP (for hardware
> >> to detect) or are you connecting it as a gpio which software must detect?
> > 
> > I tested SanDisk 8GB SD card, class 10, UHS1, on Armada 388 based SolidRun 
> > Clearfog Base. The SDHCI_PRESENT_STATE register consistently reads 
> > 0x01f6, 
> > that is, CARD_PRESENT is disabled, DETECT_PIN_LEVEL is enabled.
> > 
> > The SD card-detect GPIO is present at the hardware level, but it is not 
> > accessible from SPL code because there is currently no SPL_DM_GPIO. The 
> > main 
> > U-Boot image detects the SD card correctly (once the other MMC patches I 
> > posted are applied).
> > 
> > Without this patch boot from SD card is broken. What is the right fix then?
> 
> There are two choices to implement card detect:
> 
> 1. Mux the card detect line from the SD card cage directly to the host
> controller and expect PRESENT state register to indicate whether card is
> present or not.
> 
> 2. Mux the card detect line as a GPIO and use software
> (dm_gpio_get_value() call) to detect whether card is present or not. In
> that case, PRESENT_STATE[16,17,18] are completely useless because there
> is no card detect line going into the IP.
> 
> It seems that you are using #2. What confuses me is how any cards are
> able to assert CARD_DETECT.

As far as I can see the Armada 388 SD host controller does not provide option 
#1. The Clearfog indeed uses option #2. Until commit da18c62b6e6a4 ("mmc: 
sdhci: Implement SDHCI card detect") it used to work because the mv_sdhci 
driver does not implement the get_cd callback, so card-detect was ignored. Now 
we have a get_cd implementation at the sdhci level that returns 0 in SPL 
because the GPIO is not accessible.

What would you suggest?

baruch

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[U-Boot] [PATCH v3 1/5] armv8: ls1088a: The ls1088a platform supports the I2C driver model.

[Chuanhua Han]

DM_I2C_COMPAT is a compatibility layer that allows using the non-DM
I2C API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for
compilation, a compilation error will be generated. This patch
solves the problem that the i2c-related api of the ls1088a platform
does not support dm.

Signed-off-by: Chuanhua Han 
---
depends on:
- http://patchwork.ozlabs.org/project/uboot/list/?series=110856
- http://patchwork.ozlabs.org/project/uboot/list/?series=109459

Changes in v3:
- Change the Kconfig file to !TFABOOT.
- Define the use of CONFIG_SYS_I2C for non-dm.
Changes in v2:
- No change.

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |   8 +-
 board/freescale/ls1088a/ls1088a.c | 148 ++
 include/configs/ls1088a_common.h  |   3 +
 include/configs/ls1088ardb.h  |   2 -
 4 files changed, 155 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index ffda02a..b2768ed 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -155,10 +155,10 @@ config ARCH_LS1088A
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
-   select SYS_I2C_MXC_I2C1
-   select SYS_I2C_MXC_I2C2
-   select SYS_I2C_MXC_I2C3
-   select SYS_I2C_MXC_I2C4
+   select SYS_I2C_MXC_I2C1 if !TFABOOT
+   select SYS_I2C_MXC_I2C2 if !TFABOOT
+   select SYS_I2C_MXC_I2C3 if !TFABOOT
+   select SYS_I2C_MXC_I2C4 if !TFABOOT
imply SCSI
imply PANIC_HANG
 
diff --git a/board/freescale/ls1088a/ls1088a.c 
b/board/freescale/ls1088a/ls1088a.c
index 6d11a13..2bac070 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -373,7 +373,15 @@ int select_i2c_ch_pca9547(u8 ch)
 {
int ret;
 
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+   struct udevice *dev;
+
+   ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+   if (!ret)
+   ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@@ -392,38 +400,89 @@ void board_retimer_init(void)
 
/* Access to Control/Shared register */
reg = 0x0;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+#else
+   struct udevice *dev;
+
+   i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
+   dm_i2c_write(dev, 0xff, ®, 1);
+#endif
 
/* Read device revision and ID */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
+#else
+   dm_i2c_read(dev, 1, ®, 1);
+#endif
debug("Retimer version id = 0x%x\n", reg);
 
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+#else
+   dm_i2c_write(dev, 0xff, ®, 1);
+#endif
 
/* Reset Channel Registers */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+#else
+   dm_i2c_read(dev, 0, ®, 1);
+#endif
reg |= 0x4;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+#else
+   dm_i2c_write(dev, 0, ®, 1);
+#endif
 
/* Set data rate as 10.3125 Gbps */
reg = 0x90;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
+#else
+   dm_i2c_write(dev, 0x60, ®, 1);
+#endif
reg = 0xb3;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
+#else
+   dm_i2c_write(dev, 0x61, ®, 1);
+#endif
reg = 0x90;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
+#else
+   dm_i2c_write(dev, 0x62, ®, 1);
+#endif
reg = 0xb3;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
+#else
+   dm_i2c_write(dev, 0x63, ®, 1);
+#endif
reg = 0xcd;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
+#else
+   dm_i2c_write(dev, 0x64, ®, 1);
+#endif
 
/* Select VCO Divider to full rate (000) */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
+#else
+   dm_i2c_read(dev, 0x2F, ®, 1);
+#endif
reg &= 0x0f;
reg |= 0x70;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
+#else
+   dm_i2c_write(dev, 0x2F, ®, 1);
+#endif
 
 #ifdef CONFIG_TARGET_LS1088AQDS
/* Retimer is connected to I2C1_CH5 */
@@ -431,38 +490,88 @@ void board_retimer_init(void)
 
/* Access to Control/Shared register */
reg = 0x0;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
+#else
+   i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
+   dm_i2c_write(dev, 0xff, ®, 1);
+#endif
 
/* Read device revision and ID */
+#ifndef CONFIG_DM_I2C
i2c_read(

[U-Boot] [PATCH v3 2/5] gpio: do not include on ARCH_LS1088A

[Chuanhua Han]

As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include  for
arch ls1088a.

Signed-off-by: Chuanhua Han 
---
depends on: 
- http://patchwork.ozlabs.org/project/uboot/list/?series=110856
- http://patchwork.ozlabs.org/project/uboot/list/?series=109459

Changes in v3: 
- No change.
Changes in v2: 
- No change.

 arch/arm/include/asm/gpio.h |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index f78b976..0ca15c9 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -1,7 +1,7 @@
 #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \
!defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \
-   !defined(CONFIG_ARCH_LX2160A)
+   !defined(CONFIG_ARCH_LX2160A) && !defined(CONFIG_ARCH_LS1088A)
 #include 
 #endif
 #include 
-- 
1.7.1

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[U-Boot] [PATCH v3 4/5] armv8: dts: fsl-ls1088a: add I2C node support

[Chuanhua Han]

One ls1088a, there is four I2C controllers.
This patch is to add I2C node for ls1088a.

Signed-off-by: Chuanhua Han 
---
depends on: 
- http://patchwork.ozlabs.org/project/uboot/list/?series=110856
- http://patchwork.ozlabs.org/project/uboot/list/?series=109459

Changes in v3: 
- No change.
Changes in v2: 
- No change.

 arch/arm/dts/fsl-ls1088a.dtsi |   32 
 1 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 7c70585..4be1ab8 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -34,6 +34,38 @@
 <1 10 0x8>; /* Hypervisor PPI, active-low */
};
 
+   i2c0: i2c@200 {
+   compatible = "fsl,vf610-i2c";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x200 0x0 0x1>;
+   interrupts = <0 34 4>;
+   };
+
+   i2c1: i2c@201 {
+   compatible = "fsl,vf610-i2c";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x201 0x0 0x1>;
+   interrupts = <0 34 4>;
+   };
+
+   i2c2: i2c@202 {
+   compatible = "fsl,vf610-i2c";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x202 0x0 0x1>;
+   interrupts = <0 35 4>;
+   };
+
+   i2c3: i2c@203 {
+   compatible = "fsl,vf610-i2c";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x203 0x0 0x1>;
+   interrupts = <0 35 4>;
+   };
+
serial0: serial@21c0500 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
-- 
1.7.1

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[U-Boot] [PATCH v3 5/5] armv8: dts: ls1088ardb: Add slave nodes under the i2c0 controller

[Chuanhua Han]

This patch adds some slave nodes to support the i2c dm on the device
side under the i2c0 controller.

Signed-off-by: Chuanhua Han 
---
depends on: 
- http://patchwork.ozlabs.org/project/uboot/list/?series=110856
- http://patchwork.ozlabs.org/project/uboot/list/?series=109459

Change in v3:
- No change.
Change in v2: 
- Delete unnecessary i2c slave nodes.

 arch/arm/dts/fsl-ls1088a-rdb.dts |   23 +++
 1 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts
index 765d1e3..0fe3519 100644
--- a/arch/arm/dts/fsl-ls1088a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1088a-rdb.dts
@@ -17,6 +17,29 @@
};
 };
 
+&i2c0 {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+
+   i2c-mux@77 {
+   compatible = "nxp,pca9547";
+   reg = <0x77>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   i2c@3 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x3>;
+
+   rtc@51 {
+   compatible = "pcf2127-rtc";
+   reg = <0x51>;
+   };
+   };
+   };
+};
+
 &qspi {
bus-num = <0>;
status = "okay";
-- 
1.7.1

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[U-Boot] [PATCH v3 3/5] configs: ls1088a: enable DM support for pcf2127 rtc

[Chuanhua Han]

Enable related configs to support pcf2127 rtc DM feature for
ls1088ardb board.

Signed-off-by: Chuanhua Han 
---
depends on: 
- http://patchwork.ozlabs.org/project/uboot/list/?series=110856
- http://patchwork.ozlabs.org/project/uboot/list/?series=109459

Changes in v3: 
- Add configuration options for i2c dm to set default bus number 
Settings.
Changes in v2: 
- No change.

 configs/ls1088ardb_tfa_SECURE_BOOT_defconfig |10 +-
 configs/ls1088ardb_tfa_defconfig |10 +-
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig 
b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
index 3c4437d..364fc59 100644
--- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1088ARDB=y
+CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_SYS_TEXT_BASE=0x8200
 CONFIG_SECURE_BOOT=y
 CONFIG_QSPI_AHB_INIT=y
@@ -9,7 +10,6 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -63,3 +63,11 @@ CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_DM_RTC=y
+CONFIG_DM_GPIO=y
+CONFIG_RTC_PCF2127=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index 8cea8c7..eb35782 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1088ARDB=y
+CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_SYS_TEXT_BASE=0x8200
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_TFABOOT=y
@@ -8,7 +9,6 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -61,3 +61,11 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_DM_RTC=y
+CONFIG_DM_GPIO=y
+CONFIG_RTC_PCF2127=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
-- 
1.7.1

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Re: [U-Boot] [GIT] Pull request: u-boot-dfu (22.07.2019)

[Marek Vasut]

On 7/22/19 6:17 PM, Lukasz Majewski wrote:
> Dear Marek,
> 
> Repo:  g...@gitlab.denx.de:u-boot/custodians/u-boot-dfu.git
> Branch: master

Applied, thanks
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Re: [U-Boot] R-Car-gpio0_00-fails-with-“gpio input” command

[Marek Vasut]

On 7/23/19 3:00 AM, Tiezhuang Dong wrote:
> Hi,

Hi,

> Attached is to fix below issue:
> 
> --
> 
> => gpio input gpio@e6050 
> gpio: requesting pin 0 failed
> gpio - query and control gpio pins
> 
> --
> 
> Fix:
> 
> drivers/pinctrl/renesas/pfc.c +470
> 
> //for (i = 1; i < pfc->info->nr_pins; i++) {
> 
>     for (i = 0; i < pfc->info->nr_pins; i++) {
sh_pfc_gpio_disable_free() needs similar change, right ?

Can you send the patch using git send-email and also add proper commit
message ? Thanks

-- 
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Marek Vasut
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Re: [U-Boot] [PATCH] mmd: sdhci: fix non GPIO card detect

[Faiz Abbas]

Hi Baruch,

On 23/07/19 4:16 PM, Baruch Siach wrote:
> Hi Faiz,
> 
> On Tue, Jul 23, 2019 at 03:35:31PM +0530, Faiz Abbas wrote:
>> On 23/07/19 2:39 PM, Baruch Siach wrote:
>>> On Tue, Jul 23, 2019 at 02:27:28PM +0530, Faiz Abbas wrote:
 On 23/07/19 1:30 PM, Peng Fan wrote:
> + Faiz
>
>> Subject: [PATCH] mmd: sdhci: fix non GPIO card detect
>>
>> Some SD cards do not assert the SDHCI_CARD_PRESENT bit. Only the
>> SDHCI_CARD_DETECT_PIN_LEVEL is enabled. Consider that enough for card
>> detect indication.
>>
>> This fixes SD card access from SPL, since DM_GPIO is not available in SPL
>> code.
>>
>> Fixes: da18c62b6e6a ("mmc: sdhci: Implement SDHCI card detect")
>> Cc: T Karthik Reddy 
>> Cc: Michal Simek 
>> Signed-off-by: Baruch Siach 
>> ---
>>  drivers/mmc/sdhci.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index
>> 2779bca93f08..17a28181fcca 100644
>> --- a/drivers/mmc/sdhci.c
>> +++ b/drivers/mmc/sdhci.c
>> @@ -683,7 +683,7 @@ int sdhci_get_cd(struct udevice *dev)
>>  }
>>  #endif
>>  value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
>> -   SDHCI_CARD_PRESENT);
>> +   (SDHCI_CARD_PRESENT | SDHCI_CARD_DETECT_PIN_LEVEL));
>
> Faiz, are you fine with this change?

 Not really. The spec is pretty clear that DETECT_PIN_LEVEL is not to be
 trusted. Also how does the CARD_PRESENT assertion depend on the SD card
 you use? Are you normally muxing the SDCD line to the IP (for hardware
 to detect) or are you connecting it as a gpio which software must detect?
>>>
>>> I tested SanDisk 8GB SD card, class 10, UHS1, on Armada 388 based SolidRun 
>>> Clearfog Base. The SDHCI_PRESENT_STATE register consistently reads 
>>> 0x01f6, 
>>> that is, CARD_PRESENT is disabled, DETECT_PIN_LEVEL is enabled.
>>>
>>> The SD card-detect GPIO is present at the hardware level, but it is not 
>>> accessible from SPL code because there is currently no SPL_DM_GPIO. The 
>>> main 
>>> U-Boot image detects the SD card correctly (once the other MMC patches I 
>>> posted are applied).
>>>
>>> Without this patch boot from SD card is broken. What is the right fix then?
>>
>> There are two choices to implement card detect:
>>
>> 1. Mux the card detect line from the SD card cage directly to the host
>> controller and expect PRESENT state register to indicate whether card is
>> present or not.
>>
>> 2. Mux the card detect line as a GPIO and use software
>> (dm_gpio_get_value() call) to detect whether card is present or not. In
>> that case, PRESENT_STATE[16,17,18] are completely useless because there
>> is no card detect line going into the IP.
>>
>> It seems that you are using #2. What confuses me is how any cards are
>> able to assert CARD_DETECT.
> 
> As far as I can see the Armada 388 SD host controller does not provide option 
> #1. The Clearfog indeed uses option #2. Until commit da18c62b6e6a4 ("mmc: 
> sdhci: Implement SDHCI card detect") it used to work because the mv_sdhci 
> driver does not implement the get_cd callback, so card-detect was ignored. 
> Now 
> we have a get_cd implementation at the sdhci level that returns 0 in SPL 
> because the GPIO is not accessible.
> 
> What would you suggest?
> 

You can just add your own get_cd() callback instead of using sdhci_get_cd().

Thanks,
Faiz
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Re: [U-Boot] [PATCH v5 3/8] x86: slimbootloader: Add memory configuration

[Andy Shevchenko]

On Tue, Jul 23, 2019 at 8:51 AM Bin Meng  wrote:
> On Mon, Jul 22, 2019 at 11:33 PM Andy Shevchenko
>  wrote:
> > On Wed, Jul 17, 2019 at 7:41 AM Park, Aiden  wrote:
> > >
> > > Slim Bootloader provides memory map info thru its HOB list pointer.
> > > Configure memory size and relocation memory from the HOB data, and
> > > provide e820 entries as well.
> > > - Get memory size from the memory map info hob
> > > - Set ram top for U-Boot relocation lower than 4GB
> > > - Provide e820 entries from the memory map info hob
> >
> > > +++ b/arch/x86/cpu/slimbootloader/dram.c
> >
> > sdram.c is more common name in the sources AFAICS.
>
> Looks we have both sdram.c and dram.c :)

True, but among x86 platforms sdram is *more* common.

-- 
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Andy Shevchenko
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Re: [U-Boot] [PATCH v5 7/8] board: intel: Add new slimbootloader board

[Andy Shevchenko]

On Tue, Jul 23, 2019 at 9:15 AM Bin Meng  wrote:
> On Mon, Jul 22, 2019 at 11:49 PM Andy Shevchenko
>  wrote:
> > On Wed, Jul 17, 2019 at 7:42 AM Park, Aiden  wrote:

> > >  board/intel/slimbootloader/README   | 133 
> >
> > Shouldn't become reST one?
>
> I think this will need be converted to reST after my doc series are applied.

I had an impression that reST conversion is targeting 2019.10. It
means in your branch you will have it applied earlier.

> > > +int board_early_init_r(void)
> > > +{
> > > +   /*
> > > +* Make sure PCI bus is enumerated so that peripherals on the PCI 
> > > bus
> > > +* can be discovered by their drivers
> > > +*/
> > > +   pci_init();
> >
> > I'm not sure this is how U-Boot is designed with DM.
> > At least my expectations that bus gets initialized followed by the
> > certain driver in a lazy way.
> > Isn't it the case? Bin?
>
> For most x86 board, yes, PCI gets enumerated automatically if some PCI
> APIs are called in the early initialization codes: eg: pci_{read,
> write}_config().
>
> But for boards like coreboot/slimbootloader, if there is no touch to
> any PCI config register on that board in the early phase, PCI bus
> remains not probed.

Thanks for explanation!
Perhaps this needs a comment in the code.

-- 
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Andy Shevchenko
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Re: [U-Boot] [EXT] Re: Upstreaming usb host drivers for iMX8/iMX8M

[Igor Opaniuk]

Hi Sherry,

On Tue, Jul 2, 2019 at 4:26 AM Sherry Sun  wrote:
>
> + Ying
>
> > -邮件原件-
> > 发件人: Igor Opaniuk 
> > 发送时间: 2019年7月1日 19:32
> > 收件人: Sherry Sun 
> > 抄送: Peng Fan ; Jun Li ; Ye Li
> > ; U-Boot Mailing List ; Peter Chen
> > ; dl-uboot-imx ; Marcel Ziswiler
> > ; Max Krummenacher
> > ; Igor Opaniuk
> > ; Frank Li 
> > 主题: [EXT] Re: Upstreaming usb host drivers for iMX8/iMX8M
> >
> > Caution: EXT Email
> >
> > Hi Sherry,
> >
> > On Fri, Jun 28, 2019 at 8:02 AM Sherry Sun  wrote:
> > >
> > > Hi, Igor
> > >
> > > We have the plan to do the upstream job of cdns3 host/gadget drivers on
> > imx8.
> > > Now we just have done the DM switch of cdns3 gadget driver, and there
> > > also some changes in xhci_imx8.c.
> > Thanks for the details!
> >
> > > We plan to start our upstream job from next week, and the first
> > > version will be send to maintainer within two or three weeks. We hope
> > > it will be included in uboot v2019.07 RC2.
> > I'm afraid we're a bit late here.
> > v2019.07 is going to be released next Monday (there was a release of
> > v2019.07-rc4 already in June 11), so the next merge window for
> > v2019.10 opens July 9.
>
> Yes, you are right.
> Anyway, I will try my best and finish the upstream job as soon as possible.
>
> > > Do you think this is okay?
> > Sounds good! Looking forward to your patches in the mailing list!
> >
> > >
> > > Best regards
> > > Sherry sun
> > >
> > >
> > Just a bit off-topic, but are you aware about similar plans for upstreaming 
> > of
> > DPU driver for i.MX8 (driver/video/imxdpuv1.c)?
>
> Sorry, I am not quite sure.
> Ying knows more about this. Maybe he can answer you.
>
> Best regards
> Sherry sun
>
> > > -邮件原件-
> > > 发件人: Peng Fan
> > > 发送时间: 2019年6月27日 17:58
> > > 收件人: Igor Opaniuk ; Sherry Sun
> > > ; Jun Li 
> > > 抄送: U-Boot Mailing List ; Ye Li ;
> > > Peter Chen ; dl-uboot-imx ;
> > > Marcel Ziswiler ; Max Krummenacher
> > > ; Igor Opaniuk
> > > ; Frank Li 
> > > 主题: RE: Upstreaming usb host drivers for iMX8/iMX8M
> > >
> > > + Sherry, Jun
> > >
> > > > Subject: Re: Upstreaming usb host drivers for iMX8/iMX8M
> > > >
> > > > Hi Peng,
> > > >
> > > > On Thu, Jun 27, 2019 at 8:32 AM Peng Fan  wrote:
> > > > >
> > > > >
> > > > > Hi Igor,
> > > > >
> > > > > > Subject: Upstreaming usb host drivers for iMX8/iMX8M
> > > > > >
> > > > > > Hi Peng, Ye, Peter,
> > > > > >
> > > > > > Currently there in no any usb host/gadget support in the
> > > > > > mainline U-boot, and seems that no one has posted anything yet
> > > > > > to the mailing list (at least I haven't found anything related to 
> > > > > > this in the
> > ML archives).
> > > > > >
> > > > > > I've spent some time testing (usb host, ums etc.) the one in the
> > > > > > downstream NXP U-boot (I'm still not sure where is the official
> > > > > > NXP downstream rep, because there are no any updates in [1] for
> > > > > > the last two years, so I looked into [2], [3]), and just curious
> > > > > > if there any plans to get it upstreamed in the near future?
> > > > >
> > > > > In NXP downstream, there is work to migrate the i.MX8 usb/gadget to
> > DM.
> > > > > When that ready, the patches will be posted to community.
> > > >
> > > > So do you need any help with this?
> > >
> > > I am not working on that. But I welcome any contribution to make more
> > features supported in upstream.
> > >
> > > Won't you mind if we start up-streaming at
> > > > least xhci-imx8.c, which is used in both our SoMs Apalis iMX8 and
> > > > Colibri iMX8QXP. Based on what I've seen in [1], the initial
> > > > conversion to DM_USB is already done. Is there anything else that is
> > > > expected to be changed in xhci-imx8.c (by asking this I just want to 
> > > > avoid
> > duplicating the effort)?
> > >
> > > Sherry, Jun has some work on the driver. So they might have comments to
> > avoid duplicating efforts, in case they has plan recently.
> > >
> > > Regards,
> > > Peng.
> > >
> > > >
> > > > Frankly, this is currently a kind of showstopper for us, as it adds
> > > > some complications for the next release of our BSP (we would like to
> > > > enable usb host/gadget support or iMX8-based SoMS, including all
> > > > dependent features like fastboot/usb storage/ums etc.), where we
> > > > made a decision to move towards the usage of the mainline U-boot
> > > > (with the minimal divergence and minimal amount of legacy downstream
> > patches on top of it).
> > > >
> > > > >
> > > > >
> > > > > Regards,
> > > > > Peng.
> > > > >
> > > > > >
> > > > > > Thanks and looking forward to your reply!
> > > > > >
> > > > > > [1]
> > > > > > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2
> > > > > >
> > Fgit.free&data=02%7C01%7Csherry.sun%40nxp.com%7C67623cb689cf
> > > > > >
> > 479bb27608d6fe17c430%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> > 0%
> > > > > >
> > 7C636975775374207078&sdata=FLmaX%2Bg0SGJS%2B0qiFF7Mq%2BAA
> > TLc
> > > > > > FEnPv%2FRF530WY%2B%2FY%3D&reserved=0
> > > > > >
> > > >
> > scale

[U-Boot] [PATCH 0/3] dm: pcie_fsl: Fix some issues

[Hou Zhiqiang]

The current driver is not working on some PowerPC T-series, P-series
and MPC85xx platforms due to the difference in PCIe IP revisions and
the various integration on different platforms. This patch set fixes
these issues.

Hou Zhiqiang (3):
  dm: pcie_fsl: Fix workaround of P4080 erratum A003
  dm: pcie_fsl: Fix the Class Code fixup function
  dm: pcie_fsl: Fix the calculation of controller index

 drivers/pci/pcie_fsl.c | 33 ++---
 drivers/pci/pcie_fsl.h | 16 
 2 files changed, 42 insertions(+), 7 deletions(-)

-- 
2.9.5

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[U-Boot] [PATCH 2/3] dm: pcie_fsl: Fix the Class Code fixup function

[Hou Zhiqiang]

The Class Code fixup method was changed from PCIe block
revision 3.0, the current fixup is only valid for the
revision 3.0 and the later ones.

This patch is to add the Class Code fixup for the block
revision < 3.0.

Signed-off-by: Hou Zhiqiang 
---
 drivers/pci/pcie_fsl.c | 17 +
 drivers/pci/pcie_fsl.h |  3 +++
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 999e9c9..7a7da1f 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -503,12 +503,21 @@ static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
ccsr_fsl_pci_t *regs = pcie->regs;
u32 val;
 
-   setbits_be32(®s->dbi_ro_wr_en, 0x01);
-   fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val);
+   if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
+   setbits_be32(®s->dbi_ro_wr_en, 0x01);
+   fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val);
+   val &= 0xff;
+   val |= PCI_CLASS_BRIDGE_PCI << 16;
+   fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val);
+   clrbits_be32(®s->dbi_ro_wr_en, 0x01);
+
+   return 0;
+   }
+
+   fsl_pcie_hose_read_config_dword(pcie, CSR_CLASSCODE, &val);
val &= 0xff;
val |= PCI_CLASS_BRIDGE_PCI << 16;
-   fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val);
-   clrbits_be32(®s->dbi_ro_wr_en, 0x01);
+   fsl_pcie_hose_write_config_dword(pcie, CSR_CLASSCODE, val);
 
return 0;
 }
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
index e09099b..a872921 100644
--- a/drivers/pci/pcie_fsl.h
+++ b/drivers/pci/pcie_fsl.h
@@ -10,6 +10,9 @@
 #ifndef _PCIE_FSL_H_
 #define _PCIE_FSL_H_
 
+/* GPEX CSR */
+#define CSR_CLASSCODE  0x474
+
 #ifdef CONFIG_SYS_FSL_PCI_VER_3_X
 #define FSL_PCIE_CAP_ID0x70
 #else
-- 
2.9.5

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[U-Boot] [PATCH 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003

[Hou Zhiqiang]

In the workaround of P4080 erratum A003, it uses the macro
CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block
register address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is
defined as following:

#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)

This is valid on P4080, but on non-corenet platforms, such
as MPC8548, there is not definition of
CONFIG_SYS_FSL_CORENET_SERDES_OFFSET, then on these platforms
the following build error will come up:

drivers/pci/pcie_fsl.c: In function 'fsl_pcie_init_port':
./arch/powerpc/include/asm/immap_85xx.h:3000:21: error:
'CONFIG_SYS_FSL_CORENET_SERDES_OFFSET' undeclared (first use
in this function); did you mean 'CONFIG_SYS_FSL_CORENET_SERDES_ADDR'?
  (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 ^~~~

Signed-off-by: Hou Zhiqiang 
---
 drivers/pci/pcie_fsl.c | 2 +-
 drivers/pci/pcie_fsl.h | 6 ++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index bfb207e..999e9c9 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -445,7 +445,7 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie)
!fsl_pcie_link_up(pcie)) {
serdes_corenet_t *srds_regs;
 
-   srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+   srds_regs = (void *)P4080_SERDES_ADDR;
val_32 = in_be32(&srds_regs->srdspccr0);
 
if ((val_32 >> 28) == 3) {
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
index ce2b1af..e09099b 100644
--- a/drivers/pci/pcie_fsl.h
+++ b/drivers/pci/pcie_fsl.h
@@ -41,6 +41,12 @@
 #define LTSSM_L0_REV3  0x11
 #define LTSSM_L0   0x16
 
+#ifdef ARCH_P4080
+#define P4080_SERDES_ADDR  CONFIG_SYS_FSL_CORENET_SERDES_ADDR
+#else
+#define P4080_SERDES_ADDR  0
+#endif
+
 struct fsl_pcie {
int idx;
struct udevice *bus;
-- 
2.9.5

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[U-Boot] [PATCH 3/3] dm: pcie_fsl: Fix the calculation of controller index

[Hou Zhiqiang]

The PCIe controller register address in CCSR is different
on various platforms, the current code erroneously use
the hardcoded address (0xffe24) and stride (0x1)
to calculate the controller's index.

Fix it by adding the related info to the driver data
structure.

Signed-off-by: Hou Zhiqiang 
---
 drivers/pci/pcie_fsl.c | 14 --
 drivers/pci/pcie_fsl.h |  7 +++
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 7a7da1f..e13e5a6 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -580,6 +580,7 @@ static int fsl_pcie_probe(struct udevice *dev)
 static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
 {
struct fsl_pcie *pcie = dev_get_priv(dev);
+   struct fsl_pcie_data *info;
int ret;
 
pcie->regs = dev_remap_addr(dev);
@@ -594,7 +595,10 @@ static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
return ret;
}
 
-   pcie->idx = (dev_read_addr(dev) - 0xffe24) / 0x1;
+   info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
+   pcie->info = info;
+   pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
+   info->block_offset) / info->stride;
 
return 0;
 }
@@ -604,8 +608,14 @@ static const struct dm_pci_ops fsl_pcie_ops = {
.write_config   = fsl_pcie_write_config,
 };
 
+static struct fsl_pcie_data t2080_data = {
+   .block_offset = 0x24,
+   .block_offset_mask = 0x3f,
+   .stride = 0x1,
+};
+
 static const struct udevice_id fsl_pcie_ids[] = {
-   { .compatible = "fsl,pcie-t2080" },
+   { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
{ }
 };
 
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
index a872921..8335c62 100644
--- a/drivers/pci/pcie_fsl.h
+++ b/drivers/pci/pcie_fsl.h
@@ -50,6 +50,12 @@
 #define P4080_SERDES_ADDR  0
 #endif
 
+struct fsl_pcie_data {
+   u32 block_offset;   /* Offset from CCSR of 1st controller */
+   u32 block_offset_mask;  /* Mask out the CCSR base */
+   u32 stride; /* Offset stride between controllers */
+};
+
 struct fsl_pcie {
int idx;
struct udevice *bus;
@@ -59,6 +65,7 @@ struct fsl_pcie {
bool mode;  /* RC&EP mode flag */
bool enabled;   /* Enable status */
struct list_head list;
+   struct fsl_pcie_data *info;
 };
 
 extern struct list_head fsl_pcie_list;
-- 
2.9.5

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Re: [U-Boot] [PATCH 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003

[Bin Meng]

On Tue, Jul 23, 2019 at 8:53 PM Hou Zhiqiang  wrote:
>
> In the workaround of P4080 erratum A003, it uses the macro
> CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block
> register address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is
> defined as following:
>
> #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
> (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
>
> This is valid on P4080, but on non-corenet platforms, such
> as MPC8548, there is not definition of
> CONFIG_SYS_FSL_CORENET_SERDES_OFFSET, then on these platforms
> the following build error will come up:
>
> drivers/pci/pcie_fsl.c: In function 'fsl_pcie_init_port':
> ./arch/powerpc/include/asm/immap_85xx.h:3000:21: error:
> 'CONFIG_SYS_FSL_CORENET_SERDES_OFFSET' undeclared (first use
> in this function); did you mean 'CONFIG_SYS_FSL_CORENET_SERDES_ADDR'?
>   (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
>  ^~~~
>
> Signed-off-by: Hou Zhiqiang 
> ---
>  drivers/pci/pcie_fsl.c | 2 +-
>  drivers/pci/pcie_fsl.h | 6 ++
>  2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
> index bfb207e..999e9c9 100644
> --- a/drivers/pci/pcie_fsl.c
> +++ b/drivers/pci/pcie_fsl.c
> @@ -445,7 +445,7 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie)
> !fsl_pcie_link_up(pcie)) {
> serdes_corenet_t *srds_regs;
>
> -   srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
> +   srds_regs = (void *)P4080_SERDES_ADDR;
> val_32 = in_be32(&srds_regs->srdspccr0);
>
> if ((val_32 >> 28) == 3) {
> diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
> index ce2b1af..e09099b 100644
> --- a/drivers/pci/pcie_fsl.h
> +++ b/drivers/pci/pcie_fsl.h
> @@ -41,6 +41,12 @@
>  #define LTSSM_L0_REV3  0x11
>  #define LTSSM_L0   0x16
>
> +#ifdef ARCH_P4080
> +#define P4080_SERDES_ADDR  CONFIG_SYS_FSL_CORENET_SERDES_ADDR
> +#else
> +#define P4080_SERDES_ADDR  0

So for non-P4080 platform, we are accessing address at zero?

Regards,
Bin
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Re: [U-Boot] [PATCH v1] imx: add u-boot-nand.imx target

[Igor Opaniuk]

Hi Jagan,

On Tue, Jul 16, 2019 at 1:51 PM Jagan Teki  wrote:
>
> On Tue, Jul 16, 2019 at 3:01 PM Igor Opaniuk  wrote:
> >
> > From: Igor Opaniuk 
> >
> > Add an additional target which prepends the u-boot.imx image with
> > 0x400 padding bytes. On Vybrid and i.MX 7, i.MX6ULL this is required
> > for NAND boot devices. The configuration CONFIG_IMX_NAND enables this
> > image for a board.
>
> How about trying like this for imx7.
>
> https://patchwork.ozlabs.org/patch/1100412/

yeah, makes sense, we can avoid messing with make
instructions in arch/arm/config.mk and handle this in Kconfig.
Will fix and send v2 soon.

Thanks

--
Best regards - Freundliche Grüsse - Meilleures salutations

Igor Opaniuk

mailto: igor.opan...@gmail.com
skype: igor.opanyuk
+380 (93) 836 40 67
http://ua.linkedin.com/in/iopaniuk
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[U-Boot] [PATCH 00/47] powerpc: Enable PCIe DM drvier for some platforms

[Hou Zhiqiang]

Enable PCIe DM driver for some PowerPC platforms which has supported
device tree.

Depends on the following 2 series:
http://patchwork.ozlabs.org/project/uboot/list/?series=120960
http://patchwork.ozlabs.org/project/uboot/list/?series=115008

Hou Zhiqiang (47):
  powerpc: T208xRDB: Compile legacy PCIe routines conditionally
  powerpc: T208xRDB: Disable legacy PCIe driver when DM_PCI is enabled
  configs: T2080RDB: Enable PCIe driver
  powerpc: T4RDB: Compile legacy PCIe routines conditionally
  dm: pcie_fsl: Add T4240 PCIe support
  t4240: dts: Added PCIe DT nodes
  powerpc: T4240RDB: Disable legacy PCIe driver when DM_PCI is enabled
  configs: T4240RDB: Enable PCIe driver
  powerpc: T102xRDB: Compile legacy PCIe routines conditionally
  dm: pcie_fsl: Add T102x PCIe support
  t102x: dts: Added PCIe DT nodes
  powerpc: T102xRDB: Remove the useless macro CONFIG_ARCH_T1040
  powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled
  configs: T1024RDB: Enable PCIe driver
  powerpc: T104xRDB: Compile legacy PCIe routines conditionally
  dm: pcie_fsl: Add T104x PCIe support
  t104x: dts: Added PCIe DT nodes
  powerpc: T104xRDB: Disable legacy PCIe driver when DM_PCI is enabled
  configs: T1042D4RDB: Enable PCIe driver
  powerpc: p1_p2_rdb: Compile legacy PCIe routines conditionally
  dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs
  P1020: dts: Added PCIe DT nodes
  powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled
  configs: P1020RDB: Enable PCIe driver
  P2020: dts: Added PCIe DT nodes
  configs: P2020RDB: Enable PCIe driver
  powerpc: p_corenet: Compile legacy PCIe routines conditionally
  dm: pcie_fsl: Add P2041 PCIe support
  P2041: dts: Added PCIe DT nodes
  powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled
  configs: P2041RDB: Enable PCIe driver
  dm: pcie_fsl: Add P3041 PCIe support
  P3041: dts: Added PCIe DT nodes
  powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled
  configs: P3041DS: Enable PCIe driver
  dm: pcie_fsl: Add P4080 PCIe support
  P4080: dts: Added PCIe DT nodes
  configs: P4080DS: Enable PCIe driver
  dm: pcie_fsl: Add P5040 PCIe support
  P5040: dts: Added PCIe DT nodes
  configs: P5040DS: Enable PCIe driver
  powerpc: MPC8548CDS: Compile legacy PCIe routines conditionally
  powerpc: MPC85xxCDS: Disable legacy PCI fixup when DM_PCI is selected
  dm: pcie_fsl: Add MPC8548 PCIe support
  MPC8548: dts: Added PCIe DT node
  powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled
  configs: MPC8548CDS: Enable PCIe driver

 arch/powerpc/dts/mpc8548-post.dtsi   |  9 
 arch/powerpc/dts/mpc8548cds.dts  |  6 +++
 arch/powerpc/dts/mpc8548cds_36b.dts  |  6 +++
 arch/powerpc/dts/p1020-post.dtsi | 20 +++
 arch/powerpc/dts/p1020rdb-pc.dts | 12 +
 arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 +
 arch/powerpc/dts/p1020rdb-pd.dts | 12 +
 arch/powerpc/dts/p2020-post.dtsi | 30 +++
 arch/powerpc/dts/p2020rdb-pc.dts | 17 ++
 arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 ++
 arch/powerpc/dts/p2041.dtsi  | 36 +
 arch/powerpc/dts/p3041.dtsi  | 48 +
 arch/powerpc/dts/p4080.dtsi  | 36 +
 arch/powerpc/dts/p5040.dtsi  | 36 +
 arch/powerpc/dts/t102x.dtsi  | 36 +
 arch/powerpc/dts/t104x.dtsi  | 48 +
 arch/powerpc/dts/t4240.dtsi  | 48 +
 board/freescale/common/cds_pci_ft.c  |  4 +-
 board/freescale/common/p_corenet/pci.c   |  2 +
 board/freescale/mpc8548cds/mpc8548cds.c  |  6 ++-
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c  |  4 +-
 board/freescale/t102xrdb/pci.c   |  2 +
 board/freescale/t104xrdb/pci.c   |  2 +
 board/freescale/t208xrdb/pci.c   |  2 +
 board/freescale/t4rdb/pci.c  |  2 +
 configs/MPC8548CDS_36BIT_defconfig   |  4 ++
 configs/MPC8548CDS_defconfig |  4 ++
 configs/MPC8548CDS_legacy_defconfig  |  4 ++
 configs/P1020RDB-PC_36BIT_NAND_defconfig |  4 ++
 configs/P1020RDB-PC_36BIT_SDCARD_defconfig   |  4 ++
 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig |  4 ++
 configs/P1020RDB-PC_36BIT_defconfig  |  4 ++
 configs/P1020RDB-PC_NAND_defconfig   |  4 ++
 configs/P1020RDB-PC_SDCARD_defconfig |  4 ++
 configs/P1020RDB-PC_SPIFLASH_defconfig   |  4 ++
 configs/P1020RDB-PC_defconfig|  4 ++
 configs/P1020RDB-PD_NAND_defconfig   |  4 ++
 configs/P1020RDB-PD_SDCARD_defconfig |  4 ++
 configs/P1020RDB-PD_SPIFLASH_defconfig   |  4 ++
 configs/P1020RDB-PD_defconfig|  4 ++
 configs/P2020RDB-PC_36BIT_NAND_defconfig |  4 ++
 configs/P2020RDB-PC_36BIT_SDCARD_defconfig   |  4 ++
 configs/P2020RDB-PC_36BIT_SPIFLASH

[U-Boot] [PATCH 02/47] powerpc: T208xRDB: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang 
---
 include/configs/T208xRDB.h | 36 +++-
 1 file changed, 19 insertions(+), 17 deletions(-)

diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 1a5a93e..b1ae050 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -439,49 +439,51 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PCIE2   /* PCIE controller 2 */
 #define CONFIG_PCIE3   /* PCIE controller 3 */
 #define CONFIG_PCIE4   /* PCIE controller 4 */
-#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
 /* controller 1, direct to uli, tgtid 3, Base address 2 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT  0x8000
-#define CONFIG_SYS_PCIE1_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE1_MEM_PHYS  0xcull
-#define CONFIG_SYS_PCIE1_MEM_SIZE  0x2000  /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT   0xf800
-#define CONFIG_SYS_PCIE1_IO_BUS0x
 #define CONFIG_SYS_PCIE1_IO_PHYS   0xff800ull
-#define CONFIG_SYS_PCIE1_IO_SIZE   0x0001  /* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT  0xa000
-#define CONFIG_SYS_PCIE2_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE2_MEM_PHYS  0xc2000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE  0x1000 /* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT   0xf801
-#define CONFIG_SYS_PCIE2_IO_BUS0x
 #define CONFIG_SYS_PCIE2_IO_PHYS   0xff801ull
-#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT  0xb000
-#define CONFIG_SYS_PCIE3_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE3_MEM_PHYS  0xc3000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE  0x1000  /* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT   0xf802
-#define CONFIG_SYS_PCIE3_IO_BUS0x
 #define CONFIG_SYS_PCIE3_IO_PHYS   0xff802ull
-#define CONFIG_SYS_PCIE3_IO_SIZE   0x0001  /* 64k */
 
 /* controller 4, Base address 203000 */
 #define CONFIG_SYS_PCIE4_MEM_VIRT   0xc000
-#define CONFIG_SYS_PCIE4_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE4_MEM_PHYS  0xc4000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE  0x1000  /* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS0x
 #define CONFIG_SYS_PCIE4_IO_PHYS   0xff803ull
-#define CONFIG_SYS_PCIE4_IO_SIZE   0x0001  /* 64k */
 
 #ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE1_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS0x
+#define CONFIG_SYS_PCIE1_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE2_MEM_SIZE  0x1000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS0x
+#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE3_MEM_SIZE  0x1000  /* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS0x
+#define CONFIG_SYS_PCIE3_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE4_MEM_SIZE  0x1000  /* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS0x
+#define CONFIG_SYS_PCIE4_IO_SIZE   0x0001  /* 64k */
 #define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
 #endif
 
-- 
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[U-Boot] [PATCH 01/47] powerpc: T208xRDB: Compile legacy PCIe routines conditionally

[Hou Zhiqiang]

Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang 
---
 board/freescale/t208xrdb/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c
index 161b8cb..adc128d 100644
--- a/board/freescale/t208xrdb/pci.c
+++ b/board/freescale/t208xrdb/pci.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 
+#if !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
 {
FT_FSL_PCI_SETUP;
 }
+#endif
-- 
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[U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes

[Hou Zhiqiang]

P1020 integrated 2 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang 
---
 arch/powerpc/dts/p1020-post.dtsi | 20 
 arch/powerpc/dts/p1020rdb-pc.dts | 12 
 arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 
 arch/powerpc/dts/p1020rdb-pd.dts | 12 
 4 files changed, 56 insertions(+)

diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index e1a4f50..1e5e678 100644
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -25,3 +25,23 @@
last-interrupt-source = <255>;
};
 };
+
+/* PCIe controller base address 0x9000 */
+&pci1 {
+   compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+   law_trgt_if = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+&pci0 {
+   compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+   law_trgt_if = <2>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
index fd68b8b..7ebaa61 100644
--- a/arch/powerpc/dts/p1020rdb-pc.dts
+++ b/arch/powerpc/dts/p1020rdb-pc.dts
@@ -18,6 +18,18 @@
soc: soc@ffe0 {
ranges = <0x0 0x0 0xffe0 0x10>;
};
+
+   pci1: pcie@ffe09000 {
+   reg = <0x0 0xffe09000 0x0 0x1000>;  /* registers */
+   ranges = <0x0100 0x0 0x 0x0 0xffc1 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xa000 0x0 0xa000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pci0: pcie@ffe0a000 {
+   reg = <0x0 0xffe0a000 0x0 0x1000>;  /* registers */
+   ranges = <0x0100 0x0 0x 0x0 0xffc0 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0x8000 0x0 0x8000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
 };
 
 /include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts 
b/arch/powerpc/dts/p1020rdb-pc_36b.dts
index a23d031..c0e5ef4 100644
--- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -18,6 +18,18 @@
soc: soc@fffe0 {
ranges = <0x0 0xf 0xffe0 0x10>;
};
+
+   pci1: pcie@fffe09000 {
+   reg = <0xf 0xffe09000 0x0 0x1000>;  /* registers */
+   ranges = <0x0100 0x0 0x 0xf 0xffc1 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xc000 0xc 0x2000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pci0: pcie@fffe0a000 {
+   reg = <0xf 0xffe0a000 0x0 0x1000>;  /* registers */
+   ranges = <0x0100 0x0 0x 0xf 0xffc0 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0x8000 0xc 0x 0x0 
0x2000>; /* non-prefetchable memory */
+   };
 };
 
 /include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
index 81f25a3..21174a0 100644
--- a/arch/powerpc/dts/p1020rdb-pd.dts
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -18,6 +18,18 @@
soc: soc@ffe0 {
ranges = <0x0 0x0 0xffe0 0x10>;
};
+
+   pci1: pcie@ffe09000 {
+   reg = <0x0 0xffe09000 0x0 0x1000>;  /* registers */
+   ranges = <0x0100 0x0 0x 0x0 0xffc1 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xa000 0x0 0xa000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pci0: pcie@ffe0a000 {
+   reg = <0x0 0xffe0a000 0x0 0x1000>;  /* registers */
+   ranges = <0x0100 0x0 0x 0x0 0xffc0 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0x8000 0x0 0x8000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
 };
 
 /include/ "p1020-post.dtsi"
-- 
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[U-Boot] [PATCH 10/47] dm: pcie_fsl: Add T102x PCIe support

[Hou Zhiqiang]

Add compatible string for T102x PCIe.

Signed-off-by: Hou Zhiqiang 
---
 drivers/pci/pcie_fsl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 961d8e3..25df84d 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -615,6 +615,7 @@ static struct fsl_pcie_data t2080_data = {
 };
 
 static const struct udevice_id fsl_pcie_ids[] = {
+   { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
{ .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
{ }
-- 
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[U-Boot] [PATCH 06/47] t4240: dts: Added PCIe DT nodes

[Hou Zhiqiang]

T4240 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 3.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang 
---
 arch/powerpc/dts/t4240.dtsi | 48 +
 1 file changed, 48 insertions(+)

diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi
index 4d8fc71..fc34974 100644
--- a/arch/powerpc/dts/t4240.dtsi
+++ b/arch/powerpc/dts/t4240.dtsi
@@ -99,4 +99,52 @@
clock-frequency = <0x0>;
};
};
+
+   pcie@ffe24 {
+   compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe24 0x0 0x4000>;   /* registers */
+   law_trgt_if = <0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf800 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe25 {
+   compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe25 0x0 0x4000>;   /* registers */
+   law_trgt_if = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf801 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe26 {
+   compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe26 0x0 0x4000>;   /* registers */
+   law_trgt_if = <2>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf802 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x4000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe27 {
+   compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe27 0x0 0x4000>;   /* registers */
+   law_trgt_if = <3>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf803 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x6000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
 };
-- 
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[U-Boot] [PATCH 08/47] configs: T4240RDB: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in T4240RDB defconfig.

Signed-off-by: Hou Zhiqiang 
---
 configs/T4240RDB_SDCARD_defconfig | 4 
 configs/T4240RDB_defconfig| 4 
 2 files changed, 8 insertions(+)

diff --git a/configs/T4240RDB_SDCARD_defconfig 
b/configs/T4240RDB_SDCARD_defconfig
index a70c237..cce4872 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -50,6 +50,10 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index d4ce176..bdadfa8 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -39,6 +39,10 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
-- 
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[U-Boot] [PATCH 14/47] configs: T1024RDB: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in T1024RDB defconfig.

Signed-off-by: Hou Zhiqiang 
---
 configs/T1024RDB_NAND_defconfig | 4 
 configs/T1024RDB_SDCARD_defconfig   | 4 
 configs/T1024RDB_SPIFLASH_defconfig | 4 
 configs/T1024RDB_defconfig  | 4 
 4 files changed, 16 insertions(+)

diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 30acd0e..faea7d2 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -60,6 +60,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T1024RDB_SDCARD_defconfig 
b/configs/T1024RDB_SDCARD_defconfig
index 7569e4e..bce2fc3 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -59,6 +59,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig 
b/configs/T1024RDB_SPIFLASH_defconfig
index 470674b..55f80f8 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -60,6 +60,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 146551d..f8b3227 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -48,6 +48,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-- 
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[U-Boot] [PATCH 37/47] P4080: dts: Added PCIe DT nodes

[Hou Zhiqiang]

P4080 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang 
---
 arch/powerpc/dts/p4080.dtsi | 36 
 1 file changed, 36 insertions(+)

diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi
index 7c8dbae..ab76680 100644
--- a/arch/powerpc/dts/p4080.dtsi
+++ b/arch/powerpc/dts/p4080.dtsi
@@ -80,4 +80,40 @@
clock-frequency = <0x0>;
};
};
+
+   pcie@ffe20 {
+   compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe20 0x0 0x1000>;   /* registers */
+   law_trgt_if = <0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf800 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe201000 {
+   compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+   law_trgt_if = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf801 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe202000 {
+   compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+   law_trgt_if = <2>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf802 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x4000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
 };
-- 
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[U-Boot] [PATCH 18/47] powerpc: T104xRDB: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang 
---
 include/configs/T104xRDB.h | 38 --
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 470f60a..5d9dd10 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -151,13 +151,11 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 
 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCIE1   /* PCIE controller 1 */
 #define CONFIG_PCIE2   /* PCIE controller 2 */
 #define CONFIG_PCIE3   /* PCIE controller 3 */
 #define CONFIG_PCIE4   /* PCIE controller 4 */
 
-#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -530,51 +528,55 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 /* controller 1, direct to uli, tgtid 3, Base address 2 */
 #ifdef CONFIG_PCIE1
 #defineCONFIG_SYS_PCIE1_MEM_VIRT   0x8000
-#defineCONFIG_SYS_PCIE1_MEM_BUS0xe000
 #defineCONFIG_SYS_PCIE1_MEM_PHYS   0xcull
-#define CONFIG_SYS_PCIE1_MEM_SIZE  0x1000  /* 256M */
 #define CONFIG_SYS_PCIE1_IO_VIRT   0xf800
-#define CONFIG_SYS_PCIE1_IO_BUS0x
 #define CONFIG_SYS_PCIE1_IO_PHYS   0xff800ull
-#define CONFIG_SYS_PCIE1_IO_SIZE   0x0001  /* 64k */
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #ifdef CONFIG_PCIE2
 #define CONFIG_SYS_PCIE2_MEM_VIRT  0x9000
-#define CONFIG_SYS_PCIE2_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE2_MEM_PHYS  0xc1000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE  0x1000  /* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT   0xf801
-#define CONFIG_SYS_PCIE2_IO_BUS0x
 #define CONFIG_SYS_PCIE2_IO_PHYS   0xff801ull
-#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
 #endif
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #ifdef CONFIG_PCIE3
 #define CONFIG_SYS_PCIE3_MEM_VIRT  0xa000
-#define CONFIG_SYS_PCIE3_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE3_MEM_PHYS  0xc2000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE  0x1000  /* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT   0xf802
-#define CONFIG_SYS_PCIE3_IO_BUS0x
 #define CONFIG_SYS_PCIE3_IO_PHYS   0xff802ull
-#define CONFIG_SYS_PCIE3_IO_SIZE   0x0001  /* 64k */
 #endif
 
 /* controller 4, Base address 203000 */
 #ifdef CONFIG_PCIE4
 #define CONFIG_SYS_PCIE4_MEM_VIRT  0xb000
-#define CONFIG_SYS_PCIE4_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE4_MEM_PHYS  0xc3000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE  0x1000  /* 256M */
 #define CONFIG_SYS_PCIE4_IO_VIRT   0xf803
-#define CONFIG_SYS_PCIE4_IO_BUS0x
 #define CONFIG_SYS_PCIE4_IO_PHYS   0xff803ull
-#define CONFIG_SYS_PCIE4_IO_SIZE   0x0001  /* 64k */
 #endif
 
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE1_MEM_SIZE  0x1000  /* 256M */
+#define CONFIG_SYS_PCIE1_IO_BUS0x
+#define CONFIG_SYS_PCIE1_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE2_MEM_SIZE  0x1000  /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS0x
+#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE3_MEM_SIZE  0x1000  /* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS0x
+#define CONFIG_SYS_PCIE3_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE4_MEM_SIZE  0x1000  /* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS0x
+#define CONFIG_SYS_PCIE4_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
 #endif /* CONFIG_PCI */
 
-- 
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[U-Boot] [PATCH 09/47] powerpc: T102xRDB: Compile legacy PCIe routines conditionally

[Hou Zhiqiang]

Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang 
---
 board/freescale/t102xrdb/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c
index 161b8cb..adc128d 100644
--- a/board/freescale/t102xrdb/pci.c
+++ b/board/freescale/t102xrdb/pci.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 
+#if !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
 {
FT_FSL_PCI_SETUP;
 }
+#endif
-- 
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[U-Boot] [PATCH 26/47] configs: P2020RDB: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in P2020RDB defconfig.

Signed-off-by: Hou Zhiqiang 
---
 configs/P2020RDB-PC_36BIT_NAND_defconfig | 4 
 configs/P2020RDB-PC_36BIT_SDCARD_defconfig   | 4 
 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 4 
 configs/P2020RDB-PC_36BIT_defconfig  | 4 
 configs/P2020RDB-PC_NAND_defconfig   | 4 
 configs/P2020RDB-PC_SDCARD_defconfig | 4 
 configs/P2020RDB-PC_SPIFLASH_defconfig   | 4 
 configs/P2020RDB-PC_defconfig| 4 
 8 files changed, 32 insertions(+)

diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig 
b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index d8c04e2..a51a34c 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -60,6 +60,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig 
b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 7c45996..9c97b3d 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig 
b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 5372d98..fee83e5 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig 
b/configs/P2020RDB-PC_36BIT_defconfig
index 79f4f3c..bb5c6bd 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -47,6 +47,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig 
b/configs/P2020RDB-PC_NAND_defconfig
index 2f91691..610bd96 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -59,6 +59,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig 
b/configs/P2020RDB-PC_SDCARD_defconfig
index a5cee06..46d430c 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -56,6 +56,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig 
b/configs/P2020RDB-PC_SPIFLASH_defconfig
index a2f9d87..f3eb66e 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 4000459..b94c67e 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -46,6 +46,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
-- 
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[U-Boot] [PATCH 28/47] dm: pcie_fsl: Add P2041 PCIe support

[Hou Zhiqiang]

Add compatible string for P2041 PCIe.

Signed-off-by: Hou Zhiqiang 
---
 drivers/pci/pcie_fsl.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index c8b8e3b..61f08e7 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -614,6 +614,12 @@ static struct fsl_pcie_data p1_p2_data = {
.stride = 0x1000,
 };
 
+static struct fsl_pcie_data p2041_data = {
+   .block_offset = 0x20,
+   .block_offset_mask = 0x3f,
+   .stride = 0x1000,
+};
+
 static struct fsl_pcie_data t2080_data = {
.block_offset = 0x24,
.block_offset_mask = 0x3f,
@@ -622,6 +628,7 @@ static struct fsl_pcie_data t2080_data = {
 
 static const struct udevice_id fsl_pcie_ids[] = {
{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
+   { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
-- 
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[U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang 
---
 include/configs/T102xRDB.h | 54 +-
 1 file changed, 15 insertions(+), 39 deletions(-)

diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 3715e25..4fb1709 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -500,72 +500,48 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PCIE1   /* PCIE controller 1 */
 #define CONFIG_PCIE2   /* PCIE controller 2 */
 #define CONFIG_PCIE3   /* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
-#define CONFIG_PCI_INDIRECT_BRIDGE
 
 #ifdef CONFIG_PCI
 /* controller 1, direct to uli, tgtid 3, Base address 2 */
 #ifdef CONFIG_PCIE1
 #defineCONFIG_SYS_PCIE1_MEM_VIRT   0x8000
-#ifdef CONFIG_PHYS_64BIT
-#defineCONFIG_SYS_PCIE1_MEM_BUS0xe000
 #defineCONFIG_SYS_PCIE1_MEM_PHYS   0xcull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS   0x8000
-#define CONFIG_SYS_PCIE1_MEM_PHYS  0x8000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE  0x1000  /* 256M */
 #define CONFIG_SYS_PCIE1_IO_VIRT   0xf800
-#define CONFIG_SYS_PCIE1_IO_BUS0x
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS   0xff800ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS   0xf800
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE   0x0001  /* 64k */
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #ifdef CONFIG_PCIE2
 #define CONFIG_SYS_PCIE2_MEM_VIRT  0x9000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE2_MEM_PHYS  0xc1000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS   0x9000
-#define CONFIG_SYS_PCIE2_MEM_PHYS  0x9000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE  0x1000  /* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT   0xf801
-#define CONFIG_SYS_PCIE2_IO_BUS0x
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS   0xff801ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS   0xf801
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
 #endif
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #ifdef CONFIG_PCIE3
 #define CONFIG_SYS_PCIE3_MEM_VIRT  0xa000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE3_MEM_PHYS  0xc2000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS   0xa000
-#define CONFIG_SYS_PCIE3_MEM_PHYS  0xa000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE  0x1000  /* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT   0xf802
-#define CONFIG_SYS_PCIE3_IO_BUS0x
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS   0xff802ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS   0xf802
 #endif
+
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE1_MEM_SIZE  0x1000  /* 256M */
+#define CONFIG_SYS_PCIE1_IO_BUS0x
+#define CONFIG_SYS_PCIE1_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE2_MEM_SIZE  0x1000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS0x
+#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE3_MEM_SIZE  0x1000  /* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS0x
 #define CONFIG_SYS_PCIE3_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_PCI_INDIRECT_BRIDGE
 #endif
 
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
-- 
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[U-Boot] [PATCH 33/47] P3041: dts: Added PCIe DT nodes

[Hou Zhiqiang]

P3041 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang 
---
 arch/powerpc/dts/p3041.dtsi | 48 +
 1 file changed, 48 insertions(+)

diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi
index 7d5c713..197896d 100644
--- a/arch/powerpc/dts/p3041.dtsi
+++ b/arch/powerpc/dts/p3041.dtsi
@@ -60,4 +60,52 @@
clock-frequency = <0x0>;
};
};
+
+   pcie@ffe20 {
+   compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe20 0x0 0x1000>;   /* registers */
+   law_trgt_if = <0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf800 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe201000 {
+   compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+   law_trgt_if = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf801 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe202000 {
+   compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+   law_trgt_if = <2>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf802 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x4000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe203000 {
+   compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe203000 0x0 0x1000>;   /* registers */
+   law_trgt_if = <3>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf803 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x6000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
 };
-- 
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[U-Boot] [PATCH 17/47] t104x: dts: Added PCIe DT nodes

[Hou Zhiqiang]

T104x integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang 
---
 arch/powerpc/dts/t104x.dtsi | 48 +
 1 file changed, 48 insertions(+)

diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi
index ff0da93..5998967 100644
--- a/arch/powerpc/dts/t104x.dtsi
+++ b/arch/powerpc/dts/t104x.dtsi
@@ -59,4 +59,52 @@
clock-frequency = <0x0>;
};
};
+
+   pcie@ffe24 {
+   compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe24 0x0 0x1000>;   /* registers */
+   law_trgt_if = <0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf800 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x 0x0 
0x1000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe25 {
+   compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe25 0x0 0x1000>;   /* registers */
+   law_trgt_if = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf801 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x1000 0x0 
0x1000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe26 {
+   compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe26 0x0 0x1000>;   /* registers */
+   law_trgt_if = <2>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf802 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0 
0x1000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe27 {
+   compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe27 0x0 0x1000>;   /* registers */
+   law_trgt_if = <3>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf803 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x3000 0x0 
0x1000>; /* non-prefetchable memory */
+   };
 };
-- 
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[U-Boot] [PATCH 42/47] powerpc: MPC8548CDS: Compile legacy PCIe routines conditionally

[Hou Zhiqiang]

Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang 
---
 board/freescale/mpc8548cds/mpc8548cds.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/board/freescale/mpc8548cds/mpc8548cds.c 
b/board/freescale/mpc8548cds/mpc8548cds.c
index 7d819d8..2799b5b 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -164,7 +164,7 @@ void lbc_sdram_init(void)
 #endif /* enable SDRAM init */
 }
 
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+#if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI)
 /* For some reason the Tundra PCI bridge shows up on itself as a
  * different device.  Work around that by refusing to configure it.
  */
@@ -189,6 +189,7 @@ static struct pci_config_table 
pci_mpc85xxcds_config_table[] = {
 static struct pci_controller pci1_hose;
 #endif /* CONFIG_PCI */
 
+#if !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -268,6 +269,7 @@ void pci_init_board(void)
 
fsl_pcie_init_board(first_free_busno);
 }
+#endif
 
 void configure_rgmii(void)
 {
@@ -349,7 +351,7 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
 }
 
-#if defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI)
 void ft_pci_setup(void *blob, bd_t *bd)
 {
FT_FSL_PCI_SETUP;
-- 
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[U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in T2080RDB defconfig.

Signed-off-by: Hou Zhiqiang 
---
 configs/T2080RDB_NAND_defconfig | 4 
 configs/T2080RDB_SDCARD_defconfig   | 4 
 configs/T2080RDB_SPIFLASH_defconfig | 4 
 configs/T2080RDB_defconfig  | 4 
 4 files changed, 16 insertions(+)

diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 7eb7058..30ec72b 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -57,6 +57,10 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080RDB_SDCARD_defconfig 
b/configs/T2080RDB_SDCARD_defconfig
index 9ea6698..22c2e05 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -56,6 +56,10 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig 
b/configs/T2080RDB_SPIFLASH_defconfig
index 988897b..e70fa0d 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -56,6 +56,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 3f7e282..b620349 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -45,6 +45,10 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
-- 
2.9.5

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[U-Boot] [PATCH 34/47] powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang 
---
 include/configs/corenet_ds.h | 63 +---
 1 file changed, 19 insertions(+), 44 deletions(-)

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index f974291..07844c1 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -54,7 +54,6 @@
 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_PCIE1   /* PCIE controller 1 */
 #define CONFIG_PCIE2   /* PCIE controller 2 */
-#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -362,68 +361,25 @@
 
 /* controller 1, direct to uli, tgtid 3, Base address 2 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT  0x8000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE1_MEM_PHYS  0xcull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS   0x8000
-#define CONFIG_SYS_PCIE1_MEM_PHYS  0x8000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE  0x2000  /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT   0xf800
-#define CONFIG_SYS_PCIE1_IO_BUS0x
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS   0xff800ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS   0xf800
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE   0x0001  /* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT  0xa000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE2_MEM_PHYS  0xc2000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS   0xa000
-#define CONFIG_SYS_PCIE2_MEM_PHYS  0xa000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE  0x2000  /* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT   0xf801
-#define CONFIG_SYS_PCIE2_IO_BUS0x
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS   0xff801ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS   0xf801
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT  0xc000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE3_MEM_PHYS  0xc4000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS   0xc000
-#define CONFIG_SYS_PCIE3_MEM_PHYS  0xc000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE  0x2000  /* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT   0xf802
-#define CONFIG_SYS_PCIE3_IO_BUS0x
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS   0xff802ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS   0xf802
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE   0x0001  /* 64k */
 
 /* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE4_MEM_PHYS  0xc6000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE  0x2000  /* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS0x
 #define CONFIG_SYS_PCIE4_IO_PHYS   0xff803ull
-#define CONFIG_SYS_PCIE4_IO_SIZE   0x0001  /* 64k */
 
 /* Qman/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS10
@@ -505,7 +461,26 @@
 #endif
 
 #ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE1_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE1_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS0x
+#define CONFIG_SYS_PCIE1_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE2_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS0x
+#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE3_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE3_IO_BUS0x
+#define CONFIG_SYS_PCIE3_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE4_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS0x
+#define CONFIG_SYS_PCIE4_IO_SIZE   0x0001  /* 64k */
+#endif
 
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
 #endif /* CONFIG_PCI */
-- 
2.9.5

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[U-Boot] [PATCH 23/47] powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled
for P1020, P1021, P1024, P1025 and P2020 RDB boards.

Signed-off-by: Hou Zhiqiang 
---
 include/configs/p1_p2_rdb_pc.h | 36 +++-
 1 file changed, 23 insertions(+), 13 deletions(-)

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index b1367a9..d3fb3da 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -215,8 +215,6 @@
 
 #define CONFIG_PCIE1   /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2   /* PCIE controller 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -580,44 +578,56 @@
  */
 
 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME  "PCIe SLOT"
 #define CONFIG_SYS_PCIE2_MEM_VIRT  0xa000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS   0xc000
 #define CONFIG_SYS_PCIE2_MEM_PHYS  0xc2000ull
 #else
-#define CONFIG_SYS_PCIE2_MEM_BUS   0xa000
 #define CONFIG_SYS_PCIE2_MEM_PHYS  0xa000
 #endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE  0x2000  /* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT   0xffc1
-#define CONFIG_SYS_PCIE2_IO_BUS0x
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS   0xfffc1ull
 #else
 #define CONFIG_SYS_PCIE2_IO_PHYS   0xffc1
 #endif
-#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
 
 /* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME  "mini PCIe SLOT"
 #define CONFIG_SYS_PCIE1_MEM_VIRT  0x8000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS   0x8000
 #define CONFIG_SYS_PCIE1_MEM_PHYS  0xcull
 #else
-#define CONFIG_SYS_PCIE1_MEM_BUS   0x8000
 #define CONFIG_SYS_PCIE1_MEM_PHYS  0x8000
 #endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE  0x2000  /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT   0xffc0
-#define CONFIG_SYS_PCIE1_IO_BUS0x
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS   0xfffc0ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS   0xffc0
 #endif
+
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE2_NAME  "PCIe SLOT"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS   0xc000
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS   0xa000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS0x
+#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
+
+#define CONFIG_SYS_PCIE1_NAME  "mini PCIe SLOT"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS   0x8000
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS   0x8000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS0x
 #define CONFIG_SYS_PCIE1_IO_SIZE   0x0001  /* 64k */
+#endif
 
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
 #endif /* CONFIG_PCI */
-- 
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[U-Boot] [PATCH 35/47] configs: P3041DS: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in P3041DS defconfig.

Signed-off-by: Hou Zhiqiang 
---
 configs/P3041DS_NAND_defconfig | 4 
 configs/P3041DS_SDCARD_defconfig   | 4 
 configs/P3041DS_SPIFLASH_defconfig | 4 
 configs/P3041DS_defconfig  | 4 
 4 files changed, 16 insertions(+)

diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index b315840..87958db 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 50dee40..90a0efe 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig 
b/configs/P3041DS_SPIFLASH_defconfig
index 984ff5f..7682877 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index 5728cbb..ce9289f 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-- 
2.9.5

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[U-Boot] [PATCH 27/47] powerpc: p_corenet: Compile legacy PCIe routines conditionally

[Hou Zhiqiang]

Compile the legacy PCIe initialization reoutines for P2041RDB,
P3041, P4080, P5020 and P5040 DS boards only when DM_PCI is
 not enabled.

Signed-off-by: Hou Zhiqiang 
---
 board/freescale/common/p_corenet/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/common/p_corenet/pci.c 
b/board/freescale/common/p_corenet/pci.c
index a2df928..a6abe66 100644
--- a/board/freescale/common/p_corenet/pci.c
+++ b/board/freescale/common/p_corenet/pci.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 
+#if !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
 {
FT_FSL_PCI_SETUP;
 }
+#endif
-- 
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[U-Boot] [PATCH 11/47] t102x: dts: Added PCIe DT nodes

[Hou Zhiqiang]

T102x integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang 
---
 arch/powerpc/dts/t102x.dtsi | 36 
 1 file changed, 36 insertions(+)

diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi
index 2393e31..c49fd21 100644
--- a/arch/powerpc/dts/t102x.dtsi
+++ b/arch/powerpc/dts/t102x.dtsi
@@ -49,4 +49,40 @@
clock-frequency = <0x0>;
};
};
+
+   pcie@ffe24 {
+   compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe24 0x0 0x1000>;   /* registers */
+   law_trgt_if = <0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf800 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x 0x0 
0x1000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe25 {
+   compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe25 0x0 0x1000>;   /* registers */
+   law_trgt_if = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf801 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x1000 0x0 
0x1000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe26 {
+   compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe26 0x0 0x1000>;   /* registers */
+   law_trgt_if = <2>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf802 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0 
0x1000>; /* non-prefetchable memory */
+   };
 };
-- 
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[U-Boot] [PATCH 36/47] dm: pcie_fsl: Add P4080 PCIe support

[Hou Zhiqiang]

Add compatible string for P4080 PCIe.

Signed-off-by: Hou Zhiqiang 
---
 drivers/pci/pcie_fsl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index a4e0cd1..f61e39e 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -630,6 +630,7 @@ static const struct udevice_id fsl_pcie_ids[] = {
{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
+   { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
-- 
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[U-Boot] [PATCH 41/47] configs: P5040DS: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in P5040DS defconfig.

Signed-off-by: Hou Zhiqiang 
---
 configs/P5040DS_NAND_defconfig | 4 
 configs/P5040DS_SDCARD_defconfig   | 4 
 configs/P5040DS_SPIFLASH_defconfig | 4 
 configs/P5040DS_defconfig  | 4 
 4 files changed, 16 insertions(+)

diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index cbccb4c..bab7561 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -42,6 +42,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index cdefb2d..517708a 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig 
b/configs/P5040DS_SPIFLASH_defconfig
index c636b16..cb019f2 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 6572ff1..31a8fca 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-- 
2.9.5

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[U-Boot] [PATCH 46/47] powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang 
---
 include/configs/MPC8548CDS.h | 22 ++
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 4252fbe..4809bbd 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -18,8 +18,6 @@
 #define CONFIG_PCI1/* PCI controller 1 */
 #define CONFIG_PCIE1   /* PCIE controller 1 (slot 1) */
 #undef CONFIG_PCI2
-#define CONFIG_FSL_PCI_INIT1   /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1   /* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT   1   /* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -343,24 +341,18 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI1_IO_SIZE0x0010  /* 1M */
 
 #ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_NAME  "Slot"
 #define CONFIG_SYS_PCIE1_MEM_VIRT  0xa000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE1_MEM_PHYS  0xc2000ull
 #else
-#define CONFIG_SYS_PCIE1_MEM_BUS   0xa000
 #define CONFIG_SYS_PCIE1_MEM_PHYS  0xa000
 #endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE  0x2000  /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT   0xe300
-#define CONFIG_SYS_PCIE1_IO_BUS0x
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS0xfe300ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS   0xe300
 #endif
-#define CONFIG_SYS_PCIE1_IO_SIZE   0x0010  /*   1M */
 #endif
 
 /*
@@ -386,6 +378,20 @@ extern unsigned long get_clock_freq(void);
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT1   /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1
+#define CONFIG_SYS_PCIE1_NAME  "Slot"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS   0xe000
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS   0xa000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS0x
+#define CONFIG_SYS_PCIE1_IO_SIZE   0x0010  /*   1M */
+#endif
+
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
 
 #endif /* CONFIG_PCI */
-- 
2.9.5

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[U-Boot] [PATCH 44/47] dm: pcie_fsl: Add MPC8548 PCIe support

[Hou Zhiqiang]

Add compatible string for MPC8548 PCIe.

Signed-off-by: Hou Zhiqiang 
---
 drivers/pci/pcie_fsl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 1411b1f..112f3b9 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -627,6 +627,7 @@ static struct fsl_pcie_data t2080_data = {
 };
 
 static const struct udevice_id fsl_pcie_ids[] = {
+   { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
-- 
2.9.5

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Re: [U-Boot] [PATCH] rockchip: dts: rk3399: Add 'same-as-spl' for Rock PI 4

[kever . yang]

On Tue, Jul 16, 2019 at 1:35 PM Andy Yan  wrote:
>
> Let the board continue boot from the storage device where
> it bootup.
>
> Signed-off-by: Andy Yan 
> ---

Reviewed-by: Jagan Teki 
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Applied to u-boot-rockchip, thanks!
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[U-Boot] [PATCH 38/47] configs: P4080DS: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in P4080DS defconfig.

Signed-off-by: Hou Zhiqiang 
---
 configs/P4080DS_SDCARD_defconfig   | 4 
 configs/P4080DS_SPIFLASH_defconfig | 4 
 configs/P4080DS_defconfig  | 4 
 3 files changed, 12 insertions(+)

diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index 0aaf09a..5e5b30c 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig 
b/configs/P4080DS_SPIFLASH_defconfig
index 3a91df2..29560f3 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index d89d69f..aa42a0b 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-- 
2.9.5

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[U-Boot] [PATCH 21/47] dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs

[Hou Zhiqiang]

Add compatible string for PCIe of P1020, P1021, P1024, P1025
and P2020 SoCs.

Signed-off-by: Hou Zhiqiang 
---
 drivers/pci/pcie_fsl.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index c4b4ace..c8b8e3b 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -608,6 +608,12 @@ static const struct dm_pci_ops fsl_pcie_ops = {
.write_config   = fsl_pcie_write_config,
 };
 
+static struct fsl_pcie_data p1_p2_data = {
+   .block_offset = 0xa000,
+   .block_offset_mask = 0x,
+   .stride = 0x1000,
+};
+
 static struct fsl_pcie_data t2080_data = {
.block_offset = 0x24,
.block_offset_mask = 0x3f,
@@ -615,6 +621,7 @@ static struct fsl_pcie_data t2080_data = {
 };
 
 static const struct udevice_id fsl_pcie_ids[] = {
+   { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
-- 
2.9.5

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[U-Boot] [PATCH 04/47] powerpc: T4RDB: Compile legacy PCIe routines conditionally

[Hou Zhiqiang]

Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang 
---
 board/freescale/t4rdb/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c
index 4100370..7d670e1 100644
--- a/board/freescale/t4rdb/pci.c
+++ b/board/freescale/t4rdb/pci.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 
+#if !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
 {
FT_FSL_PCI_SETUP;
 }
+#endif
-- 
2.9.5

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[U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes

[Hou Zhiqiang]

P2020 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang 
---
 arch/powerpc/dts/p2020-post.dtsi | 30 ++
 arch/powerpc/dts/p2020rdb-pc.dts | 17 +
 arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +
 3 files changed, 64 insertions(+)

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index f20d1fa..f696f35 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -25,3 +25,33 @@
last-interrupt-source = <255>;
};
 };
+
+/* PCIe controller base address 0x8000 */
+&pci2 {
+   compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+   law_trgt_if = <0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0x9000 */
+&pci1 {
+   compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+   law_trgt_if = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+&pci0 {
+   compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+   law_trgt_if = <2>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 4800b76..08befd4 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -18,6 +18,23 @@
soc: soc@ffe0 {
ranges = <0x0 0x0 0xffe0 0x10>;
};
+
+   pci2: pcie@ffe08000 {
+   reg = <0x0 0xffe08000 0x0 0x1000>;  /* registers */
+   status = "disabled";
+   };
+
+   pci1: pcie@ffe09000 {
+   reg = <0x0 0xffe09000 0x0 0x1000>;  /* registers */
+   ranges = <0x0100 0x0 0x 0x0 0xffc1 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xa000 0x0 0xa000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pci0: pcie@ffe0a000 {
+   reg = <0x0 0xffe0a000 0x0 0x1000>;  /* registers */
+   ranges = <0x0100 0x0 0x 0x0 0xffc0 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0x8000 0x0 0x8000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
 };
 
 /include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts 
b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 8323b90..04b2519 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -18,6 +18,23 @@
soc: soc@fffe0 {
ranges = <0x0 0xf 0xffe0 0x10>;
};
+
+   pci2: pcie@fffe08000 {
+   reg = <0xf 0xffe08000 0x0 0x1000>;  /* registers */
+   status = "disabled";
+   };
+
+   pci1: pcie@fffe09000 {
+   reg = <0xf 0xffe09000 0x0 0x1000>;  /* registers */
+   ranges = <0x0100 0x0 0x 0xf 0xffc1 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xc000 0xc 0x2000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pci0: pcie@fffe0a000 {
+   reg = <0xf 0xffe0a000 0x0 0x1000>;  /* registers */
+   ranges = <0x0100 0x0 0x 0xf 0xffc0 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0x8000 0xc 0x 0x0 
0x2000>; /* non-prefetchable memory */
+   };
 };
 
 /include/ "p2020-post.dtsi"
-- 
2.9.5

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[U-Boot] [PATCH 47/47] configs: MPC8548CDS: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in MPC8548CDS defconfig.

Signed-off-by: Hou Zhiqiang 
---
 configs/MPC8548CDS_36BIT_defconfig  | 4 
 configs/MPC8548CDS_defconfig| 4 
 configs/MPC8548CDS_legacy_defconfig | 4 
 3 files changed, 12 insertions(+)

diff --git a/configs/MPC8548CDS_36BIT_defconfig 
b/configs/MPC8548CDS_36BIT_defconfig
index f259f19..102716b 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -26,6 +26,10 @@ CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 72239da..9cccb60 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -25,6 +25,10 @@ CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/MPC8548CDS_legacy_defconfig 
b/configs/MPC8548CDS_legacy_defconfig
index f2420c3..782f827 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -25,6 +25,10 @@ CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
-- 
2.9.5

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[U-Boot] [PATCH 30/47] powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang 
---
 include/configs/P2041RDB.h | 55 +-
 1 file changed, 15 insertions(+), 40 deletions(-)

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index b433308..ba670d7 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -37,7 +37,6 @@
 #define CONFIG_PCIE1   /* PCIE controller 1 */
 #define CONFIG_PCIE2   /* PCIE controller 2 */
 #define CONFIG_PCIE3   /* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
 
 #define CONFIG_SYS_SRIO
@@ -354,60 +353,21 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 
 /* controller 1, direct to uli, tgtid 3, Base address 2 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT  0x8000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE1_MEM_PHYS  0xcull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS   0x8000
-#define CONFIG_SYS_PCIE1_MEM_PHYS  0x8000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE  0x2000  /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT   0xf800
-#define CONFIG_SYS_PCIE1_IO_BUS0x
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS   0xff800ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS   0xf800
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE   0x0001  /* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT  0xa000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE2_MEM_PHYS  0xc2000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS   0xa000
-#define CONFIG_SYS_PCIE2_MEM_PHYS  0xa000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE  0x2000  /* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT   0xf801
-#define CONFIG_SYS_PCIE2_IO_BUS0x
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS   0xff801ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS   0xf801
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT  0xc000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE3_MEM_PHYS  0xc4000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS   0xc000
-#define CONFIG_SYS_PCIE3_MEM_PHYS  0xc000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE  0x2000  /* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT   0xf802
-#define CONFIG_SYS_PCIE3_IO_BUS0x
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS   0xff802ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS   0xf802
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE   0x0001  /* 64k */
 
 /* Qman/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS10
@@ -489,7 +449,22 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 
 #ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE1_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE1_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS0x
+#define CONFIG_SYS_PCIE1_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE2_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS0x
+#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE3_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE3_IO_BUS0x
+#define CONFIG_SYS_PCIE3_IO_SIZE   0x0001  /* 64k */
+#endif
 
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
 #endif /* CONFIG_PCI */
-- 
2.9.5

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[U-Boot] [PATCH 45/47] MPC8548: dts: Added PCIe DT node

[Hou Zhiqiang]

MPC8548 integrated a PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for the PCIe controller.

Signed-off-by: Hou Zhiqiang 
---
 arch/powerpc/dts/mpc8548-post.dtsi  | 9 +
 arch/powerpc/dts/mpc8548cds.dts | 6 ++
 arch/powerpc/dts/mpc8548cds_36b.dts | 6 ++
 3 files changed, 21 insertions(+)

diff --git a/arch/powerpc/dts/mpc8548-post.dtsi 
b/arch/powerpc/dts/mpc8548-post.dtsi
index 5533a4b..2206f2d 100644
--- a/arch/powerpc/dts/mpc8548-post.dtsi
+++ b/arch/powerpc/dts/mpc8548-post.dtsi
@@ -25,3 +25,12 @@
last-interrupt-source = <255>;
};
 };
+
+&pcie {
+   compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq";
+   law_trgt_if = <2>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/mpc8548cds.dts b/arch/powerpc/dts/mpc8548cds.dts
index cceea34..3b927bd 100644
--- a/arch/powerpc/dts/mpc8548cds.dts
+++ b/arch/powerpc/dts/mpc8548cds.dts
@@ -18,6 +18,12 @@
soc: soc8548@e000 {
ranges = <0x0 0x0 0xe000 0x10>;
};
+
+   pcie: pcie@e000a000 {
+   reg = <0x0 0xe000a000 0x0 0x1000>;  /* registers */
+   ranges = <0x0100 0x0 0x 0x0 0xe300 0x0 
0x0010   /* downstream I/O */
+ 0x0200 0x0 0xa000 0x0 0xa000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
 };
 
 /include/ "mpc8548-post.dtsi"
diff --git a/arch/powerpc/dts/mpc8548cds_36b.dts 
b/arch/powerpc/dts/mpc8548cds_36b.dts
index faff35c..98d7c24 100644
--- a/arch/powerpc/dts/mpc8548cds_36b.dts
+++ b/arch/powerpc/dts/mpc8548cds_36b.dts
@@ -18,6 +18,12 @@
soc: soc8548@fe000 {
ranges = <0x0 0xf 0xe000 0x10>;
};
+
+   pcie: pcie@fe000a000 {
+   reg = <0xf 0xe000a000 0x0 0x1000>;  /* registers */
+   ranges = <0x0100 0x0 0x 0xf 0xe300 0x0 
0x0010   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
 };
 
 /include/ "mpc8548-post.dtsi"
-- 
2.9.5

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[U-Boot] [PATCH 19/47] configs: T1042D4RDB: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in T1042D4RDB defconfig.

Signed-off-by: Hou Zhiqiang 
---
 configs/T1042D4RDB_NAND_defconfig | 4 
 configs/T1042D4RDB_SDCARD_defconfig   | 4 
 configs/T1042D4RDB_SPIFLASH_defconfig | 4 
 configs/T1042D4RDB_defconfig  | 4 
 4 files changed, 16 insertions(+)

diff --git a/configs/T1042D4RDB_NAND_defconfig 
b/configs/T1042D4RDB_NAND_defconfig
index 2edd3b3..e51124b 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig 
b/configs/T1042D4RDB_SDCARD_defconfig
index f5a8613..fa9b3e3 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig 
b/configs/T1042D4RDB_SPIFLASH_defconfig
index 945740a..fdec9a2 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 3be988c..86c0a7f 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -46,6 +46,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-- 
2.9.5

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[U-Boot] [PATCH 39/47] dm: pcie_fsl: Add P5040 PCIe support

[Hou Zhiqiang]

Add compatible string for P5040 PCIe.

Signed-off-by: Hou Zhiqiang 
---
 drivers/pci/pcie_fsl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index f61e39e..1411b1f 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -631,6 +631,7 @@ static const struct udevice_id fsl_pcie_ids[] = {
{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
{ .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
+   { .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
-- 
2.9.5

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[U-Boot] [PATCH 16/47] dm: pcie_fsl: Add T104x PCIe support

[Hou Zhiqiang]

Add compatible string for T104x PCIe.

Signed-off-by: Hou Zhiqiang 
---
 drivers/pci/pcie_fsl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 25df84d..c4b4ace 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -616,6 +616,7 @@ static struct fsl_pcie_data t2080_data = {
 
 static const struct udevice_id fsl_pcie_ids[] = {
{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
+   { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
{ .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
{ }
-- 
2.9.5

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[U-Boot] [PATCH 29/47] P2041: dts: Added PCIe DT nodes

[Hou Zhiqiang]

P2041 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang 
---
 arch/powerpc/dts/p2041.dtsi | 36 
 1 file changed, 36 insertions(+)

diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi
index 9aa0422..55f7adc 100644
--- a/arch/powerpc/dts/p2041.dtsi
+++ b/arch/powerpc/dts/p2041.dtsi
@@ -60,4 +60,40 @@
clock-frequency = <0x0>;
};
};
+
+   pcie@ffe20 {
+   compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe20 0x0 0x1000>;   /* registers */
+   law_trgt_if = <0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf800 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe201000 {
+   compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+   law_trgt_if = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf801 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x2000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
+
+   pcie@ffe202000 {
+   compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+   reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+   law_trgt_if = <2>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   bus-range = <0x0 0xff>;
+   ranges = <0x0100 0x0 0x 0xf 0xf802 0x0 
0x0001   /* downstream I/O */
+ 0x0200 0x0 0xe000 0xc 0x4000 0x0 
0x2000>; /* non-prefetchable memory */
+   };
 };
-- 
2.9.5

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[U-Boot] [PATCH 15/47] powerpc: T104xRDB: Compile legacy PCIe routines conditionally

[Hou Zhiqiang]

Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang 
---
 board/freescale/t104xrdb/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c
index 9fd6659..6b666ba 100644
--- a/board/freescale/t104xrdb/pci.c
+++ b/board/freescale/t104xrdb/pci.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 
+#if !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
 {
FT_FSL_PCI_SETUP;
 }
+#endif
-- 
2.9.5

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[U-Boot] mkimage unable to assign sign value to fitimage

[deepak kumar Pradhan]

HI ,

I am using marvell armada 388 clearfog pro device.
I am using fitimage to upgrade my device. To make the device bootup secure
I want to sign the fitimage and verify the same in u-boot.
1. However I am observing that the mkimage is unable to assign sign value
to my fit image.
2. One more issue I am facing that is when I am enabling the CONFIG_FIT and
FIT_SIGNATURE, the mkimage is throughing error like below



*"mkimage -f fitimage-temp.its -k keys
fitimage-kernel-rfs-dtb.itbUnsupported signature algorithm (sha1,rs2048)
for 'signature@1' signature node in 'kernel@1' image nodemkimage Can't add
hashes to FIT blob"*

Can someone help me out and uide me what I am doing wrong?

Below are the outputs
*mkimage -F -k keys bkp-fitimage-initramfs-script.bin *
FIT description: U-Boot fitImage for Aprisa
NEXT/4.14.54+gitAUTOINC+7c0df4bf46/clearfog
Created: Tue Jul 16 12:25:27 2019
 Image 0 (kernel@1)
  Description:  Linux kernel
  Created:  Tue Jul 16 12:25:27 2019
  Type: Kernel Image
  Compression:  uncompressed
  Data Size:4906704 Bytes = 4791.70 KiB = 4.68 MiB
  Architecture: ARM
  OS:   Linux
  Load Address: 0x01314c40
  Entry Point:  0x01314c40
  Hash algo:crc32
  Hash value:   8aeccf3a
  Hash algo:sha1
  Hash value:   b8fafa028a78428a90304ab913877d2d0adbfd88

*  Sign algo:sha1,rs2048:my_key  Sign value:   unavailable*
  Timestamp:unavailable
 Image 1 (f...@armada-388-clearfog.dtb)
  Description:  Flattened Device Tree blob
  Created:  Tue Jul 16 12:25:27 2019
  Type: Flat Device Tree
  Compression:  uncompressed
  Data Size:18373 Bytes = 17.94 KiB = 0.02 MiB
  Architecture: ARM
  Hash algo:crc32
  Hash value:   dbe5de9d
  Hash algo:sha1
  Hash value:   c1b29ef3c908ecf4c9e800f573a7c33184954b4f
*  Sign algo:sha1,rs2048:my_key*
*  Sign value:   unavailable*
  Timestamp:unavailable

-- 
Deepak Kumar Pradhan
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[U-Boot] [PATCH 05/47] dm: pcie_fsl: Add T4240 PCIe support

[Hou Zhiqiang]

Add compatible string for T4240 PCIe.

Signed-off-by: Hou Zhiqiang 
---
 drivers/pci/pcie_fsl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index e13e5a6..961d8e3 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -616,6 +616,7 @@ static struct fsl_pcie_data t2080_data = {
 
 static const struct udevice_id fsl_pcie_ids[] = {
{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
+   { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
{ }
 };
 
-- 
2.9.5

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[U-Boot] [PATCH 07/47] powerpc: T4240RDB: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang 
---
 include/configs/T4240RDB.h | 35 +++
 1 file changed, 19 insertions(+), 16 deletions(-)

diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index a818f0c..8cdc17c 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -63,7 +63,6 @@
 #define CONFIG_PCIE1   /* PCIE controller 1 */
 #define CONFIG_PCIE2   /* PCIE controller 2 */
 #define CONFIG_PCIE3   /* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -178,44 +177,48 @@
 
 /* controller 1, direct to uli, tgtid 3, Base address 2 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT  0x8000
-#define CONFIG_SYS_PCIE1_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE1_MEM_PHYS  0xcull
-#define CONFIG_SYS_PCIE1_MEM_SIZE  0x2000  /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT   0xf800
-#define CONFIG_SYS_PCIE1_IO_BUS0x
 #define CONFIG_SYS_PCIE1_IO_PHYS   0xff800ull
-#define CONFIG_SYS_PCIE1_IO_SIZE   0x0001  /* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT  0xa000
-#define CONFIG_SYS_PCIE2_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE2_MEM_PHYS  0xc2000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE  0x2000  /* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT   0xf801
-#define CONFIG_SYS_PCIE2_IO_BUS0x
 #define CONFIG_SYS_PCIE2_IO_PHYS   0xff801ull
-#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT  0xc000
-#define CONFIG_SYS_PCIE3_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE3_MEM_PHYS  0xc4000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE  0x2000  /* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT   0xf802
-#define CONFIG_SYS_PCIE3_IO_BUS0x
 #define CONFIG_SYS_PCIE3_IO_PHYS   0xff802ull
-#define CONFIG_SYS_PCIE3_IO_SIZE   0x0001  /* 64k */
 
 /* controller 4, Base address 203000 */
 #define CONFIG_SYS_PCIE4_MEM_BUS   0xe000
 #define CONFIG_SYS_PCIE4_MEM_PHYS  0xc6000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE  0x2000  /* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS0x
 #define CONFIG_SYS_PCIE4_IO_PHYS   0xff803ull
-#define CONFIG_SYS_PCIE4_IO_SIZE   0x0001  /* 64k */
 
 #ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE1_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS0x
+#define CONFIG_SYS_PCIE1_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE2_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS0x
+#define CONFIG_SYS_PCIE2_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE3_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE3_IO_BUS0x
+#define CONFIG_SYS_PCIE3_IO_SIZE   0x0001  /* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS   0xe000
+#define CONFIG_SYS_PCIE4_MEM_SIZE  0x2000  /* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS0x
+#define CONFIG_SYS_PCIE4_IO_SIZE   0x0001  /* 64k */
 #define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
 
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
 #endif /* CONFIG_PCI */
-- 
2.9.5

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