[U-Boot] [PATCH] serial: Kconfig: make MXC_UART usable for MX7 and IMX8M

[Peng Fan]

i.MX7 and i.MX8M use mxc uart driver, so let's make the SoC could
use MXC_UART kconfig.

Signed-off-by: Peng Fan 
---
 drivers/serial/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 8a447fd6e3..e5657979ff 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -569,7 +569,7 @@ config MCFUART
 
 config MXC_UART
bool "IMX serial port support"
-   depends on MX5 || MX6
+   depends on MX5 || MX6 || MX7 || IMX8M
help
  If you have a machine based on a Motorola IMX CPU you
  can enable its onboard serial port by enabling this option.
-- 
2.16.4

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[U-Boot] [PATCH] spl: pass args to board_return_to_bootrom

[Peng Fan]

Pass spl_image and bootdev to board_return_bootrom.
i.MX8MN needs the args to let ROM to load images

Cc: Simon Glass 
Cc: Philipp Tomsich 
Cc: Kever Yang 
Signed-off-by: Peng Fan 
---

This is to prepare i.MX8MM ROMAPI support, and
This is an updated version for https://patchwork.ozlabs.org/patch/1128834/,
because there are changes in rockchip spl/tpl.

Kever, Philipp
 Please help review again. Thanks.

 arch/arm/cpu/arm926ejs/spear/spl.c | 5 -
 arch/arm/mach-rockchip/spl.c   | 5 -
 arch/arm/mach-rockchip/tpl.c   | 5 -
 common/spl/spl_bootrom.c   | 7 ---
 include/spl.h  | 3 ++-
 5 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c 
b/arch/arm/cpu/arm926ejs/spear/spl.c
index fc332fb626..a919a455eb 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -277,7 +277,8 @@ void board_init_f(ulong dummy)
  * BootROM code right after having initialized a few components like the DRAM).
  * The following function is called from SPL common code (board_init_r).
  */
-void board_return_to_bootrom(void)
+int board_return_to_bootrom(struct spl_image_info *spl_image,
+   struct spl_boot_device *bootdev)
 {
/*
 * Retrieve the BootROM's stack pointer and jump back to the start of
@@ -294,4 +295,6 @@ void board_return_to_bootrom(void)
  "bl back_to_bootrom;"
 #endif
  );
+
+   return 0;
 }
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index 33137cc5ef..92102b39e7 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -14,9 +14,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void board_return_to_bootrom(void)
+int board_return_to_bootrom(struct spl_image_info *spl_image,
+   struct spl_boot_device *bootdev)
 {
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+
+   return 0;
 }
 
 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
index 55f6e922d0..c3734cb070 100644
--- a/arch/arm/mach-rockchip/tpl.c
+++ b/arch/arm/mach-rockchip/tpl.c
@@ -77,9 +77,12 @@ void board_init_f(ulong dummy)
}
 }
 
-void board_return_to_bootrom(void)
+int board_return_to_bootrom(struct spl_image_info *spl_image,
+   struct spl_boot_device *bootdev)
 {
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+
+   return 0;
 }
 
 u32 spl_boot_device(void)
diff --git a/common/spl/spl_bootrom.c b/common/spl/spl_bootrom.c
index 076f5d8d93..0eefd39a51 100644
--- a/common/spl/spl_bootrom.c
+++ b/common/spl/spl_bootrom.c
@@ -6,8 +6,10 @@
 #include 
 #include 
 
-__weak void board_return_to_bootrom(void)
+__weak int board_return_to_bootrom(struct spl_image_info *spl_image,
+  struct spl_boot_device *bootdev)
 {
+   return 0;
 }
 
 static int spl_return_to_bootrom(struct spl_image_info *spl_image,
@@ -19,8 +21,7 @@ static int spl_return_to_bootrom(struct spl_image_info 
*spl_image,
 * the ROM), it will implement board_return_to_bootrom() and
 * should not return from it.
 */
-   board_return_to_bootrom();
-   return false;
+   return board_return_to_bootrom(spl_image, bootdev);
 }
 
 SPL_LOAD_IMAGE_METHOD("BOOTROM", 0, BOOT_DEVICE_BOOTROM, 
spl_return_to_bootrom);
diff --git a/include/spl.h b/include/spl.h
index a90f971a23..f4a5461b4e 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -382,7 +382,8 @@ void spl_optee_entry(void *arg0, void *arg1, void *arg2, 
void *arg3);
  * stage wants to return to the ROM code to continue booting, boards
  * can implement 'board_return_to_bootrom'.
  */
-void board_return_to_bootrom(void);
+int board_return_to_bootrom(struct spl_image_info *spl_image,
+   struct spl_boot_device *bootdev);
 
 /**
  * board_spl_fit_post_load - allow process images after loading finished
-- 
2.16.4

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Re: [U-Boot] [PATCH] board: amlogic: document alternative libretech-cc installation methods

[Peter Robinson]

On Wed, 7 Aug 2019, 04:25 Daniel Drake,  wrote:

> On Tue, Aug 6, 2019 at 4:31 PM Remi Pommarel  wrote:
> > I don't know if it worth being mentioned here, but there is also a
> > reverse engineered effort on bl31 for gxl.
> >
> > Thus it should be possible to use a bl31 built from mainline branch of
> > https://github.com/ARM-software/arm-trusted-firmware.
>
> That's really cool! I think I'll leave it for another day though, and
> leave this patch just about the alternative/easier installation of the
> existing blobs.
>
> Separately, it would be great to have an arm-trusted-firmware release
> that includes this new gxl work so that distros like Debian pick it
> up.
>

They release every 6 months or so, I would expect the next one around
September. It's unrelated to U-Boot thought.

>
>
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Re: [U-Boot] [PATCH] board: amlogic: document alternative libretech-cc installation methods

[Daniel Drake]

On Tue, Aug 6, 2019 at 4:31 PM Remi Pommarel  wrote:
> I don't know if it worth being mentioned here, but there is also a
> reverse engineered effort on bl31 for gxl.
>
> Thus it should be possible to use a bl31 built from mainline branch of
> https://github.com/ARM-software/arm-trusted-firmware.

That's really cool! I think I'll leave it for another day though, and
leave this patch just about the alternative/easier installation of the
existing blobs.

Separately, it would be great to have an arm-trusted-firmware release
that includes this new gxl work so that distros like Debian pick it
up.

Daniel
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[U-Boot] [PATCH] spi: add NXP FlexSPI driver

[Peng Fan]

Add NXP Flexspi driver for i.MX8 Family usage.
Flexible Serial Peripheral Interface (FlexSPI) host controller
supports two SPI channels and up to 4 external devices.
Each channel supports Single/Dual/Quad/Octal mode data
transfer (1/2/4/8 bidirectional data lines).

Signed-off-by: Peng Fan 
---
 drivers/spi/Kconfig|   19 +
 drivers/spi/Makefile   |1 +
 drivers/spi/fsl_fspi.c | 1291 
 drivers/spi/fsl_fspi.h |  170 +++
 4 files changed, 1481 insertions(+)
 create mode 100644 drivers/spi/fsl_fspi.c
 create mode 100644 drivers/spi/fsl_fspi.h

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f459c0a411..b71f289fb7 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -372,6 +372,25 @@ config FSL_ESPI
  access the SPI interface and SPI NOR flash on platforms embedding
  this Freescale eSPI IP core.
 
+config FSL_FSPI
+   bool "NXP FlexSPI driver"
+   help
+ Enable the NXP FlexSPI (FSPI) driver. This driver can be
+ used to access the SPI NOR flash on platforms embedding this
+ NXP IP core.
+
+if FSL_FSPI
+config FSPI_QUAD_SUPPORT
+   bool "FlexSPI QUAD support"
+   help
+ Enable Quad Read/write
+
+config FSPI_AHB
+   bool "FlexSPI AHB support"
+   help
+ Enable AHB buffer read
+endif
+
 config FSL_QSPI
bool "Freescale QSPI driver"
imply SPI_FLASH_BAR
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ae4f2958f8..867feb994b 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
 obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
 obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
+obj-$(CONFIG_FSL_FSPI) += fsl_fspi.o
 obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
 obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
diff --git a/drivers/spi/fsl_fspi.c b/drivers/spi/fsl_fspi.c
new file mode 100644
index 00..7f9d2f0b45
--- /dev/null
+++ b/drivers/spi/fsl_fspi.c
@@ -0,0 +1,1291 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "fsl_fspi.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define RX_BUFFER_SIZE 0x200
+#define TX_BUFFER_SIZE 0x400
+#define AHB_BUFFER_SIZE0x800
+
+/* SEQID */
+#define SEQID_READ 0
+#define SEQID_WREN 1
+#define SEQID_FAST_READ2
+#define SEQID_RDSR 3
+#define SEQID_SE   4
+#define SEQID_CHIP_ERASE   5
+#define SEQID_PP   6
+#define SEQID_RDID 7
+#define SEQID_BE_4K8
+#ifdef CONFIG_SPI_FLASH_BAR
+#define SEQID_BRRD 9
+#define SEQID_BRWR 10
+#define SEQID_RDEAR11
+#define SEQID_WREAR12
+#endif
+#define SEQID_RDEVCR   13
+#define SEQID_WREVCR   14
+#define SEQID_QUAD_OUTPUT  15
+#define SEQID_RDFSR16
+#define SEQID_EN4B 17
+#define SEQID_CRFSR18
+
+/* FSPI CMD */
+#define FSPI_CMD_PP0x02/* Page program (up to 256 bytes) */
+#define FSPI_CMD_RDSR  0x05/* Read status register */
+#define FSPI_CMD_WREN  0x06/* Write enable */
+#define FSPI_CMD_FAST_READ 0x0b/* Read data bytes (high frequency) */
+#define FSPI_CMD_READ  0x03/* Read data bytes */
+#define FSPI_CMD_BE_4K 0x20/* 4K erase */
+#define FSPI_CMD_CHIP_ERASE0xc7/* Erase whole flash chip */
+#define FSPI_CMD_SE0xd8/* Sector erase (usually 64KiB) */
+#define FSPI_CMD_RDID  0x9f/* Read JEDEC ID */
+
+/* Used for Micron, winbond and Macronix flashes */
+#defineFSPI_CMD_WREAR  0xc5/* EAR register write */
+#defineFSPI_CMD_RDEAR  0xc8/* EAR reigster read */
+
+/* Used for Spansion flashes only. */
+#defineFSPI_CMD_BRRD   0x16/* Bank register read */
+#defineFSPI_CMD_BRWR   0x17/* Bank register write */
+
+/* 4-byte address FSPI CMD - used on Spansion and some Macronix flashes */
+#define FSPI_CMD_FAST_READ_4B  0x0c/* Read data bytes (high frequency) */
+#define FSPI_CMD_PP_4B 0x12/* Page program (up to 256 bytes) */
+#define FSPI_CMD_SE_4B 0xdc/* Sector erase (usually 64KiB) */
+#define FSPI_CMD_BE_4K_4B  0x21/* 4K erase */
+
+#define FSPI_CMD_RD_EVCR   0x65/* Read EVCR register */
+#define FSPI_CMD_WR_EVCR   0x61/* Write EVCR register */
+
+#define FSPI_CMD_EN4B  0xB7
+
+/* 1-1-4 READ CMD */
+#define FSPI_CMD_QUAD_OUTPUT   0x6b
+#define FSPI_CMD_DDR_QUAD_OUTPUT   0x6d
+
+/* read flag status register */
+#define FSPI_CMD_RDFSR 0x70
+#define FSPI_CMD_CRFSR 0x50
+
+/* fsl_fspi_platdata flags */
+#define FSPI_FLAG_REGMAP_ENDIAN_B

[U-Boot] Standalone application support in SPL

[William Zhang]

Hi All,



Has anyone come across to the need to run the standalone application in
SPL?   Due to the onchip SRAM size limitation in our chip, we will need run
the small foot print SPL to initialization DDR before we load the u-boot
proper to the main DDR memory.  We will have to run our DDR initialization
in standalone application binary mode due to some restriction of library. I
posted a separate thread here
https://lists.denx.de/pipermail/u-boot/2019-August/379585.html.  Understand
SPL does not have a shell to load the application interactively but one can
load the binary from flash and jump to its entry point when it is needed
during the boot of SPL.



I looked through u-boot code and it is fairly straightforward to enable
standalone application in SPL.  All it takes are adding configure option in
spl/Kconfig, makefile changes to include export.c and examples folder and
jumptable init in the spl init time.



I do need to ifdef the do_reset as dummy for SPL in the _export.h due to
the fact that do_reset function is not available in SPL without enabling a
lot of supporting code.   It looks to me add ifdef is the simplest way to
go and does not break any other build.

#if !defined(CONFIG_SPL_STANDALONE)

   EXPORT_FUNC(do_reset, int, do_reset, cmd_tbl_t *,

  int , int , char * const [])

#else

   EXPORT_FUNC(dummy, void, do_reset, void)

#endif



Any feedback and comments are appreciated! I can post a patch for review
and contribute to u-boot if this sounds a good add-on for SPL.



Thanks,

William
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Re: [U-Boot] [PATCH] Update include/android_image.h from AOSP

[Sam Protsenko]

Hi Alex,

On Mon, Aug 5, 2019 at 11:25 PM Alex Deymo  wrote:
>
> This takes the latest changes from AOSP from the file
> include/bootimg/bootimg.h from the repository:
> https://android.googlesource.com/platform/system/tools/mkbootimg
> and update the U-Boot version with the latest changes.
>
> This file keeps the changes from AOSP to a minimum:
>  * Comments were converted from C++ to C style.
>  * Code inside __cplusplus #ifdef blocks were removed.
>  * C++11 struct extensions replaced with a single struct.
>
> Signed-off-by: Alex Deymo 
> ---

Thanks for submitting this, Alex.

Reviewed-by: Sam Protsenko 

Tom, can this be applied for -rc2? It shouldn't break anything, as all
fields are preserved (patch only adds new ones), and header size is
page_size everywhere anyway. I can send another patch on top of this
one, to change associated routines a bit, so that users are able to
boot boot.img v1 and v2 as well as legacy one (v0).

>  include/android_image.h | 120 ++--
>  1 file changed, 90 insertions(+), 30 deletions(-)
>
> diff --git a/include/android_image.h b/include/android_image.h
> index d78db9e2b7..0519ece368 100644
> --- a/include/android_image.h
> +++ b/include/android_image.h
> @@ -1,59 +1,78 @@
> -/* SPDX-License-Identifier: BSD-2-Clause */
> +/* SPDX-License-Identifier: BSD-3-Clause */
>  /*
>   * This is from the Android Project,
> - * Repository: https://android.googlesource.com/platform/system/core/
> - * File: mkbootimg/bootimg.h
> - * Commit: d162828814b08ada310846a33205befb69ef5799
> + * Repository: 
> https://android.googlesource.com/platform/system/tools/mkbootimg
> + * File: include/bootimg/bootimg.h
> + * Commit: e55998a0f2b61b685d5eb4a486ca3a0c680b1a2f
>   *
> - * Copyright (C) 2008 The Android Open Source Project
> + * Copyright (C) 2007 The Android Open Source Project
>   */
>
>  #ifndef _ANDROID_IMAGE_H_
>  #define _ANDROID_IMAGE_H_
>
> -typedef struct andr_img_hdr andr_img_hdr;
> -
>  #define ANDR_BOOT_MAGIC "ANDROID!"
>  #define ANDR_BOOT_MAGIC_SIZE 8
>  #define ANDR_BOOT_NAME_SIZE 16
>  #define ANDR_BOOT_ARGS_SIZE 512
>  #define ANDR_BOOT_EXTRA_ARGS_SIZE 1024
>
> +/*
> + * It is expected that callers would explicitly specify which version of the
> + * boot image header they need to use.
> + */
> +typedef struct andr_img_hdr andr_img_hdr;
> +
> +/* The bootloader expects the structure of andr_img_hdr with header
> + * version 0 to be as follows: */
>  struct andr_img_hdr {
> -   char magic[ANDR_BOOT_MAGIC_SIZE];
> +/* Must be ANDR_BOOT_MAGIC. */
> +char magic[ANDR_BOOT_MAGIC_SIZE];
>
> -   u32 kernel_size;/* size in bytes */
> -   u32 kernel_addr;/* physical load addr */
> +u32 kernel_size; /* size in bytes */
> +u32 kernel_addr; /* physical load addr */
>
> -   u32 ramdisk_size;   /* size in bytes */
> -   u32 ramdisk_addr;   /* physical load addr */
> +u32 ramdisk_size; /* size in bytes */
> +u32 ramdisk_addr; /* physical load addr */
>
> -   u32 second_size;/* size in bytes */
> -   u32 second_addr;/* physical load addr */
> +u32 second_size; /* size in bytes */
> +u32 second_addr; /* physical load addr */
>
> -   u32 tags_addr;  /* physical addr for kernel tags */
> -   u32 page_size;  /* flash page size we assume */
> -   u32 unused; /* reserved for future expansion: MUST be 0 */
> +u32 tags_addr; /* physical addr for kernel tags */
> +u32 page_size; /* flash page size we assume */
>
> -   /* operating system version and security patch level; for
> -* version "A.B.C" and patch level "Y-M-D":
> -* ver = A << 14 | B << 7 | C (7 bits for each of A, B, C)
> -* lvl = ((Y - 2000) & 127) << 4 | M  (7 bits for Y, 4 bits for M)
> -* os_version = ver << 11 | lvl */
> -   u32 os_version;
> +/* Version of the boot image header. */
> +u32 header_version;
>
> -   char name[ANDR_BOOT_NAME_SIZE]; /* asciiz product name */
> +/* Operating system version and security patch level.
> + * For version "A.B.C" and patch level "Y-M-D":
> + *   (7 bits for each of A, B, C; 7 bits for (Y-2000), 4 bits for M)
> + *   os_version = A[31:25] B[24:18] C[17:11] (Y-2000)[10:4] M[3:0] */
> +u32 os_version;
>
> -   char cmdline[ANDR_BOOT_ARGS_SIZE];
> +char name[ANDR_BOOT_NAME_SIZE]; /* asciiz product name */
>
> -   u32 id[8]; /* timestamp / checksum / sha1 / etc */
> +char cmdline[ANDR_BOOT_ARGS_SIZE];
>
> -   /* Supplemental command line data; kept here to maintain
> -* binary compatibility with older versions of mkbootimg */
> -   char extra_cmdline[ANDR_BOOT_EXTRA_ARGS_SIZE];
> +u32 id[8]; /* timestamp / checksum / sha1 / etc */
> +
> +/* Supplemental command line data; kept here to maintain
> + * binary compatibility with older versions of mkbootimg. */
> +char extra_cmdline[ANDR_BOOT_EXTRA_ARGS

Re: [U-Boot] EFI_PXE_BASE_CODE_PROTOCOL

[Leif Lindholm]

On Tue, Aug 06, 2019 at 08:52:09PM +0200, Heinrich Schuchardt wrote:
> > > > EFI_PXE_BASE_CODE_PACKET DhcpAck is a union:
> > > > 
> > > > typedef union {
> > > >   UINT8 Raw[1472];
> > > >   EFI_PXE_BASE_CODE_DHCPV4_PACKET   Dhcpv4;
> > > >   EFI_PXE_BASE_CODE_DHCPV6_PACKET   Dhcpv6;
> > > > } EFI_PXE_BASE_CODE_PACKET;
> > > > 
> > > > Should the check be done in grub_efi_net_config_real()?
> > > 
> > > Possibly. I've cc:d Peter since he's the last person I know who took a
> > > proper look at this.
> > 
> > That's actually what we've got in our current patch set, based on
> > Michael Chang at SuSE's https work.  Javier Martinez (cc'd) is working
> > on getting those ready for upstream, but in the mean time, check out the
> > patches nearby to:
> > 
> > https://github.com/rhboot/grub2/commit/4f977935a9271727bf21889526fdf82f0fc8fed9
> 
> Thank you for the link.
> 
> There are currently no plans to implement these device paths in U-Boot:
> 
> * IPv4 Device Path
> * IPv6 Device Path
> * Uniform Resource Identifiers (URI) Device Path
> 
> I assume that these device paths would only be installed on handles
> implementing the EFI DHCPv4 Protocol or the EFI DHCPv6 Protocol but
> could not identify the relevant information in the specification.

10.3.4.12/13 (UEFI 2.8 spec) for IPv4/IPv6.
10.3.4.23 for URI.
(And 10.3.4.21 for iSCSI.)

But if you are only asking because you found the (NULLed-out) PXE
protocol implemented, then I would suggest we can ignore this for now.

I guess it could be useful for netbooting GRUB (the device paths, and
passing DHCP information retrieved by U-Boot into GRUB), not the
EFI_PXE_BASE_CODE_PROTOCOL).

/
Leif
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Re: [U-Boot] EFI_PXE_BASE_CODE_PROTOCOL

[Heinrich Schuchardt]

On 8/6/19 7:02 PM, Peter Jones wrote:

On Tue, Aug 06, 2019 at 09:44:14AM +0100, Leif Lindholm wrote:

+Peter Jones (sorry Peter)


+ Javier Martinez Canillas


On Tue, Aug 06, 2019 at 08:34:58AM +0200, Heinrich Schuchardt wrote:

iPXE uses the EFI simple network protocol to execute DHCP.


OK.


Can GRUB already do the same when the EFI_PXE_BASE_CODE_PROTOCOL is not
present?


Yes. As of very recently (proper* DHCP support was only merged in
March 2019, so is included in 2.04 release, prior to that it
technically performed BOOTP).

SNP means you do your own networking - it gives you access to the raw
(usually) Ethernet packets.

* proper as in "it now conceptually does the correct thing", not as in
   "I have extensively tested this".


What I do not understand about GRUB's grub_net_configure_by_dhcp_ack()
is that it silently assumes IPv4 being used without even checking. This
contradicts the definition of the PXE base code protocol in the UEFI
standard:


Well, it would not surprise me if this function predates GRUB's UEFI
support.

It actually gets even slightly messier when you look at what GRUB does
when netbooting itself; it starts out using MNP (and hence IP
addresses assigned by UEFI) to load its modules, switching to SNP once
it loads efinet.mod.


EFI_PXE_BASE_CODE_PACKET DhcpAck is a union:

typedef union {
  UINT8 Raw[1472];
  EFI_PXE_BASE_CODE_DHCPV4_PACKET   Dhcpv4;
  EFI_PXE_BASE_CODE_DHCPV6_PACKET   Dhcpv6;
} EFI_PXE_BASE_CODE_PACKET;

Should the check be done in grub_efi_net_config_real()?


Possibly. I've cc:d Peter since he's the last person I know who took a
proper look at this.


That's actually what we've got in our current patch set, based on
Michael Chang at SuSE's https work.  Javier Martinez (cc'd) is working
on getting those ready for upstream, but in the mean time, check out the
patches nearby to:

https://github.com/rhboot/grub2/commit/4f977935a9271727bf21889526fdf82f0fc8fed9



Thank you for the link.

There are currently no plans to implement these device paths in U-Boot:

* IPv4 Device Path
* IPv6 Device Path
* Uniform Resource Identifiers (URI) Device Path

I assume that these device paths would only be installed on handles
implementing the EFI DHCPv4 Protocol or the EFI DHCPv6 Protocol but
could not identify the relevant information in the specification.

Best regards

Heinrich
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Re: [U-Boot] [PATCH 1/2] watchdog: imx: Add DT ext-reset handling

[Robert Hancock]

On 2019-08-06 11:11 a.m., Marek Vasut wrote:
> On 8/6/19 7:05 PM, Robert Hancock wrote:
>> The Linux imx2_wdt driver uses a fsl,ext-reset-output boolean in the
>> device tree to specify whether the board design should use the external
>> reset instead of the internal reset. Use this boolean to determine which
>> mode to use rather than using external reset unconditionally.
>>
>> For the legacy non-DM mode, the external reset is always used in order
>> to maintain the previous behavior.
>>
>> Signed-off-by: Robert Hancock 
> 
> [...]
> 
>> @@ -124,6 +129,8 @@ static int imx_wdt_probe(struct udevice *dev)
>>  if (!priv->base)
>>  return -ENOENT;
>>  
>> +priv->ext_reset = dev_read_bool(dev, "fsl,ext-reset-output");
>> +
> 
> Do we need a vendor-specific, undocumented, DT property ?

It is documented in Linux in
Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt:

- fsl,ext-reset-output: If present the watchdog device is configured to
  assert its external reset (WDOG_B) instead of issuing a software reset.

I'm not aware of anything non-vendor-specific defined for this.

-- 
Robert Hancock
Senior Software Developer
SED Systems, a division of Calian Ltd.
Email: hanc...@sedsystems.ca
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Re: [U-Boot] [PATCH 1/2] watchdog: imx: Add DT ext-reset handling

[Marek Vasut]

On 8/6/19 7:05 PM, Robert Hancock wrote:
> The Linux imx2_wdt driver uses a fsl,ext-reset-output boolean in the
> device tree to specify whether the board design should use the external
> reset instead of the internal reset. Use this boolean to determine which
> mode to use rather than using external reset unconditionally.
> 
> For the legacy non-DM mode, the external reset is always used in order
> to maintain the previous behavior.
> 
> Signed-off-by: Robert Hancock 

[...]

> @@ -124,6 +129,8 @@ static int imx_wdt_probe(struct udevice *dev)
>   if (!priv->base)
>   return -ENOENT;
>  
> + priv->ext_reset = dev_read_bool(dev, "fsl,ext-reset-output");
> +

Do we need a vendor-specific, undocumented, DT property ?
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Re: [U-Boot] [PATCH 2/2] efi_loader: set the dhcp ack received flag

[Heinrich Schuchardt]

On 8/4/19 1:52 PM, Heinrich Schuchardt wrote:

On 8/2/19 9:26 PM, Patrick Wildt wrote:

On Wed, Apr 10, 2019 at 11:24:53AM +0200, Patrick Wildt wrote:

On Wed, Apr 10, 2019 at 11:20:35AM +0200, Patrick Wildt wrote:

On Thu, Jan 31, 2019 at 07:29:04PM +0100, Heinrich Schuchardt wrote:

Do we really need multiple functions to update the DHCP status?

I would prefer a single function with a parameter telling which DHCP
status has been reached.



I think this diff below might be better.  There we have an update
function that is called after it switch the state, and on REQUESTING
we save the packet information and on BOUND we received the ack.



The current network device can be determined via eth_get_dev().
In function eth_current_changed() this eth_get_dev() function is
used to
update the ethact environment variable.

If we have a single update function we can determine the active
network
device there.


The efi network object is only created on bootefi, so there is no DHCP
going on at that point.  It all happens some time before bootefi is
called.  The only thing that we could do is try to memorize for which
ethernet we received the DHCP packets, and when we create the EFI
network object we can try to see if the DHCP packets match to the
current ethernet we create the object for.

Patrick


Updated diff.  We should probably reset the DHCP Ack flag when we
switch to the REQUEST state.  Thus on a second dhcp call, where we
might get a different IP (on a different device) the ACK is properly
reset.

diff --git a/include/efi_loader.h b/include/efi_loader.h
index 00b81c6010..7e8f3b04b5 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -290,8 +290,8 @@ efi_status_t efi_smbios_register(void);
  struct efi_simple_file_system_protocol *
  efi_fs_from_path(struct efi_device_path *fp);

-/* Called by networking code to memorize the dhcp ack package */
-void efi_net_set_dhcp_ack(void *pkt, int len);
+/* Called by networking code to memorize dhcp information */
+void efi_net_update_dhcp(int state, void *pkt, int len);
  /* Called by efi_set_watchdog_timer to reset the timer */
  efi_status_t efi_set_watchdog(unsigned long timeout);

@@ -578,7 +578,7 @@ static inline efi_status_t
efi_add_runtime_mmio(void *mmio_ptr, u64 len)
  static inline void efi_restore_gd(void) { }
  static inline void efi_set_bootdev(const char *dev, const char *devnr,
 const char *path) { }
-static inline void efi_net_set_dhcp_ack(void *pkt, int len) { }
+static inline void efi_net_update_dhcp(int state, void *pkt, int
len) {}
  static inline void efi_print_image_infos(void *pc) { }

  #endif /* CONFIG_IS_ENABLED(EFI_LOADER) */
diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c
index c7d9da8521..192e7f0bb7 100644
--- a/lib/efi_loader/efi_net.c
+++ b/lib/efi_loader/efi_net.c
@@ -8,6 +8,7 @@
  #include 
  #include 
  #include 
+#include "../net/bootp.h"

  static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_GUID;
  static const efi_guid_t efi_pxe_guid = EFI_PXE_GUID;
@@ -15,6 +16,7 @@ static struct efi_pxe_packet *dhcp_ack;
  static bool new_rx_packet;
  static void *new_tx_packet;
  static void *transmit_buffer;
+static int dhcp_ack_received;

  /*
   * The notification function of this event is called in every timer
cycle
@@ -522,18 +524,24 @@ out:
  }

  /**
- * efi_net_set_dhcp_ack() - take note of a selected DHCP IP address
+ * efi_net_update_dhcp() - take note of DHCP information
   *
   * This function is called by dhcp_handler().
   */
-void efi_net_set_dhcp_ack(void *pkt, int len)
+void efi_net_update_dhcp(int state, void *pkt, int len)
  {
  int maxsize = sizeof(*dhcp_ack);

  if (!dhcp_ack)
  dhcp_ack = malloc(maxsize);

-    memcpy(dhcp_ack, pkt, min(len, maxsize));
+    if (state == REQUESTING) {
+    memcpy(dhcp_ack, pkt, min(len, maxsize));
+    dhcp_ack_received = 0;
+    }
+
+    if (state == BOUND)
+    dhcp_ack_received = 1;
  }

  /**
@@ -645,8 +653,10 @@ efi_status_t efi_net_register(void)
  netobj->net_mode.if_type = ARP_ETHER;

  netobj->pxe.mode = &netobj->pxe_mode;
-    if (dhcp_ack)
+    if (dhcp_ack) {
  netobj->pxe_mode.dhcp_ack = *dhcp_ack;
+    netobj->pxe_mode.dhcp_ack_received = dhcp_ack_received;
+    }

  /*
   * Create WaitForPacket event.
diff --git a/net/bootp.c b/net/bootp.c
index 9a2b512e4a..987fc47d06 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -1067,11 +1067,11 @@ static void dhcp_handler(uchar *pkt, unsigned
dest, struct in_addr sip,
  strlen(CONFIG_SYS_BOOTFILE_PREFIX)) == 0) {
  #endif    /* CONFIG_SYS_BOOTFILE_PREFIX */
  dhcp_packet_process_options(bp);
-    efi_net_set_dhcp_ack(pkt, len);

  debug("TRANSITIONING TO REQUESTING STATE\n");
  dhcp_state = REQUESTING;

+    efi_net_update_dhcp(dhcp_state, pkt, len);
  net_set_timeout_handler(5000, bootp_timeout_handler);
  dhcp_send_request_packet(bp);
  #

[U-Boot] [PATCH v4 2/5] usb: usb_submit_int_msg -> usb_int_msg

[Michal Suchanek]

This aligns naming with usb_bulk_msg and usb_control_msg.

Signed-off-by: Michal Suchanek 
---
v2: new patch
v4: fix indentation of function arguments
---
 common/usb.c | 4 ++--
 common/usb_kbd.c | 8 
 include/usb.h| 4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/common/usb.c b/common/usb.c
index b70f614d244f..14b27521395c 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -194,8 +194,8 @@ int usb_disable_asynch(int disable)
 /*
  * submits an Interrupt Message
  */
-int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
-   void *buffer, int transfer_len, int interval)
+int usb_int_msg(struct usb_device *dev, unsigned long pipe,
+   void *buffer, int transfer_len, int interval)
 {
return submit_int_msg(dev, pipe, buffer, transfer_len, interval);
 }
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 5ee6006012f2..aafa08f3c004 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -339,8 +339,8 @@ static inline void usb_kbd_poll_for_event(struct usb_device 
*dev)
struct usb_kbd_pdata *data = dev->privptr;
 
/* Submit a interrupt transfer request */
-   if (usb_submit_int_msg(dev, data->intpipe, &data->new[0],
-  data->intpktsize, data->intinterval) >= 0)
+   if (usb_int_msg(dev, data->intpipe, &data->new[0],
+   data->intpktsize, data->intinterval) >= 0)
usb_kbd_irq_worker(dev);
 #elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP) || \
   defined(CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE)
@@ -503,8 +503,8 @@ static int usb_kbd_probe_dev(struct usb_device *dev, 
unsigned int ifnum)
if (usb_get_report(dev, iface->desc.bInterfaceNumber,
   1, 0, data->new, USB_KBD_BOOT_REPORT_SIZE) < 0) {
 #else
-   if (usb_submit_int_msg(dev, data->intpipe, data->new, data->intpktsize,
-  data->intinterval) < 0) {
+   if (usb_int_msg(dev, data->intpipe, data->new, data->intpktsize,
+   data->intinterval) < 0) {
 #endif
printf("Failed to get keyboard state from device %04x:%04x\n",
   dev->descriptor.idVendor, dev->descriptor.idProduct);
diff --git a/include/usb.h b/include/usb.h
index 420a30e49fa1..0d38d8333a98 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -261,8 +261,8 @@ int usb_control_msg(struct usb_device *dev, unsigned int 
pipe,
void *data, unsigned short size, int timeout);
 int usb_bulk_msg(struct usb_device *dev, unsigned int pipe,
void *data, int len, int *actual_length, int timeout);
-int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
-   void *buffer, int transfer_len, int interval);
+int usb_int_msg(struct usb_device *dev, unsigned long pipe,
+   void *buffer, int transfer_len, int interval);
 int usb_disable_asynch(int disable);
 int usb_maxpacket(struct usb_device *dev, unsigned long pipe);
 int usb_get_configuration_no(struct usb_device *dev, int cfgno,
-- 
2.22.0

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[U-Boot] [PATCH v4 1/5] usb_kdb: only process events succesfully received

[Michal Suchanek]

Causes unbound key repeat on error otherwise.

Signed-off-by: Michal Suchanek 
---
v2: fix indentation
v4: fix ! condition to >= 0
---
 common/usb_kbd.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index cc99c6be0720..5ee6006012f2 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -339,10 +339,9 @@ static inline void usb_kbd_poll_for_event(struct 
usb_device *dev)
struct usb_kbd_pdata *data = dev->privptr;
 
/* Submit a interrupt transfer request */
-   usb_submit_int_msg(dev, data->intpipe, &data->new[0], data->intpktsize,
-  data->intinterval);
-
-   usb_kbd_irq_worker(dev);
+   if (usb_submit_int_msg(dev, data->intpipe, &data->new[0],
+  data->intpktsize, data->intinterval) >= 0)
+   usb_kbd_irq_worker(dev);
 #elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP) || \
   defined(CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE)
 #if defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP)
-- 
2.22.0

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[U-Boot] [PATCH v4 3/5] usb: storage: submit_int_msg -> usb_int_msg

[Michal Suchanek]

Use the wrapper as other callers do.

Signed-off-by: Michal Suchanek 
---
v2: usb_submit_int_msg -> usb_int_msg
v3: fix indentation
---
 common/usb_storage.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/usb_storage.c b/common/usb_storage.c
index 8c889bb1a648..995a96baa57d 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -650,8 +650,8 @@ static int usb_stor_CBI_get_status(struct scsi_cmd *srb, 
struct us_data *us)
int timeout;
 
us->ip_wanted = 1;
-   submit_int_msg(us->pusb_dev, us->irqpipe,
-   (void *) &us->ip_data, us->irqmaxp, us->irqinterval);
+   usb_int_msg(us->pusb_dev, us->irqpipe,
+   (void *) &us->ip_data, us->irqmaxp, us->irqinterval);
timeout = 1000;
while (timeout--) {
if (us->ip_wanted == 0)
-- 
2.22.0

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[U-Boot] [PATCH v4 5/5] dwc2: use the nonblock argument in submit_int_msg

[Michal Suchanek]

An USB 1.1 keyboard connected to dwc2 through a high-speed hub does not
report status until it changes. With this patch you can enable keyboard
by pressing a key while USB devices are probed. Without a keypress no
state is reported and the probe times out. We don't want to wait for a
keypress or timeout while polling for keypresses so implement an int_msg
nonblock variant that exits early on error.

Signed-off-by: Michal Suchanek 
---
v2: move superfluous hunk to earlier patch
---
 drivers/usb/host/dwc2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index b4121a49b805..78829d56199c 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -1123,7 +1123,7 @@ int _submit_int_msg(struct dwc2_priv *priv, struct 
usb_device *dev,
return -ETIMEDOUT;
}
ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
-   if (ret != -EAGAIN)
+   if ((ret != -EAGAIN) || nonblock)
return ret;
}
 }
-- 
2.22.0

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[U-Boot] [PATCH v4 4/5] usb: Add nonblock argument to submit_int_msg

[Michal Suchanek]

This will be used to implement non-blocking keyboard polling in case of
errors.

Signed-off-by: Michal Suchanek 
---
v2: add missing hunk from last patch
v4:
  - propagate nonblock argument to wrapper
  - add documentation of nonblock argument to wrapper
---
 common/usb.c  |  9 ++---
 common/usb_kbd.c  |  4 ++--
 common/usb_storage.c  |  2 +-
 drivers/usb/host/dwc2.c   | 12 +++-
 drivers/usb/host/ehci-hcd.c   | 13 -
 drivers/usb/host/ohci-hcd.c   |  4 ++--
 drivers/usb/host/r8a66597-hcd.c   |  2 +-
 drivers/usb/host/sl811-hcd.c  |  2 +-
 drivers/usb/host/usb-uclass.c |  4 ++--
 drivers/usb/host/xhci.c   | 13 -
 drivers/usb/musb-new/musb_uboot.c | 12 +++-
 include/usb.h |  6 +++---
 12 files changed, 48 insertions(+), 35 deletions(-)

diff --git a/common/usb.c b/common/usb.c
index 14b27521395c..d9bcb5a57e89 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -192,12 +192,15 @@ int usb_disable_asynch(int disable)
  */
 
 /*
- * submits an Interrupt Message
+ * submits an Interrupt Message. Some drivers may implement non-blocking
+ * polling: when non-block is true and the device is not responding return
+ * -EAGAIN instead of waiting for device to respond.
  */
 int usb_int_msg(struct usb_device *dev, unsigned long pipe,
-   void *buffer, int transfer_len, int interval)
+   void *buffer, int transfer_len, int interval, bool nonblock)
 {
-   return submit_int_msg(dev, pipe, buffer, transfer_len, interval);
+   return submit_int_msg(dev, pipe, buffer, transfer_len, interval,
+ nonblock);
 }
 
 /*
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index aafa08f3c004..194cc1ff3a10 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -340,7 +340,7 @@ static inline void usb_kbd_poll_for_event(struct usb_device 
*dev)
 
/* Submit a interrupt transfer request */
if (usb_int_msg(dev, data->intpipe, &data->new[0],
-   data->intpktsize, data->intinterval) >= 0)
+   data->intpktsize, data->intinterval, true) >= 0)
usb_kbd_irq_worker(dev);
 #elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP) || \
   defined(CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE)
@@ -504,7 +504,7 @@ static int usb_kbd_probe_dev(struct usb_device *dev, 
unsigned int ifnum)
   1, 0, data->new, USB_KBD_BOOT_REPORT_SIZE) < 0) {
 #else
if (usb_int_msg(dev, data->intpipe, data->new, data->intpktsize,
-   data->intinterval) < 0) {
+   data->intinterval, false) < 0) {
 #endif
printf("Failed to get keyboard state from device %04x:%04x\n",
   dev->descriptor.idVendor, dev->descriptor.idProduct);
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 995a96baa57d..6e7cdfbca988 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -651,7 +651,7 @@ static int usb_stor_CBI_get_status(struct scsi_cmd *srb, 
struct us_data *us)
 
us->ip_wanted = 1;
usb_int_msg(us->pusb_dev, us->irqpipe,
-   (void *) &us->ip_data, us->irqmaxp, us->irqinterval);
+   (void *) &us->ip_data, us->irqmaxp, us->irqinterval, false);
timeout = 1000;
while (timeout--) {
if (us->ip_wanted == 0)
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index a62a2f8a951d..b4121a49b805 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -1108,7 +1108,8 @@ static int _submit_control_msg(struct dwc2_priv *priv, 
struct usb_device *dev,
 }
 
 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
-   unsigned long pipe, void *buffer, int len, int interval)
+   unsigned long pipe, void *buffer, int len, int interval,
+   bool nonblock)
 {
unsigned long timeout;
int ret;
@@ -1236,9 +1237,10 @@ int submit_bulk_msg(struct usb_device *dev, unsigned 
long pipe, void *buffer,
 }
 
 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-  int len, int interval)
+  int len, int interval, bool nonblock)
 {
-   return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
+   return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
+  nonblock);
 }
 
 /* U-Boot USB control interface */
@@ -1292,13 +1294,13 @@ static int dwc2_submit_bulk_msg(struct udevice *dev, 
struct usb_device *udev,
 
 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
   unsigned long pipe, void *buffer, int length,
-  int interval)
+  int interval, bool nonblock)
 {
struct dwc2_priv *priv = dev_get_priv(dev);
 
debug("%s: dev='%s', udev=%p\

[U-Boot] [PATCH 2/2] watchdog: imx: Use immediate reset bits for expire_now

[Robert Hancock]

The expire_now function was previously setting the watchdog timeout to
minimum and waiting for the watchdog to expire. However, this watchdog
also has bits to trigger immediate reset. Use those instead, like the
Linux imx2_wdt driver does.

Signed-off-by: Robert Hancock 
---
 drivers/watchdog/imx_watchdog.c | 22 +++---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 05bbfe0..c030360 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -15,15 +15,23 @@
 #endif
 #include 
 
-static void imx_watchdog_expire_now(struct watchdog_regs *wdog)
+static void imx_watchdog_expire_now(struct watchdog_regs *wdog, bool ext_reset)
 {
-   clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
+   u16 wcr = WCR_WDE;
+
+   if (ext_reset)
+   wcr |= WCR_SRS; /* do not assert internal reset */
+   else
+   wcr |= WCR_WDA; /* do not assert external reset */
+
+   /* Write 3 times to ensure it works, due to IMX6Q errata ERR004346 */
+   writew(wcr, &wdog->wcr);
+   writew(wcr, &wdog->wcr);
+   writew(wcr, &wdog->wcr);
 
-   writew(0x, &wdog->wsr);
-   writew(0x, &wdog->wsr); /* load minimum 1/2 second timeout */
while (1) {
/*
-* spin for .5 seconds before reset
+* spin before reset
 */
}
 }
@@ -34,7 +42,7 @@ void __attribute__((weak)) reset_cpu(ulong addr)
 {
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 
-   imx_watchdog_expire_now(wdog);
+   imx_watchdog_expire_now(wdog, true);
 }
 #endif
 
@@ -106,7 +114,7 @@ static int imx_wdt_expire_now(struct udevice *dev, ulong 
flags)
 {
struct imx_wdt_priv *priv = dev_get_priv(dev);
 
-   imx_watchdog_expire_now(priv->base);
+   imx_watchdog_expire_now(priv->base, priv->ext_reset);
hang();
 
return 0;
-- 
1.8.3.1

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[U-Boot] [PATCH 1/2] watchdog: imx: Add DT ext-reset handling

[Robert Hancock]

The Linux imx2_wdt driver uses a fsl,ext-reset-output boolean in the
device tree to specify whether the board design should use the external
reset instead of the internal reset. Use this boolean to determine which
mode to use rather than using external reset unconditionally.

For the legacy non-DM mode, the external reset is always used in order
to maintain the previous behavior.

Signed-off-by: Robert Hancock 
---
 drivers/watchdog/imx_watchdog.c | 19 +--
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 53a3e9f..05bbfe0 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -47,9 +47,10 @@ static void imx_watchdog_reset(struct watchdog_regs *wdog)
 #endif /* CONFIG_WATCHDOG_RESET_DISABLE*/
 }
 
-static void imx_watchdog_init(struct watchdog_regs *wdog)
+static void imx_watchdog_init(struct watchdog_regs *wdog, bool ext_reset)
 {
u16 timeout;
+   u16 wcr;
 
/*
 * The timer watchdog can be set between
@@ -61,11 +62,14 @@ static void imx_watchdog_init(struct watchdog_regs *wdog)
 #endif
timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
 #ifdef CONFIG_FSL_LSCH2
-   writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr);
+   wcr = (WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout;
 #else
-   writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
-   WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr);
+   wcr = WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_SRS |
+   WCR_WDA | SET_WCR_WT(timeout);
+   if (ext_reset)
+   wcr |= WCR_WDT;
 #endif /* CONFIG_FSL_LSCH2*/
+   writew(wcr, &wdog->wcr);
imx_watchdog_reset(wdog);
 }
 
@@ -81,11 +85,12 @@ void hw_watchdog_init(void)
 {
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 
-   imx_watchdog_init(wdog);
+   imx_watchdog_init(wdog, true);
 }
 #else
 struct imx_wdt_priv {
void __iomem *base;
+   bool ext_reset;
 };
 
 static int imx_wdt_reset(struct udevice *dev)
@@ -111,7 +116,7 @@ static int imx_wdt_start(struct udevice *dev, u64 timeout, 
ulong flags)
 {
struct imx_wdt_priv *priv = dev_get_priv(dev);
 
-   imx_watchdog_init(priv->base);
+   imx_watchdog_init(priv->base, priv->ext_reset);
 
return 0;
 }
@@ -124,6 +129,8 @@ static int imx_wdt_probe(struct udevice *dev)
if (!priv->base)
return -ENOENT;
 
+   priv->ext_reset = dev_read_bool(dev, "fsl,ext-reset-output");
+
return 0;
 }
 
-- 
1.8.3.1

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[U-Boot] [PATCH 0/2] imx watchdog updates

[Robert Hancock]

Update the iMX watchdog driver functionality to more closely match the
Linux driver by controlling the external reset bits according to the device
tree settings, and using the immediate reset bits when told to expire now.

Robert Hancock (2):
  watchdog: imx: Add DT ext-reset handling
  watchdog: imx: Use immediate reset bits for expire_now

 drivers/watchdog/imx_watchdog.c | 41 -
 1 file changed, 28 insertions(+), 13 deletions(-)

-- 
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Re: [U-Boot] EFI_PXE_BASE_CODE_PROTOCOL

[Peter Jones]

On Tue, Aug 06, 2019 at 09:44:14AM +0100, Leif Lindholm wrote:
> +Peter Jones (sorry Peter)

+ Javier Martinez Canillas

> On Tue, Aug 06, 2019 at 08:34:58AM +0200, Heinrich Schuchardt wrote:
> > iPXE uses the EFI simple network protocol to execute DHCP.
> 
> OK.
> 
> > Can GRUB already do the same when the EFI_PXE_BASE_CODE_PROTOCOL is not
> > present?
> 
> Yes. As of very recently (proper* DHCP support was only merged in
> March 2019, so is included in 2.04 release, prior to that it
> technically performed BOOTP).
> 
> SNP means you do your own networking - it gives you access to the raw
> (usually) Ethernet packets.
> 
> * proper as in "it now conceptually does the correct thing", not as in
>   "I have extensively tested this".
> 
> > What I do not understand about GRUB's grub_net_configure_by_dhcp_ack()
> > is that it silently assumes IPv4 being used without even checking. This
> > contradicts the definition of the PXE base code protocol in the UEFI
> > standard:
> 
> Well, it would not surprise me if this function predates GRUB's UEFI
> support.
> 
> It actually gets even slightly messier when you look at what GRUB does
> when netbooting itself; it starts out using MNP (and hence IP
> addresses assigned by UEFI) to load its modules, switching to SNP once
> it loads efinet.mod.
> 
> > EFI_PXE_BASE_CODE_PACKET DhcpAck is a union:
> > 
> > typedef union {
> >  UINT8 Raw[1472];
> >  EFI_PXE_BASE_CODE_DHCPV4_PACKET   Dhcpv4;
> >  EFI_PXE_BASE_CODE_DHCPV6_PACKET   Dhcpv6;
> > } EFI_PXE_BASE_CODE_PACKET;
> > 
> > Should the check be done in grub_efi_net_config_real()?
> 
> Possibly. I've cc:d Peter since he's the last person I know who took a
> proper look at this.

That's actually what we've got in our current patch set, based on
Michael Chang at SuSE's https work.  Javier Martinez (cc'd) is working
on getting those ready for upstream, but in the mean time, check out the
patches nearby to:

https://github.com/rhboot/grub2/commit/4f977935a9271727bf21889526fdf82f0fc8fed9

-- 
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Re: [U-Boot] [PATCH 06/14] net: ti: icssg-prueth: Add ICSSG ethernet driver

[Andreas Dannenberg]

On Tue, Aug 06, 2019 at 04:08:36PM +0530, Keerthy wrote:
> This is the Ethernet driver for TI SoCs with the
> ICSSG PRU Sub-system running EMAC firmware.
> This driver caters to either of the slices(pru/rtu pair)
> of the icssg subsystem.
> 
> Following are the firmwares needed to run cores:
> 
> am65x-pru0-prueth-fw.elf for pru0 of slice0
> am65x-rtu0-prueth-fw.elf for rtu0 of slice0
> am65x-pru1-prueth-fw.elf for pru1 of slice1
> am65x-rtu1-prueth-fw.elf for rtu1 of slice1
> 
> One and exactly one of the slices is supported
> as the u-boot ethernet supports probing one interface
> at a time.
> 
> Signed-off-by: Keerthy 
> ---
>  drivers/net/ti/Kconfig|   8 +
>  drivers/net/ti/Makefile   |   1 +
>  drivers/net/ti/icssg-prueth.c | 517 ++
>  drivers/net/ti/icssg.h|  31 ++
>  drivers/net/ti/icssg_classifier.c | 397 +++
>  5 files changed, 954 insertions(+)
>  create mode 100644 drivers/net/ti/icssg-prueth.c
>  create mode 100644 drivers/net/ti/icssg.h
>  create mode 100644 drivers/net/ti/icssg_classifier.c
> 
> diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
> index ecf642de10..1b6285709f 100644
> --- a/drivers/net/ti/Kconfig
> +++ b/drivers/net/ti/Kconfig
> @@ -26,3 +26,11 @@ config TI_AM65_CPSW_NUSS
>   help
> This driver supports TI K3 MCU CPSW Nuss Ethernet controller
> in Texas Instruments K3 AM65x SoCs.
> +
> +config TI_AM64_ICSSG_PRUETH
> + bool "TI Gigabit PRU Ethernet driver"
> + depends on ARCH_K3
> + select PHYLIB
> + help
> +   Support Gigabit Ethernet ports over the ICSSG PRU Subsystem
> +   This subsystem is available starting with the AM65 platform.
> diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
> index 8d3808bb4b..b486498909 100644
> --- a/drivers/net/ti/Makefile
> +++ b/drivers/net/ti/Makefile
> @@ -6,3 +6,4 @@ obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o 
> cpsw_mdio.o
>  obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
>  obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o
>  obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o cpsw_mdio.o
> +obj-$(CONFIG_TI_AM64_ICSSG_PRUETH) += icssg-prueth.o cpsw_mdio.o 
> icssg_classifier.o
> diff --git a/drivers/net/ti/icssg-prueth.c b/drivers/net/ti/icssg-prueth.c
> new file mode 100644
> index 00..f8935ee087
> --- /dev/null
> +++ b/drivers/net/ti/icssg-prueth.c
> @@ -0,0 +1,517 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Texas Instruments K3 AM65 PRU Ethernet Driver

If the driver is AM65x specific that should be reflected in the driver
name, like already done for CPSW_NUSS, for consistency and scalability
sake.

> + *
> + * Copyright (C) 2019, Texas Instruments, Incorporated
> + *
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "cpsw_mdio.h"
> +#include "icssg.h"
> +
> +#define ICSS_SLICE0 0
> +#define ICSS_SLICE1 1
> +
> +#ifdef PKTSIZE_ALIGN
> +#define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN
> +#else
> +#define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN)
> +#endif
> +
> +#ifdef PKTBUFSRX
> +#define UDMA_RX_DESC_NUM PKTBUFSRX
> +#else
> +#define UDMA_RX_DESC_NUM 4
> +#endif
> +
> +enum prueth_mac {
> + PRUETH_MAC0 = 0,
> + PRUETH_MAC1,
> + PRUETH_NUM_MACS,
> +};
> +
> +enum prueth_port {
> + PRUETH_PORT_HOST = 0,   /* host side port */
> + PRUETH_PORT_MII0,   /* physical port MII 0 */
> + PRUETH_PORT_MII1,   /* physical port MII 1 */
> +};
> +
> +/* Config region lies in shared RAM */
> +#define ICSS_CONFIG_OFFSET_SLICE00
> +#define ICSS_CONFIG_OFFSET_SLICE10x8000
> +
> +/* Firmware flags */
> +#define ICSS_SET_RUN_FLAG_VLAN_ENABLEBIT(0)  /* switch only 
> */
> +#define ICSS_SET_RUN_FLAG_FLOOD_UNICAST  BIT(1)  /* switch only 
> */
> +#define ICSS_SET_RUN_FLAG_PROMISCBIT(2)  /* MAC only */
> +#define ICSS_SET_RUN_FLAG_MULTICAST_PROMISC  BIT(3)  /* MAC only */
> +
> +/* CTRLMMR_ICSSG_RGMII_CTRL register bits */
> +#define ICSSG_CTRL_RGMII_ID_MODE BIT(24)
> +
> +/**
> + * enum pruss_pru_id - PRU core identifiers
> + */
> +enum pruss_pru_id {
> + PRUSS_PRU0 = 0,
> + PRUSS_PRU1,
> + PRUSS_NUM_PRUS,
> +};
> +
> +struct prueth {
> + struct udevice  *dev;
> + struct regmap   *miig_rt;
> + fdt_addr_t  mdio_base;
> + phys_addr_t pruss_shrdram2;
> + struct mii_dev  *bus;
> + u32 port_id;
> + u32 sram_pa;
> + struct phy_device   *phydev;
> + boolhas_phy;
> + ofnode  phy_node;
> + u32 phy_addr;
> + ofnode  eth_node[PRU

Re: [U-Boot] [PATCH 12/14] arm64: dts: ti: am654-base-board: add ICSSG2 Ethernet support

[Andreas Dannenberg]

On Tue, Aug 06, 2019 at 04:08:42PM +0530, Keerthy wrote:
> ICSSG2 provide dual Gigabit Ethernet support.
> Currently mdio clock is part of this node and also
> the icssg2_rgmii_pins_default pinmux node has the
> mdio pins as there is no davinci mdio driver.
> 
> Currently icssg2 instances are supported.
> Either mii0 or mii1 can be enabled at a time.
> 
> Signed-off-by: Keerthy 
> ---
>  arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 118 +++
>  1 file changed, 118 insertions(+)
> 
> diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi 
> b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
> index 71a7069e74..53399dfff6 100644
> --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
> +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
> @@ -16,6 +16,63 @@
>   serial2 = &main_uart0;
>   ethernet0 = &cpsw_port1;
>   };
> +
> + /* Dual Ethernet application node on PRU-ICSSG2 */
> + pruss2_eth: pruss2_eth {
> + compatible = "ti,am654-icssg-prueth";
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg2_rgmii_pins_default>;
> + sram = <&icssg2_sram>;
> + clocks = <&k3_clks 64 3>;
> + clock-names = "mdio_fck";
> + u-boot,dm-spl;
> +
> + prus = <&pru2_0>, <&rtu2_0>, <&pru2_1>, <&rtu2_1>;
> + firmware-name = "ti-pruss/am65x-pru0-prueth-fw.elf",
> + "ti-pruss/am65x-rtu0-prueth-fw.elf",
> + "ti-pruss/am65x-pru1-prueth-fw.elf",
> + "ti-pruss/am65x-rtu1-prueth-fw.elf";
> + mii-g-rt = <&icssg2_mii_g_rt>;
> + dma-coherent;
> + dmas = <&mcu_udmap &icssg2 0 UDMA_DIR_TX>,  /* egress slice 
> 0 */
> +<&mcu_udmap &icssg2 1 UDMA_DIR_TX>, /* egress slice 0 */
> +<&mcu_udmap &icssg2 2 UDMA_DIR_TX>, /* egress slice 0 */
> +<&mcu_udmap &icssg2 3 UDMA_DIR_TX>, /* mgmnt cmd slice 0 
> */
> +<&mcu_udmap &icssg2 4 UDMA_DIR_TX>, /* egress slice 1 */
> +<&mcu_udmap &icssg2 5 UDMA_DIR_TX>, /* egress slice 1 */
> +<&mcu_udmap &icssg2 6 UDMA_DIR_TX>, /* egress slice 1 */
> +<&mcu_udmap &icssg2 7 UDMA_DIR_TX>, /* mgmnt cmd slice 1 
> */
> +
> +<&mcu_udmap &icssg2 0 UDMA_DIR_RX>, /* ingress slice 0 */
> +<&mcu_udmap &icssg2 1 UDMA_DIR_RX>, /* ingress slice 1 */
> +<&mcu_udmap &icssg2 2 UDMA_DIR_RX>, /* mgmnt rsp slice 0 
> */
> +<&mcu_udmap &icssg2 3 UDMA_DIR_RX>; /* mgmnt rsp slice 1 
> */
> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
> + "rx0", "rx1",
> + "rxmgm0", "rxmgm1";
> +
> + pruss2_emac0: ethernet-mii0 {
> + phy-handle = <&pruss2_eth0_phy>;
> + phy-mode = "rgmii-id";
> + syscon-rgmii-delay = <&scm_conf 0x4120>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> +
> +/*
> + * Commenting out the second mii interface as the framework
> + * supports one interface in a single probe
> + * So either mii1 or mii2 can be used. In case mii1 is needed
> + * uncomment mii1 and comment out mii0
> + pruss2_emac1: ethernet-mii1 {
> + phy-handle = <&pruss2_eth1_phy>;
> + phy-mode = "rgmii-id";
> + syscon-rgmii-delay = <&scm_conf 0x4124>;
> + local-mac-address = [00 00 00 00 00 00];
> + };
> +*/
> + };
>  };
>  
>  &cbass_main{
> @@ -274,6 +331,47 @@
>   u-boot,dm-spl;
>   };
>  
> + icssg2_rgmii_pins_default: icssg2_rgmii_pins_default {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x00ac, PIN_INPUT , 2) /* (AH15) 
> PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */

Why are there spaces behind the pin direction definitions
(PIN_INPUT[space], ...)? I've never seen that before. The pinmix
definitions are supposed to be a 1:1 copy from our AM64x pinmux tool for
consistency sake. Is the pinmux tool broken?

--
Andreas Dannenberg
Texas Instruments Inc

> + AM65X_IOPAD(0x00b0, PIN_INPUT , 2) /* (AC16) 
> PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */
> + AM65X_IOPAD(0x00b4, PIN_INPUT , 2) /* (AD17) 
> PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */
> + AM65X_IOPAD(0x00b8, PIN_INPUT , 2) /* (AH14) 
> PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */
> + AM65X_IOPAD(0x00cc, PIN_OUTPUT , 2) /* (AD15) 
> PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */
> + AM65X_IOPAD(0x00d0, PIN_OUTPUT , 2) /* (AF14) 
> PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */
> + AM65X_IOPAD(0x00d4, PIN_OUTPUT , 2) /*

[U-Boot] [PATCH v3 1/7] net: mvpp2x: fix traffic stuck after PHY start error

[nhed+uboot]

From: Stefan Chulski 

Issue:
- Network stuck if autonegotion fails.

Issue root cause:

- When autonegotiation fails during port open procedure, the packet
  processor configuration does not finish and open procedure exits
  with error.
- However, this doesn't prevent u-boot network framework from
  calling send and receive procedures.
- Using transmit and receive functions of misconfigured packet
  processor will cause traffic to get stuck.

Fix:

- Continue packet processor configuration even if autonegotiation
  fails.  Only error message is triggered in this case.
- Exit transmit and receive functions if there is no PHY link
  indication.
- U-boot network framework now calls open procedure again during next
  transmit initiation.

Signed-off-by: Stefan Chulski 
Reviewed-by: Igal Liberman 
Tested-by: Igal Liberman 
---
 drivers/net/mvpp2.c | 27 ++-
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index bd89725e77..f36c8236b1 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4494,7 +4494,7 @@ static void mvpp2_stop_dev(struct mvpp2_port *port)
gop_port_enable(port, 0);
 }
 
-static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
+static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
 {
struct phy_device *phy_dev;
 
@@ -4504,7 +4504,7 @@ static int mvpp2_phy_connect(struct udevice *dev, struct 
mvpp2_port *port)
port->phy_dev = phy_dev;
if (!phy_dev) {
netdev_err(port->dev, "cannot connect to phy\n");
-   return -ENODEV;
+   return;
}
phy_dev->supported &= PHY_GBIT_FEATURES;
phy_dev->advertising = phy_dev->supported;
@@ -4516,18 +4516,14 @@ static int mvpp2_phy_connect(struct udevice *dev, 
struct mvpp2_port *port)
 
phy_config(phy_dev);
phy_startup(phy_dev);
-   if (!phy_dev->link) {
+   if (!phy_dev->link)
printf("%s: No link\n", phy_dev->dev->name);
-   return -1;
-   }
-
-   port->init = 1;
+   else
+   port->init = 1;
} else {
mvpp2_egress_enable(port);
mvpp2_ingress_enable(port);
}
-
-   return 0;
 }
 
 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
@@ -4567,10 +4563,7 @@ static int mvpp2_open(struct udevice *dev, struct 
mvpp2_port *port)
}
 
if (port->phy_node) {
-   err = mvpp2_phy_connect(dev, port);
-   if (err < 0)
-   return err;
-
+   mvpp2_phy_connect(dev, port);
mvpp2_link_event(port);
} else {
mvpp2_egress_enable(port);
@@ -5175,6 +5168,10 @@ static int mvpp2_recv(struct udevice *dev, int flags, 
uchar **packetp)
struct mvpp2_rx_queue *rxq;
u8 *data;
 
+   if (port->phy_node)
+   if (!port->phy_dev->link)
+   return 0;
+
/* Process RX packets */
rxq = port->rxqs[0];
 
@@ -5240,6 +5237,10 @@ static int mvpp2_send(struct udevice *dev, void *packet, 
int length)
int tx_done;
int timeout;
 
+   if (port->phy_node)
+   if (!port->phy_dev->link)
+   return 0;
+
txq = port->txqs[0];
aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
 
-- 
2.21.0

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[U-Boot] [PATCH v3 0/7] Switch MVPP2 to use new MVMDIO

[nhed+uboot]

From: Nevo Hed 

This patchset includes several commits form Marvell's downstream repo
including Ken Ma's patch to replace the SMI implementation with his
own Marvell MDIO impolementation.  That MVMDIO implementation never
made it to upstream and has since been re-implemented by Alex
Marginean and seems to be in line for inclusion [1].  My last patch in
this set modified Ken's mvpp2 patch to use this new MVMDIO
implementation.  Few other mvpp2 patches picked as they seemed
important yet missing from upstream.

Changes since v2:
 - Removed `Reviewed-on` lines from Marvell commits, they are meaningless
   in upstream U-Boot
 - Commit messages rewording
 - Split out Kconfig (select of MVMDIO & DM_MDIO by MVPP2)
 - reworded heading on dtsi change to match last commit (due to noticing
   no delegates weere listed on patchworks)

Changes since v1:
 - removes a redaundant fixed-link patch

  [1] https://patchwork.ozlabs.org/cover/1136769/

Grzegorz Jaszczyk (1):
  net: mvpp2: mark phy as invalid in case of missing appropriate driver

Ken Ma (1):
  net: mvpp2: Replace SMI implementation with marvell MDIO API

Nevo Hed (4):
  net: mvpp2: no deref null
  arm: dts: armada-cp110-*dtsi: add xmdio nodes
  net: mvpp2: use new MVMDIO driver
  net: mvpp2: MVPP2 now needs MVMDIO

Stefan Chulski (1):
  net: mvpp2x: fix traffic stuck after PHY start error

 arch/arm/dts/armada-cp110-master.dtsi |   9 +
 arch/arm/dts/armada-cp110-slave.dtsi  |   9 +
 drivers/net/Kconfig   |   2 +
 drivers/net/mvpp2.c   | 240 ++
 4 files changed, 72 insertions(+), 188 deletions(-)

--
2.21.0

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[U-Boot] [PATCH v3 4/7] net: mvpp2: no deref null

[nhed+uboot]

From: Nevo Hed 

phy_dev ptr is set from return of phy_connect() and is used before
test to see if NULL.  Obviously since the test already sxists someone
made the determination that this NULL is possible.

Signed-off-by: Nevo Hed 
---
 drivers/net/mvpp2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index fae7090121..5f908113f2 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4494,7 +4494,8 @@ static void mvpp2_phy_connect(struct udevice *dev, struct 
mvpp2_port *port)
 * an option because it is required for the phy_fw_down
 * procedure.
 */
-   if (phy_dev->drv->uid == 0x) {/* Generic phy */
+   if (phy_dev &&
+   phy_dev->drv->uid == 0x) {/* Generic phy */
netdev_warn(port->dev,
"Marking phy as invalid, link will not be 
checked\n");
/* set phy_addr to invalid value */
-- 
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[U-Boot] [PATCH v3 5/7] arm: dts: armada-cp110-*dtsi: add xmdio nodes

[nhed+uboot]

From: Nevo Hed 

Based on upstream-linux
See https://github.com/torvalds/linux/commit/f66b2aff.

However made the XSMI register window 0x16 (22) bytes per my reading
of the functional spec.  Similar commits in Marvels own repo bump it
to 0x200 (512) bytes but I did not see the reasoning for that.

https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/4d932b4.

Also added device-name attributes to prevent ambiguity in the `mdio`
command.

Signed-off-by: Nevo Hed 
---
 arch/arm/dts/armada-cp110-master.dtsi | 9 +
 arch/arm/dts/armada-cp110-slave.dtsi  | 9 +
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/dts/armada-cp110-master.dtsi 
b/arch/arm/dts/armada-cp110-master.dtsi
index e4c17e9f4b..cd5c974482 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -99,6 +99,15 @@
device-name = "cpm-mdio";
};
 
+   cpm_xmdio: mdio@12a600 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "marvell,xmdio";
+   reg = <0x12a600 0x16>;
+   status = "disabled";
+   device-name = "cpm-xmdio";
+   };
+
cpm_syscon0: system-controller@44 {
compatible = "marvell,cp110-system-controller0",
 "syscon";
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi 
b/arch/arm/dts/armada-cp110-slave.dtsi
index 2fbd7b5514..b426a4eb69 100644
--- a/arch/arm/dts/armada-cp110-slave.dtsi
+++ b/arch/arm/dts/armada-cp110-slave.dtsi
@@ -99,6 +99,15 @@
device-name = "cps-mdio";
};
 
+   cps_xmdio: mdio@12a600 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "marvell,xmdio";
+   reg = <0x12a600 0x16>;
+   status = "disabled";
+   device-name = "cps-xmdio";
+   };
+
cps_syscon0: system-controller@44 {
compatible = "marvell,cp110-system-controller0",
 "syscon";
-- 
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[U-Boot] [PATCH v3 6/7] net: mvpp2: use new MVMDIO driver

[nhed+uboot]

From: Nevo Hed 

An earlier commit in this changeset is taken from Marvells repos but
was based on an MVMDIO implementation that never made it into U-Boot.
With this patch the mvpp2 driver switches to use the new MVMDIO driver
that is based on a more universal mdio-uclass implementation.

Signed-off-by: Nevo Hed 
---
 drivers/net/mvpp2.c | 45 ++---
 1 file changed, 10 insertions(+), 35 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 5f908113f2..de1b8fce84 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -32,7 +32,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -936,7 +936,6 @@ struct mvpp2_port {
 
/* Per-port registers' base address */
void __iomem *base;
-   void __iomem *mdio_base;
 
struct mvpp2_rx_queue **rxqs;
struct mvpp2_tx_queue **txqs;
@@ -958,7 +957,7 @@ struct mvpp2_port {
struct phy_device *phy_dev;
phy_interface_t phy_interface;
int phyaddr;
-   struct mii_dev *bus;
+   struct udevice *mdio_dev;
 #ifdef CONFIG_DM_GPIO
struct gpio_desc phy_reset_gpio;
struct gpio_desc phy_tx_disable_gpio;
@@ -4482,8 +4481,8 @@ static void mvpp2_phy_connect(struct udevice *dev, struct 
mvpp2_port *port)
struct phy_device *phy_dev;
 
if (!port->init || port->link == 0) {
-   phy_dev = phy_connect(port->bus, port->phyaddr, dev,
- port->phy_interface);
+   phy_dev = dm_mdio_phy_connect(port->mdio_dev, port->phyaddr,
+ dev, port->phy_interface);
 
/* If the phy doesn't match with any existing u-boot drivers the
 * phy framework will connect it to generic one which
@@ -4708,24 +4707,18 @@ static int phy_info_parse(struct udevice *dev, struct 
mvpp2_port *port)
int phy_mode = -1;
int ret;
 
-   /* Default mdio_base from the same eth base */
-   if (port->priv->hw_version == MVPP21)
-   port->mdio_base = port->priv->lms_base + MVPP21_SMI;
-   else
-   port->mdio_base = port->priv->iface_base + MVPP22_SMI;
-
phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
 
if (phy_node > 0) {
-   ofnode phy_ofnode;
-   fdt_addr_t phy_base;
-
+   int parent;
phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
if (phyaddr < 0) {
dev_err(&pdev->dev, "could not find phy address\n");
return -1;
}
-   ret = mdio_mii_bus_get_from_phy(phy_node, &port->bus);
+   parent = fdt_parent_offset(gd->fdt_blob, phy_node);
+   ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
+&port->mdio_dev);
if (ret)
return ret;
} else {
@@ -5044,7 +5037,7 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
return 0;
 }
 
-int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
+static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 {
struct mvpp2_port *port = dev_get_priv(dev);
struct mvpp2_rx_desc *rx_desc;
@@ -5309,31 +5302,13 @@ static int mvpp2_probe(struct udevice *dev)
 {
struct mvpp2_port *port = dev_get_priv(dev);
struct mvpp2 *priv = dev_get_priv(dev->parent);
-   struct mii_dev *bus;
int err;
 
/* Only call the probe function for the parent once */
if (!priv->probe_done)
err = mvpp2_base_probe(dev->parent);
 
-   port->priv = dev_get_priv(dev->parent);
-
-   /* Create and register the MDIO bus driver */
-   bus = mdio_alloc();
-   if (!bus) {
-   printf("Failed to allocate MDIO bus\n");
-   return -ENOMEM;
-   }
-
-   bus->read = mpp2_mdio_read;
-   bus->write = mpp2_mdio_write;
-   snprintf(bus->name, sizeof(bus->name), dev->name);
-   bus->priv = (void *)port;
-   port->bus = bus;
-
-   err = mdio_register(bus);
-   if (err)
-   return err;
+   port->priv = priv;
 
err = phy_info_parse(dev, port);
if (err)
-- 
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[U-Boot] [PATCH v3 3/7] net: mvpp2: mark phy as invalid in case of missing appropriate driver

[nhed+uboot]

From: Grzegorz Jaszczyk 

If the phy doesn't match with any existing u-boot drivers, the phy
framework will connect it to the generic one which uid ==
0x. In this case, act as if the phy wouldn't be declared in
dts. Otherwise, in case of 3310 (for which the driver doesn't exist)
the link is marked as always down. Removing phy entry from dts in case
of 3310 is not a good option because it is required for the
phy_fw_down procedure.

This patch fixes the issue with the link always down on MCBIN board.

Signed-off-by: Grzegorz Jaszczyk 
Reviewed-by: Igal Liberman 
Tested-by: Igal Liberman 
---
 drivers/net/mvpp2.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index b6dfed5c54..fae7090121 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4484,6 +4484,27 @@ static void mvpp2_phy_connect(struct udevice *dev, 
struct mvpp2_port *port)
if (!port->init || port->link == 0) {
phy_dev = phy_connect(port->bus, port->phyaddr, dev,
  port->phy_interface);
+
+   /* If the phy doesn't match with any existing u-boot drivers the
+* phy framework will connect it to generic one which
+* uid == 0x. In this case act as if the phy wouldn't be
+* declared in dts. Otherwise in case of 3310 (for which the
+* driver doesn't exist) the link will not be correctly
+* detected. Removing phy entry from dts in case of 3310 is not
+* an option because it is required for the phy_fw_down
+* procedure.
+*/
+   if (phy_dev->drv->uid == 0x) {/* Generic phy */
+   netdev_warn(port->dev,
+   "Marking phy as invalid, link will not be 
checked\n");
+   /* set phy_addr to invalid value */
+   port->phyaddr = PHY_MAX_ADDR;
+   mvpp2_egress_enable(port);
+   mvpp2_ingress_enable(port);
+
+   return;
+   }
+
port->phy_dev = phy_dev;
if (!phy_dev) {
netdev_err(port->dev, "cannot connect to phy\n");
-- 
2.21.0

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[U-Boot] [PATCH v3 2/7] net: mvpp2: Replace SMI implementation with marvell MDIO API

[nhed+uboot]

From: Ken Ma 

The availability of the marvell MDIO driver enables us to eliminate
the SMI function implementation within the mvpp2 driver.
This replacement also fixes 2 old issues:
1. Each pp2 port device now has its own mdio bus field member since
   some pp2 ports may use SMI mdio bus while some other pp2 ports may
   use XSMI mdio bus, but the old mvpp2_base device has a shared bus
   for all its pp2 ports; this patch moves mdio bus field member from
   struct mvpp2 to struct mvpp2_port;
2. Old code uses mvpp2_base device name as mdio bus name; but for
   Armada80x0, cp0 ethernet device and cp1 ethernet device have the
   same device name - "ethernet@0"; and because mdio_register() checks
   unique name, then the second probed mvpp2_base device fails to
   register mdio bus; since new marvell MDIO driver has resolved the
   unique name issue - different mdio names can be set in fdt and if a
   mdio name is not set, the default mdio name is generated from the
   mdio bus base address, so this issue is fixed by this replacement.

Signed-off-by: Ken Ma 
Reviewed-by: Igal Liberman 
Tested-by: Igal Liberman 
Signed-off-by: Nevo Hed 
---
 drivers/net/mvpp2.c | 158 
 1 file changed, 12 insertions(+), 146 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index f36c8236b1..b6dfed5c54 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -32,6 +32,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -62,8 +63,6 @@ do {  
\
 #define MTU1500
 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
 
-#define MVPP2_SMI_TIMEOUT  1
-
 /* RX Fifo Registers */
 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port)  (0x00 + 4 * (port))
 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port)  (0x20 + 4 * (port))
@@ -490,23 +489,8 @@ do {   
\
 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
(((index) < (q)->last_desc) ? ((index) + 1) : 0)
 
-/* SMI: 0xc0054 -> offset 0x54 to lms_base */
-#define MVPP21_SMI 0x0054
 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
 #define MVPP22_SMI 0x1200
-#define MVPP2_PHY_REG_MASK 0x1f
-/* SMI register fields */
-#define MVPP2_SMI_DATA_OFFS0   /* Data */
-#define MVPP2_SMI_DATA_MASK(0x << 
MVPP2_SMI_DATA_OFFS)
-#define MVPP2_SMI_DEV_ADDR_OFFS16  /* PHY device address */
-#define MVPP2_SMI_REG_ADDR_OFFS21  /* PHY device reg addr*/
-#define MVPP2_SMI_OPCODE_OFFS  26  /* Write/Read opcode */
-#define MVPP2_SMI_OPCODE_READ  (1 << MVPP2_SMI_OPCODE_OFFS)
-#define MVPP2_SMI_READ_VALID   (1 << 27)   /* Read Valid */
-#define MVPP2_SMI_BUSY (1 << 28)   /* Busy */
-
-#define MVPP2_PHY_ADDR_MASK0x1f
-#define MVPP2_PHY_REG_MASK 0x1f
 
 /* Additional PPv2.2 offsets */
 #define MVPP22_MPCS0x007000
@@ -973,7 +957,6 @@ struct mvpp2_port {
 
struct phy_device *phy_dev;
phy_interface_t phy_interface;
-   int phy_node;
int phyaddr;
struct mii_dev *bus;
 #ifdef CONFIG_DM_GPIO
@@ -4562,7 +4545,7 @@ static int mvpp2_open(struct udevice *dev, struct 
mvpp2_port *port)
return err;
}
 
-   if (port->phy_node) {
+   if (port->phyaddr < PHY_MAX_ADDR) {
mvpp2_phy_connect(dev, port);
mvpp2_link_event(port);
} else {
@@ -4701,6 +4684,7 @@ static int phy_info_parse(struct udevice *dev, struct 
mvpp2_port *port)
u32 id;
u32 phyaddr = 0;
int phy_mode = -1;
+   int ret;
 
/* Default mdio_base from the same eth base */
if (port->priv->hw_version == MVPP21)
@@ -4719,17 +4703,12 @@ static int phy_info_parse(struct udevice *dev, struct 
mvpp2_port *port)
dev_err(&pdev->dev, "could not find phy address\n");
return -1;
}
-
-   phy_ofnode = ofnode_get_parent(offset_to_ofnode(phy_node));
-   phy_base = ofnode_get_addr(phy_ofnode);
-   port->mdio_base = (void *)phy_base;
-
-   if (port->mdio_base < 0) {
-   dev_err(&pdev->dev, "could not find mdio base 
address\n");
-   return -1;
-   }
+   ret = mdio_mii_bus_get_from_phy(phy_node, &port->bus);
+   if (ret)
+   return ret;
} else {
-   phy_node = 0;
+   /* phy_addr is set to invalid value */
+   phyaddr = PHY_MAX_ADDR;
}
 
phy_mode_str = fdt_getprop(gd->

[U-Boot] [PATCH v3 7/7] net: mvpp2: MVPP2 now needs MVMDIO

[nhed+uboot]

From: Nevo Hed 

Changes to mvpp2.c require the MVMDIO module which in turn uses
DM_MDIO.

Signed-off-by: Nevo Hed 
---
 drivers/net/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 5fd31b03cf..81f39d0928 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -297,6 +297,8 @@ config MVPP2
bool "Marvell Armada 375/7K/8K network interface support"
depends on ARMADA_375 || ARMADA_8K
select PHYLIB
+   select MVMDIO
+   select DM_MDIO
help
  This driver supports the network interface units in the
  Marvell ARMADA 375, 7K and 8K SoCs.
-- 
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Re: [U-Boot] [PATCH 04/14] soc: ti: pruss: add a misc driver for PRUSS in TI SoCs

[Andreas Dannenberg]

On Tue, Aug 06, 2019 at 04:08:34PM +0530, Keerthy wrote:
> The Programmable Real-Time Unit - Industrial Communication
> Subsystem (PRU-ICSS) is present of various TI SoCs such as
> AM335x or AM437x or the AM654x family. Each SoC can have
> one or more PRUSS instances that may or may not be identical.
> 
> The PRUSS consists of dual 32-bit RISC cores called the
> Programmable Real-Time Units (PRUs), some shared, data and
> instruction memories, some internal peripheral modules, and
> an interrupt controller. The programmable nature of the PRUs
> provide flexibility to implement custom peripheral interfaces,
> fast real-time responses, or specialized data handling.
> 
> Add support for pruss driver. Currently am654x family
> is supported.
> 
> Signed-off-by: Keerthy 
> ---
>  drivers/soc/ti/Kconfig  |  13 
>  drivers/soc/ti/Makefile |   1 +
>  drivers/soc/ti/pruss.c  | 128 
>  include/ti-pruss.h  |  12 
>  4 files changed, 154 insertions(+)
>  create mode 100644 drivers/soc/ti/pruss.c
>  create mode 100644 include/ti-pruss.h
> 
> diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig
> index e4f8834448..179b73a541 100644
> --- a/drivers/soc/ti/Kconfig
> +++ b/drivers/soc/ti/Kconfig
> @@ -23,4 +23,17 @@ config TI_KEYSTONE_SERDES
>SerDes driver for Keystone SoC used for ethernet support on TI
>K2 platforms.
>  
> +config TI_PRUSS
> + bool "Support for TI's K3 based Pruss driver"
> + depends on DM
> + depends on ARCH_K3
> + depends on OF_CONTROL
> + depends on SYSCON
> + help
> +

Usually there is no blank line below 'help', the next line should follow
immediately to better indicate those things belong together.

> +   Support for TI PRU-ICSSG subsystem.
> +
> +  Currently supported on AM65xx SoCs Say Y here to support the

First sentence is missing the period ('.')

> +   Programmable Realtime Unit (PRU).
> +
>  endif # SOC_TI
> diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile
> index 4ec04ee125..34f80aad29 100644
> --- a/drivers/soc/ti/Makefile
> +++ b/drivers/soc/ti/Makefile
> @@ -2,3 +2,4 @@
>  
>  obj-$(CONFIG_TI_K3_NAVSS_RINGACC)+= k3-navss-ringacc.o
>  obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o
> +obj-$(CONFIG_TI_PRUSS)   += pruss.o
> diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c
> new file mode 100644
> index 00..03ddaaa539
> --- /dev/null
> +++ b/drivers/soc/ti/pruss.c
> @@ -0,0 +1,128 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PRU-ICSS platform driver for various TI SoCs
> + *
> + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
> + *   Keerthy 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define PRUSS_CFG_IEPCLK 0x30
> +#define ICSSG_CFG_CORE_SYNC  0x3c
> +
> +/* PRUSS_IEPCLK register bits */
> +#define PRUSS_IEPCLK_IEP_OCP_CLK_EN  BIT(0)
> +
> +/* ICSSG CORE_SYNC register bits */
> +#define ICSSG_CORE_VBUSP_SYNC_EN BIT(0)
> +
> +/**
> + * enum pruss_mem - PRUSS memory range identifiers
> + */
> +enum pruss_mem {
> + PRUSS_MEM_DRAM0 = 0,
> + PRUSS_MEM_DRAM1,
> + PRUSS_MEM_SHRD_RAM2,
> + PRUSS_MEM_MAX,
> +};
> +
> +int pruss_request_shrmem_region(struct udevice *dev, phys_addr_t *loc)
> +{
> + struct pruss *priv;
> +
> + priv = dev_get_priv(dev);
> + if (!priv || !priv->pruss_shrdram2)
> + return -EINVAL;
> +
> + *loc = priv->pruss_shrdram2;
> +
> + return 0;
> +}
> +
> +static int pruss_bind(struct udevice *dev)
> +{
> + return dm_scan_fdt_dev(dev);
> +}
> +
> +/**
> + * pruss_probe() - Basic probe
> + * @dev: corresponding k3 device
> + *
> + * Return: 0 if all goes good, else appropriate error message.
> + */
> +static int pruss_probe(struct udevice *dev)
> +{
> + struct pruss *priv;
> + int ret, idx;
> + ofnode sub_node, node, memories;
> + struct regmap *regmap_cfg;
> + struct udevice *syscon;
> +
> + priv = dev_get_priv(dev);
> + node = dev_ofnode(dev);
> + sub_node = ofnode_find_subnode(node, "cfg");
> + memories = ofnode_find_subnode(node, "memories");
> +
> + idx = ofnode_stringlist_search(memories, "reg-names", "dram0");
> + priv->pruss_dram0 = ofnode_get_addr_size_index(memories, idx,
> +(u64 
> *)&priv->pruss_dram0sz);
> + idx = ofnode_stringlist_search(memories, "reg-names", "dram1");
> + priv->pruss_dram1 = ofnode_get_addr_size_index(memories, idx,
> +(u64 
> *)&priv->pruss_dram1sz);
> + idx = ofnode_stringlist_search(memories, "reg-names", "shrdram2");
> + priv->pruss_shrdram2 = ofnode_get_addr_size_index(memories, idx,
> +   (u64 
> *)&priv->pruss_shrdram2sz);
> +
> + ret

Re: [U-Boot] [PATCH 11/14] arm: dts: k3-am65-main: Add pruss nodes for ICSSG2

[Suman Anna]

Hi Keerthy,

On 8/6/19 5:38 AM, Keerthy wrote:
> Add pruss nodes. Add nodes as in the 4.19 integration kernel.
> 
> Signed-off-by: Keerthy 
> ---
>  arch/arm/dts/k3-am65-main.dtsi | 183 +
>  1 file changed, 183 insertions(+)
> 
> diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
> index 0cd3e5e606..d357966dac 100644
> --- a/arch/arm/dts/k3-am65-main.dtsi
> +++ b/arch/arm/dts/k3-am65-main.dtsi
> @@ -5,6 +5,8 @@
>   * Copyright (C) 2016-2018 Texas Instruments Incorporated - 
> http://www.ti.com/
>   */
>  
> +#include 
> +
>  &cbass_main {
>   msmc_ram: sram@7000 {
>   compatible = "mmio-sram";
> @@ -172,4 +174,185 @@
>   clocks = <&k3_clks 113 1>;
>   power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
>   };
> +
> + icssg_soc_bus2: pruss-soc-bus@b226004 {
> + compatible = "ti,am654-icssg-soc-bus", "simple-bus";
> + reg = <0x00 0x0b226004 0x00 0x4>;
> + power-domains = <&k3_pds 64>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0b20 0x00 0x0b20 0x10>;
> + dma-ranges;

So, the SoC bus nodes are rejected on the kernel-side, and the overall
PRUSS bindings are still a work in progress.

> +
> + icssg2: icssg@b20 {
> + compatible = "ti,am654-icssg";
> + reg = <0xb20 0x8>;
> + interrupts = ,
> +  ,
> +  ,
> +  ,
> +  ,
> +  ,
> +  ,
> +  ;
> + interrupt-names = "host2", "host3", "host4",
> +   "host5", "host6", "host7",
> +   "host8", "host9";

These are going away as well, and being moved into the INTC node.

> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + dma-ranges;
> + ti,psil-base = <0x4300>;/* ICSSG2 PSIL thread 
> start */
> +
> + ti,psil-config0 {
> + linux,udma-mode = ;
> + statictr-type = ;
> + ti,needs-epib;
> + ti,psd-size = <16>;
> + };
> +
> + ti,psil-config1 {
> + linux,udma-mode = ;
> + statictr-type = ;
> + ti,needs-epib;
> + ti,psd-size = <16>;
> + };
> +
> + ti,psil-config2 {
> + linux,udma-mode = ;
> + statictr-type = ;
> + ti,needs-epib;
> + ti,psd-size = <16>;
> + };
> +
> + ti,psil-config3 {
> + linux,udma-mode = ;
> + statictr-type = ;
> + ti,needs-epib;
> + ti,psd-size = <16>;
> + };
> +
> + ti,psil-config4 {
> + linux,udma-mode = ;
> + statictr-type = ;
> + ti,needs-epib;
> + ti,psd-size = <16>;
> + };
> +
> + ti,psil-config5 {
> + linux,udma-mode = ;
> + statictr-type = ;
> + ti,needs-epib;
> + ti,psd-size = <16>;
> + };
> +
> + ti,psil-config6 {
> + linux,udma-mode = ;
> + statictr-type = ;
> + ti,needs-epib;
> + ti,psd-size = <16>;
> + };
> +
> + ti,psil-config7 {
> + linux,udma-mode = ;
> + statictr-type = ;
> + ti,needs-epib;
> + ti,psd-size = <16>;
> + };

These are still up for debate. So, I think this whole series is a bit
premature.

regards
Suman

> +
> + icssg2_mem: memories@b20 {
> + reg = <0xb20 0x2000>,
> +   <0xb202000 0x2000>,
> +   <0xb21 0x1>;
> + reg-names = "dram0", "dram1",
> + "shrdram2";
> + };
> +
> + ics

Re: [U-Boot] [PATCH] board: amlogic: document alternative libretech-cc installation methods

[Neil Armstrong]

Hi Daniel,

On 06/08/2019 10:10, Daniel Drake wrote:
> As already documented in this README, several binaries must be
> glued together in order to boot the device.
> 
> Extend the documentation to cover the prebuilt binaries
> (saving you the hassle of installing ancient cross-compilers),
> and also mention the open source replacements for the encryption
> tool (which is especially useful if you want to avoid requiring
> 32-bit x86 binaries in your build system).

Looks fine, could also be added to other board's README files.
Waiting a few more days until we have more comments on it by Andreas
and others.

Thanks,

Neil

> 
> Signed-off-by: Daniel Drake 
> Cc: Neil Armstrong 
> ---
>  board/amlogic/p212/README.libretech-cc | 41 +++---
>  1 file changed, 37 insertions(+), 4 deletions(-)
> 
> diff --git a/board/amlogic/p212/README.libretech-cc 
> b/board/amlogic/p212/README.libretech-cc
> index d007f58764..6af7de3cfa 100644
> --- a/board/amlogic/p212/README.libretech-cc
> +++ b/board/amlogic/p212/README.libretech-cc
> @@ -38,9 +38,28 @@ U-Boot compilation
>  Image creation
>  ==
>  
> -Amlogic doesn't provide sources for the firmware and for tools needed
> -to create the bootloader image, so it is necessary to obtain them from
> -the git tree published by the board vendor:
> +To boot the system, u-boot must be combined with several earlier stage
> +bootloaders:
> +
> +* bl2.bin: vendor-provided binary blob
> +* bl21.bin: built from vendor u-boot source
> +* bl30.bin: vendor-provided binary blob
> +* bl301.bin: built from vendor u-boot source
> +* bl31.bin: vendor-provided binary blob
> +* acs.bin: built from vendor u-boot source
> +
> +These binaries and the tools required below have been collected and prebuilt
> +for convenience at 
> +
> +Download and extract the libretech-cc release from there, and set FIPDIR to
> +point to the `fip` subdirectory.
> +
> + > export FIPDIR=/path/to/extracted/fip
> +
> +Alternatively, you can obtain the original vendor u-boot tree which
> +contains the required blobs and sources, and build yourself.
> +Note that old compilers are required for this to build. The compilers here
> +are suggested by Amlogic, and they are 32-bit x86 binaries.
>  
>   > wget 
> https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
>   > wget 
> https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> @@ -53,7 +72,10 @@ the git tree published by the board vendor:
>   > make
>   > export FIPDIR=$PWD/fip
>  
> -Go back to mainline U-Boot source tree then :
> +Once you have the binaries available (either through the prebuilt download,
> +or having built the vendor u-boot yourself), you can then proceed to glue
> +everything together. Go back to mainline U-Boot source tree then :
> +
>   > mkdir fip
>  
>   > cp $FIPDIR/gxl/bl2.bin fip/
> @@ -100,3 +122,14 @@ and then write the image to SD with:
>   > DEV=/dev/your_sd_device
>   > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 
> seek=1
>   > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
> +
> +Note that Amlogic provides aml_encrypt_gxl as a 32-bit x86 binary with no
> +source code. Should you prefer to avoid that, there are open source reverse
> +engineered versions available:
> +
> +1. gxlimg , which comes with a handy
> +   Makefile that automates the whole process.
> +2. meson-tools 
> +
> +However, these community-developed alternatives are not endorsed by or
> +supported by Amlogic.
> 

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[U-Boot] [PATCH v2 6/7] ARM: meson: Add support for fastboot_set_reboot_flag()

[Neil Armstrong]

Add support for fastboot_set_reboot_flag() by storing the reboot
flag in the common code to be used by the custom PSCI reboot handler.

Signed-off-by: Neil Armstrong 
---
 arch/arm/mach-meson/board-common.c | 33 ++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/mach-meson/board-common.c 
b/arch/arm/mach-meson/board-common.c
index 18383f774e..9b3fb4707d 100644
--- a/arch/arm/mach-meson/board-common.c
+++ b/arch/arm/mach-meson/board-common.c
@@ -14,6 +14,11 @@
 #include 
 #include 
 
+#if CONFIG_IS_ENABLED(FASTBOOT)
+#include 
+#include 
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 __weak int board_init(void)
@@ -142,7 +147,35 @@ int board_late_init(void)
return meson_board_late_init();
 }
 
+#if CONFIG_IS_ENABLED(FASTBOOT)
+static unsigned int reboot_reason = REBOOT_REASON_NORMAL;
+
+int fastboot_set_reboot_flag()
+{
+   reboot_reason = REBOOT_REASON_BOOTLOADER;
+
+   printf("Using reboot reason: 0x%x\n", reboot_reason);
+
+   return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+   struct pt_regs regs;
+
+   regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_RESET;
+   regs.regs[1] = reboot_reason;
+
+   printf("Rebooting with reason: 0x%lx\n", regs.regs[1]);
+
+   smc_call(®s);
+
+   while (1)
+   ;
+}
+#else
 void reset_cpu(ulong addr)
 {
psci_system_reset();
 }
+#endif
-- 
2.22.0

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[U-Boot] [PATCH v2 3/7] arm: meson: add sm cmd to retrieve SoC serial

[Neil Armstrong]

The Secure Monitor offers multiple services, like returning the
SoC unique serial number, already used to generate an unique MAC
address.

This adds a new, Amlogic specific, "sm" cmd with a "serial" subcommand
to write the SoC unique serial to memory.

This "cm" command will be extended in further patches.

Signed-off-by: Neil Armstrong 
---
 arch/arm/mach-meson/sm.c | 48 
 1 file changed, 48 insertions(+)

diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index 05b7f0bdf2..99fa17d9a8 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -77,3 +77,51 @@ int meson_sm_get_serial(void *buffer, size_t size)
 
return 0;
 }
+
+static int do_sm_serial(cmd_tbl_t *cmdtp, int flag, int argc,
+   char *const argv[])
+{
+   ulong address;
+   int ret;
+
+   if (argc < 2)
+   return CMD_RET_USAGE;
+
+   address = simple_strtoul(argv[1], NULL, 0);
+
+   ret = meson_sm_get_serial((void *)address, SM_CHIP_ID_SIZE);
+   if (ret)
+   return CMD_RET_FAILURE;
+
+   return CMD_RET_SUCCESS;
+}
+
+static cmd_tbl_t cmd_sm_sub[] = {
+   U_BOOT_CMD_MKENT(serial, 2, 1, do_sm_serial, "", ""),
+};
+
+static int do_sm(cmd_tbl_t *cmdtp, int flag, int argc,
+char *const argv[])
+{
+   cmd_tbl_t *c;
+
+   if (argc < 2)
+   return CMD_RET_USAGE;
+
+   /* Strip off leading 'sm' command argument */
+   argc--;
+   argv++;
+
+   c = find_cmd_tbl(argv[0], &cmd_sm_sub[0], ARRAY_SIZE(cmd_sm_sub));
+
+   if (c)
+   return c->cmd(cmdtp, flag, argc, argv);
+   else
+   return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+   sm, 5, 0, do_sm,
+   "Secure Monitor Control",
+   "serial  - read chip unique id to memory address"
+);
-- 
2.22.0

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[U-Boot] [PATCH v2 5/7] boards: meson: add g12a sei510

[Neil Armstrong]

From: Jerome Brunet 

The SEI510 board is based on the Amlogic S905X2 SoC
from the Amlogic G12A SoC family.

The board has the following specifications :
- Amlogic S905X2 ARM Cortex-A53 quad-core SoC
- XGB DDR4 SDRAM
- 10/100 Ethernet (Internal PHY)
- 1 x USB 3.0 Host
- eMMC
- SDcard
- Infrared receiver
- SDIO WiFi Module

The board default behaviour is for booting Android and triggers
fastboot on recovery or reboot mode.

USB vendor ID (used by fastboot) is 0x18d1 (Google) for
default udev rules for existing android users work out of the box.

Signed-off-by: Kevin Hilman 
Signed-off-by: Jerome Brunet 
Signed-off-by: Guillaume La Roque 
Signed-off-by: Neil Armstrong 
---
 board/amlogic/sei510/MAINTAINERS |   5 ++
 board/amlogic/sei510/Makefile|   6 ++
 board/amlogic/sei510/README  | 123 +++
 board/amlogic/sei510/sei510.c|  26 ++
 configs/sei510_defconfig |  74 +
 include/configs/sei510.h | 137 +++
 6 files changed, 371 insertions(+)
 create mode 100644 board/amlogic/sei510/MAINTAINERS
 create mode 100644 board/amlogic/sei510/Makefile
 create mode 100644 board/amlogic/sei510/README
 create mode 100644 board/amlogic/sei510/sei510.c
 create mode 100644 configs/sei510_defconfig
 create mode 100644 include/configs/sei510.h

diff --git a/board/amlogic/sei510/MAINTAINERS b/board/amlogic/sei510/MAINTAINERS
new file mode 100644
index 00..792ae22176
--- /dev/null
+++ b/board/amlogic/sei510/MAINTAINERS
@@ -0,0 +1,5 @@
+U200
+M: Neil Armstrong 
+S: Maintained
+F: board/amlogic/sei510/
+F: configs/sei510_defconfig
diff --git a/board/amlogic/sei510/Makefile b/board/amlogic/sei510/Makefile
new file mode 100644
index 00..03399a3849
--- /dev/null
+++ b/board/amlogic/sei510/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 BayLibre, SAS
+# Author: Neil Armstrong 
+
+obj-y  := sei510.o
diff --git a/board/amlogic/sei510/README b/board/amlogic/sei510/README
new file mode 100644
index 00..216ff06093
--- /dev/null
+++ b/board/amlogic/sei510/README
@@ -0,0 +1,123 @@
+U-Boot for Amlogic SEI510
+===
+
+SEI510 is a custemer board manufactured by SEI Robotics with the following
+specifications:
+
+ - Amlogic S905X2 ARM Cortex-A53 quad-core SoC
+ - 2GB DDR4 SDRAM
+ - 10/100 Ethernet (Internal PHY)
+ - 1 x USB 3.0 Host
+ - eMMC
+ - SDcard
+ - Infrared receiver
+ - SDIO WiFi Module
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - Ethernet
+ - Regulators
+ - Clock controller
+
+u-boot compilation
+==
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make sei510_defconfig
+ > make
+
+Image creation
+==
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget 
https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget 
https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export 
PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b 
buildroot-openlinux-20180418 amlogic-u-boot
+ > cd amlogic-u-boot
+ > make g12a_u200_v1_defconfig
+ > make
+ > export UBOOTDIR=$PWD
+
+Download the latest Amlogic Buildroot package, and extract it :
+ > wget 
http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz
+ > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz 
buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader
+ > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
+ > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
+
+Go back to mainline U-Boot source tree then :
+ > mkdir fip
+
+ > wget 
https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh
 -O fip/blx_fix.sh
+ > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/
+ > cp $FIPDIR/g12a/ddr3_1d.fw fip/
+ > cp $FIPDIR/g12a/ddr4_1d.fw fip/
+ > cp $FIPDIR/g12a/ddr4_2d.fw fip/
+ > cp $FIPDIR/g12a/diag_lpddr4.fw fip/
+ > cp $FIPDIR/g12a/lpddr4_1d.fw fip/
+ > cp $FIPDIR/g12a/lpddr4_2d.fw fip/
+ > cp $FIPDIR/g12a/piei.fw fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > sh fip/blx_fix.sh \
+   fip/bl30.bin \
+   fip/zero_tmp \
+   fip/bl30

[U-Boot] [PATCH v2 7/7] configs: sei510: disable PSCI_RESET to support fastboot reboot_flag

[Neil Armstrong]

Disable the PSCI_RESET reboot handler to permit handling the reboot
flag and calling the PSCI handler with the flag in parameter.

Signed-off-by: Neil Armstrong 
---
 configs/sei510_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig
index 20534bd6b4..6c89d4a381 100644
--- a/configs/sei510_defconfig
+++ b/configs/sei510_defconfig
@@ -7,6 +7,7 @@ CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_IDENT_STRING=" sei510"
+# CONFIG_PSCI_RESET is not set
 CONFIG_DEBUG_UART=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_OF_BOARD_SETUP=y
-- 
2.22.0

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Re: [U-Boot] [PATCH 08/14] arm: dts: k3-am65-main: Add msmc_ram node

[Andreas Dannenberg]

On Tue, Aug 06, 2019 at 04:08:38PM +0530, Keerthy wrote:
> Add msmc_ram node needed for prueth
> 
> Signed-off-by: Keerthy 
> ---
>  arch/arm/dts/k3-am65-main.dtsi | 21 +
>  arch/arm/dts/k3-am65.dtsi  |  4 +++-
>  2 files changed, 24 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
> index 7d03706057..8e2a506185 100644
> --- a/arch/arm/dts/k3-am65-main.dtsi
> +++ b/arch/arm/dts/k3-am65-main.dtsi
> @@ -6,6 +6,27 @@
>   */
>  
>  &cbass_main {
> + msmc_ram: sram@7000 {
> + compatible = "mmio-sram";
> + reg = <0x0 0x7000 0x0 0x20>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x7000 0x20>;
> + u-boot,dm-spl;
> +
> + atf-sram@0 {
> + reg = <0x0 0x2>;
> + };
> +
> + sysfw-sram@f {
> + reg = <0xf 0x1>;
> + };
> +
> + l3cache-sram@10 {
> + reg = <0x10 0x10>;
> + };
> + };
> +
>   gic500: interrupt-controller@180 {
>   compatible = "arm,gic-v3";
>   #address-cells = <2>;
> diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi
> index a3abd146d1..431b27813a 100644
> --- a/arch/arm/dts/k3-am65.dtsi
> +++ b/arch/arm/dts/k3-am65.dtsi
> @@ -76,7 +76,9 @@
><0x00 0x4204 0x00 0x4204 0x00 0x03ac2400>,
><0x00 0x4510 0x00 0x4510 0x00 0x00c24000>,
><0x00 0x4600 0x00 0x4600 0x00 0x0020>,
> -  <0x00 0x4700 0x00 0x4700 0x00 0x00068400>;
> +  <0x00 0x4700 0x00 0x4700 0x00 0x00068400>,
> +  <0x07 0x 0x07 0x 0x01 0x000>,

Should align the width of the last block of zeroes with the other
numbers...

--
Andreas Dannenberg
Texas Instruments Inc


> +  <0x00 0x7000 0x00 0x7000 0x00 0x0020>;
>  
>   cbass_mcu: interconnect@2838 {
>   compatible = "simple-bus";
> -- 
> 2.17.1
> 
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[U-Boot] [PATCH v2 2/7] configs: meson64: permit redefining ENV_SIZE

[Neil Armstrong]

Permit redefining ENV_SIZE for board specific configs.

Signed-off-by: Neil Armstrong 
---
 include/configs/meson64.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 78b1615d5c..f8d3eee292 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -37,7 +37,9 @@
 
 #define CONFIG_CPU_ARMV8
 #define CONFIG_REMAKE_ELF
+#ifndef CONFIG_ENV_SIZE
 #define CONFIG_ENV_SIZE0x2000
+#endif
 #define CONFIG_SYS_MAXARGS 32
 #define CONFIG_SYS_MALLOC_LEN  (32 << 20)
 #define CONFIG_SYS_CBSIZE  1024
-- 
2.22.0

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[U-Boot] [PATCH v2 1/7] ARM: dts: Import Amlogic G12A SEI510 DT from Linux 5.3-rc1

[Neil Armstrong]

Import Linux 5.2-rc1 sei510 DT from 5f9e832c1370 ("Linus 5.3-rc1") for the
meson-g12a-sei510 board.

Signed-off-by: Neil Armstrong 
---
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/meson-g12a-sei510.dts | 502 +
 2 files changed, 503 insertions(+)
 create mode 100644 arch/arm/dts/meson-g12a-sei510.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ad4d2357bb..67b625e4f6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -136,6 +136,7 @@ dtb-$(CONFIG_ARCH_MESON) += \
meson-gxm-khadas-vim2.dtb \
meson-axg-s400.dtb \
meson-g12a-u200.dtb \
+   meson-g12a-sei510.dtb \
meson-g12b-odroid-n2.dtb
 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
diff --git a/arch/arm/dts/meson-g12a-sei510.dts 
b/arch/arm/dts/meson-g12a-sei510.dts
new file mode 100644
index 00..c7a8736885
--- /dev/null
+++ b/arch/arm/dts/meson-g12a-sei510.dts
@@ -0,0 +1,502 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-g12a.dtsi"
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "seirobotics,sei510", "amlogic,g12a";
+   model = "SEI Robotics SEI510";
+
+   adc_keys {
+   compatible = "adc-keys";
+   io-channels = <&saradc 0>;
+   io-channel-names = "buttons";
+   keyup-threshold-microvolt = <180>;
+
+   button-onoff {
+   label = "On/Off";
+   linux,code = ;
+   press-threshold-microvolt = <170>;
+   };
+   };
+
+   aliases {
+   serial0 = &uart_AO;
+   ethernet0 = ðmac;
+   };
+
+   mono_dac: audio-codec-0 {
+   compatible = "maxim,max98357a";
+   #sound-dai-cells = <0>;
+   sound-name-prefix = "U16";
+   sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>;
+   };
+
+   dmics: audio-codec-1 {
+   #sound-dai-cells = <0>;
+   compatible = "dmic-codec";
+   num-channels = <2>;
+   wakeup-delay-ms = <50>;
+   status = "okay";
+   sound-name-prefix = "MIC";
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   cvbs-connector {
+   compatible = "composite-video-connector";
+
+   port {
+   cvbs_connector_in: endpoint {
+   remote-endpoint = <&cvbs_vdac_out>;
+   };
+   };
+   };
+
+   emmc_pwrseq: emmc-pwrseq {
+   compatible = "mmc-pwrseq-emmc";
+   reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+   };
+
+   hdmi-connector {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_connector_in: endpoint {
+   remote-endpoint = <&hdmi_tx_tmds_out>;
+   };
+   };
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x4000>;
+   };
+
+   ao_5v: regulator-ao_5v {
+   compatible = "regulator-fixed";
+   regulator-name = "AO_5V";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   vin-supply = <&dc_in>;
+   regulator-always-on;
+   };
+
+   dc_in: regulator-dc_in {
+   compatible = "regulator-fixed";
+   regulator-name = "DC_IN";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   };
+
+   emmc_1v8: regulator-emmc_1v8 {
+   compatible = "regulator-fixed";
+   regulator-name = "EMMC_1V8";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   vin-supply = <&vddao_3v3>;
+   regulator-always-on;
+   };
+
+   vddao_3v3: regulator-vddao_3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "VDDAO_3V3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   vin-supply = <&dc_in>;
+   regulator-always-on;
+   };
+
+   vddao_3v3_t: regultor-vddao_3v3_t {
+   compatible = "regulator-fixed";
+   regulator-name = "VDDAO_3V3_T";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   vin-supply = <&vddao_3v3>;
+   gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+   enable-active-high;
+   };
+
+   vddio_ao1v8: regulator-vddio_ao1v8 {
+  

[U-Boot] [PATCH v2 4/7] arm: meson: add sm command to retrieve the reboot reason

[Neil Armstrong]

The Secure Monitor offers multiple services, like returning the
SoC unique serial number, and can provide the "reboot reason" as
set by the previous booted system.

This extends the Amlogic specific "sm" cmd with a "reboot_reason" subcommand
to print or set a specified environment variable with the reboot reason in
human readable format.

Signed-off-by: Neil Armstrong 
---
 arch/arm/include/asm/arch-meson/sm.h | 18 ++
 arch/arm/mach-meson/sm.c | 87 +++-
 2 files changed, 104 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-meson/sm.h 
b/arch/arm/include/asm/arch-meson/sm.h
index 60d04ae228..f3ae46a6d6 100644
--- a/arch/arm/include/asm/arch-meson/sm.h
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -12,4 +12,22 @@ ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, 
size_t size);
 
 int meson_sm_get_serial(void *buffer, size_t size);
 
+enum {
+   REBOOT_REASON_COLD = 0,
+   REBOOT_REASON_NORMAL = 1,
+   REBOOT_REASON_RECOVERY = 2,
+   REBOOT_REASON_UPDATE = 3,
+   REBOOT_REASON_FASTBOOT = 4,
+   REBOOT_REASON_SUSPEND_OFF = 5,
+   REBOOT_REASON_HIBERNATE = 6,
+   REBOOT_REASON_BOOTLOADER = 7,
+   REBOOT_REASON_SHUTDOWN_REBOOT = 8,
+   REBOOT_REASON_RPMBP = 9,
+   REBOOT_REASON_CRASH_DUMP = 11,
+   REBOOT_REASON_KERNEL_PANIC = 12,
+   REBOOT_REASON_WATCHDOG_REBOOT = 13,
+};
+
+int meson_sm_get_reboot_reason(void);
+
 #endif /* __MESON_SM_H__ */
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index 99fa17d9a8..fabcb3bfd7 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -8,6 +8,10 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#include 
 
 #define FN_GET_SHARE_MEM_INPUT_BASE0x8220
 #define FN_GET_SHARE_MEM_OUTPUT_BASE   0x8221
@@ -78,6 +82,39 @@ int meson_sm_get_serial(void *buffer, size_t size)
return 0;
 }
 
+#define AO_SEC_SD_CFG150xfc
+#define REBOOT_REASON_MASK GENMASK(15, 12)
+
+int meson_sm_get_reboot_reason(void)
+{
+   struct regmap *regmap;
+   int nodeoffset;
+   ofnode node;
+   unsigned int reason;
+
+   /* find the offset of compatible node */
+   nodeoffset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+  
"amlogic,meson-gx-ao-secure");
+   if (nodeoffset < 0) {
+   printf("%s: failed to get amlogic,meson-gx-ao-secure\n",
+  __func__);
+   return -ENODEV;
+   }
+
+   /* get regmap from the syscon node */
+   node = offset_to_ofnode(nodeoffset);
+   regmap = syscon_node_to_regmap(node);
+   if (IS_ERR(regmap)) {
+   printf("%s: failed to get regmap\n", __func__);
+   return -EINVAL;
+   }
+
+   regmap_read(regmap, AO_SEC_SD_CFG15, &reason);
+
+   /* The SMC call is not used, we directly use AO_SEC_SD_CFG15 */
+   return FIELD_GET(REBOOT_REASON_MASK, reason);
+}
+
 static int do_sm_serial(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
 {
@@ -96,8 +133,55 @@ static int do_sm_serial(cmd_tbl_t *cmdtp, int flag, int 
argc,
return CMD_RET_SUCCESS;
 }
 
+#define MAX_REBOOT_REASONS 14
+
+static const char *reboot_reasons[MAX_REBOOT_REASONS] = {
+   [REBOOT_REASON_COLD] = "cold_boot",
+   [REBOOT_REASON_NORMAL] = "normal",
+   [REBOOT_REASON_RECOVERY] = "recovery",
+   [REBOOT_REASON_UPDATE] = "update",
+   [REBOOT_REASON_FASTBOOT] = "fastboot",
+   [REBOOT_REASON_SUSPEND_OFF] = "suspend_off",
+   [REBOOT_REASON_HIBERNATE] = "hibernate",
+   [REBOOT_REASON_BOOTLOADER] = "bootloader",
+   [REBOOT_REASON_SHUTDOWN_REBOOT] = "shutdown_reboot",
+   [REBOOT_REASON_RPMBP] = "rpmbp",
+   [REBOOT_REASON_CRASH_DUMP] = "crash_dump",
+   [REBOOT_REASON_KERNEL_PANIC] = "kernel_panic",
+   [REBOOT_REASON_WATCHDOG_REBOOT] = "watchdog_reboot",
+};
+
+static int do_sm_reboot_reason(cmd_tbl_t *cmdtp, int flag, int argc,
+   char *const argv[])
+{
+   const char *reason_str;
+   char *destarg = NULL;
+   int reason;
+
+   if (argc > 1)
+   destarg = argv[1];
+
+   reason = meson_sm_get_reboot_reason();
+   if (reason < 0)
+   return CMD_RET_FAILURE;
+
+   if (reason >= MAX_REBOOT_REASONS ||
+   !reboot_reasons[reason])
+   reason_str = "unknown";
+   else
+   reason_str = reboot_reasons[reason];
+
+   if (destarg)
+   env_set(destarg, reason_str);
+   else
+   printf("reboot reason: %s (%x)\n", reason_str, reason);
+
+   return CMD_RET_SUCCESS;
+}
+
 static cmd_tbl_t cmd_sm_sub[] = {
U_BOOT_CMD_MKENT(serial, 2, 1, do_sm_serial, "", ""),
+   U_BOOT_CMD_MKENT(reboot_reason, 1, 1, do_sm_reboot_reason, "", ""),
 };
 
 static int do_sm(cmd_tbl_t *cmdtp, int flag, int argc,
@@ -123,5 +2

[U-Boot] [PATCH v2 0/7] amlogic: add support for the SEI Robotic SEI510

[Neil Armstrong]

The SEI510 board is based on the Amlogic S905X2 SoC
from the Amlogic G12A SoC family.

The board has the following specifications :
- Amlogic S905X2 ARM Cortex-A53 quad-core SoC
- XGB DDR4 SDRAM
- 10/100 Ethernet (Internal PHY)
- 1 x USB 3.0 Host
- eMMC
- SDcard
- Infrared receiver
- SDIO WiFi Module

The board default behaviour is for booting Android and triggers
fastboot on recovery or reboot mode.

Changes since v1:
- moved sm and reboot_reason code into separate patches
- removed unused sm subcommand

Jerome Brunet (1):
  boards: meson: add g12a sei510

Neil Armstrong (6):
  ARM: dts: Import Amlogic G12A SEI510 DT from Linux 5.3-rc1
  configs: meson64: permit redefining ENV_SIZE
  arm: meson: add sm cmd to retrieve SoC serial
  arm: meson: add sm command to retrieve the reboot reason
  ARM: meson: Add support for fastboot_set_reboot_flag()
  configs: sei510: disable PSCI_RESET to support fastboot reboot_flag

 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/meson-g12a-sei510.dts   | 502 +++
 arch/arm/include/asm/arch-meson/sm.h |  18 +
 arch/arm/mach-meson/board-common.c   |  33 ++
 arch/arm/mach-meson/sm.c | 133 +++
 board/amlogic/sei510/MAINTAINERS |   5 +
 board/amlogic/sei510/Makefile|   6 +
 board/amlogic/sei510/README  | 123 +++
 board/amlogic/sei510/sei510.c|  26 ++
 configs/sei510_defconfig |  75 
 include/configs/meson64.h|   2 +
 include/configs/sei510.h | 137 
 12 files changed, 1061 insertions(+)
 create mode 100644 arch/arm/dts/meson-g12a-sei510.dts
 create mode 100644 board/amlogic/sei510/MAINTAINERS
 create mode 100644 board/amlogic/sei510/Makefile
 create mode 100644 board/amlogic/sei510/README
 create mode 100644 board/amlogic/sei510/sei510.c
 create mode 100644 configs/sei510_defconfig
 create mode 100644 include/configs/sei510.h

-- 
2.22.0

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Re: [U-Boot] [PATCH 03/14] misc: uclass: Introduce misc_init_by_ofnode

[Andreas Dannenberg]

On Tue, Aug 06, 2019 at 04:08:33PM +0530, Keerthy wrote:
> Introduce misc_init_by_ofnode to probe a misc device
> using its ofnode.
> 
> Signed-off-by: Keerthy 
> ---
>  drivers/misc/misc-uclass.c | 25 +
>  include/misc.h |  9 +
>  2 files changed, 34 insertions(+)
> 
> diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c
> index 55381edc98..835d3f7118 100644
> --- a/drivers/misc/misc-uclass.c
> +++ b/drivers/misc/misc-uclass.c
> @@ -5,6 +5,8 @@
>  
>  #include 
>  #include 
> +#include 
> +#include 
>  #include 
>  #include 
>  
> @@ -65,6 +67,29 @@ int misc_set_enabled(struct udevice *dev, bool val)
>   return ops->set_enabled(dev, val);
>  }
>  
> +int misc_init_by_ofnode(ofnode node)
> +{
> + struct udevice *dev = NULL;
> + int ret;
> + long temp1, temp2;
> +
> + temp1 = ofnode_to_offset(node);
> +
> + for (ret = uclass_find_first_device(UCLASS_MISC, &dev); dev;
> +  ret = uclass_find_next_device(&dev)) {
> + temp2 = ofnode_to_offset(dev_ofnode(dev));
> + if (temp1 == temp2) {
> + ret = device_probe(dev);
> + if (ret)
> + debug("%s: Failed to initialize - %d\n",

Doesn't that put a 'minus' in front of an already negative number? Might
look more confusing than it needs to be. I've often seen the formatting
specifier for errors be like "...(%d)...".

> +   dev->name, ret);
> + return ret;
> + }
> + }
> +
> + return -ENODEV;
> +}
> +
>  UCLASS_DRIVER(misc) = {
>   .id = UCLASS_MISC,
>   .name   = "misc",
> diff --git a/include/misc.h b/include/misc.h
> index 12d1325ee2..79263ed480 100644
> --- a/include/misc.h
> +++ b/include/misc.h
> @@ -76,6 +76,15 @@ int misc_call(struct udevice *dev, int msgid, void 
> *tx_msg, int tx_size,
>   */
>  int misc_set_enabled(struct udevice *dev, bool val);
>  
> +/**
> + * misc_init_by_ofnode() - Probe a misc device by using ofnode.
> + * @node: ofnode of the misc device.
> + *
> + * A misc device is probed using ofnode.
> + *
> + * Return: -ve on error, 0 on success
> + */
> +int misc_init_by_ofnode(ofnode node);

Missing blank line here.

--
Andreas Dannenberg
Texas Instruments Inc



>  /*
>   * struct misc_ops - Driver model Misc operations
>   *
> -- 
> 2.17.1
> 
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Re: [U-Boot] [PATCH 00/14] net: ti: icssg: Add prueth support

[Andreas Dannenberg]

Keerthy,

On Tue, Aug 06, 2019 at 04:08:30PM +0530, Keerthy wrote:
> The series adds support for icssg_prueth functionality
> on u-boot. This series is based on top of master branch.
> rproc init needs to be done from uboot command prompt.
> The pru/rtu firmware loading is done by prueth driver soon after
> config paramters are setup.

for everybody's benefit, where does this firmware come from so one can
experiment with this patch series?

--
Andreas Dannenberg
Texas Instruments Inc

> 
> Currently only slice0/1 of icssg2 instance on am6-evm
> is supported. i.e Both slices of icssg2 instance are supported.
> 
> On u-boot prompt following commands to test icssg2_port 0 on am654-evm:
> 
> setenv ethact pruss2_eth;  setenv serverip 172.24.191.45; fatload mmc 1 
> ${pru0loadaddr} am65x-pru0-prueth-fw.elf; fatload mmc 1 ${rtu0loadaddr} 
> am65x-rtu0-prueth-fw.elf; rproc init; setenv autoload no; dhcp; tftp 
> 0x8200 Image; tftp 0x8300 k3-am654-base-board.dtb; booti 0x8200 - 
> 0x8300
> 
> This tests tftp on prueth.
> 
> Note: Uboot ethernet driver architecture supports once
> instance per probe. So only one of the ports are supported
> per instance. So DT of prueth node should have either ethernet-mii0
> or ethernet-mii1. 
> 
> Keerthy (14):
>   net: eth-uclass: eth_get_dev based on SEQ_ALIAS instead of probe order
>   net: eth-uclass: call stop only for active devices
>   misc: uclass: Introduce misc_init_by_ofnode
>   soc: ti: pruss: add a misc driver for PRUSS in TI SoCs
>   remoteproc: pruss: add PRU remoteproc driver
>   net: ti: icssg-prueth: Add ICSSG ethernet driver
>   net: ti: icssg-prueth: Workaround to shutdown the prueth firmware
>   arm: dts: k3-am65-main: Add msmc_ram node
>   arm: dts: k3-am654-base-board-u-boot: Add icssg specific msmc_ram
> carveout nodes
>   arm: dts: k3-am65-main: Add scm_conf node
>   arm: dts: k3-am65-main: Add pruss nodes for ICSSG2
>   arm64: dts: ti: am654-base-board: add ICSSG2 Ethernet support
>   configs: am65x_evm_a53_defconfig: Enable CONFIG_REMOTEPROC_TI_PRU
>   configs: am65x_evm_a53_defconfig: Enable CONFIG_CMD_REMOTEPROC
> 
>  arch/arm/dts/k3-am65-main.dtsi   | 212 
>  arch/arm/dts/k3-am65.dtsi|   4 +-
>  arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 130 +
>  configs/am65x_evm_a53_defconfig  |   5 +
>  drivers/misc/misc-uclass.c   |  25 +
>  drivers/net/ti/Kconfig   |   8 +
>  drivers/net/ti/Makefile  |   1 +
>  drivers/net/ti/icssg-prueth.c| 525 +++
>  drivers/net/ti/icssg.h   |  31 ++
>  drivers/net/ti/icssg_classifier.c| 397 ++
>  drivers/remoteproc/Kconfig   |  11 +
>  drivers/remoteproc/Makefile  |   1 +
>  drivers/remoteproc/pru_rproc.c   | 384 ++
>  drivers/soc/ti/Kconfig   |  13 +
>  drivers/soc/ti/Makefile  |   1 +
>  drivers/soc/ti/pruss.c   | 143 +
>  include/misc.h   |   9 +
>  include/ti-pruss.h   |  13 +
>  net/eth-uclass.c |   7 +-
>  19 files changed, 1916 insertions(+), 4 deletions(-)
>  create mode 100644 drivers/net/ti/icssg-prueth.c
>  create mode 100644 drivers/net/ti/icssg.h
>  create mode 100644 drivers/net/ti/icssg_classifier.c
>  create mode 100644 drivers/remoteproc/pru_rproc.c
>  create mode 100644 drivers/soc/ti/pruss.c
>  create mode 100644 include/ti-pruss.h
> 
> -- 
> 2.17.1
> 
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[U-Boot] [PATCH v3 2/8] phy: mediatek: add MediaTek T-PHY support for PCIe

[Frank Wunderlich]

From: Ryder Lee 

The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now
we just enable PCIe. As for the other functionalities will be
added gradually in upcoming days.

This is adapted from the Linux version.

changes since v2:
 - use clrsetbits_le32 instead of readl/writel
 - change SSC-delta

Tested-by: Frank Wunderlich 
Signed-off-by: Ryder Lee 
Signed-off-by: Frank Wunderlich 
---
 drivers/phy/Kconfig|  11 ++
 drivers/phy/Makefile   |   1 +
 drivers/phy/phy-mtk-tphy.c | 362 +
 3 files changed, 374 insertions(+)
 create mode 100644 drivers/phy/phy-mtk-tphy.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 957efb3984..2099dd9547 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -190,4 +190,15 @@ config MT76X8_USB_PHY

  This PHY is found on MT76x8 devices supporting USB.

+config PHY_MTK_TPHY
+   bool "MediaTek T-PHY Driver"
+   depends on PHY
+   depends on ARCH_MEDIATEK
+   help
+ MediaTek T-PHY driver supports usb2.0, usb3.0 ports, PCIe and
+ SATA, and meanwhile supports two version T-PHY which have
+ different banks layout, the T-PHY with shared banks between
+ multi-ports is first version, otherwise is second veriosn,
+ so you can easily distinguish them by banks layout.
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 90646ca55b..15b4d58a2d 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
 obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
 obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o
 obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
+obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c
new file mode 100644
index 00..3701481256
--- /dev/null
+++ b/drivers/phy/phy-mtk-tphy.c
@@ -0,0 +1,362 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2015 - 2019 MediaTek Inc.
+ * Author: Chunfeng Yun 
+ *Ryder Lee 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/* version V1 sub-banks offset base address */
+/* banks shared by multiple phys */
+#define SSUSB_SIFSLV_V1_SPLLC  0x000   /* shared by u3 phys */
+#define SSUSB_SIFSLV_V1_CHIP   0x300   /* shared by u3 phys */
+/* u3/pcie/sata phy banks */
+#define SSUSB_SIFSLV_V1_U3PHYD 0x000
+#define SSUSB_SIFSLV_V1_U3PHYA 0x200
+
+#define U3P_U3_CHIP_GPIO_CTLD  0x0c
+#define P3C_REG_IP_SW_RST  BIT(31)
+#define P3C_MCU_BUS_CK_GATE_EN BIT(30)
+#define P3C_FORCE_IP_SW_RSTBIT(29)
+
+#define U3P_U3_CHIP_GPIO_CTLE  0x10
+#define P3C_RG_SWRST_U3_PHYD   BIT(25)
+#define P3C_RG_SWRST_U3_PHYD_FORCE_EN  BIT(24)
+
+#define U3P_U3_PHYA_REG0   0x000
+#define P3A_RG_CLKDRV_OFF  GENMASK(3, 2)
+#define P3A_RG_CLKDRV_OFF_VAL(x)   ((0x3 & (x)) << 2)
+
+#define U3P_U3_PHYA_REG1   0x004
+#define P3A_RG_CLKDRV_AMP  GENMASK(31, 29)
+#define P3A_RG_CLKDRV_AMP_VAL(x)   ((0x7 & (x)) << 29)
+
+#define U3P_U3_PHYA_DA_REG00x100
+#define P3A_RG_XTAL_EXT_PE2H   GENMASK(17, 16)
+#define P3A_RG_XTAL_EXT_PE2H_VAL(x)((0x3 & (x)) << 16)
+#define P3A_RG_XTAL_EXT_PE1H   GENMASK(13, 12)
+#define P3A_RG_XTAL_EXT_PE1H_VAL(x)((0x3 & (x)) << 12)
+#define P3A_RG_XTAL_EXT_EN_U3  GENMASK(11, 10)
+#define P3A_RG_XTAL_EXT_EN_U3_VAL(x)   ((0x3 & (x)) << 10)
+
+#define U3P_U3_PHYA_DA_REG40x108
+#define P3A_RG_PLL_DIVEN_PE2H  GENMASK(21, 19)
+#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
+#define P3A_RG_PLL_BC_PE2H_VAL(x)  ((0x3 & (x)) << 6)
+
+#define U3P_U3_PHYA_DA_REG50x10c
+#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
+#define P3A_RG_PLL_BR_PE2H_VAL(x)  ((0x3 & (x)) << 28)
+#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
+#define P3A_RG_PLL_IC_PE2H_VAL(x)  ((0xf & (x)) << 12)
+
+#define U3P_U3_PHYA_DA_REG60x110
+#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
+#define P3A_RG_PLL_IR_PE2H_VAL(x)  ((0xf & (x)) << 16)
+
+#define U3P_U3_PHYA_DA_REG70x114
+#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
+#define P3A_RG_PLL_BP_PE2H_VAL(x)  ((0xf & (x)) << 16)
+
+#define U3P_U3_PHYA_DA_REG20   0x13c
+#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
+#define P3A_RG_PLL_DELTA1_PE2H_VAL(x)  ((0x & (x)) << 16)
+
+#define U3P_U3_PHYA_DA_REG25   0x148
+#define P3A_RG_PLL_DELTA_PE2H  GENMASK(15, 0)
+#define P3A_RG_PLL_DELTA_PE2H_VAL(x)   (0x & (x))
+
+#define U3P_U3_PHYD_RXDET1 0x128
+#define P3D_RG_RXDET_STB2_SET  GENMASK(17, 9)
+#define P3D_RG_RXDET_STB2_SET_VAL(x)   ((0x1ff & (x)) << 9)
+
+#define U3P_U3_PHYD_RXDET2 0x12c
+#define P3D_RG_RXDET_STB2_SET_P3   GENMASK(8, 0)

[U-Boot] [PATCH v3 1/8] pci: mediatek: add PCIe controller support for MT7623

[Frank Wunderlich]

From: Ryder Lee 

This adds PCIe controller support for MT7623.
This is adapted from the Linux version.

changes since v2:
 - rename driver to "MediaTek PCIe Gen2 controller"
 - use clrsetbits_le32 instead of readl/writel

Tested-by: Frank Wunderlich 
Signed-off-by: Ryder Lee 
Signed-off-by: Frank Wunderlich 
---
 drivers/pci/Kconfig |   8 ++
 drivers/pci/Makefile|   1 +
 drivers/pci/pcie_mediatek.c | 279 
 3 files changed, 288 insertions(+)
 create mode 100644 drivers/pci/pcie_mediatek.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 3fe38f7315..88df9001ee 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -145,4 +145,12 @@ config PCI_MVEBU
  Say Y here if you want to enable PCIe controller support on
  Armada XP/38x SoCs.

+config PCIE_MEDIATEK
+   bool "MediaTek PCIe Gen2 controller"
+   depends on DM_PCI
+   depends on ARCH_MEDIATEK
+   help
+ Say Y here if you want to enable Gen2 PCIe controller,
+ which could be found on MT7623 SoC family.
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index b5ebd50c85..7093d63918 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
pcie_layerscape_gen4_fixup.o
 obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
 obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
+obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c
new file mode 100644
index 00..a0dcb258b0
--- /dev/null
+++ b/drivers/pci/pcie_mediatek.c
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2017-2019 MediaTek Inc.
+ * Author: Ryder Lee 
+ *Honghui Zhang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PCIe shared registers */
+#define PCIE_SYS_CFG   0x00
+#define PCIE_INT_ENABLE0x0c
+#define PCIE_CFG_ADDR  0x20
+#define PCIE_CFG_DATA  0x24
+
+/* PCIe per port registers */
+#define PCIE_BAR0_SETUP0x10
+#define PCIE_CLASS 0x34
+#define PCIE_LINK_STATUS   0x50
+
+#define PCIE_PORT_INT_EN(x)BIT(20 + (x))
+#define PCIE_PORT_PERST(x) BIT(1 + (x))
+#define PCIE_PORT_LINKUP   BIT(0)
+#define PCIE_BAR_MAP_MAX   GENMASK(31, 16)
+
+#define PCIE_BAR_ENABLEBIT(0)
+#define PCIE_REVISION_ID   BIT(0)
+#define PCIE_CLASS_CODE(0x60400 << 8)
+#define PCIE_CONF_REG(regn)(((regn) & GENMASK(7, 2)) | \
+   regn) >> 8) & GENMASK(3, 0)) << 24))
+#define PCIE_CONF_ADDR(regn, bdf) \
+   (PCIE_CONF_REG(regn) | (bdf))
+
+/* MediaTek specific configuration registers */
+#define PCIE_FTS_NUM   0x70c
+#define PCIE_FTS_NUM_MASK  GENMASK(15, 8)
+#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
+
+#define PCIE_FC_CREDIT 0x73c
+#define PCIE_FC_CREDIT_MASK(GENMASK(31, 31) | GENMASK(28, 16))
+#define PCIE_FC_CREDIT_VAL(x)  ((x) << 16)
+
+struct mtk_pcie_port {
+   void __iomem *base;
+   struct list_head list;
+   struct mtk_pcie *pcie;
+   struct reset_ctl reset;
+   struct clk sys_ck;
+   struct phy phy;
+   u32 slot;
+};
+
+struct mtk_pcie {
+   void __iomem *base;
+   struct clk free_ck;
+   struct list_head ports;
+};
+
+static int mtk_pcie_config_address(struct udevice *udev, pci_dev_t bdf,
+  uint offset, void **paddress)
+{
+   struct mtk_pcie *pcie = dev_get_priv(udev);
+
+   writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR);
+   *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3);
+
+   return 0;
+}
+
+static int mtk_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
+   uint offset, ulong *valuep,
+   enum pci_size_t size)
+{
+   return pci_generic_mmap_read_config(bus, mtk_pcie_config_address,
+   bdf, offset, valuep, size);
+}
+
+static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
+uint offset, ulong value,
+enum pci_size_t size)
+{
+   return pci_generic_mmap_write_config(bus, mtk_pcie_config_address,
+bdf, offset, value, size);
+}
+
+static const struct dm_pci_ops mtk_pcie_ops = {
+   .read_config= mtk_pcie_read_config,
+   .write_config   = mtk_pcie_write_config,
+};
+
+static void mtk_pcie_port_free(struct mtk_pcie_port *port)
+{
+   list_del(&port->list);
+   free(port);
+}
+
+static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
+{
+   struct mtk_pcie *pcie = port->pcie;
+   u32 slot = 

[U-Boot] [PATCH v3 5/8] dt-bindings: pcie: add a document for MT7623 PCIe controller

[Frank Wunderlich]

From: Ryder Lee 

This adds a document for MT7623 PCIe controller.

changes since v2: dt-bindings added with v3

Signed-off-by: Ryder Lee 
Signed-off-by: Frank Wunderlich 
---
 .../pci/mediatek-pcie.txt | 122 ++
 1 file changed, 122 insertions(+)
 create mode 100644 doc/device-tree-bindings/pci/mediatek-pcie.txt

diff --git a/doc/device-tree-bindings/pci/mediatek-pcie.txt 
b/doc/device-tree-bindings/pci/mediatek-pcie.txt
new file mode 100644
index 00..2f9f549b7a
--- /dev/null
+++ b/doc/device-tree-bindings/pci/mediatek-pcie.txt
@@ -0,0 +1,122 @@
+MediaTek Gen2 PCIe controller
+
+Required properties:
+- compatible: Should contain one of the following strings:
+   "mediatek,mt7623-pcie"
+- device_type: Must be "pci"
+- reg: Base addresses and lengths of the PCIe subsys and root ports.
+- reg-names: Names of the above areas to use during resource lookup.
+- #address-cells: Address representation for root ports (must be 3)
+- #size-cells: Size representation for root ports (must be 2)
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names:
+  Mandatory entries:
+   - sys_ckN :transaction layer and data link layer clock
+  Required entries for MT7623:
+   - free_ck :for reference clock of PCIe subsys
+  where N starting from 0 to one less than the number of root ports.
+- phys: List of PHY specifiers (used by generic PHY framework).
+- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
+  number of PHYs as specified in *phys* property.
+- power-domains: A phandle and power domain specifier pair to the power domain
+  which is responsible for collapsing and restoring power to the peripheral.
+- bus-range: Range of bus numbers associated with this controller.
+- ranges: Ranges for the PCI memory and I/O regions.
+
+Required properties for MT7623:
+- #interrupt-cells: Size representation for interrupts (must be 1)
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+  Please refer to the standard PCI bus binding document for a more detailed
+  explanation.
+- resets: Must contain an entry for each entry in reset-names.
+- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
+  number of root ports.
+
+In addition, the device tree node must have sub-nodes describing each
+PCIe port interface, having the following mandatory properties:
+
+Required properties:
+- device_type: Must be "pci"
+- reg: Only the first four bytes are used to refer to the correct bus number
+  and device number.
+- #address-cells: Must be 3
+- #size-cells: Must be 2
+- #interrupt-cells: Must be 1
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+  Please refer to the standard PCI bus binding document for a more detailed
+  explanation.
+- ranges: Sub-ranges distributed from the PCIe controller node. An empty
+  property is sufficient.
+
+Examples for MT7623:
+
+   hifsys: syscon@1a00 {
+   compatible = "mediatek,mt7623-hifsys",
+"syscon";
+   reg = <0x1a00 0x1000>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+   pcie: pcie@1a14 {
+   compatible = "mediatek,mt7623-pcie";
+   device_type = "pci";
+   reg = <0x1a14 0x1000>, /* PCIe shared registers */
+ <0x1a142000 0x1000>, /* Port0 registers */
+ <0x1a143000 0x1000>, /* Port1 registers */
+ <0x1a144000 0x1000>; /* Port2 registers */
+   reg-names = "subsys", "port0", "port1", "port2";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0xf800 0 0 0>;
+   interrupt-map = <0x 0 0 0 &sysirq GIC_SPI 193 
IRQ_TYPE_LEVEL_LOW>,
+   <0x0800 0 0 0 &sysirq GIC_SPI 194 
IRQ_TYPE_LEVEL_LOW>,
+   <0x1000 0 0 0 &sysirq GIC_SPI 195 
IRQ_TYPE_LEVEL_LOW>;
+   clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+<&hifsys CLK_HIFSYS_PCIE0>,
+<&hifsys CLK_HIFSYS_PCIE1>,
+<&hifsys CLK_HIFSYS_PCIE2>;
+   clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+   resets = <&hifsys HIFSYS_PCIE0_RST>,
+<&hifsys HIFSYS_PCIE1_RST>,
+<&hifsys HIFSYS_PCIE2_RST>;
+   reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+   phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
+  <&pcie2_phy PHY_TYPE_PCIE>;
+   phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+   power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+   bus-range = <0x00 0xff>;
+   ranges = <0x8100 0 0x1a16 0x1a16 0 0x0001   
/* I/O space */

[U-Boot] [PATCH v3 4/8] arm: dts: split mtk-reset.h into per-chip header

[Frank Wunderlich]

From: Ryder Lee 

This follows the linux header rules to avoid conflict bitfields.

changes since v2: none

Tested-by: Frank Wunderlich 
Signed-off-by: Ryder Lee 
Signed-off-by: Frank Wunderlich 
---
 arch/arm/dts/mt7623.dtsi  |  2 +-
 arch/arm/dts/mt7629.dtsi  |  2 +-
 .../reset/{mtk-reset.h => mt7623-reset.h} |  4 +--
 include/dt-bindings/reset/mt7629-reset.h  | 36 +++
 4 files changed, 39 insertions(+), 5 deletions(-)
 rename include/dt-bindings/reset/{mtk-reset.h => mt7623-reset.h} (88%)
 create mode 100644 include/dt-bindings/reset/mt7629-reset.h

diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 3a868ea2ee..1135b1e1ae 100644
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -11,7 +11,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include "skeleton.dtsi"

 / {
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index ecbd29d7ae..3c9eab9770 100644
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -10,7 +10,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include "skeleton.dtsi"

 / {
diff --git a/include/dt-bindings/reset/mtk-reset.h 
b/include/dt-bindings/reset/mt7623-reset.h
similarity index 88%
rename from include/dt-bindings/reset/mtk-reset.h
rename to include/dt-bindings/reset/mt7623-reset.h
index 78fcdab009..a859a5b26a 100644
--- a/include/dt-bindings/reset/mtk-reset.h
+++ b/include/dt-bindings/reset/mt7623-reset.h
@@ -6,11 +6,9 @@
 #ifndef _DT_BINDINGS_MTK_RESET_H_
 #define _DT_BINDINGS_MTK_RESET_H_

-/* ETHSYS */
+/* ETHSYS resets */
 #define ETHSYS_PPE_RST 31
-#define ETHSYS_EPHY_RST24
 #define ETHSYS_GMAC_RST23
-#define ETHSYS_ESW_RST 16
 #define ETHSYS_FE_RST  6
 #define ETHSYS_MCM_RST 2
 #define ETHSYS_SYS_RST 0
diff --git a/include/dt-bindings/reset/mt7629-reset.h 
b/include/dt-bindings/reset/mt7629-reset.h
new file mode 100644
index 00..8f1634f7a6
--- /dev/null
+++ b/include/dt-bindings/reset/mt7629-reset.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MTK_RESET_H_
+#define _DT_BINDINGS_MTK_RESET_H_
+
+/* PCIe Subsystem resets */
+#define PCIE1_CORE_RST 19
+#define PCIE1_MMIO_RST 20
+#define PCIE1_HRST 21
+#define PCIE1_USER_RST 22
+#define PCIE1_PIPE_RST 23
+#define PCIE0_CORE_RST 27
+#define PCIE0_MMIO_RST 28
+#define PCIE0_HRST 29
+#define PCIE0_USER_RST 30
+#define PCIE0_PIPE_RST 31
+
+/* SSUSB Subsystem resets */
+#define SSUSB_PHY_PWR_RST  3
+#define SSUSB_MAC_PWR_RST  4
+
+/* ETH Subsystem resets */
+#define ETHSYS_SYS_RST 0
+#define ETHSYS_MCM_RST 2
+#define ETHSYS_HSDMA_RST   5
+#define ETHSYS_FE_RST  6
+#define ETHSYS_ESW_RST 16
+#define ETHSYS_GMAC_RST23
+#define ETHSYS_EPHY_RST24
+#define ETHSYS_CRYPTO_RST  29
+#define ETHSYS_PPE_RST 31
+
+#endif /* _DT_BINDINGS_MTK_RESET_H_ */
--
2.17.1

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[U-Boot] [PATCH v3 6/8] dt-bindings: phy: add a document for MediaTek tphy

[Frank Wunderlich]

From: Ryder Lee 

This adds a document for tphy which supports physical layer
functionality for a number of controllers on MediaTek SoCs,
such as, USB2.0, USB3.0, PCIe, and SATA.

changes since v2: dt-bindings added with v3

Signed-off-by: Ryder Lee 
Signed-off-by: Frank Wunderlich 
---
 doc/device-tree-bindings/phy/phy-mtk-tphy.txt | 86 +++
 1 file changed, 86 insertions(+)
 create mode 100644 doc/device-tree-bindings/phy/phy-mtk-tphy.txt

diff --git a/doc/device-tree-bindings/phy/phy-mtk-tphy.txt 
b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt
new file mode 100644
index 00..037c5a4be5
--- /dev/null
+++ b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt
@@ -0,0 +1,86 @@
+MediaTek T-PHY binding
+--
+
+T-phy controller supports physical layer functionality for a number of
+controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
+
+Required properties (controller (parent) node):
+ - compatible  : should be one of
+ "mediatek,generic-tphy-v1"
+ - clocks  : (deprecated, use port's clocks instead) a list of phandle +
+ clock-specifier pairs, one for each entry in clock-names
+ - clock-names : (deprecated, use port's one instead) must contain
+ "u3phya_ref": for reference clock of usb3.0 analog phy.
+
+Required nodes : a sub-node is required for each port the controller
+ provides. Address range information including the usual
+ 'reg' property is used inside these nodes to describe
+ the controller's topology.
+
+Optional properties (controller (parent) node):
+ - reg : offset and length of register shared by multiple ports,
+ exclude port's private register.
+ - mediatek,src-ref-clk-mhz: frequency of reference clock for slew rate
+ calibrate
+ - mediatek,src-coef   : coefficient for slew rate calibrate, depends on
+ SoC process
+
+Required properties (port (child) node):
+- reg  : address and length of the register set for the port.
+- clocks   : a list of phandle + clock-specifier pairs, one for each
+ entry in clock-names
+- clock-names  : must contain
+ "ref": 48M reference clock for HighSpeed analog phy; and 26M
+   reference clock for SuperSpeed analog phy, sometimes is
+   24M, 25M or 27M, depended on platform.
+- #phy-cells   : should be 1 (See second example)
+ cell after port phandle is phy type from:
+   - PHY_TYPE_USB2
+   - PHY_TYPE_USB3
+   - PHY_TYPE_PCIE
+   - PHY_TYPE_SATA
+
+Example:
+
+   u3phy2: usb-phy@1a244000 {
+   compatible = "mediatek,generic-tphy-v1";
+   reg = <0x1a244000 0x0700>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   status = "disabled";
+
+   u2port1: usb-phy@1a244800 {
+   reg = <0x1a244800 0x0100>;
+   clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+   clock-names = "ref";
+   #phy-cells = <1>;
+   status = "okay";
+   };
+
+   u3port1: usb-phy@1a244900 {
+   reg = <0x1a244900 0x0700>;
+   clocks = <&clk26m>;
+   clock-names = "ref";
+   #phy-cells = <1>;
+   status = "okay";
+   };
+   };
+
+Specifying phy control of devices
+-
+
+Device nodes should specify the configuration required in their "phys"
+property, containing a phandle to the phy port node and a device type;
+phy-names for each port are optional.
+
+Example:
+
+#include 
+
+usb30: usb@1127 {
+   ...
+   phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+   phy-names = "usb2-0", "usb3-0";
+   ...
+};
--
2.17.1

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[U-Boot] [PATCH v3 0/8] add PCIe, its PHY and AHCI support for mt7623

[Frank Wunderlich]

This series adds PCIe/PHY drivers which were adapted from Linux version.
The related drivers were tested on bpi-r2.

To get AHCI (SATA) working on R2 (ASM1061 PCIe2SATA-Controller) 2 addional
changes are needed (see Parts 5+6 from Oleksandr Rybalko)


changes since v2:
 - rename pcie-driver to "MediaTek PCIe Gen2 controller"
 - replaced readl/writel with (clr/set)bits_le32
 - add dt-binding documents for pcie and phy
changes since v1:
  - replaced mt2701 PCIe driver with version (PHY+PCIe) from Ryder

Oleksandr Rybalko (2):
  ahci-pci: ASM1061 report wrong class, but support AHCI.
  ata: ahci: Don't forget to clear upper address regs.

Ryder Lee (6):
  pci: mediatek: add PCIe controller support for MT7623
  phy: mediatek: add MediaTek T-PHY support for PCIe
  arm: dts: add PCIe controller for MT7623 SoC
  arm: dts: split mtk-reset.h into per-chip header
  dt-bindings: pcie: add a document for MT7623 PCIe controller
  dt-bindings: phy: add a document for MediaTek tphy

 arch/arm/dts/mt7623.dtsi  | 130 ++-
 arch/arm/dts/mt7623n-bananapi-bpi-r2.dts  |  29 ++
 arch/arm/dts/mt7629.dtsi  |   2 +-
 .../pci/mediatek-pcie.txt | 122 ++
 doc/device-tree-bindings/phy/phy-mtk-tphy.txt |  86 +
 drivers/ata/ahci-pci.c|   1 +
 drivers/ata/ahci.c|   9 +-
 drivers/pci/Kconfig   |   8 +
 drivers/pci/Makefile  |   1 +
 drivers/pci/pcie_mediatek.c   | 279 ++
 drivers/phy/Kconfig   |  11 +
 drivers/phy/Makefile  |   1 +
 drivers/phy/phy-mtk-tphy.c| 362 ++
 .../reset/{mtk-reset.h => mt7623-reset.h} |   4 +-
 include/dt-bindings/reset/mt7629-reset.h  |  36 ++
 15 files changed, 1074 insertions(+), 7 deletions(-)
 create mode 100644 doc/device-tree-bindings/pci/mediatek-pcie.txt
 create mode 100644 doc/device-tree-bindings/phy/phy-mtk-tphy.txt
 create mode 100644 drivers/pci/pcie_mediatek.c
 create mode 100644 drivers/phy/phy-mtk-tphy.c
 rename include/dt-bindings/reset/{mtk-reset.h => mt7623-reset.h} (88%)
 create mode 100644 include/dt-bindings/reset/mt7629-reset.h

--
2.17.1

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[U-Boot] [PATCH v3 8/8] ata: ahci: Don't forget to clear upper address regs.

[Frank Wunderlich]

From: Oleksandr Rybalko 

In 32bits mode upper bits need to be set to 0, otherwise controller will
try to DMA into not existing memory and stops with error.

changes since v2: none

Tested-by: Frank Wunderlich 
Signed-off-by: Frank Wunderlich 
Signed-off-by: Oleksandr Rybalko 
---
 drivers/ata/ahci.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index e3135bb75f..716f9c1c7e 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -593,10 +593,15 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, 
u8 port)
pp->cmd_tbl_sg =
(struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);

-   writel_with_flush((unsigned long)pp->cmd_slot,
- port_mmio + PORT_LST_ADDR);
+   writel_with_flush((u32)pp->cmd_slot, port_mmio + PORT_LST_ADDR);
+#ifndef CONFIG_PHYS_64BIT
+   writel_with_flush(0, port_mmio + PORT_LST_ADDR_HI);
+#endif

writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
+#ifndef CONFIG_PHYS_64BIT
+   writel_with_flush(0, port_mmio + PORT_FIS_ADDR_HI);
+#endif

 #ifdef CONFIG_SUNXI_AHCI
sunxi_dma_init(port_mmio);
--
2.17.1

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[U-Boot] [PATCH v3 3/8] arm: dts: add PCIe controller for MT7623 SoC

[Frank Wunderlich]

From: Ryder Lee 

This adds PCIe and its PHY nodes for MT7623.

changes since v2: none

Tested-by: Frank Wunderlich 
Signed-off-by: Ryder Lee 
Signed-off-by: Frank Wunderlich 
---
 arch/arm/dts/mt7623.dtsi | 128 +++
 arch/arm/dts/mt7623n-bananapi-bpi-r2.dts |  29 +
 2 files changed, 157 insertions(+)

diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 64079c61bf..3a868ea2ee 100644
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "skeleton.dtsi"
@@ -255,6 +256,133 @@
#reset-cells = <1>;
};

+   pcie: pcie@1a14 {
+   compatible = "mediatek,mt7623-pcie";
+   device_type = "pci";
+   reg = <0x1a14 0x1000>, /* PCIe shared registers */
+ <0x1a142000 0x1000>, /* Port0 registers */
+ <0x1a143000 0x1000>, /* Port1 registers */
+ <0x1a144000 0x1000>; /* Port2 registers */
+   reg-names = "subsys", "port0", "port1", "port2";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0xf800 0 0 0>;
+   interrupt-map = <0x 0 0 0 &sysirq GIC_SPI 193 
IRQ_TYPE_LEVEL_LOW>,
+   <0x0800 0 0 0 &sysirq GIC_SPI 194 
IRQ_TYPE_LEVEL_LOW>,
+   <0x1000 0 0 0 &sysirq GIC_SPI 195 
IRQ_TYPE_LEVEL_LOW>;
+   clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+<&hifsys CLK_HIFSYS_PCIE0>,
+<&hifsys CLK_HIFSYS_PCIE1>,
+<&hifsys CLK_HIFSYS_PCIE2>;
+   clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+   resets = <&hifsys HIFSYS_PCIE0_RST>,
+<&hifsys HIFSYS_PCIE1_RST>,
+<&hifsys HIFSYS_PCIE2_RST>;
+   reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+   phys = <&pcie0_port PHY_TYPE_PCIE>,
+  <&pcie1_port PHY_TYPE_PCIE>,
+  <&u3port1 PHY_TYPE_PCIE>;
+   phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+   power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+   bus-range = <0x00 0xff>;
+   status = "disabled";
+   ranges = <0x8100 0 0x1a16 0x1a16 0 0x0001
+ 0x8300 0 0x6000 0x6000 0 0x1000>;
+
+   pcie@0,0 {
+   reg = <0x 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   status = "disabled";
+   };
+
+   pcie@1,0 {
+   reg = <0x0800 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   status = "disabled";
+   };
+
+   pcie@2,0 {
+   reg = <0x1000 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   status = "disabled";
+   };
+   };
+
+   pcie0_phy: pcie-phy@1a149000 {
+   compatible = "mediatek,generic-tphy-v1";
+   reg = <0x1a149000 0x0700>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   status = "disabled";
+
+   pcie0_port: pcie-phy@1a149900 {
+   reg = <0x1a149900 0x0700>;
+   clocks = <&clk26m>;
+   clock-names = "ref";
+   #phy-cells = <1>;
+   status = "okay";
+   };
+   };
+
+   pcie1_phy: pcie-phy@1a14a000 {
+   compatible = "mediatek,generic-tphy-v1";
+   reg = <0x1a14a000 0x0700>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   status = "disabled";
+
+   pcie1_port: pcie-phy@1a14a900 {
+   reg = <0x1a14a900 0x0700>;
+   clocks = <&clk26m>;
+ 

[U-Boot] [PATCH v3 7/8] ahci-pci: ASM1061 report wrong class, but support AHCI.

[Frank Wunderlich]

From: Oleksandr Rybalko 

changes since v2: none

Tested-by: Frank Wunderlich 
Signed-off-by: Frank Wunderlich 
Signed-off-by: Oleksandr Rybalko 
---
 drivers/ata/ahci-pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c
index 1ca439d3fa..11ec98b56f 100644
--- a/drivers/ata/ahci-pci.c
+++ b/drivers/ata/ahci-pci.c
@@ -35,6 +35,7 @@ U_BOOT_DRIVER(ahci_pci) = {

 static struct pci_device_id ahci_pci_supported[] = {
{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) },
+   { PCI_DEVICE(0x1b21, 0x0611) },
{},
 };

--
2.17.1

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Re: [U-Boot] [RFC PATCH] cmd: avb: Support A/B slots

[Sam Protsenko]

Hi Igor,

On Tue, Aug 6, 2019 at 4:07 PM Igor Opaniuk  wrote:
>
> Hi Sam,
>
> Sorry for the late reply,
>
> On Fri, Aug 2, 2019 at 9:57 PM Sam Protsenko  
> wrote:
> >
> > Hi Igor, Jens,
> >
> > Can you please comments on next topics:
> >   1. With enabled A/B partitions, we have boot_a/boot_b,
> >  system_a/system_b, vendor_a/vendor_b partitions. Therefore
> >  requested_partitions[] should be slotted (which is done in this RFC
> >  patch). But this patch doesn' handle item (2) below.
> >   2. With dynamic partitions enabled, we don't have system/vendor
> >  anymore; instead we have single "super" partitions. Therefore
> >  requested_partitions[] table contains wrong partitions list for
> >  that particular case.
>
> This case can be handled in the latest libavb by
> 49936b4c010(libavb: Support vbmeta blobs in beginning of partition) [1].
> Anyway, this will require to pull the latest libavb sources into U-boot.
>
> >
> > Question: can we allow user to select which partition to verify, instead
> > of trying to verify hard-coded partitions from requested_partitions[]
> > table? This would solve both (1) and (2) items. But I'm not sure about
> > next possible issues:
> >   a. Wouldn't it break chain of trust somehow?
>
> It wont. If the user can obtain access to U-boot shell or edit U-boot
> env, the chain of trust is already broken (he can just wipe off
> `avb_verify` cmd invocation and that's it). But anyway, at first,
> check this solution [1].
>

Thanks for your reply. So as I understand we need to:
  1. Pull new libavb from AOSP to U-Boot
  2. Provide a parameter to 'avb verify' command, to pass partition to verify
  3. Rework AM57x boot procedure, and instead of just one 'avb verify'
call we should call 'avb verify' several times,one time per partition

Is that correct or you have another idea how to improve it?

> >   b. Is it ok to run avb_slot_verify() several times (one time per one
> >  partition?
> >
> > If (a) or (b) is of any concern, then maybe we can provide a way for the
> > user to pass any number of arguments to 'avb verify', like this:
> >
> > => avb verify boot_a super_a dtbo_a
> >
> > so help synopsis for 'avb verify' can be like this:
> >
> > avb verify  ...
> >
> > What do you think about this? Which would be the best course of action
> > to fix both issues (1) and (2)?
> >
> > Thanks.
> >
> > Signed-off-by: Sam Protsenko 
> > ---
> >  cmd/avb.c | 13 +
> >  1 file changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/cmd/avb.c b/cmd/avb.c
> > index 3f6fd763a0..d1942d6605 100644
> > --- a/cmd/avb.c
> > +++ b/cmd/avb.c
> > @@ -235,6 +235,7 @@ int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
> > AvbSlotVerifyData *out_data;
> > char *cmdline;
> > char *extra_args;
> > +   char *slot_suffix = "";
> >
> > bool unlocked = false;
> > int res = CMD_RET_FAILURE;
> > @@ -244,9 +245,12 @@ int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
> > return CMD_RET_FAILURE;
> > }
> >
> > -   if (argc != 1)
> > +   if (argc < 1 || argc > 2)
> > return CMD_RET_USAGE;
> >
> > +   if (argc == 2)
> > +   slot_suffix = argv[1];
> > +
> > printf("## Android Verified Boot 2.0 version %s\n",
> >avb_version_string());
> >
> > @@ -259,7 +263,7 @@ int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
> > slot_result =
> > avb_slot_verify(avb_ops,
> > requested_partitions,
> > -   "",
> > +   slot_suffix,
> > unlocked,
> > 
> > AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE,
> > &out_data);
> > @@ -419,7 +423,7 @@ static cmd_tbl_t cmd_avb[] = {
> > U_BOOT_CMD_MKENT(read_part, 5, 0, do_avb_read_part, "", ""),
> > U_BOOT_CMD_MKENT(read_part_hex, 4, 0, do_avb_read_part_hex, "", ""),
> > U_BOOT_CMD_MKENT(write_part, 5, 0, do_avb_write_part, "", ""),
> > -   U_BOOT_CMD_MKENT(verify, 1, 0, do_avb_verify_part, "", ""),
> > +   U_BOOT_CMD_MKENT(verify, 2, 0, do_avb_verify_part, "", ""),
> >  #ifdef CONFIG_OPTEE_TA_AVB
> > U_BOOT_CMD_MKENT(read_pvalue, 3, 0, do_avb_read_pvalue, "", ""),
> > U_BOOT_CMD_MKENT(write_pvalue, 3, 0, do_avb_write_pvalue, "", ""),
> > @@ -462,6 +466,7 @@ U_BOOT_CMD(
> > "avb read_pvalue   - read a persistent value \n"
> > "avb write_pvalue   - write a persistent value 
> > \n"
> >  #endif
> > -   "avb verify - run verification process using hash data\n"
> > +   "avb verify [slot_suffix] - run verification process using hash 
> > data\n"
> > "from vbmeta structure\n"
> > +   "[slot_suffix] - _a, _b, etc (if vbmeta partition is slotted)\n"
> > );
> > --
> > 2.20.1
> >
>
> Thanks
>
> [1] 
> https://android.googlesou

Re: [U-Boot] [RFC PATCH] cmd: avb: Support A/B slots

[Igor Opaniuk]

Hi Sam,

Sorry for the late reply,

On Fri, Aug 2, 2019 at 9:57 PM Sam Protsenko  wrote:
>
> Hi Igor, Jens,
>
> Can you please comments on next topics:
>   1. With enabled A/B partitions, we have boot_a/boot_b,
>  system_a/system_b, vendor_a/vendor_b partitions. Therefore
>  requested_partitions[] should be slotted (which is done in this RFC
>  patch). But this patch doesn' handle item (2) below.
>   2. With dynamic partitions enabled, we don't have system/vendor
>  anymore; instead we have single "super" partitions. Therefore
>  requested_partitions[] table contains wrong partitions list for
>  that particular case.

This case can be handled in the latest libavb by
49936b4c010(libavb: Support vbmeta blobs in beginning of partition) [1].
Anyway, this will require to pull the latest libavb sources into U-boot.

>
> Question: can we allow user to select which partition to verify, instead
> of trying to verify hard-coded partitions from requested_partitions[]
> table? This would solve both (1) and (2) items. But I'm not sure about
> next possible issues:
>   a. Wouldn't it break chain of trust somehow?

It wont. If the user can obtain access to U-boot shell or edit U-boot
env, the chain of trust is already broken (he can just wipe off
`avb_verify` cmd invocation and that's it). But anyway, at first,
check this solution [1].

>   b. Is it ok to run avb_slot_verify() several times (one time per one
>  partition?
>
> If (a) or (b) is of any concern, then maybe we can provide a way for the
> user to pass any number of arguments to 'avb verify', like this:
>
> => avb verify boot_a super_a dtbo_a
>
> so help synopsis for 'avb verify' can be like this:
>
> avb verify  ...
>
> What do you think about this? Which would be the best course of action
> to fix both issues (1) and (2)?
>
> Thanks.
>
> Signed-off-by: Sam Protsenko 
> ---
>  cmd/avb.c | 13 +
>  1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/cmd/avb.c b/cmd/avb.c
> index 3f6fd763a0..d1942d6605 100644
> --- a/cmd/avb.c
> +++ b/cmd/avb.c
> @@ -235,6 +235,7 @@ int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
> AvbSlotVerifyData *out_data;
> char *cmdline;
> char *extra_args;
> +   char *slot_suffix = "";
>
> bool unlocked = false;
> int res = CMD_RET_FAILURE;
> @@ -244,9 +245,12 @@ int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
> return CMD_RET_FAILURE;
> }
>
> -   if (argc != 1)
> +   if (argc < 1 || argc > 2)
> return CMD_RET_USAGE;
>
> +   if (argc == 2)
> +   slot_suffix = argv[1];
> +
> printf("## Android Verified Boot 2.0 version %s\n",
>avb_version_string());
>
> @@ -259,7 +263,7 @@ int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
> slot_result =
> avb_slot_verify(avb_ops,
> requested_partitions,
> -   "",
> +   slot_suffix,
> unlocked,
> 
> AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE,
> &out_data);
> @@ -419,7 +423,7 @@ static cmd_tbl_t cmd_avb[] = {
> U_BOOT_CMD_MKENT(read_part, 5, 0, do_avb_read_part, "", ""),
> U_BOOT_CMD_MKENT(read_part_hex, 4, 0, do_avb_read_part_hex, "", ""),
> U_BOOT_CMD_MKENT(write_part, 5, 0, do_avb_write_part, "", ""),
> -   U_BOOT_CMD_MKENT(verify, 1, 0, do_avb_verify_part, "", ""),
> +   U_BOOT_CMD_MKENT(verify, 2, 0, do_avb_verify_part, "", ""),
>  #ifdef CONFIG_OPTEE_TA_AVB
> U_BOOT_CMD_MKENT(read_pvalue, 3, 0, do_avb_read_pvalue, "", ""),
> U_BOOT_CMD_MKENT(write_pvalue, 3, 0, do_avb_write_pvalue, "", ""),
> @@ -462,6 +466,7 @@ U_BOOT_CMD(
> "avb read_pvalue   - read a persistent value \n"
> "avb write_pvalue   - write a persistent value \n"
>  #endif
> -   "avb verify - run verification process using hash data\n"
> +   "avb verify [slot_suffix] - run verification process using hash 
> data\n"
> "from vbmeta structure\n"
> +   "[slot_suffix] - _a, _b, etc (if vbmeta partition is slotted)\n"
> );
> --
> 2.20.1
>

Thanks

[1] 
https://android.googlesource.com/platform/external/avb/+/49936b4c0109411fdd38bd4ba3a32a01c40439a9

-- 
Best regards - Freundliche Grüsse - Meilleures salutations

Igor Opaniuk

mailto: igor.opan...@gmail.com
skype: igor.opanyuk
+380 (93) 836 40 67
http://ua.linkedin.com/in/iopaniuk
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[U-Boot] [PATCH 11/14] arm: dts: k3-am65-main: Add pruss nodes for ICSSG2

[Keerthy]

Add pruss nodes. Add nodes as in the 4.19 integration kernel.

Signed-off-by: Keerthy 
---
 arch/arm/dts/k3-am65-main.dtsi | 183 +
 1 file changed, 183 insertions(+)

diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index 0cd3e5e606..d357966dac 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -5,6 +5,8 @@
  * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
  */
 
+#include 
+
 &cbass_main {
msmc_ram: sram@7000 {
compatible = "mmio-sram";
@@ -172,4 +174,185 @@
clocks = <&k3_clks 113 1>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
};
+
+   icssg_soc_bus2: pruss-soc-bus@b226004 {
+   compatible = "ti,am654-icssg-soc-bus", "simple-bus";
+   reg = <0x00 0x0b226004 0x00 0x4>;
+   power-domains = <&k3_pds 64>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0x0b20 0x00 0x0b20 0x10>;
+   dma-ranges;
+
+   icssg2: icssg@b20 {
+   compatible = "ti,am654-icssg";
+   reg = <0xb20 0x8>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+   interrupt-names = "host2", "host3", "host4",
+ "host5", "host6", "host7",
+ "host8", "host9";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   dma-ranges;
+   ti,psil-base = <0x4300>;/* ICSSG2 PSIL thread 
start */
+
+   ti,psil-config0 {
+   linux,udma-mode = ;
+   statictr-type = ;
+   ti,needs-epib;
+   ti,psd-size = <16>;
+   };
+
+   ti,psil-config1 {
+   linux,udma-mode = ;
+   statictr-type = ;
+   ti,needs-epib;
+   ti,psd-size = <16>;
+   };
+
+   ti,psil-config2 {
+   linux,udma-mode = ;
+   statictr-type = ;
+   ti,needs-epib;
+   ti,psd-size = <16>;
+   };
+
+   ti,psil-config3 {
+   linux,udma-mode = ;
+   statictr-type = ;
+   ti,needs-epib;
+   ti,psd-size = <16>;
+   };
+
+   ti,psil-config4 {
+   linux,udma-mode = ;
+   statictr-type = ;
+   ti,needs-epib;
+   ti,psd-size = <16>;
+   };
+
+   ti,psil-config5 {
+   linux,udma-mode = ;
+   statictr-type = ;
+   ti,needs-epib;
+   ti,psd-size = <16>;
+   };
+
+   ti,psil-config6 {
+   linux,udma-mode = ;
+   statictr-type = ;
+   ti,needs-epib;
+   ti,psd-size = <16>;
+   };
+
+   ti,psil-config7 {
+   linux,udma-mode = ;
+   statictr-type = ;
+   ti,needs-epib;
+   ti,psd-size = <16>;
+   };
+
+   icssg2_mem: memories@b20 {
+   reg = <0xb20 0x2000>,
+ <0xb202000 0x2000>,
+ <0xb21 0x1>;
+   reg-names = "dram0", "dram1",
+   "shrdram2";
+   };
+
+   icssg2_cfg: cfg@b226000 {
+   compatible = "syscon";
+   reg = <0xb226000 0x200>;
+   };
+
+   icssg2_iep: iep@b22e000 {
+   compatible = "syscon";
+   reg = <0xb22e000 0x1000>;
+   };
+
+   icssg2_mii_rt: mii

[U-Boot] [PATCH 14/14] configs: am65x_evm_a53_defconfig: Enable CONFIG_CMD_REMOTEPROC

[Keerthy]

Enable CONFIG_CMD_REMOTEPROC needed to load prueth firmwares.

Signed-off-by: Keerthy 
---
 configs/am65x_evm_a53_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index dfb5bec794..a127610380 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -34,6 +34,7 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 # CONFIG_ISO_PARTITION is not set
-- 
2.17.1

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[U-Boot] [PATCH 12/14] arm64: dts: ti: am654-base-board: add ICSSG2 Ethernet support

[Keerthy]

ICSSG2 provide dual Gigabit Ethernet support.
Currently mdio clock is part of this node and also
the icssg2_rgmii_pins_default pinmux node has the
mdio pins as there is no davinci mdio driver.

Currently icssg2 instances are supported.
Either mii0 or mii1 can be enabled at a time.

Signed-off-by: Keerthy 
---
 arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 118 +++
 1 file changed, 118 insertions(+)

diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi 
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 71a7069e74..53399dfff6 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -16,6 +16,63 @@
serial2 = &main_uart0;
ethernet0 = &cpsw_port1;
};
+
+   /* Dual Ethernet application node on PRU-ICSSG2 */
+   pruss2_eth: pruss2_eth {
+   compatible = "ti,am654-icssg-prueth";
+   pinctrl-names = "default";
+   pinctrl-0 = <&icssg2_rgmii_pins_default>;
+   sram = <&icssg2_sram>;
+   clocks = <&k3_clks 64 3>;
+   clock-names = "mdio_fck";
+   u-boot,dm-spl;
+
+   prus = <&pru2_0>, <&rtu2_0>, <&pru2_1>, <&rtu2_1>;
+   firmware-name = "ti-pruss/am65x-pru0-prueth-fw.elf",
+   "ti-pruss/am65x-rtu0-prueth-fw.elf",
+   "ti-pruss/am65x-pru1-prueth-fw.elf",
+   "ti-pruss/am65x-rtu1-prueth-fw.elf";
+   mii-g-rt = <&icssg2_mii_g_rt>;
+   dma-coherent;
+   dmas = <&mcu_udmap &icssg2 0 UDMA_DIR_TX>,  /* egress slice 
0 */
+  <&mcu_udmap &icssg2 1 UDMA_DIR_TX>, /* egress slice 0 */
+  <&mcu_udmap &icssg2 2 UDMA_DIR_TX>, /* egress slice 0 */
+  <&mcu_udmap &icssg2 3 UDMA_DIR_TX>, /* mgmnt cmd slice 0 
*/
+  <&mcu_udmap &icssg2 4 UDMA_DIR_TX>, /* egress slice 1 */
+  <&mcu_udmap &icssg2 5 UDMA_DIR_TX>, /* egress slice 1 */
+  <&mcu_udmap &icssg2 6 UDMA_DIR_TX>, /* egress slice 1 */
+  <&mcu_udmap &icssg2 7 UDMA_DIR_TX>, /* mgmnt cmd slice 1 
*/
+
+  <&mcu_udmap &icssg2 0 UDMA_DIR_RX>, /* ingress slice 0 */
+  <&mcu_udmap &icssg2 1 UDMA_DIR_RX>, /* ingress slice 1 */
+  <&mcu_udmap &icssg2 2 UDMA_DIR_RX>, /* mgmnt rsp slice 0 
*/
+  <&mcu_udmap &icssg2 3 UDMA_DIR_RX>; /* mgmnt rsp slice 1 
*/
+   dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+   "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+   "rx0", "rx1",
+   "rxmgm0", "rxmgm1";
+
+   pruss2_emac0: ethernet-mii0 {
+   phy-handle = <&pruss2_eth0_phy>;
+   phy-mode = "rgmii-id";
+   syscon-rgmii-delay = <&scm_conf 0x4120>;
+   /* Filled in by bootloader */
+   local-mac-address = [00 00 00 00 00 00];
+   };
+
+/*
+ * Commenting out the second mii interface as the framework
+ * supports one interface in a single probe
+ * So either mii1 or mii2 can be used. In case mii1 is needed
+ * uncomment mii1 and comment out mii0
+   pruss2_emac1: ethernet-mii1 {
+   phy-handle = <&pruss2_eth1_phy>;
+   phy-mode = "rgmii-id";
+   syscon-rgmii-delay = <&scm_conf 0x4124>;
+   local-mac-address = [00 00 00 00 00 00];
+   };
+*/
+   };
 };
 
 &cbass_main{
@@ -274,6 +331,47 @@
u-boot,dm-spl;
};
 
+   icssg2_rgmii_pins_default: icssg2_rgmii_pins_default {
+   pinctrl-single,pins = <
+   AM65X_IOPAD(0x00ac, PIN_INPUT , 2) /* (AH15) 
PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */
+   AM65X_IOPAD(0x00b0, PIN_INPUT , 2) /* (AC16) 
PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */
+   AM65X_IOPAD(0x00b4, PIN_INPUT , 2) /* (AD17) 
PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */
+   AM65X_IOPAD(0x00b8, PIN_INPUT , 2) /* (AH14) 
PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */
+   AM65X_IOPAD(0x00cc, PIN_OUTPUT , 2) /* (AD15) 
PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */
+   AM65X_IOPAD(0x00d0, PIN_OUTPUT , 2) /* (AF14) 
PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */
+   AM65X_IOPAD(0x00d4, PIN_OUTPUT , 2) /* (AC15) 
PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */
+   AM65X_IOPAD(0x00d8, PIN_OUTPUT , 2) /* (AD14) 
PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */
+   AM65X_IOPAD(0x00dc, PIN_INPUT , 2) /* (AE14) 
PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */
+   AM65X_IOPAD(0x00c4, PIN_OUTPUT , 2) /* (AC17) 
PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */
+   AM65X_IOPAD(0x00c0, PIN_INPUT , 2) /* (AG15) 
PRG2

[U-Boot] [PATCH 10/14] arm: dts: k3-am65-main: Add scm_conf node

[Keerthy]

Add scm_conf node needed for prueth.

Signed-off-by: Keerthy 
---
 arch/arm/dts/k3-am65-main.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index 8e2a506185..0cd3e5e606 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -50,6 +50,14 @@
};
};
 
+   scm_conf: scm_conf@10 {
+   compatible = "syscon", "simple-mfd";
+   reg = <0 0x0010 0 0x1c000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0x0 0x0 0x0010 0x1c000>;
+   };
+
secure_proxy_main: mailbox@32c0 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
-- 
2.17.1

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[U-Boot] [PATCH 08/14] arm: dts: k3-am65-main: Add msmc_ram node

[Keerthy]

Add msmc_ram node needed for prueth

Signed-off-by: Keerthy 
---
 arch/arm/dts/k3-am65-main.dtsi | 21 +
 arch/arm/dts/k3-am65.dtsi  |  4 +++-
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index 7d03706057..8e2a506185 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -6,6 +6,27 @@
  */
 
 &cbass_main {
+   msmc_ram: sram@7000 {
+   compatible = "mmio-sram";
+   reg = <0x0 0x7000 0x0 0x20>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0x0 0x0 0x7000 0x20>;
+   u-boot,dm-spl;
+
+   atf-sram@0 {
+   reg = <0x0 0x2>;
+   };
+
+   sysfw-sram@f {
+   reg = <0xf 0x1>;
+   };
+
+   l3cache-sram@10 {
+   reg = <0x10 0x10>;
+   };
+   };
+
gic500: interrupt-controller@180 {
compatible = "arm,gic-v3";
#address-cells = <2>;
diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi
index a3abd146d1..431b27813a 100644
--- a/arch/arm/dts/k3-am65.dtsi
+++ b/arch/arm/dts/k3-am65.dtsi
@@ -76,7 +76,9 @@
 <0x00 0x4204 0x00 0x4204 0x00 0x03ac2400>,
 <0x00 0x4510 0x00 0x4510 0x00 0x00c24000>,
 <0x00 0x4600 0x00 0x4600 0x00 0x0020>,
-<0x00 0x4700 0x00 0x4700 0x00 0x00068400>;
+<0x00 0x4700 0x00 0x4700 0x00 0x00068400>,
+<0x07 0x 0x07 0x 0x01 0x000>,
+<0x00 0x7000 0x00 0x7000 0x00 0x0020>;
 
cbass_mcu: interconnect@2838 {
compatible = "simple-bus";
-- 
2.17.1

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[U-Boot] [PATCH 13/14] configs: am65x_evm_a53_defconfig: Enable CONFIG_REMOTEPROC_TI_PRU

[Keerthy]

Enable CONFIG_REMOTEPROC_TI_PRU and related configs.
With that enable ICSSG_PRUETH config.

Signed-off-by: Keerthy 
---
 configs/am65x_evm_a53_defconfig | 4 
 1 file changed, 4 insertions(+)

diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index d43df6a187..dfb5bec794 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -48,6 +48,7 @@ CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_REGMAP=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
@@ -69,6 +70,7 @@ CONFIG_PHY_TI=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
 CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_TI_AM64_ICSSG_PRUETH=y
 CONFIG_PHY=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
@@ -77,10 +79,12 @@ CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_REMOTEPROC_TI_PRU=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_TI=y
+CONFIG_TI_PRUSS=y
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
-- 
2.17.1

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[U-Boot] [PATCH 07/14] net: ti: icssg-prueth: Workaround to shutdown the prueth firmware

[Keerthy]

Currently shutdown command is yet to be implemented. So work
around clearing the task manager of ICSSG.

Signed-off-by: Keerthy 
---
 drivers/net/ti/icssg-prueth.c |  8 
 drivers/soc/ti/pruss.c| 15 +++
 include/ti-pruss.h|  1 +
 3 files changed, 24 insertions(+)

diff --git a/drivers/net/ti/icssg-prueth.c b/drivers/net/ti/icssg-prueth.c
index f8935ee087..980a1d9ee8 100644
--- a/drivers/net/ti/icssg-prueth.c
+++ b/drivers/net/ti/icssg-prueth.c
@@ -84,6 +84,7 @@ struct prueth {
struct regmap   *miig_rt;
fdt_addr_t  mdio_base;
phys_addr_t pruss_shrdram2;
+   phys_addr_t tmaddr;
struct mii_dev  *bus;
u32 port_id;
u32 sram_pa;
@@ -277,6 +278,9 @@ static void prueth_stop(struct udevice *dev)
 
dma_disable(&priv->dma_rx);
dma_free(&priv->dma_rx);
+
+   /* Workaround for shutdown command */
+   writel(0x0, priv->tmaddr + priv->slice * 0x200);
 }
 
 static const struct eth_ops prueth_ops = {
@@ -391,6 +395,10 @@ static int prueth_probe(struct udevice *dev)
if (ret)
return ret;
 
+   ret = pruss_request_tm_region(*prussdev, &prueth->tmaddr);
+   if (ret)
+   return ret;
+
node = dev_ofnode(dev);
eth0_node = ofnode_find_subnode(node, "ethernet-mii0");
eth1_node = ofnode_find_subnode(node, "ethernet-mii1");
diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c
index 03ddaaa539..0d53d0a26b 100644
--- a/drivers/soc/ti/pruss.c
+++ b/drivers/soc/ti/pruss.c
@@ -21,6 +21,8 @@
 #define PRUSS_CFG_IEPCLK   0x30
 #define ICSSG_CFG_CORE_SYNC0x3c
 
+#define ICSSG_TASK_MGR_OFFSET  0x2a000
+
 /* PRUSS_IEPCLK register bits */
 #define PRUSS_IEPCLK_IEP_OCP_CLK_ENBIT(0)
 
@@ -37,6 +39,19 @@ enum pruss_mem {
PRUSS_MEM_MAX,
 };
 
+int pruss_request_tm_region(struct udevice *dev, phys_addr_t *loc)
+{
+   struct pruss *priv;
+
+   priv = dev_get_priv(dev);
+   if (!priv || !priv->pruss_dram0)
+   return -EINVAL;
+
+   *loc = priv->pruss_dram0 + ICSSG_TASK_MGR_OFFSET;
+
+   return 0;
+}
+
 int pruss_request_shrmem_region(struct udevice *dev, phys_addr_t *loc)
 {
struct pruss *priv;
diff --git a/include/ti-pruss.h b/include/ti-pruss.h
index 547ec5ee33..9eadeef172 100644
--- a/include/ti-pruss.h
+++ b/include/ti-pruss.h
@@ -10,3 +10,4 @@ struct pruss {
 };
 
 int pruss_request_shrmem_region(struct udevice *dev, phys_addr_t *loc);
+int pruss_request_tm_region(struct udevice *dev, phys_addr_t *loc);
-- 
2.17.1

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[U-Boot] [PATCH 06/14] net: ti: icssg-prueth: Add ICSSG ethernet driver

[Keerthy]

This is the Ethernet driver for TI SoCs with the
ICSSG PRU Sub-system running EMAC firmware.
This driver caters to either of the slices(pru/rtu pair)
of the icssg subsystem.

Following are the firmwares needed to run cores:

am65x-pru0-prueth-fw.elf for pru0 of slice0
am65x-rtu0-prueth-fw.elf for rtu0 of slice0
am65x-pru1-prueth-fw.elf for pru1 of slice1
am65x-rtu1-prueth-fw.elf for rtu1 of slice1

One and exactly one of the slices is supported
as the u-boot ethernet supports probing one interface
at a time.

Signed-off-by: Keerthy 
---
 drivers/net/ti/Kconfig|   8 +
 drivers/net/ti/Makefile   |   1 +
 drivers/net/ti/icssg-prueth.c | 517 ++
 drivers/net/ti/icssg.h|  31 ++
 drivers/net/ti/icssg_classifier.c | 397 +++
 5 files changed, 954 insertions(+)
 create mode 100644 drivers/net/ti/icssg-prueth.c
 create mode 100644 drivers/net/ti/icssg.h
 create mode 100644 drivers/net/ti/icssg_classifier.c

diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index ecf642de10..1b6285709f 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -26,3 +26,11 @@ config TI_AM65_CPSW_NUSS
help
  This driver supports TI K3 MCU CPSW Nuss Ethernet controller
  in Texas Instruments K3 AM65x SoCs.
+
+config TI_AM64_ICSSG_PRUETH
+   bool "TI Gigabit PRU Ethernet driver"
+   depends on ARCH_K3
+   select PHYLIB
+   help
+ Support Gigabit Ethernet ports over the ICSSG PRU Subsystem
+ This subsystem is available starting with the AM65 platform.
diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
index 8d3808bb4b..b486498909 100644
--- a/drivers/net/ti/Makefile
+++ b/drivers/net/ti/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
 obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
 obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o
 obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o cpsw_mdio.o
+obj-$(CONFIG_TI_AM64_ICSSG_PRUETH) += icssg-prueth.o cpsw_mdio.o 
icssg_classifier.o
diff --git a/drivers/net/ti/icssg-prueth.c b/drivers/net/ti/icssg-prueth.c
new file mode 100644
index 00..f8935ee087
--- /dev/null
+++ b/drivers/net/ti/icssg-prueth.c
@@ -0,0 +1,517 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 AM65 PRU Ethernet Driver
+ *
+ * Copyright (C) 2019, Texas Instruments, Incorporated
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "cpsw_mdio.h"
+#include "icssg.h"
+
+#define ICSS_SLICE0 0
+#define ICSS_SLICE1 1
+
+#ifdef PKTSIZE_ALIGN
+#define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN
+#else
+#define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN)
+#endif
+
+#ifdef PKTBUFSRX
+#define UDMA_RX_DESC_NUM PKTBUFSRX
+#else
+#define UDMA_RX_DESC_NUM 4
+#endif
+
+enum prueth_mac {
+   PRUETH_MAC0 = 0,
+   PRUETH_MAC1,
+   PRUETH_NUM_MACS,
+};
+
+enum prueth_port {
+   PRUETH_PORT_HOST = 0,   /* host side port */
+   PRUETH_PORT_MII0,   /* physical port MII 0 */
+   PRUETH_PORT_MII1,   /* physical port MII 1 */
+};
+
+/* Config region lies in shared RAM */
+#define ICSS_CONFIG_OFFSET_SLICE0  0
+#define ICSS_CONFIG_OFFSET_SLICE1  0x8000
+
+/* Firmware flags */
+#define ICSS_SET_RUN_FLAG_VLAN_ENABLE  BIT(0)  /* switch only */
+#define ICSS_SET_RUN_FLAG_FLOOD_UNICASTBIT(1)  /* switch only 
*/
+#define ICSS_SET_RUN_FLAG_PROMISC  BIT(2)  /* MAC only */
+#define ICSS_SET_RUN_FLAG_MULTICAST_PROMISCBIT(3)  /* MAC only */
+
+/* CTRLMMR_ICSSG_RGMII_CTRL register bits */
+#define ICSSG_CTRL_RGMII_ID_MODE   BIT(24)
+
+/**
+ * enum pruss_pru_id - PRU core identifiers
+ */
+enum pruss_pru_id {
+   PRUSS_PRU0 = 0,
+   PRUSS_PRU1,
+   PRUSS_NUM_PRUS,
+};
+
+struct prueth {
+   struct udevice  *dev;
+   struct regmap   *miig_rt;
+   fdt_addr_t  mdio_base;
+   phys_addr_t pruss_shrdram2;
+   struct mii_dev  *bus;
+   u32 port_id;
+   u32 sram_pa;
+   struct phy_device   *phydev;
+   boolhas_phy;
+   ofnode  phy_node;
+   u32 phy_addr;
+   ofnode  eth_node[PRUETH_NUM_MACS];
+   struct icssg_config config[PRUSS_NUM_PRUS];
+   u32 mdio_freq;
+   int phy_interface;
+   struct  clk mdiofck;
+   struct dma  dma_tx;
+   struct dma  dma_rx;
+   u32 rx_next;
+   u32 rx_pend;
+   int slice;
+};
+
+static int icssg_phy_init(struct udevice *d

[U-Boot] [PATCH 09/14] arm: dts: k3-am654-base-board-u-boot: Add icssg specific msmc_ram carveout nodes

[Keerthy]

Add icssg specific msmc_ram carveout nodes

Signed-off-by: Keerthy 
---

Carving out as there is no msmc-ram driver.
Suggestions welcome.

 arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi 
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 8589f76d23..71a7069e74 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -361,3 +361,15 @@
 &wkup_i2c0 {
u-boot,dm-spl;
 };
+
+&msmc_ram {
+   icssg0_sram: icssg0-sram@4 {
+   reg = <0x4 0x1>;
+   };
+   icssg1_sram: icssg1-sram@5 {
+   reg = <0x5 0x1>;
+   };
+   icssg2_sram: icssg2-sram@6 {
+   reg = <0x6 0x1>;
+   };
+};
-- 
2.17.1

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[U-Boot] [PATCH 05/14] remoteproc: pruss: add PRU remoteproc driver

[Keerthy]

The Programmable Real-Time Unit Subsystem (PRUSS) consists of
dual 32-bit RISC cores (Programmable Real-Time Units, or PRUs)
for program execution. This patch adds a remoteproc platform
driver for managing the individual PRU RISC cores life cycle.

The driver currently supports the AM65xx SoC

Signed-off-by: Keerthy 
---
 drivers/remoteproc/Kconfig |  11 +
 drivers/remoteproc/Makefile|   1 +
 drivers/remoteproc/pru_rproc.c | 384 +
 3 files changed, 396 insertions(+)
 create mode 100644 drivers/remoteproc/pru_rproc.c

diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index f54a245424..15aeca65ab 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -61,4 +61,15 @@ config REMOTEPROC_TI_POWER
help
  Say 'y' here to add support for TI power processors such as those
  found on certain TI keystone and OMAP generation SoCs.
+
+config REMOTEPROC_TI_PRU
+   bool "Support for TI's K3 based PRU remoteproc driver"
+   select REMOTEPROC
+   depends on DM
+   depends on TI_PRUSS
+   depends on ARCH_K3
+   depends on OF_CONTROL
+   help
+ Say 'y' here to add support for TI' K3 remoteproc driver.
+
 endmenu
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 271ba55b09..73d061757a 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o
 obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o
 obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o
 obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
+obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o
diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
new file mode 100644
index 00..7768cb77e1
--- /dev/null
+++ b/drivers/remoteproc/pru_rproc.c
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PRU-RTU remoteproc driver for various SoCs
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Keerthy 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PRU_ICSS_PRU_CTRL registers */
+#define PRU_CTRL_CTRL  0x
+#define PRU_CTRL_STS   0x0004
+#define PRU_CTRL_WAKEUP_EN 0x0008
+#define PRU_CTRL_CYCLE 0x000C
+#define PRU_CTRL_STALL 0x0010
+#define PRU_CTRL_CTBIR00x0020
+#define PRU_CTRL_CTBIR10x0024
+#define PRU_CTRL_CTPPR00x0028
+#define PRU_CTRL_CTPPR10x002C
+
+/* CTRL register bit-fields */
+#define CTRL_CTRL_SOFT_RST_N   BIT(0)
+#define CTRL_CTRL_EN   BIT(1)
+#define CTRL_CTRL_SLEEPING BIT(2)
+#define CTRL_CTRL_CTR_EN   BIT(3)
+#define CTRL_CTRL_SINGLE_STEP  BIT(8)
+#define CTRL_CTRL_RUNSTATE BIT(15)
+
+#define RPROC_FLAGS_SHIFT  16
+#define RPROC_FLAGS_NONE   0
+#define RPROC_FLAGS_ELF_PHDR   BIT(0 + RPROC_FLAGS_SHIFT)
+#define RPROC_FLAGS_ELF_SHDR   BIT(1 + RPROC_FLAGS_SHIFT)
+
+/**
+ * enum pru_mem - PRU core memory range identifiers
+ */
+enum pru_mem {
+   PRU_MEM_IRAM = 0,
+   PRU_MEM_CTRL,
+   PRU_MEM_DEBUG,
+   PRU_MEM_MAX,
+};
+
+struct pru_privdata {
+   phys_addr_t pru_iram;
+   phys_addr_t pru_ctrl;
+   phys_addr_t pru_debug;
+   fdt_size_t pru_iramsz;
+   fdt_size_t pru_ctrlsz;
+   fdt_size_t pru_debugsz;
+   const char *fw_name;
+   u32 iram_da;
+   u32 pdram_da;
+   u32 sdram_da;
+   u32 shrdram_da;
+   u32 bootaddr;
+   int id;
+   struct pruss *prusspriv;
+};
+
+static int pru_start(struct udevice *dev)
+{
+   struct pru_privdata *priv;
+   int val = 0;
+
+   priv = dev_get_priv(dev);
+
+   val = CTRL_CTRL_EN | ((priv->bootaddr >> 2) << 16);
+   writel(val, priv->pru_ctrl + PRU_CTRL_CTRL);
+
+   return 0;
+}
+
+static int pru_stop(struct udevice *dev)
+{
+   struct pru_privdata *priv;
+   int val = 0;
+
+   priv = dev_get_priv(dev);
+
+   val = readl(priv->pru_ctrl + PRU_CTRL_CTRL);
+   val &= ~CTRL_CTRL_EN;
+   writel(val, priv->pru_ctrl + PRU_CTRL_CTRL);
+
+   return 0;
+}
+
+/**
+ * pru_init() - Initialize the remote processor
+ * @dev:   rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int pru_init(struct udevice *dev)
+{
+   return 0;
+}
+
+/*
+ * Convert PRU device address (data spaces only) to kernel virtual address
+ *
+ * Each PRU has access to all data memories within the PRUSS, accessible at
+ * different ranges. So, look through both its primary and secondary Data
+ * RAMs as well as any shared Data RAM to convert a PRU device address to
+ * kernel virtual address. Data RAM0 is primary Data RAM for PRU0 and Data
+ * RAM1 is primary Data RAM for PRU1.
+ */
+static void *pru_d_da_to_pa(struct pru_privdata *priv, 

[U-Boot] [PATCH 04/14] soc: ti: pruss: add a misc driver for PRUSS in TI SoCs

[Keerthy]

The Programmable Real-Time Unit - Industrial Communication
Subsystem (PRU-ICSS) is present of various TI SoCs such as
AM335x or AM437x or the AM654x family. Each SoC can have
one or more PRUSS instances that may or may not be identical.

The PRUSS consists of dual 32-bit RISC cores called the
Programmable Real-Time Units (PRUs), some shared, data and
instruction memories, some internal peripheral modules, and
an interrupt controller. The programmable nature of the PRUs
provide flexibility to implement custom peripheral interfaces,
fast real-time responses, or specialized data handling.

Add support for pruss driver. Currently am654x family
is supported.

Signed-off-by: Keerthy 
---
 drivers/soc/ti/Kconfig  |  13 
 drivers/soc/ti/Makefile |   1 +
 drivers/soc/ti/pruss.c  | 128 
 include/ti-pruss.h  |  12 
 4 files changed, 154 insertions(+)
 create mode 100644 drivers/soc/ti/pruss.c
 create mode 100644 include/ti-pruss.h

diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig
index e4f8834448..179b73a541 100644
--- a/drivers/soc/ti/Kconfig
+++ b/drivers/soc/ti/Kconfig
@@ -23,4 +23,17 @@ config TI_KEYSTONE_SERDES
 SerDes driver for Keystone SoC used for ethernet support on TI
 K2 platforms.
 
+config TI_PRUSS
+   bool "Support for TI's K3 based Pruss driver"
+   depends on DM
+   depends on ARCH_K3
+   depends on OF_CONTROL
+   depends on SYSCON
+   help
+
+ Support for TI PRU-ICSSG subsystem.
+
+  Currently supported on AM65xx SoCs Say Y here to support the
+ Programmable Realtime Unit (PRU).
+
 endif # SOC_TI
diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile
index 4ec04ee125..34f80aad29 100644
--- a/drivers/soc/ti/Makefile
+++ b/drivers/soc/ti/Makefile
@@ -2,3 +2,4 @@
 
 obj-$(CONFIG_TI_K3_NAVSS_RINGACC)  += k3-navss-ringacc.o
 obj-$(CONFIG_TI_KEYSTONE_SERDES)   += keystone_serdes.o
+obj-$(CONFIG_TI_PRUSS) += pruss.o
diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c
new file mode 100644
index 00..03ddaaa539
--- /dev/null
+++ b/drivers/soc/ti/pruss.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PRU-ICSS platform driver for various TI SoCs
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Keerthy 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PRUSS_CFG_IEPCLK   0x30
+#define ICSSG_CFG_CORE_SYNC0x3c
+
+/* PRUSS_IEPCLK register bits */
+#define PRUSS_IEPCLK_IEP_OCP_CLK_ENBIT(0)
+
+/* ICSSG CORE_SYNC register bits */
+#define ICSSG_CORE_VBUSP_SYNC_EN   BIT(0)
+
+/**
+ * enum pruss_mem - PRUSS memory range identifiers
+ */
+enum pruss_mem {
+   PRUSS_MEM_DRAM0 = 0,
+   PRUSS_MEM_DRAM1,
+   PRUSS_MEM_SHRD_RAM2,
+   PRUSS_MEM_MAX,
+};
+
+int pruss_request_shrmem_region(struct udevice *dev, phys_addr_t *loc)
+{
+   struct pruss *priv;
+
+   priv = dev_get_priv(dev);
+   if (!priv || !priv->pruss_shrdram2)
+   return -EINVAL;
+
+   *loc = priv->pruss_shrdram2;
+
+   return 0;
+}
+
+static int pruss_bind(struct udevice *dev)
+{
+   return dm_scan_fdt_dev(dev);
+}
+
+/**
+ * pruss_probe() - Basic probe
+ * @dev:   corresponding k3 device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int pruss_probe(struct udevice *dev)
+{
+   struct pruss *priv;
+   int ret, idx;
+   ofnode sub_node, node, memories;
+   struct regmap *regmap_cfg;
+   struct udevice *syscon;
+
+   priv = dev_get_priv(dev);
+   node = dev_ofnode(dev);
+   sub_node = ofnode_find_subnode(node, "cfg");
+   memories = ofnode_find_subnode(node, "memories");
+
+   idx = ofnode_stringlist_search(memories, "reg-names", "dram0");
+   priv->pruss_dram0 = ofnode_get_addr_size_index(memories, idx,
+  (u64 
*)&priv->pruss_dram0sz);
+   idx = ofnode_stringlist_search(memories, "reg-names", "dram1");
+   priv->pruss_dram1 = ofnode_get_addr_size_index(memories, idx,
+  (u64 
*)&priv->pruss_dram1sz);
+   idx = ofnode_stringlist_search(memories, "reg-names", "shrdram2");
+   priv->pruss_shrdram2 = ofnode_get_addr_size_index(memories, idx,
+ (u64 
*)&priv->pruss_shrdram2sz);
+
+   ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, sub_node,
+ &syscon);
+
+   regmap_cfg = syscon_get_regmap(syscon);
+
+   /*
+* The CORE block uses two multiplexers to allow software to
+* select one of three source clocks (ICSSGn_CORE_CLK, ICSSGn_ICLK or
+* ICSSGn_IEP_CLK) for the final clock source of the CORE block.
+* The user needs to configure ICSSG_CORE_SYNC_REG[0]

[U-Boot] [PATCH 01/14] net: eth-uclass: eth_get_dev based on SEQ_ALIAS instead of probe order

[Keerthy]

In case of multiple eth interfaces currently eth_get_dev
fetches the device based on the probe order which can be
random hence try with the alias.

Signed-off-by: Keerthy 
---
 net/eth-uclass.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 031d558625..f11c307b8c 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -68,8 +68,8 @@ struct udevice *eth_get_dev(void)
 
uc_priv = eth_get_uclass_priv();
if (!uc_priv->current)
-   eth_errno = uclass_first_device(UCLASS_ETH,
-   &uc_priv->current);
+   eth_errno = uclass_get_device_by_seq(UCLASS_ETH,
+0, &uc_priv->current);
return uc_priv->current;
 }
 
-- 
2.17.1

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[U-Boot] [PATCH 03/14] misc: uclass: Introduce misc_init_by_ofnode

[Keerthy]

Introduce misc_init_by_ofnode to probe a misc device
using its ofnode.

Signed-off-by: Keerthy 
---
 drivers/misc/misc-uclass.c | 25 +
 include/misc.h |  9 +
 2 files changed, 34 insertions(+)

diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c
index 55381edc98..835d3f7118 100644
--- a/drivers/misc/misc-uclass.c
+++ b/drivers/misc/misc-uclass.c
@@ -5,6 +5,8 @@
 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 
@@ -65,6 +67,29 @@ int misc_set_enabled(struct udevice *dev, bool val)
return ops->set_enabled(dev, val);
 }
 
+int misc_init_by_ofnode(ofnode node)
+{
+   struct udevice *dev = NULL;
+   int ret;
+   long temp1, temp2;
+
+   temp1 = ofnode_to_offset(node);
+
+   for (ret = uclass_find_first_device(UCLASS_MISC, &dev); dev;
+ret = uclass_find_next_device(&dev)) {
+   temp2 = ofnode_to_offset(dev_ofnode(dev));
+   if (temp1 == temp2) {
+   ret = device_probe(dev);
+   if (ret)
+   debug("%s: Failed to initialize - %d\n",
+ dev->name, ret);
+   return ret;
+   }
+   }
+
+   return -ENODEV;
+}
+
 UCLASS_DRIVER(misc) = {
.id = UCLASS_MISC,
.name   = "misc",
diff --git a/include/misc.h b/include/misc.h
index 12d1325ee2..79263ed480 100644
--- a/include/misc.h
+++ b/include/misc.h
@@ -76,6 +76,15 @@ int misc_call(struct udevice *dev, int msgid, void *tx_msg, 
int tx_size,
  */
 int misc_set_enabled(struct udevice *dev, bool val);
 
+/**
+ * misc_init_by_ofnode() - Probe a misc device by using ofnode.
+ * @node: ofnode of the misc device.
+ *
+ * A misc device is probed using ofnode.
+ *
+ * Return: -ve on error, 0 on success
+ */
+int misc_init_by_ofnode(ofnode node);
 /*
  * struct misc_ops - Driver model Misc operations
  *
-- 
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[U-Boot] [PATCH 02/14] net: eth-uclass: call stop only for active devices

[Keerthy]

Currently stop is being called unconditionally without even
checking if start is called which will result in crash where
multiple instances are present and stop gets called even
without calling start.

Signed-off-by: Keerthy 
---
 net/eth-uclass.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index f11c307b8c..58d6f26e04 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -557,7 +557,8 @@ static int eth_pre_remove(struct udevice *dev)
 {
struct eth_pdata *pdata = dev->platdata;
 
-   eth_get_ops(dev)->stop(dev);
+   if (eth_is_active(dev))
+   eth_get_ops(dev)->stop(dev);
 
/* clear the MAC address */
memset(pdata->enetaddr, 0, ARP_HLEN);
-- 
2.17.1

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[U-Boot] [PATCH 00/14] net: ti: icssg: Add prueth support

[Keerthy]

The series adds support for icssg_prueth functionality
on u-boot. This series is based on top of master branch.
rproc init needs to be done from uboot command prompt.
The pru/rtu firmware loading is done by prueth driver soon after
config paramters are setup.

Currently only slice0/1 of icssg2 instance on am6-evm
is supported. i.e Both slices of icssg2 instance are supported.

On u-boot prompt following commands to test icssg2_port 0 on am654-evm:

setenv ethact pruss2_eth;  setenv serverip 172.24.191.45; fatload mmc 1 
${pru0loadaddr} am65x-pru0-prueth-fw.elf; fatload mmc 1 ${rtu0loadaddr} 
am65x-rtu0-prueth-fw.elf; rproc init; setenv autoload no; dhcp; tftp 0x8200 
Image; tftp 0x8300 k3-am654-base-board.dtb; booti 0x8200 - 0x8300

This tests tftp on prueth.

Note: Uboot ethernet driver architecture supports once
instance per probe. So only one of the ports are supported
per instance. So DT of prueth node should have either ethernet-mii0
or ethernet-mii1. 

Keerthy (14):
  net: eth-uclass: eth_get_dev based on SEQ_ALIAS instead of probe order
  net: eth-uclass: call stop only for active devices
  misc: uclass: Introduce misc_init_by_ofnode
  soc: ti: pruss: add a misc driver for PRUSS in TI SoCs
  remoteproc: pruss: add PRU remoteproc driver
  net: ti: icssg-prueth: Add ICSSG ethernet driver
  net: ti: icssg-prueth: Workaround to shutdown the prueth firmware
  arm: dts: k3-am65-main: Add msmc_ram node
  arm: dts: k3-am654-base-board-u-boot: Add icssg specific msmc_ram
carveout nodes
  arm: dts: k3-am65-main: Add scm_conf node
  arm: dts: k3-am65-main: Add pruss nodes for ICSSG2
  arm64: dts: ti: am654-base-board: add ICSSG2 Ethernet support
  configs: am65x_evm_a53_defconfig: Enable CONFIG_REMOTEPROC_TI_PRU
  configs: am65x_evm_a53_defconfig: Enable CONFIG_CMD_REMOTEPROC

 arch/arm/dts/k3-am65-main.dtsi   | 212 
 arch/arm/dts/k3-am65.dtsi|   4 +-
 arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 130 +
 configs/am65x_evm_a53_defconfig  |   5 +
 drivers/misc/misc-uclass.c   |  25 +
 drivers/net/ti/Kconfig   |   8 +
 drivers/net/ti/Makefile  |   1 +
 drivers/net/ti/icssg-prueth.c| 525 +++
 drivers/net/ti/icssg.h   |  31 ++
 drivers/net/ti/icssg_classifier.c| 397 ++
 drivers/remoteproc/Kconfig   |  11 +
 drivers/remoteproc/Makefile  |   1 +
 drivers/remoteproc/pru_rproc.c   | 384 ++
 drivers/soc/ti/Kconfig   |  13 +
 drivers/soc/ti/Makefile  |   1 +
 drivers/soc/ti/pruss.c   | 143 +
 include/misc.h   |   9 +
 include/ti-pruss.h   |  13 +
 net/eth-uclass.c |   7 +-
 19 files changed, 1916 insertions(+), 4 deletions(-)
 create mode 100644 drivers/net/ti/icssg-prueth.c
 create mode 100644 drivers/net/ti/icssg.h
 create mode 100644 drivers/net/ti/icssg_classifier.c
 create mode 100644 drivers/remoteproc/pru_rproc.c
 create mode 100644 drivers/soc/ti/pruss.c
 create mode 100644 include/ti-pruss.h

-- 
2.17.1

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Re: [U-Boot] [PATCH] board: amlogic: document alternative libretech-cc installation methods

[Remi Pommarel]

Hi Daniel,

On Tue, Aug 06, 2019 at 04:10:42PM +0800, Daniel Drake wrote:
> As already documented in this README, several binaries must be
> glued together in order to boot the device.
> 
> Extend the documentation to cover the prebuilt binaries
> (saving you the hassle of installing ancient cross-compilers),
> and also mention the open source replacements for the encryption
> tool (which is especially useful if you want to avoid requiring
> 32-bit x86 binaries in your build system).
> 
> Signed-off-by: Daniel Drake 
> Cc: Neil Armstrong 
> ---
>  board/amlogic/p212/README.libretech-cc | 41 +++---
>  1 file changed, 37 insertions(+), 4 deletions(-)
> 
> diff --git a/board/amlogic/p212/README.libretech-cc 
> b/board/amlogic/p212/README.libretech-cc
> index d007f58764..6af7de3cfa 100644
> --- a/board/amlogic/p212/README.libretech-cc
> +++ b/board/amlogic/p212/README.libretech-cc
> @@ -38,9 +38,28 @@ U-Boot compilation
>  Image creation
>  ==
>  
> -Amlogic doesn't provide sources for the firmware and for tools needed
> -to create the bootloader image, so it is necessary to obtain them from
> -the git tree published by the board vendor:
> +To boot the system, u-boot must be combined with several earlier stage
> +bootloaders:
> +
> +* bl2.bin: vendor-provided binary blob
> +* bl21.bin: built from vendor u-boot source
> +* bl30.bin: vendor-provided binary blob
> +* bl301.bin: built from vendor u-boot source
> +* bl31.bin: vendor-provided binary blob
> +* acs.bin: built from vendor u-boot source

I don't know if it worth being mentioned here, but there is also a
reverse engineered effort on bl31 for gxl.

Thus it should be possible to use a bl31 built from mainline branch of
https://github.com/ARM-software/arm-trusted-firmware.

-- 
Remi

> +
> +These binaries and the tools required below have been collected and prebuilt
> +for convenience at 
> +
> +Download and extract the libretech-cc release from there, and set FIPDIR to
> +point to the `fip` subdirectory.
> +
> + > export FIPDIR=/path/to/extracted/fip
> +
> +Alternatively, you can obtain the original vendor u-boot tree which
> +contains the required blobs and sources, and build yourself.
> +Note that old compilers are required for this to build. The compilers here
> +are suggested by Amlogic, and they are 32-bit x86 binaries.
>  
>   > wget 
> https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
>   > wget 
> https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> @@ -53,7 +72,10 @@ the git tree published by the board vendor:
>   > make
>   > export FIPDIR=$PWD/fip
>  
> -Go back to mainline U-Boot source tree then :
> +Once you have the binaries available (either through the prebuilt download,
> +or having built the vendor u-boot yourself), you can then proceed to glue
> +everything together. Go back to mainline U-Boot source tree then :
> +
>   > mkdir fip
>  
>   > cp $FIPDIR/gxl/bl2.bin fip/
> @@ -100,3 +122,14 @@ and then write the image to SD with:
>   > DEV=/dev/your_sd_device
>   > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 
> seek=1
>   > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
> +
> +Note that Amlogic provides aml_encrypt_gxl as a 32-bit x86 binary with no
> +source code. Should you prefer to avoid that, there are open source reverse
> +engineered versions available:
> +
> +1. gxlimg , which comes with a handy
> +   Makefile that automates the whole process.
> +2. meson-tools 
> +
> +However, these community-developed alternatives are not endorsed by or
> +supported by Amlogic.
> -- 
> 2.20.1
> 
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[U-Boot] [PATCH] i2c: mxc: add CONFIG_CLK support

[Peng Fan]

When CONFIG_CLK enabled, use CLK UCLASS for clk related settings.

Signed-off-by: Peng Fan 
---
 arch/arm/include/asm/mach-imx/mxc_i2c.h |  6 ++
 drivers/i2c/mxc_i2c.c   | 17 +
 2 files changed, 23 insertions(+)

diff --git a/arch/arm/include/asm/mach-imx/mxc_i2c.h 
b/arch/arm/include/asm/mach-imx/mxc_i2c.h
index 8e1ea9af19..81fd981444 100644
--- a/arch/arm/include/asm/mach-imx/mxc_i2c.h
+++ b/arch/arm/include/asm/mach-imx/mxc_i2c.h
@@ -6,6 +6,9 @@
 #define __ASM_ARCH_MXC_MXC_I2C_H__
 #include 
 #include 
+#if CONFIG_IS_ENABLED(CLK)
+#include 
+#endif
 
 struct i2c_pin_ctrl {
iomux_v3_cfg_t i2c_mode;
@@ -47,6 +50,9 @@ struct mxc_i2c_bus {
ulong driver_data;
int speed;
struct i2c_pads_info *pads_info;
+#if CONFIG_IS_ENABLED(CLK)
+   struct clk per_clk;
+#endif
 #ifndef CONFIG_DM_I2C
int (*idle_bus_fn)(void *p);
void *idle_bus_data;
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 23119cce65..2e157bca58 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -890,9 +890,22 @@ static int mxc_i2c_probe(struct udevice *bus)
i2c_bus->bus = bus;
 
/* Enable clk */
+#if CONFIG_IS_ENABLED(CLK)
+   ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
+   if (ret) {
+   printf("Failed to get i2c clk\n");
+   return ret;
+   }
+   ret = clk_enable(&i2c_bus->per_clk);
+   if (ret) {
+   printf("Failed to enable i2c clk\n");
+   return ret;
+   }
+#else
ret = enable_i2c_clk(1, bus->seq);
if (ret < 0)
return ret;
+#endif
 
/*
 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
@@ -919,7 +932,11 @@ static int mxc_i2c_probe(struct udevice *bus)
ret = i2c_idle_bus(i2c_bus);
if (ret < 0) {
/* Disable clk */
+#if CONFIG_IS_ENABLED(CLK)
+   clk_disable(&i2c_bus->per_clk);
+#else
enable_i2c_clk(0, bus->seq);
+#endif
return ret;
}
 
-- 
2.16.4

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[U-Boot] [PATCH] tools: imx8mimage: fix HDMI/FIT parsing

[Peng Fan]

Add missed break for HDMI entry.
And moving FIT parsing earlier, because it does not have parameter,
it will not runs into CFG_REG_SIZE.

Signed-off-by: Peng Fan 
---
 tools/imx8mimage.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
index 50a256cbac..6c02337698 100644
--- a/tools/imx8mimage.c
+++ b/tools/imx8mimage.c
@@ -99,8 +99,6 @@ static void parse_cfg_cmd(int32_t cmd, char *token, char 
*name, int lineno)
break;
case CMD_SIGNED_HDMI:
signed_hdmi = token;
-   case CMD_FIT:
-   using_fit = 1;
break;
case CMD_DDR_FW:
/* Do nothing */
@@ -120,6 +118,11 @@ static void parse_cfg_fld(int32_t *cmd, char *token,
name, lineno, token);
exit(EXIT_FAILURE);
}
+   switch (*cmd) {
+   case CMD_FIT:
+   using_fit = 1;
+   break;
+   }
break;
case CFG_REG_SIZE:
parse_cfg_cmd(*cmd, token, name, lineno);
-- 
2.16.4

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[U-Boot] [PATCH] pinctrl: imx: use devfdt_get_addr_size_index

[Peng Fan]

fdtdec_get_addr_size could not parse addr/size correctly is
using address-cells 2 and size-cells 2 on an ARM32 SoC.
So switch to use devfdt_get_addr_size_index.

Signed-off-by: Peng Fan 
---
 drivers/pinctrl/nxp/pinctrl-imx.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c 
b/drivers/pinctrl/nxp/pinctrl-imx.c
index 0c9d15cb0c..69c4144365 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx.c
@@ -214,9 +214,7 @@ int imx_pinctrl_probe(struct udevice *dev,
if (info->flags & IMX8_USE_SCU)
return 0;
 
-   addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
-   &size);
-
+   addr = devfdt_get_addr_size_index(dev, 0, &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
 
-- 
2.16.4

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[U-Boot] [PATCH 2/4] clk: imx: add pll14xx driver

[Peng Fan]

Add pll14xx driver

Signed-off-by: Peng Fan 
---
 drivers/clk/imx/clk-pll14xx.c | 371 ++
 drivers/clk/imx/clk.h |  25 +++
 2 files changed, 396 insertions(+)
 create mode 100644 drivers/clk/imx/clk-pll14xx.c

diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
new file mode 100644
index 00..21c258a380
--- /dev/null
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017-2019 NXP.
+ *
+ * Peng Fan 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
+#define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
+
+#define GNRL_CTL   0x0
+#define DIV_CTL0x4
+#define LOCK_STATUSBIT(31)
+#define LOCK_SEL_MASK  BIT(29)
+#define CLKE_MASK  BIT(11)
+#define RST_MASK   BIT(9)
+#define BYPASS_MASKBIT(4)
+#define MDIV_SHIFT 12
+#define MDIV_MASK  GENMASK(21, 12)
+#define PDIV_SHIFT 4
+#define PDIV_MASK  GENMASK(9, 4)
+#define SDIV_SHIFT 0
+#define SDIV_MASK  GENMASK(2, 0)
+#define KDIV_SHIFT 0
+#define KDIV_MASK  GENMASK(15, 0)
+
+#define LOCK_TIMEOUT_US1
+
+struct clk_pll14xx {
+   struct clk  clk;
+   void __iomem*base;
+   enum imx_pll14xx_type   type;
+   const struct imx_pll14xx_rate_table *rate_table;
+   int rate_count;
+};
+
+#define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
+
+static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
+   struct clk_pll14xx *pll, unsigned long rate)
+{
+   const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
+   int i;
+
+   for (i = 0; i < pll->rate_count; i++)
+   if (rate == rate_table[i].rate)
+   return &rate_table[i];
+
+   return NULL;
+}
+
+static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
+{
+   struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
+   u64 fvco = clk_get_parent_rate(clk);
+   u32 mdiv, pdiv, sdiv, pll_div;
+
+   pll_div = readl(pll->base + 4);
+   mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
+   pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
+   sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
+
+   fvco *= mdiv;
+   do_div(fvco, pdiv << sdiv);
+
+   return fvco;
+}
+
+static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
+{
+   struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
+   u64 fvco = clk_get_parent_rate(clk);
+   u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
+   short int kdiv;
+
+   pll_div_ctl0 = readl(pll->base + 4);
+   pll_div_ctl1 = readl(pll->base + 8);
+   mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
+   pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
+   sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
+   kdiv = pll_div_ctl1 & KDIV_MASK;
+
+   /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
+   fvco *= (mdiv * 65536 + kdiv);
+   pdiv *= 65536;
+
+   do_div(fvco, pdiv << sdiv);
+
+   return fvco;
+}
+
+static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table 
*rate,
+ u32 pll_div)
+{
+   u32 old_mdiv, old_pdiv;
+
+   old_mdiv = (pll_div >> MDIV_SHIFT) & MDIV_MASK;
+   old_pdiv = (pll_div >> PDIV_SHIFT) & PDIV_MASK;
+
+   return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
+}
+
+static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table 
*rate,
+  u32 pll_div_ctl0, u32 pll_div_ctl1)
+{
+   u32 old_mdiv, old_pdiv, old_kdiv;
+
+   old_mdiv = (pll_div_ctl0 >> MDIV_SHIFT) & MDIV_MASK;
+   old_pdiv = (pll_div_ctl0 >> PDIV_SHIFT) & PDIV_MASK;
+   old_kdiv = (pll_div_ctl1 >> KDIV_SHIFT) & KDIV_MASK;
+
+   return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
+   rate->kdiv != old_kdiv;
+}
+
+static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table 
*rate,
+ u32 pll_div_ctl0, u32 pll_div_ctl1)
+{
+   u32 old_mdiv, old_pdiv, old_kdiv;
+
+   old_mdiv = (pll_div_ctl0 >> MDIV_SHIFT) & MDIV_MASK;
+   old_pdiv = (pll_div_ctl0 >> PDIV_SHIFT) & PDIV_MASK;
+   old_kdiv = (pll_div_ctl1 >> KDIV_SHIFT) & KDIV_MASK;
+
+   return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
+   rate->kdiv != old_kdiv;
+}
+
+static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
+{
+   u32 val;
+
+   return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US,
+   LOCK_TIMEOUT_US);
+}
+
+static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)
+{
+   struct clk_pll14xx *pll = to_cl

[U-Boot] [PATCH 4/4] clk: imx: add i.MX8MM clk driver

[Peng Fan]

Add i.MX8MM clk driver support.

Signed-off-by: Peng Fan 
---
 drivers/clk/imx/Makefile |   2 +
 drivers/clk/imx/clk-imx8mm.c | 414 +++
 2 files changed, 416 insertions(+)
 create mode 100644 drivers/clk/imx/clk-imx8mm.c

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 105a58ca90..5ad7967fe9 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -10,3 +10,5 @@ ifdef CONFIG_CLK_IMX8
 obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
 obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
 endif
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
+   clk-composite-8m.o
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
new file mode 100644
index 00..9459d8ab8e
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Peng Fan 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s)  \
+   {   \
+   .rate   =   (_rate),\
+   .mdiv   =   (_m),   \
+   .pdiv   =   (_p),   \
+   .sdiv   =   (_s),   \
+   }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)  \
+   {   \
+   .rate   =   (_rate),\
+   .mdiv   =   (_m),   \
+   .pdiv   =   (_p),   \
+   .sdiv   =   (_s),   \
+   .kdiv   =   (_k),   \
+   }
+
+static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
+   PLL_1416X_RATE(18U, 225, 3, 0),
+   PLL_1416X_RATE(16U, 200, 3, 0),
+   PLL_1416X_RATE(12U, 300, 3, 1),
+   PLL_1416X_RATE(10U, 250, 3, 1),
+   PLL_1416X_RATE(8U,  200, 3, 1),
+   PLL_1416X_RATE(75000U,  250, 2, 2),
+   PLL_1416X_RATE(7U,  350, 3, 2),
+   PLL_1416X_RATE(6U,  300, 3, 2),
+};
+
+static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
+   PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+};
+
+static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
+   .type = PLL_1443X,
+   .rate_table = imx8mm_drampll_tbl,
+   .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
+   .type = PLL_1416X,
+   .rate_table = imx8mm_pll1416x_tbl,
+   .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
+   .type = PLL_1416X,
+   .rate_table = imx8mm_pll1416x_tbl,
+   .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
+};
+
+static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", 
"dummy", };
+static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
+static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
+static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
+static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
+
+static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", 
"sys_pll2_500m", "sys_pll2_1000m",
+   "sys_pll1_800m", "sys_pll1_400m", 
"audio_pll1_out", "sys_pll3_out", };
+
+static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", 
"sys_pll1_800m", "sys_pll1_400m",
+   "sys_pll2_125m", "sys_pll3_out", 
"audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", 
"sys_pll1_800m", "sys_pll2_250m",
+"sys_pll2_200m", "audio_pll1_out", 
"video_pll1_out", "sys_pll3_out", };
+
+static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", 
"sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
+  "sys_pll1_133m", "sys_pll3_out", 
"sys_pll2_250m", "audio_pll1_out", };
+
+static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll1_800m", "sys_pll2_500m",
+  "sys_pll3_out", "sys_pll1_266m", 
"audio_pll2_out", "sys_pll1_100m", };
+
+static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll1_800m", "sys_pll2_500m",
+  "sys_pll3_out", "sys_pll1_266m", 
"audio_pll2_out", "sys_pll1_100m", };
+
+static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m",

[U-Boot] [PATCH 1/4] clk: imx: add Kconfig entry for i.MX8MM

[Peng Fan]

Add Kconfig entry for i.MX8MM

Signed-off-by: Peng Fan 
---
 drivers/clk/Kconfig |  4 ++--
 drivers/clk/imx/Kconfig | 16 
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index a3f0171b45..fce595b4b3 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -48,7 +48,7 @@ config CLK_BOSTON
 
 config SPL_CLK_CCF
bool "SPL Common Clock Framework [CCF] support "
-   depends on SPL_CLK_IMX6Q
+   depends on SPL_CLK_IMX6Q || ARCH_IMX8M
help
  Enable this option if you want to (re-)use the Linux kernel's Common
  Clock Framework [CCF] code in U-Boot's SPL.
@@ -62,7 +62,7 @@ config SPL_CLK_COMPOSITE_CCF
 
 config CLK_CCF
bool "Common Clock Framework [CCF] support "
-   depends on CLK_IMX6Q || SANDBOX_CLK_CCF
+   depends on CLK_IMX6Q || ARCH_IMX8M || SANDBOX_CLK_CCF
help
  Enable this option if you want to (re-)use the Linux kernel's Common
  Clock Framework [CCF] code in U-Boot's clock driver.
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 3e6a980c8c..aae69cf9b0 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -20,3 +20,19 @@ config CLK_IMX8
select CLK
help
  This enables support clock driver for i.MX8 platforms.
+
+config SPL_CLK_IMX8MM
+   bool "SPL clock support for i.MX8MM"
+   depends on ARCH_IMX8M && SPL
+   select SPL_CLK
+   select SPL_CLK_CCF
+   help
+ This enables SPL DM/DTS support for clock driver in i.MX8MM
+
+config CLK_IMX8MM
+   bool "Clock support for i.MX8MM"
+   depends on ARCH_IMX8M
+   select CLK
+   select CLK_CCF
+   help
+ This enables support clock driver for i.MX8MM platforms.
-- 
2.16.4

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[U-Boot] [PATCH 3/4] clk: imx: add i.MX8M composite clk support

[Peng Fan]

Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2

Signed-off-by: Peng Fan 
---
 drivers/clk/imx/clk-composite-8m.c | 170 +
 1 file changed, 170 insertions(+)
 create mode 100644 drivers/clk/imx/clk-composite-8m.c

diff --git a/drivers/clk/imx/clk-composite-8m.c 
b/drivers/clk/imx/clk-composite-8m.c
new file mode 100644
index 00..57ebbc3bb0
--- /dev/null
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_COMPOSITE "imx_clk_composite"
+
+#define PCG_PREDIV_SHIFT   16
+#define PCG_PREDIV_WIDTH   3
+#define PCG_PREDIV_MAX 8
+
+#define PCG_DIV_SHIFT  0
+#define PCG_DIV_WIDTH  6
+#define PCG_DIV_MAX64
+
+#define PCG_PCS_SHIFT  24
+#define PCG_PCS_MASK   0x7
+
+#define PCG_CGC_SHIFT  28
+
+static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk)
+{
+   struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
+   struct clk_composite *composite = (struct clk_composite *)clk->data;
+   ulong parent_rate = clk_get_parent_rate(&composite->clk);
+   unsigned long prediv_rate;
+   unsigned int prediv_value;
+   unsigned int div_value;
+
+   debug("%s: name %s prate: %lu reg: %p\n", __func__,
+ (&composite->clk)->dev->name, parent_rate, divider->reg);
+   prediv_value = readl(divider->reg) >> divider->shift;
+   prediv_value &= clk_div_mask(divider->width);
+
+   prediv_rate = divider_recalc_rate(clk, parent_rate, prediv_value,
+ NULL, divider->flags,
+ divider->width);
+
+   div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
+   div_value &= clk_div_mask(PCG_DIV_WIDTH);
+
+   return divider_recalc_rate(clk, prediv_rate, div_value, NULL,
+  divider->flags, PCG_DIV_WIDTH);
+}
+
+static int imx8m_clk_composite_compute_dividers(unsigned long rate,
+   unsigned long parent_rate,
+   int *prediv, int *postdiv)
+{
+   int div1, div2;
+   int error = INT_MAX;
+   int ret = -EINVAL;
+
+   *prediv = 1;
+   *postdiv = 1;
+
+   for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
+   for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
+   int new_error = ((parent_rate / div1) / div2) - rate;
+
+   if (abs(new_error) < abs(error)) {
+   *prediv = div1;
+   *postdiv = div2;
+   error = new_error;
+   ret = 0;
+   }
+   }
+   }
+   return ret;
+}
+
+/*
+ * The clk are not binded to a dev, because it is part of composite clk
+ * use composite clk to get dev
+ */
+static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk,
+ unsigned long rate)
+{
+   struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
+   struct clk_composite *composite = (struct clk_composite *)clk->data;
+   ulong parent_rate = clk_get_parent_rate(&composite->clk);
+   int prediv_value;
+   int div_value;
+   int ret;
+   u32 val;
+
+   ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
+  &prediv_value, &div_value);
+   if (ret)
+   return -EINVAL;
+
+   val = readl(divider->reg);
+   val &= ~((clk_div_mask(divider->width) << divider->shift) |
+   (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
+
+   val |= (u32)(prediv_value  - 1) << divider->shift;
+   val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
+   writel(val, divider->reg);
+
+   return clk_get_rate(&composite->clk);
+}
+
+static const struct clk_ops imx8m_clk_composite_divider_ops = {
+   .get_rate = imx8m_clk_composite_divider_recalc_rate,
+   .set_rate = imx8m_clk_composite_divider_set_rate,
+};
+
+struct clk *imx8m_clk_composite_flags(const char *name,
+ const char * const *parent_names,
+ int num_parents, void __iomem *reg,
+ unsigned long flags)
+{
+   struct clk *clk = ERR_PTR(-ENOMEM);
+   struct clk_divider *div = NULL;
+   struct clk_gate *gate = NULL;
+   struct clk_mux *mux = NULL;
+
+   mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+   if (!mux)
+   goto fail;
+
+   mux->reg = reg;
+   mux->shift = PCG_PCS_SHIFT;
+   mux->mask = PCG_PCS_MASK;
+   mux->num_parents = num_parents;
+   mux-

[U-Boot] [PATCH 0/4] Prepare i.MX8MM clk

[Peng Fan]

This is to support i.MX8MM clk driver.
i.MX8MM use similar clock design as i.MX7D, but it has
use different PLL, so we need to add pll14xx driver.
And to simplify the clock usage, import the composite clk
driver from Linux Kernel, then we could have simple clk tree.

This is to split the previous patchset
https://github.com/MrVan/u-boot/commits/imx8mmn-ccf
for i.MX8MM/N support

There are some checkpatch warnings that not addressed, because
import from Linux Kernel.

Peng Fan (4):
  clk: imx: add Kconfig entry for i.MX8MM
  clk: imx: add pll14xx driver
  clk: imx: add i.MX8M composite clk support
  clk: imx: add i.MX8MM clk driver

 drivers/clk/Kconfig|   4 +-
 drivers/clk/imx/Kconfig|  16 ++
 drivers/clk/imx/Makefile   |   2 +
 drivers/clk/imx/clk-composite-8m.c | 170 +++
 drivers/clk/imx/clk-imx8mm.c   | 414 +
 drivers/clk/imx/clk-pll14xx.c  | 371 +
 drivers/clk/imx/clk.h  |  25 +++
 7 files changed, 1000 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/imx/clk-composite-8m.c
 create mode 100644 drivers/clk/imx/clk-imx8mm.c
 create mode 100644 drivers/clk/imx/clk-pll14xx.c

-- 
2.16.4

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Re: [U-Boot] [RESEND PATCH v2 06/15] arm: socfpga: agilex: Add system manager support

[Ley Foon Tan]

On Fri, Jul 12, 2019 at 6:50 PM Simon Goldschmidt
 wrote:
>
> On Thu, Jul 11, 2019 at 12:56 AM Ley Foon Tan  wrote:
> >
> > On Tue, Jul 9, 2019 at 1:09 PM Simon Goldschmidt
> >  wrote:
> > >
> > > Am 04.07.2019 um 10:56 schrieb Ley Foon Tan:
> > > > Add system manager support for Agilex.
> > > >
> > > > Signed-off-by: Ley Foon Tan 
> > > >
> > > > ---
> > > > v2:
> > > > - Include system_manager_s10_agilex_common.h in system_manager_agilex.h
> > > > ---
> > > >   .../include/mach/system_manager.h |   2 +
> > > >   .../include/mach/system_manager_agilex.h  | 129 ++
> > > >   .../mach/system_manager_s10_agilex_common.h   |   3 +-
> > > >   3 files changed, 133 insertions(+), 1 deletion(-)
> > > >   create mode 100644 
> > > > arch/arm/mach-socfpga/include/mach/system_manager_agilex.h
> > >
> > > See my reply to 05/15: I'd strongly suggest to come up with a name for
> > > S10/Agilex common things. Because seeing how much these have in common,
> > > it seems like people at Altera/Intel are so satisfied with that design
> > > that it could stay with us for some hardware-releases to come...
> > >
> > > >
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
> > > > b/arch/arm/mach-socfpga/include/mach/system_manager.h
> > > > index 7e76df74b7..79e3777e39 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/system_manager.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
> > > > @@ -8,6 +8,8 @@
> > > >
> > > >   #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > > >   #include 
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
> > > > +#include 
> > > >   #else
> > > >   #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
> > > >   #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h 
> > > > b/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h
> > > > new file mode 100644
> > > > index 00..e84eed9754
> > > > --- /dev/null
> > > > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h
> > > > @@ -0,0 +1,129 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0 */
> > > > +/*
> > > > + * Copyright (C) 2019 Intel Corporation 
> > > > + */
> > > > +
> > > > +#ifndef  _SYSTEM_MANAGER_AGILEX_
> > > > +#define  _SYSTEM_MANAGER_AGILEX_
> > > > +
> > > > +struct socfpga_system_manager {
> > >
> > > And here, see my reply to 03/15: why do we need a complete different
> > > struct here? It seems like only some of the struct members change
> > > between S10 and Agilex?
> > Yes, some of registers are different between Stratix 10 and Agilex.
> > We need add some #ifdef in struct if want share between them. But,
> > this will make code hard to read too. Unless we want convert struct to
> > #define offset.
> >
> > What is your preferable way?
>
> That depends. I think here, you're using only some registers of a rather big
> struct. Plus the registers you actually use are same for Stratix10 and Agilex.
> If my analysis is correct, I think here, defines would be better than structs.
Yes, you are correct. Will try to convert to defines, but this involve
many files change.

Regards
Ley Foon

>
> >
> > Regards
> > Ley Foon
> > >
> > > > + /* System Manager Module */
> > > > + u32 siliconid1; /* 0x00 */
> > > > + u32 siliconid2;
> > > > + u32 wddbg;
> > > > + u32 _pad_0xc;
> > > > + u32 mpu_status; /* 0x10 */
> > > > + u32 mpu_ace;
> > > > + u32 _pad_0x18_0x1c[2];
> > > > + u32 dma;/* 0x20 */
> > > > + u32 dma_periph;
> > > > + /* SDMMC Controller Group */
> > > > + u32 sdmmcgrp_ctrl;
> > > > + u32 sdmmcgrp_l3master;
> > > > + /* NAND Flash Controller Register Group */
> > > > + u32 nandgrp_bootstrap;  /* 0x30 */
> > > > + u32 nandgrp_l3master;
> > > > + /* USB Controller Group */
> > > > + u32 usb0_l3master;
> > > > + u32 usb1_l3master;
> > > > + /* EMAC Group */
> > > > + u32 emac_gbl;   /* 0x40 */
> > > > + u32 emac0;
> > > > + u32 emac1;
> > > > + u32 emac2;
> > > > + u32 emac0_ace;  /* 0x50 */
> > > > + u32 emac1_ace;
> > > > + u32 emac2_ace;
> > > > + u32 nand_axuser;
> > > > + u32 _pad_0x60_0x64[2];  /* 0x60 */
> > > > + /* FPGA interface Group */
> > > > + u32 fpgaintf_en_1;
> > > > + u32 fpgaintf_en_2;
> > > > + u32 fpgaintf_en_3;  /* 0x70 */
> > > > + u32 dma_l3master;
> > > > + u32 etr_l3master;
> > > > + u32 _pad_0x7c;
> > > > + u32 sec_ctrl_slt;   /* 0x80 */
> > > > + u32 osc_trim;
> > > > + u32 _pad_0x88_0x8c[2];
> > > > + /* ECC Group */
> > > > + u32 ecc_intmask_value;   

Re: [U-Boot] [RESEND PATCH v2 07/15] clk: agilex: Add clock driver for Agilex.

[Ley Foon Tan]

On Fri, Jul 12, 2019 at 6:47 PM Simon Goldschmidt
 wrote:
>
> On Thu, Jul 11, 2019 at 1:03 AM Ley Foon Tan  wrote:
> >
> > On Tue, Jul 9, 2019 at 1:13 PM Simon Goldschmidt
> >  wrote:
> > >
> > > Am 04.07.2019 um 10:56 schrieb Ley Foon Tan:
> > > > Add clock manager driver for Agilex. Provides clock initialization
> > > > and get_rate functions.
> > >
> > > Thanks for adding this to the patchset. This is quite a big change, I
> > > don't have the time currently to review it. Just a question to the
> > > message above: does 'clock' initialization mean it reads the
> > > initialization values from devicetree instead of reading them from qts
> > > header files? If so, is the code better integrated then the A10 code?
> > For S10 and Agilex, the initialization values is from handoff in FPGA
> > image, not from device tree as A10.
> > It is much simpler than A10 implementation.
> > >
> > > And further asked, if this works for Agilex, and you added
> > > "stratix10-clock.h", does this work for S10, too?
> > Actually "stratix10-clock.h" is from Linux tree,
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/stratix10-clock.h
> > I can add Linux commit ID in commit message.
>
> You already did that. My question was: does this clock driver work for
> Stratix10, too, given the name of the file you imported?
>
Clock manager for Stratix10 and Agilex are different.
But, include/dt-bindings/clock/stratix10-clock.h can use for both
Stratix10 and Agilex.
stratix10-clock.h contains SW define index for each clock, so it is
not depend on HW.

Regards
Ley Foon
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Re: [U-Boot] EFI_PXE_BASE_CODE_PROTOCOL

[Leif Lindholm]

+Peter Jones (sorry Peter)

On Tue, Aug 06, 2019 at 08:34:58AM +0200, Heinrich Schuchardt wrote:
> iPXE uses the EFI simple network protocol to execute DHCP.

OK.

> Can GRUB already do the same when the EFI_PXE_BASE_CODE_PROTOCOL is not
> present?

Yes. As of very recently (proper* DHCP support was only merged in
March 2019, so is included in 2.04 release, prior to that it
technically performed BOOTP).

SNP means you do your own networking - it gives you access to the raw
(usually) Ethernet packets.

* proper as in "it now conceptually does the correct thing", not as in
  "I have extensively tested this".

> What I do not understand about GRUB's grub_net_configure_by_dhcp_ack()
> is that it silently assumes IPv4 being used without even checking. This
> contradicts the definition of the PXE base code protocol in the UEFI
> standard:

Well, it would not surprise me if this function predates GRUB's UEFI
support.

It actually gets even slightly messier when you look at what GRUB does
when netbooting itself; it starts out using MNP (and hence IP
addresses assigned by UEFI) to load its modules, switching to SNP once
it loads efinet.mod.

> EFI_PXE_BASE_CODE_PACKET DhcpAck is a union:
> 
> typedef union {
>  UINT8 Raw[1472];
>  EFI_PXE_BASE_CODE_DHCPV4_PACKET   Dhcpv4;
>  EFI_PXE_BASE_CODE_DHCPV6_PACKET   Dhcpv6;
> } EFI_PXE_BASE_CODE_PACKET;
> 
> Should the check be done in grub_efi_net_config_real()?

Possibly. I've cc:d Peter since he's the last person I know who took a
proper look at this.

Certainly, it would be useful if you could raise a bug on Savannah on
the ipv4 assumption.

Best Regards,

Leif
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Re: [U-Boot] [PATCH u-boot-marvell 1/1] arm: mvebu: turris_omnia: update defconfig

[Stefan Roese]

On 16.07.19 15:50, Marek Behún wrote:

Add Macronis SPI flash support - some Omnia routers are shipped with
this SPI flash chip.
Also add the memtest command to defconfig.

Signed-off-by: Marek Behún 


Reviewed-by: Stefan Roese 

Thanks,
Stefan
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[U-Boot] [PATCH] board: amlogic: document alternative libretech-cc installation methods

[Daniel Drake]

As already documented in this README, several binaries must be
glued together in order to boot the device.

Extend the documentation to cover the prebuilt binaries
(saving you the hassle of installing ancient cross-compilers),
and also mention the open source replacements for the encryption
tool (which is especially useful if you want to avoid requiring
32-bit x86 binaries in your build system).

Signed-off-by: Daniel Drake 
Cc: Neil Armstrong 
---
 board/amlogic/p212/README.libretech-cc | 41 +++---
 1 file changed, 37 insertions(+), 4 deletions(-)

diff --git a/board/amlogic/p212/README.libretech-cc 
b/board/amlogic/p212/README.libretech-cc
index d007f58764..6af7de3cfa 100644
--- a/board/amlogic/p212/README.libretech-cc
+++ b/board/amlogic/p212/README.libretech-cc
@@ -38,9 +38,28 @@ U-Boot compilation
 Image creation
 ==
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+To boot the system, u-boot must be combined with several earlier stage
+bootloaders:
+
+* bl2.bin: vendor-provided binary blob
+* bl21.bin: built from vendor u-boot source
+* bl30.bin: vendor-provided binary blob
+* bl301.bin: built from vendor u-boot source
+* bl31.bin: vendor-provided binary blob
+* acs.bin: built from vendor u-boot source
+
+These binaries and the tools required below have been collected and prebuilt
+for convenience at 
+
+Download and extract the libretech-cc release from there, and set FIPDIR to
+point to the `fip` subdirectory.
+
+ > export FIPDIR=/path/to/extracted/fip
+
+Alternatively, you can obtain the original vendor u-boot tree which
+contains the required blobs and sources, and build yourself.
+Note that old compilers are required for this to build. The compilers here
+are suggested by Amlogic, and they are 32-bit x86 binaries.
 
  > wget 
https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
  > wget 
https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
@@ -53,7 +72,10 @@ the git tree published by the board vendor:
  > make
  > export FIPDIR=$PWD/fip
 
-Go back to mainline U-Boot source tree then :
+Once you have the binaries available (either through the prebuilt download,
+or having built the vendor u-boot yourself), you can then proceed to glue
+everything together. Go back to mainline U-Boot source tree then :
+
  > mkdir fip
 
  > cp $FIPDIR/gxl/bl2.bin fip/
@@ -100,3 +122,14 @@ and then write the image to SD with:
  > DEV=/dev/your_sd_device
  > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
  > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+
+Note that Amlogic provides aml_encrypt_gxl as a 32-bit x86 binary with no
+source code. Should you prefer to avoid that, there are open source reverse
+engineered versions available:
+
+1. gxlimg , which comes with a handy
+   Makefile that automates the whole process.
+2. meson-tools 
+
+However, these community-developed alternatives are not endorsed by or
+supported by Amlogic.
-- 
2.20.1

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