Re: [PATCH v3 10/13] arm: dts: am335x: add 'u-boot,dm-pre-reloc' to panel
On 22.02.20 14:05, Dario Binacchi wrote: Add the "u-boot,dm-pre-reloc" property to the "ti,tilcdc,panel" compatible node. In this way the video-uclass module can allocate the amount of memory needed to be assigned to the frame buffer. For boards that support Linux the property is added to the *-u-boot.dtsi file since it is a u-boot specific dt flag. Ran building tests with CONFIG_AM335X_LCD enabled and disabled for the following configurations: - brxre1_defconfig --> success - am335x_guardian_defconfig --> success - am335x_evm_defconfig --> success - da850evm_defconfig --> failure with CONFIG_AM335X_LCD enabled Enabling CONFIG_AM335X_LCD in da850evm_defconfig causes building errors even without applying the patch. The driver has never been enabled on the da850 and must be adapted for this platform. Signed-off-by: Dario Binacchi Tested-by: Dario Binacchi Reviewed-by: Felix Brack -- Felix
[PATCH v3 10/13] arm: dts: am335x: add 'u-boot, dm-pre-reloc' to panel
Add the "u-boot,dm-pre-reloc" property to the "ti,tilcdc,panel"
compatible node. In this way the video-uclass module can allocate the
amount of memory needed to be assigned to the frame buffer.
For boards that support Linux the property is added to the *-u-boot.dtsi
file since it is a u-boot specific dt flag.
Ran building tests with CONFIG_AM335X_LCD enabled and disabled for the
following configurations:
- brxre1_defconfig --> success
- am335x_guardian_defconfig --> success
- am335x_evm_defconfig --> success
- da850evm_defconfig --> failure with CONFIG_AM335X_LCD enabled
Enabling CONFIG_AM335X_LCD in da850evm_defconfig causes building errors
even without applying the patch. The driver has never been enabled on the
da850 and must be adapted for this platform.
Signed-off-by: Dario Binacchi
Tested-by: Dario Binacchi
---
Changes in v3:
- Add panel to the root node so that the dts linux file of the board
does not need to be updated.
Changes in v2:
- Change subject line in: arm: dts: am335x:
- Move 'u-boot,dm-pre-reloc' property in *-u-boot.dtsi files for
boards tha support Linux
arch/arm/dts/am335x-brppt1-mmc.dts | 2 ++
arch/arm/dts/am335x-brppt1-nand.dts | 2 ++
arch/arm/dts/am335x-brppt1-spi.dts | 2 ++
arch/arm/dts/am335x-brsmarc1.dts | 1 +
arch/arm/dts/am335x-brxre1.dts | 2 ++
arch/arm/dts/am335x-evm-u-boot.dtsi | 6 ++
arch/arm/dts/am335x-evmsk-u-boot.dtsi| 12
arch/arm/dts/am335x-guardian-u-boot.dtsi | 4
arch/arm/dts/am335x-pdu001-u-boot.dtsi | 4
arch/arm/dts/am335x-pxm50-u-boot.dtsi| 12
arch/arm/dts/am335x-rut-u-boot.dtsi | 12
arch/arm/dts/da850-evm-u-boot.dtsi | 4
12 files changed, 63 insertions(+)
create mode 100644 arch/arm/dts/am335x-evmsk-u-boot.dtsi
create mode 100644 arch/arm/dts/am335x-pxm50-u-boot.dtsi
create mode 100644 arch/arm/dts/am335x-rut-u-boot.dtsi
diff --git a/arch/arm/dts/am335x-brppt1-mmc.dts
b/arch/arm/dts/am335x-brppt1-mmc.dts
index 9be34d9da0..6f919711f0 100644
--- a/arch/arm/dts/am335x-brppt1-mmc.dts
+++ b/arch/arm/dts/am335x-brppt1-mmc.dts
@@ -53,6 +53,8 @@
bkl-pwm = <>;
bkl-tps = <_bl>;
+ u-boot,dm-pre-reloc;
+
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
diff --git a/arch/arm/dts/am335x-brppt1-nand.dts
b/arch/arm/dts/am335x-brppt1-nand.dts
index 11bd5c551c..9d4340f591 100644
--- a/arch/arm/dts/am335x-brppt1-nand.dts
+++ b/arch/arm/dts/am335x-brppt1-nand.dts
@@ -53,6 +53,8 @@
bkl-pwm = <>;
bkl-tps = <_bl>;
+ u-boot,dm-pre-reloc;
+
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
diff --git a/arch/arm/dts/am335x-brppt1-spi.dts
b/arch/arm/dts/am335x-brppt1-spi.dts
index 01ab74be5e..c078af8fba 100644
--- a/arch/arm/dts/am335x-brppt1-spi.dts
+++ b/arch/arm/dts/am335x-brppt1-spi.dts
@@ -54,6 +54,8 @@
bkl-pwm = <>;
bkl-tps = <_bl>;
+ u-boot,dm-pre-reloc;
+
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
diff --git a/arch/arm/dts/am335x-brsmarc1.dts b/arch/arm/dts/am335x-brsmarc1.dts
index a63fc2da22..7e9516e8f8 100644
--- a/arch/arm/dts/am335x-brsmarc1.dts
+++ b/arch/arm/dts/am335x-brsmarc1.dts
@@ -59,6 +59,7 @@
/*backlight = <_bl>; */
compatible = "ti,tilcdc,panel";
status = "okay";
+ u-boot,dm-pre-reloc;
panel-info {
ac-bias = <255>;
diff --git a/arch/arm/dts/am335x-brxre1.dts b/arch/arm/dts/am335x-brxre1.dts
index 33d8ab78d8..6091a12fb7 100644
--- a/arch/arm/dts/am335x-brxre1.dts
+++ b/arch/arm/dts/am335x-brxre1.dts
@@ -79,6 +79,8 @@
backlight = <_bl>;
+ u-boot,dm-pre-reloc;
+
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi
b/arch/arm/dts/am335x-evm-u-boot.dtsi
index b6b97ed16d..d7b049ef20 100644
--- a/arch/arm/dts/am335x-evm-u-boot.dtsi
+++ b/arch/arm/dts/am335x-evm-u-boot.dtsi
@@ -3,6 +3,12 @@
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*/
+/ {
+ panel {
+ u-boot,dm-pre-reloc;
+ };
+};
+
{
status = "disabled";
diff --git a/arch/arm/dts/am335x-evmsk-u-boot.dtsi
b/arch/arm/dts/am335x-evmsk-u-boot.dtsi
new file mode 100644
index 00..599fb377e6
--- /dev/null
+++ b/arch/arm/dts/am335x-evmsk-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am335x-evmsk U-Boot Additions
+ *
+ * Copyright (C) 2020 Dario Binacchi
+ */
+
+/ {
+ panel {
+
[PATCH v3 13/13] board: brxre1: fix building errors
Fix building errors if CONFIG_DM_VIDEO is enabled. This is the only u-boot board that enables CONFIG_AM335X_LCD and from which I started to develop the version of the frame buffer driver that supports the driver model. Signed-off-by: Dario Binacchi --- Changes in v3: None Changes in v2: None board/BuR/common/br_resetc.c | 2 +- board/BuR/common/bur_common.h | 3 +++ board/BuR/common/common.c | 2 +- include/configs/brxre1.h | 2 ++ 4 files changed, 7 insertions(+), 2 deletions(-) diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c index c0e7fb65b2..70ad8322ef 100644 --- a/board/BuR/common/br_resetc.c +++ b/board/BuR/common/br_resetc.c @@ -22,7 +22,7 @@ #define BMODE_PME 12 #define BMODE_DIAG 15 -#ifdef CONFIG_LCD +#if CONFIG_IS_ENABLED(LCD) && !CONFIG_IS_ENABLED(DM_VIDEO) #include #define LCD_SETCURSOR(x, y)lcd_position_cursor(x, y) #define LCD_PUTS(x)lcd_puts(x) diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h index 2591bf4bb3..618cebc1a5 100644 --- a/board/BuR/common/bur_common.h +++ b/board/BuR/common/bur_common.h @@ -11,9 +11,12 @@ #ifndef _BUR_COMMON_H_ #define _BUR_COMMON_H_ +#if !CONFIG_IS_ENABLED(DM_VIDEO) #include <../../../drivers/video/am335x-fb.h> int load_lcdtiming(struct am335x_lcdpanel *panel); +#endif + void br_summaryscreen(void); void pmicsetup(u32 mpupll, unsigned int bus); void enable_uart0_pin_mux(void); diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 148fc9075e..de8d455c27 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; /* --*/ #if defined(CONFIG_LCD) && defined(CONFIG_AM335X_LCD) && \ - !defined(CONFIG_SPL_BUILD) + !defined(CONFIG_DM_VIDEO) && !defined(CONFIG_SPL_BUILD) #include #include #include diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index ea15912c90..006663373b 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -14,7 +14,9 @@ #include #include /* - */ +#if !defined(CONFIG_AM335X_LCD) #define CONFIG_AM335X_LCD +#endif #define LCD_BPPLCD_COLOR32 /* memory */ -- 2.17.1
Re: [RFC PATCH 00/10] arm: add support for SoC S5P4418
Hi, On Tue, Feb 4, 2020 at 1:12 AM Stefan Bosch wrote: > > > This patch adds support for SAMSUNG's/NEXELL's ARM Cortex-A9 based > S5P4418 SoC, especially FriendlyARM's NanoPi2 and NanoPC-T2 boards. > It is based on the following FriendlyARM's U-Boot version: > https://github.com/friendlyarm/u-boot/tree/nanopi2-v2016.01. > I don't think this is the right approach, i.e. to take everything from BSP source as it is and put it into mainline U-BOOT. AFAIR, Some of the peripherals present on these NEXELL SoC's are compatible with SAMSUNG IP (for instance the UART). So, are we sure that some of the already existing code in U-BOOT can't be re-used to drive those compatible peripherals at-least ? Thanks -Amit
[PATCH v3 09/13] video: omap: add support for DM/DTS
Update the driver to support the device tree and the driver model.
Timings and panel parameters are now loaded from the device tree.
The DM code replaces the am335x_lcdpanel structure with
tilcdc_panel_info taken from the linux kernel, as well the management
of additional parameters not covered in the legacy code. In addition,
the am335x_lcdpanel structure contains parameters and operations that
were probably a requirement of the board for which this driver was
developed and which, however, were not developed in the linux kernel.
All this led to rewrite th DM controller initialization code, except
for the pixel clock setting that is executed in a function created in a
previous patch with code taken from the legacy am335xfb_init.
The patch has been tested on a custom board with u-boot 2018.11-rc2 and
the following device-tree configuration:
panel {
compatible = "ti,tilcdc,panel";
pinctrl-names = "default";
pinctrl-0 = <_enable_pins>;
enable-gpios = < 31 0>;
backlight = <>;
status = "okay";
u-boot,dm-pre-reloc;
panel-info {
ac-bias = <255>;
ac-bias-intrpt= <0>;
dma-burst-sz = <16>;
bpp = <16>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
native-mode = <>;
timing0: 800x480 {
hactive = <800>;
vactive = <480>;
hback-porch = <46>;
hfront-porch= <210>;
hsync-len = <20>;
vback-porch = <23>;
vfront-porch= <22>;
vsync-len = <10>;
clock-frequency = <3300>;
hsync-active= <0>;
vsync-active= <0>;
};
};
};
Signed-off-by: Dario Binacchi
Tested-by: Dario Binacchi
---
Changes in v3: None
Changes in v2:
- Move clock enabling sequence to arch/arm/mach-omap2/
- Create a Kconfig symbol for CONFIG_AM335X_LCD
arch/arm/mach-omap2/am33xx/clock_am33xx.c | 4 +
drivers/video/Kconfig | 6 +
drivers/video/am335x-fb.c | 337 +-
drivers/video/am335x-fb.h | 4 +
4 files changed, 341 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c
b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
index f2cd496607..2427933c8b 100644
--- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c
+++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
@@ -226,6 +226,10 @@ void enable_basic_clocks(void)
>usb0clkctrl,
>emiffwclkctrl,
>emifclkctrl,
+#if CONFIG_IS_ENABLED(AM335X_LCD)
+ >lcdclkctrl,
+ >lcdcclkstctrl,
+#endif
0
};
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 4c93369702..7c5012a67f 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -473,6 +473,12 @@ config ATMEL_HLCD
help
HLCDC supports video output to an attached LCD panel.
+config AM335X_LCD
+ bool "Enable AM335x video support"
+ depends on DM_VIDEO
+ help
+ Supports video output to an attached LCD panel.
+
config LOGICORE_DP_TX
bool "Enable Logicore DP TX driver"
depends on DISPLAY
diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index c426ff8aec..30543a945b 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -2,6 +2,7 @@
/*
* Copyright (C) 2013-2018 Hannes Schmelzer
* B Industrial Automation GmbH - http://www.br-automation.com
+ * Copyright (C) 2020 Dario Binacchi
*
* minimal framebuffer driver for TI's AM335x SoC to be compatible with
* Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
@@ -11,19 +12,18 @@
* - starts output DMA from gd->fb_base buffer
*/
#include
+#include
#include
#include
#include
#include
#include
+#include
#include
#include
+#include
#include "am335x-fb.h"
-#if !defined(LCD_CNTL_BASE)
-#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
-#endif
-
#define LCDC_FMAX 2
/* LCD Control Register */
@@ -41,6 +41,7 @@
#define LCDC_DMA_CTRL_BURST_4 0x2
#define LCDC_DMA_CTRL_BURST_8 0x3
#define
[PATCH v3 12/13] video: omap: fix pixel-per-line bitfield setting
Fix the macro to set the pplmsb field (bit 3) of the RASTER_TIMING_0 register. It is used in order to support up to 2048 pixels per line. Signed-off-by: Dario Binacchi --- Changes in v3: None Changes in v2: None drivers/video/am335x-fb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c index 30543a945b..eb5add2a20 100644 --- a/drivers/video/am335x-fb.c +++ b/drivers/video/am335x-fb.c @@ -43,7 +43,7 @@ #define LCDC_DMA_CTRL_BURST_16 0x4 #define LCDC_DMA_CTRL_FIFO_TH(x) (((x) & GENMASK(2, 0)) << 8) /* LCD Timing_0 Register */ -#define LCDC_RASTER_TIMING_0_HORMSB(x) (x) >> 4) - 1) & 0x40) >> 4) +#define LCDC_RASTER_TIMING_0_HORMSB(x) x) - 1) & BIT(10)) >> 7) #define LCDC_RASTER_TIMING_0_HORLSB(x) (x) >> 4) - 1) & GENMASK(5, 0)) << 4) #define LCDC_RASTER_TIMING_0_HSWLSB(x) x) - 1) & GENMASK(5, 0)) << 10) #define LCDC_RASTER_TIMING_0_HFPLSB(x) x) - 1) & GENMASK(7, 0)) << 16) -- 2.17.1
[PATCH v3 11/13] fdt: video: omap: add framebuffer and panel bindings
Add device-tree binding documentation for ti framebuffer and generic
panel output driver.
Signed-off-by: Dario Binacchi
Reviewed-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
.../video/tilcdc/panel.txt| 66 +++
.../video/tilcdc/tilcdc.txt | 82 +++
2 files changed, 148 insertions(+)
create mode 100644 doc/device-tree-bindings/video/tilcdc/panel.txt
create mode 100644 doc/device-tree-bindings/video/tilcdc/tilcdc.txt
diff --git a/doc/device-tree-bindings/video/tilcdc/panel.txt
b/doc/device-tree-bindings/video/tilcdc/panel.txt
new file mode 100644
index 00..808216310e
--- /dev/null
+++ b/doc/device-tree-bindings/video/tilcdc/panel.txt
@@ -0,0 +1,66 @@
+Device-Tree bindings for tilcdc DRM generic panel output driver
+
+Required properties:
+ - compatible: value should be "ti,tilcdc,panel".
+ - panel-info: configuration info to configure LCDC correctly for the panel
+ - ac-bias: AC Bias Pin Frequency
+ - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
+ - dma-burst-sz: DMA burst size
+ - bpp: Bits per pixel
+ - fdd: FIFO DMA Request Delay
+ - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
+ - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
+ - raster-order: Raster Data Order Select: 1=Most-to-least 0=Least-to-most
+ - fifo-th: DMA FIFO threshold
+ - display-timings: typical videomode of lcd panel. Multiple video modes
+ can be listed if the panel supports multiple timings, but the 'native-mode'
+ should be the preferred/default resolution. Refer to
+ Documentation/devicetree/bindings/display/panel/display-timing.txt for
display
+ timing binding details.
+
+Optional properties:
+- backlight: phandle of the backlight device attached to the panel
+- enable-gpios: GPIO pin to enable or disable the panel
+
+Recommended properties:
+ - pinctrl-names, pinctrl-0: the pincontrol settings to configure
+ muxing properly for pins that connect to TFP410 device
+
+Example:
+
+ /* Settings for CDTech_S035Q01 / LCD3 cape: */
+ lcd3 {
+ compatible = "ti,tilcdc,panel";
+ pinctrl-names = "default";
+ pinctrl-0 = <_lcd3_cape_lcd_pins>;
+ backlight = <>;
+ enable-gpios = < 19 0>;
+
+ panel-info {
+ ac-bias = <255>;
+ ac-bias-intrpt= <0>;
+ dma-burst-sz = <16>;
+ bpp = <16>;
+ fdd = <0x80>;
+ sync-edge = <0>;
+ sync-ctrl = <1>;
+ raster-order = <0>;
+ fifo-th = <0>;
+ };
+ display-timings {
+ native-mode = <>;
+ timing0: 320x240 {
+ hactive = <320>;
+ vactive = <240>;
+ hback-porch = <21>;
+ hfront-porch= <58>;
+ hsync-len = <47>;
+ vback-porch = <11>;
+ vfront-porch= <23>;
+ vsync-len = <2>;
+ clock-frequency = <800>;
+ hsync-active= <0>;
+ vsync-active= <0>;
+ };
+ };
+ };
diff --git a/doc/device-tree-bindings/video/tilcdc/tilcdc.txt
b/doc/device-tree-bindings/video/tilcdc/tilcdc.txt
new file mode 100644
index 00..7bf1bb4448
--- /dev/null
+++ b/doc/device-tree-bindings/video/tilcdc/tilcdc.txt
@@ -0,0 +1,82 @@
+Device-Tree bindings for tilcdc DRM driver
+
+Required properties:
+ - compatible: value should be one of the following:
+- "ti,am33xx-tilcdc" for AM335x based boards
+- "ti,da850-tilcdc" for DA850/AM18x/OMAP-L138 based boards
+ - interrupts: the interrupt number
+ - reg: base address and size of the LCDC device
+
+Recommended properties:
+ - ti,hwmods: Name of the hwmod associated to the LCDC
+
+Optional properties:
+ - max-bandwidth: The maximum pixels per second that the memory
+ interface / lcd controller combination can sustain
+ - max-width: The maximum horizontal pixel width supported by
+ the lcd controller.
+ - max-pixelclock: The maximum pixel clock that can be supported
+ by the lcd controller in KHz.
+ - blue-and-red-wiring: Recognized values "straight" or "crossed".
+ This property deals with the LCDC revision 2 (found on AM335x)
+ color errata [1].
+- "straight" indicates normal wiring that supports RGB565,
+ BGR888, and XBGR color formats.
+- "crossed" indicates wiring that has blue and red wires
+ crossed. This setup supports BGR565, RGB888 and
[PATCH v3 08/13] video: omap: create two routines to set the pixel clock rate
Created in preparation to support driver-model, they can also be called
from legacy code. In this way, code duplication is avoided.
Signed-off-by: Dario Binacchi
---
Changes in v3: None
Changes in v2:
- Use GENMASK macro for clock divisor mask
drivers/video/am335x-fb.c | 130 --
1 file changed, 97 insertions(+), 33 deletions(-)
diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index 684223f275..c426ff8aec 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#include "am335x-fb.h"
@@ -26,6 +27,7 @@
#define LCDC_FMAX 2
/* LCD Control Register */
+#define LCDC_CTRL_CLK_DIVISOR_MASK GENMASK(15, 8)
#define LCDC_CTRL_RASTER_MODE BIT(0)
#define LCDC_CTRL_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8)
/* LCD Clock Enable Register */
@@ -98,10 +100,95 @@ struct am335x_lcdhw {
unsigned intclkc_reset; /* 0x70 */
};
+struct dpll_data {
+ unsigned long rounded_rate;
+ u16 rounded_m;
+ u8 rounded_n;
+ u8 rounded_div;
+};
+
static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
DECLARE_GLOBAL_DATA_PTR;
+/**
+ * am335x_dpll_round_rate() - Round a target rate for an OMAP DPLL
+ *
+ * @dpll_data: struct dpll_data pointer for the DPLL
+ * @rate: New DPLL clock rate
+ * @return rounded rate and the computed m, n and div values in the dpll_data
+ * structure, or -ve error code.
+ */
+static ulong am335x_dpll_round_rate(struct dpll_data *dd, ulong rate)
+{
+ unsigned int m, n, d;
+ unsigned long rounded_rate;
+ int err, err_r;
+
+ dd->rounded_rate = -EFAULT;
+ err = rate;
+ err_r = err;
+
+ for (d = 2; err && d < 255; d++) {
+ for (m = 2; m < 2047; m++) {
+ if ((V_OSCK * m) < (rate * d))
+ continue;
+
+ n = (V_OSCK * m) / (rate * d);
+ if (n > 127)
+ break;
+
+ if (((V_OSCK * m) / n) > LCDC_FMAX)
+ break;
+
+ rounded_rate = (V_OSCK * m) / n / d;
+ err = abs(rounded_rate - rate);
+ if (err < err_r) {
+ err_r = err;
+ dd->rounded_rate = rounded_rate;
+ dd->rounded_m = m;
+ dd->rounded_n = n;
+ dd->rounded_div = d;
+ if (err == 0)
+ break;
+ }
+ }
+ }
+
+ debug("DPLL display: best error %d Hz (M %d, N %d, DIV %d)\n",
+ err_r, dd->rounded_m, dd->rounded_n, dd->rounded_div);
+
+ return dd->rounded_rate;
+}
+
+/**
+ * am335x_fb_set_pixel_clk_rate() - Set pixel clock rate.
+ *
+ * @am335x_lcdhw: Base address of the LCD controller registers.
+ * @rate: New clock rate in Hz.
+ * @return new rate, or -ve error code.
+ */
+static ulong am335x_fb_set_pixel_clk_rate(struct am335x_lcdhw *regs, ulong
rate)
+{
+ struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 };
+ struct dpll_data dd;
+ ulong round_rate;
+ u32 reg;
+
+ round_rate = am335x_dpll_round_rate(, rate);
+ if (IS_ERR_VALUE(round_rate))
+ return round_rate;
+
+ dpll_disp.m = dd.rounded_m;
+ dpll_disp.n = dd.rounded_n;
+ do_setup_dpll(_disp_regs, _disp);
+
+ reg = readl(>ctrl) & ~LCDC_CTRL_CLK_DIVISOR_MASK;
+ reg |= LCDC_CTRL_CLK_DIVISOR(dd.rounded_div);
+ writel(reg, >ctrl);
+ return round_rate;
+}
+
int lcd_get_size(int *line_length)
{
*line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
@@ -111,11 +198,9 @@ int lcd_get_size(int *line_length)
int am335xfb_init(struct am335x_lcdpanel *panel)
{
u32 raster_ctrl = 0;
-
struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
- struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 };
- unsigned int m, n, d, best_d = 2;
- int err = 0, err_r = 0;
+ ulong rate;
+ u32 reg;
if (gd->fb_base == 0) {
printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
@@ -156,34 +241,9 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
debug("using frambuffer at 0x%08x with size %d.\n",
(unsigned int)gd->fb_base, FBSIZE(panel));
- /* setup display pll for requested clock frequency */
- err = panel->pxl_clk;
- err_r = err;
-
- for (d = 2; err_r && d < 255; d++) {
- for (m = 2; m < 2047; m++) {
- if ((V_OSCK * m) < (panel->pxl_clk * d))
-
[PATCH v3 06/13] video: omap: fix debug message
"DISP" -> "DIV"
Signed-off-by: Dario Binacchi
Reviewed-by: Lokesh Vutla
---
Changes in v3: None
Changes in v2: None
drivers/video/am335x-fb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index 9f488f656e..bbe965af84 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -179,7 +179,7 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
}
}
}
- debug("%s: PLL: best error %d Hz (M %d, N %d, DISP %d)\n",
+ debug("%s: PLL: best error %d Hz (M %d, N %d, DIV %d)\n",
__func__, err_r, dpll_disp.m, dpll_disp.n, best_d);
do_setup_dpll(_disp_regs, _disp);
--
2.17.1
[PATCH v3 05/13] video: omap: rename LCD controller registers
Add more clarity by prefixing the name of the register to the bitfields. Signed-off-by: Dario Binacchi --- Changes in v3: None Changes in v2: None drivers/video/am335x-fb.c | 107 +++--- 1 file changed, 54 insertions(+), 53 deletions(-) diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c index 648ce508cc..9f488f656e 100644 --- a/drivers/video/am335x-fb.c +++ b/drivers/video/am335x-fb.c @@ -26,42 +26,42 @@ #define LCDC_FMAX 2 /* LCD Control Register */ -#define LCD_RASTER_MODEBIT(0) -#define LCD_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8) +#define LCDC_CTRL_RASTER_MODE BIT(0) +#define LCDC_CTRL_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8) /* LCD Clock Enable Register */ -#define LCD_CORECLKEN BIT(0) -#define LCD_LIDDCLKEN BIT(1) -#define LCD_DMACLKEN BIT(2) +#define LCDC_CLKC_ENABLE_CORECLKEN BIT(0) +#define LCDC_CLKC_ENABLE_LIDDCLKEN BIT(1) +#define LCDC_CLKC_ENABLE_DMACLKEN BIT(2) /* LCD DMA Control Register */ -#define LCD_DMA_BURST_SIZE(x) (((x) & GENMASK(2, 0)) << 4) -#define LCD_DMA_BURST_10x0 -#define LCD_DMA_BURST_20x1 -#define LCD_DMA_BURST_40x2 -#define LCD_DMA_BURST_80x3 -#define LCD_DMA_BURST_16 0x4 +#define LCDC_DMA_CTRL_BURST_SIZE(x)(((x) & GENMASK(2, 0)) << 4) +#define LCDC_DMA_CTRL_BURST_1 0x0 +#define LCDC_DMA_CTRL_BURST_2 0x1 +#define LCDC_DMA_CTRL_BURST_4 0x2 +#define LCDC_DMA_CTRL_BURST_8 0x3 +#define LCDC_DMA_CTRL_BURST_16 0x4 /* LCD Timing_0 Register */ -#define LCD_HORMSB(x) (x) >> 4) - 1) & 0x40) >> 4) -#define LCD_HORLSB(x) (x) >> 4) - 1) & GENMASK(5, 0)) << 4) -#define LCD_HSWLSB(x) x) - 1) & GENMASK(5, 0)) << 10) -#define LCD_HFPLSB(x) x) - 1) & GENMASK(7, 0)) << 16) -#define LCD_HBPLSB(x) x) - 1) & GENMASK(7, 0)) << 24) +#define LCDC_RASTER_TIMING_0_HORMSB(x) (x) >> 4) - 1) & 0x40) >> 4) +#define LCDC_RASTER_TIMING_0_HORLSB(x) (x) >> 4) - 1) & GENMASK(5, 0)) << 4) +#define LCDC_RASTER_TIMING_0_HSWLSB(x) x) - 1) & GENMASK(5, 0)) << 10) +#define LCDC_RASTER_TIMING_0_HFPLSB(x) x) - 1) & GENMASK(7, 0)) << 16) +#define LCDC_RASTER_TIMING_0_HBPLSB(x) x) - 1) & GENMASK(7, 0)) << 24) /* LCD Timing_1 Register */ -#define LCD_VERLSB(x) (((x) - 1) & GENMASK(9, 0)) -#define LCD_VSW(x) x) - 1) & GENMASK(5, 0)) << 10) -#define LCD_VFP(x) (((x) & GENMASK(7, 0)) << 16) -#define LCD_VBP(x) (((x) & GENMASK(7, 0)) << 24) +#define LCDC_RASTER_TIMING_1_VERLSB(x) (((x) - 1) & GENMASK(9, 0)) +#define LCDC_RASTER_TIMING_1_VSW(x)x) - 1) & GENMASK(5, 0)) << 10) +#define LCDC_RASTER_TIMING_1_VFP(x)(((x) & GENMASK(7, 0)) << 16) +#define LCDC_RASTER_TIMING_1_VBP(x)(((x) & GENMASK(7, 0)) << 24) /* LCD Timing_2 Register */ -#define LCD_HFPMSB(x) x) - 1) & GENMASK(9, 8)) >> 8) -#define LCD_HBPMSB(x) x) - 1) & GENMASK(9, 8)) >> 4) -#define LCD_INVMASK(x) ((x) & GENMASK(25, 20)) -#define LCD_VERMSB(x) x) - 1) & BIT(10)) << 16) -#define LCD_HSWMSB(x) x) - 1) & GENMASK(9, 6)) << 21) +#define LCDC_RASTER_TIMING_2_HFPMSB(x) x) - 1) & GENMASK(9, 8)) >> 8) +#define LCDC_RASTER_TIMING_2_HBPMSB(x) x) - 1) & GENMASK(9, 8)) >> 4) +#define LCDC_RASTER_TIMING_2_INVMASK(x)((x) & GENMASK(25, 20)) +#define LCDC_RASTER_TIMING_2_VERMSB(x) x) - 1) & BIT(10)) << 16) +#define LCDC_RASTER_TIMING_2_HSWMSB(x) x) - 1) & GENMASK(9, 6)) << 21) /* LCD Raster Ctrl Register */ -#define LCD_RASTER_ENABLE BIT(0) -#define LCD_TFT_MODE BIT(7) -#define LCD_PALMODE_RAWDATA(0x02 << 20) -#define LCD_TFT_24BPP_MODE BIT(25) -#define LCD_TFT_24BPP_UNPACK BIT(26) +#define LCDC_RASTER_CTRL_ENABLEBIT(0) +#define LCDC_RASTER_CTRL_TFT_MODE BIT(7) +#define LCDC_RASTER_CTRL_PALMODE_RAWDATA (0x02 << 20) +#define LCDC_RASTER_CTRL_TFT_24BPP_MODEBIT(25) +#define LCDC_RASTER_CTRL_TFT_24BPP_UNPACK BIT(26) /* Macro definitions */ #define FBSIZE(x) ((x->hactive * x->vactive * x->bpp) >> 3) @@ -131,10 +131,10 @@ int am335xfb_init(struct am335x_lcdpanel *panel) case 16: break; case 32: -
[PATCH v3 04/13] video: omap: fix bitfields order
Arrange the bitfields of each register in the ascending order. Signed-off-by: Dario Binacchi --- Changes in v3: None Changes in v2: None drivers/video/am335x-fb.c | 29 ++--- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c index 92e37bd1e0..648ce508cc 100644 --- a/drivers/video/am335x-fb.c +++ b/drivers/video/am335x-fb.c @@ -26,8 +26,8 @@ #define LCDC_FMAX 2 /* LCD Control Register */ -#define LCD_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8) #define LCD_RASTER_MODEBIT(0) +#define LCD_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8) /* LCD Clock Enable Register */ #define LCD_CORECLKEN BIT(0) #define LCD_LIDDCLKEN BIT(1) @@ -40,29 +40,28 @@ #define LCD_DMA_BURST_80x3 #define LCD_DMA_BURST_16 0x4 /* LCD Timing_0 Register */ -#define LCD_HBPLSB(x) x) - 1) & GENMASK(7, 0)) << 24) -#define LCD_HFPLSB(x) x) - 1) & GENMASK(7, 0)) << 16) -#define LCD_HSWLSB(x) x) - 1) & GENMASK(5, 0)) << 10) -#define LCD_HORLSB(x) (x) >> 4) - 1) & GENMASK(5, 0)) << 4) #define LCD_HORMSB(x) (x) >> 4) - 1) & 0x40) >> 4) +#define LCD_HORLSB(x) (x) >> 4) - 1) & GENMASK(5, 0)) << 4) +#define LCD_HSWLSB(x) x) - 1) & GENMASK(5, 0)) << 10) +#define LCD_HFPLSB(x) x) - 1) & GENMASK(7, 0)) << 16) +#define LCD_HBPLSB(x) x) - 1) & GENMASK(7, 0)) << 24) /* LCD Timing_1 Register */ -#define LCD_VBP(x) (((x) & GENMASK(7, 0)) << 24) -#define LCD_VFP(x) (((x) & GENMASK(7, 0)) << 16) -#define LCD_VSW(x) x) - 1) & GENMASK(5, 0)) << 10) #define LCD_VERLSB(x) (((x) - 1) & GENMASK(9, 0)) +#define LCD_VSW(x) x) - 1) & GENMASK(5, 0)) << 10) +#define LCD_VFP(x) (((x) & GENMASK(7, 0)) << 16) +#define LCD_VBP(x) (((x) & GENMASK(7, 0)) << 24) /* LCD Timing_2 Register */ -#define LCD_HSWMSB(x) x) - 1) & GENMASK(9, 6)) << 21) -#define LCD_VERMSB(x) x) - 1) & BIT(10)) << 16) -#define LCD_HBPMSB(x) x) - 1) & GENMASK(9, 8)) >> 4) #define LCD_HFPMSB(x) x) - 1) & GENMASK(9, 8)) >> 8) +#define LCD_HBPMSB(x) x) - 1) & GENMASK(9, 8)) >> 4) #define LCD_INVMASK(x) ((x) & GENMASK(25, 20)) +#define LCD_VERMSB(x) x) - 1) & BIT(10)) << 16) +#define LCD_HSWMSB(x) x) - 1) & GENMASK(9, 6)) << 21) /* LCD Raster Ctrl Register */ +#define LCD_RASTER_ENABLE BIT(0) +#define LCD_TFT_MODE BIT(7) +#define LCD_PALMODE_RAWDATA(0x02 << 20) #define LCD_TFT_24BPP_MODE BIT(25) #define LCD_TFT_24BPP_UNPACK BIT(26) -#define LCD_PALMODE_RAWDATA(0x02 << 20) -#define LCD_TFT_MODE BIT(7) -#define LCD_RASTER_ENABLE BIT(0) - /* Macro definitions */ #define FBSIZE(x) ((x->hactive * x->vactive * x->bpp) >> 3) -- 2.17.1
[PATCH v3 07/13] video: omap: add loop exit conditions to the dpll setup
In case of null error, round rate is equal to target rate, so it is
useless to continue to search the DPLL setup parameters to get the
desidered pixel clock rate.
Signed-off-by: Dario Binacchi
Reviewed-by: Lokesh Vutla
---
Changes in v3: None
Changes in v2: None
drivers/video/am335x-fb.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index bbe965af84..684223f275 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -160,7 +160,7 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
err = panel->pxl_clk;
err_r = err;
- for (d = 2; d < 255; d++) {
+ for (d = 2; err_r && d < 255; d++) {
for (m = 2; m < 2047; m++) {
if ((V_OSCK * m) < (panel->pxl_clk * d))
continue;
@@ -176,6 +176,8 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
dpll_disp.m = m;
dpll_disp.n = n;
best_d = d;
+ if (err_r == 0)
+ break;
}
}
}
--
2.17.1
[PATCH v3 02/13] video: omap: add missing bitfield masks
Add, if missing, the bitfield masks in the setting macros of the LCD controller registers. Signed-off-by: Dario Binacchi --- Changes in v3: None Changes in v2: - Use GENMASK macro drivers/video/am335x-fb.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c index 7065d57148..4fd3b7f65a 100644 --- a/drivers/video/am335x-fb.c +++ b/drivers/video/am335x-fb.c @@ -26,14 +26,14 @@ #define LCDC_FMAX 2 /* LCD Control Register */ -#define LCD_CLK_DIVISOR(x) ((x) << 8) +#define LCD_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8) #define LCD_RASTER_MODEBIT(0) /* LCD Clock Enable Register */ #define LCD_CORECLKEN BIT(0) #define LCD_LIDDCLKEN BIT(1) #define LCD_DMACLKEN BIT(2) /* LCD DMA Control Register */ -#define LCD_DMA_BURST_SIZE(x) ((x) << 4) +#define LCD_DMA_BURST_SIZE(x) (((x) & GENMASK(2, 0)) << 4) #define LCD_DMA_BURST_10x0 #define LCD_DMA_BURST_20x1 #define LCD_DMA_BURST_40x2 @@ -46,9 +46,9 @@ #define LCD_HORLSB(x) (x) >> 4) - 1) & GENMASK(5, 0)) << 4) #define LCD_HORMSB(x) (x) >> 4)-1) & 0x40) >> 4) /* LCD Timing_1 Register */ -#define LCD_VBP(x) ((x) << 24) -#define LCD_VFP(x) ((x) << 16) -#define LCD_VSW(x) (((x)-1) << 10) +#define LCD_VBP(x) (((x) & GENMASK(7, 0)) << 24) +#define LCD_VFP(x) (((x) & GENMASK(7, 0)) << 16) +#define LCD_VSW(x) x) - 1) & GENMASK(5, 0)) << 10) #define LCD_VERLSB(x) (((x) - 1) & GENMASK(9, 0)) /* LCD Timing_2 Register */ #define LCD_HSWMSB(x) x) - 1) & GENMASK(9, 6)) << 21) -- 2.17.1
[PATCH v3 03/13] video: omap: fix coding style on use of spaces
Use one space around (on each side of) the binary '-' operator. Signed-off-by: Dario Binacchi --- Changes in v3: None Changes in v2: None drivers/video/am335x-fb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c index 4fd3b7f65a..92e37bd1e0 100644 --- a/drivers/video/am335x-fb.c +++ b/drivers/video/am335x-fb.c @@ -44,7 +44,7 @@ #define LCD_HFPLSB(x) x) - 1) & GENMASK(7, 0)) << 16) #define LCD_HSWLSB(x) x) - 1) & GENMASK(5, 0)) << 10) #define LCD_HORLSB(x) (x) >> 4) - 1) & GENMASK(5, 0)) << 4) -#define LCD_HORMSB(x) (x) >> 4)-1) & 0x40) >> 4) +#define LCD_HORMSB(x) (x) >> 4) - 1) & 0x40) >> 4) /* LCD Timing_1 Register */ #define LCD_VBP(x) (((x) & GENMASK(7, 0)) << 24) #define LCD_VFP(x) (((x) & GENMASK(7, 0)) << 16) -- 2.17.1
[PATCH v3 01/13] video: omap: use BIT() and GENMASK() macros
Use the standard BIT() and GENMASK() macros for bitfield definitions. Signed-off-by: Dario Binacchi --- Changes in v3: None Changes in v2: - Use GENMASK macro too drivers/video/am335x-fb.c | 36 ++-- drivers/video/am335x-fb.h | 12 ++-- 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c index 51c1af587f..7065d57148 100644 --- a/drivers/video/am335x-fb.c +++ b/drivers/video/am335x-fb.c @@ -27,11 +27,11 @@ /* LCD Control Register */ #define LCD_CLK_DIVISOR(x) ((x) << 8) -#define LCD_RASTER_MODE0x01 +#define LCD_RASTER_MODEBIT(0) /* LCD Clock Enable Register */ -#define LCD_CORECLKEN (0x01 << 0) -#define LCD_LIDDCLKEN (0x01 << 1) -#define LCD_DMACLKEN (0x01 << 2) +#define LCD_CORECLKEN BIT(0) +#define LCD_LIDDCLKEN BIT(1) +#define LCD_DMACLKEN BIT(2) /* LCD DMA Control Register */ #define LCD_DMA_BURST_SIZE(x) ((x) << 4) #define LCD_DMA_BURST_10x0 @@ -40,28 +40,28 @@ #define LCD_DMA_BURST_80x3 #define LCD_DMA_BURST_16 0x4 /* LCD Timing_0 Register */ -#define LCD_HBPLSB(x) x)-1) & 0xFF) << 24) -#define LCD_HFPLSB(x) x)-1) & 0xFF) << 16) -#define LCD_HSWLSB(x) x)-1) & 0x3F) << 10) -#define LCD_HORLSB(x) (x) >> 4)-1) & 0x3F) << 4) +#define LCD_HBPLSB(x) x) - 1) & GENMASK(7, 0)) << 24) +#define LCD_HFPLSB(x) x) - 1) & GENMASK(7, 0)) << 16) +#define LCD_HSWLSB(x) x) - 1) & GENMASK(5, 0)) << 10) +#define LCD_HORLSB(x) (x) >> 4) - 1) & GENMASK(5, 0)) << 4) #define LCD_HORMSB(x) (x) >> 4)-1) & 0x40) >> 4) /* LCD Timing_1 Register */ #define LCD_VBP(x) ((x) << 24) #define LCD_VFP(x) ((x) << 16) #define LCD_VSW(x) (((x)-1) << 10) -#define LCD_VERLSB(x) (((x)-1) & 0x3FF) +#define LCD_VERLSB(x) (((x) - 1) & GENMASK(9, 0)) /* LCD Timing_2 Register */ -#define LCD_HSWMSB(x) x)-1) & 0x3C0) << 21) -#define LCD_VERMSB(x) x)-1) & 0x400) << 16) -#define LCD_HBPMSB(x) x)-1) & 0x300) >> 4) -#define LCD_HFPMSB(x) x)-1) & 0x300) >> 8) -#define LCD_INVMASK(x) ((x) & 0x3F0) +#define LCD_HSWMSB(x) x) - 1) & GENMASK(9, 6)) << 21) +#define LCD_VERMSB(x) x) - 1) & BIT(10)) << 16) +#define LCD_HBPMSB(x) x) - 1) & GENMASK(9, 8)) >> 4) +#define LCD_HFPMSB(x) x) - 1) & GENMASK(9, 8)) >> 8) +#define LCD_INVMASK(x) ((x) & GENMASK(25, 20)) /* LCD Raster Ctrl Register */ -#define LCD_TFT_24BPP_MODE (1 << 25) -#define LCD_TFT_24BPP_UNPACK (1 << 26) +#define LCD_TFT_24BPP_MODE BIT(25) +#define LCD_TFT_24BPP_UNPACK BIT(26) #define LCD_PALMODE_RAWDATA(0x02 << 20) -#define LCD_TFT_MODE (0x01 << 7) -#define LCD_RASTER_ENABLE (0x01 << 0) +#define LCD_TFT_MODE BIT(7) +#define LCD_RASTER_ENABLE BIT(0) /* Macro definitions */ diff --git a/drivers/video/am335x-fb.h b/drivers/video/am335x-fb.h index f5883c02dd..ad9b015e09 100644 --- a/drivers/video/am335x-fb.h +++ b/drivers/video/am335x-fb.h @@ -7,7 +7,7 @@ #ifndef AM335X_FB_H #define AM335X_FB_H -#define HSVS_CONTROL (0x01 << 25)/* +#define HSVS_CONTROL BIT(25) /* * 0 = lcd_lp and lcd_fp are driven on * opposite edges of pixel clock than * the lcd_pixel_o @@ -17,7 +17,7 @@ * Matrix displays the edge timing is * fixed */ -#define HSVS_RISEFALL (0x01 << 24)/* +#define HSVS_RISEFALL BIT(24) /* * 0 = lcd_lp and lcd_fp are driven on * the rising edge of pixel clock (bit * 25 must be set to 1) @@ -25,19 +25,19 @@ * the falling edge of pixel clock (bit * 25 must be set to 1)
[PATCH v3 00/13] Add DM/DTS support for omap video driver
Changes: - Fix coding style - Refactor some parts of the driver - Add support for driver model and device-tree - Update the boards device-tree - Add device-tree binding documentation Changes in v3: - Add panel to the root node so that the dts linux file of the board does not need to be updated. Changes in v2: - Use GENMASK macro too - Use GENMASK macro - Use GENMASK macro for clock divisor mask - Move clock enabling sequence to arch/arm/mach-omap2/ - Create a Kconfig symbol for CONFIG_AM335X_LCD - Change subject line in: arm: dts: am335x: - Move 'u-boot,dm-pre-reloc' property in *-u-boot.dtsi files for boards tha support Linux Dario Binacchi (13): video: omap: use BIT() and GENMASK() macros video: omap: add missing bitfield masks video: omap: fix coding style on use of spaces video: omap: fix bitfields order video: omap: rename LCD controller registers video: omap: fix debug message video: omap: add loop exit conditions to the dpll setup video: omap: create two routines to set the pixel clock rate video: omap: add support for DM/DTS arm: dts: am335x: add 'u-boot,dm-pre-reloc' to panel fdt: video: omap: add framebuffer and panel bindings video: omap: fix pixel-per-line bitfield setting board: brxre1: fix building errors arch/arm/dts/am335x-brppt1-mmc.dts| 2 + arch/arm/dts/am335x-brppt1-nand.dts | 2 + arch/arm/dts/am335x-brppt1-spi.dts| 2 + arch/arm/dts/am335x-brsmarc1.dts | 1 + arch/arm/dts/am335x-brxre1.dts| 2 + arch/arm/dts/am335x-evm-u-boot.dtsi | 6 + arch/arm/dts/am335x-evmsk-u-boot.dtsi | 12 + arch/arm/dts/am335x-guardian-u-boot.dtsi | 4 + arch/arm/dts/am335x-pdu001-u-boot.dtsi| 4 + arch/arm/dts/am335x-pxm50-u-boot.dtsi | 12 + arch/arm/dts/am335x-rut-u-boot.dtsi | 12 + arch/arm/dts/da850-evm-u-boot.dtsi| 4 + arch/arm/mach-omap2/am33xx/clock_am33xx.c | 4 + board/BuR/common/br_resetc.c | 2 +- board/BuR/common/bur_common.h | 3 + board/BuR/common/common.c | 2 +- .../video/tilcdc/panel.txt| 66 ++ .../video/tilcdc/tilcdc.txt | 82 +++ drivers/video/Kconfig | 6 + drivers/video/am335x-fb.c | 567 +++--- drivers/video/am335x-fb.h | 16 +- include/configs/brxre1.h | 2 + 22 files changed, 713 insertions(+), 100 deletions(-) create mode 100644 arch/arm/dts/am335x-evmsk-u-boot.dtsi create mode 100644 arch/arm/dts/am335x-pxm50-u-boot.dtsi create mode 100644 arch/arm/dts/am335x-rut-u-boot.dtsi create mode 100644 doc/device-tree-bindings/video/tilcdc/panel.txt create mode 100644 doc/device-tree-bindings/video/tilcdc/tilcdc.txt -- 2.17.1
Re: [RFC PATCH 03/10] i2c: mmc: add nexell driver (gpio, i2c, mmc, pwm)
Hello Stefan,
Am 20.02.2020 um 18:49 schrieb Stefan B.:
Hello Heiko,
see below my feedback, please give me further advise where indicated.
Unfortunately there have been some Bugs in the i2c-driver and I learned that this driver has not
been used at all ("i2c-gpio" has been used instead). So I have done several Bugfixes and
improvements appart from your proposals.
Regards
Stefan
Am 04.02.20 um 07:58 schrieb Heiko Schocher:
Hello Stefan,
Am 03.02.2020 um 21:40 schrieb Stefan Bosch:
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- i2c/nx_i2c.c: Some adaptions mainly because of changes in
"struct udevice".
- mmc: nexell_dw_mmc.c changed to nexell_dw_mmc_dm.c (switched to DM).
Signed-off-by: Stefan Bosch
---
drivers/gpio/Kconfig | 9 +
drivers/gpio/Makefile | 1 +
drivers/gpio/nx_gpio.c | 252 +++
drivers/i2c/Kconfig | 9 +
drivers/i2c/Makefile | 1 +
drivers/i2c/nx_i2c.c | 537 +
drivers/mmc/Kconfig | 6 +
drivers/mmc/Makefile | 1 +
drivers/mmc/nexell_dw_mmc_dm.c | 350 +++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-nexell.c | 252 +++
drivers/pwm/pwm-nexell.h | 54 +
Could you please split this patch into 4 parts (i2c, gpio, mmc and
pwm) ?
Thanks!
Ok, I will split this patch.
Thanks!
12 files changed, 1473 insertions(+)
create mode 100644 drivers/gpio/nx_gpio.c
create mode 100644 drivers/i2c/nx_i2c.c
create mode 100644 drivers/mmc/nexell_dw_mmc_dm.c
create mode 100644 drivers/pwm/pwm-nexell.c
create mode 100644 drivers/pwm/pwm-nexell.h
[...]
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 449046b..e3340de 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -65,3 +65,4 @@ obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
+obj-$(CONFIG_NX_GPIO) += nx_gpio.o
Please keep lists sorted.
The list is not sorted (at least in no alphabetical order), but I can e.g. move "... += nx_gpio.o"
one line up?
Find for me.
diff --git a/drivers/gpio/nx_gpio.c b/drivers/gpio/nx_gpio.c
new file mode 100644
index 000..86472f6
--- /dev/null
+++ b/drivers/gpio/nx_gpio.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Nexell
+ * DeokJin, Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct nx_gpio_regs {
+ u32 data; /* Data register */
+ u32 outputenb; /* Output Enable register */
+ u32 detmode[2]; /* Detect Mode Register */
+ u32 intenb; /* Interrupt Enable Register */
+ u32 det; /* Event Detect Register */
+ u32 pad; /* Pad Status Register */
+};
+
+struct nx_alive_gpio_regs {
+ u32 pwrgate; /* Power Gating Register */
+ u32 reserved0[28]; /* Reserved0 */
+ u32 outputenb_reset;/* Alive GPIO Output Enable Reset Register */
+ u32 outputenb; /* Alive GPIO Output Enable Register */
+ u32 outputenb_read; /* Alive GPIO Output Read Register */
+ u32 reserved1[3]; /* Reserved1 */
+ u32 pad_reset; /* Alive GPIO Output Reset Register */
+ u32 data; /* Alive GPIO Output Register */
+ u32 pad_read; /* Alive GPIO Pad Read Register */
+ u32 reserved2[33]; /* Reserved2 */
+ u32 pad; /* Alive GPIO Input Value Register */
+};
+
+struct nx_gpio_platdata {
+ void *regs;
+ int gpio_count;
+ const char *bank_name;
+};
+
+static int nx_alive_gpio_is_check(struct udevice *dev)
+{
+ struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ const char *bank_name = plat->bank_name;
+
+ if (!strcmp(bank_name, "gpio_alv"))
+ return 1;
+
+ return 0;
+}
+
+static int nx_alive_gpio_direction_input(struct udevice *dev, unsigned int pin)
+{
+ struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_alive_gpio_regs *const regs = plat->regs;
+
+ setbits_le32(>outputenb_reset, 1 << pin);
+
+ return 0;
+}
+
+static int nx_alive_gpio_direction_output(struct udevice *dev, unsigned int
pin,
+ int val)
+{
+ struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_alive_gpio_regs *const regs = plat->regs;
+
+ if (val)
+ setbits_le32(>data, 1 << pin);
+ else
+ setbits_le32(>pad_reset, 1 << pin);
+
+ setbits_le32(>outputenb, 1 << pin);
+
+ return 0;
+}
+
+static int nx_alive_gpio_get_value(struct udevice *dev, unsigned int pin)
+{
+ struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_alive_gpio_regs *const regs = plat->regs;
+ unsigned int mask = 1UL << pin;
+ unsigned int value;
+
+ value =
Re: [PATCH] bootcounter: add DM support for memory based bootcounter
Hello Simon,
Am 21.02.2020 um 01:50 schrieb Simon Glass:
Hi Heiko,
On Thu, 20 Feb 2020 at 02:28, Heiko Schocher wrote:
add DM/DTS support for the memory based bootcounter
in drivers/bootcount/bootcount.c.
Let the old implementation in, so boards which have
not yet convert to DM/DTS do not break.
Signed-off-by: Heiko Schocher
---
Travis build:
https://travis-ci.org/hsdenx/u-boot-test/builds/652839618
doc/device-tree-bindings/misc/bootcounter.txt | 21 +
drivers/bootcount/Kconfig | 5 ++
drivers/bootcount/Makefile| 1 +
drivers/bootcount/bootcount.c | 86 +++
4 files changed, 113 insertions(+)
create mode 100644 doc/device-tree-bindings/misc/bootcounter.txt
diff --git a/doc/device-tree-bindings/misc/bootcounter.txt
b/doc/device-tree-bindings/misc/bootcounter.txt
new file mode 100644
index 00..f4a4a731b9
--- /dev/null
+++ b/doc/device-tree-bindings/misc/bootcounter.txt
@@ -0,0 +1,21 @@
+U-Boot bootcounter Devicetree Binding
+=
+
+The device tree node describes the U-Boot bootcounter
+memory based device binding.
+
+Required properties :
+
+- compatible : "uboot,bootcount";
I think we use u-boot in other bindings
Yes. I just porting some mpc83xx boards to DM/DTS and they use
"uboot,bootcounter" ... but I think, it should be possible to change
this in the respectiv DTS files.
+- singleword : set this, if you have only one word space
+for storing the bootcounter.
single-word
Yep
I think this is a boolean property, right?
Yes.
What is a word? Is it 32 bits? Also, what does it actually mean/do?
If enabled bootcounter driver does use one word (32 bit) only.
See CONFIG_SYS_BOOTCOUNT_SINGLEWORD in current version of mainline
driver.
+
+Example
+---
+
+MPC83xx based board:
+
+bootcount@0x13ff8 {
+ compatible = "uboot,bootcount";
+ reg = <0x13ff8 0x08>;
+};
diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index 0e506c9ea2..88203607a8 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig
@@ -106,6 +106,11 @@ config DM_BOOTCOUNT_I2C_EEPROM
pointing to the underlying i2c eeprom device) and an optional
'offset'
property are supported.
+config BOOTCOUNT_MEM
+ bool "memory based bootcounter"
+ help
+ Memory based bootcount, compatible = "uboot,bootcount";
+
endmenu
endif
diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile
index 73ccfb5a08..059d40d16b 100644
--- a/drivers/bootcount/Makefile
+++ b/drivers/bootcount/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_BOOTCOUNT_GENERIC)+= bootcount.o
+obj-$(CONFIG_BOOTCOUNT_MEM)+= bootcount.o
obj-$(CONFIG_BOOTCOUNT_AT91) += bootcount_at91.o
obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o
obj-$(CONFIG_BOOTCOUNT_RAM)+= bootcount_ram.o
diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c
index 7a6d03dcca..53bd416cf6 100644
--- a/drivers/bootcount/bootcount.c
+++ b/drivers/bootcount/bootcount.c
@@ -8,6 +8,7 @@
#include
#include
+#if !defined(CONFIG_DM_BOOTCOUNT)
/* Now implement the generic default functions */
__weak void bootcount_store(ulong a)
{
@@ -49,3 +50,88 @@ __weak ulong bootcount_load(void)
return raw_bootcount_load(reg);
#endif /* defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) */
}
+#else
+#include
+
Comment for struct
Of course, I add one, sorry for this.
+struct bootcount_mem_priv {
+ phys_addr_t base;
+ u8 singleword;
bool?
Yes, I change this to bool.
+};
+
+static int bootcount_mem_get(struct udevice *dev, u32 *a)
+{
+ struct bootcount_mem_priv *priv = dev_get_priv(dev);
+ void *reg = (void *)priv->base;
+ u32 magic = CONFIG_SYS_BOOTCOUNT_MAGIC;
+
+ if (priv->singleword) {
+ u32 tmp = raw_bootcount_load(reg);
+
+ if ((tmp & 0x) != (magic & 0x))
+ return -ENODEV;
+
+ *a = (tmp & 0x);
+ } else {
+ if (raw_bootcount_load(reg + 4) != magic)
+ return -ENODEV;
+
+ *a = raw_bootcount_load(reg);
+ }
+
+ return 0;
+};
+
+static int bootcount_mem_set(struct udevice *dev, const u32 a)
+{
+ struct bootcount_mem_priv *priv = dev_get_priv(dev);
+ void *reg = (void *)priv->base;
+ u32 magic = CONFIG_SYS_BOOTCOUNT_MAGIC;
+ uintptr_t flush_start = rounddown(priv->base,
+ CONFIG_SYS_CACHELINE_SIZE);
+ uintptr_t flush_end;
+
+ if (priv->singleword) {
+ raw_bootcount_store(reg, (magic & 0x) | a);
+ flush_end = roundup(priv->base + 4,
+ CONFIG_SYS_CACHELINE_SIZE);
+ } else {
+ raw_bootcount_store(reg, a);
+
RE: [PATCH v2 13/21] arm: socfpga: Secure register access for reading PLL frequency
> > From: Chee Hong Ang
> >
> > Allow reading external oscillator and FPGA clock's frequency from
> > System Manager's Boot Scratch Register 1 and Boot Scratch Register 2
> > in non-secure mode (EL2) on SoC 64bits platform.
> >
> > Signed-off-by: Chee Hong Ang
> > ---
> > arch/arm/mach-socfpga/wrap_pll_config_s10.c | 9 +
> > 1 file changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> > b/arch/arm/mach- socfpga/wrap_pll_config_s10.c index 3da8579..7bd92d0
> > 100644
> > --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> > +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> > @@ -9,6 +9,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > const struct cm_config * const cm_get_default_config(void) { @@
> > -39,8 +40,8 @@ const unsigned int cm_get_osc_clk_hz(void)
> > writel(clock,
> >socfpga_get_sysmgr_addr() +
> > SYSMGR_SOC64_BOOT_SCRATCH_COLD1); #endif
> > - return readl(socfpga_get_sysmgr_addr() +
> > -SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
> > + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> > +
> > SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
> > }
> >
> > const unsigned int cm_get_intosc_clk_hz(void) @@ -56,6 +57,6 @@ const
> > unsigned int cm_get_fpga_clk_hz(void)
> > writel(clock,
> >socfpga_get_sysmgr_addr() +
> > SYSMGR_SOC64_BOOT_SCRATCH_COLD2); #endif
> > - return readl(socfpga_get_sysmgr_addr() +
> > -SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
> > + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> > +
> > SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
> > }
> > --
> > 2.7.4
> This clock info could be directly read from the handoff table (OCRAM) instead
> of
> the System Manager's boot scratch register (secure zone).
> Please refer to my full explanation in my previous email reply:
> [PATCH v2 11/21] arm: socfpga: Secure register access for clock manager (SoC
> 64bits)
Simon raised a good security concern on this approach. I will drop this
approach.
Will go for high-level APIs in ATF for clock queries:
INTEL_SIP_SMC_CLK_GET_OSC
INTEL_SIP_SMC_CLK_GET_FPGA
RE: [PATCH v2 11/21] arm: socfpga: Secure register access for clock manager (SoC 64bits)
Ang, Chee Hong mailto:chee.hong@intel.com>>
schrieb am Sa., 22. Feb. 2020, 06:30:
> From: Chee Hong Ang mailto:chee.hong@intel.com>>
>
> Allow clock manager driver to access the System Manager's Boot Scratch
> Register 0 in non-secure mode (EL2) on SoC 64bits platform.
>
> Signed-off-by: Chee Hong Ang
> mailto:chee.hong@intel.com>>
> ---
> arch/arm/mach-socfpga/clock_manager_agilex.c | 5 +++--
> arch/arm/mach-socfpga/clock_manager_s10.c| 5 +++--
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-
> socfpga/clock_manager_agilex.c
> index 4ee2b7b..e5a0998 100644
> --- a/arch/arm/mach-socfpga/clock_manager_agilex.c
> +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
> @@ -12,6 +12,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -65,8 +66,8 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
>
> u32 cm_get_qspi_controller_clk_hz(void)
> {
> - return readl(socfpga_get_sysmgr_addr() +
> - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> +
> SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> }
>
> void cm_print_clock_quick_summary(void)
> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-
> socfpga/clock_manager_s10.c
> index 05e4212..02578cc 100644
> --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> @@ -9,6 +9,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -385,8 +386,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
>
> unsigned int cm_get_qspi_controller_clk_hz(void)
> {
> - return readl(socfpga_get_sysmgr_addr() +
> - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> +
> SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> }
>
> unsigned int cm_get_spi_controller_clk_hz(void)
> --
> 2.7.4
>SPL reads the clock info from handoff table (OCRAM) and write
>the clock info into the System Manager's boot scratch register.
>U-Boot proper will read from the System Manager's boot scratch
>register to get the clock info in case the handoff table (OCRAM)
>is no longer available.
>After some investigations, the handoff table in OCRAM should be preserved
>for warm boot. In other words, this handoff table should be left untouched.
>SPL and U-Boot should directly read the clock info from handoff table in OCRAM.
>Therefore, U-Boot proper no longer need to read the clock info from
>System Manager's boot scratch register (secure zone) from non-secure world
>(EL2).
>I don't think that's a good idea: for security reasons, SPL memory should not
>be accessible from EL2 if it is required/used for the next reboot.
>
>Regards,
>Simon
Right. I think I will have to go for proper high-level API in ATF for EL2 to
query the clock frequency:
INTEL_SIP_SMC_CLK_GET_QSPI
