[PATCH U-BOOT v2 0/3] fs: btrfs: Fix false LZO decompression error due to missing page boundary check

[Qu Wenruo]

There is a bug that uboot can't load LZO compressed data extent while
kernel can handle it without any problem.

It turns out to be a page boundary case. The 3nd patch is the proper
fix, cross-ported from btrfs-progs.

The first patch is just to make my eyes less hurt.
The second patch is to make sure the driver will reject sector size not
matching PAGE_SIZE.
This keeps the behavior the same as kernel, even in theory we could do
better in U-boot. This is just a temporary fix, before better btrfs
driver implemented.

I guess it's time to backport proper code from btrfs-progs, other than
using tons of immediate codes.

Changelog:
v2:
- Fix code style problems
- Add a new patch to reject non-page-sized sector size
  Since kernel does the same thing, and non-4K page size u-boot boards
  are really rare, it shouldn't be a big problem.

Qu Wenruo (3):
  fs: btrfs: Use LZO_LEN to replace immediate number
  fs: btrfs: Reject fs with sector size other than PAGE_SIZE
  fs: btrfs: Fix LZO false decompression error caused by pending zero

 fs/btrfs/compression.c | 42 +++---
 fs/btrfs/super.c   |  8 
 2 files changed, 39 insertions(+), 11 deletions(-)

-- 
2.26.0

[PATCH U-BOOT v2 3/3] fs: btrfs: Fix LZO false decompression error caused by pending zero

[Qu Wenruo]

For certain btrfs files with compressed file extent, uboot will fail to
load it:

  btrfs_read_extent_reg: disk_bytenr=14229504 disk_len=73728 offset=0 
nr_bytes=131
  072
  decompress_lzo: tot_len=70770
  decompress_lzo: in_len=1389
  decompress_lzo: in_len=2400
  decompress_lzo: in_len=3002
  decompress_lzo: in_len=1379
  decompress_lzo: in_len=88539136
  decompress_lzo: header error, in_len=88539136 clen=65534 tot_len=62580

NOTE: except the last line, all other lines are debug output.

Btrfs lzo compression uses its own format to record compressed size
(segment header, LE32).

However to make decompression easier, we never put such segment header
across page boundary.

In above case, the xxd dump of the lzo compressed data looks like this:

1fe0: 4cdc 02fc 0bfd 02c0 dc02 0d13 0100 0001  L...
1ff0:  0008 0300   0011 |  
2000: 4705  0001 cc02    1e01  G...

'|' is the "expected" segment header start position.

But in that page, there are only 2 bytes left, can't contain the 4 bytes
segment header.

So btrfs compression will skip that 2 bytes, put the segment header in
next page directly.

Uboot doesn't have such check, and read the header with 2 bytes offset,
result 0x0547 (88539136), other than the expected result
0x0547 (1351), resulting above error.

Follow the btrfs-progs restore implementation, by introducing tot_in to
record total processed bytes (including headers), and do proper page
boundary skip to fix it.

Please note that, current code base doesn't parse fs_info thus we can't
grab sector size easily, so it uses PAGE_SIZE, and relying on fs open
time check to exclude unsupported sector size.

Signed-off-by: Qu Wenruo 
Cc: Marek Behun 
---
 fs/btrfs/compression.c | 20 +++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/fs/btrfs/compression.c b/fs/btrfs/compression.c
index 4ef44ce11485..b1884fc15ee0 100644
--- a/fs/btrfs/compression.c
+++ b/fs/btrfs/compression.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -16,7 +17,7 @@
 #define LZO_LEN4
 static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen)
 {
-   u32 tot_len, in_len, res;
+   u32 tot_len, tot_in, in_len, res;
size_t out_len;
int ret;
 
@@ -24,9 +25,11 @@ static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 
*dbuf, u32 dlen)
return -1;
 
tot_len = le32_to_cpu(get_unaligned((u32 *)cbuf));
+   tot_in = 0;
cbuf += LZO_LEN;
clen -= LZO_LEN;
tot_len -= LZO_LEN;
+   tot_in += LZO_LEN;
 
if (tot_len == 0 && dlen)
return -1;
@@ -36,6 +39,8 @@ static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 *dbuf, 
u32 dlen)
res = 0;
 
while (tot_len > LZO_LEN) {
+   u32 rem_page;
+
in_len = le32_to_cpu(get_unaligned((u32 *)cbuf));
cbuf += LZO_LEN;
clen -= LZO_LEN;
@@ -44,6 +49,7 @@ static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 *dbuf, 
u32 dlen)
return -1;
 
tot_len -= (LZO_LEN + in_len);
+   tot_in += (LZO_LEN + in_len);
 
out_len = dlen;
ret = lzo1x_decompress_safe(cbuf, in_len, dbuf, &out_len);
@@ -56,6 +62,18 @@ static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 
*dbuf, u32 dlen)
dlen -= out_len;
 
res += out_len;
+
+   /*
+* If the 4 bytes header does not fit to the rest of the page we
+* have to move to next one, or we read some garbage.
+*/
+   rem_page = PAGE_SIZE - (tot_in % PAGE_SIZE);
+   if (rem_page < LZO_LEN) {
+   cbuf += rem_page;
+   tot_in += rem_page;
+   clen -= rem_page;
+   tot_len -= rem_page;
+   }
}
 
return res;
-- 
2.26.0

[PATCH U-BOOT v2 1/3] fs: btrfs: Use LZO_LEN to replace immediate number

[Qu Wenruo]

Just a cleanup. These immediate numbers make my eyes hurt.

Signed-off-by: Qu Wenruo 
Cc: Marek Behun 
---
 fs/btrfs/compression.c | 22 --
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/fs/btrfs/compression.c b/fs/btrfs/compression.c
index 346875d45a1b..4ef44ce11485 100644
--- a/fs/btrfs/compression.c
+++ b/fs/btrfs/compression.c
@@ -12,36 +12,38 @@
 #include 
 #include 
 
+/* Header for each segment, LE32, recording the compressed size */
+#define LZO_LEN4
 static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen)
 {
u32 tot_len, in_len, res;
size_t out_len;
int ret;
 
-   if (clen < 4)
+   if (clen < LZO_LEN)
return -1;
 
tot_len = le32_to_cpu(get_unaligned((u32 *)cbuf));
-   cbuf += 4;
-   clen -= 4;
-   tot_len -= 4;
+   cbuf += LZO_LEN;
+   clen -= LZO_LEN;
+   tot_len -= LZO_LEN;
 
if (tot_len == 0 && dlen)
return -1;
-   if (tot_len < 4)
+   if (tot_len < LZO_LEN)
return -1;
 
res = 0;
 
-   while (tot_len > 4) {
+   while (tot_len > LZO_LEN) {
in_len = le32_to_cpu(get_unaligned((u32 *)cbuf));
-   cbuf += 4;
-   clen -= 4;
+   cbuf += LZO_LEN;
+   clen -= LZO_LEN;
 
-   if (in_len > clen || tot_len < 4 + in_len)
+   if (in_len > clen || tot_len < LZO_LEN + in_len)
return -1;
 
-   tot_len -= 4 + in_len;
+   tot_len -= (LZO_LEN + in_len);
 
out_len = dlen;
ret = lzo1x_decompress_safe(cbuf, in_len, dbuf, &out_len);
-- 
2.26.0

[PATCH U-BOOT v2 2/3] fs: btrfs: Reject fs with sector size other than PAGE_SIZE

[Qu Wenruo]

Although in theory u-boot fs driver could easily support more sector
sizes, current code base doesn't have good enough way to grab sector
size yet.

This would cause problem for later LZO fixes which rely on sector size.

And considering that most u-boot boards are using 4K page size, which is
also the most common sector size for btrfs, rejecting fs with
non-page-sized sector size shouldn't cause much problem.

This should only be a quick fix before we implement better sector size
support.

Signed-off-by: Qu Wenruo 
Cc: Marek Behun 
---
 fs/btrfs/super.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
index 2dc4a6fcd7a3..b693a073fc0b 100644
--- a/fs/btrfs/super.c
+++ b/fs/btrfs/super.c
@@ -7,6 +7,7 @@
 
 #include "btrfs.h"
 #include 
+#include 
 
 #define BTRFS_SUPER_FLAG_SUPP  (BTRFS_HEADER_FLAG_WRITTEN  \
 | BTRFS_HEADER_FLAG_RELOC  \
@@ -232,6 +233,13 @@ int btrfs_read_superblock(void)
return -1;
}
 
+   if (sb->sectorsize != PAGE_SIZE) {
+   printf(
+   "%s: Unsupported sector size (%u), only supports %u as sector size\n",
+   __func__, sb->sectorsize, PAGE_SIZE);
+   return -1;
+   }
+
if (btrfs_info.sb.num_devices != 1) {
printf("%s: Unsupported number of devices (%lli). This driver "
   "only supports filesystem on one device.\n", __func__,
-- 
2.26.0

Re: [PATCH v3 3/3] configs: rpi_4_32b_defconfig: enable SDHCI_SDMA config

[Jaehoon Chung]

On 3/26/20 1:09 AM, Matthias Brugger wrote:
> 
> 
> On 24/03/2020 23:58, Jaehoon Chung wrote:
>> Enable SDHCI_SDMA configuration.
>>
>> Signed-off-by: Jaehoon Chung 
>> Reviewed-by: Peng Fan 
>> Reviewed-by: Minkyu Kang 
>> ---
>>  configs/rpi_4_32b_defconfig | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
>> index 72cda5d949..7189914606 100644
>> --- a/configs/rpi_4_32b_defconfig
>> +++ b/configs/rpi_4_32b_defconfig
>> @@ -25,6 +25,7 @@ CONFIG_DFU_MMC=y
>>  CONFIG_DM_KEYBOARD=y
>>  CONFIG_DM_MMC=y
>>  CONFIG_MMC_SDHCI=y
>> +CONFIG_MMC_SDHCI_SDMA=y
> 
> RPi4 can only do DMA transfers to the first GiB of memory. I wasn't sucessfull
> in understanding the mmc/sdhci code to see where we take the dma-ranges 
> property
> into account so that we don't use an address > 1 GiB.

Sorry i don't understand clearly what you said.

> 
> Are we safe in this regard? If we are, then we can also enable this for
> rpi_4_defconfig and rpi_arm64_defconfig I think.

I checked rpi_arm64_defconfig history. it's unified config for RPi3/RPI4.
As i know, RPi3 doesn't support SDMA mode. So i don't have a plan to apply 
rpi_arm64_defconfig.
(If i understood wrong, let me know,plz.)

I have tested SDMA mode With rpi_4_defconfig / rpi_4_32b_defconfig.
Test Environment
- Target : RPI4 (1G/2G/4G) target
- config : rpi_4_defconfig / rpi_4_32b_defconfig

Read/write some files from Sd-card.
Read/write performance is increased than before.

I will resend with rpi_4_defconfig, except rpi_arm64_defconfig.

Best Regards,
Jaehoon Chung

> 
> Regards,
> Matthias
> 
>>  CONFIG_MMC_SDHCI_BCM2835=y
>>  CONFIG_DM_ETH=y
>>  CONFIG_BCMGENET=y
>>
> 
> 

Re: [PATCH 1/7] arm: juno: Fix Juno address variables

[Tom Rini]

On Wed, Mar 25, 2020 at 02:46:56PM +, Andre Przywara wrote:

> The U-Boot documentation explains that variables ending with "_r" hold
> addresses in DRAM, while those without that ending point to flash/ROM.
> The default variables for the Juno board pointing to the kernel and DTB
> load addresses were not complying with this scheme: they lack the
> extension, but point to DRAM. This is particularly confusing since the
> Juno board features parallel NOR flash, so there *is* a memory mapped
> NOR address holding a DTB, for instance.
> 
> Fix the variables to use the proper names. On the way adjust the FDT
> load address to be situated *before* the kernel, since users happened
> to overwrite the DTB by the kernel clearing its .BSS section during
> initialisation.
> 
> That fixes loading debug kernels, which happened to overwrite the DTB on
> certain setups.
> 
> Signed-off-by: Andre Przywara 
> Reviewed-by: Liviu Dudau 
[snip]
> - "fdt_addr=0x8300\0" \
> + "fdt_addr_r=0x8000\0" \
>   "fdt_high=0x\0" \
>   "initrd_high=0x\0" \

On a related note, using fdt_high=0xff... to disable relocation is a bad
idea and can lead to U-Boot knowing we have it at an invalid (unaligned)
location but doing nothing and causing problems down the chain.  Please
use bootm_size or similar (documented in the README, still) to limit
where the fdt can be.  Thanks!

-- 
Tom


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Description: PGP signature

Re: [PATCH v1] x86: acpi: Describe USB 3 host controller found on Intel Tangier

[Bin Meng]

On Thu, Mar 26, 2020 at 12:46 AM Andy Shevchenko
 wrote:
>
> USB 3 host controller may be described in ACPI to allow users alter
> the properties or other features. Describe it for Intel Tangier SoC.
>
> Signed-off-by: Andy Shevchenko 
> ---
>  .../asm/arch-tangier/acpi/southcluster.asl| 38 +++
>  1 file changed, 38 insertions(+)
>
> diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl 
> b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
> index 6ccdc25136..953780a936 100644
> --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
> +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
> @@ -321,6 +321,44 @@ Device (PCI0)
>  }
>  }
>
> +Device (DWC3)
> +{
> +Name (_ADR, 0x0011)
> +Name (_DEP, Package ()
> +{
> +^IPC1.PMIC
> +})
> +
> +Method (_STA, 0, NotSerialized)
> +{
> +Return (STA_VISIBLE)
> +}
> +
> +Device (RHUB)
> +{
> +Name (_ADR, Zero)
> +
> +// GPLD: Generate Port Location Data (PLD)

nits: please use /* */

> +Method (GPLD, 1, Serialized) {
> +Name (PCKG, Package () {
> +Buffer (0x10) {}
> +})
> +
> +// REV: Revision 0x02 for ACPI 5.0
> +CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
> +Store (0x02, REV)
> +
> +// VISI: Port visibility to user per port
> +CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
> +Store (Arg0, VISI)
> +Return (PCKG)
> +}
> +
> +Device (HS01) { Name (_ADR, 1) }
> +Device (SS01) { Name (_ADR, 2) }
> +}
> +}
> +
>  Device (PWM0)
>  {
>  Name (_ADR, 0x0017)

Otherwise, looks good to me

Reviewed-by: Bin Meng 

[PATCH V2] ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2

[Marek Vasut]

Add DT entries, Kconfig entries and board-specific entries to configure
FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot.

Signed-off-by: Marek Vasut 
Cc: Patrick Delaunay 
Cc: Patrice Chotard 
---
V2: Configure FMC2 nCS4 for SRAM as well
---
 arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 68 ++
 board/dhelectronics/dh_stm32mp1/board.c| 27 +
 configs/stm32mp15_dhcom_basic_defconfig|  1 +
 3 files changed, 96 insertions(+)

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi 
b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index 6c952a57ee..eba3588540 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -37,6 +37,12 @@
default-state = "on";
};
};
+
+   /* This is actually on FMC2, but we do not have bus driver for that */
+   ksz8851: ks8851mll@6400 {
+   compatible = "micrel,ks8851-mll";
+   reg = <0x6400 0x2>;
+   };
 };
 
 &i2c4 {
@@ -50,6 +56,68 @@
};
 };
 
+&pinctrl {
+   /* These should bound to FMC2 bus driver, but we do not have one */
+   pinctrl-0 = <&fmc_pins_b>;
+   pinctrl-1 = <&fmc_sleep_pins_b>;
+   pinctrl-names = "default", "sleep";
+
+   fmc_pins_b: fmc-0 {
+   pins1 {
+   pinmux = , /* FMC_NOE */
+, /* FMC_NWE */
+, /* FMC_NL */
+, /* FMC_D0 */
+, /* FMC_D1 */
+, /* FMC_D2 */
+, /* FMC_D3 */
+, /* FMC_D4 */
+, /* FMC_D5 */
+, /* FMC_D6 */
+, /* FMC_D7 */
+, /* FMC_D8 */
+, /* FMC_D9 */
+, /* FMC_D10 */
+, /* FMC_D11 */
+, /* FMC_D12 */
+, /* FMC_D13 */
+, /* FMC_D14 */
+, /* FMC_D15 */
+, /* 
FMC_NE2_FMC_NCE */
+; /* FMC_NE4 */
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <3>;
+   };
+   };
+
+   fmc_sleep_pins_b: fmc-sleep-0 {
+   pins {
+   pinmux = , /* FMC_NOE */
+, /* FMC_NWE */
+, /* FMC_NL */
+, /* FMC_D0 */
+, /* FMC_D1 */
+, /* FMC_D2 */
+, /* FMC_D3 */
+, /* FMC_D4 */
+, /* FMC_D5 */
+, /* FMC_D6 */
+, /* FMC_D7 */
+, /* FMC_D8 */
+, /* FMC_D9 */
+, /* FMC_D10 */
+, /* FMC_D11 */
+, /* FMC_D12 */
+, /* FMC_D13 */
+, /* FMC_D14 */
+, /* FMC_D15 */
+, /* 
FMC_NE2_FMC_NCE */
+; /* FMC_NE4 */
+   };
+   };
+};
+
 &pmic {
u-boot,dm-pre-reloc;
 };
diff --git a/board/dhelectronics/dh_stm32mp1/board.c 
b/board/dhelectronics/dh_stm32mp1/board.c
index b663696983..26cdc15ded 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -376,6 +376,31 @@ static void sysconf_init(void)
 #endif
 }
 
+static void board_init_fmc2(void)
+{
+   /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
+#define FMC2_BASE  0x58002000
+#define FMC2_BCR1  0x0
+#define FMC2_BTR1  0x4
+#define FMC2_BWTR1 0x104
+#define FMC2_BCR(x)((x) * 0x8 + FMC2_BCR1)
+#define FMC2_BTR(x)((x) * 0x8 + FMC2_BTR1)
+#define FMC2_BWTR(x)   ((x) * 0x8 + FMC2_BWTR1)
+
+
+   writel(BIT(12), 0x5218);/* AHB6RSTCLRR */
+   writel(BIT(12), 0x519c);/* AHB6ENSETR */
+
+   /* KS8851-16MLL */
+   writel(0x10db, FMC2_BASE + FMC2_BCR(1));
+   writel(0xc002, FMC2_BASE + FMC2_BTR(1));
+   /* AS7C34098 SRAM on X11 */
+   writel(0x10db, FMC2_BASE + FMC2_BCR(3));
+   writel(0xc002, FMC2_BASE + FMC2_BTR(3));
+
+   setbits_le32(FMC2_BASE + FMC2_BCR1, BIT(31));
+}
+
 /* board dependent setup after realloc */
 int board_init(void)
 {
@@ -399,6 +424,8 @@ int board_init(void)
 
sysconf_init();
 
+   board_init_fmc2();
+
if (CONFIG_IS_ENABLED(CO

[PATCH] ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2

[Marek Vasut]

Add DT entries, Kconfig entries and board-specific entries to configure
FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot.

Signed-off-by: Marek Vasut 
Cc: Patrick Delaunay 
Cc: Patrice Chotard 
---
V2: Configure FMC2 nCS4 for SRAM as well
---
 arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 68 ++
 board/dhelectronics/dh_stm32mp1/board.c| 27 +
 configs/stm32mp15_dhcom_basic_defconfig|  1 +
 3 files changed, 96 insertions(+)

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi 
b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index 6c952a57ee..eba3588540 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -37,6 +37,12 @@
default-state = "on";
};
};
+
+   /* This is actually on FMC2, but we do not have bus driver for that */
+   ksz8851: ks8851mll@6400 {
+   compatible = "micrel,ks8851-mll";
+   reg = <0x6400 0x2>;
+   };
 };
 
 &i2c4 {
@@ -50,6 +56,68 @@
};
 };
 
+&pinctrl {
+   /* These should bound to FMC2 bus driver, but we do not have one */
+   pinctrl-0 = <&fmc_pins_b>;
+   pinctrl-1 = <&fmc_sleep_pins_b>;
+   pinctrl-names = "default", "sleep";
+
+   fmc_pins_b: fmc-0 {
+   pins1 {
+   pinmux = , /* FMC_NOE */
+, /* FMC_NWE */
+, /* FMC_NL */
+, /* FMC_D0 */
+, /* FMC_D1 */
+, /* FMC_D2 */
+, /* FMC_D3 */
+, /* FMC_D4 */
+, /* FMC_D5 */
+, /* FMC_D6 */
+, /* FMC_D7 */
+, /* FMC_D8 */
+, /* FMC_D9 */
+, /* FMC_D10 */
+, /* FMC_D11 */
+, /* FMC_D12 */
+, /* FMC_D13 */
+, /* FMC_D14 */
+, /* FMC_D15 */
+, /* 
FMC_NE2_FMC_NCE */
+; /* FMC_NE4 */
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <3>;
+   };
+   };
+
+   fmc_sleep_pins_b: fmc-sleep-0 {
+   pins {
+   pinmux = , /* FMC_NOE */
+, /* FMC_NWE */
+, /* FMC_NL */
+, /* FMC_D0 */
+, /* FMC_D1 */
+, /* FMC_D2 */
+, /* FMC_D3 */
+, /* FMC_D4 */
+, /* FMC_D5 */
+, /* FMC_D6 */
+, /* FMC_D7 */
+, /* FMC_D8 */
+, /* FMC_D9 */
+, /* FMC_D10 */
+, /* FMC_D11 */
+, /* FMC_D12 */
+, /* FMC_D13 */
+, /* FMC_D14 */
+, /* FMC_D15 */
+, /* 
FMC_NE2_FMC_NCE */
+; /* FMC_NE4 */
+   };
+   };
+};
+
 &pmic {
u-boot,dm-pre-reloc;
 };
diff --git a/board/dhelectronics/dh_stm32mp1/board.c 
b/board/dhelectronics/dh_stm32mp1/board.c
index b663696983..26cdc15ded 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -376,6 +376,31 @@ static void sysconf_init(void)
 #endif
 }
 
+static void board_init_fmc2(void)
+{
+   /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
+#define FMC2_BASE  0x58002000
+#define FMC2_BCR1  0x0
+#define FMC2_BTR1  0x4
+#define FMC2_BWTR1 0x104
+#define FMC2_BCR(x)((x) * 0x8 + FMC2_BCR1)
+#define FMC2_BTR(x)((x) * 0x8 + FMC2_BTR1)
+#define FMC2_BWTR(x)   ((x) * 0x8 + FMC2_BWTR1)
+
+
+   writel(BIT(12), 0x5218);/* AHB6RSTCLRR */
+   writel(BIT(12), 0x519c);/* AHB6ENSETR */
+
+   /* KS8851-16MLL */
+   writel(0x10db, FMC2_BASE + FMC2_BCR(1));
+   writel(0xc002, FMC2_BASE + FMC2_BTR(1));
+   /* AS7C34098 SRAM on X11 */
+   writel(0x10db, FMC2_BASE + FMC2_BCR(3));
+   writel(0xc002, FMC2_BASE + FMC2_BTR(3));
+
+   setbits_le32(FMC2_BASE + FMC2_BCR1, BIT(31));
+}
+
 /* board dependent setup after realloc */
 int board_init(void)
 {
@@ -399,6 +424,8 @@ int board_init(void)
 
sysconf_init();
 
+   board_init_fmc2();
+
if (CONFIG_IS_ENABLED(CO

[PATCH] MAINTAINERS: Add usb.h entry to usb

[Marek Vasut]

Add usb.h file into the USB list.

Signed-off-by: Marek Vasut 
Cc: Tom Rini 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 92dda40a85..9c1543f17d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -937,6 +937,7 @@ T:  git 
https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git
 F: drivers/usb/
 F: common/usb.c
 F: common/usb_kbd.c
+F: include/usb.h
 
 USB xHCI
 M: Bin Meng 
-- 
2.25.1

Re: [PATCH] fs: ext4: Fix alignment of cache buffers

[Stephen Warren]

On 3/25/20 2:27 PM, Jan Kiszka wrote:
> From: Jan Kiszka 
> 
> We need to align the cache buffer to ARCH_DMA_MINALIGN in order to avoid
> access errors like
> 
> CACHE: Misaligned operation at range [be0231e0, be0235e0]
> 
> seen on the MCIMX7SABRE.
> 
> Fixes: d5aee659f217 ("fs: ext4: cache extent data")
> Signed-off-by: Jan Kiszka 

Reviewed-by: Stephen Warren 

It's probably just a fluke that this happens to show up on some
SoCs/boards/configurations but not others. Or perhaps the MINALIGN value
differs?

Re: [PATCH] fs: ext4: Fix alignment of cache buffers

[Tom Rini]

On Wed, Mar 25, 2020 at 09:27:51PM +0100, Jan Kiszka wrote:

> From: Jan Kiszka 
> 
> We need to align the cache buffer to ARCH_DMA_MINALIGN in order to avoid
> access errors like
> 
> CACHE: Misaligned operation at range [be0231e0, be0235e0]
> 
> seen on the MCIMX7SABRE.
> 
> Fixes: d5aee659f217 ("fs: ext4: cache extent data")
> Signed-off-by: Jan Kiszka 
> ---
>  fs/ext4/ext4fs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
> index 1c616a26a2..966b427a97 100644
> --- a/fs/ext4/ext4fs.c
> +++ b/fs/ext4/ext4fs.c
> @@ -288,7 +288,7 @@ int ext_cache_read(struct ext_block_cache *cache, 
> lbaint_t block, int size)
>   if (cache->buf && cache->block == block && cache->size == size)
>   return 1;
>   ext_cache_fini(cache);
> - cache->buf = malloc(size);
> + cache->buf = memalign(ARCH_DMA_MINALIGN, size);
>   if (!cache->buf)
>   return 0;
>   if (!ext4fs_devread(block, 0, size, cache->buf)) {

Thanks for digging in to this.

Reviewed-by: Tom Rini 

-- 
Tom


signature.asc
Description: PGP signature

[PATCH] fs: ext4: Fix alignment of cache buffers

[Jan Kiszka]

From: Jan Kiszka 

We need to align the cache buffer to ARCH_DMA_MINALIGN in order to avoid
access errors like

CACHE: Misaligned operation at range [be0231e0, be0235e0]

seen on the MCIMX7SABRE.

Fixes: d5aee659f217 ("fs: ext4: cache extent data")
Signed-off-by: Jan Kiszka 
---
 fs/ext4/ext4fs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 1c616a26a2..966b427a97 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -288,7 +288,7 @@ int ext_cache_read(struct ext_block_cache *cache, lbaint_t 
block, int size)
if (cache->buf && cache->block == block && cache->size == size)
return 1;
ext_cache_fini(cache);
-   cache->buf = malloc(size);
+   cache->buf = memalign(ARCH_DMA_MINALIGN, size);
if (!cache->buf)
return 0;
if (!ext4fs_devread(block, 0, size, cache->buf)) {
-- 
2.16.4


-- 
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

RE: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

[Tom Warren]

-Original Message-
From: Stephen Warren  
Sent: Wednesday, March 25, 2020 12:31 PM
To: Tom Warren 
Cc: u-boot@lists.denx.de; Stephen Warren ; Thierry Reding 
; Jonathan Hunter ; 
tomcwarren3...@gmail.com
Subject: Re: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

External email: Use caution opening links or attachments


On 3/24/20 1:03 PM, twar...@nvidia.com wrote:
> From: Tom Warren 
>
> The Jetson Nano Developer Kit is a Tegra X1-based development board. 
> It is similar to Jetson TX1 but it is not pin compatible. It features 
> 4GB of LPDDR4, a SPI NOR flash for early boot firmware and an SD card 
> slot used for storage.
>
> HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 
> 2.0 and 1 USB 3.0) can be used to attach a variety of peripherals and 
> a PCI Ethernet controller provides onboard network connectivity. NVMe 
> support has also been added. Env save is at the end of QSPI (4MB-8K).
>
> A 40-pin header on the board can be used to extend the capabilities 
> and exposed interfaces of the Jetson Nano.

>  arch/arm/dts/tegra210-p3450-.dts | 147 
> +

This filename is consistent with other DT filenames in U-Boot, but there's been 
a movement downstream to name DT after baseboard plus module rather than 
combination, so tegra210-p3449-+p3448-.dts.
Either is probably fine for now since this board was released before the push 
towards the more descriptive naming.
[Tom] I'll stick with this naming, someone can float a change to move all Tegra 
boards to module+baseboard naming later if we so choose. This fits in the 
current U-Boot naming scheme.

> diff --git a/arch/arm/mach-tegra/board2.c 
> b/arch/arm/mach-tegra/board2.c

> +#if defined(CONFIG_DISABLE_SDMMC1_EARLY)
> + /*
> +  * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
> +  * We do this because earlier bootloaders have enabled power to
> +  * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
> +  * results in power being back-driven into the SD-card and SDMMC1
> +  * HW, which is 'bad' as per the HW team.
> +  *
> +  * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
> +  * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
> +  * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
> +  * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
> +  * voltage turns off. Since the SDCard voltage is no longer there, the
> +  * SDMMC CLK/DAT lines are backdriving into what essentially is a
> +  * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
> +  *
> +  * Note that this can probably be removed when we change over to storing
> +  * all BL components on QSPI on Nano, and U-Boot then becomes the first
> +  * one to turn on SDMMC1 power. Another fix would be to have CBoot
> +  * disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
> +  */
> + reset_set_enable(PERIPH_ID_SDMMC1, 1);
> + clock_set_enable(PERIPH_ID_SDMMC1, 0);
> +#endif   /* CONFIG_DISABLE_SDMMC1_EARLY */

I imagine we can remove this completely now that cboot does 100% of the pinmux 
init, so the referenced pinmux_init() function in U-Boot no longer causes a 
problem?
[Tom] That's a good point, but I'll have to engage w/the HW team to see if they 
can set up to measure the SD-card signals again w/o this change to see if the 
back-driving is gone.
I'd like to leave it in, though, as a precaution so we don't damage anyone's 
SD-cards. If/when we can re-measure it, I can float a new patch to remove the 
SDMMC1_EARLY switch and/or just remove this code entirely.

> diff --git a/board/nvidia/p3450-/p3450-.c 
> b/board/nvidia/p3450-/p3450-.c

> +static void ft_carveout_setup(void *fdt)

If/when we upstream the DT node/property copying feature, can this code be 
replaced by simply adding extra nodes/properties to the copy list?
[Tom] Good question, I'll look into it. I still need to finesse the FDT copy 
feature a bit, I'll look at it then.

> diff --git a/configs/p3450-_defconfig 
> b/configs/p3450-_defconfig

> +CONFIG_DISABLE_SDMMC1_EARLY=y

We can drop this assuming the code chunk I commented on above gets dropped.
[Tom] When I can get the HW team to re-measure SD card voltages w/o this I'll 
float a patch to remove it, assuming it looks good.

> +CONFIG_NVME=y

Does this work already? I thought it was still under development for Tegra.
[Tom] Yep, I bought a M.2 E key -> M.2 NVMe adapter for Nano & put a WD Black 
NVMe stick in it, and I can see/read/write the NVMe device in U-Boot using the 
'nvme' commands. And it visible in the kernel.  So for T210, it works (in 
U-Boot). Supporting NVMe in other bootloaders/SoCs that don’t use U-Boot is 
still a WIP.

--nvpublic

Re: ext4: invalid extent block on imx7

[Jan Kiszka]

On 25.03.20 21:01, Stephen Warren wrote:

On 3/25/20 1:11 PM, Jan Kiszka wrote:

On 25.03.20 16:00, Tom Rini wrote:

On Wed, Mar 25, 2020 at 07:32:30AM +0100, Jan Kiszka wrote:

On 20.03.20 19:21, Tom Rini wrote:

On Mon, Mar 16, 2020 at 08:09:53PM +0100, Jan Kiszka wrote:

Hi all,

=> ls mmc 0:1 /usr/lib/linux-image-4.9.11-1.3.0-dirty
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
invalid extent block

I'm using master (50be9f0e1ccc) on the MCIMX7SABRE, defconfig.

What could this be? The filesystem is fine from Linux POV.


Use tune2fs -l and see if there's any new'ish features enabled that we
need some sort of check-and-reject for would be my first guess.



Here are the reported feature flags:

has_journal ext_attr resize_inode dir_index filetype extent 64bit
flex_bg
sparse_super large_file huge_file dir_nlink extra_isize metadata_csum


Of that, only metadata_csum means that you can't write to that image,
but you're just trying to read and that should be fine.  Can you go back
in time a little and see if this problem persists or if it's been
introduced of late?  Or recreate it on other platforms/SoCs?  Thanks!



Bisected, regression of d5aee659f217 ("fs: ext4: cache extent data").
Reverting this commit over master resolves the issue.

Any idea what could be wrong? What I noticed is that the extent has a
zeroed magic when things go wrong, so maybe it is falsely considered to
be cached?


This is puzzling. I took another look at that patch and I don't see
anything wrong. My guess would be:

- Some unrelated memory corruption bug was exposed simply because this
patch uses dynamic memory or stack slightly differently than before.

- Something writes to the cached block, whereas the cache code assumes
the buffer is read-only.

The cache metadata exists on the stack and so only lasts for the
duration of read_allocated_block() or ext4fs_read_file(), so there's no
issue with re-using the cache across different devices, or persisting
across an ext4 write operation or anything like that. Is this easy to
reproduce; is there a small disk image that shows the problem?



Found it: alignment issue, apparently surfaced by your change when 
switching from zalloc (which does cacheline? alignment) to malloc. Is 
this sensitivity maybe SoC specific?


Jan

--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

Re: ext4: invalid extent block on imx7

[Stephen Warren]

On 3/25/20 1:11 PM, Jan Kiszka wrote:
> On 25.03.20 16:00, Tom Rini wrote:
>> On Wed, Mar 25, 2020 at 07:32:30AM +0100, Jan Kiszka wrote:
>>> On 20.03.20 19:21, Tom Rini wrote:
 On Mon, Mar 16, 2020 at 08:09:53PM +0100, Jan Kiszka wrote:
> Hi all,
>
> => ls mmc 0:1 /usr/lib/linux-image-4.9.11-1.3.0-dirty
> CACHE: Misaligned operation at range [bdfff998, bdfffd98]
> CACHE: Misaligned operation at range [bdfff998, bdfffd98]
> CACHE: Misaligned operation at range [bdfff998, bdfffd98]
> CACHE: Misaligned operation at range [bdfff998, bdfffd98]
> invalid extent block
>
> I'm using master (50be9f0e1ccc) on the MCIMX7SABRE, defconfig.
>
> What could this be? The filesystem is fine from Linux POV.

 Use tune2fs -l and see if there's any new'ish features enabled that we
 need some sort of check-and-reject for would be my first guess.

>>>
>>> Here are the reported feature flags:
>>>
>>> has_journal ext_attr resize_inode dir_index filetype extent 64bit
>>> flex_bg
>>> sparse_super large_file huge_file dir_nlink extra_isize metadata_csum
>>
>> Of that, only metadata_csum means that you can't write to that image,
>> but you're just trying to read and that should be fine.  Can you go back
>> in time a little and see if this problem persists or if it's been
>> introduced of late?  Or recreate it on other platforms/SoCs?  Thanks!
>>
> 
> Bisected, regression of d5aee659f217 ("fs: ext4: cache extent data").
> Reverting this commit over master resolves the issue.
> 
> Any idea what could be wrong? What I noticed is that the extent has a
> zeroed magic when things go wrong, so maybe it is falsely considered to
> be cached?

This is puzzling. I took another look at that patch and I don't see
anything wrong. My guess would be:

- Some unrelated memory corruption bug was exposed simply because this
patch uses dynamic memory or stack slightly differently than before.

- Something writes to the cached block, whereas the cache code assumes
the buffer is read-only.

The cache metadata exists on the stack and so only lasts for the
duration of read_allocated_block() or ext4fs_read_file(), so there's no
issue with re-using the cache across different devices, or persisting
across an ext4 write operation or anything like that. Is this easy to
reproduce; is there a small disk image that shows the problem?

Re: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

[Stephen Warren]

On 3/24/20 1:03 PM, twar...@nvidia.com wrote:
> From: Tom Warren 
> 
> The Jetson Nano Developer Kit is a Tegra X1-based development board. It
> is similar to Jetson TX1 but it is not pin compatible. It features 4GB
> of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot
> used for storage.
> 
> HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
> and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
> Ethernet controller provides onboard network connectivity. NVMe support
> has also been added. Env save is at the end of QSPI (4MB-8K).
> 
> A 40-pin header on the board can be used to extend the capabilities and
> exposed interfaces of the Jetson Nano.

>  arch/arm/dts/tegra210-p3450-.dts | 147 +

This filename is consistent with other DT filenames in U-Boot, but
there's been a movement downstream to name DT after baseboard plus
module rather than combination, so tegra210-p3449-+p3448-.dts.
Either is probably fine for now since this board was released before the
push towards the more descriptive naming.

> diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c

> +#if defined(CONFIG_DISABLE_SDMMC1_EARLY)
> + /*
> +  * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
> +  * We do this because earlier bootloaders have enabled power to
> +  * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
> +  * results in power being back-driven into the SD-card and SDMMC1
> +  * HW, which is 'bad' as per the HW team.
> +  *
> +  * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
> +  * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
> +  * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
> +  * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
> +  * voltage turns off. Since the SDCard voltage is no longer there, the
> +  * SDMMC CLK/DAT lines are backdriving into what essentially is a
> +  * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
> +  *
> +  * Note that this can probably be removed when we change over to storing
> +  * all BL components on QSPI on Nano, and U-Boot then becomes the first
> +  * one to turn on SDMMC1 power. Another fix would be to have CBoot
> +  * disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
> +  */
> + reset_set_enable(PERIPH_ID_SDMMC1, 1);
> + clock_set_enable(PERIPH_ID_SDMMC1, 0);
> +#endif   /* CONFIG_DISABLE_SDMMC1_EARLY */

I imagine we can remove this completely now that cboot does 100% of the
pinmux init, so the referenced pinmux_init() function in U-Boot no
longer causes a problem?

> diff --git a/board/nvidia/p3450-/p3450-.c 
> b/board/nvidia/p3450-/p3450-.c

> +static void ft_carveout_setup(void *fdt)

If/when we upstream the DT node/property copying feature, can this code
be replaced by simply adding extra nodes/properties to the copy list?

> diff --git a/configs/p3450-_defconfig b/configs/p3450-_defconfig

> +CONFIG_DISABLE_SDMMC1_EARLY=y

We can drop this assuming the code chunk I commented on above gets dropped.

> +CONFIG_NVME=y

Does this work already? I thought it was still under development for Tegra.

Re: ext4: invalid extent block on imx7

[Jan Kiszka]

On 25.03.20 16:00, Tom Rini wrote:

On Wed, Mar 25, 2020 at 07:32:30AM +0100, Jan Kiszka wrote:

On 20.03.20 19:21, Tom Rini wrote:

On Mon, Mar 16, 2020 at 08:09:53PM +0100, Jan Kiszka wrote:

Hi all,

=> ls mmc 0:1 /usr/lib/linux-image-4.9.11-1.3.0-dirty
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
invalid extent block

I'm using master (50be9f0e1ccc) on the MCIMX7SABRE, defconfig.

What could this be? The filesystem is fine from Linux POV.


Use tune2fs -l and see if there's any new'ish features enabled that we
need some sort of check-and-reject for would be my first guess.



Here are the reported feature flags:

has_journal ext_attr resize_inode dir_index filetype extent 64bit flex_bg
sparse_super large_file huge_file dir_nlink extra_isize metadata_csum


Of that, only metadata_csum means that you can't write to that image,
but you're just trying to read and that should be fine.  Can you go back
in time a little and see if this problem persists or if it's been
introduced of late?  Or recreate it on other platforms/SoCs?  Thanks!



Bisected, regression of d5aee659f217 ("fs: ext4: cache extent data"). 
Reverting this commit over master resolves the issue.


Any idea what could be wrong? What I noticed is that the extent has a 
zeroed magic when things go wrong, so maybe it is falsely considered to 
be cached?


Jan


Anything too fancy in here? But the method of creating this filesystem does
not deviate from many other setups we have for U-Boot (on other boards).


Yes, but for some time now e2fsprogs has introduced new default features
that require compatibility checks.



--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

[PATCH] ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2

[Marek Vasut]

Add DT entries, Kconfig entries and board-specific entries to configure
FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot.

Signed-off-by: Marek Vasut 
Cc: Patrick Delaunay 
Cc: Patrice Chotard 
---
 arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 66 ++
 board/dhelectronics/dh_stm32mp1/board.c| 19 +++
 configs/stm32mp15_dhcom_basic_defconfig|  1 +
 3 files changed, 86 insertions(+)

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi 
b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index 6c952a57ee..9f5b5f11f9 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -37,6 +37,12 @@
default-state = "on";
};
};
+
+   /* This is actually on FMC2, but we do not have bus driver for that */
+   ksz8851: ks8851mll@6400 {
+   compatible = "micrel,ks8851-mll";
+   reg = <0x6400 0x2>;
+   };
 };
 
 &i2c4 {
@@ -50,6 +56,66 @@
};
 };
 
+&pinctrl {
+   /* These should bound to FMC2 bus driver, but we do not have one */
+   pinctrl-0 = <&fmc_pins_b>;
+   pinctrl-1 = <&fmc_sleep_pins_b>;
+   pinctrl-names = "default", "sleep";
+
+   fmc_pins_b: fmc-0 {
+   pins1 {
+   pinmux = , /* FMC_NOE */
+, /* FMC_NWE */
+, /* FMC_NL */
+, /* FMC_D0 */
+, /* FMC_D1 */
+, /* FMC_D2 */
+, /* FMC_D3 */
+, /* FMC_D4 */
+, /* FMC_D5 */
+, /* FMC_D6 */
+, /* FMC_D7 */
+, /* FMC_D8 */
+, /* FMC_D9 */
+, /* FMC_D10 */
+, /* FMC_D11 */
+, /* FMC_D12 */
+, /* FMC_D13 */
+, /* FMC_D14 */
+, /* FMC_D15 */
+; /* 
FMC_NE2_FMC_NCE */
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <3>;
+   };
+   };
+
+   fmc_sleep_pins_b: fmc-sleep-0 {
+   pins {
+   pinmux = , /* FMC_NOE */
+, /* FMC_NWE */
+, /* FMC_NL */
+, /* FMC_D0 */
+, /* FMC_D1 */
+, /* FMC_D2 */
+, /* FMC_D3 */
+, /* FMC_D4 */
+, /* FMC_D5 */
+, /* FMC_D6 */
+, /* FMC_D7 */
+, /* FMC_D8 */
+, /* FMC_D9 */
+, /* FMC_D10 */
+, /* FMC_D11 */
+, /* FMC_D12 */
+, /* FMC_D13 */
+, /* FMC_D14 */
+, /* FMC_D15 */
+; /* 
FMC_NE2_FMC_NCE */
+   };
+   };
+};
+
 &pmic {
u-boot,dm-pre-reloc;
 };
diff --git a/board/dhelectronics/dh_stm32mp1/board.c 
b/board/dhelectronics/dh_stm32mp1/board.c
index b663696983..2617bc5167 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -376,6 +376,23 @@ static void sysconf_init(void)
 #endif
 }
 
+static void board_init_fmc2(void)
+{
+   /* Set up FMC2 bus for KS8851-16MLL */
+#define FMC2_BASE  0x58002000
+#define FMC2_BCR1  0x0
+#define FMC2_BTR1  0x4
+#define FMC2_BCR(x)((x) * 0x8 + FMC2_BCR1)
+#define FMC2_BTR(x)((x) * 0x8 + FMC2_BTR1)
+
+   writel(BIT(12), 0x5218);/* AHB6RSTCLRR */
+   writel(BIT(12), 0x519c);/* AHB6ENSETR */
+
+   writel(0xc002, FMC2_BASE + FMC2_BTR(1));
+   writel(0x10db, FMC2_BASE + FMC2_BCR(1));
+   setbits_le32(FMC2_BASE + FMC2_BCR1, BIT(31));
+}
+
 /* board dependent setup after realloc */
 int board_init(void)
 {
@@ -399,6 +416,8 @@ int board_init(void)
 
sysconf_init();
 
+   board_init_fmc2();
+
if (CONFIG_IS_ENABLED(CONFIG_LED))
led_default_state();
 
diff --git a/configs/stm32mp15_dhcom_basic_defconfig 
b/configs/stm32mp15_dhcom_basic_defconfig
index 921dea242a..683f15e7d5 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -93,6 +93,7 @@ CONFIG_SPI_FLASH_MTD=y
 CONFIG_SPL_SPI_FLASH_MTD=y
 CONFIG_DM_ETH=y
 CONFIG_DWC_ETH_QOS=y
+CONFIG_KS8851_MLL=y
 CONFIG

[PATCH 12/12] net: ks8851: Add Kconfig entries

[Marek Vasut]

Convert CONFIG_KS8851_MLL and CONFIG_KS8851_MLL_BASEADDR to Kconfig

Signed-off-by: Marek Vasut 
Cc: Eugen Hristev 
Cc: Joe Hershberger 
---
 configs/at91sam9n12ek_mmc_defconfig   |  2 ++
 configs/at91sam9n12ek_nandflash_defconfig |  2 ++
 configs/at91sam9n12ek_spiflash_defconfig  |  2 ++
 drivers/net/Kconfig   | 14 ++
 include/configs/at91sam9n12ek.h   |  3 ---
 scripts/config_whitelist.txt  |  2 --
 6 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/configs/at91sam9n12ek_mmc_defconfig 
b/configs/at91sam9n12ek_mmc_defconfig
index 075daa79d3..308f097b60 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -47,6 +47,8 @@ CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=3000
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_KS8851_MLL=y
+CONFIG_KS8851_MLL_BASEADDR=0x3000
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/at91sam9n12ek_nandflash_defconfig 
b/configs/at91sam9n12ek_nandflash_defconfig
index b02be84493..fd6d13db9b 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -48,6 +48,8 @@ CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=3000
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_KS8851_MLL=y
+CONFIG_KS8851_MLL_BASEADDR=0x3000
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig 
b/configs/at91sam9n12ek_spiflash_defconfig
index f816d27a55..1beb3bb648 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -49,6 +49,8 @@ CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=3000
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_KS8851_MLL=y
+CONFIG_KS8851_MLL_BASEADDR=0x3000
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4d1013c984..29e185adab 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -301,6 +301,20 @@ config FSLDMAFEC
  This driver supports the network interface units in the
  ColdFire family.
 
+config KS8851_MLL
+   bool "Microchip KS8851-MLL controller driver"
+   help
+ The Microchip KS8851 parallel bus external ethernet interface chip.
+
+if KS8851_MLL
+if !DM_ETH
+config KS8851_MLL_BASEADDR
+   hex "Microchip KS8851-MLL Base Address"
+   help
+ Define this to hold the physical address of the device (I/O space)
+endif #DM_ETH
+endif #KS8851_MLL
+
 config MVGBE
bool "Marvell Orion5x/Kirkwood network interface support"
depends on KIRKWOOD || ORION5X
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index caa487b038..7916c6792a 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -63,9 +63,6 @@
"bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
 
 /* Ethernet */
-#define CONFIG_KS8851_MLL
-#define CONFIG_KS8851_MLL_BASEADDR 0x3000 /* use NCS2 */
-
 #define CONFIG_SYS_LOAD_ADDR   0x2200 /* load address */
 
 #define CONFIG_SYS_MEMTEST_START   CONFIG_SYS_SDRAM_BASE
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 6908431d03..dba74593b4 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -948,8 +948,6 @@ CONFIG_KONA
 CONFIG_KONA_GPIO
 CONFIG_KONA_RESET_S
 CONFIG_KPROBES
-CONFIG_KS8851_MLL
-CONFIG_KS8851_MLL_BASEADDR
 CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE
 CONFIG_KSNAV_NETCP_PDMA_RX_BASE
 CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM
-- 
2.25.1

[PATCH 10/12] net: ks8851: Receive one packet per recv call

[Marek Vasut]

Instead of reading out the entire FIFO and possibly overwriting U-Boot
memory, read out one packet per recv call, pass it to U-Boot network
stack, and repeat. It is however necessary to cache RXFC value, because
reading that one out clears it.

Signed-off-by: Marek Vasut 
Cc: Eugen Hristev 
Cc: Joe Hershberger 
---
 drivers/net/ks8851_mll.c | 65 ++--
 1 file changed, 36 insertions(+), 29 deletions(-)

diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c
index d70f0a4dc2..5a566d1c66 100644
--- a/drivers/net/ks8851_mll.c
+++ b/drivers/net/ks8851_mll.c
@@ -30,6 +30,7 @@ struct ks_net {
phys_addr_t iobase;
int bus_width;
u16 sharedbus;
+   u16 rxfc;
u8  extra_byte;
 };
 
@@ -223,33 +224,31 @@ static inline void ks_read_qmu(struct ks_net *ks, u16 
*buf, u32 len)
ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
 }
 
-static void ks_rcv(struct ks_net *ks, uchar **pv_data)
+static int ks_rcv(struct ks_net *ks, uchar *data)
 {
-   unsigned int frame_cnt;
u16 sts, len;
-   int i;
-
-   frame_cnt = ks_rdreg16(ks, KS_RXFCTR) >> 8;
-
-   /* read all header information */
-   for (i = 0; i < frame_cnt; i++) {
-   /* Checking Received packet status */
-   sts = ks_rdreg16(ks, KS_RXFHSR);
-   /* Get packet len from hardware */
-   len = ks_rdreg16(ks, KS_RXFHBCR);
-
-   if ((sts & RXFSHR_RXFV) && len && (len < RX_BUF_SIZE)) {
-   /* read data block including CRC 4 bytes */
-   ks_read_qmu(ks, (u16 *)(*pv_data), len);
-
-   /* net_rx_packets buffer size is ok (*pv_data) */
-   net_process_received_packet(*pv_data, len);
-   pv_data++;
-   } else {
-   ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF);
-   printf(DRIVERNAME ": bad packet\n");
-   }
+
+   if (!ks->rxfc)
+   ks->rxfc = ks_rdreg16(ks, KS_RXFCTR) >> 8;
+
+   if (!ks->rxfc)
+   return 0;
+
+   /* Checking Received packet status */
+   sts = ks_rdreg16(ks, KS_RXFHSR);
+   /* Get packet len from hardware */
+   len = ks_rdreg16(ks, KS_RXFHBCR);
+
+   if ((sts & RXFSHR_RXFV) && len && (len < RX_BUF_SIZE)) {
+   /* read data block including CRC 4 bytes */
+   ks_read_qmu(ks, (u16 *)data, len);
+   ks->rxfc--;
+   return len - 4;
}
+
+   ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF);
+   printf(DRIVERNAME ": bad packet\n");
+   return 0;
 }
 
 /*
@@ -405,6 +404,8 @@ static int ks8851_mll_init_common(struct ks_net *ks)
/* Configure the PHY, initialize the link state */
ks8851_mll_phy_configure(ks);
 
+   ks->rxfc = 0;
+
/* Turn on Tx + Rx */
ks8851_mll_enable(ks);
 
@@ -464,16 +465,17 @@ static void ks8851_mll_halt_common(struct ks_net *ks)
  * needs to be enough to prevent a packet being discarded while
  * we are processing the previous one.
  */
-static int ks8851_mll_recv_common(struct ks_net *ks, uchar **data)
+static int ks8851_mll_recv_common(struct ks_net *ks, uchar *data)
 {
u16 status;
+   int ret = 0;
 
status = ks_rdreg16(ks, KS_ISR);
 
ks_wrreg16(ks, KS_ISR, status);
 
-   if (status & IRQ_RXI)
-   ks_rcv(ks, data);
+   if (ks->rxfc || (status & IRQ_RXI))
+   ret = ks_rcv(ks, data);
 
if (status & IRQ_LDI) {
u16 pmecr = ks_rdreg16(ks, KS_PMECR);
@@ -482,7 +484,7 @@ static int ks8851_mll_recv_common(struct ks_net *ks, uchar 
**data)
ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
}
 
-   return 0;
+   return ret;
 }
 
 static void ks8851_mll_write_hwaddr_common(struct ks_net *ks, u8 enetaddr[6])
@@ -522,8 +524,13 @@ static int ks8851_mll_send(struct eth_device *dev, void 
*packet, int length)
 static int ks8851_mll_recv(struct eth_device *dev)
 {
struct ks_net *ks = container_of(dev, struct ks_net, dev);
+   int ret;
+
+   ret = ks8851_mll_recv_common(ks, net_rx_packets[0]);
+   if (ret)
+   net_process_received_packet(net_rx_packets[0], ret);
 
-   return ks8851_mll_recv_common(ks, (uchar **)net_rx_packets);
+   return ret;
 }
 
 static int ks8851_mll_write_hwaddr(struct eth_device *dev)
-- 
2.25.1

[PATCH 11/12] net: ks8851: Add DM support

[Marek Vasut]

Add support for U-Boot DM and DT probing.

Signed-off-by: Marek Vasut 
Cc: Eugen Hristev 
Cc: Joe Hershberger 
---
 drivers/net/ks8851_mll.c | 103 +++
 1 file changed, 103 insertions(+)

diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c
index 5a566d1c66..279cf71332 100644
--- a/drivers/net/ks8851_mll.c
+++ b/drivers/net/ks8851_mll.c
@@ -26,7 +26,9 @@
  * @extra_byte : number of extra byte prepended rx pkt.
  */
 struct ks_net {
+#ifndef CONFIG_DM_ETH
struct eth_device   dev;
+#endif
phys_addr_t iobase;
int bus_width;
u16 sharedbus;
@@ -500,6 +502,7 @@ static void ks8851_mll_write_hwaddr_common(struct ks_net 
*ks, u8 enetaddr[6])
ks_wrreg16(ks, KS_MARL, addrl);
 }
 
+#ifndef CONFIG_DM_ETH
 static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
 {
struct ks_net *ks = container_of(dev, struct ks_net, dev);
@@ -569,3 +572,103 @@ int ks8851_mll_initialize(u8 dev_num, int base_addr)
 
return 0;
 }
+#else  /* ifdef CONFIG_DM_ETH */
+static int ks8851_start(struct udevice *dev)
+{
+   struct ks_net *ks = dev_get_priv(dev);
+
+   return ks8851_mll_init_common(ks);
+}
+
+static void ks8851_stop(struct udevice *dev)
+{
+   struct ks_net *ks = dev_get_priv(dev);
+
+   ks8851_mll_halt_common(ks);
+}
+
+static int ks8851_send(struct udevice *dev, void *packet, int length)
+{
+   struct ks_net *ks = dev_get_priv(dev);
+   int ret;
+
+   ret = ks8851_mll_send_common(ks, packet, length);
+
+   return ret ? 0 : -ETIMEDOUT;
+}
+
+static int ks8851_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+   struct ks_net *ks = dev_get_priv(dev);
+   uchar *data = net_rx_packets[0];
+   int ret;
+
+   ret = ks8851_mll_recv_common(ks, data);
+   if (ret)
+   *packetp = (void *)data;
+
+   return ret ? ret : -EAGAIN;
+}
+
+static int ks8851_write_hwaddr(struct udevice *dev)
+{
+   struct ks_net *ks = dev_get_priv(dev);
+   struct eth_pdata *pdata = dev_get_platdata(dev);
+
+   ks8851_mll_write_hwaddr_common(ks, pdata->enetaddr);
+
+   return 0;
+}
+
+static int ks8851_bind(struct udevice *dev)
+{
+   return device_set_name(dev, dev->name);
+}
+
+static int ks8851_probe(struct udevice *dev)
+{
+   struct ks_net *ks = dev_get_priv(dev);
+
+   /* Try to detect chip. Will fail if not present. */
+   ks8851_mll_detect_chip(ks);
+
+   return 0;
+}
+
+static int ks8851_ofdata_to_platdata(struct udevice *dev)
+{
+   struct ks_net *ks = dev_get_priv(dev);
+   struct eth_pdata *pdata = dev_get_platdata(dev);
+
+   pdata->iobase = devfdt_get_addr(dev);
+   ks->iobase = pdata->iobase;
+
+   return 0;
+}
+
+static const struct eth_ops ks8851_ops = {
+   .start  = ks8851_start,
+   .stop   = ks8851_stop,
+   .send   = ks8851_send,
+   .recv   = ks8851_recv,
+   .write_hwaddr   = ks8851_write_hwaddr,
+};
+
+static const struct udevice_id ks8851_ids[] = {
+   { .compatible = "micrel,ks8851-mll" },
+   { }
+};
+
+U_BOOT_DRIVER(ks8851) = {
+   .name   = "eth_ks8851",
+   .id = UCLASS_ETH,
+   .of_match   = ks8851_ids,
+   .bind   = ks8851_bind,
+   .ofdata_to_platdata = ks8851_ofdata_to_platdata,
+   .probe  = ks8851_probe,
+   .ops= &ks8851_ops,
+   .priv_auto_alloc_size = sizeof(struct ks_net),
+   .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+   .flags  = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
-- 
2.25.1

[PATCH 09/12] net: ks8851: Split non-DM specific bits from common code

[Marek Vasut]

Split network handling functions into non-DM specific parts and
common code in preparation for conversion to DM.

Signed-off-by: Marek Vasut 
Cc: Eugen Hristev 
Cc: Joe Hershberger 
---
 drivers/net/ks8851_mll.c | 60 +---
 1 file changed, 44 insertions(+), 16 deletions(-)

diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c
index a59ce0e81a..d70f0a4dc2 100644
--- a/drivers/net/ks8851_mll.c
+++ b/drivers/net/ks8851_mll.c
@@ -393,10 +393,8 @@ static void ks8851_mll_enable(struct ks_net *ks)
ks_enable_qmu(ks);
 }
 
-static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
+static int ks8851_mll_init_common(struct ks_net *ks)
 {
-   struct ks_net *ks = container_of(dev, struct ks_net, dev);
-
if (ks_read_selftest(ks)) {
printf(DRIVERNAME ": Selftest failed\n");
return -1;
@@ -435,9 +433,8 @@ static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 
len)
do { } while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE);
 }
 
-static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
+static int ks8851_mll_send_common(struct ks_net *ks, void *packet, int length)
 {
-   struct ks_net *ks = container_of(dev, struct ks_net, dev);
u8 *data = (u8 *)packet;
u16 tmplen = (u16)length;
u16 retv;
@@ -456,10 +453,8 @@ static int ks8851_mll_send(struct eth_device *dev, void 
*packet, int length)
return -1;
 }
 
-static void ks8851_mll_halt(struct eth_device *dev)
+static void ks8851_mll_halt_common(struct ks_net *ks)
 {
-   struct ks_net *ks = container_of(dev, struct ks_net, dev);
-
ks8851_mll_reset(ks);
 }
 
@@ -469,9 +464,8 @@ static void ks8851_mll_halt(struct eth_device *dev)
  * needs to be enough to prevent a packet being discarded while
  * we are processing the previous one.
  */
-static int ks8851_mll_recv(struct eth_device *dev)
+static int ks8851_mll_recv_common(struct ks_net *ks, uchar **data)
 {
-   struct ks_net *ks = container_of(dev, struct ks_net, dev);
u16 status;
 
status = ks_rdreg16(ks, KS_ISR);
@@ -479,7 +473,7 @@ static int ks8851_mll_recv(struct eth_device *dev)
ks_wrreg16(ks, KS_ISR, status);
 
if (status & IRQ_RXI)
-   ks_rcv(ks, (uchar **)net_rx_packets);
+   ks_rcv(ks, data);
 
if (status & IRQ_LDI) {
u16 pmecr = ks_rdreg16(ks, KS_PMECR);
@@ -491,18 +485,52 @@ static int ks8851_mll_recv(struct eth_device *dev)
return 0;
 }
 
-static int ks8851_mll_write_hwaddr(struct eth_device *dev)
+static void ks8851_mll_write_hwaddr_common(struct ks_net *ks, u8 enetaddr[6])
 {
-   struct ks_net *ks = container_of(dev, struct ks_net, dev);
u16 addrl, addrm, addrh;
 
-   addrh = (ks->dev.enetaddr[0] << 8) | ks->dev.enetaddr[1];
-   addrm = (ks->dev.enetaddr[2] << 8) | ks->dev.enetaddr[3];
-   addrl = (ks->dev.enetaddr[4] << 8) | ks->dev.enetaddr[5];
+   addrh = (enetaddr[0] << 8) | enetaddr[1];
+   addrm = (enetaddr[2] << 8) | enetaddr[3];
+   addrl = (enetaddr[4] << 8) | enetaddr[5];
 
ks_wrreg16(ks, KS_MARH, addrh);
ks_wrreg16(ks, KS_MARM, addrm);
ks_wrreg16(ks, KS_MARL, addrl);
+}
+
+static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
+{
+   struct ks_net *ks = container_of(dev, struct ks_net, dev);
+
+   return ks8851_mll_init_common(ks);
+}
+
+static void ks8851_mll_halt(struct eth_device *dev)
+{
+   struct ks_net *ks = container_of(dev, struct ks_net, dev);
+
+   ks8851_mll_halt_common(ks);
+}
+
+static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
+{
+   struct ks_net *ks = container_of(dev, struct ks_net, dev);
+
+   return ks8851_mll_send_common(ks, packet, length);
+}
+
+static int ks8851_mll_recv(struct eth_device *dev)
+{
+   struct ks_net *ks = container_of(dev, struct ks_net, dev);
+
+   return ks8851_mll_recv_common(ks, (uchar **)net_rx_packets);
+}
+
+static int ks8851_mll_write_hwaddr(struct eth_device *dev)
+{
+   struct ks_net *ks = container_of(dev, struct ks_net, dev);
+
+   ks8851_mll_write_hwaddr_common(ks, ks->dev.enetaddr);
 
return 0;
 }
-- 
2.25.1

[PATCH 08/12] net: ks8851: Pass around driver private data

[Marek Vasut]

Introduce a private data structure for this driver with embedded
struct eth_device and pass it around. This prepares the driver to
work with both DM and non-DM systems.

Signed-off-by: Marek Vasut 
Cc: Eugen Hristev 
Cc: Joe Hershberger 
---
 drivers/net/ks8851_mll.c | 257 ---
 1 file changed, 133 insertions(+), 124 deletions(-)

diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c
index 54a273aa69..a59ce0e81a 100644
--- a/drivers/net/ks8851_mll.c
+++ b/drivers/net/ks8851_mll.c
@@ -19,42 +19,46 @@
 
 /*
  * struct ks_net - KS8851 driver private data
+ * @dev: legacy non-DM ethernet device structure
+ * @iobase : register base
  * @bus_width  : i/o bus width.
  * @sharedbus  : Multipex(addr and data bus) mode indicator.
  * @extra_byte : number of extra byte prepended rx pkt.
  */
 struct ks_net {
+   struct eth_device   dev;
+   phys_addr_t iobase;
int bus_width;
u16 sharedbus;
u8  extra_byte;
-} ks_str, *ks;
+};
 
 #define BE3 0x8000  /* Byte Enable 3 */
 #define BE2 0x4000  /* Byte Enable 2 */
 #define BE1 0x2000  /* Byte Enable 1 */
 #define BE0 0x1000  /* Byte Enable 0 */
 
-static u8 ks_rdreg8(struct eth_device *dev, u16 offset)
+static u8 ks_rdreg8(struct ks_net *ks, u16 offset)
 {
u8 shift_bit = offset & 0x03;
u8 shift_data = (offset & 1) << 3;
 
-   writew(offset | (BE0 << shift_bit), dev->iobase + 2);
+   writew(offset | (BE0 << shift_bit), ks->iobase + 2);
 
-   return (u8)(readw(dev->iobase) >> shift_data);
+   return (u8)(readw(ks->iobase) >> shift_data);
 }
 
-static u16 ks_rdreg16(struct eth_device *dev, u16 offset)
+static u16 ks_rdreg16(struct ks_net *ks, u16 offset)
 {
-   writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
+   writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
 
-   return readw(dev->iobase);
+   return readw(ks->iobase);
 }
 
-static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val)
+static void ks_wrreg16(struct ks_net *ks, u16 offset, u16 val)
 {
-   writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
-   writew(val, dev->iobase);
+   writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
+   writew(val, ks->iobase);
 }
 
 /*
@@ -64,12 +68,12 @@ static void ks_wrreg16(struct eth_device *dev, u16 offset, 
u16 val)
  * @wptr: buffer address to save data
  * @len: length in byte to read
  */
-static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len)
+static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len)
 {
len >>= 1;
 
while (len--)
-   *wptr++ = readw(dev->iobase);
+   *wptr++ = readw(ks->iobase);
 }
 
 /*
@@ -78,42 +82,42 @@ static inline void ks_inblk(struct eth_device *dev, u16 
*wptr, u32 len)
  * @wptr: buffer address
  * @len: length in byte to write
  */
-static inline void ks_outblk(struct eth_device *dev, u16 *wptr, u32 len)
+static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
 {
len >>= 1;
 
while (len--)
-   writew(*wptr++, dev->iobase);
+   writew(*wptr++, ks->iobase);
 }
 
-static void ks_enable_int(struct eth_device *dev)
+static void ks_enable_int(struct ks_net *ks)
 {
-   ks_wrreg16(dev, KS_IER, IRQ_LCI | IRQ_TXI | IRQ_RXI);
+   ks_wrreg16(ks, KS_IER, IRQ_LCI | IRQ_TXI | IRQ_RXI);
 }
 
-static void ks_set_powermode(struct eth_device *dev, unsigned int pwrmode)
+static void ks_set_powermode(struct ks_net *ks, unsigned int pwrmode)
 {
unsigned int pmecr;
 
-   ks_rdreg16(dev, KS_GRR);
-   pmecr = ks_rdreg16(dev, KS_PMECR);
+   ks_rdreg16(ks, KS_GRR);
+   pmecr = ks_rdreg16(ks, KS_PMECR);
pmecr &= ~PMECR_PM_MASK;
pmecr |= pwrmode;
 
-   ks_wrreg16(dev, KS_PMECR, pmecr);
+   ks_wrreg16(ks, KS_PMECR, pmecr);
 }
 
 /*
  * ks_read_config - read chip configuration of bus width.
  * @ks: The chip information
  */
-static void ks_read_config(struct eth_device *dev)
+static void ks_read_config(struct ks_net *ks)
 {
u16 reg_data = 0;
 
/* Regardless of bus width, 8 bit read should always work. */
-   reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF;
-   reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8;
+   reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF;
+   reg_data |= ks_rdreg8(ks, KS_CCR + 1) << 8;
 
/* addr/data bus are multiplexed */
ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
@@ -147,58 +151,58 @@ static void ks_read_config(struct eth_device *dev)
  * not currently specify the exact sequence, we have chosen something
  * that seems to work with our device.
  */
-static void ks_soft_reset(struct eth_device *dev, unsigned int op)
+static void ks_soft_reset(struct ks_net *ks, uns

[PATCH 06/12] net: ks8851: Clean up chip ID readout

[Marek Vasut]

There is only one chip ID in the table of chip IDs for this chip.
Read out the chip ID instead and mask off the last "revision" bit
to check the chip ID, this works for all chips in the family. Then
drop the chip ID passing around.

Signed-off-by: Marek Vasut 
Cc: Eugen Hristev 
Cc: Joe Hershberger 
---
 drivers/net/ks8851_mll.c | 21 ++---
 1 file changed, 2 insertions(+), 19 deletions(-)

diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c
index 2d854d855d..503da7a3bf 100644
--- a/drivers/net/ks8851_mll.c
+++ b/drivers/net/ks8851_mll.c
@@ -17,11 +17,6 @@
 
 #define RX_BUF_SIZE2000
 
-static const struct chip_id chip_ids[] =  {
-   {CIDER_ID, "KSZ8851"},
-   {0, NULL},
-};
-
 /*
  * struct ks_net - KS8851 driver private data
  * @bus_width  : i/o bus width.
@@ -331,7 +326,7 @@ static void ks_setup_int(struct eth_device *dev)
 
 static int ks8851_mll_detect_chip(struct eth_device *dev)
 {
-   unsigned short val, i;
+   unsigned short val;
 
ks_read_config(dev);
 
@@ -348,19 +343,11 @@ static int ks8851_mll_detect_chip(struct eth_device *dev)
 
debug("Read back KS8851 id 0x%x\n", val);
 
-   /* only one entry in the table */
-   val &= 0xfff0;
-   for (i = 0; chip_ids[i].id != 0; i++) {
-   if (chip_ids[i].id == val)
-   break;
-   }
-   if (!chip_ids[i].id) {
+   if ((val & 0xfff0) != CIDER_ID) {
printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
return -1;
}
 
-   dev->priv = (void *)&chip_ids[i];
-
return 0;
 }
 
@@ -404,10 +391,6 @@ static void ks8851_mll_enable(struct eth_device *dev)
 
 static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
 {
-   struct chip_id *id = dev->priv;
-
-   debug(DRIVERNAME ": detected %s controller\n", id->name);
-
if (ks_read_selftest(dev)) {
printf(DRIVERNAME ": Selftest failed\n");
return -1;
-- 
2.25.1

[PATCH 04/12] net: ks8851: Trim down struct ks_net

[Marek Vasut]

Most of the entries in the structure are useless, remove them. Inline
the rest of uses where applicable.

Signed-off-by: Marek Vasut 
Cc: Eugen Hristev 
Cc: Joe Hershberger 
---
 drivers/net/ks8851_mll.c | 70 ++--
 1 file changed, 9 insertions(+), 61 deletions(-)

diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c
index c60c2183a1..7d6328afab 100644
--- a/drivers/net/ks8851_mll.c
+++ b/drivers/net/ks8851_mll.c
@@ -25,44 +25,12 @@ static const struct chip_id chip_ids[] =  {
{0, NULL},
 };
 
-/*
- * union ks_tx_hdr - tx header data
- * @txb: The header as bytes
- * @txw: The header as 16bit, little-endian words
- *
- * A dual representation of the tx header data to allow
- * access to individual bytes, and to allow 16bit accesses
- * with 16bit alignment.
- */
-union ks_tx_hdr {
-   u8  txb[4];
-   __le16  txw[2];
-};
-
 /*
  * struct ks_net - KS8851 driver private data
- * @net_device : The network device we're bound to
- * @txh: temporaly buffer to save status/length.
  * @frame_head_info: frame header information for multi-pkt rx.
- * @statelock  : Lock on this structure for tx list.
- * @msg_enable : The message flags controlling driver output (see ethtool).
- * @frame_cnt  : number of frames received.
  * @bus_width  : i/o bus width.
- * @irq: irq number assigned to this device.
- * @rc_txcr: Cached copy of KS_TXCR.
- * @rc_ier : Cached copy of KS_IER.
  * @sharedbus  : Multipex(addr and data bus) mode indicator.
- * @cmd_reg_cache  : command register cached.
- * @cmd_reg_cache_int  : command register cached. Used in the irq handler.
- * @promiscuous: promiscuous mode indicator.
- * @all_mcast  : mutlicast indicator.
- * @mcast_lst_size : size of multicast list.
- * @mcast_lst  : multicast list.
- * @mcast_bits : multicast enabed.
- * @mac_addr   : MAC address assigned to this device.
- * @fid: frame id.
  * @extra_byte : number of extra byte prepended rx pkt.
- * @enabled: indicator this device works.
  */
 
 /* Receive multiplex framer header info */
@@ -72,27 +40,10 @@ struct type_frame_head {
 } fr_h_i[MAX_RECV_FRAMES];
 
 struct ks_net {
-   struct net_device   *netdev;
-   union ks_tx_hdr txh;
struct type_frame_head  *frame_head_info;
-   u32 msg_enable;
-   u32 frame_cnt;
int bus_width;
-   int irq;
-   u16 rc_txcr;
-   u16 rc_ier;
u16 sharedbus;
-   u16 cmd_reg_cache;
-   u16 cmd_reg_cache_int;
-   u16 promiscuous;
-   u16 all_mcast;
-   u16 mcast_lst_size;
-   u8  mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN];
-   u8  mcast_bits[HW_MCAST_SIZE];
-   u8  mac_addr[6];
-   u8  fid;
u8  extra_byte;
-   u8  enabled;
 } ks_str, *ks;
 
 #define BE3 0x8000  /* Byte Enable 3 */
@@ -154,7 +105,7 @@ static inline void ks_outblk(struct eth_device *dev, u16 
*wptr, u32 len)
 
 static void ks_enable_int(struct eth_device *dev)
 {
-   ks_wrreg16(dev, KS_IER, ks->rc_ier);
+   ks_wrreg16(dev, KS_IER, IRQ_LCI | IRQ_TXI | IRQ_RXI);
 }
 
 static void ks_set_powermode(struct eth_device *dev, unsigned pwrmode)
@@ -288,12 +239,13 @@ static inline void ks_read_qmu(struct eth_device *dev, 
u16 *buf, u32 len)
 static void ks_rcv(struct eth_device *dev, uchar **pv_data)
 {
struct type_frame_head *frame_hdr = ks->frame_head_info;
+   unsigned int frame_cnt;
int i;
 
-   ks->frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8;
+   frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8;
 
/* read all header information */
-   for (i = 0; i < ks->frame_cnt; i++) {
+   for (i = 0; i < frame_cnt; i++) {
/* Checking Received packet status */
frame_hdr->sts = ks_rdreg16(dev, KS_RXFHSR);
/* Get packet len from hardware */
@@ -302,7 +254,7 @@ static void ks_rcv(struct eth_device *dev, uchar **pv_data)
}
 
frame_hdr = ks->frame_head_info;
-   while (ks->frame_cnt--) {
+   while (frame_cnt--) {
if ((frame_hdr->sts & RXFSHR_RXFV) &&
(frame_hdr->len < RX_BUF_SIZE) &&
frame_hdr->len) {
@@ -392,13 +344,8 @@ static void ks_setup(struct eth_device *dev)
 
 static void ks_setup_int(struct eth_device *dev)
 {
-   ks->rc_ier = 0x00;
-
/* Clear the interrupts status of the hardware. */
ks_wrreg16(dev, KS_ISR, 0x);
-
-   /* Enables the interrupts of the hardware. */
-   ks->rc_ier = (IRQ_L

[PATCH 05/12] net: ks8851: Remove type_frame_head

[Marek Vasut]

The packet status and length information should be extracted from the
FIFO per-packet. Adjust the code such that it reads the packet meta
data and then the packet afterward, if applicable.

Signed-off-by: Marek Vasut 
Cc: Eugen Hristev 
Cc: Joe Hershberger 
---
 drivers/net/ks8851_mll.c | 36 +++-
 1 file changed, 7 insertions(+), 29 deletions(-)

diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c
index 7d6328afab..2d854d855d 100644
--- a/drivers/net/ks8851_mll.c
+++ b/drivers/net/ks8851_mll.c
@@ -15,9 +15,6 @@
 
 #define DRIVERNAME "ks8851_mll"
 
-#define MAX_RECV_FRAMES32
-#define MAX_BUF_SIZE   2048
-#define TX_BUF_SIZE2000
 #define RX_BUF_SIZE2000
 
 static const struct chip_id chip_ids[] =  {
@@ -27,20 +24,11 @@ static const struct chip_id chip_ids[] =  {
 
 /*
  * struct ks_net - KS8851 driver private data
- * @frame_head_info: frame header information for multi-pkt rx.
  * @bus_width  : i/o bus width.
  * @sharedbus  : Multipex(addr and data bus) mode indicator.
- * @extra_byte : number of extra byte prepended rx pkt.
+ * @extra_byte : number of extra byte prepended rx pkt.
  */
-
-/* Receive multiplex framer header info */
-struct type_frame_head {
-   u16 sts; /* Frame status */
-   u16 len; /* Byte count */
-} fr_h_i[MAX_RECV_FRAMES];
-
 struct ks_net {
-   struct type_frame_head  *frame_head_info;
int bus_width;
u16 sharedbus;
u8  extra_byte;
@@ -238,8 +226,8 @@ static inline void ks_read_qmu(struct eth_device *dev, u16 
*buf, u32 len)
 
 static void ks_rcv(struct eth_device *dev, uchar **pv_data)
 {
-   struct type_frame_head *frame_hdr = ks->frame_head_info;
unsigned int frame_cnt;
+   u16 sts, len;
int i;
 
frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8;
@@ -247,28 +235,21 @@ static void ks_rcv(struct eth_device *dev, uchar 
**pv_data)
/* read all header information */
for (i = 0; i < frame_cnt; i++) {
/* Checking Received packet status */
-   frame_hdr->sts = ks_rdreg16(dev, KS_RXFHSR);
+   sts = ks_rdreg16(dev, KS_RXFHSR);
/* Get packet len from hardware */
-   frame_hdr->len = ks_rdreg16(dev, KS_RXFHBCR);
-   frame_hdr++;
-   }
+   len = ks_rdreg16(dev, KS_RXFHBCR);
 
-   frame_hdr = ks->frame_head_info;
-   while (frame_cnt--) {
-   if ((frame_hdr->sts & RXFSHR_RXFV) &&
-   (frame_hdr->len < RX_BUF_SIZE) &&
-   frame_hdr->len) {
+   if ((sts & RXFSHR_RXFV) && len && (len < RX_BUF_SIZE)) {
/* read data block including CRC 4 bytes */
-   ks_read_qmu(dev, (u16 *)(*pv_data), frame_hdr->len);
+   ks_read_qmu(dev, (u16 *)(*pv_data), len);
 
/* net_rx_packets buffer size is ok (*pv_data) */
-   net_process_received_packet(*pv_data, frame_hdr->len);
+   net_process_received_packet(*pv_data, len);
pv_data++;
} else {
ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF);
printf(DRIVERNAME ": bad packet\n");
}
-   frame_hdr++;
}
 }
 
@@ -437,9 +418,6 @@ static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
/* Configure the PHY, initialize the link state */
ks8851_mll_phy_configure(dev);
 
-   /* static allocation of private informations */
-   ks->frame_head_info = fr_h_i;
-
/* Turn on Tx + Rx */
ks8851_mll_enable(dev);
 
-- 
2.25.1

[PATCH 07/12] net: ks8851: Checkpatch cleanup

[Marek Vasut]

Fix various checkpatch complaints.

Signed-off-by: Marek Vasut 
Cc: Eugen Hristev 
Cc: Joe Hershberger 
---
 drivers/net/ks8851_mll.c | 19 ++-
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c
index 503da7a3bf..54a273aa69 100644
--- a/drivers/net/ks8851_mll.c
+++ b/drivers/net/ks8851_mll.c
@@ -91,9 +91,9 @@ static void ks_enable_int(struct eth_device *dev)
ks_wrreg16(dev, KS_IER, IRQ_LCI | IRQ_TXI | IRQ_RXI);
 }
 
-static void ks_set_powermode(struct eth_device *dev, unsigned pwrmode)
+static void ks_set_powermode(struct eth_device *dev, unsigned int pwrmode)
 {
-   unsigned pmecr;
+   unsigned int pmecr;
 
ks_rdreg16(dev, KS_GRR);
pmecr = ks_rdreg16(dev, KS_PMECR);
@@ -147,7 +147,7 @@ static void ks_read_config(struct eth_device *dev)
  * not currently specify the exact sequence, we have chosen something
  * that seems to work with our device.
  */
-static void ks_soft_reset(struct eth_device *dev, unsigned op)
+static void ks_soft_reset(struct eth_device *dev, unsigned int op)
 {
/* Disable interrupt first */
ks_wrreg16(dev, KS_IER, 0x);
@@ -417,7 +417,7 @@ static void ks_write_qmu(struct eth_device *dev, u8 *pdata, 
u16 len)
/* 1. set sudo-DMA mode */
ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
-   /* 2. write status/lenth info */
+   /* 2. write status/length info */
ks_outblk(dev, txw, 4);
/* 3. write pkt data */
ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4));
@@ -443,10 +443,10 @@ static int ks8851_mll_send(struct eth_device *dev, void 
*packet, int length)
if (retv >= tmplen + 12) {
ks_write_qmu(dev, data, tmplen);
return 0;
-   } else {
-   printf(DRIVERNAME ": failed to send packet: No buffer\n");
-   return -1;
}
+
+   printf(DRIVERNAME ": failed to send packet: No buffer\n");
+   return -1;
 }
 
 static void ks8851_mll_halt(struct eth_device *dev)
@@ -468,11 +468,12 @@ static int ks8851_mll_recv(struct eth_device *dev)
 
ks_wrreg16(dev, KS_ISR, status);
 
-   if ((status & IRQ_RXI))
+   if (status & IRQ_RXI)
ks_rcv(dev, (uchar **)net_rx_packets);
 
-   if ((status & IRQ_LDI)) {
+   if (status & IRQ_LDI) {
u16 pmecr = ks_rdreg16(dev, KS_PMECR);
+
pmecr &= ~PMECR_WKEVT_MASK;
ks_wrreg16(dev, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
}
-- 
2.25.1

[PATCH 03/12] net: ks8851: Use 16bit RXQCR access

[Marek Vasut]

Per KS8851-16MLL, the RXQCR is a 16bit register. Use 16bit accessors
to it consistently and drop the ks_wrreg8() function altogether, as
it is not used anymore.

Signed-off-by: Marek Vasut 
Cc: Eugen Hristev 
Cc: Joe Hershberger 
---
 drivers/net/ks8851_mll.c | 17 -
 1 file changed, 4 insertions(+), 13 deletions(-)

diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c
index 367ad2a397..c60c2183a1 100644
--- a/drivers/net/ks8851_mll.c
+++ b/drivers/net/ks8851_mll.c
@@ -117,15 +117,6 @@ static u16 ks_rdreg16(struct eth_device *dev, u16 offset)
return readw(dev->iobase);
 }
 
-static void ks_wrreg8(struct eth_device *dev, u16 offset, u8 val)
-{
-   u8 shift_bit = (offset & 0x03);
-   u16 value_write = (u16)(val << ((offset & 1) << 3));
-
-   writew(offset | (BE0 << shift_bit), dev->iobase + 2);
-   writew(value_write, dev->iobase);
-}
-
 static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val)
 {
writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
@@ -273,7 +264,7 @@ static inline void ks_read_qmu(struct eth_device *dev, u16 
*buf, u32 len)
 
/* 1. set sudo DMA mode */
ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
-   ks_wrreg8(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
+   ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
 
/*
 * 2. read prepend data
@@ -291,7 +282,7 @@ static inline void ks_read_qmu(struct eth_device *dev, u16 
*buf, u32 len)
ks_inblk(dev, buf, ALIGN(len, 4));
 
/* 4. reset sudo DMA Mode */
-   ks_wrreg8(dev, KS_RXQCR, RXQCR_CMD_CNTL);
+   ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL);
 }
 
 static void ks_rcv(struct eth_device *dev, uchar **pv_data)
@@ -516,13 +507,13 @@ static void ks_write_qmu(struct eth_device *dev, u8 
*pdata, u16 len)
 
/* 1. set sudo-DMA mode */
ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
-   ks_wrreg8(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
+   ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
/* 2. write status/lenth info */
ks_outblk(dev, ks->txh.txw, 4);
/* 3. write pkt data */
ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4));
/* 4. reset sudo-DMA mode */
-   ks_wrreg8(dev, KS_RXQCR, RXQCR_CMD_CNTL);
+   ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL);
/* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE);
/* 6. wait until TXQCR_METFE is auto-cleared */
-- 
2.25.1

[PATCH 02/12] net: ks8851: Remove RXQCR cache

[Marek Vasut]

The cached RXQCR value is never updated, remove the cache and just use
the bits in the cache directly in the code.

Signed-off-by: Marek Vasut 
Cc: Eugen Hristev 
Cc: Joe Hershberger 
---
 drivers/net/ks8851_mll.c | 15 ++-
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c
index 4386763bac..367ad2a397 100644
--- a/drivers/net/ks8851_mll.c
+++ b/drivers/net/ks8851_mll.c
@@ -49,7 +49,6 @@ union ks_tx_hdr {
  * @frame_cnt  : number of frames received.
  * @bus_width  : i/o bus width.
  * @irq: irq number assigned to this device.
- * @rc_rxqcr   : Cached copy of KS_RXQCR.
  * @rc_txcr: Cached copy of KS_TXCR.
  * @rc_ier : Cached copy of KS_IER.
  * @sharedbus  : Multipex(addr and data bus) mode indicator.
@@ -80,7 +79,6 @@ struct ks_net {
u32 frame_cnt;
int bus_width;
int irq;
-   u16 rc_rxqcr;
u16 rc_txcr;
u16 rc_ier;
u16 sharedbus;
@@ -275,7 +273,7 @@ static inline void ks_read_qmu(struct eth_device *dev, u16 
*buf, u32 len)
 
/* 1. set sudo DMA mode */
ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
-   ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
+   ks_wrreg8(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
 
/*
 * 2. read prepend data
@@ -293,7 +291,7 @@ static inline void ks_read_qmu(struct eth_device *dev, u16 
*buf, u32 len)
ks_inblk(dev, buf, ALIGN(len, 4));
 
/* 4. reset sudo DMA Mode */
-   ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
+   ks_wrreg8(dev, KS_RXQCR, RXQCR_CMD_CNTL);
 }
 
 static void ks_rcv(struct eth_device *dev, uchar **pv_data)
@@ -324,7 +322,7 @@ static void ks_rcv(struct eth_device *dev, uchar **pv_data)
net_process_received_packet(*pv_data, frame_hdr->len);
pv_data++;
} else {
-   ks_wrreg16(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
+   ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF);
printf(DRIVERNAME ": bad packet\n");
}
frame_hdr++;
@@ -379,8 +377,7 @@ static void ks_setup(struct eth_device *dev)
ks_wrreg16(dev, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
 
/* Setup RxQ Command Control (RXQCR) */
-   ks->rc_rxqcr = RXQCR_CMD_CNTL;
-   ks_wrreg16(dev, KS_RXQCR, ks->rc_rxqcr);
+   ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL);
 
/*
 * set the force mode to half duplex, default is full duplex
@@ -519,13 +516,13 @@ static void ks_write_qmu(struct eth_device *dev, u8 
*pdata, u16 len)
 
/* 1. set sudo-DMA mode */
ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
-   ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
+   ks_wrreg8(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
/* 2. write status/lenth info */
ks_outblk(dev, ks->txh.txw, 4);
/* 3. write pkt data */
ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4));
/* 4. reset sudo-DMA mode */
-   ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
+   ks_wrreg8(dev, KS_RXQCR, RXQCR_CMD_CNTL);
/* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE);
/* 6. wait until TXQCR_METFE is auto-cleared */
-- 
2.25.1

[PATCH 01/12] net: ks8851: Replace malloc()+memset() with calloc()

[Marek Vasut]

Replace combination of malloc()+memset() with calloc() as the behavior
is exactly the same and the amount of code is reduced. Moreover, remove
printf() in the fail path, as it is useless, and return proper -ENOMEM
return code.

Signed-off-by: Marek Vasut 
Cc: Eugen Hristev 
Cc: Joe Hershberger 
---
 drivers/net/ks8851_mll.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c
index 718a7dd019..4386763bac 100644
--- a/drivers/net/ks8851_mll.c
+++ b/drivers/net/ks8851_mll.c
@@ -602,12 +602,9 @@ int ks8851_mll_initialize(u8 dev_num, int base_addr)
 {
struct eth_device *dev;
 
-   dev = malloc(sizeof(*dev));
-   if (!dev) {
-   printf("Error: Failed to allocate memory\n");
-   return -1;
-   }
-   memset(dev, 0, sizeof(*dev));
+   dev = calloc(1, sizeof(*dev));
+   if (!dev)
+   return -ENOMEM;
 
dev->iobase = base_addr;
 
-- 
2.25.1

Re: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

[Tom Rini]

On Wed, Mar 25, 2020 at 06:28:20PM +, Tom Warren wrote:
> 
> 
> -Original Message-
> From: Tom Rini  
> Sent: Wednesday, March 25, 2020 11:26 AM
> To: Tom Warren 
> Cc: Peter Robinson ; u-boot@lists.denx.de; Stephen 
> Warren ; Thierry Reding ; Jonathan 
> Hunter ; tomcwarren3...@gmail.com
> Subject: Re: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support
> 
> On Wed, Mar 25, 2020 at 06:24:43PM +, Tom Warren wrote:
> 
> > > That is strange, please re-post them and we'll see what happens.  If they 
> > > don't show up right away I can poke people.  Thanks!
> > 
> > Just resent the Nano patch via:
> > 
> > git send-email 0001*.patch --to u-boot@lists.denx.de --confirm always 
> > --annotate --from tomcwarren3...@gmail.com --cc swar...@nvidia.com 
> > --cc tred...@nvidia.com --cc jonath...@nvidia.com --cc 
> > twar...@nvidia.com
> > 
> > This time I used my Gmail address in 'from' and put my work address in 'cc'.
> > 
> > Let's see if it shows up in Patchwork.
> 
> There's http://patchwork.ozlabs.org/patch/1261582/ now, just that one patch?
> [Tom] yes, the one I resent above, but using my gmail address 
> (tomcwarren3959) instead of my work address (twar...@nvidia.com). Any idea 
> why that would make any difference?
> I'll work on resending the others using that address.

Not sure what went wrong, sorry.

-- 
Tom


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Description: PGP signature

RE: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

[Tom Warren]

-Original Message-
From: Tom Rini  
Sent: Wednesday, March 25, 2020 11:26 AM
To: Tom Warren 
Cc: Peter Robinson ; u-boot@lists.denx.de; Stephen Warren 
; Thierry Reding ; Jonathan Hunter 
; tomcwarren3...@gmail.com
Subject: Re: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

On Wed, Mar 25, 2020 at 06:24:43PM +, Tom Warren wrote:

> > That is strange, please re-post them and we'll see what happens.  If they 
> > don't show up right away I can poke people.  Thanks!
> 
> Just resent the Nano patch via:
> 
> git send-email 0001*.patch --to u-boot@lists.denx.de --confirm always 
> --annotate --from tomcwarren3...@gmail.com --cc swar...@nvidia.com 
> --cc tred...@nvidia.com --cc jonath...@nvidia.com --cc 
> twar...@nvidia.com
> 
> This time I used my Gmail address in 'from' and put my work address in 'cc'.
> 
> Let's see if it shows up in Patchwork.

There's http://patchwork.ozlabs.org/patch/1261582/ now, just that one patch?
[Tom] yes, the one I resent above, but using my gmail address (tomcwarren3959) 
instead of my work address (twar...@nvidia.com). Any idea why that would make 
any difference?
I'll work on resending the others using that address.

--
Tom
---
This email message is for the sole use of the intended recipient(s) and may 
contain
confidential information.  Any unauthorized review, use, disclosure or 
distribution
is prohibited.  If you are not the intended recipient, please contact the 
sender by
reply email and destroy all copies of the original message.
---

Re: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

[Tom Rini]

On Wed, Mar 25, 2020 at 06:24:43PM +, Tom Warren wrote:

> > That is strange, please re-post them and we'll see what happens.  If they 
> > don't show up right away I can poke people.  Thanks!
> 
> Just resent the Nano patch via:
> 
> git send-email 0001*.patch --to u-boot@lists.denx.de --confirm always 
> --annotate --from tomcwarren3...@gmail.com --cc swar...@nvidia.com --cc 
> tred...@nvidia.com --cc jonath...@nvidia.com --cc twar...@nvidia.com
> 
> This time I used my Gmail address in 'from' and put my work address in 'cc'.
> 
> Let's see if it shows up in Patchwork.

There's http://patchwork.ozlabs.org/patch/1261582/ now, just that one
patch?

-- 
Tom


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Description: PGP signature

RE: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

[Tom Warren]

> That is strange, please re-post them and we'll see what happens.  If they 
> don't show up right away I can poke people.  Thanks!

Just resent the Nano patch via:

git send-email 0001*.patch --to u-boot@lists.denx.de --confirm always 
--annotate --from tomcwarren3...@gmail.com --cc swar...@nvidia.com --cc 
tred...@nvidia.com --cc jonath...@nvidia.com --cc twar...@nvidia.com

This time I used my Gmail address in 'from' and put my work address in 'cc'.

Let's see if it shows up in Patchwork.

Tom

-Original Message-
From: Tom Rini  
Sent: Wednesday, March 25, 2020 10:56 AM
To: Tom Warren 
Cc: Peter Robinson ; u-boot@lists.denx.de; Stephen Warren 
; Thierry Reding ; Jonathan Hunter 
; tomcwarren3...@gmail.com
Subject: Re: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

On Wed, Mar 25, 2020 at 05:44:25PM +, Tom Warren wrote:

> -Original Message-
> From: Peter Robinson 
> Sent: Wednesday, March 25, 2020 5:53 AM
> To: Tom Warren 
> Cc: u-boot@lists.denx.de; Stephen Warren ; Thierry 
> Reding ; Jonathan Hunter ; 
> tomcwarren3...@gmail.com
> Subject: Re: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit 
> support
> 
> External email: Use caution opening links or attachments
> 
> 
> Hi Tom,
> 
> Do you have this and the other patches you've posted on a git branch 
> somewhere, for some reason they're not showing up in patchwork [1] which 
> makes it less straight forward to test.
> 
> Peter
> [1] http://patchwork.ozlabs.org/project/uboot/list/?q=tegra
> 
> [Tom] That's weird, I sent them all using git send-email to 
> u-boot@lists.denx.de. But you are right, I don't see any of them on 
> Patchwork. TomR - any idea why?

That is strange, please re-post them and we'll see what happens.  If they don't 
show up right away I can poke people.  Thanks!

--
Tom
---
This email message is for the sole use of the intended recipient(s) and may 
contain
confidential information.  Any unauthorized review, use, disclosure or 
distribution
is prohibited.  If you are not the intended recipient, please contact the 
sender by
reply email and destroy all copies of the original message.
---

[PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

[tomcwarren3959]

From: Tom Warren 

The Jetson Nano Developer Kit is a Tegra X1-based development board. It
is similar to Jetson TX1 but it is not pin compatible. It features 4GB
of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot
used for storage.

HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
Ethernet controller provides onboard network connectivity. NVMe support
has also been added. Env save is at the end of QSPI (4MB-8K).

A 40-pin header on the board can be used to extend the capabilities and
exposed interfaces of the Jetson Nano.

Signed-off-by: Thierry Reding 
Signed-off-by: Tom Warren 
---
retry send-email to see if it shows up in Patchwork

 arch/arm/dts/Makefile|   3 +-
 arch/arm/dts/tegra210-p3450-.dts | 147 +
 arch/arm/mach-tegra/board2.c |  25 +
 arch/arm/mach-tegra/tegra210/Kconfig |   7 ++
 board/nvidia/p3450-/Kconfig  |  12 +++
 board/nvidia/p3450-/MAINTAINERS  |   6 ++
 board/nvidia/p3450-/Makefile |   8 ++
 board/nvidia/p3450-/p3450-.c | 178 +++
 configs/p3450-_defconfig |  64 +
 include/configs/p3450-.h |  46 +
 10 files changed, 495 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/tegra210-p3450-.dts
 create mode 100644 board/nvidia/p3450-/Kconfig
 create mode 100644 board/nvidia/p3450-/MAINTAINERS
 create mode 100644 board/nvidia/p3450-/Makefile
 create mode 100644 board/nvidia/p3450-/p3450-.c
 create mode 100644 configs/p3450-_defconfig
 create mode 100644 include/configs/p3450-.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9c593b2..820ee97 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -180,7 +180,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra210-e2220-1170.dtb \
tegra210-p2371-.dtb \
tegra210-p2371-2180.dtb \
-   tegra210-p2571.dtb
+   tegra210-p2571.dtb \
+   tegra210-p3450-.dtb
 
 dtb-$(CONFIG_ARCH_MVEBU) +=\
armada-3720-db.dtb  \
diff --git a/arch/arm/dts/tegra210-p3450-.dts 
b/arch/arm/dts/tegra210-p3450-.dts
new file mode 100644
index 000..9ef744a
--- /dev/null
+++ b/arch/arm/dts/tegra210-p3450-.dts
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2019-2020 NVIDIA Corporation 
+ */
+/dts-v1/;
+
+#include "tegra210.dtsi"
+
+/ {
+   model = "NVIDIA Jetson Nano Developer Kit";
+   compatible = "nvidia,p3450-", "nvidia,tegra210";
+
+   chosen {
+   stdout-path = &uarta;
+   };
+
+   aliases {
+   ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
+   i2c0 = "/i2c@7000d000";
+   i2c2 = "/i2c@7000c400";
+   i2c3 = "/i2c@7000c500";
+   i2c4 = "/i2c@7000c700";
+   mmc0 = "/sdhci@700b0600";
+   mmc1 = "/sdhci@700b";
+   spi0 = "/spi@7041";
+   usb0 = "/usb@7d00";
+   };
+
+   memory {
+   reg = <0x0 0x8000 0x0 0xc000>;
+   };
+
+   pcie@1003000 {
+   status = "okay";
+
+   pci@1,0 {
+   status = "okay";
+   };
+
+   pci@2,0 {
+   status = "okay";
+
+   ethernet@0,0 {
+   reg = <0x00 0 0 0 0>;
+   local-mac-address = [ 00 00 00 00 00 00 ];
+   };
+   };
+   };
+
+   serial@70006000 {
+   status = "okay";
+   };
+
+   padctl@7009f000 {
+   pinctrl-0 = <&padctl_default>;
+   pinctrl-names = "default";
+
+   padctl_default: pinmux {
+   xusb {
+   nvidia,lanes = "otg-1", "otg-2";
+   nvidia,function = "xusb";
+   nvidia,iddq = <0>;
+   };
+
+   usb3 {
+   nvidia,lanes = "pcie-5", "pcie-6";
+   nvidia,function = "usb3";
+   nvidia,iddq = <0>;
+   };
+
+   pcie-x1 {
+   nvidia,lanes = "pcie-0";
+   nvidia,function = "pcie-x1";
+   nvidia,iddq = <0>;
+   };
+
+   pcie-x4 {
+   nvidia,lanes = "pcie-1", "pcie-2",
+  "pcie-3", "pcie-4";
+   nvidia,function = "pcie-x4";
+   nvidia,iddq = <0>;
+   };
+
+   sata {
+  

Re: latest u-boot branch for Marvell Armada 88F3720

[Marek Behun]

On Wed, 25 Mar 2020 18:48:50 +0100
Marek Behun  wrote:

> One thing that may need reworking (to become compatible with Linux) is
> the comphy driver. Linux' comphy driver for this SOC uses smccc calls
> to ARM Trusted Firmware, but U-Boot does not, and instead initializes
> SERDESes on its own.

By this I mean that it works in U-Boot, but the driver should be
rewritten to at least have the same DTS bindings as Linux.

Re: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

[Tom Rini]

On Wed, Mar 25, 2020 at 05:44:25PM +, Tom Warren wrote:

> -Original Message-
> From: Peter Robinson  
> Sent: Wednesday, March 25, 2020 5:53 AM
> To: Tom Warren 
> Cc: u-boot@lists.denx.de; Stephen Warren ; Thierry Reding 
> ; Jonathan Hunter ; 
> tomcwarren3...@gmail.com
> Subject: Re: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support
> 
> External email: Use caution opening links or attachments
> 
> 
> Hi Tom,
> 
> Do you have this and the other patches you've posted on a git branch 
> somewhere, for some reason they're not showing up in patchwork [1] which 
> makes it less straight forward to test.
> 
> Peter
> [1] http://patchwork.ozlabs.org/project/uboot/list/?q=tegra 
> 
> [Tom] That's weird, I sent them all using git send-email to 
> u-boot@lists.denx.de. But you are right, I don't see any of them on 
> Patchwork. TomR - any idea why?

That is strange, please re-post them and we'll see what happens.  If
they don't show up right away I can poke people.  Thanks!

-- 
Tom


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Description: PGP signature

Re: latest u-boot branch for Marvell Armada 88F3720

[Marek Behun]

Hi,

mainline U-Boot should work for Armada 3720, although I haven't tested
recent master (so I don't know if there are some regressions). But
Turris Mox uses cca 1 year old upstream with just few Mox specific
patches atop (which I plan to get merged soon). You can find it here:
https://gitlab.labs.nic.cz/turris/mox-u-boot

One thing that may need reworking (to become compatible with Linux) is
the comphy driver. Linux' comphy driver for this SOC uses smccc calls
to ARM Trusted Firmware, but U-Boot does not, and instead initializes
SERDESes on its own.

Bear in mind that U-Boot is not enough for booting Armada 3720 SOC. You
do also need ARM Trusted Firmware (you don't need to use Marvell's
ATF, since their patches are merged into upstream ATF), and you also
need firmware for the secure Cortex-M3 processor (Marvell's name for
this firmware is WTMI), which does DDR training. Marvell has this in
A3700-utils-marvell repository. For Turris MOX, we build all of this via
https://gitlab.labs.nic.cz/turris/mox-boot-builder
but this code can be MOX specific, so if you want to use it for other
boards, I can provide more explanation of which does what and so on.

Marek

On Wed, 25 Mar 2020 17:44:57 +0100
Stefan Roese  wrote:

> Hi Moritz,
> 
> On 25.03.20 16:05, Moritz Berghof wrote:
> > My Name is Moritz and we evaluate the Marvell Armada 88F3720
> > on the Marvell ESPRESSObin and the TURRIS MOX.
> > 
> > Does someone know, where is the actual or latest u-boot branch
> > for Marvell Armada 88F3720 placed? At the u-boot master or a
> > marvell custodian tree or somewhere else? Does Marvell develop
> > u-boot still for their Armada 88F3720 and when yes, where?  
> 
> Those boards are supported in general in mainline U-Boot. Though I
> have to admit, that I didn't test any of those ports recently. I
> added Marek Behun to Cc, as he did submit most of the Turris Mox
> stuff and has more recent experience than I do.
> 
> > Because that https://github.com/MarvellEmbeddedProcessors/u-boot-marvell,
> > which is well used on the ESPRESSObin is NOT up-to-date. 4 Years ago,
> > last commit.  
> 
> I just took a quick glance at this repo and there are newer, more
> recent branches, e.g. "u-boot-2018.03-armada-18.12". But still, this
> is far away from mainline, I agree.
> 
> Perhaps someone else (Marek) can comment on the current status of
> mainline U-Boot on those boards? Is something missing? If yes, it
> would be great to get it ported to mainline.
> 
> Thanks,
> Stefan
> 
> > I'm searching an actual u-boot platform for my Chip.
> > 
> > 
> > I look forward to your reply, thank you very much,
> > 
> > --
> > Moritz Berghof
> > Software Engineer
> > Tel. +49 30 921028-209
> > Fax +49 30 921028-020
> > mberg...@phoenixcontact.com
> > www.phoenixcontact.com
> > 
> > PHOENIX CONTACT Cyber Security GmbH
> > Richard-Willstätter-Straße 6
> > D-12489 Berlin
> > Register Court: AG Charlottenburg, HR B 202908
> > Geschäftsführer/General Manager: Kilian Golm
> > 
> > 
> > ...
> > PHOENIX CONTACT Cyber Security GmbH
> > Richard-Willstätter-Straße 6
> > D-12489 Berlin
> >   
> > Register Court: AG Charlottenburg, HR B 202908
> > Geschäftsführer/General Manager: Kilian Golm
> >   

RE: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

[Tom Warren]

-Original Message-
From: Peter Robinson  
Sent: Wednesday, March 25, 2020 5:53 AM
To: Tom Warren 
Cc: u-boot@lists.denx.de; Stephen Warren ; Thierry Reding 
; Jonathan Hunter ; 
tomcwarren3...@gmail.com
Subject: Re: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

External email: Use caution opening links or attachments


Hi Tom,

Do you have this and the other patches you've posted on a git branch somewhere, 
for some reason they're not showing up in patchwork [1] which makes it less 
straight forward to test.

Peter
[1] http://patchwork.ozlabs.org/project/uboot/list/?q=tegra 

[Tom] That's weird, I sent them all using git send-email to 
u-boot@lists.denx.de. But you are right, I don't see any of them on Patchwork. 
TomR - any idea why?
Peter - you can find all of the patches (plus a WIP fix for a couple of load 
address conflicts when loading an FDT from extlinux) in tegra/next upstream, 
just updated today.

On Tue, Mar 24, 2020 at 7:03 PM  wrote:
>
> From: Tom Warren 
>
> The Jetson Nano Developer Kit is a Tegra X1-based development board. 
> It is similar to Jetson TX1 but it is not pin compatible. It features 
> 4GB of LPDDR4, a SPI NOR flash for early boot firmware and an SD card 
> slot used for storage.
>
> HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 
> 2.0 and 1 USB 3.0) can be used to attach a variety of peripherals and 
> a PCI Ethernet controller provides onboard network connectivity. NVMe 
> support has also been added. Env save is at the end of QSPI (4MB-8K).
>
> A 40-pin header on the board can be used to extend the capabilities 
> and exposed interfaces of the Jetson Nano.
>
> Signed-off-by: Thierry Reding 
> Signed-off-by: Tom Warren 
> ---
>  arch/arm/dts/Makefile|   3 +-
>  arch/arm/dts/tegra210-p3450-.dts | 147 +
>  arch/arm/mach-tegra/board2.c |  25 +
>  arch/arm/mach-tegra/tegra210/Kconfig |   7 ++
>  board/nvidia/p3450-/Kconfig  |  12 +++
>  board/nvidia/p3450-/MAINTAINERS  |   6 ++
>  board/nvidia/p3450-/Makefile |   8 ++
>  board/nvidia/p3450-/p3450-.c | 178 
> +++
>  configs/p3450-_defconfig |  64 +
>  include/configs/p3450-.h |  46 +
>  10 files changed, 495 insertions(+), 1 deletion(-)  create mode 
> 100644 arch/arm/dts/tegra210-p3450-.dts
>  create mode 100644 board/nvidia/p3450-/Kconfig  create mode 
> 100644 board/nvidia/p3450-/MAINTAINERS
>  create mode 100644 board/nvidia/p3450-/Makefile  create mode 
> 100644 board/nvidia/p3450-/p3450-.c
>  create mode 100644 configs/p3450-_defconfig  create mode 100644 
> include/configs/p3450-.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 
> 9c593b2..820ee97 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -180,7 +180,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
> tegra210-e2220-1170.dtb \
> tegra210-p2371-.dtb \
> tegra210-p2371-2180.dtb \
> -   tegra210-p2571.dtb
> +   tegra210-p2571.dtb \
> +   tegra210-p3450-.dtb
>
>  dtb-$(CONFIG_ARCH_MVEBU) +=\
> armada-3720-db.dtb  \
> diff --git a/arch/arm/dts/tegra210-p3450-.dts 
> b/arch/arm/dts/tegra210-p3450-.dts
> new file mode 100644
> index 000..9ef744a
> --- /dev/null
> +++ b/arch/arm/dts/tegra210-p3450-.dts
> @@ -0,0 +1,147 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + *  (C) Copyright 2019-2020 NVIDIA Corporation   */ 
> +/dts-v1/;
> +
> +#include "tegra210.dtsi"
> +
> +/ {
> +   model = "NVIDIA Jetson Nano Developer Kit";
> +   compatible = "nvidia,p3450-", "nvidia,tegra210";
> +
> +   chosen {
> +   stdout-path = &uarta;
> +   };
> +
> +   aliases {
> +   ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
> +   i2c0 = "/i2c@7000d000";
> +   i2c2 = "/i2c@7000c400";
> +   i2c3 = "/i2c@7000c500";
> +   i2c4 = "/i2c@7000c700";
> +   mmc0 = "/sdhci@700b0600";
> +   mmc1 = "/sdhci@700b";
> +   spi0 = "/spi@7041";
> +   usb0 = "/usb@7d00";
> +   };
> +
> +   memory {
> +   reg = <0x0 0x8000 0x0 0xc000>;
> +   };
> +
> +   pcie@1003000 {
> +   status = "okay";
> +
> +   pci@1,0 {
> +   status = "okay";
> +   };
> +
> +   pci@2,0 {
> +   status = "okay";
> +
> +   ethernet@0,0 {
> +   reg = <0x00 0 0 0 0>;
> +   local-mac-address = [ 00 00 00 00 00 00 ];
> +   };
> +   };
> +   };
> +
> +   serial@70006000 {
> +   status = "okay";
> +   };
> +
> +   padctl@7009f000 {
> +  

[PATCH V4 13/13] net: smc911x: Add DM support

[Marek Vasut]

Add support for U-Boot DM and DT probing. Furthermore, build the
SMC911x standalone EEPROM example only for the non-DM case, as it
is not converted yet.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: Drop the board-specific bits
Hide SMC911X_BASE from Kconfig if DM_ETH
V3: No change
V4: No change
---
 drivers/net/Kconfig  |   2 +
 drivers/net/smc911x.c| 114 +++
 examples/standalone/Makefile |   5 +-
 3 files changed, 120 insertions(+), 1 deletion(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4d1013c984..095395813a 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -388,11 +388,13 @@ config SMC911X
 
 if SMC911X
 
+if !DM_ETH
 config SMC911X_BASE
hex "SMC911X Base Address"
help
  Define this to hold the physical address
  of the device (I/O space)
+endif #DM_ETH
 
 choice
prompt "SMC911X bus width"
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 95f955f6d8..89be192d5f 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -21,7 +21,9 @@ struct chip_id {
 };
 
 struct smc911x_priv {
+#ifndef CONFIG_DM_ETH
struct eth_device   dev;
+#endif
phys_addr_t iobase;
const struct chip_id*chipid;
unsigned char   enetaddr[6];
@@ -370,6 +372,8 @@ static int smc911x_recv_common(struct smc911x_priv *priv, 
u32 *data)
return pktlen;
 }
 
+#ifndef CONFIG_DM_ETH
+
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 /* wrapper for smc911x_eth_phy_read */
 static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
@@ -516,3 +520,113 @@ err_detect:
free(priv);
return ret;
 }
+
+#else  /* ifdef CONFIG_DM_ETH */
+
+static int smc911x_start(struct udevice *dev)
+{
+   struct eth_pdata *plat = dev_get_platdata(dev);
+   struct smc911x_priv *priv = dev_get_priv(dev);
+
+   memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
+
+   return smc911x_init_common(priv);
+}
+
+static void smc911x_stop(struct udevice *dev)
+{
+   struct smc911x_priv *priv = dev_get_priv(dev);
+
+   smc911x_halt_common(priv);
+}
+
+static int smc911x_send(struct udevice *dev, void *packet, int length)
+{
+   struct smc911x_priv *priv = dev_get_priv(dev);
+   int ret;
+
+   ret = smc911x_send_common(priv, packet, length);
+
+   return ret ? 0 : -ETIMEDOUT;
+}
+
+static int smc911x_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+   struct smc911x_priv *priv = dev_get_priv(dev);
+   u32 *data = (u32 *)net_rx_packets[0];
+   int ret;
+
+   ret = smc911x_recv_common(priv, data);
+   if (ret)
+   *packetp = (void *)data;
+
+   return ret ? ret : -EAGAIN;
+}
+
+static int smc911x_bind(struct udevice *dev)
+{
+   return device_set_name(dev, dev->name);
+}
+
+static int smc911x_probe(struct udevice *dev)
+{
+   struct smc911x_priv *priv = dev_get_priv(dev);
+   unsigned long addrh, addrl;
+   int ret;
+
+   /* Try to detect chip. Will fail if not present. */
+   ret = smc911x_detect_chip(priv);
+   if (ret)
+   return ret;
+
+   addrh = smc911x_get_mac_csr(priv, ADDRH);
+   addrl = smc911x_get_mac_csr(priv, ADDRL);
+   if (!(addrl == 0x && addrh == 0x)) {
+   /* address is obtained from optional eeprom */
+   priv->enetaddr[0] = addrl;
+   priv->enetaddr[1] = addrl >>  8;
+   priv->enetaddr[2] = addrl >> 16;
+   priv->enetaddr[3] = addrl >> 24;
+   priv->enetaddr[4] = addrh;
+   priv->enetaddr[5] = addrh >> 8;
+   }
+
+   return 0;
+}
+
+static int smc911x_ofdata_to_platdata(struct udevice *dev)
+{
+   struct smc911x_priv *priv = dev_get_priv(dev);
+   struct eth_pdata *pdata = dev_get_platdata(dev);
+
+   pdata->iobase = devfdt_get_addr(dev);
+   priv->iobase = pdata->iobase;
+
+   return 0;
+}
+
+static const struct eth_ops smc911x_ops = {
+   .start  = smc911x_start,
+   .send   = smc911x_send,
+   .recv   = smc911x_recv,
+   .stop   = smc911x_stop,
+};
+
+static const struct udevice_id smc911x_ids[] = {
+   { .compatible = "smsc,lan9115" },
+   { }
+};
+
+U_BOOT_DRIVER(smc911x) = {
+   .name   = "eth_smc911x",
+   .id = UCLASS_ETH,
+   .of_match   = smc911x_ids,
+   .bind   = smc911x_bind,
+   .ofdata_to_platdata = smc911x_ofdata_to_platdata,
+   .probe  = smc911x_probe,
+   .ops= &smc911x_ops,
+   .priv_auto_alloc_size = sizeof(struct smc911x_priv),
+   .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+   .flags  = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
index 0b17a91804..6b061bac69 100644
--- a/examples/standalone/Makefil

[PATCH V4 10/13] net: smc911x: Pass around driver private data

[Marek Vasut]

Introduce a private data structure for this driver with embedded
struct eth_device and pass it around. This prepares the driver to
work with both DM and non-DM systems.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
V4: Repair the calloc conversion again
---
 drivers/net/smc911x.c | 232 ++
 1 file changed, 124 insertions(+), 108 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 364f8c5da8..07066ce108 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -20,6 +20,13 @@ struct chip_id {
char *name;
 };
 
+struct smc911x_priv {
+   struct eth_device   dev;
+   phys_addr_t iobase;
+   const struct chip_id*chipid;
+   unsigned char   enetaddr[6];
+};
+
 static const struct chip_id chip_ids[] =  {
{ CHIP_89218, "LAN89218" },
{ CHIP_9115, "LAN9115" },
@@ -45,57 +52,57 @@ static const struct chip_id chip_ids[] =  {
 #endif
 
 #if defined (CONFIG_SMC911X_32_BIT)
-static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
 {
-   return readl(dev->iobase + offset);
+   return readl(priv->iobase + offset);
 }
 
-static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
+static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
 {
-   writel(val, dev->iobase + offset);
+   writel(val, priv->iobase + offset);
 }
 #elif defined (CONFIG_SMC911X_16_BIT)
-static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
 {
-   return (readw(dev->iobase + offset) & 0x) |
-  (readw(dev->iobase + offset + 2) << 16);
+   return (readw(priv->iobase + offset) & 0x) |
+  (readw(priv->iobase + offset + 2) << 16);
 }
-static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
+static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
 {
-   writew(val & 0x, dev->iobase + offset);
-   writew(val >> 16, dev->iobase + offset + 2);
+   writew(val & 0x, priv->iobase + offset);
+   writew(val >> 16, priv->iobase + offset + 2);
 }
 #else
 #error "SMC911X: undefined bus width"
 #endif /* CONFIG_SMC911X_16_BIT */
 
-static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
+static u32 smc911x_get_mac_csr(struct smc911x_priv *priv, u8 reg)
 {
-   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
-   smc911x_reg_write(dev, MAC_CSR_CMD,
+   smc911x_reg_write(priv, MAC_CSR_CMD,
MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
-   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
 
-   return smc911x_reg_read(dev, MAC_CSR_DATA);
+   return smc911x_reg_read(priv, MAC_CSR_DATA);
 }
 
-static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
+static void smc911x_set_mac_csr(struct smc911x_priv *priv, u8 reg, u32 data)
 {
-   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
-   smc911x_reg_write(dev, MAC_CSR_DATA, data);
-   smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
-   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   smc911x_reg_write(priv, MAC_CSR_DATA, data);
+   smc911x_reg_write(priv, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
+   while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
 }
 
-static int smc911x_detect_chip(struct eth_device *dev)
+static int smc911x_detect_chip(struct smc911x_priv *priv)
 {
unsigned long val, i;
 
-   val = smc911x_reg_read(dev, BYTE_TEST);
+   val = smc911x_reg_read(priv, BYTE_TEST);
if (val == 0x) {
/* Special case -- no chip present */
return -1;
@@ -104,7 +111,7 @@ static int smc911x_detect_chip(struct eth_device *dev)
return -1;
}
 
-   val = smc911x_reg_read(dev, ID_REV) >> 16;
+   val = smc911x_reg_read(priv, ID_REV) >> 16;
for (i = 0; chip_ids[i].id != 0; i++) {
if (chip_ids[i].id == val) break;
}
@@ -113,12 +120,12 @@ static int smc911x_detect_chip(struct eth_device *dev)
return -1;
}
 
-   dev->priv = (void *)&chip_ids[i];
+   priv->chipid = &chip_ids[i];
 
return 0;
 }
 
-static void smc911x_reset(struct eth_device *dev)
+static void smc911x_reset(struct smc911x_priv *priv)
 {
int timeout;
 
@@ -126,14 +133,14 @@ static void smc911x_reset(struct eth_d

[PATCH V4 12/13] net: smc911x: Split non-DM specific bits from common code

[Marek Vasut]

Split network handling functions into non-DM specific parts and
common code in preparation for conversion to DM.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
Acked-by: Joe Hershberger 
---
V2: Add AB from Joe
V3: No change
V4: No change
---
 drivers/net/smc911x.c | 57 ---
 1 file changed, 43 insertions(+), 14 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 2d1a9e0f5a..95f955f6d8 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -277,9 +277,8 @@ static void smc911x_enable(struct smc911x_priv *priv)
MAC_CR_HBDIS);
 }
 
-static int smc911x_init(struct eth_device *dev, bd_t * bd)
+static int smc911x_init_common(struct smc911x_priv *priv)
 {
-   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
const struct chip_id *id = priv->chipid;
 
printf(DRIVERNAME ": detected %s controller\n", id->name);
@@ -297,9 +296,9 @@ static int smc911x_init(struct eth_device *dev, bd_t * bd)
return 0;
 }
 
-static int smc911x_send(struct eth_device *dev, void *packet, int length)
+static int smc911x_send_common(struct smc911x_priv *priv,
+  void *packet, int length)
 {
-   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
u32 *data = (u32*)packet;
u32 tmplen;
u32 status;
@@ -337,18 +336,14 @@ static int smc911x_send(struct eth_device *dev, void 
*packet, int length)
return -1;
 }
 
-static void smc911x_halt(struct eth_device *dev)
+static void smc911x_halt_common(struct smc911x_priv *priv)
 {
-   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
-
smc911x_reset(priv);
smc911x_handle_mac_address(priv);
 }
 
-static int smc911x_recv(struct eth_device *dev)
+static int smc911x_recv_common(struct smc911x_priv *priv, u32 *data)
 {
-   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
-   u32 *data = (u32 *)net_rx_packets[0];
u32 pktlen, tmplen;
u32 status;
 
@@ -365,14 +360,14 @@ static int smc911x_recv(struct eth_device *dev)
while (tmplen--)
*data++ = smc911x_reg_read(priv, RX_DATA_FIFO);
 
-   if (status & RX_STS_ES)
+   if (status & RX_STS_ES) {
printf(DRIVERNAME
": dropped bad packet. Status: 0x%08x\n",
status);
-   else
-   net_process_received_packet(net_rx_packets[0], pktlen);
+   return 0;
+   }
 
-   return 0;
+   return pktlen;
 }
 
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
@@ -435,6 +430,40 @@ static int smc911x_initialize_mii(struct smc911x_priv 
*priv)
 }
 #endif
 
+static int smc911x_init(struct eth_device *dev, bd_t *bd)
+{
+   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+   return smc911x_init_common(priv);
+}
+
+static void smc911x_halt(struct eth_device *dev)
+{
+   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+   smc911x_halt_common(priv);
+}
+
+static int smc911x_send(struct eth_device *dev, void *packet, int length)
+{
+   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+   return smc911x_send_common(priv, packet, length);
+}
+
+static int smc911x_recv(struct eth_device *dev)
+{
+   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+   u32 *data = (u32 *)net_rx_packets[0];
+   int ret;
+
+   ret = smc911x_recv_common(priv, data);
+   if (ret)
+   net_process_received_packet(net_rx_packets[0], ret);
+
+   return ret;
+}
+
 int smc911x_initialize(u8 dev_num, int base_addr)
 {
unsigned long addrl, addrh;
-- 
2.25.1

[PATCH V4 11/13] net: smc911x: Clean up the status handling in smc911x_recv()

[Marek Vasut]

Invert the status handling logic in smc911x_recv(), to make the
function easier to read, no functional change.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: Simplify RX_FIFO_INF_RXSUSED mask handling
s@Invest@Invert@
V3: No change
V4: No change
---
 drivers/net/smc911x.c | 30 --
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 07066ce108..2d1a9e0f5a 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -352,23 +352,25 @@ static int smc911x_recv(struct eth_device *dev)
u32 pktlen, tmplen;
u32 status;
 
-   if ((smc911x_reg_read(priv, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
-   status = smc911x_reg_read(priv, RX_STATUS_FIFO);
-   pktlen = (status & RX_STS_PKT_LEN) >> 16;
+   status = smc911x_reg_read(priv, RX_FIFO_INF);
+   if (!(status & RX_FIFO_INF_RXSUSED))
+   return 0;
 
-   smc911x_reg_write(priv, RX_CFG, 0);
+   status = smc911x_reg_read(priv, RX_STATUS_FIFO);
+   pktlen = (status & RX_STS_PKT_LEN) >> 16;
 
-   tmplen = (pktlen + 3) / 4;
-   while (tmplen--)
-   *data++ = smc911x_reg_read(priv, RX_DATA_FIFO);
+   smc911x_reg_write(priv, RX_CFG, 0);
 
-   if (status & RX_STS_ES)
-   printf(DRIVERNAME
-   ": dropped bad packet. Status: 0x%08x\n",
-   status);
-   else
-   net_process_received_packet(net_rx_packets[0], pktlen);
-   }
+   tmplen = (pktlen + 3) / 4;
+   while (tmplen--)
+   *data++ = smc911x_reg_read(priv, RX_DATA_FIFO);
+
+   if (status & RX_STS_ES)
+   printf(DRIVERNAME
+   ": dropped bad packet. Status: 0x%08x\n",
+   status);
+   else
+   net_process_received_packet(net_rx_packets[0], pktlen);
 
return 0;
 }
-- 
2.25.1

[PATCH V4 09/13] net: smc911x: Convert IO accessors to {read, write}{w, l}()

[Marek Vasut]

Convert the IO accessors to standard ones instead of using volatile
void pointers, as those do not cover all the bus access details.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
V4: No change
---
 drivers/net/smc911x.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index effee5367c..364f8c5da8 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "smc911x.h"
@@ -46,23 +47,23 @@ static const struct chip_id chip_ids[] =  {
 #if defined (CONFIG_SMC911X_32_BIT)
 static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
 {
-   return *(volatile u32*)(dev->iobase + offset);
+   return readl(dev->iobase + offset);
 }
 
 static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
 {
-   *(volatile u32*)(dev->iobase + offset) = val;
+   writel(val, dev->iobase + offset);
 }
 #elif defined (CONFIG_SMC911X_16_BIT)
 static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
 {
-   volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
-   return ((*addr_16 & 0x) | (*(addr_16 + 1) << 16));
+   return (readw(dev->iobase + offset) & 0x) |
+  (readw(dev->iobase + offset + 2) << 16);
 }
 static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
 {
-   *(volatile u16 *)(dev->iobase + offset) = (u16)val;
-   *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
+   writew(val & 0x, dev->iobase + offset);
+   writew(val >> 16, dev->iobase + offset + 2);
 }
 #else
 #error "SMC911X: undefined bus width"
-- 
2.25.1

Re: [PATCH V3 10/13] net: smc911x: Pass around driver private data

[Marek Vasut]

On 3/25/20 5:14 PM, Harald Seiler wrote:

[...]

>> @@ -421,51 +436,52 @@ static int smc911x_initialize_mii(struct eth_device 
>> *dev)
>>  int smc911x_initialize(u8 dev_num, int base_addr)
>>  {
>>  unsigned long addrl, addrh;
>> -struct eth_device *dev;
>> +struct smc911x_priv *priv;
>>  int ret;
>>  
>> -dev = calloc(1, sizeof(*dev));
>> +dev = calloc(1, sizeof(*priv));
>>  if (!dev)
>>  return -ENOMEM;
> 
> Shouldn't this be
> 
>   priv = calloc(1, sizeof(*priv));
>   if (!priv)
>   return -ENOMEM;
> 
> ?

Yes, it should.

[...]

-- 
Best regards,
Marek Vasut

[PATCH V4 08/13] net: smc911x: Drop weak alias from 32bit accessors

[Marek Vasut]

These accessors are not overridden by any board, and even if they were,
this is something which should be handled via DM now, so remove the
weak alias option. Moreover, drop the inline keyword, as the compiler
can decide better.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: s@overriden@overridden@
V3: No change
V4: No change
---
 drivers/net/smc911x.c| 14 --
 examples/standalone/smc911x_eeprom.c | 16 +---
 2 files changed, 9 insertions(+), 21 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index ff285f14b4..effee5367c 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -44,28 +44,22 @@ static const struct chip_id chip_ids[] =  {
 #endif
 
 #if defined (CONFIG_SMC911X_32_BIT)
-static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
+static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
 {
return *(volatile u32*)(dev->iobase + offset);
 }
-u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
-   __attribute__((weak, alias("__smc911x_reg_read")));
 
-static inline void __smc911x_reg_write(struct eth_device *dev,
-   u32 offset, u32 val)
+static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
 {
*(volatile u32*)(dev->iobase + offset) = val;
 }
-void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
-   __attribute__((weak, alias("__smc911x_reg_write")));
 #elif defined (CONFIG_SMC911X_16_BIT)
-static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
 {
volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
return ((*addr_16 & 0x) | (*(addr_16 + 1) << 16));
 }
-static inline void smc911x_reg_write(struct eth_device *dev,
-   u32 offset, u32 val)
+static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
 {
*(volatile u16 *)(dev->iobase + offset) = (u16)val;
*(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
diff --git a/examples/standalone/smc911x_eeprom.c 
b/examples/standalone/smc911x_eeprom.c
index 19ad9e6297..270588bcf5 100644
--- a/examples/standalone/smc911x_eeprom.c
+++ b/examples/standalone/smc911x_eeprom.c
@@ -51,28 +51,22 @@ static const struct chip_id chip_ids[] =  {
 };
 
 #if defined (CONFIG_SMC911X_32_BIT)
-static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
+static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
 {
return *(volatile u32*)(dev->iobase + offset);
 }
-u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
-   __attribute__((weak, alias("__smc911x_reg_read")));
 
-static inline void __smc911x_reg_write(struct eth_device *dev,
-   u32 offset, u32 val)
+static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
 {
*(volatile u32*)(dev->iobase + offset) = val;
 }
-void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
-   __attribute__((weak, alias("__smc911x_reg_write")));
 #elif defined (CONFIG_SMC911X_16_BIT)
-static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
 {
volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
-   return ((*addr_16 & 0x) | (*(addr_16 + 1) << 16));
+   return (*addr_16 & 0x) | (*(addr_16 + 1) << 16);
 }
-static inline void smc911x_reg_write(struct eth_device *dev,
-   u32 offset, u32 val)
+static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
 {
*(volatile u16 *)(dev->iobase + offset) = (u16)val;
*(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
-- 
2.25.1

[PATCH V4 06/13] net: smc911x: Pull MII registration into separate function

[Marek Vasut]

Pull the MII interface registration into separate function to avoid the
ifdeffery in smc911x_initialize(). Moreover, adjust the fail path such
that we use goto labels.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: New patch
V3: No change
V4: No change
---
 drivers/net/smc911x.c | 64 +++
 1 file changed, 40 insertions(+), 24 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 4459da5945..65c25f3bfd 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -240,12 +240,39 @@ static int smc911x_miiphy_write(struct mii_dev *bus, int 
phy, int devad,
 
return smc911x_eth_phy_write(dev, phy, reg, val);
 }
+
+static int smc911x_initialize_mii(struct eth_device *dev)
+{
+   struct mii_dev *mdiodev = mdio_alloc();
+   int ret;
+
+   if (!mdiodev)
+   return -ENOMEM;
+
+   strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+   mdiodev->read = smc911x_miiphy_read;
+   mdiodev->write = smc911x_miiphy_write;
+
+   ret = mdio_register(mdiodev);
+   if (ret < 0) {
+   mdio_free(mdiodev);
+   return ret;
+   }
+
+   return 0;
+}
+#else
+static int smc911x_initialize_mii(struct eth_device *dev)
+{
+   return 0;
+}
 #endif
 
 int smc911x_initialize(u8 dev_num, int base_addr)
 {
unsigned long addrl, addrh;
struct eth_device *dev;
+   int ret;
 
dev = calloc(1, sizeof(*dev));
if (!dev)
@@ -254,9 +281,10 @@ int smc911x_initialize(u8 dev_num, int base_addr)
dev->iobase = base_addr;
 
/* Try to detect chip. Will fail if not present. */
-   if (smc911x_detect_chip(dev)) {
-   free(dev);
-   return 0;
+   ret = smc911x_detect_chip(dev);
+   if (ret) {
+   ret = 0;/* Card not detected is not an error */
+   goto err_detect;
}
 
addrh = smc911x_get_mac_csr(dev, ADDRH);
@@ -279,27 +307,15 @@ int smc911x_initialize(u8 dev_num, int base_addr)
 
eth_register(dev);
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-   int retval;
-   struct mii_dev *mdiodev = mdio_alloc();
-   if (!mdiodev) {
-   eth_unregister(dev);
-   free(dev);
-   return -ENOMEM;
-   }
-
-   strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
-   mdiodev->read = smc911x_miiphy_read;
-   mdiodev->write = smc911x_miiphy_write;
-
-   retval = mdio_register(mdiodev);
-   if (retval < 0) {
-   mdio_free(mdiodev);
-   eth_unregister(dev);
-   free(dev);
-   return retval;
-   }
-#endif
+   ret = smc911x_initialize_mii(dev);
+   if (ret)
+   goto err_mii;
 
return 1;
+
+err_mii:
+   eth_unregister(dev);
+err_detect:
+   free(dev);
+   return ret;
 }
-- 
2.25.1

[PATCH V4 07/13] net: smc911x: Inline all functions from header file

[Marek Vasut]

Inline all the functions from the header file, as they are not used
outside of the driver or the standalone EEPROM example.

Note that this does introduce considerable amount of duplication in
the standalone EEPROM example, however that one has to be rewritten
anyway, roughly such that the SMC911x driver would expose DM EEPROM
interface and the standalone example would use that.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
V4: No change
---
 drivers/net/smc911x.c| 157 ++-
 drivers/net/smc911x.h| 157 ---
 examples/standalone/smc911x_eeprom.c | 156 ++
 3 files changed, 312 insertions(+), 158 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 65c25f3bfd..ff285f14b4 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -10,9 +10,165 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "smc911x.h"
 
+struct chip_id {
+   u16 id;
+   char *name;
+};
+
+static const struct chip_id chip_ids[] =  {
+   { CHIP_89218, "LAN89218" },
+   { CHIP_9115, "LAN9115" },
+   { CHIP_9116, "LAN9116" },
+   { CHIP_9117, "LAN9117" },
+   { CHIP_9118, "LAN9118" },
+   { CHIP_9211, "LAN9211" },
+   { CHIP_9215, "LAN9215" },
+   { CHIP_9216, "LAN9216" },
+   { CHIP_9217, "LAN9217" },
+   { CHIP_9218, "LAN9218" },
+   { CHIP_9220, "LAN9220" },
+   { CHIP_9221, "LAN9221" },
+   { 0, NULL },
+};
+
+#define DRIVERNAME "smc911x"
+
+#if defined (CONFIG_SMC911X_32_BIT) && \
+   defined (CONFIG_SMC911X_16_BIT)
+#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
+   CONFIG_SMC911X_16_BIT shall be set"
+#endif
+
+#if defined (CONFIG_SMC911X_32_BIT)
+static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
+{
+   return *(volatile u32*)(dev->iobase + offset);
+}
+u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+   __attribute__((weak, alias("__smc911x_reg_read")));
+
+static inline void __smc911x_reg_write(struct eth_device *dev,
+   u32 offset, u32 val)
+{
+   *(volatile u32*)(dev->iobase + offset) = val;
+}
+void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
+   __attribute__((weak, alias("__smc911x_reg_write")));
+#elif defined (CONFIG_SMC911X_16_BIT)
+static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+{
+   volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
+   return ((*addr_16 & 0x) | (*(addr_16 + 1) << 16));
+}
+static inline void smc911x_reg_write(struct eth_device *dev,
+   u32 offset, u32 val)
+{
+   *(volatile u16 *)(dev->iobase + offset) = (u16)val;
+   *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
+}
+#else
+#error "SMC911X: undefined bus width"
+#endif /* CONFIG_SMC911X_16_BIT */
+
+static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
+{
+   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   ;
+   smc911x_reg_write(dev, MAC_CSR_CMD,
+   MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
+   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   ;
+
+   return smc911x_reg_read(dev, MAC_CSR_DATA);
+}
+
+static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
+{
+   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   ;
+   smc911x_reg_write(dev, MAC_CSR_DATA, data);
+   smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
+   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   ;
+}
+
+static int smc911x_detect_chip(struct eth_device *dev)
+{
+   unsigned long val, i;
+
+   val = smc911x_reg_read(dev, BYTE_TEST);
+   if (val == 0x) {
+   /* Special case -- no chip present */
+   return -1;
+   } else if (val != 0x87654321) {
+   printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
+   return -1;
+   }
+
+   val = smc911x_reg_read(dev, ID_REV) >> 16;
+   for (i = 0; chip_ids[i].id != 0; i++) {
+   if (chip_ids[i].id == val) break;
+   }
+   if (!chip_ids[i].id) {
+   printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
+   return -1;
+   }
+
+   dev->priv = (void *)&chip_ids[i];
+
+   return 0;
+}
+
+static void smc911x_reset(struct eth_device *dev)
+{
+   int timeout;
+
+   /*
+*  Take out of PM setting first
+*  Device is already wake up if PMT_CTRL_READY bit is set
+*/
+   if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) {
+   /* Write to the bytetest will take out of powerdown */
+   smc911x_reg_write(dev, BYTE_TEST, 0x0);
+
+   t

[PATCH V4 05/13] net: smc911x: Fix potential memleak() in init fail path

[Marek Vasut]

Fix memleak in the init fail path, where if allocation or registration
of MDIO bus fails, then ethernet interface is not unregistered and the
private data are not freed, yet the probe function reports a failure.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
V4: No change
---
 drivers/net/smc911x.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index ceb4f81215..4459da5945 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -282,15 +282,23 @@ int smc911x_initialize(u8 dev_num, int base_addr)
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
int retval;
struct mii_dev *mdiodev = mdio_alloc();
-   if (!mdiodev)
+   if (!mdiodev) {
+   eth_unregister(dev);
+   free(dev);
return -ENOMEM;
+   }
+
strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = smc911x_miiphy_read;
mdiodev->write = smc911x_miiphy_write;
 
retval = mdio_register(mdiodev);
-   if (retval < 0)
+   if (retval < 0) {
+   mdio_free(mdiodev);
+   eth_unregister(dev);
+   free(dev);
return retval;
+   }
 #endif
 
return 1;
-- 
2.25.1

[PATCH V4 04/13] net: smc911x: Invert the logic in smc911x_miiphy_{read, write}()

[Marek Vasut]

Invert the logic in the aforementioned functions to reduce indent,
no functional change.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
V4: No change
---
 drivers/net/smc911x.c | 27 ---
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 6da6c89546..ceb4f81215 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -216,24 +216,29 @@ static int smc911x_recv(struct eth_device *dev)
 static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
   int reg)
 {
-   u16 val = 0;
struct eth_device *dev = eth_get_dev_by_name(bus->name);
-   if (dev) {
-   int retval = smc911x_eth_phy_read(dev, phy, reg, &val);
-   if (retval < 0)
-   return retval;
-   return val;
-   }
-   return -ENODEV;
+   u16 val = 0;
+   int ret;
+
+   if (!dev)
+   return -ENODEV;
+
+   ret = smc911x_eth_phy_read(dev, phy, reg, &val);
+   if (ret < 0)
+   return ret;
+
+   return val;
 }
 /* wrapper for smc911x_eth_phy_write */
 static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
int reg, u16 val)
 {
struct eth_device *dev = eth_get_dev_by_name(bus->name);
-   if (dev)
-   return smc911x_eth_phy_write(dev, phy, reg, val);
-   return -ENODEV;
+
+   if (!dev)
+   return -ENODEV;
+
+   return smc911x_eth_phy_write(dev, phy, reg, val);
 }
 #endif
 
-- 
2.25.1

[PATCH V4 00/13] net: smc911x: Convert to DM

[Marek Vasut]

Perform DM conversion of the SMC911x driver.

Note that the DT compatible is set only for 9115 , so this might need
to be changed.

Marek Vasut (13):
  net: smc911x: Remove pkt_data_{push,pull}
  net: smc911x: Replace malloc()+memset() with calloc()
  net: smc911x: Rename smc911x_rx() to smc911x_recv()
  net: smc911x: Invert the logic in smc911x_miiphy_{read,write}()
  net: smc911x: Fix potential memleak() in init fail path
  net: smc911x: Pull MII registration into separate function
  net: smc911x: Inline all functions from header file
  net: smc911x: Drop weak alias from 32bit accessors
  net: smc911x: Convert IO accessors to {read,write}{w,l}()
  net: smc911x: Pass around driver private data
  net: smc911x: Clean up the status handling in smc911x_recv()
  net: smc911x: Split non-DM specific bits from common code
  net: smc911x: Add DM support

 drivers/net/Kconfig  |   2 +
 drivers/net/smc911x.c| 559 +--
 drivers/net/smc911x.h| 157 
 examples/standalone/Makefile |   5 +-
 examples/standalone/smc911x_eeprom.c | 150 +++
 5 files changed, 602 insertions(+), 271 deletions(-)

Cc: Joe Hershberger 
Cc: Masahiro Yamada 

-- 
2.25.1

[PATCH V4 02/13] net: smc911x: Replace malloc()+memset() with calloc()

[Marek Vasut]

Replace combination of malloc()+memset() with calloc() as the behavior
is exactly the same and the amount of code is reduced.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: - Use kzalloc()
- Return -ENOMEM on alloc fail
V3: - Switch back to calloc(), it's not worth pulling in all the
  linux-compatibility complexity
V4: No change
---
 drivers/net/smc911x.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 24b4eaeb3f..2c72e3469d 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -242,11 +242,9 @@ int smc911x_initialize(u8 dev_num, int base_addr)
unsigned long addrl, addrh;
struct eth_device *dev;
 
-   dev = malloc(sizeof(*dev));
-   if (!dev) {
-   return -1;
-   }
-   memset(dev, 0, sizeof(*dev));
+   dev = calloc(1, sizeof(*dev));
+   if (!dev)
+   return -ENOMEM;
 
dev->iobase = base_addr;
 
-- 
2.25.1

[PATCH V4 03/13] net: smc911x: Rename smc911x_rx() to smc911x_recv()

[Marek Vasut]

Rename the function to keep the naming scheme consistent,
no functional change.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
V4: No change
---
 drivers/net/smc911x.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 2c72e3469d..6da6c89546 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -184,7 +184,7 @@ static void smc911x_halt(struct eth_device *dev)
smc911x_handle_mac_address(dev);
 }
 
-static int smc911x_rx(struct eth_device *dev)
+static int smc911x_recv(struct eth_device *dev)
 {
u32 *data = (u32 *)net_rx_packets[0];
u32 pktlen, tmplen;
@@ -269,7 +269,7 @@ int smc911x_initialize(u8 dev_num, int base_addr)
dev->init = smc911x_init;
dev->halt = smc911x_halt;
dev->send = smc911x_send;
-   dev->recv = smc911x_rx;
+   dev->recv = smc911x_recv;
sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
 
eth_register(dev);
-- 
2.25.1

[PATCH V4 01/13] net: smc911x: Remove pkt_data_{push,pull}

[Marek Vasut]

These functions are never used and are likely a pre-DM remnant
from times long past, just remove them.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
V4: No change
---
 drivers/net/smc911x.c | 9 ++---
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 257b0385c2..24b4eaeb3f 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -13,11 +13,6 @@
 
 #include "smc911x.h"
 
-u32 pkt_data_pull(struct eth_device *dev, u32 addr) \
-   __attribute__ ((weak, alias ("smc911x_reg_read")));
-void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) \
-   __attribute__ ((weak, alias ("smc911x_reg_write")));
-
 static void smc911x_handle_mac_address(struct eth_device *dev)
 {
unsigned long addrh, addrl;
@@ -157,7 +152,7 @@ static int smc911x_send(struct eth_device *dev, void 
*packet, int length)
tmplen = (length + 3) / 4;
 
while (tmplen--)
-   pkt_data_push(dev, TX_DATA_FIFO, *data++);
+   smc911x_reg_write(dev, TX_DATA_FIFO, *data++);
 
/* wait for transmission */
while (!((smc911x_reg_read(dev, TX_FIFO_INF) &
@@ -203,7 +198,7 @@ static int smc911x_rx(struct eth_device *dev)
 
tmplen = (pktlen + 3) / 4;
while (tmplen--)
-   *data++ = pkt_data_pull(dev, RX_DATA_FIFO);
+   *data++ = smc911x_reg_read(dev, RX_DATA_FIFO);
 
if (status & RX_STS_ES)
printf(DRIVERNAME
-- 
2.25.1

[PATCH v1] x86: acpi: Describe USB 3 host controller found on Intel Tangier

[Andy Shevchenko]

USB 3 host controller may be described in ACPI to allow users alter
the properties or other features. Describe it for Intel Tangier SoC.

Signed-off-by: Andy Shevchenko 
---
 .../asm/arch-tangier/acpi/southcluster.asl| 38 +++
 1 file changed, 38 insertions(+)

diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl 
b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
index 6ccdc25136..953780a936 100644
--- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
+++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
@@ -321,6 +321,44 @@ Device (PCI0)
 }
 }
 
+Device (DWC3)
+{
+Name (_ADR, 0x0011)
+Name (_DEP, Package ()
+{
+^IPC1.PMIC
+})
+
+Method (_STA, 0, NotSerialized)
+{
+Return (STA_VISIBLE)
+}
+
+Device (RHUB)
+{
+Name (_ADR, Zero)
+
+// GPLD: Generate Port Location Data (PLD)
+Method (GPLD, 1, Serialized) {
+Name (PCKG, Package () {
+Buffer (0x10) {}
+})
+
+// REV: Revision 0x02 for ACPI 5.0
+CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
+Store (0x02, REV)
+
+// VISI: Port visibility to user per port
+CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
+Store (Arg0, VISI)
+Return (PCKG)
+}
+
+Device (HS01) { Name (_ADR, 1) }
+Device (SS01) { Name (_ADR, 2) }
+}
+}
+
 Device (PWM0)
 {
 Name (_ADR, 0x0017)
-- 
2.25.1

Re: latest u-boot branch for Marvell Armada 88F3720

[Stefan Roese]

Hi Moritz,

On 25.03.20 16:05, Moritz Berghof wrote:

My Name is Moritz and we evaluate the Marvell Armada 88F3720
on the Marvell ESPRESSObin and the TURRIS MOX.

Does someone know, where is the actual or latest u-boot branch
for Marvell Armada 88F3720 placed? At the u-boot master or a
marvell custodian tree or somewhere else? Does Marvell develop
u-boot still for their Armada 88F3720 and when yes, where?


Those boards are supported in general in mainline U-Boot. Though I
have to admit, that I didn't test any of those ports recently. I
added Marek Behun to Cc, as he did submit most of the Turris Mox
stuff and has more recent experience than I do.


Because that https://github.com/MarvellEmbeddedProcessors/u-boot-marvell,
which is well used on the ESPRESSObin is NOT up-to-date. 4 Years ago,
last commit.


I just took a quick glance at this repo and there are newer, more
recent branches, e.g. "u-boot-2018.03-armada-18.12". But still, this
is far away from mainline, I agree.

Perhaps someone else (Marek) can comment on the current status of
mainline U-Boot on those boards? Is something missing? If yes, it
would be great to get it ported to mainline.

Thanks,
Stefan


I'm searching an actual u-boot platform for my Chip.


I look forward to your reply, thank you very much,

--
Moritz Berghof
Software Engineer
Tel. +49 30 921028-209
Fax +49 30 921028-020
mberg...@phoenixcontact.com
www.phoenixcontact.com

PHOENIX CONTACT Cyber Security GmbH
Richard-Willstätter-Straße 6
D-12489 Berlin
Register Court: AG Charlottenburg, HR B 202908
Geschäftsführer/General Manager: Kilian Golm


...
PHOENIX CONTACT Cyber Security GmbH
Richard-Willstätter-Straße 6
D-12489 Berlin
  
Register Court: AG Charlottenburg, HR B 202908

Geschäftsführer/General Manager: Kilian Golm

Re: [PATCH V3 10/13] net: smc911x: Pass around driver private data

[Harald Seiler]

Hi Marek,

On Wed, 2020-03-25 at 16:36 +0100, Marek Vasut wrote:
> Introduce a private data structure for this driver with embedded
> struct eth_device and pass it around. This prepares the driver to
> work with both DM and non-DM systems.
> 
> Signed-off-by: Marek Vasut 
> Cc: Joe Hershberger 
> Cc: Masahiro Yamada 
> ---
> V2: No change
> V3: No change
> ---
>  drivers/net/smc911x.c | 230 ++
>  1 file changed, 123 insertions(+), 107 deletions(-)
> 
> diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
> index 364f8c5da8..786ab220b2 100644
> --- a/drivers/net/smc911x.c
> +++ b/drivers/net/smc911x.c
> @@ -20,6 +20,13 @@ struct chip_id {
>   char *name;
>  };
>  
> +struct smc911x_priv {
> + struct eth_device   dev;
> + phys_addr_t iobase;
> + const struct chip_id*chipid;
> + unsigned char   enetaddr[6];
> +};
> +
>  static const struct chip_id chip_ids[] =  {
>   { CHIP_89218, "LAN89218" },
>   { CHIP_9115, "LAN9115" },
> @@ -45,57 +52,57 @@ static const struct chip_id chip_ids[] =  {
>  #endif
>  
>  #if defined (CONFIG_SMC911X_32_BIT)
> -static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
> +static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
>  {
> - return readl(dev->iobase + offset);
> + return readl(priv->iobase + offset);
>  }
>  
> -static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
> +static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
>  {
> - writel(val, dev->iobase + offset);
> + writel(val, priv->iobase + offset);
>  }
>  #elif defined (CONFIG_SMC911X_16_BIT)
> -static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
> +static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
>  {
> - return (readw(dev->iobase + offset) & 0x) |
> -(readw(dev->iobase + offset + 2) << 16);
> + return (readw(priv->iobase + offset) & 0x) |
> +(readw(priv->iobase + offset + 2) << 16);
>  }
> -static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
> +static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
>  {
> - writew(val & 0x, dev->iobase + offset);
> - writew(val >> 16, dev->iobase + offset + 2);
> + writew(val & 0x, priv->iobase + offset);
> + writew(val >> 16, priv->iobase + offset + 2);
>  }
>  #else
>  #error "SMC911X: undefined bus width"
>  #endif /* CONFIG_SMC911X_16_BIT */
>  
> -static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
> +static u32 smc911x_get_mac_csr(struct smc911x_priv *priv, u8 reg)
>  {
> - while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
> + while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
>   ;
> - smc911x_reg_write(dev, MAC_CSR_CMD,
> + smc911x_reg_write(priv, MAC_CSR_CMD,
>   MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
> - while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
> + while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
>   ;
>  
> - return smc911x_reg_read(dev, MAC_CSR_DATA);
> + return smc911x_reg_read(priv, MAC_CSR_DATA);
>  }
>  
> -static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
> +static void smc911x_set_mac_csr(struct smc911x_priv *priv, u8 reg, u32 data)
>  {
> - while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
> + while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
>   ;
> - smc911x_reg_write(dev, MAC_CSR_DATA, data);
> - smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
> - while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
> + smc911x_reg_write(priv, MAC_CSR_DATA, data);
> + smc911x_reg_write(priv, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
> + while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
>   ;
>  }
>  
> -static int smc911x_detect_chip(struct eth_device *dev)
> +static int smc911x_detect_chip(struct smc911x_priv *priv)
>  {
>   unsigned long val, i;
>  
> - val = smc911x_reg_read(dev, BYTE_TEST);
> + val = smc911x_reg_read(priv, BYTE_TEST);
>   if (val == 0x) {
>   /* Special case -- no chip present */
>   return -1;
> @@ -104,7 +111,7 @@ static int smc911x_detect_chip(struct eth_device *dev)
>   return -1;
>   }
>  
> - val = smc911x_reg_read(dev, ID_REV) >> 16;
> + val = smc911x_reg_read(priv, ID_REV) >> 16;
>   for (i = 0; chip_ids[i].id != 0; i++) {
>   if (chip_ids[i].id == val) break;
>   }
> @@ -113,12 +120,12 @@ static int smc911x_detect_chip(struct eth_device *dev)
>   return -1;
>   }
>  
> - dev->priv = (void *)&chip_ids[i];
> + priv->chipid = &chip_ids[i];
>  
>   return 0;
>  }
>  
> -static void smc9

Re: STM32MP1 boot slow

[Marek Vasut]

On 3/25/20 4:57 PM, Patrick DELAUNAY wrote:
> Hi,

Hi,

>> From: Marek Vasut 
>> Sent: mercredi 25 mars 2020 00:39
>>
>> Hi,
>>
>> I was looking at the STM32MP1 boot time and I noticed it takes about 2 
>> seconds
>> to get to U-Boot.
> 
> Thanks for the feedback.
> 
> To be clear, the SPL is not the ST priority as we have many limitation 
> (mainly on
> power management) for the SPL boot chain (stm32mp15_basic_defconfig):
> Rom code => SPL => U-Boot
> 
> The preconized boot chain for STM32MP1 is Rom code => TF-A => U-Boot
> (stm32mp15_trusted_defconfg).

I don't want to use TF-A because it's problematic at best.

However, these issues I listed here are present also in U-Boot, so this
comment is irrelevant anyway.

>> One problem is the insane I2C timing calculation in stm32f7 i2c driver, 
>> which is
>> almost a mallocator and CPU stress test and takes about 1 second to complete 
>> in
>> SPL -- we need some simpler replacement for that, possibly the one in DWC I2C
>> driver might do?
> 
> Our first idea to manage this I2C settings (prescaler/timings setting) was to 
> set this values 
> in device tree, but this binding was refused so this function 
> stm32_i2c_choose_solution()
> provided the better settings for any input clock and I2C frequency (called 
> for each probe).
> 
> But it is brutal and not optimum solution: try all the solution to found the 
> better one.
> And the performance problem of this loop (shared code between Linux / 
> U-Boot/TF-A drivers)
> had be already see/checked on ST side in TF-A context.
> 
> We try to improve the solution, without success, but finally the performance 
> issue
> was solved by dcache activation in TF-A before to execute this loop.

That's not a solution but a workaround.

> But as in SPL the data cache is not activated, this loop has terrible 
> performance.
> 
> We need to ding again of this topic for U-Boot point of view
> (SPL & also in U-Boot, before relocation and after relocation) .
> 
> And I had shared this issue with the ST owner of this code.
> 
> For information, I add some trace and I get for same code execution on DK2 
> board.
> - 440ms in SPL (dcache OFF)
> - 36ms in U-Boot (dcache ON)

Still, this is a workaround.

The calculation should be simplified. And why do you even need all that
memory allocations in there ?

>> Another item I found is that, in U-Boot, initf_dm() takes about half a 
>> second and so
>> does serial_init(). I didn't dig into it to find out why, but I suspect it 
>> has to do with
>> the massive amount of UCLASSes the DM has to traverse OR with the CPU being
>> slow at that point, as the clock driver didn't get probed just yet.
>>
>> Thoughts ?
> 
> Yes, it is the first parsing of device tree, and it is really slow... 
> directly linked to device
> tree size and libfdt.
> 
> And because it is done before relocation (before dache enable).
> 
> Measurement on DK2 = 649ms
> 
> It is a other topic in my TODO list.
> 
> I want to explore livetree activation to reduce the DT parsing time.
>  
> And also activate dcache in pre-location stage
> (and potentially also in SPL as it was done in 
> http://patchwork.ozlabs.org/patch/699899/)
> 
> A other solution (workaround ?) is to reduced the U-Boot device-tree (remove 
> all the nodes not used in
> U-Boot in soc file stm32mp157.dtsi or use /omit-if-no-ref/ for pincontrol 
> nodes).
> 
> See bootsage report on DK2, we have dm_f = 648ms
> 
> STM32MP> bootstage report
> Timer summary in microseconds (12 records):
>MarkElapsed  Stage
>   0  0  reset
> 195,613195,613  SPL
> 837,867642,254  end SPL
> 840,117  2,250  board_init_f
>   2,739,639  1,899,522  board_init_r
>   3,066,815327,176  id=64
>   3,103,377 36,562  id=65
>   3,104,078701  main_loop
>   3,142,171 38,093  id=175
> 
> Accumulated time:
> 38,124  dm_spl
> 41,956  dm_r
>648,861  dm_f
> 
> For information the time in spent in 
>   dm_extended_scan_fdt
>   => dm_scan_fdt(blob, pre_reloc_only);
> 
> This time is reduce d (few millisecond) 
> with http://patchwork.ozlabs.org/patch/1240117/
> 
> But only the data cache activation before relocation should improve this part.

For this one, I think we have no better options than the Dcache indeed.
Thanks

Re: [PATCH v3 3/3] configs: rpi_4_32b_defconfig: enable SDHCI_SDMA config

[Matthias Brugger]

On 24/03/2020 23:58, Jaehoon Chung wrote:
> Enable SDHCI_SDMA configuration.
> 
> Signed-off-by: Jaehoon Chung 
> Reviewed-by: Peng Fan 
> Reviewed-by: Minkyu Kang 
> ---
>  configs/rpi_4_32b_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
> index 72cda5d949..7189914606 100644
> --- a/configs/rpi_4_32b_defconfig
> +++ b/configs/rpi_4_32b_defconfig
> @@ -25,6 +25,7 @@ CONFIG_DFU_MMC=y
>  CONFIG_DM_KEYBOARD=y
>  CONFIG_DM_MMC=y
>  CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_SDMA=y

RPi4 can only do DMA transfers to the first GiB of memory. I wasn't sucessfull
in understanding the mmc/sdhci code to see where we take the dma-ranges property
into account so that we don't use an address > 1 GiB.

Are we safe in this regard? If we are, then we can also enable this for
rpi_4_defconfig and rpi_arm64_defconfig I think.

Regards,
Matthias

>  CONFIG_MMC_SDHCI_BCM2835=y
>  CONFIG_DM_ETH=y
>  CONFIG_BCMGENET=y
> 

RE: STM32MP1 boot slow

[Patrick DELAUNAY]

Hi,

> From: Marek Vasut 
> Sent: mercredi 25 mars 2020 00:39
> 
> Hi,
> 
> I was looking at the STM32MP1 boot time and I noticed it takes about 2 seconds
> to get to U-Boot.

Thanks for the feedback.

To be clear, the SPL is not the ST priority as we have many limitation (mainly 
on
power management) for the SPL boot chain (stm32mp15_basic_defconfig):
Rom code => SPL => U-Boot

The preconized boot chain for STM32MP1 is Rom code => TF-A => U-Boot
(stm32mp15_trusted_defconfg).

> One problem is the insane I2C timing calculation in stm32f7 i2c driver, which 
> is
> almost a mallocator and CPU stress test and takes about 1 second to complete 
> in
> SPL -- we need some simpler replacement for that, possibly the one in DWC I2C
> driver might do?

Our first idea to manage this I2C settings (prescaler/timings setting) was to 
set this values 
in device tree, but this binding was refused so this function 
stm32_i2c_choose_solution()
provided the better settings for any input clock and I2C frequency (called for 
each probe).

But it is brutal and not optimum solution: try all the solution to found the 
better one.
And the performance problem of this loop (shared code between Linux / 
U-Boot/TF-A drivers)
had be already see/checked on ST side in TF-A context.

We try to improve the solution, without success, but finally the performance 
issue
was solved by dcache activation in TF-A before to execute this loop.

But as in SPL the data cache is not activated, this loop has terrible 
performance.

We need to ding again of this topic for U-Boot point of view
(SPL & also in U-Boot, before relocation and after relocation) .

And I had shared this issue with the ST owner of this code.

For information, I add some trace and I get for same code execution on DK2 
board.
- 440ms in SPL (dcache OFF)
- 36ms in U-Boot (dcache ON)

> Another item I found is that, in U-Boot, initf_dm() takes about half a second 
> and so
> does serial_init(). I didn't dig into it to find out why, but I suspect it 
> has to do with
> the massive amount of UCLASSes the DM has to traverse OR with the CPU being
> slow at that point, as the clock driver didn't get probed just yet.
>
> Thoughts ?

Yes, it is the first parsing of device tree, and it is really slow... directly 
linked to device
tree size and libfdt.

And because it is done before relocation (before dache enable).

Measurement on DK2 = 649ms

It is a other topic in my TODO list.

I want to explore livetree activation to reduce the DT parsing time.
 
And also activate dcache in pre-location stage
(and potentially also in SPL as it was done in 
http://patchwork.ozlabs.org/patch/699899/)

A other solution (workaround ?) is to reduced the U-Boot device-tree (remove 
all the nodes not used in
U-Boot in soc file stm32mp157.dtsi or use /omit-if-no-ref/ for pincontrol 
nodes).

See bootsage report on DK2, we have dm_f = 648ms

STM32MP> bootstage report
Timer summary in microseconds (12 records):
   MarkElapsed  Stage
  0  0  reset
195,613195,613  SPL
837,867642,254  end SPL
840,117  2,250  board_init_f
  2,739,639  1,899,522  board_init_r
  3,066,815327,176  id=64
  3,103,377 36,562  id=65
  3,104,078701  main_loop
  3,142,171 38,093  id=175

Accumulated time:
38,124  dm_spl
41,956  dm_r
   648,861  dm_f

For information the time in spent in 
dm_extended_scan_fdt
=> dm_scan_fdt(blob, pre_reloc_only);

This time is reduce d (few millisecond) 
with http://patchwork.ozlabs.org/patch/1240117/

But only the data cache activation before relocation should improve this part.

> 
> --
> Best regards,
> Marek Vasut

Regards
Patrick

[PATCH V3 13/13] net: smc911x: Add DM support

[Marek Vasut]

Add support for U-Boot DM and DT probing. Furthermore, build the
SMC911x standalone EEPROM example only for the non-DM case, as it
is not converted yet.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: Drop the board-specific bits
Hide SMC911X_BASE from Kconfig if DM_ETH
V3: No change
---
 drivers/net/Kconfig  |   2 +
 drivers/net/smc911x.c| 114 +++
 examples/standalone/Makefile |   5 +-
 3 files changed, 120 insertions(+), 1 deletion(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4d1013c984..095395813a 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -388,11 +388,13 @@ config SMC911X
 
 if SMC911X
 
+if !DM_ETH
 config SMC911X_BASE
hex "SMC911X Base Address"
help
  Define this to hold the physical address
  of the device (I/O space)
+endif #DM_ETH
 
 choice
prompt "SMC911X bus width"
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 7d88089da5..908a4753b3 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -21,7 +21,9 @@ struct chip_id {
 };
 
 struct smc911x_priv {
+#ifndef CONFIG_DM_ETH
struct eth_device   dev;
+#endif
phys_addr_t iobase;
const struct chip_id*chipid;
unsigned char   enetaddr[6];
@@ -370,6 +372,8 @@ static int smc911x_recv_common(struct smc911x_priv *priv, 
u32 *data)
return pktlen;
 }
 
+#ifndef CONFIG_DM_ETH
+
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 /* wrapper for smc911x_eth_phy_read */
 static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
@@ -516,3 +520,113 @@ err_detect:
free(priv);
return ret;
 }
+
+#else  /* ifdef CONFIG_DM_ETH */
+
+static int smc911x_start(struct udevice *dev)
+{
+   struct eth_pdata *plat = dev_get_platdata(dev);
+   struct smc911x_priv *priv = dev_get_priv(dev);
+
+   memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
+
+   return smc911x_init_common(priv);
+}
+
+static void smc911x_stop(struct udevice *dev)
+{
+   struct smc911x_priv *priv = dev_get_priv(dev);
+
+   smc911x_halt_common(priv);
+}
+
+static int smc911x_send(struct udevice *dev, void *packet, int length)
+{
+   struct smc911x_priv *priv = dev_get_priv(dev);
+   int ret;
+
+   ret = smc911x_send_common(priv, packet, length);
+
+   return ret ? 0 : -ETIMEDOUT;
+}
+
+static int smc911x_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+   struct smc911x_priv *priv = dev_get_priv(dev);
+   u32 *data = (u32 *)net_rx_packets[0];
+   int ret;
+
+   ret = smc911x_recv_common(priv, data);
+   if (ret)
+   *packetp = (void *)data;
+
+   return ret ? ret : -EAGAIN;
+}
+
+static int smc911x_bind(struct udevice *dev)
+{
+   return device_set_name(dev, dev->name);
+}
+
+static int smc911x_probe(struct udevice *dev)
+{
+   struct smc911x_priv *priv = dev_get_priv(dev);
+   unsigned long addrh, addrl;
+   int ret;
+
+   /* Try to detect chip. Will fail if not present. */
+   ret = smc911x_detect_chip(priv);
+   if (ret)
+   return ret;
+
+   addrh = smc911x_get_mac_csr(priv, ADDRH);
+   addrl = smc911x_get_mac_csr(priv, ADDRL);
+   if (!(addrl == 0x && addrh == 0x)) {
+   /* address is obtained from optional eeprom */
+   priv->enetaddr[0] = addrl;
+   priv->enetaddr[1] = addrl >>  8;
+   priv->enetaddr[2] = addrl >> 16;
+   priv->enetaddr[3] = addrl >> 24;
+   priv->enetaddr[4] = addrh;
+   priv->enetaddr[5] = addrh >> 8;
+   }
+
+   return 0;
+}
+
+static int smc911x_ofdata_to_platdata(struct udevice *dev)
+{
+   struct smc911x_priv *priv = dev_get_priv(dev);
+   struct eth_pdata *pdata = dev_get_platdata(dev);
+
+   pdata->iobase = devfdt_get_addr(dev);
+   priv->iobase = pdata->iobase;
+
+   return 0;
+}
+
+static const struct eth_ops smc911x_ops = {
+   .start  = smc911x_start,
+   .send   = smc911x_send,
+   .recv   = smc911x_recv,
+   .stop   = smc911x_stop,
+};
+
+static const struct udevice_id smc911x_ids[] = {
+   { .compatible = "smsc,lan9115" },
+   { }
+};
+
+U_BOOT_DRIVER(smc911x) = {
+   .name   = "eth_smc911x",
+   .id = UCLASS_ETH,
+   .of_match   = smc911x_ids,
+   .bind   = smc911x_bind,
+   .ofdata_to_platdata = smc911x_ofdata_to_platdata,
+   .probe  = smc911x_probe,
+   .ops= &smc911x_ops,
+   .priv_auto_alloc_size = sizeof(struct smc911x_priv),
+   .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+   .flags  = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
index 0b17a91804..6b061bac69 100644
--- a/examples/standalone/Makefile
+++ b/exampl

[PATCH] arm: dts: rockchip: rk3399-roc-pc: Enable FE1.1 USB 2.0 HUB on roc-rk3399-pc

[sunil]

From: Suniel Mahesh 

roc-rk3399-pc has an FE1.1 USB 2.0 HUB which connects two USB ports
(HOST1 and HOST2). For end devices to work we need to enable USB hub
so that HOST detects there presence and enumerates them accordingly.
This requires explicit pinctrl within gpio enablement.

Signed-off-by: Suniel Mahesh 
---
Note:
1. tested this on roc-rk3399-pc board version roc-rk3399-pc-v1.1-a 2018-9-25
2. after this changeset, HOST1 works but HOST2 still doesnt work. I have
tested them with linux-next, linux-rockchip and Firefly's source (both u-boot
and kernel), HOST2 doesn't work.
3. Request to test this changetest who have access to target and please advice
on HOST2
---
 arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi 
b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
index 5746442..598e0e2 100644
--- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
@@ -14,6 +14,16 @@
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
+
+   vcc_hub_en: vcc_hub_en-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&hub_rst>;
+   regulator-name = "vcc_hub_en";
+   regulator-always-on;
+   };
 };
 
 &vdd_log {
-- 
2.7.4

[PATCH V3 12/13] net: smc911x: Split non-DM specific bits from common code

[Marek Vasut]

Split network handling functions into non-DM specific parts and
common code in preparation for conversion to DM.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
Acked-by: Joe Hershberger 
---
V2: Add AB from Joe
V3: No change
---
 drivers/net/smc911x.c | 57 ---
 1 file changed, 43 insertions(+), 14 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 4a1145e641..7d88089da5 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -277,9 +277,8 @@ static void smc911x_enable(struct smc911x_priv *priv)
MAC_CR_HBDIS);
 }
 
-static int smc911x_init(struct eth_device *dev, bd_t * bd)
+static int smc911x_init_common(struct smc911x_priv *priv)
 {
-   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
const struct chip_id *id = priv->chipid;
 
printf(DRIVERNAME ": detected %s controller\n", id->name);
@@ -297,9 +296,9 @@ static int smc911x_init(struct eth_device *dev, bd_t * bd)
return 0;
 }
 
-static int smc911x_send(struct eth_device *dev, void *packet, int length)
+static int smc911x_send_common(struct smc911x_priv *priv,
+  void *packet, int length)
 {
-   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
u32 *data = (u32*)packet;
u32 tmplen;
u32 status;
@@ -337,18 +336,14 @@ static int smc911x_send(struct eth_device *dev, void 
*packet, int length)
return -1;
 }
 
-static void smc911x_halt(struct eth_device *dev)
+static void smc911x_halt_common(struct smc911x_priv *priv)
 {
-   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
-
smc911x_reset(priv);
smc911x_handle_mac_address(priv);
 }
 
-static int smc911x_recv(struct eth_device *dev)
+static int smc911x_recv_common(struct smc911x_priv *priv, u32 *data)
 {
-   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
-   u32 *data = (u32 *)net_rx_packets[0];
u32 pktlen, tmplen;
u32 status;
 
@@ -365,14 +360,14 @@ static int smc911x_recv(struct eth_device *dev)
while (tmplen--)
*data++ = smc911x_reg_read(priv, RX_DATA_FIFO);
 
-   if (status & RX_STS_ES)
+   if (status & RX_STS_ES) {
printf(DRIVERNAME
": dropped bad packet. Status: 0x%08x\n",
status);
-   else
-   net_process_received_packet(net_rx_packets[0], pktlen);
+   return 0;
+   }
 
-   return 0;
+   return pktlen;
 }
 
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
@@ -435,6 +430,40 @@ static int smc911x_initialize_mii(struct smc911x_priv 
*priv)
 }
 #endif
 
+static int smc911x_init(struct eth_device *dev, bd_t *bd)
+{
+   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+   return smc911x_init_common(priv);
+}
+
+static void smc911x_halt(struct eth_device *dev)
+{
+   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+   smc911x_halt_common(priv);
+}
+
+static int smc911x_send(struct eth_device *dev, void *packet, int length)
+{
+   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+   return smc911x_send_common(priv, packet, length);
+}
+
+static int smc911x_recv(struct eth_device *dev)
+{
+   struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+   u32 *data = (u32 *)net_rx_packets[0];
+   int ret;
+
+   ret = smc911x_recv_common(priv, data);
+   if (ret)
+   net_process_received_packet(net_rx_packets[0], ret);
+
+   return ret;
+}
+
 int smc911x_initialize(u8 dev_num, int base_addr)
 {
unsigned long addrl, addrh;
-- 
2.25.1

[PATCH V3 11/13] net: smc911x: Clean up the status handling in smc911x_recv()

[Marek Vasut]

Invert the status handling logic in smc911x_recv(), to make the
function easier to read, no functional change.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: Simplify RX_FIFO_INF_RXSUSED mask handling
s@Invest@Invert@
V3: No change
---
 drivers/net/smc911x.c | 30 --
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 786ab220b2..4a1145e641 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -352,23 +352,25 @@ static int smc911x_recv(struct eth_device *dev)
u32 pktlen, tmplen;
u32 status;
 
-   if ((smc911x_reg_read(priv, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
-   status = smc911x_reg_read(priv, RX_STATUS_FIFO);
-   pktlen = (status & RX_STS_PKT_LEN) >> 16;
+   status = smc911x_reg_read(priv, RX_FIFO_INF);
+   if (!(status & RX_FIFO_INF_RXSUSED))
+   return 0;
 
-   smc911x_reg_write(priv, RX_CFG, 0);
+   status = smc911x_reg_read(priv, RX_STATUS_FIFO);
+   pktlen = (status & RX_STS_PKT_LEN) >> 16;
 
-   tmplen = (pktlen + 3) / 4;
-   while (tmplen--)
-   *data++ = smc911x_reg_read(priv, RX_DATA_FIFO);
+   smc911x_reg_write(priv, RX_CFG, 0);
 
-   if (status & RX_STS_ES)
-   printf(DRIVERNAME
-   ": dropped bad packet. Status: 0x%08x\n",
-   status);
-   else
-   net_process_received_packet(net_rx_packets[0], pktlen);
-   }
+   tmplen = (pktlen + 3) / 4;
+   while (tmplen--)
+   *data++ = smc911x_reg_read(priv, RX_DATA_FIFO);
+
+   if (status & RX_STS_ES)
+   printf(DRIVERNAME
+   ": dropped bad packet. Status: 0x%08x\n",
+   status);
+   else
+   net_process_received_packet(net_rx_packets[0], pktlen);
 
return 0;
 }
-- 
2.25.1

[PATCH V3 07/13] net: smc911x: Inline all functions from header file

[Marek Vasut]

Inline all the functions from the header file, as they are not used
outside of the driver or the standalone EEPROM example.

Note that this does introduce considerable amount of duplication in
the standalone EEPROM example, however that one has to be rewritten
anyway, roughly such that the SMC911x driver would expose DM EEPROM
interface and the standalone example would use that.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
---
 drivers/net/smc911x.c| 157 ++-
 drivers/net/smc911x.h| 157 ---
 examples/standalone/smc911x_eeprom.c | 156 ++
 3 files changed, 312 insertions(+), 158 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 65c25f3bfd..ff285f14b4 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -10,9 +10,165 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "smc911x.h"
 
+struct chip_id {
+   u16 id;
+   char *name;
+};
+
+static const struct chip_id chip_ids[] =  {
+   { CHIP_89218, "LAN89218" },
+   { CHIP_9115, "LAN9115" },
+   { CHIP_9116, "LAN9116" },
+   { CHIP_9117, "LAN9117" },
+   { CHIP_9118, "LAN9118" },
+   { CHIP_9211, "LAN9211" },
+   { CHIP_9215, "LAN9215" },
+   { CHIP_9216, "LAN9216" },
+   { CHIP_9217, "LAN9217" },
+   { CHIP_9218, "LAN9218" },
+   { CHIP_9220, "LAN9220" },
+   { CHIP_9221, "LAN9221" },
+   { 0, NULL },
+};
+
+#define DRIVERNAME "smc911x"
+
+#if defined (CONFIG_SMC911X_32_BIT) && \
+   defined (CONFIG_SMC911X_16_BIT)
+#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
+   CONFIG_SMC911X_16_BIT shall be set"
+#endif
+
+#if defined (CONFIG_SMC911X_32_BIT)
+static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
+{
+   return *(volatile u32*)(dev->iobase + offset);
+}
+u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+   __attribute__((weak, alias("__smc911x_reg_read")));
+
+static inline void __smc911x_reg_write(struct eth_device *dev,
+   u32 offset, u32 val)
+{
+   *(volatile u32*)(dev->iobase + offset) = val;
+}
+void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
+   __attribute__((weak, alias("__smc911x_reg_write")));
+#elif defined (CONFIG_SMC911X_16_BIT)
+static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+{
+   volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
+   return ((*addr_16 & 0x) | (*(addr_16 + 1) << 16));
+}
+static inline void smc911x_reg_write(struct eth_device *dev,
+   u32 offset, u32 val)
+{
+   *(volatile u16 *)(dev->iobase + offset) = (u16)val;
+   *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
+}
+#else
+#error "SMC911X: undefined bus width"
+#endif /* CONFIG_SMC911X_16_BIT */
+
+static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
+{
+   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   ;
+   smc911x_reg_write(dev, MAC_CSR_CMD,
+   MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
+   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   ;
+
+   return smc911x_reg_read(dev, MAC_CSR_DATA);
+}
+
+static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
+{
+   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   ;
+   smc911x_reg_write(dev, MAC_CSR_DATA, data);
+   smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
+   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   ;
+}
+
+static int smc911x_detect_chip(struct eth_device *dev)
+{
+   unsigned long val, i;
+
+   val = smc911x_reg_read(dev, BYTE_TEST);
+   if (val == 0x) {
+   /* Special case -- no chip present */
+   return -1;
+   } else if (val != 0x87654321) {
+   printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
+   return -1;
+   }
+
+   val = smc911x_reg_read(dev, ID_REV) >> 16;
+   for (i = 0; chip_ids[i].id != 0; i++) {
+   if (chip_ids[i].id == val) break;
+   }
+   if (!chip_ids[i].id) {
+   printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
+   return -1;
+   }
+
+   dev->priv = (void *)&chip_ids[i];
+
+   return 0;
+}
+
+static void smc911x_reset(struct eth_device *dev)
+{
+   int timeout;
+
+   /*
+*  Take out of PM setting first
+*  Device is already wake up if PMT_CTRL_READY bit is set
+*/
+   if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) {
+   /* Write to the bytetest will take out of powerdown */
+   smc911x_reg_write(dev, BYTE_TEST, 0x0);
+
+   timeout = 10;
+

[PATCH V3 10/13] net: smc911x: Pass around driver private data

[Marek Vasut]

Introduce a private data structure for this driver with embedded
struct eth_device and pass it around. This prepares the driver to
work with both DM and non-DM systems.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
---
 drivers/net/smc911x.c | 230 ++
 1 file changed, 123 insertions(+), 107 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 364f8c5da8..786ab220b2 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -20,6 +20,13 @@ struct chip_id {
char *name;
 };
 
+struct smc911x_priv {
+   struct eth_device   dev;
+   phys_addr_t iobase;
+   const struct chip_id*chipid;
+   unsigned char   enetaddr[6];
+};
+
 static const struct chip_id chip_ids[] =  {
{ CHIP_89218, "LAN89218" },
{ CHIP_9115, "LAN9115" },
@@ -45,57 +52,57 @@ static const struct chip_id chip_ids[] =  {
 #endif
 
 #if defined (CONFIG_SMC911X_32_BIT)
-static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
 {
-   return readl(dev->iobase + offset);
+   return readl(priv->iobase + offset);
 }
 
-static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
+static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
 {
-   writel(val, dev->iobase + offset);
+   writel(val, priv->iobase + offset);
 }
 #elif defined (CONFIG_SMC911X_16_BIT)
-static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
 {
-   return (readw(dev->iobase + offset) & 0x) |
-  (readw(dev->iobase + offset + 2) << 16);
+   return (readw(priv->iobase + offset) & 0x) |
+  (readw(priv->iobase + offset + 2) << 16);
 }
-static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
+static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
 {
-   writew(val & 0x, dev->iobase + offset);
-   writew(val >> 16, dev->iobase + offset + 2);
+   writew(val & 0x, priv->iobase + offset);
+   writew(val >> 16, priv->iobase + offset + 2);
 }
 #else
 #error "SMC911X: undefined bus width"
 #endif /* CONFIG_SMC911X_16_BIT */
 
-static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
+static u32 smc911x_get_mac_csr(struct smc911x_priv *priv, u8 reg)
 {
-   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
-   smc911x_reg_write(dev, MAC_CSR_CMD,
+   smc911x_reg_write(priv, MAC_CSR_CMD,
MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
-   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
 
-   return smc911x_reg_read(dev, MAC_CSR_DATA);
+   return smc911x_reg_read(priv, MAC_CSR_DATA);
 }
 
-static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
+static void smc911x_set_mac_csr(struct smc911x_priv *priv, u8 reg, u32 data)
 {
-   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
-   smc911x_reg_write(dev, MAC_CSR_DATA, data);
-   smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
-   while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+   smc911x_reg_write(priv, MAC_CSR_DATA, data);
+   smc911x_reg_write(priv, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
+   while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
 }
 
-static int smc911x_detect_chip(struct eth_device *dev)
+static int smc911x_detect_chip(struct smc911x_priv *priv)
 {
unsigned long val, i;
 
-   val = smc911x_reg_read(dev, BYTE_TEST);
+   val = smc911x_reg_read(priv, BYTE_TEST);
if (val == 0x) {
/* Special case -- no chip present */
return -1;
@@ -104,7 +111,7 @@ static int smc911x_detect_chip(struct eth_device *dev)
return -1;
}
 
-   val = smc911x_reg_read(dev, ID_REV) >> 16;
+   val = smc911x_reg_read(priv, ID_REV) >> 16;
for (i = 0; chip_ids[i].id != 0; i++) {
if (chip_ids[i].id == val) break;
}
@@ -113,12 +120,12 @@ static int smc911x_detect_chip(struct eth_device *dev)
return -1;
}
 
-   dev->priv = (void *)&chip_ids[i];
+   priv->chipid = &chip_ids[i];
 
return 0;
 }
 
-static void smc911x_reset(struct eth_device *dev)
+static void smc911x_reset(struct smc911x_priv *priv)
 {
int timeout;
 
@@ -126,14 +133,14 @@ static void smc911x_reset(struct eth_device *dev)
 *  Take out of PM 

[PATCH V3 08/13] net: smc911x: Drop weak alias from 32bit accessors

[Marek Vasut]

These accessors are not overridden by any board, and even if they were,
this is something which should be handled via DM now, so remove the
weak alias option. Moreover, drop the inline keyword, as the compiler
can decide better.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: s@overriden@overridden@
V3: No change
---
 drivers/net/smc911x.c| 14 --
 examples/standalone/smc911x_eeprom.c | 16 +---
 2 files changed, 9 insertions(+), 21 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index ff285f14b4..effee5367c 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -44,28 +44,22 @@ static const struct chip_id chip_ids[] =  {
 #endif
 
 #if defined (CONFIG_SMC911X_32_BIT)
-static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
+static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
 {
return *(volatile u32*)(dev->iobase + offset);
 }
-u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
-   __attribute__((weak, alias("__smc911x_reg_read")));
 
-static inline void __smc911x_reg_write(struct eth_device *dev,
-   u32 offset, u32 val)
+static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
 {
*(volatile u32*)(dev->iobase + offset) = val;
 }
-void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
-   __attribute__((weak, alias("__smc911x_reg_write")));
 #elif defined (CONFIG_SMC911X_16_BIT)
-static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
 {
volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
return ((*addr_16 & 0x) | (*(addr_16 + 1) << 16));
 }
-static inline void smc911x_reg_write(struct eth_device *dev,
-   u32 offset, u32 val)
+static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
 {
*(volatile u16 *)(dev->iobase + offset) = (u16)val;
*(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
diff --git a/examples/standalone/smc911x_eeprom.c 
b/examples/standalone/smc911x_eeprom.c
index 19ad9e6297..270588bcf5 100644
--- a/examples/standalone/smc911x_eeprom.c
+++ b/examples/standalone/smc911x_eeprom.c
@@ -51,28 +51,22 @@ static const struct chip_id chip_ids[] =  {
 };
 
 #if defined (CONFIG_SMC911X_32_BIT)
-static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
+static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
 {
return *(volatile u32*)(dev->iobase + offset);
 }
-u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
-   __attribute__((weak, alias("__smc911x_reg_read")));
 
-static inline void __smc911x_reg_write(struct eth_device *dev,
-   u32 offset, u32 val)
+static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
 {
*(volatile u32*)(dev->iobase + offset) = val;
 }
-void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
-   __attribute__((weak, alias("__smc911x_reg_write")));
 #elif defined (CONFIG_SMC911X_16_BIT)
-static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
 {
volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
-   return ((*addr_16 & 0x) | (*(addr_16 + 1) << 16));
+   return (*addr_16 & 0x) | (*(addr_16 + 1) << 16);
 }
-static inline void smc911x_reg_write(struct eth_device *dev,
-   u32 offset, u32 val)
+static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
 {
*(volatile u16 *)(dev->iobase + offset) = (u16)val;
*(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
-- 
2.25.1

[PATCH V3 06/13] net: smc911x: Pull MII registration into separate function

[Marek Vasut]

Pull the MII interface registration into separate function to avoid the
ifdeffery in smc911x_initialize(). Moreover, adjust the fail path such
that we use goto labels.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: New patch
V3: No change
---
 drivers/net/smc911x.c | 64 +++
 1 file changed, 40 insertions(+), 24 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 4459da5945..65c25f3bfd 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -240,12 +240,39 @@ static int smc911x_miiphy_write(struct mii_dev *bus, int 
phy, int devad,
 
return smc911x_eth_phy_write(dev, phy, reg, val);
 }
+
+static int smc911x_initialize_mii(struct eth_device *dev)
+{
+   struct mii_dev *mdiodev = mdio_alloc();
+   int ret;
+
+   if (!mdiodev)
+   return -ENOMEM;
+
+   strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+   mdiodev->read = smc911x_miiphy_read;
+   mdiodev->write = smc911x_miiphy_write;
+
+   ret = mdio_register(mdiodev);
+   if (ret < 0) {
+   mdio_free(mdiodev);
+   return ret;
+   }
+
+   return 0;
+}
+#else
+static int smc911x_initialize_mii(struct eth_device *dev)
+{
+   return 0;
+}
 #endif
 
 int smc911x_initialize(u8 dev_num, int base_addr)
 {
unsigned long addrl, addrh;
struct eth_device *dev;
+   int ret;
 
dev = calloc(1, sizeof(*dev));
if (!dev)
@@ -254,9 +281,10 @@ int smc911x_initialize(u8 dev_num, int base_addr)
dev->iobase = base_addr;
 
/* Try to detect chip. Will fail if not present. */
-   if (smc911x_detect_chip(dev)) {
-   free(dev);
-   return 0;
+   ret = smc911x_detect_chip(dev);
+   if (ret) {
+   ret = 0;/* Card not detected is not an error */
+   goto err_detect;
}
 
addrh = smc911x_get_mac_csr(dev, ADDRH);
@@ -279,27 +307,15 @@ int smc911x_initialize(u8 dev_num, int base_addr)
 
eth_register(dev);
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-   int retval;
-   struct mii_dev *mdiodev = mdio_alloc();
-   if (!mdiodev) {
-   eth_unregister(dev);
-   free(dev);
-   return -ENOMEM;
-   }
-
-   strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
-   mdiodev->read = smc911x_miiphy_read;
-   mdiodev->write = smc911x_miiphy_write;
-
-   retval = mdio_register(mdiodev);
-   if (retval < 0) {
-   mdio_free(mdiodev);
-   eth_unregister(dev);
-   free(dev);
-   return retval;
-   }
-#endif
+   ret = smc911x_initialize_mii(dev);
+   if (ret)
+   goto err_mii;
 
return 1;
+
+err_mii:
+   eth_unregister(dev);
+err_detect:
+   free(dev);
+   return ret;
 }
-- 
2.25.1

[PATCH V3 04/13] net: smc911x: Invert the logic in smc911x_miiphy_{read, write}()

[Marek Vasut]

Invert the logic in the aforementioned functions to reduce indent,
no functional change.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
---
 drivers/net/smc911x.c | 27 ---
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 6da6c89546..ceb4f81215 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -216,24 +216,29 @@ static int smc911x_recv(struct eth_device *dev)
 static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
   int reg)
 {
-   u16 val = 0;
struct eth_device *dev = eth_get_dev_by_name(bus->name);
-   if (dev) {
-   int retval = smc911x_eth_phy_read(dev, phy, reg, &val);
-   if (retval < 0)
-   return retval;
-   return val;
-   }
-   return -ENODEV;
+   u16 val = 0;
+   int ret;
+
+   if (!dev)
+   return -ENODEV;
+
+   ret = smc911x_eth_phy_read(dev, phy, reg, &val);
+   if (ret < 0)
+   return ret;
+
+   return val;
 }
 /* wrapper for smc911x_eth_phy_write */
 static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
int reg, u16 val)
 {
struct eth_device *dev = eth_get_dev_by_name(bus->name);
-   if (dev)
-   return smc911x_eth_phy_write(dev, phy, reg, val);
-   return -ENODEV;
+
+   if (!dev)
+   return -ENODEV;
+
+   return smc911x_eth_phy_write(dev, phy, reg, val);
 }
 #endif
 
-- 
2.25.1

[PATCH V3 05/13] net: smc911x: Fix potential memleak() in init fail path

[Marek Vasut]

Fix memleak in the init fail path, where if allocation or registration
of MDIO bus fails, then ethernet interface is not unregistered and the
private data are not freed, yet the probe function reports a failure.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
---
 drivers/net/smc911x.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index ceb4f81215..4459da5945 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -282,15 +282,23 @@ int smc911x_initialize(u8 dev_num, int base_addr)
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
int retval;
struct mii_dev *mdiodev = mdio_alloc();
-   if (!mdiodev)
+   if (!mdiodev) {
+   eth_unregister(dev);
+   free(dev);
return -ENOMEM;
+   }
+
strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = smc911x_miiphy_read;
mdiodev->write = smc911x_miiphy_write;
 
retval = mdio_register(mdiodev);
-   if (retval < 0)
+   if (retval < 0) {
+   mdio_free(mdiodev);
+   eth_unregister(dev);
+   free(dev);
return retval;
+   }
 #endif
 
return 1;
-- 
2.25.1

[PATCH V3 03/13] net: smc911x: Rename smc911x_rx() to smc911x_recv()

[Marek Vasut]

Rename the function to keep the naming scheme consistent,
no functional change.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
---
 drivers/net/smc911x.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 2c72e3469d..6da6c89546 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -184,7 +184,7 @@ static void smc911x_halt(struct eth_device *dev)
smc911x_handle_mac_address(dev);
 }
 
-static int smc911x_rx(struct eth_device *dev)
+static int smc911x_recv(struct eth_device *dev)
 {
u32 *data = (u32 *)net_rx_packets[0];
u32 pktlen, tmplen;
@@ -269,7 +269,7 @@ int smc911x_initialize(u8 dev_num, int base_addr)
dev->init = smc911x_init;
dev->halt = smc911x_halt;
dev->send = smc911x_send;
-   dev->recv = smc911x_rx;
+   dev->recv = smc911x_recv;
sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
 
eth_register(dev);
-- 
2.25.1

[PATCH V3 02/13] net: smc911x: Replace malloc()+memset() with calloc()

[Marek Vasut]

Replace combination of malloc()+memset() with calloc() as the behavior
is exactly the same and the amount of code is reduced.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: - Use kzalloc()
- Return -ENOMEM on alloc fail
V3: - Switch back to calloc(), it's not worth pulling in all the
  linux-compatibility complexity
---
 drivers/net/smc911x.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 24b4eaeb3f..2c72e3469d 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -242,11 +242,9 @@ int smc911x_initialize(u8 dev_num, int base_addr)
unsigned long addrl, addrh;
struct eth_device *dev;
 
-   dev = malloc(sizeof(*dev));
-   if (!dev) {
-   return -1;
-   }
-   memset(dev, 0, sizeof(*dev));
+   dev = calloc(1, sizeof(*dev));
+   if (!dev)
+   return -ENOMEM;
 
dev->iobase = base_addr;
 
-- 
2.25.1

[PATCH V3 01/13] net: smc911x: Remove pkt_data_{push,pull}

[Marek Vasut]

These functions are never used and are likely a pre-DM remnant
from times long past, just remove them.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
---
 drivers/net/smc911x.c | 9 ++---
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 257b0385c2..24b4eaeb3f 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -13,11 +13,6 @@
 
 #include "smc911x.h"
 
-u32 pkt_data_pull(struct eth_device *dev, u32 addr) \
-   __attribute__ ((weak, alias ("smc911x_reg_read")));
-void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) \
-   __attribute__ ((weak, alias ("smc911x_reg_write")));
-
 static void smc911x_handle_mac_address(struct eth_device *dev)
 {
unsigned long addrh, addrl;
@@ -157,7 +152,7 @@ static int smc911x_send(struct eth_device *dev, void 
*packet, int length)
tmplen = (length + 3) / 4;
 
while (tmplen--)
-   pkt_data_push(dev, TX_DATA_FIFO, *data++);
+   smc911x_reg_write(dev, TX_DATA_FIFO, *data++);
 
/* wait for transmission */
while (!((smc911x_reg_read(dev, TX_FIFO_INF) &
@@ -203,7 +198,7 @@ static int smc911x_rx(struct eth_device *dev)
 
tmplen = (pktlen + 3) / 4;
while (tmplen--)
-   *data++ = pkt_data_pull(dev, RX_DATA_FIFO);
+   *data++ = smc911x_reg_read(dev, RX_DATA_FIFO);
 
if (status & RX_STS_ES)
printf(DRIVERNAME
-- 
2.25.1

[PATCH V3 09/13] net: smc911x: Convert IO accessors to {read, write}{w, l}()

[Marek Vasut]

Convert the IO accessors to standard ones instead of using volatile
void pointers, as those do not cover all the bus access details.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Masahiro Yamada 
---
V2: No change
V3: No change
---
 drivers/net/smc911x.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index effee5367c..364f8c5da8 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "smc911x.h"
@@ -46,23 +47,23 @@ static const struct chip_id chip_ids[] =  {
 #if defined (CONFIG_SMC911X_32_BIT)
 static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
 {
-   return *(volatile u32*)(dev->iobase + offset);
+   return readl(dev->iobase + offset);
 }
 
 static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
 {
-   *(volatile u32*)(dev->iobase + offset) = val;
+   writel(val, dev->iobase + offset);
 }
 #elif defined (CONFIG_SMC911X_16_BIT)
 static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
 {
-   volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
-   return ((*addr_16 & 0x) | (*(addr_16 + 1) << 16));
+   return (readw(dev->iobase + offset) & 0x) |
+  (readw(dev->iobase + offset + 2) << 16);
 }
 static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
 {
-   *(volatile u16 *)(dev->iobase + offset) = (u16)val;
-   *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
+   writew(val & 0x, dev->iobase + offset);
+   writew(val >> 16, dev->iobase + offset + 2);
 }
 #else
 #error "SMC911X: undefined bus width"
-- 
2.25.1

[PATCH V3 00/13] net: smc911x: Convert to DM

[Marek Vasut]

Perform DM conversion of the SMC911x driver.

Note that the DT compatible is set only for 9115 , so this might need
to be changed.

Marek Vasut (13):
  net: smc911x: Remove pkt_data_{push,pull}
  net: smc911x: Replace malloc()+memset() with calloc()
  net: smc911x: Rename smc911x_rx() to smc911x_recv()
  net: smc911x: Invert the logic in smc911x_miiphy_{read,write}()
  net: smc911x: Fix potential memleak() in init fail path
  net: smc911x: Pull MII registration into separate function
  net: smc911x: Inline all functions from header file
  net: smc911x: Drop weak alias from 32bit accessors
  net: smc911x: Convert IO accessors to {read,write}{w,l}()
  net: smc911x: Pass around driver private data
  net: smc911x: Clean up the status handling in smc911x_recv()
  net: smc911x: Split non-DM specific bits from common code
  net: smc911x: Add DM support

 drivers/net/Kconfig  |   2 +
 drivers/net/smc911x.c| 559 +--
 drivers/net/smc911x.h| 157 
 examples/standalone/Makefile |   5 +-
 examples/standalone/smc911x_eeprom.c | 150 +++
 5 files changed, 602 insertions(+), 271 deletions(-)

Cc: Joe Hershberger 
Cc: Masahiro Yamada 

-- 
2.25.1

Re: [PATCH 00/12] net: smc911x: Convert to DM

[Marek Vasut]

On 3/24/20 2:41 AM, Adam Ford wrote:
> On Sat, Mar 21, 2020 at 11:57 AM Marek Vasut  wrote:
>>
>> On 3/17/20 7:17 AM, Masahiro Yamada wrote:
>>> Hi Marek,
>>
>> Hi,
>>
>>> On Mon, Mar 16, 2020 at 1:59 AM Marek Vasut  wrote:

 Perform DM conversion of the SMC911x driver. Note that as I do not have
> 
> Thanks for taking this on.
> 
 any hardware with this chip, I only compile-tested this conversion. But
 it seems Yamada-san has one, so please test.
> 
> I have a DM3730 with this chip.  Without DM_ETH, the
> omap3_logic_defconfig doesn't compile with the following errors:
> 
> drivers/net/smc911x.c: In function ‘smc911x_initialize’:
> drivers/net/smc911x.c:477:2: error: ‘dev’ undeclared (first use in
> this function)
>   477 |  dev = kzalloc(sizeof(*priv), GFP_KERNEL);
>   |  ^~~
> drivers/net/smc911x.c:477:2: note: each undeclared identifier is
> reported only once for each function it appears in
> drivers/net/smc911x.c:477:8: warning: implicit declaration of function
> ‘kzalloc’; did you mean ‘calloc’? [-Wimplicit-function-declaration]
>   477 |  dev = kzalloc(sizeof(*priv), GFP_KERNEL);
>   |^~~
>   |calloc
> drivers/net/smc911x.c:477:31: error: ‘GFP_KERNEL’ undeclared (first
> use in this function)
>   477 |  dev = kzalloc(sizeof(*priv), GFP_KERNEL);
>   |   ^~
> make[1]: *** [scripts/Makefile.build:279: drivers/net/smc911x.o] Error 1

Well, replace the kzalloc with calloc.

>>> With a quick test on my board, it worked for me.
>>>
>>> I will leave comments to each patch, but
>>> they are mostly nit-picking.
>>>
>>> Thanks for the cleanups and the conversion.
>>
>> I fixed most of those, thanks for testing.
> 
> If I enable DM_ETH, I need to make a few changes to the device tree,
> but with those changes, I was able to get the Ethernet working.
> The OMAP3 boards have the Ethernet node attached to their GPMC bus
> which currently doesn't have a driver.  Making the GPMC compatible
> with 'simple-bus' wasn't sufficient. With only that change, the system
> would hang while trying to probe the network interface.
> 
> What I ended up having to do was add the following to my root node:
> 
> ethernet@0800 {
>  compatible = "smsc,lan9221","smsc,lan9115";
>  reg = <0x0800>;
>  bank-width = <2>;
>  vddvario-supply = <&vddvario>;
>  vdd33a-supply = <&vdd33a>;
>  reg-io-width = <4>;
>  smsc,save-mac-address;
> };
> 
> I didn't look to see if I needed all those entries, but I was able to
> get an IP address and ping a different computer.
> If there is a future revision to fix the default build errors, I can
> add similar comments with my tested-by if you want to CC me.

I'm about to send a V3.

Re: [PATCH V2 02/13] net: smc911x: Replace malloc()+memset() with calloc()

[Marek Vasut]

On 3/22/20 6:38 PM, Masahiro Yamada wrote:
> On Sun, Mar 22, 2020 at 2:06 AM Marek Vasut  wrote:
>>
>> Replace combination of malloc()+memset() with calloc() as the behavior
> 
> calloc() -> kzalloc()
> 
> to sync with the actual code.
> 
> Please fix the subject as well.

I'm switching this back to calloc(), it's not worth pulling in all the
linux compat stuff for one single function.

latest u-boot branch for Marvell Armada 88F3720

[Moritz Berghof]

Dear U-Boot developers,

My Name is Moritz and we evaluate the Marvell Armada 88F3720 on the Marvell 
ESPRESSObin and the TURRIS MOX.

Does someone know, where is the actual or latest u-boot branch for Marvell 
Armada 88F3720 placed? At the u-boot master or a marvell custodian tree or 
somewhere else? Does Marvell develop u-boot still for their Armada 88F3720 and 
when yes, where?

Because that https://github.com/MarvellEmbeddedProcessors/u-boot-marvell, which 
is well used on the ESPRESSObin is NOT up-to-date. 4 Years ago, last commit.

I'm searching an actual u-boot platform for my Chip.


I look forward to your reply, thank you very much,

--
Moritz Berghof
Software Engineer
Tel. +49 30 921028-209
Fax +49 30 921028-020
mberg...@phoenixcontact.com
www.phoenixcontact.com

PHOENIX CONTACT Cyber Security GmbH
Richard-Willstätter-Straße 6
D-12489 Berlin
Register Court: AG Charlottenburg, HR B 202908
Geschäftsführer/General Manager: Kilian Golm


...
PHOENIX CONTACT Cyber Security GmbH 
Richard-Willstätter-Straße 6  
D-12489 Berlin  
 
Register Court: AG Charlottenburg, HR B 202908 
Geschäftsführer/General Manager: Kilian Golm

Re: ext4: invalid extent block on imx7

[Tom Rini]

On Wed, Mar 25, 2020 at 07:32:30AM +0100, Jan Kiszka wrote:
> On 20.03.20 19:21, Tom Rini wrote:
> > On Mon, Mar 16, 2020 at 08:09:53PM +0100, Jan Kiszka wrote:
> > > Hi all,
> > > 
> > > => ls mmc 0:1 /usr/lib/linux-image-4.9.11-1.3.0-dirty
> > > CACHE: Misaligned operation at range [bdfff998, bdfffd98]
> > > CACHE: Misaligned operation at range [bdfff998, bdfffd98]
> > > CACHE: Misaligned operation at range [bdfff998, bdfffd98]
> > > CACHE: Misaligned operation at range [bdfff998, bdfffd98]
> > > invalid extent block
> > > 
> > > I'm using master (50be9f0e1ccc) on the MCIMX7SABRE, defconfig.
> > > 
> > > What could this be? The filesystem is fine from Linux POV.
> > 
> > Use tune2fs -l and see if there's any new'ish features enabled that we
> > need some sort of check-and-reject for would be my first guess.
> > 
> 
> Here are the reported feature flags:
> 
> has_journal ext_attr resize_inode dir_index filetype extent 64bit flex_bg
> sparse_super large_file huge_file dir_nlink extra_isize metadata_csum

Of that, only metadata_csum means that you can't write to that image,
but you're just trying to read and that should be fine.  Can you go back
in time a little and see if this problem persists or if it's been
introduced of late?  Or recreate it on other platforms/SoCs?  Thanks!

> Anything too fancy in here? But the method of creating this filesystem does
> not deviate from many other setups we have for U-Boot (on other boards).

Yes, but for some time now e2fsprogs has introduced new default features
that require compatibility checks.

-- 
Tom


signature.asc
Description: PGP signature

[PATCH 2/7] uart: pl011: Add proper DM clock support

[Andre Przywara]

Even though the PL011 UART driver claims to be DM compliant, it does not
really a good job with parsing DT nodes. U-Boot seems to adhere to a
non-standard binding, either requiring to have a "skip-init" property in
the node, or to have an extra "clock" property holding the base
*frequency* value for the baud rate generator.
DTs in the U-Boot tree seem to have been hacked to match this
requirement.

The official binding does not mention any of these properties, instead
recommends a standard "clocks" property to point to the baud base clock.

Some boards use simple "fixed-clock" providers, which U-Boot readily
supports, so let's add some simple DM clock code to the PL011 driver to
learn the rate of the first clock, as described by the official binding.

These clock nodes seem to be not ready very early in the boot process,
so provide a fallback value, by re-using the already existing
CONFIG_PL011_CLOCK variable.

Signed-off-by: Andre Przywara 
---
 drivers/serial/serial_pl01x.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 2a5f256184..1ab0ccadb2 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -12,6 +12,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -340,14 +341,21 @@ static const struct udevice_id pl01x_serial_id[] ={
 int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
 {
struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
+   struct clk clk;
fdt_addr_t addr;
+   int ret;
 
addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
 
plat->base = addr;
-   plat->clock = dev_read_u32_default(dev, "clock", 1);
+   plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
+   ret = clk_get_by_index(dev, 0, &clk);
+   if (!ret) {
+   clk_enable(&clk);
+   plat->clock = clk_get_rate(&clk);
+   }
plat->type = dev_get_driver_data(dev);
plat->skip_init = dev_read_bool(dev, "skip-init");
 
-- 
2.14.5

[PATCH 7/7] arm: vexpress64: Remove unneeded CONFIG_ check

[Andre Przywara]

CONFIG_SEMIHOSTING is selected for the VFP target by the means of
Kconfig already, there is no need to check this in the header file.

Signed-off-by: Andre Przywara 
---
 include/configs/vexpress_aemv8a.h | 6 --
 1 file changed, 6 deletions(-)

diff --git a/include/configs/vexpress_aemv8a.h 
b/include/configs/vexpress_aemv8a.h
index b02caae96c..adbe886ae5 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -7,12 +7,6 @@
 #ifndef __VEXPRESS_AEMV8A_H
 #define __VEXPRESS_AEMV8A_H
 
-#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
-#ifndef CONFIG_SEMIHOSTING
-#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
-#endif
-#endif
-
 #define CONFIG_REMAKE_ELF
 
 /* Link Definitions */
-- 
2.14.5

[PATCH 5/7] arm: juno: Use PSCI based reset

[Andre Przywara]

So far the Juno board wasn't implementing reset. Let's just use the
already existing PSCI_RESET based method to avoid any extra code.

Signed-off-by: Andre Przywara 
Acked-by: Liviu Dudau 
---
 arch/arm/Kconfig | 2 ++
 board/armltd/vexpress64/vexpress64.c | 4 +---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2d3e79bf52..f5c8ae1b8d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1132,6 +1132,8 @@ config TARGET_VEXPRESS64_JUNO
select OF_BOARD
select CLK
select DM_SERIAL
+   select ARM_PSCI_FW
+   select PSCI_RESET
 
 config TARGET_LS2080A_EMU
bool "Support ls2080a_emu"
diff --git a/board/armltd/vexpress64/vexpress64.c 
b/board/armltd/vexpress64/vexpress64.c
index ba49b32e58..5c7a8f55f0 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -139,9 +139,7 @@ void *board_fdt_blob_setup(void)
 }
 #endif
 
-/*
- * Board specific reset that is system reset.
- */
+/* Actual reset is done via PSCI. */
 void reset_cpu(ulong addr)
 {
 }
-- 
2.14.5

[PATCH 6/7] arm: juno: enable USB

[Andre Przywara]

The Juno board features a standard compliant EHCI/OHCI USB host
controller pair, which we can just enable.
The platform data is taken from the device tree.

This allows to use USB mass storage (the only storage on a Juno r0)
for loading.

Signed-off-by: Andre Przywara 
Acked-by: Liviu Dudau 
---
 arch/arm/Kconfig   | 4 
 configs/vexpress_aemv8a_juno_defconfig | 5 +
 include/configs/vexpress_aemv8a.h  | 5 +
 3 files changed, 14 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f5c8ae1b8d..dad7596683 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1134,6 +1134,10 @@ config TARGET_VEXPRESS64_JUNO
select DM_SERIAL
select ARM_PSCI_FW
select PSCI_RESET
+   select DM
+   select BLK
+   select USB
+   select DM_USB
 
 config TARGET_LS2080A_EMU
bool "Support ls2080a_emu"
diff --git a/configs/vexpress_aemv8a_juno_defconfig 
b/configs/vexpress_aemv8a_juno_defconfig
index 6cb21e7a1b..ca7aa5ab02 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_ARMFLASH=y
 CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
 CONFIG_CMD_UBI=y
+CONFIG_CMD_USB=y
 # CONFIG_ISO_PARTITION is not set
 # CONFIG_EFI_PARTITION is not set
 CONFIG_ENV_IS_IN_FLASH=y
@@ -41,3 +42,7 @@ CONFIG_SYS_FLASH_CFI=y
 CONFIG_SMC911X=y
 CONFIG_SMC911X_BASE=0x01800
 CONFIG_SMC911X_32_BIT=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
diff --git a/include/configs/vexpress_aemv8a.h 
b/include/configs/vexpress_aemv8a.h
index d788d21acf..b02caae96c 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -211,6 +211,11 @@
 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
 #define CONFIG_SYS_MAX_FLASH_BANKS 1
 
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+#endif
+
 #define CONFIG_SYS_FLASH_EMPTY_INFO/* flinfo indicates empty blocks */
 #define FLASH_MAX_SECTOR_SIZE  0x0004
 
-- 
2.14.5

[PATCH 4/7] arm: juno: Enable OF_CONTROL

[Andre Przywara]

The Arm Juno board was still somewhat stuck in "hardcoded land", even
though there are stable DTs around, and one happens to actually be on
the memory mapped NOR flash.

Enable the configuration options to let the board use OF_CONTROL, and
add a routine to find the address of the DTB partition in NOR
flash, to use that for U-Boot's own purposes.
This can also passed on via $fdtcontroladdr to any kernel or EFI
application, removing the need to actually load a device tree.

Since the existing "afs" command and its flash routines require
flash_init() to be called before being usable, and this is done much
later in the boot process, we introduce a stripped-down partition finder
routine in vexpress64.c, to scan the NOR flash partitions for the
DT partition. This location is then used for U-Boot to find and probe
devices.

The name of the partition can be configured, if needed, but defaults
to "board.dtb", which is used by Linaro's firmware image provided.

Signed-off-by: Andre Przywara 
---
 arch/arm/Kconfig   |  5 +++
 board/armltd/vexpress64/Kconfig|  7 +
 board/armltd/vexpress64/vexpress64.c   | 57 ++
 configs/vexpress_aemv8a_juno_defconfig |  4 +--
 4 files changed, 70 insertions(+), 3 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5d367888d8..2d3e79bf52 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1127,6 +1127,11 @@ config TARGET_VEXPRESS64_JUNO
bool "Support Versatile Express Juno Development Platform"
select ARM64
select PL01X_SERIAL
+   select DM
+   select OF_CONTROL
+   select OF_BOARD
+   select CLK
+   select DM_SERIAL
 
 config TARGET_LS2080A_EMU
bool "Support ls2080a_emu"
diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
index 9014418433..1d13f542e6 100644
--- a/board/armltd/vexpress64/Kconfig
+++ b/board/armltd/vexpress64/Kconfig
@@ -9,4 +9,11 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
default "vexpress_aemv8a"
 
+config JUNO_DTB_PART
+   string "NOR flash partition holding DTB"
+   default "board.dtb"
+   help
+ The ARM partition name in the NOR flash memory holding the
+ device tree blob to configure U-Boot.
+
 endif
diff --git a/board/armltd/vexpress64/vexpress64.c 
b/board/armltd/vexpress64/vexpress64.c
index dd0ebdd303..ba49b32e58 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -82,6 +82,63 @@ int dram_init_banksize(void)
return 0;
 }
 
+#ifdef CONFIG_OF_BOARD
+#define JUNO_FLASH_SEC_SIZE(256 * 1024)
+static phys_addr_t find_dtb_in_nor_flash(const char *partname)
+{
+   phys_addr_t sector = CONFIG_SYS_FLASH_BASE;
+   int i;
+
+   for (i = 0;
+i < CONFIG_SYS_MAX_FLASH_SECT;
+i++, sector += JUNO_FLASH_SEC_SIZE) {
+   int len = strlen(partname) + 1;
+   int offs;
+   phys_addr_t imginfo;
+   u32 reg;
+
+   reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04);
+/* This makes up the string "HSLFTOOF" flash footer */
+   if (reg != 0x464F4F54U)
+   continue;
+   reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08);
+if (reg != 0x464C5348U)
+   continue;
+
+   for (offs = 0; offs < 32; offs += 4, len -= 4) {
+   reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs);
+   if (strncmp(partname + offs, (char *)®,
+   len > 4 ? 4 : len))
+   break;
+
+   if (len > 4)
+   continue;
+
+   reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10);
+   imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
+   reg = readl(imginfo + 0x54);
+
+   return CONFIG_SYS_FLASH_BASE +
+  reg * JUNO_FLASH_SEC_SIZE;
+   }
+   }
+
+   printf("No DTB found\n");
+
+   return ~0;
+}
+
+void *board_fdt_blob_setup(void)
+{
+   phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
+
+   if (fdt_rom_addr == ~0UL)
+   return NULL;
+
+   return (void *)fdt_rom_addr;
+}
+#endif
+
 /*
  * Board specific reset that is system reset.
  */
diff --git a/configs/vexpress_aemv8a_juno_defconfig 
b/configs/vexpress_aemv8a_juno_defconfig
index 8628d05e68..6cb21e7a1b 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -10,6 +10,7 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=1
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait 
earlycon=pl011,0x7ff8 debug user_debug=31 androidboot.hardware=juno 
loglevel=9"
+CONFIG_OF_BOARD=y
 # CONFIG_USE_BOOTCOMMAND is not set
 # CONFIG_DISPLA

[PATCH 3/7] arm: juno: Fix UART clock rate

[Andre Przywara]

The UART base clock rate was typo-ed in the header file, probably because
the reference (the Linux .dts) was also wrong[1].

Fix the number to make the baud rate more correct.

Signed-off-by: Andre Przywara 

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=39a1a8941b2
---
 include/configs/vexpress_aemv8a.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/vexpress_aemv8a.h 
b/include/configs/vexpress_aemv8a.h
index edb08b0e68..d788d21acf 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -102,7 +102,7 @@
 
 /* PL011 Serial Configuration */
 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
-#define CONFIG_PL011_CLOCK 7273800
+#define CONFIG_PL011_CLOCK 7372800
 #else
 #define CONFIG_PL011_CLOCK 2400
 #endif
-- 
2.14.5

[PATCH 1/7] arm: juno: Fix Juno address variables

[Andre Przywara]

The U-Boot documentation explains that variables ending with "_r" hold
addresses in DRAM, while those without that ending point to flash/ROM.
The default variables for the Juno board pointing to the kernel and DTB
load addresses were not complying with this scheme: they lack the
extension, but point to DRAM. This is particularly confusing since the
Juno board features parallel NOR flash, so there *is* a memory mapped
NOR address holding a DTB, for instance.

Fix the variables to use the proper names. On the way adjust the FDT
load address to be situated *before* the kernel, since users happened
to overwrite the DTB by the kernel clearing its .BSS section during
initialisation.

That fixes loading debug kernels, which happened to overwrite the DTB on
certain setups.

Signed-off-by: Andre Przywara 
Reviewed-by: Liviu Dudau 
---
 include/configs/vexpress_aemv8a.h | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/include/configs/vexpress_aemv8a.h 
b/include/configs/vexpress_aemv8a.h
index 9a9cec414c..edb08b0e68 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -138,35 +138,35 @@
 #define CONFIG_EXTRA_ENV_SETTINGS  \
"kernel_name=norkern\0" \
"kernel_alt_name=Image\0"   \
-   "kernel_addr=0x8008\0" \
+   "kernel_addr_r=0x8008\0" \
"initrd_name=ramdisk.img\0" \
-   "initrd_addr=0x8400\0"  \
+   "initrd_addr_r=0x8800\0"\
"fdtfile=board.dtb\0" \
"fdt_alt_name=juno\0" \
-   "fdt_addr=0x8300\0" \
+   "fdt_addr_r=0x8000\0" \
"fdt_high=0x\0" \
"initrd_high=0x\0" \
 
 /* Copy the kernel and FDT to DRAM memory and boot */
-#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \
+#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr_r} ;"\
"if test $? -eq 1; then "\
"  echo Loading ${kernel_alt_name} instead of "\
"${kernel_name}; "\
-   "  afs load ${kernel_alt_name} ${kernel_addr};"\
+   "  afs load ${kernel_alt_name} 
${kernel_addr_r};"\
"fi ; "\
-   "afs load  ${fdtfile} ${fdt_addr} ; " \
+   "afs load ${fdtfile} ${fdt_addr_r} ;"\
"if test $? -eq 1; then "\
"  echo Loading ${fdt_alt_name} instead of "\
"${fdtfile}; "\
-   "  afs load ${fdt_alt_name} ${fdt_addr}; "\
+   "  afs load ${fdt_alt_name} ${fdt_addr_r}; "\
"fi ; "\
-   "fdt addr ${fdt_addr}; fdt resize; " \
-   "if afs load  ${initrd_name} ${initrd_addr} ; "\
+   "fdt addr ${fdt_addr_r}; fdt resize; " \
+   "if afs load  ${initrd_name} ${initrd_addr_r} ; 
"\
"then "\
-   "  setenv initrd_param ${initrd_addr}; "\
+   "  setenv initrd_param ${initrd_addr_r}; "\
"  else setenv initrd_param -; "\
"fi ; " \
-   "booti ${kernel_addr} ${initrd_param} 
${fdt_addr}"
+   "booti ${kernel_addr_r} ${initrd_param} 
${fdt_addr_r}"
 
 
 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
-- 
2.14.5

[PATCH 0/7] Arm Juno board OF_CONTROL upgrade

[Andre Przywara]

Hi,

The Juno port in U-Boot didn't see much love lately, so it has fallen
a bit behind. We already get a build warning for using an old network
driver, but there is more:
- The port is using hardcoded information, even though we have quite
  decent DTs available to find things at runtime.
- There is no support for USB or PCI, which pretty much limits the board
  to load a kernel from flash (yuck!) or TFTP (at least!).
- Probably because of this, newer features like UEFI support don't work
  properly.
- There are minor things like less-than-ideal default load addresses and
  missing reset support.

This series is the first part of fixing this. The main part is to switch
the board port to use OF_CONTROL, so U-Boot will use a DT to configure
itself at runtime. This requires some update to the PL011 driver first
(patch 2/7), and allows us to simply enable USB in the defconfig (patch
6/7). USB requires two "usb reset" calls after the initial "usb start" to
recognise any devices, not sure why this is.
But eventually I am able to load grub from a USB hard drive and do a full
featured Ubuntu UEFI boot from there (with a distro kernel).

Patches 1, 3, and 7 are mere fixes, patch 4/7 does the actual OF_CONTROL
conversion.

I also have some proper DM_PCI compliant driver in an advanced state,
which allows to load from a SATA hard disk. Unfortunately there is no
sky2 network driver in U-Boot, so the Gigabit Ethernet chip connected
to PCI will not work easily.
I will post this once this is cleaned up and tested.

Converting the smc network driver to DM_ETH is on my list as well, but
the code is shared with some U-Boot *application* code, also used by
some PowerPC boards, so that's not really a low hanging fruit.
But it would remove the deprecation warning.

Cheers,
Andre

P.S. In case you want to test this without flashing it, you can
chainload U-Boot from an existing U-Boot installation:
$ mkimage -A arm64 -O u-boot -T standalone -C none -a 0xe000 -e 0xe000
  -d u-boot.bin -n U-Boot /srv/tftp/u-boot-juno.img
VExpress64# tftpboot 0xe000 u-boot-juno.img
VExpress64# bootm 0xe000

Andre Przywara (7):
  arm: juno: Fix Juno address variables
  uart: pl011: Add proper DM clock support
  arm: juno: Fix UART clock rate
  arm: juno: Enable OF_CONTROL
  arm: juno: Use PSCI based reset
  arm: juno: enable USB
  arm: vexpress64: Remove unneeded CONFIG_ check

 arch/arm/Kconfig   | 11 ++
 board/armltd/vexpress64/Kconfig|  7 
 board/armltd/vexpress64/vexpress64.c   | 61 --
 configs/vexpress_aemv8a_juno_defconfig |  9 +++--
 drivers/serial/serial_pl01x.c  | 10 +-
 include/configs/vexpress_aemv8a.h  | 35 ++-
 6 files changed, 108 insertions(+), 25 deletions(-)

-- 
2.14.5

Re: [PATCH 1/1] cmd: blkls: Add blkls command

[Niel Fourie]

Hi Stefan,

On 3/25/20 3:13 PM, Stefan Roese wrote:

+config CMD_LSBLK
+    depends on HAVE_BLOCK_DEVICE


You depend on CONFIG_HAVE_BLOCK_DEVICE here...


+
+#if CONFIG_IS_ENABLED(HAVE_BLOCK_DEVICE)


... so this #ifdef should not be necessary, right?


Oops, you are right... I forgot to take out the #ifdef after adding the 
Kconfig dependency. Will fix. Well spotted, thanks!


Best regards,
Niel Fourie

--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-21 Fax: +49-8142-66989-80  Email: lu...@denx.de

SPI driver for Raspberry Pi 4 (BMC2835)

[J. Holland]

Hi,

does anyone know, if there is a SPI driver for Raspberry Pi 4 in U-Boot?

I want to communicate with a TPM 2.0 via hardware SPI. So far I've compiled
mainline U-Boot with TPM driver support. However, the SPI driver seems to be
missing.

The linux kernel ships the driver (drivers/spi/spi-bcm2835.c). Does
anyone know
if there is there a port for U-Boot or if anyone is currently working on it?

In theory, I should be able to use the soft SPI driver (since there is a
GPIO
driver), but I'd very much prefer using the hardware SPI controller.

Many thanks!

Best,
Johannes

Re: [PATCH 1/1] cmd: blkls: Add blkls command

[Stefan Roese]

Hi Niel,

On 25.03.20 14:46, Niel Fourie wrote:

Add a command to print a list of available block device drivers,
and for each, the list of known block devices.

Signed-off-by: Niel Fourie 
---
  cmd/Kconfig |  8 
  cmd/Makefile|  1 +
  cmd/lsblk.c | 83 +
  test/py/tests/test_lsblk.py | 23 ++
  4 files changed, 115 insertions(+)
  create mode 100644 cmd/lsblk.c
  create mode 100644 test/py/tests/test_lsblk.py

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 6403bc45a5..ee6ff467ae 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1047,6 +1047,14 @@ config CMD_LOADS
help
  Load an S-Record file over serial line
  
+config CMD_LSBLK

+   depends on HAVE_BLOCK_DEVICE


You depend on CONFIG_HAVE_BLOCK_DEVICE here...


+   bool "lsblk - list block drivers and devices"
+   default n
+   help
+ Print list of available block device drivers, and for each, the list
+ of known block devices.
+
  config CMD_MMC
bool "mmc"
help
diff --git a/cmd/Makefile b/cmd/Makefile
index f1dd513a4b..6f80974a55 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -83,6 +83,7 @@ obj-$(CONFIG_CMD_LED) += led.o
  obj-$(CONFIG_CMD_LICENSE) += license.o
  obj-y += load.o
  obj-$(CONFIG_CMD_LOG) += log.o
+obj-$(CONFIG_CMD_LSBLK) += lsblk.o
  obj-$(CONFIG_ID_EEPROM) += mac.o
  obj-$(CONFIG_CMD_MD5SUM) += md5sum.o
  obj-$(CONFIG_CMD_MEMORY) += mem.o
diff --git a/cmd/lsblk.c b/cmd/lsblk.c
new file mode 100644
index 00..575a1c9277
--- /dev/null
+++ b/cmd/lsblk.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020
+ * Niel Fourie, DENX Software Engineering, lu...@denx.de.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#if CONFIG_IS_ENABLED(HAVE_BLOCK_DEVICE)


... so this #ifdef should not be necessary, right?

Thanks,
Stefan


+#if CONFIG_IS_ENABLED(BLK)
+static int do_lsblk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   struct driver *d = ll_entry_start(struct driver, driver);
+   const int n_ents = ll_entry_count(struct driver, driver);
+   struct driver *entry;
+   struct udevice *udev;
+   struct uclass *uc;
+   struct blk_desc *desc;
+   int i;
+
+   puts("Block Driver  Devices\n");
+   puts("-\n");
+   uclass_get(UCLASS_BLK, &uc);
+   for (entry = d; entry < d + n_ents; entry++) {
+   if (entry->id != UCLASS_BLK)
+   continue;
+   i = 0;
+   printf("%-20.20s", entry->name);
+   uclass_foreach_dev(udev, uc) {
+   if (udev->driver != entry)
+   continue;
+   desc = dev_get_uclass_platdata(udev);
+   printf("%c %s %u", i ? ',' : ':',
+  blk_get_if_type_name(desc->if_type),
+  desc->devnum);
+   i++;
+   }
+   if (!i)
+   puts(": ");
+   puts("\n");
+   }
+   return CMD_RET_SUCCESS;
+}
+#else
+static int do_lsblk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   struct blk_driver *drv = ll_entry_start(struct blk_driver, blk_driver);
+   const int n_ents = ll_entry_count(struct blk_driver, blk_driver);
+   struct blk_driver *entry;
+   struct blk_desc *desc;
+   int i, j;
+
+   puts("Block Driver  Devices\n");
+   puts("-\n");
+   for (entry = drv; entry != drv + n_ents; entry++) {
+   i = 0;
+   printf("%-20.20s", entry->if_typename);
+   for (j = 0; j < entry->max_devs; j++) {
+   desc = &entry->desc[j];
+   if (!entry->get_dev)
+   continue;
+   if (entry->get_dev(j, &desc))
+   continue;
+   if (desc->type == DEV_TYPE_UNKNOWN)
+   continue;
+   printf("%c %s %u", i ? ',' : ':', entry->if_typename,
+  desc->devnum);
+   i++;
+   }
+   if (!i)
+   puts(": ");
+   puts("\n");
+   }
+   return CMD_RET_SUCCESS;
+}
+#endif /* CONFIG_IS_ENABLED(BLK) */
+U_BOOT_CMD(lsblk, 1, 0, do_lsblk, "list block drivers and devices",
+  "- display list of block device drivers and attached block devices"
+);
+#endif /* CONFIG_IS_ENABLED(HAVE_BLOCK_DEVICE) */
diff --git a/test/py/tests/test_lsblk.py b/test/py/tests/test_lsblk.py
new file mode 100644
index 00..f4b36b581e
--- /dev/null
+++ b/test/py/tests/test_lsblk.py
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2020
+# Niel Fourie, DENX Software Engineering, lu...@denx.de
+
+import pyt

[PATCH 1/1] cmd: blkls: Add blkls command

[Niel Fourie]

Add a command to print a list of available block device drivers,
and for each, the list of known block devices.

Signed-off-by: Niel Fourie 
---
 cmd/Kconfig |  8 
 cmd/Makefile|  1 +
 cmd/lsblk.c | 83 +
 test/py/tests/test_lsblk.py | 23 ++
 4 files changed, 115 insertions(+)
 create mode 100644 cmd/lsblk.c
 create mode 100644 test/py/tests/test_lsblk.py

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 6403bc45a5..ee6ff467ae 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1047,6 +1047,14 @@ config CMD_LOADS
help
  Load an S-Record file over serial line
 
+config CMD_LSBLK
+   depends on HAVE_BLOCK_DEVICE
+   bool "lsblk - list block drivers and devices"
+   default n
+   help
+ Print list of available block device drivers, and for each, the list
+ of known block devices.
+
 config CMD_MMC
bool "mmc"
help
diff --git a/cmd/Makefile b/cmd/Makefile
index f1dd513a4b..6f80974a55 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -83,6 +83,7 @@ obj-$(CONFIG_CMD_LED) += led.o
 obj-$(CONFIG_CMD_LICENSE) += license.o
 obj-y += load.o
 obj-$(CONFIG_CMD_LOG) += log.o
+obj-$(CONFIG_CMD_LSBLK) += lsblk.o
 obj-$(CONFIG_ID_EEPROM) += mac.o
 obj-$(CONFIG_CMD_MD5SUM) += md5sum.o
 obj-$(CONFIG_CMD_MEMORY) += mem.o
diff --git a/cmd/lsblk.c b/cmd/lsblk.c
new file mode 100644
index 00..575a1c9277
--- /dev/null
+++ b/cmd/lsblk.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020
+ * Niel Fourie, DENX Software Engineering, lu...@denx.de.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#if CONFIG_IS_ENABLED(HAVE_BLOCK_DEVICE)
+#if CONFIG_IS_ENABLED(BLK)
+static int do_lsblk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   struct driver *d = ll_entry_start(struct driver, driver);
+   const int n_ents = ll_entry_count(struct driver, driver);
+   struct driver *entry;
+   struct udevice *udev;
+   struct uclass *uc;
+   struct blk_desc *desc;
+   int i;
+
+   puts("Block Driver  Devices\n");
+   puts("-\n");
+   uclass_get(UCLASS_BLK, &uc);
+   for (entry = d; entry < d + n_ents; entry++) {
+   if (entry->id != UCLASS_BLK)
+   continue;
+   i = 0;
+   printf("%-20.20s", entry->name);
+   uclass_foreach_dev(udev, uc) {
+   if (udev->driver != entry)
+   continue;
+   desc = dev_get_uclass_platdata(udev);
+   printf("%c %s %u", i ? ',' : ':',
+  blk_get_if_type_name(desc->if_type),
+  desc->devnum);
+   i++;
+   }
+   if (!i)
+   puts(": ");
+   puts("\n");
+   }
+   return CMD_RET_SUCCESS;
+}
+#else
+static int do_lsblk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   struct blk_driver *drv = ll_entry_start(struct blk_driver, blk_driver);
+   const int n_ents = ll_entry_count(struct blk_driver, blk_driver);
+   struct blk_driver *entry;
+   struct blk_desc *desc;
+   int i, j;
+
+   puts("Block Driver  Devices\n");
+   puts("-\n");
+   for (entry = drv; entry != drv + n_ents; entry++) {
+   i = 0;
+   printf("%-20.20s", entry->if_typename);
+   for (j = 0; j < entry->max_devs; j++) {
+   desc = &entry->desc[j];
+   if (!entry->get_dev)
+   continue;
+   if (entry->get_dev(j, &desc))
+   continue;
+   if (desc->type == DEV_TYPE_UNKNOWN)
+   continue;
+   printf("%c %s %u", i ? ',' : ':', entry->if_typename,
+  desc->devnum);
+   i++;
+   }
+   if (!i)
+   puts(": ");
+   puts("\n");
+   }
+   return CMD_RET_SUCCESS;
+}
+#endif /* CONFIG_IS_ENABLED(BLK) */
+U_BOOT_CMD(lsblk, 1, 0, do_lsblk, "list block drivers and devices",
+  "- display list of block device drivers and attached block devices"
+);
+#endif /* CONFIG_IS_ENABLED(HAVE_BLOCK_DEVICE) */
diff --git a/test/py/tests/test_lsblk.py b/test/py/tests/test_lsblk.py
new file mode 100644
index 00..f4b36b581e
--- /dev/null
+++ b/test/py/tests/test_lsblk.py
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2020
+# Niel Fourie, DENX Software Engineering, lu...@denx.de
+
+import pytest
+
+@pytest.mark.buildconfigspec('have_block_device')
+@pytest.mark.buildconfigspec('blk')
+@pytest.mark.buildconfigspec('cmd_lsblk')
+def test_lsblk(u_boot_console):
+"""Test that 

[RFC PATCH 1/1] Makefile: Expand legacy (non-DM) driver warnings

[Niel Fourie]

Expand warnings printed by Makefile after compile when legacy
drivers are in use. These include:

- CONFIG_HAVE_BLOCK_DEVICE without CONFIG_BLK
- CONFIG_BOOTCOUNT_LIMIT without CONFIG_DM_BOOTCOUNT
- CONFIG_MTD without CONFIG_DM_MTD
- CONFIG_PHYLIB without CONFIG_DM_MDIO
- CONFIG_POWER, also without CONFIG_DM_PMIC
- Absence of CONFIG_RAM and CONFIG_SPL_RAM

Also replaced existing CONFIG_DM_SPI warning for consistency.
Removed CONFIG_BLK requirement for CONFIG_DM_USB, as all USB
devices not block devices.

Signed-off-by: Niel Fourie 
Cc: Simon Glass 
---
 Makefile | 73 +++-
 1 file changed, 67 insertions(+), 6 deletions(-)

diff --git a/Makefile b/Makefile
index fa687f13a5..0df58ca7c1 100644
--- a/Makefile
+++ b/Makefile
@@ -963,11 +963,6 @@ cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
 all:   $(ALL-y)
 ifeq ($(CONFIG_DEPRECATED),y)
$(warning "You have deprecated configuration options enabled in your 
.config! Please check your configuration.")
-ifeq ($(CONFIG_SPI),y)
-ifneq ($(CONFIG_DM_SPI)$(CONFIG_OF_CONTROL),yy)
-   $(warning "The relevant config item with associated code will remove in 
v2019.07 release.")
-endif
-endif
 endif
 ifneq ($(CONFIG_DM),y)
@echo >&2 "= WARNING =="
@@ -988,7 +983,7 @@ ifneq 
($(CONFIG_DM_MMC)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy)
 endif
 endif
 ifeq ($(CONFIG_USB),y)
-ifneq ($(CONFIG_DM_USB)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy)
+ifneq ($(CONFIG_DM_USB)$(CONFIG_OF_CONTROL),yy)
@echo >&2 "= WARNING =="
@echo >&2 "This board does not use CONFIG_DM_USB. Please update"
@echo >&2 "the board to use CONFIG_DM_USB before the v2019.07 release."
@@ -1046,6 +1041,16 @@ ifeq ($(CONFIG_OF_EMBED),y)
@echo >&2 "See doc/README.fdt-control for more info."
@echo >&2 ""
 endif
+ifeq ($(CONFIG_SPI),y)
+ifneq ($(CONFIG_DM_SPI)$(CONFIG_OF_CONTROL),yy)
+   @echo >&2 "= WARNING =="
+   @echo >&2 "This board uses CONFIG_SPI without having CONFIG_DM_SPI"
+   @echo >&2 "enabled. Please update the board before the v2019.07 
release."
+   @echo >&2 "Failure to update by the deadline may result in board 
removal."
+   @echo >&2 "See doc/driver-model/migration.rst for more info."
+   @echo >&2 ""
+endif
+endif
 ifeq ($(CONFIG_SPI_FLASH),y)
 ifneq ($(CONFIG_DM_SPI_FLASH)$(CONFIG_OF_CONTROL),yy)
@echo >&2 "= WARNING =="
@@ -1078,6 +1083,62 @@ ifneq ($(CONFIG_DM_ETH),y)
@echo >&2 ""
 endif
 endif
+ifeq ($(CONFIG_HAVE_BLOCK_DEVICE),y)
+ifneq ($(CONFIG_BLK),y)
+   @echo >&2 "= WARNING =="
+   @echo >&2 "This board uses CONFIG_HAVE_BLOCK_DEVICE but does not"
+   @echo >&2 "have CONFIG_BLK enabled. This implies legacy block"
+   @echo >&2 "device support is enabled without driver model (DM)."
+   @echo >&2 ""
+endif
+endif
+ifeq ($(CONFIG_BOOTCOUNT_LIMIT),y)
+ifneq ($(CONFIG_DM_BOOTCOUNT),y)
+   @echo >&2 "= WARNING =="
+   @echo >&2 "This board uses CONFIG_BOOTCOUNT_LIMIT without"
+   @echo >&2 "having CONFIG_DM_BOOTCOUNT enabled. This implies a"
+   @echo >&2 "legacy bootcounter without driver model (DM) support."
+   @echo >&2 ""
+endif
+endif
+ifeq ($(CONFIG_MTD),y)
+ifneq ($(CONFIG_DM_MTD),y)
+   @echo >&2 "= WARNING =="
+   @echo >&2 "This board uses CONFIG_MTD without having CONFIG_DM_MTD"
+   @echo >&2 "enabled. This implies legacy MTD support, without"
+   @echo >&2 "driver model (DM)."
+   @echo >&2 ""
+endif
+endif
+ifeq ($(CONFIG_PHYLIB),y)
+ifneq ($(CONFIG_DM_MDIO),y)
+   @echo >&2 "= WARNING =="
+   @echo >&2 "This board uses CONFIG_PHYLIB, without having"
+   @echo >&2 "CONFIG_DM_MDIO enabled. This implies legacy ethernet"
+   @echo >&2 "phy support, without driver model (DM)."
+   @echo >&2 ""
+endif
+endif
+ifeq ($(CONFIG_POWER),y)
+   @echo >&2 "= WARNING =="
+   @echo >&2 "This board uses CONFIG_POWER which enables the legacy"
+   @echo >&2 "pre-DM PMIC support."
+ifneq ($(CONFIG_DM_PMIC),y)
+   @echo >&2 "CONFIG_DM_PMIC is disabled, therefore no driver model"
+   @echo >&2 "(DM) PMIC support is enabled."
+endif
+   @echo >&2 ""
+endif
+ifneq ($(CONFIG_RAM),y)
+ifne

[PATCH] net: ping: reset stored IP once the command finishes

[Marek Szyprowski]

Reset stored ping IP address before leaving the netloop to ensure that
the subsequent calls to the netloop, especially for the other protocols,
won't be interrupted by the received ICMP_ECHO_REPLY packet.

Signed-off-by: Marek Szyprowski 
---
 net/ping.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/net/ping.c b/net/ping.c
index 633c942..d912e3d 100644
--- a/net/ping.c
+++ b/net/ping.c
@@ -63,6 +63,7 @@ static int ping_send(void)
 static void ping_timeout_handler(void)
 {
eth_halt();
+   net_ping_ip.s_addr = 0;
net_set_state(NETLOOP_FAIL);/* we did not get the reply */
 }
 
@@ -84,8 +85,10 @@ void ping_receive(struct ethernet_hdr *et, struct ip_udp_hdr 
*ip, int len)
switch (icmph->type) {
case ICMP_ECHO_REPLY:
src_ip = net_read_ip((void *)&ip->ip_src);
-   if (src_ip.s_addr == net_ping_ip.s_addr)
+   if (src_ip.s_addr == net_ping_ip.s_addr) {
+   net_ping_ip.s_addr = 0;
net_set_state(NETLOOP_SUCCESS);
+   }
return;
case ICMP_ECHO_REQUEST:
eth_hdr_size = net_update_ether(et, et->et_src, PROT_IP);
-- 
1.9.1

Re: [PATCH v1] x86: acpi: Add I²C timings to Intel Merrifield platform

[Bin Meng]

Hi Andy,

On Wed, Mar 25, 2020 at 7:41 PM Andy Shevchenko
 wrote:
>
> On Wed, Mar 25, 2020 at 9:15 AM Bin Meng  wrote:
> >
> > On Sat, Mar 21, 2020 at 1:46 AM Andy Shevchenko
> >  wrote:
> > >
> > > There is established way to provide I²C timings, or actually counters,
> > > to the OS via ACPI. Fill them for Intel Merrifield platform.
> > >
> > > Signed-off-by: Andy Shevchenko 
> > > ---
> > >  .../asm/arch-tangier/acpi/southcluster.asl| 20 +++
> > >  1 file changed, 20 insertions(+)
> > >
> >
> > applied to u-boot-x86, thanks!
>
> There is a v2 of it. Should I send a fix up or you can replace?

Sorry I replied the wrong email. I did apply the v2 patch, and
manually added Simon's RB tag.

Regards,
Bin

Re: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

[Peter Robinson]

Hi Tom,

Do you have this and the other patches you've posted on a git branch
somewhere, for some reason they're not showing up in patchwork [1]
which makes it less straight forward to test.

Peter

[1] http://patchwork.ozlabs.org/project/uboot/list/?q=tegra

On Tue, Mar 24, 2020 at 7:03 PM  wrote:
>
> From: Tom Warren 
>
> The Jetson Nano Developer Kit is a Tegra X1-based development board. It
> is similar to Jetson TX1 but it is not pin compatible. It features 4GB
> of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot
> used for storage.
>
> HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
> and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
> Ethernet controller provides onboard network connectivity. NVMe support
> has also been added. Env save is at the end of QSPI (4MB-8K).
>
> A 40-pin header on the board can be used to extend the capabilities and
> exposed interfaces of the Jetson Nano.
>
> Signed-off-by: Thierry Reding 
> Signed-off-by: Tom Warren 
> ---
>  arch/arm/dts/Makefile|   3 +-
>  arch/arm/dts/tegra210-p3450-.dts | 147 +
>  arch/arm/mach-tegra/board2.c |  25 +
>  arch/arm/mach-tegra/tegra210/Kconfig |   7 ++
>  board/nvidia/p3450-/Kconfig  |  12 +++
>  board/nvidia/p3450-/MAINTAINERS  |   6 ++
>  board/nvidia/p3450-/Makefile |   8 ++
>  board/nvidia/p3450-/p3450-.c | 178 
> +++
>  configs/p3450-_defconfig |  64 +
>  include/configs/p3450-.h |  46 +
>  10 files changed, 495 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/tegra210-p3450-.dts
>  create mode 100644 board/nvidia/p3450-/Kconfig
>  create mode 100644 board/nvidia/p3450-/MAINTAINERS
>  create mode 100644 board/nvidia/p3450-/Makefile
>  create mode 100644 board/nvidia/p3450-/p3450-.c
>  create mode 100644 configs/p3450-_defconfig
>  create mode 100644 include/configs/p3450-.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 9c593b2..820ee97 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -180,7 +180,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
> tegra210-e2220-1170.dtb \
> tegra210-p2371-.dtb \
> tegra210-p2371-2180.dtb \
> -   tegra210-p2571.dtb
> +   tegra210-p2571.dtb \
> +   tegra210-p3450-.dtb
>
>  dtb-$(CONFIG_ARCH_MVEBU) +=\
> armada-3720-db.dtb  \
> diff --git a/arch/arm/dts/tegra210-p3450-.dts 
> b/arch/arm/dts/tegra210-p3450-.dts
> new file mode 100644
> index 000..9ef744a
> --- /dev/null
> +++ b/arch/arm/dts/tegra210-p3450-.dts
> @@ -0,0 +1,147 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + *  (C) Copyright 2019-2020 NVIDIA Corporation 
> + */
> +/dts-v1/;
> +
> +#include "tegra210.dtsi"
> +
> +/ {
> +   model = "NVIDIA Jetson Nano Developer Kit";
> +   compatible = "nvidia,p3450-", "nvidia,tegra210";
> +
> +   chosen {
> +   stdout-path = &uarta;
> +   };
> +
> +   aliases {
> +   ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
> +   i2c0 = "/i2c@7000d000";
> +   i2c2 = "/i2c@7000c400";
> +   i2c3 = "/i2c@7000c500";
> +   i2c4 = "/i2c@7000c700";
> +   mmc0 = "/sdhci@700b0600";
> +   mmc1 = "/sdhci@700b";
> +   spi0 = "/spi@7041";
> +   usb0 = "/usb@7d00";
> +   };
> +
> +   memory {
> +   reg = <0x0 0x8000 0x0 0xc000>;
> +   };
> +
> +   pcie@1003000 {
> +   status = "okay";
> +
> +   pci@1,0 {
> +   status = "okay";
> +   };
> +
> +   pci@2,0 {
> +   status = "okay";
> +
> +   ethernet@0,0 {
> +   reg = <0x00 0 0 0 0>;
> +   local-mac-address = [ 00 00 00 00 00 00 ];
> +   };
> +   };
> +   };
> +
> +   serial@70006000 {
> +   status = "okay";
> +   };
> +
> +   padctl@7009f000 {
> +   pinctrl-0 = <&padctl_default>;
> +   pinctrl-names = "default";
> +
> +   padctl_default: pinmux {
> +   xusb {
> +   nvidia,lanes = "otg-1", "otg-2";
> +   nvidia,function = "xusb";
> +   nvidia,iddq = <0>;
> +   };
> +
> +   usb3 {
> +   nvidia,lanes = "pcie-5", "pcie-6";
> +   nvidia,function = "usb3";
> +   nvidia,iddq = <0>;
> +   };
> +
> +   pcie-x1 {
> +   nvid

Re: [PATCH v1] x86: acpi: Add I²C timings to Intel Merrifield platform

[Andy Shevchenko]

On Wed, Mar 25, 2020 at 9:15 AM Bin Meng  wrote:
>
> On Sat, Mar 21, 2020 at 1:46 AM Andy Shevchenko
>  wrote:
> >
> > There is established way to provide I²C timings, or actually counters,
> > to the OS via ACPI. Fill them for Intel Merrifield platform.
> >
> > Signed-off-by: Andy Shevchenko 
> > ---
> >  .../asm/arch-tangier/acpi/southcluster.asl| 20 +++
> >  1 file changed, 20 insertions(+)
> >
>
> applied to u-boot-x86, thanks!

There is a v2 of it. Should I send a fix up or you can replace?

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 0/5] CMD_SAVEENV ifdef cleanup

[Rasmus Villemoes]

On 25/03/2020 08.50, Wolfgang Denk wrote:
> Dear Rasmus Villemoes,
> 
> In message <9c03710e-5eec-da6e-6c15-2f8a14cfc...@prevas.dk> you wrote:
>>
>> Can I ask whether you request changes to this patch series or if my
>> answers to your various comments have been satisfactory?
> 
> I think you did no really answer to some of my concerns.
> 
> In Message <20200219132715.1f81a240...@gemini.denx.de> I asked:
> 
> | Have you tested that this works?  How do the sizes of the
> | images differe before and after applying your changes?
> 
> You replied:
> 
> ...
> Now also enable CONFIG_SPL_SAVEENV and SPL_FAT_WRITE, then with my
> patches we get
> 
> | $ size u-boot spl/u-boot-spl
> |textdata bss dec hex filename
> |  407173   45308   98352  550833   867b1 u-boot
> |   582983360   65860  127518   1f21e spl/u-boot-spl
> | 
> | but without,
> | 
> | $ size u-boot spl/u-boot-spl
> |textdata bss dec hex filename
> |  407173   45308   98352  550833   867b1 u-boot
> |   526593360 280   56299dbeb spl/u-boot-spl
> 
> We can observe that
> 
> - the text size of the SPL grows from 52659 to 58298, i. e. by about
>   5.5 kB or more than 10%
> - the BSS size explodes from 280 to 65860 bytes, i. e. it grows from
>   a few hndet bytes to more than 64 kB
> 
> I can see where the increase in text size is coming from - your
> removal of #ifdef's now unconditionally includes some code that was
> omitted before, for example functions env_fat_save(),
> env_ext4_save(), env_sf_save(), plus a few variables.

As intended for CONFIG_SPL_SAVEENV=y, no?

With my patches and CONFIG_SPL_SAVEENV=n, those env_fat_save,
env_ext4_save etc. are compiled, but then discarded (being static, they
are discarded already at compile-time, but otherwise they would be at
link-time), instead of being ifdeffed out unconditionally just because
of CONFIG_SPL_BUILD. I know that you share the opinion that one should
use IS_ENABLED() in preference to preprocessor conditionals, so I really
don't understand what you can possibly have against this approach.

> It is not obvious to me but scary to see such an explosion of BSS
> size.

> It's difficult to comment here as it is not clear to me which exact
> configuration you reported about,

Huh? I wrote exactly what I used to obtain those numbers for the FAT
case. Let me quote a bit more


With or without these patches, I get

$ size u-boot spl/u-boot-spl
   textdata bss dec hex filename
 407173   45308   98352  550833   867b1 u-boot
  524033360 276   56039dae7 spl/u-boot-spl
$ nm spl/u-boot-spl | grep env_fat
0090c5e8 t env_fat_load
$ nm u-boot | grep env_fat
17826cb4 t env_fat_load
17826c10 t env_fat_save

for a wandboard_defconfig modified by

-CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_ENV_IS_IN_FAT=y

So in the "read-only environment access in SPL" case, everything is the
same before and after.


That was the answer to "does it affect the generated code when one
doesn't enable CONFIG_SPL_SAVEENV". It doesn't, not at all, the code is
exactly the same. The next part then demonstrated how CONFIG_SPL_SAVEENV
is currently being ignored because of the ifdeffery in fat.c:


Now also enable CONFIG_SPL_SAVEENV and SPL_FAT_WRITE, then with my
patches we get

$ size u-boot spl/u-boot-spl
   textdata bss dec hex filename
 407173   45308   98352  550833   867b1 u-boot
  582983360   65860  127518   1f21e spl/u-boot-spl
$ nm spl/u-boot-spl | grep env_fat
0090c6e0 t env_fat_load
0090c63c t env_fat_save

but without,

$ size u-boot spl/u-boot-spl
   textdata bss dec hex filename
 407173   45308   98352  550833   867b1 u-boot
  526593360 280   56299dbeb spl/u-boot-spl
$ nm spl/u-boot-spl | grep env_fat
0090c5e8 t env_fat_load

So without the fat.c patch, CONFIG_SPL_SAVEENV is effectively ignored.


The .bss increase is simply due to the extra code that no longer gets
discarded by the linker, more precisely the .map file says there's a

 .bss.tmpbuf_cluster
0x0x1 fs/built-in.o

that gets discarded without my patches (but with the config options
chosen so one would _expect_ to have save support in SPL). So yes, of
course there's a price to pay for enabling environment save support in
the SPL, with some backends being more expensive (in terms of footprint)
than others.

> and it's also not clear if this is
> a typical result, of if it's the only configuration you ever
> tested.
> 
> 
> Your patch description sounds as if it was just a #ifdef cleanup
> without actual impact on the generated code, but the SPL size
> differences above make it clear that it is not - or that your
> testing has issues.

There is _no_ change in code size, u-boot or spl, when
CONFIG_SPL_SAVEENV=n. My patches _only_ affect the case where
CONFIG_SPL_SAVEENV=y, and only in a way that the developer most likely
intended, namely actually allowin

Re: [PATCH 2/2] uboot: fs/btrfs: Fix LZO false decompression error caused by pending zero

[Qu Wenruo]

On 2020/3/25 下午7:00, Marek Behun wrote:
> On Wed, 25 Mar 2020 16:27:16 +0800
> Qu Wenruo  wrote:
> 
>> On 2020/3/25 下午4:09, Marek Behun wrote:
>>> On Thu, 19 Mar 2020 20:33:19 +0800
>>> Qu Wenruo  wrote:
>>>   
 [BUG]  
>>>
>>> The subject line should not contain uboot keyword. If you check git log
>>> for fs/btrfs, the commits always start with:
>>>   fs: btrfs:
>>>
>>> Also please don't use [BUG] [CAUSE] and [FIX] in commit messages.  
>>
>> Why? I think such section makes the analyse much easier to read.
> 
> Hi Qu,
> 
> I think your commit message without the tags is well-readable, but maybe
> this is just my personal view. On the other hand such tagging is not
> customary for U-Boot commit messages nor for Linux.

Got it, would try to control my eager to use such sections at least for
U-boot code.

> 
>>>
>>> You could have also added myself to CC, since I am the original author
>>> of U-Boots btrfs implementation. I just stumbled on your patches by
>>> chance.  
>>
>> Since there is no maintainer name in MAINTAINERS file, there is no way
>> other guys would know who to CC.
> 
> You have a fair point, sorry about that.
> 
>>
>>>
>>> Also do not add linux-btrfs mailing list for u-boot patches.  
>>
>> I don't see any reason why we can't include the mail list for more
>> experts to review.
> 
> See below.
> 
>>>   
 For certain btrfs files with compressed file extent, uboot will fail to
 load it:

   btrfs_read_extent_reg: disk_bytenr=14229504 disk_len=73728 offset=0 
 nr_bytes=131
   072
   decompress_lzo: tot_len=70770
   decompress_lzo: in_len=1389
   decompress_lzo: in_len=2400
   decompress_lzo: in_len=3002
   decompress_lzo: in_len=1379
   decompress_lzo: in_len=88539136
   decompress_lzo: header error, in_len=88539136 clen=65534 tot_len=62580

 NOTE: except the last line, all other lines are debug output.

 [CAUSE]
 Btrfs lzo compression uses its own format to record compressed size
 (segmant header, LE32).

 However to make decompression easier, we never put such segment header
 across page boundary.

 In above case, the xxd dump of the lzo compressed data looks like this:

 1fe0: 4cdc 02fc 0bfd 02c0 dc02 0d13 0100 0001  L...
 1ff0:  0008 0300   0011 |  
 2000: 4705  0001 cc02    1e01  G...

 '|' is the "expected" segment header start position.

 But in that page, there are only 2 bytes left, can't contain the 4 bytes
 segment header.

 So btrfs compression will skip that 2 bytes, put the segment header in
 next page directly.

 Uboot doesn't have such check, and read the header with 2 bytes offset,
 result 0x0547 (88539136), other than the expected result
 0x0547 (1351), resulting above error.

 [FIX]
 Follow the btrfs-progs restore implementation, by introducing tot_in to
 record total processed bytes (including headers), and do proper page
 boundary skip to fix it.

 Signed-off-by: Qu Wenruo 
 ---
  fs/btrfs/compression.c | 20 
  1 file changed, 20 insertions(+)

 diff --git a/fs/btrfs/compression.c b/fs/btrfs/compression.c
 index 4ef44ce11485..2a6ac8bb1029 100644
 --- a/fs/btrfs/compression.c
 +++ b/fs/btrfs/compression.c
 @@ -9,6 +9,7 @@
  #include 
  #include 
  #include 
 +#include 
  #include 
  #include 
  
 @@ -17,6 +18,7 @@
  static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen)
  {
u32 tot_len, in_len, res;
 +  u32 tot_in = 0;  
>>>
>>> This function does not define local variable values in declaration,
>>> please don't mix this. Also tot_in is of the same type as the variables
>>> above, so use
>>>   u32 tot_len, tot_in, in_len, res;  
>>
>> Please give us the proper code style doc, I understand that each project
>> or even each subsystem has its own style, but without proper doc it will
>> be a mess to maintain.
>>
>> So, please show the proper code style for us to follow.
> 
> When patches are being sent for example to netdev, sometimes netdev
> maintainer or reviewers nitpick about coding style and ask the author
> to fix this. Not all of these coding style requests are
> documented nor does the checkpatch script checks for all of them.
> Sometimes the only way for to get to know the coding style is by
> reading the code, and sometimes even that does not suffice. Either way
> these are reasonable requests and the authors fix the patches.
> I know that I always did it, for example when I sent patches for the
> mv88e6xxx linux driver, and Vivien or David asked me to fix such things.
> 
> I understand that people may find this exaggeration, but we know what
> happens when nobody cares about such things: look at U-Boot's ext4
> driver.

Fine.

Although it may be tricky that i

Re: [PATCH 2/2] uboot: fs/btrfs: Fix LZO false decompression error caused by pending zero

[Marek Behun]

On Wed, 25 Mar 2020 12:00:20 +0100
Marek Behun  wrote:

> I also did not collaborate with Linux btrfs authors when writing this
> driver. These are the reasons why I don't see much point in adding
> linux-btrfs mailing list to Cc, since they may have never seen the
> codebase.

On the other hand it can't hurt for Linux btrfs authors to have
a look at U-Boot's implementation, so I am withdrawing my objection. :)
Sorry.