[PATCH v2 6/6] rockchip: rk3328: Add support for ROC-RK3328-CC board
From: Chen-Yu Tsai
The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit
card size development board based on the Rockchip RK3328 SoC, with:
- 1/2/4 GB DDR4 DRAM
- eMMC connector for optional module
- micro SD card slot
- 1 x USB 3.0 host port
- 2 x USB 2.0 host port
- 1 x USB 2.0 OTG port
- HDMI video output
- TRRS connector with audio and composite video output
- gigabit Ethernet
- consumer IR receiver
- debug UART pins
The ROC-RK3328-CC has the enable pin of the SD card power switch tied
to GPIO_0_D6. This pin also has the function SDMMC0_PWREN, which is
muxed by default. SDMMC0_PWREN is an active high signal controlled by
the MMC controller, however the switch enable is active low, and
pulled low (enabled) by default to make things work on boot.
As such, we need to mux away from SDMMC0_PWREN and use GPIO to enable
power to the card. The default GPIO state for the pin is pull-down and
input, which doesn't require extra configuration when paired with the
external pull-down and active low switch.
Deal with this by enabling regulator support in SPL, and setting
"u-boot,dm-spl" for the regulator and other device nodes needed for
muxing the pin.
The device tree file is synced from the Linux kernel next-20200324.
Signed-off-by: Chen-Yu Tsai
---
Changes since v1:
- Drop custom target; use pinctrl and regulators in SPL
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 38 +++
arch/arm/dts/rk3328-roc-cc.dts | 354 +
board/rockchip/evb_rk3328/MAINTAINERS | 7 +
configs/roc-cc-rk3328_defconfig| 103 +++
doc/README.rockchip| 4 +-
6 files changed, 506 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3328-roc-cc.dts
create mode 100644 configs/roc-cc-rk3328_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9c593b2c986a..023cb010532d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -104,6 +104,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
+ rk3328-roc-cc.dtb \
rk3328-rock64.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
new file mode 100644
index ..c268fbb9b5b6
--- /dev/null
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr4-666.dtsi"
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_gpio {
+ u-boot,dm-spl;
+};
+
+_pull_up_4ma {
+ u-boot,dm-spl;
+};
+
+_host0_xhci {
+ vbus-supply = <_host1_5v>;
+ status = "okay";
+};
+
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
+_sd {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts
new file mode 100644
index ..8d553c92182a
--- /dev/null
+++ b/arch/arm/dts/rk3328-roc-cc.dts
@@ -0,0 +1,354 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+ model = "Firefly roc-rk3328-cc";
+ compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = < RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_gpio>;
+ regulator-boot-on;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_io>;
+ };
+
+ vcc_sdio: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <_gpio 0 GPIO_ACTIVE_HIGH>;
+ states = <180 0x1
+ 330 0x0>;
+ regulator-name = "vcc_sdio";
+ regulator-type = "voltage";
+
[PATCH v2 2/6] rockchip: dts: rk3328-evb: Move gmac2io related nodes to -u-boot.dtsi
From: Chen-Yu Tsai
The device tree file for rk3328-evb in the Linux kernel does not have
gmac2io enabled. Instead, gmac2phy is enabled, but that is not supported
in U-boot.
Move the gmac2io related nodes to rk3328-evb-u-boot.dtsi to preserve the
current functionality. When the device tree files are synced, gmac2phy
should be marked as "broken" in -u-boot.dtsi files.
Reviewed-by: Kever Yang
Signed-off-by: Chen-Yu Tsai
---
Changes since v1:
- Added Kever's reviewed-by
---
arch/arm/dts/rk3328-evb-u-boot.dtsi | 23 +++
arch/arm/dts/rk3328-evb.dts | 23 ---
2 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi
b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 5679897279aa..8ba53cf8f44b 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -7,6 +7,13 @@
#include "rk3328-sdram-ddr3-666.dtsi"
/{
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
compatible = "regulator-fixed";
enable-active-high;
@@ -17,6 +24,22 @@
};
};
+ {
+ phy-supply = <_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = < RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+ assigned-clocks = < SCLK_MAC2IO>, < SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <_clkin>, <_clkin>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ tx_delay = <0x26>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
_host0_xhci {
vbus-supply = <_host_xhci>;
status = "okay";
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index e9bc849f8c23..97bef37cf610 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -14,13 +14,6 @@
stdout-path =
};
- gmac_clkin: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <12500>;
- clock-output-names = "gmac_clkin";
- #clock-cells = <0>;
- };
-
vcc3v3_sdmmc: sdmmc-pwren {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
@@ -78,22 +71,6 @@
status = "okay";
};
- {
- phy-supply = <_phy>;
- phy-mode = "rgmii";
- clock_in_out = "input";
- snps,reset-gpio = < RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 1 5>;
- assigned-clocks = < SCLK_MAC2IO>, < SCLK_MAC2IO_EXT>;
- assigned-clock-parents = <_clkin>, <_clkin>;
- pinctrl-names = "default";
- pinctrl-0 = <_pins>;
- tx_delay = <0x26>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
_host0_ehci {
status = "okay";
};
--
2.26.0
[PATCH v2 0/6] rockchip: rk3328: sync dts and add ROC-RK3328-CC board
From: Chen-Yu Tsai
Hi everyone,
This is v2 of my ROC-RK3328-CC series. Changes from v1 are mainly
dropping the custom board target, and dealing with the pinmuxing
through proper use of DM regulators / GPIO / pinctrl in SPL.
This series adds proper support for Firefly / Libre Computer ROC-RK3328-CC
single board computer.
The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit
card size development board based on the Rockchip RK3328 SoC, with:
- 1/2/4 GB DDR4 DRAM
- eMMC connector for optional module
- micro SD card slot
- 1 x USB 3.0 host port
- 2 x USB 2.0 host port
- 1 x USB 2.0 OTG port
- HDMI video output
- TRRS connector with audio and composite video output
- gigabit Ethernet
- consumer IR receiver
- debug UART pins
Originally I started with Loic's patches, and syncing the device tree
files from Linux. That didn't get very far, with SPL failing to detect
the SD card. Examining the schematics and internal state of GRF and
GPIOs, I realized that the logic for the SD card power enable switch
is opposite that of what the SD card controller's SDMMC0_PWREN pin
would use. Instead, directly using the GPIO is required.
To deal with this, DM regulator and GPIO are enabled in SPL, and
various device nodes are marked with u-boot,dm-spl to have them work.
pinctrl properties are not stripped, so as to have the SDMMC0_PWREN
pin muxed over to GPIO.
Along the way, there are some clean-ups of existing dts files, moving
U-boot only features to -u-boot.dtsi files, and then a wholesale sync
from Linux. Only boards already existing in U-boot are synced. DT
binding header files are synced separately as there is already one
patch floating around. The DT sync also includes clean-up changes only
recently posted, and likely won't make it in for at least a few weeks.
Please have a look, and test if possible. I cc-ed a couple people that
showed interest in this board on mailing lists recently.
Regards
ChenYu
Chen-Yu Tsai (6):
rockchip: dts: rk3328-evb: Move vcc5v0-host-xhci-drv to -u-boot.dtsi
rockchip: dts: rk3328-evb: Move gmac2io related nodes to -u-boot.dtsi
dt-bindings: clock: rk3328: sync from upstream Linux kernel
dt-bindings: power: rk3328-power: sync from upstream Linux kernel
rockchip: dts: rk3328: Sync device tree files from Linux
rockchip: rk3328: Add support for ROC-RK3328-CC board
arch/arm/dts/Makefile |1 +
arch/arm/dts/rk3328-evb-u-boot.dtsi | 39 +
arch/arm/dts/rk3328-evb.dts | 220 +--
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi| 38 +
.../{rk3328-rock64.dts => rk3328-roc-cc.dts} | 135 +-
arch/arm/dts/rk3328-rock64.dts| 132 +-
arch/arm/dts/rk3328.dtsi | 1420 +++--
board/rockchip/evb_rk3328/MAINTAINERS |7 +
configs/roc-cc-rk3328_defconfig | 103 ++
doc/README.rockchip |4 +-
include/dt-bindings/clock/rk3328-cru.h| 212 +--
include/dt-bindings/power/rk3328-power.h | 19 +
12 files changed, 1578 insertions(+), 752 deletions(-)
create mode 100644 arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
copy arch/arm/dts/{rk3328-rock64.dts => rk3328-roc-cc.dts} (68%)
create mode 100644 configs/roc-cc-rk3328_defconfig
create mode 100644 include/dt-bindings/power/rk3328-power.h
--
2.26.0
[PATCH v2 1/6] rockchip: dts: rk3328-evb: Move vcc5v0-host-xhci-drv to -u-boot.dtsi
From: Chen-Yu Tsai
USB 3.0 is only supported in U-boot, not in the Linux kernel where the
device tree files are ultimately synced from. While the xhci node was
moved, the external vbus regulator was not.
Move it as well.
Fixes: 2e91e2025c1b ("rockchip: rk3328: migrate u-boot node to -u-boot.dtsi")
Reviewed-by: Kever Yang
Signed-off-by: Chen-Yu Tsai
---
Changes since v1:
- Added Kever's reviewed-by
---
arch/arm/dts/rk3328-evb-u-boot.dtsi | 11 +++
arch/arm/dts/rk3328-evb.dts | 9 -
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi
b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 4a827063c555..5679897279aa 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -6,6 +6,17 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr3-666.dtsi"
+/{
+ vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < 0 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc5v0_host_xhci";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+};
+
_host0_xhci {
vbus-supply = <_host_xhci>;
status = "okay";
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index a2ee838fcd6b..e9bc849f8c23 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -38,15 +38,6 @@
regulator-max-microvolt = <500>;
};
- vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
- compatible = "regulator-fixed";
- enable-active-high;
- regulator-name = "vcc5v0_host_xhci";
- gpio = < 0 GPIO_ACTIVE_HIGH>;
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- };
-
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
--
2.26.0
[PATCH v2 5/6] rockchip: dts: rk3328: Sync device tree files from Linux
From: Chen-Yu Tsai
This syncs rk3328 device tree files from the Linux kernel next-20200324.
The last commit to touch these files is:
b2411befed60 ("arm64: dts: add bus to rockchip amba nodenames")
Additional changes not yet in the Linux kernel include:
arm64: dts: rockchip: rk3328: drop #address-cells, #size-cells from grf node
arm64: dts: rockchip: rk3328: drop non-existent gmac2phy pinmux options
arm64: dts: rockchip: rk3328: Replace RK805 PMIC node name with "pmic"
Changes include:
- conversion of raw pin numbers to macros
- removal of deprecated RK_FUNC_* macros
- update of device tree binding headers
- new devices
- device tree cleanups
- gmac2phy disabled in -u-boot.dtsi as it is not supported in U-boot
Reviewed-by: Kever Yang
Signed-off-by: Chen-Yu Tsai
---
Changes since v1:
- Added Kever's reviewed-by
---
arch/arm/dts/rk3328-evb-u-boot.dtsi |5 +
arch/arm/dts/rk3328-evb.dts | 196 ++--
arch/arm/dts/rk3328-rock64.dts | 132 ++-
arch/arm/dts/rk3328.dtsi| 1420 +--
4 files changed, 1164 insertions(+), 589 deletions(-)
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi
b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 8ba53cf8f44b..4bfa0c2330ba 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -40,6 +40,11 @@
status = "okay";
};
+ {
+ /* Integrated PHY unsupported by U-boot */
+ status = "broken";
+};
+
_host0_xhci {
vbus-supply = <_host_xhci>;
status = "okay";
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 97bef37cf610..6abc6f4a86cf 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
@@ -11,24 +11,51 @@
compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
chosen {
- stdout-path =
+ stdout-path = "serial2:150n8";
};
- vcc3v3_sdmmc: sdmmc-pwren {
+ dc_12v: dc-12v {
compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- gpio = < 30 GPIO_ACTIVE_LOW>;
+ regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <_enable_h>;
+
+ /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+* - SDIO_RESET_L_WL_REG_ON
+* - PDN (power down when low)
+*/
+ reset-gpios = < 18 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = < 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_io>;
};
- vcc5v0_otg: vcc5v0-otg-drv {
+ vcc_sys: vcc-sys {
compatible = "regulator-fixed";
- enable-active-high;
- regulator-name = "vcc5v0_otg";
- gpio = < 27 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
+ vin-supply = <_12v>;
};
vcc_phy: vcc-phy-regulator {
@@ -39,80 +66,60 @@
};
};
- {
- status = "okay";
-};
-
- {
- status = "okay";
-};
-
- {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- disable-wp;
- num-slots = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <_clk>, <_cmd>, <_dectn>,
<_bus4>;
- status = "okay";
+ {
+ cpu-supply = <_arm>;
};
{
bus-width = <8>;
cap-mmc-highspeed;
- supports-emmc;
- disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <_clk _cmd _bus8>;
status = "okay";
};
-_host0_ehci {
- status = "okay";
-};
+ {
+ phy-supply = <_phy>;
+ clock_in_out = "output";
+ assigned-clocks = < SCLK_MAC2PHY_SRC>;
+ assigned-clock-rate = <5000>;
+ assigned-clocks = < SCLK_MAC2PHY>;
+
[PATCH v2 3/6] dt-bindings: clock: rk3328: sync from upstream Linux kernel
From: Chen-Yu Tsai
This syncs the rk3328 clock header file from Linux kernel next-20200324,
to support newer hardware blocks when syncing the device tree files.
The last non-merge commit to touch it was
0dc14b013f79 ("clk: rockchip: add clock id for watchdog pclk on rk3328")
Reviewed-by: Kever Yang
Signed-off-by: Chen-Yu Tsai
---
Changes since v1:
- Added Kever's reviewed-by
---
include/dt-bindings/clock/rk3328-cru.h | 212 -
1 file changed, 106 insertions(+), 106 deletions(-)
diff --git a/include/dt-bindings/clock/rk3328-cru.h
b/include/dt-bindings/clock/rk3328-cru.h
index cde61ed8830b..555b4ff660ae 100644
--- a/include/dt-bindings/clock/rk3328-cru.h
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -1,6 +1,7 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Elaine
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
@@ -90,119 +91,118 @@
#define SCLK_MAC2IO_EXT102
/* dclk gates */
-#define DCLK_LCDC 180
-#define DCLK_HDMIPHY 181
-#define HDMIPHY182
-#define USB480M183
-#define DCLK_LCDC_SRC 184
+#define DCLK_LCDC 120
+#define DCLK_HDMIPHY 121
+#define HDMIPHY122
+#define USB480M123
+#define DCLK_LCDC_SRC 124
/* aclk gates */
-#define ACLK_AXISRAM 190
-#define ACLK_VOP_PRE 191
-#define ACLK_USB3OTG 192
-#define ACLK_RGA_PRE 193
-#define ACLK_DMAC 194
-#define ACLK_GPU 195
-#define ACLK_BUS_PRE 196
-#define ACLK_PERI_PRE 197
-#define ACLK_RKVDEC_PRE198
-#define ACLK_RKVDEC199
-#define ACLK_RKVENC200
-#define ACLK_VPU_PRE 201
-#define ACLK_VIO_PRE 202
-#define ACLK_VPU 203
-#define ACLK_VIO 204
-#define ACLK_VOP 205
-#define ACLK_GMAC 206
-#define ACLK_H265 207
-#define ACLK_H264 208
-#define ACLK_MAC2PHY 209
-#define ACLK_MAC2IO210
-#define ACLK_DCF 211
-#define ACLK_TSP 212
-#define ACLK_PERI 213
-#define ACLK_RGA 214
-#define ACLK_IEP 215
-#define ACLK_CIF 216
-#define ACLK_HDCP 217
+#define ACLK_AXISRAM 130
+#define ACLK_VOP_PRE 131
+#define ACLK_USB3OTG 132
+#define ACLK_RGA_PRE 133
+#define ACLK_DMAC 134
+#define ACLK_GPU 135
+#define ACLK_BUS_PRE 136
+#define ACLK_PERI_PRE 137
+#define ACLK_RKVDEC_PRE138
+#define ACLK_RKVDEC139
+#define ACLK_RKVENC140
+#define ACLK_VPU_PRE 141
+#define ACLK_VIO_PRE 142
+#define ACLK_VPU 143
+#define ACLK_VIO 144
+#define ACLK_VOP 145
+#define ACLK_GMAC 146
+#define ACLK_H265 147
+#define ACLK_H264 148
+#define ACLK_MAC2PHY 149
+#define ACLK_MAC2IO150
+#define ACLK_DCF 151
+#define ACLK_TSP 152
+#define ACLK_PERI 153
+#define ACLK_RGA 154
+#define ACLK_IEP 155
+#define ACLK_CIF 156
+#define ACLK_HDCP 157
/* pclk gates */
-#define PCLK_GPIO0 300
-#define PCLK_GPIO1 301
-#define PCLK_GPIO2 302
-#define PCLK_GPIO3 303
-#define PCLK_GRF 304
-#define PCLK_I2C0 305
-#define PCLK_I2C1 306
-#define PCLK_I2C2 307
-#define PCLK_I2C3 308
-#define PCLK_SPI 309
-#define PCLK_UART0 310
-#define PCLK_UART1 311
-#define PCLK_UART2 312
-#define PCLK_TSADC 313
-#define PCLK_PWM 314
-#define PCLK_TIMER 315
-#define PCLK_BUS_PRE 316
-#define PCLK_PERI_PRE 317
-#define PCLK_HDMI_CTRL 318
-#define PCLK_HDMI_PHY 319
-#define PCLK_GMAC 320
-#define PCLK_H265 321
-#define PCLK_MAC2PHY 322
-#define PCLK_MAC2IO323
-#define PCLK_USB3PHY_OTG 324
-#define PCLK_USB3PHY_PIPE 325
-#define PCLK_USB3_GRF 326
-#define PCLK_USB2_GRF 327
-#define PCLK_HDMIPHY 328
-#define PCLK_DDR 329
-#define PCLK_PERI 330
-#define PCLK_HDMI 331
-#define PCLK_HDCP 332
-#define PCLK_DCF 333
-#define PCLK_SARADC334
+#define PCLK_GPIO0 200
+#define PCLK_GPIO1 201
+#define PCLK_GPIO2 202
+#define PCLK_GPIO3 203
+#define
[PATCH v2 4/6] dt-bindings: power: rk3328-power: sync from upstream Linux kernel
From: Chen-Yu Tsai
This syncs the rk3328 power domain header file from Linux kernel
next-20200324, to support newer hardware blocks when syncing the
device tree files.
The last non-merge commit to touch it was
b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
files with no license")
Reviewed-by: Kever Yang
Signed-off-by: Chen-Yu Tsai
---
Changes since v1:
- Added Kever's reviewed-by
---
include/dt-bindings/power/rk3328-power.h | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 include/dt-bindings/power/rk3328-power.h
diff --git a/include/dt-bindings/power/rk3328-power.h
b/include/dt-bindings/power/rk3328-power.h
new file mode 100644
index ..02e3d7fc1cce
--- /dev/null
+++ b/include/dt-bindings/power/rk3328-power.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__
+#define __DT_BINDINGS_POWER_RK3328_POWER_H__
+
+/**
+ * RK3328 idle id Summary.
+ */
+#define RK3328_PD_CORE 0
+#define RK3328_PD_GPU 1
+#define RK3328_PD_BUS 2
+#define RK3328_PD_MSCH 3
+#define RK3328_PD_PERI 4
+#define RK3328_PD_VIDEO5
+#define RK3328_PD_HEVC 6
+#define RK3328_PD_SYS 7
+#define RK3328_PD_VPU 8
+#define RK3328_PD_VIO 9
+
+#endif
--
2.26.0
Please pull u-boot-x86
Hi Tom, This PR includes the following changes for v2020.04 release: - verdin-imx8mm board reST documentation update - Intel Edison board ACPI table I2C/USB minor updates - Fix a regression of ns16550 serial driver that breaks Intel Edison The following changes since commit e0718b3ab754860bd47677e6b4fc5b70da42c4ab: Merge tag 'dm-pull-1apr20' of git://git.denx.de/u-boot-dm (2020-04-01 14:29:21 -0400) are available in the git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-x86 for you to fetch changes up to 9e6ce62190b7cd874d2bf727c7681292551ba6b9: serial: ns16550: Fix ordering of getting base address (2020-04-04 22:08:44 +0800) Andy Shevchenko (3): x86: acpi: Refactor XSDT handling in acpi_add_table() x86: acpi: Add I²C timings to Intel Merrifield platform x86: acpi: Describe USB 3 host controller found on Intel Tangier Bin Meng (1): serial: ns16550: Fix ordering of getting base address Igor Opaniuk (1): doc: board: verdin-imx8mm: use mainline TF-A arch/x86/include/asm/arch-tangier/acpi/southcluster.asl | 77 + arch/x86/lib/acpi_table.c | 37 +++-- doc/board/toradex/verdin-imx8mm.rst | 26 ++ drivers/serial/ns16550.c| 39 ++- 4 files changed, 124 insertions(+), 55 deletions(-) Regards, Bin
[PULL] u-boot-sh/master
This is a small fix for current release (2020.04) The following changes since commit e0718b3ab754860bd47677e6b4fc5b70da42c4ab: Merge tag 'dm-pull-1apr20' of git://git.denx.de/u-boot-dm (2020-04-01 14:29:21 -0400) are available in the Git repository at: git://git.denx.de/u-boot-sh.git master for you to fetch changes up to b13da11255a01475d41bdc5d367d55ed3656bae8: net: sh_eth: Init the hardware before PHY access (2020-04-04 15:06:37 +0200) Marek Vasut (1): net: sh_eth: Init the hardware before PHY access drivers/net/sh_eth.c | 4 1 file changed, 4 insertions(+)
Re: [PATCH] efi_loader: enable RNG if DM_RNG is enabled
On Wed, 1 Apr 2020 at 15:45, Peter Robinson wrote: > Enable EFI_RNG_PROTOCOL by default if DM_RNG is set. > > Signed-off-by: Peter Robinson > --- > > I think it makes sense to enable EFI_RNG_PROTOCOL by default if a config > has enabled both DM_RNG and UEFI. > Acked-by: Sughosh Ganu -sughosh > > lib/efi_loader/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig > index 9890144d41..b9a770281e 100644 > --- a/lib/efi_loader/Kconfig > +++ b/lib/efi_loader/Kconfig > @@ -125,6 +125,7 @@ config EFI_GRUB_ARM32_WORKAROUND > > config EFI_RNG_PROTOCOL > bool "EFI_RNG_PROTOCOL support" > + default y if DM_RNG > depends on DM_RNG > help > Provide a EFI_RNG_PROTOCOL implementation using the hardware > random > -- > 2.26.0 > >
Re: [PATCH 1/5] arm: dts: rockchip: rk3399: add and enable rng node
On Tue, 31 Mar 2020 at 15:10, Lin Jinhan wrote:
> Add rng node in rk3399-u-boot.dtsi and enable it in
> rk3399-evb-u-boot.dtsi.
>
> Signed-off-by: Lin Jinhan
>
For the series
Reviewed-by: Sughosh Ganu
I guess Kever can pick it up directly in the rockchip tree. Thanks.
-sughosh
> ---
> arch/arm/dts/rk3399-evb-u-boot.dtsi | 5 +
> arch/arm/dts/rk3399-u-boot.dtsi | 6 ++
> 2 files changed, 11 insertions(+)
>
> diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi
> b/arch/arm/dts/rk3399-evb-u-boot.dtsi
> index ccb33d34d1..5b50c5ba30 100644
> --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
> +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
> @@ -11,3 +11,8 @@
> u-boot,spl-boot-order = ,
> };
> };
> +
> + {
> + status = "okay";
> +};
> +
> diff --git a/arch/arm/dts/rk3399-u-boot.dtsi
> b/arch/arm/dts/rk3399-u-boot.dtsi
> index 8b857ccfc7..757b8c10a2 100644
> --- a/arch/arm/dts/rk3399-u-boot.dtsi
> +++ b/arch/arm/dts/rk3399-u-boot.dtsi
> @@ -25,6 +25,12 @@
> clock-names = "pclk_ddr_mon";
> };
>
> + rng: rng@ff8b8000 {
> + compatible = "rockchip,cryptov1-rng";
> + reg = <0x0 0xff8b8000 0x0 0x1000>;
> + status = "disabled";
> + };
> +
> dmc: dmc {
> u-boot,dm-pre-reloc;
> compatible = "rockchip,rk3399-dmc";
> --
> 2.17.1
>
>
>
>
RE: [U-Boot] [PATCH v2 5/5] sifive: fu540: Enable spi-nor flash support
Hello Jagan,
> -Original Message-
> From: Jagan Teki
> Sent: Saturday, April 4, 2020 11:45 PM
> To: Sagar Kadam
> Cc: Bin Meng ; Palmer Dabbelt
> ; U-Boot Mailing List ; linux-
> amarula
> Subject: Re: [U-Boot] [PATCH v2 5/5] sifive: fu540: Enable spi-nor flash
> support
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> Hi Sagar,
>
> On Mon, Nov 18, 2019 at 2:29 AM Sagar Kadam
> wrote:
> >
> >
> > Hello Jagan/Bin,
> >
> > > -Original Message-
> > > From: U-Boot On Behalf Of Bin Meng
> > > Sent: Monday, November 11, 2019 8:02 PM
> > > To: Jagan Teki
> > > Cc: Palmer Dabbelt ( Sifive) ; U-Boot Mailing List
> > > b...@lists.denx.de>; linux-amarula amar...@amarulasolutions.com>
> > > Subject: Re: [U-Boot] [PATCH v2 5/5] sifive: fu540: Enable spi-nor flash
> > > support
> > >
> > > Hi Jagan,
> > >
> > > On Sat, Nov 9, 2019 at 7:57 PM Jagan Teki
>
> > > wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > On Tue, Oct 29, 2019 at 3:50 PM Bin Meng
> wrote:
> > > > >
> > > > > Hi Jagan,
> > > > >
> > > > > On Tue, Oct 29, 2019 at 5:38 PM Bin Meng
> > > wrote:
> > > > > >
> > > > > > Hi Jagan,
> > > > > >
> > > > > > On Wed, Oct 16, 2019 at 10:58 PM Jagan Teki
> > > wrote:
> > > > > > >
> > > > > > > HiFive Unleashed A00 support is25wp256 spi-nor flash,
> > > > > > > So enable the same and add test result log for future
> > > > > > > reference.
> > > > > > >
> > > > > > > Tested on SiFive FU540 board.
> > > > > > >
> > > > > > > Signed-off-by: Jagan Teki
> > > > > > > Reviewed-by: Bin Meng
> > > > > > > Tested-by: Bin Meng
> > > > > > > ---
> > > > > > > .../dts/hifive-unleashed-a00-u-boot.dtsi | 1 +
> > > > > > > board/sifive/fu540/Kconfig| 3 +++
> > > > > > > doc/board/sifive/fu540.rst| 19
> +++
> > > > > > > 3 files changed, 23 insertions(+)
> > > > > > >
> > > > > > > diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > > b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > > > > > > index 25ec8265a5..d7a64134db 100644
> > > > > > > --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > > > > > > +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > > > > > > @@ -5,6 +5,7 @@
> > > > > > >
> > > > > > > / {
> > > > > > > aliases {
> > > > > > > + spi0 =
> > > > > > > spi2 =
> > > > > > > };
> > > > > > > };
> > > > > > > diff --git a/board/sifive/fu540/Kconfig
> b/board/sifive/fu540/Kconfig
> > > > > > > index 5d65080429..c5a1bca03c 100644
> > > > > > > --- a/board/sifive/fu540/Kconfig
> > > > > > > +++ b/board/sifive/fu540/Kconfig
> > > > > > > @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> > > > > > > imply CMD_FS_GENERIC
> > > > > > > imply CMD_NET
> > > > > > > imply CMD_PING
> > > > > > > + imply CMD_SF
> > > > > > > imply CLK_SIFIVE
> > > > > > > imply CLK_SIFIVE_FU540_PRCI
> > > > > > > imply DOS_PARTITION
> > > > > > > @@ -40,6 +41,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> > > > > > > imply SIFIVE_SERIAL
> > > > > > > imply SPI
> > > > > > > imply SPI_SIFIVE
> > > > > > > + imply SPI_FLASH
> > > > > > > + imply SPI_FLASH_ISSI
> > > > > > > imply MMC
> > > > > > > imply MMC_SPI
> > > > > > > imply MMC_BROKEN_CD
> > > > > > > diff --git a/doc/board/sifive/fu540.rst
> b/doc/board/sifive/fu540.rst
> > > > > > > index 91b94ee06f..2e70cad02e 100644
> > > > > > > --- a/doc/board/sifive/fu540.rst
> > > > > > > +++ b/doc/board/sifive/fu540.rst
> > > > > > > @@ -366,3 +366,22 @@ load uImage.
> > > > > > >
> > > > > > > Please press Enter to activate this console.
> > > > > > > / #
> > > > > > > +
> > > > > > > +Sample spi nor flash test
> > > > > > > +-
> > > > > > > +
> > > > > > > +.. code-block:: none
> > > > > > > +
> > > > > > > + => sf probe 0:2
> > > > > >
> > > > > > The cs number can't be 2. It should be zero.
> > > > >
> > > > > With this patch series, we got crazy duplicated flash devices created,
> > > > > see below:
> > > > >
> > > > > => sf probe
> > > > > unrecognized JEDEC id bytes: ff, ff, ff
> > > > > Failed to initialize SPI flash at 0:0 (error -2)
> > > > > => sf probe 0:2
> > > > > SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB,
> total 32
> > > MiB
> > > > > => sf probe 0:4
> > > > > SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB,
> total 32
> > > MiB
> > > > > => sf probe 0:6
> > > > > SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB,
> total 32
> > > MiB
> > > > > => dm tree
> > > > > Class Index Probed DriverName
> > > > > ---
> > > > > root 0 [ + ] root_driver root_driver
> > > > > simple_bus0 [ + ] generic_simple_bus|-- soc
> > >
Re: [U-Boot] [PATCH v2 5/5] sifive: fu540: Enable spi-nor flash support
Hi Bin,
On Mon, Nov 18, 2019 at 8:19 AM Bin Meng wrote:
>
> Hi Segar Kadam,
>
> On Mon, Nov 18, 2019 at 4:59 AM Sagar Kadam wrote:
> >
> >
> > Hello Jagan/Bin,
> >
> > > -Original Message-
> > > From: U-Boot On Behalf Of Bin Meng
> > > Sent: Monday, November 11, 2019 8:02 PM
> > > To: Jagan Teki
> > > Cc: Palmer Dabbelt ( Sifive) ; U-Boot Mailing List > > b...@lists.denx.de>; linux-amarula
> > > Subject: Re: [U-Boot] [PATCH v2 5/5] sifive: fu540: Enable spi-nor flash
> > > support
> > >
> > > Hi Jagan,
> > >
> > > On Sat, Nov 9, 2019 at 7:57 PM Jagan Teki
> > > wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > On Tue, Oct 29, 2019 at 3:50 PM Bin Meng wrote:
> > > > >
> > > > > Hi Jagan,
> > > > >
> > > > > On Tue, Oct 29, 2019 at 5:38 PM Bin Meng
> > > wrote:
> > > > > >
> > > > > > Hi Jagan,
> > > > > >
> > > > > > On Wed, Oct 16, 2019 at 10:58 PM Jagan Teki
> > > wrote:
> > > > > > >
> > > > > > > HiFive Unleashed A00 support is25wp256 spi-nor flash,
> > > > > > > So enable the same and add test result log for future
> > > > > > > reference.
> > > > > > >
> > > > > > > Tested on SiFive FU540 board.
> > > > > > >
> > > > > > > Signed-off-by: Jagan Teki
> > > > > > > Reviewed-by: Bin Meng
> > > > > > > Tested-by: Bin Meng
> > > > > > > ---
> > > > > > > .../dts/hifive-unleashed-a00-u-boot.dtsi | 1 +
> > > > > > > board/sifive/fu540/Kconfig| 3 +++
> > > > > > > doc/board/sifive/fu540.rst| 19
> > > > > > > +++
> > > > > > > 3 files changed, 23 insertions(+)
> > > > > > >
> > > > > > > diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > > b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > > > > > > index 25ec8265a5..d7a64134db 100644
> > > > > > > --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > > > > > > +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > > > > > > @@ -5,6 +5,7 @@
> > > > > > >
> > > > > > > / {
> > > > > > > aliases {
> > > > > > > + spi0 =
> > > > > > > spi2 =
> > > > > > > };
> > > > > > > };
> > > > > > > diff --git a/board/sifive/fu540/Kconfig
> > > > > > > b/board/sifive/fu540/Kconfig
> > > > > > > index 5d65080429..c5a1bca03c 100644
> > > > > > > --- a/board/sifive/fu540/Kconfig
> > > > > > > +++ b/board/sifive/fu540/Kconfig
> > > > > > > @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> > > > > > > imply CMD_FS_GENERIC
> > > > > > > imply CMD_NET
> > > > > > > imply CMD_PING
> > > > > > > + imply CMD_SF
> > > > > > > imply CLK_SIFIVE
> > > > > > > imply CLK_SIFIVE_FU540_PRCI
> > > > > > > imply DOS_PARTITION
> > > > > > > @@ -40,6 +41,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> > > > > > > imply SIFIVE_SERIAL
> > > > > > > imply SPI
> > > > > > > imply SPI_SIFIVE
> > > > > > > + imply SPI_FLASH
> > > > > > > + imply SPI_FLASH_ISSI
> > > > > > > imply MMC
> > > > > > > imply MMC_SPI
> > > > > > > imply MMC_BROKEN_CD
> > > > > > > diff --git a/doc/board/sifive/fu540.rst
> > > > > > > b/doc/board/sifive/fu540.rst
> > > > > > > index 91b94ee06f..2e70cad02e 100644
> > > > > > > --- a/doc/board/sifive/fu540.rst
> > > > > > > +++ b/doc/board/sifive/fu540.rst
> > > > > > > @@ -366,3 +366,22 @@ load uImage.
> > > > > > >
> > > > > > > Please press Enter to activate this console.
> > > > > > > / #
> > > > > > > +
> > > > > > > +Sample spi nor flash test
> > > > > > > +-
> > > > > > > +
> > > > > > > +.. code-block:: none
> > > > > > > +
> > > > > > > + => sf probe 0:2
> > > > > >
> > > > > > The cs number can't be 2. It should be zero.
> > > > >
> > > > > With this patch series, we got crazy duplicated flash devices created,
> > > > > see below:
> > > > >
> > > > > => sf probe
> > > > > unrecognized JEDEC id bytes: ff, ff, ff
> > > > > Failed to initialize SPI flash at 0:0 (error -2)
> > > > > => sf probe 0:2
> > > > > SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB,
> > > > > total 32
> > > MiB
> > > > > => sf probe 0:4
> > > > > SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB,
> > > > > total 32
> > > MiB
> > > > > => sf probe 0:6
> > > > > SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB,
> > > > > total 32
> > > MiB
> > > > > => dm tree
> > > > > Class Index Probed DriverName
> > > > > ---
> > > > > root 0 [ + ] root_driver root_driver
> > > > > simple_bus0 [ + ] generic_simple_bus|-- soc
> > > > > clk 0 [ + ] sifive-fu540-prci | |--
> > > > > clock-controller@1000
> > > > > serial0 [ + ] serial_sifive | |--
> > > > > serial@1001
> > > > > serial1 [ ] serial_sifive | |--
> > > > > serial@10011000
> > > > > spi 0 [
Re: [U-Boot] [PATCH v2 5/5] sifive: fu540: Enable spi-nor flash support
Hi Sagar,
On Mon, Nov 18, 2019 at 2:29 AM Sagar Kadam wrote:
>
>
> Hello Jagan/Bin,
>
> > -Original Message-
> > From: U-Boot On Behalf Of Bin Meng
> > Sent: Monday, November 11, 2019 8:02 PM
> > To: Jagan Teki
> > Cc: Palmer Dabbelt ( Sifive) ; U-Boot Mailing List > b...@lists.denx.de>; linux-amarula
> > Subject: Re: [U-Boot] [PATCH v2 5/5] sifive: fu540: Enable spi-nor flash
> > support
> >
> > Hi Jagan,
> >
> > On Sat, Nov 9, 2019 at 7:57 PM Jagan Teki
> > wrote:
> > >
> > > Hi Bin,
> > >
> > > On Tue, Oct 29, 2019 at 3:50 PM Bin Meng wrote:
> > > >
> > > > Hi Jagan,
> > > >
> > > > On Tue, Oct 29, 2019 at 5:38 PM Bin Meng
> > wrote:
> > > > >
> > > > > Hi Jagan,
> > > > >
> > > > > On Wed, Oct 16, 2019 at 10:58 PM Jagan Teki
> > wrote:
> > > > > >
> > > > > > HiFive Unleashed A00 support is25wp256 spi-nor flash,
> > > > > > So enable the same and add test result log for future
> > > > > > reference.
> > > > > >
> > > > > > Tested on SiFive FU540 board.
> > > > > >
> > > > > > Signed-off-by: Jagan Teki
> > > > > > Reviewed-by: Bin Meng
> > > > > > Tested-by: Bin Meng
> > > > > > ---
> > > > > > .../dts/hifive-unleashed-a00-u-boot.dtsi | 1 +
> > > > > > board/sifive/fu540/Kconfig| 3 +++
> > > > > > doc/board/sifive/fu540.rst| 19
> > > > > > +++
> > > > > > 3 files changed, 23 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > > > > > index 25ec8265a5..d7a64134db 100644
> > > > > > --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > > > > > +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > > > > > @@ -5,6 +5,7 @@
> > > > > >
> > > > > > / {
> > > > > > aliases {
> > > > > > + spi0 =
> > > > > > spi2 =
> > > > > > };
> > > > > > };
> > > > > > diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
> > > > > > index 5d65080429..c5a1bca03c 100644
> > > > > > --- a/board/sifive/fu540/Kconfig
> > > > > > +++ b/board/sifive/fu540/Kconfig
> > > > > > @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> > > > > > imply CMD_FS_GENERIC
> > > > > > imply CMD_NET
> > > > > > imply CMD_PING
> > > > > > + imply CMD_SF
> > > > > > imply CLK_SIFIVE
> > > > > > imply CLK_SIFIVE_FU540_PRCI
> > > > > > imply DOS_PARTITION
> > > > > > @@ -40,6 +41,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> > > > > > imply SIFIVE_SERIAL
> > > > > > imply SPI
> > > > > > imply SPI_SIFIVE
> > > > > > + imply SPI_FLASH
> > > > > > + imply SPI_FLASH_ISSI
> > > > > > imply MMC
> > > > > > imply MMC_SPI
> > > > > > imply MMC_BROKEN_CD
> > > > > > diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst
> > > > > > index 91b94ee06f..2e70cad02e 100644
> > > > > > --- a/doc/board/sifive/fu540.rst
> > > > > > +++ b/doc/board/sifive/fu540.rst
> > > > > > @@ -366,3 +366,22 @@ load uImage.
> > > > > >
> > > > > > Please press Enter to activate this console.
> > > > > > / #
> > > > > > +
> > > > > > +Sample spi nor flash test
> > > > > > +-
> > > > > > +
> > > > > > +.. code-block:: none
> > > > > > +
> > > > > > + => sf probe 0:2
> > > > >
> > > > > The cs number can't be 2. It should be zero.
> > > >
> > > > With this patch series, we got crazy duplicated flash devices created,
> > > > see below:
> > > >
> > > > => sf probe
> > > > unrecognized JEDEC id bytes: ff, ff, ff
> > > > Failed to initialize SPI flash at 0:0 (error -2)
> > > > => sf probe 0:2
> > > > SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB,
> > > > total 32
> > MiB
> > > > => sf probe 0:4
> > > > SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB,
> > > > total 32
> > MiB
> > > > => sf probe 0:6
> > > > SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB,
> > > > total 32
> > MiB
> > > > => dm tree
> > > > Class Index Probed DriverName
> > > > ---
> > > > root 0 [ + ] root_driver root_driver
> > > > simple_bus0 [ + ] generic_simple_bus|-- soc
> > > > clk 0 [ + ] sifive-fu540-prci | |--
> > > > clock-controller@1000
> > > > serial0 [ + ] serial_sifive | |-- serial@1001
> > > > serial1 [ ] serial_sifive | |-- serial@10011000
> > > > spi 0 [ + ] sifive_spi| |-- spi@1004
> > > > spi_flash 0 [ ] spi_flash_std | | |-- flash@0
> > > > spi_flash 1 [ + ] spi_flash_std | | |--
> > > > spi_flash@0:2
> > > > spi_flash 2 [ + ] spi_flash_std | | |--
> > > > spi_flash@0:4
> > > > spi_flash 3 [ + ] spi_flash_std | | `--
> >
Re: [PATCH v3] serial: ns16550: Fix ordering of getting base address
On Sat, Apr 4, 2020 at 6:32 PM Andy Shevchenko
wrote:
>
> On Fri, Apr 03, 2020 at 06:35:32PM -0700, Bin Meng wrote:
> > Currently the driver gets ns16550 base address in the driver
> > probe() routine, which may potentially break any ns16550 wrapper
> > driver that does additional initialization before calling
> > ns16550_serial_probe().
> >
> > Things are complicated that we need consider ns16550 devices on
> > both simple-bus and PCI bus. To fix the issue we move the base
> > address assignment for simple-bus ns16550 device back to the
> > ofdata_to_platdata(), and assign base address for PCI ns16550
> > device in ns16550_serial_probe().
> >
> > This is still not perfect. If any PCI bus based ns16550 wrapper
> > driver tries to access plat->base before calling probe(), it is
> > still subject to break.
> >
> > Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from
> > ofdata_to_platdata() to probe()")
> > Reported-by: Andy Shevchenko
> > Signed-off-by: Bin Meng
>
> And re-tested. Works for me, thanks!
>
> > Tested-by: Andy Shevchenko
> > Reviewed-by: Wolfgang Wallner
> > Tested-by: Wolfgang Wallner
> >
applied to u-boot-x86, thanks!
[PATCH] ARM: dts: rmobile: Synchronize Gen2 DTs with Linux 5.6.2
Synchronize R-Car Gen2 device trees with Linux 5.6.2,
commit 9fbe5c87eaa9b72db08425c52c373eb5f6537a0a .
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/dts/r8a7790-lager.dts| 23 +--
arch/arm/dts/r8a7790-stout.dts| 9 +-
arch/arm/dts/r8a7790.dtsi | 167 +++---
arch/arm/dts/r8a7791-koelsch.dts | 18 ++-
arch/arm/dts/r8a7791-porter.dts | 15 +-
arch/arm/dts/r8a7791.dtsi | 159 ++--
arch/arm/dts/r8a7792-blanche.dts | 29 +++-
arch/arm/dts/r8a7792.dtsi | 102 -
arch/arm/dts/r8a7793-gose.dts | 128 +
arch/arm/dts/r8a7793.dtsi | 123
arch/arm/dts/r8a7794-alt.dts | 55 ++-
arch/arm/dts/r8a7794-silk.dts | 5 +-
arch/arm/dts/r8a7794.dtsi | 111 +++---
include/dt-bindings/clock/r8a7790-clock.h | 6 +-
include/dt-bindings/clock/r8a7791-clock.h | 6 +-
include/dt-bindings/clock/r8a7792-clock.h | 6 +-
include/dt-bindings/power/r8a7790-sysc.h | 5 +-
include/dt-bindings/power/r8a7791-sysc.h | 5 +-
include/dt-bindings/power/r8a7792-sysc.h | 5 +-
include/dt-bindings/power/r8a7793-sysc.h | 5 +-
20 files changed, 551 insertions(+), 431 deletions(-)
diff --git a/arch/arm/dts/r8a7790-lager.dts b/arch/arm/dts/r8a7790-lager.dts
index 7b9508e83d..097fd9317c 100644
--- a/arch/arm/dts/r8a7790-lager.dts
+++ b/arch/arm/dts/r8a7790-lager.dts
@@ -56,7 +56,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
@@ -150,8 +150,7 @@
gpios = < 29 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <330 1
- 180 0>;
+ states = <330 1>, <180 0>;
};
vcc_sdhi2: regulator-vcc-sdhi2 {
@@ -174,8 +173,7 @@
gpios = < 30 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <330 1
- 180 0>;
+ states = <330 1>, <180 0>;
};
audio_clock: audio_clock {
@@ -325,10 +323,10 @@
#size-cells = <0>;
};
-/*
- * IIC2 and I2C2 may be switched using pinmux.
- * A fallback to GPIO is also provided.
- */
+ /*
+* IIC2 and I2C2 may be switched using pinmux.
+* A fallback to GPIO is also provided.
+*/
i2chdmi: i2c-12 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <>, <>, <>;
@@ -423,6 +421,8 @@
*/
i2cpwr: i2c-13 {
compatible = "i2c-demux-pinctrl";
+ pinctrl-names = "default";
+ pinctrl-0 = <_irq_pins>;
i2c-parent = <>, <>;
i2c-bus-name = "i2c-pwr";
#address-cells = <1>;
@@ -615,6 +615,11 @@
function = "iic3";
};
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
+
hsusb_pins: hsusb {
groups = "usb0_ovc_vbus";
function = "usb0";
diff --git a/arch/arm/dts/r8a7790-stout.dts b/arch/arm/dts/r8a7790-stout.dts
index 7a7d3b84d1..a315ba749a 100644
--- a/arch/arm/dts/r8a7790-stout.dts
+++ b/arch/arm/dts/r8a7790-stout.dts
@@ -19,7 +19,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
@@ -179,6 +179,11 @@
function = "iic3";
};
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
+
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
@@ -317,7 +322,7 @@
{
pinctrl-names = "default";
- pinctrl-0 = <_pins>;
+ pinctrl-0 = <_pins _irq_pins>;
status = "okay";
pmic@58 {
diff --git a/arch/arm/dts/r8a7790.dtsi b/arch/arm/dts/r8a7790.dtsi
index 5a2747758f..334ba19769 100644
--- a/arch/arm/dts/r8a7790.dtsi
+++ b/arch/arm/dts/r8a7790.dtsi
@@ -487,6 +487,9 @@
icram0: sram@e63a {
compatible = "mmio-sram";
reg = <0 0xe63a 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a 0x12000>;
};
icram1: sram@e63c {
@@ -669,8 +672,8 @@
compatible = "renesas,r8a7790-usb-dmac",
"renesas,usb-dmac";
[PATCH] bmips: allow disabling usb support
Currently, if usb is disabled the following error is produced: CC drivers/usb/host/ohci-hcd.o drivers/usb/host/ohci-hcd.c: In function ‘usb_lowlevel_init’: drivers/usb/host/ohci-hcd.c:2057:35: error: ‘CONFIG_SYS_USB_OHCI_REGS_BASE’ undeclared (first use in this function); did you mean ‘CONFIG_SYS_MONITOR_BASE’? gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; ^ CONFIG_SYS_MONITOR_BASE drivers/usb/host/ohci-hcd.c:2057:35: note: each undeclared identifier is reported only once for each function it appears in drivers/usb/host/ohci-hcd.c:2061:20: error: ‘CONFIG_SYS_USB_OHCI_SLOT_NAME’ undeclared (first use in this function); did you mean ‘CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS’? gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; ^ CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS Signed-off-by: Álvaro Fernández Rojas --- include/configs/bmips_bcm6318.h | 2 ++ include/configs/bmips_bcm63268.h | 2 ++ include/configs/bmips_bcm6328.h | 2 ++ include/configs/bmips_bcm6348.h | 2 ++ include/configs/bmips_bcm6358.h | 2 ++ include/configs/bmips_bcm6362.h | 2 ++ include/configs/bmips_bcm6368.h | 2 ++ 7 files changed, 14 insertions(+) diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index c7e7119aaf..45eb931c25 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -19,7 +19,9 @@ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index 45f26bb309..eed321eb6f 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -19,7 +19,9 @@ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index 8d59438785..c78099a49d 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -19,7 +19,9 @@ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index 061d6b25b7..547cf857ce 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -17,7 +17,9 @@ /* USB */ #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index 583217d262..116e9705b6 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -19,7 +19,9 @@ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index 570bc3b33d..e5e8b15e18 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -19,7 +19,9 @@ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index ab5bdac726..4d4403f8d2 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -19,7 +19,9 @@ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M -- 2.20.1
Re: i.MX8QXP hangs in SPL after a "reboot" command
On Thu, Apr 2, 2020 at 4:21 PM Fabio Estevam wrote:
> U-Boot SPL 2020.04-rc4-00061-ge0718b3ab7 (Apr 02 2020 - 16:14:22 -0300)
> Normal Boot
> WDT: Not found!
> Trying to boot from MMC2_2
> spl: mmc init failed with error: -70
> SPL: failed to boot from all boot devices
> ### ERROR ### Please RESET the board ###
I added the following debug line:
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -499,6 +499,7 @@ static int esdhc_send_cmd_common(struct
fsl_esdhc_priv *priv, struct mmc *mmc,
irqstat = esdhc_read32(>irqstat);
if (irqstat & CMD_ERR) {
+ printf("** -ECOMM comming from 1\n");
err = -ECOMM;
goto out;
}
And this is what I got after issuing a 'reboot' command in Linux:
# reboot
# Stopping network: OK
Saving random seed: [5.255229] random: dd: uninitialized urandom
read (512 bytes read)
OK
Stopping klogd: OK
Stopping syslogd: OK
umount: devtmpfs busy - remounted read-only
[5.309631] EXT4-fs (mmcblk1p2): re-mounted. Opts: (null)
The system is going down NOW!
Sent SIGTERM to all processes
Sen[7.318988] kvm: exiting hardware virtualization
[7.339445] reboot: Restarting system
U-Boot SPL 2020.04-rc4-00062-g1e193557d5-dirty (Apr 04 2020 - 10:14:43 -0300)
Normal Boot
WDT: Not found!
Trying to boot from MMC2_2
** -ECOMM comming from 1
** -ECOMM comming from 1
spl: mmc init failed with error: -70
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Any ideas as to why CMD_ERR bit is being set in the irqstat register?
Thanks
[PATCH] net: sh_eth: Init the hardware before PHY access
To access the PHY, the MAC registers must be initialized. Call the init
function in probe() to make it so, otherwise the PHY ID readout returns
all zeroes.
Signed-off-by: Marek Vasut
Cc: Joe Hershberger
Cc: Nobuhiro Iwamatsu
---
NOTE: This is for 2020.04
---
drivers/net/sh_eth.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 183e8e3083..f8e5d05722 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -859,6 +859,10 @@ static int sh_ether_probe(struct udevice *udev)
goto err_mdio_register;
#endif
+ ret = sh_eth_init_common(eth, pdata->enetaddr);
+ if (ret)
+ goto err_phy_config;
+
ret = sh_eth_phy_config(udev);
if (ret) {
printf(SHETHER_NAME ": phy config timeout\n");
--
2.25.1
Re: [PATCH 3/3] dm: core: refactor functions reading an u32 from dt
> Il 2 aprile 2020 alle 20.54 Simon Glass ha scritto: > > > Hi Dario, > > On Wed, 1 Apr 2020 at 13:34, wrote: > > > > > > > Il 31 marzo 2020 alle 1.57 Simon Glass ha scritto: > > > > > > > > > On Sun, 29 Mar 2020 at 10:05, Dario Binacchi wrote: > > > > > > > > Now reading a 32 bit value from a device-tree property can be expressed > > > > as reading the first element of an array with a single value. > > > > > > > > Signed-off-by: Dario Binacchi > > > > > > > > --- > > > > > > > > drivers/core/of_access.c | 16 +--- > > > > drivers/core/ofnode.c| 23 ++- > > > > 2 files changed, 3 insertions(+), 36 deletions(-) > > > > > > Reviewed-by: Simon Glass > > > > > > Can you please check the code-size delta in SPL on a suitable board? > > > > I have a black beaglebone available (am335x_evm_defconfig). > > > > u-boot-spl.map generated without applying the refactoring patch > > > > .text.ofnode_read_u32 > > 0x 0x2e drivers/built-in.o > > .text.ofnode_read_u32_index > > 0x 0x38 drivers/built-in.o > > .text.ofnode_read_u32_default > > 0x 0x12 drivers/built-in.o > > > > u-boot-spl.map genarated with the refactoring patch applied > > > > .text.ofnode_read_u32_index > > 0x 0x38 drivers/built-in.o > > .text.ofnode_read_u32 > > 0x0x8 drivers/built-in.o > > .text.ofnode_read_u32_default > > 0x 0x14 drivers/built-in.o > > Possibly, but a better test is to build your branch with the patch in: > > buildman -b > > Then check the size: > > buildman -b -sS > > or function detail: > > buildman -b -sSB > > That will give us a true picture for SPL. It will show incremental > size increase with your patch. Hi Simon, this is the buildman response: ... 03: dm: core: support reading a single indexed u32 value 04: dm: core: refactor functions reading an u32 from dt arm: (for 4/708 boards) all +11.5 bss -10.0 text +21.5 am335x_hs_evm : all +24 text +24 u-boot: add: 1/0, grow: 1/-1 bytes: 64/-38 (26) function old new delta ofnode_read_u32_index- 62 +62 ofnode_read_u32_default 18 20 +2 ofnode_read_u32 46 8 -38 am335x_hs_evm_uart: all +24 text +24 u-boot: add: 1/0, grow: 1/-1 bytes: 64/-38 (26) function old new delta ofnode_read_u32_index- 62 +62 ofnode_read_u32_default 18 20 +2 ofnode_read_u32 46 8 -38 am335x_evm : bss -24 text +24 u-boot: add: 1/0, grow: 1/-1 bytes: 64/-38 (26) function old new delta ofnode_read_u32_index- 62 +62 ofnode_read_u32_default 18 20 +2 ofnode_read_u32 46 8 -38 am335x_boneblack_vboot: all -2 bss -16 text +14 u-boot: add: 1/0, grow: 1/-1 bytes: 64/-38 (26) function old new delta ofnode_read_u32_index- 62 +62 ofnode_read_u32_default 18 20 +2 ofnode_read_u32 46 8 -38 Regards, Dario > > See buildman docs for more info. > > Regards, > Simon
[PATCH V2 5/5] mmc: tmio: sdhi: Implement get_b_max function
Implement get_b_max() for the Renesas R-Car SDHI controller driver, limit
the b_max per hardware capabilities such that select Gen2 controllers have
16bit block transfer limit, the rest has 32bit block transfer limit and on
Gen3, the block transfer limit on addresses above the 32bit boundary is set
to 1/4 of the malloc area.
Originally, on Gen3, the block transfers above the 32bit area were limited
to PIO only, which resulted in (R8A7795 Salvator-X , HS200 eMMC):
=> time mmc read 0x0007 0 0x1
time: 0.151 seconds
=> time mmc read 0x0007 0 0x10
time: 11.090 seconds
with bounce buffer in place and b_max adjustment in place:
=> time mmc read 0x0007 0 0x1
time: 0.156 seconds
=> time mmc read 0x0007 0 0x10
time: 2.349 seconds
Note that the bounce buffer does mallocate and free the bounce buffer
for every transfer. Experiment which removes this results in further
increase of read speed, from 2.349s to 2.156s per 512 MiB of data,
which is not such a significant improvement anymore. It might however
be interesting to have bounce buffer directly in the MMC core or even
block core.
Signed-off-by: Marek Vasut
Cc: Daniel Schwierzeck
Cc: Masahiro Yamada
Cc: Peng Fan
Cc: Simon Glass
Cc: Tom Rini
---
V2: Fix printing of ubuf on 32bit systems, use %lx instead
---
drivers/mmc/renesas-sdhi.c | 46 +-
drivers/mmc/tmio-common.h | 1 +
2 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 231a78178c..88a7160b0a 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -692,28 +692,26 @@ static int renesas_sdhi_wait_dat0(struct udevice *dev,
int state,
#define RENESAS_SDHI_DMA_ALIGNMENT 128
-static int renesas_sdhi_addr_aligned(struct bounce_buffer *state)
+static int renesas_sdhi_addr_aligned_gen(uintptr_t ubuf,
+size_t len, size_t len_aligned)
{
- uintptr_t ubuf = (uintptr_t)state->user_buffer;
-
/* Check if start is aligned */
if (!IS_ALIGNED(ubuf, RENESAS_SDHI_DMA_ALIGNMENT)) {
- debug("Unaligned buffer address %p\n", state->user_buffer);
+ debug("Unaligned buffer address %lx\n", ubuf);
return 0;
}
/* Check if length is aligned */
- if (state->len != state->len_aligned) {
- debug("Unaligned buffer length %zu\n", state->len);
+ if (len != len_aligned) {
+ debug("Unaligned buffer length %zu\n", len);
return 0;
}
#ifdef CONFIG_PHYS_64BIT
/* Check if below 32bit boundary */
- if ((ubuf >> 32) || (ubuf + state->len_aligned) >> 32) {
- debug("Buffer above 32bit boundary %p-%p\n",
- state->user_buffer,
- state->user_buffer + state->len_aligned);
+ if ((ubuf >> 32) || (ubuf + len_aligned) >> 32) {
+ debug("Buffer above 32bit boundary %lx-%lx\n",
+ ubuf, ubuf + len_aligned);
return 0;
}
#endif
@@ -722,6 +720,14 @@ static int renesas_sdhi_addr_aligned(struct bounce_buffer
*state)
return 1;
}
+static int renesas_sdhi_addr_aligned(struct bounce_buffer *state)
+{
+ uintptr_t ubuf = (uintptr_t)state->user_buffer;
+
+ return renesas_sdhi_addr_aligned_gen(ubuf, state->len,
+state->len_aligned);
+}
+
static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
@@ -789,6 +795,24 @@ static int renesas_sdhi_send_cmd(struct udevice *dev,
struct mmc_cmd *cmd,
return 0;
}
+int renesas_sdhi_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct mmc *mmc = upriv->mmc;
+ size_t len = blkcnt * mmc->read_bl_len;
+ size_t len_align = roundup(len, RENESAS_SDHI_DMA_ALIGNMENT);
+
+ if (renesas_sdhi_addr_aligned_gen((uintptr_t)dst, len, len_align)) {
+ if (priv->quirks & TMIO_SD_CAP_16BIT)
+ return U16_MAX;
+ else
+ return U32_MAX;
+ } else {
+ return (CONFIG_SYS_MALLOC_LEN / 4) / mmc->read_bl_len;
+ }
+}
+
static const struct dm_mmc_ops renesas_sdhi_ops = {
.send_cmd = renesas_sdhi_send_cmd,
.set_ios = renesas_sdhi_set_ios,
@@ -801,6 +825,7 @@ static const struct dm_mmc_ops renesas_sdhi_ops = {
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
.wait_dat0 = renesas_sdhi_wait_dat0,
#endif
+ .get_b_max = renesas_sdhi_get_b_max,
};
#define RENESAS_GEN2_QUIRKSTMIO_SD_CAP_RCAR_GEN2
@@ -966,6 +991,7 @@ static int renesas_sdhi_probe(struct udevice *dev)
return
[PATCH V2 4/5] mmc: Add option to adjust b_max before long read
Add getter function which permits adjusting the maximum number of
blocks that could be read in a single sustained read transfer based
on the location of the source/target buffer and length, before such
transfer starts.
This is mainly useful on systems which have various DMA restrictions
for different memory locations, e.g. DMA limited to 32bit addresses,
and where a bounce buffer is used to work around such restrictions.
Since the U-Boot bounce buffer is mallocated, it's size is limited
by the malloc area size, and the read transfer to such a buffer must
also be limited. However, as not all areas are limited equally, the
b_max should be adjusted accordinly as needed to avoid degrading
performance unnecessarily.
Signed-off-by: Marek Vasut
Cc: Daniel Schwierzeck
Cc: Masahiro Yamada
Cc: Peng Fan
Cc: Simon Glass
Cc: Tom Rini
---
V2: No change
---
drivers/mmc/mmc-uclass.c | 16
drivers/mmc/mmc.c| 16 ++--
include/mmc.h| 16
3 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index c75892a72c..cb26d841be 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -13,6 +13,22 @@
#include
#include "mmc_private.h"
+int dm_mmc_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt)
+{
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+
+ if (ops->get_b_max)
+ return ops->get_b_max(dev, dst, blkcnt);
+ else
+ return mmc->cfg->b_max;
+}
+
+int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt)
+{
+ return dm_mmc_get_b_max(mmc->dev, dst, blkcnt);
+}
+
int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 3e36566693..e22834398f 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -409,6 +409,16 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst,
lbaint_t start,
return blkcnt;
}
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt)
+{
+ if (mmc->cfg->ops->get_b_max)
+ return mmc->cfg->ops->get_b_max(mmc, dst, blkcnt);
+ else
+ return mmc->cfg->b_max;
+}
+#endif
+
#if CONFIG_IS_ENABLED(BLK)
ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void
*dst)
#else
@@ -422,6 +432,7 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start,
lbaint_t blkcnt,
int dev_num = block_dev->devnum;
int err;
lbaint_t cur, blocks_todo = blkcnt;
+ uint b_max;
if (blkcnt == 0)
return 0;
@@ -451,9 +462,10 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t
start, lbaint_t blkcnt,
return 0;
}
+ b_max = mmc_get_b_max(mmc, dst, blkcnt);
+
do {
- cur = (blocks_todo > mmc->cfg->b_max) ?
- mmc->cfg->b_max : blocks_todo;
+ cur = (blocks_todo > b_max) ? b_max : blocks_todo;
if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
pr_debug("%s: Failed to read blocks\n", __func__);
return 0;
diff --git a/include/mmc.h b/include/mmc.h
index e83c22423b..a24e58b867 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -488,6 +488,19 @@ struct dm_mmc_ops {
* @return 0 if not present, 1 if present, -ve on error
*/
int (*host_power_cycle)(struct udevice *dev);
+
+ /**
+* get_b_max - get maximum length of single transfer
+* Called before reading blocks from the card,
+* useful for system which have e.g. DMA limits
+* on various memory ranges.
+*
+* @dev:Device to check
+* @dst:Destination buffer in memory
+* @blkcnt: Total number of blocks in this transfer
+* @return maximum number of blocks for this transfer
+*/
+ int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt);
};
#define mmc_get_ops(dev)((struct dm_mmc_ops *)(dev)->driver->ops)
@@ -501,6 +514,7 @@ int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us);
int dm_mmc_host_power_cycle(struct udevice *dev);
int dm_mmc_deferred_probe(struct udevice *dev);
+int dm_mmc_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt);
/* Transition functions for compatibility */
int mmc_set_ios(struct mmc *mmc);
@@ -511,6 +525,7 @@ int mmc_wait_dat0(struct mmc *mmc, int state, int
timeout_us);
int mmc_set_enhanced_strobe(struct mmc *mmc);
int mmc_host_power_cycle(struct mmc *mmc);
int mmc_deferred_probe(struct mmc *mmc);
+int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
#else
struct mmc_ops {
@@ -521,6 +536,7 @@
[PATCH V2 2/5] ARM: rmobile: Increase malloc area size
Increase the malloc area size significantly to cater for bounce buffer used by the SDHI driver. Signed-off-by: Marek Vasut Cc: Daniel Schwierzeck Cc: Masahiro Yamada Cc: Peng Fan Cc: Simon Glass Cc: Tom Rini --- V2: No change --- include/configs/rcar-gen3-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 6528f1fa62..8f400ba05a 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -47,7 +47,7 @@ #define CONFIG_SYS_MONITOR_BASE0x #define CONFIG_SYS_MONITOR_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* The HF/QSPI layout permits up to 1 MiB large bootloader blob */ -- 2.25.1
[PATCH V2 1/5] common: bouncebuf: Permit passing custom alignment check function
Add extended version of the bounce_buffer_start(), which permits passing in
a custom alignment checker function for the buffer. This is useful e.g. on
systems with various DMA restrictions and where the checker function might
be more complex than a simple CPU cache alignment check.
Signed-off-by: Marek Vasut
Cc: Daniel Schwierzeck
Cc: Masahiro Yamada
Cc: Peng Fan
Cc: Simon Glass
Cc: Tom Rini
---
V2: No change
---
common/bouncebuf.c | 20 +++-
include/bouncebuf.h | 15 +++
2 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/common/bouncebuf.c b/common/bouncebuf.c
index 614eb36c78..0ace152b98 100644
--- a/common/bouncebuf.c
+++ b/common/bouncebuf.c
@@ -31,17 +31,19 @@ static int addr_aligned(struct bounce_buffer *state)
return 1;
}
-int bounce_buffer_start(struct bounce_buffer *state, void *data,
- size_t len, unsigned int flags)
+int bounce_buffer_start_extalign(struct bounce_buffer *state, void *data,
+size_t len, unsigned int flags,
+size_t alignment,
+int (*addr_is_aligned)(struct bounce_buffer
*state))
{
state->user_buffer = data;
state->bounce_buffer = data;
state->len = len;
- state->len_aligned = roundup(len, ARCH_DMA_MINALIGN);
+ state->len_aligned = roundup(len, alignment);
state->flags = flags;
- if (!addr_aligned(state)) {
- state->bounce_buffer = memalign(ARCH_DMA_MINALIGN,
+ if (!addr_is_aligned(state)) {
+ state->bounce_buffer = memalign(alignment,
state->len_aligned);
if (!state->bounce_buffer)
return -ENOMEM;
@@ -62,6 +64,14 @@ int bounce_buffer_start(struct bounce_buffer *state, void
*data,
return 0;
}
+int bounce_buffer_start(struct bounce_buffer *state, void *data,
+ size_t len, unsigned int flags)
+{
+ return bounce_buffer_start_extalign(state, data, len, flags,
+ ARCH_DMA_MINALIGN,
+ addr_aligned);
+}
+
int bounce_buffer_stop(struct bounce_buffer *state)
{
if (state->flags & GEN_BB_WRITE) {
diff --git a/include/bouncebuf.h b/include/bouncebuf.h
index fd9b0f3b28..7427bd12e2 100644
--- a/include/bouncebuf.h
+++ b/include/bouncebuf.h
@@ -62,6 +62,21 @@ struct bounce_buffer {
*/
int bounce_buffer_start(struct bounce_buffer *state, void *data,
size_t len, unsigned int flags);
+
+/**
+ * bounce_buffer_start() -- Start the bounce buffer session with external
align check function
+ * state: stores state passed between bounce_buffer_{start,stop}
+ * data: pointer to buffer to be aligned
+ * len:length of the buffer
+ * flags: flags describing the transaction, see above.
+ * alignment: alignment of the newly allocated bounce buffer
+ * addr_is_aligned: function for checking the alignment instead of the default
one
+ */
+int bounce_buffer_start_extalign(struct bounce_buffer *state, void *data,
+size_t len, unsigned int flags,
+size_t alignment,
+int (*addr_is_aligned)(struct bounce_buffer
*state));
+
/**
* bounce_buffer_stop() -- Finish the bounce buffer session
* state: stores state passed between bounce_buffer_{start,stop}
--
2.25.1
[PATCH V2 3/5] mmc: tmio: sdhi: Use bounce buffer to avoid DMA limitations
The R-Car SDHI DMA controller has various restrictions. To work around
those restrictions without falling back to PIO, implement bounce buffer
with custom alignment check function which tests for those limitations.
Signed-off-by: Marek Vasut
Cc: Daniel Schwierzeck
Cc: Masahiro Yamada
Cc: Peng Fan
Cc: Simon Glass
Cc: Tom Rini
---
V2: Apply 32bit check only on 64bit platforms
---
drivers/mmc/Kconfig| 1 +
drivers/mmc/renesas-sdhi.c | 77 ++
2 files changed, 78 insertions(+)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index bb38787eca..8f0df568b9 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -358,6 +358,7 @@ config RENESAS_SDHI
depends on ARCH_RMOBILE
depends on BLK && DM_MMC
depends on OF_CONTROL
+ select BOUNCE_BUFFER
help
This selects support for the Matsushita SD/MMC Host Controller on
Renesas R-Car SoCs.
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index c3b13136f8..231a78178c 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -689,12 +690,88 @@ static int renesas_sdhi_wait_dat0(struct udevice *dev,
int state,
}
#endif
+#define RENESAS_SDHI_DMA_ALIGNMENT 128
+
+static int renesas_sdhi_addr_aligned(struct bounce_buffer *state)
+{
+ uintptr_t ubuf = (uintptr_t)state->user_buffer;
+
+ /* Check if start is aligned */
+ if (!IS_ALIGNED(ubuf, RENESAS_SDHI_DMA_ALIGNMENT)) {
+ debug("Unaligned buffer address %p\n", state->user_buffer);
+ return 0;
+ }
+
+ /* Check if length is aligned */
+ if (state->len != state->len_aligned) {
+ debug("Unaligned buffer length %zu\n", state->len);
+ return 0;
+ }
+
+#ifdef CONFIG_PHYS_64BIT
+ /* Check if below 32bit boundary */
+ if ((ubuf >> 32) || (ubuf + state->len_aligned) >> 32) {
+ debug("Buffer above 32bit boundary %p-%p\n",
+ state->user_buffer,
+ state->user_buffer + state->len_aligned);
+ return 0;
+ }
+#endif
+
+ /* Aligned */
+ return 1;
+}
+
static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
+ struct bounce_buffer bbstate;
+ unsigned int bbflags;
+ bool bbok = false;
+ size_t len;
+ void *buf;
int ret;
+ if (data) {
+ if (data->flags & MMC_DATA_READ) {
+ buf = data->dest;
+ bbflags = GEN_BB_WRITE;
+ } else {
+ buf = (void *)data->src;
+ bbflags = GEN_BB_READ;
+ }
+ len = data->blocks * data->blocksize;
+
+ ret = bounce_buffer_start_extalign(, buf, len, bbflags,
+ RENESAS_SDHI_DMA_ALIGNMENT,
+ renesas_sdhi_addr_aligned);
+ /*
+* If the amount of data to transfer is too large, we can get
+* -ENOMEM when starting the bounce buffer. If that happens,
+* fall back to PIO as it was before, otherwise use the BB.
+*/
+ if (!ret) {
+ bbok = true;
+ if (data->flags & MMC_DATA_READ)
+ data->dest = bbstate.bounce_buffer;
+ else
+ data->src = bbstate.bounce_buffer;
+ }
+ }
+
ret = tmio_sd_send_cmd(dev, cmd, data);
+
+ if (data && bbok) {
+ buf = bbstate.user_buffer;
+
+ bounce_buffer_stop();
+
+ if (data->flags & MMC_DATA_READ)
+ data->dest = buf;
+ else
+ data->src = buf;
+ }
+
if (ret)
return ret;
--
2.25.1
Re: [PATCH v3] serial: ns16550: Fix ordering of getting base address
On Fri, Apr 03, 2020 at 06:35:32PM -0700, Bin Meng wrote:
> Currently the driver gets ns16550 base address in the driver
> probe() routine, which may potentially break any ns16550 wrapper
> driver that does additional initialization before calling
> ns16550_serial_probe().
>
> Things are complicated that we need consider ns16550 devices on
> both simple-bus and PCI bus. To fix the issue we move the base
> address assignment for simple-bus ns16550 device back to the
> ofdata_to_platdata(), and assign base address for PCI ns16550
> device in ns16550_serial_probe().
>
> This is still not perfect. If any PCI bus based ns16550 wrapper
> driver tries to access plat->base before calling probe(), it is
> still subject to break.
>
> Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from
> ofdata_to_platdata() to probe()")
> Reported-by: Andy Shevchenko
> Signed-off-by: Bin Meng
And re-tested. Works for me, thanks!
> Tested-by: Andy Shevchenko
> Reviewed-by: Wolfgang Wallner
> Tested-by: Wolfgang Wallner
>
> ---
>
> Changes in v3:
> - extract the base address assignment to a helper
>
> Changes in v2:
> - not to break Fixes, etc to two or more lines in the commit message
> - add the same CONFIG_SYS_NS16550_PORT_MAPPED ifdefs in the PCI case
>
> drivers/serial/ns16550.c | 39 ++-
> 1 file changed, 22 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> index c1b303f..a2f1b35 100644
> --- a/drivers/serial/ns16550.c
> +++ b/drivers/serial/ns16550.c
> @@ -479,39 +479,38 @@ static int ns16550_serial_getinfo(struct udevice *dev,
> return 0;
> }
>
> -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
> -static int ns1655_serial_set_base_addr(struct udevice *dev)
> +static int ns16550_serial_assign_base(struct ns16550_platdata *plat, ulong
> base)
> {
> - fdt_addr_t addr;
> - struct ns16550_platdata *plat;
> -
> - plat = dev_get_platdata(dev);
> -
> - addr = dev_read_addr_pci(dev);
> - if (addr == FDT_ADDR_T_NONE)
> + if (base == FDT_ADDR_T_NONE)
> return -EINVAL;
>
> #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> - plat->base = addr;
> + plat->base = base;
> #else
> - plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
> + plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE);
> #endif
>
> return 0;
> }
> -#endif
>
> int ns16550_serial_probe(struct udevice *dev)
> {
> + struct ns16550_platdata *plat = dev->platdata;
> struct NS16550 *const com_port = dev_get_priv(dev);
> struct reset_ctl_bulk reset_bulk;
> + fdt_addr_t addr;
> int ret;
>
> -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
> - ret = ns1655_serial_set_base_addr(dev);
> - if (ret)
> - return ret;
> -#endif
> + /*
> + * If we are on PCI bus, either directly attached to a PCI root port,
> + * or via a PCI bridge, assign platdata->base before probing hardware.
> + */
> + if (device_is_on_pci_bus(dev)) {
> + addr = devfdt_get_addr_pci(dev);
> + ret = ns16550_serial_assign_base(plat, addr);
> + if (ret)
> + return ret;
> + }
>
> ret = reset_get_bulk(dev, _bulk);
> if (!ret)
> @@ -535,9 +534,15 @@ int ns16550_serial_ofdata_to_platdata(struct udevice
> *dev)
> {
> struct ns16550_platdata *plat = dev->platdata;
> const u32 port_type = dev_get_driver_data(dev);
> + fdt_addr_t addr;
> struct clk clk;
> int err;
>
> + addr = dev_read_addr(dev);
> + err = ns16550_serial_assign_base(plat, addr);
> + if (err && !device_is_on_pci_bus(dev))
> + return err;
> +
> plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
> plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
> plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
> --
> 2.7.4
>
--
With Best Regards,
Andy Shevchenko
[PATCH] net: Fix warning when including netdev.h on DM systems
If the DM_ETH is enabled and netdev.h is included somewhere, the struct eth_device may not be defined, yet it is used in the header file as an argument to fecmxc_register_mii_postcall. Add forward declaration to remove the warning. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- include/netdev.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/netdev.h b/include/netdev.h index 68a3fceab6..f2d21c45d0 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -125,6 +125,7 @@ int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, /* * Allow FEC to fine-tune MII configuration on boards which require this. */ +struct eth_device; int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)); #endif -- 2.25.1
