Re: [PATCH 6/7] riscv: Remove CONFIG_IS_ENABLED(SMP) in global data

[Bin Meng]

On Sat, Apr 11, 2020 at 9:02 AM Atish Patra  wrote:
>
> On Wed, Apr 8, 2020 at 6:42 AM Bin Meng  wrote:
> >
> > Currently generic-asm-offsets.h and asm-offsets.h are generated based
> > on U-Boot proper config options. The same asm-offsets files are used
> > when building U-Boot SPL/TPL.
> >
> > But the generated macros, e.g.: GD_AVAILABLE_HARTS, create potential
> > mismatch if U-Boot proper has different config options from U-Boot
> > SPL/TPL, like in this case, SMP.
> >
> > Remove CONFIG_IS_ENABLED(SMP) in global data to get a consistent value
> > of GD_AVAILABLE_HARTS.
> >
> > Signed-off-by: Bin Meng 
> > ---
> >
> >  arch/riscv/include/asm/global_data.h | 2 --
> >  1 file changed, 2 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/global_data.h 
> > b/arch/riscv/include/asm/global_data.h
> > index 72fb4b4..dc9ba1f 100644
> > --- a/arch/riscv/include/asm/global_data.h
> > +++ b/arch/riscv/include/asm/global_data.h
> > @@ -24,9 +24,7 @@ struct arch_global_data {
> >  #ifdef CONFIG_ANDES_PLMT
> > void __iomem *plmt; /* plmt base address */
> >  #endif
> > -#if CONFIG_IS_ENABLED(SMP)
> > struct ipi_data ipi[CONFIG_NR_CPUS];
> > -#endif
> >  #ifndef CONFIG_XIP
> > ulong available_harts;
> >  #endif
>
> CONFIG_NR_CPUS is only defined for SMP/SPL_SMP. It will result in
> compilation error if somebody tries to compile non-smp u-boot.
>

Yes, I noticed when I looked at the CI testing results. Will fix in v2.

> How about moving available_harts to the top right after boot_hart?
>

Sound good to me.

Regards,
Bin

Re: [PATCH 4/7] riscv: Add SMP Kconfig option dependency for U-Boot proper

[Bin Meng]

On Sat, Apr 11, 2020 at 7:55 AM Atish Patra  wrote:
>
> On Wed, Apr 8, 2020 at 6:42 AM Bin Meng  wrote:
> >
> > U-Boot proper running in S-mode only need SMP support when using
> > SBI v0.1. With SBI v0.2 HSM extension, it does not need implement
> > multicore boot in U-Boot proper.
> >
> > Signed-off-by: Bin Meng 
> > ---
> >
> >  arch/riscv/Kconfig | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 10478ae..502143f 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -193,6 +193,7 @@ config SYS_MALLOC_F_LEN
> >
> >  config SMP
> > bool "Symmetric Multi-Processing"
> > +   depends on SBI_V01
>
> What about RISCV_MMODE ?

Yes this needs to be considered.

>
> > help
> >   This enables support for systems with more than one CPU. If
> >   you say N here, U-Boot will run on single and multiprocessor

Regards,
Bin

Re: [PATCH v2 2/3] buildman: Support fetching gcc 9.2.0

[Tom Rini]

On Mon, Apr 06, 2020 at 06:06:59AM -0700, Bin Meng wrote:

> This adds support to fetch gcc 9.2.0 toolchains.
> 
> Signed-off-by: Bin Meng 
> Reviewed-by: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 3/3] travis: Switch to gcc 9.2.0

[Tom Rini]

On Mon, Apr 06, 2020 at 06:07:00AM -0700, Bin Meng wrote:

> Use gcc 9.2.0 to do the build testing.
> 
> Signed-off-by: Bin Meng 
> Reviewed-by: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 5/5] azure/gitlab/travis: Add RISC-V SPL testing

[Tom Rini]

On Sat, Mar 28, 2020 at 07:25:29AM -0700, Bin Meng wrote:

> This adds QEMU RISC-V 32/64 SPL testing. Unlike QEMU RISC-V 32/64,
> we test SPL running in M-mode and U-Boot proper running in S-mode,
> with a 4-core SMP configuration.
> 
> Signed-off-by: Bin Meng 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 1/3] video: sunxi: Change sunxi_get_mon_desc() to not return NULL for the default case

[Tom Rini]

On Mon, Apr 06, 2020 at 06:06:58AM -0700, Bin Meng wrote:

> When building with gcc 9.2.0, the following build warning was seen:
> 
>   drivers/video/sunxi/sunxi_display.c: In function 'video_hw_init':
>   drivers/video/sunxi/sunxi_display.c:1217:2:
> error: '%s' directive argument is null [-Werror=format-overflow=]
> 
> Change sunxi_get_mon_desc() to not return NULL for the default case,
> to fix the compiler warning.
> 
> Signed-off-by: Bin Meng 
> Reviewed-by: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 1/5] travis: Replace pre-built ARM/ARM64 GRUB images with the one built from source

[Tom Rini]

On Sat, Mar 28, 2020 at 07:25:25AM -0700, Bin Meng wrote:

> As of today travis uses the pre-built GRUB ARM/ARM64 images from
> opensuse. But azure/gitlab are using images built from GRUB 2.04
> source. This updates travis to build GRUB ARM/ARM64 UEFI targets
> from source, to keep in sync with azure/gitlab.
> 
> Signed-off-by: Bin Meng 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 4/5] test/py: Update u_boot_utils.find_ram_base to bypass the low 2MiB memory

[Tom Rini]

On Sat, Mar 28, 2020 at 07:25:28AM -0700, Bin Meng wrote:

> On some RISC-V targets the low memory is protected that prevents
> S-mode U-Boot from access.
> 
> Signed-off-by: Bin Meng 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 3/5] azure/gitlab/travis: Add qemu-riscv32 testing

[Tom Rini]

On Sat, Mar 28, 2020 at 07:25:27AM -0700, Bin Meng wrote:

> This adds the qemu-riscv32_defconfig test configuration.
> 
> Signed-off-by: Bin Meng 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 2/5] travis: Build GRUB image for RISC-V 32-bit and 64-bit

[Tom Rini]

On Sat, Mar 28, 2020 at 07:25:26AM -0700, Bin Meng wrote:

> This adds the GRUB image build for RISC-V 32-bit and 64-bit.
> 
> Signed-off-by: Bin Meng 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 6/7] riscv: Remove CONFIG_IS_ENABLED(SMP) in global data

[Atish Patra]

On Wed, Apr 8, 2020 at 6:42 AM Bin Meng  wrote:
>
> Currently generic-asm-offsets.h and asm-offsets.h are generated based
> on U-Boot proper config options. The same asm-offsets files are used
> when building U-Boot SPL/TPL.
>
> But the generated macros, e.g.: GD_AVAILABLE_HARTS, create potential
> mismatch if U-Boot proper has different config options from U-Boot
> SPL/TPL, like in this case, SMP.
>
> Remove CONFIG_IS_ENABLED(SMP) in global data to get a consistent value
> of GD_AVAILABLE_HARTS.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/riscv/include/asm/global_data.h | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/global_data.h 
> b/arch/riscv/include/asm/global_data.h
> index 72fb4b4..dc9ba1f 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -24,9 +24,7 @@ struct arch_global_data {
>  #ifdef CONFIG_ANDES_PLMT
> void __iomem *plmt; /* plmt base address */
>  #endif
> -#if CONFIG_IS_ENABLED(SMP)
> struct ipi_data ipi[CONFIG_NR_CPUS];
> -#endif
>  #ifndef CONFIG_XIP
> ulong available_harts;
>  #endif

CONFIG_NR_CPUS is only defined for SMP/SPL_SMP. It will result in
compilation error if somebody tries to compile non-smp u-boot.

How about moving available_harts to the top right after boot_hart?

> --
> 2.7.4
>


--
Regards,
Atish

Re: [PATCH 3/7] riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL

[Atish Patra]

On Wed, Apr 8, 2020 at 6:42 AM Bin Meng  wrote:
>
> With SBI v0.2 HSM extension, only a single hart need to boot and
> enter operating system. The booting hart can bring up secondary
> harts one by one afterwards.
>
> For U-Boot running in SPL, SMP can be turned on, while in U-Boot
> proper, SMP can be optionally turned off if using SBI v0.2 HSM.
>
> Introduce a new SPL_SMP Kconfig option to support this.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/riscv/Kconfig   | 13 -
>  arch/riscv/cpu/start.S   | 14 +++---
>  arch/riscv/include/asm/global_data.h |  2 +-
>  arch/riscv/lib/Makefile  |  2 +-
>  arch/riscv/lib/spl.c |  2 +-
>  common/spl/spl_opensbi.c |  2 +-
>  6 files changed, 23 insertions(+), 12 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index cc87da7..10478ae 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -200,10 +200,21 @@ config SMP
>   machine. If you say Y here, U-Boot will run on many, but not
>   all, single processor machines.
>
> +config SPL_SMP
> +   bool "Symmetric Multi-Processing in SPL"
> +   depends on SPL && SPL_RISCV_MMODE
> +   default y
> +   help
> + This enables support for systems with more than one CPU in SPL.
> + If you say N here, U-Boot SPL will run on single and multiprocessor
> + machines, but will use only one CPU of a multiprocessor
> + machine. If you say Y here, U-Boot SPL will run on many, but not
> + all, single processor machines.
> +
>  config NR_CPUS
> int "Maximum number of CPUs (2-32)"
> range 2 32
> -   depends on SMP
> +   depends on SMP || SPL_SMP
> default 8
> help
>   On multiprocessor machines, U-Boot sets up a stack for each CPU.
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index ecf0482..fce0982 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -53,7 +53,7 @@ _start:
> /* mask all interrupts */
> csrwMODE_PREFIX(ie), zero
>
> -#ifdef CONFIG_SMP
> +#if CONFIG_IS_ENABLED(SMP)
> /* check if hart is within range */
> /* tp: hart id */
> li  t0, CONFIG_NR_CPUS
> @@ -91,7 +91,7 @@ call_board_init_f_0:
> mv  gp, a0
>
> /* setup stack */
> -#ifdef CONFIG_SMP
> +#if CONFIG_IS_ENABLED(SMP)
> /* tp: hart id */
> sllit0, tp, CONFIG_STACK_SIZE_SHIFT
> sub sp, a0, t0
> @@ -182,7 +182,7 @@ spl_stack_gd_setup:
> mv  s0, a0
>
> /* setup stack on main hart */
> -#ifdef CONFIG_SMP
> +#if CONFIG_IS_ENABLED(SMP)
> /* tp: hart id */
> sllit0, tp, CONFIG_STACK_SIZE_SHIFT
> sub sp, s0, t0
> @@ -231,7 +231,7 @@ relocate_code:
>   *Set up the stack
>   */
>  stack_setup:
> -#ifdef CONFIG_SMP
> +#if CONFIG_IS_ENABLED(SMP)
> /* tp: hart id */
> sllit0, tp, CONFIG_STACK_SIZE_SHIFT
> sub sp, s2, t0
> @@ -326,7 +326,7 @@ clbss_l:
> blt t0, t1, clbss_l
>
>  relocate_secondary_harts:
> -#ifdef CONFIG_SMP
> +#if CONFIG_IS_ENABLED(SMP)
> /* send relocation IPI */
> la  t0, secondary_hart_relocate
> add a0, t0, t6
> @@ -370,7 +370,7 @@ call_board_init_r:
>   */
> jr  t4  /* jump to board_init_r() */
>
> -#ifdef CONFIG_SMP
> +#if CONFIG_IS_ENABLED(SMP)
>  hart_out_of_bounds_loop:
> /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
> wfi
> @@ -393,7 +393,7 @@ secondary_hart_relocate:
>  secondary_hart_loop:
> wfi
>
> -#ifdef CONFIG_SMP
> +#if CONFIG_IS_ENABLED(SMP)
> csrrt0, MODE_PREFIX(ip)
>  #if CONFIG_IS_ENABLED(RISCV_MMODE)
> andit0, t0, MIE_MSIE
> diff --git a/arch/riscv/include/asm/global_data.h 
> b/arch/riscv/include/asm/global_data.h
> index b74bd7e..72fb4b4 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -24,7 +24,7 @@ struct arch_global_data {
>  #ifdef CONFIG_ANDES_PLMT
> void __iomem *plmt; /* plmt base address */
>  #endif
> -#ifdef CONFIG_SMP
> +#if CONFIG_IS_ENABLED(SMP)
> struct ipi_data ipi[CONFIG_NR_CPUS];
>  #endif
>  #ifndef CONFIG_XIP
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index adadbf4..bd7b2c4 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -22,7 +22,7 @@ endif
>  obj-y  += interrupts.o
>  obj-y  += reset.o
>  obj-y   += setjmp.o
> -obj-$(CONFIG_SMP) += smp.o
> +obj-$(CONFIG_$(SPL_)SMP) += smp.o
>  obj-$(CONFIG_SPL_BUILD)+= spl.o
>
>  # For building EFI apps
> diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
> index ae07bbe..4ca038b 100644
> --- a/arch/riscv/lib/spl.c
> +++ b/arch/riscv/lib/spl.c
> @@ -41,7 +41,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info 
> *spl_image)
> 

Re: [PATCH 5/5] riscv: Implement new SBI v0.2 extensions

[Atish Patra]

On Mon, Mar 9, 2020 at 7:36 PM Bin Meng  wrote:
>
> Few v0.1 SBI calls are being replaced by new SBI calls that follows
> v0.2 calling convention.
>
> Implement the replacement extensions and few additional new SBI
> function calls that makes way for a better SBI interface in future.
>
> Signed-off-by: Bin Meng 
>
> ---
>
>  arch/riscv/include/asm/sbi.h | 24 
>  arch/riscv/lib/sbi.c | 16 +---
>  2 files changed, 33 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index c65104f..3595ee8 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -53,6 +53,30 @@ enum sbi_ext_rfence_fid {
> SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
>  };
>
> +#ifdef CONFIG_SBI_V01
> +#define SBI_EXT_SET_TIMER  SBI_EXT_0_1_SET_TIMER
> +#define SBI_FID_SET_TIMER  0
> +#define SBI_EXT_SEND_IPI   SBI_EXT_0_1_SEND_IPI
> +#define SBI_FID_SEND_IPI   0
> +#define SBI_EXT_REMOTE_FENCE_I SBI_EXT_0_1_REMOTE_FENCE_I
> +#define SBI_FID_REMOTE_FENCE_I 0
> +#define SBI_EXT_REMOTE_SFENCE_VMA  SBI_EXT_0_1_REMOTE_SFENCE_VMA
> +#define SBI_FID_REMOTE_SFENCE_VMA  0
> +#define SBI_EXT_REMOTE_SFENCE_VMA_ASID SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID
> +#define SBI_FID_REMOTE_SFENCE_VMA_ASID 0
> +#else
> +#define SBI_EXT_SET_TIMER  SBI_EXT_TIME
> +#define SBI_FID_SET_TIMER  SBI_EXT_TIME_SET_TIMER
> +#define SBI_EXT_SEND_IPI   SBI_EXT_IPI
> +#define SBI_FID_SEND_IPI   SBI_EXT_IPI_SEND_IPI
> +#define SBI_EXT_REMOTE_FENCE_I SBI_EXT_RFENCE
> +#define SBI_FID_REMOTE_FENCE_I SBI_EXT_RFENCE_REMOTE_FENCE_I
> +#define SBI_EXT_REMOTE_SFENCE_VMA  SBI_EXT_RFENCE
> +#define SBI_FID_REMOTE_SFENCE_VMA  SBI_EXT_RFENCE_REMOTE_SFENCE_VMA
> +#define SBI_EXT_REMOTE_SFENCE_VMA_ASID SBI_EXT_RFENCE
> +#define SBI_FID_REMOTE_SFENCE_VMA_ASID SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID
> +#endif
> +
>  #define SBI_SPEC_VERSION_DEFAULT   0x1
>  #define SBI_SPEC_VERSION_MAJOR_SHIFT   24
>  #define SBI_SPEC_VERSION_MAJOR_MASK0x7f
> diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
> index 604a3a8..7bdf071 100644
> --- a/arch/riscv/lib/sbi.c
> +++ b/arch/riscv/lib/sbi.c
> @@ -97,10 +97,11 @@ void sbi_shutdown(void)
>  void sbi_set_timer(uint64_t stime_value)
>  {
>  #if __riscv_xlen == 32
> -   sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
> +   sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value,
>   stime_value >> 32, 0, 0, 0, 0);
>  #else
> -   sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
> +   sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value,
> + 0, 0, 0, 0, 0);
>  #endif
>  }
>
> @@ -112,7 +113,7 @@ void sbi_set_timer(uint64_t stime_value)
>   */
>  void sbi_send_ipi(const unsigned long *hart_mask)
>  {
> -   sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
> +   sbi_ecall(SBI_EXT_SEND_IPI, SBI_FID_SEND_IPI, (unsigned 
> long)hart_mask,
>   0, 0, 0, 0, 0);
>  }
>
> @@ -124,8 +125,8 @@ void sbi_send_ipi(const unsigned long *hart_mask)
>   */
>  void sbi_remote_fence_i(const unsigned long *hart_mask)
>  {
> -   sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
> - 0, 0, 0, 0, 0);
> +   sbi_ecall(SBI_EXT_REMOTE_FENCE_I, SBI_FID_REMOTE_FENCE_I,
> + (unsigned long)hart_mask, 0, 0, 0, 0, 0);
>  }
>
>  /**
> @@ -141,7 +142,7 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask,
>unsigned long start,
>unsigned long size)
>  {
> -   sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> +   sbi_ecall(SBI_EXT_REMOTE_SFENCE_VMA, SBI_FID_REMOTE_SFENCE_VMA,
>   (unsigned long)hart_mask, start, size, 0, 0, 0);
>  }
>
> @@ -161,7 +162,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long 
> *hart_mask,
> unsigned long size,
> unsigned long asid)
>  {
> -   sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> +   sbi_ecall(SBI_EXT_REMOTE_SFENCE_VMA_ASID,
> + SBI_FID_REMOTE_SFENCE_VMA_ASID,
>   (unsigned long)hart_mask, start, size, asid, 0, 0);
>  }
>
This is incorrect. IPI and SFENCE extension in SBI v0.2 accepts hart
mask as a value compared to a pointer to virtual address in SBI v0.1.
Maybe we should move this code to SBI_V01 given that SMP will be
enabled only for M-mode or  SBI_V01 as per your latest patch ?

> --
> 2.7.4
>


-- 
Regards,
Atish

Re: [PATCH 7/7] riscv: Make SBI v0.2 the default SBI version

[Atish Patra]

On Wed, Apr 8, 2020 at 6:42 AM Bin Meng  wrote:
>
> To work with latest OpenSBI release (v0.7 or above) that has the HSM
> extension support, select the SBI v0.2 support by default.
>

Just for clarification: OpenSBI v0.7 will be available soon after
Linux kernel 5.-7-rc1 is available.

> Signed-off-by: Bin Meng 
>
> ---
>
>  arch/riscv/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index ae801d3..9bdaf2d 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -228,7 +228,7 @@ config SBI
>
>  choice
> prompt "SBI support"
> -   default SBI_V01
> +   default SBI_V02
>
>  config SBI_V01
> bool "SBI v0.1 support"
> --
> 2.7.4
>

Reviewed-by: Atish Patra 
-- 
Regards,
Atish

Re: [PATCH 4/7] riscv: Add SMP Kconfig option dependency for U-Boot proper

[Atish Patra]

On Wed, Apr 8, 2020 at 6:42 AM Bin Meng  wrote:
>
> U-Boot proper running in S-mode only need SMP support when using
> SBI v0.1. With SBI v0.2 HSM extension, it does not need implement
> multicore boot in U-Boot proper.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/riscv/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 10478ae..502143f 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -193,6 +193,7 @@ config SYS_MALLOC_F_LEN
>
>  config SMP
> bool "Symmetric Multi-Processing"
> +   depends on SBI_V01

What about RISCV_MMODE ?

> help
>   This enables support for systems with more than one CPU. If
>   you say N here, U-Boot will run on single and multiprocessor
> --
> 2.7.4
>


-- 
Regards,
Atish

Re: [PATCH 5/7] riscv: Add Kconfig option for SBI v0.2

[Atish Patra]

On Wed, Apr 8, 2020 at 6:42 AM Bin Meng  wrote:
>
> SBI v0.2 is more scalable and extendable to handle future needs
> for RISC-V supervisor interfaces. For example, with SBI v0.2 HSM
> extension, only a single hart need to boot and enter operating
> system. The booting hart can bring up secondary harts one by one
> afterwards.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/riscv/Kconfig | 20 +++-
>  1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 502143f..ae801d3 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -226,14 +226,32 @@ config SBI
> bool
> default y if RISCV_SMODE || SPL_RISCV_SMODE
>
> +choice
> +   prompt "SBI support"
> +   default SBI_V01
> +
>  config SBI_V01
> bool "SBI v0.1 support"
> -   default y
> depends on SBI
> help
>   This config allows kernel to use SBI v0.1 APIs. This will be
>   deprecated in future once legacy M-mode software are no longer in 
> use.
>
> +config SBI_V02
> +   bool "SBI v0.2 support"
> +   depends on SBI
> +   help
> + This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
> + scalable and extendable to handle future needs for RISC-V supervisor
> + interfaces. For example, with SBI v0.2 HSM extension, only a single
> + hart need to boot and enter operating system. The booting hart can
> + bring up secondary harts one by one afterwards.
> +
> + Choose this option if OpenSBI v0.7 or above release is used together
> + with U-Boot.
> +
> +endchoice
> +
>  config SBI_IPI
> bool
> depends on SBI
> --
> 2.7.4
>

Reviewed-by: Atish Patra 

-- 
Regards,
Atish

Re: [PATCH 2/7] riscv: Merge unnecessary SMP ifdefs in start.S

[Atish Patra]

On Wed, Apr 8, 2020 at 6:41 AM Bin Meng  wrote:
>
> Two consecutive SMP ifdefs blocks can be combined into one.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/riscv/cpu/start.S | 4 
>  1 file changed, 4 deletions(-)
>
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index 6b3ff99..ecf0482 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -58,9 +58,7 @@ _start:
> /* tp: hart id */
> li  t0, CONFIG_NR_CPUS
> bge tp, t0, hart_out_of_bounds_loop
> -#endif
>
> -#ifdef CONFIG_SMP
> /* set xSIE bit to receive IPIs */
>  #if CONFIG_IS_ENABLED(RISCV_MMODE)
> li  t0, MIE_MSIE
> @@ -377,9 +375,7 @@ hart_out_of_bounds_loop:
> /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
> wfi
> j   hart_out_of_bounds_loop
> -#endif
>
> -#ifdef CONFIG_SMP
>  /* SMP relocation entry */
>  secondary_hart_relocate:
> /* a1: new sp */
> --
> 2.7.4
>

Reviewed-by: Atish Patra 

-- 
Regards,
Atish

[PATCH] Azure/GitLab: Switch over to using LLVM-10

[Tom Rini]

At this point LLVM-7 is rather old.  Switch over to LLVM-10 to enable
some amount of CI coverage with newer compilers.

Signed-off-by: Tom Rini 
---
 .azure-pipelines.yml | 2 +-
 .gitlab-ci.yml   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 192c7ef5fe6d..d4a79c6dd0a9 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -163,7 +163,7 @@ jobs:
 sandbox_clang:
   TEST_PY_BD: "sandbox"
   BUILDMAN: "^sandbox$"
-  OVERRIDE: "-O clang-7"
+  OVERRIDE: "-O clang-10"
 sandbox_spl:
   TEST_PY_BD: "sandbox_spl"
   TEST_PY_TEST_SPEC: "test_ofplatdata"
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index ae158aa17c1b..4b615eb40cc9 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -190,7 +190,7 @@ sandbox with clang test.py:
   variables:
 TEST_PY_BD: "sandbox"
 BUILDMAN: "^sandbox$"
-OVERRIDE: "-O clang-7"
+OVERRIDE: "-O clang-10"
   <<: *buildman_and_testpy_dfn
 
 sandbox_spl test.py:
-- 
2.17.1

[PATCH] Dockerfile: Switch over to using LLVM-10

[Tom Rini]

At this point LLVM-7 is rather old.  Switch over to LLVM-10 to enable
some amount of CI coverage with newer compilers.

Signed-off-by: Tom Rini 
---
 Dockerfile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Dockerfile b/Dockerfile
index e9e5aa3c3905..daf896f5c466 100644
--- a/Dockerfile
+++ b/Dockerfile
@@ -12,7 +12,7 @@ ENV DEBIAN_FRONTEND=noninteractive
 # Add LLVM repository
 RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf 
/var/lib/apt/lists/*
 RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add -
-RUN echo deb http://apt.llvm.org/bionic/ llvm-toolchain-bionic-7 main | tee 
/etc/apt/sources.list.d/llvm.list
+RUN echo deb http://apt.llvm.org/bionic/ llvm-toolchain-bionic-10 main | tee 
/etc/apt/sources.list.d/llvm.list
 
 # Manually install the kernel.org "Crosstool" based toolchains for gcc-7.3
 RUN wget -O - 
https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/x86_64-gcc-9.2.0-nolibc-aarch64-linux.tar.xz
 | tar -C /opt -xJ
@@ -39,7 +39,7 @@ RUN apt-get update && apt-get install -y \
bc \
bison \
build-essential \
-   clang-7 \
+   clang-10 \
coreutils \
cpio \
cppcheck \
-- 
2.17.1

Re: [PATCH 1/3] Dockerfile: Install riscv32 toolchain from kernel.org

[Tom Rini]

On Thu, Mar 26, 2020 at 09:04:52AM -0700, Bin Meng wrote:

> This is required to build GRUB UEFI target for RISC-V 32-bit.
> 
> Signed-off-by: Bin Meng 

Applied to gitlab-ci-runner/master, thanks!

-- 
Tom


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Description: PGP signature

Re: [PATCH 2/3] Dockerfile: Build GRUB UEFI target for RISC-V 32-bit

[Tom Rini]

On Thu, Mar 26, 2020 at 09:04:53AM -0700, Bin Meng wrote:

> Build GRUB UEFI target grubriscv32.efi.
> 
> Signed-off-by: Bin Meng 

Applied to gitlab-ci-runner/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature

Re: [PATCH] Dockerfile: Switch to gcc 9.2.0

[Tom Rini]

On Mon, Apr 06, 2020 at 05:33:00AM -0700, Bin Meng wrote:

> Use gcc 9.2.0 to do the build testing.
> 
> Signed-off-by: Bin Meng 

Applied to gitlab-ci-runner/master, thanks!

-- 
Tom


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Description: PGP signature

Re: [PATCH 3/3] Dockerfile: Build QEMU for RISC-V 32-bit

[Tom Rini]

On Thu, Mar 26, 2020 at 09:04:54AM -0700, Bin Meng wrote:

> Build qemu-system-riscv32 executable for U-Boot testing.
> 
> Signed-off-by: Bin Meng 

Applied to gitlab-ci-runner/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature

Re: [PATCH] tiny-printf: Support %i

[Marek Vasut]

On 4/10/20 10:47 PM, Simon Glass wrote:
> Hi Marek,
> 
> On Fri, 10 Apr 2020 at 12:54, Marek Vasut  wrote:
>>
>> The most basic printf("%i", value) formating string was missing,
>> add it for the sake of convenience.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Simon Glass 
>> Cc: Stefan Roese 
>> ---
>>  lib/tiny-printf.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> Can you add to the test in print_ut.c?

Sure, is that a hard-requirement for such a minor patch ?
Is there an example for the other %u / %d variants ?

Re: [PATCH] tiny-printf: Support %i

[Simon Glass]

Hi Marek,

On Fri, 10 Apr 2020 at 12:54, Marek Vasut  wrote:
>
> The most basic printf("%i", value) formating string was missing,
> add it for the sake of convenience.
>
> Signed-off-by: Marek Vasut 
> Cc: Simon Glass 
> Cc: Stefan Roese 
> ---
>  lib/tiny-printf.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Can you add to the test in print_ut.c?

Regards,
Simon

Re: [PATCH 2/3] README: remove references on no more used config CONFIG_SYS_RCAR_I2C*

[Simon Glass]

On Fri, 10 Apr 2020 at 08:34, Patrick Delaunay  wrote:
>
> Remove the references in README on CONFIG_SYS_RCAR_I2C_* not use
> in U-Boot drivers/i2c/rcar_i2c.c, since commit a4d9aafadb31 ("i2c:
>  rcar_i2c: Remove the driver") and commit a06a0ac36d59 ("i2c: rcar_i2c:
>  Add DM and DT capable I2C driver")
>
> Checked by the command: grep -r SYS_RCAR_I2C *
> And these CONFIG are only defined in
> arch/arm/mach-rmobile/include/mach/rcar-base.h
>
> Signed-off-by: Patrick Delaunay 
> ---
>
>  README | 10 --
>  1 file changed, 10 deletions(-)

Reviewed-by: Simon Glass 

Nice clean-up.

Re: [PATCH 1/3] cosmetic: README: Fix one CONFIG name

[Simon Glass]

On Fri, 10 Apr 2020 at 08:34, Patrick Delaunay  wrote:
>
> Only replace CONFIF_ by CONFIG_
>
> Signed-off-by: Patrick Delaunay 
> ---
>
>  README | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Simon Glass 

Please pull u-boot/next

[Simon Glass]

Hi Tom,

The following changes since commit 587e4a4296982f85b2a40fc8a704db65079e0aac:

  kconfig / kbuild: Re-sync with Linux 4.19 (2020-04-10 11:18:32 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-dm.git tags/dm-next-pull-10apr20

for you to fetch changes up to f7553b0e808f38d6303445661db062b74e865de9:

  dm: core: Read parent ofdata before children (2020-04-10 13:11:10 -0600)


Functions for reading indexed values from device tree
Enhancements to 'dm' command
Log test enhancements and syslog driver
DM change to read parent ofdata before children
Minor fixes


Dario Binacchi (3):
  dm: test: add test case for dev_read_u64 function
  dm: core: support reading a single indexed u32 value
  dm: core: refactor functions reading an u32 from dt

Heinrich Schuchardt (12):
  dm: core: remove redundant if statement
  dm: core: remove redundant assignment
  log: correct CONFIG_LOG_TEST prerequisites
  log: syslog driver
  log: output for CONFIG_LOG=n
  test: log functions with CONFIG_LOG=n
  test: log: test syslog logging driver
  configs: sandbox: enable LOG_SYSLOG
  doc: driver-model: there is no UCLASS_ETHERNET
  sandbox: add reserved-memory node in device tree
  sandbox: implement ft_board_setup()
  sandbox: enable CMD_BOOTEFI_HELLO and CMD_EFIDEBUG

Laurentiu Tudor (2):
  fdtdec: support multiple phandles in memory carveout
  test: fdtdec: test fdtdec_set_carveout()

Michael Walle (1):
  dm: uclass: don't assign aliased seq numbers

Ovidiu Panait (2):
  dm: dump.c: Fix segfault when entry->of_match is NULL
  dm: dump.c: Refactor dm_dump_drivers prints

Patrick Delaunay (2):
  dm: core: Move "/chosen" and "/firmware" node scan
  dm: core: remove the duplicated function dm_ofnode_pre_reloc

Rasmus Villemoes (1):
  sandbox: also restore terminal settings when killed by SIGINT

Sean Anderson (1):
  serial: Set baudrate on boot

Simon Glass (5):
  sandbox: p2sb: Silence compiler warning
  patman: Apply the cc limit to the cover letter also
  dm: core: Add logging on unbind failure
  dm: core: Add a way to skip powering down power domains
  dm: core: Read parent ofdata before children

Tom Rini (1):
  sandbox: Update PCI nodes in dts files

Tom Warren (1):
  fdt: Fix 'system' command

 MAINTAINERS|   4 +-
 arch/Kconfig   |   1 +
 arch/sandbox/cpu/os.c  |   9 ++
 arch/sandbox/dts/sandbox.dts   |  24 +++-
 arch/sandbox/dts/sandbox.dtsi  |   2 +-
 arch/sandbox/dts/sandbox64.dts |  25 -
 arch/sandbox/dts/test.dts  |  15 ++-
 board/sandbox/sandbox.c|   6 +
 cmd/fdt.c  |   2 +-
 common/Kconfig |   9 +-
 common/Makefile|   1 +
 common/log_syslog.c| 117 
 configs/sandbox64_defconfig|   3 +
 configs/sandbox_defconfig  |   2 +
 configs/sandbox_flattree_defconfig |   3 +
 configs/sandbox_spl_defconfig  |   2 +
 doc/README.log |   3 +
 doc/driver-model/design.rst|  96 +++-
 doc/driver-model/pci-info.rst  |  10 +-
 drivers/clk/altera/clk-arria10.c   |   2 +-
 drivers/clk/at91/pmc.c |   2 +-
 drivers/core/device-remove.c   |  23 ++--
 drivers/core/device.c  |  22 +++-
 drivers/core/dump.c|  17 ++-
 drivers/core/lists.c   |   2 +-
 drivers/core/of_access.c   |  40 ---
 drivers/core/ofnode.c  |  49 ++---
 drivers/core/read.c|  13 +++
 drivers/core/root.c|  52 +++--
 drivers/core/uclass.c  |  28 +++--
 drivers/core/util.c|  28 -
 drivers/misc/p2sb_emul.c   |   2 +-
 drivers/serial/serial-uclass.c |   1 +
 include/configs/sandbox.h  |   6 +-
 include/dm/device.h|  11 +-
 include/dm/of_access.h |  19 
 include/dm/ofnode.h|  25 +
 include/dm/read.h  |  40 +++
 include/dm/util.h  |  27 -
 include/log.h  |  10 +-
 include/test/log.h |  16 +++
 include/test/suites.h  |   1 +
 include/test/ut.h  |  16 +++
 lib/fdtdec.c   |  36 --
 test/Kconfig   |   9 ++
 test/Makefile  |   2 +-
 test/cmd_ut.c  |   6 +
 test/dm/Makefile   |   1 +
 test/dm/eth.c  |  14 +--
 test/dm/fdtdec.c   |  59 ++
 test/dm/test-fdt.c |  88 ++-
 test/log/Makefile  |  14 +++
 test/log/nolog_test.c  | 135 

Re: [PATCH 5/8] xhci: mediatek: Add support for MTK xHCI host controller

[Marek Vasut]

On 4/10/20 9:14 PM, Simon Glass wrote:
> Hi Marek,

Hi,

> On Fri, 10 Apr 2020 at 12:45, Marek Vasut  wrote:
>>
>> On 3/31/20 6:05 PM, Marek Vasut wrote:
>>> On 3/31/20 4:16 PM, Simon Glass wrote:
 HI Marek,
>>>
>>> Hi,
>>>
>>> [...]
>>>
 OK I have updated the coding style page with all of this.
>>>
>>> Which page ?
>>
>> https://www.denx.de/wiki/U-Boot/CodingStyle
>
> " U-Boot typically uses a C structure to map out the registers in an I/O
> region, rather than offsets. The reasons for this are: " is misleading
> and suggests that using structures is the best practice. This should be
> reworded to make it clear both options are equally valid.

 I'd like to see a preference to use struct where it makes sense and
 not use it when it doesn't, with the different tradeoffs clearly
 written. Are asking that we say nothing about which is better in each
 situation?
>>>
>>> Correct, because I don't see a clear agreement on which one is better
>>> and should be preferred.
>>
>> I see the wiki has still not been correctly reworded, can you please
>> repair it ?
> 
> What sort of 'repairs' are you thinking of?

"
 This may need to change to the kernel model if we allow for more
run-time detection of what drivers are appropriate for what we're
running on.
"

This was removed. I believe this is quite important to leave there.

> I did add your counterpoints but did not change the text in the first
> part, which has been long-standing. I think to do that we really would
> need a wider discussion than just the two of us, particularly as we
> seem not to agree on the 'default' position.

ACK.

Re: Please pull u-boot-dm

[Tom Rini]

On Fri, Apr 10, 2020 at 07:57:21AM -0600, Simon Glass wrote:

> Hi Tom,
> 
> (final?) fixes for DM
> 
> The following changes since commit dfd5321becc54d7ce9fd564aaaba70a2132c058e:
> 
>   Merge tag 'u-boot-imx-20200408' of
> https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-04-08
> 12:06:39 -0400)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-dm.git tags/dm-pull9apr20
> 
> for you to fetch changes up to 2ca38ecc1c427d41db92c624cbf6d343df74:
> 
>   dm: dump.c: Refactor dm_dump_drivers prints (2020-04-09 15:12:34 -0600)
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature

Re: [PATCH 5/8] xhci: mediatek: Add support for MTK xHCI host controller

[Simon Glass]

Hi Marek,

On Fri, 10 Apr 2020 at 12:45, Marek Vasut  wrote:
>
> On 3/31/20 6:05 PM, Marek Vasut wrote:
> > On 3/31/20 4:16 PM, Simon Glass wrote:
> >> HI Marek,
> >
> > Hi,
> >
> > [...]
> >
> >> OK I have updated the coding style page with all of this.
> >
> > Which page ?
> 
>  https://www.denx.de/wiki/U-Boot/CodingStyle
> >>>
> >>> " U-Boot typically uses a C structure to map out the registers in an I/O
> >>> region, rather than offsets. The reasons for this are: " is misleading
> >>> and suggests that using structures is the best practice. This should be
> >>> reworded to make it clear both options are equally valid.
> >>
> >> I'd like to see a preference to use struct where it makes sense and
> >> not use it when it doesn't, with the different tradeoffs clearly
> >> written. Are asking that we say nothing about which is better in each
> >> situation?
> >
> > Correct, because I don't see a clear agreement on which one is better
> > and should be preferred.
>
> I see the wiki has still not been correctly reworded, can you please
> repair it ?

What sort of 'repairs' are you thinking of?

I did add your counterpoints but did not change the text in the first
part, which has been long-standing. I think to do that we really would
need a wider discussion than just the two of us, particularly as we
seem not to agree on the 'default' position.

Regards,
Simon

[PATCH V2 6/6] ARM: stm32: Implement DDR3 coding on DHCOR SoM

[Marek Vasut]

The DHCOR board does exist in multiple variants with different DDR3
DRAM sizes. To cater for all of them, implement DDR3 code handling.
There are two GPIOs which code the DRAM size populated on the SoM,
read them out and use the value to pick the correct DDR3 config.

Signed-off-by: Marek Vasut 
Cc: Manivannan Sadhasivam 
Cc: Patrick Delaunay 
Cc: Patrice Chotard 
---
V2: Match on compatible string
---
 arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi |  2 ++
 arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi |  2 ++
 board/dhelectronics/dh_stm32mp1/board.c| 26 +-
 configs/stm32mp15_dhcom_basic_defconfig|  1 +
 configs/stm32mp15_dhcor_basic_defconfig|  1 +
 5 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi 
b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index fcdc5e6859..54416acd5c 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -5,6 +5,7 @@
 
 #include 
 #include "stm32mp157-u-boot.dtsi"
+#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
 
 / {
@@ -26,6 +27,7 @@
st,stm32prog-gpios = < 14 GPIO_ACTIVE_LOW>;
#gpio-cells = <2>;
dh,som-coding-gpios = < 12 0>, < 13 0>, < 15 
0>;
+   dh,ddr3-coding-gpios = < 6 0>, < 7 0>;
};
 
led {
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi 
b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index 17a23ae21c..6db4ac37e1 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -9,6 +9,7 @@
 
 #include 
 #include "stm32mp157-u-boot.dtsi"
+#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
 
 / {
@@ -16,6 +17,7 @@
config {
u-boot,dm-pre-reloc;
#gpio-cells = <2>;
+   dh,ddr3-coding-gpios = < 0 0>, < 1 0>;
dh,som-coding-gpios = < 7 0>, < 3 0>;
};
 };
diff --git a/board/dhelectronics/dh_stm32mp1/board.c 
b/board/dhelectronics/dh_stm32mp1/board.c
index b72d113a6f..07a2bab10c 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -135,6 +135,7 @@ int checkboard(void)
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 static u8 brdcode __section("data");
+static u8 ddr3code __section("data");
 static u8 somcode __section("data");
 
 static void board_get_coding_straps(void)
@@ -150,6 +151,7 @@ static void board_get_coding_straps(void)
}
 
brdcode = 0;
+   ddr3code = 0;
somcode = 0;
 
ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
@@ -158,13 +160,34 @@ static void board_get_coding_straps(void)
for (i = 0; i < ret; i++)
somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
 
+   ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
+ gpio, ARRAY_SIZE(gpio),
+ GPIOD_IS_IN);
+   for (i = 0; i < ret; i++)
+   ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
+
ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
  gpio, ARRAY_SIZE(gpio),
  GPIOD_IS_IN);
for (i = 0; i < ret; i++)
brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
 
-   printf("Code:  SoM:rev=%d Board:rev=%d\n", somcode, brdcode);
+   printf("Code:  SoM:rev=%d,ddr3=%d Board:rev=%d\n",
+   somcode, ddr3code, brdcode);
+}
+
+int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
+const char *name)
+{
+   if (ddr3code == 2 &&
+   !strcmp(name, "st,ddr3-1066-888-bin-g-1x4gb-533mhz"))
+   return 0;
+
+   if (ddr3code == 3 &&
+   !strcmp(name, "st,ddr3-1066-888-bin-g-2x4gb-533mhz"))
+   return 0;
+
+   return -EINVAL;
 }
 
 int board_early_init_f(void)
@@ -537,6 +560,7 @@ int board_late_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
env_set_ulong("dh_som_rev", somcode);
env_set_ulong("dh_board_rev", brdcode);
+   env_set_ulong("dh_ddr3_code", ddr3code);
 #endif
 
return 0;
diff --git a/configs/stm32mp15_dhcom_basic_defconfig 
b/configs/stm32mp15_dhcom_basic_defconfig
index 81222ce444..415bb7111b 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -14,6 +14,7 @@ CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its"
 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
diff --git a/configs/stm32mp15_dhcor_basic_defconfig 

[PATCH V2 5/6] ARM: dts: stm32: Rework DDR DT inclusion

[Marek Vasut]

Adjust the DDR configuration dtsi such that they only generate the
DRAM configuration node, the DDR controller node is moved into the
stm32mp157-u-boot.dtsi itself. This permits including multiple DDR
configuration dtsi files in board DT.

Signed-off-by: Marek Vasut 
Cc: Manivannan Sadhasivam 
Cc: Patrick Delaunay 
Cc: Patrice Chotard 
---
V2: Add compatible string
---
 arch/arm/dts/stm32mp15-ddr.dtsi   | 358 +++---
 .../dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi   |   1 +
 .../dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi   |   1 +
 arch/arm/dts/stm32mp157-u-boot.dtsi   |  25 ++
 4 files changed, 248 insertions(+), 137 deletions(-)

diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
index 38f29bb789..026237b088 100644
--- a/arch/arm/dts/stm32mp15-ddr.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr.dtsi
@@ -2,153 +2,237 @@
 /*
  * Copyright : STMicroelectronics 2018
  */
+#include 
 
-/ {
-   soc {
-   ddr: ddr@5a003000 {
-   u-boot,dm-pre-reloc;
+ {
+   config-DDR_MEM_COMPATIBLE {
+   u-boot,dm-pre-reloc;
 
-   compatible = "st,stm32mp1-ddr";
+   compatible = __stringify(st,DDR_MEM_COMPATIBLE);
 
-   reg = <0x5A003000 0x550
-  0x5A004000 0x234>;
+   st,mem-name = DDR_MEM_NAME;
+   st,mem-speed = ;
+   st,mem-size = ;
 
-   clocks = < AXIDCG>,
-< DDRC1>,
-< DDRC2>,
-< DDRPHYC>,
-< DDRCAPB>,
-< DDRPHYCAPB>;
+   st,ctl-reg = <
+   DDR_MSTR
+   DDR_MRCTRL0
+   DDR_MRCTRL1
+   DDR_DERATEEN
+   DDR_DERATEINT
+   DDR_PWRCTL
+   DDR_PWRTMG
+   DDR_HWLPCTL
+   DDR_RFSHCTL0
+   DDR_RFSHCTL3
+   DDR_CRCPARCTL0
+   DDR_ZQCTL0
+   DDR_DFITMG0
+   DDR_DFITMG1
+   DDR_DFILPCFG0
+   DDR_DFIUPD0
+   DDR_DFIUPD1
+   DDR_DFIUPD2
+   DDR_DFIPHYMSTR
+   DDR_ODTMAP
+   DDR_DBG0
+   DDR_DBG1
+   DDR_DBGCMD
+   DDR_POISONCFG
+   DDR_PCCFG
+   >;
 
-   clock-names = "axidcg",
- "ddrc1",
- "ddrc2",
- "ddrphyc",
- "ddrcapb",
- "ddrphycapb";
+   st,ctl-timing = <
+   DDR_RFSHTMG
+   DDR_DRAMTMG0
+   DDR_DRAMTMG1
+   DDR_DRAMTMG2
+   DDR_DRAMTMG3
+   DDR_DRAMTMG4
+   DDR_DRAMTMG5
+   DDR_DRAMTMG6
+   DDR_DRAMTMG7
+   DDR_DRAMTMG8
+   DDR_DRAMTMG14
+   DDR_ODTCFG
+   >;
 
-   st,mem-name = DDR_MEM_NAME;
-   st,mem-speed = ;
-   st,mem-size = ;
+   st,ctl-map = <
+   DDR_ADDRMAP1
+   DDR_ADDRMAP2
+   DDR_ADDRMAP3
+   DDR_ADDRMAP4
+   DDR_ADDRMAP5
+   DDR_ADDRMAP6
+   DDR_ADDRMAP9
+   DDR_ADDRMAP10
+   DDR_ADDRMAP11
+   >;
 
-   st,ctl-reg = <
-   DDR_MSTR
-   DDR_MRCTRL0
-   DDR_MRCTRL1
-   DDR_DERATEEN
-   DDR_DERATEINT
-   DDR_PWRCTL
-   DDR_PWRTMG
-   DDR_HWLPCTL
-   DDR_RFSHCTL0
-   DDR_RFSHCTL3
-   DDR_CRCPARCTL0
-   DDR_ZQCTL0
-   DDR_DFITMG0
-   DDR_DFITMG1
-   DDR_DFILPCFG0
-   DDR_DFIUPD0
-   DDR_DFIUPD1
-   DDR_DFIUPD2
-   DDR_DFIPHYMSTR
-   DDR_ODTMAP
-   DDR_DBG0
-   DDR_DBG1
-  

[PATCH V2 1/6] ARM: stm32: Add default config for DHCOR

[Marek Vasut]

Add default U-Boot configuration for the DHCOR SoM on AV96 board.

Signed-off-by: Marek Vasut 
Cc: Manivannan Sadhasivam 
Cc: Patrick Delaunay 
Cc: Patrice Chotard 
---
V2: No change
---
 configs/stm32mp15_dhcor_basic_defconfig | 138 
 1 file changed, 138 insertions(+)
 create mode 100644 configs/stm32mp15_dhcor_basic_defconfig

diff --git a/configs/stm32mp15_dhcor_basic_defconfig 
b/configs/stm32mp15_dhcor_basic_defconfig
new file mode 100644
index 00..4a968609fe
--- /dev/null
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -0,0 +1,138 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_SYS_MALLOC_F_LEN=0x3000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_TARGET_DH_STM32MP1_PDK2=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_SPL_TEXT_BASE=0x2FFC2500
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8
+CONFIG_SYS_PROMPT="STM32MP> "
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcor-avenger96"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended 
interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names 
assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=1000
+CONFIG_USE_ENV_SPI_MODE=y
+CONFIG_ENV_SPI_MODE=0x0
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=1536
+CONFIG_STM32_ADC=y
+CONFIG_SPL_BLOCK_CACHE=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_VIRT=y
+CONFIG_DM_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_STM32=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_STM32_IPCC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_STM32_SDMMC2=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_SPL_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_KS8851_MLL=y
+CONFIG_PHY=y
+CONFIG_PHY_STM32_USBPHYC=y
+CONFIG_PINCONF=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_PINCTRL_STMFX=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_PMIC_STPMIC1=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_STM32_VREFBUF=y
+CONFIG_DM_REGULATOR_STPMIC1=y
+CONFIG_REMOTEPROC_STM32_COPRO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_STM32=y
+CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
+CONFIG_STM32_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="dh"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0483
+CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_DSI=y
+CONFIG_VIDEO_STM32_MAX_XRES=1280
+CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_LZO=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
-- 
2.25.1

[PATCH V2 3/6] ARM: stm32: Implement board coding on AV96

[Marek Vasut]

The AV96 board does exist in multiple variants. To cater for all of
them, implement board code handling. There are two GPIOs which code
the type of the board, read them out and use the value to pick the
correct device tree from an fitImage.

Signed-off-by: Marek Vasut 
Cc: Manivannan Sadhasivam 
Cc: Patrick Delaunay 
Cc: Patrice Chotard 
---
V2: No change
---
 arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi|  3 +
 .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi   |  1 +
 arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi|  9 +++
 board/dhelectronics/dh_stm32mp1/Kconfig   |  2 +-
 board/dhelectronics/dh_stm32mp1/board.c   | 61 +++
 .../dh_stm32mp1/u-boot-dhcom.its  | 39 
 .../dh_stm32mp1/u-boot-dhcor.its  | 39 
 configs/stm32mp15_dhcom_basic_defconfig   |  3 +
 configs/stm32mp15_dhcor_basic_defconfig   |  3 +
 include/configs/dh_stm32mp1.h | 15 +
 10 files changed, 174 insertions(+), 1 deletion(-)
 create mode 100644 board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
 create mode 100644 board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
 create mode 100644 include/configs/dh_stm32mp1.h

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi 
b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index eba3588540..fcdc5e6859 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -19,10 +19,13 @@
};
 
config {
+   u-boot,dm-pre-reloc;
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
st,fastboot-gpios = < 13 GPIO_ACTIVE_LOW>;
st,stm32prog-gpios = < 14 GPIO_ACTIVE_LOW>;
+   #gpio-cells = <2>;
+   dh,som-coding-gpios = < 12 0>, < 13 0>, < 15 
0>;
};
 
led {
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi 
b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
index 4207a96618..7ccec95f15 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
@@ -15,6 +15,7 @@
config {
u-boot,boot-led = "led1";
u-boot,error-led = "led4";
+   dh,board-coding-gpios = < 13 0>, < 9 0>;
};
 };
 
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi 
b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index 02dad81b0b..17a23ae21c 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -11,6 +11,15 @@
 #include "stm32mp157-u-boot.dtsi"
 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
 
+/ {
+   u-boot,dm-pre-reloc;
+   config {
+   u-boot,dm-pre-reloc;
+   #gpio-cells = <2>;
+   dh,som-coding-gpios = < 7 0>, < 3 0>;
+   };
+};
+
  {
u-boot,dm-pre-reloc;
 };
diff --git a/board/dhelectronics/dh_stm32mp1/Kconfig 
b/board/dhelectronics/dh_stm32mp1/Kconfig
index 8eab986640..0a839f2546 100644
--- a/board/dhelectronics/dh_stm32mp1/Kconfig
+++ b/board/dhelectronics/dh_stm32mp1/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
default "dhelectronics"
 
 config SYS_CONFIG_NAME
-   default "stm32mp1"
+   default "dh_stm32mp1"
 
 config ENV_SECT_SIZE
default 0x1 if ENV_IS_IN_SPI_FLASH
diff --git a/board/dhelectronics/dh_stm32mp1/board.c 
b/board/dhelectronics/dh_stm32mp1/board.c
index a3458a2623..b72d113a6f 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -133,6 +133,62 @@ int checkboard(void)
return 0;
 }
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+static u8 brdcode __section("data");
+static u8 somcode __section("data");
+
+static void board_get_coding_straps(void)
+{
+   struct gpio_desc gpio[4];
+   ofnode node;
+   int i, ret;
+
+   node = ofnode_path("/config");
+   if (!ofnode_valid(node)) {
+   printf("%s: no /config node?\n", __func__);
+   return;
+   }
+
+   brdcode = 0;
+   somcode = 0;
+
+   ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
+ gpio, ARRAY_SIZE(gpio),
+ GPIOD_IS_IN);
+   for (i = 0; i < ret; i++)
+   somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
+
+   ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
+ gpio, ARRAY_SIZE(gpio),
+ GPIOD_IS_IN);
+   for (i = 0; i < ret; i++)
+   brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
+
+   printf("Code:  SoM:rev=%d Board:rev=%d\n", somcode, brdcode);
+}
+
+int board_early_init_f(void)
+{
+   board_get_coding_straps();
+
+   return 0;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+   char test[20];
+
+   snprintf(test, 

[PATCH V2 4/6] ram: stm32mp1: Add support for multiple configs

[Marek Vasut]

Add support for multiple DRAM configuration subnodes, while retaining
the support for a single flat DRAM configuration node. This is useful
on systems which can be manufactured in multiple configurations and
where the DRAM configuration can be determined at runtime.

The code is augmented by a function which can be overridden on board
level, allowing a match on the configuration node name, very much like
the fitImage configuration node name matching works. The default match
is on the single top-level DRAM configuration, if matching on subnodes
is required, then this board_stm32mp1_ddr_config_name_match() must be
overridden.

Signed-off-by: Marek Vasut 
Cc: Manivannan Sadhasivam 
Cc: Patrick Delaunay 
Cc: Patrice Chotard 
---
V2: Match on compatible string
---
 drivers/ram/stm32mp1/stm32mp1_ram.c | 39 +
 1 file changed, 34 insertions(+), 5 deletions(-)

diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c 
b/drivers/ram/stm32mp1/stm32mp1_ram.c
index eb78f1198d..21c220694e 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ram.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -57,6 +57,33 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t 
mem_speed)
return 0;
 }
 
+__weak int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
+   const char *name)
+{
+   return 0;   /* Always match */
+}
+
+static ofnode stm32mp1_ddr_get_ofnode(struct udevice *dev)
+{
+   const char *name;
+   int name_size;
+   ofnode node;
+
+   node = dev_ofnode(dev);
+   name = ofnode_get_property(node, "compatible", _size);
+   if (!board_stm32mp1_ddr_config_name_match(dev, name))
+   return node;
+
+   dev_for_each_subnode(node, dev) {
+   name = ofnode_get_property(node, "compatible", _size);
+
+   if (!board_stm32mp1_ddr_config_name_match(dev, name))
+   return node;
+   }
+
+   return ofnode_null();
+}
+
 static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
 {
struct ddr_info *priv = dev_get_priv(dev);
@@ -64,6 +91,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice 
*dev)
unsigned int idx;
struct clk axidcg;
struct stm32mp1_ddr_config config;
+   ofnode node = stm32mp1_ddr_get_ofnode(dev);
 
 #define PARAM(x, y) \
{ x,\
@@ -87,9 +115,9 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice 
*dev)
PHY_PARAM(cal)
};
 
-   config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0);
-   config.info.size = dev_read_u32_default(dev, "st,mem-size", 0);
-   config.info.name = dev_read_string(dev, "st,mem-name");
+   config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0);
+   config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
+   config.info.name = ofnode_read_string(node, "st,mem-name");
if (!config.info.name) {
debug("%s: no st,mem-name\n", __func__);
return -EINVAL;
@@ -97,7 +125,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice 
*dev)
printf("RAM: %s\n", config.info.name);
 
for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
-   ret = dev_read_u32_array(dev, param[idx].name,
+   ret = ofnode_read_u32_array(node, param[idx].name,
 (void *)((u32) +
  param[idx].offset),
 param[idx].size);
@@ -164,7 +192,8 @@ static int stm32mp1_ddr_probe(struct udevice *dev)
priv->info.size = 0;
return stm32mp1_ddr_setup(dev);
 #else
-   priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0);
+   ofnode node = stm32mp1_ddr_get_ofnode(dev);
+   priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
return 0;
 #endif
 }
-- 
2.25.1

[PATCH V2 2/6] ARM: stm32: Add board_early_init_f() to SPL

[Marek Vasut]

Add weak implementation of board_early_init_f() hook into the
STM32MP1 SPL. This can be used to read out e.g. configuration
straps before initializing the DRAM.

Signed-off-by: Marek Vasut 
Cc: Manivannan Sadhasivam 
Cc: Patrick Delaunay 
Cc: Patrice Chotard 
---
V2: No change
---
 arch/arm/mach-stm32mp/spl.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
index ca4231cd0d..cd14d1065e 100644
--- a/arch/arm/mach-stm32mp/spl.c
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -76,6 +76,11 @@ void spl_display_print(void)
 }
 #endif
 
+__weak int board_early_init_f(void)
+{
+   return 0;
+}
+
 void board_init_f(ulong dummy)
 {
struct udevice *dev;
@@ -110,6 +115,12 @@ void board_init_f(ulong dummy)
/* enable console uart printing */
preloader_console_init();
 
+   ret = board_early_init_f();
+   if (ret) {
+   debug("board_early_init_f() failed: %d\n", ret);
+   hang();
+   }
+
ret = uclass_get_device(UCLASS_RAM, 0, );
if (ret) {
printf("DRAM init failed: %d\n", ret);
-- 
2.25.1

[PATCH] tiny-printf: Support %i

[Marek Vasut]

The most basic printf("%i", value) formating string was missing,
add it for the sake of convenience.

Signed-off-by: Marek Vasut 
Cc: Simon Glass 
Cc: Stefan Roese 
---
 lib/tiny-printf.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 1138c7012a..8fc7e48d99 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -242,6 +242,7 @@ static int _vprintf(struct printf_info *info, const char 
*fmt, va_list va)
goto abort;
case 'u':
case 'd':
+   case 'i':
div = 10;
if (islong) {
num = va_arg(va, unsigned long);
@@ -251,7 +252,7 @@ static int _vprintf(struct printf_info *info, const char 
*fmt, va_list va)
num = va_arg(va, unsigned int);
}
 
-   if (ch == 'd') {
+   if (ch != 'u') {
if (islong && (long)num < 0) {
num = -(long)num;
out(info, '-');
-- 
2.25.1

Re: [PATCH V3] ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2

[Marek Vasut]

On 4/9/20 7:38 PM, Patrick DELAUNAY wrote:
Hi,

[...]

>> That looks like a hack, it would collide with the actual FMC2 driver and it 
>> seems
>> the FMC2 DT compatible string is not even stable yet (cfr the Linux 
>> patches). So I
>> am reluctant to do anything like depending on the FMC DT bindings thus far.
> 
> You are aligned with Christophe, he push me to accept your temporarily 
> solution.

Great, thanks.

I had a look into writing the bus driver in the meantime, but it's not
as simple as I originally anticipated. So, I'll wait until the Linux DT
bindings stabilize and revisit it then.

Thanks

Re: [PATCH 5/8] xhci: mediatek: Add support for MTK xHCI host controller

[Marek Vasut]

On 3/31/20 6:05 PM, Marek Vasut wrote:
> On 3/31/20 4:16 PM, Simon Glass wrote:
>> HI Marek,
> 
> Hi,
> 
> [...]
> 
>> OK I have updated the coding style page with all of this.
>
> Which page ?

 https://www.denx.de/wiki/U-Boot/CodingStyle
>>>
>>> " U-Boot typically uses a C structure to map out the registers in an I/O
>>> region, rather than offsets. The reasons for this are: " is misleading
>>> and suggests that using structures is the best practice. This should be
>>> reworded to make it clear both options are equally valid.
>>
>> I'd like to see a preference to use struct where it makes sense and
>> not use it when it doesn't, with the different tradeoffs clearly
>> written. Are asking that we say nothing about which is better in each
>> situation?
> 
> Correct, because I don't see a clear agreement on which one is better
> and should be preferred.

I see the wiki has still not been correctly reworded, can you please
repair it ?

Re: [PATCH] board: stm32mp1: correct CONFIG_IS_ENABLED usage for LED

[Marek Vasut]

On 4/10/20 7:14 PM, Patrick Delaunay wrote:
> Use the correct macro to test presence CONFIG_LED:
> replace CONFIG_IS_ENABLED(CONFIG_LED) by CONFIG_IS_ENABLED(LED)
> 
> Issue see during review unrelated patch
> "board: stm32mp1: update management of boot-led"
> http://patchwork.ozlabs.org/patch/1264823/
> 
> Cc: Marek Vasut 
> Cc: Patrice Chotard 
> Signed-off-by: Patrick Delaunay 

Reviewed-by: Marek Vasut 

Re: [PATCH 3/4] [RFC] ARM: dts: stm32: Rework DDR DT inclusion

[Marek Vasut]

On 4/9/20 7:05 PM, Patrick DELAUNAY wrote:
> Hi Marek,
> 
>> From: Marek Vasut 
>> Sent: mercredi 8 avril 2020 15:54
>>
>> On 4/8/20 12:09 PM, Patrick DELAUNAY wrote:
>>> Hi,
>>
>> Hi,
>>
 From: Marek Vasut 
 Sent: mardi 7 avril 2020 22:01

 On 4/7/20 3:00 PM, Patrick DELAUNAY wrote:
> Dear Marek,

 Hi,

> 
> [...]
> 
>
> And I want to propose, for DH board with several configuration
>
>   {
>   config-1 {
> #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
>   }
>   config-2 {
> #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
>   }
> }
>
>
> For ST board with only one configuration (don't change the device
> tree, config at the same level)   { #include
> "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
> }
>
>
> 
> [...]
> 

 I would much rather prefer to avoid manually writing the config@
 parts, that should be handled by some macro magic instead. With my
 proposal, it is not necessary at all either.
>>>
> 
> []
> 
>>>
>>> So the file generate by CubeMX don't change =  stm32mp15-ddr3-1x4Gb-1066-
>> binG.dtsi and stm32mp15-ddr3-2x4Gb-1066-binG.dtsi.
>>>
>>> The ST board devicetree don't change: the DDR configuration is still
>>> in ddr node (as in TF-A)
>>>
>>> For your board, the device tree
>>> /arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
>>>
>>> [...]
>>> #define DDR_MEM_CONFIG 2
>>> #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
>>>
>>> #define DDR_MEM_CONFIG 3
>>> #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
>>> [...]
>>>
>>> And you can directly compare reg value of sub node with ddr3code.
>>>
>>> It is more acceptable ?
>>
>> I wonder, can't we have some sort of macro where you would specify a 
>> compatible
>> string for the DDR config (on which you can match in your
>> board_stm32mp1_ddr_config_name_match() and the dtsi file to be included, and
>> the macro would generate the necessary entries in the  {} controller 
>> node ?
>>
>> E.g. like this:
>>
>> #include "stm32mp15-ddr.dtsi"
>> STM32MP15_DDR("vendor,board-1gib", stm32mp15-ddr3-2x4Gb-1066-binG.dtsi);
>> STM32MP15_DDR("vendor,board-2gib", stm32mp15-ddr3-4x4Gb-1066-binG.dtsi);
>>
>> and then in board_stm32mp1_ddr_config_name_match()
>> {
>>  if (!strcmp(..., "vendor,board-1gib"))
>> return 0;
>>  ...
>> }
> 
> Yes, I agree, compatible is the better solution and the binding 
> 
> ./doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt becomes
> 
> ddr: ddr@0x5A003000{
>   compatible = "st,stm32mp1-ddr";
>   [...]
> 
>   config-1 {
>   compatible = "vendor,board-1gib";
> 
>   st,mem-name = "..."
>   [...]
>   st,phy-timing = <...>
>   }
>   config-2 {
>   compatible = "vendor,board-2gib";
>   st,mem-name = "..."
>   [...]
>   st,phy-timing = <...>
>   }
>   status = "okay";
> }
> 
> And you match this configuration with compatible.
> 
> For the macro, it should be perfect, if it is not too complicate.
> 
> Because I afraid that "#include" in macro isn't allowed.

I'll send a V2 now. The compatible string is easy enough.

Re: iMX8MM USB support?

[Tim Harvey]

On Thu, Apr 9, 2020 at 2:45 PM Tim Harvey  wrote:
>
> On Thu, Apr 9, 2020 at 3:02 AM Schrempf Frieder
>  wrote:
> >
> > On 08.04.20 17:31, Tim Harvey wrote:
> > [...]
> > >>
> > >> In my case I'm loading a FIT image, so things are a bit different.
> > >> Where are you loading the image to?
> > >>
> > >> I have the following line in mx8mm_usb_sdp_spl.conf to load my FIT image
> > >> to DDR and jump to it:
> > >>
> > >> /path/to/image/u-boot.itb:load 0x4020, jump_direct 0x4020
> > >>
> > >
> > > Frieder,
> > >
> > > I was trying to load u-boot.img
> > >
> > > The SPL boots fine:
> > > U-Boot SPL 2020.01-00029-g5ad7797 (Apr 08 2020 - 08:16:53 -0700)
> > > read error from device: 9310b8 register: x!Normal Boot
> > > Trying to boot from USB SDP
> > > SDP: initialize...
> > > SDP: handle requests..
> > >
> > > But when I 'imx_usb u-boot.img' it complains there is no header on
> > > u-boot.img. I enabled FIT generation and attempted to 'imx_usb
> > > u-boot.itb' but imx_usb still complains about no header found.
> > >
> > > My mx8mm_usb_sdp_spl.conf loooks like this:
> > > mx8mm_spl_sdp
> > > #hid/bulk,[old_header,]max packet size, {ram start, ram size}(repeat
> > > valid ram areas)
> > > #In SPL, we typically load u-boot.img which has a U-boot header...
> > > hid,1024,0x91,0x4000,1G,0x0090,0x4
> > >
> > > #0x6 - 0x8400 = 0x57c00, +0x3000=5ac00 (FIT image)
> > > ../u-boot-imx6/u-boot.bin:load 0x4020
> > > ../u-boot-imx6/bl31-iMX8MM.bin:load 0x0092,jump 0x92
> > >
> > > What does your mx8mm_usb_sdp_spl.conf look like? I must admit I don't
> > > really understand how these are configured.
> >
> > It looks just like yours except that I have a single instruction as
> > already stated above:
> >
> > /path/to/image/u-boot.itb:load 0x4020, jump_direct 0x4020
> >
> > and I'm loading the FIT image by running './imx_usb' without arguments.
> >
> > As imx_usb_loader can't parse FIT image headers, I use 'jump_direct' to
> > jump to the raw image entry point and let SPL parse the FIT. I think in
> > that case imx_usb_loader shouldn't complain about a missing header.
>
> Frieder,
>
> Ok, I finally understand. Using 'imx_usb ' which is what I was
> doing is not the same as loading it via the conf file and was why it
> was looking for a header.
>
> So now that I'm using the imx_usb.conf files fully instead It's
> loading u-boot.itb and jumping but unfortunately I'm still not quite
> there.
>
> Here's what I'm seeing:
>
> U-Boot SPL 2020.01-00029-g6529a03-dirty (Apr 09 2020 - 13:02:21 -0700)
> Normal Boot
> Trying to boot from USB SDP
> SDP: initialize...
> SDP: handle requests...
> Downloading file of size 584020 to 0x4020... done
> Jumping to header at 0x4020
> Header Tag is not an IMX image
>
> Is the 'Header Tag' message normal? From adding some debugging it
> appears to matching the dts name in my board_fit_config_name_match and
> parsing the FIT image, loading the ATF and jumping but then I get
> nothing. What would I expect at this point and do you have any
> troubleshooting tips?
>

Frieder,

My issue was that I forgot to set ATF_LOAD_ADDR=0x92!

So I'm running now, booting imx8mm-evk via SDP using your USB patches
and imx_usb configuration.

Thank you for your help!

Tim

[PATCH v2 3/3] rockchip: Enable SF distro bootcmd

[Jagan Teki]

Enable SPI flash(SF) distro boot command in Rockchip.

This distro boot will read the boot script at specific
location at the flash and start sourcing the same.

Included the SF device at the last of the target devices
list since all the rest of the devices on the list have
more possibility to boot the distribution due to the
size of the SPI flash is concern.

Cc: Tom Rini 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- update BOOT_TARGET_SF 

 include/configs/rk3399_common.h   | 1 +
 include/configs/rockchip-common.h | 9 -
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 01a9174bd2..f0ae6e67a7 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -60,6 +60,7 @@
 #endif
 
 #include 
+#include 
 #define CONFIG_EXTRA_ENV_SETTINGS \
ENV_MEM_LAYOUT_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
diff --git a/include/configs/rockchip-common.h 
b/include/configs/rockchip-common.h
index b55e09a9ca..d97395db90 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -41,11 +41,18 @@
#define BOOT_TARGET_DHCP(func)
 #endif
 
+#if CONFIG_IS_ENABLED(CMD_SF)
+   #define BOOT_TARGET_SF(func)func(SF, sf, 0)
+#else
+   #define BOOT_TARGET_SF(func)
+#endif
+
 #define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_MMC(func) \
BOOT_TARGET_USB(func) \
BOOT_TARGET_PXE(func) \
-   BOOT_TARGET_DHCP(func)
+   BOOT_TARGET_DHCP(func) \
+   BOOT_TARGET_SF(func)
 
 #ifdef CONFIG_ARM64
 #define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0"
-- 
2.17.1

[PATCH v2 1/3] environment: distro: Add SF distro command

[Jagan Teki]

Add distro boot command support for SPI flash (SF).

This distro boot will read the boot script at specific
location at the flash and start sourcing the same.

This file need to include on required include/config
file.

Cc: Tom Rini 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- new patch

 include/environment/distro/sf.h | 41 +
 1 file changed, 41 insertions(+)
 create mode 100644 include/environment/distro/sf.h

diff --git a/include/environment/distro/sf.h b/include/environment/distro/sf.h
new file mode 100644
index 00..e793be06c6
--- /dev/null
+++ b/include/environment/distro/sf.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Amarula Solutions(India)
+ *
+ * SF distro configurations.
+ */
+
+#ifndef __DISTRO_SF_CONFIG_H
+#define __DISTRO_SF_CONFIG_H
+
+#if CONFIG_IS_ENABLED(CMD_SF)
+#define BOOTENV_SHARED_SF(devtypel)\
+   #devtypel "_boot="  \
+   "if " #devtypel " probe ${busnum}; then "   \
+   "devtype=" #devtypel "; "   \
+   "run scan_sf_for_scripts; " \
+   "fi\0"
+#define BOOTENV_DEV_SF(devtypeu, devtypel, instance)   \
+   "bootcmd_" #devtypel #instance "="  \
+   "busnum=" #instance "; "\
+   "run " #devtypel "_boot\0"
+#define BOOTENV_DEV_NAME_SF(devtypeu, devtypel, instance)  \
+   #devtypel #instance " "
+#else
+#define BOOTENV_SHARED_SF(devtypel)
+#define BOOTENV_DEV_SF \
+   BOOT_TARGET_DEVICES_references_SF_without_CONFIG_CMD_SF
+#define BOOTENV_DEV_NAME_SF \
+   BOOT_TARGET_DEVICES_references_SF_without_CONFIG_CMD_SF
+
+#endif /* CONFIG_CMD_SF */
+
+#define BOOTENV_SF \
+   BOOTENV_SHARED_SF(sf) \
+   "scan_sf_for_scripts="  \
+   "${devtype} read ${scriptaddr} "\
+   "${script_offset_f} ${script_size_f}; " \
+   "source ${scriptaddr}; "\
+   "echo SCRIPT FAILED: continuing...\0"
+
+#endif /* __DISTRO_SF_CONFIG_H */
-- 
2.17.1

[PATCH v2 2/3] rk3399: Add boot flash script offset, size

[Jagan Teki]

Most of the SPI flash devices in rockchip (rk3399)
are 16MiB size. So, let's use the script offset at
the end of 8K. 

This way it cannot overlap any offsets being used
by software components in flash layout.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v2:
- new patch

 include/configs/rk3399_common.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 89a8a44bbe..01a9174bd2 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -48,6 +48,8 @@
 
 #define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x0050\0" \
+   "script_offset_f=0xffe000\0" \
+   "script_size_f=0x2000\0" \
"pxefile_addr_r=0x0060\0" \
"fdt_addr_r=0x01f0\0" \
"kernel_addr_r=0x0208\0" \
-- 
2.17.1

[PATCH v2 0/3] environment: distro: Add SF distro support

[Jagan Teki]

This patch is based on Tom comments from previous 
version[1] for adding new distro support separately
as in include/environment/distro/sf.h 

This new sf distro command not touch the existing
include/config_distro_bootcmd.h.

Used this new SF distro command in rk3399 platform.

[1] https://patchwork.ozlabs.org/patch/1232666/

Any inputs?
Jagan.

Jagan Teki (3):
  environment: distro: Add SF distro command
  rk3399: Add boot flash script offset, size
  rockchip: Enable SF distro bootcmd

 include/configs/rk3399_common.h   |  3 +++
 include/configs/rockchip-common.h |  9 ++-
 include/environment/distro/sf.h   | 41 +++
 3 files changed, 52 insertions(+), 1 deletion(-)
 create mode 100644 include/environment/distro/sf.h

-- 
2.17.1

Re: [PATCH 2/3] arm: caches: add DCACHE_DEFAULT_OPTION

[Marek Vasut]

On 4/10/20 4:58 PM, Patrick DELAUNAY wrote:
> Hi Marek,
> 
>> From: Marek Vasut 
>> Sent: vendredi 10 avril 2020 10:14
>>
>> On 4/9/20 8:06 PM, Patrick DELAUNAY wrote:
>>> Dear Marek,
>>
>> Hi,
>>
 Sent: jeudi 9 avril 2020 12:21
 To: Patrick DELAUNAY ; u-boot@lists.denx.de

 On 4/9/20 12:01 PM, Patrick DELAUNAY wrote:
> Dear Marek,

 Hi,

>> From: Uboot-stm32
>> 
>> On Behalf Of Patrick DELAUNAY
>>
>> Dear Marek,
>>
>>> From: Marek Vasut 
>>> Sent: vendredi 3 avril 2020 23:29
>>>
>>> On 4/3/20 10:28 AM, Patrick Delaunay wrote:
 Add the new flags DCACHE_DEFAULT_OPTION to define the default
 option to use according the compilation flags
 CONFIG_SYS_ARM_CACHE_WRITETHROUGH or
>>> CONFIG_SYS_ARM_CACHE_WRITEALLOC.
>>>
>>> Can't you unify these macros into a single Kconfig "select"
>>> statement instead , and then just select the matching cache
>>> configuration in
 Kconfig ?
>>
>> Yes I will try, with 2 steps
>> - migrate existing CONFIG_SYS_ARM_CACHE_ in Kconfig
>
> First step done...
> I will push it as a separate patchset I think.
>
>> - add new option CONFIG_SYS_ARM_CACHE_OPTION
>
> In fact it is to difficult to use select because each defines
> DCACHE_XXX value can have several values
>
> they are build according CONFIG_ARM64 / LPAE
>
> But, I can't use this define in Kconfig
>
> I try :
> optionARM_OPTION
>   int "option"
>   default DCACHE_WRITETHROUGHT if
 CONFIG_SYS_ARM_CACHE_WRITETHROUGH
>   default DCACHE_ WRITEALLOC if CONFIG_SYS_ARM_CACHE_
 WRITEALLOC
>   default DCACHE_WRITEBACK if
 CONFIG_SYS_ARM_CACHE_WRITEBACK
>
> int and hex is invalid, and string can't be use with "".
>
> And I don't found way to build it automatically when option is activated.
>
> Any idea ?

 Maybe you can have a select in the Kconfig to set some differently
 named option, e.g.

 DCACHE_MODE_WRITE{THROUGH,ALLOC,BACK}

 and then an ifdef in some header file, e.g.

 #ifdef CONFIG_DCACHE_MODE_WRITETHROUGH #define
>> ARM_CACHE_MODE
 DCACHE_WRITETHROUGH ...

 And then use ARM_CACHE_MODE where you need a value and
 CONFIG_DCACHE_MODE{...} where you need a config option check.

 Does this work ?
>>>
>>> I try with string and default (as select is allowed on for bolean or
>>> trisate), And I failed :-<
>>>
>>> I don't found a way to have the de-stringficate the KConfig option to
>>> generated the correct define
>>
>> The result is a boolean , isn't it ? One out of N configs ends up being 
>> defined and
>> the rest are not defined.
>>
>>> config SYS_ARM_CACHE_POLICY
>>> string "Name of the ARM data write cache policy"
>>> default WRITEBACK if SYS_ARM_CACHE_WRITEBACK
>>> default WRITETHROUGH if SYS_ARM_CACHE_WRITEBACK
>>> default WRITEALLOC if SYS_ARM_CACHE_WRITEALLOC
>>>
>>> #define DCACHE_DEFAULT_OPTION   DCACHE_ ##
>> CONFIG_SYS_ARM_CACHE_POLICY
>>>
>>> => error: ‘DCACHE_CONFIG_SYS_ARM_CACHE_POLICY’ undeclared (first
>> use in this function); did you mean ‘CONFIG_SYS_ARM_CACHE_POLICY’?
>>>
>>> #define DCACHE_OPTION(s)DCACHE_ ##
>> CONFIG_SYS_ARM_CACHE_POLICY
>>>
>>> #define DCACHE_DEFAULT_OPTION
>>  DCACHE_OPTION(CONFIG_SYS_ARM_CACHE_POLICY)
>>>
>>> arch/arm/include/asm/system.h:488:26: error: ‘DCACHE_’ undeclared (first use
>> in this function); did you mean ‘DCACHE_OFF’?
>>> arch/arm/lib/cache-cp15.c:99:25: error: expected ‘)’ before string
>>> constant
>>>
>>> The stringification is possible but not the inverse operation (remove the 
>>> quote)...
>>>
>>> In my .config, CONFIG_SYS_ARM_CACHE_POLICY="WRITEBACK"
>>
>> What about this:
>>
>> choice
>> prompt "Cache policy"
>>  default CACHE_WRITEBACK
>>
>> config CACHE_WRITEBACK
>>  bool "Writeback"
>>
>> config ...
>>
>> endchoice
>>
>> and then in some header
>>
>> #ifdef CONFIG_CACHE_WRITEBACK
>> #define CONFIF_SYS_ARM_CACHE_WRITEBACK
>> #else
>> ...
>>
>> Would that work ?
> 
> Yes, it can work it seems complicated
> 
> I push v2 for CONFIG_SYS_ARM_CACHE_* migration in Kconfig
> 
> My proposal becomes:
> 
> +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
> +#define DCACHE_DEFAULT_OPTIONDCACHE_WRITETHROUGH
> +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
> +#define DCACHE_DEFAULT_OPTIONDCACHE_WRITEALLOC
> +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
> +#define DCACHE_DEFAULT_OPTIONDCACHE_WRITEBACK
> +#endif
> +
> 
> I think it is is more clear solution.
> 
> 
> I can use macro magic to build DCACHE_DEFAULT_OPTION 
> 
> +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
> +#define ARM_CACHE_POLICY WRITETHROUGH
> +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
> +#define ARM_CACHE_POLICY WRITEALLOC
> +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
> +#define ARM_CACHE_POLICY WRITEBACK
> +#endif
>  
> +#define 

Re: [PATCH 3/3] arm: caches: manage phys_addr_t overflow in mmu_set_region_dcache_behaviour

[Marek Vasut]

On 4/10/20 3:24 PM, Patrick DELAUNAY wrote:
> Dear Marek
> 
>> From: Marek Vasut 
>> Sent: vendredi 10 avril 2020 10:06
>>
>> On 4/9/20 4:18 PM, Patrick DELAUNAY wrote:
>>>
>>>
 -Original Message-
 From: Marek Vasut 
 Sent: vendredi 3 avril 2020 23:31
 To: Patrick DELAUNAY ; u-boot@lists.denx.de
 Cc: Simon Glass ; Alexey Brodkin
 ; Lokesh Vutla ; Tom Rini
 ; Trevor Woerner ; U-Boot
 STM32 
 Subject: Re: [PATCH 3/3] arm: caches: manage phys_addr_t overflow in
 mmu_set_region_dcache_behaviour
 Importance: High

 On 4/3/20 10:28 AM, Patrick Delaunay wrote:
> Detect and solve the overflow on phys_addr_t type for start + size
> in
> mmu_set_region_dcache_behaviour() function.
>
> This issue occurs for example with ARM32, start = 0xC000 and
> size = 0x4000: start + size = 0x1 and end = 0x0.
>
> Overflow is detected when end < start.
> In normal case the previous behavior is still used: when start is
> not aligned on MMU section, the end address is only aligned after
> the sum start + size.
>
> Signed-off-by: Patrick Delaunay 
> ---
>
>  arch/arm/lib/cache-cp15.c | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> index d15144188b..e5a7fd0ef4 100644
> --- a/arch/arm/lib/cache-cp15.c
> +++ b/arch/arm/lib/cache-cp15.c
> @@ -63,6 +63,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t
> start, size_t size,
>
>   end = ALIGN(start + size, MMU_SECTION_SIZE) >>
 MMU_SECTION_SHIFT;
>   start = start >> MMU_SECTION_SHIFT;
> +
> + /* phys_addr_t overflow detected */
> + if (end < start)
> + end = (~(phys_addr_t)0x0 >> MMU_SECTION_SHIFT) + 1;
> +

 Or, you can divide $start and $size separately by MMU_SECTION_SIZE
 and then add them up .
>>>
>>> It was my first idea but that change the function behavior, because
>>> today start and size can be not aligned on MMU_SECTION aligned.
>>>
>>> I think it is strange, but I preferred to don't change this part.
>>>
>>> Example with shift = 21 and 2MB section size: 0x20
>>>
>>> Start = 0x100
>>> Size = 0x100
>>>
>>> End = 0x200
>>>
>>> => after alignment start = 0x0, end = 0x1
>>>
>>> But if we align the start and size before addition as proposed, the
>>> final result change
>>>
>>> Start = 0x100 => 0
>>> Size = 0x100 => 0
>>>
>>> End = 0x0
>>>
>>> I prefer don't modify this current (strange) behavior to avoid regression.
>>>
>>> But if it is acceptable (because the caller MUST always use start and
>>> size MMU_SECTION aligned), I will change the proposal
>>
>> The minimum page size is 4k, right ? Then divide both by 4k and then by the 
>> rest
>> of MMU_SECTION_SHIFT.
> 
> Yes, good idea...
> I am waiting possible other feedbacks
> 
> but I think ii ts candidate to integrate V2.

It's much better than dealing with overflows, esp. if you're shifting by
power-of-two anyway. And using 4k should also take care of LPAE 36bit
address space.

[PATCH] board: stm32mp1: correct CONFIG_IS_ENABLED usage for LED

[Patrick Delaunay]

Use the correct macro to test presence CONFIG_LED:
replace CONFIG_IS_ENABLED(CONFIG_LED) by CONFIG_IS_ENABLED(LED)

Issue see during review unrelated patch
"board: stm32mp1: update management of boot-led"
http://patchwork.ozlabs.org/patch/1264823/

Cc: Marek Vasut 
Cc: Patrice Chotard 
Signed-off-by: Patrick Delaunay 
---

 board/dhelectronics/dh_stm32mp1/board.c | 2 +-
 board/st/stm32mp1/stm32mp1.c| 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/dhelectronics/dh_stm32mp1/board.c 
b/board/dhelectronics/dh_stm32mp1/board.c
index 7bcd713a86..3c14d8206d 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -398,7 +398,7 @@ int board_init(void)
 
sysconf_init();
 
-   if (CONFIG_IS_ENABLED(CONFIG_LED))
+   if (CONFIG_IS_ENABLED(LED))
led_default_state();
 
return 0;
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 07f5344ec9..053c5e1f07 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -647,7 +647,7 @@ int board_init(void)
 
sysconf_init();
 
-   if (CONFIG_IS_ENABLED(CONFIG_LED))
+   if (CONFIG_IS_ENABLED(LED))
led_default_state();
 
return 0;
-- 
2.17.1

RE: [PATCH 08/16] board: stm32mp1: update management of boot-led

[Patrick DELAUNAY]

Dear Anatolij

> From: Anatolij Gustschin 
> Sent: mercredi 1 avril 2020 13:43
> 
> Hi Patrick,
> 
> On Tue, 31 Mar 2020 18:04:25 +0200
> Patrick Delaunay patrick.delau...@st.com wrote:
> ...
> > @@ -648,8 +652,10 @@ int board_init(void)
> >
> > sysconf_init();
> >
> > -   if (CONFIG_IS_ENABLED(CONFIG_LED))
> > +   if (CONFIG_IS_ENABLED(CONFIG_LED)) {
> > led_default_state();
> 
> Did you verify that this works like expected? We either use
>   if (CONFIG_IS_ENABLED(LED))
> or
>   if (IS_ENABLED(CONFIG_LED))
> 
> Please check.

You are right: it is not working.

I had already make this error,
I will solve the issue a in separate patch (also impacting dh_stm32mp1).

Thanks for review.

> --
> Anatolij

Patrick

Re: [PATCH] ARM: stm32: Enable bootd, iminfo, imxtract on DHCOM

[Marek Vasut]

On 4/10/20 5:40 PM, Patrick DELAUNAY wrote:
> Dear Marek,
> 
>> From: Marek Vasut 
>> Sent: mercredi 1 avril 2020 17:13
>>
>> Enable these standard U-Boot commands for image manipulation and for starting
>> the default boot command using 'boot' command in U-Boot shell.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Patrick Delaunay 
>> Cc: Patrice Chotard 
>> ---
> 
> Reviewed-by: Patrick Delaunay 
> 
> And I think I will done the same patch on ST defconfig.

Yes please, without this, it was quite annoying on the stm32mp1.

Re: [PATCH 3/3] rmobile: rcar: removed used CONFIG_SYS_RCAR_I2C*_BASE

[Marek Vasut]

On 4/10/20 4:34 PM, Patrick Delaunay wrote:
> As this "CONFIG" are never used, CONFIG_SYS_RCAR_I2C*_BASE can
> be removed without effect and the file config_whitelist.txt is
> also clean-up.
> 
> Signed-off-by: Patrick Delaunay 
> ---
> 
>  arch/arm/mach-rmobile/include/mach/rcar-base.h | 6 --
>  scripts/config_whitelist.txt   | 4 
>  2 files changed, 10 deletions(-)

Update the README too, otherwise look good, thanks.

RE: [PATCH V4] ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2

[Patrick DELAUNAY]

Dear Marek,

> From: Marek Vasut 
> Sent: samedi 28 mars 2020 02:02
> 
> Add DT entries, Kconfig entries and board-specific entries to configure
> FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot.
> 
> Signed-off-by: Marek Vasut 
> Cc: Patrick Delaunay 
> Cc: Patrice Chotard 
> ---
> V2: Configure FMC2 nCS4 for SRAM as well
> V3: Adjust the register macros
> V4: Use more macros
> ---

Reviewed-by: Patrick Delaunay 

Thanks

Patrick

[PATCH] ARM: stm32: Enable bootd, iminfo, imxtract on ST defconfig

[Patrick Delaunay]

Enable these standard U-Boot commands for image manipulation and for
starting the default boot command using 'boot' command in U-Boot shell.

Cc: Marek Vasut 
Cc: Patrice Chotard 
Signed-off-by: Patrick Delaunay 
---

 configs/stm32mp15_basic_defconfig   | 3 ---
 configs/stm32mp15_trusted_defconfig | 3 ---
 2 files changed, 6 deletions(-)

diff --git a/configs/stm32mp15_basic_defconfig 
b/configs/stm32mp15_basic_defconfig
index 6d82365348..c8f1780cab 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -21,10 +21,7 @@ CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x8
 CONFIG_SYS_PROMPT="STM32MP> "
-# CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 CONFIG_CMD_MEMINFO=y
diff --git a/configs/stm32mp15_trusted_defconfig 
b/configs/stm32mp15_trusted_defconfig
index 6928e9a65c..82a8b709cd 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -9,10 +9,7 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
 CONFIG_SYS_PROMPT="STM32MP> "
-# CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 CONFIG_CMD_MEMINFO=y
-- 
2.17.1

[PATCH] efi_loader: function descriptions efi_watchdog.c

[Heinrich Schuchardt]

Correct function descriptions in efi_watchdog.c.
Add the descriptions to the generated HTML documentation.

Signed-off-by: Heinrich Schuchardt 
---
 doc/api/efi.rst   |  6 ++
 lib/efi_loader/efi_watchdog.c | 18 +++---
 2 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/doc/api/efi.rst b/doc/api/efi.rst
index b9c0c6efc5..0667c3aef7 100644
--- a/doc/api/efi.rst
+++ b/doc/api/efi.rst
@@ -78,6 +78,12 @@ Memory services
 .. kernel-doc:: lib/efi_loader/efi_memory.c
:internal:

+SetWatchdogTimer service
+
+
+.. kernel-doc:: lib/efi_loader/efi_watchdog.c
+   :internal:
+
 Runtime services
 

diff --git a/lib/efi_loader/efi_watchdog.c b/lib/efi_loader/efi_watchdog.c
index 6f69b76e4d..61ea0f7926 100644
--- a/lib/efi_loader/efi_watchdog.c
+++ b/lib/efi_loader/efi_watchdog.c
@@ -13,7 +13,9 @@

 static struct efi_event *watchdog_timer_event;

-/*
+/**
+ * efi_watchdog_timer_notify() - resets system upon watchdog event
+ *
  * Reset the system when the watchdog event is notified.
  *
  * @event: the watchdog event
@@ -31,13 +33,13 @@ static void EFIAPI efi_watchdog_timer_notify(struct 
efi_event *event,
EFI_EXIT(EFI_UNSUPPORTED);
 }

-/*
- * Reset the watchdog timer.
+/**
+ * efi_set_watchdog() - resets the watchdog timer
  *
  * This function is used by the SetWatchdogTimer service.
  *
  * @timeout:   seconds before reset by watchdog
- * @return:status code
+ * Return: status code
  */
 efi_status_t efi_set_watchdog(unsigned long timeout)
 {
@@ -53,10 +55,12 @@ efi_status_t efi_set_watchdog(unsigned long timeout)
return r;
 }

-/*
- * Initialize the EFI watchdog.
+/**
+ * efi_watchdog_register() - initializes the EFI watchdog
+ *
+ * This function is called by efi_init_obj_list().
  *
- * This function is called by efi_init_obj_list()
+ * Return: status code
  */
 efi_status_t efi_watchdog_register(void)
 {
--
2.25.1

RE: [PATCH] ARM: stm32: Enable bootd, iminfo, imxtract on DHCOM

[Patrick DELAUNAY]

Dear Marek,

> From: Marek Vasut 
> Sent: mercredi 1 avril 2020 17:13
> 
> Enable these standard U-Boot commands for image manipulation and for starting
> the default boot command using 'boot' command in U-Boot shell.
> 
> Signed-off-by: Marek Vasut 
> Cc: Patrick Delaunay 
> Cc: Patrice Chotard 
> ---

Reviewed-by: Patrick Delaunay 

And I think I will done the same patch on ST defconfig.

Thanks

Patrick

[PATCH 1/1] efi_loader: function descriptions efi_unicode_collation.c

[Heinrich Schuchardt]

Correct function descriptions in efi_unicode_collation.c
Add the Unicode collation protocol to the generated HTML documentation.

Signed-off-by: Heinrich Schuchardt 
---
 doc/api/efi.rst| 6 ++
 lib/efi_loader/efi_unicode_collation.c | 6 ++
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/doc/api/efi.rst b/doc/api/efi.rst
index 631c0ceb1d..b9c0c6efc5 100644
--- a/doc/api/efi.rst
+++ b/doc/api/efi.rst
@@ -151,3 +151,9 @@ Text IO protocols

 .. kernel-doc:: lib/efi_loader/efi_console.c
:internal:
+
+Unicode Collation protocol
+~~
+
+.. kernel-doc:: lib/efi_loader/efi_unicode_collation.c
+   :internal:
diff --git a/lib/efi_loader/efi_unicode_collation.c 
b/lib/efi_loader/efi_unicode_collation.c
index c700be8756..6655c68092 100644
--- a/lib/efi_loader/efi_unicode_collation.c
+++ b/lib/efi_loader/efi_unicode_collation.c
@@ -169,8 +169,8 @@ static bool metai_match(const u16 *string, const u16 
*pattern)
  *case-insenitively
  *
  * @this:  unicode collation protocol instance
- * @s: string to compare
- * @p: pattern string
+ * @string:string to compare
+ * @pattern:   pattern string
  *
  * The pattern string may use these:
  * - * matches >= 0 characters
@@ -199,7 +199,6 @@ static bool EFIAPI efi_metai_match(struct 
efi_unicode_collation_protocol *this,
  *
  * @this:  unicode collation protocol instance
  * @string:string to convert
- * @p: pattern string
  *
  * The conversion is done in place. As long as upper and lower letters use the
  * same number of words this does not pose a problem.
@@ -221,7 +220,6 @@ static void EFIAPI efi_str_lwr(struct 
efi_unicode_collation_protocol *this,
  *
  * @this:  unicode collation protocol instance
  * @string:string to convert
- * @p: pattern string
  *
  * The conversion is done in place. As long as upper and lower letters use the
  * same number of words this does not pose a problem.
--
2.25.1

[PATCH 1/1] efi_loader: add missing doc comments in efi_disk.c

[Heinrich Schuchardt]

Add missing descriptions for functions in efi_disk.c.

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_disk.c | 52 ---
 1 file changed, 49 insertions(+), 3 deletions(-)

diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index fc0682bc48..fd8fe17567 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -108,6 +108,21 @@ static efi_status_t efi_disk_rw_blocks(struct efi_block_io 
*this,
return EFI_SUCCESS;
 }

+/**
+ * efi_disk_read_blocks() - reads blocks from device
+ *
+ * This function implements the ReadBlocks service of the 
EFI_BLOCK_IO_PROTOCOL.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @this:  pointer to the BLOCK_IO_PROTOCOL
+ * @media_id:  id of the medium to be read from
+ * @lba:   starting logical block for reading
+ * @buffer_size:   size of the read buffer
+ * @buffer:pointer to the destination buffer
+ * Return: status code
+ */
 static efi_status_t EFIAPI efi_disk_read_blocks(struct efi_block_io *this,
u32 media_id, u64 lba, efi_uintn_t buffer_size,
void *buffer)
@@ -157,6 +172,22 @@ static efi_status_t EFIAPI efi_disk_read_blocks(struct 
efi_block_io *this,
return EFI_EXIT(r);
 }

+/**
+ * efi_disk_write_blocks() - writes blocks to device
+ *
+ * This function implements the WriteBlocks service of the
+ * EFI_BLOCK_IO_PROTOCOL.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @this:  pointer to the BLOCK_IO_PROTOCOL
+ * @media_id:  id of the medium to be written to
+ * @lba:   starting logical block for writing
+ * @buffer_size:   size of the write buffer
+ * @buffer:pointer to the source buffer
+ * Return: status code
+ */
 static efi_status_t EFIAPI efi_disk_write_blocks(struct efi_block_io *this,
u32 media_id, u64 lba, efi_uintn_t buffer_size,
void *buffer)
@@ -208,9 +239,22 @@ static efi_status_t EFIAPI efi_disk_write_blocks(struct 
efi_block_io *this,
return EFI_EXIT(r);
 }

+/**
+ * efi_disk_flush_blocks() - flushes modified data to the device
+ *
+ * This function implements the FlushBlocks service of the
+ * EFI_BLOCK_IO_PROTOCOL.
+ *
+ * As we always write synchronously nothing is done here.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @this:  pointer to the BLOCK_IO_PROTOCOL
+ * Return: status code
+ */
 static efi_status_t EFIAPI efi_disk_flush_blocks(struct efi_block_io *this)
 {
-   /* We always write synchronously */
EFI_ENTRY("%p", this);
return EFI_EXIT(EFI_SUCCESS);
 }
@@ -286,7 +330,7 @@ static int efi_fs_exists(struct blk_desc *desc, int part)
return 1;
 }

-/*
+/**
  * efi_disk_add_dev() - create a handle for a partition or disk
  *
  * @parent:parent handle
@@ -295,6 +339,8 @@ static int efi_fs_exists(struct blk_desc *desc, int part)
  * @desc:  internal block device
  * @dev_index: device index for block device
  * @offset:offset into disk for simple partitions
+ * @part:  partition
+ * @disk:  pointer to receive the created handle
  * Return: disk object
  */
 static efi_status_t efi_disk_add_dev(
@@ -381,7 +427,7 @@ static efi_status_t efi_disk_add_dev(
  * Create handles and protocols for the partitions of a block device.
  *
  * @parent:handle of the parent disk
- * @blk_desc:  block device
+ * @desc:  block device
  * @if_typename:   interface type
  * @diskid:device number
  * @pdevname:  device name
--
2.25.1

Re: [PATCHv2] kconfig / kbuild: Re-sync with Linux 4.19

[Tom Rini]

On Fri, Mar 27, 2020 at 11:46:27AM -0400, Tom Rini wrote:

> Align Kconfig and Kbuild logic to Linux 4.19 release with minimal impact
> on files outside of this scope.
> 
> Our previous Kconfig sync was done by commit 5972ff077e0f ("kconfig /
> kbuild: re-sync with Linux 4.18").
> 
> In this particular re-sync in order to keep clang support working a
> number of related changes needed to be pulled in that had been missed
> previously.  Not all of these changes we easily traceable and so have
> been omitted from the list below.
> 
> The imported Linux commits are:
> [From prior to v4.18]
> 9f3f1fd29976 kbuild: Add __cc-option macro
> d7f14c66c273 kbuild: Enable Large File Support for hostprogs
> 6d79a7b424a5 kbuild: suppress warnings from 'getconf LFS_*'
> 24403874316a Shared library support
> 86a9df597cdd kbuild: fix linker feature test macros when cross compiling with 
> Clang
> 0294e6f4a000 kbuild: simplify ld-option implementation
> 
> [From v4.18 to v4.19]
> 96f14fe738b6 kbuild: Rename HOSTCFLAGS to KBUILD_HOSTCFLAGS
> 10844aebf448 kbuild: Rename HOSTCXXFLAGS to KBUILD_HOSTCXXFLAGS
> b90a368000ab kbuild: Rename HOSTLDFLAGS to KBUILD_HOSTLDFLAGS
> 8377bd2b9ee1 kbuild: Rename HOST_LOADLIBES to KBUILD_HOSTLDLIBS
> f92d19e0ef9b kbuild: Use HOST*FLAGS options from the command line
> 4ab3b80159d4 kconfig: check for pkg-config on make {menu,n,g,x}config
> 693359f7ac90 kconfig: rename SYMBOL_AUTO to SYMBOL_NO_WRITE
> f60b992e30ff kbuild: replace $(LDFLAGS) $(ldflags-y) with $(ld_flags)
> 2fb9279f2c3e kbuild: change ld_flags to contain LDFLAGS_$(@F)
> c931d34ea085 arm64: build with baremetal linker target instead of Linux when 
> available
> 5accd7f3360e kconfig: handle format string before calling 
> conf_message_callback()
> a2ff4040151a kconfig: rename file_write_dep and move it to confdata.c
> 0608182ad542 kconfig: split out useful helpers in confdata.c
> adc18acf42a1 kconfig: remove unneeded directory generation from local*config
> 79123b1389cc kconfig: create directories needed for syncconfig by itself
> 16952b77d8b5 kconfig: make syncconfig update .config regardless of 
> sym_change_count
> d6c6ab93e17f kbuild: remove deprecated host-progs variable
> 56869d45e364 kconfig: fix the rule of mainmenu_stmt symbol
> c151272d1687 kconfig: remove unused sym_get_env_prop() function
> 1880861226c1 kconfig: remove P_ENV property type
> e3fd9b5384f3 scripts/dtc: consolidate include path options in Makefile
> 4bf6a9af0e91 kconfig: add build-only configurator targets
> f1575595d156 kconfig: error out when seeing recursive dependency
> 5e8c5299d315 kconfig: report recursive dependency involving 'imply'
> f498926c47aa kconfig: improve the recursive dependency report
> 98a4afbfafd2 kconfig: fix "Can't open ..." in parallel build
> 9a9ddcf47831 kconfig: suppress "configuration written to .config" for 
> syncconfig
> 87a32e624037 kbuild: pass LDFLAGS to recordmcount.pl
> d503ac531a52 kbuild: rename LDFLAGS to KBUILD_LDFLAGS
> 217c3e019675 disable stringop truncation warnings for now
> bc8d2e20a3eb kconfig: remove a spurious self-assignment
> fd65465b7016 kconfig: do not require pkg-config on make {menu,n}config
> 5a4630aadb9a ftrace: Build with CPPFLAGS to get -Qunused-arguments
> 
> Note that this adds new cleanup work to do in that we should adapt the
> shared library support we have to what is now upstream.
> 
> Signed-off-by: Tom Rini 
> Reviewed-by: Masahiro Yamada 

Applied to u-boot/next, thanks!

-- 
Tom


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Description: PGP signature

RE: [PATCH 2/3] arm: caches: add DCACHE_DEFAULT_OPTION

[Patrick DELAUNAY]

Hi Marek,

> From: Marek Vasut 
> Sent: vendredi 10 avril 2020 10:14
> 
> On 4/9/20 8:06 PM, Patrick DELAUNAY wrote:
> > Dear Marek,
> 
> Hi,
> 
> >> Sent: jeudi 9 avril 2020 12:21
> >> To: Patrick DELAUNAY ; u-boot@lists.denx.de
> >>
> >> On 4/9/20 12:01 PM, Patrick DELAUNAY wrote:
> >>> Dear Marek,
> >>
> >> Hi,
> >>
>  From: Uboot-stm32
>  
>  On Behalf Of Patrick DELAUNAY
> 
>  Dear Marek,
> 
> > From: Marek Vasut 
> > Sent: vendredi 3 avril 2020 23:29
> >
> > On 4/3/20 10:28 AM, Patrick Delaunay wrote:
> >> Add the new flags DCACHE_DEFAULT_OPTION to define the default
> >> option to use according the compilation flags
> >> CONFIG_SYS_ARM_CACHE_WRITETHROUGH or
> > CONFIG_SYS_ARM_CACHE_WRITEALLOC.
> >
> > Can't you unify these macros into a single Kconfig "select"
> > statement instead , and then just select the matching cache
> > configuration in
> >> Kconfig ?
> 
>  Yes I will try, with 2 steps
>  - migrate existing CONFIG_SYS_ARM_CACHE_ in Kconfig
> >>>
> >>> First step done...
> >>> I will push it as a separate patchset I think.
> >>>
>  - add new option CONFIG_SYS_ARM_CACHE_OPTION
> >>>
> >>> In fact it is to difficult to use select because each defines
> >>> DCACHE_XXX value can have several values
> >>>
> >>> they are build according CONFIG_ARM64 / LPAE
> >>>
> >>> But, I can't use this define in Kconfig
> >>>
> >>> I try :
> >>> optionARM_OPTION
> >>>   int "option"
> >>>   default DCACHE_WRITETHROUGHT if
> >> CONFIG_SYS_ARM_CACHE_WRITETHROUGH
> >>>   default DCACHE_ WRITEALLOC if CONFIG_SYS_ARM_CACHE_
> >> WRITEALLOC
> >>>   default DCACHE_WRITEBACK if
> >> CONFIG_SYS_ARM_CACHE_WRITEBACK
> >>>
> >>> int and hex is invalid, and string can't be use with "".
> >>>
> >>> And I don't found way to build it automatically when option is activated.
> >>>
> >>> Any idea ?
> >>
> >> Maybe you can have a select in the Kconfig to set some differently
> >> named option, e.g.
> >>
> >> DCACHE_MODE_WRITE{THROUGH,ALLOC,BACK}
> >>
> >> and then an ifdef in some header file, e.g.
> >>
> >> #ifdef CONFIG_DCACHE_MODE_WRITETHROUGH #define
> ARM_CACHE_MODE
> >> DCACHE_WRITETHROUGH ...
> >>
> >> And then use ARM_CACHE_MODE where you need a value and
> >> CONFIG_DCACHE_MODE{...} where you need a config option check.
> >>
> >> Does this work ?
> >
> > I try with string and default (as select is allowed on for bolean or
> > trisate), And I failed :-<
> >
> > I don't found a way to have the de-stringficate the KConfig option to
> > generated the correct define
> 
> The result is a boolean , isn't it ? One out of N configs ends up being 
> defined and
> the rest are not defined.
> 
> > config SYS_ARM_CACHE_POLICY
> > string "Name of the ARM data write cache policy"
> > default WRITEBACK if SYS_ARM_CACHE_WRITEBACK
> > default WRITETHROUGH if SYS_ARM_CACHE_WRITEBACK
> > default WRITEALLOC if SYS_ARM_CACHE_WRITEALLOC
> >
> > #define DCACHE_DEFAULT_OPTION   DCACHE_ ##
> CONFIG_SYS_ARM_CACHE_POLICY
> >
> > => error: ‘DCACHE_CONFIG_SYS_ARM_CACHE_POLICY’ undeclared (first
> use in this function); did you mean ‘CONFIG_SYS_ARM_CACHE_POLICY’?
> >
> > #define DCACHE_OPTION(s)DCACHE_ ##
> CONFIG_SYS_ARM_CACHE_POLICY
> >
> > #define DCACHE_DEFAULT_OPTION
>   DCACHE_OPTION(CONFIG_SYS_ARM_CACHE_POLICY)
> >
> > arch/arm/include/asm/system.h:488:26: error: ‘DCACHE_’ undeclared (first use
> in this function); did you mean ‘DCACHE_OFF’?
> > arch/arm/lib/cache-cp15.c:99:25: error: expected ‘)’ before string
> > constant
> >
> > The stringification is possible but not the inverse operation (remove the 
> > quote)...
> >
> > In my .config, CONFIG_SYS_ARM_CACHE_POLICY="WRITEBACK"
> 
> What about this:
> 
> choice
> prompt "Cache policy"
>  default CACHE_WRITEBACK
> 
> config CACHE_WRITEBACK
>  bool "Writeback"
> 
> config ...
> 
> endchoice
> 
> and then in some header
> 
> #ifdef CONFIG_CACHE_WRITEBACK
> #define CONFIF_SYS_ARM_CACHE_WRITEBACK
> #else
> ...
> 
> Would that work ?

Yes, it can work it seems complicated

I push v2 for CONFIG_SYS_ARM_CACHE_* migration in Kconfig

My proposal becomes:

+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+#define DCACHE_DEFAULT_OPTION  DCACHE_WRITETHROUGH
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+#define DCACHE_DEFAULT_OPTION  DCACHE_WRITEALLOC
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
+#define DCACHE_DEFAULT_OPTION  DCACHE_WRITEBACK
+#endif
+

I think it is is more clear solution.


I can use macro magic to build DCACHE_DEFAULT_OPTION 

+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+#define ARM_CACHE_POLICY   WRITETHROUGH
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+#define ARM_CACHE_POLICY   WRITEALLOC
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
+#define ARM_CACHE_POLICY   WRITEBACK
+#endif
 
+#define _DCACHE_OPTION(policy) DCACHE_ ## policy
+#define DCACHE_OPTION(policy)  _DCACHE_OPTION(policy)
+#define DCACHE_DEFAULT_OPTION  

[PATCH 3/3] rmobile: rcar: removed used CONFIG_SYS_RCAR_I2C*_BASE

[Patrick Delaunay]

As this "CONFIG" are never used, CONFIG_SYS_RCAR_I2C*_BASE can
be removed without effect and the file config_whitelist.txt is
also clean-up.

Signed-off-by: Patrick Delaunay 
---

 arch/arm/mach-rmobile/include/mach/rcar-base.h | 6 --
 scripts/config_whitelist.txt   | 4 
 2 files changed, 10 deletions(-)

diff --git a/arch/arm/mach-rmobile/include/mach/rcar-base.h 
b/arch/arm/mach-rmobile/include/mach/rcar-base.h
index a20740679f..811a1183ba 100644
--- a/arch/arm/mach-rmobile/include/mach/rcar-base.h
+++ b/arch/arm/mach-rmobile/include/mach/rcar-base.h
@@ -78,12 +78,6 @@
 #define CONFIG_SYS_I2C_SH_BASE00xE650
 #define CONFIG_SYS_I2C_SH_BASE10xE651
 
-/* RCAR-I2C */
-#define CONFIG_SYS_RCAR_I2C0_BASE  0xE6508000
-#define CONFIG_SYS_RCAR_I2C1_BASE  0xE6518000
-#define CONFIG_SYS_RCAR_I2C2_BASE  0xE653
-#define CONFIG_SYS_RCAR_I2C3_BASE  0xE654
-
 /* SDHI */
 #define CONFIG_SYS_SH_SDHI0_BASE   0xEE10
 
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 0f747ac0a3..0f9d8cb0d7 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3668,10 +3668,6 @@ CONFIG_SYS_QRIO_BR_PRELIM
 CONFIG_SYS_QRIO_OR_PRELIM
 CONFIG_SYS_R7780MP_OLD_FLASH
 CONFIG_SYS_RAMBOOT
-CONFIG_SYS_RCAR_I2C0_BASE
-CONFIG_SYS_RCAR_I2C1_BASE
-CONFIG_SYS_RCAR_I2C2_BASE
-CONFIG_SYS_RCAR_I2C3_BASE
 CONFIG_SYS_RCWH_PCIHOST
 CONFIG_SYS_READ_SPD
 CONFIG_SYS_RESET_ADDR
-- 
2.17.1

[PATCH 1/3] cosmetic: README: Fix one CONFIG name

[Patrick Delaunay]

Only replace CONFIF_ by CONFIG_

Signed-off-by: Patrick Delaunay 
---

 README | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README b/README
index 8cfa92fac9..6cb7656fa0 100644
--- a/README
+++ b/README
@@ -1640,7 +1640,7 @@ The following options need to be configured:
  - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
  - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
  - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
- - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
+ - CONFIG_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
 
- drivers/i2c/sh_i2c.c:
  - activate this driver with CONFIG_SYS_I2C_SH
-- 
2.17.1

[PATCH 2/3] README: remove references on no more used config CONFIG_SYS_RCAR_I2C*

[Patrick Delaunay]

Remove the references in README on CONFIG_SYS_RCAR_I2C_* not use
in U-Boot drivers/i2c/rcar_i2c.c, since commit a4d9aafadb31 ("i2c:
 rcar_i2c: Remove the driver") and commit a06a0ac36d59 ("i2c: rcar_i2c:
 Add DM and DT capable I2C driver")

Checked by the command: grep -r SYS_RCAR_I2C *
And these CONFIG are only defined in
arch/arm/mach-rmobile/include/mach/rcar-base.h

Signed-off-by: Patrick Delaunay 
---

 README | 10 --
 1 file changed, 10 deletions(-)

diff --git a/README b/README
index 6cb7656fa0..3cc99f0805 100644
--- a/README
+++ b/README
@@ -1632,16 +1632,6 @@ The following options need to be configured:
  - activate this driver with CONFIG_SYS_I2C_RCAR
  - This driver adds 4 i2c buses
 
- - CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0
- - CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0
- - CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1
- - CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1
- - CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2
- - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
- - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
- - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
- - CONFIG_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
-
- drivers/i2c/sh_i2c.c:
  - activate this driver with CONFIG_SYS_I2C_SH
  - This driver adds from 2 to 5 i2c buses
-- 
2.17.1

[PATCH v2] configs: migrate CONFIG_SYS_ARM_CACHE_* in Kconfig

[Patrick Delaunay]

Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and
CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py.

Kconfig uses a choice between the 3 values supported in U-Boot,
including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK
(the default configuration).

The patch also avoids to select simultaneously 2 configurations.

Signed-off-by: Patrick Delaunay 
---

Changes in v2:
- default SYS_ARM_CACHE_WRITETHROUGH if CPU_PXA || RZA1
  and remove defconfig impacts for grpeach and colibri_pxa270

 arch/arm/Kconfig| 28 +
 arch/arm/include/asm/iproc-common/configs.h |  1 -
 include/configs/grpeach.h   |  1 -
 include/configs/pxa-common.h|  2 --
 scripts/config_whitelist.txt|  1 -
 5 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bbb1e2738b..f2bffddb44 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -340,6 +340,34 @@ config SYS_CACHELINE_SIZE
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
 
+choice
+   prompt "Select the ARM data write cache policy"
+   default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
+ TARGET_BCMNSP || CPU_PXA || RZA1
+   default SYS_ARM_CACHE_WRITEBACK
+
+config SYS_ARM_CACHE_WRITEBACK
+   bool "Write-back (WB)"
+   help
+ A write updates the cache only and marks the cache line as dirty.
+ External memory is updated only when the line is evicted or explicitly
+ cleaned.
+
+config SYS_ARM_CACHE_WRITETHROUGH
+   bool "Write-through (WT)"
+   help
+ A write updates both the cache and the external memory system.
+ This does not mark the cache line as dirty.
+
+config SYS_ARM_CACHE_WRITEALLOC
+   bool "Write allocation (WA)"
+   help
+ A cache line is allocated on a write miss. This means that executing a
+ store instruction on the processor might cause a burst read to occur.
+ There is a linefill to obtain the data for the cache line, before the
+ write is performed.
+endchoice
+
 config ARCH_CPU_INIT
bool "Enable ARCH_CPU_INIT"
help
diff --git a/arch/arm/include/asm/iproc-common/configs.h 
b/arch/arm/include/asm/iproc-common/configs.h
index 96c4f54f4a..4733c0793c 100644
--- a/arch/arm/include/asm/iproc-common/configs.h
+++ b/arch/arm/include/asm/iproc-common/configs.h
@@ -10,7 +10,6 @@
 
 /* Architecture, CPU, chip, etc */
 #define CONFIG_IPROC
-#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 
 /* Memory Info */
 #define CONFIG_SYS_SDRAM_BASE  0x6100
diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index b875f9b132..af5b92443e 100644
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -16,7 +16,6 @@
 
 /* Miscellaneous */
 #define CONFIG_SYS_PBSIZE  256
-#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 #define CONFIG_CMDLINE_TAG
 
 /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h
index e25800a095..2632d48cc9 100644
--- a/include/configs/pxa-common.h
+++ b/include/configs/pxa-common.h
@@ -8,8 +8,6 @@
 #ifndef__CONFIG_PXA_COMMON_H__
 #define__CONFIG_PXA_COMMON_H__
 
-#defineCONFIG_SYS_ARM_CACHE_WRITETHROUGH
-
 /*
  * KGDB
  */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 6908431d03..0f747ac0a3 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1773,7 +1773,6 @@ CONFIG_SYS_AMASK4
 CONFIG_SYS_AMASK5
 CONFIG_SYS_AMASK6
 CONFIG_SYS_AMASK7
-CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 CONFIG_SYS_AT91_CPU_NAME
 CONFIG_SYS_AT91_MAIN_CLOCK
 CONFIG_SYS_AT91_PLLA
-- 
2.17.1

Please pull u-boot-dm

[Simon Glass]

Hi Tom,

(final?) fixes for DM

The following changes since commit dfd5321becc54d7ce9fd564aaaba70a2132c058e:

  Merge tag 'u-boot-imx-20200408' of
https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-04-08
12:06:39 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-dm.git tags/dm-pull9apr20

for you to fetch changes up to 2ca38ecc1c427d41db92c624cbf6d343df74:

  dm: dump.c: Refactor dm_dump_drivers prints (2020-04-09 15:12:34 -0600)


Fixes segfault in 'dm drivers' command


Ovidiu Panait (2):
  dm: dump.c: Fix segfault when entry->of_match is NULL
  dm: dump.c: Refactor dm_dump_drivers prints

 drivers/core/dump.c | 17 +++--
 1 file changed, 11 insertions(+), 6 deletions(-)

Regards,
Simon

RE: [PATCH 3/3] arm: caches: manage phys_addr_t overflow in mmu_set_region_dcache_behaviour

[Patrick DELAUNAY]

Dear Marek

> From: Marek Vasut 
> Sent: vendredi 10 avril 2020 10:06
> 
> On 4/9/20 4:18 PM, Patrick DELAUNAY wrote:
> >
> >
> >> -Original Message-
> >> From: Marek Vasut 
> >> Sent: vendredi 3 avril 2020 23:31
> >> To: Patrick DELAUNAY ; u-boot@lists.denx.de
> >> Cc: Simon Glass ; Alexey Brodkin
> >> ; Lokesh Vutla ; Tom Rini
> >> ; Trevor Woerner ; U-Boot
> >> STM32 
> >> Subject: Re: [PATCH 3/3] arm: caches: manage phys_addr_t overflow in
> >> mmu_set_region_dcache_behaviour
> >> Importance: High
> >>
> >> On 4/3/20 10:28 AM, Patrick Delaunay wrote:
> >>> Detect and solve the overflow on phys_addr_t type for start + size
> >>> in
> >>> mmu_set_region_dcache_behaviour() function.
> >>>
> >>> This issue occurs for example with ARM32, start = 0xC000 and
> >>> size = 0x4000: start + size = 0x1 and end = 0x0.
> >>>
> >>> Overflow is detected when end < start.
> >>> In normal case the previous behavior is still used: when start is
> >>> not aligned on MMU section, the end address is only aligned after
> >>> the sum start + size.
> >>>
> >>> Signed-off-by: Patrick Delaunay 
> >>> ---
> >>>
> >>>  arch/arm/lib/cache-cp15.c | 5 +
> >>>  1 file changed, 5 insertions(+)
> >>>
> >>> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> >>> index d15144188b..e5a7fd0ef4 100644
> >>> --- a/arch/arm/lib/cache-cp15.c
> >>> +++ b/arch/arm/lib/cache-cp15.c
> >>> @@ -63,6 +63,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t
> >>> start, size_t size,
> >>>
> >>>   end = ALIGN(start + size, MMU_SECTION_SIZE) >>
> >> MMU_SECTION_SHIFT;
> >>>   start = start >> MMU_SECTION_SHIFT;
> >>> +
> >>> + /* phys_addr_t overflow detected */
> >>> + if (end < start)
> >>> + end = (~(phys_addr_t)0x0 >> MMU_SECTION_SHIFT) + 1;
> >>> +
> >>
> >> Or, you can divide $start and $size separately by MMU_SECTION_SIZE
> >> and then add them up .
> >
> > It was my first idea but that change the function behavior, because
> > today start and size can be not aligned on MMU_SECTION aligned.
> >
> > I think it is strange, but I preferred to don't change this part.
> >
> > Example with shift = 21 and 2MB section size: 0x20
> >
> > Start = 0x100
> > Size = 0x100
> >
> > End = 0x200
> >
> > => after alignment start = 0x0, end = 0x1
> >
> > But if we align the start and size before addition as proposed, the
> > final result change
> >
> > Start = 0x100 => 0
> > Size = 0x100 => 0
> >
> > End = 0x0
> >
> > I prefer don't modify this current (strange) behavior to avoid regression.
> >
> > But if it is acceptable (because the caller MUST always use start and
> > size MMU_SECTION aligned), I will change the proposal
> 
> The minimum page size is 4k, right ? Then divide both by 4k and then by the 
> rest
> of MMU_SECTION_SHIFT.

Yes, good idea...
I am waiting possible other feedbacks

but I think ii ts candidate to integrate V2.

Patrick

Re: [PULL] MIPS fixes for v2020.04

[Tom Rini]

On Thu, Apr 09, 2020 at 11:26:43PM +0200, Daniel Schwierzeck wrote:

> Hi Tom,
> 
> actually I've prepared this pull reuqest some weeks ago but was quite busy
> since then to finally send it. This is just small stuff whcih can't break
> anything. It would be great if you could sqeeze it in the release, thanks.
> 
> Gitlab: https://gitlab.denx.de/u-boot/custodians/u-boot-mips/pipelines/2695
> Travis CI: 
> https://travis-ci.org/github/danielschwierzeck/u-boot/builds/673086037
> 
> 
> The following changes since commit dfd5321becc54d7ce9fd564aaaba70a2132c058e:
> 
>   Merge tag 'u-boot-imx-20200408' of 
> https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-04-08 12:06:39 
> -0400)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-mips.git tags/mips-fixes-for-2020.04
> 
> for you to fetch changes up to fb9acad30562177287d8cffec19e5dfa6f072de7:
> 
>   mips: cmd: go: Flush cache before jumping to app/image (2020-04-09 19:00:00 
> +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Description: PGP signature

Re: [PATCH] usb: Keep async schedule running only across mass storage xfers

[Tom Rini]

On Fri, Apr 10, 2020 at 08:21:20AM +0200, Lukasz Majewski wrote:
> On Thu, 9 Apr 2020 19:23:26 -0400
> Tom Rini  wrote:
> 
> > On Mon, Apr 06, 2020 at 02:29:44PM +0200, Marek Vasut wrote:
> > 
> > > Rather than keeping the asynchronous schedule running always, keep
> > > it running only across USB mass storage transfers for now, as it
> > > seems that keeping it running all the time interferes with certain
> > > control transfers during device enumeration.
> > > 
> > > Note that running the async schedule all the time should not be an
> > > issue, especially on EHCI HCD, as that one implements most of the
> > > transfers using async schedule.
> > > 
> > > Note that we have usb_disable_asynch(), which however is utterly
> > > broken. The usb_disable_asynch() blocks the USB core from doing
> > > async transfers by setting a global flag. The async schedule should
> > > however be disabled per USB controller. Moreover, setting a global
> > > flag does not prevent the controller from using the async schedule,
> > > which e.g. the EHCI HCD does.
> > > 
> > > This patch implements additional callback to the controller, which
> > > permits it to lock the async schedule and keep it running across
> > > multiple transfers. Once the schedule is unlocked, it must also be
> > > disabled. This thus prevents the async schedule from running outside
> > > of the USB mass storage transfers.
> > > 
> > > Signed-off-by: Marek Vasut 
> > > Cc: Lukasz Majewski 
> > > Cc: Tom Rini 
> > > Tested-by: Tom Rini  [omap3_beagle, previously
> > > failing]  
> > 
> > Applied to u-boot/master, thanks!
> > 
> 
> It is a really short time between posting the patch (Monday) and being
> applied (midnight on Friday).
> 
> It is the Pre-Easter period with some other world-wide issues... and not
> all of us have enough time now to review and test patches.

So, I took this patch at this point in the cycle as it fixes a
regression that we've had reported for a while and because the custodian
asked me to grab it directly.  All things considered, it is unlikely to
make the situation worse and may fix some of the other regressions we've
had in the area.  Thanks!

-- 
Tom


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[PATCH v8 20/21] doc: riscv: Add documentation for Sipeed Maix Bit

[Sean Anderson]

This patch adds documentation for the Sipeed Maix bit, and more generally
for the Kendryte K210 processor.

Signed-off-by: Sean Anderson 
---

Changes in v7:
- Split off into its own patch
- Fix size of clint


 doc/board/index.rst|   1 +
 doc/board/sipeed/index.rst |   9 ++
 doc/board/sipeed/maix.rst  | 298 +
 3 files changed, 308 insertions(+)
 create mode 100644 doc/board/sipeed/index.rst
 create mode 100644 doc/board/sipeed/maix.rst

diff --git a/doc/board/index.rst b/doc/board/index.rst
index 51a2ae6f28..dcc47c5a21 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -16,6 +16,7 @@ Board-specific doc
renesas/index
rockchip/index
sifive/index
+   sipeed/index
st/index
toradex/index
xilinx/index
diff --git a/doc/board/sipeed/index.rst b/doc/board/sipeed/index.rst
new file mode 100644
index 00..3518e2d8f4
--- /dev/null
+++ b/doc/board/sipeed/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Sipeed
+==
+
+.. toctree::
+   :maxdepth: 2
+
+   maix
diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst
new file mode 100644
index 00..5f7018da28
--- /dev/null
+++ b/doc/board/sipeed/maix.rst
@@ -0,0 +1,298 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2020 Sean Anderson 
+
+Maix Bit
+
+
+Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor,
+a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate
+neural network processing and other "ai" tasks. This includes a "KPU" neural
+network processor, an audio processor supporting beamforming reception, and a
+digital video port supporting capture and output at VGA resolution. Other
+peripherals include 8M of SRAM (accessible with and without caching); 
remappable
+pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller;
+and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi 
flash;
+on-board usb-serial bridges; ports for cameras, displays, and sd cards; and
+ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but
+the boards are fairly similar.
+
+Documentation for Maix boards is available from
+`Sipeed's website `_.
+Documentation for the Kendryte K210 is available from
+`Kendryte's website `_. However, hardware
+details are rather lacking, so most technical reference has been taken from the
+`standalone sdk `_.
+
+Build and boot steps
+
+
+To build u-boot, run
+
+.. code-block:: none
+
+make sipeed_maix_bitm_defconfig
+make CROSS_COMPILE=
+
+To flash u-boot to a maix bit, run
+
+.. code-block:: none
+
+kflash -tp /dev/ -B bit_mic u-boot-dtb.bin
+
+Boot output should look like the following:
+
+.. code-block:: none
+
+U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
+
+DRAM:  8 MiB
+In:serial@3800
+Out:   serial@3800
+Err:   serial@3800
+=>
+
+Loading Images
+^^
+
+To load a kernel, transfer it over serial.
+
+.. code-block:: none
+
+=> loady 8000 150
+## Switch baudrate to 150 bps and press ENTER ...
+
+*** baud: 150
+
+*** baud: 150 ***
+## Ready for binary (ymodem) download to 0x8000 at 150 bps...
+C
+*** file: loader.bin
+$ sz -vv loader.bin
+Sending: loader.bin
+Bytes Sent:2478208   BPS:72937
+Sending:
+Ymodem sectors/kbytes sent:   0/ 0k
+Transfer complete
+
+*** exit status: 0 ***
+## Total Size  = 0x0025d052 = 2478162 Bytes
+## Switch baudrate to 115200 bps and press ESC ...
+
+*** baud: 115200
+
+*** baud: 115200 ***
+=>
+
+Running Programs
+
+
+Binaries
+
+
+To run a bare binary, use the ``go`` command:
+
+.. code-block:: none
+
+=> loady
+## Ready for binary (ymodem) download to 0x8000 at 115200 bps...
+C
+*** file: ./examples/standalone/hello_world.bin
+$ sz -vv ./examples/standalone/hello_world.bin
+Sending: hello_world.bin
+Bytes Sent:   4864   BPS:649
+Sending:
+Ymodem sectors/kbytes sent:   0/ 0k
+Transfer complete
+
+*** exit status: 0 ***
+(CAN) packets, 5 retries
+## Total Size  = 0x12f8 = 4856 Bytes
+=> go 8000
+## Starting application at 0x8000 ...
+Example expects ABI version 9
+Actual U-Boot ABI version 9
+Hello World
+argc = 1
+argv[0] = "8000"
+argv[1] = ""
+Hit any key to exit ...
+
+Legacy Images
+"
+
+To run legacy images, use the ``bootm`` command:
+
+.. code-block:: none
+
+$ tools/mkimage -A riscv -O u-boot -T standalone -C none -a 8000 -e 
8000 -d examples/standalone/hello_world.bin hello_world.img
+Image Name:
+Created:  Thu Mar  5 12:04:10 2020
+Image Type:   RISC-V U-Boot 

[PATCH v8 17/21] riscv: Try to get cpu frequency from a "clocks" node if it exists

[Sean Anderson]

Instead of always using the "clock-frequency" property to determine cpu
frequency, try using a clock in "clocks" if it exists. This patch also
fixes a bug where there could be spurious higher frequencies if sizeof(u32)
!= sizeof(ulong).

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---
This patch was previously sumbitted on its own as
https://patchwork.ozlabs.org/patch/1232420/

This patch is the combination of the patches
https://patchwork.ozlabs.org/patch/1223933/
https://patchwork.ozlabs.org/patch/1224957/
"riscv: Fix incorrect cpu frequency on RV64"
"riscv: Try to get cpu frequency from device tree"

Changes in v5:
- Include linux/err.h explicitly
- Reword commit message

Changes in v4:
- New


 drivers/cpu/riscv_cpu.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 28ad0aa30f..c6ed060abc 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -3,12 +3,14 @@
  * Copyright (C) 2018, Bin Meng 
  */
 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -27,9 +29,24 @@ static int riscv_cpu_get_desc(struct udevice *dev, char 
*buf, int size)
 
 static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
 {
+   int ret;
+   struct clk clk;
const char *mmu;
 
-   dev_read_u32(dev, "clock-frequency", (u32 *)>cpu_freq);
+   /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */
+   info->cpu_freq = 0;
+
+   /* First try getting the frequency from the assigned clock */
+   ret = clk_get_by_index(dev, 0, );
+   if (!ret) {
+   ret = clk_get_rate();
+   if (!IS_ERR_VALUE(ret))
+   info->cpu_freq = ret;
+   clk_free();
+   }
+
+   if (!info->cpu_freq)
+   dev_read_u32(dev, "clock-frequency", (u32 *)>cpu_freq);
 
mmu = dev_read_string(dev, "mmu-type");
if (!mmu)
-- 
2.25.1

[PATCH v8 19/21] riscv: Add device tree for K210 and Sipeed Maix BitM

[Sean Anderson]

Where possible, I have tried to find compatible drivers based on the layout
of registers. However, many devices remain untested. All untested devices
have been left disabled, but some tentative properties (such as compatible
strings, and clocks, interrupts, and resets properties) have been added.

Signed-off-by: Sean Anderson 
---

Changes in v7:
- Move clocks node to be just before soc node, matching linux's tree
- Merge memory nodes into one node with different registers
- Add aliases for uclasses which use them
- Fix size of clint

Changes in v6:
- Remove spi, gpio, pinmux, wdt, and led bindings
- Use consistent capitalization for hex digits

Changes in v5:
- Add more compatible strings
- Add cache line size
- Document CPUs as rocket cores
- Flesh out the gpio devices
- Add ports for audio and video devices
- Add fpioa pinctrl support
- Configure pins for MMC on SPI1
- Enable MMC
- Fix a couple uart properties (Thanks laanwj)
- Reorder ram now that relocation is handled with CONFIG_SYS defines
- Enable WDT
- Add pinctrl properties
- Add gpio support
- Add led support
- Add assorted AV bindings
- Add compatible strings for ram
- Use GPIO-based CS for MMC
- Limit SPI flash to 50 MHz

Changes in v4:
- Set regs sizes to full address range
- Remove clock-frequency property from cpus
- Add spi-max-frequency to spi devices from documentation
- Add more compatible strings for each device
- Add AI ram as a separate memory bank. Its clock is disabled on boot, and
  it cannot be accessed
- Reorder memory banks so u-boot relocates higher, leaving more room to
  load boot images
- Add designware ssi CTRL0 field shifts to spi devices
- Don't enable the MMC slot
- Update copyright
- Lint

Changes in v3:
- Move this patch to the end of the series
- Add a max frequency for spi3
- Remov unused compatible strings from spi-flash@0
- Add s and u to isa string
- Fix mmu-type
- Remove cache-line size since it is unused (in u-boot) and undocumented
  (upstream)
- Add timer interrupts to clint0
- Round up various registers
- Add riscv,max-priority to plic
- Add apb* busses, since they have clocks which need to be enabled to
  access their devices
- Change uart compatible strings to "snps,dw-apb-uart", since that appears
  to match their registers
- Add compatible string for wdt*
- Add system reset device under sysctl
- Add reset device under sysctl

Changes in v2:
- Model changed to "Sipeed Maix Bit" to match file name
- Value of stdout-path fixed
- SD card slot compatible changed to "mmc-spi-slot"
- "jedec,spi-nor" added to spi flash compatible list
- Aliases for spi busses added
- timebase-frequency divided by 50 to match timer speed
- cpu-frequency renamed to clock-frequency
- CPUX_intc restyled to cpuX_intc
- "kendryte,k210-soc" added to soc compatible list for future-proofing
- PLIC handle renamed to plic0 from pic0
- K210_RST_SOC removed from sysrst, due to not being located in the reset
  register
- K210_RST_* numbers changed to match their bit offset within the reset
  register
- gpio_controller restyled to gpio-controller
- Added a second clock to the dma binding to match what the driver expects
- Changed "snps,designware-spi" compatible string to "snps,dw-apb-ssi" to
  match the correct driver
- Added a name to the spi clocks
- Added reg-io-width property to spi bindings
- Assigned a default parent to K210_CLK_SPI3
- Removed assigned clocks for ACLK and PLLs
- Removed u-boot,dm-pre-reloc bindings

 arch/riscv/dts/Makefile |   1 +
 arch/riscv/dts/k210-maix-bit.dts|  47 ++
 arch/riscv/dts/k210.dtsi| 594 
 include/dt-bindings/reset/k210-sysctl.h |  38 ++
 4 files changed, 680 insertions(+)
 create mode 100644 arch/riscv/dts/k210-maix-bit.dts
 create mode 100644 arch/riscv/dts/k210.dtsi
 create mode 100644 include/dt-bindings/reset/k210-sysctl.h

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 4f30e6936f..3a6f96c67d 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
 
 dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts
new file mode 100644
index 00..5b32c5fd5f
--- /dev/null
+++ b/arch/riscv/dts/k210-maix-bit.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson 
+ */
+
+/dts-v1/;
+
+#include "k210.dtsi"
+
+#include 
+
+/ {
+   model = "Sipeed Maix Bit 2.0";
+   compatible = "sipeed,maix-bitm", "sipeed,maix-bit", "kendryte,k210";
+
+   chosen {
+   stdout-path = "serial0:115200";
+   };
+
+   sound {
+   compatible = "simple-audio-card";
+   simple-audio-card,format = "i2s";
+   status = "disabled";
+
+   simple-audio-card,cpu {
+  

[PATCH v8 18/21] riscv: Enable cpu clock if it is present

[Sean Anderson]

The cpu clock is probably already enabled if we are executing code (though
we could be executing from a different core). This patch prevents the cpu
clock or its parents from being disabled.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---
This patch was previously submitted on its own as
https://patchwork.ozlabs.org/patch/1232420/

Changes in v4:
- New


 drivers/cpu/riscv_cpu.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index c6ed060abc..9ce58695aa 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2018, Bin Meng 
+ * Copyright (C) 2020, Sean Anderson 
  */
 
 #include 
@@ -117,6 +118,24 @@ static int riscv_cpu_bind(struct udevice *dev)
return 0;
 }
 
+static int riscv_cpu_probe(struct udevice *dev)
+{
+   int ret = 0;
+   struct clk clk;
+
+   /* Get a clock if it exists */
+   ret = clk_get_by_index(dev, 0, );
+   if (ret)
+   return 0;
+
+   ret = clk_enable();
+   clk_free();
+   if (ret == -ENOSYS || ret == -ENOTSUPP)
+   return 0;
+   else
+   return ret;
+}
+
 static const struct cpu_ops riscv_cpu_ops = {
.get_desc   = riscv_cpu_get_desc,
.get_info   = riscv_cpu_get_info,
@@ -133,6 +152,7 @@ U_BOOT_DRIVER(riscv_cpu) = {
.id = UCLASS_CPU,
.of_match = riscv_cpu_ids,
.bind = riscv_cpu_bind,
+   .probe = riscv_cpu_probe,
.ops = _cpu_ops,
.flags = DM_FLAG_PRE_RELOC,
 };
-- 
2.25.1

[PATCH v8 16/21] riscv: Allow use of reset drivers

[Sean Anderson]

Currently, one cannot use a reset driver on RISC-V. Follow the MIPS
example, and disable the default reset handler when the sysreset driver is
enabled.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---

Changes in v3:
- New


 arch/riscv/lib/reset.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
index ce3c1cf872..7622e5df43 100644
--- a/arch/riscv/lib/reset.c
+++ b/arch/riscv/lib/reset.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 
+#ifndef CONFIG_SYSRESET
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
printf("resetting ...\n");
@@ -16,3 +17,4 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
 
return 0;
 }
+#endif
-- 
2.25.1

[PATCH v8 13/21] riscv: Clear pending interrupts before enabling IPIs

[Sean Anderson]

On some platforms (k210), the previous stage bootloader may have not
cleared pending IPIs before transferring control to U-Boot. This can cause
race conditions, as multiple harts all attempt to initialize the IPI
controller at once. This patch clears IPIs before enabling them, ensuring
that only one hart modifies shared memory at once.

Signed-off-by: Sean Anderson 
Reviewed-by: Rick Chen 
---

Changes in v7:
- Split of into its own patch


 arch/riscv/cpu/start.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 6b3ff99c38..e8740c8568 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -67,6 +67,8 @@ _start:
 #else
li  t0, SIE_SSIE
 #endif
+   /* Clear any pending IPIs */
+   csrcMODE_PREFIX(ip), t0
csrsMODE_PREFIX(ie), t0
 #endif
 
-- 
2.25.1

[PATCH v8 21/21] riscv: Add Sipeed Maix support

[Sean Anderson]

The Sipeed Maix series is a collection of boards built around the RISC-V
Kendryte K210 processor. This processor contains several peripherals to
accelerate neural network processing and other "ai" tasks. This includes a
"KPU" neural network processor, an audio processor supporting beamforming
reception, and a digital video port supporting capture and output at VGA
resolution. Other peripherals include 8M of sram (accessible with and
without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256
accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix
peripherals vary, but include spi flash; on-board usb-serial bridges; ports
for cameras, displays, and sd cards; and ESP32 chips. Currently, only the
Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly
similar.

Documentation for Maix boards is located at
.  Documentation for the Kendryte K210 is
located at . However, hardware details are
rather lacking, so most technical reference has been taken from the
standalone sdk located at
.

Signed-off-by: Sean Anderson 
---

Changes in v8:
- Remove unnecessary fdt fixup for sipeed maix

Changes in v7:
- Split docs off into their own patch
- Enable ram clocks by name

Changes in v6:
- Remove trailing whitespace from documentation
- Remove configuration for spi/pinmux/gpio features
- Flesh out documentation some more

Changes in v5:
- Configure relocation location with CONFIG_SYS_SDRAM_*
- Enable ram clocks
- Add pinmux/gpio/led support
- Remove (broken) MMC support
- Store the environment in flash
- Add partitions
- Add bootcmd
- Add docs for pinctrl and booting

Changes in v4:
- Rework documentation to be organized by board mfg not cpu mfg
- Update docs to reflect working SPI support
- Add proper spi support
- Don't define unneecessary macros in config.h
- Lower the default stack so it isn't clobbered on relocation
- Update MAINTAINERS
- Update copyright

Changes in v3:
- Reorder to be last in the patch series
- Add documentation for the board
- Generate defconfig with "make savedefconfig"
- Update Kconfig to imply most features we need
- Update MAINTAINERS

Changes in v2:
- Select CONFIG_SYS_RISCV_NOCOUNTER
- Imply CONFIG_CLK_K210
- Remove spurious references to CONFIG_ARCH_K210
- Remove many configs from defconfig where the defaults were fine
- Add a few "not set" lines to suppress unneeded defaults
- Reduce pre-reloc malloc space, now that clocks initialization happens
  later

 arch/riscv/Kconfig |  4 +++
 board/sipeed/maix/Kconfig  | 47 ++
 board/sipeed/maix/MAINTAINERS  | 11 +++
 board/sipeed/maix/Makefile |  5 
 board/sipeed/maix/maix.c   | 41 ++
 configs/sipeed_maix_bitm_defconfig |  8 +
 include/configs/sipeed-maix.h  | 24 +++
 7 files changed, 140 insertions(+)
 create mode 100644 board/sipeed/maix/Kconfig
 create mode 100644 board/sipeed/maix/MAINTAINERS
 create mode 100644 board/sipeed/maix/Makefile
 create mode 100644 board/sipeed/maix/maix.c
 create mode 100644 configs/sipeed_maix_bitm_defconfig
 create mode 100644 include/configs/sipeed-maix.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a42cb58b56..eb7b3171eb 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT
 config TARGET_SIFIVE_FU540
bool "Support SiFive FU540 Board"
 
+config TARGET_SIPEED_MAIX
+   bool "Support Sipeed Maix Board"
+
 endchoice
 
 config SYS_ICACHE_OFF
@@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/fu540/Kconfig"
+source "board/sipeed/maix/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
new file mode 100644
index 00..0cdcd32adc
--- /dev/null
+++ b/board/sipeed/maix/Kconfig
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2019-20 Sean Anderson 
+
+if TARGET_SIPEED_MAIX
+
+config SYS_BOARD
+   default "maix"
+
+config SYS_VENDOR
+   default "sipeed"
+
+config SYS_CPU
+   default "generic"
+
+config SYS_CONFIG_NAME
+   default "sipeed-maix"
+
+config SYS_TEXT_BASE
+   default 0x8000
+
+config DEFAULT_DEVICE_TREE
+   default "k210-maix-bit"
+
+config NR_CPUS
+   default 2
+
+config NR_DRAM_BANKS
+   default 3
+
+config BOARD_SPECIFIC_OPTIONS
+   def_bool y
+   select GENERIC_RISCV
+   select RISCV_PRIV_1_9
+   imply SMP
+   imply DM_SERIAL
+   imply SIFIVE_SERIAL
+   imply SIFIVE_CLINT
+   imply POWER_DOMAIN
+   imply SIMPLE_PM_BUS
+   imply CLK_CCF
+   imply CLK_COMPOSITE_CCF
+   imply CLK_K210
+   imply DM_RESET
+   imply 

[PATCH v8 15/21] riscv: Add option to support RISC-V privileged spec 1.9

[Sean Anderson]

Some older processors (notably the Kendryte K210) use an older version of
the RISC-V privileged specification. The primary changes between the old
and new are in virtual memory, and in the merging of three separate counter
enable CSRs.  Using the new CSR on an old processor causes an illegal
instruction exception.  This patch adds an option to use the old CSRs
instead of the new one.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---

Changes in v6:
- Reformat so chechpatch errors less

Changes in v5:
- Rename to 1.9 to reflect the spec as implemented by the k210

Changes in v4:
- Fixed CSRs not being defined properly (thanks bmeng)
- Added ifdefs for all changed CSRs (e.g. for VM)
- Also properly disable VM on boot

Changes in v3:
- Renamed from "riscv: Add option to disable writes to mcounteren"
- Added original functionality back for older priv specs.

Changes in v2:
- Moved forward in the patch series

 arch/riscv/Kconfig   | 10 +
 arch/riscv/cpu/cpu.c |  9 
 arch/riscv/include/asm/csr.h | 40 
 3 files changed, 59 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index cc87da7e04..a42cb58b56 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -238,6 +238,16 @@ config XIP
 config SHOW_REGS
bool "Show registers on unhandled exception"
 
+config RISCV_PRIV_1_9
+   bool "Use version 1.9 of the RISC-V priviledged specification"
+   help
+ Older versions of the RISC-V priviledged specification had
+ separate counter enable CSRs for each privilege mode. Writing
+ to the unified mcounteren CSR on a processor implementing the
+ old specification will result in an illegal instruction
+ exception. In addition to counter CSR changes, the way virtual
+ memory is configured was also changed.
+
 config STACK_SIZE_SHIFT
int
default 14
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index f851374255..3c1836694a 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -89,11 +89,20 @@ int arch_cpu_init_dm(void)
 * Enable perf counters for cycle, time,
 * and instret counters only
 */
+#ifdef CONFIG_RISCV_PRIV_1_9
+   csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
+   csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
+#else
csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
+#endif
 
/* Disable paging */
if (supports_extension('s'))
+#ifdef CONFIG_RISCV_PRIV_1_9
+   csr_read_clear(CSR_MSTATUS, SR_VM);
+#else
csr_write(CSR_SATP, 0);
+#endif
}
 
 #ifdef CONFIG_SMP
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index d1520743a2..1a15089cae 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -15,7 +15,11 @@
 #define SR_SIE _AC(0x0002, UL) /* Supervisor Interrupt Enable */
 #define SR_SPIE_AC(0x0020, UL) /* Previous Supervisor IE */
 #define SR_SPP _AC(0x0100, UL) /* Previously Supervisor */
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define SR_PUM _AC(0x0004, UL) /* Protect User Memory Access */
+#else
 #define SR_SUM _AC(0x0004, UL) /* Supervisor User Memory Access */
+#endif
 
 #define SR_FS  _AC(0x6000, UL) /* Floating-point Status */
 #define SR_FS_OFF  _AC(0x, UL)
@@ -29,6 +33,22 @@
 #define SR_XS_CLEAN_AC(0x0001, UL)
 #define SR_XS_DIRTY_AC(0x00018000, UL)
 
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define SR_VM  _AC(0x1F00, UL) /* Virtualization Management */
+#define SR_VM_MODE_BARE_AC(0x, UL) /* No translation or 
protection */
+#define SR_VM_MODE_BB  _AC(0x0100, UL) /* Single base-and-bound */
+/* Separate instruction and data base-and-bound */
+#define SR_VM_MODE_BBID_AC(0x0200, UL)
+#ifndef CONFIG_64BIT
+#define SR_VM_MODE_32  _AC(0x0800, UL)
+#define SR_VM_MODE SR_VM_MODE_32
+#else
+#define SR_VM_MODE_39  _AC(0x0900, UL)
+#define SR_VM_MODE_48  _AC(0x0A00, UL)
+#define SR_VM_MODE SR_VM_MODE_39
+#endif
+#endif
+
 #ifndef CONFIG_64BIT
 #define SR_SD  _AC(0x8000, UL) /* FS/XS dirty */
 #else
@@ -36,6 +56,7 @@
 #endif
 
 /* SATP flags */
+#ifndef CONFIG_RISCV_PRIV_1_9
 #ifndef CONFIG_64BIT
 #define SATP_PPN   _AC(0x003F, UL)
 #define SATP_MODE_32   _AC(0x8000, UL)
@@ -45,6 +66,7 @@
 #define SATP_MODE_39   _AC(0x8000, UL)
 #define SATP_MODE  SATP_MODE_39
 #endif
+#endif
 
 /* SCAUSE */
 #define SCAUSE_IRQ_FLAG(_AC(1, UL) << (__riscv_xlen - 1))
@@ -88,17 +110,35 @@
 #define CSR_SCAUSE 0x142
 #define CSR_STVAL  0x143
 #define CSR_SIP0x144
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define CSR_SPTBR  0x180
+#else
 #define CSR_SATP   0x180
+#endif
 #define CSR_MSTATUS 

[PATCH v8 14/21] riscv: Clean up IPI initialization code

[Sean Anderson]

The previous IPI code initialized the device whenever the first call was
made to a riscv_*_ipi function. This made it difficult to determine when
the IPI device was initialized. This patch introduces a new function
riscv_init_ipi. It is called once during arch_cpu_init_dm. Before this
point, no riscv_*_ipi functions should be called.

Signed-off-by: Sean Anderson 
Reviewed-by: Rick Chen 
---

Changes in v7:
- Split IPI clearing off into its own patch

Changes in v6:
- Fix some formatting
- Clear IPIs before enabling interrupts instead of using a ipi_ready flag
- Only print messages on error in smp code

Changes in v5:
- New


 arch/riscv/cpu/cpu.c  |  6 
 arch/riscv/include/asm/smp.h  | 43 +++
 arch/riscv/lib/andes_plic.c   | 34 -
 arch/riscv/lib/sbi_ipi.c  |  5 
 arch/riscv/lib/sifive_clint.c | 33 +++--
 arch/riscv/lib/smp.c  | 56 ---
 6 files changed, 90 insertions(+), 87 deletions(-)

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index e457f6acbf..f851374255 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -96,6 +96,12 @@ int arch_cpu_init_dm(void)
csr_write(CSR_SATP, 0);
}
 
+#ifdef CONFIG_SMP
+   ret = riscv_init_ipi();
+   if (ret)
+   return ret;
+#endif
+
return 0;
 }
 
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 74de92ed13..1b428856b2 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -51,4 +51,47 @@ void handle_ipi(ulong hart);
  */
 int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait);
 
+/**
+ * riscv_init_ipi() - Initialize inter-process interrupt (IPI) driver
+ *
+ * Platform code must provide this function. This function is called once after
+ * the cpu driver is initialized. No other riscv_*_ipi() calls will be made
+ * before this function is called.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int riscv_init_ipi(void);
+
+/**
+ * riscv_send_ipi() - Send inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of receiving hart
+ * @return 0 if OK, -ve on error
+ */
+int riscv_send_ipi(int hart);
+
+/**
+ * riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be cleared
+ * @return 0 if OK, -ve on error
+ */
+int riscv_clear_ipi(int hart);
+
+/**
+ * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be checked
+ * @pending: Pointer to variable with result of the check,
+ *   1 if IPI is pending, 0 otherwise
+ * @return 0 if OK, -ve on error
+ */
+int riscv_get_ipi(int hart, int *pending);
+
 #endif
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 20529ab3eb..8484f76386 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -30,20 +30,6 @@
 #define SEND_IPI_TO_HART(hart)  (0x80 >> (hart))
 
 DECLARE_GLOBAL_DATA_PTR;
-static int init_plic(void);
-
-#define PLIC_BASE_GET(void)\
-   do {\
-   long *ret;  \
-   \
-   if (!gd->arch.plic) {   \
-   ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
-   if (IS_ERR(ret))\
-   return PTR_ERR(ret);\
-   gd->arch.plic = ret;\
-   init_plic();\
-   }   \
-   } while (0)
 
 static int enable_ipi(int hart)
 {
@@ -93,13 +79,21 @@ static int init_plic(void)
return -ENODEV;
 }
 
+int riscv_init_ipi(void)
+{
+   int ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
+
+   if (IS_ERR(ret))
+   return PTR_ERR(ret);
+   gd->arch.plic = ret;
+
+   return init_plic();
+}
+
 int riscv_send_ipi(int hart)
 {
-   unsigned int ipi;
+   unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
 
-   PLIC_BASE_GET();
-
-   ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
 
@@ -110,8 +104,6 @@ int riscv_clear_ipi(int hart)
 {
u32 source_id;
 
-   PLIC_BASE_GET();
-
source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
 
@@ -120,8 +112,6 @@ int 

[PATCH v8 05/21] clk: Add K210 pll support

[Sean Anderson]

This pll code is primarily based on the code from the kendryte standalone
sdk in lib/drivers/sysctl.c. k210_pll_calc_params is roughly analogous to
the algorithm used to set the pll frequency, but it has been completely
rewritten to be fixed-point based.

Signed-off-by: Sean Anderson 
---

Changes in v8:
- Rename k210_pll_params to k210_pll_config to avoid a name conflict with the
  rest of the clock code

Changes in v6:
- Reformat code to reduce checkpatch errors

Changes in v5:
- Add function to register from a struct

Changes in v4:
- Rename the reference clock to "divider clock", and input clock to "reference
  clock" to match the upstream documentation.
- Add a test for calc_params. This currently resides in test/dm, but perhaps it
  should be moved to its own directory.
- Update MAINTAINERS
- Update copyright
- Lint

Changes in v3:
- Add an option to not include support for setting the pll rate. This saves
  around 1K in the final executable.
- Remove udelays to suppress warnings
- Bypass PLL after enabling, instead of before
- Check if the PLL is enabled already before doing a reset
- Fix bug with locked mask

Changes in v2:
- Rename driver to "k210_clk_pll"
- Add additional in-line documentation on algorithm and PLLs
- Restrict the range of internal VCO and reference frequencies
- Don't load driver before relocation
- Remove spurious references to mach-k210

 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   1 +
 drivers/clk/kendryte/Kconfig  |  12 +
 drivers/clk/kendryte/Makefile |   1 +
 drivers/clk/kendryte/pll.c| 601 ++
 include/kendryte/pll.h|  57 
 include/test/export.h |  16 +
 test/dm/Makefile  |   1 +
 test/dm/k210_pll.c|  96 ++
 9 files changed, 786 insertions(+)
 create mode 100644 drivers/clk/kendryte/Kconfig
 create mode 100644 drivers/clk/kendryte/Makefile
 create mode 100644 drivers/clk/kendryte/pll.c
 create mode 100644 include/kendryte/pll.h
 create mode 100644 include/test/export.h
 create mode 100644 test/dm/k210_pll.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 1992d4a4b4..fb8335267b 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -155,6 +155,7 @@ source "drivers/clk/analogbits/Kconfig"
 source "drivers/clk/at91/Kconfig"
 source "drivers/clk/exynos/Kconfig"
 source "drivers/clk/imx/Kconfig"
+source "drivers/clk/kendryte/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/owl/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e01783391d..d911954581 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
 obj-$(CONFIG_CLK_EXYNOS) += exynos/
 obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
 obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
+obj-$(CONFIG_CLK_K210) += kendryte/
 obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
 obj-$(CONFIG_CLK_OWL) += owl/
 obj-$(CONFIG_CLK_RENESAS) += renesas/
diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig
new file mode 100644
index 00..7b69c8afaf
--- /dev/null
+++ b/drivers/clk/kendryte/Kconfig
@@ -0,0 +1,12 @@
+config CLK_K210
+   bool "Clock support for Kendryte K210"
+   depends on CLK && CLK_CCF
+   help
+ This enables support clock driver for Kendryte K210 platforms.
+
+config CLK_K210_SET_RATE
+   bool "Enable setting the Kendryte K210 PLL rate"
+   depends on CLK_K210
+   help
+ Add functionality to calculate new rates for K210 PLLs. Enabling this
+ feature adds around 1K to U-Boot's final size.
diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
new file mode 100644
index 00..c56d93ea1c
--- /dev/null
+++ b/drivers/clk/kendryte/Makefile
@@ -0,0 +1 @@
+obj-y += pll.o
diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c
new file mode 100644
index 00..2c5d5b8857
--- /dev/null
+++ b/drivers/clk/kendryte/pll.c
@@ -0,0 +1,601 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson 
+ */
+#include 
+
+#define LOG_CATEGORY UCLASS_CLK
+#include 
+/* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CLK_K210_PLL "k210_clk_pll"
+
+#ifdef CONFIG_CLK_K210_SET_RATE
+static int k210_pll_enable(struct clk *clk);
+static int k210_pll_disable(struct clk *clk);
+
+/*
+ * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
+ * General-Purpose PLL. The logical layout of the PLL with internal feedback is
+ * approximately the following:
+ *
+ *  +---+
+ *  |reference clock|
+ *  +---+
+ *  |
+ *  v
+ *+--+
+ *|/r|
+ *+--+
+ *  |
+ *  v
+ *   +-+
+ *   |divided clock|
+ *   +-+
+ *  |
+ *  v
+ *  

[PATCH v8 12/21] riscv: Add headers for asm/global_data.h

[Sean Anderson]

This header depended on bd_t and ulong, but did not include the appropriate
headers.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---

Changes in v4:
- Include compiler.h not linux/compiler.h


 arch/riscv/include/asm/global_data.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index b74bd7e738..7276d9763f 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -11,6 +11,8 @@
 #define __ASM_GBL_DATA_H
 
 #include 
+#include 
+#include 
 
 /* Architecture-specific global data */
 struct arch_global_data {
-- 
2.25.1

[PATCH v8 10/21] reset: Add generic reset driver

[Sean Anderson]

This patch adds a generic reset driver. It is designed to be useful when
one has a register in a regmap which contains bits that reset other
devices. I thought this seemed like a very generic use, so here is a
generic driver. The overall structure has been modeled on the syscon-reboot
driver.

Signed-off-by: Sean Anderson 
Reviewed-by: Simon Glass 
---

Changes in v5:
- Reorder includes
- Include linux/err.h explicitly

Changes in v4:
- Added basic test
- Fix incorrect usage of regmap_update_bits

Changes in v3:
- New


 arch/sandbox/dts/test.dts | 15 
 configs/sandbox_defconfig |  2 +
 .../reset/syscon-reset.txt| 36 +
 drivers/reset/Kconfig |  5 ++
 drivers/reset/Makefile|  1 +
 drivers/reset/reset-syscon.c  | 80 +++
 test/dm/Makefile  |  1 +
 test/dm/syscon-reset.c| 58 ++
 8 files changed, 198 insertions(+)
 create mode 100644 doc/device-tree-bindings/reset/syscon-reset.txt
 create mode 100644 drivers/reset/reset-syscon.c
 create mode 100644 test/dm/syscon-reset.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 96e0b55eed..6f2fcc64a4 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -940,6 +940,21 @@
clocks = <_sandbox 4>;
power-domains = < 1>;
};
+
+   resetc2: syscon-reset {
+   compatible = "syscon-reset";
+   #reset-cells = <1>;
+   regmap = <>;
+   offset = <1>;
+   mask = <0x27FF>;
+   assert-high = <0>;
+   };
+
+   syscon-reset-test {
+   compatible = "sandbox,misc_sandbox";
+   resets = < 15>, < 30>, < 60>;
+   reset-names = "valid", "no_mask", "out_of_range";
+   };
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index ef49cd2b83..787546243d 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -190,6 +190,8 @@ CONFIG_REMOTEPROC_SANDBOX=y
 CONFIG_DM_RESET=y
 CONFIG_SANDBOX_RESET=y
 CONFIG_DM_RNG=y
+CONFIG_RNG_SANDBOX=y
+CONFIG_RESET_SYSCON=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_RV8803=y
 CONFIG_DEBUG_UART_SANDBOX=y
diff --git a/doc/device-tree-bindings/reset/syscon-reset.txt 
b/doc/device-tree-bindings/reset/syscon-reset.txt
new file mode 100644
index 00..f136b3d225
--- /dev/null
+++ b/doc/device-tree-bindings/reset/syscon-reset.txt
@@ -0,0 +1,36 @@
+Generic SYSCON mapped register reset driver
+
+This is a generic reset driver using syscon to map the reset register.
+The reset is generally performed with a write to the reset register
+defined by the register map pointed by syscon reference plus the offset and
+shifted by the reset specifier/
+
+To assert a reset on some device, the equivalent of the following operation is
+performed, where reset_id is the reset specifier from the device's resets
+property.
+
+   if (BIT(reset_id) & mask)
+   regmap[offset][reset_id] = assert-high;
+
+Required properties:
+- compatible: should contain "syscon-reset"
+- #reset-cells: must be 1
+- regmap: this is phandle to the register map node
+- offset: offset in the register map for the reboot register (in bytes)
+
+Optional properties:
+- mask: accept only the reset specifiers defined by the mask (32 bit)
+- assert-high: Bit to write when asserting a reset. Defaults to 1.
+
+Default will be little endian mode, 32 bit access only.
+
+Example:
+
+   reset-controller {
+   compatible = "syscon-reset";
+   #reset-cells = <1>;
+   regmap = <>;
+   offset = <0x20>;
+   mask = <0x27FF>;
+   assert-high = <0>;
+   };
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 75ccd65799..097bf32b21 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -148,4 +148,9 @@ config RESET_IMX7
help
  Support for reset controller on i.MX7/8 SoCs.
 
+config RESET_SYSCON
+   bool "Enable generic syscon reset driver support"
+   depends on DM_RESET
+   help
+ Support generic syscon mapped register reset devices.
 endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 0a044d5d8c..433f1eca54 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
diff --git a/drivers/reset/reset-syscon.c b/drivers/reset/reset-syscon.c
new file mode 100644
index 00..34dfe0bab6
--- /dev/null
+++ b/drivers/reset/reset-syscon.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Sean Anderson
+ 

[PATCH v8 08/21] dm: Add support for simple-pm-bus

[Sean Anderson]

This type of bus is used in Linux to designate buses which have power
domains and/or clocks which need to be enabled before their child devices
can be used. Because power domains are automatically enabled before probing
in U-Boot, we just need to enable any clocks present.

Signed-off-by: Sean Anderson 
Reviewed-by: Simon Glass 
---

Changes in v5:
- Reorder includes (simple pm)

Changes in v4:
- Split the bus off into its own driver
- Add test
- Fix line spacing in Kconfig
- Lint

Changes in v3:
- New


 arch/sandbox/dts/test.dts |  6 ++
 arch/sandbox/include/asm/clk.h|  1 +
 configs/sandbox_defconfig |  1 +
 .../bus/simple-pm-bus.txt | 44 +++
 drivers/core/Kconfig  |  7 +++
 drivers/core/Makefile |  1 +
 drivers/core/simple-pm-bus.c  | 56 +++
 test/dm/Makefile  |  1 +
 test/dm/simple-pm-bus.c   | 45 +++
 9 files changed, 162 insertions(+)
 create mode 100644 doc/device-tree-bindings/bus/simple-pm-bus.txt
 create mode 100644 drivers/core/simple-pm-bus.c
 create mode 100644 test/dm/simple-pm-bus.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 4a277934a7..96e0b55eed 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -934,6 +934,12 @@
mdio: mdio-test {
compatible = "sandbox,mdio";
};
+
+   pm-bus-test {
+   compatible = "simple-pm-bus";
+   clocks = <_sandbox 4>;
+   power-domains = < 1>;
+   };
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
index 1573e4a134..c184c4bffc 100644
--- a/arch/sandbox/include/asm/clk.h
+++ b/arch/sandbox/include/asm/clk.h
@@ -21,6 +21,7 @@ enum sandbox_clk_id {
SANDBOX_CLK_ID_I2C,
SANDBOX_CLK_ID_UART1,
SANDBOX_CLK_ID_UART2,
+   SANDBOX_CLK_ID_BUS,
 
SANDBOX_CLK_ID_COUNT,
 };
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index f96891ecae..ef49cd2b83 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -90,6 +90,7 @@ CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_DEVRES=y
 CONFIG_DEBUG_DEVRES=y
+CONFIG_SIMPLE_PM_BUS=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
 CONFIG_AXI=y
diff --git a/doc/device-tree-bindings/bus/simple-pm-bus.txt 
b/doc/device-tree-bindings/bus/simple-pm-bus.txt
new file mode 100644
index 00..6f15037131
--- /dev/null
+++ b/doc/device-tree-bindings/bus/simple-pm-bus.txt
@@ -0,0 +1,44 @@
+Simple Power-Managed Bus
+
+
+A Simple Power-Managed Bus is a transparent bus that doesn't need a real
+driver, as it's typically initialized by the boot loader.
+
+However, its bus controller is part of a PM domain, or under the control of a
+functional clock.  Hence, the bus controller's PM domain and/or clock must be
+enabled for child devices connected to the bus (either on-SoC or externally)
+to function.
+
+While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
+in the Devicetree Specification, it is not an extension of "simple-bus".
+
+
+Required properties:
+  - compatible: Must contain at least "simple-pm-bus".
+   Must not contain "simple-bus".
+   It's recommended to let this be preceded by one or more
+   vendor-specific compatible values.
+  - #address-cells, #size-cells, ranges: Must describe the mapping between
+   parent address and child address spaces.
+
+Optional platform-specific properties for clock or PM domain control (at least
+one of them is required):
+  - clocks: Must contain a reference to the functional clock(s),
+  - power-domains: Must contain a reference to the PM domain.
+Please refer to the binding documentation for the clock and/or PM domain
+providers for more details.
+
+
+Example:
+
+   bsc: bus@fec1 {
+   compatible = "renesas,bsc-sh73a0", "renesas,bsc",
+"simple-pm-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0 0x2000>;
+   reg = <0xfec1 0x400>;
+   interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = <_clk>;
+   power-domains = <_a4s>;
+   };
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 3b95b5387b..0cd687526e 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -195,6 +195,13 @@ config SPL_SIMPLE_BUS
  Supports the 'simple-bus' driver, which is used on some systems
  in SPL.
 
+config SIMPLE_PM_BUS
+   bool "Support simple-pm-bus driver"
+   depends on DM && OF_CONTROL && CLK && POWER_DOMAIN
+   help
+ Supports the 'simple-pm-bus' driver, which is used for busses that
+ have power domains and/or clocks which need to be 

[PATCH v8 11/21] lib: Always set errno in hcreate_r

[Sean Anderson]

This could give a confusing error message if it failed and didn't set
errno.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---

Changes in v5:
- New


 lib/hashtable.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/lib/hashtable.c b/lib/hashtable.c
index 907e8a642f..e9ac7e252e 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -109,8 +109,10 @@ int hcreate_r(size_t nel, struct hsearch_data *htab)
}
 
/* There is still another table active. Return with error. */
-   if (htab->table != NULL)
+   if (htab->table != NULL) {
+   __set_errno(EINVAL);
return 0;
+   }
 
/* Change nel to the first prime number not smaller as nel. */
nel |= 1;   /* make odd */
@@ -123,8 +125,10 @@ int hcreate_r(size_t nel, struct hsearch_data *htab)
/* allocate memory and zero out */
htab->table = (struct env_entry_node *)calloc(htab->size + 1,
sizeof(struct env_entry_node));
-   if (htab->table == NULL)
+   if (htab->table == NULL) {
+   __set_errno(ENOMEM);
return 0;
+   }
 
/* everything went alright */
return 1;
-- 
2.25.1

[PATCH v8 06/21] clk: Add a bypass clock for K210

[Sean Anderson]

This is a small driver to do a software bypass of a clock if hardware
bypass is not working. I have tried to write this in a generic fashion, so
that it could be potentially broken out of the kendryte code at some future
date. For the K210, it is used to have aclk bypass pll0 and use in0 instead
so that the CPU keeps on working.

Signed-off-by: Sean Anderson 
---

Changes in v5:
- Add function to register from a struct bypass

Changes in v4:
- New


 drivers/clk/kendryte/Makefile |   2 +-
 drivers/clk/kendryte/bypass.c | 270 ++
 include/kendryte/bypass.h |  31 
 3 files changed, 302 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/kendryte/bypass.c
 create mode 100644 include/kendryte/bypass.h

diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
index c56d93ea1c..47f682fce3 100644
--- a/drivers/clk/kendryte/Makefile
+++ b/drivers/clk/kendryte/Makefile
@@ -1 +1 @@
-obj-y += pll.o
+obj-y += bypass.o pll.o
diff --git a/drivers/clk/kendryte/bypass.c b/drivers/clk/kendryte/bypass.c
new file mode 100644
index 00..eb3e27d055
--- /dev/null
+++ b/drivers/clk/kendryte/bypass.c
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sean Anderson 
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#define LOG_CATEGORY UCLASS_CLK
+#include 
+
+#define CLK_K210_BYPASS "k210_clk_bypass"
+
+/*
+ * This is a small driver to do a software bypass of a clock if hardware bypass
+ * is not working. I have tried to write this in a generic fashion, so that it
+ * could be potentially broken out of the kendryte code at some future date.
+ *
+ * Say you have the following clock configuration
+ *
+ * +---+ +---+
+ * |osc| |pll|
+ * +---+ +---+
+ * ^
+ */|
+ *   / |
+ *  /  |
+ * /   |
+ */|
+ * +---+ +---+
+ * |clk| |clk|
+ * +---+ +---+
+ *
+ * But the pll does not have a bypass, so when you configure the pll, the
+ * configuration needs to change to look like
+ *
+ * +---+ +---+
+ * |osc| |pll|
+ * +---+ +---+
+ *   ^
+ *   |\
+ *   | \
+ *   |  \
+ *   |   \
+ *   |\
+ * +---+ +---+
+ * |clk| |clk|
+ * +---+ +---+
+ *
+ * To set this up, create a bypass clock with bypassee=pll and alt=osc. When
+ * creating the child clocks, set their parent to the bypass clock. After
+ * creating all the children, call k210_bypass_setchildren().
+ */
+
+static int k210_bypass_dobypass(struct k210_bypass *bypass)
+{
+   int ret, i;
+
+   /*
+* If we already have saved parents, then the children are already
+* bypassed
+*/
+   if (bypass->child_count && bypass->saved_parents[0])
+   return 0;
+
+   for (i = 0; i < bypass->child_count; i++) {
+   struct clk *child = bypass->children[i];
+   struct clk *parent = clk_get_parent(child);
+
+   if (IS_ERR(parent)) {
+   for (; i; i--)
+   bypass->saved_parents[i] = NULL;
+   return PTR_ERR(parent);
+   }
+   bypass->saved_parents[i] = parent;
+   }
+
+   for (i = 0; i < bypass->child_count; i++) {
+   struct clk *child = bypass->children[i];
+
+   ret = clk_set_parent(child, bypass->alt);
+   if (ret) {
+   for (; i; i--)
+   clk_set_parent(bypass->children[i],
+  bypass->saved_parents[i]);
+   for (i = 0; i < bypass->child_count; i++)
+   bypass->saved_parents[i] = NULL;
+   return ret;
+   }
+   }
+
+   return 0;
+}
+
+static int k210_bypass_unbypass(struct k210_bypass *bypass)
+{
+   int err, ret, i;
+
+   if (!bypass->child_count && !bypass->saved_parents[0]) {
+   log_warning("Cannot unbypass children; dobypass not called 
first\n");
+   return 0;
+   }
+
+   ret = 0;
+   for (i = 0; i < bypass->child_count; i++) {
+   err = clk_set_parent(bypass->children[i],
+bypass->saved_parents[i]);
+   if (err)
+   ret = err;
+   bypass->saved_parents[i] = NULL;
+   }
+   return ret;
+}
+
+static ulong k210_bypass_get_rate(struct clk *clk)
+{
+   struct k210_bypass *bypass = to_k210_bypass(clk);
+   const struct clk_ops *ops = bypass->bypassee_ops;
+
+   if (ops->get_rate)
+   return ops->get_rate(bypass->bypassee);
+   else
+   return clk_get_parent_rate(bypass->bypassee);
+}
+
+static ulong k210_bypass_set_rate(struct clk *clk, unsigned long rate)
+{
+   int ret;
+   struct k210_bypass *bypass = to_k210_bypass(clk);
+   const struct clk_ops *ops = bypass->bypassee_ops;
+
+   /* Don't bother bypassing if we aren't going to set the rate */
+   if 

[PATCH v8 07/21] clk: Add K210 clock support

[Sean Anderson]

Due to the large number of clocks, I decided to use the CCF. The overall
structure is modeled after the imx code. Clocks are stored in several
arrays. There are some translation macros (FOOIFY()) which allow for more
dense packing.  A possible improvement could be to only store the
parameters we need, instead of the whole CCF struct.

Signed-off-by: Sean Anderson 
---

Changes in v8:
- Rework code to not need a new CCF api
- Add some documentation

Changes in v7:
- Add numbering to some sysctl registers

Changes in v6:
- Reformat code so checkpatch generates fewer warnings
- Give "fictional" clocks their own ids
- Rename sysctl CLK_FREQ register to UART_BAUD to better reflect its
  semantics

Changes in v5:
- Don't unmap priv->reg
- Remove comment on APB clocks since it has been clarified by Kendryte
- Add i2s mclks
- Reorder clock ids to be continuous
- Rewrite to statically allocate all clocks. This has helped find several
  bugs (since it is easy to see when a clock has the wrong register).
- Fix ACLK sometimes having the wrong parent
- Fix SPI3 having the wrong divider
- Prevent being probed multiple times on failure

Changes in v4:
- Reparent aclk before configuring pll0
- Update copyright
- Lint

Changes in v3:
- Removed sysctl struct, replacing it with defines. This is to have the
  same interface to sysctl from C as from the device tree.
- Fixed clocks having the same id
- Fixed clocks not using the correct register/bits
- Aligned the defines in headers

Changes in v2:
- Add clk.o to obj-y
- Don't probe before relocation

 MAINTAINERS   |   7 +
 .../mfd/kendryte,k210-sysctl.txt  |  33 +
 drivers/clk/kendryte/Kconfig  |   2 +-
 drivers/clk/kendryte/Makefile |   2 +-
 drivers/clk/kendryte/clk.c| 663 ++
 include/dt-bindings/clock/k210-sysctl.h   |  59 ++
 include/dt-bindings/mfd/k210-sysctl.h |  38 +
 include/kendryte/clk.h|  35 +
 8 files changed, 837 insertions(+), 2 deletions(-)
 create mode 100644 doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
 create mode 100644 drivers/clk/kendryte/clk.c
 create mode 100644 include/dt-bindings/clock/k210-sysctl.h
 create mode 100644 include/dt-bindings/mfd/k210-sysctl.h
 create mode 100644 include/kendryte/clk.h

diff --git a/MAINTAINERS b/MAINTAINERS
index b50652bd85..119da03512 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -829,6 +829,13 @@ F: arch/riscv/
 F: cmd/riscv/
 F: tools/prelink-riscv.c
 
+RISC-V KENDRYTE
+M: Sean Anderson 
+S: Maintained
+F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
+F: drivers/clk/kendryte/
+F: include/kendryte/
+
 RNG
 M: Sughosh Ganu 
 R: Heinrich Schuchardt 
diff --git a/doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt 
b/doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
new file mode 100644
index 00..5b24abcb62
--- /dev/null
+++ b/doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
@@ -0,0 +1,33 @@
+Kendryte K210 Sysctl
+
+This binding describes the K210 sysctl device, which contains many 
miscellaneous
+registers controlling system functionality. This node is a register map and can
+be reference by other bindings which need a phandle to the K210 sysctl regmap.
+
+Required properties:
+- compatible: should be
+   "kendryte,k210-sysctl", "syscon", "simple-mfd"
+- reg: address and length of the sysctl registers
+- reg-io-width: must be <4>
+
+Clock sub-node
+
+This node is a binding for the clock tree driver
+
+Required properties:
+- compatible: should be "kendryte,k210-clk"
+- clocks: phandle to the "in0" external oscillator
+- #clock-cells: must be <1>
+
+Example:
+sysctl: syscon@5044 {
+   compatible = "kendryte,k210-sysctl", "syscon", "simple-mfd";
+   reg = <0x5044 0x100>;
+   reg-io-width = <4>;
+
+   sysclk: clock-controller {
+   compatible = "kendryte,k210-clk";
+   clocks = <>;
+   #clock-cells = <1>;
+   };
+};
diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig
index 7b69c8afaf..073fca0781 100644
--- a/drivers/clk/kendryte/Kconfig
+++ b/drivers/clk/kendryte/Kconfig
@@ -1,6 +1,6 @@
 config CLK_K210
bool "Clock support for Kendryte K210"
-   depends on CLK && CLK_CCF
+   depends on CLK && CLK_CCF && CLK_COMPOSITE_CCF
help
  This enables support clock driver for Kendryte K210 platforms.
 
diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
index 47f682fce3..6fb68253ae 100644
--- a/drivers/clk/kendryte/Makefile
+++ b/drivers/clk/kendryte/Makefile
@@ -1 +1 @@
-obj-y += bypass.o pll.o
+obj-y += bypass.o clk.o pll.o
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
new file mode 100644
index 00..981b3b7699
--- /dev/null
+++ b/drivers/clk/kendryte/clk.c
@@ -0,0 +1,663 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 

[PATCH v8 02/21] clk: Check that ops of composite clock components exist before calling

[Sean Anderson]

clk_composite_ops was shared between all devices in the composite clock
driver.  If one clock had a feature (such as supporting set_parent) which
another clock did not, it could call a null pointer dereference.

This patch does three things
1. It adds null-pointer checks to all composite clock functions.
2. It makes clk_composite_ops const and sets its functions at compile-time.
3. It adds some basic sanity checks to num_parents.

The combined effect of these changes is that any of mux, rate, or gate can
be NULL, and composite clocks will still function normally. Previously, at
least mux had to exist, since clk_composite_get_parent was used to
determine the parent for clk_register.

Signed-off-by: Sean Anderson 
Acked-by: Lukasz Majewski 
---

Changes in v4:
- Return ENOTSUPP not ENOSYS with no set_parent

Changes in v3:
- Don't return an error code where a no-op would be fine


 drivers/clk/clk-composite.c | 57 +++--
 1 file changed, 35 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 2ff1d6b47f..819bfca2fc 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -24,7 +24,10 @@ static u8 clk_composite_get_parent(struct clk *clk)
(struct clk *)dev_get_clk_ptr(clk->dev) : clk);
struct clk *mux = composite->mux;
 
-   return clk_mux_get_parent(mux);
+   if (mux)
+   return clk_mux_get_parent(mux);
+   else
+   return 0;
 }
 
 static int clk_composite_set_parent(struct clk *clk, struct clk *parent)
@@ -34,7 +37,10 @@ static int clk_composite_set_parent(struct clk *clk, struct 
clk *parent)
const struct clk_ops *mux_ops = composite->mux_ops;
struct clk *mux = composite->mux;
 
-   return mux_ops->set_parent(mux, parent);
+   if (mux && mux_ops)
+   return mux_ops->set_parent(mux, parent);
+   else
+   return -ENOTSUPP;
 }
 
 static unsigned long clk_composite_recalc_rate(struct clk *clk)
@@ -44,7 +50,10 @@ static unsigned long clk_composite_recalc_rate(struct clk 
*clk)
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk *rate = composite->rate;
 
-   return rate_ops->get_rate(rate);
+   if (rate && rate_ops)
+   return rate_ops->get_rate(rate);
+   else
+   return clk_get_parent_rate(clk);
 }
 
 static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
@@ -54,7 +63,10 @@ static ulong clk_composite_set_rate(struct clk *clk, 
unsigned long rate)
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk *clk_rate = composite->rate;
 
-   return rate_ops->set_rate(clk_rate, rate);
+   if (rate && rate_ops)
+   return rate_ops->set_rate(clk_rate, rate);
+   else
+   return clk_get_rate(clk);
 }
 
 static int clk_composite_enable(struct clk *clk)
@@ -64,7 +76,10 @@ static int clk_composite_enable(struct clk *clk)
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk *gate = composite->gate;
 
-   return gate_ops->enable(gate);
+   if (gate && gate_ops)
+   return gate_ops->enable(gate);
+   else
+   return 0;
 }
 
 static int clk_composite_disable(struct clk *clk)
@@ -74,15 +89,12 @@ static int clk_composite_disable(struct clk *clk)
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk *gate = composite->gate;
 
-   gate_ops->disable(gate);
-
-   return 0;
+   if (gate && gate_ops)
+   return gate_ops->disable(gate);
+   else
+   return 0;
 }
 
-struct clk_ops clk_composite_ops = {
-   /* This will be set according to clk_register_composite */
-};
-
 struct clk *clk_register_composite(struct device *dev, const char *name,
   const char * const *parent_names,
   int num_parents, struct clk *mux,
@@ -96,7 +108,9 @@ struct clk *clk_register_composite(struct device *dev, const 
char *name,
struct clk *clk;
struct clk_composite *composite;
int ret;
-   struct clk_ops *composite_ops = _composite_ops;
+
+   if (!num_parents || (num_parents != 1 && !mux))
+   return ERR_PTR(-EINVAL);
 
composite = kzalloc(sizeof(*composite), GFP_KERNEL);
if (!composite)
@@ -105,8 +119,6 @@ struct clk *clk_register_composite(struct device *dev, 
const char *name,
if (mux && mux_ops) {
composite->mux = mux;
composite->mux_ops = mux_ops;
-   if (mux_ops->set_parent)
-   composite_ops->set_parent = clk_composite_set_parent;
mux->data = (ulong)composite;
}
 
@@ -115,11 +127,6 @@ struct clk *clk_register_composite(struct device *dev, 
const char *name,
clk = ERR_PTR(-EINVAL);
goto err;
   

[PATCH v8 04/21] clk: Fix clk_get_by_* handling of index

[Sean Anderson]

clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean
predicate instead of the index. Other clk_get_by_* functions got the clock
correctly, but passed a predicate instead of the index to clk_get_by_tail.
This could lead to confusing error messages.

Signed-off-by: Sean Anderson 
---

Changes in v7:
- New


 drivers/clk/clk-uclass.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index aa8dd9d027..c082fe95ff 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -121,7 +121,7 @@ static int clk_get_by_indexed_prop(struct udevice *dev, 
const char *prop_name,
 
 
return clk_get_by_index_tail(ret, dev_ofnode(dev), , "clocks",
-index > 0, clk);
+index, clk);
 }
 
 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
@@ -133,7 +133,7 @@ int clk_get_by_index(struct udevice *dev, int index, struct 
clk *clk)
 index, );
 
return clk_get_by_index_tail(ret, dev_ofnode(dev), , "clocks",
-index > 0, clk);
+index, clk);
 }
 
 int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
@@ -142,10 +142,10 @@ int clk_get_by_index_nodev(ofnode node, int index, struct 
clk *clk)
int ret;
 
ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
-index > 0, );
+index, );
 
return clk_get_by_index_tail(ret, node, , "clocks",
-index > 0, clk);
+index, clk);
 }
 
 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
-- 
2.25.1

[PATCH v8 09/21] dm: Fix error handling for dev_read_addr_ptr

[Sean Anderson]

dev_read_addr_ptr had different semantics depending on whether OF_LIVE was
enabled. This patch converts both implementations to return NULL on error,
and converts all call sites which check for FDT_ADDR_T_NONE to check for
NULL instead. This patch also removes the call to map_physmem, since we
have dev_remap_addr* for those semantics.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
Reviewed-by: Simon Glass 
---

Changes in v5:
- New


 drivers/clk/imx/clk-imx8mp.c  | 2 +-
 drivers/core/read.c   | 2 +-
 drivers/pinctrl/broadcom/pinctrl-bcm283x.c| 2 +-
 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 2 +-
 include/dm/read.h | 4 +++-
 5 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index a2693d2f7a..df30f4a087 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -281,7 +281,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", 
"sys_pll2_out", 1, 1));
 
base = dev_read_addr_ptr(dev);
-   if (base == (void *)FDT_ADDR_T_NONE)
+   if (!base)
return -EINVAL;
 
clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 
24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
diff --git a/drivers/core/read.c b/drivers/core/read.c
index 1f999b1b31..2a8813fff1 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -154,7 +154,7 @@ void *dev_read_addr_ptr(const struct udevice *dev)
 {
fdt_addr_t addr = dev_read_addr(dev);
 
-   return (addr == FDT_ADDR_T_NONE) ? NULL : map_sysmem(addr, 0);
+   return (addr == FDT_ADDR_T_NONE) ? NULL : addr;
 }
 
 void *dev_remap_addr(const struct udevice *dev)
diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c 
b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
index eb720f09f8..6961536a4d 100644
--- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
+++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
@@ -116,7 +116,7 @@ int bcm283x_pinctl_probe(struct udevice *dev)
}
 
priv->base_reg = dev_read_addr_ptr(dev);
-   if (priv->base_reg == (void *)FDT_ADDR_T_NONE) {
+   if (!priv->base_reg) {
debug("%s: Failed to get base address\n", __func__);
return -EINVAL;
}
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c 
b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index c7351f32bb..bd95662ed5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -630,7 +630,7 @@ int mtk_pinctrl_common_probe(struct udevice *dev,
int ret;
 
priv->base = dev_read_addr_ptr(dev);
-   if (priv->base == (void *)FDT_ADDR_T_NONE)
+   if (!priv->base)
return -EINVAL;
 
priv->soc = soc;
diff --git a/include/dm/read.h b/include/dm/read.h
index da8c7f25e7..d7183713dd 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -715,7 +715,9 @@ static inline fdt_addr_t dev_read_addr(const struct udevice 
*dev)
 
 static inline void *dev_read_addr_ptr(const struct udevice *dev)
 {
-   return devfdt_get_addr_ptr(dev);
+   void *addr = devfdt_get_addr_ptr(dev);
+
+   return ((fdt_addr_t)addr == FDT_ADDR_T_NONE) ? NULL : addr;
 }
 
 static inline fdt_addr_t dev_read_addr_pci(const struct udevice *dev)
-- 
2.25.1

[PATCH v8 00/21] riscv: Add Sipeed Maix support

[Sean Anderson]

This patch series adds support for Sipeed Maix boards and the Kendryte
K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
models are similar.

Known Bugs/Limitations:
- Accessing the AI ram hangs, limiting available ram to 6M
- Trying to boot an image with bootm fails with
  ERROR: Failed to allocate 0x7d60 bytes below 0x8000.

To flash u-boot to a maix bit, run
kflash -tp /dev/ -B bit_mic u-boot-dtb.bin

Boot output should look like the following:

U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)

DRAM:  8 MiB
In:serial@3800
Out:   serial@3800
Err:   serial@3800
=>

Changes for v8:
- Removed dependency on the patch "clk: Add functions to register CCF clock
  structs". Hopefully this will make reviewing easier.

Changes for v7:
- Split documentation from other board support
- Split IPI clear from other IPI cleanup
- Rebased onto a clean upstream. Hopefully this fixes any patching
  problems.

Changes for v6:
- Remove spi, pinmux, gpio, led, and wdt support --- to be added in separate
  patches
- Rebase onto master
- Clear IPIs before enabling them
- Reorganize code so checkpatch errors less

Changes for v5:
- Rebase onto master
- Add pinconf support
- Add gpio support
- Store environment in spi flash
- Group patches by prefix
- Add additional documentation
- Add SMP support
- Add WDT support

Changes for v4:
- Linted several patches
- Updated the copyright year for several files
- Added tests for syscon-reset, simple-pm-bus, and the pll calc_rate function
- Added/updated documentation
- Fixed SPI for the nor flash
- Fixed PLLs not enabling/setting rate properly
- RISCV_PRIV_1_9_1 now (un)defines all diferring CSRs, and also disables VM
- More devicetree changes

Changes for v3:
- Remove patch to set RV64I as default
- Remove patch for a separate sysctl driver
- Split off cpu frequency patch into its own series
- Reorder support/devicetree patches to come last
- Add patch for reset driver
- Add simple-pm-bus for busses with their own clocks
- Add additional documentation
- Reword mcounteren patch to refer to the RISC-V priv spec 1.9.1
- Many devicetree changes
- Switch to "make savedefconfig" to generate the config

Changes for v2:
- Many bugfixes for the device tree
- Modify the config to build without errors
- Add support for keeping internal PLL frequencies in-range
- Fix several rebase-induced artifacts

Sean Anderson (21):
  clk: Always use the supplied struct clk
  clk: Check that ops of composite clock components exist before calling
  clk: Unconditionally recursively en-/dis-able clocks
  clk: Fix clk_get_by_* handling of index
  clk: Add K210 pll support
  clk: Add a bypass clock for K210
  clk: Add K210 clock support
  dm: Add support for simple-pm-bus
  dm: Fix error handling for dev_read_addr_ptr
  reset: Add generic reset driver
  lib: Always set errno in hcreate_r
  riscv: Add headers for asm/global_data.h
  riscv: Clear pending interrupts before enabling IPIs
  riscv: Clean up IPI initialization code
  riscv: Add option to support RISC-V privileged spec 1.9
  riscv: Allow use of reset drivers
  riscv: Try to get cpu frequency from a "clocks" node if it exists
  riscv: Enable cpu clock if it is present
  riscv: Add device tree for K210 and Sipeed Maix BitM
  doc: riscv: Add documentation for Sipeed Maix Bit
  riscv: Add Sipeed Maix support

 MAINTAINERS   |   7 +
 arch/riscv/Kconfig|  14 +
 arch/riscv/cpu/cpu.c  |  15 +
 arch/riscv/cpu/start.S|   2 +
 arch/riscv/dts/Makefile   |   1 +
 arch/riscv/dts/k210-maix-bit.dts  |  47 ++
 arch/riscv/dts/k210.dtsi  | 594 
 arch/riscv/include/asm/csr.h  |  40 ++
 arch/riscv/include/asm/global_data.h  |   2 +
 arch/riscv/include/asm/smp.h  |  43 ++
 arch/riscv/lib/andes_plic.c   |  34 +-
 arch/riscv/lib/reset.c|   2 +
 arch/riscv/lib/sbi_ipi.c  |   5 +
 arch/riscv/lib/sifive_clint.c |  33 +-
 arch/riscv/lib/smp.c  |  56 +-
 arch/sandbox/dts/test.dts |  21 +
 arch/sandbox/include/asm/clk.h|   1 +
 board/sipeed/maix/Kconfig |  47 ++
 board/sipeed/maix/MAINTAINERS |  11 +
 board/sipeed/maix/Makefile|   5 +
 board/sipeed/maix/maix.c  |  41 ++
 configs/sandbox_defconfig |   3 +
 configs/sipeed_maix_bitm_defconfig|   8 +
 doc/board/index.rst   |   1 +
 doc/board/sipeed/index.rst|   9 +
 doc/board/sipeed/maix.rst | 298 
 .../bus/simple-pm-bus.txt |  44 ++
 .../mfd/kendryte,k210-sysctl.txt  |  33 +
 .../reset/syscon-reset.txt

[PATCH v8 03/21] clk: Unconditionally recursively en-/dis-able clocks

[Sean Anderson]

For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
just enable them as normal. The enable count is local to the struct clk,
but this will never result in the actual en-/dis-able op being called
(unless the same struct clk is enabled twice).

For clocks in the CCF, we always traverse up the tree when enabling.
Previously, CCF clocks without id set would be skipped, stopping the
traversal too early.

Signed-off-by: Sean Anderson 
---

Changes in v6:
- Fix disable incorrectly recursing into non-clock devices

Changes in v5:
- Clear enable_count on request

Changes in v4:
- Lint

Changes in v3:
- New


 drivers/clk/clk-uclass.c | 60 ++--
 1 file changed, 27 insertions(+), 33 deletions(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 71878474eb..aa8dd9d027 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -410,6 +410,7 @@ int clk_request(struct udevice *dev, struct clk *clk)
ops = clk_dev_ops(dev);
 
clk->dev = dev;
+   clk->enable_count = 0;
 
if (!ops->request)
return 0;
@@ -521,7 +522,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 int clk_enable(struct clk *clk)
 {
const struct clk_ops *ops;
-   struct clk *clkp = NULL;
int ret;
 
debug("%s(clk=%p)\n", __func__, clk);
@@ -530,32 +530,29 @@ int clk_enable(struct clk *clk)
ops = clk_dev_ops(clk->dev);
 
if (CONFIG_IS_ENABLED(CLK_CCF)) {
-   /* Take id 0 as a non-valid clk, such as dummy */
-   if (clk->id && !clk_get_by_id(clk->id, )) {
-   if (clkp->enable_count) {
-   clkp->enable_count++;
-   return 0;
-   }
-   if (clkp->dev->parent &&
-   device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
-   ret = 
clk_enable(dev_get_clk_ptr(clkp->dev->parent));
-   if (ret) {
-   printf("Enable %s failed\n",
-  clkp->dev->parent->name);
-   return ret;
-   }
+   if (clk->enable_count) {
+   clk->enable_count++;
+   return 0;
+   }
+   if (clk->dev->parent &&
+   device_get_uclass_id(clk->dev->parent) == UCLASS_CLK) {
+   ret = clk_enable(dev_get_clk_ptr(clk->dev->parent));
+   if (ret) {
+   printf("Enable %s failed\n",
+  clk->dev->parent->name);
+   return ret;
}
}
 
if (ops->enable) {
ret = ops->enable(clk);
if (ret) {
-   printf("Enable %s failed\n", clk->dev->name);
+   printf("Enable %s failed (error %d)\n",
+  clk->dev->name, ret);
return ret;
}
}
-   if (clkp)
-   clkp->enable_count++;
+   clk->enable_count++;
} else {
if (!ops->enable)
return -ENOSYS;
@@ -581,7 +578,6 @@ int clk_enable_bulk(struct clk_bulk *bulk)
 int clk_disable(struct clk *clk)
 {
const struct clk_ops *ops;
-   struct clk *clkp = NULL;
int ret;
 
debug("%s(clk=%p)\n", __func__, clk);
@@ -590,29 +586,27 @@ int clk_disable(struct clk *clk)
ops = clk_dev_ops(clk->dev);
 
if (CONFIG_IS_ENABLED(CLK_CCF)) {
-   if (clk->id && !clk_get_by_id(clk->id, )) {
-   if (clkp->enable_count == 0) {
-   printf("clk %s already disabled\n",
-  clkp->dev->name);
-   return 0;
-   }
-
-   if (--clkp->enable_count > 0)
-   return 0;
+   if (clk->enable_count == 0) {
+   printf("clk %s already disabled\n",
+  clk->dev->name);
+   return 0;
}
 
+   if (--clk->enable_count > 0)
+   return 0;
+
if (ops->disable) {
ret = ops->disable(clk);
if (ret)
return ret;
}
 
-   if (clkp && clkp->dev->parent &&
-   device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
-   ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
+   if (clk->dev->parent &&
+   

[PATCH v8 01/21] clk: Always use the supplied struct clk

[Sean Anderson]

CCF clocks should always use the struct clock passed to their methods for
extracting the driver-specific clock information struct. Previously, many
functions would use the clk->dev->priv if the device was bound. This could
cause problems with composite clocks. The individual clocks in a composite
clock did not have the ->dev field filled in. This was fine, because the
device-specific clock information would be used. However, since there was
no ->dev, there was no way to get the parent clock. This caused the
recalc_rate method of the CCF divider clock to fail. One option would be to
use the clk->priv field to get the composite clock and from there get the
appropriate parent device. However, this would tie the implementation to
the composite clock. In general, different devices should not rely on the
contents of ->priv from another device.

The simple solution to this problem is to just always use the supplied
struct clock. The composite clock now fills in the ->dev pointer of its
child clocks.  This allows child clocks to make calls like clk_get_parent()
without issue.

imx avoided the above problem by using a custom get_rate function with
composite clocks.

Signed-off-by: Sean Anderson 
Acked-by: Lukasz Majewski 
---

Changes in v4:
- Lint

Changes in v3:
- Documented new assumptions in the CCF
- Wrapped docs to 80 columns


 doc/imx/clk/ccf.txt| 63 +-
 drivers/clk/clk-composite.c|  7 
 drivers/clk/clk-divider.c  |  6 ++--
 drivers/clk/clk-fixed-factor.c |  3 +-
 drivers/clk/clk-gate.c |  6 ++--
 drivers/clk/clk-mux.c  | 12 +++
 drivers/clk/imx/clk-gate2.c|  4 +--
 7 files changed, 50 insertions(+), 51 deletions(-)

diff --git a/doc/imx/clk/ccf.txt b/doc/imx/clk/ccf.txt
index 36b60dc438..e40ac360e8 100644
--- a/doc/imx/clk/ccf.txt
+++ b/doc/imx/clk/ccf.txt
@@ -1,42 +1,37 @@
 Introduction:
 =
 
-This documentation entry describes the Common Clock Framework [CCF]
-port from Linux kernel (v5.1.12) to U-Boot.
+This documentation entry describes the Common Clock Framework [CCF] port from
+Linux kernel (v5.1.12) to U-Boot.
 
-This code is supposed to bring CCF to IMX based devices (imx6q, imx7
-imx8). Moreover, it also provides some common clock code, which would
-allow easy porting of CCF Linux code to other platforms.
+This code is supposed to bring CCF to IMX based devices (imx6q, imx7 imx8).
+Moreover, it also provides some common clock code, which would allow easy
+porting of CCF Linux code to other platforms.
 
 Design decisions:
 =
 
-* U-Boot's driver model [DM] for clk differs from Linux CCF. The most
-  notably difference is the lack of support for hierarchical clocks and
-  "clock as a manager driver" (single clock DTS node acts as a starting
-  point for all other clocks).
+* U-Boot's driver model [DM] for clk differs from Linux CCF. The most notably
+  difference is the lack of support for hierarchical clocks and "clock as a
+  manager driver" (single clock DTS node acts as a starting point for all other
+  clocks).
 
-* The clk_get_rate() caches the previously read data if CLK_GET_RATE_NOCACHE
-  is not set (no need for recursive access).
+* The clk_get_rate() caches the previously read data if CLK_GET_RATE_NOCACHE is
+  not set (no need for recursive access).
 
-* On purpose the "manager" clk driver (clk-imx6q.c) is not using large
-  table to store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] = 
-  Instead we use udevice's linked list for the same class (UCLASS_CLK).
+* On purpose the "manager" clk driver (clk-imx6q.c) is not using large table to
+  store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] =  Instead we
+  use udevice's linked list for the same class (UCLASS_CLK).
 
   Rationale:
   --
-When porting the code as is from Linux, one would need ~1KiB of RAM to
-store it. This is way too much if we do plan to use this driver in SPL.
+When porting the code as is from Linux, one would need ~1KiB of RAM to 
store
+it. This is way too much if we do plan to use this driver in SPL.
 
 * The "central" structure of this patch series is struct udevice and its
   uclass_priv field contains the struct clk pointer (to the originally created
   one).
 
-* Up till now U-Boot's driver model (DM) CLK operates on udevice (main
-  access to clock is by udevice ops)
-  In the CCF the access to struct clk (embodying pointer to *dev) is
-  possible via dev_get_clk_ptr() (it is a wrapper on dev_get_uclass_priv()).
-
 * To keep things simple the struct udevice's uclass_priv pointer is used to
   store back pointer to corresponding struct clk. However, it is possible to
   modify clk-uclass.c file and add there struct uc_clk_priv, which would have
@@ -45,13 +40,17 @@ Design decisions:
   setting .per_device_auto_alloc_size = sizeof(struct uc_clk_priv)) the
   uclass_priv stores the pointer to struct clk.
 
+* Non-CCF clocks do not have a pointer to a clock in 

Re: [PATCH] Revert "mpc85xx: ddr: Always start DDR RAM in Self Refresh mode"

[Joakim Tjernlund]

On Fri, 2020-04-10 at 11:40 +, Priyanka Jain wrote:
> 
> > -Original Message-
> > From: Joakim Tjernlund 
> > Sent: Thursday, April 9, 2020 6:24 PM
> > To: Priyanka Jain ; Biwen Li (OSS)
> > 
> > Cc: u-boot@lists.denx.de; Biwen Li ; Jiafei Pan
> > 
> > Subject: Re: [PATCH] Revert "mpc85xx: ddr: Always start DDR RAM in Self
> > Refresh mode"
> > 
> > On Thu, 2020-04-09 at 20:44 +0800, Biwen Li wrote:
> > 
> > This revert will bring back another bug, can you try finding out why it does
> > work?
> > May there are some minor tweaks needed ?
> > 
> >   Jocke
> The patch has impacted boot to prompt on many powerpc boards.
> I agree with you that we also need to have solution to the original problem 
> reported by you.
> We are working on fixing of DDR errata workaround implementation issue that 
> you reported.

Is anyone working on the eSPI driver as well? I recall someone at NXP 
volunteered but cannot recall who.

> 
> But I need this workaround patch to be reverted now as a quick fix for 
> v2020.04 release which is only few days away.

I see

 Jocke

> 
> Thanks
> Priyanka
> > > From: Biwen Li 
> > > 
> > > This reverts commit 2a5d5d27edfbdb0e02a7fcf05569f92c02ae44ee.
> > > After applied this patch, failed to boot to uboot(hang in ddr init) on
> > > P3041DS, P4080DS and so on.
> > > ---
> > >  drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 13 +++--
> > >  1 file changed, 7 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
> > > b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
> > > index 952b296dd8..a9b085db8c 100644
> > > --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
> > > +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
> > > @@ -370,8 +370,6 @@ step2:
> > > debug("Setting DEBUG_3[21] to 0x%08x\n",
> > > in_be32(>debug[2]));
> > > 
> > >  #endif /* part 1 of the workaound */
> > > -   /* Always start in self-refresh, clear after MEM_EN */
> > > -   setbits_be32(>sdram_cfg_2, SDRAM_CFG2_FRC_SR);
> > > 
> > > /*
> > >  * 500 painful micro-seconds must elapse between @@ -384,6
> > > +382,8 @@ step2:
> > > 
> > >  #ifdef CONFIG_DEEP_SLEEP
> > > if (is_warm_boot()) {
> > > +   /* enter self-refresh */
> > > +   setbits_be32(>sdram_cfg_2, SDRAM_CFG2_FRC_SR);
> > > /* do board specific memory setup */
> > > board_mem_sleep_setup();
> > > temp_sdram_cfg = (in_be32(>sdram_cfg) |
> > > SDRAM_CFG_BI); @@ -395,10 +395,6 @@ step2:
> > > out_be32(>sdram_cfg, temp_sdram_cfg |
> > SDRAM_CFG_MEM_EN);
> > > asm volatile("sync;isync");
> > > 
> > > -   /* Exit self-refresh after DDR conf as some ddr memories can 
> > > fail. */
> > > -   clrbits_be32(>sdram_cfg_2, SDRAM_CFG2_FRC_SR);
> > > -   asm volatile("sync;isync");
> > > -
> > > total_gb_size_per_controller = 0;
> > > for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
> > > if (!(regs->cs[i].config & 0x8000)) @@ -548,4
> > > +544,9 @@ step2:
> > > clrbits_be32(>sdram_cfg, 0x2);
> > > }
> > >  #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
> > > +#ifdef CONFIG_DEEP_SLEEP
> > > +   if (is_warm_boot())
> > > +   /* exit self-refresh */
> > > +   clrbits_be32(>sdram_cfg_2, SDRAM_CFG2_FRC_SR);
> > > +#endif
> > >  }
> > > --
> > > 2.17.1
> > > 

[RFC PATCH 0/2] Move FSP-S configuration to device-tree

[Bernhard Messerklinger]

This patch series moves the configuration of FPS-S for Apollo Lake
based SoCs from the code to the device-tree.

This is similar to the previous patch series for FSP-M.


Bernhard Messerklinger (2):
  arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
  arch: x86: apl: Read FSP-S configuration from device-tree

 arch/x86/cpu/apollolake/fsp_s.c   | 1084 +++--
 arch/x86/dts/chromebook_coral.dts |   35 +-
 .../asm/arch-apollolake/fsp/fsp_s_upd.h   |  268 
 .../fsp/fsp2/apollolake/fsp-m.txt |  310 +
 .../fsp/fsp2/apollolake/fsp-s.txt |  485 
 5 files changed, 1807 insertions(+), 375 deletions(-)
 create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt
 create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt

-- 
2.26.0

[RFC PATCH 2/2] arch: x86: apl: Read FSP-S configuration from device-tree

[Bernhard Messerklinger]

Move FSP-S configuration to the device-tree like it's already done for
other SoCs (Baytrail).

Signed-off-by: Bernhard Messerklinger 
---

 arch/x86/cpu/apollolake/fsp_s.c   | 1070 +++--
 arch/x86/dts/chromebook_coral.dts |   35 +-
 .../asm/arch-apollolake/fsp/fsp_s_upd.h   |  268 +
 .../fsp/fsp2/apollolake/fsp-m.txt |  310 +
 .../fsp/fsp2/apollolake/fsp-s.txt |  485 
 5 files changed, 1799 insertions(+), 369 deletions(-)
 create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt
 create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 458825bc49..7d516adc92 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -27,309 +27,90 @@
 #define INTEL_GSPI_MAX 3
 #define MAX_USB2_PORTS 8
 
-enum {
-   CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
-   CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
-};
-
-/* Serial IRQ control. SERIRQ_QUIET is the default (0) */
-enum serirq_mode {
-   SERIRQ_QUIET,
-   SERIRQ_CONTINUOUS,
-   SERIRQ_OFF,
-};
-
-struct gspi_cfg {
-   /* Bus speed in MHz */
-   u32 speed_mhz;
-   /* Bus should be enabled prior to ramstage with temporary base */
-   u8 early_init;
-};
-
-/*
- * This structure will hold data required by common blocks.
- * These are soc specific configurations which will be filled by soc.
- * We'll fill this structure once during init and use the data in common block.
- */
-struct soc_intel_common_config {
-   int chipset_lockdown;
-   struct gspi_cfg gspi[INTEL_GSPI_MAX];
-};
-
-enum pnp_settings {
-   PNP_PERF,
-   PNP_POWER,
-   PNP_PERF_POWER,
-};
-
-struct usb2_eye_per_port {
-   u8 per_port_tx_pe_half;
-   u8 per_port_pe_txi_set;
-   u8 per_port_txi_set;
-   u8 hs_skew_sel;
-   u8 usb_tx_emphasis_en;
-   u8 per_port_rxi_set;
-   u8 hs_npre_drv_sel;
-   u8 override_en;
-};
-
-struct apl_config {
-   /* Common structure containing soc config data required by common code*/
-   struct soc_intel_common_config common_soc_config;
-
-   /*
-* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
-* four CLKREQ inputs, but six root ports. Root ports without an
-* associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
-*/
-   u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
-
-   /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */
-   u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS];
-
-   /* De-emphasis enable configuration for each PCIe root port */
-   u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS];
-
-   /*
-* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR mode Number of dealy elements.Each = 125pSec.
-*/
-   u32 emmc_tx_cmd_cntl;
-
-   /*
-* [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
-*/
-   u32 emmc_tx_data_cntl1;
-
-   /*
-* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
-* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
-* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR12/Compatibility mode Number of dealy elements.
-*   Each = 125pSec.
-*/
-   u32 emmc_tx_data_cntl2;
-
-   /*
-* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
-* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
-* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR12/Compatibility mode Number of dealy elements.
-*   Each = 125pSec.
-*/
-   u32 emmc_rx_cmd_data_cntl1;
-
-   /*
-* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
-* [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
-*/
-   u32 emmc_rx_strobe_cntl;
-
-   /*
-* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
-* [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
-*/
-   u32 emmc_rx_cmd_data_cntl2;
-
-   /* Select the eMMC max speed allowed */
-   u32 emmc_host_max_speed;
-
-   /* Specifies on which IRQ the SCI will internally appear */
-   u32 sci_irq;
-
-   /* Configure serial IRQ (SERIRQ) line */
-   enum serirq_mode serirq_mode;
-
-   /* Configure LPSS S0ix Enable */
-   bool lpss_s0ix_enable;
-
-   /* Enable DPTF support */
-   bool dptf_enable;
-
-   /* TCC activation offset value in degrees Celsius */
-   int tcc_offset;
-
-   /*
-* Configure Audio clk gate and power gate
-* IOSF-SB port ID 92 offset 0x530 [5] and [3]
-*/
- 

[RFC PATCH 1/2] arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled

[Bernhard Messerklinger]

Only load VBT if it's present in the u-boot.rom.

Signed-off-by: Bernhard Messerklinger 
---

 arch/x86/cpu/apollolake/fsp_s.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 1f22c1ea3c..458825bc49 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -327,16 +327,17 @@ int fsps_update_config(struct udevice *dev, ulong 
rom_offset,
 {
struct fsp_s_config *cfg = >config;
struct apl_config *apl;
+#ifdef CONFIG_HAVE_VBT
struct binman_entry vbt;
-   void *buf;
int ret;
+   void *vbt_buf;
 
ret = binman_entry_find("intel-vbt", );
if (ret)
return log_msg_ret("Cannot find VBT", ret);
vbt.image_pos += rom_offset;
-   buf = malloc(vbt.size);
-   if (!buf)
+   vbt_buf = malloc(vbt.size);
+   if (!vbt_buf)
return log_msg_ret("Alloc VBT", -ENOMEM);
 
/*
@@ -344,11 +345,12 @@ int fsps_update_config(struct udevice *dev, ulong 
rom_offset,
 * memory-mapped SPI at present.
 */
bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
-   memcpy(buf, (void *)vbt.image_pos, vbt.size);
+   memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size);
bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
-   if (*(u32 *)buf != VBT_SIGNATURE)
+   if (*(u32 *)vbt_buf != VBT_SIGNATURE)
return log_msg_ret("VBT signature", -EINVAL);
-   cfg->graphics_config_ptr = (ulong)buf;
+   cfg->graphics_config_ptr = (ulong)vbt_buf;
+#endif
 
apl = malloc(sizeof(*apl));
if (!apl)
-- 
2.26.0

RE: [PATCH] Revert "mpc85xx: ddr: Always start DDR RAM in Self Refresh mode"

[Priyanka Jain]

>-Original Message-
>From: Joakim Tjernlund 
>Sent: Thursday, April 9, 2020 6:24 PM
>To: Priyanka Jain ; Biwen Li (OSS)
>
>Cc: u-boot@lists.denx.de; Biwen Li ; Jiafei Pan
>
>Subject: Re: [PATCH] Revert "mpc85xx: ddr: Always start DDR RAM in Self
>Refresh mode"
>
>On Thu, 2020-04-09 at 20:44 +0800, Biwen Li wrote:
>
>This revert will bring back another bug, can you try finding out why it does
>work?
>May there are some minor tweaks needed ?
>
>   Jocke
The patch has impacted boot to prompt on many powerpc boards.
I agree with you that we also need to have solution to the original problem 
reported by you.
We are working on fixing of DDR errata workaround implementation issue that you 
reported.

But I need this workaround patch to be reverted now as a quick fix for v2020.04 
release which is only few days away.

Thanks
Priyanka
>>
>> From: Biwen Li 
>>
>> This reverts commit 2a5d5d27edfbdb0e02a7fcf05569f92c02ae44ee.
>> After applied this patch, failed to boot to uboot(hang in ddr init) on
>> P3041DS, P4080DS and so on.
>> ---
>>  drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 13 +++--
>>  1 file changed, 7 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
>> b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
>> index 952b296dd8..a9b085db8c 100644
>> --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
>> +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
>> @@ -370,8 +370,6 @@ step2:
>> debug("Setting DEBUG_3[21] to 0x%08x\n",
>> in_be32(>debug[2]));
>>
>>  #endif /* part 1 of the workaound */
>> -   /* Always start in self-refresh, clear after MEM_EN */
>> -   setbits_be32(>sdram_cfg_2, SDRAM_CFG2_FRC_SR);
>>
>> /*
>>  * 500 painful micro-seconds must elapse between @@ -384,6
>> +382,8 @@ step2:
>>
>>  #ifdef CONFIG_DEEP_SLEEP
>> if (is_warm_boot()) {
>> +   /* enter self-refresh */
>> +   setbits_be32(>sdram_cfg_2, SDRAM_CFG2_FRC_SR);
>> /* do board specific memory setup */
>> board_mem_sleep_setup();
>> temp_sdram_cfg = (in_be32(>sdram_cfg) |
>> SDRAM_CFG_BI); @@ -395,10 +395,6 @@ step2:
>> out_be32(>sdram_cfg, temp_sdram_cfg |
>SDRAM_CFG_MEM_EN);
>> asm volatile("sync;isync");
>>
>> -   /* Exit self-refresh after DDR conf as some ddr memories can fail. */
>> -   clrbits_be32(>sdram_cfg_2, SDRAM_CFG2_FRC_SR);
>> -   asm volatile("sync;isync");
>> -
>> total_gb_size_per_controller = 0;
>> for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
>> if (!(regs->cs[i].config & 0x8000)) @@ -548,4
>> +544,9 @@ step2:
>> clrbits_be32(>sdram_cfg, 0x2);
>> }
>>  #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
>> +#ifdef CONFIG_DEEP_SLEEP
>> +   if (is_warm_boot())
>> +   /* exit self-refresh */
>> +   clrbits_be32(>sdram_cfg_2, SDRAM_CFG2_FRC_SR);
>> +#endif
>>  }
>> --
>> 2.17.1
>>

[RFC PATCH 3/3] mips: spl: Flush cache before jumping to U-Boot proper

[Stefan Roese]

This patch adds a MIPS specific jump_to_image_no_args() implementation,
which flushes the U-Boot proper image loaded from the boot device in
SPL before jumping to it.

It has been noticed on MT76x8, that this cache flush is needed. Other
MIPS platforms might need it as well.

Signed-off-by: Stefan Roese 
Cc: Weijie Gao 
Cc: Daniel Schwierzeck 
Cc: Simon Goldschmidt 
---
 arch/mips/lib/boot.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c
index db862f6379..bc620abd9b 100644
--- a/arch/mips/lib/boot.c
+++ b/arch/mips/lib/boot.c
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -21,3 +22,16 @@ unsigned long do_go_exec(ulong (*entry)(int, char * const 
[]),
 
return entry(argc, argv);
 }
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+   typedef void __noreturn (*image_entry_noargs_t)(void);
+   image_entry_noargs_t image_entry =
+   (image_entry_noargs_t)spl_image->entry_point;
+
+   /* Flush cache before jumping to application */
+   flush_cache((unsigned long)spl_image->load_addr, spl_image->size);
+
+   debug("image entry point: 0x%lx\n", spl_image->entry_point);
+   image_entry();
+}
-- 
2.26.0

[RFC PATCH 1/3] spl: spl_nor: Move legacy image loading into spl_legacy.c

[Stefan Roese]

Move the legacy image loading into spl_legacy.c. This makes it easier
to extend the legacy image handling with new features that other
SPL loaders might use (e.g. spl_spi.c etc).

No functional change intended.

Signed-off-by: Stefan Roese 
Cc: Weijie Gao 
Cc: Daniel Schwierzeck 
Cc: Simon Goldschmidt 
---
RFC comment: I'm sendig these 3 patches as RFC and once we've come to an
agreement on these (Acked etc), I'll integrate them into the mtmips SPL
patchset from Weijie and will send v7.

Thanks,
Stefan

 common/spl/spl_legacy.c | 20 
 common/spl/spl_nor.c| 27 +--
 include/spl.h   | 13 +
 3 files changed, 46 insertions(+), 14 deletions(-)

diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c
index 772135193e..7f00fc8885 100644
--- a/common/spl/spl_legacy.c
+++ b/common/spl/spl_legacy.c
@@ -51,3 +51,23 @@ int spl_parse_legacy_header(struct spl_image_info *spl_image,
 
return 0;
 }
+
+int spl_load_legacy_img(struct spl_image_info *spl_image,
+   struct spl_load_info *load, ulong header)
+{
+   struct image_header hdr;
+   int ret;
+
+   /* Read header into local struct */
+   load->read(load, header, sizeof(hdr), );
+
+   ret = spl_parse_image_header(spl_image, );
+   if (ret)
+   return ret;
+
+   /* Read image */
+   load->read(load, header + sizeof(hdr), spl_image->size,
+  (void *)(unsigned long)spl_image->load_addr);
+
+   return 0;
+}
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index b1e79b9ded..3f03ffe6a3 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -24,7 +24,6 @@ unsigned long __weak spl_nor_get_uboot_base(void)
 static int spl_nor_load_image(struct spl_image_info *spl_image,
  struct spl_boot_device *bootdev)
 {
-   int ret;
__maybe_unused const struct image_header *header;
__maybe_unused struct spl_load_info load;
 
@@ -43,6 +42,8 @@ static int spl_nor_load_image(struct spl_image_info 
*spl_image,
header = (const struct image_header *)CONFIG_SYS_OS_BASE;
 #ifdef CONFIG_SPL_LOAD_FIT
if (image_get_magic(header) == FDT_MAGIC) {
+   int ret;
+
debug("Found FIT\n");
load.bl_len = 1;
load.read = spl_nor_load_read;
@@ -61,6 +62,7 @@ static int spl_nor_load_image(struct spl_image_info 
*spl_image,
 #endif
if (image_get_os(header) == IH_OS_LINUX) {
/* happy - was a Linux */
+   int ret;
 
ret = spl_parse_image_header(spl_image, header);
if (ret)
@@ -93,11 +95,9 @@ static int spl_nor_load_image(struct spl_image_info 
*spl_image,
debug("Found FIT format U-Boot\n");
load.bl_len = 1;
load.read = spl_nor_load_read;
-   ret = spl_load_simple_fit(spl_image, ,
- spl_nor_get_uboot_base(),
- (void *)header);
-
-   return ret;
+   return spl_load_simple_fit(spl_image, ,
+  spl_nor_get_uboot_base(),
+  (void *)header);
}
 #endif
if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
@@ -107,14 +107,13 @@ static int spl_nor_load_image(struct spl_image_info 
*spl_image,
  spl_nor_get_uboot_base());
}
 
-   ret = spl_parse_image_header(spl_image,
-   (const struct image_header *)spl_nor_get_uboot_base());
-   if (ret)
-   return ret;
-
-   memcpy((void *)(unsigned long)spl_image->load_addr,
-  (void *)(spl_nor_get_uboot_base() + sizeof(struct image_header)),
-  spl_image->size);
+   /* Legacy image handling */
+   if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_SUPPORT)) {
+   load.bl_len = 1;
+   load.read = spl_nor_load_read;
+   return spl_load_legacy_img(spl_image, ,
+  spl_nor_get_uboot_base());
+   }
 
return 0;
 }
diff --git a/include/spl.h b/include/spl.h
index 6087cd793c..c6c64b6a72 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -219,6 +219,19 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 #define SPL_COPY_PAYLOAD_ONLY  1
 #define SPL_FIT_FOUND  2
 
+/**
+ * spl_load_legacy_img() - Loads a legacy image from a device.
+ * @spl_image: Image description to set up
+ * @load:  Structure containing the information required to load data.
+ * @header:Pointer to image header (including appended image)
+ *
+ * Reads an legacy image from the device. Loads u-boot image to
+ * specified load address.
+ * Returns 0 on success.
+ */
+int spl_load_legacy_img(struct 

[RFC PATCH 2/3] spl: spl_legacy: Add lzma decompression support for legacy image

[Stefan Roese]

From: Weijie Gao 

This patch adds support for decompressing LZMA compressed u-boot payload
in legacy uImage format.

Using this patch together with u-boot-lzma.img may be useful for some
platforms as they can reduce the size and load time of u-boot payload.

Signed-off-by: Weijie Gao 
Signed-off-by: Stefan Roese 
Cc: Daniel Schwierzeck 
Cc: Simon Goldschmidt 
---
 common/spl/spl_legacy.c | 50 +++--
 1 file changed, 48 insertions(+), 2 deletions(-)

diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c
index 7f00fc8885..41734c026f 100644
--- a/common/spl/spl_legacy.c
+++ b/common/spl/spl_legacy.c
@@ -4,8 +4,15 @@
  */
 
 #include 
+#include 
 #include 
 
+#include 
+#include 
+#include 
+
+#define LZMA_LEN   (1 << 20)
+
 int spl_parse_legacy_header(struct spl_image_info *spl_image,
const struct image_header *header)
 {
@@ -55,7 +62,10 @@ int spl_parse_legacy_header(struct spl_image_info *spl_image,
 int spl_load_legacy_img(struct spl_image_info *spl_image,
struct spl_load_info *load, ulong header)
 {
+   __maybe_unused SizeT lzma_len;
+   __maybe_unused void *src;
struct image_header hdr;
+   ulong dataptr;
int ret;
 
/* Read header into local struct */
@@ -65,9 +75,45 @@ int spl_load_legacy_img(struct spl_image_info *spl_image,
if (ret)
return ret;
 
+   dataptr = header + sizeof(hdr);
+
/* Read image */
-   load->read(load, header + sizeof(hdr), spl_image->size,
-  (void *)(unsigned long)spl_image->load_addr);
+   switch (image_get_comp()) {
+   case IH_COMP_NONE:
+   load->read(load, dataptr, spl_image->size,
+  (void *)(unsigned long)spl_image->load_addr);
+   break;
+
+#if IS_ENABLED(CONFIG_SPL_LZMA)
+   case IH_COMP_LZMA:
+   lzma_len = LZMA_LEN;
+
+   debug("LZMA: Decompressing %08lx to %08lx\n",
+ dataptr, spl_image->load_addr);
+   src = malloc(spl_image->size);
+   if (!src) {
+   printf("Unable to allocate %d bytes for LZMA\n",
+  spl_image->size);
+   return -ENOMEM;
+   }
+
+   load->read(load, dataptr, spl_image->size, src);
+   ret = lzmaBuffToBuffDecompress((void *)spl_image->load_addr,
+  _len, src, spl_image->size);
+   if (ret) {
+   printf("LZMA decompression error: %d\n", ret);
+   return ret;
+   }
+
+   spl_image->size = lzma_len;
+   break;
+#endif
+
+   default:
+   debug("Compression method %s is not supported\n",
+ genimg_get_comp_short_name(image_get_comp()));
+   return -EINVAL;
+   }
 
return 0;
 }
-- 
2.26.0

Re: [PATCH v2 1/2] arm: stm32mp: activate data cache in SPL and before relocation

[Marek Vasut]

On 4/9/20 8:32 PM, Patrick DELAUNAY wrote:
> Dear Marek,
> 
>> From: Marek Vasut 
>> Sent: vendredi 3 avril 2020 23:32
>>
>> On 4/3/20 11:25 AM, Patrick Delaunay wrote:
>> [...]
>>> diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
>>> index 36a9205819..c22c1a9bbc 100644
>>> --- a/arch/arm/mach-stm32mp/cpu.c
>>> +++ b/arch/arm/mach-stm32mp/cpu.c
>>> @@ -75,6 +75,12 @@
>>>  #define PKG_SHIFT  27
>>>  #define PKG_MASK   GENMASK(2, 0)
>>>
>>> +/*
>>> + * early TLB into the .data section so that it not get cleared
>>> + * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)  */
>>> +u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
>>
>> Can you early-malloc this one ?
> 
> I try to early maloc and it is failing because my code in arch_cpu_init() is 
> executed before 
> the early poll initialization done in spl_common_init () called by 
> spl_early_init()
> So it too late for my use case
> 
> And if I initialise the MMU and the cache after this function it is too late, 
> as
> dm_init_and_scan and fdt parsin is also called in spl_common_init()

Aha, OK. Can you document it in the commit message ? That's a real good
piece of information.

>> (why do you need this in __section("data") ?)
> 
> I try to use .bss and it is failing because the bss is resetted to 0 in SPL 
> after board_init_f, and the MMU is cleared without notice.
> 
> In fact BBS is not available, board_init_f() can use only stack variables
> and global_data (see README:258).
> 
> When I investigate the issue, I found CONFIG_SPL_EARLY_BSS
> that explain this point :
> 
> config SPL_EARLY_BSS
>   depends on ARM && !ARM64
>   bool "Allows initializing BSS early before entering board_init_f"
>   help
> On some platform we have sufficient memory available early on to
> allow setting up and using a basic BSS prior to entering
> board_init_f. Activating this option will also de-activate the
> clearing of BSS during the SPL relocation process, thus allowing
> to carry state from board_init_f to board_init_r by way of BSS.
> 
> So it is s compromise between harcoded addred (end of SYSRAM)
> or glabal variable in .data section
> 
> V2 patch with .data seems more elegant for me (it avoid assumption on
> U-Boot size for preloc case).
> 
> And if you have size issue for SPL you can deactivate cache for SPL only
> (CONFIG_SPL_SYS_DCACHE_OFF).

OK