Re: [PATCH v1 07/10] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian.
On Sat, Apr 25, 2020 at 12:52 AM Sylwester Nawrocki
wrote:
>
> From: Nicolas Saenz Julienne
>
> Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
> an in depth explanation and two fixes from Johannes Berg:
> e7d4a95da86e0 "bitfield: fix *_encode_bits()",
> 37a3862e12382 "bitfield: add u8 helpers".
>
> Signed-off-by: Nicolas Saenz Julienne
> Signed-off-by: Sylwester Nawrocki
nits: remove the ending period in the commit title
> ---
> Changes since RFC:
> - new patch.
> ---
> include/linux/bitfield.h | 46 ++
> 1 file changed, 46 insertions(+)
>
> diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
> index 8b9d6ff..4964213 100644
> --- a/include/linux/bitfield.h
> +++ b/include/linux/bitfield.h
> @@ -103,4 +103,50 @@
> (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
> })
>
> +extern void __compiletime_error("value doesn't fit into mask")
> +__field_overflow(void);
> +extern void __compiletime_error("bad bitfield mask")
> +__bad_mask(void);
> +static __always_inline u64 field_multiplier(u64 field)
> +{
> + if ((field | (field - 1)) & ((field | (field - 1)) + 1))
> + __bad_mask();
> + return field & -field;
> +}
> +static __always_inline u64 field_mask(u64 field)
> +{
> + return field / field_multiplier(field);
> +}
> +#define MAKE_OP(type,base,to,from) \
> +static __always_inline __##type type##_encode_bits(base v, base field) \
> +{ \
> + if (__builtin_constant_p(v) && (v & ~field_mask(field)))\
> + __field_overflow(); \
> + return to((v & field_mask(field)) * field_multiplier(field)); \
> +} \
> +static __always_inline __##type type##_replace_bits(__##type old, \
> + base val, base field) \
> +{ \
> + return (old & ~to(field)) | type##_encode_bits(val, field); \
> +} \
> +static __always_inline void type##p_replace_bits(__##type *p, \
> + base val, base field) \
> +{ \
> + *p = (*p & ~to(field)) | type##_encode_bits(val, field);\
> +} \
> +static __always_inline base type##_get_bits(__##type v, base field)\
> +{ \
> + return (from(v) & field)/field_multiplier(field); \
> +}
> +#define __MAKE_OP(size)
> \
> + MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \
> + MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \
> + MAKE_OP(u##size,u##size,,)
> +MAKE_OP(u8,u8,,)
> +__MAKE_OP(16)
> +__MAKE_OP(32)
> +__MAKE_OP(64)
> +#undef __MAKE_OP
> +#undef MAKE_OP
> +
> #endif
Could we add blank line between macros and functions to improve some readablity?
Regards,
Bin
Re: [PATCH v1 02/10] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq
On Sat, Apr 25, 2020 at 12:51 AM Sylwester Nawrocki wrote: > > There might be hardware configurations where 64-bit data accesses > to XHCI registers are not supported properly. This patch removes > the readq/writeq so always two 32-bit accesses are used to read/write > 64-bit XHCI registers, similarly as it is done in Linux kernel. > > This patch fixes operation of the XHCI controller on RPI4 Broadcom > BCM2711 SoC based board, where the VL805 USB XHCI controller is > connected to the PCIe Root Complex, which is attached to the system > through the SCB bridge. > > Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely > the 64-bit wide register accesses initiated by the CPU are not properly > translated to a sequence of 32-bit PCIe accesses. > xhci_readq(), for example, always returns same value in upper and lower > 32-bits, e.g. 0xabcd1234abcd1234 instead of 0xabcd1234. > > Cc: Sergey Temerkhanov > Signed-off-by: Sylwester Nawrocki > --- > Changes since RFC: > - dropped Kconfig option, switched to not using readq/writeq >unconditionally. > --- > include/usb/xhci.h | 8 > 1 file changed, 8 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH v6 09/17] clk: sifive: fu540-prci: Add clock initialization for SPL
Hi Pragnesh, On Sat, Apr 25, 2020 at 12:27 AM Pragnesh Patel wrote: > > Hi Bin, > > >-Original Message- > >From: Bin Meng > >Sent: 24 April 2020 19:25 > >To: Pragnesh Patel > >Cc: Jagan Teki ; U-Boot-Denx >b...@lists.denx.de>; Atish Patra ; Palmer Dabbelt > >; Paul Walmsley ; > >Troy Benjegerdes ; Anup Patel > >; Sagar Kadam ; Rick Chen > >; Lukasz Majewski ; Simon Glass > > > >Subject: Re: [PATCH v6 09/17] clk: sifive: fu540-prci: Add clock > >initialization for > >SPL > > > >[External Email] Do not click links or attachments unless you recognize the > >sender and know the content is safe > > > >Hi Pragnesh, > > > >On Fri, Apr 24, 2020 at 9:34 PM Pragnesh Patel > >wrote: > >> > >> > >> > >> Hi Bin, > >> > >> >-Original Message- > >> >From: Bin Meng > >> >Sent: 24 April 2020 18:31 > >> >To: Pragnesh Patel > >> >Cc: Jagan Teki ; U-Boot-Denx >> >b...@lists.denx.de>; Atish Patra ; Palmer > >> >Dabbelt ; Paul Walmsley > >> >; Troy Benjegerdes > >> >; Anup Patel ; Sagar > >> >Kadam ; Rick Chen ; > >> >Lukasz Majewski ; Simon Glass > >> >Subject: Re: [PATCH v6 09/17] clk: sifive: fu540-prci: Add clock > >> >initialization for SPL > >> > > >> >[External Email] Do not click links or attachments unless you > >> >recognize the sender and know the content is safe > >> > > >> >Hi Pragnesh, > >> > > >> >On Fri, Apr 24, 2020 at 6:08 PM Pragnesh Patel > >> > > >> >wrote: > >> >> > >> >> Hi Bin, Jagan > >> >> > >> >> >-Original Message- > >> >> >From: Bin Meng > >> >> >Sent: 20 April 2020 14:30 > >> >> >To: Jagan Teki > >> >> >Cc: Pragnesh Patel ; U-Boot-Denx >> >> >b...@lists.denx.de>; Atish Patra ; Palmer > >> >> >Dabbelt ; Paul Walmsley > >> >> >; Troy Benjegerdes > >> >> >; Anup Patel ; > >> >> >Sagar Kadam ; Rick Chen > >> >> >; Lukasz Majewski ; Simon > >Glass > >> >> > > >> >> >Subject: Re: [PATCH v6 09/17] clk: sifive: fu540-prci: Add clock > >> >> >initialization for SPL > >> >> > > >> >> >[External Email] Do not click links or attachments unless you > >> >> >recognize the sender and know the content is safe > >> >> > > >> >> >Hi Jagan, Pragnesh, > >> >> > > >> >> >On Tue, Apr 7, 2020 at 3:35 AM Jagan Teki > >> >> > > >> >> >wrote: > >> >> >> > >> >> >> On Sun, Mar 29, 2020 at 10:37 PM Pragnesh Patel > >> >> >> wrote: > >> >> >> > > >> >> >> > Set corepll, ddrpll and ethernet PLL for u-boot-spl > >> >> >> > > >> >> >> > Signed-off-by: Pragnesh Patel > >> >> >> > --- > >> >> >> > drivers/clk/sifive/fu540-prci.c | 118 > >> >> >> > > >> >> >> > 1 file changed, 118 insertions(+) > >> >> >> > > >> >> >> > diff --git a/drivers/clk/sifive/fu540-prci.c > >> >> >> > b/drivers/clk/sifive/fu540-prci.c index e6214cd821..3a73c2c8d1 > >> >> >> > 100644 > >> >> >> > --- a/drivers/clk/sifive/fu540-prci.c > >> >> >> > +++ b/drivers/clk/sifive/fu540-prci.c > >> >> >> > @@ -41,6 +41,10 @@ > >> >> >> > #include > >> >> >> > #include > >> >> >> > > >> >> >> > +#define DDRCTLPLL_F55 > >> >> >> > +#define DDRCTLPLL_Q2 > >> >> >> > +#define MHz100 > >> >> >> > + > >> >> >> > /* > >> >> >> > * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this > >> >> >> > driver > >> >> >expects: > >> >> >> > * hfclk and rtcclk > >> >> >> > @@ -152,6 +156,27 @@ > >> >> >> > #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \ > >> >> >> > (0x1 << > >> >> >> > PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT) > >> >> >> > > >> >> >> > +/* PROCMONCFG */ > >> >> >> > +#define PRCI_PROCMONCFG_OFFSET 0xF0 > >> >> >> > +#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24 > >> >> >> > +#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \ > >> >> >> > + (0x1 << > >> >> >> > +PRCI_PROCMONCFG_CORE_CLOCK_SHIFT) > >> >> >> > + > >> >> >> > +#define PLL_R(x) \ > >> >> >> > + ((x) << PRCI_DDRPLLCFG0_DIVR_SHIFT) & > >> >> >> > +PRCI_DDRPLLCFG0_DIVR_MASK #define PLL_F(x) \ > >> >> >> > + ((x) << PRCI_DDRPLLCFG0_DIVF_SHIFT) & > >> >> >> > +PRCI_DDRPLLCFG0_DIVF_MASK #define PLL_Q(x) \ > >> >> >> > + ((x) << PRCI_DDRPLLCFG0_DIVQ_SHIFT) & > >> >> >> > +PRCI_DDRPLLCFG0_DIVQ_MASK #define PLL_RANGE(x) \ > >> >> >> > + ((x) << PRCI_DDRPLLCFG0_RANGE_SHIFT) & > >> >> >> > +PRCI_DDRPLLCFG0_RANGE_MASK #define PLL_BYPASS(x) \ > >> >> >> > + ((x) << PRCI_DDRPLLCFG0_BYPASS_SHIFT) & > >> >> >> > +PRCI_DDRPLLCFG0_BYPASS_MASK #define PLL_FSE(x) \ > >> >> >> > + ((x) << PRCI_DDRPLLCFG0_FSE_SHIFT) & > >> >> >> > +PRCI_DDRPLLCFG0_FSE_MASK #define PLL_LOCK(x) \ > >> >> >> > + ((x) << PRCI_DDRPLLCFG0_LOCK_SHIFT) & > >> >> >> > +PRCI_DDRPLLCFG0_LOCK_MASK > >> >> >> > + > >> >> >> > /* > >> >> >> > * Private structures > >> >> >> > */ > >> >> >> > @@ -654,6 +679,93 @@ static int > >> >> >> > sifive_fu540_prci_disable(struct clk > >> >*clk) > >> >> >> > return pc->ops->enable_clk(pc, 0); } > >> >> >> > > >> >> >> > +#ifdef CONFIG_SPL_BUILD > >> >> >> > +static void corepll_init(struc
[PATCH] rockpro64: Enable HDMI output on rockpro64 board
See 9778edae5576e0a43a13387f9081ce11ef633025 for a similar commit that adds HDMI to other rk3399 boards. Signed-off-by: Andrius Štikonas Cc: Manivannan Sadhasivam Cc: Jagan Teki Cc: Kever Yang --- configs/rockpro64-rk3399_defconfig | 7 +++ include/configs/rockpro64_rk3399.h | 5 + 2 files changed, 12 insertions(+) diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 8074e4665a..53abce0057 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -58,5 +58,12 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_KEYBOARD=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_BPP16=y +CONFIG_VIDEO_BPP32=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/include/configs/rockpro64_rk3399.h b/include/configs/rockpro64_rk3399.h index 5f52c1e4f6..c92863e213 100644 --- a/include/configs/rockpro64_rk3399.h +++ b/include/configs/rockpro64_rk3399.h @@ -6,6 +6,11 @@ #ifndef __ROCKPRO64_RK3399_H #define __ROCKPRO64_RK3399_H +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + #include #define CONFIG_SYS_MMC_ENV_DEV 0 -- 2.26.2
Re: [PATCH] dlmalloc: Add an option to default malloc to init
> > OK, thanks. Can you please re-send and include the above re-phrased to > make sense in a commit message, in the body of the commit as well so > it's documented more in-tree when this would be helpful? Thanks again! > > -- > Tom Sure Tom. Will do that Monday/Tuesday. Thanks, Marek
Re: [PATCH 1/1] doc: correct detection of Sphinx version
On 4/24/20 11:18 PM, Heinrich Schuchardt wrote:
> Starting with Sphinx 1.3 sphinx.ext.pngmath was replaced by
> sphinx.ext.imgmath. Unfortunately conf.py does not detect that version
> 2.4 is greater 1.3. This results in an error
>
> Could not import extension sphinx.ext.pngmath
> (exception: No module named 'sphinx.ext.pngmath')
>
> in Debian Bullseye which uses Sphinx 2.4 since this month.
>
> Fix the detection of the Sphinx version.
>
> Signed-off-by: Heinrich Schuchardt
This is already fixed by
9b544c9eb312 ("docs: Fix conf.py for Sphinx 2.0")
> ---
> The Linux kernel starts recommending Sphinx 2.4. Cf.
> https://lkml.org/lkml/2020/4/14/1037
> ---
> doc/conf.py | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/doc/conf.py b/doc/conf.py
> index 0772fb6f0c..50518a4b2c 100644
> --- a/doc/conf.py
> +++ b/doc/conf.py
> @@ -37,7 +37,7 @@ needs_sphinx = '1.3'
> extensions = ['kerneldoc', 'rstFlatTable', 'kernel_include', 'cdomain',
> 'kfigure']
>
> # The name of the math extension changed on Sphinx 1.4
> -if major == 1 and minor > 3:
> +if major > 1 or major == 1 and minor > 3:
> extensions.append("sphinx.ext.imgmath")
> else:
> extensions.append("sphinx.ext.pngmath")
> --
> 2.26.2
>
[PATCH] doc: describe the analysis of crash dumps
Provide an overview of the analysis of U-Boot crash dumps.
Signed-off-by: Heinrich Schuchardt
---
doc/develop/crash_dumps.rst | 122
doc/develop/index.rst | 10 +++
doc/index.rst | 11
3 files changed, 143 insertions(+)
create mode 100644 doc/develop/crash_dumps.rst
create mode 100644 doc/develop/index.rst
diff --git a/doc/develop/crash_dumps.rst b/doc/develop/crash_dumps.rst
new file mode 100644
index 00..5aede4a9af
--- /dev/null
+++ b/doc/develop/crash_dumps.rst
@@ -0,0 +1,122 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (c) 2020 Heinrich Schuchardt
+
+Analyzing crash dumps
+=
+
+When the CPU detects an instruction that it cannot execute it raises an
+interrupt. U-Boot than writes a crash dump. This chapter describes how such
+dump can be analyzed.
+
+Creating a crash dump voluntarily
+-
+
+For describing the analysis of a crash dump we need an example. U-Boot comes
+with a command 'exception' that comes in handy here. The command is enabled
+by::
+
+CONFIG_CMD_EXCEPTION=y
+
+The example output below was recorded when running qemu\_arm64\_defconfig on
+QEMU::
+
+=> exception undefined
+"Synchronous Abort" handler, esr 0x0200
+elr: 000101fc lr : 000214ec (reloc)
+elr: 7ff291fc lr : 7ff3a4ec
+x0 : 7ffbd7f8 x1 :
+x2 : 0001 x3 : 7eedce18
+x4 : 7ff291fc x5 : 7eedce50
+x6 : 0064 x7 : 7eedce10
+x8 : x9 : 0004
+x10: 6db6db6db6db6db7 x11: 000d
+x12: 0006 x13: 0001869f
+x14: 7edd7dc0 x15: 0002
+x16: 7ff291fc x17:
+x18: 7eed8dc0 x19:
+x20: 7ffbd7f8 x21:
+x22: 7eedce10 x23: 0002
+x24: 7ffd4c80 x25:
+x26: x27:
+x28: 7eedce70 x29: 7edd7b40
+
+Code: b3c0 912ad000 940029d6 1752 (e7f7defb)
+Resetting CPU ...
+
+resetting ...
+
+The first line provides us with the type of interrupt that occurred.
+(On ARMv8 a synchronous abort is an exception where the return address stored
+in the ESR register indicates the instruction that caused the exception.)
+
+The second line provides the contents of the elr and the lr register after
+subtracting the relocation offset. - U-Boot relocates itself after being
+loaded. - The relocation offset can also be displayed using the bdinfo command.
+
+After the contents of the registers we get a line indicating the machine
+code of the instructions preceding the crash and in parentheses the instruction
+leading to the dump.
+
+Analyzing the code location
+---
+
+We can convert the instructions in the line starting with 'Code:' into
mnemonics
+using the objdump command. To make things easier scripts/decodecode is
+supplied::
+
+$echo 'Code: b3c0 912ad000 940029d6 1752 (e7f7defb)' | \
+ CROSS_COMPILE=aarch64-linux-gnu- ARCH=arm64 scripts/decodecode
+Code: b3c0 912ad000 940029d6 1752 (e7f7defb)
+All code
+
+ 0: b3c0 adrp x0, 0x79000
+ 4: 912ad000 addx0, x0, #0xab4
+ 8: 940029d6 bl 0xa760
+ c: 1752 b 0xfd54
+ 10:* e7f7defb .inst 0xe7f7defb ; undefined <-- trapping instruction
+
+Code starting with the faulting instruction
+===
+ 0: e7f7defb .inst 0xe7f7defb ; undefined
+
+Now lets use the locations provided by the elr and lr registers after
+subtracting the relocation offset to find out where in the code the crash
+occurred and from where it was invoked.
+
+File u-boot.map contains the memory layout of the U-Boot binary. Here we find
+these lines::
+
+ .text.do_undefined
+ 0x000101fc0xc cmd/built-in.o
+ .text.exception_complete
+ 0x00010208 0x90 cmd/built-in.o
+ ...
+ .text.cmd_process
+ 0x000213b8 0x164 common/built-in.o
+ 0x000213b8cmd_process
+ .text.cmd_process_error
+ 0x0002151c 0x40 common/built-in.o
+ 0x0002151ccmd_process_error
+
+So the error occurred at the start of function do\_undefined() and this
+function was invoked from somewhere inside function cmd\_process().
+
+If we want to dive deeper, we can disassemble the U-Boot binary::
+
+$ aarch64-linux-gnu-objdump -S -D u-boot | less
+
+000101fc :
+{
+/*
+ * 0xe7f...f. is undefined in ARM mode
+ * 0xde.. is undefined in Thumb mode
+*
Re: [PATCH] CMD: random: fix return code
Hi Simon, Tom, I guess it's perfect time to apply this patch. Thanks! --- Eugeniy Paltsev From: Simon Glass Sent: Monday, March 23, 2020 18:37 To: Eugeniy Paltsev Cc: Tom Rini; U-Boot Mailing List; uboot-snps-...@synopsys.com; Alexey Brodkin; linux-snps-...@lists.infradead.org Subject: Re: [PATCH] CMD: random: fix return code On Fri, 20 Mar 2020 at 10:38, Eugeniy Paltsev wrote: > > As of today 'random' command return 1 (CMD_RET_FAILURE) in case > of successful execution and 0 (CMD_RET_SUCCESS) in case of bad > arguments. Fix that. > > NOTE: we remove printing usage information from command body > so it won't print twice. > > Signed-off-by: Eugeniy Paltsev > --- > cmd/mem.c | 9 - > 1 file changed, 4 insertions(+), 5 deletions(-) > Reviewed-by: Simon Glass
[PATCH 1/1] doc: correct detection of Sphinx version
Starting with Sphinx 1.3 sphinx.ext.pngmath was replaced by
sphinx.ext.imgmath. Unfortunately conf.py does not detect that version
2.4 is greater 1.3. This results in an error
Could not import extension sphinx.ext.pngmath
(exception: No module named 'sphinx.ext.pngmath')
in Debian Bullseye which uses Sphinx 2.4 since this month.
Fix the detection of the Sphinx version.
Signed-off-by: Heinrich Schuchardt
---
The Linux kernel starts recommending Sphinx 2.4. Cf.
https://lkml.org/lkml/2020/4/14/1037
---
doc/conf.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/conf.py b/doc/conf.py
index 0772fb6f0c..50518a4b2c 100644
--- a/doc/conf.py
+++ b/doc/conf.py
@@ -37,7 +37,7 @@ needs_sphinx = '1.3'
extensions = ['kerneldoc', 'rstFlatTable', 'kernel_include', 'cdomain',
'kfigure']
# The name of the math extension changed on Sphinx 1.4
-if major == 1 and minor > 3:
+if major > 1 or major == 1 and minor > 3:
extensions.append("sphinx.ext.imgmath")
else:
extensions.append("sphinx.ext.pngmath")
--
2.26.2
[PATCH] BDINFO: ARC: print info about relocations
Print relocation information in bdinfo.
NOTE: this patch changes only ARC part of bdinfo code.
Signed-off-by: Eugeniy Paltsev
---
cmd/bdinfo.c | 4
1 file changed, 4 insertions(+)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index d6a7175b379..31ec4615641 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -439,20 +439,24 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char
* const argv[])
return 0;
}
#elif defined(CONFIG_ARC)
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bd_t *bd = gd->bd;
print_bi_mem(bd);
+ if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
+ print_num("relocaddr", gd->relocaddr);
+ print_num("reloc off", gd->reloc_off);
+ }
print_eth_ip_addr();
print_baudrate();
return 0;
}
#elif defined(CONFIG_XTENSA)
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
--
2.21.1
Re: [PATCH 0/7] Add support for CONFIG_API on RISC-V
On Fri, Apr 24, 2020 at 1:52 PM Tom Rini wrote: > > On Mon, Apr 20, 2020 at 06:34:11PM -0400, mho...@freebsd.org wrote: > > > From: Mitchell Horne > > > > FreeBSD makes use of u-boot's CONFIG_API to provide a version of its > > standard bootloader for embedded architectures. This series adds the > > necessary support for the RISC-V architecture, along with some small > > fixes to the API demo program for 64-bit systems. > > Adding in the RISC-V maintainer and EFI maintainer. I thought the > intention was for OSes to use the EFI loader here, even for "embedded" ? > Thanks! > Hi Tom, You are right, EFI is preferred. FreeBSD's loader has two implementations on arm: one that is an EFI application, and one based on this u-boot API (known as "ubldr"). ubldr precedes the EFI implementation by a few years. For RISC-V my intention is also to implement both versions, and ubldr was simpler on FreeBSD's side, so I chose to do that first. Do you think this series is still worth pursuing if u-boot is going the way of EFI? Cheers, Mitchell > -- > Tom
Re: [PATCH 0/7] Add support for CONFIG_API on RISC-V
On Fri, Apr 24, 2020 at 05:46:43PM -0300, Mitchell Horne wrote: > On Fri, Apr 24, 2020 at 1:52 PM Tom Rini wrote: > > > > On Mon, Apr 20, 2020 at 06:34:11PM -0400, mho...@freebsd.org wrote: > > > > > From: Mitchell Horne > > > > > > FreeBSD makes use of u-boot's CONFIG_API to provide a version of its > > > standard bootloader for embedded architectures. This series adds the > > > necessary support for the RISC-V architecture, along with some small > > > fixes to the API demo program for 64-bit systems. > > > > Adding in the RISC-V maintainer and EFI maintainer. I thought the > > intention was for OSes to use the EFI loader here, even for "embedded" ? > > Thanks! > > > > Hi Tom, > > You are right, EFI is preferred. FreeBSD's loader has two > implementations on arm: one that is an EFI application, and one based > on this u-boot API (known as "ubldr"). ubldr precedes the EFI > implementation by a few years. > > For RISC-V my intention is also to implement both versions, and ubldr > was simpler on FreeBSD's side, so I chose to do that first. Do you > think this series is still worth pursuing if u-boot is going the way > of EFI? In my mind at least, the EFI interface is preferred as it's a defined external standard interface. If the architecture maintainers want to support both the U-Boot API and EFI on RISC-V, I don't object. But one of the intentions is to have there be less work for OS folks to have to do for example. So that you found this a good first step for your use case means perhaps we need to continue to have the U-Boot API method be around (not that we had planned any sort of removal). Thanks! -- Tom signature.asc Description: PGP signature
[PATCH 13/14] ARC: HSDK-4xD: use separate config file
HSDK-4xD has quite different environment so let's split
HSDK and HSDK-4xD configs file.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/Kconfig | 3 +-
board/synopsys/hsdk/MAINTAINERS | 2 +
include/configs/hsdk-4xd.h | 120
3 files changed, 124 insertions(+), 1 deletion(-)
create mode 100644 include/configs/hsdk-4xd.h
diff --git a/board/synopsys/hsdk/Kconfig b/board/synopsys/hsdk/Kconfig
index 5e23b3229a9..d9c0e27a41d 100644
--- a/board/synopsys/hsdk/Kconfig
+++ b/board/synopsys/hsdk/Kconfig
@@ -7,7 +7,8 @@ config SYS_VENDOR
default "synopsys"
config SYS_CONFIG_NAME
- default "hsdk"
+ default "hsdk" if BOARD_HSDK
+ default "hsdk-4xd" if BOARD_HSDK_4XD
choice
prompt "HSDK board type"
diff --git a/board/synopsys/hsdk/MAINTAINERS b/board/synopsys/hsdk/MAINTAINERS
index d385951048f..73f71fd06bc 100644
--- a/board/synopsys/hsdk/MAINTAINERS
+++ b/board/synopsys/hsdk/MAINTAINERS
@@ -4,3 +4,5 @@ S: Maintained
F: board/synopsys/hsdk/
F: configs/hsdk_defconfig
F: configs/hsdk_4xd_defconfig
+F: include/configs/hsdk-4xd.h
+F: include/configs/hsdk.h
diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h
new file mode 100644
index 000..4628108075e
--- /dev/null
+++ b/include/configs/hsdk-4xd.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev
+ */
+
+#ifndef _CONFIG_HSDK_H_
+#define _CONFIG_HSDK_H_
+
+#include
+
+/*
+ * CPU configuration
+ */
+#define NR_CPUS4
+#define ARC_PERIPHERAL_BASE0xF000
+#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
+#define ARC_DWGMAC_BASE(ARC_PERIPHERAL_BASE + 0x18000)
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x8000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE SZ_1G
+
+#define CONFIG_SYS_INIT_SP_ADDR\
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN SZ_2M
+#define CONFIG_SYS_BOOTM_LEN SZ_128M
+#define CONFIG_SYS_LOAD_ADDR 0x8200
+
+/*
+ * UART configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK
+#define CONFIG_SYS_NS16550_MEM32
+
+/*
+ * Ethernet PHY configuration
+ */
+
+/*
+ * USB 1.1 configuration
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+
+/*
+ * Environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "upgrade=if mmc rescan && " \
+ "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
+ "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
+ "\"Fail to upgrade.\n" \
+ "Do you have u-boot-update.scr and u-boot.head on first (FAT)
SD card partition?\"" \
+ "; fi\0" \
+ "core_mask=0xF\0" \
+ "hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \
+setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs48x2=run hsdk_hs47dx2;\0" \
+ "hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
+ "hsdk_hs48x3=run hsdk_hs47dx3;\0" \
+ "hsdk_hs47dx3=setenv core_mask 0x7; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_en
[PATCH 11/14] ARC: HSDK-4xD: add CSM configuration support
Add support for CSM enable/disable and CSM relocation via
hsdk_init command. We allow to relocate CSM to the beginning of
any aperture even if HW support finer granularity.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/include/asm/arcregs.h | 3 +++
board/synopsys/hsdk/hsdk.c | 27 +++
2 files changed, 30 insertions(+)
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index f3cd4a889ac..516c14e105b 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -51,6 +51,9 @@
#define ARC_AUX_DCCM_BASE 0x18/* DCCM Base Addr ARCv2 */
#define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
+/* CSM auxiliary registers */
+#define ARC_AUX_CSM_ENABLE 0x9A0
+
/* Timer related auxiliary registers */
#define ARC_AUX_TIMER0_CNT 0x21/* Timer 0 count */
#define ARC_AUX_TIMER0_CTRL0x22/* Timer 0 control */
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index b25b1331874..2cbb59d8092 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -80,6 +80,7 @@ struct hsdk_env_common_ctl {
u32_env nvlim;
u32_env icache;
u32_env dcache;
+ u32_env csm_location;
u32_env l2_cache;
};
@@ -132,6 +133,7 @@ static const struct env_map_common env_map_common[] = {
{ "dcache_ena", ENV_HEX, true, 0, 1, &env_common.dcache },
#if defined(CONFIG_BOARD_HSDK_4XD)
{ "l2_cache_ena", ENV_HEX, true, 0, 1,
&env_common.l2_cache },
+ { "csm_location", ENV_HEX, true, 0, NO_CCM,
&env_common.csm_location },
#endif /* CONFIG_BOARD_HSDK_4XD */
{}
};
@@ -299,6 +301,30 @@ static void init_cluster_slc(void)
slc_disable();
}
+#define CREG_CSM_BASE (CREG_BASE + 0x210)
+
+static void init_cluster_csm(void)
+{
+ /* ARC HS38 in HSDK SoC doesn't include CSM */
+ if (!is_board_match_config(T_BOARD_HSDK_4XD))
+ return;
+
+ if (env_common.csm_location.val == NO_CCM) {
+ write_aux_reg(ARC_AUX_CSM_ENABLE, 0);
+ } else {
+ /*
+* CSM base address is 256kByte aligned but we allow to map
+* CSM only to aperture start (256MByte aligned)
+* The field in CREG_CSM_BASE is in 17:2 bits itself so we need
+* to shift it.
+*/
+ u32 csm_base = (env_common.csm_location.val * SZ_1K) << 2;
+
+ write_aux_reg(ARC_AUX_CSM_ENABLE, 1);
+ writel(csm_base, (void __iomem *)CREG_CSM_BASE);
+ }
+}
+
static void init_master_icache(void)
{
if (icache_status()) {
@@ -678,6 +704,7 @@ static void do_init_cluster(void)
* cores.
*/
init_cluster_nvlim();
+ init_cluster_csm();
init_cluster_slc();
}
--
2.21.1
[PATCH 14/14] ARC: HSDK-4xD: make init status resistant to U-boot reloading
Use register instead of static variable to store HSDK init status as
we want to avoid the situation when we reload U-boot via MDB after
previous init is done but HW reset (board reset) isn't done. So
let's store the init status in unused register - CREG_CPU_0_ENTRY
so status will survive after U-boot is reloaded via MDB.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/hsdk.c | 28 +---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 329427ed4ba..a3e0563ff45 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -42,6 +42,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define CREG_CPU_START_MASK0xF
#define CREG_CPU_START_POL BIT(4)
+#define CREG_CPU_0_ENTRY (CREG_BASE + 0x404)
+
#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
@@ -969,9 +971,29 @@ U_BOOT_CMD(
"hsdk_go halt - Boot stand-alone application on HSDK, halt CPU just
before application run\n"
);
+/*
+ * We may simply use static variable here to store init status, but we also
want
+ * to avoid the situation when we reload U-boot via MDB after previous
+ * init is done but HW reset (board reset) isn't done. So let's store the
+ * init status in any unused register (i.e CREG_CPU_0_ENTRY) so status will
+ * survive after U-boot is reloaded via MDB.
+ */
+#define INIT_MARKER_REGISTER ((void __iomem *)CREG_CPU_0_ENTRY)
+/* must be equal to INIT_MARKER_REGISTER reset value */
+#define INIT_MARKER_PENDING0
+
+static bool init_marker_get(void)
+{
+ return readl(INIT_MARKER_REGISTER) != INIT_MARKER_PENDING;
+}
+
+static void init_mark_done(void)
+{
+ writel(~INIT_MARKER_PENDING, INIT_MARKER_REGISTER);
+}
+
static int do_hsdk_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const
argv[])
{
- static bool done = false;
int ret;
if (board_mismatch()) {
@@ -980,14 +1002,14 @@ static int do_hsdk_init(cmd_tbl_t *cmdtp, int flag, int
argc, char *const argv[]
}
/* hsdk_init can be run only once */
- if (done) {
+ if (init_marker_get()) {
printf("HSDK HW is already initialized! Please reset the board
if you want to change the configuration.\n");
return CMD_RET_FAILURE;
}
ret = prepare_cpus();
if (!ret)
- done = true;
+ init_mark_done();
return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
}
--
2.21.1
[PATCH 07/14] ARC: HSDK-4xD: print info about HDMI clocks
HSDK-4xD has HDMI working so let's print info about HDMI clocks.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/hsdk.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 577893de2a1..45bc5ebe7db 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -985,7 +985,8 @@ static int do_hsdk_clock_print_all(cmd_tbl_t *cmdtp, int
flag, int argc,
soc_clk_ctl("eth-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("usb-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("sdio-clk", NULL, CLK_PRINT | CLK_MHZ);
-/* soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ); */
+ if (is_board_match_runtime(T_BOARD_HSDK_4XD))
+ soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
@@ -1003,9 +1004,11 @@ static int do_hsdk_clock_print_all(cmd_tbl_t *cmdtp, int
flag, int argc,
printf("\n");
/* HDMI clock domain */
-/* soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ); */
-/* soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ); */
-/* printf("\n"); */
+ if (is_board_match_runtime(T_BOARD_HSDK_4XD)) {
+ soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ);
+ printf("\n");
+ }
/* TUN clock domain */
soc_clk_ctl("tun-pll", NULL, CLK_PRINT | CLK_MHZ);
--
2.21.1
[PATCH 04/14] ARC: HSDK: split HSDK and HSDK-4xD DTS
Split HSDK and HSDK-4xD device tree files so they can have
different model names.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/dts/Makefile | 2 +-
arch/arc/dts/hsdk-4xd.dts | 12 +++
arch/arc/dts/hsdk-common.dtsi | 150 ++
arch/arc/dts/hsdk.dts | 145 +---
configs/hsdk_4xd_defconfig| 2 +-
5 files changed, 167 insertions(+), 144 deletions(-)
create mode 100644 arch/arc/dts/hsdk-4xd.dts
create mode 100644 arch/arc/dts/hsdk-common.dtsi
diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile
index 4f1e4637ce9..515fe1fe535 100644
--- a/arch/arc/dts/Makefile
+++ b/arch/arc/dts/Makefile
@@ -5,7 +5,7 @@ dtb-$(CONFIG_TARGET_AXS103) += axs103.dtb
dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb
dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
dtb-$(CONFIG_TARGET_EMSDP) += emsdp.dtb
-dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb
+dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb hsdk-4xd.dtb
dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb
targets += $(dtb-y)
diff --git a/arch/arc/dts/hsdk-4xd.dts b/arch/arc/dts/hsdk-4xd.dts
new file mode 100644
index 000..b245eea7692
--- /dev/null
+++ b/arch/arc/dts/hsdk-4xd.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev
+ */
+/dts-v1/;
+
+#include "hsdk-common.dtsi"
+
+/ {
+ model = "snps,hsdk-4xd";
+};
diff --git a/arch/arc/dts/hsdk-common.dtsi b/arch/arc/dts/hsdk-common.dtsi
new file mode 100644
index 000..7292a8da514
--- /dev/null
+++ b/arch/arc/dts/hsdk-common.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include "dt-bindings/clock/snps,hsdk-cgu.h"
+#include "dt-bindings/reset/snps,hsdk-reset.h"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ console = &uart0;
+ spi0 = &spi0;
+ };
+
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <5>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clk-fmeas {
+ clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
+<&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
+<&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
+<&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
+<&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
+<&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
+<&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
+<&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk
CLK_SYS_GFX_DMA>,
+<&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk
CLK_SYS_DMAC_CORE>,
+<&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk
CLK_SYS_SDIO_REF>,
+<&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
+<&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk
CLK_SYS_EBI_REF>,
+<&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
+ clock-names = "cpu-pll", "sys-pll",
+ "tun-pll", "ddr-clk",
+ "cpu-clk", "hdmi-pll",
+ "tun-clk", "hdmi-clk",
+ "apb-clk", "axi-clk",
+ "eth-clk", "usb-clk",
+ "sdio-clk", "hdmi-sys-clk",
+ "gfx-core-clk", "gfx-dma-clk",
+ "gfx-cfg-clk", "dmac-core-clk",
+ "dmac-cfg-clk", "sdio-ref-clk",
+ "spi-clk", "i2c-clk",
+ "uart-clk", "ebi-clk",
+ "rom-clk", "pwm-clk";
+ };
+
+ cgu_clk: cgu-clk@f000 {
+ compatible = "snps,hsdk-cgu-clock";
+ reg = <0xf000 0x10>, <0xf00014B8 0x4>;
+ #clock-cells = <1>;
+ };
+
+ cgu_rst: reset-controller@f8a0 {
+ compatible = "snps,hsdk-reset";
+ #reset-cells = <1>;
+ reg = <0xf8a0 0x4>, <0xfff0 0x4>;
+ };
+
+ uart0: serial0@f0005000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xf0005000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ ethernet@f0008000 {
+ #interrupt-cells = <1>;
+ compatible = "snps,arc-dwmac-3.70a";
+ reg = <0xf0008000 0x2000>;
+ phy-mode = "gmii";
+ };
+
+ ehci@0xf004 {
+ compatible = "generic-ehci";
+
[PATCH 10/14] ARC: HSDK-4xD: add support for SLC enable/disable
Add support for SLC enable/disable via hsdk_init command.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/hsdk.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index b8b995db47d..b25b1331874 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -80,6 +80,7 @@ struct hsdk_env_common_ctl {
u32_env nvlim;
u32_env icache;
u32_env dcache;
+ u32_env l2_cache;
};
/*
@@ -129,6 +130,9 @@ static const struct env_map_common env_map_common[] = {
{ "non_volatile_limit", ENV_HEX, true, 0, 0xF, &env_common.nvlim },
{ "icache_ena", ENV_HEX, true, 0, 1, &env_common.icache },
{ "dcache_ena", ENV_HEX, true, 0, 1, &env_common.dcache },
+#if defined(CONFIG_BOARD_HSDK_4XD)
+ { "l2_cache_ena", ENV_HEX, true, 0, 1,
&env_common.l2_cache },
+#endif /* CONFIG_BOARD_HSDK_4XD */
{}
};
@@ -188,6 +192,11 @@ static bool is_board_match_runtime(enum board_type
type_req)
return get_board_type_runtime() == type_req;
}
+static bool is_board_match_config(enum board_type type_req)
+{
+ return get_board_type_config() == type_req;
+}
+
static const char * board_name(enum board_type type)
{
switch (type) {
@@ -278,6 +287,18 @@ static void init_cluster_nvlim(void)
flush_n_invalidate_dcache_all();
}
+static void init_cluster_slc(void)
+{
+ /* ARC HS38 doesn't support SLC disabling */
+ if (!is_board_match_config(T_BOARD_HSDK_4XD))
+ return;
+
+ if (env_common.l2_cache.val)
+ slc_enable();
+ else
+ slc_disable();
+}
+
static void init_master_icache(void)
{
if (icache_status()) {
@@ -657,6 +678,7 @@ static void do_init_cluster(void)
* cores.
*/
init_cluster_nvlim();
+ init_cluster_slc();
}
static int check_master_cpu_id(void)
--
2.21.1
[PATCH 12/14] ARC: HSDK-4xD: tweak memory map
For HSDK-4xD we do additional AXI bridge tweaking while doing
hsdk_init command:
- we shrink IOC region.
- we configure ARC HS CORE SLV1 aperture depending on
haps_apb_location environment variable.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/hsdk.c | 58 ++
1 file changed, 58 insertions(+)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 2cbb59d8092..329427ed4ba 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -82,6 +82,7 @@ struct hsdk_env_common_ctl {
u32_env dcache;
u32_env csm_location;
u32_env l2_cache;
+ u32_env haps_apb;
};
/*
@@ -134,6 +135,7 @@ static const struct env_map_common env_map_common[] = {
#if defined(CONFIG_BOARD_HSDK_4XD)
{ "l2_cache_ena", ENV_HEX, true, 0, 1,
&env_common.l2_cache },
{ "csm_location", ENV_HEX, true, 0, NO_CCM,
&env_common.csm_location },
+ { "haps_apb_location", ENV_HEX, true, 0, 1,
&env_common.haps_apb },
#endif /* CONFIG_BOARD_HSDK_4XD */
{}
};
@@ -671,6 +673,61 @@ void init_memory_bridge(void)
writel(UPDATE_VAL, CREG_PAE_UPDT);
}
+/*
+ * For HSDK-4xD we do additional AXI bridge tweaking in hsdk_init command:
+ * - we shrink IOC region.
+ * - we configure HS CORE SLV1 aperture depending on haps_apb_location
+ * environment variable.
+ *
+ * As we've already configured AXI bridge in init_memory_bridge we don't
+ * do full configuration here but reconfigure changed part.
+ *
+ * m master AXI_M_m_SLV0AXI_M_m_SLV1AXI_M_m_OFFSET0
AXI_M_m_OFFSET1
+ * 0 HS (CBU)0x 0x6311 0xFEDCBA98
0x0E543210 [haps_apb_location = 0]
+ * 0 HS (CBU)0x 0x6111 0xFEDCBA98
0x06543210 [haps_apb_location = 1]
+ * 1 HS (RTT)0x 0x 0xFEDCBA98
0x76543210
+ * 2 AXI Tunnel 0x 0x 0xFEDCBA98
0x76543210
+ * 3 HDMI-VIDEO 0x 0x 0xFEDCBA98
0x76543210
+ * 4 HDMI-ADUIO 0x 0x 0xFEDCBA98
0x76543210
+ * 5 USB-HOST0x 0x 0xFEDCBA98
0x7654BA98
+ * 6 ETHERNET0x 0x 0xFEDCBA98
0x7654BA98
+ * 7 SDIO0x 0x 0xFEDCBA98
0x7654BA98
+ * 8 GPU 0x 0x 0xFEDCBA98
0x76543210
+ * 9 DMAC (port #1) 0x 0x 0xFEDCBA98
0x76543210
+ * 10 DMAC (port #2) 0x 0x 0xFEDCBA98
0x76543210
+ * 11 DVFS0x 0x6000 0x
0x
+ */
+void tweak_memory_bridge_cfg(void)
+{
+ /*
+* Only HSDK-4xD requre additional AXI bridge tweaking depending on
+* haps_apb_location environment variable
+*/
+ if (!is_board_match_config(T_BOARD_HSDK_4XD))
+ return;
+
+ if (env_common.haps_apb.val) {
+ writel(0x6111, CREG_AXI_M_SLV1(M_HS_CORE));
+ writel(0x06543210, CREG_AXI_M_OFT1(M_HS_CORE));
+ } else {
+ writel(0x6311, CREG_AXI_M_SLV1(M_HS_CORE));
+ writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
+ }
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
+
+ writel(0x, CREG_AXI_M_SLV1(M_USB_HOST));
+ writel(0x7654BA98, CREG_AXI_M_OFT1(M_USB_HOST));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
+
+ writel(0x, CREG_AXI_M_SLV1(M_ETHERNET));;
+ writel(0x7654BA98, CREG_AXI_M_OFT1(M_ETHERNET));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
+
+ writel(0x, CREG_AXI_M_SLV1(M_SDIO));
+ writel(0x7654BA98, CREG_AXI_M_OFT1(M_SDIO));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
+}
+
static void setup_clocks(void)
{
ulong rate;
@@ -706,6 +763,7 @@ static void do_init_cluster(void)
init_cluster_nvlim();
init_cluster_csm();
init_cluster_slc();
+ tweak_memory_bridge_cfg();
}
static int check_master_cpu_id(void)
--
2.21.1
[PATCH 08/14] ARC: HSDK-4xD: drop additional GPU clock info
HSDK-4xD has other GPU type so it consumes only GPU core clock.
Even we have additional GPU clock dividers they are not routed
to anything. So drop information about those additional clocks
in hsdk_clock print_all command.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/hsdk.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 45bc5ebe7db..7ba2a56c331 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -988,8 +988,10 @@ static int do_hsdk_clock_print_all(cmd_tbl_t *cmdtp, int
flag, int argc,
if (is_board_match_runtime(T_BOARD_HSDK_4XD))
soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ);
- soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
- soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
+ if (is_board_match_runtime(T_BOARD_HSDK)) {
+ soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
+ }
soc_clk_ctl("dmac-core-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("dmac-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("sdio-ref-clk", NULL, CLK_PRINT | CLK_MHZ);
--
2.21.1
[PATCH 06/14] ARC: HSDK-4xD: fix headerize script for HSDK-4xD compatibility
ARC HS CPU in HSDK-4xD has ARC ID = 0x54, so fix headerize script
accordingly.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/config.mk | 12 ++--
board/synopsys/hsdk/headerize-hsdk.py | 2 +-
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/board/synopsys/hsdk/config.mk b/board/synopsys/hsdk/config.mk
index 1d01ef50379..def944aad2b 100644
--- a/board/synopsys/hsdk/config.mk
+++ b/board/synopsys/hsdk/config.mk
@@ -6,18 +6,26 @@ ifdef CONFIG_BOARD_HSDK
PLATFORM_CPPFLAGS += -mcpu=hs38_linux -mlittle-endian -matomic -mll64 \
-mdiv-rem -mswap -mnorm -mmpy-option=9 -mbarrel-shifter \
-mfpu=fpud_all
+
+bsp-generate: u-boot u-boot.bin
+ $(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \
+ --arc-id 0x52 --image $(srctree)/u-boot.bin \
+ --elf $(srctree)/u-boot
+ $(Q)tools/mkimage -T script -C none -n 'uboot update script' \
+ -d $(srctree)/u-boot-update.txt \
+ $(srctree)/u-boot-update.scr &> /dev/null
endif
ifdef CONFIG_BOARD_HSDK_4XD
PLATFORM_CPPFLAGS += -mcpu=hs4x_rel31 -mlittle-endian -matomic -mll64 \
-mdiv-rem -mswap -mnorm -mmpy-option=9 -mbarrel-shifter \
-mfpu=fpud_all
-endif
bsp-generate: u-boot u-boot.bin
$(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \
- --arc-id 0x52 --image $(srctree)/u-boot.bin \
+ --arc-id 0x54 --image $(srctree)/u-boot.bin \
--elf $(srctree)/u-boot
$(Q)tools/mkimage -T script -C none -n 'uboot update script' \
-d $(srctree)/u-boot-update.txt \
$(srctree)/u-boot-update.scr &> /dev/null
+endif
diff --git a/board/synopsys/hsdk/headerize-hsdk.py
b/board/synopsys/hsdk/headerize-hsdk.py
index fce749723ed..7b047cf4a38 100644
--- a/board/synopsys/hsdk/headerize-hsdk.py
+++ b/board/synopsys/hsdk/headerize-hsdk.py
@@ -27,7 +27,7 @@ def calc_check_sum(filename):
def arg_verify(uboot_bin_filename, uboot_elf_filename, arc_id):
-if arc_id not in [0x52, 0x53]:
+if arc_id not in [0x52, 0x53, 0x54]:
print("unknown ARC ID: " + hex(arc_id))
sys.exit(2)
--
2.21.1
[PATCH 09/14] ARC: HSDK-4xD: print timer clock value
Print timer clock value in hsdk_clock print_all command.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/dts/hsdk-common.dtsi | 6 --
board/synopsys/hsdk/hsdk.c| 2 ++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arc/dts/hsdk-common.dtsi b/arch/arc/dts/hsdk-common.dtsi
index 7292a8da514..fd4245e1646 100644
--- a/arch/arc/dts/hsdk-common.dtsi
+++ b/arch/arc/dts/hsdk-common.dtsi
@@ -40,7 +40,8 @@
<&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk
CLK_SYS_SDIO_REF>,
<&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
<&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk
CLK_SYS_EBI_REF>,
-<&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
+<&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>,
+<&cgu_clk CLK_TUN_TIMER>;
clock-names = "cpu-pll", "sys-pll",
"tun-pll", "ddr-clk",
"cpu-clk", "hdmi-pll",
@@ -53,7 +54,8 @@
"dmac-cfg-clk", "sdio-ref-clk",
"spi-clk", "i2c-clk",
"uart-clk", "ebi-clk",
- "rom-clk", "pwm-clk";
+ "rom-clk", "pwm-clk",
+ "timer-clk";
};
cgu_clk: cgu-clk@f000 {
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 7ba2a56c331..b8b995db47d 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -1017,6 +1017,8 @@ static int do_hsdk_clock_print_all(cmd_tbl_t *cmdtp, int
flag, int argc,
soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("rom-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("pwm-clk", NULL, CLK_PRINT | CLK_MHZ);
+ if (is_board_match_runtime(T_BOARD_HSDK_4XD))
+ soc_clk_ctl("timer-clk", NULL, CLK_PRINT | CLK_MHZ);
printf("\n");
return CMD_RET_SUCCESS;
--
2.21.1
[PATCH 03/14] ARC: HSDK-4xD: add initial board support
Add initial HSDK-4xD board support.
The ARC HS4x/HS4xD Development Kit includes a multicore ARC HS4xD-based
chip that integrates a wide range of interfaces including Ethernet,
HDMI, WiFi, Bluetooth, USB, SDIO, I2C, SPI, UART, I2S, ADC, PWM and
GPIO, as well as a Think Silicon GPU.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/Kconfig| 2 +-
board/synopsys/hsdk/Kconfig | 17
board/synopsys/hsdk/MAINTAINERS | 3 +-
board/synopsys/hsdk/config.mk | 8
board/synopsys/hsdk/hsdk.c | 71 -
configs/hsdk_4xd_defconfig | 67 +++
6 files changed, 164 insertions(+), 4 deletions(-)
create mode 100644 configs/hsdk_4xd_defconfig
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 63413d90bb2..6ff201fa816 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -173,7 +173,7 @@ config TARGET_EMSDP
select CPU_ARCEM6
config TARGET_HSDK
- bool "Support Synpsys HS DevelopmentKit board"
+ bool "Support Synopsys HSDK or HSDK-4xD board"
config TARGET_IOT_DEVKIT
bool "Synopsys Brite IoT Development kit"
diff --git a/board/synopsys/hsdk/Kconfig b/board/synopsys/hsdk/Kconfig
index e8c00a6e7d0..5e23b3229a9 100644
--- a/board/synopsys/hsdk/Kconfig
+++ b/board/synopsys/hsdk/Kconfig
@@ -9,4 +9,21 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "hsdk"
+choice
+ prompt "HSDK board type"
+ default BOARD_HSDK
+
+config BOARD_HSDK
+ bool "ARC HS Development Kit"
+ help
+ ARC HS Development Kit based on quard core ARC HS38 processor
+
+config BOARD_HSDK_4XD
+ bool "ARC HS4x/HS4xD Development Kit"
+ help
+ ARC HS4x/HS4xD Development Kit based on quard core ARC HS48/HS47D
+ processor
+
+endchoice
+
endif
diff --git a/board/synopsys/hsdk/MAINTAINERS b/board/synopsys/hsdk/MAINTAINERS
index e22bd1e40b2..d385951048f 100644
--- a/board/synopsys/hsdk/MAINTAINERS
+++ b/board/synopsys/hsdk/MAINTAINERS
@@ -1,5 +1,6 @@
-HSDK BOARD
+HSDK BOARDs
M: Eugeniy Paltsev
S: Maintained
F: board/synopsys/hsdk/
F: configs/hsdk_defconfig
+F: configs/hsdk_4xd_defconfig
diff --git a/board/synopsys/hsdk/config.mk b/board/synopsys/hsdk/config.mk
index 5ae22fa2b75..1d01ef50379 100644
--- a/board/synopsys/hsdk/config.mk
+++ b/board/synopsys/hsdk/config.mk
@@ -2,9 +2,17 @@
#
# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ifdef CONFIG_BOARD_HSDK
PLATFORM_CPPFLAGS += -mcpu=hs38_linux -mlittle-endian -matomic -mll64 \
-mdiv-rem -mswap -mnorm -mmpy-option=9 -mbarrel-shifter \
-mfpu=fpud_all
+endif
+
+ifdef CONFIG_BOARD_HSDK_4XD
+PLATFORM_CPPFLAGS += -mcpu=hs4x_rel31 -mlittle-endian -matomic -mll64 \
+ -mdiv-rem -mswap -mnorm -mmpy-option=9 -mbarrel-shifter \
+ -mfpu=fpud_all
+endif
bsp-generate: u-boot u-boot.bin
$(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 67a29e334d7..771f7bbf886 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -154,6 +154,56 @@ static const struct env_map_percpu env_map_go[] = {
{}
};
+enum board_type {
+ T_BOARD_NONE,
+ T_BOARD_HSDK,
+ T_BOARD_HSDK_4XD
+};
+
+static inline enum board_type get_board_type_runtime(void)
+{
+ u32 arc_id = read_aux_reg(ARC_AUX_IDENTITY) & 0xFF;
+
+ if (arc_id == 0x52)
+ return T_BOARD_HSDK;
+ else if (arc_id == 0x54)
+ return T_BOARD_HSDK_4XD;
+ else
+ return T_BOARD_NONE;
+}
+
+static inline enum board_type get_board_type_config(void)
+{
+ if (IS_ENABLED(CONFIG_BOARD_HSDK))
+ return T_BOARD_HSDK;
+ else if (IS_ENABLED(CONFIG_BOARD_HSDK_4XD))
+ return T_BOARD_HSDK_4XD;
+ else
+ return T_BOARD_NONE;
+}
+
+static bool is_board_match_runtime(enum board_type type_req)
+{
+ return get_board_type_runtime() == type_req;
+}
+
+static const char * board_name(enum board_type type)
+{
+ switch (type) {
+ case T_BOARD_HSDK:
+ return "ARC HS Development Kit";
+ case T_BOARD_HSDK_4XD:
+ return "ARC HS4x/HS4xD Development Kit";
+ default:
+ return "?";
+ }
+}
+
+static bool board_mismatch(void)
+{
+ return get_board_type_config() != get_board_type_runtime();
+}
+
static void sync_cross_cpu_data(void)
{
u32 value;
@@ -221,7 +271,9 @@ static void init_cluster_nvlim(void)
flush_dcache_all();
write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val);
- write_aux_reg(AUX_AUX_CACHE_LIMIT, val);
+ /* AUX_AUX_CACHE_LIMIT reg is missing starting from HS48 */
+ if (is_board_match_runtime(T_BOARD_HSDK))
+ write_aux_reg(AUX_AUX_CACHE_LIMIT, val);
fl
[PATCH 05/14] ARC: HSDK-4xD: use active low polarity of cpu_start pulse
Add quirk for HSDK-4xD - due to HW issues HSDK can use any pulse
polarity but HSDK-4xD require active low polarity of cpu_start pulse.
So use low polarity of cpu_start pulse for both board.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/hsdk.c | 26 +++---
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 771f7bbf886..577893de2a1 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -40,6 +40,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
#define CREG_CPU_START (CREG_BASE + 0x400)
#define CREG_CPU_START_MASK0xF
+#define CREG_CPU_START_POL BIT(4)
#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
@@ -331,25 +332,36 @@ static inline void halt_this_cpu(void)
__builtin_arc_flag(1);
}
-static void smp_kick_cpu_x(u32 cpu_id)
+static u32 get_masked_cpu_ctart_reg(void)
{
int cmd = readl((void __iomem *)CREG_CPU_START);
+ /*
+* Quirk for HSDK-4xD - due to HW issues HSDK can use any pulse polarity
+* and HSDK-4xD require active low polarity of cpu_start pulse.
+*/
+ cmd &= ~CREG_CPU_START_POL;
+
+ cmd &= ~CREG_CPU_START_MASK;
+
+ return cmd;
+}
+
+static void smp_kick_cpu_x(u32 cpu_id)
+{
+ int cmd;
+
if (cpu_id > NR_CPUS)
return;
- cmd &= ~CREG_CPU_START_MASK;
+ cmd = get_masked_cpu_ctart_reg();
cmd |= (1 << cpu_id);
writel(cmd, (void __iomem *)CREG_CPU_START);
}
static u32 prepare_cpu_ctart_reg(void)
{
- int cmd = readl((void __iomem *)CREG_CPU_START);
-
- cmd &= ~CREG_CPU_START_MASK;
-
- return cmd | env_common.core_mask.val;
+ return get_masked_cpu_ctart_reg() | env_common.core_mask.val;
}
/* slave CPU entry for configuration */
--
2.21.1
[PATCH 01/14] ARC: ARCv2: handle DSP presence in HW
In case of DSP extension presence in HW some instructions
(related to integer multiply, multiply-accumulate, and divide
operation) executes on this DSP execution unit. So their
execution will depend on dsp configuration register (DSP_CTRL)
As we want these instructions to execute the same way regardless
of DSP presence we need to set DSP_CTRL properly.
NOTE:
we do the same adjustments in Linux kernel, see in kernel tree:
commit 4827d0cf744e ("ARC: handle DSP presence in HW")
Signed-off-by: Eugeniy Paltsev
---
arch/arc/include/asm/arcregs.h | 1 +
arch/arc/lib/start.S | 15 +++
2 files changed, 16 insertions(+)
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index fff6591c681..f3cd4a889ac 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -100,6 +100,7 @@
/* DSP-extensions related auxiliary registers */
#define ARC_AUX_DSP_BUILD 0x7A
+#define ARC_AUX_DSP_CTRL 0x59F
/* ARC Subsystems related auxiliary registers */
#define ARC_AUX_SUBSYS_BUILD 0xF0
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 8c744f5be7f..016ae85be23 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -61,6 +61,21 @@ ENTRY(_start)
1:
#endif
+#ifdef CONFIG_ISA_ARCV2
+ ; In case of DSP extension presence in HW some instructions
+ ; (related to integer multiply, multiply-accumulate, and divide
+ ; operation) executes on this DSP execution unit. So their
+ ; execution will depend on dsp configuration register (DSP_CTRL)
+ ; As we want these instructions to execute the same way regardless
+ ; of DSP presence we need to set DSP_CTRL properly.
+ lr r5, [ARC_AUX_DSP_BUILD]
+ bmskr5, r5, 7
+ breqr5, 0, 1f
+ mov r5, 0
+ sr r5, [ARC_AUX_DSP_CTRL]
+1:
+#endif
+
#ifdef __ARC_UNALIGNED__
/*
* Enable handling of unaligned access in the CPU as by default
--
2.21.1
[PATCH 02/14] ARC: HSDK: CGU: add support for timer clock
Add support for additional timer clock which belongs to tunnel
domain.
Signed-off-by: Eugeniy Paltsev
---
drivers/clk/clk-hsdk-cgu.c| 9 ++---
include/dt-bindings/clock/snps,hsdk-cgu.h | 5 +++--
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 6eaafdeaf99..3035c5fb38e 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -67,6 +67,7 @@
#define CGU_TUN_IDIV_TUN 0x380
#define CGU_TUN_IDIV_ROM 0x390
#define CGU_TUN_IDIV_PWM 0x3A0
+#define CGU_TUN_IDIV_TIMER 0x3B0
#define CGU_HDMI_IDIV_APB 0x480
#define CGU_SYS_IDIV_APB 0x180
#define CGU_SYS_IDIV_AXI 0x190
@@ -123,12 +124,12 @@
#define MIN_PLL_RATE 1 /* 100 MHz */
#define PARENT_RATE_33 /* fixed clock - xtal */
#define PARENT_RATE_27 2700 /* fixed clock - xtal */
-#define CGU_MAX_CLOCKS 26
+#define CGU_MAX_CLOCKS 27
#define CGU_SYS_CLOCKS 16
#define MAX_AXI_CLOCKS 4
-#define CGU_TUN_CLOCKS 3
+#define CGU_TUN_CLOCKS 4
#define MAX_TUN_CLOCKS 6
struct hsdk_tun_idiv_cfg {
@@ -147,7 +148,8 @@ static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
{ 6, 6, 6, 6, 75000, 6 }, {
{ CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
{ CGU_TUN_IDIV_ROM, { 4,4, 4, 4, 5, 4 } },
- { CGU_TUN_IDIV_PWM, { 8,8, 8, 8, 10, 8 } }
+ { CGU_TUN_IDIV_PWM, { 8,8, 8, 8, 10, 8 } },
+ { CGU_TUN_IDIV_TIMER, { 12, 12, 12, 12, 15, 12 } }
}
};
@@ -316,6 +318,7 @@ static const struct hsdk_cgu_clock_map clock_map[] = {
{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get,
tun_clk_set, idiv_off },
{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set,
idiv_off },
{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TIMER, &sdt_pll_dat, idiv_get, idiv_set,
idiv_off },
{ CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
{ CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get,
idiv_set, idiv_off }
};
diff --git a/include/dt-bindings/clock/snps,hsdk-cgu.h
b/include/dt-bindings/clock/snps,hsdk-cgu.h
index 2cfe34eb35f..1ce7661cd93 100644
--- a/include/dt-bindings/clock/snps,hsdk-cgu.h
+++ b/include/dt-bindings/clock/snps,hsdk-cgu.h
@@ -36,7 +36,8 @@
#define CLK_TUN_TUN21
#define CLK_TUN_ROM22
#define CLK_TUN_PWM23
-#define CLK_HDMI_PLL 24
-#define CLK_HDMI 25
+#define CLK_TUN_TIMER 24
+#define CLK_HDMI_PLL 25
+#define CLK_HDMI 26
#endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */
--
2.21.1
[PATCH 00/14] ARC: add HSDK-4xD board support
Eugeniy Paltsev (14): ARC: ARCv2: handle DSP presence in HW ARC: HSDK: CGU: add support for timer clock ARC: HSDK-4xD: add initial board support ARC: HSDK: split HSDK and HSDK-4xD DTS ARC: HSDK-4xD: use active low polarity of cpu_start pulse ARC: HSDK-4xD: fix headerize script for HSDK-4xD compatibility ARC: HSDK-4xD: print info about HDMI clocks ARC: HSDK-4xD: drop additional GPU clock info ARC: HSDK-4xD: print timer clock value ARC: HSDK-4xD: add support for SLC enable/disable ARC: HSDK-4xD: add CSM configuration support ARC: HSDK-4xD: tweak memory map ARC: HSDK-4xD: use separate config file ARC: HSDK-4xD: make init status resistant to U-boot reloading arch/arc/Kconfig | 2 +- arch/arc/dts/Makefile | 2 +- arch/arc/dts/hsdk-4xd.dts | 12 ++ arch/arc/dts/hsdk-common.dtsi | 152 + arch/arc/dts/hsdk.dts | 145 + arch/arc/include/asm/arcregs.h| 4 + arch/arc/lib/start.S | 15 ++ board/synopsys/hsdk/Kconfig | 20 +- board/synopsys/hsdk/MAINTAINERS | 5 +- board/synopsys/hsdk/config.mk | 16 ++ board/synopsys/hsdk/headerize-hsdk.py | 2 +- board/synopsys/hsdk/hsdk.c| 251 -- configs/hsdk_4xd_defconfig| 67 ++ drivers/clk/clk-hsdk-cgu.c| 9 +- include/configs/hsdk-4xd.h| 120 +++ include/dt-bindings/clock/snps,hsdk-cgu.h | 5 +- 16 files changed, 657 insertions(+), 170 deletions(-) create mode 100644 arch/arc/dts/hsdk-4xd.dts create mode 100644 arch/arc/dts/hsdk-common.dtsi create mode 100644 configs/hsdk_4xd_defconfig create mode 100644 include/configs/hsdk-4xd.h -- 2.21.1
Re: [PATCH 07/24] imx: update is_imx6ull to include i.MX6ULZ
Hi, Am Donnerstag, 23. April 2020, 03:33:49 CEST schrieb Peng Fan: > > Subject: Re: [PATCH 07/24] imx: update is_imx6ull to include i.MX6ULZ > > > > Am Mittwoch, 22. April 2020, 15:52:18 CEST schrieb Peng Fan: > > > Update is_imx6ull helper to include i.MX6ULZ SoC. i.MX6ULZ could share > > > same macro, then we no need to add is_imx6ulz in various drivers. > > > > > > Signed-off-by: Peng Fan > > > --- > > > arch/arm/include/asm/mach-imx/sys_proto.h | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h > > > b/arch/arm/include/asm/mach-imx/sys_proto.h > > > index a02cd40c7d..2a997f280d 100644 > > > --- a/arch/arm/include/asm/mach-imx/sys_proto.h > > > +++ b/arch/arm/include/asm/mach-imx/sys_proto.h > > > @@ -37,7 +37,7 @@ > > > #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) #define > > is_mx6solo() > > > (is_cpu_type(MXC_CPU_MX6SOLO)) #define is_mx6ul() > > > (is_cpu_type(MXC_CPU_MX6UL)) -#define is_mx6ull() > > > (is_cpu_type(MXC_CPU_MX6ULL)) > > > +#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || > > > +is_cpu_type(MXC_CPU_MX6ULZ)) > > > > While I probably understand your intentions, I fear that it will lead to > > confusion when the helper's name does not reflect that more than one cpu > > type can match. > > What about introducing is_mx6ulX() to signal that the last letter is "don't > > care"? > > Renaming the macro needs to modify drivers using this macro, this is risk > to easy break existing code. > I prefer to keep as is. but when you look at the drivers using this is_mx6ull() macro, then you'll find already a bunch of other is_mx...() macros used in addition. Then it would also be possible to add the is_mx6ulz() one - it won't make the situation worse at these points. In my eyes, this is better than hiding two CPUs behind one macro. Thanks, Michael > > Thanks, > Peng. > > > > > Best regards, > > Michael > > > > > #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ)) #define > > > is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) > > > > > > > > > > > > >
Re: [PATCH] lib: strto: Fix parsing MTD partition size
On Friday 24 April 2020 21:33:42 Pali Rohár wrote:
> On Friday 24 April 2020 15:28:01 Tom Rini wrote:
> > On Fri, Apr 24, 2020 at 09:15:43PM +0200, Pali Rohár wrote:
> > > On Friday 24 April 2020 15:12:42 Tom Rini wrote:
> > > > On Fri, Apr 24, 2020 at 08:29:41PM +0200, Pali Rohár wrote:
> > > > > On Friday 24 April 2020 20:21:33 Pali Rohár wrote:
> > > > > > Commit 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base
> > > > > > 16
> > > > > > detection") broke parsing MTD partition sizes specified in decimal
> > > > > > base.
> > > > > >
> > > > > > E.g. "128k(bootloader)" is parsed by drivers/mtd/mtdpart.c as
> > > > > > hexadecimal
> > > > > > number (0x128 << 10) because character 'a' in substring
> > > > > > "bootloader" caused
> > > > > > parsing whole number as hexadecimal.
> > > > > >
> > > > > > This patch stop doing hexadecimal base heuristic on first non-valid
> > > > > > hexadecimal number, so "128k(bootloader)" is parsed as decimal
> > > > > > number 128.
> > > > > >
> > > > > > Fixes: 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base
> > > > > > 16...")
> > > > > > Signed-off-by: Pali Rohár
> > > > > > ---
> > > > > > lib/strto.c | 3 +++
> > > > > > 1 file changed, 3 insertions(+)
> > > > > >
> > > > > > diff --git a/lib/strto.c b/lib/strto.c
> > > > > > index 1ac2b09c72..060b66b915 100644
> > > > > > --- a/lib/strto.c
> > > > > > +++ b/lib/strto.c
> > > > > > @@ -30,6 +30,9 @@ static const char
> > > > > > *_parse_integer_fixup_radix(const char *s, unsigned int *base)
> > > > > >
> > > > > > do {
> > > > > > var = tolower(s[i++]);
> > > > > > + if (!(var >= '0' && var <= '9') &&
> > > > > > + !(var >= 'a' && var <= 'f'))
> > > > > > + break;
> > > > > > if (var >= 'a' && var <= 'f') {
> > > > > > *base = 16;
> > > > > > break;
> > > > > > --
> > > > > > 2.20.1
> > > > > >
> > > > >
> > > > > CC Tom, this problem was detected by my in-progress Travis Nokia N900
> > > > > test which tries to boot kernel from the OneNAND. Build log is there:
> > > > > https://travis-ci.org/github/u-boot/u-boot/jobs/679007310
> > > >
> > > > This is the same as:
> > > > http://patchwork.ozlabs.org/project/uboot/patch/1a681dbefac4c353ad53d7f6cd1a75812036739a.158653.git.michal.si...@xilinx.com/
> > > > yes? Thanks!
> > >
> > > Yes, this is the same problem.
> >
> > Can you please test (and Tested-by) that one? Thanks!
>
> It is basically same patch as mine... but ok I'm going to run that my
> automated Nokia N900 test locally with above patch.
That patch is working fine, you can add my Tested-by: Pali Rohár
for it
[PATCH] ARM: imx: imx8m: Do not warn about cpu-idle-states if missing
If the cpu-idle-states is missing from the DT in the first place, do
not fail on removing in. Just move on and do not even print an error,
since not being able to remove something which is not there in the
first place is not an error and surely does not justify failing to
boot.
Turn the surrounding prints into debugs to reduce the useless noise.
Signed-off-by: Marek Vasut
Cc: Frieder Schrempf
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
---
arch/arm/mach-imx/imx8m/soc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 7fcbd53f30..bbfc9c5576 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -364,16 +364,18 @@ int ft_system_setup(void *blob, bd_t *bd)
if (nodeoff < 0)
continue; /* Not found, skip it */
- printf("Found %s node\n", nodes_path[i]);
+ debug("Found %s node\n", nodes_path[i]);
rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
+ if (rc == -FDT_ERR_NOTFOUND)
+ continue;
if (rc) {
printf("Unable to update property %s:%s,
err=%s\n",
nodes_path[i], "status",
fdt_strerror(rc));
return rc;
}
- printf("Remove %s:%s\n", nodes_path[i],
+ debug("Remove %s:%s\n", nodes_path[i],
"cpu-idle-states");
}
}
--
2.25.1
[PATCH] ARM: imx: imx8mm: Add missing clock entries for FEC clock
All the FEC ethernet clock entries for iMX8MM are missing, while they
are already present on iMX8MQ. Fill in the nodes on iMX8MM, as the FEC
ethernet gets bogus clock information otherwise which makes ethernet
inoperable.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
---
arch/arm/mach-imx/imx8m/clock_imx8mm.c | 49 ++
arch/arm/mach-imx/imx8m/clock_slice.c | 25 +
2 files changed, 74 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index c423ac0058..d123ba1625 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -578,3 +578,52 @@ u32 mxc_get_clock(enum mxc_clock clk)
return 0;
}
+
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type)
+{
+ u32 target;
+ u32 enet1_ref;
+
+ switch (type) {
+ case ENET_125MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+ break;
+ case ENET_50MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+ break;
+ case ENET_25MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* disable the clock first */
+ clock_enable(CCGR_ENET1, 0);
+ clock_enable(CCGR_SIM_ENET, 0);
+
+ /* set enet axi clock 266Mhz */
+ target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
+CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | enet1_ref |
+CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_REF_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON |
+ ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
+
+ /* enable clock */
+ clock_enable(CCGR_SIM_ENET, 1);
+ clock_enable(CCGR_ENET1, 1);
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c
b/arch/arm/mach-imx/imx8m/clock_slice.c
index 8b7a4dad65..9e84e8d5b1 100644
--- a/arch/arm/mach-imx/imx8m/clock_slice.c
+++ b/arch/arm/mach-imx/imx8m/clock_slice.c
@@ -482,6 +482,16 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
},
+ {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
+{OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
+{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+ },
{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
@@ -509,6 +519,21 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
+ {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
+{OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
+ },
+ {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
+{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+ VIDEO_PLL_CLK}
+ },
+ {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
+{OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
{UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
--
2.25.1
Re: [PATCH] lib: strto: Fix parsing MTD partition size
On Friday 24 April 2020 15:28:01 Tom Rini wrote:
> On Fri, Apr 24, 2020 at 09:15:43PM +0200, Pali Rohár wrote:
> > On Friday 24 April 2020 15:12:42 Tom Rini wrote:
> > > On Fri, Apr 24, 2020 at 08:29:41PM +0200, Pali Rohár wrote:
> > > > On Friday 24 April 2020 20:21:33 Pali Rohár wrote:
> > > > > Commit 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base 16
> > > > > detection") broke parsing MTD partition sizes specified in decimal
> > > > > base.
> > > > >
> > > > > E.g. "128k(bootloader)" is parsed by drivers/mtd/mtdpart.c as
> > > > > hexadecimal
> > > > > number (0x128 << 10) because character 'a' in substring "bootloader"
> > > > > caused
> > > > > parsing whole number as hexadecimal.
> > > > >
> > > > > This patch stop doing hexadecimal base heuristic on first non-valid
> > > > > hexadecimal number, so "128k(bootloader)" is parsed as decimal number
> > > > > 128.
> > > > >
> > > > > Fixes: 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base
> > > > > 16...")
> > > > > Signed-off-by: Pali Rohár
> > > > > ---
> > > > > lib/strto.c | 3 +++
> > > > > 1 file changed, 3 insertions(+)
> > > > >
> > > > > diff --git a/lib/strto.c b/lib/strto.c
> > > > > index 1ac2b09c72..060b66b915 100644
> > > > > --- a/lib/strto.c
> > > > > +++ b/lib/strto.c
> > > > > @@ -30,6 +30,9 @@ static const char *_parse_integer_fixup_radix(const
> > > > > char *s, unsigned int *base)
> > > > >
> > > > > do {
> > > > > var = tolower(s[i++]);
> > > > > + if (!(var >= '0' && var <= '9') &&
> > > > > + !(var >= 'a' && var <= 'f'))
> > > > > + break;
> > > > > if (var >= 'a' && var <= 'f') {
> > > > > *base = 16;
> > > > > break;
> > > > > --
> > > > > 2.20.1
> > > > >
> > > >
> > > > CC Tom, this problem was detected by my in-progress Travis Nokia N900
> > > > test which tries to boot kernel from the OneNAND. Build log is there:
> > > > https://travis-ci.org/github/u-boot/u-boot/jobs/679007310
> > >
> > > This is the same as:
> > > http://patchwork.ozlabs.org/project/uboot/patch/1a681dbefac4c353ad53d7f6cd1a75812036739a.158653.git.michal.si...@xilinx.com/
> > > yes? Thanks!
> >
> > Yes, this is the same problem.
>
> Can you please test (and Tested-by) that one? Thanks!
It is basically same patch as mine... but ok I'm going to run that my
automated Nokia N900 test locally with above patch.
Re: [PATCH] lib: strto: Fix parsing MTD partition size
On Fri, Apr 24, 2020 at 09:15:43PM +0200, Pali Rohár wrote:
> On Friday 24 April 2020 15:12:42 Tom Rini wrote:
> > On Fri, Apr 24, 2020 at 08:29:41PM +0200, Pali Rohár wrote:
> > > On Friday 24 April 2020 20:21:33 Pali Rohár wrote:
> > > > Commit 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base 16
> > > > detection") broke parsing MTD partition sizes specified in decimal base.
> > > >
> > > > E.g. "128k(bootloader)" is parsed by drivers/mtd/mtdpart.c as
> > > > hexadecimal
> > > > number (0x128 << 10) because character 'a' in substring "bootloader"
> > > > caused
> > > > parsing whole number as hexadecimal.
> > > >
> > > > This patch stop doing hexadecimal base heuristic on first non-valid
> > > > hexadecimal number, so "128k(bootloader)" is parsed as decimal number
> > > > 128.
> > > >
> > > > Fixes: 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base
> > > > 16...")
> > > > Signed-off-by: Pali Rohár
> > > > ---
> > > > lib/strto.c | 3 +++
> > > > 1 file changed, 3 insertions(+)
> > > >
> > > > diff --git a/lib/strto.c b/lib/strto.c
> > > > index 1ac2b09c72..060b66b915 100644
> > > > --- a/lib/strto.c
> > > > +++ b/lib/strto.c
> > > > @@ -30,6 +30,9 @@ static const char *_parse_integer_fixup_radix(const
> > > > char *s, unsigned int *base)
> > > >
> > > > do {
> > > > var = tolower(s[i++]);
> > > > + if (!(var >= '0' && var <= '9') &&
> > > > + !(var >= 'a' && var <= 'f'))
> > > > + break;
> > > > if (var >= 'a' && var <= 'f') {
> > > > *base = 16;
> > > > break;
> > > > --
> > > > 2.20.1
> > > >
> > >
> > > CC Tom, this problem was detected by my in-progress Travis Nokia N900
> > > test which tries to boot kernel from the OneNAND. Build log is there:
> > > https://travis-ci.org/github/u-boot/u-boot/jobs/679007310
> >
> > This is the same as:
> > http://patchwork.ozlabs.org/project/uboot/patch/1a681dbefac4c353ad53d7f6cd1a75812036739a.158653.git.michal.si...@xilinx.com/
> > yes? Thanks!
>
> Yes, this is the same problem.
Can you please test (and Tested-by) that one? Thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH] lib: strto: Fix parsing MTD partition size
On Friday 24 April 2020 15:12:42 Tom Rini wrote:
> On Fri, Apr 24, 2020 at 08:29:41PM +0200, Pali Rohár wrote:
> > On Friday 24 April 2020 20:21:33 Pali Rohár wrote:
> > > Commit 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base 16
> > > detection") broke parsing MTD partition sizes specified in decimal base.
> > >
> > > E.g. "128k(bootloader)" is parsed by drivers/mtd/mtdpart.c as hexadecimal
> > > number (0x128 << 10) because character 'a' in substring "bootloader"
> > > caused
> > > parsing whole number as hexadecimal.
> > >
> > > This patch stop doing hexadecimal base heuristic on first non-valid
> > > hexadecimal number, so "128k(bootloader)" is parsed as decimal number 128.
> > >
> > > Fixes: 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base 16...")
> > > Signed-off-by: Pali Rohár
> > > ---
> > > lib/strto.c | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > > diff --git a/lib/strto.c b/lib/strto.c
> > > index 1ac2b09c72..060b66b915 100644
> > > --- a/lib/strto.c
> > > +++ b/lib/strto.c
> > > @@ -30,6 +30,9 @@ static const char *_parse_integer_fixup_radix(const
> > > char *s, unsigned int *base)
> > >
> > > do {
> > > var = tolower(s[i++]);
> > > + if (!(var >= '0' && var <= '9') &&
> > > + !(var >= 'a' && var <= 'f'))
> > > + break;
> > > if (var >= 'a' && var <= 'f') {
> > > *base = 16;
> > > break;
> > > --
> > > 2.20.1
> > >
> >
> > CC Tom, this problem was detected by my in-progress Travis Nokia N900
> > test which tries to boot kernel from the OneNAND. Build log is there:
> > https://travis-ci.org/github/u-boot/u-boot/jobs/679007310
>
> This is the same as:
> http://patchwork.ozlabs.org/project/uboot/patch/1a681dbefac4c353ad53d7f6cd1a75812036739a.158653.git.michal.si...@xilinx.com/
> yes? Thanks!
Yes, this is the same problem.
Re: [PATCH] lib: strto: Fix parsing MTD partition size
On Fri, Apr 24, 2020 at 08:29:41PM +0200, Pali Rohár wrote:
> On Friday 24 April 2020 20:21:33 Pali Rohár wrote:
> > Commit 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base 16
> > detection") broke parsing MTD partition sizes specified in decimal base.
> >
> > E.g. "128k(bootloader)" is parsed by drivers/mtd/mtdpart.c as hexadecimal
> > number (0x128 << 10) because character 'a' in substring "bootloader" caused
> > parsing whole number as hexadecimal.
> >
> > This patch stop doing hexadecimal base heuristic on first non-valid
> > hexadecimal number, so "128k(bootloader)" is parsed as decimal number 128.
> >
> > Fixes: 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base 16...")
> > Signed-off-by: Pali Rohár
> > ---
> > lib/strto.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/lib/strto.c b/lib/strto.c
> > index 1ac2b09c72..060b66b915 100644
> > --- a/lib/strto.c
> > +++ b/lib/strto.c
> > @@ -30,6 +30,9 @@ static const char *_parse_integer_fixup_radix(const char
> > *s, unsigned int *base)
> >
> > do {
> > var = tolower(s[i++]);
> > + if (!(var >= '0' && var <= '9') &&
> > + !(var >= 'a' && var <= 'f'))
> > + break;
> > if (var >= 'a' && var <= 'f') {
> > *base = 16;
> > break;
> > --
> > 2.20.1
> >
>
> CC Tom, this problem was detected by my in-progress Travis Nokia N900
> test which tries to boot kernel from the OneNAND. Build log is there:
> https://travis-ci.org/github/u-boot/u-boot/jobs/679007310
This is the same as:
http://patchwork.ozlabs.org/project/uboot/patch/1a681dbefac4c353ad53d7f6cd1a75812036739a.158653.git.michal.si...@xilinx.com/
yes? Thanks!
--
Tom
signature.asc
Description: PGP signature
[PATCH] configs: ti: Fix usage of undefined variable overlay_files
The env variable overlay_files is used while adding the environment
support commands for FIT loading, but it was cleaned up just prior in
commit ee53b59511a6 ("configs: Remove unneeded overlay_files environment
variable"). Fix this by replacing the undefined variable with the
proper name_overlays env variable.
Fixes: 76470b6929d5 ("configs: ti: Add environment support commands for FIT
loading")
Signed-off-by: Suman Anna
---
include/configs/ti_armv7_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/ti_armv7_common.h
b/include/configs/ti_armv7_common.h
index a612bb5b4a8e..08829781e314 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -63,7 +63,7 @@
"name_fit=fitImage\0" \
"update_to_fit=setenv loadaddr ${addr_fit}; setenv bootfile
${name_fit}\0" \
"get_overlaystring=" \
- "for overlay in $overlay_files;" \
+ "for overlay in $name_overlays;" \
"do;" \
"setenv overlaystring ${overlaystring}'#'${overlay};" \
"done;\0" \
--
2.26.0
Re: [PATCH] lib: strto: Fix parsing MTD partition size
On Friday 24 April 2020 20:21:33 Pali Rohár wrote:
> Commit 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base 16
> detection") broke parsing MTD partition sizes specified in decimal base.
>
> E.g. "128k(bootloader)" is parsed by drivers/mtd/mtdpart.c as hexadecimal
> number (0x128 << 10) because character 'a' in substring "bootloader" caused
> parsing whole number as hexadecimal.
>
> This patch stop doing hexadecimal base heuristic on first non-valid
> hexadecimal number, so "128k(bootloader)" is parsed as decimal number 128.
>
> Fixes: 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base 16...")
> Signed-off-by: Pali Rohár
> ---
> lib/strto.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/lib/strto.c b/lib/strto.c
> index 1ac2b09c72..060b66b915 100644
> --- a/lib/strto.c
> +++ b/lib/strto.c
> @@ -30,6 +30,9 @@ static const char *_parse_integer_fixup_radix(const char
> *s, unsigned int *base)
>
> do {
> var = tolower(s[i++]);
> + if (!(var >= '0' && var <= '9') &&
> + !(var >= 'a' && var <= 'f'))
> + break;
> if (var >= 'a' && var <= 'f') {
> *base = 16;
> break;
> --
> 2.20.1
>
CC Tom, this problem was detected by my in-progress Travis Nokia N900
test which tries to boot kernel from the OneNAND. Build log is there:
https://travis-ci.org/github/u-boot/u-boot/jobs/679007310
[PATCH v3 2/2] arm: stm32mp: activate data cache on DDR in SPL
Activate cache on DDR to improves the accesses to DDR used by SPL:
- CONFIG_SPL_BSS_START_ADDR
- CONFIG_SYS_SPL_MALLOC_START
Cache is configured only when DDR is fully initialized,
to avoid speculative access and issue in get_ram_size().
Data cache is deactivated at the end of SPL, to flush the data cache
and the TLB.
Signed-off-by: Patrick Delaunay
---
Changes in v3:
- remove debug message "bye"
Changes in v2:
- new
arch/arm/mach-stm32mp/spl.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
index f85391c6af..e50a21c3b7 100644
--- a/arch/arm/mach-stm32mp/spl.c
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -115,4 +116,22 @@ void board_init_f(ulong dummy)
printf("DRAM init failed: %d\n", ret);
hang();
}
+
+ /*
+* activate cache on DDR only when DDR is fully initialized
+* to avoid speculative access and issue in get_ram_size()
+*/
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
+ DCACHE_DEFAULT_OPTION);
+}
+
+void spl_board_prepare_for_boot(void)
+{
+ dcache_disable();
+}
+
+void spl_board_prepare_for_boot_linux(void)
+{
+ dcache_disable();
}
--
2.17.1
[PATCH v3 1/2] arm: stm32mp: activate data cache in SPL and before relocation
Activate the data cache in SPL and in U-Boot before relocation.
In arch_cpu_init(), the function early_enable_caches() sets the early
TLB, early_tlb[] located .init section, and set cacheable:
- for SPL, all the SYSRAM
- for U-Boot, all the DDR
After relocation, the function enable_caches() (called by board_r)
reconfigures the MMU with new TLB location (reserved in
board_f.c::reserve_mmu) and re-enable the data cache.
This patch allows to reduce the execution time, particularly
- for the device tree parsing in U-Boot pre-reloc stage
(dm_extended_scan_fd =>dm_scan_fdt)
- in I2C timing computation in SPL (stm32_i2c_choose_solution())
For example, the result on STM32MP157C-DK2 board is:
1,6s gain for trusted boot chain with TF-A
2,2s gain for basic boot chain with SPL
For information, as TLB is added in .data section, the binary size
increased and the SPL load time by ROM code increased (30ms on DK2).
But early maloc can't be used for TLB because arch_cpu_init()
is executed before the early poll initialization done in spl_common_init()
called by spl_early_init() So it too late for this use case.
And if I initialize the MMU and the cache after this function it is
too late, as dm_init_and_scan and fdt parsin is also called in
spl_common_init().
And .BSS can be used in board_init_f(): only stack and global can use
before BSS init done in board_init_r().
So .data is the better soluttion without hardcoded location but is you
have size issue for SPL you can deactivate cache for SPL only
(with CONFIG_SPL_SYS_DCACHE_OFF).
Signed-off-by: Patrick Delaunay
---
Changes in v3:
- add Information in commit-message on early malloc and .BSS
Changes in v2:
- create a new function early_enable_caches
- use TLB in .init section
- use the default weak dram_bank_mmu_setup() and
use mmu_set_region_dcache_behaviour() to setup
the early MMU configuration
- enable data cache on DDR in SPL, after DDR controller initialization
arch/arm/mach-stm32mp/cpu.c | 43 -
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 74d03fa7dd..712c2c594b 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -75,6 +75,12 @@
#define PKG_SHIFT 27
#define PKG_MASK GENMASK(2, 0)
+/*
+ * early TLB into the .data section so that it not get cleared
+ * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
+ */
+u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
+
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
#ifndef CONFIG_TFABOOT
static void security_init(void)
@@ -186,6 +192,32 @@ u32 get_bootmode(void)
TAMP_BOOT_MODE_SHIFT;
}
+/*
+ * initialize the MMU and activate cache in SPL or in U- Boot pre-reloc stage
+ * MMU/TLB is updated in enable_caches() for U-Boot after relocation
+ * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
+ */
+static void early_enable_caches(void)
+{
+ /* I-cache is already enabled in start.S: cpu_init_cp15 */
+
+ if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ return;
+
+ gd->arch.tlb_size = PGTABLE_SIZE;
+ gd->arch.tlb_addr = (unsigned long)&early_tlb;
+
+ dcache_enable();
+
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE,
+ STM32_SYSRAM_SIZE,
+ DCACHE_DEFAULT_OPTION);
+ else
+ mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
+ DCACHE_DEFAULT_OPTION);
+}
+
/*
* Early system init
*/
@@ -193,6 +225,8 @@ int arch_cpu_init(void)
{
u32 boot_mode;
+ early_enable_caches();
+
/* early armv7 timer init: needed for polling */
timer_init();
@@ -225,7 +259,14 @@ int arch_cpu_init(void)
void enable_caches(void)
{
- /* Enable D-cache. I-cache is already enabled in start.S */
+ /* I-cache is already enabled in start.S: icache_enable() not needed */
+
+ /* deactivate the data cache, early enabled in arch_cpu_init() */
+ dcache_disable();
+ /*
+* update MMU after relocation and enable the data cache
+* warning: the TLB location udpated in board_f.c::reserve_mmu
+*/
dcache_enable();
}
--
2.17.1
[PATCH v3 0/2] arm: stm32mp1: activate data cache in SPL and before relocation
V3 after first feedbacks of the previous serie "arm: stm32mp1: activate data cache in SPL and before relocation" http://patchwork.ozlabs.org/project/uboot/list/?series=168390 This serie depends on the ARM cache serie: "arm: caches: allow to activate dcache in SPL and in U-Boot pre-reloc" http://patchwork.ozlabs.org/project/uboot/list/?series=172555 I move tlb in .data section and simplify the implementation by reusing the default weak function dram_bank_mmu_setup() for MMU configuration and mmu_set_region_dcache_behaviour() to setup the specific behavior. I also activate data cache on DDR for SPL. For information the gain of the second patch is limited (few ms) for boot from SDCARD: the SDMMC IP use internal DMA and data cache on DDR is not really used. Gain should be better for other boot use-case. Example of bootstage report on STM32MP157C-DK2, boot from SD card. 1/ For trusted boot chain with TF-A a) Before STM32MP> bootstage report Timer summary in microseconds (9 records): MarkElapsed Stage 0 0 reset 583,290583,290 board_init_f 2,348,898 1,765,608 board_init_r 2,664,580315,682 id=64 2,704,027 39,447 id=65 2,704,729702 main_loop 5,563,519 2,858,790 id=175 Accumulated time: 41,696 dm_r 615,561 dm_f b) After the serie STM32MP> bootstage report Timer summary in microseconds (9 records): MarkElapsed Stage 0 0 reset 583,401583,401 board_init_f 727,725144,324 board_init_r 1,043,362315,637 id=64 1,082,806 39,444 id=65 1,083,507701 main_loop 3,680,827 2,597,320 id=175 Accumulated time: 36,047 dm_f 41,718 dm_r 2/ And for the basic boot chain with SPL a) Before: STM32MP> bootstage report Timer summary in microseconds (12 records): MarkElapsed Stage 0 0 reset 195,613195,613 SPL 837,867642,254 end SPL 840,117 2,250 board_init_f 2,739,639 1,899,522 board_init_r 3,066,815327,176 id=64 3,103,377 36,562 id=65 3,104,078701 main_loop 3,142,171 38,093 id=175 Accumulated time: 38,124 dm_spl 41,956 dm_r 648,861 dm_f b) After the serie STM32MP> bootstage report Timer summary in microseconds (12 records): MarkElapsed Stage 0 0 reset 195,859195,859 SPL 330,190134,331 end SPL 332,408 2,218 board_init_f 482,688150,280 board_init_r 808,694326,006 id=64 845,029 36,335 id=65 845,730701 main_loop 3,281,876 2,436,146 id=175 Accumulated time: 3,169 dm_spl 36,041 dm_f 41,701 dm_r STM32MP> bootstage report Timer summary in microseconds (12 records): MarkElapsed Stage 0 0 reset 211,036211,036 SPL 343,393132,357 end SPL 345,645 2,252 board_init_f 496,596150,951 board_init_r 822,256325,660 id=64 858,451 36,195 id=65 859,153702 main_loop 3,414,706 2,555,553 id=175 Accumulated time: 3,132 dm_spl 36,005 dm_f 41,695 dm_r Changes in v3: - add Information in commit-message on early malloc and .BSS - remove debug message "bye" Changes in v2: - create a new function early_enable_caches - use TLB in .init section - use the default weak dram_bank_mmu_setup() and use mmu_set_region_dcache_behaviour() to setup the early MMU configuration - enable data cache on DDR in SPL, after DDR controller initialization - new Patrick Delaunay (2): arm: stm32mp: activate data cache in SPL and before relocation arm: stm32mp: activate data cache on DDR in SPL arch/arm/mach-stm32mp/cpu.c | 43 - arch/arm/mach-stm32mp/spl.c | 19 2 files changed, 61 insertions(+), 1 deletion(-) -- 2.17.1
[PATCH v2 3/3] arm: caches: manage phys_addr_t overflow in mmu_set_region_dcache_behaviour
Solved the overflow on phys_addr_t type for start + size in
mmu_set_region_dcache_behaviour() function.
This overflow is avoided by dividing start and end by 2 before addition,
and we only expecting that start and size are even.
This patch doesn't change the current function behavior if the
parameters (start or size) are not aligned on MMU_SECTION_SIZE.
For example, this overflow occurs on ARM32 with:
start = 0xC000 and size = 0x4000
then start + size = 0x1 and end = 0x0.
For information the function behavior change with risk of regression,
if we just shift start and size before the addition.
Example with 2MB section size:
MMU_SECTION_SIZE 0x20 and MMU_SECTION_SHIFT = 21
with start = 0x100, size = 0x100,
- with the proposed patch, start = 0 and end = 0x1 as previously
- with the more simple patch:
end = (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT)
the value of end change:
start >> 21 = 0, size >> 21 = 0 and end = 0x0 !!!
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- update patch after Marek's proposal. but I just divided by 2 instead
of 4kB (minimal MMU page size)
arch/arm/lib/cache-cp15.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index d15144188b..f803d6fb8c 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -61,8 +61,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start,
size_t size,
unsigned long startpt, stoppt;
unsigned long upto, end;
- end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
+ /* div by 2 before start + size to avoid phys_addr_t overflow */
+ end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
+ >> (MMU_SECTION_SHIFT - 1);
start = start >> MMU_SECTION_SHIFT;
+
#ifdef CONFIG_ARMV7_LPAE
debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
option);
--
2.17.1
[PATCH v2 2/3] arm: caches: add DCACHE_DEFAULT_OPTION
Add the new flags DCACHE_DEFAULT_OPTION to define the default
option to use according the compilation flags
CONFIG_SYS_ARM_CACHE_*.
This new compilation flag allows to simplify dram_bank_mmu_setup()
and can be used as third parameter (option=dcache option to select)
of mmu_set_region_dcache_behaviour function.
Signed-off-by: Patrick Delaunay
---
CONFIG_SYS_ARM_CACHE_WRITEBACK dependency with
[v2] configs: migrate CONFIG_SYS_ARM_CACHE_* in Kconfig
http://patchwork.ozlabs.org/patch/1269103/
Changes in v2: None
arch/arm/include/asm/system.h | 8
arch/arm/lib/cache-cp15.c | 11 ++-
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 81ccead112..a3147fde14 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -485,6 +485,14 @@ enum dcache_option {
};
#endif
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
+#endif
+
/* Size of an MMU section */
enum {
#ifdef CONFIG_ARMV7_LPAE
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 54509f11c3..d15144188b 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -99,15 +99,8 @@ __weak void dram_bank_mmu_setup(int bank)
for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
(bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
-i++) {
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
- set_section_dcache(i, DCACHE_WRITETHROUGH);
-#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
- set_section_dcache(i, DCACHE_WRITEALLOC);
-#else
- set_section_dcache(i, DCACHE_WRITEBACK);
-#endif
- }
+i++)
+ set_section_dcache(i, DCACHE_DEFAULT_OPTION);
}
/* to activate the MMU we need to set up virtual memory: use 1M areas */
--
2.17.1
[PATCH] lib: strto: Fix parsing MTD partition size
Commit 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base 16
detection") broke parsing MTD partition sizes specified in decimal base.
E.g. "128k(bootloader)" is parsed by drivers/mtd/mtdpart.c as hexadecimal
number (0x128 << 10) because character 'a' in substring "bootloader" caused
parsing whole number as hexadecimal.
This patch stop doing hexadecimal base heuristic on first non-valid
hexadecimal number, so "128k(bootloader)" is parsed as decimal number 128.
Fixes: 0486497e2b5f ("lib: Improve _parse_integer_fixup_radix base 16...")
Signed-off-by: Pali Rohár
---
lib/strto.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/strto.c b/lib/strto.c
index 1ac2b09c72..060b66b915 100644
--- a/lib/strto.c
+++ b/lib/strto.c
@@ -30,6 +30,9 @@ static const char *_parse_integer_fixup_radix(const char *s,
unsigned int *base)
do {
var = tolower(s[i++]);
+ if (!(var >= '0' && var <= '9') &&
+ !(var >= 'a' && var <= 'f'))
+ break;
if (var >= 'a' && var <= 'f') {
*base = 16;
break;
--
2.20.1
[PATCH v2 1/3] arm: caches: protect dram_bank_mmu_setup access to bi_dram
Add protection in dram_bank_mmu_setup() to avoid access to bd->bi_dram
before relocation.
This patch allow to use the generic weak function dram_bank_mmu_setup
to activate the MMU and the data cache in SPL or in U-Boot before
relocation, when bd->bi_dram is not yet initialized.
In this cases, the MMU must be initialized explicitly with
mmu_set_region_dcache_behaviour function.
Signed-off-by: Patrick Delaunay
---
Changes in v2: None
arch/arm/lib/cache-cp15.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index f8d20960da..54509f11c3 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -91,6 +91,10 @@ __weak void dram_bank_mmu_setup(int bank)
bd_t *bd = gd->bd;
int i;
+ /* bd->bi_dram is available only after relocation */
+ if ((gd->flags & GD_FLG_RELOC) == 0)
+ return;
+
debug("%s: bank: %d\n", __func__, bank);
for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
--
2.17.1
[PATCH v2 0/3] arm: caches: allow to activate dcache in SPL and in U-Boot pre-reloc
Hi It is a V2 serie after Marek feedback for http://patchwork.ozlabs.org/project/uboot/list/?series=168378 This serie allows dcache activation in SPL or in U-Boot preloc stage for ARM board. See "arm: stm32mp1: activate data cache in SPL and before relocation" for example of usage in SPL and in U-Boot pre-reloc of the function dcache_enable() and of mmu_set_region_dcache_behaviour(). A branch named "dcache" with the needed patches for stm32mp1 boards is available in: https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git Changes in v2: - update patch after Marek's proposal. but I just divided by 2 instead of 4kB (minimal MMU page size) Patrick Delaunay (3): arm: caches: protect dram_bank_mmu_setup access to bi_dram arm: caches: add DCACHE_DEFAULT_OPTION arm: caches: manage phys_addr_t overflow in mmu_set_region_dcache_behaviour arch/arm/include/asm/system.h | 8 arch/arm/lib/cache-cp15.c | 20 ++-- 2 files changed, 18 insertions(+), 10 deletions(-) -- 2.17.1
RE: [PATCH v4 0/5] riscv: sifive/fu540: Enable SPI-NOR support
Hello Jagan, > -Original Message- > From: Jagan Teki > Sent: Thursday, April 23, 2020 10:31 PM > To: u-boot@lists.denx.de > Cc: Rick Chen ; Bin Meng ; > Bhargav Shah ; Sagar Kadam > ; linux-amar...@amarulasolutions.com; Jagan > Teki > Subject: [PATCH v4 0/5] riscv: sifive/fu540: Enable SPI-NOR support > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > This is series v4 for SPI-NOR support on SiFive FU540 platform with HiFive > Unleashed board. > > Here is the previous version changes[1]. > > All patches on top of u-boot-spi/master. > Thanks for posting v4 for spi-nor support. Tested the series above u-boot-spi/master on HiFive Unleashed and was able to verify it for both spi-nor and mmc Additionally just confirmed the opcodes nor is configured with post spi_nor_scan: == [QUAD mode in dt with spi-tx-bus-width: <4>] pp opcode = 0x34 [QUAD MODE] read opcode = 0x6c [QUAD MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc (so as to confirm data integrity from mmc) = [SPI MODE in dt with spi-tx-bus-width: <1> ] pp opcode = 0x12 [SPI MODE] read opcode = 0xc [SPI MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc (so as to confirm data integrity from mmc) Tested-by: Sagar Kadam Thanks & BR, Sagar Kadam > Changes for v4: > - add spi-mem exec_op > - rebase on master > Changes for v3: > - fixed QPP support > - dropped sf commands log > > [1] > https://patchwork.ozlabs.org/project/uboot/cover/20200420125238.9610-1- > ja...@amarulasolutions.com/ > > Any inputs? > Jagan. > > Jagan Teki (5): > spi: sifive: Add spi-mem exec op > spi: sifive: Fix format register proto field > spi: sifive: Fix QPP transfer > riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi > sifive: fu540: Enable spi-nor flash support > > .../dts/hifive-unleashed-a00-u-boot.dtsi | 11 ++ > board/sifive/fu540/Kconfig| 3 + > drivers/spi/spi-sifive.c | 156 +++--- > 3 files changed, 146 insertions(+), 24 deletions(-) create mode 100644 > arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi > > -- > 2.17.1
Re: support of rockchip nanopiM4 2GB board
Hi Kever, On 24/04/20 3:45 pm, Kever Yang wrote: > Hi Deepak, Jagan, > > On 2020/4/23 下午7:29, Jagan Teki wrote: >> On Thu, Apr 23, 2020 at 4:37 PM Deepak Das wrote: >>> Hi Jagan, >>> >>> upstream uboot has the support for nanopi M4 board with 4GB LPDDR3 RAM. >>> I have a nanopi M4 board with 2GB DDR3 RAM and able to boot this board >>> by using ddr3 configuration. >>> >>> +// SPDX-License-Identifier: GPL-2.0+ >>> +/* >>> + * Copyright (C) 2019 Jagan Teki >>> + */ >>> + >>> +#include "rk3399-nanopi4-u-boot.dtsi" >>> +#include "rk3399-sdram-ddr3-1866.dtsi" >>> + >>> +/* #include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" */ >>> >>> how to handle this situation? do we need to treat this as a new board >>> support? >> Possible approach is to check the chip type and vendor during probe >> and source the respective .dtsi >> >> YouMin and Kever, any ideas? > > > We can auto detect the different capacity for the same DRAM type, but if the > dram type > > is not the same, it usually treat as different boards. I don't see any other difference in these two board versions apart from DRAM type. I will drop a patch to add support of this board after some basic testing. > > And this is the first time for a board use two different type DRAM, does both > type of nanopi M4 > > with DDR3 and LPDDR3 are available on the market, or maybe one of them is > internal version? > yes, both are available at amazon. https://www.amazon.com/FriendlyARM-Rockchip-Dual-Band-Support-Learning/dp/B07GXNK8M1 https://www.amazon.com/FriendlyARM-Rockchip-Dual-Band-Support-Learning/dp/B07H9S92X6 regards, Deepak > > Thanks, > > - Kever > > >> >> Jagan. >> >> > >
Re: [PATCH v3 1/2] sandbox, test: add test for GPIO_HOG function
On Wed, Feb 05, 2020 at 07:19:58AM +0100, Heiko Schocher wrote: > currently gpio hog function is not tested with "ut dm gpio" > so add some basic tests for gpio hog functionality. > > For this enable GPIO_HOG in sandbox_defconfig, add > in DTS some gpio hog entries, and add testcase in > "ut dm gpio" command. > > Signed-off-by: Heiko Schocher > Reviewed-by: Simon Glass This no longer applies cleanly/obviously, please rebase, thanks! -- Tom signature.asc Description: PGP signature
[PULL] Pull request: u-boot-stm/master =u-boot-stm32-20200424
Hi Tom,
Please pull the STM32 related fixes for v2020.07 = u-boot-stm32-20200424
With the following changes:
- Solve stm32mp15 pinctrl dts issue (patch conlict in branches master and next)
- Split device tree for DHCOR Som and AV 96 board
- Update PLL4 setting in AV96 board
- Enable bootd, iminfo, imxtract on DHCOM
CI status:
https://gitlab.denx.de/u-boot/custodians/u-boot-stm/pipelines/2909
Thanks,
Patrick
The following changes since commit dbfd9e0e61ff1f9c65703959ed8e3ceb410d1e7e:
dm: pinctrl: Use right device pointer for configuring pinctrl (2020-04-23
08:25:37 -0400)
are available in the Git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
tags/u-boot-stm32-20200424
for you to fetch changes up to 23d203d62e0ec95bc42bf96c56df991ff924f360:
ARM: stm32: Enable bootd, iminfo, imxtract on DHCOM (2020-04-24 17:59:48
+0200)
- Solve stm32mp15 pinctrl dts issue (patch conflict in branches master and next)
- Split device tree for DHCOR Som and AV 96 board
- Update PLL4 setting in AV96 board
- Enable bootd, iminfo, imxtract on DHCOM
Marek Vasut (3):
ARM: dts: stm32: Adjust PLL4 settings on AV96
ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board
ARM: stm32: Enable bootd, iminfo, imxtract on DHCOM
Patrick Delaunay (1):
ARM: dts: stm32mp1: remove file stm32mp157-pinctrl.dtsi
arch/arm/dts/Makefile
|3 +-
arch/arm/dts/stm32mp15-pinctrl.dtsi
| 96
arch/arm/dts/stm32mp157-pinctrl.dtsi
| 1153
---
arch/arm/dts/stm32mp157a-avenger96.dts
| 423 +-
arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
| 83 +++
arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
| 212 +
arch/arm/dts/{stm32mp157a-avenger96-u-boot.dtsi =>
stm32mp15xx-dhcor-u-boot.dtsi} | 86 +--
arch/arm/dts/stm32mp15xx-dhcor.dtsi
| 232 +++
configs/stm32mp15_dhcom_basic_defconfig
|3 -
doc/board/st/stm32mp1.rst
|8 +-
10 files changed, 638 insertions(+), 1661 deletions(-)
delete mode 100644 arch/arm/dts/stm32mp157-pinctrl.dtsi
create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
rename arch/arm/dts/{stm32mp157a-avenger96-u-boot.dtsi =>
stm32mp15xx-dhcor-u-boot.dtsi} (71%)
create mode 100644 arch/arm/dts/stm32mp15xx-dhcor.dtsi
Partial fix for RTL8211CL connectivity issue
Hello,
My A20-OLinuXino-LIME2 has a RTL8211CL network adapter and is affected by the
same issue described for RTL8211F_PHY_FORCE_EEE_RXC_ON. In
u-boot/drivers/net/phy/realtek.c I copied «phydev->flags |=
PHY_RTL8211F_FORCE_EEE_RXC_ON;» inside rtl8211b_probe() and the following
portion of code enabled by the fix at the beginning of rtl8211x_config():
if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) {
unsigned int reg;
reg = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
reg &= ~MDIO_PCS_CTRL1_CLKSTOP_EN;
phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, reg);
}
When rebooting from GNU/Linux in Das U-Boot, issuing «dhcp» gives me this:
=> dhcp
ethernet@1c5 Waiting for PHY auto negotiation to complete. TIMEOUT !
Could not initialize PHY ethernet@1c5
using musb-hdrc, OUT ep1out IN ep1in STATUS ep2in
MAC de:ad:be:ef:00:01
HOST MAC de:ad:be:ef:00:00
RNDIS ready
The remote end did not respond in time.
If I issue the same command once again immediately after, it will instantly
report the device as connected, with no delay at all, as if it was already
connected the first time, but the driver failed to report the device as
connected.
If you have no clue for a proper fix, I will try to set up a GDB environment to
see what's going on. I am no expert though.
Re: [PATCH] dlmalloc: Add an option to default malloc to init
On Tue, Apr 21, 2020 at 01:00:41PM +0200, Marek wrote: > > > > Can you please showcase using this feature somewhere? Thanks! > > > > -- > > Tom > > Yes. First of all, sincere apology for such a massive delay in it. > I got snowed with the corporation work of mine. > > So here is my go at showcasing it. We are in SPL U-Boot running code from > within the static memory: > arch/arm/cpu/armv8/start.S:reset vector > -> arch/arm/cpu/armv8/start.S:main() > -> arch/arm/lib/crt0_64.S:board_init_f() > -> /board//common/spl.c:board_init_f() > > board_init_f() does mem_malloc_init(malloc_start_in_static, size). It needs > the malloc for SPI flash to load off some proprietary stuff. > Note the size of the static memory is limited, so is our malloc size. > > Then along it does the DDR memory initialization. Now we have much greater > memory > and can move our malloc allocator onto it. So again it does mem_malloc_init() > but this time with an address in the DDR memory and a much greater size. > And this is where this feature comes in hand. Just calling in > mem_malloc_init() > with the updated start addr and the size isn't enough. It also mandates > resetting the malloc, namely defaulting its bins, and some bookkeeping. > > I know there is an early malloc available I can use as the first one but that > requires managing the two mallocs. This patch proposes to use a single malloc > suite (dlmalloc) and use it freely around when and how it is needed. OK, thanks. Can you please re-send and include the above re-phrased to make sense in a commit message, in the body of the commit as well so it's documented more in-tree when this would be helpful? Thanks again! > > Marek -- Tom signature.asc Description: PGP signature
Re: [PATCH] sunxi: Fix PHY regression on A20-OLinuXino-Lime2 and A20-Olimex-SOM-EVB
On Fri, Apr 24, 2020 at 07:09:56PM +0200, Anatolij Gustschin wrote:
> On Fri, 24 Apr 2020 12:34:05 -0400
> Tom Rini tr...@konsulko.com wrote:
>
> > When moving the PHYLIB PHY drivers around in Kconfig we did not at the
> > same time perform a careful migration of the related drivers and
> > sub-options. This lead to the case where previously Kconfig-enabled
> > driver choices were now disabled on some platforms. Correct this by
> > enabling both the PHY driver and sub-option on the above referenced
> > platforms.
> >
> > Fixes: af2cbfd6b982 ("drivers: net: Provide Kconfig menu for PHYLIB")
> > Fixes: 8728c97eff5b ("configs: Re-sync")
> > Reported-by: Dario
> > Signed-off-by: Tom Rini
> > ---
> > After checking back on the original commit I can see that these are the
> > only two platforms to have been broken in the change.
>
> configs/A20-OLinuXino-Lime2-eMMC_defconfig might need similar change.
>
> We get many build warnings like:
> include/configs/sunxi-common.h:276:0: warning: "CONFIG_PHY_REALTEK" redefined
>
> Could you include following change to fix it?
>
> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
> index 0ef289fd64..f4bbce8443 100644
> --- a/include/configs/sunxi-common.h
> +++ b/include/configs/sunxi-common.h
> @@ -273,8 +273,10 @@ extern int soft_i2c_gpio_scl;
> /* Ethernet support */
>
> #ifdef CONFIG_SUN7I_GMAC
> +#ifndef CONFIG_PHY_REALTEK
> #define CONFIG_PHY_REALTEK
> #endif
> +#endif
>
> #ifdef CONFIG_USB_EHCI_HCD
> #define CONFIG_USB_OHCI_NEW
The problem with that is that it's showing that this symbol, and a whole
host of others from af2cbfd6b982 need to be migrated over to defconfigs.
--
Tom
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Description: PGP signature
Re: [PATCH v2] travis: Correct error checking when building boards
On Sun, Apr 19, 2020 at 05:02:32PM -0600, Simon Glass wrote: > At present if buildman reports an error, the travis build still succeeds. > > This is because the travis script does not stop when it sees errors; nor > does it automatically return the exit code. Also the current error > checking never triggers since 'ret' is not set. > > Fix this by setting 'ret' correctly. > > Signed-off-by: Simon Glass > Reported-by: Michal Simek > Acked-by: Michal Simek Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 3/3] mkimage: fit: Free buf directly in fit_extract_data()
On Sat, Apr 18, 2020 at 01:59:11AM -0700, Bin Meng wrote: > From: Bin Meng > > If given ptr to free() is NULL, no operation is performed. > Hence we can just free buf directly in fit_extract_data(). > > Signed-off-by: Bin Meng Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] spl: Kconfig: de-dup SPL_DM_GPIO definition
On Fri, Apr 17, 2020 at 09:42:29AM -0600, Joel Johnson wrote: > Two nearly concurrent commits (d4d65e112 and bcee8d676) added a > SPL_DM_GPIO symbol. Resolve the duplication in favor of the version > in drivers/gpio/Kconfig. > > Signed-off-by: Joel Johnson > Reviewed-by: Frieder Schrempf Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v6 0/5] usb: host: dwc2: use driver model for PHY and CLOCK
On 4/24/20 3:42 PM, Patrick DELAUNAY wrote:
> Dear Marek,
>
>> From: Patrick DELAUNAY
>> Sent: mardi 10 mars 2020 11:09
>>
>>
>> In this serie I update the DWC2 host driver to use the device tree
>> information and
>> the associated PHY and CLOCK drivers when they are availables.
>>
>> V6 is minor update of the first patch of the serie; I update some clk stub
>> to return
>> success after Simon Goldschmidt remarks on V5:
>> http://patchwork.ozlabs.org/project/uboot/list/?series=162791
>>
>> I test the V4 of this serie on stm32mp157c-ev1 board, with PHY and CLK
>> support
>> (V5 was a minor update).
>>
>> The U-CLASS are provided by:
>> - PHY by USBPHYC driver = ./drivers/phy/phy-stm32-usbphyc.c
>> - CLOCK by RCC clock driver = drivers/clk/clk_stm32mp1.c
>> - RESET by RCC reset driver = drivers/reset/stm32-reset.c
>>
>> And I activate the configuration
>> +CONFIG_USB_DWC2=y
>>
>> PS: it is not the default configuration to avoid conflict with gadget
>> driver
>>
>> To solve a binding issue, I also deactivate the gadget support:
>> by default only one driver is bound to the usbotg_hs node with "snps,dwc2"
>> compatible, and today it is the device one (the first in the driver list).
>>
>> I also need to deactivate hnp-srp support with:
>>
>> &usbotg_hs {
>> /* need to disable ONLY for HOST support */
>> hnp-srp-disable;
>> };
>>
>> WARNING: OTG with device or host support is not correctly handle by DWC2
>> driver (see example for dynamic OTG role in DWC3 driver).
>>
>> The tests executed on the stm32mp157c-ev1 target:
>>
>> STM32MP> usb start
>> starting USB...
>> Bus usb-otg@4900: USB DWC2
>> Bus usbh-ehci@5800d000: USB EHCI 1.00
>> scanning bus usb-otg@4900 for devices... 2 USB Device(s) found scanning
>> bus usbh-ehci@5800d000 for devices... 3 USB Device(s) found
>>scanning usb for storage devices... 2 Storage Device(s) found
>> STM32MP> usb tree
>> USB device tree:
>> 1 Hub (480 Mb/s, 0mA)
>> | U-Boot Root Hub
>> |
>> +-2 Mass Storage (480 Mb/s, 300mA)
>>Verbatim STORE N GO 070731C8ACD7EE97
>>
>> 1 Hub (480 Mb/s, 0mA)
>> | u-boot EHCI Host Controller
>> |
>> +-2 Hub (480 Mb/s, 2mA)
>>
>> STM32MP> ls usb 0
>>4096 .
>>4096 ..
>> 16384 lost+found
>>4096 record
>> 1490212 xipImage
>> 21058006 vmlinux
>>
>> STM32MP> load usb 0 0xC000 vmlinux
>> 21058006 bytes read in 10851 ms (1.9 MiB/s)
>>
>>
>> Changes in v6:
>> - return success in stub for clk_free/clk_enable/clk_disable/
>> clk_enable_bulk/clk_disable_bulk
>>
>> Changes in v5:
>> - use ERR_PTR in clk_get_parent()
>> - force bulk->count = 0 in clk_get_bulk to avoid issue
>> for next call of clk_enable_bulk / clk_enable_bulk
>> - update commit message
>> - inverse logic for -ENOENT test on generic_phy_get_by_index result
>> - Add some comments
>>
>> Changes in v4:
>> - Add stub for all functions using 'struct clk' or 'struct clk_bulk'
>> after remarks on v3
>>
>> Changes in v3:
>> - Add stub for clk_disable_bulk
>>
>> Changes in v2:
>> - update dev_err
>> - update commit message
>> - change dev_err to dev_dbg for PHY function call
>> - treat dwc2_shutdown_phy error
>> - add clk_disable_bulk in dwc2_usb_remove
>>
>> Patrick Delaunay (5):
>> dm: clk: add stub when CONFIG_CLK is deactivated
>> usb: host: dwc2: add phy support
>> usb: host: dwc2: add clk support
>> usb: host: dwc2: force reset assert
>> usb: host: dwc2: add trace to have clean usb start
>>
>> drivers/usb/host/dwc2.c | 100 ++-
>> include/clk.h | 102 +++-
>> 2 files changed, 188 insertions(+), 14 deletions(-)
>>
>> --
>> 2.17.1
>
> Gentle reminder.
Rebase and resend please.
Re: [PATCH 2/3] mkimage: fit: Unmmap the memory before closing fd in fit_import_data()
On Sat, Apr 18, 2020 at 01:59:10AM -0700, Bin Meng wrote: > From: Lihua Zhao > > Without calling munmap(), the follow-up call to open() the same file > with a flag O_TRUNC seems not to cause any issue on Linux, but it fails > on Windows with error like below: > > Can't open kernel_fdt.itb.tmp: Permission denied > > Fix this by unmapping the memory before closing fd in fit_import_data(). > > Signed-off-by: Lihua Zhao > Signed-off-by: Bin Meng Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] doc: invalid doc link in rstFlatTable.py
On Sat, Apr 18, 2020 at 02:16:34AM +0200, Heinrich Schuchardt wrote: > Remove an invalid documentation link in rstFlatTable.py. This synchronizes > the file with Linux next-20200413. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/3] tools: Remove the out-of-date MinGW support codes
On Sat, Apr 18, 2020 at 01:59:09AM -0700, Bin Meng wrote: > From: Bin Meng > > MinGW build for U-Boot tools has been broken for years. The official > support of Windows build is now MSYS2. Remove the MinGW support codes. > > Signed-off-by: Bin Meng Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 5/5] dlmalloc: remove unit test support in SPL
On Wed, Apr 15, 2020 at 06:46:23PM +0200, Heinrich Schuchardt wrote: > We cannot run unit tests in SPL. So remove the unit test support. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 4/5] lib: do not provide hexdump in SPL
On Wed, Apr 15, 2020 at 06:46:22PM +0200, Heinrich Schuchardt wrote: > SPL should not be enlarged by building with CONFIG_HEXDUMP=y. > > Signed-off-by: Heinrich Schuchardt > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] .mailmap: map Ruchika Gupta's mail address
On Wed, Apr 15, 2020 at 06:47:38PM +, Heinrich Schuchardt wrote: > Freescale mail addresses are not valid anymore. > > Reported-by: Fabio Estevam > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/2] fixdep: Re-sync with Linux 5.7-rc1
On Thu, Apr 16, 2020 at 02:01:45PM +0900, Masahiro Yamada wrote: > fixdep is a standalone host program, so we can just re-sync it with > the latest Linux in one commit. > > I kept the U-Boot own code block surrounded by > /* hack for U-Boot */ ... /* U-boot hack end */. > > Signed-off-by: Masahiro Yamada Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/2] fixdep: handle CONFIG_IS_ENABLE() and friends for TPL
On Thu, Apr 16, 2020 at 02:01:44PM +0900, Masahiro Yamada wrote:
> Since commit f1c6e1922eb5 ("spl: dm: use CONFIG_IS_ENABLED to test for
> the DM option"), CONFIG_IS_ENABLED() handles CONFIG_TPL_* options, but
> fixdep still cannot because it hard-codes the "SPL_" prefix as follows:
>
> char tmp_buf[256] = "SPL_"; /* hack for U-Boot */
>
> Take care of the "TPL_" prefix too.
>
> Signed-off-by: Masahiro Yamada
Applied to u-boot/master, thanks!
--
Tom
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Re: [PATCH 3/5] common: image_sign_info helper functions in SPL
On Wed, Apr 15, 2020 at 06:46:21PM +0200, Heinrich Schuchardt wrote:
> Do not build image_sign_info helper functions in SPL if not needed.
>
> Fixes: b983cc2da0ba ("lib: rsa: decouple rsa from FIT image verification")
> Signed-off-by: Heinrich Schuchardt
> Reviewed-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
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Re: [PATCH v4 8/8] mkimage: fit_image: Add option to make fit header align
On Mon, Mar 30, 2020 at 11:56:24AM +0800, Kever Yang wrote: > The image is usually stored in block device like emmc, SD card, make the > offset of image data aligned to block(512 byte) can avoid data copy > during boot process. > eg. SPL boot from FIT image with external data: > - SPL read the first block of FIT image, and then parse the header; > - SPL read image data separately; > - The first image offset is the base_offset which is the header size; > - The second image offset is just after the first image; > - If the offset of imge does not aligned, SPL will do memcpy; > The header size is a ramdon number, which is very possible not aligned, so > add '-B size'to specify the align size in hex for better performance. > > example usage: > ./tools/mkimage -E -f u-boot.its -B 0x200 u-boot.itb > > Signed-off-by: Kever Yang > Reviewed-by: Punit Agrawal > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] qemu: don't allow to select 32- and 64-bit
On Fri, Apr 10, 2020 at 09:37:21AM +0200, Heinrich Schuchardt wrote: > TARGET_QEMU_ARM_64BIT and TARGET_QEMU_ARM_32BIT should be mutually > exclusive. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] tools: image-host.c: use correct output format
On Sat, Apr 11, 2020 at 06:36:04PM +0200, Heinrich Schuchardt wrote:
> When building on a 32bit host the following warning occurs:
>
> tools/image-host.c: In function ‘fit_image_read_data’:
> tools/image-host.c:310:42: warning: format ‘%ld’ expects argument of type
> ‘long int’, but argument 3 has type ‘ssize_t’ {aka ‘int’} [-Wformat=]
>printf("Can't read all file %s (read %ld bytes, expexted %ld)\n",
> ~~^
> %d
> filename, n, sbuf.st_size);
> ~
>
> n is of type ssize_t so we should use %zd for printing.
>
> Fixes: 7298e422504e ("mkimage: fit: add support to encrypt image with aes")
> Signed-off-by: Heinrich Schuchardt
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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Re: [PATCH] fvp: Add support for loading Android boot images via semihosting
On Fri, Apr 03, 2020 at 07:58:24PM -0700, Peter Collingbourne wrote: > FVP now loads an Android boot image named boot.img if available, > otherwise it falls back to the existing code path. > > Signed-off-by: Peter Collingbourne > Reviewed-by: Ryan Harkin > Reviewed-by: Linus Walleij Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/5] lib: do not build OID registry in SPL
On Wed, Apr 15, 2020 at 06:46:19PM +0200, Heinrich Schuchardt wrote:
> The OID registry is only used by crypto functions that are not built in
> SPL. So we should not build it in SPL.
>
> Fixes: a9b45e6e8382 ("lib: add oid registry utility")
> Signed-off-by: Heinrich Schuchardt
> Reviewed-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
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Re: [PATCH 1/1] Makefile: ARMv7-M has no CPSR register
On Fri, Apr 10, 2020 at 11:10:32AM +0200, Heinrich Schuchardt wrote: > Compiling on ARMv7-M fails when trying to address the CPSR register which > is not available on this architecture. > > Atomic functions refer to the CPSR register if compiled with > arch/arm/include/asm/proc-armv/system.h. On ARMv7-M we should hence > use arch/arm/thumb1/include/asm/proc-armv/system.h instead. > > Cf. > https://stackoverflow.com/questions/61097841/error-selected-processor-does-not-support-requested-special-purpose-register > > Reported-by: Sicris Rey Embay > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 5/8] tools: imx8mimage: remove redundant code
On Mon, Mar 30, 2020 at 11:56:21AM +0800, Kever Yang wrote: > The align for fit_size has been done twice, remove the first one for it > does not make any sense. > > Signed-off-by: Kever Yang > Reviewed-by: Punit Agrawal > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 7/8] libfdt: Make fdtdec_get_child_count() available for HOST
On Mon, Mar 30, 2020 at 11:56:23AM +0800, Kever Yang wrote: > The tool need to use fdtdec_get_child_count(), make it available for > HOST_CC. > > Signed-off-by: Kever Yang > Reviewed-by: Punit Agrawal > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] sunxi: Fix PHY regression on A20-OLinuXino-Lime2 and A20-Olimex-SOM-EVB
On Fri, 24 Apr 2020 12:34:05 -0400
Tom Rini tr...@konsulko.com wrote:
> When moving the PHYLIB PHY drivers around in Kconfig we did not at the
> same time perform a careful migration of the related drivers and
> sub-options. This lead to the case where previously Kconfig-enabled
> driver choices were now disabled on some platforms. Correct this by
> enabling both the PHY driver and sub-option on the above referenced
> platforms.
>
> Fixes: af2cbfd6b982 ("drivers: net: Provide Kconfig menu for PHYLIB")
> Fixes: 8728c97eff5b ("configs: Re-sync")
> Reported-by: Dario
> Signed-off-by: Tom Rini
> ---
> After checking back on the original commit I can see that these are the
> only two platforms to have been broken in the change.
configs/A20-OLinuXino-Lime2-eMMC_defconfig might need similar change.
We get many build warnings like:
include/configs/sunxi-common.h:276:0: warning: "CONFIG_PHY_REALTEK" redefined
Could you include following change to fix it?
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 0ef289fd64..f4bbce8443 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -273,8 +273,10 @@ extern int soft_i2c_gpio_scl;
/* Ethernet support */
#ifdef CONFIG_SUN7I_GMAC
+#ifndef CONFIG_PHY_REALTEK
#define CONFIG_PHY_REALTEK
#endif
+#endif
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_OHCI_NEW
Thanks!
Anatolij
Re: [PATCH v4 6/8] tool: use ALIGN() to align the size
On Mon, Mar 30, 2020 at 11:56:22AM +0800, Kever Yang wrote: > Use the ALIGN() for size align so that the code is more readable. > > Signed-off-by: Kever Yang > Reviewed-by: Punit Agrawal > Reviewed-by: Tom Rini > Reviewed-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 4/8] tools: kwbimage: use common ALIGN to do the size align
On Mon, Mar 30, 2020 at 11:56:20AM +0800, Kever Yang wrote: > The ALIGN() is now available at imagetool.h, migrate to use it. > > Signed-off-by: Kever Yang > Reviewed-by: Punit Agrawal > Reviewed-by: Tom Rini > Reviewed-by: Stefan Roese Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2] bootcount_ext: Add flag to enable/disable bootcount
On Tue, Mar 17, 2020 at 05:59:09PM +0100, Frédéric Danis wrote: > After a successful upgrade, multiple problem during boot sequence may > trigger the altbootcmd process. > This patch adds a version and an upgrade_available entries to the > bootcount file to enable/disable the bootcount check. > When failing to read the bootcount file it will consider that bootcount is > enabled, acting as previously, and update the file accordingly. > > The bootcount file is only saved when `upgrade_available` is true, this > allows to save writes to the filesystem. > > Signed-off-by: Frédéric Danis > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 3/8] tools: mkimage: use common ALIGN to do the size align
On Mon, Mar 30, 2020 at 11:56:19AM +0800, Kever Yang wrote: > The ALIGN() is now available at imagetool.h, migrate to use it. > > Signed-off-by: Kever Yang > Reviewed-by: Punit Agrawal > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 1/8] tool: Move ALIGN_MASK to header as common MACRO
On Mon, Mar 30, 2020 at 11:56:17AM +0800, Kever Yang wrote: > The ALIGN code is need by many files who need handle structure or image > align, so move the macro to imagetool.h file. > > Signed-off-by: Kever Yang > Reviewed-by: Punit Agrawal > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 4/4] make env_entry::callback conditional on !CONFIG_SPL_BUILD
On Thu, Feb 27, 2020 at 01:56:12PM +, Rasmus Villemoes wrote: > The callback member of struct env_entry is always NULL for an SPL > build. Removing it thus saves a bit of run-time memory in the > SPL (when CONFIG_SPL_ENV_SUPPORT=y) since struct env_entry is embedded > in struct env_entry_node - i.e. about 2KB for the normal case of > 512+change hash table entries. > > Two small fixups are needed for this, all other references to the > callback member are already under !CONFIG_SPL_BUILD: Don't initialize > .callback in set_flags() - hsearch_r doesn't use that value > anyway. And make env_callback_init() initialize ->callback to NULL for > a new entry instead of relying on an unused or deleted entry having > NULL in ->callback. > > Signed-off-by: Rasmus Villemoes > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 2/8] tool: aisimage: use ALIGN instead of self defiend macro
On Mon, Mar 30, 2020 at 11:56:18AM +0800, Kever Yang wrote: > The ALIGN() is available at imagetool.h, no need to self define one. > > Signed-off-by: Kever Yang > Reviewed-by: Punit Agrawal > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] docs: Fix conf.py for Sphinx 2.0
On Fri, Mar 20, 2020 at 02:18:30AM -0400, Sean Anderson wrote: > From: Jonathan Corbet > > commit 3bc8088464712fdcb078eefb68837ccfcc413c88 upstream. > > Our version check in Documentation/conf.py never envisioned a world where > Sphinx moved beyond 1.x. Now that the unthinkable has happened, fix our > version check to handle higher version numbers correctly. > > Signed-off-by: Jonathan Corbet > [rebase for u-boot] > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] watchdog: mpc8xx_wdt: Allow selection of watchdog mode through environment
On Wed, Feb 19, 2020 at 04:50:15PM +, Christophe Leroy wrote: > From: Charles Frey > > The mpc8xx watchdog can work either in 'reset mode' or 'NMI mode'. > The selection can be done at startup only. > It is desirable to select the mode without rebuilding U-boot. > It is also desirable to disable the watchdog without rebuilding. > > At watchdog startup, check environment variable 'watchdog_mode'. > If it is 'off', the watchdog is not started. If it is 'nmi', > the watchdog is started in NMI mode. Otherwise, it is started > in reset mode which is the default mode. > > Signed-off-by: Charles Frey > Signed-off-by: Christophe Leroy Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 3/4] lib/hashtable.c: don't test ->callback in SPL
On Thu, Feb 27, 2020 at 01:56:11PM +, Rasmus Villemoes wrote: > In SPL, environment callbacks are not supported, so e->callback is > always NULL. Removing this makes the SPL a little smaller (about 400 > bytes in my ppc build) with no functional change. > > Signed-off-by: Rasmus Villemoes > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/4] env: remove callback.o for an SPL build
On Thu, Feb 27, 2020 at 01:56:10PM +, Rasmus Villemoes wrote: > env.h says this about about callback declarations (U_BOOT_ENV_CALLBACK): > > * For SPL these are silently dropped to reduce code size, since environment > * callbacks are not supported with SPL. > > So env_callback_init() does a lot of work to not find anything in the > guaranteed empty env_clbk list. Drop callback.o entirely from the link > and stub out the only public function defined in callback.o. This cuts > about 600 bytes from the SPL on my ppc build. > > Signed-off-by: Rasmus Villemoes > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/4] lib/hashtable.c: create helper for calling env_entry::callback
On Thu, Feb 27, 2020 at 01:56:11PM +, Rasmus Villemoes wrote: > This is preparation for compiling out the "call the callback" code and > associated error handling for SPL, where ->callback is always NULL. > > Signed-off-by: Rasmus Villemoes > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 5/5] env/sf.c: drop private CMD_SAVEENV logic
On Wed, Feb 19, 2020 at 09:47:43AM +, Rasmus Villemoes wrote: > Deciding whether to compile the env_sf_save() function based solely on > CONFIG_SPL_BUILD is wrong: For U-Boot proper, it leads to a build > warning in case CONFIG_CMD_SAVEENV=n (because the env_save_ptr() macro > causes the function to indeed not be referenced anywhere). And for > SPL, when one selects CONFIG_SPL_SAVEENV, one obviously expects to > actually be able to save the environment. > > Signed-off-by: Rasmus Villemoes Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/5] env_internal.h: add alternative ENV_SAVE_PTR macro
On Wed, Feb 19, 2020 at 09:47:40AM +, Rasmus Villemoes wrote: > The current definition of the env_save_ptr does not take SPL_SAVEENV > into account. Moreover, the way it is implemented means that drivers > need to guard the definitions of their _save methods with ifdefs to > avoid "defined but unused" warnings in case CMD_SAVEENV=n. > > The ifdeffery can be avoided by using a "something ? x : NULL" > construction instead and still have the compiler elide the _save > method when it is not referenced. Unfortunately we can't just switch > the existing env_save_ptr macro, since that would give a lot of build > errors unless all the ifdeffery is removed at the same time. > Conversely, removing that ifdeffery first would merely lead to the > "defined but unused" warnings temporarily, but for some storage > drivers it requires a bit more work than just removing their private > CMD_SAVEENV logic. > > So introduce an alternative to env_save_ptr, which for lack of a > better name is simply uppercased, allowing one to update storage > drivers piecemeal to both reduce their ifdeffery and honour > CONFIG_SPL_SAVEENV. > > Signed-off-by: Rasmus Villemoes Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 3/5] env/fat.c: remove private CMD_SAVEENV logic
On Wed, Feb 19, 2020 at 09:47:41AM +, Rasmus Villemoes wrote: > Always compile the env_fat_save() function, and let > CONFIG_IS_ENABLED(SAVEENV) (via the ENV_SAVE_PTR macro) decide whether > it actually ends up being compiled in. > > Signed-off-by: Rasmus Villemoes Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 4/5] env/ext4.c: remove CONFIG_CMD_SAVEENV ifdef
On Wed, Feb 19, 2020 at 09:47:42AM +, Rasmus Villemoes wrote: > Removing this ifdef/endif pair yields a "defined but unused warning" > for CONFIG_CMD_SAVEENV=n, but that vanishes if we use the ENV_SAVE_PTR > macro instead. This gives slightly better compile testing, and > moreover, it's possible to have > > CONFIG_CMD_SAVEENV=n > CONFIG_SPL_SAVEENV=y > SPL_ENV_IS_IN_EXT4=y > > in which case env_ext4_save would erroneously not be compiled in. > > Signed-off-by: Rasmus Villemoes Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/5] env: add SAVEENV as an alias of the CMD_SAVEENV symbol
On Wed, Feb 19, 2020 at 09:47:39AM +, Rasmus Villemoes wrote: > Currently, testing whether to compile in support for saving the > environment is a bit awkward when one needs to take SPL_SAVEENV into > account, and quite a few storage drivers currently do not honour > SPL_SAVEENV. > > To make it a bit easier to decide whether environment saving should be > enabled, introduce SAVEENV as an alias for the CMD_SAVEENV > symbol. Then one can simply use > > CONFIG_IS_ENABLED(SAVEENV) > > Signed-off-by: Rasmus Villemoes Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [U-Boot 1/1] eth: mtk-eth: add mt7531 switch support in mediatek eth driver
On Tue, Feb 18, 2020 at 04:49:37PM +0800, Landen Chao wrote:
> mt7531 is a 7-ports switch with 5 embedded giga phys, and uses the same
> MAC design of mt7530. The cpu port6 supports SGMII only. The cpu port5
> supports RGMII or SGMII in different model.
>
> mt7531 is connected to mt7622 via both RGMII and SGMII interfaces.
> In this patch, mt7531 cpu port5 or port6 is configured to maximum
> capability to align CPU MAC setting.
>
> The dts has been committed in the commit 6efa450565cdc ("arm: dts:
> mediatek: add ethernet and sgmii dts node for mt7622")
>
> Signed-off-by: Landen Chao
> Tested-by: Frank Wunderlich
Applied to u-boot/master, thanks!
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[PATCH v1 09/10] pci: Add driver for Broadcom STB PCIe controller
This patch adds basic driver for the Broadcom STB PCIe host controller. The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI handling removed. The inbound access memory region is not currently parsed from dma-ranges DT property and a fixed 4GB region is used. The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805 USB Host Controller. Signed-off-by: Nicolas Saenz Julienne Signed-off-by: Sylwester Nawrocki --- Changes since RFC: - reworked to align with current Linux mainline version and u-boot driver by Nicolas Saenz Julienne --- drivers/pci/Kconfig| 6 + drivers/pci/Makefile | 1 + drivers/pci/pcie_brcmstb.c | 593 + 3 files changed, 600 insertions(+) create mode 100644 drivers/pci/pcie_brcmstb.c diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 437cd9a..056a021 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -197,4 +197,10 @@ config PCIE_MEDIATEK Say Y here if you want to enable Gen2 PCIe controller, which could be found on MT7623 SoC family. +config PCI_BRCMSTB + bool "Broadcom STB PCIe controller" + depends on DM_PCI + depends on ARCH_BCM283X + help + Say Y here if you want to enable Broadcom STB PCIe controller support. endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c051ecc..3e53b1f 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o +obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c new file mode 100644 index 000..dfe9833 --- /dev/null +++ b/drivers/pci/pcie_brcmstb.c @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Broadcom STB PCIe controller driver + * + * Copyright (C) 2020 Samsung Electronics Co., Ltd. + * + * Based on upstream Linux kernel driver: + * drivers/pci/controller/pcie-brcmstb.c + * Copyright (C) 2009 - 2017 Broadcom + * + * Based driver by Nicolas Saenz Julienne + * Copyright (C) 2020 Nicolas Saenz Julienne + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */ +#define BRCM_PCIE_CAP_REGS 0x00ac + +/* Broadcom STB PCIe Register Offsets */ +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc +#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0 + +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xff + +#define PCIE_RC_DL_MDIO_ADDR 0x1100 +#define PCIE_RC_DL_MDIO_WR_DATA0x1104 +#define PCIE_RC_DL_MDIO_RD_DATA0x1108 + +#define PCIE_MISC_MISC_CTRL0x4008 +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK0x1000 +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x30 +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_1280x0 +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK0xf800 + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c +#define PCIE_MEM_WIN0_LO(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4) + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 +#define PCIE_MEM_WIN0_HI(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4) + +#define PCIE_MISC_RC_BAR1_CONFIG_LO0x402c +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f + +#define PCIE_MISC_RC_BAR2_CONFIG_LO0x4034 +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f +#define PCIE_MISC_RC_BAR2_CONFIG_HI0x4038 + +#define PCIE_MISC_RC_BAR3_CONFIG_LO0x403c +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f + +#define PCIE_MISC_PCIE_STATUS 0x4068 +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80 +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20 +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10 +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40 + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT0x4070 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK0xfff0 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12 +#define PCIE_MEM_WIN0_BASE_LIMIT(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win)
[PATCH v1 10/10] config: Enable support for the XHCI controller on RPI4 board
From: Marek Szyprowski This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI and USB commands. To get it working one has to call the following commands: "pci enum; usb start;", thus such commands have been added to the default "preboot" environment variable. One has to update their environment if it is already configured to get this feature working out of the box. Signed-off-by: Marek Szyprowski --- Changes since RFC: - none. --- configs/rpi_4_32b_defconfig | 9 + configs/rpi_4_defconfig | 10 ++ configs/rpi_arm64_defconfig | 9 - 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 72cda5d..0dd763f 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set @@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y CONFIG_ENV_FAT_INTERFACE="mmc" @@ -28,12 +32,17 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 6d148da..f80e5da 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set @@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y CONFIG_ENV_FAT_INTERFACE="mmc" @@ -28,12 +32,18 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index fea86be..926dfc3 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="usb start" +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y @@ -26,11 +27,17 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_DWC2=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y -- 2.7.4
[PATCH v1 06/10] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
From: Marek Szyprowski
Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff80 CPU virtual address.
Signed-off-by: Marek Szyprowski
---
Changes since RFC:
- none.
---
arch/arm/mach-bcm283x/Kconfig | 1 +
arch/arm/mach-bcm283x/include/mach/base.h | 7 +
arch/arm/mach-bcm283x/init.c | 52 +++
3 files changed, 60 insertions(+)
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 00419bf..bcb7f1d 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -36,6 +36,7 @@ config BCM2711_32B
select BCM2711
select ARMV7_LPAE
select CPU_V7A
+ select PHYS_64BIT
config BCM2711_64B
bool "Broadcom BCM2711 SoC 64-bit support"
diff --git a/arch/arm/mach-bcm283x/include/mach/base.h
b/arch/arm/mach-bcm283x/include/mach/base.h
index c4ae398..1d10dc9 100644
--- a/arch/arm/mach-bcm283x/include/mach/base.h
+++ b/arch/arm/mach-bcm283x/include/mach/base.h
@@ -6,6 +6,13 @@
#ifndef _BCM283x_BASE_H_
#define _BCM283x_BASE_H_
+#include
+
extern unsigned long rpi_bcm283x_base;
+#ifdef CONFIG_ARMV7_LPAE
+extern void *rpi4_phys_to_virt(phys_addr_t paddr);
+#define phys_to_virt(x) rpi4_phys_to_virt(x)
+#endif
+
#endif
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 6a748da..5d0d160 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -145,6 +145,58 @@ int mach_cpu_init(void)
}
#ifdef CONFIG_ARMV7_LPAE
+
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff80UL
+
+void *rpi4_phys_to_virt(phys_addr_t paddr)
+{
+ if (paddr >= BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS)
+ paddr = paddr - BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS +
+ BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT;
+ return (void *)(unsigned long)paddr;
+}
+
+static void set_section_phys(unsigned int section, phys_addr_t phys,
+enum dcache_option option)
+{
+ u64 *page_table = (u64 *)gd->arch.tlb_addr;
+ /* Need to set the access flag to not fault */
+ u64 value = TTB_SECT_AP | TTB_SECT_AF;
+
+ /* Add the page offset */
+ value |= (phys);
+
+ /* Add caching bits */
+ value |= option;
+
+ /* Set PTE */
+ page_table[section] = value;
+}
+
+static void rpi4_create_pcie_xhci_mapping(void)
+{
+ unsigned sect = BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT >> MMU_SECTION_SHIFT;
+ phys_addr_t phys_addr = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS;
+ unsigned int size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE;
+
+ while (size) {
+ set_section_phys(sect, phys_addr, DCACHE_OFF);
+ sect++;
+ phys_addr += MMU_SECTION_SIZE;
+ size -= MMU_SECTION_SIZE;
+ }
+}
+
+void arm_init_domains(void)
+{
+ /*
+* Hijack this function to prepare a mappings for the PCIe MMIO
+* region for the XHCI controller on RPi4 board.
+* This code is called before enabling the MMU in ARM 32bit mode.
+*/
+ rpi4_create_pcie_xhci_mapping();
+}
+
void enable_caches(void)
{
dcache_enable();
--
2.7.4
Re: [PATCH 0/7] Add support for CONFIG_API on RISC-V
On Mon, Apr 20, 2020 at 06:34:11PM -0400, mho...@freebsd.org wrote: > From: Mitchell Horne > > FreeBSD makes use of u-boot's CONFIG_API to provide a version of its > standard bootloader for embedded architectures. This series adds the > necessary support for the RISC-V architecture, along with some small > fixes to the API demo program for 64-bit systems. Adding in the RISC-V maintainer and EFI maintainer. I thought the intention was for OSes to use the EFI loader here, even for "embedded" ? Thanks! -- Tom signature.asc Description: PGP signature
[PATCH v1 07/10] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian.
From: Nicolas Saenz Julienne
Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
an in depth explanation and two fixes from Johannes Berg:
e7d4a95da86e0 "bitfield: fix *_encode_bits()",
37a3862e12382 "bitfield: add u8 helpers".
Signed-off-by: Nicolas Saenz Julienne
Signed-off-by: Sylwester Nawrocki
---
Changes since RFC:
- new patch.
---
include/linux/bitfield.h | 46 ++
1 file changed, 46 insertions(+)
diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
index 8b9d6ff..4964213 100644
--- a/include/linux/bitfield.h
+++ b/include/linux/bitfield.h
@@ -103,4 +103,50 @@
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
})
+extern void __compiletime_error("value doesn't fit into mask")
+__field_overflow(void);
+extern void __compiletime_error("bad bitfield mask")
+__bad_mask(void);
+static __always_inline u64 field_multiplier(u64 field)
+{
+ if ((field | (field - 1)) & ((field | (field - 1)) + 1))
+ __bad_mask();
+ return field & -field;
+}
+static __always_inline u64 field_mask(u64 field)
+{
+ return field / field_multiplier(field);
+}
+#define MAKE_OP(type,base,to,from) \
+static __always_inline __##type type##_encode_bits(base v, base field) \
+{ \
+ if (__builtin_constant_p(v) && (v & ~field_mask(field)))\
+ __field_overflow(); \
+ return to((v & field_mask(field)) * field_multiplier(field)); \
+} \
+static __always_inline __##type type##_replace_bits(__##type old, \
+ base val, base field) \
+{ \
+ return (old & ~to(field)) | type##_encode_bits(val, field); \
+} \
+static __always_inline void type##p_replace_bits(__##type *p, \
+ base val, base field) \
+{ \
+ *p = (*p & ~to(field)) | type##_encode_bits(val, field);\
+} \
+static __always_inline base type##_get_bits(__##type v, base field)\
+{ \
+ return (from(v) & field)/field_multiplier(field); \
+}
+#define __MAKE_OP(size)
\
+ MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \
+ MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \
+ MAKE_OP(u##size,u##size,,)
+MAKE_OP(u8,u8,,)
+__MAKE_OP(16)
+__MAKE_OP(32)
+__MAKE_OP(64)
+#undef __MAKE_OP
+#undef MAKE_OP
+
#endif
--
2.7.4
[PATCH v1 05/10] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit)
From: Marek Szyprowski
Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge.
Signed-off-by: Marek Szyprowski
---
Changes since RFC:
- none.
---
arch/arm/mach-bcm283x/init.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 4295356..6a748da 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -11,10 +11,15 @@
#include
#include
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x6UL
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x80UL
+
#ifdef CONFIG_ARM64
#include
-static struct mm_region bcm283x_mem_map[] = {
+#define MAX_MAP_MAX_ENTRIES (4)
+
+static struct mm_region bcm283x_mem_map[MAX_MAP_MAX_ENTRIES] = {
{
.virt = 0xUL,
.phys = 0xUL,
@@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = {
}
};
-static struct mm_region bcm2711_mem_map[] = {
+static struct mm_region bcm2711_mem_map[MAX_MAP_MAX_ENTRIES] = {
{
.virt = 0xUL,
.phys = 0xUL,
@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = {
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
+ .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+ .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+ .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
/* List terminator */
0,
}
@@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd)
{
int i;
- for (i = 0; i < 2; i++) {
+ for (i = 0; i < MAX_MAP_MAX_ENTRIES; i++) {
mem_map[i].virt = pd[i].virt;
mem_map[i].phys = pd[i].phys;
mem_map[i].size = pd[i].size;
--
2.7.4
[PATCH v1 08/10] pci: Add some PCI Express capability register offset definitions
Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Reviewed-by: Bin Meng Signed-off-by: Sylwester Nawrocki --- Changes since RFC: - ensure the entries are added in order, sorted by ascending address values. --- include/pci.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/pci.h b/include/pci.h index 5bf91a4..5307478 100644 --- a/include/pci.h +++ b/include/pci.h @@ -479,11 +479,17 @@ #define PCI_EXP_DEVCTL 8 /* Device Control */ #define PCI_EXP_DEVCTL_BCR_FLR0x8000 /* Bridge Configuration Retry / FLR */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_SLS0x000f /* Supported Link Speeds */ +#define PCI_EXP_LNKCAP_MLW0x03f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_DLLLARC0x0010 /* Data Link Layer Link Active Reporting Capable */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_CLS0x000f /* Current Link Speed */ +#define PCI_EXP_LNKSTA_NLW0x03f0 /* Negotiated Link Width */ +#define PCI_EXP_LNKSTA_NLW_SHIFT 4/* start of NLW mask in link status */ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */ +#define PCI_EXP_LNKCTL248 /* Link Control 2 */ /* Include the ID list */ -- 2.7.4
[PATCH v1 04/10] rpi4: shorten a mapping for the DRAM
From: Marek Szyprowski
Remove the overlap between DRAM and device's IO area.
Signed-off-by: Marek Szyprowski
---
Changes since RFC:
- none.
---
arch/arm/mach-bcm283x/init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 9966d6c..4295356 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = {
{
.virt = 0xUL,
.phys = 0xUL,
- .size = 0xfe00UL,
+ .size = 0xfc00UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
--
2.7.4
