Re: [PATCH 3/3] cmd: bootefi: Honor the address & size cells properties correctly
On 6/19/20 3:51 AM, Atish Patra wrote:
fdtdec_get_addr_size reads the uses a fixed value for address & size
cell properties which may not be correct always.
Use the auto variant of the function which automatically reads
#address-cells & #size-cells from parent and uses to read the "reg"
property.
Signed-off-by: Atish Patra
---
cmd/bootefi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 0f6d0f77507c..5f3fcce597de 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -190,8 +190,9 @@ static void efi_carve_out_dt_rsv(void *fdt)
subnode = fdt_first_subnode(fdt, nodeoffset);
while (subnode >= 0) {
/* check if this subnode has a reg property */
- addr = fdtdec_get_addr_size(fdt, subnode, "reg",
- (fdt_size_t *)&size);
+ addr = fdtdec_get_addr_size_auto_parent(fdt, nodeoffset,
+ subnode, "reg", 0,
+ (fdt_size_t *)&size, false);
On qemu_arm_defconfig: sizeof(fdt_size_t) = 4, sizeof(u64) = 8. So after
the call the upper four bytes of size will be random bytes from the stack.
Best regards
Heinrich
/*
* The /reserved-memory node may have children with
* a size instead of a reg property.
[PATCH 2/3] riscv: Use optimized version of fdtdec_get_addr_size_no_parent
fdtdec_get_addr_size_no_parent is not an optimized version if parent
node is already available with the caller.
Use fdtdec_get_addr_size_auto_parent to read the "reg" property
Signed-off-by: Atish Patra
---
arch/riscv/lib/fdt_fixup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
index 91524d9a5ae9..00b84dccbef0 100644
--- a/arch/riscv/lib/fdt_fixup.c
+++ b/arch/riscv/lib/fdt_fixup.c
@@ -44,7 +44,7 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
fdt_for_each_subnode(node, src, offset) {
name = fdt_get_name(src, node, NULL);
- addr = fdtdec_get_addr_size_auto_noparent(src, node,
+ addr = fdtdec_get_addr_size_auto_parent(src, offset, node,
"reg", 0, &size,
false);
if (addr == FDT_ADDR_T_NONE) {
--
2.24.0
[PATCH 0/3] Assorted fixes related to reserved memory
This series has few small assorted fixes related to reserved memory support in RISC-V and EFI. The series is rebased on top of the following series http://patchwork.ozlabs.org/project/uboot/patch/1591767391-2669-2-git-send-email-bmeng...@gmail.com/ Changes from v1->v2: 1. Rebased on top of the Bin's series. Dropped the fix generic fdtdec code. 2. Added bootefi fix. ption-prefix PATCH v2 Atish Patra (3): riscv: Do not return error if reserved node already exists riscv: Use optimized version of fdtdec_get_addr_size_no_parent cmd: bootefi: Honor the address & size cells properties correctly arch/riscv/lib/fdt_fixup.c | 4 ++-- cmd/bootefi.c | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) -- 2.24.0
[PATCH 3/3] cmd: bootefi: Honor the address & size cells properties correctly
fdtdec_get_addr_size reads the uses a fixed value for address & size
cell properties which may not be correct always.
Use the auto variant of the function which automatically reads
#address-cells & #size-cells from parent and uses to read the "reg"
property.
Signed-off-by: Atish Patra
---
cmd/bootefi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 0f6d0f77507c..5f3fcce597de 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -190,8 +190,9 @@ static void efi_carve_out_dt_rsv(void *fdt)
subnode = fdt_first_subnode(fdt, nodeoffset);
while (subnode >= 0) {
/* check if this subnode has a reg property */
- addr = fdtdec_get_addr_size(fdt, subnode, "reg",
- (fdt_size_t *)&size);
+ addr = fdtdec_get_addr_size_auto_parent(fdt, nodeoffset,
+ subnode, "reg", 0,
+ (fdt_size_t *)&size, false);
/*
* The /reserved-memory node may have children with
* a size instead of a reg property.
--
2.24.0
[PATCH 1/3] riscv: Do not return error if reserved node already exists
Not all errors are fatal. If a reserved memory node already exists in the
destination device tree, we can continue to boot without failing.
Signed-off-by: Atish Patra
---
arch/riscv/lib/fdt_fixup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
index 6db48ad04a56..91524d9a5ae9 100644
--- a/arch/riscv/lib/fdt_fixup.c
+++ b/arch/riscv/lib/fdt_fixup.c
@@ -62,7 +62,7 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
pmp_mem.end = addr + size - 1;
err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem,
&phandle);
- if (err < 0) {
+ if (err < 0 && err != FDT_ERR_EXISTS) {
printf("failed to add reserved memory: %d\n", err);
return err;
}
--
2.24.0
[PATCH] ARM: dts: imx6qdl-sabreauto: Fix AR8031 phy-mode
As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode)
the correct phy-mode should be "rgmii-id", so fix it accordingly
to fix the Ethernet regression.
This problem has been exposed by commit:
commit 13114f38e2ccea9386726d8b9831dfc310589548
Author: Vladimir Oltean
Date: Thu May 7 00:11:51 2020 +0200
phy: atheros: Explicitly disable RGMII delays
To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.
If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.
Signed-off-by: Vladimir Oltean
Acked-by: Joe Hershberger
Fix the phy-mode accordingly to fix the regression.
Signed-off-by: Fabio Estevam
---
arch/arm/dts/imx6qdl-sabreauto.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx6qdl-sabreauto.dtsi
b/arch/arm/dts/imx6qdl-sabreauto.dtsi
index a6dc5c42c6..28a7fdb0f1 100644
--- a/arch/arm/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/dts/imx6qdl-sabreauto.dtsi
@@ -281,7 +281,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
--
2.17.1
[PATCH v3 3/4] ARM: dts: imx6qdl-sr-som: Sync with kernel 5.8-rc1
Sync the device tree with 5.8-rc1.
It basically contains the following extra kernel commit:
commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09
Author: Russell King
Date: Wed Apr 15 16:44:17 2020 +0100
ARM: dts: imx6-sr-som: add ethernet PHY configuration
Add ethernet PHY configuration ahead of removing the quirk that
configures the clocking mode for the PHY. The RGMII delay is
already set correctly.
Signed-off-by: Russell King
Reviewed-by: Fabio Estevam
Signed-off-by: Shawn Guo
, which passes the 'qca,clk-out-frequency' property and it is important
to specify the correct frequency generated by the AR8035.
Signed-off-by: Fabio Estevam
Tested-by: Tom Rini
---
Changes since v2:
- Change from AR8031 to AR8035, as cubox uses AR8035
arch/arm/dts/imx6qdl-sr-som.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/dts/imx6qdl-sr-som.dtsi b/arch/arm/dts/imx6qdl-sr-som.dtsi
index 6d7f6b9035..b06577808f 100644
--- a/arch/arm/dts/imx6qdl-sr-som.dtsi
+++ b/arch/arm/dts/imx6qdl-sr-som.dtsi
@@ -53,10 +53,21 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
+ phy-handle = <&phy>;
phy-mode = "rgmii-id";
phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@0 {
+ reg = <0>;
+ qca,clk-out-frequency = <12500>;
+ };
+ };
};
&iomuxc {
--
2.17.1
[PATCH v3 2/4] net: fec: Allow the PHY node to be retrieved
As we move towards driver model, it is required to let the FEC driver
know how to properly deal with an Ethernet PHY subnode in the device tree.
For example:
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-handle = <&phy>;
phy-mode = "rgmii-id";
phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@0 {
reg = <0>;
qca,clk-out-frequency = <12500>;
};
};
};
Currently the PHY node pointer is incorrectly associated with the
Ethernel controller instead of the PHY node itself.
This causes the PHY properties, such as "qca,clk-out-frequency" in
the example above to not get parsed.
Fix this problem by populating the phy_of_node node.
Suggested-by: Vladimir Oltean
Signed-off-by: Fabio Estevam
Tested-by: Tom Rini
---
Changes since v2:
- None
drivers/net/fec_mxc.c | 7 +--
drivers/net/fec_mxc.h | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 9ae2db033e..992180df86 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1294,7 +1294,7 @@ static const struct eth_ops fecmxc_ops = {
.read_rom_hwaddr= fecmxc_read_rom_hwaddr,
};
-static int device_get_phy_addr(struct udevice *dev)
+static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
{
struct ofnode_phandle_args phandle_args;
int reg;
@@ -1305,6 +1305,8 @@ static int device_get_phy_addr(struct udevice *dev)
return -ENODEV;
}
+ priv->phy_of_node = phandle_args.node;
+
reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
return reg;
@@ -1315,7 +1317,7 @@ static int fec_phy_init(struct fec_priv *priv, struct
udevice *dev)
struct phy_device *phydev;
int addr;
- addr = device_get_phy_addr(dev);
+ addr = device_get_phy_addr(priv, dev);
#ifdef CONFIG_FEC_MXC_PHYADDR
addr = CONFIG_FEC_MXC_PHYADDR;
#endif
@@ -1325,6 +1327,7 @@ static int fec_phy_init(struct fec_priv *priv, struct
udevice *dev)
return -ENODEV;
priv->phydev = phydev;
+ priv->phydev->node = priv->phy_of_node;
phy_config(phydev);
return 0;
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 0e8f08a51a..659d62646f 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -250,6 +250,7 @@ struct fec_priv {
struct mii_dev *bus;
#ifdef CONFIG_PHYLIB
struct phy_device *phydev;
+ ofnode phy_of_node;
#else
int phy_id;
int (*mii_postcall)(int);
--
2.17.1
[PATCH v3 4/4] mx6cuboxi: Convert to DM_ETH
Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet
Driver Model.
This also brings the benefit of restoring Ethernet functionality.
Reported-by: Tom Rini
Signed-off-by: Fabio Estevam
Tested-by: Tom Rini
---
Changes since v2:
- Removed extra Signed-off-by
board/solidrun/mx6cuboxi/mx6cuboxi.c | 134 ---
configs/mx6cuboxi_defconfig | 3 +
include/configs/mx6cuboxi.h | 6 --
3 files changed, 20 insertions(+), 123 deletions(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 94707bccb2..59e8b1dca1 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -17,7 +17,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -33,8 +32,6 @@
#include
#include
#include
-#include
-#include
#include
#include
#include
@@ -52,16 +49,6 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
#define USB_H1_VBUSIMX_GPIO_NR(1, 0)
enum board_type {
@@ -237,110 +224,6 @@ int board_mmc_init(bd_t *bis)
return 0;
}
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* AR8035 reset */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- /* AR8035 interrupt */
- IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* GPIO16 -> AR8035 25MHz */
- IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-};
-
-static void setup_iomux_enet(void)
-{
- struct gpio_desc desc;
- int ret;
-
- SETUP_IOMUX_PADS(enet_pads);
-
- ret = dm_gpio_lookup_name("GPIO4_15", &desc);
- if (ret) {
- printf("%s: phy reset lookup failed\n", __func__);
- return;
- }
-
- ret = dm_gpio_request(&desc, "phy-reset");
- if (ret) {
- printf("%s: phy reset request failed\n", __func__);
- return;
- }
-
- gpio_direction_output(ETH_PHY_RESET, 0);
- mdelay(10);
- gpio_set_value(ETH_PHY_RESET, 1);
- udelay(100);
-
- gpio_free_list_nodev(&desc, 1);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
-#define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4))
-
-int board_eth_init(bd_t *bis)
-{
- struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct mii_dev *bus;
- struct phy_device *phydev;
-
- int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
- if (ret)
- return ret;
-
- /* set gpr1[ENET_CLK_SEL] */
- setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
-
- setup_iomux_enet();
-
- bus = fec_get_miibus(IMX_FEC_BASE, -1);
- if (!bus)
- return -EINVAL;
-
- phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
- if (!phydev) {
- ret = -EINVAL;
-
[PATCH v3 1/4] phy: atheros: ar8035: Fix clock output calculation
The clock ouput frequency is calculated incorrectly for AR8035 due to
wrong masking of priv->clk_25m_reg and priv->clk_25m_mask.
This same issue has been already fixed in the kernel by:
commit b1f4c209d84057b6d40b939b6e4404854271d797
Author: Oleksij Rempel
Date: Wed Apr 1 11:57:32 2020 +0200
net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035
The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
for the values that comprise the fields, not zero-bits-set.
This patch fixes the clock frequency configuration for ATH8030 and
ATH8035 Atheros PHYs by removing the erroneous "~".
To reproduce this bug, configure the PHY with the device tree binding
"qca,clk-out-frequency" and remove the machine specific PHY fixups.
Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding")
Signed-off-by: Oleksij Rempel
Reported-by: Russell King
Reviewed-by: Russell King
Tested-by: Russell King
Signed-off-by: David S. Miller
Apply the same fix in the U-Boot driver.
Tested on a i.MX6 Hummingboard.
Signed-off-by: Fabio Estevam
Reviewed-by: Michael Walle
Tested-by: Tom Rini
---
Changes since v2:
- None
drivers/net/phy/atheros.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 13f7275d17..f922fecd6b 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -275,11 +275,10 @@ static int ar803x_of_init(struct phy_device *phydev)
* Fixup for the AR8035 which only has two bits. The two
* remaining bits map to the same frequencies.
*/
- if (phydev->drv->uid == AR8035_PHY_ID) {
- u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK;
- priv->clk_25m_mask &= ~clear;
- priv->clk_25m_reg &= ~clear;
+ if (phydev->drv->uid == AR8035_PHY_ID) {
+ priv->clk_25m_reg &= AR8035_CLK_25M_MASK;
+ priv->clk_25m_mask &= AR8035_CLK_25M_MASK;
}
}
--
2.17.1
Re: [PATCH v3 2/4] arm: Remove d2net_v2 board
On Fri, Jun 19, 2020 at 12:02:17AM +0200, Simon Guinot wrote: > On Thu, Jun 18, 2020 at 11:15:14PM +0530, Jagan Teki wrote: > Hi Jagan, > > > This board has not been converted to CONFIG_DM by the deadline. > > Is that possible to negociate a new deadline ? Well, when will you be able to spend some time bringing the platform up to current standards? Doing a quick build for net2big_v2 I see: +(net2big_v2) = WARNING == +(net2big_v2) This board does not use CONFIG_DM. CONFIG_DM will be +(net2big_v2) compulsory starting with the v2020.01 release. +(net2big_v2) Failure to update may result in board removal. +(net2big_v2) See doc/driver-model/migration.rst for more info. +(net2big_v2) +(net2big_v2) This board does not use CONFIG_DM_USB. Please update +(net2big_v2) the board to use CONFIG_DM_USB before the v2019.07 release. +(net2big_v2) Failure to update by the deadline may result in board removal. +(net2big_v2) This board does use CONFIG_MVSATA_IDE which is not +(net2big_v2) ported to driver-model (DM) yet. Please update the storage +(net2big_v2) controller driver to use CONFIG_AHCI before the v2019.07 +(net2big_v2) release. +(net2big_v2) This board does not use CONFIG_DM_SPI_FLASH. Please update +(net2big_v2) the board to use CONFIG_SPI_FLASH before the v2019.07 release. +(net2big_v2) This board does not use CONFIG_DM_ETH (Driver Model +(net2big_v2) for Ethernet drivers). Please update the board to use +(net2big_v2) CONFIG_DM_ETH before the v2020.07 release. Failure to +(net2big_v2) update by the deadline may result in board removal. So there's a lot of stuff that needs updating. Conversion to CONFIG_DM is what you'll need to then convert SPI, ETH and USB to use DM and the IDE driver also needs attention and conversion. Thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 2/4] arm: Remove d2net_v2 board
On Thu, Jun 18, 2020 at 11:15:14PM +0530, Jagan Teki wrote: Hi Jagan, > This board has not been converted to CONFIG_DM by the deadline. Is that possible to negociate a new deadline ? Thanks in advance. Simon > > Remove it. > > Cc: Simon Guinot > Signed-off-by: Jagan Teki > --- > Changes for v3: > - new patch > > arch/arm/mach-kirkwood/Kconfig | 4 - > board/LaCie/net2big_v2/Kconfig | 12 -- > board/LaCie/net2big_v2/MAINTAINERS | 7 - > board/LaCie/net2big_v2/Makefile | 13 -- > board/LaCie/net2big_v2/kwbimage.cfg | 149 > board/LaCie/net2big_v2/net2big_v2.c | 257 > board/LaCie/net2big_v2/net2big_v2.h | 28 --- > configs/d2net_v2_defconfig | 53 -- > configs/net2big_v2_defconfig| 53 -- > include/configs/lacie_kw.h | 152 > 10 files changed, 728 deletions(-) > delete mode 100644 board/LaCie/net2big_v2/Kconfig > delete mode 100644 board/LaCie/net2big_v2/MAINTAINERS > delete mode 100644 board/LaCie/net2big_v2/Makefile > delete mode 100644 board/LaCie/net2big_v2/kwbimage.cfg > delete mode 100644 board/LaCie/net2big_v2/net2big_v2.c > delete mode 100644 board/LaCie/net2big_v2/net2big_v2.h > delete mode 100644 configs/d2net_v2_defconfig > delete mode 100644 configs/net2big_v2_defconfig > delete mode 100644 include/configs/lacie_kw.h > > diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig > index ae44cb665e..ad6aef45bf 100644 > --- a/arch/arm/mach-kirkwood/Kconfig > +++ b/arch/arm/mach-kirkwood/Kconfig > @@ -35,9 +35,6 @@ config TARGET_KM_KIRKWOOD > bool "KM Kirkwood Board" > select VENDOR_KM > > -config TARGET_NET2BIG_V2 > - bool "LaCie 2Big Network v2 NAS Board" > - > config TARGET_NETSPACE_V2 > bool "LaCie netspace_v2 Board" > > @@ -80,7 +77,6 @@ source "board/cloudengines/pogo_e02/Kconfig" > source "board/d-link/dns325/Kconfig" > source "board/iomega/iconnect/Kconfig" > source "board/keymile/Kconfig" > -source "board/LaCie/net2big_v2/Kconfig" > source "board/LaCie/netspace_v2/Kconfig" > source "board/raidsonic/ib62x0/Kconfig" > source "board/Seagate/dockstar/Kconfig" > diff --git a/board/LaCie/net2big_v2/Kconfig b/board/LaCie/net2big_v2/Kconfig > deleted file mode 100644 > index ba460dba45..00 > --- a/board/LaCie/net2big_v2/Kconfig > +++ /dev/null > @@ -1,12 +0,0 @@ > -if TARGET_NET2BIG_V2 > - > -config SYS_BOARD > - default "net2big_v2" > - > -config SYS_VENDOR > - default "LaCie" > - > -config SYS_CONFIG_NAME > - default "lacie_kw" > - > -endif > diff --git a/board/LaCie/net2big_v2/MAINTAINERS > b/board/LaCie/net2big_v2/MAINTAINERS > deleted file mode 100644 > index 8fec70315f..00 > --- a/board/LaCie/net2big_v2/MAINTAINERS > +++ /dev/null > @@ -1,7 +0,0 @@ > -NET2BIG_V2 BOARD > -M: Simon Guinot > -S: Maintained > -F: board/LaCie/net2big_v2/ > -F: include/configs/lacie_kw.h > -F: configs/d2net_v2_defconfig > -F: configs/net2big_v2_defconfig > diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile > deleted file mode 100644 > index 3d12b72812..00 > --- a/board/LaCie/net2big_v2/Makefile > +++ /dev/null > @@ -1,13 +0,0 @@ > -# SPDX-License-Identifier: GPL-2.0+ > -# > -# Copyright (C) 2011 Simon Guinot > -# > -# Based on Kirkwood support: > -# (C) Copyright 2009 > -# Marvell Semiconductor > -# Written-by: Prafulla Wadaskar > - > -obj-y:= net2big_v2.o ../common/common.o > -ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),) > -obj-y+= ../common/cpld-gpio-bus.o > -endif > diff --git a/board/LaCie/net2big_v2/kwbimage.cfg > b/board/LaCie/net2big_v2/kwbimage.cfg > deleted file mode 100644 > index 3897a1197a..00 > --- a/board/LaCie/net2big_v2/kwbimage.cfg > +++ /dev/null > @@ -1,149 +0,0 @@ > -# SPDX-License-Identifier: GPL-2.0+ > -# > -# Copyright (C) 2011 Simon Guinot > -# > -# Based on Kirkwood support: > -# (C) Copyright 2009 > -# Marvell Semiconductor > -# Written-by: Prafulla Wadaskar > -# Refer doc/README.kwbimage for more details about how-to configure > -# and create kirkwood boot image > -# > - > -# Boot Media configurations > -BOOT_FROMspi # Boot from SPI flash > - > -# SOC registers configuration using bootrom header extension > -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed > - > -# Configure RGMII-0 interface pad voltage to 1.8V > -DATA 0xFFD100e0 0x1B1B1B9B > - > -#Dram initalization for SINGLE x16 CL=5 @ 400MHz > -DATA 0xFFD01400 0x43000C30 # DDR Configuration register > -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) > -# bit23-14: zero > -# bit24: 1= enable exit self refresh mode on DDR access > -# bit25: 1 required > -# bit29-26: zero > -# bit31-30: 01 > - > -DATA 0xFFD01404 0x38743000 # DDR Controller Control Low > -# bit 4:0=addr/cmd in smame cycle > -# bit 5:0=clk is driven during self refresh, we don't care for APX > -# bit 6:0=use recommended falling edge
Re: [PATCH 4/5] pinctrl: renesas: Add R8A774A1 PFC tables
On Thu, Jun 18, 2020 at 4:51 PM Marek Vasut wrote: > > On 6/18/20 11:14 PM, Adam Ford wrote: > > Add R8A774A1 PFC tables based on Renesas' repo based on 2018.09. > > It seems linux/next uses the same file for 7796 and 774a1 , can we do > the same for U-Boot ? That looks encouraging. I'll try that. It makes sense since the 774a1 is the commercial version of the automotive 7796 if I understand it correctly. adam
Re: [PATCH 4/5] pinctrl: renesas: Add R8A774A1 PFC tables
On 6/18/20 11:14 PM, Adam Ford wrote: > Add R8A774A1 PFC tables based on Renesas' repo based on 2018.09. It seems linux/next uses the same file for 7796 and 774a1 , can we do the same for U-Boot ?
Re: GPIO request failures for Renesas rcar-gen3
On 6/18/20 11:46 PM, Adam Ford wrote: [...] >>> regulator 0 [ + ] fixed regulator |-- regulator0 >>> regulator 1 [ + ] fixed regulator |-- regulator1 >>> regulator 2 [ ] fixed regulator |-- regulator_audio >>> regulator 3 [ ] fixed regulator |-- regulator-lcd >>> regulator 4 [ ] fixed regulator |-- regulator-lcd-reset >>> regulator 5 [ ] fixed regulator |-- regulator_camera >>> regulator 6 [ + ] gpio regulator|-- regulator-vccq-sdhi0 >>> clk 12 [ ] fixed_rate_clock |-- x302-clock >>> clk 13 [ ] fixed_rate_clock `-- x304-clock >> >> Isn't the PFC driver missing here ? > > That was it. Thank you! > > I'll have to fix the pfc and submit patch V2 to fix that. > > I appreciate your quick response. It's working now That's good to hear.
Re: [PATCH v2 4/4] mx6cuboxi: Convert to DM_ETH
On 18.06.20 23:25, Fabio Estevam wrote: > On Thu, Jun 18, 2020 at 6:16 PM Fabio Estevam wrote: >> >> Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet >> Driver Model. >> >> This also brings the benefit of restoring Ethernet functionality. >> >> Reported-by: Tom Rini >> Signed-off-by: Fabio Estevam >> >> Signed-off-by: Fabio Estevam >> Tested-by: Tom Rini > > Sorry, there are two Signed-off-by's from me and an extra blank line. > > Maybe Stefano could fix it while applying it? > > If not, I can send a v3. > Not needed, I fix by merging. Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
Re: GPIO request failures for Renesas rcar-gen3
On Thu, Jun 18, 2020 at 4:33 PM Marek Vasut wrote: > > On 6/18/20 11:20 PM, Adam Ford wrote: > > Hi, > > [...] > > >> Can you provide 'dm tree' output ? > > > > => dm tree > > Class Index Probed DriverName > > --- > > root 0 [ + ] root_driver root_driver > > clk 0 [ ] fixed_rate_clock |-- audio_clk_a > > clk 1 [ ] fixed_rate_clock |-- audio_clk_b > > clk 2 [ ] fixed_rate_clock |-- audio_clk_c > > clk 3 [ ] fixed_rate_clock |-- can > > clk 4 [ + ] fixed_rate_clock |-- extal > > clk 5 [ + ] fixed_rate_clock |-- extalr > > clk 6 [ ] fixed_rate_clock |-- pcie_bus > > firmware 0 [ ] psci |-- psci > > clk 7 [ ] fixed_rate_clock |-- scif > > simple_bus0 [ + ] generic_simple_bus|-- soc > > gpio 0 [ ] rcar-gpio | |-- gpio@e605 > > gpio 1 [ ] rcar-gpio | |-- gpio@e6051000 > > gpio 2 [ + ] rcar-gpio | |-- gpio@e6052000 > > gpio 3 [ ] rcar-gpio | |-- gpio@e6053000 > > gpio 4 [ ] rcar-gpio | |-- gpio@e6054000 > > gpio 5 [ ] rcar-gpio | |-- gpio@e6055000 > > gpio 6 [ + ] rcar-gpio | |-- gpio@e6055400 > > gpio 7 [ ] rcar-gpio | |-- gpio@e6055800 > > clk 8 [ + ] clk_r8a774a1 | |-- > > clock-controller@e615 > > i2c 0 [ ] i2c_rcar | |-- i2c@e650 > > i2c 1 [ ] i2c_rcar | |-- i2c@e651 > > i2c 2 [ ] i2c_rcar | |-- i2c@e66d8000 > > i2c 3 [ ] i2c_rcar | |-- i2c@e66e > > eth 0 [ ] ravb | |-- ethernet@e680 > > serial0 [ ] serial_sh | |-- serial@e6e6 > > serial1 [ + ] serial_sh | |-- serial@e6e88000 > > serial2 [ ] serial_sh | |-- serial@e6f3 > > usb 0 [ ] ehci_generic | |-- usb@ee080100 > > usb 1 [ ] ehci_generic | |-- usb@ee0a0100 > > phy 0 [ ] rcar-gen3-phy | |-- usb-phy@ee080200 > > phy 1 [ ] rcar-gen3-phy | |-- usb-phy@ee0a0200 > > mmc 0 [ + ] renesas-sdhi | |-- sd@ee10 > > blk 0 [ ] mmc_blk | | `-- > > s...@ee10.blk > > mmc 1 [ + ] renesas-sdhi | |-- sd@ee16 > > blk 1 [ + ] mmc_blk | | `-- > > s...@ee16.blk > > pci 0 [ ] rcar_gen3_pcie| |-- pcie@fe00 > > pci 1 [ ] rcar_gen3_pcie| `-- pcie@ee80 > > clk 9 [ ] fixed_rate_clock |-- usb3s0 > > clk 10 [ ] fixed_rate_clock |-- usb_extal > > clk 11 [ ] fixed_rate_clock |-- osc_32k > > regulator 0 [ + ] fixed regulator |-- regulator0 > > regulator 1 [ + ] fixed regulator |-- regulator1 > > regulator 2 [ ] fixed regulator |-- regulator_audio > > regulator 3 [ ] fixed regulator |-- regulator-lcd > > regulator 4 [ ] fixed regulator |-- regulator-lcd-reset > > regulator 5 [ ] fixed regulator |-- regulator_camera > > regulator 6 [ + ] gpio regulator|-- regulator-vccq-sdhi0 > > clk 12 [ ] fixed_rate_clock |-- x302-clock > > clk 13 [ ] fixed_rate_clock `-- x304-clock > > Isn't the PFC driver missing here ? That was it. Thank you! I'll have to fix the pfc and submit patch V2 to fix that. I appreciate your quick response. It's working now adam
Re: GPIO request failures for Renesas rcar-gen3
On 6/18/20 11:20 PM, Adam Ford wrote: Hi, [...] >> Can you provide 'dm tree' output ? > > => dm tree > Class Index Probed DriverName > --- > root 0 [ + ] root_driver root_driver > clk 0 [ ] fixed_rate_clock |-- audio_clk_a > clk 1 [ ] fixed_rate_clock |-- audio_clk_b > clk 2 [ ] fixed_rate_clock |-- audio_clk_c > clk 3 [ ] fixed_rate_clock |-- can > clk 4 [ + ] fixed_rate_clock |-- extal > clk 5 [ + ] fixed_rate_clock |-- extalr > clk 6 [ ] fixed_rate_clock |-- pcie_bus > firmware 0 [ ] psci |-- psci > clk 7 [ ] fixed_rate_clock |-- scif > simple_bus0 [ + ] generic_simple_bus|-- soc > gpio 0 [ ] rcar-gpio | |-- gpio@e605 > gpio 1 [ ] rcar-gpio | |-- gpio@e6051000 > gpio 2 [ + ] rcar-gpio | |-- gpio@e6052000 > gpio 3 [ ] rcar-gpio | |-- gpio@e6053000 > gpio 4 [ ] rcar-gpio | |-- gpio@e6054000 > gpio 5 [ ] rcar-gpio | |-- gpio@e6055000 > gpio 6 [ + ] rcar-gpio | |-- gpio@e6055400 > gpio 7 [ ] rcar-gpio | |-- gpio@e6055800 > clk 8 [ + ] clk_r8a774a1 | |-- > clock-controller@e615 > i2c 0 [ ] i2c_rcar | |-- i2c@e650 > i2c 1 [ ] i2c_rcar | |-- i2c@e651 > i2c 2 [ ] i2c_rcar | |-- i2c@e66d8000 > i2c 3 [ ] i2c_rcar | |-- i2c@e66e > eth 0 [ ] ravb | |-- ethernet@e680 > serial0 [ ] serial_sh | |-- serial@e6e6 > serial1 [ + ] serial_sh | |-- serial@e6e88000 > serial2 [ ] serial_sh | |-- serial@e6f3 > usb 0 [ ] ehci_generic | |-- usb@ee080100 > usb 1 [ ] ehci_generic | |-- usb@ee0a0100 > phy 0 [ ] rcar-gen3-phy | |-- usb-phy@ee080200 > phy 1 [ ] rcar-gen3-phy | |-- usb-phy@ee0a0200 > mmc 0 [ + ] renesas-sdhi | |-- sd@ee10 > blk 0 [ ] mmc_blk | | `-- s...@ee10.blk > mmc 1 [ + ] renesas-sdhi | |-- sd@ee16 > blk 1 [ + ] mmc_blk | | `-- s...@ee16.blk > pci 0 [ ] rcar_gen3_pcie| |-- pcie@fe00 > pci 1 [ ] rcar_gen3_pcie| `-- pcie@ee80 > clk 9 [ ] fixed_rate_clock |-- usb3s0 > clk 10 [ ] fixed_rate_clock |-- usb_extal > clk 11 [ ] fixed_rate_clock |-- osc_32k > regulator 0 [ + ] fixed regulator |-- regulator0 > regulator 1 [ + ] fixed regulator |-- regulator1 > regulator 2 [ ] fixed regulator |-- regulator_audio > regulator 3 [ ] fixed regulator |-- regulator-lcd > regulator 4 [ ] fixed regulator |-- regulator-lcd-reset > regulator 5 [ ] fixed regulator |-- regulator_camera > regulator 6 [ + ] gpio regulator|-- regulator-vccq-sdhi0 > clk 12 [ ] fixed_rate_clock |-- x302-clock > clk 13 [ ] fixed_rate_clock `-- x304-clock Isn't the PFC driver missing here ?
Re: GPIO request failures for Renesas rcar-gen3
On Thu, Jun 18, 2020 at 4:20 PM Adam Ford wrote: > > On Thu, Jun 18, 2020 at 4:00 PM Marek Vasut wrote: > > > > On 6/18/20 10:33 PM, Adam Ford wrote: > > > I am trying to port U-Boot to a new product based on a Renesas RZ/G2M > > > (rcar-gen3). We're have this working with Renesas' version from > > > 2018.09, but I am trying to integrate it with U-Boot 2020.07-rc4 > > > > > > What's happening is that it seems like all GPIO are failing to be > > > requested, so things like regulator-gpio fail, reset-gpios, etc. all > > > return errors. > > > > > > The dm tree and gpio status commands all appear to show gpio banks are > > > enumerating, but since nothing can use the GPIO's it seems like the > > > common thread is the gpio driver for the rcar3. > > > > > > I was hoping someone might have some thoughts of things I could try or > > > investigate. In order to properly set the voltage for the MMC card, I > > > need "regulator-gpio" to operate correctly. > > > > Note that RZ/G2M is not supported by mainline U-Boot. > > > > Also note that the GPIO driver and PFC drivers are working together, > > grep for sh_pfc_config_mux_for_gpio(), so unless both work and probed, > > the GPIO driver will likely not work. > > I just sent a series [1] for review for porting the PFC, clock drivers > and MMC over. > > [1] - > https://patchwork.ozlabs.org/project/uboot/patch/20200618211444.391556-2-aford...@gmail.com/ > I already submitted the board device tree stuff to the Linux community and I am waiting for feedback to finalize it before attempting to post here. If it's helpful, I can post the rest of my series with the board device tree and board files instead of waiting. > It looks to me like the gpio driver looks for "rcar-gen3-gpio" which > is included in the SoC's DTSI file. I looked in Renesas' upstream > repo, but I didn't find anything unique in the gpio driver, but maybe > there is something in the gpio driver I missed. > > > > > Can you provide 'dm tree' output ? > > => dm tree > Class Index Probed DriverName > --- > root 0 [ + ] root_driver root_driver > clk 0 [ ] fixed_rate_clock |-- audio_clk_a > clk 1 [ ] fixed_rate_clock |-- audio_clk_b > clk 2 [ ] fixed_rate_clock |-- audio_clk_c > clk 3 [ ] fixed_rate_clock |-- can > clk 4 [ + ] fixed_rate_clock |-- extal > clk 5 [ + ] fixed_rate_clock |-- extalr > clk 6 [ ] fixed_rate_clock |-- pcie_bus > firmware 0 [ ] psci |-- psci > clk 7 [ ] fixed_rate_clock |-- scif > simple_bus0 [ + ] generic_simple_bus|-- soc > gpio 0 [ ] rcar-gpio | |-- gpio@e605 > gpio 1 [ ] rcar-gpio | |-- gpio@e6051000 > gpio 2 [ + ] rcar-gpio | |-- gpio@e6052000 > gpio 3 [ ] rcar-gpio | |-- gpio@e6053000 > gpio 4 [ ] rcar-gpio | |-- gpio@e6054000 > gpio 5 [ ] rcar-gpio | |-- gpio@e6055000 > gpio 6 [ + ] rcar-gpio | |-- gpio@e6055400 > gpio 7 [ ] rcar-gpio | |-- gpio@e6055800 > clk 8 [ + ] clk_r8a774a1 | |-- > clock-controller@e615 > i2c 0 [ ] i2c_rcar | |-- i2c@e650 > i2c 1 [ ] i2c_rcar | |-- i2c@e651 > i2c 2 [ ] i2c_rcar | |-- i2c@e66d8000 > i2c 3 [ ] i2c_rcar | |-- i2c@e66e > eth 0 [ ] ravb | |-- ethernet@e680 > serial0 [ ] serial_sh | |-- serial@e6e6 > serial1 [ + ] serial_sh | |-- serial@e6e88000 > serial2 [ ] serial_sh | |-- serial@e6f3 > usb 0 [ ] ehci_generic | |-- usb@ee080100 > usb 1 [ ] ehci_generic | |-- usb@ee0a0100 > phy 0 [ ] rcar-gen3-phy | |-- usb-phy@ee080200 > phy 1 [ ] rcar-gen3-phy | |-- usb-phy@ee0a0200 > mmc 0 [ + ] renesas-sdhi | |-- sd@ee10 > blk 0 [ ] mmc_blk | | `-- s...@ee10.blk > mmc 1 [ + ] renesas-sdhi | |-- sd@ee16 > blk 1 [ + ] mmc_blk | | `-- s...@ee16.blk > pci 0 [ ] rcar_gen3_pcie| |-- pcie@fe00 > pci 1 [ ] rcar_gen3_pcie| `-- pcie@ee80 > clk 9 [ ] fixed_rate_clock |-- usb3s0 > clk 10 [ ] fixed_rate_clock |-- usb_extal > clk 11 [ ] fixed_rate_clock |-- osc_32k > regulator 0 [ + ] fix
Re: [PATCH v2 4/4] mx6cuboxi: Convert to DM_ETH
On Thu, Jun 18, 2020 at 6:16 PM Fabio Estevam wrote: > > Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet > Driver Model. > > This also brings the benefit of restoring Ethernet functionality. > > Reported-by: Tom Rini > Signed-off-by: Fabio Estevam > > Signed-off-by: Fabio Estevam > Tested-by: Tom Rini Sorry, there are two Signed-off-by's from me and an extra blank line. Maybe Stefano could fix it while applying it? If not, I can send a v3.
Re: GPIO request failures for Renesas rcar-gen3
On Thu, Jun 18, 2020 at 4:00 PM Marek Vasut wrote: > > On 6/18/20 10:33 PM, Adam Ford wrote: > > I am trying to port U-Boot to a new product based on a Renesas RZ/G2M > > (rcar-gen3). We're have this working with Renesas' version from > > 2018.09, but I am trying to integrate it with U-Boot 2020.07-rc4 > > > > What's happening is that it seems like all GPIO are failing to be > > requested, so things like regulator-gpio fail, reset-gpios, etc. all > > return errors. > > > > The dm tree and gpio status commands all appear to show gpio banks are > > enumerating, but since nothing can use the GPIO's it seems like the > > common thread is the gpio driver for the rcar3. > > > > I was hoping someone might have some thoughts of things I could try or > > investigate. In order to properly set the voltage for the MMC card, I > > need "regulator-gpio" to operate correctly. > > Note that RZ/G2M is not supported by mainline U-Boot. > > Also note that the GPIO driver and PFC drivers are working together, > grep for sh_pfc_config_mux_for_gpio(), so unless both work and probed, > the GPIO driver will likely not work. I just sent a series [1] for review for porting the PFC, clock drivers and MMC over. [1] - https://patchwork.ozlabs.org/project/uboot/patch/20200618211444.391556-2-aford...@gmail.com/ It looks to me like the gpio driver looks for "rcar-gen3-gpio" which is included in the SoC's DTSI file. I looked in Renesas' upstream repo, but I didn't find anything unique in the gpio driver, but maybe there is something in the gpio driver I missed. > > Can you provide 'dm tree' output ? => dm tree Class Index Probed DriverName --- root 0 [ + ] root_driver root_driver clk 0 [ ] fixed_rate_clock |-- audio_clk_a clk 1 [ ] fixed_rate_clock |-- audio_clk_b clk 2 [ ] fixed_rate_clock |-- audio_clk_c clk 3 [ ] fixed_rate_clock |-- can clk 4 [ + ] fixed_rate_clock |-- extal clk 5 [ + ] fixed_rate_clock |-- extalr clk 6 [ ] fixed_rate_clock |-- pcie_bus firmware 0 [ ] psci |-- psci clk 7 [ ] fixed_rate_clock |-- scif simple_bus0 [ + ] generic_simple_bus|-- soc gpio 0 [ ] rcar-gpio | |-- gpio@e605 gpio 1 [ ] rcar-gpio | |-- gpio@e6051000 gpio 2 [ + ] rcar-gpio | |-- gpio@e6052000 gpio 3 [ ] rcar-gpio | |-- gpio@e6053000 gpio 4 [ ] rcar-gpio | |-- gpio@e6054000 gpio 5 [ ] rcar-gpio | |-- gpio@e6055000 gpio 6 [ + ] rcar-gpio | |-- gpio@e6055400 gpio 7 [ ] rcar-gpio | |-- gpio@e6055800 clk 8 [ + ] clk_r8a774a1 | |-- clock-controller@e615 i2c 0 [ ] i2c_rcar | |-- i2c@e650 i2c 1 [ ] i2c_rcar | |-- i2c@e651 i2c 2 [ ] i2c_rcar | |-- i2c@e66d8000 i2c 3 [ ] i2c_rcar | |-- i2c@e66e eth 0 [ ] ravb | |-- ethernet@e680 serial0 [ ] serial_sh | |-- serial@e6e6 serial1 [ + ] serial_sh | |-- serial@e6e88000 serial2 [ ] serial_sh | |-- serial@e6f3 usb 0 [ ] ehci_generic | |-- usb@ee080100 usb 1 [ ] ehci_generic | |-- usb@ee0a0100 phy 0 [ ] rcar-gen3-phy | |-- usb-phy@ee080200 phy 1 [ ] rcar-gen3-phy | |-- usb-phy@ee0a0200 mmc 0 [ + ] renesas-sdhi | |-- sd@ee10 blk 0 [ ] mmc_blk | | `-- s...@ee10.blk mmc 1 [ + ] renesas-sdhi | |-- sd@ee16 blk 1 [ + ] mmc_blk | | `-- s...@ee16.blk pci 0 [ ] rcar_gen3_pcie| |-- pcie@fe00 pci 1 [ ] rcar_gen3_pcie| `-- pcie@ee80 clk 9 [ ] fixed_rate_clock |-- usb3s0 clk 10 [ ] fixed_rate_clock |-- usb_extal clk 11 [ ] fixed_rate_clock |-- osc_32k regulator 0 [ + ] fixed regulator |-- regulator0 regulator 1 [ + ] fixed regulator |-- regulator1 regulator 2 [ ] fixed regulator |-- regulator_audio regulator 3 [ ] fixed regulator |-- regulator-lcd regulator 4 [ ] fixed regulator |-- regulator-lcd-reset regulator 5 [ ] fixed regulator |-- regulator_camera regulator 6 [ + ] gpio regulator|-- regulator-vccq-sdhi0 clk 12 [ ] fixed_rate_
[PATCH v2 1/4] phy: atheros: ar8035: Fix clock output calculation
The clock ouput frequency is calculated incorrectly for AR8035 due to
wrong masking of priv->clk_25m_reg and priv->clk_25m_mask.
This same issue has been already fixed in the kernel by:
commit b1f4c209d84057b6d40b939b6e4404854271d797
Author: Oleksij Rempel
Date: Wed Apr 1 11:57:32 2020 +0200
net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035
The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
for the values that comprise the fields, not zero-bits-set.
This patch fixes the clock frequency configuration for ATH8030 and
ATH8035 Atheros PHYs by removing the erroneous "~".
To reproduce this bug, configure the PHY with the device tree binding
"qca,clk-out-frequency" and remove the machine specific PHY fixups.
Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding")
Signed-off-by: Oleksij Rempel
Reported-by: Russell King
Reviewed-by: Russell King
Tested-by: Russell King
Signed-off-by: David S. Miller
Apply the same fix in the U-Boot driver.
Tested on a i.MX6 Hummingboard.
Signed-off-by: Fabio Estevam
Reviewed-by: Michael Walle
Tested-by: Tom Rini
---
Changes since v1:
- None
drivers/net/phy/atheros.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 13f7275d17..f922fecd6b 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -275,11 +275,10 @@ static int ar803x_of_init(struct phy_device *phydev)
* Fixup for the AR8035 which only has two bits. The two
* remaining bits map to the same frequencies.
*/
- if (phydev->drv->uid == AR8035_PHY_ID) {
- u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK;
- priv->clk_25m_mask &= ~clear;
- priv->clk_25m_reg &= ~clear;
+ if (phydev->drv->uid == AR8035_PHY_ID) {
+ priv->clk_25m_reg &= AR8035_CLK_25M_MASK;
+ priv->clk_25m_mask &= AR8035_CLK_25M_MASK;
}
}
--
2.17.1
[PATCH v2 4/4] mx6cuboxi: Convert to DM_ETH
Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet
Driver Model.
This also brings the benefit of restoring Ethernet functionality.
Reported-by: Tom Rini
Signed-off-by: Fabio Estevam
Signed-off-by: Fabio Estevam
Tested-by: Tom Rini
---
Changes since v1:
- Remove header - Baruch
- Remove ENET_PAD_CTRL definitions - Baruch
- Remove DM_MDIO- Vladimir
board/solidrun/mx6cuboxi/mx6cuboxi.c | 134 ---
configs/mx6cuboxi_defconfig | 3 +
include/configs/mx6cuboxi.h | 6 --
3 files changed, 20 insertions(+), 123 deletions(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 94707bccb2..59e8b1dca1 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -17,7 +17,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -33,8 +32,6 @@
#include
#include
#include
-#include
-#include
#include
#include
#include
@@ -52,16 +49,6 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
#define USB_H1_VBUSIMX_GPIO_NR(1, 0)
enum board_type {
@@ -237,110 +224,6 @@ int board_mmc_init(bd_t *bis)
return 0;
}
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* AR8035 reset */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- /* AR8035 interrupt */
- IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* GPIO16 -> AR8035 25MHz */
- IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-};
-
-static void setup_iomux_enet(void)
-{
- struct gpio_desc desc;
- int ret;
-
- SETUP_IOMUX_PADS(enet_pads);
-
- ret = dm_gpio_lookup_name("GPIO4_15", &desc);
- if (ret) {
- printf("%s: phy reset lookup failed\n", __func__);
- return;
- }
-
- ret = dm_gpio_request(&desc, "phy-reset");
- if (ret) {
- printf("%s: phy reset request failed\n", __func__);
- return;
- }
-
- gpio_direction_output(ETH_PHY_RESET, 0);
- mdelay(10);
- gpio_set_value(ETH_PHY_RESET, 1);
- udelay(100);
-
- gpio_free_list_nodev(&desc, 1);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
-#define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4))
-
-int board_eth_init(bd_t *bis)
-{
- struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct mii_dev *bus;
- struct phy_device *phydev;
-
- int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
- if (ret)
- return ret;
-
- /* set gpr1[ENET_CLK_SEL] */
- setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
-
- setup_iomux_enet();
-
- bus = fec_get_miibus(IMX_FEC_BASE, -1);
- if (!bus)
- return -EINVAL;
-
- phydev = phy_find_by_mask(bus
[PATCH v2 3/4] ARM: dts: imx6qdl-sr-som: Sync with kernel 5.8-rc1
Sync the device tree with 5.8-rc1.
It basically contains the following extra kernel commit:
commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09
Author: Russell King
Date: Wed Apr 15 16:44:17 2020 +0100
ARM: dts: imx6-sr-som: add ethernet PHY configuration
Add ethernet PHY configuration ahead of removing the quirk that
configures the clocking mode for the PHY. The RGMII delay is
already set correctly.
Signed-off-by: Russell King
Reviewed-by: Fabio Estevam
Signed-off-by: Shawn Guo
, which passes the 'qca,clk-out-frequency' property and it is important
to specify the correct frequency generated by the AR8031.
Signed-off-by: Fabio Estevam
Tested-by: Tom Rini
---
Changes since v1:
- None
arch/arm/dts/imx6qdl-sr-som.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/dts/imx6qdl-sr-som.dtsi b/arch/arm/dts/imx6qdl-sr-som.dtsi
index 6d7f6b9035..b06577808f 100644
--- a/arch/arm/dts/imx6qdl-sr-som.dtsi
+++ b/arch/arm/dts/imx6qdl-sr-som.dtsi
@@ -53,10 +53,21 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
+ phy-handle = <&phy>;
phy-mode = "rgmii-id";
phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@0 {
+ reg = <0>;
+ qca,clk-out-frequency = <12500>;
+ };
+ };
};
&iomuxc {
--
2.17.1
[PATCH v2 2/4] net: fec: Allow the PHY node to be retrieved
As we move towards driver model, it is required to let the FEC driver
know how to properly deal with an Ethernet PHY subnode in the device tree.
For example:
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-handle = <&phy>;
phy-mode = "rgmii-id";
phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@0 {
reg = <0>;
qca,clk-out-frequency = <12500>;
};
};
};
Currently the PHY node pointer is incorrectly associated with the
Ethernel controller instead of the PHY node itself.
This causes the PHY properties, such as "qca,clk-out-frequency" in
the example above to not get parsed.
Fix this problem by populating the phy_of_node node.
Suggested-by: Vladimir Oltean
Signed-off-by: Fabio Estevam
Tested-by: Tom Rini
---
Changes since v1:
- None
drivers/net/fec_mxc.c | 7 +--
drivers/net/fec_mxc.h | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 9ae2db033e..992180df86 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1294,7 +1294,7 @@ static const struct eth_ops fecmxc_ops = {
.read_rom_hwaddr= fecmxc_read_rom_hwaddr,
};
-static int device_get_phy_addr(struct udevice *dev)
+static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
{
struct ofnode_phandle_args phandle_args;
int reg;
@@ -1305,6 +1305,8 @@ static int device_get_phy_addr(struct udevice *dev)
return -ENODEV;
}
+ priv->phy_of_node = phandle_args.node;
+
reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
return reg;
@@ -1315,7 +1317,7 @@ static int fec_phy_init(struct fec_priv *priv, struct
udevice *dev)
struct phy_device *phydev;
int addr;
- addr = device_get_phy_addr(dev);
+ addr = device_get_phy_addr(priv, dev);
#ifdef CONFIG_FEC_MXC_PHYADDR
addr = CONFIG_FEC_MXC_PHYADDR;
#endif
@@ -1325,6 +1327,7 @@ static int fec_phy_init(struct fec_priv *priv, struct
udevice *dev)
return -ENODEV;
priv->phydev = phydev;
+ priv->phydev->node = priv->phy_of_node;
phy_config(phydev);
return 0;
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 0e8f08a51a..659d62646f 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -250,6 +250,7 @@ struct fec_priv {
struct mii_dev *bus;
#ifdef CONFIG_PHYLIB
struct phy_device *phydev;
+ ofnode phy_of_node;
#else
int phy_id;
int (*mii_postcall)(int);
--
2.17.1
[PATCH 2/5] ARM: dts: r8a774a1: Import DTS from Linux 5.8-rc1
This patch imports the device tree and required bindings to permit
the device tree to build for the R8Z774A1 (RZ/G2M).
Signed-off-by: Adam Ford
diff --git a/arch/arm/dts/r8a774a1.dtsi b/arch/arm/dts/r8a774a1.dtsi
new file mode 100644
index 00..a603d94797
--- /dev/null
+++ b/arch/arm/dts/r8a774a1.dtsi
@@ -0,0 +1,2787 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a774a1 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "renesas,r8a774a1";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c_dvfs;
+ };
+
+ /*
+* The external audio clocks are configured as 0 Hz fixed frequency
+* clocks by default.
+* Boards that provide audio clocks should override them.
+*/
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-5 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ opp-10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ opp-15 {
+ opp-hz = /bits/ 64 <15>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-8 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ opp-10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ opp-12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&a57_0>;
+ };
+ core1 {
+ cpu = <&a57_1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&a53_0>;
+ };
+ core1 {
+ cpu = <&a53_1>;
+ };
+ core2 {
+ cpu = <&a53_2>;
+ };
+ core3 {
+ cpu = <&a53_3>;
+ };
+ };
+ };
+
+ a57_0: cpu@0 {
+ compatible = "arm,cortex-a57";
+ reg = <0x0>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
+ next-level-cache = <&L2_CA57>;
+ enable-method = "psci";
+ dynamic-power-coefficient = <854>;
+ clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
+ capacity-dmips-mhz = <1024>;
+
[PATCH 5/5] mmc: renesas-sdhi: Enable support for R8A774A1
The renesas-shdi controller can drive the r8a774a1 and shares its
quirks with R8A7796. This patch adds the compatibilty flag, to
support the SDHI controller.
Signed-off-by: Adam Ford
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index d6ea99d2ce..8b8e300caf 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -20,7 +20,6 @@
#include
#include
#include
-
#include "tmio-common.h"
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
@@ -843,6 +842,7 @@ static const struct udevice_id renesas_sdhi_match[] = {
{ .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
{ .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
+ { .compatible = "renesas,sdhi-r8a774a1", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
--
2.25.1
[PATCH 1/5] ARM: renesas: Add basic R8A774A1 Support
In order to build boards based on the R8A774A1, there needs to be a config option from which to enable other drivers and/or flags for this SoC. Signed-off-by: Adam Ford diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index c8f93c68bb..bfd513a361 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -2,6 +2,9 @@ if RCAR_GEN3 menu "Select Target SoC" +config R8A774A1 +bool "Renesas SoC R8A774A1" + config R8A7795 bool "Renesas SoC R8A7795" imply CLK_R8A7795 -- 2.25.1
[PATCH 3/5] clk: renesas: Add R8A774A1 clock tables
This sync's the clock tables with the official release from
Renesas' repo based on U-Boot 2018.09 and modified to build into
the latest version of U-Boot.
Signed-off-by: Adam Ford
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index e78817829b..284e2138b3 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -48,6 +48,13 @@ config CLK_RCAR_GEN3
help
Enable this to support the clocks on Renesas RCar Gen3 SoC.
+config CLK_R8A774A1
+bool "Renesas R8A774A1 clock driver"
+def_bool y if R8A774A1
+depends on CLK_RCAR_GEN3
+help
+ Enable this to support the clocks on Renesas R8A774A1 SoC.
+
config CLK_R8A7795
bool "Renesas R8A7795 clock driver"
depends on CLK_RCAR_GEN3
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 88339e9d7e..dd599b757e 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o
obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
+obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
new file mode 100644
index 00..0341d8e61c
--- /dev/null
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -0,0 +1,343 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas R8A774A1 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2019 Marek Vasut
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ */
+
+#include
+#include
+#include
+
+#include
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A774A1_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL3,
+ CLK_PLL4,
+ CLK_PLL1_DIV2,
+ CLK_PLL1_DIV4,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+ CLK_RPCSRC,
+ CLK_SSPSRC,
+ CLK_RINT,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a774a1_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+ DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0",CLK_S0,CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1",CLK_S1,CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".rpcsrc",CLK_RPCSRC,CLK_PLL1, 2, 1),
+
+ DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("ztr",R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A774A1_CLK_ZT,CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A774A1_CLK_ZX,CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED("s0d1", R8A774A1_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s0d2", R8A774A1_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A774A1_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A774A1_CLK_S0D4, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6", R8A774A1_CLK_S0D6, CLK_S0, 6, 1),
+ DEF_FIXED("s0d8", R8A774A1_CLK_S0D8, CLK_S0, 8, 1),
+ DEF_FIXED("s0d12", R8A774A1_CLK_S0D12, CLK_S0,12, 1),
+ DEF_FIXED("s1d1", R8A774A1_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A774A1_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A774A1_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A774A1_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED
[PATCH 0/5] Add Basic support for R8A774A1 (RZ/G2M)
The R8A774A1 (RZ/G2M) a commercial SoC based off the automotive R8A7796 SoC. This series will start the foundation to support this SoC by importing porting the device tree and bindings from Linux 5.8-rc1, then porting the clock driver, pinctrl driver, and sdhi drivers from Renesas' RZG2M repo found: https://github.com/renesas-rz/renesas-u-boot-cip/tree/v2018.09/rzg2 Adam Ford (5): ARM: renesas: Add basic R8A774A1 Support ARM: dts: r8a774a1: Import DTS from Linux 5.8-rc1 clk: renesas: Add R8A774A1 clock tables pinctrl: renesas: Add R8A774A1 PFC tables mmc: renesas-sdhi: Enable support for R8A774A1 arch/arm/dts/r8a774a1.dtsi| 2787 arch/arm/mach-rmobile/Kconfig.64 |3 + drivers/clk/renesas/Kconfig |7 + drivers/clk/renesas/Makefile |1 + drivers/clk/renesas/r8a774a1-cpg-mssr.c | 343 + drivers/mmc/renesas-sdhi.c|2 +- drivers/pinctrl/renesas/Kconfig | 10 + drivers/pinctrl/renesas/Makefile |1 + drivers/pinctrl/renesas/pfc-r8a774a1.c| 6196 + include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 65 + include/dt-bindings/power/r8a774a1-sysc.h | 33 + 11 files changed, 9447 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/r8a774a1.dtsi create mode 100644 drivers/clk/renesas/r8a774a1-cpg-mssr.c create mode 100644 drivers/pinctrl/renesas/pfc-r8a774a1.c create mode 100644 include/dt-bindings/clock/r8a774a1-cpg-mssr.h create mode 100644 include/dt-bindings/power/r8a774a1-sysc.h -- 2.25.1
Please pull u-boot-video
Hi Tom, please pull some fixes for v2020.07-rc4. Thanks! gitlab CI: https://gitlab.denx.de/u-boot/custodians/u-boot-video/pipelines/3720 The following changes since commit 9cb895203a46654f7ee6dd95be5c8ab05e4dfbd3: Merge tag 'u-boot-stm32-20200616' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm (2020-06-16 09:18:56 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-video.git tags/fixes-for-v2020.07-rc4 for you to fetch changes up to 1099b2abef35c3c887f6afac1a8ef18c7924d5d2: colibri_imx6: fix video stdout in default environment (2020-06-18 19:17:28 +0200) - fix stdout in default environment for apalis_imx6, colibri_imx6 and cm_fx6 boards Anatolij Gustschin (3): cm_fx6: fix video stdout in default environment apalis_imx6: fix video stdout in default environment colibri_imx6: fix video stdout in default environment include/configs/apalis_imx6.h | 3 ++- include/configs/cm_fx6.h | 4 ++-- include/configs/colibri_imx6.h | 3 ++- 3 files changed, 6 insertions(+), 4 deletions(-)
Re: [PATCH] video: bmp: Support 8bits BMP to 24/32 bits display
Hi Anatolij, On Wed, Jun 10, 2020 at 6:53 AM Ye Li wrote: > > Update video bmp codes to support 8 bits BMP to 32 bits conversion > so that we can display 8 bits logo on 24 bits or 32 bits display > > Signed-off-by: Ye Li I haven't had a chance to test this yet, but it seems to solve an outstanding splash screen issue on mx6ul evk/mx7d sabresd boards. Maybe we should get this one and the other two from Ye Li to 2020.07? Thanks
Re: Can't access mmc #0 on mt7623 when booted from external SD
On Thu, 2020-06-18 at 21:34 +0200, Michael Nazzareno Trimarchi wrote:
> > Looks like the pinctrl driver. This *ought* to work (with the caveat
> > that I really ought to make two pinctrl setups and change between them
> > according to the voltage, like the Linux DT and mtk-sd driver do).
> >
> > --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> > +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> > @@ -133,12 +133,14 @@
> > "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
> > "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
> > input-enable;
> > - bias-pull-up;
> > + drive-strength = <2>;
> > + bias-pull-up = <3>;
> > };
> >
> > conf-clk {
> > pins = "MSDC0_CLK";
> > - bias-pull-down;
> > + drive-strength = <2>;
> > + bias-pull-down = <3>;
> > };
> >
> > conf-rst {
> >
> >
> > But it doesn't work. Partly because the U-Boot mtk pinctrl driver
> > doesn't support the R0 R1 bits encoded in that <3>, and partly because
> > it doesn't *even* get pullup/pulldown right at all; it sets the bit in
> > the GPIO_PULLSEL registers but *not* the PUPD bit in the correct
> > register for MSDC and other pins.
>
> So change them manually, make it work, You have the board. I don't
> have any MediaTek board at the moment. Can you implement the missed part?
I think I'd rather let the MediaTek folks handle it, as it affects
other SoCs too.
It turns out Linux has a pinctrl-mt7623.c driver which looks a lot like
the U-Boot one, but *isn't* actually the one being used, because in
Linux it only matches "mediatek,mt7623-moore-pinctrl" which isn't in
this board's DT.
Linux also has a pinctrl-mt2701.c driver that matches the
"mediatek,mt7623-pinctrl" that *is* on this board, and which *does*
work correctly.
So I don't know if we just have the wrong driver in U-Boot. Or if the
mediatek,mt7623-moore-pinctrl compatible string is a temporary name for
the *same* hardware, to invoke the new driver that isn't complete yet
so it isn't being used in Linux... but is in U-Boot?
Sean?
smime.p7s
Description: S/MIME cryptographic signature
Re: GPIO request failures for Renesas rcar-gen3
On 6/18/20 10:33 PM, Adam Ford wrote: > I am trying to port U-Boot to a new product based on a Renesas RZ/G2M > (rcar-gen3). We're have this working with Renesas' version from > 2018.09, but I am trying to integrate it with U-Boot 2020.07-rc4 > > What's happening is that it seems like all GPIO are failing to be > requested, so things like regulator-gpio fail, reset-gpios, etc. all > return errors. > > The dm tree and gpio status commands all appear to show gpio banks are > enumerating, but since nothing can use the GPIO's it seems like the > common thread is the gpio driver for the rcar3. > > I was hoping someone might have some thoughts of things I could try or > investigate. In order to properly set the voltage for the MMC card, I > need "regulator-gpio" to operate correctly. Note that RZ/G2M is not supported by mainline U-Boot. Also note that the GPIO driver and PFC drivers are working together, grep for sh_pfc_config_mux_for_gpio(), so unless both work and probed, the GPIO driver will likely not work. Can you provide 'dm tree' output ?
[PATCH] Azure/GitLab: Move to latest Docker image
- Add guestfstools, efitools - Latest Ubuntu/bionic snapshot Signed-off-by: Tom Rini --- .azure-pipelines.yml | 2 +- .gitlab-ci.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 636500d6cead..28387ce17cae 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -2,7 +2,7 @@ variables: windows_vm: vs2017-win2016 ubuntu_vm: ubuntu-18.04 macos_vm: macOS-10.15 - ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200403-27Apr2020 + ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200526-18Jun2020 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index badfcb4254ed..f2e491c1172d 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -2,7 +2,7 @@ # Grab our configured image. The source for this is found at: # https://gitlab.denx.de/u-boot/gitlab-ci-runner -image: trini/u-boot-gitlab-ci-runner:bionic-20200403-27Apr2020 +image: trini/u-boot-gitlab-ci-runner:bionic-20200526-18Jun2020 # We run some tests in different order, to catch some failures quicker. stages: -- 2.17.1
Please pull u-boot-video/next
Hi Tom, please pull first video updates for -next. Thanks! gitlab CI: https://gitlab.denx.de/u-boot/custodians/u-boot-video/pipelines/3716 The following changes since commit 7a81989b7b04bd87d1e684f2bafdc92a9c16fecc: common: hash: Remove a debug printf statement (2020-06-16 11:36:30 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-video.git tags/video-next for you to fetch changes up to fb3dd9c005045c2748e30d555d252c6985b97349: video: ipuv3: remove non-DM code (2020-06-18 19:38:50 +0200) - migrate remaining imx5/imx6qd boards to DM_VIDEO - use 'vidconsole' stdout in nitrogen6x upgrade script - add option for selection of the vidconsole commands lcdputs and setcurs - allow building ipuv3 driver with disabled CONFIG_PANEL - make backlight and panel drivers optional - remove useless code from ipuv3 driver - extend existing DM_VIDEO work-around for console name to support 'vga' - remove non-DM code in ipuv3 Anatolij Gustschin (16): nitrogen6x: update video console name video: make vidconsole commands optional video: ipuv3: fix building with disabled panel driver video: make backlight and panel drivers optional video: ipuv3: remove some useless code to reduce binary size video: extend stdout video console work-around for 'vga' tbs2910: migrate to DM_VIDEO imx: convert embest boards to DM_VIDEO imx: convert pico-imx6 to DM_VIDEO imx: convert dms-ba16 boards to DM_VIDEO imx: convert cgtqmx6eval board to DM_VIDEO imx: convert mx6cuboxi board to DM_VIDEO imx: convert gwventana board to DM_VIDEO imx: convert mx51evk board to DM_VIDEO imx: convert mx53loco board to DM_VIDEO video: ipuv3: remove non-DM code Troy Kisky (1): board: nitrogen6x: migrate to CONFIG_DM_VIDEO arch/arm/mach-tegra/Kconfig | 1 - board/boundary/nitrogen6x/6x_upgrade.txt | 2 +- board/congatec/cgtqmx6eval/cgtqmx6eval.c | 5 ++ common/console.c | 7 ++- configs/cgtqmx6eval_defconfig| 10 +++- configs/dms-ba16-1g_defconfig| 10 +++- configs/dms-ba16_defconfig | 10 +++- configs/gwventana_emmc_defconfig | 10 +++- configs/gwventana_gw5904_defconfig | 10 +++- configs/gwventana_nand_defconfig | 10 +++- configs/marsboard_defconfig | 10 +++- configs/mx51evk_defconfig| 10 +++- configs/mx53loco_defconfig | 10 +++- configs/mx6cuboxi_defconfig | 12 +++- configs/mx6qsabrelite_defconfig | 6 +- configs/nitrogen6dl2g_defconfig | 6 +- configs/nitrogen6dl_defconfig| 6 +- configs/nitrogen6q2g_defconfig | 6 +- configs/nitrogen6q_defconfig | 6 +- configs/nitrogen6s1g_defconfig | 6 +- configs/nitrogen6s_defconfig | 6 +- configs/pico-imx6_defconfig | 9 ++- configs/riotboard_defconfig | 10 +++- configs/riotboard_spl_defconfig | 10 +++- configs/tbs2910_defconfig| 9 ++- drivers/video/Kconfig| 51 +--- drivers/video/Makefile | 5 +- drivers/video/imx/Kconfig| 2 +- drivers/video/imx/ipu_disp.c | 12 drivers/video/imx/mxc_ipuv3_fb.c | 99 drivers/video/vidconsole-uclass.c| 2 + include/configs/advantech_dms-ba16.h | 2 - include/configs/tbs2910.h| 10 ++-- 33 files changed, 219 insertions(+), 161 deletions(-)
GPIO request failures for Renesas rcar-gen3
I am trying to port U-Boot to a new product based on a Renesas RZ/G2M
(rcar-gen3). We're have this working with Renesas' version from
2018.09, but I am trying to integrate it with U-Boot 2020.07-rc4
What's happening is that it seems like all GPIO are failing to be
requested, so things like regulator-gpio fail, reset-gpios, etc. all
return errors.
The dm tree and gpio status commands all appear to show gpio banks are
enumerating, but since nothing can use the GPIO's it seems like the
common thread is the gpio driver for the rcar3.
I was hoping someone might have some thoughts of things I could try or
investigate. In order to properly set the voltage for the MMC card, I
need "regulator-gpio" to operate correctly.
The gpio regulator node looks like:
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <180>;
regulator-max-microvolt = <330>;
gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <330 1>, <180 0>;
regulator-always-on;
};
Log Below with some debugging turned on.
U-Boot 2020.07-rc4-00060-g9cb895203a-dirty (Jun 18 2020 - 15:27:00 -0500)
CPU: Renesas Electronics R8A7796 rev 2.1
Model: Beacon Embedded Works RZ/G2M Development Kit
DRAM: 3.9 GiB
Bank #0: 0x04800 - 0x0bfff, 1.9 GiB
Bank #1: 0x6 - 0x67fff, 2 GiB
MMC: gpio_request_tail: dm_gpio_requestf failed
gpio_request_tail: Node 'regulator-vccq-sdhi0', property 'gpios',
failed to request GPIO index 0: -19
regulator gpio - not found! Error: -19gpio_request_tail: Node
'regulator-vccq-sdhi0', property 'enable-gpios', failed to request
GPIO index 0: -2
gpio@e6055400: set_value: error: gpio gpio@e605540030 not reserved
Can't set regulator-gpio : regulator-vccq-sdhi0 gpio to: 1
gpio_request_tail: Node 'regulator0', property 'gpio', failed to
request GPIO index 0: -2
sd@ee10: 0, sd@ee16: 1
Loading Environment from MMC... gpio_request_tail: Node 'regulator1',
property 'gpio', failed to request GPIO index 0: -2
OK
In:serial@e6e88000
Out: serial@e6e88000
Err: serial@e6e88000
Net: gpio_request_tail: dm_gpio_requestf failed
gpio_request_tail: Node 'ethernet-phy@0', property 'reset-gpios',
failed to request GPIO index 0: -19
gpio@e6052000: set_value: error: gpio gpio@e605200010 not reserved
gpio@e6052000: set_value: error: gpio gpio@e605200010 not reserved
Error: ethernet@e680 address not set.
No ethernet found.
Hit any key to stop autoboot: 0
=>
Re: Can't access mmc #0 on mt7623 when booted from external SD
Hi David
On Thu, Jun 18, 2020 at 9:21 PM David Woodhouse wrote:
>
> On Thu, 2020-06-18 at 16:52 +0100, David Woodhouse wrote:
> > So... whose bug is that? :)
>
> Looks like the pinctrl driver. This *ought* to work (with the caveat
> that I really ought to make two pinctrl setups and change between them
> according to the voltage, like the Linux DT and mtk-sd driver do).
>
> --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> @@ -133,12 +133,14 @@
>"MSDC0_DAT2", "MSDC0_DAT3",
> "MSDC0_DAT4",
>"MSDC0_DAT5", "MSDC0_DAT6",
> "MSDC0_DAT7";
> input-enable;
> - bias-pull-up;
> + drive-strength = <2>;
> + bias-pull-up = <3>;
> };
>
> conf-clk {
> pins = "MSDC0_CLK";
> - bias-pull-down;
> + drive-strength = <2>;
> + bias-pull-down = <3>;
> };
>
> conf-rst {
>
>
> But it doesn't work. Partly because the U-Boot mtk pinctrl driver
> doesn't support the R0 R1 bits encoded in that <3>, and partly because
> it doesn't *even* get pullup/pulldown right at all; it sets the bit in
> the GPIO_PULLSEL registers but *not* the PUPD bit in the correct
> register for MSDC and other pins.
So change them manually, make it work, You have the board. I don't
have any MediaTek board at the moment. Can you implement the missed part?
Michael
--
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO - Founder Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |
| [`as] http://www.amarulasolutions.com |
Re: [PATCH v8 1/2] mmc: ca_dw_mmc: Misc cleanup of driver
Thanks Peng,
Could we update the state of this patch set in the patchwork DB as done? It
still at state “New”.
> On Jun 17, 2020, at 3:14 PM, Peng Fan wrote:
>
> It has been applied, could you check tom's master tree?
>
>> -Original Message-
>> From: Alex Nemirovsky [mailto:alex.nemirov...@cortina-access.com]
>> Sent: 2020年6月18日 4:25
>> To: U-Boot-Denx
>> Cc: 李冠德 ; Peng Fan
>> ; Jaehoon Chung ; Tom Rini
>>
>> Subject: Re: [PATCH v8 1/2] mmc: ca_dw_mmc: Misc cleanup of driver
>>
>> Hi Peng,
>>
>> this patch set seems to have stalled. There was some confusion as most of
>> the driver was already pushed to master and thus a new patch was created
>> for some some misc cleanup.
>> Could you review?
>>
>> Thanks
>> Alex
>>> On May 21, 2020, at 5:24 PM, Alex Nemirovsky
>> wrote:
>>>
>>> From: Arthur Li
>>>
>>> - Rename DT compatible name
>>> - Remove uneccessary if-statement to support 8-bit buswidth
>>> - Remove redundant error msg
>>> - Use symbolic constants in switch statement
>>>
>>> Signed-off-by: Arthur Li
>>> Signed-off-by: Alex Nemirovsky
>>> CC: Peng Fan
>>> CC: Jaehoon Chung
>>> CC: Tom Rini
>>> ---
>>>
>>> Changes in v8:
>>> - No code change
>>> - Split out individual driver from Cortina Package 2 patch series to
>>> help streamline acceptence into master
>>>
>>> Changes in v7: None
>>> Changes in v5:
>>> - Rebase code basis on v2020.04-rc5 which has already incorporated
>>> CA eMMC initial baseline
>>>
>>> Changes in v4:
>>> - Rename DT compatible name
>>> - Remove uneccessary if-statement to support 8-bit buswidth
>>> - Remove redundant error msg
>>> - Use symbolic constants in switch statement
>>>
>>> drivers/mmc/ca_dw_mmc.c | 34 --
>>> 1 file changed, 12 insertions(+), 22 deletions(-)
>>>
>>> diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c index
>>> acbc850..198c41f 100644
>>> --- a/drivers/mmc/ca_dw_mmc.c
>>> +++ b/drivers/mmc/ca_dw_mmc.c
>>> @@ -19,6 +19,7 @@
>>>
>>> #define SD_CLK_SEL_200MHZ (0x2)
>>> #define SD_CLK_SEL_100MHZ (0x1)
>>> +#define SD_CLK_SEL_50MHZ (0x0)
>>>
>>> #define IO_DRV_SD_DS_OFFSET (16)
>>> #define IO_DRV_SD_DS_MASK (0xff << IO_DRV_SD_DS_OFFSET)
>>> @@ -44,15 +45,11 @@ static void ca_dwmci_clksel(struct dwmci_host
>> *host)
>>> struct ca_dwmmc_priv_data *priv = host->priv;
>>> u32 val = readl(priv->sd_dll_reg);
>>>
>>> - if (host->bus_hz >= 2) {
>>> - val &= ~SD_CLK_SEL_MASK;
>>> + val &= ~SD_CLK_SEL_MASK;
>>> + if (host->bus_hz >= 2)
>>> val |= SD_CLK_SEL_200MHZ;
>>> - } else if (host->bus_hz >= 1) {
>>> - val &= ~SD_CLK_SEL_MASK;
>>> + else if (host->bus_hz >= 1)
>>> val |= SD_CLK_SEL_100MHZ;
>>> - } else {
>>> - val &= ~SD_CLK_SEL_MASK;
>>> - }
>>>
>>> writel(val, priv->sd_dll_reg);
>>> }
>>> @@ -77,14 +74,14 @@ unsigned int ca_dwmci_get_mmc_clock(struct
>> dwmci_host *host, uint freq)
>>> u8 clk_div;
>>>
>>> switch (sd_clk_sel) {
>>> - case 2:
>>> - clk_div = 1;
>>> + case SD_CLK_SEL_50MHZ:
>>> + clk_div = 4;
>>> break;
>>> - case 1:
>>> + case SD_CLK_SEL_100MHZ:
>>> clk_div = 2;
>>> break;
>>> default:
>>> - clk_div = 4;
>>> + clk_div = 1;
>>> }
>>>
>>> return SD_SCLK_MAX / clk_div / (host->div + 1); @@ -100,9 +97,6 @@
>>> static int ca_dwmmc_ofdata_to_platdata(struct udevice *dev)
>>> host->dev_index = 0;
>>>
>>> host->buswidth = dev_read_u32_default(dev, "bus-width", 1);
>>> - if (host->buswidth != 1 && host->buswidth != 4)
>>> - return -EINVAL;
>>> -
>>> host->bus_hz = dev_read_u32_default(dev, "max-frequency",
>> 5000);
>>> priv->ds = dev_read_u32_default(dev, "io_ds", 0x33);
>>> host->fifo_mode = dev_read_bool(dev, "fifo-mode"); @@ -118,10 +112,8
>>> @@ static int ca_dwmmc_ofdata_to_platdata(struct udevice *dev)
>>> return -EINVAL;
>>>
>>> host->ioaddr = dev_read_addr_ptr(dev);
>>> - if (host->ioaddr == (void *)FDT_ADDR_T_NONE) {
>>> - printf("DWMMC: base address is invalid\n");
>>> + if (!host->ioaddr)
>>> return -EINVAL;
>>> - }
>>>
>>> host->priv = priv;
>>>
>>> @@ -140,10 +132,8 @@ static int ca_dwmmc_probe(struct udevice *dev)
>>> memcpy(&ca_dwmci_dm_ops, &dm_dwmci_ops, sizeof(struct
>> dm_mmc_ops));
>>>
>>> dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, MIN_FREQ);
>>> - if (host->buswidth == 1) {
>>> - (&plat->cfg)->host_caps &= ~MMC_MODE_8BIT;
>>> - (&plat->cfg)->host_caps &= ~MMC_MODE_4BIT;
>>> - }
>>> + if (host->buswidth == 1)
>>> + (&plat->cfg)->host_caps &= ~(MMC_MODE_8BIT |
>> MMC_MODE_4BIT);
>>>
>>> host->mmc = &plat->mmc;
>>> host->mmc->priv = &priv->host;
>>> @@ -164,7 +154,7 @@ static int ca_dwmmc_bind(struct udevice *dev) }
>>>
>>> static const struct udevice_id ca_dwmmc_ids[] = {
>>> - { .compa
Re: [PATCH 4/4] mx6cuboxi: Convert to DM_ETH
Hi Fabio,
On Thu, 18 Jun 2020 at 22:07, Fabio Estevam wrote:
>
> Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet
> Driver Model.
>
> This also brings the benefit of restoring Ethernet functionality.
>
> Reported-by: Tom Rini
> Signed-off-by: Fabio Estevam
> ---
> board/solidrun/mx6cuboxi/mx6cuboxi.c | 123 ---
> configs/mx6cuboxi_defconfig | 4 +
> include/configs/mx6cuboxi.h | 6 --
> 3 files changed, 21 insertions(+), 112 deletions(-)
>
> diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
> b/board/solidrun/mx6cuboxi/mx6cuboxi.c
> index 94707bccb2..225fea2cb2 100644
> --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
> +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
> @@ -17,7 +17,6 @@
> #include
> #include
> #include
> -#include
> #include
> #include
> #include
> @@ -34,7 +33,6 @@
> #include
> #include
> #include
> -#include
> #include
> #include
> #include
> @@ -237,110 +235,6 @@ int board_mmc_init(bd_t *bis)
> return 0;
> }
>
> -static iomux_v3_cfg_t const enet_pads[] = {
> - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - /* AR8035 reset */
> - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
> - /* AR8035 interrupt */
> - IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> - /* GPIO16 -> AR8035 25MHz */
> - IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
> - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
> MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
> - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
> - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
> - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
> MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
> - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 |
> MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
> - IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 |
> MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
> -};
> -
> -static void setup_iomux_enet(void)
> -{
> - struct gpio_desc desc;
> - int ret;
> -
> - SETUP_IOMUX_PADS(enet_pads);
> -
> - ret = dm_gpio_lookup_name("GPIO4_15", &desc);
> - if (ret) {
> - printf("%s: phy reset lookup failed\n", __func__);
> - return;
> - }
> -
> - ret = dm_gpio_request(&desc, "phy-reset");
> - if (ret) {
> - printf("%s: phy reset request failed\n", __func__);
> - return;
> - }
> -
> - gpio_direction_output(ETH_PHY_RESET, 0);
> - mdelay(10);
> - gpio_set_value(ETH_PHY_RESET, 1);
> - udelay(100);
> -
> - gpio_free_list_nodev(&desc, 1);
> -}
> -
> -int board_phy_config(struct phy_device *phydev)
> -{
> - if (phydev->drv->config)
> - phydev->drv->config(phydev);
> -
> - return 0;
> -}
> -
> -/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
> -#define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4))
> -
> -int board_eth_init(bd_t *bis)
> -{
> - struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> - struct mii_dev *bus;
> - struct phy_device *phydev;
> -
> - int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
> - if (ret)
> - return ret;
> -
> - /* set gpr1[ENET_CLK_SEL] */
> - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
> -
> - setup_iomux_enet();
> -
> - bus = fec_get_miibus(IMX_FEC_BASE, -1);
> - if (!bus)
> - return -EINVAL;
> -
> - phydev = phy_find_by_mask(bus, ETH_PHY_MASK,
> PHY_INTERFACE_MODE_RGMII);
> - if (!phydev) {
> - ret = -EINVAL;
> - goto free_bus;
> - }
> -
> - debug("using phy at address %d\n", phydev->addr);
> - ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
> - if (ret)
> - goto free_phydev;
> -
> - return 0;
> -
> -free_phydev:
> - free(phydev);
> -free_bus:
> - free(bus);
> - return ret;
> -}
> -
> #ifdef CONFIG_VIDEO_IPUV3
> static void do
Re: [PATCH 4/4] mx6cuboxi: Convert to DM_ETH
On Thu, Jun 18, 2020 at 04:05:24PM -0300, Fabio Estevam wrote: > Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet > Driver Model. > > This also brings the benefit of restoring Ethernet functionality. > > Reported-by: Tom Rini > Signed-off-by: Fabio Estevam Tested-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/4] net: fec: Allow the PHY node to be retrieved
On Thu, Jun 18, 2020 at 04:05:22PM -0300, Fabio Estevam wrote:
> As we move towards driver model, it is required to let the FEC driver
> know how to properly deal with an Ethernet PHY subnode in the device tree.
>
> For example:
>
> &fec {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
> phy-handle = <&phy>;
> phy-mode = "rgmii-id";
> phy-reset-duration = <2>;
> phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
> status = "okay";
>
> mdio {
> #address-cells = <1>;
> #size-cells = <0>;
>
> phy: ethernet-phy@0 {
> reg = <0>;
> qca,clk-out-frequency = <12500>;
> };
> };
> };
>
> Currently the PHY node pointer is incorrectly associated with the
> Ethernel controller instead of the PHY node itself.
>
> This causes the PHY properties, such as "qca,clk-out-frequency" in
> the example above to not get parsed.
>
> Fix this problem by populating the phy_of_node node.
>
> Suggested-by: Vladimir Oltean
> Signed-off-by: Fabio Estevam
Tested-by: Tom Rini
--
Tom
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Description: PGP signature
Re: [PATCH 3/4] ARM: dts: imx6qdl-sr-som: Sync with kernel 5.8-rc1
On Thu, Jun 18, 2020 at 04:05:23PM -0300, Fabio Estevam wrote: > Sync the device tree with 5.8-rc1. > > It basically contains the following extra kernel commit: > > commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09 > Author: Russell King > Date: Wed Apr 15 16:44:17 2020 +0100 > > ARM: dts: imx6-sr-som: add ethernet PHY configuration > > Add ethernet PHY configuration ahead of removing the quirk that > configures the clocking mode for the PHY. The RGMII delay is > already set correctly. > > Signed-off-by: Russell King > Reviewed-by: Fabio Estevam > Signed-off-by: Shawn Guo > > , which passes the 'qca,clk-out-frequency' property and it is important > to specify the correct frequency generated by the AR8031. > > Signed-off-by: Fabio Estevam Tested-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/4] phy: atheros: ar8035: Fix clock output calculation
On Thu, Jun 18, 2020 at 04:05:21PM -0300, Fabio Estevam wrote:
> The clock ouput frequency is calculated incorrectly for AR8035 due to
> wrong masking of priv->clk_25m_reg and priv->clk_25m_mask.
>
> This same issue has been already fixed in the kernel by:
>
> commit b1f4c209d84057b6d40b939b6e4404854271d797
> Author: Oleksij Rempel
> Date: Wed Apr 1 11:57:32 2020 +0200
>
> net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035
>
> The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
> for the values that comprise the fields, not zero-bits-set.
>
> This patch fixes the clock frequency configuration for ATH8030 and
> ATH8035 Atheros PHYs by removing the erroneous "~".
>
> To reproduce this bug, configure the PHY with the device tree binding
> "qca,clk-out-frequency" and remove the machine specific PHY fixups.
>
> Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding")
> Signed-off-by: Oleksij Rempel
> Reported-by: Russell King
> Reviewed-by: Russell King
> Tested-by: Russell King
> Signed-off-by: David S. Miller
>
> Apply the same fix in the U-Boot driver.
>
> Tested on a i.MX6 Hummingboard.
>
> Signed-off-by: Fabio Estevam
> Reviewed-by: Michael Walle
Tested-by: Tom Rini
--
Tom
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Re: [PATCH v2 1/9] env: add absolute path at CONFIG_ENV_EXT4_FILE
On Tue, Jun 16, 2020 at 09:40:40AM +0200, Patrick Delaunay wrote: > Add the absolute path to the default value of > CONFIG_ENV_EXT4_FILE = "/uboot.env". > > This patch avoid the error : > Saving Environment to EXT4... File System is consistent > Please supply Absolute path > > Signed-off-by: Patrick Delaunay Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH 4/4] mx6cuboxi: Convert to DM_ETH
Hi Fabio,
Thanks for your debug and fix. Small nits below.
On Thu, Jun 18 2020, Fabio Estevam wrote:
> Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet
> Driver Model.
>
> This also brings the benefit of restoring Ethernet functionality.
>
> Reported-by: Tom Rini
> Signed-off-by: Fabio Estevam
> ---
> board/solidrun/mx6cuboxi/mx6cuboxi.c | 123 ---
> configs/mx6cuboxi_defconfig | 4 +
> include/configs/mx6cuboxi.h | 6 --
> 3 files changed, 21 insertions(+), 112 deletions(-)
>
> diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
> b/board/solidrun/mx6cuboxi/mx6cuboxi.c
> index 94707bccb2..225fea2cb2 100644
> --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
> +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
> @@ -17,7 +17,6 @@
> #include
> #include
> #include
> -#include
> #include
> #include
> #include
> @@ -34,7 +33,6 @@
> #include
> #include
> #include
Do we still need this header?
> -#include
> #include
> #include
> #include
> @@ -237,110 +235,6 @@ int board_mmc_init(bd_t *bis)
> return 0;
> }
>
> -static iomux_v3_cfg_t const enet_pads[] = {
> - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
The definitions of these ENET_PAD_CTRL* macros can go away as well.
baruch
> - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - /* AR8035 reset */
> - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
> - /* AR8035 interrupt */
> - IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
...
--
~. .~ Tk Open Systems
=}ooO--U--Ooo{=
- bar...@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
Re: [PATCH v2 2/9] env: ext4: set gd->env_valid
On Tue, Jun 16, 2020 at 09:40:41AM +0200, Patrick Delaunay wrote: > Add a missing initialization of gd->env_valid in env_ext4_load > as it is already done in some other env device. > > Set gd->env_valid = ENV_VALID in env_ext4_save() and env_ext4_load(). > > This patch allows to have a correct information in 'env info' command. > > Signed-off-by: Patrick Delaunay Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: Can't access mmc #0 on mt7623 when booted from external SD
On Thu, 2020-06-18 at 16:52 +0100, David Woodhouse wrote:
> So... whose bug is that? :)
Looks like the pinctrl driver. This *ought* to work (with the caveat
that I really ought to make two pinctrl setups and change between them
according to the voltage, like the Linux DT and mtk-sd driver do).
--- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
@@ -133,12 +133,14 @@
"MSDC0_DAT2", "MSDC0_DAT3",
"MSDC0_DAT4",
"MSDC0_DAT5", "MSDC0_DAT6",
"MSDC0_DAT7";
input-enable;
- bias-pull-up;
+ drive-strength = <2>;
+ bias-pull-up = <3>;
};
conf-clk {
pins = "MSDC0_CLK";
- bias-pull-down;
+ drive-strength = <2>;
+ bias-pull-down = <3>;
};
conf-rst {
But it doesn't work. Partly because the U-Boot mtk pinctrl driver
doesn't support the R0 R1 bits encoded in that <3>, and partly because
it doesn't *even* get pullup/pulldown right at all; it sets the bit in
the GPIO_PULLSEL registers but *not* the PUPD bit in the correct
register for MSDC and other pins.
smime.p7s
Description: S/MIME cryptographic signature
Re: [PATCH v2 5/9] sandbox: support the change of env location
On Tue, Jun 16, 2020 at 09:40:44AM +0200, Patrick Delaunay wrote: > Add support of environment location with a new sandbox command > 'env_loc'. > > When the user change the environment location with the command > 'env_loc ' the env is reinitialized and saved; > the GD_FLG_ENV_DEFAULT flag is also updated. > > When the user set the same env location, the environment is > re-loaded. > > Signed-off-by: Patrick Delaunay > --- > > Changes in v2: > - change cmd_tbl_t to struct cmd_tbl > > board/sandbox/sandbox.c | 42 - > 1 file changed, 41 insertions(+), 1 deletion(-) This is for testing, which is why it's on sandbox? But I think we should have this be a generic opt-in feature as changing where environment is saved at run time has use cases when we have multiple available. Thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 3/9] env: correctly handle result in env_init
On Tue, Jun 16, 2020 at 09:40:42AM +0200, Patrick Delaunay wrote:
> Don't return error with ret=-ENOENT when the optional ops drv->init
> is absent but only if env_driver_lookup doesn't found driver.
>
> This patch correct an issue for the code
> if (!env_init())
> env_load()
> When only ext4 is supported (CONFIG_ENV_IS_IN_EXT4),
> as the backend env/ext4.c doesn't define an ops .init
>
> Signed-off-by: Patrick Delaunay
> ---
>
> (no changes since v1)
>
> env/env.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/env/env.c b/env/env.c
> index dcc25c030b..819c88f729 100644
> --- a/env/env.c
> +++ b/env/env.c
> @@ -295,7 +295,10 @@ int env_init(void)
> int prio;
>
> for (prio = 0; (drv = env_driver_lookup(ENVOP_INIT, prio)); prio++) {
> - if (!drv->init || !(ret = drv->init()))
> + ret = 0;
> + if (drv->init)
> + ret = drv->init();
> + if (!ret)
> env_set_inited(drv->location);
>
> debug("%s: Environment %s init done (ret=%d)\n", __func__,
I'm adding in Marek here because this reminds me of similar questions /
concerns I had looking in to his series. At root, I think we're not
being consistent in each of our env backing implementations about where
flags such as ENV_VALID are set, and return values / checks of
functions.
Just outside of the start of the patch context here, we set ret to
-ENOENT and just past this, if still -ENOENT we say ENV_VALID and point
at the default environment.
But, I don't follow the patch commit message here. If we don't have
drv->init we call env_set_inited(drv->location) but we won't have change
ret to 0, which means that later on down the function we go back to
default environment.
So isn't this a problem in most environment cases then? Thanks!
--
Tom
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[PATCH 3/4] ARM: dts: imx6qdl-sr-som: Sync with kernel 5.8-rc1
Sync the device tree with 5.8-rc1.
It basically contains the following extra kernel commit:
commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09
Author: Russell King
Date: Wed Apr 15 16:44:17 2020 +0100
ARM: dts: imx6-sr-som: add ethernet PHY configuration
Add ethernet PHY configuration ahead of removing the quirk that
configures the clocking mode for the PHY. The RGMII delay is
already set correctly.
Signed-off-by: Russell King
Reviewed-by: Fabio Estevam
Signed-off-by: Shawn Guo
, which passes the 'qca,clk-out-frequency' property and it is important
to specify the correct frequency generated by the AR8031.
Signed-off-by: Fabio Estevam
---
arch/arm/dts/imx6qdl-sr-som.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/dts/imx6qdl-sr-som.dtsi b/arch/arm/dts/imx6qdl-sr-som.dtsi
index 6d7f6b9035..b06577808f 100644
--- a/arch/arm/dts/imx6qdl-sr-som.dtsi
+++ b/arch/arm/dts/imx6qdl-sr-som.dtsi
@@ -53,10 +53,21 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
+ phy-handle = <&phy>;
phy-mode = "rgmii-id";
phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@0 {
+ reg = <0>;
+ qca,clk-out-frequency = <12500>;
+ };
+ };
};
&iomuxc {
--
2.17.1
[PATCH 2/4] net: fec: Allow the PHY node to be retrieved
As we move towards driver model, it is required to let the FEC driver
know how to properly deal with an Ethernet PHY subnode in the device tree.
For example:
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-handle = <&phy>;
phy-mode = "rgmii-id";
phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@0 {
reg = <0>;
qca,clk-out-frequency = <12500>;
};
};
};
Currently the PHY node pointer is incorrectly associated with the
Ethernel controller instead of the PHY node itself.
This causes the PHY properties, such as "qca,clk-out-frequency" in
the example above to not get parsed.
Fix this problem by populating the phy_of_node node.
Suggested-by: Vladimir Oltean
Signed-off-by: Fabio Estevam
---
drivers/net/fec_mxc.c | 7 +--
drivers/net/fec_mxc.h | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 9ae2db033e..992180df86 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1294,7 +1294,7 @@ static const struct eth_ops fecmxc_ops = {
.read_rom_hwaddr= fecmxc_read_rom_hwaddr,
};
-static int device_get_phy_addr(struct udevice *dev)
+static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
{
struct ofnode_phandle_args phandle_args;
int reg;
@@ -1305,6 +1305,8 @@ static int device_get_phy_addr(struct udevice *dev)
return -ENODEV;
}
+ priv->phy_of_node = phandle_args.node;
+
reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
return reg;
@@ -1315,7 +1317,7 @@ static int fec_phy_init(struct fec_priv *priv, struct
udevice *dev)
struct phy_device *phydev;
int addr;
- addr = device_get_phy_addr(dev);
+ addr = device_get_phy_addr(priv, dev);
#ifdef CONFIG_FEC_MXC_PHYADDR
addr = CONFIG_FEC_MXC_PHYADDR;
#endif
@@ -1325,6 +1327,7 @@ static int fec_phy_init(struct fec_priv *priv, struct
udevice *dev)
return -ENODEV;
priv->phydev = phydev;
+ priv->phydev->node = priv->phy_of_node;
phy_config(phydev);
return 0;
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 0e8f08a51a..659d62646f 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -250,6 +250,7 @@ struct fec_priv {
struct mii_dev *bus;
#ifdef CONFIG_PHYLIB
struct phy_device *phydev;
+ ofnode phy_of_node;
#else
int phy_id;
int (*mii_postcall)(int);
--
2.17.1
[PATCH 4/4] mx6cuboxi: Convert to DM_ETH
Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet
Driver Model.
This also brings the benefit of restoring Ethernet functionality.
Reported-by: Tom Rini
Signed-off-by: Fabio Estevam
---
board/solidrun/mx6cuboxi/mx6cuboxi.c | 123 ---
configs/mx6cuboxi_defconfig | 4 +
include/configs/mx6cuboxi.h | 6 --
3 files changed, 21 insertions(+), 112 deletions(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 94707bccb2..225fea2cb2 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -17,7 +17,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -34,7 +33,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -237,110 +235,6 @@ int board_mmc_init(bd_t *bis)
return 0;
}
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* AR8035 reset */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- /* AR8035 interrupt */
- IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* GPIO16 -> AR8035 25MHz */
- IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-};
-
-static void setup_iomux_enet(void)
-{
- struct gpio_desc desc;
- int ret;
-
- SETUP_IOMUX_PADS(enet_pads);
-
- ret = dm_gpio_lookup_name("GPIO4_15", &desc);
- if (ret) {
- printf("%s: phy reset lookup failed\n", __func__);
- return;
- }
-
- ret = dm_gpio_request(&desc, "phy-reset");
- if (ret) {
- printf("%s: phy reset request failed\n", __func__);
- return;
- }
-
- gpio_direction_output(ETH_PHY_RESET, 0);
- mdelay(10);
- gpio_set_value(ETH_PHY_RESET, 1);
- udelay(100);
-
- gpio_free_list_nodev(&desc, 1);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
-#define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4))
-
-int board_eth_init(bd_t *bis)
-{
- struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct mii_dev *bus;
- struct phy_device *phydev;
-
- int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
- if (ret)
- return ret;
-
- /* set gpr1[ENET_CLK_SEL] */
- setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
-
- setup_iomux_enet();
-
- bus = fec_get_miibus(IMX_FEC_BASE, -1);
- if (!bus)
- return -EINVAL;
-
- phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
- if (!phydev) {
- ret = -EINVAL;
- goto free_bus;
- }
-
- debug("using phy at address %d\n", phydev->addr);
- ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
- if (ret)
- goto free_phydev;
-
- return 0;
-
-free_phydev:
- free(phydev);
-free_bus:
- free(bus);
- return ret;
-}
-
#ifdef CONFIG_VIDEO_IPUV3
static void do_enable_hdmi(struct display_info_t const *dev)
{
@@ -433,6 +327,21 @@ static int setup_display(void)
}
#endif /* CONFIG_VIDEO_IPUV3 */
+static int setup_fec(void)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ ret = enable_fec_anatop_clock(0, ENET_25MHZ);
+ if (ret)
+ return ret;
+
[PATCH 1/4] phy: atheros: ar8035: Fix clock output calculation
The clock ouput frequency is calculated incorrectly for AR8035 due to
wrong masking of priv->clk_25m_reg and priv->clk_25m_mask.
This same issue has been already fixed in the kernel by:
commit b1f4c209d84057b6d40b939b6e4404854271d797
Author: Oleksij Rempel
Date: Wed Apr 1 11:57:32 2020 +0200
net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035
The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
for the values that comprise the fields, not zero-bits-set.
This patch fixes the clock frequency configuration for ATH8030 and
ATH8035 Atheros PHYs by removing the erroneous "~".
To reproduce this bug, configure the PHY with the device tree binding
"qca,clk-out-frequency" and remove the machine specific PHY fixups.
Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding")
Signed-off-by: Oleksij Rempel
Reported-by: Russell King
Reviewed-by: Russell King
Tested-by: Russell King
Signed-off-by: David S. Miller
Apply the same fix in the U-Boot driver.
Tested on a i.MX6 Hummingboard.
Signed-off-by: Fabio Estevam
Reviewed-by: Michael Walle
---
drivers/net/phy/atheros.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 13f7275d17..f922fecd6b 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -275,11 +275,10 @@ static int ar803x_of_init(struct phy_device *phydev)
* Fixup for the AR8035 which only has two bits. The two
* remaining bits map to the same frequencies.
*/
- if (phydev->drv->uid == AR8035_PHY_ID) {
- u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK;
- priv->clk_25m_mask &= ~clear;
- priv->clk_25m_reg &= ~clear;
+ if (phydev->drv->uid == AR8035_PHY_ID) {
+ priv->clk_25m_reg &= AR8035_CLK_25M_MASK;
+ priv->clk_25m_mask &= AR8035_CLK_25M_MASK;
}
}
--
2.17.1
[PATCH] ARM: dts: stm32: Reinstate card detect behavior on DHSOM
The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far
unsupported, reinstate the old cd-gpios behavior until this handling
is fully implemented. This permits the DHSOM to boot from SD again,
without this patch the card detect fails.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index 75d75266e8..df63ad4a24 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -273,6 +273,9 @@
&sdmmc1 {
u-boot,dm-spl;
+ broken-cd;
+ /delete-property/ cd-gpios;
+ /delete-property/ disable-wp;
};
&sdmmc1_b4_pins_a {
--
2.27.0
Re: Mainlining advice for new (MStar/SigmaStar) ARMv7 SoC family
On Wed, Jun 17, 2020 at 12:44:08AM +0900, Daniel Palmer wrote: > Hi all, > > I'm attempting to get initial support for MStar/Sigmastar's family of > ARMv7 chips into Linux > and I thought I should probably at least attempt to mainling the > u-boot support while I'm at it. > > I did some googling and couldn't find a "how to mainline a new SoC" > guide for u-boot so if > possible could I get some advice on how I should go about this. > > Right now I have a very janky tree that can either piggy back the > vendor's second stage > bootloader (bootloader after bootrom) or on some of the chips produce > an SPL that can > run straight after the bootrom exits. > > I need to chop it up into acceptable parts but I'm not sure how that would > look. > For Linux I'm attempting to get in a small patch set[0] that adds the > initial device tree prefixes > and then adds just enough machine specific bits to get to a shell from > an initramfs. > > For u-boot would enough to load a kernel very slowly via loady be a good > target? > As the platform is device tree based do I need to wait until my > prefixes get accepted to even start? Well, lets see. It would be good to get the DTS stuff sorted out upstream first, but so long a you keep U-Boot in sync, that's fine. It's also fine to piggyback on a vendor prior stage if we can't yet (or won't, period) be able to replace it. Similar to how for Linux you're aiming to start with UART and initramfs, UART and any drivers that already exist because of shared / re-used IP blocks is a good first step, and then add drivers on top. -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/2] riscv: Use correct version of fdtdec_get_addr_size
On Thu, Jun 18, 2020 at 12:19 AM Bin Meng wrote:
>
> Hi Atish,
>
> On Thu, Jun 18, 2020 at 3:04 PM Atish Patra wrote:
> >
> > On Wed, Jun 17, 2020 at 5:46 PM Bin Meng wrote:
> > >
> > > Hi Atish,
> > >
> > > On Thu, Jun 18, 2020 at 7:51 AM Atish Patra wrote:
> > > >
> > > > fdtdec_get_addr_size uses a fixed value for address_cells & size_cells
> > > > which may not work correctly always. fdtdec_get_addr_size_no_parent
> > > > will automatically calculate the cell sizes from parent but not
> > > > optimized especially when parent node is already available with the
> > > > caller.
> > > >
> > > > Use fdtdec_get_addr_size_auto_parent that automatically calculate the
> > > > cell sizes and optimized for the given usecase.
> > > >
> > > > Signed-off-by: Atish Patra
> > > > ---
> > > > arch/riscv/lib/fdt_fixup.c | 2 +-
> > > > lib/fdtdec.c | 3 ++-
> > > > 2 files changed, 3 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
> > > > index 6db48ad04a56..f2ec37b57b15 100644
> > > > --- a/arch/riscv/lib/fdt_fixup.c
> > > > +++ b/arch/riscv/lib/fdt_fixup.c
> > > > @@ -44,7 +44,7 @@ int riscv_fdt_copy_resv_mem_node(const void *src,
> > > > void *dst)
> > > > fdt_for_each_subnode(node, src, offset) {
> > > > name = fdt_get_name(src, node, NULL);
> > > >
> > > > - addr = fdtdec_get_addr_size_auto_noparent(src, node,
> > > > + addr = fdtdec_get_addr_size_auto_parent(src, offset,
> > > > node,
> > > > "reg", 0,
> > > > &size,
> > > > false);
> > > > if (addr == FDT_ADDR_T_NONE) {
> > > > diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> > > > index 1f2b763acc31..b62eb142ccc3 100644
> > > > --- a/lib/fdtdec.c
> > > > +++ b/lib/fdtdec.c
> > > > @@ -1296,7 +1296,8 @@ int fdtdec_add_reserved_memory(void *blob, const
> > > > char *basename,
> > > > const char *name = fdt_get_name(blob, node, NULL);
> > > > phys_addr_t addr, size;
> > > >
> > > > - addr = fdtdec_get_addr_size(blob, node, "reg", &size);
> > > > + addr = fdtdec_get_addr_size_auto_parent(blob, parent,
> > > > node,
> > > > + "reg", 0,
> > > > &size, false);
> > >
> > > There is already a patch for this change (although slightly different,
> > > but fixed the same thing)
> > > http://patchwork.ozlabs.org/project/uboot/patch/1591767391-2669-2-git-send-email-bmeng...@gmail.com/
> > >
> >
> > Ah I missed that. I used this version compared to
> > fdtdec_get_addr_size_fixed because of the following comment
> > in the header file.
> >
> > "You probably don't want to use this function directly except to parse
> > non-standard properties, and never to parse the "reg" property. Instead,
> > use one of the "auto" variants below, which automatically honor the
> > #address-cells and #size-cells properties in the parent node."
> >
> > Do you want to update your patch or I can send v2 by splitting riscv &
> > generic changes ?
> > Please let me know your preference.
>
> I intended to use fdtdec_get_addr_size_fixed() because na and ns are
> already known at this point. Calling
> fdtdec_get_addr_size_auto_parent() duplicates the efforts of getting
> values of na and ns, and is not necessary.
>
Yes. But the duplication effort is just reading two parameters.
Anyways, it's not a big deal. I will drop the generic fix from my
patch and resent after
rebasing on top of your series.
> >
> > > Please also send them in separate patches in the future, as one is
> > > RISC-V specific and the other one is for generic codes.
>
> Regards,
> Bin
--
Regards,
Atish
Re: [GIT PULL] TI changes for v2020.10 next
On Thu, Jun 18, 2020 at 07:25:43PM +0530, Lokesh Vutla wrote: > Hi Tom, > Please find the pull request for v2020.10 next containing TI specific > changes. > > Travis-CI build: > https://travis-ci.org/github/lokeshvutla/u-boot/builds/698883325 > > The following changes since commit be79009f3b9bbdbce283e67a865121e576d790ea: > > Merge tag 'u-boot-imx-20200609' of > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-06-09 09:17:24 > -0400) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-ti.git tags/ti-v2020.10-next > > for you to fetch changes up to c0a8d6e1e67cc7feee5c9e6c7e8c13bb953734f1: > > ARM: da850-evm: Remove SPI from SPL when booting from NAND (2020-06-16 > 17:00:50 +0530) > Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL u-boot] Please pull u-boot-amlogic-20200618
On Thu, Jun 18, 2020 at 03:44:11PM +0200, Neil Armstrong wrote: > Hi Tom, > > This PR moves the amlogic boards documentation in doc/board/amlogic in RsT > format. > > > The CI job is at > https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic/pipelines/3707 > > Thanks, > Neil > > The following changes since commit 9cb895203a46654f7ee6dd95be5c8ab05e4dfbd3: > > Merge tag 'u-boot-stm32-20200616' of > https://gitlab.denx.de/u-boot/custodians/u-boot-stm (2020-06-16 09:18:56 > -0400) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic.git > tags/u-boot-amlogic-20200618 > > for you to fetch changes up to 9c55f5d11260c5aa0f91d8cb32aa0ad00910659d: > > board: amlogic: add board doc files to MAINTAINERS (2020-06-18 10:24:13 > +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH v3 3/4] db-88f6281-bp-nand: Enable DM_SPI/SPI_FLASH
Enable DM_SPI, DM_SPI_FLASH for db-88f6281-bp-nand board. Cc: Chris Packham Signed-off-by: Jagan Teki --- Changes for v3: - new patch configs/db-88f6281-bp-nand_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/db-88f6281-bp-nand_defconfig b/configs/db-88f6281-bp-nand_defconfig index f98e462d42..5a580f28b5 100644 --- a/configs/db-88f6281-bp-nand_defconfig +++ b/configs/db-88f6281-bp-nand_defconfig @@ -20,7 +20,6 @@ CONFIG_CMD_DM=y CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -43,7 +42,7 @@ CONFIG_DM=y CONFIG_MVSATA_IDE=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y @@ -53,6 +52,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y CONFIG_DM_USB=y -- 2.25.1
[PATCH v3 4/4] arm: Remove netspace_v2 board
This board has not been converted to CONFIG_DM by the deadline. Remove it. Patch-cc: Simon Guinot Signed-off-by: Jagan Teki --- Changes for v3: - new patch arch/arm/mach-kirkwood/Kconfig| 4 - board/LaCie/netspace_v2/Kconfig | 12 -- board/LaCie/netspace_v2/MAINTAINERS | 14 -- board/LaCie/netspace_v2/Makefile | 10 -- board/LaCie/netspace_v2/kwbimage-is2.cfg | 149 -- board/LaCie/netspace_v2/kwbimage-ns2l.cfg | 149 -- board/LaCie/netspace_v2/kwbimage.cfg | 149 -- board/LaCie/netspace_v2/netspace_v2.c | 120 - board/LaCie/netspace_v2/netspace_v2.h | 22 configs/inetspace_v2_defconfig| 53 configs/netspace_lite_v2_defconfig| 53 configs/netspace_max_v2_defconfig | 53 configs/netspace_mini_v2_defconfig| 48 --- configs/netspace_v2_defconfig | 53 14 files changed, 889 deletions(-) delete mode 100644 board/LaCie/netspace_v2/Kconfig delete mode 100644 board/LaCie/netspace_v2/MAINTAINERS delete mode 100644 board/LaCie/netspace_v2/Makefile delete mode 100644 board/LaCie/netspace_v2/kwbimage-is2.cfg delete mode 100644 board/LaCie/netspace_v2/kwbimage-ns2l.cfg delete mode 100644 board/LaCie/netspace_v2/kwbimage.cfg delete mode 100644 board/LaCie/netspace_v2/netspace_v2.c delete mode 100644 board/LaCie/netspace_v2/netspace_v2.h delete mode 100644 configs/inetspace_v2_defconfig delete mode 100644 configs/netspace_lite_v2_defconfig delete mode 100644 configs/netspace_max_v2_defconfig delete mode 100644 configs/netspace_mini_v2_defconfig delete mode 100644 configs/netspace_v2_defconfig diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index ad6aef45bf..899c079773 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -35,9 +35,6 @@ config TARGET_KM_KIRKWOOD bool "KM Kirkwood Board" select VENDOR_KM -config TARGET_NETSPACE_V2 - bool "LaCie netspace_v2 Board" - config TARGET_IB62X0 bool "ib62x0 Board" @@ -77,7 +74,6 @@ source "board/cloudengines/pogo_e02/Kconfig" source "board/d-link/dns325/Kconfig" source "board/iomega/iconnect/Kconfig" source "board/keymile/Kconfig" -source "board/LaCie/netspace_v2/Kconfig" source "board/raidsonic/ib62x0/Kconfig" source "board/Seagate/dockstar/Kconfig" source "board/Seagate/goflexhome/Kconfig" diff --git a/board/LaCie/netspace_v2/Kconfig b/board/LaCie/netspace_v2/Kconfig deleted file mode 100644 index 930b822dfb..00 --- a/board/LaCie/netspace_v2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_NETSPACE_V2 - -config SYS_BOARD - default "netspace_v2" - -config SYS_VENDOR - default "LaCie" - -config SYS_CONFIG_NAME - default "lacie_kw" - -endif diff --git a/board/LaCie/netspace_v2/MAINTAINERS b/board/LaCie/netspace_v2/MAINTAINERS deleted file mode 100644 index 55fd50d4eb..00 --- a/board/LaCie/netspace_v2/MAINTAINERS +++ /dev/null @@ -1,14 +0,0 @@ -NETSPACE_V2 BOARD -M: Simon Guinot -S: Maintained -F: board/LaCie/netspace_v2/ -F: include/configs/lacie_kw.h -F: configs/inetspace_v2_defconfig -F: configs/netspace_max_v2_defconfig -F: configs/netspace_v2_defconfig - -NETSPACE_LITE_V2 BOARD -#M:- -S: Maintained -F: configs/netspace_lite_v2_defconfig -F: configs/netspace_mini_v2_defconfig diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile deleted file mode 100644 index a6270bdd4b..00 --- a/board/LaCie/netspace_v2/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Simon Guinot -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar - -obj-y := netspace_v2.o ../common/common.o diff --git a/board/LaCie/netspace_v2/kwbimage-is2.cfg b/board/LaCie/netspace_v2/kwbimage-is2.cfg deleted file mode 100644 index 50f584ae70..00 --- a/board/LaCie/netspace_v2/kwbimage-is2.cfg +++ /dev/null @@ -1,149 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Simon Guinot -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1B1B1B9B - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000618 # DDR Configuration register -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit
[PATCH v3 2/4] arm: Remove d2net_v2 board
This board has not been converted to CONFIG_DM by the deadline. Remove it. Cc: Simon Guinot Signed-off-by: Jagan Teki --- Changes for v3: - new patch arch/arm/mach-kirkwood/Kconfig | 4 - board/LaCie/net2big_v2/Kconfig | 12 -- board/LaCie/net2big_v2/MAINTAINERS | 7 - board/LaCie/net2big_v2/Makefile | 13 -- board/LaCie/net2big_v2/kwbimage.cfg | 149 board/LaCie/net2big_v2/net2big_v2.c | 257 board/LaCie/net2big_v2/net2big_v2.h | 28 --- configs/d2net_v2_defconfig | 53 -- configs/net2big_v2_defconfig| 53 -- include/configs/lacie_kw.h | 152 10 files changed, 728 deletions(-) delete mode 100644 board/LaCie/net2big_v2/Kconfig delete mode 100644 board/LaCie/net2big_v2/MAINTAINERS delete mode 100644 board/LaCie/net2big_v2/Makefile delete mode 100644 board/LaCie/net2big_v2/kwbimage.cfg delete mode 100644 board/LaCie/net2big_v2/net2big_v2.c delete mode 100644 board/LaCie/net2big_v2/net2big_v2.h delete mode 100644 configs/d2net_v2_defconfig delete mode 100644 configs/net2big_v2_defconfig delete mode 100644 include/configs/lacie_kw.h diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index ae44cb665e..ad6aef45bf 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -35,9 +35,6 @@ config TARGET_KM_KIRKWOOD bool "KM Kirkwood Board" select VENDOR_KM -config TARGET_NET2BIG_V2 - bool "LaCie 2Big Network v2 NAS Board" - config TARGET_NETSPACE_V2 bool "LaCie netspace_v2 Board" @@ -80,7 +77,6 @@ source "board/cloudengines/pogo_e02/Kconfig" source "board/d-link/dns325/Kconfig" source "board/iomega/iconnect/Kconfig" source "board/keymile/Kconfig" -source "board/LaCie/net2big_v2/Kconfig" source "board/LaCie/netspace_v2/Kconfig" source "board/raidsonic/ib62x0/Kconfig" source "board/Seagate/dockstar/Kconfig" diff --git a/board/LaCie/net2big_v2/Kconfig b/board/LaCie/net2big_v2/Kconfig deleted file mode 100644 index ba460dba45..00 --- a/board/LaCie/net2big_v2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_NET2BIG_V2 - -config SYS_BOARD - default "net2big_v2" - -config SYS_VENDOR - default "LaCie" - -config SYS_CONFIG_NAME - default "lacie_kw" - -endif diff --git a/board/LaCie/net2big_v2/MAINTAINERS b/board/LaCie/net2big_v2/MAINTAINERS deleted file mode 100644 index 8fec70315f..00 --- a/board/LaCie/net2big_v2/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -NET2BIG_V2 BOARD -M: Simon Guinot -S: Maintained -F: board/LaCie/net2big_v2/ -F: include/configs/lacie_kw.h -F: configs/d2net_v2_defconfig -F: configs/net2big_v2_defconfig diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile deleted file mode 100644 index 3d12b72812..00 --- a/board/LaCie/net2big_v2/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Simon Guinot -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar - -obj-y := net2big_v2.o ../common/common.o -ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),) -obj-y += ../common/cpld-gpio-bus.o -endif diff --git a/board/LaCie/net2big_v2/kwbimage.cfg b/board/LaCie/net2big_v2/kwbimage.cfg deleted file mode 100644 index 3897a1197a..00 --- a/board/LaCie/net2big_v2/kwbimage.cfg +++ /dev/null @@ -1,149 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Simon Guinot -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1B1B1B9B - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000C30 # DDR Configuration register -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x38743000 # DDR Controller Control Low -# bit 4:0=addr/cmd in smame cycle -# bit 5:0=clk is driven during self refresh, we don't care for APX -# bit 6:0=use recommended falling edge of clk for addr/cmd -# bit14:0=input buffer always powered up -# bit18:1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31:0=no additional STARTBURST delay - -DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +
[PATCH v3 0/4] spi: kirkwood: dm-conversion (part4)
Series of kirkwood boards to switch DM_SPI and drop which are not DM enabled still. Any inputs? Jagan. Bhargav Shah (1): spi: kirkwood: Drop nondm code Jagan Teki (3): arm: Remove d2net_v2 board db-88f6281-bp-nand: Enable DM_SPI/SPI_FLASH arm: Remove netspace_v2 board arch/arm/mach-kirkwood/Kconfig| 8 - board/LaCie/net2big_v2/Kconfig| 12 - board/LaCie/net2big_v2/MAINTAINERS| 7 - board/LaCie/net2big_v2/Makefile | 13 -- board/LaCie/net2big_v2/kwbimage.cfg | 149 - board/LaCie/net2big_v2/net2big_v2.c | 257 -- board/LaCie/net2big_v2/net2big_v2.h | 28 --- board/LaCie/netspace_v2/Kconfig | 12 - board/LaCie/netspace_v2/MAINTAINERS | 14 -- board/LaCie/netspace_v2/Makefile | 10 - board/LaCie/netspace_v2/kwbimage-is2.cfg | 149 - board/LaCie/netspace_v2/kwbimage-ns2l.cfg | 149 - board/LaCie/netspace_v2/kwbimage.cfg | 149 - board/LaCie/netspace_v2/netspace_v2.c | 120 -- board/LaCie/netspace_v2/netspace_v2.h | 22 -- configs/d2net_v2_defconfig| 53 - configs/db-88f6281-bp-nand_defconfig | 4 +- configs/inetspace_v2_defconfig| 53 - configs/net2big_v2_defconfig | 53 - configs/netspace_lite_v2_defconfig| 53 - configs/netspace_max_v2_defconfig | 53 - configs/netspace_mini_v2_defconfig| 48 configs/netspace_v2_defconfig | 53 - drivers/spi/Kconfig | 12 +- drivers/spi/kirkwood_spi.c| 136 ++-- include/configs/lacie_kw.h| 152 - scripts/config_whitelist.txt | 1 - 27 files changed, 21 insertions(+), 1749 deletions(-) delete mode 100644 board/LaCie/net2big_v2/Kconfig delete mode 100644 board/LaCie/net2big_v2/MAINTAINERS delete mode 100644 board/LaCie/net2big_v2/Makefile delete mode 100644 board/LaCie/net2big_v2/kwbimage.cfg delete mode 100644 board/LaCie/net2big_v2/net2big_v2.c delete mode 100644 board/LaCie/net2big_v2/net2big_v2.h delete mode 100644 board/LaCie/netspace_v2/Kconfig delete mode 100644 board/LaCie/netspace_v2/MAINTAINERS delete mode 100644 board/LaCie/netspace_v2/Makefile delete mode 100644 board/LaCie/netspace_v2/kwbimage-is2.cfg delete mode 100644 board/LaCie/netspace_v2/kwbimage-ns2l.cfg delete mode 100644 board/LaCie/netspace_v2/kwbimage.cfg delete mode 100644 board/LaCie/netspace_v2/netspace_v2.c delete mode 100644 board/LaCie/netspace_v2/netspace_v2.h delete mode 100644 configs/d2net_v2_defconfig delete mode 100644 configs/inetspace_v2_defconfig delete mode 100644 configs/net2big_v2_defconfig delete mode 100644 configs/netspace_lite_v2_defconfig delete mode 100644 configs/netspace_max_v2_defconfig delete mode 100644 configs/netspace_mini_v2_defconfig delete mode 100644 configs/netspace_v2_defconfig delete mode 100644 include/configs/lacie_kw.h -- 2.25.1
[PATCH v3 1/4] spi: kirkwood: Drop nondm code
From: Bhargav Shah
Drop the nondm code from kirkwood_spi.c since there
is no board or any other code using for it.
Signed-off-by: Bhargav Shah
Signed-off-by: Jagan Teki
---
Changes for v3:
- updated commit message
- updated config_whitelist.txt
drivers/spi/Kconfig | 12 ++--
drivers/spi/kirkwood_spi.c | 136 ---
scripts/config_whitelist.txt | 1 -
3 files changed, 19 insertions(+), 130 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 09b9cb17d8..0945177efb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -162,6 +162,12 @@ config ICH_SPI
access the SPI NOR flash on platforms embedding this Intel
ICH IP core.
+config KIRKWOOD_SPI
+ bool "Marvell Kirkwood SPI Driver"
+ help
+ Enable support for SPI on various Marvell SoCs, such as
+ Kirkwood and Armada 375.
+
config MESON_SPIFC
bool "Amlogic Meson SPI Flash Controller driver"
depends on ARCH_MESON
@@ -417,12 +423,6 @@ config SH_QSPI
Enable the Renesas Quad SPI controller driver. This driver can be
used on Renesas SoCs.
-config KIRKWOOD_SPI
- bool "Marvell Kirkwood SPI Driver"
- help
- Enable support for SPI on various Marvell SoCs, such as
- Kirkwood and Armada 375.
-
config MXC_SPI
bool "MXC SPI Driver"
help
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 3986b06b25..92dc2e13c5 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -19,6 +19,19 @@
#endif
#include
+struct mvebu_spi_dev {
+ boolis_errata_50mhz_ac;
+};
+
+struct mvebu_spi_platdata {
+ struct kwspi_registers *spireg;
+ bool is_errata_50mhz_ac;
+};
+
+struct mvebu_spi_priv {
+ struct kwspi_registers *spireg;
+};
+
static void _spi_cs_activate(struct kwspi_registers *reg)
{
setbits_le32(®->ctrl, KWSPI_CSN_ACT);
@@ -94,128 +107,6 @@ static int _spi_xfer(struct kwspi_registers *reg, unsigned
int bitlen,
return 0;
}
-#ifndef CONFIG_DM_SPI
-
-static struct kwspi_registers *spireg =
- (struct kwspi_registers *)MVEBU_SPI_BASE;
-
-#ifdef CONFIG_ARCH_KIRKWOOD
-static u32 cs_spi_mpp_back[2];
-#endif
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct spi_slave *slave;
- u32 data;
-#ifdef CONFIG_ARCH_KIRKWOOD
- static const u32 kwspi_mpp_config[2][2] = {
- { MPP0_SPI_SCn, 0 }, /* if cs == 0 */
- { MPP7_SPI_SCn, 0 } /* if cs != 0 */
- };
-#endif
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- slave = spi_alloc_slave_base(bus, cs);
- if (!slave)
- return NULL;
-
- writel(KWSPI_SMEMRDY, &spireg->ctrl);
-
- /* calculate spi clock prescaller using max_hz */
- data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
- data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
- data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
-
- /* program spi clock prescaller using max_hz */
- writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
- debug("data = 0x%08x\n", data);
-
- writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
- writel(KWSPI_IRQMASK, &spireg->irq_mask);
-
-#ifdef CONFIG_ARCH_KIRKWOOD
- /* program mpp registers to select SPI_CSn */
- kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
-#endif
-
- return slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-#ifdef CONFIG_ARCH_KIRKWOOD
- kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
-#endif
- free(slave);
-}
-
-__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
-{
- return 0;
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- return board_spi_claim_bus(slave);
-}
-
-__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
-{
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- board_spi_release_bus(slave);
-}
-
-#ifndef CONFIG_SPI_CS_IS_VALID
-/*
- * you can define this function board specific
- * define above CONFIG in board specific config file and
- * provide the function in board specific src file
- */
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && (cs == 0 || cs == 1);
-}
-#endif
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- _spi_cs_activate(spireg);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- _spi_cs_deactivate(spireg);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-const void *dout, void *din, unsigned long flags)
-{
- return _spi_xfer(spireg, bitlen, dout, din, flags);
-}
-
-#else
-
-/* Here now the DM part */
-
-struct mvebu_spi_dev {
- boolis_errata_50mhz_ac;
-};
-
-struct mvebu_spi_platdata {
-
Re: [PATCH v2 3/3] video: sunxi_display: Convert to DM_VIDEO
Hi
On Thu, Jun 18, 2020 at 6:07 PM Jagan Teki wrote:
>
> On Thu, Jun 18, 2020 at 12:54 PM Maxime Ripard wrote:
> >
> > On Thu, Jun 18, 2020 at 01:54:37AM +0530, Jagan Teki wrote:
> > > DM_VIDEO migration deadline is already expired, but around
> > > 80 Allwinner boards are still using video in a legacy way.
> > >
> > > = WARNING ==
> > > This board does not use CONFIG_DM_VIDEO Please update
> > > the board to use CONFIG_DM_VIDEO before the v2019.07 release.
> > > Failure to update by the deadline may result in board removal.
> > > See doc/driver-model/migration.rst for more info.
> > >
> > >
> > > So let's live these boards on the tree before the video maintainer
> > > removes it by converting in to DM_VIDEO.
> > >
> > > Tested in Bananapi M1+ Plus 1920x1200 HDMI out.
> > >
> > > Signed-off-by: Jagan Teki
> > > ---
> > > Changes for v2:
> > > - add BMP support
> > >
> > > arch/arm/mach-sunxi/Kconfig | 4 +-
> > > drivers/video/sunxi/sunxi_display.c | 264
> > > include/configs/sunxi-common.h | 17 --
> > > scripts/config_whitelist.txt| 1 -
> > > 4 files changed, 157 insertions(+), 129 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> > > index be0822bfb7..7d2fb55ff0 100644
> > > --- a/arch/arm/mach-sunxi/Kconfig
> > > +++ b/arch/arm/mach-sunxi/Kconfig
> > > @@ -758,8 +758,10 @@ config VIDEO_SUNXI
> > > depends on !MACH_SUN9I
> > > depends on !MACH_SUN50I
> > > depends on !MACH_SUN50I_H6
> > > - select VIDEO
> > > + select DM_VIDEO
> > > + select DISPLAY
> > > imply VIDEO_DT_SIMPLEFB
> > > + imply CMD_BMP
> > > default y
> > > ---help---
> > > Say Y here to add support for using a cfb console on the HDMI, LCD
> > > diff --git a/drivers/video/sunxi/sunxi_display.c
> > > b/drivers/video/sunxi/sunxi_display.c
> > > index f52aba4d21..fb51b0c5ba 100644
> > > --- a/drivers/video/sunxi/sunxi_display.c
> > > +++ b/drivers/video/sunxi/sunxi_display.c
> > > @@ -7,6 +7,8 @@
> > > */
> > >
> > > #include
> > > +#include
> > > +#include
> > > #include
> > > #include
> > > #include
> > > @@ -28,7 +30,9 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #include
> > > +#include
> > > #include "../videomodes.h"
> > > #include "../anx9804.h"
> > > #include "../hitachi_tx18d42vm_lcd.h"
> > > @@ -45,6 +49,13 @@
> > >
> > > DECLARE_GLOBAL_DATA_PTR;
> > >
> > > +enum {
> > > + /* Maximum LCD size we support */
> > > + LCD_MAX_WIDTH = 3840,
> > > + LCD_MAX_HEIGHT = 2160,
> > > + LCD_MAX_LOG2_BPP= VIDEO_BPP32,
> > > +};
> >
> > Why is that an enum? Those three values don't have any relationship with
> > each other.
>
> Not sure I understand your question. These are maximum resolution
> followed by maximum bpp supporting. based on these the fbbuffer
> allocation happens, please see sunxi_de_bind on this patch.
>
> >
> > > enum sunxi_monitor {
> > > sunxi_monitor_none,
> > > sunxi_monitor_dvi,
> > > @@ -59,12 +70,11 @@ enum sunxi_monitor {
> > > #define SUNXI_MONITOR_LAST sunxi_monitor_composite_pal_nc
> > >
> > > struct sunxi_display {
> > > - GraphicDevice graphic_device;
> > > enum sunxi_monitor monitor;
> > > unsigned int depth;
> > > unsigned int fb_addr;
> > > unsigned int fb_size;
> > > -} sunxi_display;
> > > +};
> >
> > This looks unrelated?
> >
> > > const struct ctfb_res_modes composite_video_modes[2] = {
> > > /* x y hz pixclk ps/kHz le ri up lo hs vs s vmode
> > > */
> > > @@ -214,7 +224,8 @@ static int sunxi_hdmi_edid_get_block(int block, u8
> > > *buf)
> > > return r;
> > > }
> > >
> > > -static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode,
> > > +static int sunxi_hdmi_edid_get_mode(struct sunxi_display *sunxi_display,
> > > + struct ctfb_res_modes *mode,
> > > bool verbose_mode)
> > > {
> > > struct edid1_info edid1;
> > > @@ -291,14 +302,14 @@ static int sunxi_hdmi_edid_get_mode(struct
> > > ctfb_res_modes *mode,
> > > }
> > >
> > > /* Check for basic audio support, if found enable hdmi output */
> > > - sunxi_display.monitor = sunxi_monitor_dvi;
> > > + sunxi_display->monitor = sunxi_monitor_dvi;
> > > for (i = 0; i < ext_blocks; i++) {
> > > if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
> > > cea681[i].revision < 2)
> > > continue;
> > >
> > > if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
> > > - sunxi_display.monitor = sunxi_monitor_hdmi;
> > > + sunxi_display->monitor = sunxi_monitor_hdmi;
> > > }
> > >
> > > return 0;
> > > @@ -414,9 +425,9 @@ stati
Re: [GIT PULL] TI changes for v2020.10 next
On Thu, Jun 18, 2020 at 09:41:22PM +0530, Lokesh Vutla wrote: > > > On 18/06/20 9:15 pm, Tom Rini wrote: > > On Thu, Jun 18, 2020 at 07:25:43PM +0530, Lokesh Vutla wrote: > > > >> Hi Tom, > >>Please find the pull request for v2020.10 next containing TI specific > >> changes. > >> > >> Travis-CI build: > >> https://travis-ci.org/github/lokeshvutla/u-boot/builds/698883325 > >> > >> The following changes since commit > >> be79009f3b9bbdbce283e67a865121e576d790ea: > >> > >> Merge tag 'u-boot-imx-20200609' of > >> https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-06-09 09:17:24 > >> -0400) > >> > >> are available in the Git repository at: > >> > >> https://gitlab.denx.de/u-boot/custodians/u-boot-ti.git > >> tags/ti-v2020.10-next > >> > >> for you to fetch changes up to c0a8d6e1e67cc7feee5c9e6c7e8c13bb953734f1: > >> > >> ARM: da850-evm: Remove SPI from SPL when booting from NAND (2020-06-16 > >> 17:00:50 +0530) > >> > > > > This breaks my j6eco: > > U-Boot SPL 2020.07-rc4-00098-g83fdb4388253-dirty (Jun 18 2020 - 11:44:19 > > -0400) > > DRA752-GP ES1.1 > > This is J6. And I see dirty in the in SPL version. Are there any changes on > top > of this PR? Sorry for the noise, local error, the SD card got disturbed and needed an eject/re-insert. -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/2] firmware: PSCI: Fix PSCI support for OF live trees
On Thu, Jun 18, 2020 at 04:19:51PM +, Tom Warren wrote:
> No worries, I can fix it when I add them to u-boot-tegra. I have some other
> patches to add & generate a PR, I'll get it out by EOW. TomR - do you want
> me to take this patch as well as the ARM: tegra: patch in my PR, or do you
> want Jon's first patch to go thru a different repo?
You can take them all, thanks!
>
> Tom
> --
> nvpublic
>
> -Original Message-
> From: Jonathan Hunter
> Sent: Thursday, June 18, 2020 8:47 AM
> To: Tom Rini ; Tom Warren
> Cc: Stephen Warren ; Thierry Reding ;
> Peter Robinson ; Heinrich Schuchardt
> ; u-boot@lists.denx.de
> Subject: Re: [PATCH 1/2] firmware: PSCI: Fix PSCI support for OF live trees
>
>
> On 18/06/2020 12:54, Jon Hunter wrote:
> > When CONFIG_OF_LIVE is enabled, dev_of_offset() cannot be used and if
> > used returns an invalid offset. This causes the call to
> > fdt_stringlist_get() in the psci_probe() to fail to read the 'method'
> > property from the PSCI node for the device and hence prevents PSCI
> > from working. Fix this by using the ofnode_read_string() API instead
> > of the fdt_stringlist_get() because this will handle reading the
> > property both when CONFIG_OF_LIVE is enabled or disabled.
> >
> > Due to the above problem and since commit 81ea00838c68 ("efi_loader:
> > PSCI reset and shutdown") was added, the EFI system reset has been
> > broken for Tegra210 and Tegra196 platforms. This also fixes the EFI
> > system reset for these Tegra platforms.
>
> Oops, just spotted the above typo. Should be Tegra186 and not Tegra196 (which
> does not exist!). I can correct that.
>
> Jon
>
> --
> nvpublic
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH v2 03/23] am335x: baltos: Enable DM_SPI
On Mon, Jun 15, 2020 at 12:07 AM Yegor Yefremov wrote: > > On Sat, Jun 13, 2020 at 8:01 PM Jagan Teki wrote: > > > > On Wed, May 27, 2020 at 6:26 PM Jagan Teki > > wrote: > > > > > > Enable DM_SPI for am355x baltos board. > > > > > > Build is fine, but not tested. > > > > > > Cc: Yegor Yefremov > > > > Any comments? > > Reviewed-by: Yegor Yefremov Applied to u-boot-spi/master
RE: [PATCH 1/2] firmware: PSCI: Fix PSCI support for OF live trees
No worries, I can fix it when I add them to u-boot-tegra. I have some other
patches to add & generate a PR, I'll get it out by EOW. TomR - do you want me
to take this patch as well as the ARM: tegra: patch in my PR, or do you want
Jon's first patch to go thru a different repo?
Tom
--
nvpublic
-Original Message-
From: Jonathan Hunter
Sent: Thursday, June 18, 2020 8:47 AM
To: Tom Rini ; Tom Warren
Cc: Stephen Warren ; Thierry Reding ;
Peter Robinson ; Heinrich Schuchardt
; u-boot@lists.denx.de
Subject: Re: [PATCH 1/2] firmware: PSCI: Fix PSCI support for OF live trees
On 18/06/2020 12:54, Jon Hunter wrote:
> When CONFIG_OF_LIVE is enabled, dev_of_offset() cannot be used and if
> used returns an invalid offset. This causes the call to
> fdt_stringlist_get() in the psci_probe() to fail to read the 'method'
> property from the PSCI node for the device and hence prevents PSCI
> from working. Fix this by using the ofnode_read_string() API instead
> of the fdt_stringlist_get() because this will handle reading the
> property both when CONFIG_OF_LIVE is enabled or disabled.
>
> Due to the above problem and since commit 81ea00838c68 ("efi_loader:
> PSCI reset and shutdown") was added, the EFI system reset has been
> broken for Tegra210 and Tegra196 platforms. This also fixes the EFI
> system reset for these Tegra platforms.
Oops, just spotted the above typo. Should be Tegra186 and not Tegra196 (which
does not exist!). I can correct that.
Jon
--
nvpublic
Re: [PATCH v2 00/10] spi: dm-conversion (part2)
On Sat, Jun 13, 2020 at 5:51 PM Jagan Teki wrote: > > This is rebased v2 for previous version spi dm-conversion > series[1] on fsl_espi boards. > > All these patches dropped the boards which are not converted > spi dm and also the maintainer is accepted to remove the > same. > Rest of the patches in this series are trying to switch spi dm. > > Changes for v2: > - rebase on master > - updated commit message > - collect Priyanka r-b tag > > [1] > https://patchwork.ozlabs.org/project/uboot/cover/20200527164655.177741-1-ja...@amarulasolutions.com/ > > Any inputs? > Jagan. > > Jagan Teki (10): > powerpc: Remove configs/B4420QDS_NAND_defconfig board > powerpc: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board > powerpc: Remove configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig > board > powerpc: Remove configs/C29XPCIE_NAND_defconfig board > powerpc: Remove configs/MPC8536DS_36BIT_defconfig board > powerpc: Remove P1022DS_36BIT_NAND_defconfig board > powerpc: Remove T1024QDS_DDR4_SECURE_BOOT_defconfig board > powerpc: Remove T1040QDS_DDR4_defconfig board > powerpc: Remove T4160QDS_NAND_defconfig board > powerpc: Remove TWR-P1025_defconfig board Applied to u-boot-spi/master
[PATCH 3/3] ARM: dts: rockchip: Add Radxa Rock Pi N8 initial support
Rock Pi N8 is a Rockchip RK3288 based SBC, which has
- VMARC RK3288 SOM (as per SMARC standard) from Vamrs.
- Compatible carrier board from Radxa.
VAMRC RK3288 SOM need to mount on top of radxa dalang
carrier board for making Rock Pi N8 SBC.
So, add initial support for Rock Pi N8 by including rk3288,
rk3288 vamrc-som and raxda dalang carrier board dtsi files.
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi | 33 +++
arch/arm/dts/rk3288-rock-pi-n8.dts | 17 ++
arch/arm/dts/rk3288-vmarc-som.dtsi | 9 ---
board/rockchip/evb_rk3288/MAINTAINERS | 6 ++
configs/rock-pi-n8-rk3288_defconfig| 66 ++
6 files changed, 123 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3288-rock-pi-n8.dts
create mode 100644 configs/rock-pi-n8-rk3288_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 07dfe06230..aae95811c1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -92,6 +92,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-phycore-rdk.dtb \
rk3288-popmetal.dtb \
rk3288-rock2-square.dtb \
+ rk3288-rock-pi-n8.dtb \
rk3288-tinker.dtb \
rk3288-tinker-s.dtb \
rk3288-veyron-jerry.dtb \
diff --git a/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi
b/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi
new file mode 100644
index 00..e9d7404ed9
--- /dev/null
+++ b/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Jagan Teki
+ */
+
+#include "rk3288-u-boot.dtsi"
+
+&dmc {
+ rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+ 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+ 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+ 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+ 0x8 0x1f4>;
+ rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+ 0x0 0xc3 0x6 0x2>;
+ rockchip,sdram-params = <0x20d266a4 0x5b6 2 53300 6 9 0>;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-rock-pi-n8.dts
b/arch/arm/dts/rk3288-rock-pi-n8.dts
new file mode 100644
index 00..c8637a50c1
--- /dev/null
+++ b/arch/arm/dts/rk3288-rock-pi-n8.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Vamrs Limited
+ * Copyright (c) 2019 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "rk3288.dtsi"
+#include "rk3288-vmarc-som.dtsi"
+#include
+
+/ {
+ model = "Radxa ROCK Pi N8";
+ compatible = "radxa,rockpi-n8", "vamrs,rk3288-vmarc-som",
+"rockchip,rk3288";
+};
diff --git a/arch/arm/dts/rk3288-vmarc-som.dtsi
b/arch/arm/dts/rk3288-vmarc-som.dtsi
index 1549ac4044..3cffe61cdf 100644
--- a/arch/arm/dts/rk3288-vmarc-som.dtsi
+++ b/arch/arm/dts/rk3288-vmarc-som.dtsi
@@ -251,15 +251,6 @@
};
};
-&io_domains {
- bb-supply = <&vcc_io>;
- flash0-supply = <&vccio_flash>;
- gpio1830-supply = <&vcc_18>;
- gpio30-supply = <&vcc_io>;
- sdcard-supply = <&vccio_sd>;
- status = "okay";
-};
-
&pinctrl {
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
drive-strength = <8>;
diff --git a/board/rockchip/evb_rk3288/MAINTAINERS
b/board/rockchip/evb_rk3288/MAINTAINERS
index 8a4f127f88..9bd6b1e8a4 100644
--- a/board/rockchip/evb_rk3288/MAINTAINERS
+++ b/board/rockchip/evb_rk3288/MAINTAINERS
@@ -4,3 +4,9 @@ S: Maintained
F: board/rockchip/evb_rk3288
F: include/configs/evb_rk3288.h
F: configs/evb-rk3288_defconfig
+
+ROCK-PI-N8
+M: Jagan Teki
+S: Maintained
+F: configs/rock-pi-n8-rk3288_defconfig
+F: arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi
diff --git a/configs/rock-pi-n8-rk3288_defconfig
b/configs/rock-pi-n8-rk3288_defconfig
new file mode 100644
index 00..6b31e19eda
--- /dev/null
+++ b/configs/rock-pi-n8-rk3288_defconfig
@@ -0,0 +1,66 @@
+CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0010
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3288=y
+CONFIG_TARGET_EVB_RK3288=y
+CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xff69
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_DEBUG_UART=y
+CONFIG_USE_PREBOOT=y
+CONFIG_SILENT_CONSOLE=y
+CONFIG_DEFAULT_FDT_FILE="rk3288-rock-pi-n8.dtb"
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_CMD_SPL=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG
[PATCH 2/3] ARM: dts: rockchip: Add VMARC RK3288 SOM initial support
VMARC RK3288 SOM is a standard SMARC SOM design with
Rockchip RK3288 SoC, which is designed by Vamrs.
Specification:
- Rockchip RK3288
- PMIC: RK808
- SD slot, 16GiB eMMC
- 2xUSB-2.0, 1xUSB3.0
- USB-C for power supply
- Ethernet, PCIe
- HDMI, MIPI-DSI/CSI, eDP
Add initial support for VMARC RK3288 SOM, this would use
with associated carrier board.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3288-vmarc-som.dtsi | 298 +
1 file changed, 298 insertions(+)
create mode 100644 arch/arm/dts/rk3288-vmarc-som.dtsi
diff --git a/arch/arm/dts/rk3288-vmarc-som.dtsi
b/arch/arm/dts/rk3288-vmarc-som.dtsi
new file mode 100644
index 00..1549ac4044
--- /dev/null
+++ b/arch/arm/dts/rk3288-vmarc-som.dtsi
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Vamrs Limited
+ * Copyright (c) 2019 Amarula Solutions(India)
+ */
+
+#include
+#include
+#include
+
+/ {
+ compatible = "vamrs,rk3288-vmarc-som", "rockchip,rk3288";
+
+ ext_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ vccio_flash: vccio-flash-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_flash";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ startup-delay-us = <150>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ clock_in_out = "input";
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_io>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ max-speed = <1000>;
+};
+
+&i2c0 {
+ clock-frequency = <40>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = ;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int &global_pwroff>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_io>;
+ vcc9-supply = <&vcc_io>;
+ vcc10-supply = <&vcc_sys>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc_io>;
+ vddio-supply = <&vcc_io>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <75>;
+ regulator-max-microvolt = <140>;
+ regulator-name = "vdd_arm";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <85>;
+ regulator-max-microvolt = <125>;
+ regulator-name = "vdd_gpu";
+ regulator-ramp-delay = <6000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+
[PATCH 1/3] ARM: dts: rockchip: radxa-dalang: Update sdmmc properties
Radxa dalang carrier boards are used to mount vmarc SoM's
of rk3399pro and rk3288 to make complete SBC.
Among these combinations, card detection gpio, max-frequency
properties are used with rk3399pro SoM but not required for
rk3288 SoM based on the hardware schematics.
So, let's move these sdmmc specific properties on associate
vmarc dtsi to make common use of dalang carrier device tree file.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3399pro-vmarc-som.dtsi | 5 +
arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi | 2 --
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3399pro-vmarc-som.dtsi
b/arch/arm/dts/rk3399pro-vmarc-som.dtsi
index 0a516334f1..6fd17e8a81 100644
--- a/arch/arm/dts/rk3399pro-vmarc-som.dtsi
+++ b/arch/arm/dts/rk3399pro-vmarc-som.dtsi
@@ -317,6 +317,11 @@
status = "okay";
};
+&sdmmc {
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ max-frequency = <15000>;
+};
+
&tsadc {
status = "okay";
rockchip,hw-tshut-mode = <1>;
diff --git a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi
b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi
index df3712aedf..3e54f38f0a 100644
--- a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi
+++ b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi
@@ -52,10 +52,8 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
vqmmc-supply = <&vccio_sd>;
- max-frequency = <15000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
status = "okay";
--
2.25.1
[PATCH 0/3] rockchip: Add Radxa Rock Pi N8 support
Rock Pi N8 is a Rockchip RK3288 based SBC, which has - VMARC RK3288 SOM (as per SMARC standard) from Vamrs. - Compatible carrier board from Radxa. VMARC RK3288 SOM need to mount on top of dalang carrier board for making Rock PI N8 SBC. All these respective dts patches are in Linux mainling list. N8 board support TPL boot flow. Any inputs? Jagan. Jagan Teki (3): ARM: dts: rockchip: radxa-dalang: Update sdmmc properties ARM: dts: rockchip: Add VMARC RK3288 SOM initial support ARM: dts: rockchip: Add Radxa Rock Pi N8 initial support arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi| 33 ++ arch/arm/dts/rk3288-rock-pi-n8.dts| 17 ++ arch/arm/dts/rk3288-vmarc-som.dtsi| 289 ++ arch/arm/dts/rk3399pro-vmarc-som.dtsi | 5 + .../dts/rockchip-radxa-dalang-carrier.dtsi| 2 - board/rockchip/evb_rk3288/MAINTAINERS | 6 + configs/rock-pi-n8-rk3288_defconfig | 66 8 files changed, 417 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi create mode 100644 arch/arm/dts/rk3288-rock-pi-n8.dts create mode 100644 arch/arm/dts/rk3288-vmarc-som.dtsi create mode 100644 configs/rock-pi-n8-rk3288_defconfig -- 2.25.1
Re: [GIT PULL] TI changes for v2020.10 next
On 18/06/20 9:15 pm, Tom Rini wrote: > On Thu, Jun 18, 2020 at 07:25:43PM +0530, Lokesh Vutla wrote: > >> Hi Tom, >> Please find the pull request for v2020.10 next containing TI specific >> changes. >> >> Travis-CI build: >> https://travis-ci.org/github/lokeshvutla/u-boot/builds/698883325 >> >> The following changes since commit be79009f3b9bbdbce283e67a865121e576d790ea: >> >> Merge tag 'u-boot-imx-20200609' of >> https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-06-09 09:17:24 >> -0400) >> >> are available in the Git repository at: >> >> https://gitlab.denx.de/u-boot/custodians/u-boot-ti.git >> tags/ti-v2020.10-next >> >> for you to fetch changes up to c0a8d6e1e67cc7feee5c9e6c7e8c13bb953734f1: >> >> ARM: da850-evm: Remove SPI from SPL when booting from NAND (2020-06-16 >> 17:00:50 +0530) >> > > This breaks my j6eco: > U-Boot SPL 2020.07-rc4-00098-g83fdb4388253-dirty (Jun 18 2020 - 11:44:19 > -0400) > DRA752-GP ES1.1 This is J6. And I see dirty in the in SPL version. Are there any changes on top of this PR? The only patches that can cause this issue are the below patches. Let me see if these are causing any troubles. board: ti: common: Fix pointer-bool-conversion warnings mmc: omap_hsmmc: Add guards around omap_hsmmc_get_cfg() Thanks and regards, Lokesh > Trying to boot from MMC1 > no pinctrl state for default mode > MMC: no card present > spl: mmc init failed with error: -123 > SPL: failed to boot from all boot devices > ### ERROR ### Please RESET the board ### >
[PATCH v4 3/5] roc-rk3399-pc: Move leds setup in SPL
roc-rk3399-pc has some specific requirements to support LEDS,
environment. board detection and etc prior to U-Boot proper.
So as of now SPL would be a better stage for these custom board
requirements to support unlike TPL. Adding few of these custom
requirements like LEDS in TPL would require extra code pulling
and also the size of TPL can grow.
So, this patch moves the leds code from TPL into SPL after relocation.
Signed-off-by: Jagan Teki
Tested-by: Suniel Mahesh
---
Changes for v4:
- none
arch/arm/mach-rockchip/tpl.c| 7 ---
board/firefly/roc-pc-rk3399/Makefile| 4
board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 21 ---
board/firefly/roc-pc-rk3399/spl.c | 23 +
configs/roc-pc-mezzanine-rk3399_defconfig | 2 +-
configs/roc-pc-rk3399_defconfig | 2 +-
6 files changed, 29 insertions(+), 30 deletions(-)
create mode 100644 board/firefly/roc-pc-rk3399/spl.c
diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
index 88f80b05a9..cc908e1b0e 100644
--- a/arch/arm/mach-rockchip/tpl.c
+++ b/arch/arm/mach-rockchip/tpl.c
@@ -43,18 +43,11 @@ __weak void rockchip_stimer_init(void)
TIMER_CONTROL_REG);
}
-__weak int board_early_init_f(void)
-{
- return 0;
-}
-
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
- board_early_init_f();
-
#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT)
/*
* Debug UART can be used from here if required:
diff --git a/board/firefly/roc-pc-rk3399/Makefile
b/board/firefly/roc-pc-rk3399/Makefile
index 29c79b25d7..3a9c4c744d 100644
--- a/board/firefly/roc-pc-rk3399/Makefile
+++ b/board/firefly/roc-pc-rk3399/Makefile
@@ -4,4 +4,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
obj-y += roc-pc-rk3399.o
+endif
diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
index 7c3a803654..581cdcd3b0 100644
--- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
+++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
@@ -6,13 +6,8 @@
#include
#include
#include
-#include
#include
-#include
-#include
-#include
-#ifndef CONFIG_SPL_BUILD
int board_early_init_f(void)
{
struct udevice *regulator;
@@ -30,19 +25,3 @@ int board_early_init_f(void)
out:
return 0;
}
-#endif
-
-#if defined(CONFIG_TPL_BUILD)
-
-#define GPIO0_BASE 0xff72
-
-int board_early_init_f(void)
-{
- struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE;
-
- /* Turn on red LED, indicating full power mode */
- spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
-
- return 0;
-}
-#endif
diff --git a/board/firefly/roc-pc-rk3399/spl.c
b/board/firefly/roc-pc-rk3399/spl.c
new file mode 100644
index 00..a7664c6b86
--- /dev/null
+++ b/board/firefly/roc-pc-rk3399/spl.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+#include
+#include
+#include
+
+#define GPIO0_BASE 0xff72
+
+static void led_setup(void)
+{
+ struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE;
+
+ /* Turn on red LED, indicating full power mode */
+ spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
+}
+
+void rk_spl_board_init(void)
+{
+ led_setup();
+}
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig
b/configs/roc-pc-mezzanine-rk3399_defconfig
index 595f052cb7..060b4bfecf 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
@@ -20,7 +21,6 @@ CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
-CONFIG_TPL_GPIO_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index 1c4db3443f..9897a52cd8 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
@@ -20,7 +21,6 @@ CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
-CONFIG_TPL_GPIO_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
--
2.25.1
[PATCH v4 1/5] rockchip: spl: Add spl_board_init
spl_board_init is a proper location and common practice
option to have a custom board initialization code after
relocation in SPL.
This patch add the feasibility to add the custom SPL board
initzlaization throughout rockchip platforms and adjust
existing the spl board code on respective boards.
Signed-off-by: Jagan Teki
---
Changes for v4:
- new patch
arch/arm/Kconfig | 1 +
arch/arm/mach-rockchip/Kconfig| 2 -
arch/arm/mach-rockchip/rk3188/rk3188.c| 2 +-
arch/arm/mach-rockchip/rk3399/rk3399.c| 57 -
arch/arm/mach-rockchip/spl.c | 10 +++
board/firefly/firefly-rk3288/firefly-rk3288.c | 2 +-
board/phytec/phycore_rk3288/phycore-rk3288.c | 2 +-
.../puma_rk3399/puma-rk3399.c | 61 +++
8 files changed, 75 insertions(+), 62 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index edc9e38c6c..57ddf15cb3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1679,6 +1679,7 @@ config ARCH_ROCKCHIP
select ENABLE_ARM_SOC_BOOT0_HOOK
select OF_CONTROL
select SPI
+ select SPL_BOARD_INIT if SPL
select SPL_DM if SPL
select SYS_MALLOC_F
select SYS_THUMB_BUILD if !ARM64
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 0cb1f23d0f..b1008a5058 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -49,7 +49,6 @@ config ROCKCHIP_RK3128
config ROCKCHIP_RK3188
bool "Support Rockchip RK3188"
select CPU_V7A
- select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
select SPL
select SPL_CLK
@@ -208,7 +207,6 @@ config ROCKCHIP_RK3399
select SPL
select SPL_ATF
select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
- select SPL_BOARD_INIT if SPL
select SPL_LOAD_FIT
select SPL_CLK if SPL
select SPL_PINCTRL if SPL
diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c
b/arch/arm/mach-rockchip/rk3188/rk3188.c
index ef57dfd761..0c0fe84ad5 100644
--- a/arch/arm/mach-rockchip/rk3188/rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188/rk3188.c
@@ -111,7 +111,7 @@ static int setup_led(void)
return 0;
}
-void spl_board_init(void)
+void rk_spl_board_init(void)
{
int ret;
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c
b/arch/arm/mach-rockchip/rk3399/rk3399.c
index 4fda93b152..b53a111769 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -217,61 +217,4 @@ void spl_perform_fixups(struct spl_image_info *spl_image)
"u-boot,spl-boot-device", boot_ofpath);
}
-#if defined(SPL_GPIO_SUPPORT)
-static void rk3399_force_power_on_reset(void)
-{
- ofnode node;
- struct gpio_desc sysreset_gpio;
-
- debug("%s: trying to force a power-on reset\n", __func__);
-
- node = ofnode_path("/config");
- if (!ofnode_valid(node)) {
- debug("%s: no /config node?\n", __func__);
- return;
- }
-
- if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
- &sysreset_gpio, GPIOD_IS_OUT)) {
- debug("%s: could not find a /config/sysreset-gpio\n", __func__);
- return;
- }
-
- dm_gpio_set_value(&sysreset_gpio, 1);
-}
-#endif
-
-void spl_board_init(void)
-{
-#if defined(SPL_GPIO_SUPPORT)
- struct rockchip_cru *cru = rockchip_get_cru();
-
- /*
-* The RK3399 resets only 'almost all logic' (see also in the TRM
-* "3.9.4 Global software reset"), when issuing a software reset.
-* This may cause issues during boot-up for some configurations of
-* the application software stack.
-*
-* To work around this, we test whether the last reset reason was
-* a power-on reset and (if not) issue an overtemp-reset to reset
-* the entire module.
-*
-* While this was previously fixed by modifying the various places
-* that could generate a software reset (e.g. U-Boot's sysreset
-* driver, the ATF or Linux), we now have it here to ensure that
-* we no longer have to track this through the various components.
-*/
- if (cru->glb_rst_st != 0)
- rk3399_force_power_on_reset();
-#endif
-
-#if defined(SPL_DM_REGULATOR)
- /*
-* Turning the eMMC and SPI back on (if disabled via the Qseven
-* BIOS_ENABLE) signal is done through a always-on regulator).
-*/
- if (regulators_enable_boot_on(false))
- debug("%s: Cannot enable boot on regulator\n", __func__);
-#endif
-}
#endif
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index cddf4fd3d5..d4c83a1119 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -150,6 +150,16 @@ void board_init_f(ulong dummy)
preloader_console_init();
}
+_
[PATCH v4 5/5] roc-rk3399-pc: Set LED only during POR and pwr_key=y
ROC-RK3399-PC has specific set of configurations for
on-board led setup.
Due to easiness for user to know the state of the board
roc-rk339-pc board code will setup the low power led
on/off, and waiting for user to press power key and then
glow full power led.
All this needs to happen only during power-on-reset not
for soft reset or WDT.
Also, it is not a proper usage to ask the user to press
the Power key if the board connected remotely, so add
the environment variable 'pwr_key' to check as well.
So, user need to press Power key only
- during POR
- pwr_key=y
Tested-by: Suniel Mahesh
Signed-off-by: Jagan Teki
---
Changes for v4:
- none
board/firefly/roc-pc-rk3399/spl.c | 35 ++-
configs/roc-pc-mezzanine-rk3399_defconfig | 4 ++-
configs/roc-pc-rk3399_defconfig | 4 ++-
3 files changed, 40 insertions(+), 3 deletions(-)
diff --git a/board/firefly/roc-pc-rk3399/spl.c
b/board/firefly/roc-pc-rk3399/spl.c
index a7664c6b86..771a7fb2f2 100644
--- a/board/firefly/roc-pc-rk3399/spl.c
+++ b/board/firefly/roc-pc-rk3399/spl.c
@@ -4,16 +4,49 @@
*/
#include
+#include
#include
+#include
+#include
#include
+#include
+#define PMUGRF_BASE0xff32
#define GPIO0_BASE 0xff72
+/**
+ * LED setup for roc-rk3399-pc
+ *
+ * 1. Set the low power leds (only during POR, pwr_key env is 'y')
+ *glow yellow LED, termed as low power
+ *poll for on board power key press
+ *once powe key pressed, turn off yellow
+ * 2. Turn on red LED, indicating full power mode
+ */
static void led_setup(void)
{
struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE;
+ struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
+ bool press_pwr_key = false;
+
+ if (IS_ENABLED(CONFIG_SPL_ENV_SUPPORT)) {
+ env_init();
+ env_load();
+ if (env_get_yesno("pwr_key") == 1)
+ press_pwr_key = true;
+ }
+
+ if (press_pwr_key && !strcmp(get_reset_cause(), "POR")) {
+ spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1);
+
+ spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5),
+ GPIO_PULL_NORMAL);
+ while (readl(&gpio0->ext_port) & 0x20)
+ ;
+
+ spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0);
+ }
- /* Turn on red LED, indicating full power mode */
spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
}
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig
b/configs/roc-pc-mezzanine-rk3399_defconfig
index 060b4bfecf..7ca9fd0906 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -18,7 +18,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -33,6 +34,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index 9897a52cd8..440c1ab303 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -18,7 +18,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -32,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
--
2.25.1
[PATCH v4 4/5] rockchip: Separate the reset cause from display cpuinfo
reset cause is a generic functionality based on the soc
cru registers in rockchip. This can be used for printing
the cause of reset in cpuinfo or some other place where
reset cause is needed.
Other than cpuinfo, reset cause can also be using during
bootcount for checking the specific reset cause and glow
the led based on the reset cause.
So, let's separate the reset cause code from cpuinfo, and
add a check to build it for rk3399, rk3288 since these two
soc are supporting reset cause as of now.
Signed-off-by: Jagan Teki
Tested-by: Suniel Mahesh
---
Changes for v4:
- none
arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
arch/arm/mach-rockchip/Makefile | 5 -
arch/arm/mach-rockchip/cpu-info.c| 20
3 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
b/arch/arm/include/asm/arch-rockchip/cru.h
index 5eb17f9d55..317eb61049 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -31,4 +31,6 @@ enum {
#define MHz100
+char *get_reset_cause(void);
+
#endif /* _ROCKCHIP_CLOCK_H */
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 5b38526fe0..ef4898e00c 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -15,6 +15,10 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
+ifeq ($(CONFIG_ROCKCHIP_RK3288)$(CONFIG_ROCKCHIP_RK3399), y)
+obj-y += cpu-info.o
+endif
+
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
# Always include boot_mode.o, as we bypass it (i.e. turn it off)
@@ -22,7 +26,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
# we can have the preprocessor correctly recognise both 0x0 and 0
# meaning "turn it off".
obj-y += boot_mode.o
-obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
diff --git a/arch/arm/mach-rockchip/cpu-info.c
b/arch/arm/mach-rockchip/cpu-info.c
index 21ca9dedce..76a840e2c3 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -13,7 +13,7 @@
#include
#include
-static char *get_reset_cause(void)
+char *get_reset_cause(void)
{
struct rockchip_cru *cru = rockchip_get_cru();
char *cause = NULL;
@@ -41,12 +41,6 @@ static char *get_reset_cause(void)
cause = "unknown reset";
}
- /**
-* reset_reason env is used by rk3288, due to special use case
-* to figure it the boot behavior. so keep this as it is.
-*/
- env_set("reset_reason", cause);
-
/*
* Clear glb_rst_st, so we can determine the last reset cause
* for following resets.
@@ -56,12 +50,22 @@ static char *get_reset_cause(void)
return cause;
}
+#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
+ char *cause = get_reset_cause();
+
printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
- printf("Reset cause: %s\n", get_reset_cause());
+ printf("Reset cause: %s\n", cause);
+
+ /**
+* reset_reason env is used by rk3288, due to special use case
+* to figure it the boot behavior. so keep this as it is.
+*/
+ env_set("reset_reason", cause);
/* TODO print operating temparature and clock */
return 0;
}
+#endif
--
2.25.1
[PATCH v4 2/5] rk3399: spl: Print SPL banner after relocation
Usually printing the SPL banner varies between architecture
or board codes.
- Some would print before relocation at the end board_init_f
for making sure all initialization prior to this would happen
properly. if at all there is a requirement for serial init,
that happens properly since it prints all after that.
- Some would print after relocation at the spl_board_init for
making sure all initialization prior to relocation would
happen properly. Also debug uart on these cases would be
available before relocation. So debug support is available
in before and after relocation.
Rockchip SPL is following formar step to print the banner at
the end of board_init_f.
To support various custom use cases in SPL like leds, environment,
board detections later options like printing the banner after
relocation would be a better option. Printing banner would also
help to support debugging availability between relocation codes,
like debug uart available before relocation and banner availability
after relation.
By demonstrating all the above use cases, this patch is trying
to print the SPL banner after relocation.
Signed-off-by: Jagan Teki
Tested-by: Suniel Mahesh
---
Changes for v4:
- none
arch/arm/mach-rockchip/spl.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index d4c83a1119..6d5c058548 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -147,7 +147,6 @@ void board_init_f(ulong dummy)
gd->ram_top = gd->ram_base + get_effective_memsize();
gd->ram_top = board_get_usable_ram_top(gd->ram_size);
#endif
- preloader_console_init();
}
__weak void rk_spl_board_init(void)
@@ -158,6 +157,8 @@ void spl_board_init(void)
{
/* board specific spl init */
rk_spl_board_init();
+
+ preloader_console_init();
}
#ifdef CONFIG_SPL_LOAD_FIT
--
2.25.1
Re: [PATCH v2 3/3] video: sunxi_display: Convert to DM_VIDEO
On Thu, Jun 18, 2020 at 12:54 PM Maxime Ripard wrote:
>
> On Thu, Jun 18, 2020 at 01:54:37AM +0530, Jagan Teki wrote:
> > DM_VIDEO migration deadline is already expired, but around
> > 80 Allwinner boards are still using video in a legacy way.
> >
> > = WARNING ==
> > This board does not use CONFIG_DM_VIDEO Please update
> > the board to use CONFIG_DM_VIDEO before the v2019.07 release.
> > Failure to update by the deadline may result in board removal.
> > See doc/driver-model/migration.rst for more info.
> >
> >
> > So let's live these boards on the tree before the video maintainer
> > removes it by converting in to DM_VIDEO.
> >
> > Tested in Bananapi M1+ Plus 1920x1200 HDMI out.
> >
> > Signed-off-by: Jagan Teki
> > ---
> > Changes for v2:
> > - add BMP support
> >
> > arch/arm/mach-sunxi/Kconfig | 4 +-
> > drivers/video/sunxi/sunxi_display.c | 264
> > include/configs/sunxi-common.h | 17 --
> > scripts/config_whitelist.txt| 1 -
> > 4 files changed, 157 insertions(+), 129 deletions(-)
> >
> > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> > index be0822bfb7..7d2fb55ff0 100644
> > --- a/arch/arm/mach-sunxi/Kconfig
> > +++ b/arch/arm/mach-sunxi/Kconfig
> > @@ -758,8 +758,10 @@ config VIDEO_SUNXI
> > depends on !MACH_SUN9I
> > depends on !MACH_SUN50I
> > depends on !MACH_SUN50I_H6
> > - select VIDEO
> > + select DM_VIDEO
> > + select DISPLAY
> > imply VIDEO_DT_SIMPLEFB
> > + imply CMD_BMP
> > default y
> > ---help---
> > Say Y here to add support for using a cfb console on the HDMI, LCD
> > diff --git a/drivers/video/sunxi/sunxi_display.c
> > b/drivers/video/sunxi/sunxi_display.c
> > index f52aba4d21..fb51b0c5ba 100644
> > --- a/drivers/video/sunxi/sunxi_display.c
> > +++ b/drivers/video/sunxi/sunxi_display.c
> > @@ -7,6 +7,8 @@
> > */
> >
> > #include
> > +#include
> > +#include
> > #include
> > #include
> > #include
> > @@ -28,7 +30,9 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > +#include
> > #include "../videomodes.h"
> > #include "../anx9804.h"
> > #include "../hitachi_tx18d42vm_lcd.h"
> > @@ -45,6 +49,13 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +enum {
> > + /* Maximum LCD size we support */
> > + LCD_MAX_WIDTH = 3840,
> > + LCD_MAX_HEIGHT = 2160,
> > + LCD_MAX_LOG2_BPP= VIDEO_BPP32,
> > +};
>
> Why is that an enum? Those three values don't have any relationship with
> each other.
Not sure I understand your question. These are maximum resolution
followed by maximum bpp supporting. based on these the fbbuffer
allocation happens, please see sunxi_de_bind on this patch.
>
> > enum sunxi_monitor {
> > sunxi_monitor_none,
> > sunxi_monitor_dvi,
> > @@ -59,12 +70,11 @@ enum sunxi_monitor {
> > #define SUNXI_MONITOR_LAST sunxi_monitor_composite_pal_nc
> >
> > struct sunxi_display {
> > - GraphicDevice graphic_device;
> > enum sunxi_monitor monitor;
> > unsigned int depth;
> > unsigned int fb_addr;
> > unsigned int fb_size;
> > -} sunxi_display;
> > +};
>
> This looks unrelated?
>
> > const struct ctfb_res_modes composite_video_modes[2] = {
> > /* x y hz pixclk ps/kHz le ri up lo hs vs s vmode */
> > @@ -214,7 +224,8 @@ static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
> > return r;
> > }
> >
> > -static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode,
> > +static int sunxi_hdmi_edid_get_mode(struct sunxi_display *sunxi_display,
> > + struct ctfb_res_modes *mode,
> > bool verbose_mode)
> > {
> > struct edid1_info edid1;
> > @@ -291,14 +302,14 @@ static int sunxi_hdmi_edid_get_mode(struct
> > ctfb_res_modes *mode,
> > }
> >
> > /* Check for basic audio support, if found enable hdmi output */
> > - sunxi_display.monitor = sunxi_monitor_dvi;
> > + sunxi_display->monitor = sunxi_monitor_dvi;
> > for (i = 0; i < ext_blocks; i++) {
> > if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
> > cea681[i].revision < 2)
> > continue;
> >
> > if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
> > - sunxi_display.monitor = sunxi_monitor_hdmi;
> > + sunxi_display->monitor = sunxi_monitor_hdmi;
> > }
> >
> > return 0;
> > @@ -414,9 +425,9 @@ static void sunxi_frontend_mode_set(const struct
> > ctfb_res_modes *mode,
> > static void sunxi_frontend_enable(void) {}
> > #endif
> >
> > -static bool sunxi_is_composite(void)
> > +static bool sunxi_is_composite(enum sunxi_monitor monitor)
> > {
> > - switch (sunxi_display.monitor) {
> > + switch (monitor) {
> > case sunxi_
[PATCH v4 0/5] roc-rk3399-pc: Custom SPL init
This series supports custom initialization code required for roc-rk3399-pc board on SPL stage. Here is the previous v3 this series[1]. Now this series is well mature code handling to add custom spl_board_init code parts. roc-rk3399-pc would require custom leds initialization based on user intervention of the power key. This code handles the user intervention via SPI environment variable. If someone or production systems wants this feature then 'pwr_key' has to be set otherwise it is normal like other rk3399 boards in Mainline. Changes for v4: - enable SPL_BOARD_INIT in all platforms Changes for v3: - support leds on SPL - support env 'pwr_key' [1] https://patchwork.ozlabs.org/project/uboot/cover/20200608183144.26809-1-ja...@amarulasolutions.com Any inputs? Jagan. Jagan Teki (5): rockchip: spl: Add spl_board_init rk3399: spl: Print SPL banner after relocation roc-rk3399-pc: Move leds setup in SPL rockchip: Separate the reset cause from display cpuinfo roc-rk3399-pc: Set LED only during POR and pwr_key=y arch/arm/Kconfig | 1 + arch/arm/include/asm/arch-rockchip/cru.h | 2 + arch/arm/mach-rockchip/Kconfig| 2 - arch/arm/mach-rockchip/Makefile | 5 +- arch/arm/mach-rockchip/cpu-info.c | 20 +++--- arch/arm/mach-rockchip/rk3188/rk3188.c| 2 +- arch/arm/mach-rockchip/rk3399/rk3399.c| 57 - arch/arm/mach-rockchip/spl.c | 11 arch/arm/mach-rockchip/tpl.c | 7 --- board/firefly/firefly-rk3288/firefly-rk3288.c | 2 +- board/firefly/roc-pc-rk3399/Makefile | 4 ++ board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 21 --- board/firefly/roc-pc-rk3399/spl.c | 56 + board/phytec/phycore_rk3288/phycore-rk3288.c | 2 +- .../puma_rk3399/puma-rk3399.c | 61 +++ configs/roc-pc-mezzanine-rk3399_defconfig | 6 +- configs/roc-pc-rk3399_defconfig | 6 +- 17 files changed, 162 insertions(+), 103 deletions(-) create mode 100644 board/firefly/roc-pc-rk3399/spl.c -- 2.25.1
Re: [PATCH] phy: atheros: ar8035: Fix clock output calculation
Hi Tom, On Thu, Jun 18, 2020 at 10:38 AM Tom Rini wrote: > What else do I need with this to test it myself? This alone doesn't do > it (but I'm not surprised) and adding the 2 DM_ETH patches you sent to > convert the platform still gives the "Could not get PHY for FEC0: addr > 0" error message. Thanks! I will submit later today the complete series for you to test.
Re: Can't access mmc #0 on mt7623 when booted from external SD
On Tue, 2020-06-16 at 22:12 +0100, David Woodhouse wrote: > On Tue, 2020-06-16 at 21:38 +0200, Michael Nazzareno Trimarchi wrote: > > Have you already tried to dump the pinmux using the cmd? in both > > situation? > > U-Boot> pinmux status -a > > -- > > pinctrl@10005000: > > Ops get_pin_muxing error (-38) > > Can't display pin muxing for pinctrl@10005000 > > exit not allowed from main input shell. > I found a datasheet... Booted from SD, not working... U-Boot> md 0x10005cc0 c 10005cc0: 0111 0111 0111 0111 10005cd0: 0111 0111 0111 0111 10005ce0: 0011 0011 0011 0011 Booted from eMMC, working... U-Boot> md 0x10005cc0 c 10005cc0: 0910 0910 0910 0910 10005cd0: 0c10 0c10 0c10 0c10 10005ce0: 0010 0010 0010 0010 Now when I start U-Boot from the SD card I can make it work... U-Boot> mmc list mmc@1123: 0 mmc@1124: 1 (SD) U-Boot> mmc dev 0 U-Boot> mw 0x10005cc0 0x910 U-Boot> mw 0x10005cd0 0xc10 U-Boot> mw 0x10005ce0 0x10 U-Boot> mmc dev 0 switch to partitions #0, OK mmc0(part 0) is current device U-Boot> mmc list mmc@1123: 0 (eMMC) mmc@1124: 1 (SD) U-Boot> So... whose bug is that? :) smime.p7s Description: S/MIME cryptographic signature
Re: [PATCH 1/2] firmware: PSCI: Fix PSCI support for OF live trees
On 18/06/2020 12:54, Jon Hunter wrote:
> When CONFIG_OF_LIVE is enabled, dev_of_offset() cannot be used and
> if used returns an invalid offset. This causes the call to
> fdt_stringlist_get() in the psci_probe() to fail to read the 'method'
> property from the PSCI node for the device and hence prevents PSCI
> from working. Fix this by using the ofnode_read_string() API instead
> of the fdt_stringlist_get() because this will handle reading the
> property both when CONFIG_OF_LIVE is enabled or disabled.
>
> Due to the above problem and since commit 81ea00838c68 ("efi_loader:
> PSCI reset and shutdown") was added, the EFI system reset has been
> broken for Tegra210 and Tegra196 platforms. This also fixes the EFI
> system reset for these Tegra platforms.
Oops, just spotted the above typo. Should be Tegra186 and not Tegra196
(which does not exist!). I can correct that.
Jon
--
nvpublic
Re: [GIT PULL] TI changes for v2020.10 next
On Thu, Jun 18, 2020 at 07:25:43PM +0530, Lokesh Vutla wrote: > Hi Tom, > Please find the pull request for v2020.10 next containing TI specific > changes. > > Travis-CI build: > https://travis-ci.org/github/lokeshvutla/u-boot/builds/698883325 > > The following changes since commit be79009f3b9bbdbce283e67a865121e576d790ea: > > Merge tag 'u-boot-imx-20200609' of > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-06-09 09:17:24 > -0400) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-ti.git tags/ti-v2020.10-next > > for you to fetch changes up to c0a8d6e1e67cc7feee5c9e6c7e8c13bb953734f1: > > ARM: da850-evm: Remove SPI from SPL when booting from NAND (2020-06-16 > 17:00:50 +0530) > This breaks my j6eco: U-Boot SPL 2020.07-rc4-00098-g83fdb4388253-dirty (Jun 18 2020 - 11:44:19 -0400) DRA752-GP ES1.1 Trying to boot from MMC1 no pinctrl state for default mode MMC: no card present spl: mmc init failed with error: -123 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/2] firmware: PSCI: Fix PSCI support for OF live trees
On Thu, Jun 18, 2020 at 12:55 PM Jon Hunter wrote:
>
> When CONFIG_OF_LIVE is enabled, dev_of_offset() cannot be used and
> if used returns an invalid offset. This causes the call to
> fdt_stringlist_get() in the psci_probe() to fail to read the 'method'
> property from the PSCI node for the device and hence prevents PSCI
> from working. Fix this by using the ofnode_read_string() API instead
> of the fdt_stringlist_get() because this will handle reading the
> property both when CONFIG_OF_LIVE is enabled or disabled.
>
> Due to the above problem and since commit 81ea00838c68 ("efi_loader:
> PSCI reset and shutdown") was added, the EFI system reset has been
> broken for Tegra210 and Tegra196 platforms. This also fixes the EFI
> system reset for these Tegra platforms.
>
> Signed-off-by: Jon Hunter
Tested-by: Peter Robinson
Tested on the Jetson Nano and it now reboots as expected.
> ---
> drivers/firmware/psci.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
> index e0d66d74f54d..23cf807591c4 100644
> --- a/drivers/firmware/psci.c
> +++ b/drivers/firmware/psci.c
> @@ -67,11 +67,9 @@ static int psci_bind(struct udevice *dev)
>
> static int psci_probe(struct udevice *dev)
> {
> - DECLARE_GLOBAL_DATA_PTR;
> const char *method;
>
> - method = fdt_stringlist_get(gd->fdt_blob, dev_of_offset(dev),
> "method",
> - 0, NULL);
> + method = ofnode_read_string(dev_ofnode(dev), "method");
> if (!method) {
> pr_warn("missing \"method\" property\n");
> return -ENXIO;
> --
> 2.17.1
>
Re: [PATCH 2/2] ARM: tegra: Enable PSCI support for Tegra210 and Tegra186
On Thu, Jun 18, 2020 at 12:56 PM Jon Hunter wrote:
>
> The PSCI nodes are currently not populated for the Tegra210 and Tegra186
> devices. This prevents the PSCI driver from being able to identify the
> PSCI method used by these devices and causes the probe of the PSCI
> driver to fail.
>
> Since commit 81ea00838c68 ("efi_loader: PSCI reset and shutdown") was
> added, which moves the PSCI EFI system reset handler into the PSCI
> driver, this has prevented the EFI system reset from working for
> Tegra210 and Tegra186. Therefore, populating these nodes is necessary
> to fix the EFI system reset for Tegra210 and Tegra186.
>
> Signed-off-by: Jon Hunter
Tested-by: Peter Robinson
Tested on the Jetson Nano and it now reboots as expected.
> ---
> arch/arm/dts/tegra186.dtsi | 5 +
> arch/arm/dts/tegra210.dtsi | 5 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi
> index 0a9db9825b85..edcb7aacb8ee 100644
> --- a/arch/arm/dts/tegra186.dtsi
> +++ b/arch/arm/dts/tegra186.dtsi
> @@ -335,4 +335,9 @@
> status = "disabled";
> };
> };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> };
> diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi
> index 3ec54b11c43f..a521a43d6cfd 100644
> --- a/arch/arm/dts/tegra210.dtsi
> +++ b/arch/arm/dts/tegra210.dtsi
> @@ -867,6 +867,11 @@
> };
> };
>
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts = --
> 2.17.1
>
Re: [PATCH v2 0/2] ARM: at91: Allow running SPL with DTB append
On 05.06.2020 11:43, Gregory CLEMENT wrote: > Hello, > > a few months ago I submitted a small series allowing to run SPL with > DTB append. Indeed according to the linker BSS section was all the > time separated for SPL but the symbol SPL_SEPARATE_BSS was only > enabled on some boards. > > In this v2 the changes are: > - add reviewed-by Stefan Roese > - modify a new defconfig sama5d3_xplained_nandflash_defconfig > > Thanks, > > Gregory > > > Gregory CLEMENT (2): >ARM: at91: Enable SPL_SEPARATE_BSS by default >configs: atmel: cleanup CONFIG_SPL_SEPARATE_BSS > > arch/arm/Kconfig| 1 + > configs/gardena-smart-gateway-at91sam_defconfig | 1 - > configs/sama5d27_som1_ek_mmc1_defconfig | 1 - > configs/sama5d27_som1_ek_mmc_defconfig | 1 - > configs/sama5d27_som1_ek_qspiflash_defconfig| 1 - > configs/sama5d27_wlsom1_ek_mmc_defconfig| 1 - > configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 1 - > configs/sama5d2_icp_mmc_defconfig | 1 - > configs/sama5d2_xplained_emmc_defconfig | 1 - > configs/sama5d2_xplained_mmc_defconfig | 1 - > configs/sama5d2_xplained_qspiflash_defconfig| 1 - > configs/sama5d3_xplained_mmc_defconfig | 1 - > configs/sama5d3xek_mmc_defconfig| 1 - > configs/sama5d4_xplained_mmc_defconfig | 1 - > configs/sama5d4ek_mmc_defconfig | 1 - > 15 files changed, 1 insertion(+), 14 deletions(-) > > -- > 2.26.2 > Applied to u-boot-atmel/master, Thanks!
Re: [PATCH 1/2] ARM: dts: sama5d4: fix gadget endpoint address warning
On 05.06.2020 09:51, Eugen Hristev wrote: > arch/arm/dts/at91-sama5d4ek.dtb: Warning (graph_endpoint): > /ahb/gadget@0040/endpoint@10: graph node unit address error, expected "a" > arch/arm/dts/at91-sama5d4ek.dtb: Warning (graph_endpoint): > /ahb/gadget@0040/endpoint@11: graph node unit address error, expected "b" > arch/arm/dts/at91-sama5d4ek.dtb: Warning (graph_endpoint): > /ahb/gadget@0040/endpoint@12: graph node unit address error, expected "c" > arch/arm/dts/at91-sama5d4ek.dtb: Warning (graph_endpoint): > /ahb/gadget@0040/endpoint@13: graph node unit address error, expected "d" > arch/arm/dts/at91-sama5d4ek.dtb: Warning (graph_endpoint): > /ahb/gadget@0040/endpoint@14: graph node unit address error, expected "e" > arch/arm/dts/at91-sama5d4ek.dtb: Warning (graph_endpoint): > /ahb/gadget@0040/endpoint@15: graph node unit address error, expected "f" > > Fixed by changing address in node name to hex. > > Signed-off-by: Eugen Hristev > --- Applied both to u-boot-atmel/master
[PATCH] board: amlogic: Add Odroid-N2 board support
From: Pascal Vizeli
Add a proper Odroid-N2 board support to handle the Ethernet MAC
address stored in the in-SoC eFuses.
Signed-off-by: Pascal Vizeli
Signed-off-by: Neil Armstrong
---
board/amlogic/odroid-n2/MAINTAINERS | 7 +
board/amlogic/odroid-n2/Makefile| 6
board/amlogic/odroid-n2/odroid-n2.c | 49 +
board/amlogic/w400/MAINTAINERS | 2 --
configs/odroid-n2_defconfig | 2 +-
5 files changed, 63 insertions(+), 3 deletions(-)
create mode 100644 board/amlogic/odroid-n2/MAINTAINERS
create mode 100644 board/amlogic/odroid-n2/Makefile
create mode 100644 board/amlogic/odroid-n2/odroid-n2.c
diff --git a/board/amlogic/odroid-n2/MAINTAINERS
b/board/amlogic/odroid-n2/MAINTAINERS
new file mode 100644
index 00..5627e54058
--- /dev/null
+++ b/board/amlogic/odroid-n2/MAINTAINERS
@@ -0,0 +1,7 @@
+ODROID-N2
+M: Neil Armstrong
+S: Maintained
+L: u-boot-amlo...@groups.io
+F: board/amlogic/odroid-n2/
+F: configs/odroid-n2_defconfig
+F: doc/board/amlogic/odroid-n2.rst
diff --git a/board/amlogic/odroid-n2/Makefile b/board/amlogic/odroid-n2/Makefile
new file mode 100644
index 00..68e4e2a828
--- /dev/null
+++ b/board/amlogic/odroid-n2/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2020 BayLibre, SAS
+# Author: Neil Armstrong
+
+obj-y := odroid-n2.o
diff --git a/board/amlogic/odroid-n2/odroid-n2.c
b/board/amlogic/odroid-n2/odroid-n2.c
new file mode 100644
index 00..caf7fd6810
--- /dev/null
+++ b/board/amlogic/odroid-n2/odroid-n2.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 BayLibre, SAS
+ * Author: Neil Armstrong
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define EFUSE_MAC_OFFSET 20
+#define EFUSE_MAC_SIZE 12
+#define MAC_ADDR_LEN 6
+
+int misc_init_r(void)
+{
+ u8 mac_addr[MAC_ADDR_LEN];
+ char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
+ ssize_t len;
+
+ meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+
+ if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+ len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+ efuse_mac_addr, EFUSE_MAC_SIZE);
+ if (len != EFUSE_MAC_SIZE)
+ return 0;
+
+ /* MAC is stored in ASCII format, 1bytes = 2characters */
+ for (int i = 0; i < 6; i++) {
+ tmp[0] = efuse_mac_addr[i * 2];
+ tmp[1] = efuse_mac_addr[i * 2 + 1];
+ tmp[2] = '\0';
+ mac_addr[i] = simple_strtoul(tmp, NULL, 16);
+ }
+
+ if (is_valid_ethaddr(mac_addr))
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ else
+ meson_generate_serial_ethaddr();
+ }
+
+ return 0;
+}
diff --git a/board/amlogic/w400/MAINTAINERS b/board/amlogic/w400/MAINTAINERS
index 5e837cfaef..a1b0ac8636 100644
--- a/board/amlogic/w400/MAINTAINERS
+++ b/board/amlogic/w400/MAINTAINERS
@@ -5,8 +5,6 @@ L: u-boot-amlo...@groups.io
F: board/amlogic/w400/
F: configs/khadas-vim3_defconfig
F: configs/khadas-vim3l_defconfig
-F: configs/odroid-n2_defconfig
F: doc/board/amlogic/w400.rst
F: doc/board/amlogic/khadas-vim3.rst
F: doc/board/amlogic/khadas-vim3l.rst
-F: doc/board/amlogic/odroid-n2.rst
diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig
index e0cc6e3729..063809416e 100644
--- a/configs/odroid-n2_defconfig
+++ b/configs/odroid-n2_defconfig
@@ -1,5 +1,5 @@
CONFIG_ARM=y
-CONFIG_SYS_BOARD="w400"
+CONFIG_SYS_BOARD="odroid-n2"
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x0100
CONFIG_ENV_SIZE=0x2000
--
2.22.0
[PATCH v6 8/8] spl: fit: select SPL_CRYPTO_SUPPORT for SPL_FIT_SIGNATURE
From: Heiko Stuebner Verifying FIT images obviously needs the rsa parts of crypto support and while main uboot always compiles crypto support, it's optional for SPL and we should thus select the necessary option to not end up in compile errors like: u-boot/lib/rsa/rsa-verify.c:328: undefined reference to `rsa_mod_exp' So select SPL_CRYPTO_SUPPORT in SPL_FIT_SIGNATURE. Signed-off-by: Heiko Stuebner Reviewed-by: Philipp Tomsich --- Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/Kconfig b/Kconfig index 091c500ecc..b34fbf5827 100644 --- a/Kconfig +++ b/Kconfig @@ -459,6 +459,7 @@ config SPL_FIT_SIGNATURE bool "Enable signature verification of FIT firmware within SPL" depends on SPL_DM select SPL_FIT + select SPL_CRYPTO_SUPPORT select SPL_HASH_SUPPORT select SPL_RSA select SPL_RSA_VERIFY -- 2.26.2
[PATCH v6 5/8] lib: rsa: free local arrays after use in rsa_gen_key_prop()
From: Heiko Stuebner
n, rr and rrtmp are used for internal calculations, but in the end
the results are copied into separately allocated elements of the
actual key_prop, so the n, rr and rrtmp elements are not used anymore
when returning from the function and should of course be freed.
Signed-off-by: Heiko Stuebner
---
changes in v4:
- new patch
lib/rsa/rsa-keyprop.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/lib/rsa/rsa-keyprop.c b/lib/rsa/rsa-keyprop.c
index 83b942615f..195ce30181 100644
--- a/lib/rsa/rsa-keyprop.c
+++ b/lib/rsa/rsa-keyprop.c
@@ -654,17 +654,17 @@ int rsa_gen_key_prop(const void *key, uint32_t keylen,
struct key_prop **prop)
{
struct rsa_key rsa_key;
uint32_t *n = NULL, *rr = NULL, *rrtmp = NULL;
- int rlen, i, ret;
+ int rlen, i, ret = 0;
*prop = calloc(sizeof(**prop), 1);
if (!(*prop)) {
ret = -ENOMEM;
- goto err;
+ goto out;
}
ret = rsa_parse_pub_key(&rsa_key, key, keylen);
if (ret)
- goto err;
+ goto out;
/* modulus */
/* removing leading 0's */
@@ -674,7 +674,7 @@ int rsa_gen_key_prop(const void *key, uint32_t keylen,
struct key_prop **prop)
(*prop)->modulus = malloc(rsa_key.n_sz - i);
if (!(*prop)->modulus) {
ret = -ENOMEM;
- goto err;
+ goto out;
}
memcpy((void *)(*prop)->modulus, &rsa_key.n[i], rsa_key.n_sz - i);
@@ -690,7 +690,7 @@ int rsa_gen_key_prop(const void *key, uint32_t keylen,
struct key_prop **prop)
(*prop)->public_exponent = calloc(1, sizeof(uint64_t));
if (!(*prop)->public_exponent) {
ret = -ENOMEM;
- goto err;
+ goto out;
}
memcpy((void *)(*prop)->public_exponent + sizeof(uint64_t)
- rsa_key.e_sz,
@@ -714,16 +714,15 @@ int rsa_gen_key_prop(const void *key, uint32_t keylen,
struct key_prop **prop)
(*prop)->rr = malloc(rlen);
if (!(*prop)->rr) {
ret = -ENOMEM;
- goto err;
+ goto out;
}
br_i32_encode((void *)(*prop)->rr, rlen, rr);
- return 0;
-
-err:
+out:
free(n);
free(rr);
free(rrtmp);
- rsa_free_key_prop(*prop);
+ if (ret < 0)
+ rsa_free_key_prop(*prop);
return ret;
}
--
2.26.2
[PATCH v6 6/8] lib: rsa: add documentation to padding_pss_verify to document limitations
From: Heiko Stuebner padding_pss_verify only works with the default pss salt setting of -2 (length to be automatically determined based on the PSS block structure) not -1 (salt length set to the maximum permissible value), which makes verifications of signatures with that saltlen fail. Until this gets implemented at least document this behaviour. Signed-off-by: Heiko Stuebner --- changes in v4: - new patch lib/rsa/rsa-verify.c | 13 + 1 file changed, 13 insertions(+) diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 048f1ab789..61d98e6e2d 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -194,6 +194,19 @@ out: return ret; } +/* + * padding_pss_verify() - verify the pss padding of a signature + * + * Only works with a rsa_pss_saltlen:-2 (default value) right now + * saltlen:-1 "set the salt length to the digest length" is currently + * not supported. + * + * @info: Specifies key and FIT information + * @msg: byte array of message, len equal to msg_len + * @msg_len: Message length + * @hash: Pointer to the expected hash + * @hash_len: Length of the hash + */ int padding_pss_verify(struct image_sign_info *info, uint8_t *msg, int msg_len, const uint8_t *hash, int hash_len) -- 2.26.2
[PATCH v6 4/8] lib: rsa: fix allocated size for rr and rrtmp in rsa_gen_key_prop()
From: Heiko Stuebner
When calculating rrtmp/rr rsa_gen_key_prop() tries to make
(((rlen + 31) >> 5) + 1) steps in the rr uint32_t array and
(((rlen + 7) >> 3) + 1) / 4 steps in uint32_t rrtmp[]
with rlen being num_bits * 2
On a 4096bit key this comes down to to 257 uint32_t elements
in rr and 256 elements in rrtmp but with the current allocation
rr and rrtmp only have 129 uint32_t elements.
On 2048bit keys this works by chance as the defined max_rsa_size=4096
allocates a suitable number of elements, but with an actual 4096bit key
this results in other memory parts getting overwritten.
So as suggested by Heinrich Schuchardt just use the actual bis-size
of the key as base for the size calculation, in turn making the code
compatible to any future keysizes.
Suggested-by: Heinrich Schuchardt
Signed-off-by: Heiko Stuebner
---
changes in v6:
- drop max_rsa_size and use the keysize as base
changes in v4:
- new patch
lib/rsa/rsa-keyprop.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/lib/rsa/rsa-keyprop.c b/lib/rsa/rsa-keyprop.c
index 4b54db44c4..83b942615f 100644
--- a/lib/rsa/rsa-keyprop.c
+++ b/lib/rsa/rsa-keyprop.c
@@ -654,14 +654,10 @@ int rsa_gen_key_prop(const void *key, uint32_t keylen,
struct key_prop **prop)
{
struct rsa_key rsa_key;
uint32_t *n = NULL, *rr = NULL, *rrtmp = NULL;
- const int max_rsa_size = 4096;
int rlen, i, ret;
*prop = calloc(sizeof(**prop), 1);
- n = calloc(sizeof(uint32_t), 1 + (max_rsa_size >> 5));
- rr = calloc(sizeof(uint32_t), 1 + (max_rsa_size >> 5));
- rrtmp = calloc(sizeof(uint32_t), 1 + (max_rsa_size >> 5));
- if (!(*prop) || !n || !rr || !rrtmp) {
+ if (!(*prop)) {
ret = -ENOMEM;
goto err;
}
@@ -682,6 +678,14 @@ int rsa_gen_key_prop(const void *key, uint32_t keylen,
struct key_prop **prop)
}
memcpy((void *)(*prop)->modulus, &rsa_key.n[i], rsa_key.n_sz - i);
+ n = calloc(sizeof(uint32_t), 1 + ((*prop)->num_bits >> 5));
+ rr = calloc(sizeof(uint32_t), 1 + (((*prop)->num_bits * 2) >> 5));
+ rrtmp = calloc(sizeof(uint32_t), 1 + (((*prop)->num_bits * 2) >> 5));
+ if (!n || !rr || !rrtmp) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
/* exponent */
(*prop)->public_exponent = calloc(1, sizeof(uint64_t));
if (!(*prop)->public_exponent) {
--
2.26.2
[PATCH v6 7/8] spl: fit: select SPL_HASH_SUPPORT for SPL_FIT_SIGNATURE
From: Heiko Stuebner rsa-checsum needs support for hash functions or else will run into compile errors like: u-boot/lib/rsa/rsa-checksum.c:28: undefined reference to `hash_progressive_lookup_algo' So similar to the main FIT_SIGNATURE entry selects HASH, select SPL_HASH_SUPPORT for SPL_FIT_SIGNATURE. Cc: Heinrich Schuchardt Signed-off-by: Heiko Stuebner Reviewed-by: Philipp Tomsich --- Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/Kconfig b/Kconfig index 8f3fba085a..091c500ecc 100644 --- a/Kconfig +++ b/Kconfig @@ -459,6 +459,7 @@ config SPL_FIT_SIGNATURE bool "Enable signature verification of FIT firmware within SPL" depends on SPL_DM select SPL_FIT + select SPL_HASH_SUPPORT select SPL_RSA select SPL_RSA_VERIFY select SPL_IMAGE_SIGN_INFO -- 2.26.2
[PATCH v6 2/8] lib: rsa: take spl/non-spl into account when building rsa_verify_with_pkey()
From: Heiko Stuebner
Right now in multiple places there are only checks for the full
CONFIG_RSA_VERIFY_WITH_PKEY option, not split into main,spl,tpl variants.
This breaks when the rsa functions get enabled for SPL, for example to
verify u-boot proper from spl.
So fix this by using the existing helpers to distinguis between
build-steps.
Signed-off-by: Heiko Stuebner
---
changes in v5:
- include the additional config-check that landed in patch 1/8
in v4
changes in v3.1:
- drop changeid
changes in v3:
- new patch with another build issue
lib/rsa/Makefile | 2 +-
lib/rsa/rsa-verify.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile
index c61ebfd79e..8b75d41f04 100644
--- a/lib/rsa/Makefile
+++ b/lib/rsa/Makefile
@@ -6,5 +6,5 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
obj-$(CONFIG_$(SPL_TPL_)RSA_VERIFY) += rsa-verify.o rsa-checksum.o
-obj-$(CONFIG_RSA_VERIFY_WITH_PKEY) += rsa-keyprop.o
+obj-$(CONFIG_$(SPL_TPL_)RSA_VERIFY_WITH_PKEY) += rsa-keyprop.o
obj-$(CONFIG_RSA_SOFTWARE_EXP) += rsa-mod-exp.o
diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
index 1d55b997e3..048f1ab789 100644
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -285,7 +285,7 @@ out:
}
#endif
-#if CONFIG_IS_ENABLED(FIT_SIGNATURE) || IS_ENABLED(CONFIG_RSA_VERIFY_WITH_PKEY)
+#if CONFIG_IS_ENABLED(FIT_SIGNATURE) || CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY)
/**
* rsa_verify_key() - Verify a signature against some data using RSA Key
*
@@ -359,7 +359,7 @@ static int rsa_verify_key(struct image_sign_info *info,
}
#endif
-#ifdef CONFIG_RSA_VERIFY_WITH_PKEY
+#if CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY)
/**
* rsa_verify_with_pkey() - Verify a signature against some data using
* only modulus and exponent as RSA key properties.
@@ -492,7 +492,7 @@ int rsa_verify(struct image_sign_info *info,
return -EINVAL;
}
- if (IS_ENABLED(CONFIG_RSA_VERIFY_WITH_PKEY) && !info->fdt_blob) {
+ if (CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY) && !info->fdt_blob) {
/* don't rely on fdt properties */
ret = rsa_verify_with_pkey(info, hash, sig, sig_len);
--
2.26.2
[PATCH v6 3/8] lib: rsa: bring exp_len in line when generating a key_prop
From: Heiko Stuebner The exponent field of struct key_prop gets allocated an uint64_t, and the contents are positioned from the back, so an exponent of "0x01 0x00 0x01" becomes 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1" Right now rsa_gen_key_prop() allocates a uint64_t but sets exp_len to the size returned from the parser, while on the other hand the when getting the key from the devicetree exp_len always gets set to sizeof(uint64_t). So bring that in line with the established code. Signed-off-by: Heiko Stuebner --- changes in v4: - new patch lib/rsa/rsa-keyprop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/rsa/rsa-keyprop.c b/lib/rsa/rsa-keyprop.c index 9464df0093..4b54db44c4 100644 --- a/lib/rsa/rsa-keyprop.c +++ b/lib/rsa/rsa-keyprop.c @@ -691,7 +691,7 @@ int rsa_gen_key_prop(const void *key, uint32_t keylen, struct key_prop **prop) memcpy((void *)(*prop)->public_exponent + sizeof(uint64_t) - rsa_key.e_sz, rsa_key.e, rsa_key.e_sz); - (*prop)->exp_len = rsa_key.e_sz; + (*prop)->exp_len = sizeof(uint64_t); /* n0 inverse */ br_i32_decode(n, &rsa_key.n[i], rsa_key.n_sz - i); -- 2.26.2
[PATCH v6 1/8] lib: rsa: distinguish between tpl and spl for CONFIG_RSA_VERIFY
From: Heiko Stuebner While the SPL may want to do signature checking this won't be the case for TPL in all cases, as TPL is mostly used when the amount of initial memory is not enough for a full SPL. So on a system where SPL uses DM but TPL does not we currently end up with a TPL compile error of: lib/rsa/rsa-verify.c:48:25: error: dereferencing pointer to incomplete type ‘struct checksum_algo’ To prevent that change the $(SPL_) to $(SPL_TPL_) to distinguish between both. If someone really needs FIT signature checking in TPL as well, a new TPL_RSA_VERIFY config symbol needs to be added. Signed-off-by: Heiko Stuebner Reviewed-by: Philipp Tomsich --- changes in v5: - drop change that belongs in patch 2/8 changes in v4: - amound -> amount - found another entry to handle changes in v2: - fix typo "distinguis(h)" lib/rsa/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile index 14ed3cb401..c61ebfd79e 100644 --- a/lib/rsa/Makefile +++ b/lib/rsa/Makefile @@ -5,6 +5,6 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, w...@denx.de. -obj-$(CONFIG_$(SPL_)RSA_VERIFY) += rsa-verify.o rsa-checksum.o +obj-$(CONFIG_$(SPL_TPL_)RSA_VERIFY) += rsa-verify.o rsa-checksum.o obj-$(CONFIG_RSA_VERIFY_WITH_PKEY) += rsa-keyprop.o obj-$(CONFIG_RSA_SOFTWARE_EXP) += rsa-mod-exp.o -- 2.26.2
[PATCH v2 6/6] roc-rk3399-pc: Update ENV offset, size
Adjust the ENV offset, size to fit into all images on 16MB flash. Signed-off-by: Jagan Teki --- Changes for v2: - rebase on master configs/rock-pi-4-rk3399_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 0d86fdc895..2487872219 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y @@ -35,11 +36,14 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y configs/roc-pc-mezzanine-rk3399_defconfig | 4 ++-- configs/roc-pc-rk3399_defconfig | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 7906948374..595f052cb7 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -1,8 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x0020 -CONFIG_ENV_SIZE=0x6000 -CONFIG_ENV_OFFSET=0x46 +CONFIG_ENV_SIZE=0x8000 +CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROC_PC_RK3399=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 046fb73858..1c4db3443f 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -1,8 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x0020 -CONFIG_ENV_SIZE=0x6000 -CONFIG_ENV_OFFSET=0x46 +CONFIG_ENV_SIZE=0x8000 +CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROC_PC_RK3399=y -- 2.25.1
