Re: [PATCH] sandbox, test: change hog gpio
Hello Philippe,
Am 24.07.2020 um 15:51 schrieb Philippe Reynes:
Since commit 9ba84329dc45 ("sandbox, test: add test for GPIO_HOG
function"), the gpio_a 0,1,2 and 3 are used by hog in test.dts.
But 2 leds 'sandbox:red' and 'sandbox:green' are using gpio_a 0
and 1. As hog always request his gpios, the led command on both
led is broken:
=> led sandbox:red
LED 'sandbox:red' not found (err=-16)
The gpio is already requested by hog, so it can't be enabled
for led 'sandbox:red'.
This commit change the gpio used by hog to 10, 11, 12 and 13,
so the led command could be used again with 'sandbox:red' and
'sandbox:green'.
Signed-off-by: Philippe Reynes
---
arch/sandbox/dts/test.dts | 8
test/dm/gpio.c| 12 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
Thanks!
Reviewed-by: Heiko Schocher
bye,
Heiko
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[PATCH v1 48/54] x86: coral: Add audio descriptor files
Add files describing the various audio configurations supported on coral.
These are passed to Linux in the ACPI tables.
Signed-off-by: Simon Glass
---
Changes in v1:
- Add new patch with coral audio descriptor files
.../chromebook_coral/dialog-2ch-48khz-24b.dat| Bin 0 -> 100 bytes
.../chromebook_coral/dmic-1ch-48khz-16b.dat | Bin 0 -> 3048 bytes
.../chromebook_coral/dmic-2ch-48khz-16b.dat | Bin 0 -> 3048 bytes
.../chromebook_coral/dmic-4ch-48khz-16b.dat | Bin 0 -> 3048 bytes
.../max98357-render-2ch-48khz-24b.dat| Bin 0 -> 116 bytes
5 files changed, 0 insertions(+), 0 deletions(-)
create mode 100644 board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
create mode 100644 board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
create mode 100644 board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
create mode 100644 board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
create mode 100644
board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
diff --git a/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
b/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
new file mode 100644
index
..46c0efbd0adc0883564cf8404503fa1de7c4cc33
GIT binary patch
literal 100
zcmZQzU|?WnWOx?=qy_%}|8E4u0zd*AHfO)k$iPr=0H_oQW->7YNf2go01_a;&(5v@
Oq?n-iKR*Kl2m=7w%Nqy)
literal 0
HcmV?d1
diff --git a/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
b/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
new file mode 100644
index
..6a7f2cef4efea7707f4b2c57f8278962a53ca7c6
GIT binary patch
literal 3048
zcmeH{?Q5207{-tL@yX`Po^x&`v;5##(}YE((R^uH$tuM#U0sSgT?D0{yFuU;8_>nsFU%595k~&|1!xVg3wf4xSI4XZ~IM
zY{u4OjJKW(t!KS{tklW=ulhpU*;^6P0DDUQ2)*1Nn#uTKoNYK0YV8eWFO^=pQd-I0
z4}N0qY^Y_5bg)y9{Lw%E^wyUN7lcDKfgf?OCmRV9IYAydL)XScJf;e}r)beHM
z_<>LtHcFRDi~kJm&4%vc{(=XH`x@!#_Ru|Vg*Gmfvh@Vbnf|8G{n+blmX?-D->)O4
zH$$VJl0M!jjcp6PSQ~mDKQ23r7WiB~BXsLF{Ogc5(^4Bk^9w>ZRG{tTL``=~SDnmg
zurf6H6Y0@A5+#R1Z$FvQsz*ZaEJxIJi5l+?15a!WEU$kY3-SV;wC^4jai)*M(3w`PqrCb?Cnu
z-N%ueZKp#E>F1))64vIi?^({Zz{h*!^?B@OX@mUtGB?0ljy;FTbFjaL)_~n=?l?vm
zi`chi3{v96cKT_IbNDl#GdKMen##Rh+}Dl|6POzhTN(DP!axLp@yF#@WTp-;CWU
z_;>nu_@Pywf=TY%%G!ZK7@i25S4b-e`a#bAjDK6O`+864As8zDG4#wYp%1xl8mxSC
zxzt)N9i1+1nkwyrrya1`0Z(Pe(EM{a`!v*ZB(#V7W)b)G-+78{jp#6
z`)?ZyAUdQeDt%LQjF4o67Sug8m{j8()w650II$Lk+ZvCAH=fin%
zew-)g%XxGDoJZ%=d3AoBXXo2_cmB%(>8dU4)bth%XQ{@bKSZA
pT!*+YRF|`1RF6@u|2r>V@!&&%f{a_dWl<|KHyCe*hgO-4Xx*
literal 0
HcmV?d1
diff --git a/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
b/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
new file mode 100644
index
..71d7648202154b6e8116dcf99cb7336f92731ac9
GIT binary patch
literal 3048
zcmeH{?Q7O$6vw~6dv`V;cAq_zX!*jirU{EmqxsOXl2wXfy54A^^}^Or(~PZpv(f~M
zYQ_R>L~rgn5i3N4A)!6_7(J{A3$0a-qODMKwp84@`+R3_g#LoKZ@Bi`bzSE=*E!$w
zIaea7cxomel!jnim<3P$+v<-Zc9O_!`L-}rat{odq?|J?K9
zT*f*sS;b{_Y3b>dG(HzPITWg9ua^1CeBWUH=HH=}%mLwj3%;IYzWID;E%Q2g>JM$jwlbtaY|8!!y*3b<#{98jsqt*6tuK_lQhN1T
zX*sqZ|HRt4Q0qkLKq)$$2vzlj`o~M{*GmJZLQ}p7ZNT3h)1@lZT6!?lhs^*7Px^oNhbxIoaIO_TKBTTM;Wx_|;{QI@2HDGDbA_O*;g{MK;C
zanhKN-KLR9Nf2B4PG+7Xo;jSk?XS=z?(OEj4q_-_Z47K>uv?pvzJ`YexVVe63s}D$
zzY~e?%jHsSZJ-q52kRQhA+`CmfzbRv{gmB5jx??SQ9ku-XYv<;T(db2$4n)O$3vi~FXN_s!IB=PYb$(F2_iakdRs
z=i~poy`h=gLNj1uXJ=^D4{%*39i1yJX@uPurIXFf;qO;+`V7|gEJOc_(Bjh2Z!<$>
zoZWagI*(1X_hO>e$5NVx_^*#iYejW>`0KgXy>C0)`<&0)kNw%N{reu@=X-s><8VBV
z%keo*$LqKqzw>ZD`5roxgRk9@fSBSSRac-K?K=w4T=0`dVk}ZQZTE>)?90
zF0PO3Rnp5*?Zq2VbHqYkTe4BIgZtl&$`@sF+zHooIPuwr=8~2a<$o=HLa(}tc+;8qX
n_n-Ta5Qh8G{YeP<_ub5)SN?s^zwi0?Jw5#1=im4L$NT;ddMe!=
literal 0
HcmV?d1
diff --git a/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
b/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
new file mode 100644
index
..142ab353f3736f110f30e9befbd72f7e8ae4264b
GIT binary patch
literal 3048
zcmeH{?Q7O$6vw~6dv`V;cAq_zX!*jirU{F1M)RR%C94#}biJ`c>xHeMrWsrHW~B)h
z)rSg%;;f7Sg5UX6m5l?v!=dBlH)mel!P0(0>3P$482}`6!e}?vEL-%lh;X~wogY;}?=)Si@8x}~}Mv~^tU`yyh{B^fVOUkA1
z*OJp)p;6CBpKOrEbc9~64}Cx!R~<$RVy>tT-M*Fhx};5v)cVl8!q82XXgeuU%e~Td
zr!pF@3QhV{di<_L$)V6YPiM69vCzBA5Or;$<_AJgo-5Lui$kNk6V>0GQVn_Tsx8vK
z6-7FYpPJSJ?d?sgvm~vKr77J#AZ6xCvkE0b0Ucswe20z=j4U;5rbay%L%q~z7rHi}
z|0;AJOKrBE2`%6|2YnW^Hy69-IoAds?^D+o@tb7~^M5~UL+s_SIZT}c`#MGwervho
z7-=lTZu4lQB#0e+r!vnG@>ggI_x5mKCoz<;HV(Ej*saS*-@rp7T-?FgMXcY7
z-^s*x=6CpE)SiY(?%TrNfg%_l51ZFW%SrlS+h%oALWbU+57SD*Z9^+%KVzxNj<~
ze0#OjULhTwCT*M|y$(-1VYLgM%8#M>7jX7jsP9N<5BJR^@9ETV_Z)2M&;y+hakd>+
z7vlf;{?P25p;<7oyDPN%2e>Yij?9C0)`<&0)kNw%N{reu@=X-s><8VBV
z%keo*$LqKqzw>ZD`5roxgRk9@fSBSSRac-K?K=w4T=0`dVk}ZQZTE>)?90
zF0PO3Rnp5*?Zq2VbHqYkTe4BIgZtl&$`@sF+zHooIPuwr=8~2a<$o=HLa(}tc+;8qX
n_n-Ta5Jvja{YeP<_ub5)SN?s^zwi0?Jw5W?=im4L$NT;dsY=};
literal 0
HcmV?d1
diff --git a/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
b/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
new file mode 100644
index
[PATCH v1 54/54] x86: coral: Update config and device tree for ACPI
Enable new features and provide require device-tree config so that U-Boot
produces the correct ACPI tables on Coral.
Signed-off-by: Simon Glass
---
Changes in v1:
- Add NHLT information
- Fix i2c PCI addresses
- Rename acpi-probed to linux,probed
- Rename cpi,hid-desc-reg-offset to hid-desc-addr
- UIse hid-over-i2 compatible string
- Update ACPI ordering to include multiple CPUs
- Use acpi,ddn instead of acpi,desc
arch/x86/dts/chromebook_coral.dts | 224 +++--
configs/chromebook_coral_defconfig | 11 +-
2 files changed, 220 insertions(+), 15 deletions(-)
diff --git a/arch/x86/dts/chromebook_coral.dts
b/arch/x86/dts/chromebook_coral.dts
index a17a9c28003..8c08259b001 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -15,14 +15,20 @@
#include "flashmap-16mb-rw.dtsi"
#endif
+#include
+#include
+#include
+#include
#include
#include
+#include
#include
#include
#include
#include
#include
#include
+#include
/ {
model = "Google Coral";
@@ -40,6 +46,14 @@
i2c5 = _5;
i2c6 = _6;
i2c7 = _7;
+ mmc1 =
+ };
+
+ board: board {
+ compatible = "google,coral";
+ recovery-gpios = <_nw (-1) GPIO_ACTIVE_LOW>;
+ write-protect-gpios = <_nw GPIO_75 GPIO_ACTIVE_HIGH>;
+ phase-enforce-gpios = <_n GPIO_10 GPIO_ACTIVE_HIGH>;
};
config {
@@ -48,6 +62,15 @@
chosen {
stdout-path =
+ e820-entries = /bits/ 64 <
+ IOMAP_P2SB_BAR IOMAP_P2SB_SIZE E820_RESERVED
+ MCH_BASE_ADDRESS MCH_SIZE E820_RESERVED>;
+ u-boot,acpi-ssdt-order = <_0 _1 _2 _3
+ _0 _1 _2 _3 _4 _5
+_codec _codec
+ _touchscreen _touchscreen
+ _touchpad _touchpad _digitizer>;
+ u-boot,acpi-dsdt-order = < >;
};
clk: clock {
@@ -60,7 +83,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu_0: cpu@0 {
u-boot,dm-pre-reloc;
device_type = "cpu";
compatible = "intel,apl-cpu";
@@ -68,21 +91,21 @@
intel,apic-id = <0>;
};
- cpu@1 {
+ cpu_1: cpu@1 {
device_type = "cpu";
compatible = "intel,apl-cpu";
reg = <1>;
intel,apic-id = <2>;
};
- cpu@2 {
+ cpu_2: cpu@2 {
device_type = "cpu";
compatible = "intel,apl-cpu";
reg = <2>;
intel,apic-id = <4>;
};
- cpu@3 {
+ cpu_3: cpu@3 {
device_type = "cpu";
compatible = "intel,apl-cpu";
reg = <3>;
@@ -128,6 +151,10 @@
*/
fsp_s: fsp-s {
};
+
+ nhlt {
+ intel,dmic-channels = <4>;
+ };
};
punit@0,1 {
@@ -136,21 +163,29 @@
compatible = "intel,apl-punit";
};
+ gma@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ compatible = "vesa-fb";
+ };
+
p2sb: p2sb@d,0 {
u-boot,dm-pre-reloc;
reg = <0x02006810 0 0 0 0>;
compatible = "intel,p2sb";
early-regs = ;
+ pci,no-autoconfig;
n {
compatible = "intel,apl-pinctrl";
u-boot,dm-pre-reloc;
intel,p2sb-port-id = ;
+ acpi,path = "\\_SB.GPO0";
gpio_n: gpio-n {
compatible = "intel,gpio";
u-boot,dm-pre-reloc;
gpio-controller;
#gpio-cells = <2>;
+ linux-name = "INT3452:00";
};
};
@@ -159,11 +194,13 @@
compatible = "intel,apl-pinctrl";
intel,p2sb-port-id = ;
#gpio-cells = <2>;
+ acpi,path = "\\_SB.GPO1";
gpio_nw: gpio-nw {
compatible = "intel,gpio";
[PATCH v1 51/54] x86: fsp: Show FSP-S or FSP-M address in fsp_get_header()
At present this function only supports FSP-M but it is also used to read
FSP-S, in which case FSP-M may be zero. Add support for showing whichever
address is present in the FSP binary.
Also change the debug() statements to log_debug() while here.
Signed-off-by: Simon Glass
---
arch/x86/lib/fsp2/fsp_support.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/x86/lib/fsp2/fsp_support.c b/arch/x86/lib/fsp2/fsp_support.c
index 3f2ca840dc9..f220ef498b0 100644
--- a/arch/x86/lib/fsp2/fsp_support.c
+++ b/arch/x86/lib/fsp2/fsp_support.c
@@ -35,7 +35,8 @@ int fsp_get_header(ulong offset, ulong size, bool
use_spi_flash,
*
* You are in a maze of twisty little headers all alike.
*/
- debug("offset=%x buf=%x\n", (uint)offset, (uint)buf);
+ log_debug("offset=%x buf=%x, use_spi_flash=%d\n", (uint)offset,
+ (uint)buf, use_spi_flash);
if (use_spi_flash) {
ret = uclass_first_device_err(UCLASS_SPI_FLASH, );
if (ret)
@@ -52,16 +53,16 @@ int fsp_get_header(ulong offset, ulong size, bool
use_spi_flash,
fv = ptr;
/* Check the FV signature, _FVH */
- debug("offset=%x sign=%x\n", (uint)offset, (uint)fv->sign);
+ log_debug("offset=%x sign=%x\n", (uint)offset, (uint)fv->sign);
if (fv->sign != EFI_FVH_SIGNATURE)
return log_msg_ret("Base FV signature", -EINVAL);
/* Go to the end of the FV header and align the address */
- debug("fv->ext_hdr_off = %x\n", fv->ext_hdr_off);
+ log_debug("fv->ext_hdr_off = %x\n", fv->ext_hdr_off);
ptr += fv->ext_hdr_off;
exhdr = ptr;
ptr += ALIGN(exhdr->ext_hdr_size, 8);
- debug("ptr=%x\n", ptr - (void *)buf);
+ log_debug("ptr=%x\n", ptr - (void *)buf);
/* Check the FFS GUID */
file_hdr = ptr;
@@ -71,7 +72,7 @@ int fsp_get_header(ulong offset, ulong size, bool
use_spi_flash,
ptr = file_hdr + 1;
raw = ptr;
- debug("raw->type = %x\n", raw->type);
+ log_debug("raw->type = %x\n", raw->type);
if (raw->type != EFI_SECTION_RAW)
return log_msg_ret("Section type not RAW", -ENOEXEC);
@@ -80,13 +81,18 @@ int fsp_get_header(ulong offset, ulong size, bool
use_spi_flash,
fsp = ptr;
/* Check the FSPH header */
- debug("fsp %x\n", (uint)fsp);
+ log_debug("fsp %x, fsp-buf=%x, si=%x\n", (uint)fsp, ptr - (void *)buf,
+ (void *)>fsp_silicon_init - (void *)buf);
if (fsp->sign != EFI_FSPH_SIGNATURE)
return log_msg_ret("Base FSPH signature", -EACCES);
base = (void *)fsp->img_base;
- debug("Image base %x\n", (uint)base);
- debug("Image addr %x\n", (uint)fsp->fsp_mem_init);
+ log_debug("image base %x\n", (uint)base);
+ if (fsp->fsp_mem_init)
+ log_debug("mem_init offset %x\n", (uint)fsp->fsp_mem_init);
+ else if (fsp->fsp_silicon_init)
+ log_debug("silicon_init offset %x\n",
+ (uint)fsp->fsp_silicon_init);
if (use_spi_flash) {
ret = spi_flash_read_dm(dev, offset, size, base);
if (ret)
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 52/54] acpi: Use defines for field lengths
A few fields have an open-coded length. Use the defines for this purpose
instead.
Signed-off-by: Simon Glass
---
include/acpi/acpi_table.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index 9fba6536f50..3a243bf19ce 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -13,6 +13,7 @@
#ifndef __ACPI_TABLE_H__
#define __ACPI_TABLE_H__
+#include
#include
#define RSDP_SIG "RSD PTR " /* RSDP pointer signature */
@@ -48,7 +49,7 @@ struct acpi_rsdp {
/* Generic ACPI header, provided by (almost) all tables */
struct __packed acpi_table_header {
- char signature[4]; /* ACPI signature (4 ASCII characters) */
+ char signature[ACPI_NAME_LEN]; /* ACPI signature (4 ASCII chars) */
u32 length; /* Table length in bytes (incl. header) */
u8 revision;/* Table version (not ACPI version!) */
volatile u8 checksum; /* To make sum of entire table == 0 */
@@ -263,7 +264,7 @@ struct __packed acpi_fadt {
/* FACS (Firmware ACPI Control Structure) */
struct acpi_facs {
- char signature[4]; /* "FACS" */
+ char signature[ACPI_NAME_LEN]; /* "FACS" */
u32 length; /* Length in bytes (>= 64) */
u32 hardware_signature; /* Hardware signature */
u32 firmware_waking_vector; /* Firmware waking vector */
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 53/54] x86: Add a way to add to the e820 memory table
Some boards want to reserve extra regions of memory. Add a 'chosen'
property to support this.
Signed-off-by: Simon Glass
---
arch/x86/lib/fsp/fsp_dram.c | 17 +
doc/device-tree-bindings/chosen.txt | 18 ++
2 files changed, 35 insertions(+)
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 01d498c21ed..5e0da610b3c 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -92,6 +93,8 @@ unsigned int install_e820_map(unsigned int max_entries,
unsigned int num_entries = 0;
const struct hob_header *hdr;
struct hob_res_desc *res_desc;
+ const fdt64_t *prop;
+ int size;
hdr = gd->arch.hob_list;
@@ -133,6 +136,20 @@ unsigned int install_e820_map(unsigned int max_entries,
num_entries++;
}
+ prop = ofnode_read_chosen_prop("e820-entries", );
+ if (prop) {
+ int count = size / (sizeof(u64) * 3);
+ int i;
+
+ if (num_entries + count >= max_entries)
+ return -ENOSPC;
+ for (i = 0; i < count; i++, num_entries++, prop += 3) {
+ entries[num_entries].addr = fdt64_to_cpu(prop[0]);
+ entries[num_entries].size = fdt64_to_cpu(prop[1]);
+ entries[num_entries].type = fdt64_to_cpu(prop[2]);
+ }
+ }
+
return num_entries;
}
diff --git a/doc/device-tree-bindings/chosen.txt
b/doc/device-tree-bindings/chosen.txt
index d4dfc05847b..e5ba6720ce1 100644
--- a/doc/device-tree-bindings/chosen.txt
+++ b/doc/device-tree-bindings/chosen.txt
@@ -143,3 +143,21 @@ This provides the ordering to use when writing device data
to the ACPI SSDT
node to add. The ACPI information is written in this order.
If the ordering does not include all nodes, an error is generated.
+
+e820-entries
+
+
+This provides a way to add entries to the e820 table which tells the OS about
+the memory map. The property contains three sets of 64-bit values:
+
+ address - Start address of region
+ size - Size of region
+ flags - Flags (E820_...)
+
+Example:
+
+chosen {
+ e820-entries = /bits/ 64 <
+ IOMAP_P2SB_BAR IOMAP P2SB_SIZE E820_RESERVED
+ MCH_BASE_ADDRESS MCH_SIZE E820_RESERVED>;
+};
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 50/54] x86: fsp: Add more debugging for silicon init
If locating the FSP header hangs for whatever reason it is useful to see
where it got stuck. Add a debug print. Also show the address of the FSP-S
entry point as a sanity check.
Signed-off-by: Simon Glass
---
arch/x86/lib/fsp2/fsp_silicon_init.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/lib/fsp2/fsp_silicon_init.c
b/arch/x86/lib/fsp2/fsp_silicon_init.c
index 0f221a864fb..ead3493de82 100644
--- a/arch/x86/lib/fsp2/fsp_silicon_init.c
+++ b/arch/x86/lib/fsp2/fsp_silicon_init.c
@@ -26,8 +26,10 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash)
struct binman_entry entry;
struct udevice *dev;
ulong rom_offset = 0;
+ u32 init_addr;
int ret;
+ log_debug("Locating FSP\n");
ret = fsp_locate_fsp(FSP_S, , use_spi_flash, , ,
_offset);
if (ret)
@@ -44,7 +46,7 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash)
ret = fsps_update_config(dev, rom_offset, );
if (ret)
return log_msg_ret("Could not setup config", ret);
- log_debug("Silicon init...");
+ log_debug("Silicon init @ %x...", init_addr);
bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_S, "fsp-s");
func = (fsp_silicon_init_func)(hdr->img_base + hdr->fsp_silicon_init);
ret = func();
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 46/54] acpi: tpm: Add a TPM1 table
This provides information about a v1 TPM in the system. Generate this
table if the TPM is present.
Add a required new bloblist type and correct the header order of one
header file.
Signed-off-by: Simon Glass
---
arch/x86/lib/acpi_table.c | 54 ++-
include/acpi/acpi_table.h | 7 +
include/bloblist.h| 1 +
3 files changed, 61 insertions(+), 1 deletion(-)
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 9b13880f996..a3db94b8318 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -215,6 +215,47 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
header->checksum = table_compute_checksum((void *)mcfg, header->length);
}
+/**
+ * acpi_create_tcpa() - Create a TCPA table
+ *
+ * @tcpa: Pointer to place to put table
+ *
+ * Trusted Computing Platform Alliance Capabilities Table
+ * TCPA PC Specific Implementation SpecificationTCPA is defined in the PCI
+ * Firmware Specification 3.0
+ */
+static int acpi_create_tcpa(struct acpi_tcpa *tcpa)
+{
+ struct acpi_table_header *header = >header;
+ u32 current = (u32)tcpa + sizeof(struct acpi_tcpa);
+ int size = 0x1; /* Use this as the default size */
+ void *log;
+ int ret;
+
+ if (!CONFIG_IS_ENABLED(BLOBLIST))
+ return -ENXIO;
+ memset(tcpa, '\0', sizeof(struct acpi_tcpa));
+
+ /* Fill out header fields */
+ acpi_fill_header(header, "TCPA");
+ header->length = sizeof(struct acpi_tcpa);
+ header->revision = 1;
+
+ ret = bloblist_ensure_size_ret(BLOBLISTT_TCPA_LOG, , );
+ if (ret)
+ return log_msg_ret("blob", ret);
+
+ tcpa->platform_class = 0;
+ tcpa->laml = size;
+ tcpa->lasa = (ulong)log;
+
+ /* (Re)calculate length and checksum */
+ header->length = current - (u32)tcpa;
+ header->checksum = table_compute_checksum((void *)tcpa, header->length);
+
+ return 0;
+}
+
static int get_tpm2_log(void **ptrp, int *sizep)
{
const int tpm2_default_log_len = 0x1;
@@ -455,11 +496,13 @@ ulong write_acpi_tables(ulong start_addr)
struct acpi_fadt *fadt;
struct acpi_table_header *ssdt;
struct acpi_mcfg *mcfg;
+ struct acpi_tcpa *tcpa;
struct acpi_madt *madt;
struct acpi_csrt *csrt;
struct acpi_spcr *spcr;
void *start;
ulong addr;
+ int ret;
int i;
start = map_sysmem(start_addr, 0);
@@ -547,7 +590,6 @@ ulong write_acpi_tables(ulong start_addr)
if (IS_ENABLED(CONFIG_TPM_V2)) {
struct acpi_tpm2 *tpm2;
- int ret;
debug("ACPI:* TPM2\n");
tpm2 = (struct acpi_tpm2 *)ctx->current;
@@ -566,6 +608,16 @@ ulong write_acpi_tables(ulong start_addr)
acpi_inc_align(ctx, madt->header.length);
acpi_add_table(ctx, madt);
+ debug("ACPI:* TCPA\n");
+ tcpa = (struct acpi_tcpa *)ctx->current;
+ ret = acpi_create_tcpa(tcpa);
+ if (ret) {
+ log_warning("Failed to create TCPA table (err=%d)\n", ret);
+ } else {
+ acpi_inc_align(ctx, tcpa->header.length);
+ acpi_add_table(ctx, tcpa);
+ }
+
debug("ACPI:* CSRT\n");
csrt = ctx->current;
if (!acpi_create_csrt(csrt)) {
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index c7ee8b55da4..9fba6536f50 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -104,6 +104,13 @@ struct __packed acpi_tpm2 {
u64 lasa;
};
+struct __packed acpi_tcpa {
+ struct acpi_table_header header;
+ u16 platform_class;
+ u32 laml;
+ u64 lasa;
+};
+
/* FADT Preferred Power Management Profile */
enum acpi_pm_profile {
ACPI_PM_UNSPECIFIED = 0,
diff --git a/include/bloblist.h b/include/bloblist.h
index dc7d80bd851..5784c2226e7 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -34,6 +34,7 @@ enum bloblist_tag_t {
BLOBLISTT_ACPI_GNVS,
BLOBLISTT_INTEL_VBT,/* Intel Video-BIOS table */
BLOBLISTT_TPM2_TCG_LOG, /* TPM v2 log space */
+ BLOBLISTT_TCPA_LOG, /* TPM log space */
};
/**
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 40/54] x86: Sort the MTRR table
At present the MTRR registers are programmed with the list the U-Boot
builds up in the same order. In some cases this list may be out of order.
It looks better in Linux to have the registers in order, so sort them,
Signed-off-by: Simon Glass
---
arch/x86/cpu/mtrr.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index 2468d88a80a..08fa80f8bc7 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -124,6 +125,16 @@ static int mtrr_copy_to_aps(void)
return 0;
}
+static int h_comp_mtrr(const void *p1, const void *p2)
+{
+ const struct mtrr_request *req1 = p1;
+ const struct mtrr_request *req2 = p2;
+
+ s64 diff = req1->start - req2->start;
+
+ return diff < 0 ? -1 : diff > 0 ? 1 : 0;
+}
+
int mtrr_commit(bool do_caches)
{
struct mtrr_request *req = gd->arch.mtrr_req;
@@ -139,6 +150,7 @@ int mtrr_commit(bool do_caches)
debug("open\n");
mtrr_open(, do_caches);
debug("open done\n");
+ qsort(req, gd->arch.mtrr_req_count, sizeof(*req), h_comp_mtrr);
for (i = 0; i < gd->arch.mtrr_req_count; i++, req++)
set_var_mtrr(i, req->type, req->start, req->size);
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 47/54] x86: acpi: Set the log category for x86 table generation
This file doesn't currently have a log category. Add one so that items are logged correctly. Signed-off-by: Simon Glass --- arch/x86/lib/acpi_table.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index a3db94b8318..faab9d9de3c 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -6,6 +6,8 @@ * Copyright (C) 2016, Bin Meng */ +#define LOG_CATEGORY LOGC_ACPI + #include #include #include -- 2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 49/54] x86: apl: Check low-level init in FSP-S pre-init
If U-Boot is not running FSP-S it should not do the pre-init either. Add a
condition to handle this.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/fsp_s.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index e54b0ac1047..715ceab6ac7 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -157,6 +157,8 @@ int arch_fsps_preinit(void)
struct udevice *itss;
int ret;
+ if (!ll_boot_init())
+ return 0;
ret = irq_first_device_type(X86_IRQT_ITSS, );
if (ret)
return log_msg_ret("no itss", ret);
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 45/54] acpi: tpm: Add a TPM2 table
This provides information about a v2 TPM in the system. Generate this
table if the TPM is present.
Signed-off-by: Simon Glass
---
arch/x86/lib/acpi_table.c | 74 +++
include/acpi/acpi_table.h | 11 ++
include/bloblist.h| 1 +
3 files changed, 86 insertions(+)
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 667059b5ace..9b13880f996 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -7,6 +7,7 @@
*/
#include
+#include
#include
#include
#include
@@ -214,6 +215,64 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
header->checksum = table_compute_checksum((void *)mcfg, header->length);
}
+static int get_tpm2_log(void **ptrp, int *sizep)
+{
+ const int tpm2_default_log_len = 0x1;
+ int size;
+ int ret;
+
+ *sizep = 0;
+ size = tpm2_default_log_len;
+ ret = bloblist_ensure_size_ret(BLOBLISTT_TPM2_TCG_LOG, , ptrp);
+ if (ret)
+ return log_msg_ret("blob", ret);
+ *sizep = size;
+
+ return 0;
+}
+
+static int acpi_create_tpm2(struct acpi_tpm2 *tpm2)
+{
+ struct acpi_table_header *header = >header;
+ int tpm2_log_len;
+ void *lasa;
+ int ret;
+
+ memset((void *)tpm2, 0, sizeof(struct acpi_tpm2));
+
+ /*
+* Some payloads like SeaBIOS depend on log area to use TPM2.
+* Get the memory size and address of TPM2 log area or initialize it.
+*/
+ ret = get_tpm2_log(, _log_len);
+ if (ret)
+ return ret;
+
+ /* Fill out header fields. */
+ acpi_fill_header(header, "TPM2");
+ memcpy(header->aslc_id, ASLC_ID, 4);
+
+ header->length = sizeof(struct acpi_tpm2);
+ header->revision = acpi_get_table_revision(ACPITAB_TPM2);
+
+ /* Hard to detect for coreboot. Just set it to 0 */
+ tpm2->platform_class = 0;
+
+ /* Must be set to 0 for FIFO-interface support */
+ tpm2->control_area = 0;
+ tpm2->start_method = 6;
+ memset(tpm2->msp, 0, sizeof(tpm2->msp));
+
+ /* Fill the log area size and start address fields. */
+ tpm2->laml = tpm2_log_len;
+ tpm2->lasa = (uintptr_t)lasa;
+
+ /* Calculate checksum. */
+ header->checksum = table_compute_checksum((void *)tpm2, header->length);
+
+ return 0;
+}
+
__weak u32 acpi_fill_csrt(u32 current)
{
return 0;
@@ -486,6 +545,21 @@ ulong write_acpi_tables(ulong start_addr)
acpi_inc_align(ctx, mcfg->header.length);
acpi_add_table(ctx, mcfg);
+ if (IS_ENABLED(CONFIG_TPM_V2)) {
+ struct acpi_tpm2 *tpm2;
+ int ret;
+
+ debug("ACPI:* TPM2\n");
+ tpm2 = (struct acpi_tpm2 *)ctx->current;
+ ret = acpi_create_tpm2(tpm2);
+ if (!ret) {
+ acpi_inc_align(ctx, tpm2->header.length);
+ acpi_add_table(ctx, tpm2);
+ } else {
+ log_warning("TPM2 table creation failed\n");
+ }
+ }
+
debug("ACPI:* MADT\n");
madt = ctx->current;
acpi_create_madt(madt);
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index a2e510cf56e..c7ee8b55da4 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -93,6 +93,17 @@ struct __packed acpi_hpet {
u8 attributes;
};
+struct __packed acpi_tpm2 {
+ struct acpi_table_header header;
+ u16 platform_class;
+ u8 reserved[2];
+ u64 control_area;
+ u32 start_method;
+ u8 msp[12];
+ u32 laml;
+ u64 lasa;
+};
+
/* FADT Preferred Power Management Profile */
enum acpi_pm_profile {
ACPI_PM_UNSPECIFIED = 0,
diff --git a/include/bloblist.h b/include/bloblist.h
index 7d8480548e0..dc7d80bd851 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -33,6 +33,7 @@ enum bloblist_tag_t {
*/
BLOBLISTT_ACPI_GNVS,
BLOBLISTT_INTEL_VBT,/* Intel Video-BIOS table */
+ BLOBLISTT_TPM2_TCG_LOG, /* TPM v2 log space */
};
/**
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 44/54] x86: Correct handling of MADT table CPUs
At present if hyperthreading is disabled the CPU numbering is not
sequential. Fix this.
Signed-off-by: Simon Glass
---
arch/x86/lib/acpi_table.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index b0cc1f123e2..667059b5ace 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -66,14 +66,17 @@ int acpi_create_madt_lapics(u32 current)
{
struct udevice *dev;
int total_length = 0;
+ int cpu_num = 0;
for (uclass_find_first_device(UCLASS_CPU, );
dev;
uclass_find_next_device()) {
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
- int length = acpi_create_madt_lapic(
- (struct acpi_madt_lapic *)current,
- plat->cpu_id, plat->cpu_id);
+ int length;
+
+ length = acpi_create_madt_lapic(
+ (struct acpi_madt_lapic *)current, cpu_num++,
+ plat->cpu_id);
current += length;
total_length += length;
}
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 41/54] x86: Notify the FSP of the 'end firmware' event
Send this notification when U-Boot is about to boot into Linux, as
requested by the FSP.
Currently this causes a crash with the APL FSP, so leave it disabled for
now.
Signed-off-by: Simon Glass
---
arch/x86/cpu/cpu.c| 15 +++
arch/x86/lib/fsp/fsp_common.c | 16
2 files changed, 31 insertions(+)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 69c14189d1f..f8692753963 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -189,6 +189,14 @@ __weak void board_final_init(void)
{
}
+/*
+ * Implement a weak default function for boards that need to do some final
+ * processing before booting the OS.
+ */
+__weak void board_final_cleanup(void)
+{
+}
+
int last_stage_init(void)
{
struct acpi_fadt __maybe_unused *fadt;
@@ -218,6 +226,13 @@ int last_stage_init(void)
}
}
+ /*
+* TODO(s...@chromium.org): Move this to bootm_announce_and_cleanup()
+* once APL FSP-S at 0x20 does not overlap with the bzimage at
+* 0x10.
+*/
+ board_final_cleanup();
+
return 0;
}
#endif
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index ea529547254..4061fa244c4 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -60,6 +60,22 @@ void board_final_init(void)
debug("OK\n");
}
+void board_final_cleanup(void)
+{
+ u32 status;
+
+ /* TODO(s...@chromium.org): This causes Linux to crash */
+ return;
+
+ /* call into FspNotify */
+ debug("Calling into FSP (notify phase INIT_PHASE_END_FIRMWARE): ");
+ status = fsp_notify(NULL, INIT_PHASE_END_FIRMWARE);
+ if (status)
+ debug("fail, error code %x\n", status);
+ else
+ debug("OK\n");
+}
+
int fsp_save_s3_stack(void)
{
struct udevice *dev;
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 42/54] x86: Correct the assembly guard in e820.h
This is currently in the wrong place, so including the file in the device
tree fails. Fix it.
Signed-off-by: Simon Glass
---
Changes in v1:
- Update commit message with a comma
arch/x86/include/asm/e820.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h
index 9d29f82f972..87af0f492ec 100644
--- a/arch/x86/include/asm/e820.h
+++ b/arch/x86/include/asm/e820.h
@@ -21,10 +21,9 @@ struct e820_entry {
#define ISA_START_ADDRESS 0xa
#define ISA_END_ADDRESS0x10
-#endif /* __ASSEMBLY__ */
-
/* Implementation defined function to install an e820 map */
unsigned int install_e820_map(unsigned int max_entries,
struct e820_entry *);
+#endif /* __ASSEMBLY__ */
#endif /* _ASM_X86_E820_H */
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 43/54] x86: Add a header guard to asm/acpi_table.h
This file cannot currently be included in ASL files. Add a header guard to permit this. Signed-off-by: Simon Glass --- arch/x86/include/asm/acpi_table.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index faf31730730..1b49ccadc0c 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -9,6 +9,8 @@ #ifndef __ASM_ACPI_TABLE_H__ #define __ASM_ACPI_TABLE_H__ +#ifndef __ACPI__ + struct acpi_facs; struct acpi_fadt; struct acpi_global_nvs; @@ -213,4 +215,6 @@ void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs, */ void intel_acpi_fill_fadt(struct acpi_fadt *fadt); +#endif /* !__ACPI__ */ + #endif /* __ASM_ACPI_TABLE_H__ */ -- 2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 37/54] tpm: cr50: Add ACPI support
Generate ACPI information for this device so that Linux can use it
correctly.
Signed-off-by: Simon Glass
---
Changes in v1:
- Capitalise ACPI_OPS_PTR
- Update for acpi_device_write_i2c_dev() return-value change
- Use acpi,ddn instead of acpi,desc
drivers/tpm/cr50_i2c.c | 55 ++
1 file changed, 55 insertions(+)
diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c
index 1942c07c605..64831a42232 100644
--- a/drivers/tpm/cr50_i2c.c
+++ b/drivers/tpm/cr50_i2c.c
@@ -14,11 +14,14 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
#include
#include
+#include
enum {
TIMEOUT_INIT_MS = 3, /* Very long timeout for TPM init */
@@ -581,6 +584,53 @@ static int cr50_i2c_cleanup(struct udevice *dev)
return 0;
}
+static int cr50_acpi_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ char scope[ACPI_PATH_MAX];
+ char name[ACPI_NAME_MAX];
+ const char *hid;
+ int ret;
+
+ ret = acpi_device_scope(dev, scope, sizeof(scope));
+ if (ret)
+ return log_msg_ret("scope", ret);
+ ret = acpi_get_name(dev, name);
+ if (ret)
+ return log_msg_ret("name", ret);
+
+ hid = dev_read_string(dev, "acpi,hid");
+ if (!hid)
+ return log_msg_ret("hid", ret);
+
+ /* Device */
+ acpigen_write_scope(ctx, scope);
+ acpigen_write_device(ctx, name);
+ acpigen_write_name_string(ctx, "_HID", hid);
+ acpigen_write_name_integer(ctx, "_UID",
+ dev_read_u32_default(dev, "acpi,uid", 0));
+ acpigen_write_name_string(ctx, "_DDN",
+ dev_read_string(dev, "acpi,ddn"));
+ acpigen_write_sta(ctx, acpi_device_status(dev));
+
+ /* Resources */
+ acpigen_write_name(ctx, "_CRS");
+ acpigen_write_resourcetemplate_header(ctx);
+ ret = acpi_device_write_i2c_dev(ctx, dev);
+ if (ret < 0)
+ return log_msg_ret("i2c", ret);
+ ret = acpi_device_write_interrupt_or_gpio(ctx, (struct udevice *)dev,
+ "ready-gpios");
+ if (ret < 0)
+ return log_msg_ret("irq_gpio", ret);
+
+ acpigen_write_resourcetemplate_footer(ctx);
+
+ acpigen_pop_len(ctx); /* Device */
+ acpigen_pop_len(ctx); /* Scope */
+
+ return 0;
+}
+
enum {
TPM_TIMEOUT_MS = 5,
SHORT_TIMEOUT_MS= 750,
@@ -653,6 +703,10 @@ static int cr50_i2c_probe(struct udevice *dev)
return 0;
}
+struct acpi_ops cr50_acpi_ops = {
+ .fill_ssdt = cr50_acpi_fill_ssdt,
+};
+
static const struct tpm_ops cr50_i2c_ops = {
.open = cr50_i2c_open,
.get_desc = cr50_i2c_get_desc,
@@ -675,5 +729,6 @@ U_BOOT_DRIVER(cr50_i2c) = {
.probe = cr50_i2c_probe,
.remove = cr50_i2c_cleanup,
.priv_auto_alloc_size = sizeof(struct cr50_priv),
+ ACPI_OPS_PTR(_acpi_ops)
.flags = DM_FLAG_OS_PREPARE,
};
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 36/54] x86: apl: Drop unnecessary code in PMC driver
We don't have CONFIG_PCI in TPL but it is present in SPL, etc. So this
code is not needed. Drop it, and fix a code-style nit just above.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/pmc.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c
index 192dec7109a..576d0187570 100644
--- a/arch/x86/cpu/apollolake/pmc.c
+++ b/arch/x86/cpu/apollolake/pmc.c
@@ -118,7 +118,8 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
int size;
int ret;
- ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
+ ret = dev_read_u32_array(dev, "early-regs", base,
+ARRAY_SIZE(base));
if (ret)
return log_msg_ret("Missing/short early-regs", ret);
if (spl_phase() == PHASE_TPL) {
@@ -133,11 +134,6 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
}
upriv->acpi_base = base[4];
- /* Since PCI is not enabled, we must get the BDF manually */
- plat->bdf = pci_get_devfn(dev);
- if (plat->bdf < 0)
- return log_msg_ret("Cannot get PMC PCI address", plat->bdf);
-
/* Get the dwX values for pmc gpe settings */
size = dev_read_size(dev, "gpe0-dw");
if (size < 0)
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 39/54] x86: cpu: Report address width from cpu_get_info()
Add support for this new field in the common code used by most x86 CPU
drivers.
Signed-off-by: Simon Glass
---
arch/x86/cpu/i386/cpu.c | 23 +++
arch/x86/cpu/intel_common/cpu.c | 1 +
arch/x86/cpu/x86_64/cpu.c | 5 +
arch/x86/include/asm/cpu.h | 9 +
4 files changed, 38 insertions(+)
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 8f342dd06e2..7517b756f43 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -34,6 +34,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#define CPUID_FEATURE_PAE BIT(6)
+#define CPUID_FEATURE_PSE36BIT(17)
+#define CPUID_FEAURE_HTT BIT(28)
+
/*
* Constructor for a conventional segment GDT (or LDT) entry
* This is a macro so it can be used in initialisers
@@ -388,6 +392,25 @@ static void setup_identity(void)
}
}
+static uint cpu_cpuid_extended_level(void)
+{
+ return cpuid_eax(0x8000);
+}
+
+int cpu_phys_address_size(void)
+{
+ if (!has_cpuid())
+ return 32;
+
+ if (cpu_cpuid_extended_level() >= 0x8008)
+ return cpuid_eax(0x8008) & 0xff;
+
+ if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+ return 36;
+
+ return 32;
+}
+
/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
static void setup_pci_ram_top(void)
{
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index d8a3d60ae72..39aa0f63c65 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -127,6 +127,7 @@ int cpu_intel_get_info(struct cpu_info *info, int bclk)
info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 100;
info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
+ info->address_width = cpu_phys_address_size();
return 0;
}
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 1b4d3971b04..90a766c3c57 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -70,3 +70,8 @@ int x86_cpu_reinit_f(void)
{
return 0;
}
+
+int cpu_phys_address_size(void)
+{
+ return CONFIG_CPU_ADDR_BITS;
+}
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 21a05dab7de..5b001bbee21 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -288,4 +288,13 @@ u32 cpu_get_family_model(void);
*/
u32 cpu_get_stepping(void);
+/**
+ * cpu_phys_address_size() - Get the physical address size in bits
+ *
+ * This is 32 for older CPUs but newer ones may support 36.
+ *
+ * @return address size (typically 32 or 36)
+ */
+int cpu_phys_address_size(void);
+
#endif
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 38/54] x86: fsp: Update the FSP API with the end-firmware method
This new method is intended to be called when UEFI shuts down the 'boot
services', i.e. any lingering code in the boot loader that might be used
by the OS.
Add a definition for this new method and update the comments a little.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/fsp/fsp_api.h | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/fsp/fsp_api.h
b/arch/x86/include/asm/fsp/fsp_api.h
index 4941e2d74f0..3a9b61903c0 100644
--- a/arch/x86/include/asm/fsp/fsp_api.h
+++ b/arch/x86/include/asm/fsp/fsp_api.h
@@ -10,9 +10,18 @@
enum fsp_phase {
/* Notification code for post PCI enuermation */
- INIT_PHASE_PCI = 0x20,
- /* Notification code before transferring control to the payload */
- INIT_PHASE_BOOT = 0x40
+ INIT_PHASE_PCI = 0x20,
+ /*
+* Notification code before transferring control to the payload.
+* This is issued at the end of init before starting main(), i.e.
+* the command line / boot script.
+*/
+ INIT_PHASE_BOOT = 0x40,
+ /*
+* Notification code before existing boot services. This is issued
+* just before removing devices and booting the kernel.
+*/
+ INIT_PHASE_END_FIRMWARE = 0xf0,
};
struct fsp_notify_params {
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 35/54] x86: apl: Generate ACPI table for LPC
Add an ACPI table for the LPC on Apollo Lake.
Signed-off-by: Simon Glass
---
Changes in v1:
- Capitalise ACPI_OPS_PTR
arch/x86/cpu/apollolake/lpc.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c
index b81a458f2eb..a29832c879a 100644
--- a/arch/x86/cpu/apollolake/lpc.c
+++ b/arch/x86/cpu/apollolake/lpc.c
@@ -9,10 +9,14 @@
#include
#include
#include
+#include
+#include
+#include
#include
#include
#include
#include
+#include
#include
void lpc_enable_fixed_io_ranges(uint io_enables)
@@ -110,6 +114,19 @@ void lpc_io_setup_comm_a_b(void)
lpc_enable_fixed_io_ranges(com_enable);
}
+static int apl_acpi_lpc_get_name(const struct udevice *dev, char *out_name)
+{
+ return acpi_copy_name(out_name, "LPCB");
+}
+
+struct acpi_ops apl_lpc_acpi_ops = {
+ .get_name = apl_acpi_lpc_get_name,
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+ .write_tables = intel_southbridge_write_acpi_tables,
+#endif
+ .inject_dsdt= southbridge_inject_dsdt,
+};
+
static const struct udevice_id apl_lpc_ids[] = {
{ .compatible = "intel,apl-lpc" },
{ }
@@ -120,4 +137,5 @@ U_BOOT_DRIVER(apl_lpc_drv) = {
.name = "intel_apl_lpc",
.id = UCLASS_LPC,
.of_match = apl_lpc_ids,
+ ACPI_OPS_PTR(_lpc_acpi_ops)
};
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 34/54] x86: apl: Generate CPU tables
Add ACPI generation to the APL CPU driver.
Signed-off-by: Simon Glass
---
Changes in v1:
- Capitalise ACPI_OPS_PTR
- Handle table generation without callbacks
arch/x86/cpu/apollolake/cpu.c | 77 ++
arch/x86/lib/Makefile | 3 +-
configs/chromebook_coral_defconfig | 1 +
3 files changed, 80 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c
index 0a6d2ad7a4a..8da2e64e226 100644
--- a/arch/x86/cpu/apollolake/cpu.c
+++ b/arch/x86/cpu/apollolake/cpu.c
@@ -6,14 +6,90 @@
#include
#include
#include
+#include
+#include
+#include
#include
#include
+#include
+#include
+#include
+
+#define CSTATE_RES(address_space, width, offset, address) \
+ { \
+ .space_id = address_space, \
+ .bit_width = width, \
+ .bit_offset = offset, \
+ .addrl = address, \
+ }
+
+static struct acpi_cstate cstate_map[] = {
+ {
+ /* C1 */
+ .ctype = 1, /* ACPI C1 */
+ .latency = 1,
+ .power = 1000,
+ .resource = {
+ .space_id = ACPI_ADDRESS_SPACE_FIXED,
+ },
+ }, {
+ .ctype = 2, /* ACPI C2 */
+ .latency = 50,
+ .power = 10,
+ .resource = {
+ .space_id = ACPI_ADDRESS_SPACE_IO,
+ .bit_width = 8,
+ .addrl = 0x415,
+ },
+ }, {
+ .ctype = 3, /* ACPI C3 */
+ .latency = 150,
+ .power = 10,
+ .resource = {
+ .space_id = ACPI_ADDRESS_SPACE_IO,
+ .bit_width = 8,
+ .addrl = 0x419,
+ },
+ },
+};
static int apl_get_info(const struct udevice *dev, struct cpu_info *info)
{
return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
}
+static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ uint core_id = dev->req_seq;
+ int cores_per_package;
+ int ret;
+
+ cores_per_package = cpu_get_cores_per_package();
+ ret = acpi_generate_cpu_header(ctx, core_id, cstate_map,
+ ARRAY_SIZE(cstate_map));
+
+ /* Generate P-state tables */
+ generate_p_state_entries(ctx, core_id, cores_per_package);
+
+ /* Generate T-state tables */
+ generate_t_state_entries(ctx, core_id, cores_per_package, NULL, 0);
+
+ acpigen_pop_len(ctx);
+
+ if (device_is_last_sibling(dev)) {
+ ret = acpi_generate_cpu_package_final(ctx, cores_per_package);
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+struct acpi_ops apl_cpu_acpi_ops = {
+ .fill_ssdt = acpi_cpu_fill_ssdt,
+};
+
static const struct cpu_ops cpu_x86_apl_ops = {
.get_desc = cpu_x86_get_desc,
.get_info = apl_get_info,
@@ -32,5 +108,6 @@ U_BOOT_DRIVER(cpu_x86_apl_drv) = {
.of_match = cpu_x86_apl_ids,
.bind = cpu_x86_bind,
.ops= _x86_apl_ops,
+ ACPI_OPS_PTR(_cpu_acpi_ops)
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index f04d275dd9a..1bcbb49a61f 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -38,7 +38,8 @@ obj-y += sfi.o
obj-y += acpi.o
obj-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.o
ifndef CONFIG_QEMU
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o acpigen.o
+obj-y += acpigen.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
endif
obj-y += tables.o
ifndef CONFIG_SPL_BUILD
diff --git a/configs/chromebook_coral_defconfig
b/configs/chromebook_coral_defconfig
index f7680879467..2d2ba05aad8 100644
--- a/configs/chromebook_coral_defconfig
+++ b/configs/chromebook_coral_defconfig
@@ -72,6 +72,7 @@ CONFIG_EFI_PARTITION=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_INTEL_ACPIGEN=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 32/54] x86: apl: Generate required ACPI tables
Add support for generating various ACPI tables for Apollo Lake. Add a few
S3 definitions that are needed.
Signed-off-by: Simon Glass
---
Changes in v1:
- Drop unnecessary callbacks
arch/x86/cpu/apollolake/Makefile| 1 +
arch/x86/cpu/apollolake/acpi.c | 211
arch/x86/include/asm/arch-apollolake/acpi.h | 18 ++
include/acpi/acpi_s3.h | 4 +
4 files changed, 234 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/acpi.c
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 3aa2a556765..2ddf4af62c5 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -16,6 +16,7 @@ obj-y += fsp_m.o
endif
endif
ifndef CONFIG_SPL_BUILD
+obj-y += acpi.o
obj-y += fsp_s.o
endif
diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c
new file mode 100644
index 000..69b544f0d98
--- /dev/null
+++ b/arch/x86/cpu/apollolake/acpi.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2017-2019 Siemens AG
+ * (Written by Lance Zhao for Intel Corp.)
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot apollolake/acpi.c
+ */
+
+#define LOG_CATEGORY LOGC_ACPI
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+int arch_read_sci_irq_select(void)
+{
+ struct acpi_pmc_upriv *upriv;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_ACPI_PMC, );
+ if (ret)
+ return log_msg_ret("pmc", ret);
+ upriv = dev_get_uclass_priv(dev);
+
+ return readl(upriv->pmc_bar0 + IRQ_REG);
+}
+
+int arch_write_sci_irq_select(uint scis)
+{
+ struct acpi_pmc_upriv *upriv;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_ACPI_PMC, );
+ if (ret)
+ return log_msg_ret("pmc", ret);
+ upriv = dev_get_uclass_priv(dev);
+ writel(scis, upriv->pmc_bar0 + IRQ_REG);
+
+ return 0;
+}
+
+int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
+{
+ struct udevice *cpu;
+ int ret;
+
+ /* Clear out GNV */
+ memset(gnvs, '\0', sizeof(*gnvs));
+
+ /* TODO(s...@chromium.org): Add the console log to gnvs->cbmc */
+
+#ifdef CONFIG_CHROMEOS
+ /* Initialise Verified Boot data */
+ chromeos_init_acpi(>chromeos);
+ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+#endif
+ /* Set unknown wake source */
+ gnvs->pm1i = ~0ULL;
+
+ /* CPU core count */
+ gnvs->pcnt = 1;
+ ret = uclass_find_first_device(UCLASS_CPU, );
+ if (cpu) {
+ ret = cpu_get_count(cpu);
+ if (ret > 0)
+ gnvs->pcnt = ret;
+ }
+
+ return 0;
+}
+
+uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en)
+{
+ /*
+* WAK_STS bit is set when the system is in one of the sleep states
+* (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
+* this bit, the PMC will transition the system to the ON state and
+* can only be set by hardware and can only be cleared by writing a one
+* to this bit position.
+*/
+ generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
+
+ return generic_pm1_en;
+}
+
+int arch_madt_sci_irq_polarity(int sci)
+{
+ return MP_IRQ_POLARITY_LOW;
+}
+
+void fill_fadt(struct acpi_fadt *fadt)
+{
+ fadt->pm_tmr_blk = IOMAP_ACPI_BASE + PM1_TMR;
+
+ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+
+ fadt->pm_tmr_len = 4;
+ fadt->duty_width = 3;
+
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+ fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR;
+}
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt)
+{
+ struct acpi_table_header *header = >header;
+
+ acpi_fadt_common(fadt, facs, dsdt);
+ intel_acpi_fill_fadt(fadt);
+ fill_fadt(fadt);
+ header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+int apl_acpi_fill_dmar(struct acpi_ctx *ctx)
+{
+ struct udevice *dev, *sa_dev;
+ u64 gfxvtbar = readq(MCHBAR_REG(GFXVTBAR)) & VTBAR_MASK;
+ u64 defvtbar = readq(MCHBAR_REG(DEFVTBAR)) & VTBAR_MASK;
+ bool gfxvten = readl(MCHBAR_REG(GFXVTBAR)) & VTBAR_ENABLED;
+ bool defvten = readl(MCHBAR_REG(DEFVTBAR)) & VTBAR_ENABLED;
+ void *tmp;
+ int ret;
+
+
[PATCH v1 33/54] x86: apl: Add support for hostbridge ACPI generation
Support generating a DMAR table and add a few helper routines as well.
Also set up NHLT so that audio works.
Signed-off-by: Simon Glass
---
Changes in v1:
- Add support for NHLT table
- Capitalise ACPI_OPS_PTR
- Move the acpi.h header file to this commit
- Update commit message
arch/x86/cpu/apollolake/hostbridge.c | 221 +--
1 file changed, 212 insertions(+), 9 deletions(-)
diff --git a/arch/x86/cpu/apollolake/hostbridge.c
b/arch/x86/cpu/apollolake/hostbridge.c
index 056f7e57a9a..cf60fd8b021 100644
--- a/arch/x86/cpu/apollolake/hostbridge.c
+++ b/arch/x86/cpu/apollolake/hostbridge.c
@@ -1,17 +1,45 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Google LLC
+ * Copyright (C) 2015 - 2017 Intel Corp.
+ * Copyright (C) 2017 - 2019 Siemens AG
+ * (Written by Alexandru Gagniuc for Intel
Corp.)
+ * (Written by Andrey Petrov for Intel Corp.)
+ *
+ * Portions from coreboot soc/intel/apollolake/chip.c
*/
+#define LOG_CATEGORY UCLASS_NORTHBRIDGE
+
#include
#include
#include
#include
#include
+#include
+#include
+#include
#include
#include
+#include
#include
+#include
#include
+#include
+#include
+
+enum {
+ PCIEXBAR= 0x60,
+ PCIEXBAR_LENGTH_256MB = 0,
+ PCIEXBAR_LENGTH_128MB,
+ PCIEXBAR_LENGTH_64MB,
+
+ PCIEXBAR_PCIEXBAREN = 1 << 0,
+
+ BGSM= 0xb4, /* Base GTT Stolen Memory */
+ TSEG= 0xb8, /* TSEG base */
+ TOLUD = 0xbc,
+};
/**
* struct apl_hostbridge_platdata - platform data for hostbridge
@@ -32,17 +60,100 @@ struct apl_hostbridge_platdata {
pci_dev_t bdf;
};
-enum {
- PCIEXBAR= 0x60,
- PCIEXBAR_LENGTH_256MB = 0,
- PCIEXBAR_LENGTH_128MB,
- PCIEXBAR_LENGTH_64MB,
+static const struct nhlt_format_config dmic_1ch_formats[] = {
+ /* 48 KHz 16-bits per sample. */
+ {
+ .num_channels = 1,
+ .sample_freq_khz = 48,
+ .container_bits_per_sample = 16,
+ .valid_bits_per_sample = 16,
+ .settings_file = "dmic-1ch-48khz-16b.dat",
+ },
+};
- PCIEXBAR_PCIEXBAREN = 1 << 0,
+static const struct nhlt_dmic_array_config dmic_1ch_mic_config = {
+ .tdm_config = {
+ .config_type = NHLT_TDM_MIC_ARRAY,
+ },
+ .array_type = NHLT_MIC_ARRAY_VENDOR_DEFINED,
+};
- BGSM= 0xb4, /* Base GTT Stolen Memory */
- TSEG= 0xb8, /* TSEG base */
- TOLUD = 0xbc,
+static const struct nhlt_endp_descriptor dmic_1ch_descriptors[] = {
+ {
+ .link = NHLT_LINK_PDM,
+ .device = NHLT_PDM_DEV,
+ .direction = NHLT_DIR_CAPTURE,
+ .vid = NHLT_VID,
+ .did = NHLT_DID_DMIC,
+ .cfg = _1ch_mic_config,
+ .cfg_size = sizeof(dmic_1ch_mic_config),
+ .formats = dmic_1ch_formats,
+ .num_formats = ARRAY_SIZE(dmic_1ch_formats),
+ },
+};
+
+static const struct nhlt_format_config dmic_2ch_formats[] = {
+ /* 48 KHz 16-bits per sample. */
+ {
+ .num_channels = 2,
+ .sample_freq_khz = 48,
+ .container_bits_per_sample = 16,
+ .valid_bits_per_sample = 16,
+ .settings_file = "dmic-2ch-48khz-16b.dat",
+ },
+};
+
+static const struct nhlt_dmic_array_config dmic_2ch_mic_config = {
+ .tdm_config = {
+ .config_type = NHLT_TDM_MIC_ARRAY,
+ },
+ .array_type = NHLT_MIC_ARRAY_2CH_SMALL,
+};
+
+static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = {
+ {
+ .link = NHLT_LINK_PDM,
+ .device = NHLT_PDM_DEV,
+ .direction = NHLT_DIR_CAPTURE,
+ .vid = NHLT_VID,
+ .did = NHLT_DID_DMIC,
+ .cfg = _2ch_mic_config,
+ .cfg_size = sizeof(dmic_2ch_mic_config),
+ .formats = dmic_2ch_formats,
+ .num_formats = ARRAY_SIZE(dmic_2ch_formats),
+ },
+};
+
+static const struct nhlt_format_config dmic_4ch_formats[] = {
+ /* 48 KHz 16-bits per sample. */
+ {
+ .num_channels = 4,
+ .sample_freq_khz = 48,
+ .container_bits_per_sample = 16,
+ .valid_bits_per_sample = 16,
+ .settings_file = "dmic-4ch-48khz-16b.dat",
+ },
+};
+
+static const struct nhlt_dmic_array_config dmic_4ch_mic_config = {
+ .tdm_config = {
+ .config_type = NHLT_TDM_MIC_ARRAY,
+ },
+ .array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED,
+};
+
+static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = {
+ {
+ .link = NHLT_LINK_PDM,
+ .device = NHLT_PDM_DEV,
+ .direction = NHLT_DIR_CAPTURE,
+ .vid = NHLT_VID,
+
[PATCH v1 23/54] x86: acpi: Support generation of the DBG2 table
Add an implementation of the DBG2 (Debug Port Table 2) ACPI table.
Adjust one of the header includes to be in the correct order, before
adding more.
Note that the DBG2 table is generic but the PCI UART is x86-specific at
present since it assumes an ns16550 UART. It can be generalised later
if necessary.
Signed-off-by: Simon Glass
---
Changes in v1:
- Move ASL_REVISION define into this patch
- Move acpi_create_dbg2() into generic code
- Update commit message
arch/x86/include/asm/acpi_table.h | 11 ++
arch/x86/lib/acpi_table.c | 41
include/acpi/acpi_table.h | 40 +++
lib/acpi/acpi_table.c | 64 +++
4 files changed, 156 insertions(+)
diff --git a/arch/x86/include/asm/acpi_table.h
b/arch/x86/include/asm/acpi_table.h
index 7047ee6c772..1b7ff509516 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -46,6 +46,17 @@ u32 acpi_fill_csrt(u32 current);
*/
int acpi_write_hpet(struct acpi_ctx *ctx);
+/**
+ * acpi_write_dbg2_pci_uart() - Write out a DBG2 table
+ *
+ * @ctx: Current ACPI context
+ * @dev: Debug UART device to describe
+ * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS)
+ * @return 0 if OK, -ve on error
+ */
+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
+uint access_size);
+
/**
* acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table
*
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index e1900ffe42f..28a27103342 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -575,3 +576,43 @@ int acpi_write_hpet(struct acpi_ctx *ctx)
return 0;
}
+
+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
+uint access_size)
+{
+ struct acpi_dbg2_header *dbg2 = ctx->current;
+ char path[ACPI_PATH_MAX];
+ struct acpi_gen_regaddr address;
+ phys_addr_t addr;
+ int ret;
+
+ if (!device_active(dev)) {
+ log_info("Device not enabled\n");
+ return -EACCES;
+ }
+ /*
+* PCI devices don't remember their resource allocation information in
+* U-Boot at present. We assume that MMIO is used for the UART and that
+* the address space is 32 bytes: ns16550 uses 8 registers of up to
+* 32-bits each. This is only for debugging so it is not a big deal.
+*/
+ addr = dm_pci_read_bar32(dev, 0);
+ printf("UART addr %lx\n", (ulong)addr);
+
+ memset(, '\0', sizeof(address));
+ address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
+ address.addrl = (uint32_t)addr;
+ address.addrh = (uint32_t)((addr >> 32) & 0x);
+ address.access_size = access_size;
+
+ ret = acpi_device_path(dev, path, sizeof(path));
+ if (ret)
+ return log_msg_ret("path", ret);
+ acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
+ACPI_DBG2_16550_COMPATIBLE, , 0x1000, path);
+
+ acpi_inc_align(ctx, dbg2->header.length);
+ acpi_add_table(ctx, dbg2);
+
+ return 0;
+}
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index f8140446a59..c826a797f5b 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -448,6 +448,29 @@ struct __packed acpi_dmar {
#define ACPI_DBG2_UNKNOWN 0x00FF
+/* DBG2: Microsoft Debug Port Table 2 header */
+struct __packed acpi_dbg2_header {
+ struct acpi_table_header header;
+ u32 devices_offset;
+ u32 devices_count;
+};
+
+/* DBG2: Microsoft Debug Port Table 2 device entry */
+struct __packed acpi_dbg2_device {
+ u8 revision;
+ u16 length;
+ u8 address_count;
+ u16 namespace_string_length;
+ u16 namespace_string_offset;
+ u16 oem_data_length;
+ u16 oem_data_offset;
+ u16 port_type;
+ u16 port_subtype;
+ u8 reserved[2];
+ u16 base_address_offset;
+ u16 address_size_offset;
+};
+
/* SPCR (Serial Port Console Redirection table) */
struct __packed acpi_spcr {
struct acpi_table_header header;
@@ -522,6 +545,23 @@ int acpi_get_table_revision(enum acpi_tables table);
*/
int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags);
+/**
+ * acpi_create_dbg2() - Create a DBG2 table
+ *
+ * This table describes how to access the debug UART
+ *
+ * @dbg2: Place to put information
+ * @port_type: Serial port type (see ACPI_DBG2_...)
+ * @port_subtype: Serial port sub-type (see ACPI_DBG2_...)
+ * @address: ACPI address of port
+ * @address_size: Size of address space
+ * @device_path: Path of device (created using acpi_device_path())
+ */
+void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,
+ int port_type, int port_subtype,
+
[PATCH v1 30/54] x86: apl: Allow reading hostbridge base addresses
Add a few functions to permit reading of various useful base addresses
provided by the hostbridge.
Signed-off-by: Simon Glass
---
Changes in v1:
- Add comments
arch/x86/cpu/apollolake/hostbridge.c | 27
.../include/asm/arch-apollolake/systemagent.h | 31 +++
2 files changed, 58 insertions(+)
diff --git a/arch/x86/cpu/apollolake/hostbridge.c
b/arch/x86/cpu/apollolake/hostbridge.c
index cb46ec6c0bb..056f7e57a9a 100644
--- a/arch/x86/cpu/apollolake/hostbridge.c
+++ b/arch/x86/cpu/apollolake/hostbridge.c
@@ -40,7 +40,9 @@ enum {
PCIEXBAR_PCIEXBAREN = 1 << 0,
+ BGSM= 0xb4, /* Base GTT Stolen Memory */
TSEG= 0xb8, /* TSEG base */
+ TOLUD = 0xbc,
};
static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
@@ -165,6 +167,31 @@ static int apl_hostbridge_probe(struct udevice *dev)
return 0;
}
+static ulong sa_read_reg(struct udevice *dev, int reg)
+{
+ u32 val;
+
+ /* All regions concerned for have 1 MiB alignment */
+ dm_pci_read_config32(dev, BGSM, );
+
+ return ALIGN_DOWN(val, 1 << 20);
+}
+
+ulong sa_get_tolud_base(struct udevice *dev)
+{
+ return sa_read_reg(dev, TOLUD);
+}
+
+ulong sa_get_gsm_base(struct udevice *dev)
+{
+ return sa_read_reg(dev, BGSM);
+}
+
+ulong sa_get_tseg_base(struct udevice *dev)
+{
+ return sa_read_reg(dev, TSEG);
+}
+
static const struct udevice_id apl_hostbridge_ids[] = {
{ .compatible = "intel,apl-hostbridge" },
{ }
diff --git a/arch/x86/include/asm/arch-apollolake/systemagent.h
b/arch/x86/include/asm/arch-apollolake/systemagent.h
index 9e7bd62751a..788a63d7999 100644
--- a/arch/x86/include/asm/arch-apollolake/systemagent.h
+++ b/arch/x86/include/asm/arch-apollolake/systemagent.h
@@ -35,4 +35,35 @@
*/
void enable_bios_reset_cpl(void);
+/**
+ * sa_get_tolud_base() - Get the TOLUD base address
+ *
+ * This returns the Top Of Low Useable DRAM, marking the top of usable DRAM
+ * below 4GB
+ *
+ * @dev: hostbridge device
+ * @return TOLUD address
+ */
+ulong sa_get_tolud_base(struct udevice *dev);
+
+/**
+ * sa_get_gsm_base() - Get the GSM base address
+ *
+ * This returns the base of GTT Stolen Memory, marking the start of memory used
+ * for Graphics Translation Tables.
+ *
+ * @dev: hostbridge device
+ * @return GSM address
+ */
+ulong sa_get_gsm_base(struct udevice *dev);
+
+/**
+ * sa_get_tseg_base() - Get the TSEG base address
+ *
+ * This returns the top address of DRAM available below 4GB
+ *
+ * @return TSEG base
+ */
+ulong sa_get_tseg_base(struct udevice *dev);
+
#endif
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 26/54] acpi: Add more support for generating processor tables
This adds tables relating to P-States and C-States.
Signed-off-by: Simon Glass
---
include/acpi/acpigen.h | 162 +++
lib/acpi/acpigen.c | 167 +++
test/dm/acpigen.c | 294 +
3 files changed, 623 insertions(+)
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 3a2c6339d5e..976f4dbb9af 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -10,8 +10,10 @@
#ifndef __ACPI_ACPIGEN_H
#define __ACPI_ACPIGEN_H
+#include
#include
+struct acpi_cstate;
struct acpi_ctx;
struct acpi_gen_regaddr;
struct acpi_gpio;
@@ -87,6 +89,53 @@ enum psd_coord {
HW_ALL = 0xfe
};
+/**
+ * enum csd_coord - Coordination types for C-states
+ *
+ * The type of coordination that exists (hardware) or is required (software) as
+ * a result of the underlying hardware dependency
+ */
+enum csd_coord {
+ CSD_HW_ALL = 0xfe,
+};
+
+/**
+ * struct acpi_cstate - Information about a C-State
+ *
+ * @ctype: C State type (1=C1, 2=C2, 3=C3)
+ * @latency: Worst-case latency to enter and exit the C State (in uS)
+ * @power: Average power consumption of the processor when in this C-State (mW)
+ * @resource: Register to read to place the processor in this state
+ */
+struct acpi_cstate {
+ uint ctype;
+ uint latency;
+ uint power;
+ struct acpi_gen_regaddr resource;
+};
+
+/**
+ * struct acpi_tstate - Information about a Throttling Supported State
+ *
+ * See ACPI v6.3 section 8.4.5.2: _TSS (Throttling Supported States)
+ *
+ * @percent: Percent of the core CPU operating frequency that will be
+ * available when this throttling state is invoked
+ * @power: Throttling state’s maximum power dissipation (mw)
+ * @latency: Worst-case latency (uS) that the CPU is unavailable during a
+ * transition from any throttling state to this throttling state
+ * @control: Value to be written to the Processor Control Register
+ * (THROTTLE_CTRL) to initiate a transition to this throttling state
+ * @status: Value in THROTTLE_STATUS when in this state
+ */
+struct acpi_tstate {
+ uint percent;
+ uint power;
+ uint latency;
+ uint control;
+ uint status;
+};
+
/**
* acpigen_get_current() - Get the current ACPI code output pointer
*
@@ -816,4 +865,117 @@ void acpigen_write_processor_package(struct acpi_ctx
*ctx, const char *name,
*/
void acpigen_write_processor_cnot(struct acpi_ctx *ctx, const uint num_cores);
+/**
+ * acpigen_write_ppc() - generates a function returning max P-states
+ *
+ * @ctx: ACPI context pointer
+ * @num_pstates: Number of pstates to return
+ */
+void acpigen_write_ppc(struct acpi_ctx *ctx, uint num_pstates);
+
+/**
+ * acpigen_write_ppc() - generates a function returning PPCM
+ *
+ * This returns the maximum number of supported P-states, as saved in the
+ * variable PPCM
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_ppc_nvs(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_tpc() - Write a _TPC method that returns the TPC limit
+ *
+ * @ctx: ACPI context pointer
+ * @gnvs_tpc_limit: Variable that holds the TPC limit
+ */
+void acpigen_write_tpc(struct acpi_ctx *ctx, const char *gnvs_tpc_limit);
+
+/**
+ * acpigen_write_pss_package() - Write a PSS package
+ *
+ * See ACPI v6.3 section 8.4.6: Processor Performance Control
+ *
+ * @ctx: ACPI context pointer
+ * @corefreq: CPU core frequency in MHz
+ * @translat: worst-case latency in uS that the CPU is unavailable during a
+ * transition from any performance state to this performance state
+ * @busmlat: worst-case latency in microseconds that Bus Masters are prevented
+ * from accessing memory during a transition from any performance state to
+ * this performance state
+ * @control: Value to write to PERF_CTRL to move to this performance state
+ * @status: Expected PERF_STATUS value when in this state
+ */
+void acpigen_write_pss_package(struct acpi_ctx *ctx, uint corefreq, uint power,
+ uint translat, uint busmlat, uint control,
+ uint status);
+
+/**
+ * acpigen_write_psd_package() - Write a PSD package
+ *
+ * Writes a P-State dependency package
+ *
+ * See ACPI v6.3 section 8.4.6.5: _PSD (P-State Dependency)
+ *
+ * @ctx: ACPI context pointer
+ * @domain: Dependency domain number to which this P state entry belongs
+ * @numprocs: Number of processors belonging to the domain for this logical
+ * processor’s P-states
+ * @coordtype: Coordination type
+ */
+void acpigen_write_psd_package(struct acpi_ctx *ctx, uint domain, uint
numprocs,
+ enum psd_coord coordtype);
+
+/**
+ * acpigen_write_cst_package() - Write a _CST package
+ *
+ * See ACPI v6.3 section 8.4.2.1: _CST (C States)
+ *
+ * @ctx: ACPI context pointer
+ * @entry: Array of entries
+ * @nentries; Number of entries
+ */
+void acpigen_write_cst_package(struct acpi_ctx *ctx,
+
[PATCH v1 31/54] p2sb: Add some definitions used for ACPI
Allow this header to be included in ASL files by adding a header guard and a few definitions that are needed. Signed-off-by: Simon Glass --- include/p2sb.h | 8 1 file changed, 8 insertions(+) diff --git a/include/p2sb.h b/include/p2sb.h index 93e1155dca6..a25170e3d11 100644 --- a/include/p2sb.h +++ b/include/p2sb.h @@ -10,6 +10,12 @@ /* Port Id lives in bits 23:16 and register offset lives in 15:0 of address */ #define PCR_PORTID_SHIFT 16 +#if !defined(__ACPI__) + +/* These registers contain IOAPIC and HPET devfn */ +#define PCH_P2SB_IBDF 0x6c +#define PCH_P2SB_HBDF 0x70 + /** * struct p2sb_child_platdata - Information about each child of a p2sb device * @@ -164,4 +170,6 @@ int p2sb_get_port_id(struct udevice *dev); */ void *pcr_reg_address(struct udevice *dev, uint offset); +#endif /* !__ACPI__ */ + #endif -- 2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 24/54] acpi: Add support for generating processor tables
ACPI has a number of CPU-related tables. Add utility functions to write
out the basic packages.
Signed-off-by: Simon Glass
---
include/acpi/acpigen.h | 39 +++
lib/acpi/acpigen.c | 55 +
test/dm/acpigen.c | 106 +
3 files changed, 200 insertions(+)
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index c412898169e..3a2c6339d5e 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -64,7 +64,9 @@ enum {
OR_OP = 0x7d,
NOT_OP = 0x80,
DEVICE_OP = 0x82,
+ PROCESSOR_OP= 0x83,
POWER_RES_OP= 0x84,
+ NOTIFY_OP = 0x86,
LEQUAL_OP = 0x93,
TO_BUFFER_OP= 0x96,
TO_INTEGER_OP = 0x99,
@@ -777,4 +779,41 @@ void acpigen_write_dsm_uuid_end(struct acpi_ctx *ctx);
*/
void acpigen_write_dsm_end(struct acpi_ctx *ctx);
+/**
+ * acpigen_write_processor() - Write a Processor package
+ *
+ * This emits a Processor package header with the required information. The
+ * caller must complete the information and call acpigen_pop_len() at the end
+ *
+ * @ctx: ACPI context pointer
+ * @cpuindex: CPU number
+ * @pblock_addr: PBlk system IO address
+ * @pblock_len: PBlk length
+ */
+void acpigen_write_processor(struct acpi_ctx *ctx, uint cpuindex,
+u32 pblock_addr, uint pblock_len);
+
+/**
+ * acpigen_write_processor_package() - Write a package containing the
processors
+ *
+ * The package containins the name of each processor in the SoC
+ *
+ * @ctx: ACPI context pointer
+ * @name: Package name (.e.g "PPKG")
+ * @first_core: Number of the first core (e.g. 0)
+ * @core_count: Number of cores (e.g. 4)
+ */
+void acpigen_write_processor_package(struct acpi_ctx *ctx, const char *name,
+uint first_core, uint core_count);
+
+/**
+ * acpigen_write_processor_cnot() - Write a processor notification method
+ *
+ * This writes a method that notifies all CPU cores
+ *
+ * @ctx: ACPI context pointer
+ * @num_cores: Number of CPU cores
+ */
+void acpigen_write_processor_cnot(struct acpi_ctx *ctx, const uint num_cores);
+
#endif
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index d859f378413..b9985075cde 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -17,6 +17,9 @@
#include
#include
+/* CPU path format */
+#define ACPI_CPU_STRING "\\_PR.CP%02d"
+
u8 *acpigen_get_current(struct acpi_ctx *ctx)
{
return ctx->current;
@@ -340,6 +343,58 @@ void acpigen_write_method_serialized(struct acpi_ctx *ctx,
const char *name,
ACPI_METHOD_SERIALIZED_MASK);
}
+void acpigen_write_processor(struct acpi_ctx *ctx, uint cpuindex,
+u32 pblock_addr, uint pblock_len)
+{
+ /*
+* Processor (\_PR.CPnn, cpuindex, pblock_addr, pblock_len)
+* {
+*/
+ char pscope[16];
+
+ acpigen_emit_ext_op(ctx, PROCESSOR_OP);
+ acpigen_write_len_f(ctx);
+
+ snprintf(pscope, sizeof(pscope), ACPI_CPU_STRING, cpuindex);
+ acpigen_emit_namestring(ctx, pscope);
+ acpigen_emit_byte(ctx, cpuindex);
+ acpigen_emit_dword(ctx, pblock_addr);
+ acpigen_emit_byte(ctx, pblock_len);
+}
+
+void acpigen_write_processor_package(struct acpi_ctx *ctx,
+const char *const name,
+const uint first_core,
+const uint core_count)
+{
+ uint i;
+ char pscope[16];
+
+ acpigen_write_name(ctx, name);
+ acpigen_write_package(ctx, core_count);
+ for (i = first_core; i < first_core + core_count; ++i) {
+ snprintf(pscope, sizeof(pscope), ACPI_CPU_STRING, i);
+ acpigen_emit_namestring(ctx, pscope);
+ }
+ acpigen_pop_len(ctx);
+}
+
+void acpigen_write_processor_cnot(struct acpi_ctx *ctx, const uint num_cores)
+{
+ int core_id;
+
+ acpigen_write_method(ctx, "\\_PR.CNOT", 1);
+ for (core_id = 0; core_id < num_cores; core_id++) {
+ char buffer[30];
+
+ snprintf(buffer, sizeof(buffer), ACPI_CPU_STRING, core_id);
+ acpigen_emit_byte(ctx, NOTIFY_OP);
+ acpigen_emit_namestring(ctx, buffer);
+ acpigen_emit_byte(ctx, ARG0_OP);
+ }
+ acpigen_pop_len(ctx);
+}
+
void acpigen_write_device(struct acpi_ctx *ctx, const char *name)
{
acpigen_emit_ext_op(ctx, DEVICE_OP);
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index da0071d4a9a..4206f5ae3cf 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -1344,3 +1344,109 @@ static int dm_test_acpi_write_i2c_dsm(struct
unit_test_state *uts)
}
DM_TEST(dm_test_acpi_write_i2c_dsm, 0);
+/* Test emitting a processor */
+static int dm_test_acpi_write_processor(struct
[PATCH v1 28/54] x86: Support Atom SoCs using SWSMISCI rather than the SWSCI
Some Atom SoCs use SWSMISCI for SMI control. Add a Kconfig to select this. It is used on Apollo Lake. Signed-off-by: Simon Glass --- arch/x86/Kconfig| 6 ++ arch/x86/cpu/apollolake/Kconfig | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 7062384780b..de68bf9fe14 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1005,4 +1005,10 @@ config INTEL_GENERIC_WIFI network functionality. It is only here to generate the ACPI tables required by Linux. +config INTEL_GMA_SWSMISCI + bool + help + Select this option for Atom-based platforms which use the SWSMISCI + register (0xe0) rather than the SWSCI register (0xe8). + endmenu diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index 319f12684b7..35a425cd1bc 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -17,6 +17,7 @@ config INTEL_APOLLOLAKE select PCH_SUPPORT select P2SB select SMP_AP_WORK + select INTEL_GMA_SWSMISCI select ACPI_GNVS_EXTERNAL imply ENABLE_MRC_CACHE imply AHCI_PCI -- 2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 25/54] x86: acpi: Add PCT and PTC tables
These are needed for the CPU tables. Add them into an x86-specific file
since we do not support them on sandbox, or include tests.
Signed-off-by: Simon Glass
---
Changes in v1:
- Split PCT and PTC tables into a separate patch
arch/x86/include/asm/acpigen.h | 35 +
arch/x86/lib/Makefile | 2 +-
arch/x86/lib/acpigen.c | 96 ++
3 files changed, 132 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/include/asm/acpigen.h
create mode 100644 arch/x86/lib/acpigen.c
diff --git a/arch/x86/include/asm/acpigen.h b/arch/x86/include/asm/acpigen.h
new file mode 100644
index 000..c531dd61d53
--- /dev/null
+++ b/arch/x86/include/asm/acpigen.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Generation of x86-specific ACPI tables
+ *
+ * Copyright 2020 Google LLC
+ */
+
+#ifndef __ASM_ACPIGEN_H__
+#define __ASM_ACPIGEN_H__
+
+struct acpi_ctx;
+
+/**
+ * acpigen_write_empty_pct() - Write an empty PCT
+ *
+ * See ACPI v6.3 section 8.4.6.1: _PCT (Performance Control)
+ *
+ * This writes an empty table so that CPU performance works as expected
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_empty_pct(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_empty_ptc() - Write an empty PTC
+ *
+ * See ACPI v6.3 section 8.4.5.1: _PTC (Processor Throttling Control)
+ *
+ * This writes an empty table so that CPU performance works as expected
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_empty_ptc(struct acpi_ctx *ctx);
+
+#endif /* __ASM_ACPI_H__ */
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 1185a88c27c..f04d275dd9a 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -38,7 +38,7 @@ obj-y += sfi.o
obj-y += acpi.o
obj-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.o
ifndef CONFIG_QEMU
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o acpigen.o
endif
obj-y += tables.o
ifndef CONFIG_SPL_BUILD
diff --git a/arch/x86/lib/acpigen.c b/arch/x86/lib/acpigen.c
new file mode 100644
index 000..ea2ec2a9083
--- /dev/null
+++ b/arch/x86/lib/acpigen.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+
+void acpigen_write_empty_pct(struct acpi_ctx *ctx)
+{
+ /*
+* Name (_PCT, Package (0x02)
+* {
+* ResourceTemplate ()
+* {
+* Register (FFixedHW,
+* 0x00, // Bit Width
+* 0x00, // Bit Offset
+* 0x, // Address
+* ,)
+* },
+*
+* ResourceTemplate ()
+* {
+* Register (FFixedHW,
+* 0x00, // Bit Width
+* 0x00, // Bit Offset
+* 0x, // Address
+* ,)
+* }
+* })
+*/
+ static char stream[] = {
+ /* 0030"0._PCT.," */
+ 0x08, 0x5f, 0x50, 0x43, 0x54, 0x12, 0x2c,
+ /* 0038"" */
+ 0x02, 0x11, 0x14, 0x0a, 0x11, 0x82, 0x0c, 0x00,
+ /* 0040"" */
+ 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0048"y..." */
+ 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14,
+ /* 0050"" */
+ 0x0a, 0x11, 0x82, 0x0c, 0x00, 0x7f, 0x00, 0x00,
+ /* 0058"" */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x79, 0x00
+ };
+ acpigen_emit_stream(ctx, stream, ARRAY_SIZE(stream));
+}
+
+void acpigen_write_empty_ptc(struct acpi_ctx *ctx)
+{
+ /*
+* Name (_PTC, Package (0x02)
+* {
+* ResourceTemplate ()
+* {
+* Register (FFixedHW,
+* 0x00, // Bit Width
+* 0x00, // Bit Offset
+* 0x, // Address
+* ,)
+* },
+*
+* ResourceTemplate ()
+* {
+* Register (FFixedHW,
+* 0x00, // Bit Width
+* 0x00, // Bit Offset
+* 0x, // Address
+* ,)
+* }
+* })
+*/
+ struct acpi_gen_regaddr addr = {
+ .space_id= ACPI_ADDRESS_SPACE_FIXED,
+ .bit_width = 0,
+ .bit_offset = 0,
+ .access_size = 0,
+
[PATCH v1 21/54] x86: Add a few common Intel CPU functions
Add functions to query CPU information, needed for ACPI.
Signed-off-by: Simon Glass
---
Changes in v1:
- Add more comments and rename cpu_get_bus_clock to cpu_get_bus_clock_khz()
arch/x86/cpu/intel_common/cpu.c | 64 +++
arch/x86/include/asm/cpu_common.h | 49 +++
include/acpi/acpigen.h| 12 ++
3 files changed, 125 insertions(+)
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index 509730aea96..cb4ef84013a 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -227,3 +228,66 @@ void cpu_set_eist(bool eist_status)
msr.lo &= ~MISC_ENABLE_ENHANCED_SPEEDSTEP;
msr_write(MSR_IA32_MISC_ENABLE, msr);
}
+
+int cpu_get_coord_type(void)
+{
+ return HW_ALL;
+}
+
+int cpu_get_min_ratio(void)
+{
+ msr_t msr;
+
+ /* Get bus ratio limits and calculate clock speeds */
+ msr = msr_read(MSR_PLATFORM_INFO);
+
+ return (msr.hi >> 8) & 0xff;/* Max Efficiency Ratio */
+}
+
+int cpu_get_max_ratio(void)
+{
+ u32 ratio_max;
+ msr_t msr;
+
+ if (cpu_config_tdp_levels()) {
+ /* Set max ratio to nominal TDP ratio */
+ msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+ ratio_max = msr.lo & 0xff;
+ } else {
+ msr = msr_read(MSR_PLATFORM_INFO);
+ /* Max Non-Turbo Ratio */
+ ratio_max = (msr.lo >> 8) & 0xff;
+ }
+
+ return ratio_max;
+}
+
+int cpu_get_bus_clock_khz(void)
+{
+ /*
+* CPU bus clock is set by default here to 100MHz. This function returns
+* the bus clock in KHz.
+*/
+ return INTEL_BCLK_MHZ * 1000;
+}
+
+int cpu_get_power_max(void)
+{
+ int power_unit;
+ msr_t msr;
+
+ msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
+ power_unit = 2 << ((msr.lo & 0xf) - 1);
+ msr = msr_read(MSR_PKG_POWER_SKU);
+
+ return (msr.lo & 0x7fff) * 1000 / power_unit;
+}
+
+int cpu_get_max_turbo_ratio(void)
+{
+ msr_t msr;
+
+ msr = msr_read(MSR_TURBO_RATIO_LIMIT);
+
+ return msr.lo & 0xff;
+}
diff --git a/arch/x86/include/asm/cpu_common.h
b/arch/x86/include/asm/cpu_common.h
index cdd99a90b76..a7b7112d417 100644
--- a/arch/x86/include/asm/cpu_common.h
+++ b/arch/x86/include/asm/cpu_common.h
@@ -128,4 +128,53 @@ void cpu_set_eist(bool eist_status);
*/
void cpu_set_p_state_to_turbo_ratio(void);
+/**
+ * cpu_get_coord_type() - Get the type of coordination for P-State transition
+ *
+ * See ACPI spec v6.3 section 8.4.6.5 _PSD (P-State Dependency)
+ *
+ * @return HW_ALL (always)
+ */
+int cpu_get_coord_type(void);
+
+/**
+ * cpu_get_min_ratio() - get minimum support frequency ratio for CPU
+ *
+ * @return minimum ratio
+ */
+int cpu_get_min_ratio(void);
+
+/**
+ * cpu_get_max_ratio() - get nominal TDP ration or max non-turbo ratio
+ *
+ * If a nominal TDP ratio is available, it is returned. Otherwise this returns
+ * the maximum non-turbo frequency ratio for this processor
+ *
+ * @return max ratio
+ */
+int cpu_get_max_ratio(void);
+
+/**
+ * cpu_get_bus_clock_khz() - Get the bus clock frequency in KHz
+ *
+ * This is the value the clock ratio is multiplied with
+ *
+ * @return bus-block frequency in KHz
+ */
+int cpu_get_bus_clock_khz(void);
+
+/**
+ * cpu_get_power_max() - Get maximum CPU TDP
+ *
+ * @return maximum CPU TDP (Thermal-design power) in mW
+ */
+int cpu_get_power_max(void);
+
+/**
+ * cpu_get_max_turbo_ratio() - Get maximum turbo ratio
+ *
+ * @return maximum ratio
+ */
+int cpu_get_max_turbo_ratio(void);
+
#endif
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 34b3115bc9c..c412898169e 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -73,6 +73,18 @@ enum {
RETURN_OP = 0xa4,
};
+/**
+ * enum psd_coord - Coordination types for P-states
+ *
+ * The type of coordination that exists (hardware) or is required (software) as
+ * a result of the underlying hardware dependency
+ */
+enum psd_coord {
+ SW_ALL = 0xfc,
+ SW_ANY = 0xfd,
+ HW_ALL = 0xfe
+};
+
/**
* acpigen_get_current() - Get the current ACPI code output pointer
*
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 22/54] x86: acpi: Support generation of the HPET table
Add an implementation of the HPET (High Precision Event Timer) ACPI
table. Since this is x86-specific, put it in an x86-specific file
Signed-off-by: Simon Glass
---
Changes in v1:
- Put this code in an x86-specific place and update commit message
arch/x86/include/asm/acpi_table.h | 10 ++
arch/x86/lib/acpi_table.c | 59 +++
include/acpi/acpi_table.h | 31 +++-
3 files changed, 91 insertions(+), 9 deletions(-)
diff --git a/arch/x86/include/asm/acpi_table.h
b/arch/x86/include/asm/acpi_table.h
index 733085c1785..7047ee6c772 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -36,6 +36,16 @@ int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig
*mmconfig, u32 base,
u32 acpi_fill_mcfg(u32 current);
u32 acpi_fill_csrt(u32 current);
+/**
+ * acpi_write_hpet() - Write out a HPET table
+ *
+ * Write out the table for High-Precision Event Timers
+ *
+ * @ctx: Current ACPI context
+ * @return 0 if OK, -ve on error
+ */
+int acpi_write_hpet(struct acpi_ctx *ctx);
+
/**
* acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table
*
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 942b2334eab..e1900ffe42f 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -516,3 +516,62 @@ ulong acpi_get_rsdp_addr(void)
{
return acpi_rsdp_addr;
}
+
+/**
+ * acpi_write_hpet() - Write out a HPET table
+ *
+ * Write out the table for High-Precision Event Timers
+ *
+ * @hpet: Place to put HPET table
+ */
+static int acpi_create_hpet(struct acpi_hpet *hpet)
+{
+ struct acpi_table_header *header = >header;
+ struct acpi_gen_regaddr *addr = >addr;
+
+ /*
+* See IA-PC HPET (High Precision Event Timers) Specification v1.0a
+*
https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/software-developers-hpet-spec-1-0a.pdf
+*/
+ memset((void *)hpet, '\0', sizeof(struct acpi_hpet));
+
+ /* Fill out header fields. */
+ acpi_fill_header(header, "HPET");
+
+ header->aslc_revision = ASL_REVISION;
+ header->length = sizeof(struct acpi_hpet);
+ header->revision = acpi_get_table_revision(ACPITAB_HPET);
+
+ /* Fill out HPET address */
+ addr->space_id = 0; /* Memory */
+ addr->bit_width = 64;
+ addr->bit_offset = 0;
+ addr->addrl = CONFIG_HPET_ADDRESS & 0x;
+ addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32;
+
+ hpet->id = *(u32 *)CONFIG_HPET_ADDRESS;
+ hpet->number = 0;
+ hpet->min_tick = 0; /* HPET_MIN_TICKS */
+
+ header->checksum = table_compute_checksum(hpet,
+ sizeof(struct acpi_hpet));
+
+ return 0;
+}
+
+int acpi_write_hpet(struct acpi_ctx *ctx)
+{
+ struct acpi_hpet *hpet;
+ int ret;
+
+ log_debug("ACPI:* HPET\n");
+
+ hpet = ctx->current;
+ acpi_inc_align(ctx, sizeof(struct acpi_hpet));
+ acpi_create_hpet(hpet);
+ ret = acpi_add_table(ctx, hpet);
+ if (ret)
+ return log_msg_ret("add", ret);
+
+ return 0;
+}
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index fe9b29f3f82..f8140446a59 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -20,6 +20,9 @@
#define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */
#define ASLC_ID"INTL" /* Intel ASL Compiler */
+/* TODO(s...@chromium.org): Figure out how to get compiler revision */
+#define ASL_REVISION 0
+
#define ACPI_RSDP_REV_ACPI_1_0 0
#define ACPI_RSDP_REV_ACPI_2_0 2
@@ -56,6 +59,15 @@ struct __packed acpi_table_header {
u32 aslc_revision; /* ASL compiler revision number */
};
+struct acpi_gen_regaddr {
+ u8 space_id;/* Address space ID */
+ u8 bit_width; /* Register size in bits */
+ u8 bit_offset; /* Register bit offset */
+ u8 access_size; /* Access size */
+ u32 addrl; /* Register address, low 32 bits */
+ u32 addrh; /* Register address, high 32 bits */
+};
+
/* A maximum number of 32 ACPI tables ought to be enough for now */
#define MAX_ACPI_TABLES32
@@ -71,6 +83,16 @@ struct acpi_xsdt {
u64 entry[MAX_ACPI_TABLES];
};
+/* HPET timers */
+struct __packed acpi_hpet {
+ struct acpi_table_header header;
+ u32 id;
+ struct acpi_gen_regaddr addr;
+ u8 number;
+ u16 min_tick;
+ u8 attributes;
+};
+
/* FADT Preferred Power Management Profile */
enum acpi_pm_profile {
ACPI_PM_UNSPECIFIED = 0,
@@ -138,15 +160,6 @@ enum acpi_address_space_size {
ACPI_ACCESS_SIZE_QWORD_ACCESS
};
-struct acpi_gen_regaddr {
- u8 space_id;/* Address space ID */
- u8 bit_width; /* Register size in bits */
- u8 bit_offset; /* Register bit offset */
- u8
[PATCH v1 27/54] x86: acpi: Add common Intel ACPI tables
Add various tables that are common to Intel CPUs. These functions can be
used by arch-specific CPU code.
Signed-off-by: Simon Glass
---
arch/x86/cpu/intel_common/Makefile | 2 +
arch/x86/cpu/intel_common/acpi.c | 377 +
arch/x86/cpu/intel_common/cpu.c| 14 ++
arch/x86/include/asm/acpi_table.h | 22 ++
arch/x86/include/asm/cpu_common.h | 7 +
arch/x86/include/asm/intel_acpi.h | 52
drivers/core/Kconfig | 9 +
7 files changed, 483 insertions(+)
create mode 100644 arch/x86/cpu/intel_common/acpi.c
create mode 100644 arch/x86/include/asm/intel_acpi.h
diff --git a/arch/x86/cpu/intel_common/Makefile
b/arch/x86/cpu/intel_common/Makefile
index f1d1513a981..4a5cf17e41d 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -2,6 +2,8 @@
#
# Copyright (c) 2016 Google, Inc
+obj-$(CONFIG_INTEL_ACPIGEN) += acpi.o
+
ifdef CONFIG_HAVE_MRC
obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o
diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c
new file mode 100644
index 000..a4d5fbd38a7
--- /dev/null
+++ b/arch/x86/cpu/intel_common/acpi.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generic Intel ACPI table generation
+ *
+ * Copyright (C) 2017 Intel Corp.
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot src/soc/intel/common/block/acpi.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+u32 acpi_fill_mcfg(u32 current)
+{
+ /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
+ current += acpi_create_mcfg_mmconfig((void *)current,
+CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
+(CONFIG_SA_PCIEX_LENGTH >> 20)
+- 1);
+ return current;
+}
+
+static int acpi_sci_irq(void)
+{
+ int sci_irq = 9;
+ uint scis;
+ int ret;
+
+ ret = arch_read_sci_irq_select();
+ if (IS_ERR_VALUE(ret))
+ return log_msg_ret("sci_irq", ret);
+ scis = ret;
+ scis &= SCI_IRQ_MASK;
+ scis >>= SCI_IRQ_SHIFT;
+
+ /* Determine how SCI is routed. */
+ switch (scis) {
+ case SCIS_IRQ9:
+ case SCIS_IRQ10:
+ case SCIS_IRQ11:
+ sci_irq = scis - SCIS_IRQ9 + 9;
+ break;
+ case SCIS_IRQ20:
+ case SCIS_IRQ21:
+ case SCIS_IRQ22:
+ case SCIS_IRQ23:
+ sci_irq = scis - SCIS_IRQ20 + 20;
+ break;
+ default:
+ log_warning("Invalid SCI route! Defaulting to IRQ9\n");
+ sci_irq = 9;
+ break;
+ }
+
+ log_debug("SCI is IRQ%d\n", sci_irq);
+
+ return sci_irq;
+}
+
+static unsigned long acpi_madt_irq_overrides(unsigned long current)
+{
+ int sci = acpi_sci_irq();
+ u16 flags = MP_IRQ_TRIGGER_LEVEL;
+
+ if (sci < 0)
+ return log_msg_ret("sci irq", sci);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0);
+
+ flags |= arch_madt_sci_irq_polarity(sci);
+
+ /* SCI */
+ current +=
+ acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags);
+
+ return current;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+ /* Local APICs */
+ current += acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0);
+
+ return acpi_madt_irq_overrides(current);
+}
+
+void intel_acpi_fill_fadt(struct acpi_fadt *fadt)
+{
+ const u16 pmbase = IOMAP_ACPI_BASE;
+
+ /* Use ACPI 3.0 revision. */
+ fadt->header.revision = acpi_get_table_revision(ACPITAB_FADT);
+
+ fadt->sci_int = acpi_sci_irq();
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase + PM1_STS;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
+ fadt->pm1b_cnt_blk = 0x0;
+
+ fadt->gpe0_blk = pmbase + GPE0_STS;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+
+ /* GPE0 STS/EN pairs each 32 bits wide. */
+ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
+
+ fadt->flush_size = 0x400; /* twice of cache size */
+ fadt->flush_stride = 0x10; /* Cache line width */
+ fadt->duty_offset = 1;
+ fadt->day_alrm = 0xd;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED |
[PATCH v1 20/54] x86: apl: Update iomap for ACPI
Add some more definitions to the iomap. These will be used by ACPI-generation code as well as the device tree. Signed-off-by: Simon Glass --- arch/x86/include/asm/arch-apollolake/iomap.h | 16 1 file changed, 16 insertions(+) diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h index 4ce10170558..21c5f33021a 100644 --- a/arch/x86/include/asm/arch-apollolake/iomap.h +++ b/arch/x86/include/asm/arch-apollolake/iomap.h @@ -11,11 +11,27 @@ /* Put p2sb at 0xd000 in TPL */ #define IOMAP_P2SB_BAR 0xd000 +#define IOMAP_P2SB_SIZE0x1000 #define IOMAP_SPI_BASE 0xfe01 #define IOMAP_ACPI_BASE0x400 #define IOMAP_ACPI_SIZE0x100 +#define ACPI_BASE_ADDRESS IOMAP_ACPI_BASE + +#define PMC_BAR0 0xfe042000 + +#define MCH_BASE_ADDRESS 0xfed1 +#define MCH_SIZE 0x8000 + +#ifdef __ACPI__ +#define HPET_BASE_ADDRESS 0xfed0 + +#define SRAM_BASE_00xfe90 +#define SRAM_SIZE_0(8 * KiB) +#define SRAM_BASE_20xfe902000 +#define SRAM_SIZE_2(4 * KiB) +#endif /* * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial -- 2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 29/54] x86: acpi: Add support for additional Intel tables
Apollo Lake needs to generate a few more table types used on Intel SoCs.
Add support for these into the x86 ACPI code.
Signed-off-by: Simon Glass
---
Changes in v1:
- Move this code into an x86-specific file
- Update commit message
- Use OEM_TABLE_ID instead of ACPI_TABLE_CREATOR
arch/x86/include/asm/acpi_table.h | 115 ++
arch/x86/lib/acpi_table.c | 111
include/acpi/acpi_table.h | 43 +++
3 files changed, 269 insertions(+)
diff --git a/arch/x86/include/asm/acpi_table.h
b/arch/x86/include/asm/acpi_table.h
index 3245e447813..faf31730730 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -98,4 +98,119 @@ int arch_write_sci_irq_select(uint scis);
*/
int arch_madt_sci_irq_polarity(int sci);
+/**
+ * acpi_create_dmar_drhd() - Create a table for DMA remapping with the IOMMU
+ *
+ * See here for the specification
+ *
https://software.intel.com/sites/default/files/managed/c5/15/vt-directed-io-spec.pdf
+ *
+ * @ctx: ACPI context pointer
+ * @flags: (DRHD_INCLUDE_...)
+ * @segment: PCI segment asscociated with this unit
+ * @bar: Base address of remapping hardware register-set for this unit
+ */
+void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment,
+ u64 bar);
+
+/**
+ * acpi_create_dmar_rmrr() - Set up an RMRR
+ *
+ * This sets up a Reserved-Memory Region Reporting structure, used to allow
+ * DMA to regions used by devices that the BIOS controls.
+ *
+ * @ctx: ACPI context pointer
+ * @segment: PCI segment asscociated with this unit
+ * @bar: Base address of mapping
+ * @limit: End address of mapping
+ */
+void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar,
+ u64 limit);
+
+/**
+ * acpi_dmar_drhd_fixup() - Set the length of an DRHD
+ *
+ * This sets the DRHD length field based on the current ctx->current
+ *
+ * @ctx: ACPI context pointer
+ * @base: Address of the start of the DRHD
+ */
+void acpi_dmar_drhd_fixup(struct acpi_ctx *ctx, void *base);
+
+/**
+ * acpi_dmar_rmrr_fixup() - Set the length of an RMRR
+ *
+ * This sets the RMRR length field based on the current ctx->current
+ *
+ * @ctx: ACPI context pointer
+ * @base: Address of the start of the RMRR
+ */
+void acpi_dmar_rmrr_fixup(struct acpi_ctx *ctx, void *base);
+
+/**
+ * acpi_create_dmar_ds_pci() - Set up a DMAR scope for a PCI device
+ *
+ * @ctx: ACPI context pointer
+ * @bdf: PCI device to add
+ * @return length of mapping in bytes
+ */
+int acpi_create_dmar_ds_pci(struct acpi_ctx *ctx, pci_dev_t bdf);
+
+/**
+ * acpi_create_dmar_ds_pci_br() - Set up a DMAR scope for a PCI bridge
+ *
+ * This is used to provide a mapping for a PCI bridge
+ *
+ * @ctx: ACPI context pointer
+ * @bdf: PCI device to add
+ * @return length of mapping in bytes
+ */
+int acpi_create_dmar_ds_pci_br(struct acpi_ctx *ctx, pci_dev_t bdf);
+
+/**
+ * acpi_create_dmar_ds_ioapic() - Set up a DMAR scope for an IOAPIC device
+ *
+ * @ctx: ACPI context pointer
+ * @enumeration_id: Enumeration ID (typically 2)
+ * @bdf: PCI device to add
+ * @return length of mapping in bytes
+ */
+int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id,
+ pci_dev_t bdf);
+
+/**
+ * acpi_create_dmar_ds_msi_hpet() - Set up a DMAR scope for an HPET
+ *
+ * Sets up a scope for a High-Precision Event Timer that supports
+ * Message-Signalled Interrupts
+ *
+ * @ctx: ACPI context pointer
+ * @enumeration_id: Enumeration ID (typically 0)
+ * @bdf: PCI device to add
+ * @return length of mapping in bytes
+ */
+int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id,
+pci_dev_t bdf);
+
+/**
+ * acpi_fadt_common() - Handle common parts of filling out an FADT
+ *
+ * This sets up the Fixed ACPI Description Table
+ *
+ * @fadt: Pointer to place to put FADT
+ * @facs: Pointer to the FACS
+ * @dsdt: Pointer to the DSDT
+ */
+void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt);
+
+/**
+ * intel_acpi_fill_fadt() - Set up the contents of the FADT
+ *
+ * This sets up parts of the Fixed ACPI Description Table that are common to
+ * Intel chips
+ *
+ * @fadt: Pointer to place to put FADT
+ */
+void intel_acpi_fill_fadt(struct acpi_fadt *fadt);
+
#endif /* __ASM_ACPI_TABLE_H__ */
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 28a27103342..b0cc1f123e2 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -616,3 +616,114 @@ int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct
udevice *dev,
return 0;
}
+
+void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt)
+{
+ struct acpi_table_header *header = >header;
+
+ memset((void *)fadt, '\0', sizeof(struct acpi_fadt));
+
+ acpi_fill_header(header, "FACP");
+
[PATCH v1 17/54] x86: acpi: Add a common routine to write WiFi info
Intel WiFi chips can use a common routine to write the information needed
by linux. Add an implementation of this.
Enable it for coral.
Signed-off-by: Simon Glass
---
Changes in v1:
- Capitalise ACPI_OPS_PTR
- Use acpi,ddn instead of acpi,desc
arch/x86/Kconfig | 8 ++
arch/x86/cpu/intel_common/Makefile | 1 +
arch/x86/cpu/intel_common/generic_wifi.c | 120 +++
configs/chromebook_coral_defconfig | 1 +
4 files changed, 130 insertions(+)
create mode 100644 arch/x86/cpu/intel_common/generic_wifi.c
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 96156cfd2a9..7062384780b 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -997,4 +997,12 @@ config INTEL_GMA_ACPI
connected to the device. Enable this option to create this
table so that graphics works correctly.
+config INTEL_GENERIC_WIFI
+ bool "Enable generation of ACPI tables for Intel WiFi"
+ help
+ Select this option to provide code to a build generic WiFi ACPI table
+ for Intel WiFi devices. This is not a WiFi driver and offers no
+ network functionality. It is only here to generate the ACPI tables
+ required by Linux.
+
endmenu
diff --git a/arch/x86/cpu/intel_common/Makefile
b/arch/x86/cpu/intel_common/Makefile
index 207d5413965..f1d1513a981 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -24,6 +24,7 @@ obj-y += cpu.o
obj-y += fast_spi.o
obj-y += lpc.o
obj-y += lpss.o
+obj-$(CONFIG_INTEL_GENERIC_WIFI) += generic_wifi.o
ifndef CONFIG_TARGET_EFI_APP
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
ifndef CONFIG_$(SPL_)X86_64
diff --git a/arch/x86/cpu/intel_common/generic_wifi.c
b/arch/x86/cpu/intel_common/generic_wifi.c
new file mode 100644
index 000..61ec5391b09
--- /dev/null
+++ b/arch/x86/cpu/intel_common/generic_wifi.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generic WiFi ACPI info
+ *
+ * Copyright 2019 Google LLC
+ * Modified from coreboot src/drivers/wifi/generic.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* WRDS Spec Revision */
+#define WRDS_REVISION 0x0
+
+/* EWRD Spec Revision */
+#define EWRD_REVISION 0x0
+
+/* WRDS Domain type */
+#define WRDS_DOMAIN_TYPE_WIFI 0x7
+
+/* EWRD Domain type */
+#define EWRD_DOMAIN_TYPE_WIFI 0x7
+
+/* WGDS Domain type */
+#define WGDS_DOMAIN_TYPE_WIFI 0x7
+
+/*
+ * WIFI ACPI NAME = "WF" + hex value of last 8 bits of dev_path_encode + '\0'
+ * The above representation returns unique and consistent name every time
+ * generate_wifi_acpi_name is invoked. The last 8 bits of dev_path_encode is
+ * chosen since it contains the bus address of the device.
+ */
+#define WIFI_ACPI_NAME_MAX_LEN 5
+
+/**
+ * struct generic_wifi_config - Data structure to contain common wifi config
+ * @wake: Wake pin for ACPI _PRW
+ * @maxsleep: Maximum sleep state to wake from
+ */
+struct generic_wifi_config {
+ unsigned int wake;
+ unsigned int maxsleep;
+};
+
+static int generic_wifi_fill_ssdt(struct acpi_ctx *ctx,
+ const struct udevice *dev,
+ const struct generic_wifi_config *config)
+{
+ char name[ACPI_NAME_MAX];
+ char path[ACPI_PATH_MAX];
+ pci_dev_t bdf;
+ u32 address;
+ int ret;
+
+ ret = acpi_device_path(dev_get_parent(dev), path, sizeof(path));
+ if (ret)
+ return log_msg_ret("path", ret);
+ ret = acpi_get_name(dev, name);
+ if (ret)
+ return log_msg_ret("name", ret);
+
+ /* Device */
+ acpigen_write_scope(ctx, path);
+ acpigen_write_device(ctx, name);
+ acpigen_write_name_integer(ctx, "_UID", 0);
+ acpigen_write_name_string(ctx, "_DDN",
+ dev_read_string(dev, "acpi,ddn"));
+
+ /* Address */
+ bdf = dm_pci_get_bdf(dev);
+ address = (PCI_DEV(bdf) << 16) | PCI_FUNC(bdf);
+ acpigen_write_name_dword(ctx, "_ADR", address);
+
+ /* Wake capabilities */
+ if (config)
+ acpigen_write_prw(ctx, config->wake, config->maxsleep);
+
+ acpigen_pop_len(ctx); /* Device */
+ acpigen_pop_len(ctx); /* Scope */
+
+ return 0;
+}
+
+static int intel_wifi_acpi_fill_ssdt(const struct udevice *dev,
+struct acpi_ctx *ctx)
+{
+ struct generic_wifi_config config;
+ bool have_config;
+ int ret;
+
+ ret = dev_read_u32(dev, "acpi,wake", );
+ have_config = !ret;
+ /* By default, all intel wifi chips wake from S3 */
+ config.maxsleep = 3;
+ ret = generic_wifi_fill_ssdt(ctx, dev, have_config ? : NULL);
+ if (ret)
+ return log_msg_ret("wifi", ret);
+
+ return 0;
+}
+
+struct acpi_ops wifi_acpi_ops = {
+ .fill_ssdt = intel_wifi_acpi_fill_ssdt,
+};
+
+static const struct udevice_id intel_wifi_ids[] = {
[PATCH v1 16/54] x86: apl: Support writing the IntelGraphicsMem table
This table is needed by the Linux graphics driver to handle graphics
correctly. Write it to ACPI.
Signed-off-by: Simon Glass
---
Changes in v1:
- Capitalise ACPI_OPS_PTR
- Don't build for SPL
arch/x86/Kconfig | 8 +
arch/x86/cpu/apollolake/Kconfig| 1 +
arch/x86/cpu/intel_common/Makefile | 4 +
arch/x86/cpu/intel_common/intel_opregion.c | 168 ++
arch/x86/include/asm/intel_opregion.h | 247 +
arch/x86/lib/fsp/fsp_graphics.c| 32 +++
include/bloblist.h | 1 +
7 files changed, 461 insertions(+)
create mode 100644 arch/x86/cpu/intel_common/intel_opregion.c
create mode 100644 arch/x86/include/asm/intel_opregion.h
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 61dbbab9298..96156cfd2a9 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -989,4 +989,12 @@ config PCIEX_LENGTH_128MB
config PCIEX_LENGTH_64MB
bool
+config INTEL_GMA_ACPI
+ bool "Generate ACPI table for Intel GMA graphics"
+ help
+ The Intel GMA graphics driver in Linux expects an ACPI table
+ which describes the layout of the registers and the display
+ connected to the device. Enable this option to create this
+ table so that graphics works correctly.
+
endmenu
diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
index 16ac2b3f504..319f12684b7 100644
--- a/arch/x86/cpu/apollolake/Kconfig
+++ b/arch/x86/cpu/apollolake/Kconfig
@@ -48,6 +48,7 @@ config INTEL_APOLLOLAKE
imply CMD_CLK
imply CLK_INTEL
imply ACPI_GPE
+ imply INTEL_GMA_ACPI
if INTEL_APOLLOLAKE
diff --git a/arch/x86/cpu/intel_common/Makefile
b/arch/x86/cpu/intel_common/Makefile
index 374803b8760..207d5413965 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -9,6 +9,10 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
endif
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_INTEL_GMA_ACPI) += intel_opregion.o
+endif
+
ifdef CONFIG_INTEL_CAR_CQOS
obj-$(CONFIG_TPL_BUILD) += car2.o
ifndef CONFIG_SPL_BUILD
diff --git a/arch/x86/cpu/intel_common/intel_opregion.c
b/arch/x86/cpu/intel_common/intel_opregion.c
new file mode 100644
index 000..4e6c64d9aaa
--- /dev/null
+++ b/arch/x86/cpu/intel_common/intel_opregion.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Writing IntelGraphicsMem table for ACPI
+ *
+ * Copyright 2019 Google LLC
+ * Modified from coreboot src/soc/intel/gma/opregion.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+static char vbt_data[8 << 10];
+
+static int locate_vbt(char **vbtp, int *sizep)
+{
+ struct binman_entry vbt;
+ struct udevice *dev;
+ u32 vbtsig = 0;
+ int size;
+ int ret;
+
+ ret = binman_entry_find("intel-vbt", );
+ if (ret)
+ return log_msg_ret("find VBT", ret);
+ ret = uclass_first_device_err(UCLASS_SPI_FLASH, );
+ if (ret)
+ return log_msg_ret("find flash", ret);
+ size = vbt.size;
+ if (size > sizeof(vbt_data))
+ return log_msg_ret("vbt", -E2BIG);
+ ret = spi_flash_read_dm(dev, vbt.image_pos, size, vbt_data);
+ if (ret)
+ return log_msg_ret("read", ret);
+
+ memcpy(, vbt_data, sizeof(vbtsig));
+ if (vbtsig != VBT_SIGNATURE) {
+ log_err("Missing/invalid signature in VBT data file!\n");
+ return -EINVAL;
+ }
+
+ log_info("Found a VBT of %u bytes\n", size);
+ *sizep = size;
+ *vbtp = vbt_data;
+
+ return 0;
+}
+
+/* Write ASLS PCI register and prepare SWSCI register */
+static int intel_gma_opregion_register(struct udevice *dev, ulong opregion)
+{
+ int sci_reg;
+
+ if (!device_active(dev))
+ return -ENOENT;
+
+ /*
+* Intel BIOS Specification
+* Chapter 5.3.7 "Initialise Hardware State"
+*/
+ dm_pci_write_config32(dev, ASLS, opregion);
+
+ /*
+* Atom-based platforms use a combined SMI/SCI register,
+* whereas non-Atom platforms use a separate SCI register
+*/
+ if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI))
+ sci_reg = SWSMISCI;
+ else
+ sci_reg = SWSCI;
+
+ /*
+* Intel's Windows driver relies on this:
+* Intel BIOS Specification
+* Chapter 5.4 "ASL Software SCI Handler"
+*/
+ dm_pci_clrset_config16(dev, sci_reg, GSSCIE, SMISCISEL);
+
+ return 0;
+}
+
+int intel_gma_init_igd_opregion(struct udevice *dev,
+ struct igd_opregion *opregion)
+{
+ struct optionrom_vbt *vbt = NULL;
+ char *vbt_buf;
+ int vbt_size;
+ int ret;
+
+ ret = locate_vbt(_buf, _size);
+ if (ret) {
+ log_err("GMA: VBT couldn't be
[PATCH v1 19/54] x86: apl: Add power-management definitions
Add SCI and power-state definitions required by ACPI tables. Fix the
license to match the original source file.
Als update the guard on acpi_pmc.h to avoid an error when buiding ASL.
Signed-off-by: Simon Glass
---
Changes in v1:
- Use SHIFT and MASK for defines
arch/x86/include/asm/arch-apollolake/pm.h | 40 ++-
include/power/acpi_pmc.h | 4 +--
2 files changed, 41 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/arch-apollolake/pm.h
b/arch/x86/include/asm/arch-apollolake/pm.h
index 6718290c4fe..9a8d971e910 100644
--- a/arch/x86/include/asm/arch-apollolake/pm.h
+++ b/arch/x86/include/asm/arch-apollolake/pm.h
@@ -1,12 +1,15 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015-2016 Intel Corp.
* (Written by Lance Zhao for Intel Corp.)
+ * Copyright 2019 Google LLC
*/
#ifndef _ASM_ARCH_PM_H
#define _ASM_ARCH_PM_H
+#include
+
#define PMC_GPE_SW_31_00
#define PMC_GPE_SW_63_32 1
#define PMC_GPE_NW_31_03
@@ -16,4 +19,39 @@
#define PMC_GPE_N_63_327
#define PMC_GPE_W_31_0 9
+#define IRQ_REG0x106c
+#define SCI_IRQ_SHIFT 24
+#define SCI_IRQ_MASK (0xff << SCI_IRQ_SHIFT)
+#define SCIS_IRQ9 9
+#define SCIS_IRQ10 10
+#define SCIS_IRQ11 11
+#define SCIS_IRQ20 20
+#define SCIS_IRQ21 21
+#define SCIS_IRQ22 22
+#define SCIS_IRQ23 23
+
+/* P-state configuration */
+#define PSS_MAX_ENTRIES8
+#define PSS_RATIO_STEP 2
+#define PSS_LATENCY_TRANSITION 10
+#define PSS_LATENCY_BUSMASTER 10
+
+#ifndef __ASSEMBLY__
+/* Track power state from reset to log events */
+struct __packed chipset_power_state {
+ u16 pm1_sts;
+ u16 pm1_en;
+ u32 pm1_cnt;
+ u32 gpe0_sts[GPE0_REG_MAX];
+ u32 gpe0_en[GPE0_REG_MAX];
+ u16 tco1_sts;
+ u16 tco2_sts;
+ u32 prsts;
+ u32 gen_pmcon1;
+ u32 gen_pmcon2;
+ u32 gen_pmcon3;
+ u32 prev_sleep_state;
+};
+#endif /* !__ASSEMBLY__ */
+
#endif
diff --git a/include/power/acpi_pmc.h b/include/power/acpi_pmc.h
index 5fbf7451369..88b71a4 100644
--- a/include/power/acpi_pmc.h
+++ b/include/power/acpi_pmc.h
@@ -6,7 +6,7 @@
#ifndef __ACPI_PMC_H
#define __ACPI_PMC_H
-#ifndef __ACPI__
+#ifndef __ASSEMBLY__
enum {
GPE0_REG_MAX= 4,
@@ -194,6 +194,6 @@ void pmc_dump_info(struct udevice *dev);
*/
int pmc_gpe_init(struct udevice *dev);
-#endif /* !__ACPI__ */
+#endif /* !__ASSEMBLY__ */
#endif
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 18/54] x86: Add some definitions for SMM
U-Boot does not support SMM (System Management Mode) at present, but needs a few definitions to correctly set up the ACPI table. Add these. Signed-off-by: Simon Glass --- arch/x86/include/asm/smm.h | 27 +++ 1 file changed, 27 insertions(+) create mode 100644 arch/x86/include/asm/smm.h diff --git a/arch/x86/include/asm/smm.h b/arch/x86/include/asm/smm.h new file mode 100644 index 000..1e539fda067 --- /dev/null +++ b/arch/x86/include/asm/smm.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SMM definitions (U-Boot does not support SMM itself) + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2019 Google LLC + * + * Modified from coreboot smm.h + */ + +#ifndef _ASM_SMM_H +#define _ASM_SMM_H + +#define APM_CNT0xb2 +#define APM_CNT_CST_CONTROL0x85 +#define APM_CNT_PST_CONTROL0x80 +#define APM_CNT_ACPI_DISABLE 0x1e +#define APM_CNT_ACPI_ENABLE0xe1 +#define APM_CNT_MBI_UPDATE 0xeb +#define APM_CNT_GNVS_UPDATE0xea +#define APM_CNT_FINALIZE 0xcb +#define APM_CNT_LEGACY 0xcc +#define APM_CNT_SMMSTORE 0xed +#define APM_CNT_ELOG_GSMI 0xef +#define APM_STS0xb3 + +#endif /* _ASM_SMM_H */ -- 2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 15/54] x86: Add wake sources for the acpi_gpe driver
Some devices can wake the system from sleep, e.g opening the lid on a clamshell or moving a USB mouse. Add a wake to specify this for USB devices and add the settings for Apollo Lake. Signed-off-by: Simon Glass --- arch/x86/include/asm/arch-apollolake/gpe.h | 135 arch/x86/include/asm/arch-apollolake/gpio.h | 3 + doc/device-tree-bindings/device.txt | 3 + 3 files changed, 141 insertions(+) create mode 100644 arch/x86/include/asm/arch-apollolake/gpe.h diff --git a/arch/x86/include/asm/arch-apollolake/gpe.h b/arch/x86/include/asm/arch-apollolake/gpe.h new file mode 100644 index 000..f5792960bee --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/gpe.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Intel Corporation + * Copyright 2020 Google LLC + * + * Taken from coreboot apl gpe.h + */ + +#ifndef _ASM_ARCH_GPE_H_ +#define _ASM_ARCH_GPE_H_ + +/* bit position in GPE0a_STS register */ +#define GPE0A_PCIE_SCI_STS 0 +#define GPE0A_SWGPE_STS2 +#define GPE0A_PCIE_WAKE0_STS 3 +#define GPE0A_PUNIT_SCI_STS4 +#define GPE0A_PCIE_WAKE1_STS 6 +#define GPE0A_PCIE_WAKE2_STS 7 +#define GPE0A_PCIE_WAKE3_STS 8 +#define GPE0A_PCIE_GPE_STS 9 +#define GPE0A_BATLOW_STS 10 +#define GPE0A_CSE_PME_STS 11 +#define GPE0A_XDCI_PME_STS 12 +#define GPE0A_XHCI_PME_STS 13 +#define GPE0A_AVS_PME_STS 14 +#define GPE0A_GPIO_TIER1_SCI_STS 15 +#define GPE0A_SMB_WAK_STS 16 +#define GPE0A_SATA_PME_STS 17 +#define GPE0A_CNVI_PME_STS 18 + +/* Group DW0 is reserved in Apollolake */ + +/* GPE_63_32 */ +#define GPE0_DW1_0032 +#define GPE0_DW1_0133 +#define GPE0_DW1_0234 +#define GPE0_DW1_0336 +#define GPE0_DW1_0436 +#define GPE0_DW1_0537 +#define GPE0_DW1_0638 +#define GPE0_DW1_0739 +#define GPE0_DW1_0840 +#define GPE0_DW1_0941 +#define GPE0_DW1_1042 +#define GPE0_DW1_1143 +#define GPE0_DW1_1244 +#define GPE0_DW1_1345 +#define GPE0_DW1_1446 +#define GPE0_DW1_1547 +#define GPE0_DW1_1648 +#define GPE0_DW1_1749 +#define GPE0_DW1_1850 +#define GPE0_DW1_1951 +#define GPE0_DW1_2052 +#define GPE0_DW1_2153 +#define GPE0_DW1_2254 +#define GPE0_DW1_2355 +#define GPE0_DW1_2456 +#define GPE0_DW1_2557 +#define GPE0_DW1_2658 +#define GPE0_DW1_2759 +#define GPE0_DW1_2860 +#define GPE0_DW1_2961 +#define GPE0_DW1_3062 +#define GPE0_DW1_3163 +/* GPE_95_64 */ +#define GPE0_DW2_0064 +#define GPE0_DW2_0165 +#define GPE0_DW2_0266 +#define GPE0_DW2_0367 +#define GPE0_DW2_0468 +#define GPE0_DW2_0569 +#define GPE0_DW2_0670 +#define GPE0_DW2_0771 +#define GPE0_DW2_0872 +#define GPE0_DW2_0973 +#define GPE0_DW2_1074 +#define GPE0_DW2_1175 +#define GPE0_DW2_1276 +#define GPE0_DW2_1377 +#define GPE0_DW2_1478 +#define GPE0_DW2_1579 +#define GPE0_DW2_1680 +#define GPE0_DW2_1781 +#define GPE0_DW2_1882 +#define GPE0_DW2_1983 +#define GPE0_DW2_2084 +#define GPE0_DW2_2185 +#define GPE0_DW2_2286 +#define GPE0_DW2_2387 +#define GPE0_DW2_2488 +#define GPE0_DW2_2589 +#define GPE0_DW2_2690 +#define GPE0_DW2_2791 +#define GPE0_DW2_2892 +#define GPE0_DW2_2993 +#define GPE0_DW2_3094 +#define GPE0_DW2_3195 +/* GPE_127_96 */ +#define GPE0_DW3_0096 +#define GPE0_DW3_0197 +#define GPE0_DW3_0298 +#define GPE0_DW3_0399 +#define GPE0_DW3_04100 +#define GPE0_DW3_05101 +#define GPE0_DW3_06102 +#define GPE0_DW3_07103 +#define GPE0_DW3_08104 +#define GPE0_DW3_09105 +#define GPE0_DW3_10106 +#define GPE0_DW3_11107 +#define GPE0_DW3_12108 +#define GPE0_DW3_13109 +#define GPE0_DW3_14110 +#define GPE0_DW3_15111 +#define GPE0_DW3_16112 +#define GPE0_DW3_17113 +#define GPE0_DW3_18114 +#define GPE0_DW3_19115 +#define GPE0_DW3_20116 +#define GPE0_DW3_21117 +#define GPE0_DW3_22118 +#define GPE0_DW3_23119 +#define GPE0_DW3_24120 +#define GPE0_DW3_25121 +#define
[PATCH v1 10/54] x86: coral: Add ACPI tables for coral
This device has a large set of ACPI tables. Bring these in from coreboot
so that full functionality is available (apart from SMI).
Signed-off-by: Simon Glass
---
Changes in v1:
- Add NHLT audio support
- Capitalise ACPI_OPS_PTR
- Use OEM_TABLE_ID instead of ACPI_TABLE_CREATOR
board/google/chromebook_coral/Makefile| 1 +
.../chromebook_coral/baseboard_dptf.asl | 71 +
board/google/chromebook_coral/coral.c | 135 ++
board/google/chromebook_coral/dsdt.asl| 60
.../google/chromebook_coral/variant_dptf.asl | 6 +
board/google/chromebook_coral/variant_ec.h| 75 ++
board/google/chromebook_coral/variant_gpio.h | 63
include/bloblist.h| 5 +
8 files changed, 416 insertions(+)
create mode 100644 board/google/chromebook_coral/baseboard_dptf.asl
create mode 100644 board/google/chromebook_coral/dsdt.asl
create mode 100644 board/google/chromebook_coral/variant_dptf.asl
create mode 100644 board/google/chromebook_coral/variant_ec.h
create mode 100644 board/google/chromebook_coral/variant_gpio.h
diff --git a/board/google/chromebook_coral/Makefile
b/board/google/chromebook_coral/Makefile
index 6a27ce3da1b..f7a0ca6cc0a 100644
--- a/board/google/chromebook_coral/Makefile
+++ b/board/google/chromebook_coral/Makefile
@@ -3,3 +3,4 @@
# Copyright 2019 Google LLC
obj-y += coral.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/google/chromebook_coral/baseboard_dptf.asl
b/board/google/chromebook_coral/baseboard_dptf.asl
new file mode 100644
index 000..5da963a6705
--- /dev/null
+++ b/board/google/chromebook_coral/baseboard_dptf.asl
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ */
+
+#define DPTF_CPU_PASSIVE 95
+#define DPTF_CPU_CRITICAL 105
+
+#define DPTF_TSR0_SENSOR_ID0
+#define DPTF_TSR0_SENSOR_NAME "Battery"
+#define DPTF_TSR0_PASSIVE 120
+#define DPTF_TSR0_CRITICAL 125
+
+#define DPTF_TSR1_SENSOR_ID1
+#define DPTF_TSR1_SENSOR_NAME "Ambient"
+#define DPTF_TSR1_PASSIVE 46
+#define DPTF_TSR1_CRITICAL 75
+
+#define DPTF_TSR2_SENSOR_ID2
+#define DPTF_TSR2_SENSOR_NAME "Charger"
+#define DPTF_TSR2_PASSIVE 58
+#define DPTF_TSR2_CRITICAL 90
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 2 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2,/* Revision */
+ Package () {/* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 3000, /* PowerLimitMinimum */
+ 12000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () {/* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 8000, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000/* StepSize */
+ }
+})
diff --git a/board/google/chromebook_coral/coral.c
b/board/google/chromebook_coral/coral.c
index 12d4fe63cb0..0699cf35107 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c
@@ -4,7 +4,24 @@
*/
#include
+#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "variant_gpio.h"
+
+struct cros_gpio_info {
+ const char *linux_name;
+ enum cros_gpio_t type;
+ int gpio_num;
+ int flags;
+};
int arch_misc_init(void)
{
@@ -18,3 +35,121 @@ int board_run_command(const char *cmdline)
return 0;
}
+
+int chromeos_get_gpio(const struct udevice *dev, const char *prop,
+ enum cros_gpio_t type, struct cros_gpio_info *info)
+{
+ struct udevice *pinctrl;
+
[PATCH v1 14/54] i2c: Add a generic driver to generate ACPI info
Many I2C devices produce roughly the same ACPI data with just things like
the GPIO/interrupt information being different.
This can be handled by a generic driver along with some information in the
device tree.
Add a generic i2c driver for this purpose.
Signed-off-by: Simon Glass
---
Changes in v1:
- Adjust implementation to match new ACPI GPIO generation
- Capitalise ACPI_OPS_PTR
- Rename acpi-probed to linux,probed
- Support hid-over-i2c separately as well
- Use acpi,ddn instead of acpi,desc
- Use updated acpi_device_write_dsm_i2c_hid() function
doc/device-tree-bindings/i2c/generic-acpi.txt | 42
drivers/i2c/Makefile | 3 +
drivers/i2c/acpi_i2c.c| 226 ++
drivers/i2c/acpi_i2c.h| 15 ++
drivers/i2c/i2c-uclass.c | 17 ++
include/acpi/acpi_device.h| 55 +
include/i2c.h | 23 ++
7 files changed, 381 insertions(+)
create mode 100644 doc/device-tree-bindings/i2c/generic-acpi.txt
create mode 100644 drivers/i2c/acpi_i2c.c
create mode 100644 drivers/i2c/acpi_i2c.h
diff --git a/doc/device-tree-bindings/i2c/generic-acpi.txt
b/doc/device-tree-bindings/i2c/generic-acpi.txt
new file mode 100644
index 000..f6fc1614ecf
--- /dev/null
+++ b/doc/device-tree-bindings/i2c/generic-acpi.txt
@@ -0,0 +1,42 @@
+I2C generic device
+==
+
+This is used only to generate ACPI tables for an I2C device.
+
+Required properties :
+
+ - compatible : "i2c-chip";
+ - reg : I2C chip address
+ - acpi,hid : HID name for the device
+
+Optional properies in addition to device.txt:
+
+ - reset-gpios : GPIO used to assert reset to the device
+ - irq-gpios : GPIO used for interrupt (if Interrupt is not used)
+ - stop-gpios : GPIO used to stop the device
+ - interrupts-extended : Interrupt to use for the device
+ - reset-delay-ms : Delay after de-asserting reset, in ms
+ - reset-off-delay-ms : Delay after asserting reset (during power off)
+ - enable-delay-ms : Delay after asserting enable
+ - enable-off-delay-m s: Delay after de-asserting enable (during power off)
+ - stop-delay-ms : Delay after de-aserting stop
+ - stop-off-delay-ms : Delay after asserting stop (during power off)
+ - hid-descr-addr : HID register offset (for Human Interface Devices)
+
+Example
+---
+
+ elan-touchscreen@10 {
+ compatible = "i2c-chip";
+ reg = <0x10>;
+ acpi,hid = "ELAN0001";
+ acpi,ddn = "ELAN Touchscreen";
+ interrupts-extended = <_gpe GPIO_21_IRQ
+ IRQ_TYPE_EDGE_FALLING>;
+ linux,probed;
+ reset-gpios = <_n GPIO_36 GPIO_ACTIVE_HIGH>;
+ reset-delay-ms = <20>;
+ enable-gpios = <_n GPIO_152 GPIO_ACTIVE_HIGH>;
+ enable-delay-ms = <1>;
+ acpi,has-power-resource;
+ };
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 174081e2529..53ba14ed0b2 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -3,6 +3,9 @@
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
obj-$(CONFIG_DM_I2C) += i2c-uclass.o
+ifdef CONFIG_ACPIGEN
+obj-$(CONFIG_DM_I2C) += acpi_i2c.o
+endif
obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
diff --git a/drivers/i2c/acpi_i2c.c b/drivers/i2c/acpi_i2c.c
new file mode 100644
index 000..57d29683cbf
--- /dev/null
+++ b/drivers/i2c/acpi_i2c.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#ifdef CONFIG_X86
+#include
+#endif
+#include
+#include
+
+static bool acpi_i2c_add_gpios_to_crs(struct acpi_i2c_priv *priv)
+{
+ /*
+* Return false if:
+* 1. Request to explicitly disable export of GPIOs in CRS, or
+* 2. Both reset and enable GPIOs are not provided.
+*/
+ if (priv->disable_gpio_export_in_crs ||
+ (!dm_gpio_is_valid(>reset_gpio) &&
+!dm_gpio_is_valid(>enable_gpio)))
+ return false;
+
+ return true;
+}
+
+static int acpi_i2c_write_gpio(struct acpi_ctx *ctx, struct gpio_desc *gpio,
+ int *curindex)
+{
+ int ret;
+
+ if (!dm_gpio_is_valid(gpio))
+ return -ENOENT;
+
+ acpi_device_write_gpio_desc(ctx, gpio);
+ ret = *curindex;
+ (*curindex)++;
+
+ return ret;
+}
+
+int acpi_i2c_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ int reset_gpio_index = -1, enable_gpio_index = -1, irq_gpio_index = -1;
+ enum i2c_device_t type = dev_get_driver_data(dev);
+ struct acpi_i2c_priv *priv = dev_get_priv(dev);
+ struct acpi_dp *dsd = NULL;
+ char scope[ACPI_PATH_MAX];
+
[PATCH v1 11/54] acpi: Add support for writing a _PRW
A 'Power Resource for Wake' list the resources a device depends on for
wake. Add a function to generate this.
Signed-off-by: Simon Glass
---
include/acpi/acpigen.h | 10 ++
lib/acpi/acpigen.c | 10 ++
test/dm/acpigen.c | 30 ++
3 files changed, 50 insertions(+)
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 228ac9c404b..a9b70123c0a 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -563,4 +563,14 @@ int acpigen_set_enable_tx_gpio(struct acpi_ctx *ctx, u32
tx_state_val,
const char *dw0_read, const char *dw0_write,
struct acpi_gpio *gpio, bool enable);
+/**
+ * acpigen_write_prw() - Write a power resource for wake (_PRW)
+ *
+ * @ctx: ACPI context pointer
+ * @wake: GPE that wakes up the device
+ * @level: Deepest power system sleeping state that can be entered while still
+ * providing wake functionality
+ */
+void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level);
+
#endif
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index c609ef4daa4..527de89b1e1 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -426,6 +426,16 @@ void acpigen_write_register_resource(struct acpi_ctx *ctx,
acpigen_write_resourcetemplate_footer(ctx);
}
+void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level)
+{
+ /* Name (_PRW, Package () { wake, level } */
+ acpigen_write_name(ctx, "_PRW");
+ acpigen_write_package(ctx, 2);
+ acpigen_write_integer(ctx, wake);
+ acpigen_write_integer(ctx, level);
+ acpigen_pop_len(ctx);
+}
+
/*
* ToUUID(uuid)
*
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 14a758d08a3..f53c7526d56 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -1097,3 +1097,33 @@ static int dm_test_acpi_write_name(struct
unit_test_state *uts)
return 0;
}
DM_TEST(dm_test_acpi_write_name, 0);
+
+/* Test emitting a string */
+static int dm_test_acpi_write_prw(struct unit_test_state *uts)
+{
+ struct acpi_ctx *ctx;
+ u8 *ptr;
+
+ ut_assertok(alloc_context());
+
+ ptr = acpigen_get_current(ctx);
+ acpigen_write_prw(ctx, 5, 3);
+ ut_asserteq(NAME_OP, *ptr++);
+
+ ut_asserteq_strn("_PRW", (char *)ptr);
+ ptr += 4;
+ ut_asserteq(PACKAGE_OP, *ptr++);
+ ut_asserteq(8, acpi_test_get_length(ptr));
+ ptr += 3;
+ ut_asserteq(2, *ptr++);
+ ut_asserteq(BYTE_PREFIX, *ptr++);
+ ut_asserteq(5, *ptr++);
+ ut_asserteq(BYTE_PREFIX, *ptr++);
+ ut_asserteq(3, *ptr++);
+ ut_asserteq_ptr(ptr, ctx->current);
+
+ free_context();
+
+ return 0;
+}
+DM_TEST(dm_test_acpi_write_prw, 0);
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 09/54] x86: acpi: Expand the GNVS
Expand this to 4KB so that it is possible to add custom information to it.
On Chromebooks this is used to pass verified-boot information.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/acpi/global_nvs.h | 2 +-
arch/x86/include/asm/intel_gnvs.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/acpi/global_nvs.h
b/arch/x86/include/asm/acpi/global_nvs.h
index a552cf6374f..46383629cc5 100644
--- a/arch/x86/include/asm/acpi/global_nvs.h
+++ b/arch/x86/include/asm/acpi/global_nvs.h
@@ -16,6 +16,6 @@
* DSDT, since it is created by code, so ACPI_GNVS_ADDR is unused.
*/
#define ACPI_GNVS_ADDR 0xdeadbeef
-#define ACPI_GNVS_SIZE 0x100
+#define ACPI_GNVS_SIZE 0x1000
#endif /* _ACPI_GNVS_H_ */
diff --git a/arch/x86/include/asm/intel_gnvs.h
b/arch/x86/include/asm/intel_gnvs.h
index e2d479d4f32..c1e9d65779f 100644
--- a/arch/x86/include/asm/intel_gnvs.h
+++ b/arch/x86/include/asm/intel_gnvs.h
@@ -36,6 +36,7 @@ struct __packed acpi_global_nvs {
u8 unused2[0x1000 - 0x100];/* Pad out to 4096 bytes */
#endif
};
+
#ifdef CONFIG_CHROMEOS
check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 13/54] acpi: Support generating a multi-function _DSM for devices
Add a function to generate ACPI code for a _DSM method for a device.
This includes functions for starting and ending each part of the _DSM.
Signed-off-by: Simon Glass
---
include/acpi/acpi_device.h | 14 +
include/acpi/acpigen.h | 99 +
lib/acpi/acpi_device.c | 43 +
lib/acpi/acpigen.c | 54
test/dm/acpigen.c | 126 +
5 files changed, 336 insertions(+)
diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h
index 11461e168d3..a5b12217820 100644
--- a/include/acpi/acpi_device.h
+++ b/include/acpi/acpi_device.h
@@ -28,6 +28,9 @@ struct udevice;
/* Length of a full path to an ACPI device */
#define ACPI_PATH_MAX 30
+/* UUID for an I2C _DSM method */
+#define ACPI_DSM_I2C_HID_UUID "3cdff6f7-4267-4555-ad05-b30a3d8938de"
+
/* Values that can be returned for ACPI device _STA method */
enum acpi_dev_status {
ACPI_DSTATUS_PRESENT= BIT(0),
@@ -319,6 +322,17 @@ int acpi_device_write_gpio_desc(struct acpi_ctx *ctx,
int acpi_device_write_interrupt_or_gpio(struct acpi_ctx *ctx,
struct udevice *dev, const char *prop);
+/**
+ * acpi_device_write_dsm_i2c_hid() - Write a device-specific method for HID
+ *
+ * This writes a DSM for an I2C Human-Interface Device based on the config
+ * provided
+ *
+ * @hid_desc_reg_offset: HID register offset
+ */
+int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx,
+ int hid_desc_reg_offset);
+
/**
* acpi_device_write_i2c_dev() - Write an I2C device to ACPI
*
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index fa9409e3528..34b3115bc9c 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -666,4 +666,103 @@ void acpigen_write_return_singleton_buffer(struct
acpi_ctx *ctx, uint arg);
*/
void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg);
+/**
+ * acpigen_write_dsm_start() - Start a _DSM method
+ *
+ * Generate ACPI AML code to start the _DSM method.
+ *
+ * The functions need to be called in the correct sequence as below.
+ *
+ * Within the region, Local0 and Local1 must be are left
+ * untouched, but Local2-Local7 can be used
+ *
+ * Arguments passed into _DSM method:
+ * Arg0 = UUID
+ * Arg1 = Revision
+ * Arg2 = Function index
+ * Arg3 = Function-specific arguments
+ *
+ * AML code generated looks like this:
+ * Method (_DSM, 4, Serialized) { -- acpigen_write_dsm_start)
+ * ToBuffer (Arg0, Local0)
+ * If (LEqual (Local0, ToUUID(uuid))) { -- acpigen_write_dsm_uuid_start
+ * ToInteger (Arg2, Local1)
+ * If (LEqual (Local1, 0)) { -- acpigen_write_dsm_uuid_start_cond
+ *
+ * } -- acpigen_write_dsm_uuid_end_cond
+ * ...
+ * If (LEqual (Local1, n)) { -- acpigen_write_dsm_uuid_start_cond
+ *
+ * } -- acpigen_write_dsm_uuid_end_cond
+ * Return (Buffer (One) { 0x0 })
+ * } -- acpigen_write_dsm_uuid_end
+ * ...
+ * If (LEqual (Local0, ToUUID(uuidn))) {
+ * ...
+ * }
+ * Return (Buffer (One) { 0x0 }) -- acpigen_write_dsm_end
+ * }
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_start(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_dsm_uuid_start() - Start a new UUID block
+ *
+ * This starts generation of code to handle a particular UUID:
+ *
+ * If (LEqual (Local0, ToUUID(uuid))) {
+ * ToInteger (Arg2, Local1)
+ *
+ * @ctx: ACPI context pointer
+ */
+int acpigen_write_dsm_uuid_start(struct acpi_ctx *ctx, const char *uuid);
+
+/**
+ * acpigen_write_dsm_uuid_start_cond() - Start a new condition block
+ *
+ * This starts generation of condition-checking code to handle a particular
+ * function:
+ *
+ * If (LEqual (Local1, i))
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_uuid_start_cond(struct acpi_ctx *ctx, int seq);
+
+/**
+ * acpigen_write_dsm_uuid_end_cond() - Start a new condition block
+ *
+ * This ends generation of condition-checking code to handle a particular
+ * function:
+ *
+ * }
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_uuid_end_cond(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_dsm_uuid_end() - End a UUID block
+ *
+ * This ends generation of code to handle a particular UUID:
+ *
+ * Return (Buffer (One) { 0x0 })
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_uuid_end(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_dsm_end() - End a _DSM method
+ *
+ * This ends generates of the _DSM block:
+ *
+ * Return (Buffer (One) { 0x0 })
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_end(struct acpi_ctx *ctx);
+
#endif
diff --git a/lib/acpi/acpi_device.c b/lib/acpi/acpi_device.c
index
[PATCH v1 03/54] x86: acpi: apl: Add asl files for Apollo Lake
Add Apollo Lake ASL files, taken from coreboot.
Signed-off-by: Simon Glass
---
.../include/asm/arch-apollolake/acpi/dptf.asl | 35
.../asm/arch-apollolake/acpi/globalnvs.asl| 41
.../include/asm/arch-apollolake/acpi/gpio.asl | 191 ++
.../asm/arch-apollolake/acpi/gpiolib.asl | 109 ++
.../include/asm/arch-apollolake/acpi/lpss.asl | 105 ++
.../asm/arch-apollolake/acpi/northbridge.asl | 120 +++
.../asm/arch-apollolake/acpi/pch_hda.asl | 77 +++
.../asm/arch-apollolake/acpi/pci_irqs.asl | 52 +
.../include/asm/arch-apollolake/acpi/pcie.asl | 22 ++
.../asm/arch-apollolake/acpi/pcie_port.asl| 113 +++
.../asm/arch-apollolake/acpi/platform.asl | 10 +
.../asm/arch-apollolake/acpi/pmc_ipc.asl | 49 +
.../include/asm/arch-apollolake/acpi/scs.asl | 173
.../asm/arch-apollolake/acpi/soc_int.asl | 50 +
.../asm/arch-apollolake/acpi/southbridge.asl | 34
.../include/asm/arch-apollolake/acpi/xhci.asl | 33 +++
.../arch-apollolake/acpi/xhci_apl_ports.asl | 23 +++
.../arch-apollolake/acpi/xhci_glk_ports.asl | 24 +++
18 files changed, 1261 insertions(+)
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/gpio.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/lpss.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pcie.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/platform.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/scs.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
b/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
new file mode 100644
index 000..4c50bb45c0f
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+#define DPTF_CPU_DEVICETCPU
+#define DPTF_CPU_ADDR 0x0001
+
+#ifndef DPTF_CPU_PASSIVE
+#define DPTF_CPU_PASSIVE 80
+#endif
+
+#ifndef DPTF_CPU_CRITICAL
+#define DPTF_CPU_CRITICAL 90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC0
+#define DPTF_CPU_ACTIVE_AC090
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC1
+#define DPTF_CPU_ACTIVE_AC180
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC2
+#define DPTF_CPU_ACTIVE_AC270
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC3
+#define DPTF_CPU_ACTIVE_AC360
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC4
+#define DPTF_CPU_ACTIVE_AC450
+#endif
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
b/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
new file mode 100644
index 000..7854f7e1c5d
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Alexandru Gagniuc for Intel
Corp.)
+ */
+
+/*
+ * NOTE: The layout of the GNVS structure below must match the layout in
+ * soc/intel/apollolake/include/soc/nvs.h !!!
+ *
+ */
+
+External (NVSA)
+
+OperationRegion (GNVS, SystemMemory, NVSA, ACPI_GNVS_SIZE)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+ /* Miscellaneous */
+ Offset (0x00),
+ PCNT, 8, // 0x00 - Processor Count
+ PPCM, 8, // 0x01 - Max PPC State
+ LIDS, 8, // 0x02 - LID State
+ PWRS, 8, // 0x03 - AC Power State
+ DPTE, 8, // 0x04 - Enable DPTF
+ CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console
+ PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
+ GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
+ NHLA, 64, // 0x19 - 0x20 - NHLT Address
+ NHLL, 32, // 0x21 - 0x24 - NHLT Length
+ PRT0, 32, // 0x25 - 0x28 - PERST_0 Address
+ SCDP, 8, // 0x29 - SD_CD GPIO portid
+ SCDO, 8, // 0x2A - GPIO pad offset relative to the community
+ UIOR, 8, // 0x2B - UART debug
[PATCH v1 12/54] acpi: Add support for conditions and return values
Add functions to support generating ACPI code for condition checks and
return values.
Signed-off-by: Simon Glass
---
include/acpi/acpigen.h | 93 ++
lib/acpi/acpigen.c | 68 ++
test/dm/acpigen.c | 93 +-
3 files changed, 253 insertions(+), 1 deletion(-)
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index a9b70123c0a..fa9409e3528 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -52,12 +52,24 @@ enum {
LOCAL5_OP = 0x65,
LOCAL6_OP = 0x66,
LOCAL7_OP = 0x67,
+ ARG0_OP = 0x68,
+ ARG1_OP = 0x69,
+ ARG2_OP = 0x6a,
+ ARG3_OP = 0x6b,
+ ARG4_OP = 0x6c,
+ ARG5_OP = 0x6d,
+ ARG6_OP = 0x6e,
STORE_OP= 0x70,
AND_OP = 0x7b,
OR_OP = 0x7d,
NOT_OP = 0x80,
DEVICE_OP = 0x82,
POWER_RES_OP= 0x84,
+ LEQUAL_OP = 0x93,
+ TO_BUFFER_OP= 0x96,
+ TO_INTEGER_OP = 0x99,
+ IF_OP = 0xa0,
+ ELSE_OP = 0xa1,
RETURN_OP = 0xa4,
};
@@ -573,4 +585,85 @@ int acpigen_set_enable_tx_gpio(struct acpi_ctx *ctx, u32
tx_state_val,
*/
void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level);
+/**
+ * acpigen_write_if() - Write an If block
+ *
+ * This requires a call to acpigen_pop_len() to complete the block
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_if(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_if_lequal_op_int() - Write comparison between op and integer
+ *
+ * Generates ACPI code for checking if operand1 and operand2 are equal
+ *
+ * If (Lequal (op, val))
+ *
+ * @ctx: ACPI context pointer
+ * @op: Operand to check
+ * @val: Value to check against
+ */
+void acpigen_write_if_lequal_op_int(struct acpi_ctx *ctx, uint op, u64 val);
+
+/**
+ * acpigen_write_else() - Write an Ef block
+ *
+ * This requires a call to acpigen_pop_len() to complete the block
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_else(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_to_buffer() - Write a ToBuffer operation
+ *
+ * E.g.: to generate: ToBuffer (Arg0, Local0)
+ * use acpigen_write_to_buffer(ctx, ARG0_OP, LOCAL0_OP)
+ *
+ * @ctx: ACPI context pointer
+ * @src: Source argument
+ * @dst: Destination argument
+ */
+void acpigen_write_to_buffer(struct acpi_ctx *ctx, uint src, uint dst);
+
+/**
+ * acpigen_write_to_integer() - Write a ToInteger operation
+ *
+ * E.g.: to generate: ToInteger (Arg0, Local0)
+ * use acpigen_write_to_integer(ctx, ARG0_OP, LOCAL0_OP)
+ *
+ * @ctx: ACPI context pointer
+ * @src: Source argument
+ * @dst: Destination argument
+ */
+void acpigen_write_to_integer(struct acpi_ctx *ctx, uint src, uint dst);
+
+/**
+ * acpigen_write_return_byte_buffer() - Write a return of a byte buffer
+ *
+ * @ctx: ACPI context pointer
+ * @arr: Array of bytes to return
+ * @size: Number of bytes
+ */
+void acpigen_write_return_byte_buffer(struct acpi_ctx *ctx, u8 *arr,
+ size_t size);
+
+/**
+ * acpigen_write_return_singleton_buffer() - Write a return of a 1-byte buffer
+ *
+ * @ctx: ACPI context pointer
+ * @arg: Byte to return
+ */
+void acpigen_write_return_singleton_buffer(struct acpi_ctx *ctx, uint arg);
+
+/**
+ * acpigen_write_return_byte() - Write a return of a byte
+ *
+ * @ctx: ACPI context pointer
+ * @arg: Byte to return
+ */
+void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg);
+
#endif
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index 527de89b1e1..2518bf83dda 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -541,6 +541,74 @@ void acpigen_write_debug_string(struct acpi_ctx *ctx,
const char *str)
acpigen_emit_ext_op(ctx, DEBUG_OP);
}
+void acpigen_write_if(struct acpi_ctx *ctx)
+{
+ acpigen_emit_byte(ctx, IF_OP);
+ acpigen_write_len_f(ctx);
+}
+
+void acpigen_write_if_lequal_op_int(struct acpi_ctx *ctx, uint op, u64 val)
+{
+ acpigen_write_if(ctx);
+ acpigen_emit_byte(ctx, LEQUAL_OP);
+ acpigen_emit_byte(ctx, op);
+ acpigen_write_integer(ctx, val);
+}
+
+void acpigen_write_else(struct acpi_ctx *ctx)
+{
+ acpigen_emit_byte(ctx, ELSE_OP);
+ acpigen_write_len_f(ctx);
+}
+
+void acpigen_write_to_buffer(struct acpi_ctx *ctx, uint src, uint dst)
+{
+ acpigen_emit_byte(ctx, TO_BUFFER_OP);
+ acpigen_emit_byte(ctx, src);
+ acpigen_emit_byte(ctx, dst);
+}
+
+void acpigen_write_to_integer(struct acpi_ctx *ctx, uint src, uint dst)
+{
+ acpigen_emit_byte(ctx, TO_INTEGER_OP);
+ acpigen_emit_byte(ctx, src);
+
[PATCH v1 07/54] x86: Add a common global NVS structure
Add the definition of this structure common to Intel devices. It includes
some optional Chrome OS pieces which are used when vboot is integrated.
Drop the APL version as it is basically the same.
Signed-off-by: Simon Glass
---
Changes in v1:
- Use this file in APL
.../include/asm/arch-apollolake/global_nvs.h | 23 +-
arch/x86/include/asm/intel_gnvs.h | 43 +++
2 files changed, 44 insertions(+), 22 deletions(-)
create mode 100644 arch/x86/include/asm/intel_gnvs.h
diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h
b/arch/x86/include/asm/arch-apollolake/global_nvs.h
index fe62194b02e..ef8eb228dbe 100644
--- a/arch/x86/include/asm/arch-apollolake/global_nvs.h
+++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h
@@ -10,27 +10,6 @@
#ifndef _GLOBAL_NVS_H_
#define _GLOBAL_NVS_H_
-struct __packed acpi_global_nvs {
- /* Miscellaneous */
- u8 pcnt; /* 0x00 - Processor Count */
- u8 ppcm; /* 0x01 - Max PPC State */
- u8 lids; /* 0x02 - LID State */
- u8 pwrs; /* 0x03 - AC Power State */
- u8 dpte; /* 0x04 - Enable DPTF */
- u32 cbmc; /* 0x05 - 0x08 - U-Boot Console */
- u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
- u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */
- u64 nhla; /* 0x19 - 0x20 - NHLT Address */
- u32 nhll; /* 0x21 - 0x24 - NHLT Length */
- u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */
- u8 scdp; /* 0x29 - SD_CD GPIO portid */
- u8 scdo; /* 0x2a - GPIO pad offset relative to the community */
- u8 uior; /* 0x2b - UART debug controller init on S3 resume */
- u8 ecps; /* 0x2c - SGX Enabled status */
- u64 emna; /* 0x2d - 0x34 EPC base address */
- u64 elng; /* 0x35 - 0x3c EPC Length */
- u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */
- u8 unused2[0x1000 - 0x100];/* Pad out to 4096 bytes */
-};
+#include
#endif /* _GLOBAL_NVS_H_ */
diff --git a/arch/x86/include/asm/intel_gnvs.h
b/arch/x86/include/asm/intel_gnvs.h
new file mode 100644
index 000..e2d479d4f32
--- /dev/null
+++ b/arch/x86/include/asm/intel_gnvs.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * Taken from coreboot intelblocks/nvs.h
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _INTEL_GNVS_H_
+#define _INTEL_GNVS_H_
+
+struct __packed acpi_global_nvs {
+ /* Miscellaneous */
+ u8 pcnt; /* 0x00 - Processor Count */
+ u8 ppcm; /* 0x01 - Max PPC State */
+ u8 lids; /* 0x02 - LID State */
+ u8 pwrs; /* 0x03 - AC Power State */
+ u8 dpte; /* 0x04 - Enable DPTF */
+ u32 cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
+ u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
+ u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */
+ u64 nhla; /* 0x19 - 0x20 - NHLT Address */
+ u32 nhll; /* 0x21 - 0x24 - NHLT Length */
+ u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */
+ u8 scdp; /* 0x29 - SD_CD GPIO portid */
+ u8 scdo; /* 0x2a - GPIO pad offset relative to the community */
+ u8 uior; /* 0x2b - UART debug controller init on S3 resume */
+ u8 ecps; /* 0x2c - SGX Enabled status */
+ u64 emna; /* 0x2d - 0x34 EPC base address */
+ u64 elng; /* 0x35 - 0x3C EPC Length */
+ u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */
+#ifdef CONFIG_CHROMEOS
+ /* ChromeOS-specific (0x100 - 0xfff) */
+ struct chromeos_acpi chromeos;
+#else
+ u8 unused2[0x1000 - 0x100];/* Pad out to 4096 bytes */
+#endif
+};
+#ifdef CONFIG_CHROMEOS
+check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+#endif
+
+#endif /* _INTEL_GNVS_H_ */
--
2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 08/54] x86: acpi: Support external GNVS tables
At present U-Boot puts a magic number in the ASL for the GNVS table and
searches for it later.
Add a Kconfig option to use a different approach, where the ASL files
declare the table as an external symbol. U-Boot can then put it wherever
it likes, without any magic numbers or searching.
Signed-off-by: Simon Glass
---
arch/x86/Kconfig | 7 +
arch/x86/cpu/apollolake/Kconfig| 1 +
arch/x86/include/asm/acpi/global_nvs.h | 3 ++
arch/x86/lib/acpi_table.c | 42 ++
4 files changed, 33 insertions(+), 20 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e90d1171f19..61dbbab9298 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -776,6 +776,13 @@ config GENERATE_ACPI_TABLE
by the operating system. It defines platform-independent interfaces
for configuration and power management monitoring.
+config ACPI_GNVS_EXTERNAL
+ bool
+ help
+ Put the GNVS (Global Non-Volatile Sleeping) table separate from the
+ DSDT and add a pointer to the table from the DSDT. This allows
+ U-Boot to better control the address of the GNVS.
+
endmenu
config HAVE_ACPI_RESUME
diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
index 37d6289ee41..16ac2b3f504 100644
--- a/arch/x86/cpu/apollolake/Kconfig
+++ b/arch/x86/cpu/apollolake/Kconfig
@@ -17,6 +17,7 @@ config INTEL_APOLLOLAKE
select PCH_SUPPORT
select P2SB
select SMP_AP_WORK
+ select ACPI_GNVS_EXTERNAL
imply ENABLE_MRC_CACHE
imply AHCI_PCI
imply SCSI
diff --git a/arch/x86/include/asm/acpi/global_nvs.h
b/arch/x86/include/asm/acpi/global_nvs.h
index d56d35ca533..a552cf6374f 100644
--- a/arch/x86/include/asm/acpi/global_nvs.h
+++ b/arch/x86/include/asm/acpi/global_nvs.h
@@ -11,6 +11,9 @@
* ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file
* to declare the GNVS OperationRegion, as well as write_acpi_tables()
* for the GNVS address runtime fix up.
+ *
+ * If using CONFIG_ACPI_GNVS_EXTERNAL, we don't need to locate the GNVS in
+ * DSDT, since it is created by code, so ACPI_GNVS_ADDR is unused.
*/
#define ACPI_GNVS_ADDR 0xdeadbeef
#define ACPI_GNVS_SIZE 0x100
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 3a93fedfc3e..942b2334eab 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -428,17 +428,30 @@ ulong write_acpi_tables(ulong start_addr)
dsdt->length - sizeof(struct acpi_table_header));
acpi_inc_align(ctx, dsdt->length - sizeof(struct acpi_table_header));
+ dsdt->length = ctx->current - (void *)dsdt;
- /* Pack GNVS into the ACPI table area */
- for (i = 0; i < dsdt->length; i++) {
- u32 *gnvs = (u32 *)((u32)dsdt + i);
- if (*gnvs == ACPI_GNVS_ADDR) {
- ulong addr = (ulong)map_to_sysmem(ctx->current);
-
- debug("Fix up global NVS in DSDT to %#08lx\n", addr);
- *gnvs = addr;
- break;
+ if (!IS_ENABLED(CONFIG_ACPI_GNVS_EXTERNAL)) {
+ /* Pack GNVS into the ACPI table area */
+ for (i = 0; i < dsdt->length; i++) {
+ u32 *gnvs = (u32 *)((u32)dsdt + i);
+
+ if (*gnvs == ACPI_GNVS_ADDR) {
+ *gnvs = map_to_sysmem(ctx->current);
+ debug("Fix up global NVS in DSDT to %#08x\n",
+ *gnvs);
+ break;
+ }
}
+
+ /*
+* Fill in platform-specific global NVS variables. If this fails
+* we cannot return the error but this should only happen while
+* debugging.
+*/
+ addr = acpi_create_gnvs(ctx->current);
+ if (IS_ERR_VALUE(addr))
+ printf("Error: Gailed to create GNVS\n");
+ acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));
}
/*
@@ -446,20 +459,9 @@ ulong write_acpi_tables(ulong start_addr)
* the GNVS address. Set the checksum to zero since it is part of the
* region being checksummed.
*/
- dsdt->length = ctx->current - (void *)dsdt;
dsdt->checksum = 0;
dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);
- /*
-* Fill in platform-specific global NVS variables. If this fails we
-* cannot return the error but this should only happen while debugging.
-*/
- addr = acpi_create_gnvs(ctx->current);
- if (IS_ERR_VALUE(addr))
- printf("Error: Failed to create GNVS\n");
-
- acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));
-
debug("ACPI:* FADT\n");
fadt = ctx->current;
acpi_inc_align(ctx,
[PATCH v1 01/54] x86: acpi: Add cros_ec tables
Add ASL files for the Chrome OS EC, taken from coreboot.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/acpi/cros_ec/ac.asl | 22 +
arch/x86/include/asm/acpi/cros_ec/als.asl | 56 ++
arch/x86/include/asm/acpi/cros_ec/battery.asl | 411 +
arch/x86/include/asm/acpi/cros_ec/cros_ec.asl | 57 ++
arch/x86/include/asm/acpi/cros_ec/ec.asl | 557 ++
arch/x86/include/asm/acpi/cros_ec/emem.asl| 53 ++
.../asm/acpi/cros_ec/keyboard_backlight.asl | 52 ++
arch/x86/include/asm/acpi/cros_ec/pd.asl | 15 +
arch/x86/include/asm/acpi/cros_ec/superio.asl | 159 +
arch/x86/include/asm/acpi/cros_ec/tbmc.asl| 23 +
10 files changed, 1405 insertions(+)
create mode 100644 arch/x86/include/asm/acpi/cros_ec/ac.asl
create mode 100644 arch/x86/include/asm/acpi/cros_ec/als.asl
create mode 100644 arch/x86/include/asm/acpi/cros_ec/battery.asl
create mode 100644 arch/x86/include/asm/acpi/cros_ec/cros_ec.asl
create mode 100644 arch/x86/include/asm/acpi/cros_ec/ec.asl
create mode 100644 arch/x86/include/asm/acpi/cros_ec/emem.asl
create mode 100644 arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl
create mode 100644 arch/x86/include/asm/acpi/cros_ec/pd.asl
create mode 100644 arch/x86/include/asm/acpi/cros_ec/superio.asl
create mode 100644 arch/x86/include/asm/acpi/cros_ec/tbmc.asl
diff --git a/arch/x86/include/asm/acpi/cros_ec/ac.asl
b/arch/x86/include/asm/acpi/cros_ec/ac.asl
new file mode 100644
index 000..80e0ebd3ad5
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/ac.asl
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ */
+
+// Scope (EC0)
+
+Device (AC)
+{
+ Name (_HID, "ACPI0003")
+ Name (_PCL, Package () { \_SB })
+
+ Method (_PSR)
+ {
+ Return (ACEX)
+ }
+
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+}
diff --git a/arch/x86/include/asm/acpi/cros_ec/als.asl
b/arch/x86/include/asm/acpi/cros_ec/als.asl
new file mode 100644
index 000..f3d40f889c8
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/als.asl
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ */
+
+Device (ALS)
+{
+ Name (_HID, "ACPI0008")
+ Name (_UID, 1)
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0xF)
+ }
+
+ /*
+* Returns the current ambient light illuminance reading in lux
+*
+* 0: Reading is below the range of sensitivity of the sensor
+* -1: Reading is above the range or sensitivity of the sensor
+*/
+ Method (_ALI, 0, NotSerialized)
+ {
+ Return (^^ALS0)
+ }
+
+ /*
+* Returns a recommended polling frequency in tenths of seconds
+*
+* 0: No need to poll, async notifications will indicate changes
+*/
+ Name (_ALP, 10)
+
+ /*
+* Returns a package of packages where each tuple consists of a pair
+* of integers mapping ambient light illuminance to display brightness.
+*
+* {, }
+*
+* Ambient light illuminance values are specified in lux.
+*
+* Display luminance adjustment values are relative percentages where
+* 100 is no (0%) display brightness adjustment. Values <100 indicate
+* negative adjustment (dimming) and values >100 indicate positive
+* adjustment (brightening).
+*
+* This is currently unused by the Linux kernel ACPI ALS driver but
+* is required by the ACPI specification so just define a basic two
+* point response curve.
+*/
+ Name (_ALR, Package ()
+ {
+ Package () { 70, 30 },// Min { -30% adjust at 30 lux }
+ Package () { 150, 1000 } // Max { +50% adjust at 1000 lux }
+ })
+}
diff --git a/arch/x86/include/asm/acpi/cros_ec/battery.asl
b/arch/x86/include/asm/acpi/cros_ec/battery.asl
new file mode 100644
index 000..f106088231e
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/battery.asl
@@ -0,0 +1,411 @@
+/*/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ */
+
+// Scope (EC0)
+
+/* Mutex for EC battery index interface */
+Mutex (BATM, 0)
+
+// Wait for desired battery index to be presented in shared memory
+// Arg0 = battery index
+// Returns Zero on success, One on error.
+Method (BTSW, 1)
+{
+#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE
+ If (LEqual (BTIX, Arg0)) {
+ Return (Zero)
+ }
+ If (LGreaterEqual (Arg0, BTCN)) {
+ Return (One)
+ }
+ Store (Arg0, \_SB.PCI0.LPCB.EC0.BTID)
+ Store (5, Local0) // Timeout 5 msec
+ While (LNotEqual (BTIX, Arg0))
+ {
+ Sleep (1)
+ Decrement (Local0)
+ If
[PATCH v1 06/54] x86: Add a config for the systemagent PCIEX regions size
Add a way to specify the required size for this region. This is used when generating ACPI tables. Signed-off-by: Simon Glass --- arch/x86/Kconfig| 18 ++ arch/x86/cpu/apollolake/Kconfig | 1 + 2 files changed, 19 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index ff4f06ed79c..e90d1171f19 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -964,4 +964,22 @@ config TPL_ACPI_GPE See https://queue.acm.org/blogposting.cfm?id=18977 for more info +config SA_PCIEX_LENGTH + hex + default 0x1000 if (PCIEX_LENGTH_256MB) + default 0x800 if (PCIEX_LENGTH_128MB) + default 0x400 if (PCIEX_LENGTH_64MB) + default 0x1000 + help + This option allows you to select length of PCIEX region. + +config PCIEX_LENGTH_256MB + bool + +config PCIEX_LENGTH_128MB + bool + +config PCIEX_LENGTH_64MB + bool + endmenu diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index 99d4e105c25..37d6289ee41 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -13,6 +13,7 @@ config INTEL_APOLLOLAKE select TPL_X86_TSC_TIMER_NATIVE select SPL_PCH_SUPPORT select TPL_PCH_SUPPORT + select PCIEX_LENGTH_256MB select PCH_SUPPORT select P2SB select SMP_AP_WORK -- 2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 04/54] x86: acpi: Add DPTF asl files
Add common DPTF (Intel Dynamic Performance and Thermal Framework) files,
taken from coreboot.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/acpi/dptf/charger.asl | 65 +++
arch/x86/include/asm/acpi/dptf/cpu.asl | 186
arch/x86/include/asm/acpi/dptf/dptf.asl| 121 +
arch/x86/include/asm/acpi/dptf/fan.asl | 57 +++
arch/x86/include/asm/acpi/dptf/thermal.asl | 521 +
5 files changed, 950 insertions(+)
create mode 100644 arch/x86/include/asm/acpi/dptf/charger.asl
create mode 100644 arch/x86/include/asm/acpi/dptf/cpu.asl
create mode 100644 arch/x86/include/asm/acpi/dptf/dptf.asl
create mode 100644 arch/x86/include/asm/acpi/dptf/fan.asl
create mode 100644 arch/x86/include/asm/acpi/dptf/thermal.asl
diff --git a/arch/x86/include/asm/acpi/dptf/charger.asl
b/arch/x86/include/asm/acpi/dptf/charger.asl
new file mode 100644
index 000..7f4a7ecd36e
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/charger.asl
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Device (TCHG)
+{
+ Name (_HID, "INT3403")
+ Name (_UID, 0)
+ Name (PTYP, 0x0B)
+ Name (_STR, Unicode("Battery Charger"))
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Return charger performance states defined by mainboard */
+ Method (PPSS)
+ {
+ Return (\_SB.CHPS)
+ }
+
+ /* Return maximum charger current limit */
+ Method (PPPC)
+ {
+ /* Convert size of PPSS table to index */
+ Store (SizeOf (\_SB.CHPS), Local0)
+ Decrement (Local0)
+
+ /* Check if charging is disabled (AC removed) */
+ If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) {
+ /* Return last power state */
+ Return (Local0)
+ } Else {
+ /* Return highest power state */
+ Return (0)
+ }
+
+ Return (0)
+ }
+
+ /* Set charger current limit */
+ Method (SPPC, 1)
+ {
+ /* Retrieve Control (index 4) for specified PPSS level */
+ Store (DeRefOf (Index (DeRefOf (Index
+ (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0)
+
+ /* Pass Control value to EC to limit charging */
+ \_SB.PCI0.LPCB.EC0.CHGS (Local0)
+ }
+
+ /* Initialize charger participant */
+ Method (INIT)
+ {
+ /* Disable charge limit */
+ \_SB.PCI0.LPCB.EC0.CHGD ()
+ }
+}
diff --git a/arch/x86/include/asm/acpi/dptf/cpu.asl
b/arch/x86/include/asm/acpi/dptf/cpu.asl
new file mode 100644
index 000..f77d3538386
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/cpu.asl
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+External (\_PR.CP00._PSS, PkgObj)
+External (\_PR.CP00._TSS, PkgObj)
+External (\_PR.CP00._TPC, MethodObj)
+External (\_PR.CP00._PTC, PkgObj)
+External (\_PR.CP00._TSD, PkgObj)
+External (\_SB.MPDL, IntObj)
+
+Device (DPTF_CPU_DEVICE)
+{
+ Name(_ADR, DPTF_CPU_ADDR)
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /*
+* Processor Throttling Controls
+*/
+
+ Method (_TSS)
+ {
+ If (CondRefOf (\_PR.CP00._TSS)) {
+ Return (\_PR.CP00._TSS)
+ } Else {
+ Return (Package ()
+ {
+ Package () { 0, 0, 0, 0, 0 }
+ })
+ }
+ }
+
+ Method (_TPC)
+ {
+ If (CondRefOf (\_PR.CP00._TPC)) {
+ Return (\_PR.CP00._TPC)
+ } Else {
+ Return (0)
+ }
+ }
+
+ Method (_PTC)
+ {
+ If (CondRefOf (\_PR.CP00._PTC)) {
+ Return (\_PR.CP00._PTC)
+ } Else {
+ Return (Package ()
+ {
+ Buffer () { 0 },
+ Buffer () { 0 }
+ })
+ }
+ }
+
+ Method (_TSD)
+ {
+ If (CondRefOf (\_PR.CP00._TSD)) {
+ Return (\_PR.CP00._TSD)
+ } Else {
+ Return (Package ()
+ {
+ Package () { 5, 0, 0, 0, 0 }
+ })
+ }
+
[PATCH v1 02/54] x86: acpi: Add base asl files for common x86 devices
Add common x86 ASL files, taken from coreboot.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/acpi/chromeos.asl| 108 +
arch/x86/include/asm/acpi/cpu.asl | 25
arch/x86/include/asm/acpi/cros_gnvs.asl | 29 +
arch/x86/include/asm/acpi/lpc.asl | 141 ++
arch/x86/include/asm/acpi/pci_osc.asl | 21
arch/x86/include/asm/acpi/pcr.asl | 80
arch/x86/include/asm/acpi/ramoops.asl | 32 +
arch/x86/include/asm/acpi/sleepstates.asl | 12 +-
8 files changed, 443 insertions(+), 5 deletions(-)
create mode 100644 arch/x86/include/asm/acpi/chromeos.asl
create mode 100644 arch/x86/include/asm/acpi/cpu.asl
create mode 100644 arch/x86/include/asm/acpi/cros_gnvs.asl
create mode 100644 arch/x86/include/asm/acpi/lpc.asl
create mode 100644 arch/x86/include/asm/acpi/pci_osc.asl
create mode 100644 arch/x86/include/asm/acpi/pcr.asl
create mode 100644 arch/x86/include/asm/acpi/ramoops.asl
diff --git a/arch/x86/include/asm/acpi/chromeos.asl
b/arch/x86/include/asm/acpi/chromeos.asl
new file mode 100644
index 000..2a0fd33265d
--- /dev/null
+++ b/arch/x86/include/asm/acpi/chromeos.asl
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ */
+
+#ifdef CONFIG_CHROMEOS
+
+#define CONFIG_VBOOT_VBNV_OFFSET 0x26
+
+#include
+
+/* GPIO package generated at run time. */
+External (OIPG)
+
+Device (CRHW)
+{
+ Name(_HID, EISAID("GGL0001"))
+
+ Method(_STA, 0, Serialized)
+ {
+ Return (0xb)
+ }
+
+ Method(CHSW, 0, Serialized)
+ {
+ Name (WSHC, Package() { VBT3 })
+ Return (WSHC)
+ }
+
+ Method(FWID, 0, Serialized)
+ {
+ Name (DIW1, "")
+ ToString(VBT5, 63, DIW1)
+ Name (DIWF, Package() { DIW1 })
+ Return(DIWF)
+ }
+
+ Method(FRID, 0, Serialized)
+ {
+ Name (DIR1, "")
+ ToString(VBT6, 63, DIR1)
+ Name (DIRF, Package() { DIR1 })
+ Return (DIRF)
+ }
+
+ Method(HWID, 0, Serialized)
+ {
+ Name (DIW0, "")
+ ToString(VBT4, 255, DIW0)
+ Name (DIWH, Package() { DIW0 })
+ Return (DIWH)
+ }
+
+ Method(BINF, 0, Serialized)
+ {
+ Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
+ Return (FNIB)
+ }
+
+ Method(GPIO, 0, Serialized)
+ {
+ Return (OIPG)
+
+ }
+
+ Method(VBNV, 0, Serialized)
+ {
+ Name(VNBV, Package() {
+ // See src/vendorcode/google/chromeos/Kconfig
+ // for the definition of these:
+ CONFIG_VBOOT_VBNV_OFFSET,
+ VBOOT_VBNV_BLOCK_SIZE
+ })
+ Return(VNBV)
+ }
+
+ Method(VDAT, 0, Serialized)
+ {
+ Name(TAD0,"")
+ ToBuffer(CHVD, TAD0)
+ Name (TADV, Package() { TAD0 })
+ Return (TADV)
+ }
+
+ Method(FMAP, 0, Serialized)
+ {
+ Name(PAMF, Package() { VBT9 })
+ Return(PAMF)
+ }
+
+ Method(MECK, 0, Serialized)
+ {
+ Name(HASH, Package() { MEHH })
+ Return(HASH)
+ }
+
+ Method(MLST, 0, Serialized)
+ {
+ Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
+ "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
+ })
+ Return (TSLM)
+ }
+}
+
+#include "ramoops.asl"
+
+#endif
diff --git a/arch/x86/include/asm/acpi/cpu.asl
b/arch/x86/include/asm/acpi/cpu.asl
new file mode 100644
index 000..b20b3572f2b
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cpu.asl
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+/* These come from the dynamically created CPU SSDT */
+External (\_PR.CNOT, MethodObj)
+
+/* Notify OS to re-read CPU tables */
+Method (PNOT)
+{
+ \_PR.CNOT (0x81)
+}
+
+/* Notify OS to re-read CPU _PPC limit */
+Method (PPCN)
+{
+ \_PR.CNOT (0x80)
+}
+
+/* Notify OS to re-read Throttle Limit tables */
+Method (TNOT)
+{
+ \_PR.CNOT (0x82)
+}
diff --git a/arch/x86/include/asm/acpi/cros_gnvs.asl
b/arch/x86/include/asm/acpi/cros_gnvs.asl
new file mode 100644
index 000..c20b64565e0
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_gnvs.asl
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+/* This is the ChromeOS specific ACPI information needed by
+ * the mainboard's chromeos.asl
+ */
+
+VBT0, 32,// 0x000 - Boot Reason
+VBT1, 32,// 0x004 - Active Main Firmware
+VBT2, 32,// 0x008 - Active EC Firmware
+VBT3, 16,// 0x00c - CHSW
[PATCH v1 05/54] x86: apl: Correct PCIE_ECAM_BASE
This value is incorrect and causes problems booting Linux. Fix it. Signed-off-by: Simon Glass --- board/google/chromebook_coral/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/google/chromebook_coral/Kconfig b/board/google/chromebook_coral/Kconfig index 940bee89b0b..f744b4c00cb 100644 --- a/board/google/chromebook_coral/Kconfig +++ b/board/google/chromebook_coral/Kconfig @@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_16384 config PCIE_ECAM_BASE - default 0xf000 + default 0xe000 config EARLY_POST_CROS_EC bool "Enable early post to Chrome OS EC" -- 2.28.0.rc0.142.g3c755180ce-goog
[PATCH v1 00/54] dm: Add programatic generation of ACPI tables (part D)
Note: This is part D of this effort. With this, Coral includes all required ACPI tables. At present on x86 U-Boot supports creating ACPI (Advanced Configuration and Power Interface) tables using the Intel ACPI Source Language (ASL) compiler. This is good enough for basic operation but some devices need to add their information dynamically at runtime. An example is a device that needs to report its enable GPIO. This is described in the device tree, so we want to add code in the driver to convert that device-tree description into an ACPI description for use on Linux. This series adds support for generation of ACPI tables and fragments by devices. The core support is built into driver model. Several files are brought over from coreboot to do the actual generation. As an example of using this new feature, chromebook_coral is updated to write out a wide array of ACPI tables including DSDT and SSDT. This initial version of the series lays out the general approach. More work is needed to figure out the difference between CONFIG_ACPIGEN and CONFIG_GENERATE_ACPI_TABLE with respect to what is built. Changes in v1: - Add NHLT audio support - Add NHLT information - Add comments - Add more comments and rename cpu_get_bus_clock to cpu_get_bus_clock_khz() - Add new patch with coral audio descriptor files - Add support for NHLT table - Adjust implementation to match new ACPI GPIO generation - Capitalise ACPI_OPS_PTR - Don't build for SPL - Drop unnecessary callbacks - Fix i2c PCI addresses - Handle table generation without callbacks - Move ASL_REVISION define into this patch - Move acpi_create_dbg2() into generic code - Move the acpi.h header file to this commit - Move this code into an x86-specific file - Put this code in an x86-specific place and update commit message - Rename acpi-probed to linux,probed - Rename cpi,hid-desc-reg-offset to hid-desc-addr - Split PCT and PTC tables into a separate patch - Support hid-over-i2c separately as well - UIse hid-over-i2 compatible string - Update ACPI ordering to include multiple CPUs - Update commit message - Update commit message with a comma - Update for acpi_device_write_i2c_dev() return-value change - Use OEM_TABLE_ID instead of ACPI_TABLE_CREATOR - Use SHIFT and MASK for defines - Use acpi,ddn instead of acpi,desc - Use this file in APL - Use updated acpi_device_write_dsm_i2c_hid() function Simon Glass (54): x86: acpi: Add cros_ec tables x86: acpi: Add base asl files for common x86 devices x86: acpi: apl: Add asl files for Apollo Lake x86: acpi: Add DPTF asl files x86: apl: Correct PCIE_ECAM_BASE x86: Add a config for the systemagent PCIEX regions size x86: Add a common global NVS structure x86: acpi: Support external GNVS tables x86: acpi: Expand the GNVS x86: coral: Add ACPI tables for coral acpi: Add support for writing a _PRW acpi: Add support for conditions and return values acpi: Support generating a multi-function _DSM for devices i2c: Add a generic driver to generate ACPI info x86: Add wake sources for the acpi_gpe driver x86: apl: Support writing the IntelGraphicsMem table x86: acpi: Add a common routine to write WiFi info x86: Add some definitions for SMM x86: apl: Add power-management definitions x86: apl: Update iomap for ACPI x86: Add a few common Intel CPU functions x86: acpi: Support generation of the HPET table x86: acpi: Support generation of the DBG2 table acpi: Add support for generating processor tables x86: acpi: Add PCT and PTC tables acpi: Add more support for generating processor tables x86: acpi: Add common Intel ACPI tables x86: Support Atom SoCs using SWSMISCI rather than the SWSCI x86: acpi: Add support for additional Intel tables x86: apl: Allow reading hostbridge base addresses p2sb: Add some definitions used for ACPI x86: apl: Generate required ACPI tables x86: apl: Add support for hostbridge ACPI generation x86: apl: Generate CPU tables x86: apl: Generate ACPI table for LPC x86: apl: Drop unnecessary code in PMC driver tpm: cr50: Add ACPI support x86: fsp: Update the FSP API with the end-firmware method x86: cpu: Report address width from cpu_get_info() x86: Sort the MTRR table x86: Notify the FSP of the 'end firmware' event x86: Correct the assembly guard in e820.h x86: Add a header guard to asm/acpi_table.h x86: Correct handling of MADT table CPUs acpi: tpm: Add a TPM2 table acpi: tpm: Add a TPM1 table x86: acpi: Set the log category for x86 table generation x86: coral: Add audio descriptor files x86: apl: Check low-level init in FSP-S pre-init x86: fsp: Add more debugging for silicon init x86: fsp: Show FSP-S or FSP-M address in fsp_get_header() acpi: Use defines for field lengths x86: Add a way to add to the e820 memory table x86: coral: Update config and device tree for ACPI arch/x86/Kconfig | 47 ++ arch/x86/cpu/apollolake/Kconfig | 4 + arch/x86/cpu/apollolake/Makefile
Re: [RFC PATCH v2 0/3] RFC: tiny-dm: Proposal for using driver model in SPL
Hi Simon, On 10/7/20 01:12, Walter Lozano wrote: Hi Simon, On 2/7/20 18:10, Simon Glass wrote: This series provides a proposed enhancement to driver model to reduce overhead in SPL. These patches should not be reviewed other than to comment on the approach. The code is all lumped together in a few patches and so cannot be applied as is. For now, the source tree is available at: https://gitlab.denx.de/u-boot/custodians/u-boot-dm/-/tree/dtoc-working Comments welcome! Benefits (good news) As an example of the impact of tiny-dm, chromebook_jerry is converted to use it. This shows approximately a 30% reduction in code and data size and a 85% reduction in malloc() space over of-platdata:    text  data   bss   dec   hex   filename   25248  1836 12 27096  69d8 spl/u-boot-spl (original with DT)   19727  3436 12 23175  5a87 spl/u-boot-spl (OF_PLATDATA) 78%   187%   100% 86% as %age of original   13784  1408 12 15204  3b64 spl/u-boot-spl (SPL_TINY) 70% 41%   100% 66% as %age of platdata 55% 77%   100% 56% as %age of original SPL malloc() usage drops from 944 bytes (OF_PLATDATA) to 116 (SPL_TINY). Overall the 'overhead' of tiny-dm is much less than the full driver model. Code size is currently about 600 bytes for these functions on Thumb2:    0054 T tiny_dev_probe    0034 T tiny_dev_get_by_drvdata    0024 T tiny_dev_find    001a T tiny_dev_get    003c T tinydev_alloc_data    002a t tinydev_lookup_data    0022 T tinydev_ensure_data    0014 T tinydev_get_data    0004 T tinydev_get_parent Effort (bad news) - Unfortunately it is quite a bit of work to convert drivers over to tiny-dm. First, the of-platdata conversion must be done. But on top of that, tiny-dm needs entirely separate code for dealing with devices. This means that instead of 'struct udevice' and 'struct uclass' there is just 'struct tinydev'. Each driver and uclass must be modified to support both, pulling common code into internal static functions. Another option -- Note: It is assumed that any board that is space-contrained should use of-platdata in SPL (see doc/driver-model/of-plat.rst). This is shown to reduce device-tree overhead by approximately 4KB. Designing tiny-dm has suggested a number of things that could be changed in the current driver model to make it more space-efficient for TPL and SPL. The ones with least impact on driver code are (CS=reduces code size, DS=reduces data size):    CS - drop driver_bind() and create devices (struct udevice) at build-time    CS - allocate all device- and uclass-private data at build-time    CS - remove all but the basic operations for each uclass (e.g. SPI flash only supports reading)    DS - use 8-bit indexes instead of 32/64-bit pointers for device pointers possible since these are created at build-time)    DS - use singly-linked lists    DS - use 16-bit offsets to private data, instead of 32/64-bit pointers (possible since it is all in SRAM relative to malloc() base, presumably word-aligned and < 256KB)    DS - move private pointers into a separate data structure so that NULLs are not stored    CS / DS - Combine req_seq and seq and calculate the new value at build-time More difficult are:    DS - drop some of the lesser-used driver and uclass methods    DS - drop all uclass methods except init()    DS - drop all driver methods except probe()    CS / DS - drop uclasses and require drivers to manually call uclass functions Even with all of this we would not reach tiny-dm and it would muddy up the driver-model datas structures. But we might come close to tiny-dm on size and there are some advantages: - much of the benefit would apply to all boards that use of-platdata (i.e.   with very little effort on behalf of board maintainers) - the impact on the code base is much less (we keep a single, unified   driver mode in SPL and U-Boot proper) Overall I think it is worth looking at this option. While it doesn't have the 'nuclear' impact of tiny-dm, neither does it mess with the U-Boot driver code as much and it is easier to learn. Thanks for your hard work on this topic. I think that there is great value in this research and in this conclusion. It is clear that there two different approaches, but I feel that the improvement to the current DM implementation would have a higher impact in the community. Since the first version of this proposal I have been thinking in a solution that takes some of the advantages of tiny-dm idea but that does not require so much effort. This seems to be aligned with what you have been explaining in this section. I found interesting your proposal about simplification some data structures. In
Please pull u-boot-dm (take 2)
Hi Tom, I think I figured out what was wrong with the test. It seems to depend on the number of CPUs used to run them. I got a passing run here: https://travis-ci.org/github/sjg20/u-boot/builds/711807208 The following changes since commit ada61f1ee2a4eaa1b29d699b5ba940483171df8a: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv (2020-07-24 08:43:08 -0400) are available in the Git repository at: git://git.denx.de/u-boot-dm.git tags/dm-pull-20jul20-take2a for you to fetch changes up to 347e0f00e850028b4595287d5158c5a8f36ba910: binman: Re-enable concurrent tests (2020-07-26 19:59:57 -0600) binman support for FIT new UCLASS_SOC patman switch 'test' command minor fdt fixes patman usability improvements Dave Gerlach (9): doc: Add new doc for soc ID driver model dm: soc: Introduce UCLASS_SOC for SOC ID and attribute matching test: Add tests for SOC uclass dm: soc: Introduce soc_ti_k3 driver for TI K3 SoCs arm: dts: k3-am65-wakeup: Introduce chipid node arm: dts: k3-j721e-mcu-wakeup: Introduce chipid node configs: am65x_evm: Enable CONFIG_SOC_DEVICE and CONFIG_SOC_DEVICE_TI_K3 configs: j721e_evm: Enable CONFIG_SOC_DEVICE and CONFIG_SOC_DEVICE_TI_K3 arm: mach-k3: Use SOC driver for device identification Heinrich Schuchardt (1): test/dm: check if devices exist Masahiro Yamada (6): fdt_support: add static to fdt_node_set_part_info() fdt_support: call mtdparts_init() after finding MTD node to fix up fdt_support: skip MTD node with "disabled" in fdt_fixup_mtdparts() treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr() treewide: remove (phys_addr_t) casts from devfdt_get_addr() treewide: convert devfdt_get_addr() to dev_read_addr() Michal Simek (3): ARM: rmobile: Switch back to fdtdec_setup_memory/banksize_fdt() Revert "lib: fdt: Split fdtdec_setup_memory_banksize()" Revert "lib: fdt: Split fdtdec_setup_mem_size_base()" Nicolas Boichat (2): patman: Make sure sendemail.suppresscc is (un)set correctly patman: When no tracking branch is provided, tell the user Patrick Delaunay (2): patman: Detect unexpected END Add information for skipped commit options Philippe Reynes (1): lib: libfdt: fdt_region: avoid NULL pointer access Simon Glass (35): patman: Use test_util to show test results patman: Move main code out to a control module patman: Add a test that uses gitpython patman: Allow creating patches for another branch patman: Allow skipping patches at the end patman: Convert to ArgumentParser patman: Allow different commands patman: Add a 'test' subcommand patman: Allow disabling 'bright' mode with Print output patman: Support collecting response tags in Patchstream patman: Add a -D option to enable debugging dm: core Fix long line in device_bind_common() .gitignore: Ignore Python 3 cache directories binman: Output errors to stderr binman: cbfs: Fix IFWI typo binman: Correct the search patch for pylibfdt binman: Specify the toolpath when running test coverage binman: Set a default toolpath binman: Add support for calling mkimage binman: Fix a few typos in the entry docs binman: Adjust pylibfdt for incremental build binman: Use super() instead of specifying parent type binman: Add an etype for external binary blobs binman: Convert existing binary blobs to blob_ext binman: Allow external binaries to be missing patman: Update errors and warnings to use stderr binman: Detect when valid images are not produced binman: Allow missing Intel blobs binman: Allow zero-length entries to overlap mkimage: Allow updating the FIT timestamp dtoc: Allow adding variable-sized data to a dtb binman: Add support for generating a FIT cpu: Convert the methods to use a const udevice * binman: Don't change the descriptor in tests binman: Re-enable concurrent tests .azure-pipelines.yml | 2 +- .gitignore| 3 + .gitlab-ci.yml| 2 +- .travis.yml | 2 +- arch/arm/dts/k3-am65-wakeup.dtsi | 5 + arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 4 + arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 4 + arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 5 + arch/arm/mach-k3/common.c | 48 +++--- arch/arm/mach-k3/common.h | 6 - arch/arm/mach-k3/include/mach/hardware.h | 1 - arch/arm/mach-snapdragon/clock-snapdragon.c | 2 +-
[PATCH] log: Allow LOG_DEBUG to always enable log output
At present if CONFIG_LOG enabled, putting LOG_DEBUG at the top of a file
(before log.h inclusion) causes _log() to be executed for every log()
call, regardless of the build- or run-time logging level.
However there is no guarantee that the log record will actually be
displayed. If the current log level is lower than LOGL_DEBUG then it will
not be.
Add a way to signal that the log record should always be displayed and
update log_passes_filters() to handle this.
Signed-off-by: Simon Glass
---
common/log.c | 11 ---
doc/README.log | 10 --
include/log.h | 16
test/log/syslog_test.c | 2 +-
4 files changed, 25 insertions(+), 14 deletions(-)
diff --git a/common/log.c b/common/log.c
index 734d26de4a..5ff8245922 100644
--- a/common/log.c
+++ b/common/log.c
@@ -156,16 +156,20 @@ static bool log_has_file(const char *file_list, const
char *file)
static bool log_passes_filters(struct log_device *ldev, struct log_rec *rec)
{
struct log_filter *filt;
+ int level = rec->level & LOGL_LEVEL_MASK;
+
+ if (rec->force_debug && level <= LOGL_DEBUG)
+ return true;
/* If there are no filters, filter on the default log level */
if (list_empty(>filter_head)) {
- if (rec->level > gd->default_log_level)
+ if (level > gd->default_log_level)
return false;
return true;
}
list_for_each_entry(filt, >filter_head, sibling_node) {
- if (rec->level > filt->max_level)
+ if (level > filt->max_level)
continue;
if ((filt->flags & LOGFF_HAS_CAT) &&
!log_has_cat(filt->cat_list, rec->cat))
@@ -208,7 +212,8 @@ int _log(enum log_category_t cat, enum log_level_t level,
const char *file,
va_list args;
rec.cat = cat;
- rec.level = level;
+ rec.level = level & LOGL_LEVEL_MASK;
+ rec.force_debug = level & LOGL_FORCE_DEBUG;
rec.file = file;
rec.line = line;
rec.func = func;
diff --git a/doc/README.log b/doc/README.log
index ba838824a9..554e99ca4c 100644
--- a/doc/README.log
+++ b/doc/README.log
@@ -77,12 +77,10 @@ Sometimes it is useful to turn on logging just in one file.
You can use this:
#define LOG_DEBUG
-to enable building in of all logging statements in a single file. Put it at
-the top of the file, before any #includes.
-
-To actually get U-Boot to output this you need to also set the default logging
-level - e.g. set CONFIG_LOG_DEFAULT_LEVEL to 7 (LOGL_DEBUG) or more. Otherwise
-debug output is suppressed and will not be generated.
+to enable building in of all debug logging statements in a single file. Put it
+at the top of the file, before any #includes. This overrides any log-level
+setting in U-Boot, including CONFIG_LOG_DEFAULT_LEVEL, but just for that file.
+All logging statements, up to and including LOGL_DEBUG, will be displayed.
Convenience functions
diff --git a/include/log.h b/include/log.h
index 2859ce1f2e..63052f74eb 100644
--- a/include/log.h
+++ b/include/log.h
@@ -33,6 +33,9 @@ enum log_level_t {
LOGL_COUNT,
LOGL_NONE,
+ LOGL_LEVEL_MASK = 0xf, /* Mask for valid log levels */
+ LOGL_FORCE_DEBUG = 0x10, /* Mask to force output due to LOG_DEBUG */
+
LOGL_FIRST = LOGL_EMERG,
LOGL_MAX = LOGL_DEBUG_IO,
};
@@ -133,7 +136,7 @@ static inline int _log_nop(enum log_category_t cat, enum
log_level_t level,
#if CONFIG_IS_ENABLED(LOG)
#ifdef LOG_DEBUG
-#define _LOG_DEBUG 1
+#define _LOG_DEBUG LOGL_FORCE_DEBUG
#else
#define _LOG_DEBUG 0
#endif
@@ -141,9 +144,9 @@ static inline int _log_nop(enum log_category_t cat, enum
log_level_t level,
/* Emit a log record if the level is less that the maximum */
#define log(_cat, _level, _fmt, _args...) ({ \
int _l = _level; \
- if (CONFIG_IS_ENABLED(LOG) && (_l <= _LOG_MAX_LEVEL || _LOG_DEBUG)) \
- _log((enum log_category_t)(_cat), _l, __FILE__, __LINE__, \
- __func__, \
+ if (CONFIG_IS_ENABLED(LOG) && (_LOG_DEBUG || _l <= _LOG_MAX_LEVEL)) \
+ _log((enum log_category_t)(_cat), _l | _LOG_DEBUG, __FILE__, \
+__LINE__, __func__, \
pr_fmt(_fmt), ##_args); \
})
#else
@@ -279,8 +282,12 @@ void __assert_fail(const char *assertion, const char
*file, unsigned int line,
* Memebers marked as 'allocated' are allocated (e.g. via strdup()) by the log
* system.
*
+ * TODO(s...@chromium.org): Compress this struct down a bit to reduce space,
e.g.
+ * a single u32 for cat, level, line and force_debug
+ *
* @cat: Category, representing a uclass or part of U-Boot
* @level: Severity level, less severe is higher
+ * @force_debug: Force output of debug
* @file: Name of file where the log record was generated (not allocated)
* @line: Line number where the log record
[PATCH] Add an assembly guard around linux/bitops.h
This file can be included by any header but it include C code. Guard it to avoid errors when compiling ASL, etc. Signed-off-by: Simon Glass --- include/linux/bitops.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 6b509dce58..16f28993f5 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -1,7 +1,7 @@ #ifndef _LINUX_BITOPS_H #define _LINUX_BITOPS_H -#ifndef USE_HOSTCC +#if !defined(USE_HOSTCC) && !defined(__ASSEMBLY__) #include #include @@ -218,6 +218,6 @@ static inline void generic_clear_bit(int nr, volatile unsigned long *addr) *p &= ~mask; } -#endif /* !USE_HOSTCC */ +#endif /* !USE_HOSTCC && !__ASSEMBLY__ */ #endif -- 2.28.0.rc0.142.g3c755180ce-goog
Re: [RFC 3/4] dtoc: add support for generate stuct udevice_id
Hi Simon,
On 26/7/20 11:53, Simon Glass wrote:
Hi Walter,
On Tue, 7 Jul 2020 at 08:08, Walter Lozano wrote:
Hi Simon
On 6/7/20 16:21, Simon Glass wrote:
Hi Walter,
On Fri, 19 Jun 2020 at 15:12, Walter Lozano wrote:
Based on several reports there is an increasing concern in the impact
of adding additional features to drivers based on compatible strings.
A good example of this situation is found in [1].
In order to reduce this impact and as an initial step for further
reduction, propose a new way to declare compatible strings, which allows
to only include the useful ones.
What are the useful ones?
The useful ones would be those that are used by the selected DTB by the
current configuration. The idea of this patch is to declare all the
possible compatible strings in a way that dtoc can generate code for
only those which are going to be used, and in this way avoid lots of
#ifdef like the ones shows in
http://patchwork.ozlabs.org/project/uboot/patch/20200525202429.2146-1-ag...@denx.de/
The idea is to define compatible strings in a way to be easily parsed by
dtoc, which will be responsible to build struct udevice_id [] based on
the compatible strings present in the dtb.
Additional features can be easily added, such as define constants
depending on the presence of compatible strings, which allows to enable
code blocks only in such cases without the need of adding additional
configuration options.
[1]
http://patchwork.ozlabs.org/project/uboot/patch/20200525202429.2146-1-ag...@denx.de/
Signed-off-by: Walter Lozano
---
tools/dtoc/dtb_platdata.py | 32
1 file changed, 32 insertions(+)
I think dtoc should be able to parse the compatible strings as they
are today - e.g. see the tiny-dm stuff.
Yes, I agree. My idea is that dtoc parses compatible strings as they are
today but also in this new way. The reason for this is to allow dtoc to
generate the code to include the useful compatible strings. Of course,
this only makes sense if the idea of generating the compatible string
associated code is accepted.
What do you think?
I think this is useful and better than using #ifdef in the source code
for this sort of thing. We need a way to specify the driver_data value
as well, right?
Yes, I agree, it is better than #ifdef and c/ould give us some extra
functionality.
What doe you mean by driver_data value? Are you referring to the data
field? like
static struct esdhc_soc_data usdhc_imx7d_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
| ESDHC_FLAG_HS400,
};
If that is the case, I was thinking in defining a constant when specific
compatible strings are enabled by dtoc, based in the above case
#ifdef FSL_ESDHC_IMX_V2
static struct esdhc_soc_data usdhc_imx7d_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
| ESDHC_FLAG_HS400,
};
#endif
COMPATIBLE(FSL_ESDHC, "fsl,imx7d-usdhc", _imx7d_data, FSL_ESDHC_IMX_V2)
So when dtoc parses COMPATIBLE and determines that compatible
"fsl,imx7d-usdhc" should be added it also defines FSL_ESDHC_IMX_V2.
This is alsoAs I comment you in the tread about tiny-dm I think that we
can save some space following your suggestions, and for instance implement
Re naming, perhaps DT_COMPAT() might be better than COMPATIBLE()? Or
even a name that indicates that it is optional, like DT_OPT_COMPAT() ?
I totally agree, naming is very important, and DT_COMPAT() is much better.
What I don't fully understand is what are the cases for DT_OPT_COMPAT(),
could you please clarify?
Regards,
Walter
Re: [PATCH] binman: Don't change the descriptor in tests
On Sat, 25 Jul 2020 at 15:24, Simon Glass wrote: > > At present testPackX86RomMeNoDesc removes the contents of the > descriptor.bin file and testPackX86RomMeMissingDesc removes the file > completely. > > If a test that relies on this file happens to run after it is removed, it > will not work. Since we have no control over the selecting of tests that > run in parallel and series, we must avoid changing the files. > > Update this tests to use separate files instead. > > Signed-off-by: Simon Glass > --- > > tools/binman/ftest.py| 8 +++ > tools/binman/test/163_x86_rom_me_empty.dts | 22 > tools/binman/test/164_x86_rom_me_missing.dts | 22 > 3 files changed, 47 insertions(+), 5 deletions(-) > create mode 100644 tools/binman/test/163_x86_rom_me_empty.dts > create mode 100644 tools/binman/test/164_x86_rom_me_missing.dts Applied to u-boot-dm.
RE: [PATCH] xilinx: Fix xlnx,mio_bank property
> Subject: [PATCH] xilinx: Fix xlnx,mio_bank property
>
> s/xlnx,mio_bank/xlnx,mio-bank/g
>
> DT binding is describing mio-bank not mio_bank that's why fix all DTSes and
> also driver itself.
>
> Signed-off-by: Michal Simek
Acked-by: Peng Fan
> ---
>
> arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts | 2 +-
> arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi | 2 +-
> arch/arm/dts/versal-mini-emmc0.dts| 2
> +-
> arch/arm/dts/versal-mini-emmc1.dts| 2
> +-
> arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2
> +-
> arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2
> +-
> arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 4
> ++--
> arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 4
> ++--
> arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 4
> ++--
> arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 4
> ++--
> arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts | 4 ++--
> arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 4
> ++--
> arch/arm/dts/zynqmp-zcu100-revC.dts | 4
> ++--
> arch/arm/dts/zynqmp-zcu102-revA.dts | 2
> +-
> arch/arm/dts/zynqmp-zcu104-revA.dts | 2
> +-
> arch/arm/dts/zynqmp-zcu104-revC.dts | 2
> +-
> arch/arm/dts/zynqmp-zcu106-revA.dts | 2
> +-
> arch/arm/dts/zynqmp-zcu111-revA.dts | 2
> +-
> arch/arm/dts/zynqmp-zcu1275-revB.dts | 2
> +-
> arch/arm/dts/zynqmp-zcu1285-revA.dts | 2
> +-
> arch/arm/dts/zynqmp-zcu208-revA.dts | 2
> +-
> arch/arm/dts/zynqmp-zcu216-revA.dts | 2
> +-
> drivers/mmc/zynq_sdhci.c |
> 2 +-
> 23 files changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
> b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
> index ac641ff1a582..85ab9e9e29ab 100644
> --- a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
> +++ b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
> @@ -51,7 +51,7 @@
> /* microSD card slot */
> {
> status = "okay";
> - xlnx,mio_bank = <1>;
> + xlnx,mio-bank = <1>;
> clock-frequency = <18000>;
> max-frequency = <5000>;
> no-1-8-v;
> diff --git a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
> b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
> index b635db649f43..cbcb290a5c83 100644
> --- a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
> +++ b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
> @@ -51,6 +51,6 @@
> /* Micron MTFC8GAKAJCN-4M 8 GB eMMC */
> {
> status = "okay";
> - xlnx,mio_bank = <0>;
> + xlnx,mio-bank = <0>;
> clock-frequency = <18000>;
> };
> diff --git a/arch/arm/dts/versal-mini-emmc0.dts
> b/arch/arm/dts/versal-mini-emmc0.dts
> index 7f57d232b7f9..7826a282134b 100644
> --- a/arch/arm/dts/versal-mini-emmc0.dts
> +++ b/arch/arm/dts/versal-mini-emmc0.dts
> @@ -43,7 +43,7 @@
> clocks = < >;
> xlnx,device_id = <0>;
> no-1-8-v;
> - xlnx,mio_bank = <0>;
> + xlnx,mio-bank = <0>;
> #stream-id-cells = <1>;
> };
> };
> diff --git a/arch/arm/dts/versal-mini-emmc1.dts
> b/arch/arm/dts/versal-mini-emmc1.dts
> index 4e0758f61893..2f28f856a6a3 100644
> --- a/arch/arm/dts/versal-mini-emmc1.dts
> +++ b/arch/arm/dts/versal-mini-emmc1.dts
> @@ -43,7 +43,7 @@
> clocks = < >;
> xlnx,device_id = <1>;
> no-1-8-v;
> - xlnx,mio_bank = <0>;
> + xlnx,mio-bank = <0>;
> #stream-id-cells = <1>;
> };
> };
> diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
> b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
> index c260411d7571..a8bbb14f6cd1 100644
> --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
> +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
> @@ -131,7 +131,7 @@
> status = "okay";
> no-1-8-v;
> disable-wp;
> - xlnx,mio_bank = <1>;
> + xlnx,mio-bank = <1>;
> };
>
> {
> diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
> b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
> index 09da60b10072..9468dc574fd8 100644
> --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
> +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
> @@ -70,7 +70,7 @@
> non-removable;
> disable-wp;
> bus-width = <8>;
> - xlnx,mio_bank = <0>;
> + xlnx,mio-bank = <0>;
> };
>
> { /* uart0 MIO38-39 */
> diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
> b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
> index
RE: [PATCH] mmc: zynq: Fix default value for xlnx,mio-bank
> Subject: [PATCH] mmc: zynq: Fix default value for xlnx,mio-bank > > DT binding is saying that default value is 0 not -1 that's why fix it. > > Signed-off-by: Michal Simek > --- > > Depends on > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.d > enx.de%2Fpipermail%2Fu-boot%2F2020-July%2F421231.htmldata=02 > %7C01%7Cpeng.fan%40nxp.com%7C7821c83ee3c44335e47508d82f9fabfb% > 7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6373117101129704 > 44sdata=Lx18aSVId02FV1fD7FxbGe8gL%2F81BNnViUcAQiG9oPY%3D& > amp;reserved=0 > --- > drivers/mmc/zynq_sdhci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index > 6505527616d1..e9381b949307 100644 > --- a/drivers/mmc/zynq_sdhci.c > +++ b/drivers/mmc/zynq_sdhci.c > @@ -276,7 +276,7 @@ static int arasan_sdhci_ofdata_to_platdata(struct > udevice *dev) > return PTR_ERR(priv->host->ioaddr); > > priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1); > - priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", -1); > + priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0); > > return 0; > } > -- Acked-by: Peng Fan > 2.27.0
RE: [PATCH 2/2] configs: migrate CONFIG_SPL_LOAD_FIT_ADDRESS to defconfigs
> Subject: Re: [PATCH 2/2] configs: migrate CONFIG_SPL_LOAD_FIT_ADDRESS
> to defconfigs
>
> Hi Peng,
>
> I assume the purpose of these patches is try to move all the configuration
> into
> one single file, right?
Yes
>
> However with this patch, uboot will fail on AndesCore, and I'm guessing other
> platforms may also have the same problem.
>
> If you could elaborate more on the purpose of the patchset, maybe we could
> come up with a more reasonable fix.
Kconfig is preferred over 'define xx' in header file.
Regards,
peng
>
> Thanks in advance.
> >On Mon, Jul 06, 2020 at 03:35:01PM +0800, peng@nxp.com wrote:
> > From: Peng Fan
> >
> > Done with:
> > ./tools/moveconfig.py -S SPL_LOAD_FIT_ADDRESS ./tools/moveconfig.py -S
> > SPL_LOAD_FIT_ADDRESS -H
> >
> > Signed-off-by: Peng Fan
> > ---
> > configs/am57xx_hs_evm_usb_defconfig
> | 3 ++-
> > configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 1 +
> > configs/dra7xx_evm_defconfig
> | 3 ++-
> > configs/dra7xx_hs_evm_defconfig
> | 1 +
> > configs/dra7xx_hs_evm_usb_defconfig
> | 3 ++-
> > configs/j721e_evm_a72_defconfig
> | 3 ++-
> > configs/j721e_evm_r5_defconfig
> | 3 ++-
> > configs/j721e_hs_evm_a72_defconfig
> | 3 ++-
> > configs/j721e_hs_evm_r5_defconfig
> | 3 ++-
> > configs/xilinx_zynq_virt_defconfig | 1
> +
> > configs/xilinx_zynqmp_virt_defconfig | 1
> +
> > include/configs/am57xx_evm.h
> | 1 -
> > include/configs/ax25-ae350.h
> | 6 --
> > include/configs/dra7xx_evm.h
> | 1 -
> > include/configs/j721e_evm.h
> | 2 --
> > include/configs/qemu-riscv.h |
> 2 --
> > include/configs/sifive-fu540.h | 2
> --
> > include/configs/xilinx_zynqmp.h|
> 3 ---
> > include/configs/zynq-common.h
> | 2 --
> > scripts/config_whitelist.txt | 1
> -
> > 20 files changed, 18 insertions(+), 27 deletions(-)
> >
> > diff --git a/configs/am57xx_hs_evm_usb_defconfig
> > b/configs/am57xx_hs_evm_usb_defconfig
> > index 3b155cc202..2fa60ac517 100644
> > --- a/configs/am57xx_hs_evm_usb_defconfig
> > +++ b/configs/am57xx_hs_evm_usb_defconfig
> > @@ -6,6 +6,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y
> > CONFIG_SYS_MALLOC_F_LEN=0x2000
> > CONFIG_SYS_SPI_U_BOOT_OFFS=0x4
> > CONFIG_DM_GPIO=y
> > +CONFIG_SPL_TEXT_BASE=0x40306D50
> > CONFIG_OMAP54XX=y
> > CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb0
> > CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200
> > @@ -17,10 +18,10 @@ CONFIG_ENV_OFFSET_REDUND=0x28
> > CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y
> > CONFIG_ARMV7_LPAE=y
> > -CONFIG_SPL_TEXT_BASE=0x40306D50
> > CONFIG_DISTRO_DEFAULTS=y
> > CONFIG_FIT_IMAGE_POST_PROCESS=y
> > CONFIG_SPL_LOAD_FIT=y
> > +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8020
> > CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
> > CONFIG_OF_BOARD_SETUP=y
> > CONFIG_USE_BOOTARGS=y
> > diff --git
> > a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
> > b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
> > index 030d28a5df..0ae610be56 100644
> > --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
> > +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
> > @@ -13,6 +13,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y
> > CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y
> > +CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000
> > CONFIG_BOOTDELAY=0
> > # CONFIG_DISPLAY_CPUINFO is not set
> > CONFIG_SPL_OS_BOOT=y
> > diff --git a/configs/dra7xx_evm_defconfig
> > b/configs/dra7xx_evm_defconfig index e4547d9dcc..393020fbd5 100644
> > --- a/configs/dra7xx_evm_defconfig
> > +++ b/configs/dra7xx_evm_defconfig
> > @@ -4,6 +4,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y
> > CONFIG_SYS_MALLOC_F_LEN=0x18000
> > CONFIG_SYS_SPI_U_BOOT_OFFS=0x4
> > CONFIG_DM_GPIO=y
> > +CONFIG_SPL_TEXT_BASE=0x4030
> > CONFIG_OMAP54XX=y
> > CONFIG_TARGET_DRA7XX_EVM=y
> > CONFIG_NR_DRAM_BANKS=2
> > @@ -12,10 +13,10 @@ CONFIG_ENV_OFFSET_REDUND=0x28
> > CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y
> > CONFIG_ARMV7_LPAE=y
> > -CONFIG_SPL_TEXT_BASE=0x4030
> > CONFIG_AHCI=y
> > CONFIG_DISTRO_DEFAULTS=y
> > CONFIG_SPL_LOAD_FIT=y
> > +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8020
> > CONFIG_OF_BOARD_SETUP=y
> > CONFIG_USE_BOOTARGS=y
> > CONFIG_BOOTARGS="androidboot.serialno=${serial#}
> console=ttyS0,115200 androidboot.console=ttyS0
> androidboot.hardware=jacinto6evmboard"
> > diff --git a/configs/dra7xx_hs_evm_defconfig
> > b/configs/dra7xx_hs_evm_defconfig index c08bcce903..ee57b7997a
> 100644
> > --- a/configs/dra7xx_hs_evm_defconfig
> > +++ b/configs/dra7xx_hs_evm_defconfig
> > @@ -20,6 +20,7 @@ CONFIG_AHCI=y
> > CONFIG_DISTRO_DEFAULTS=y
> > CONFIG_FIT_IMAGE_POST_PROCESS=y
> > CONFIG_SPL_LOAD_FIT=y
> > +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8020
> > CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
> > CONFIG_OF_BOARD_SETUP=y
> > CONFIG_USE_BOOTARGS=y
> >
Re: [PATCH] ARM: Samsung: Add support for iTop-4412 based on Samsung Exynos4412
Hi,
Split the patches. And add commit-msg, plz.
Best Regards,
Jaehoon Chung
On 7/25/20 9:05 PM, hyyoxhk wrote:
> Signed-off-by: hyyoxhk
> ---
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/exynos4412-itop-elite.dts | 403 ++
> arch/arm/mach-exynos/Kconfig | 4 +
> board/samsung/itop/Kconfig | 12 +
> board/samsung/itop/MAINTAINERS | 6 +
> board/samsung/itop/Makefile| 6 +
> board/samsung/itop/itop.c | 710 +
> board/samsung/itop/setup.h | 389 ++
> configs/itop_defconfig | 89
> include/configs/itop.h | 177 ++
> 10 files changed, 1798 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/exynos4412-itop-elite.dts
> create mode 100644 board/samsung/itop/Kconfig
> create mode 100644 board/samsung/itop/MAINTAINERS
> create mode 100644 board/samsung/itop/Makefile
> create mode 100644 board/samsung/itop/itop.c
> create mode 100644 board/samsung/itop/setup.h
> create mode 100644 configs/itop_defconfig
> create mode 100644 include/configs/itop.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 5726156a2d..bc70d4c58a 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
> exynos4210-universal_c210.dtb \
> exynos4210-trats.dtb \
> exynos4412-trats2.dtb \
> - exynos4412-odroid.dtb
> + exynos4412-odroid.dtb \
> + exynos4412-itop-elite.dtb
>
> dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb
> dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb
> diff --git a/arch/arm/dts/exynos4412-itop-elite.dts
> b/arch/arm/dts/exynos4412-itop-elite.dts
> new file mode 100644
> index 00..de747ee7b6
> --- /dev/null
> +++ b/arch/arm/dts/exynos4412-itop-elite.dts
> @@ -0,0 +1,403 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * TOPEET's Exynos4412 based itop board device tree source
> + *
> + * Copyright (C) 2020 hey
> + *
> + */
> +
> +/dts-v1/;
> +#include
> +#include "exynos4412.dtsi"
> +
> +/ {
> + model = "TOPEET iTop 4412 Elite board based on Exynos4412";
> + compatible = "topeet,itop4412-elite", "samsung,exynos4412";
> +
> + aliases {
> + serial0 = "/serial@1382";
> + console = "/serial@1382";
> + mmc0 = _0;
> + mmc1 =
> + };
> +
> + chosen {
> + stdout-path = "serial2:115200n8";
> + };
> +
> + memory@4000 {
> + device_type = "memory";
> + reg = <0x4000 0x4000>;
> + };
> +
> + serial@1382 {
> + status = "okay";
> + };
> +
> + ehci@1258 {
> + compatible = "samsung,exynos-ehci";
> + reg = <0x1258 0x100>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + /* In order to reset USB ethernet */
> + samsung,vbus-gpio = < 1 0>;
> +
> + phy {
> + compatible = "samsung,exynos-usb-phy";
> + reg = <0x125B 0x100>;
> + };
> + };
> +
> + emmc-reset {
> + compatible = "samsung,emmc-reset";
> + reset-gpio = < 2 0>;
> + };
> +};
> +
> +_1 {
> + samsung,i2c-sda-delay = <100>;
> + samsung,i2c-slave-addr = <0x10>;
> + samsung,i2c-max-bus-freq = <10>;
> + status = "okay";
> +
> + s5m8767-pmic@66 {
> + compatible = "samsung,s5m8767-pmic";
> + reg = <0x66>;
> + wakeup-source;
> +
> + s5m8767,pmic-buck-default-dvs-idx = <3>;
> +
> + s5m8767,pmic-buck-dvs-gpios = < 5 GPIO_ACTIVE_HIGH>,
> + < 6 GPIO_ACTIVE_HIGH>,
> + < 7 GPIO_ACTIVE_HIGH>;
> +
> + s5m8767,pmic-buck-ds-gpios = < 5 GPIO_ACTIVE_HIGH>,
> + < 6 GPIO_ACTIVE_HIGH>,
> + < 7 GPIO_ACTIVE_HIGH>;
> +
> + /* VDD_ARM */
> + s5m8767,pmic-buck2-dvs-voltage = <135>, <130>,
> + <125>, <120>,
> + <115>, <110>,
> + <100>, <95>;
> +
> + /* VDD_INT */
> + s5m8767,pmic-buck3-dvs-voltage = <110>, <110>,
> + <110>, <110>,
> + <100>, <100>,
> + <100>, <100>;
> +
> + /* VDD_G3D */
> + s5m8767,pmic-buck4-dvs-voltage = <120>, <120>,
> + <120>, <120>,
> +
Re: [PATCH v3 05/14] env: nowhere: add .load ops
On Thu, Jun 25, 2020 at 09:59:49AM +0200, Patrick Delaunay wrote:
> Add the ops .load for nowhere ENV backend to load the
> default environment.
>
> This ops is needed for the command 'env load'
>
>
>
> Signed-off-by: Patrick Delaunay
> Reviewed-by: Tom Rini
> ---
>
> Changes in v3:
> - new: add ?load ops in nowhere
>
> env/nowhere.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/env/nowhere.c b/env/nowhere.c
> index f5b0a17652..6949810a1f 100644
> --- a/env/nowhere.c
> +++ b/env/nowhere.c
> @@ -27,8 +27,17 @@ static int env_nowhere_init(void)
> return 0;
> }
>
> +static int env_nowhere_load(void)
> +{
> + env_set_default(NULL, 0);
> + gd->env_valid = ENV_INVALID;
> +
> + return 0;
> +}
> +
> U_BOOT_ENV_LOCATION(nowhere) = {
> .location = ENVL_NOWHERE,
> .init = env_nowhere_init,
> + .load = env_nowhere_load,
> ENV_NAME("nowhere")
> };
Build testing this, we get 8KiB size increase in SPL in targets which
have ENV_NOWHERE in SPL. Can we guard this somehow, with a logical
tie-in to being needed for 'env load' ? Thanks!
--
Tom
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Description: PGP signature
[PATCH v2 0/1] Fix SPL_EARLY_BSS applying to normal build
SPL_CLEAR_BSS is called regardless of build type if CONFIG_SPL_EARLY_BSS is defined. This seems to break u-boot proper and doesn't seem like the correct behavior. Early bss clearing in u-boot proper happens before relocation and causes lots of problems because .rel.dyn and .bss overlap. Changes in v2: - Adding a check to the first SPL_CLEAR_BSS resulted in BSS never getting cleared for u-boot proper. Added an or condition to the second call. - SPL_CLEAR_BSS is the only bss clearing operation. Renamed to just CLEAR_BSS for clarity. Brian Moyer (1): arm: Add SPL build check to SPL early bss clear arch/arm/lib/crt0.S | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.17.1
[PATCH v2 1/1] arm: Add SPL build check to SPL early bss clear
SPL_CLEAR_BSS is called regardless of build type if CONFIG_SPL_EARLY_BSS is defined. Add a guard for CONFIG_SPL_BUILD to fix. Signed-off-by: Brian Moyer --- Changes in v2: - Adding a check to the first SPL_CLEAR_BSS resulted in BSS never getting cleared for u-boot proper. Added an or condition to the second call. - SPL_CLEAR_BSS is the only bss clearing operation. Renamed to just CLEAR_BSS for clarity. arch/arm/lib/crt0.S | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index df9dd83e40..46b6be21a8 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -64,7 +64,7 @@ * can afford it due to sufficient memory being available early. */ -.macro SPL_CLEAR_BSS +.macro CLEAR_BSS ldr r0, =__bss_start/* this is auto-relocated! */ #ifdef CONFIG_USE_ARCH_MEMSET @@ -109,8 +109,8 @@ ENTRY(_main) mov r9, r0 bl board_init_f_init_reserve -#if defined(CONFIG_SPL_EARLY_BSS) - SPL_CLEAR_BSS +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_EARLY_BSS) + CLEAR_BSS #endif mov r0, #0 @@ -150,8 +150,8 @@ here: #endif #if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK) -#if !defined(CONFIG_SPL_EARLY_BSS) - SPL_CLEAR_BSS +#if !defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_EARLY_BSS) + CLEAR_BSS #endif # ifdef CONFIG_SPL_BUILD -- 2.17.1
[PATCH] fit_image: Fix the introduction of variable bytes
Vagrant Cascadian reported that mx6cuboxi target no longer builds
reproducibility on Debian.
One example of builds mismatches:
00096680: 696e 6700 736f 756e 642d 6461 6900 6465 ing.sound-dai.de
-00096690: 7465 6374 2d67 7069 6f73 tect-gpios..
+00096690: 7465 6374 2d67 7069 6f73 0061tect-gpios.a
The mkimage tool is incorrectly introducing variable bytes after
"detect-gpios\0".
Fix the introduction of these variable bytes by using calloc(1, ...)
instead of malloc(...).
Reported-by: Vagrant Cascadian
Suggested-by: Tom Rini
Signed-off-by: Fabio Estevam
---
tools/fit_image.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tools/fit_image.c b/tools/fit_image.c
index a082d9386d..0c6185d892 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -388,7 +388,7 @@ static int fit_build(struct image_tool_params *params,
const char *fname)
size = fit_calc_size(params);
if (size < 0)
return -1;
- buf = malloc(size);
+ buf = calloc(1, size);
if (!buf) {
fprintf(stderr, "%s: Out of memory (%d bytes)\n",
params->cmdname, size);
@@ -467,7 +467,7 @@ static int fit_extract_data(struct image_tool_params
*params, const char *fname)
* Allocate space to hold the image data we will extract,
* extral space allocate for image alignment to prevent overflow.
*/
- buf = malloc(fit_size + (align_size * image_number));
+ buf = calloc(1, fit_size + (align_size * image_number));
if (!buf) {
ret = -ENOMEM;
goto err_munmap;
@@ -572,7 +572,7 @@ static int fit_import_data(struct image_tool_params
*params, const char *fname)
/* Allocate space to hold the new FIT */
size = sbuf.st_size + 16384;
- fdt = malloc(size);
+ fdt = calloc(1, size);
if (!fdt) {
fprintf(stderr, "%s: Failed to allocate memory (%d bytes)\n",
__func__, size);
@@ -673,7 +673,7 @@ static int copyfile(const char *src, const char *dst)
goto out;
}
- buf = malloc(512);
+ buf = calloc(1, 512);
if (!buf) {
printf("Can't allocate buffer to copy file\n");
goto out;
--
2.17.1
Re: Reproducibility regression with mx6cuboxi
Hi Vagrant, On Sun, Jul 26, 2020 at 3:17 PM Vagrant Cascadian wrote: > That appears to build reproducibly for me on top of v2020.07. Haven't > tested if the resulting image boots. I can confirm it boots fine on a imx6 humming board. I will submit it as a formal patch. Thanks
Re: Reproducibility regression with mx6cuboxi
On 2020-07-26, Fabio Estevam wrote: > On Sun, Jul 26, 2020 at 2:16 PM Tom Rini wrote: > >> I mean just literally changing the malloc(...) to calloc(1, ...), audit any >> other malloc(...) calls in the file and change nothing else. Thanks! > > Thanks for the clarification, Tom > > Vagrant, > > Does the patch below fix the reproducibility regression? > https://pastebin.com/raw/MWDUDrJ2 That appears to build reproducibly for me on top of v2020.07. Haven't tested if the resulting image boots. FWIW, re-applying Marek's old patch also appeared to fix the reproducibility issues: 20a154f95bfe0a3b5bfba90bea7f001c58217536 mkimage: fit: Do not tail-pad fitImage with external data Thanks all, seems a fix is near! live well, vagrant signature.asc Description: PGP signature
Re: Reproducibility regression with mx6cuboxi
On Sun, Jul 26, 2020 at 2:16 PM Tom Rini wrote: > I mean just literally changing the malloc(...) to calloc(1, ...), audit any > other malloc(...) calls in the file and change nothing else. Thanks! Thanks for the clarification, Tom Vagrant, Does the patch below fix the reproducibility regression? https://pastebin.com/raw/MWDUDrJ2 Thanks
Re: Reproducibility regression with mx6cuboxi
On Sun, Jul 26, 2020 at 02:00:33PM -0300, Fabio Estevam wrote:
> On Sun, Jul 26, 2020 at 12:05 PM Tom Rini wrote:
>
> > We just need to use calloc() in the tool and not mess with alignment.
>
> Like this?
>
> --- a/tools/fit_image.c
> +++ b/tools/fit_image.c
> @@ -446,7 +446,6 @@ static int fit_extract_data(struct
> image_tool_params *params, const char *fname)
> int ret;
> int images;
> int node;
> - int image_number;
> int align_size;
>
> align_size = params->bl_len ? params->bl_len : 4;
> @@ -461,13 +460,12 @@ static int fit_extract_data(struct
> image_tool_params *params, const char *fname)
> ret = -EINVAL;
> goto err_munmap;
> }
> - image_number = fdtdec_get_child_count(fdt, images);
>
> /*
> * Allocate space to hold the image data we will extract,
> * extral space allocate for image alignment to prevent overflow.
> */
> - buf = malloc(fit_size + (align_size * image_number));
> + buf = calloc(1, fit_size);
> if (!buf) {
> ret = -ENOMEM;
> goto err_munmap;
>
> If this is not the right approach, care to propose a patch?
I mean just literally changing the malloc(...) to calloc(1, ...), audit any
other malloc(...) calls in the file and change nothing else. Thanks!
--
Tom
signature.asc
Description: PGP signature
[PATCH v4 1/2] arch: arm: use dt and UCLASS_IRQ to get gic details
Use device tree and UCLASS_IRQ driver to get following
Generic Interrupt Controller (GIC) details,
-GIC Distributor interface (GICD) base address and
-GIC Redistributors (GICR) base address.
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
Changes from v3:
-Address review comments from Simon,
Correct the data type of variables
Changes from v1:
-Address review comments from Tom Rini,
Fix build warning messages.
arch/arm/lib/gic-v3-its.c | 73 +++
1 file changed, 66 insertions(+), 7 deletions(-)
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index 90f37a123c..5f88643245 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -3,6 +3,7 @@
* Copyright 2019 Broadcom.
*/
#include
+#include
#include
#include
#include
@@ -15,6 +16,48 @@ static u32 lpi_id_bits;
#define LPI_PROPBASE_SZALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
+/*
+ * gic_v3_its_priv - gic details
+ *
+ * @gicd_base: gicd base address
+ * @gicr_base: gicr base address
+ */
+struct gic_v3_its_priv {
+ ulong gicd_base;
+ ulong gicr_base;
+};
+
+static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
+{
+ struct udevice *dev;
+ fdt_addr_t addr;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_IRQ,
+ DM_GET_DRIVER(arm_gic_v3_its), );
+ if (ret) {
+ pr_err("%s: failed to get %s irq device\n", __func__,
+ DM_GET_DRIVER(arm_gic_v3_its)->name);
+ return ret;
+ }
+
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GICD address\n", __func__);
+ return -EINVAL;
+ }
+ priv->gicd_base = addr;
+
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GICR address\n", __func__);
+ return -EINVAL;
+ }
+ priv->gicr_base = addr;
+
+ return 0;
+}
+
/*
* Program the GIC LPI configuration tables for all
* the re-distributors and enable the LPI table
@@ -23,15 +66,18 @@ static u32 lpi_id_bits;
*/
int gic_lpi_tables_init(u64 base, u32 num_redist)
{
+ struct gic_v3_its_priv priv;
u32 gicd_typer;
u64 val;
u64 tmp;
int i;
u64 redist_lpi_base;
- u64 pend_base = GICR_BASE + GICR_PENDBASER;
+ u64 pend_base;
- gicd_typer = readl(GICD_BASE + GICD_TYPER);
+ if (gic_v3_its_get_gic_addr())
+ return -EINVAL;
+ gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
/* GIC support for Locality specific peripheral interrupts (LPI's) */
if (!(gicd_typer & GICD_TYPER_LPIS)) {
pr_err("GIC implementation does not support LPI's\n");
@@ -46,7 +92,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
for (i = 0; i < num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
- if ((readl((uintptr_t)(GICR_BASE + offset))) &
+ if ((readl((uintptr_t)(priv.gicr_base + offset))) &
GICR_CTLR_ENABLE_LPIS) {
pr_err("Re-Distributor %d LPI is already enabled\n",
i);
@@ -64,19 +110,21 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
GICR_PROPBASER_RAWAWB |
((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
- writeq(val, (GICR_BASE + GICR_PROPBASER));
- tmp = readl(GICR_BASE + GICR_PROPBASER);
+ writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
+ tmp = readl((uintptr_t)(priv.gicr_base + GICR_PROPBASER));
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
GICR_PROPBASER_CACHEABILITY_MASK);
val |= GICR_PROPBASER_NC;
- writeq(val, (GICR_BASE + GICR_PROPBASER));
+ writeq(val,
+ (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
}
}
redist_lpi_base = base + LPI_PROPBASE_SZ;
+ pend_base = priv.gicr_base + GICR_PENDBASER;
for (i = 0; i < num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
@@ -94,9 +142,20 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
}
/* Enable LPI for the redistributor */
- writel(GICR_CTLR_ENABLE_LPIS, (uintptr_t)(GICR_BASE + offset));
+ writel(GICR_CTLR_ENABLE_LPIS,
+ (uintptr_t)(priv.gicr_base + offset));
}
return 0;
}
+static const struct udevice_id
[PATCH v4 2/2] arch: arm: use dt and UCLASS_SYSCON to get gic lpi details
Use device tree and UCLASS_SYSCON driver to get
Generic Interrupt Controller (GIC) lpi address and
maximum GIC redistributors count.
Also update Kconfig to select REGMAP and SYSCON when
GIC_V3_ITS is enabled.
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
Changes from v3:
-Address review comments from Simon,
Correct the data type of variables
Changes from v2:
-Address review comments from Tom Rini,
Fix build errors messages.
arch/arm/Kconfig| 2 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 28 +--
arch/arm/include/asm/gic-v3.h | 4 +-
arch/arm/lib/gic-v3-its.c | 63 ++---
4 files changed, 61 insertions(+), 36 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e16fe03887..f88229d092 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -64,6 +64,8 @@ endif
config GIC_V3_ITS
bool "ARM GICV3 ITS"
+ select REGMAP
+ select SYSCON
help
ARM GICV3 Interrupt translation service (ITS).
Basic support for programming locality specific peripheral
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index ad7ea05935..135fe4a462 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -41,37 +41,11 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#ifdef CONFIG_GIC_V3_ITS
-#define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
-#define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
-#define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
- PROPTABLE_MAX_SZ, SZ_1M)
-static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
-{
- u32 phandle;
- int err;
- struct fdt_memory gic_rd_tables;
-
- gic_rd_tables.start = base;
- gic_rd_tables.end = base + size - 1;
- err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", _rd_tables,
-);
- if (err < 0)
- debug("%s: failed to add reserved memory: %d\n", __func__, err);
-
- return err;
-}
-
int ls_gic_rd_tables_init(void *blob)
{
- u64 gic_lpi_base;
int ret;
- gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
- ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
- if (ret)
- return ret;
-
- ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
+ ret = gic_lpi_tables_init();
if (ret)
debug("%s: failed to init gic-lpi-tables\n", __func__);
diff --git a/arch/arm/include/asm/gic-v3.h b/arch/arm/include/asm/gic-v3.h
index 5131fabec4..35efec78c3 100644
--- a/arch/arm/include/asm/gic-v3.h
+++ b/arch/arm/include/asm/gic-v3.h
@@ -127,9 +127,9 @@
#define GIC_REDISTRIBUTOR_OFFSET 0x2
#ifdef CONFIG_GIC_V3_ITS
-int gic_lpi_tables_init(u64 base, u32 max_redist);
+int gic_lpi_tables_init(void);
#else
-int gic_lpi_tables_init(u64 base, u32 max_redist)
+int gic_lpi_tables_init(void)
{
return 0;
}
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index 5f88643245..a1657e3853 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -4,6 +4,8 @@
*/
#include
#include
+#include
+#include
#include
#include
#include
@@ -16,15 +18,22 @@ static u32 lpi_id_bits;
#define LPI_PROPBASE_SZALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
+/* Number of GIC re-distributors */
+#define MAX_GIC_REDISTRIBUTORS 8
+
/*
* gic_v3_its_priv - gic details
*
* @gicd_base: gicd base address
* @gicr_base: gicr base address
+ * @lpi_base: gic lpi base address
+ * @num_redist: number of gic re-distributors
*/
struct gic_v3_its_priv {
ulong gicd_base;
ulong gicr_base;
+ ulong lpi_base;
+ u32 num_redist;
};
static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
@@ -58,13 +67,39 @@ static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv
*priv)
return 0;
}
+static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv)
+{
+ struct regmap *regmap;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_SYSCON,
+ DM_GET_DRIVER(gic_lpi_syscon), );
+ if (ret) {
+ pr_err("%s: failed to get %s syscon device\n", __func__,
+ DM_GET_DRIVER(gic_lpi_syscon)->name);
+ return ret;
+ }
+
+ regmap = syscon_get_regmap(dev);
+ if (!regmap) {
+ pr_err("%s: failed to regmap for %s syscon device\n", __func__,
+ DM_GET_DRIVER(gic_lpi_syscon)->name);
+ return -ENODEV;
+ }
+ priv->lpi_base = regmap->ranges[0].start;
+
+ priv->num_redist =
[PATCH v4 0/2] use dt and UCLASS_IRQ/SYSCON to get gic details
Use device tree and driver class (UCLASS_IRQ and UCLASS_SYSCON) to get gic details like GICD, GICR base address, max number of redistributors and git lpi address. Changes from v3: -Address review comments from Simon, Correct the data type of variables Changes from v2: -Address review comments from Tom Rini, Fix build errors messages. Changes from v1: -Address review comments from Tom Rini, Fix build warning messages. Rayagonda Kokatanur (2): arch: arm: use dt and UCLASS_IRQ to get gic details arch: arm: use dt and UCLASS_SYSCON to get gic lpi details arch/arm/Kconfig| 2 + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 28 + arch/arm/include/asm/gic-v3.h | 4 +- arch/arm/lib/gic-v3-its.c | 136 +--- 4 files changed, 127 insertions(+), 43 deletions(-) -- 2.17.1
Re: Reproducibility regression with mx6cuboxi
On Sun, Jul 26, 2020 at 12:05 PM Tom Rini wrote:
> We just need to use calloc() in the tool and not mess with alignment.
Like this?
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -446,7 +446,6 @@ static int fit_extract_data(struct
image_tool_params *params, const char *fname)
int ret;
int images;
int node;
- int image_number;
int align_size;
align_size = params->bl_len ? params->bl_len : 4;
@@ -461,13 +460,12 @@ static int fit_extract_data(struct
image_tool_params *params, const char *fname)
ret = -EINVAL;
goto err_munmap;
}
- image_number = fdtdec_get_child_count(fdt, images);
/*
* Allocate space to hold the image data we will extract,
* extral space allocate for image alignment to prevent overflow.
*/
- buf = malloc(fit_size + (align_size * image_number));
+ buf = calloc(1, fit_size);
if (!buf) {
ret = -ENOMEM;
goto err_munmap;
If this is not the right approach, care to propose a patch?
Thanks
Re: Reproducibility regression with mx6cuboxi
On Sun, Jul 26, 2020 at 11:57:43AM -0300, Fabio Estevam wrote: > Hi Vagrant, > > On Wed, Jul 22, 2020 at 6:10 PM Tom Rini wrote: > > > > Do you mean this one? > > > http://u-boot.10912.n7.nabble.com/PATCH-V2-mkimage-fit-Do-not-tail-pad-fitImage-with-external-data-td409920.html > > > > Yes, that one. > > I know Marek's patch caused a regression on other platforms, but could > you please give it a try and see if it fixes the reproducibility > problem? > > If it works for you, then we need to come up with a solution that does > not cause the boot regression on other platforms. We just need to use calloc() in the tool and not mess with alignment. -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 1/2] arch: arm: use dt and UCLASS_IRQ to get gic details
On Sat, 18 Jul 2020 at 08:45, Rayagonda Kokatanur wrote: > > Use device tree and UCLASS_IRQ driver to get following > Generic Interrupt Controller (GIC) details, > > -GIC Distributor interface (GICD) base address and > -GIC Redistributors (GICR) base address. > > Signed-off-by: Rayagonda Kokatanur > --- > Changes from v1: > -Address review comments from Tom Rini, > Fix build warning messages. > > arch/arm/lib/gic-v3-its.c | 73 +++ > 1 file changed, 66 insertions(+), 7 deletions(-) Reviewed-by: Simon Glass
Re: Reproducibility regression with mx6cuboxi
Hi Vagrant, On Wed, Jul 22, 2020 at 6:10 PM Tom Rini wrote: > > Do you mean this one? > > http://u-boot.10912.n7.nabble.com/PATCH-V2-mkimage-fit-Do-not-tail-pad-fitImage-with-external-data-td409920.html > > Yes, that one. I know Marek's patch caused a regression on other platforms, but could you please give it a try and see if it fixes the reproducibility problem? If it works for you, then we need to come up with a solution that does not cause the boot regression on other platforms. Thanks
Re: [PATCH] sandbox, test: change hog gpio
On Fri, 24 Jul 2020 at 07:51, Philippe Reynes
wrote:
>
> Since commit 9ba84329dc45 ("sandbox, test: add test for GPIO_HOG
> function"), the gpio_a 0,1,2 and 3 are used by hog in test.dts.
> But 2 leds 'sandbox:red' and 'sandbox:green' are using gpio_a 0
> and 1. As hog always request his gpios, the led command on both
> led is broken:
>
> => led sandbox:red
> LED 'sandbox:red' not found (err=-16)
>
> The gpio is already requested by hog, so it can't be enabled
> for led 'sandbox:red'.
>
> This commit change the gpio used by hog to 10, 11, 12 and 13,
> so the led command could be used again with 'sandbox:red' and
> 'sandbox:green'.
>
> Signed-off-by: Philippe Reynes
> ---
> arch/sandbox/dts/test.dts | 8
> test/dm/gpio.c| 12 ++--
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
Reviewed-by: Simon Glass
Re: [PATCH v3 1/2] arch: arm: use dt and UCLASS_IRQ to get gic details
On Sun, 19 Jul 2020 at 03:35, Rayagonda Kokatanur
wrote:
>
> Use device tree and UCLASS_IRQ driver to get following
> Generic Interrupt Controller (GIC) details,
>
> -GIC Distributor interface (GICD) base address and
> -GIC Redistributors (GICR) base address.
>
> Signed-off-by: Rayagonda Kokatanur
> ---
> Changes from v1:
> -Address review comments from Tom Rini,
> Fix build warning messages.
>
> arch/arm/lib/gic-v3-its.c | 73 +++
> 1 file changed, 66 insertions(+), 7 deletions(-)
Reviewed-by: Simon Glass
>
> diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
> index 90f37a123c..5057cc5421 100644
> --- a/arch/arm/lib/gic-v3-its.c
> +++ b/arch/arm/lib/gic-v3-its.c
> @@ -3,6 +3,7 @@
> * Copyright 2019 Broadcom.
> */
> #include
> +#include
> #include
> #include
> #include
> @@ -15,6 +16,48 @@ static u32 lpi_id_bits;
> #define LPI_PROPBASE_SZALIGN(BIT(LPI_NRBITS), SZ_64K)
> #define LPI_PENDBASE_SZALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
>
> +/*
> + * gic_v3_its_priv - gic details
> + *
> + * @gicd_base: gicd base address
> + * @gicr_base: gicr base address
> + */
> +struct gic_v3_its_priv {
> + u32 gicd_base;
> + u32 gicr_base;
ulong I think
> +};
> +
> +static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
> +{
> + struct udevice *dev;
> + fdt_addr_t addr;
> + int ret;
> +
> + ret = uclass_get_device_by_driver(UCLASS_IRQ,
> + DM_GET_DRIVER(arm_gic_v3_its),
> );
> + if (ret) {
> + pr_err("%s: failed to get %s irq device\n", __func__,
> + DM_GET_DRIVER(arm_gic_v3_its)->name);
> + return ret;
> + }
> +
> + addr = dev_read_addr_index(dev, 0);
> + if (addr == FDT_ADDR_T_NONE) {
> + pr_err("%s: failed to get GICD address\n", __func__);
> + return -EINVAL;
> + }
> + priv->gicd_base = addr;
> +
> + addr = dev_read_addr_index(dev, 1);
> + if (addr == FDT_ADDR_T_NONE) {
> + pr_err("%s: failed to get GICR address\n", __func__);
> + return -EINVAL;
> + }
> + priv->gicr_base = addr;
> +
> + return 0;
> +}
> +
> /*
> * Program the GIC LPI configuration tables for all
> * the re-distributors and enable the LPI table
> @@ -23,15 +66,18 @@ static u32 lpi_id_bits;
> */
> int gic_lpi_tables_init(u64 base, u32 num_redist)
> {
> + struct gic_v3_its_priv priv;
> u32 gicd_typer;
> u64 val;
> u64 tmp;
> int i;
> u64 redist_lpi_base;
> - u64 pend_base = GICR_BASE + GICR_PENDBASER;
> + u64 pend_base;
>
> - gicd_typer = readl(GICD_BASE + GICD_TYPER);
> + if (gic_v3_its_get_gic_addr())
> + return -EINVAL;
>
> + gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
> /* GIC support for Locality specific peripheral interrupts (LPI's) */
> if (!(gicd_typer & GICD_TYPER_LPIS)) {
> pr_err("GIC implementation does not support LPI's\n");
> @@ -46,7 +92,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
> for (i = 0; i < num_redist; i++) {
> u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
>
> - if ((readl((uintptr_t)(GICR_BASE + offset))) &
> + if ((readl((uintptr_t)(priv.gicr_base + offset))) &
> GICR_CTLR_ENABLE_LPIS) {
> pr_err("Re-Distributor %d LPI is already enabled\n",
>i);
> @@ -64,19 +110,21 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
>GICR_PROPBASER_RAWAWB |
>((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
>
> - writeq(val, (GICR_BASE + GICR_PROPBASER));
> - tmp = readl(GICR_BASE + GICR_PROPBASER);
> + writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
> + tmp = readl((uintptr_t)(priv.gicr_base + GICR_PROPBASER));
> if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
> if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
> val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
> GICR_PROPBASER_CACHEABILITY_MASK);
> val |= GICR_PROPBASER_NC;
> - writeq(val, (GICR_BASE + GICR_PROPBASER));
> + writeq(val,
> + (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
> }
> }
>
> redist_lpi_base = base + LPI_PROPBASE_SZ;
>
> + pend_base = priv.gicr_base + GICR_PENDBASER;
> for (i = 0; i < num_redist; i++) {
> u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
>
> @@ -94,9 +142,20 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
> }
>
> /* Enable LPI for the redistributor */
> -
Re: [PATCH 1/4] firmware: add new driver for SCMI firmwares
Hi Etienne,
On Fri, 17 Jul 2020 at 09:38, Etienne Carriere
wrote:
>
> This change introduces SCMI agent driver in U-Boot in the firmware
> U-class.
>
> SCMI agent driver is designed for platforms that embed a SCMI server in
> a firmware hosted for example by a companion co-processor or the secure
> world of the executing processor.
>
> SCMI protocols allow an SCMI agent to discover and access external
> resources as clock, reset controllers and many more. SCMI agent and
> server communicate following the SCMI specification [1]. SCMI agent
> complies with the DT bindings defined in the Linux kernel source tree
> regarding SCMI agent description since v5.8-rc1.
>
> These bindings describe 2 supported message transport layer: using
> mailbox uclass devices or using Arm SMC invocation instruction. Both
> use a piece or shared memory for message data exchange.
>
> In the current state, the SCMI agent driver does not bind to any SCMI
> protocol to a U-Boot device driver. Former changes will implement
> dedicated driver (i.e. an SCMI clock driver or an SCMI reset controller
> driver) and add bind supported SCMI protocols in scmi_agent_bind().
>
> Links: [1]
> https://developer.arm.com/architectures/system-architectures/software-standards/scmi
> Signed-off-by: Etienne Carriere
> ---
>
> drivers/firmware/Kconfig | 15 ++
> drivers/firmware/Makefile | 1 +
> drivers/firmware/scmi.c | 439 ++
> include/scmi.h| 82 +++
> 4 files changed, 537 insertions(+)
> create mode 100644 drivers/firmware/scmi.c
> create mode 100644 include/scmi.h
>
> diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
> index b70a2063551..f7c7ee7a5aa 100644
> --- a/drivers/firmware/Kconfig
> +++ b/drivers/firmware/Kconfig
> @@ -1,6 +1,21 @@
> config FIRMWARE
> bool "Enable Firmware driver support"
>
> +config SCMI_FIRMWARE
> + bool "Enable SCMI support"
> + select FIRMWARE
> + select OF_TRANSLATE
> + depends on DM_MAILBOX || ARM_SMCCC
> + help
> + An SCMI agent communicates with a related SCMI server firmware
Please write out SCMI in full somewhere and add a link to the spec.
> + located in another sub-system, as a companion micro controller
> + or a companion host in the CPU system.
> +
> + Communications between agent (client) and the SCMI server are
> + based on message exchange. Messages can be exchange over tranport
> + channels as a mailbox device or an Arm SMCCC service with some
> + piece of identified shared memory.
> +
> config SPL_FIRMWARE
> bool "Enable Firmware driver support in SPL"
> depends on FIRMWARE
> diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
> index a0c250a473e..3965838179f 100644
> --- a/drivers/firmware/Makefile
> +++ b/drivers/firmware/Makefile
> @@ -2,4 +2,5 @@ obj-$(CONFIG_FIRMWARE) += firmware-uclass.o
> obj-$(CONFIG_$(SPL_)ARM_PSCI_FW) += psci.o
> obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o
> obj-$(CONFIG_SANDBOX) += firmware-sandbox.o
> +obj-$(CONFIG_SCMI_FIRMWARE)+= scmi.o
> obj-$(CONFIG_ZYNQMP_FIRMWARE) += firmware-zynqmp.o
> diff --git a/drivers/firmware/scmi.c b/drivers/firmware/scmi.c
> new file mode 100644
> index 000..fa8a91c3f3d
> --- /dev/null
> +++ b/drivers/firmware/scmi.c
> @@ -0,0 +1,439 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights
> reserved.
> + * Copyright (C) 2019-2020 Linaro Limited.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define TIMEOUT_US_10MS1
> +
> +struct error_code {
Function comment
> + int scmi;
> + int errno;
> +};
> +
> +static const struct error_code scmi_linux_errmap[] = {
> + { .scmi = SCMI_NOT_SUPPORTED, .errno = -EOPNOTSUPP, },
> + { .scmi = SCMI_INVALID_PARAMETERS, .errno = -EINVAL, },
> + { .scmi = SCMI_DENIED, .errno = -EACCES, },
> + { .scmi = SCMI_NOT_FOUND, .errno = -ENOENT, },
> + { .scmi = SCMI_OUT_OF_RANGE, .errno = -ERANGE, },
> + { .scmi = SCMI_BUSY, .errno = -EBUSY, },
> + { .scmi = SCMI_COMMS_ERROR, .errno = -ECOMM, },
> + { .scmi = SCMI_GENERIC_ERROR, .errno = -EIO, },
> + { .scmi = SCMI_HARDWARE_ERROR, .errno = -EREMOTEIO, },
> + { .scmi = SCMI_PROTOCOL_ERROR, .errno = -EPROTO, },
> +};
> +
> +int scmi_to_linux_errno(s32 scmi_code)
> +{
> + int n;
> +
> + if (scmi_code == 0)
> + return 0;
> +
> + for (n = 0; n < ARRAY_SIZE(scmi_linux_errmap); n++)
> + if (scmi_code == scmi_linux_errmap[n].scmi)
> + return scmi_linux_errmap[1].errno;
> +
> + return -EPROTO;
> +}
Re: [PATCH v2 3/3] dtoc: remove compatible string aliases support
On Wed, 22 Jul 2020 at 21:22, Walter Lozano wrote: > > After latest improvements in dtoc, compatible strings are checked > against driver and driver alias list to get a valid driver name. With > this new feature the list of compatible string aliases seems not > useful any more. > > Signed-off-by: Walter Lozano > --- > > (no changes since v1) > > tools/dtoc/dtb_platdata.py | 13 > tools/dtoc/test_dtoc.py| 43 -- > 2 files changed, 56 deletions(-) > Reviewed-by: Simon Glass
Re: [PATCH 1/1] mtd: cfi_flash: read device tree correctly
Hi Stefan,
On Sat, 25 Jul 2020 at 05:47, Stefan Roese wrote:
>
> Hi Heinrich,
>
> (added Simon to Cc)
>
> On 24.07.20 18:34, Heinrich Schuchardt wrote:
> > On 24.07.20 11:14, Rick Chen wrote:
> >> Hi Heinrich
> >>
> >>> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Heinrich
> >>> Schuchardt
> >>> Sent: Tuesday, July 21, 2020 10:51 AM
> >>> To: Stefan Roese
> >>> Cc: Simon Glass; u-boot@lists.denx.de; Heinrich Schuchardt
> >>> Subject: [PATCH 1/1] mtd: cfi_flash: read device tree correctly
> >>>
> >>> dev_read_size_cells() and dev_read_addr_cells() do not walk up the device
> >>> tree to find the number of cells. On error they return 1 and 2
> >>> respectively. On qemu_arm64_defconfig this leads to the incorrect
> >>> detection of address of the second flash bank as 0x400
> >>> instead of 0x400.
> >>>
> >>> When running
> >>>
> >>> qemu-system-aarch64 -machine virt -bios u-boot.bin \
> >>> -cpu cortex-a53 -nographic \
> >>> -drive if=pflash,format=raw,index=1,file=envstore.img
> >>>
> >>> the command 'saveenv' fails with
> >>>
> >>> Saving Environment to Flash... Error: start and/or end address not on
> >>> sector boundary
> >>> Error: start and/or end address not on sector boundary
> >>> Failed (1)
> >>>
> >>> due to this incorrect address.
> >>>
> >>> Use function fdtdec_get_addr_size_auto_noparent() to read the array of
> >>> flash banks from the device tree.
> >>>
> >>> Signed-off-by: Heinrich Schuchardt
> >>> ---
> >>> drivers/mtd/cfi_flash.c | 20
> >>> 1 file changed, 8 insertions(+), 12 deletions(-)
> >>>
> >>> diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index
> >>> b7289ba539..dfa104bcf0 100644
> >>> --- a/drivers/mtd/cfi_flash.c
> >>> +++ b/drivers/mtd/cfi_flash.c
> >>> @@ -2469,28 +2469,24 @@ unsigned long flash_init(void) static int
> >>> cfi_flash_probe(struct udevice *dev) {
> >>> const fdt32_t *cell;
> >>> - int addrc, sizec;
> >>> - int len, idx;
> >>> -
> >>> - addrc = dev_read_addr_cells(dev);
> >>> - sizec = dev_read_size_cells(dev);
> >>> + int len;
> >>>
> >>> /* decode regs; there may be multiple reg tuples. */
> >>> cell = dev_read_prop(dev, "reg", );
> >>> if (!cell)
> >>> return -ENOENT;
> >>> - idx = 0;
> >>> - len /= sizeof(fdt32_t);
> >>> - while (idx < len) {
> >>> +
> >>> + for (cfi_flash_num_flash_banks = 0; ;
> >>> ++cfi_flash_num_flash_banks) {
> >>> phys_addr_t addr;
> >>>
> >>> - addr = dev_translate_address(dev, cell + idx);
> >>> + addr = fdtdec_get_addr_size_auto_noparent(
> >>> + gd->fdt_blob, dev_of_offset(dev), "reg",
> >>> + cfi_flash_num_flash_banks, NULL, false);
> >>> + if (addr == FDT_ADDR_T_NONE)
> >>> + break;
> >>>
> >>> flash_info[cfi_flash_num_flash_banks].dev = dev;
> >>> flash_info[cfi_flash_num_flash_banks].base = addr;
> >>> - cfi_flash_num_flash_banks++;
> >>> -
> >>> - idx += addrc + sizec;
> >>> }
> >>> gd->bd->bi_flashstart = flash_info[0].base;
> >>>
> >>> --
> >>> 2.27.0
> >>>
> >>
> >> This patch remind me that I have encounter flash bank detection
> >> problem on AE350 platform a period time ago.
> >> And have commit a patch to work around this problem as below:
> >>
> >
> >> commit cca8b1e5b20cdab7299a5ee7139e70783f73ccdf
> >>
> >> riscv: dts: Add #address-cells and #size-cells in nor node
> >>
> >> Those are required for cfi-flash driver to get correct address
> >> information.
> >> Also modify size description correctly.
> >>
> >> With this patch, there is unnecessary to re-declaration address-cells
> >> and size-cells in nor node indeed.
> >>
> >> Tested-by: Rick Chen
> >>
> >> Thanks,
> >> Rick
> >>
> >
> > Dear Stefan, dear Rick,
> >
> > thanks for testing on different systems.
> >
> > The reason for the different test results is the usage of CONFIG_OF_LIVE:
> >
> > CONFIG_OF_LIVE=y
> > * octeon_ebb7304_defconfig
> >
> > CONFIG_OF_LIVE=n
> > * ae350_rv32_defconfig
> > * qemu_arm64_defconfig
> >
> > dev_translate_address() behaves differently depending on the usage of a
> > live tree.
> >
> > I will send a revised patch that only changes the behavior only for the
> > CONFIG_OF_LIVE=n case after testing qemu_arm64_defconfig both with and
> > without live tree.
>
> Thanks for looking into this. But I wonder, if it makes more sense to
> change the OF_LIVE implementation so that it matches the "non-OF_LIVE"
> version? We should strive to have both implementations achieving the
> same results I think.
>
> Or am I missing something?
Yes we should, and also add tests to catch the difference.
Regards,
Simon
Re: [PATCH 4/4] reset: add reset controller driver for SCMI agents
Hi Etienne,
On Fri, 17 Jul 2020 at 09:43, Etienne Carriere
wrote:
>
> This change introduces a reset controller driver for SCMI agent devices.
> When SCMI agent and SCMI reset domain drivers are enabled, SCMI agent
> binds a reset controller device for each SCMI reset domain protocol
> devices enabled in the FDT.
>
> SCMI reset driver is embedded upon CONFIG_RESET_SCMI=y. If enabled,
> CONFIG_SCMI_AGENT is also enabled.
>
> SCMI Reset Domain protocol is defined in the SCMI specification [1].
>
> Links: [1]
> https://developer.arm.com/architectures/system-architectures/software-standards/scmi
> Signed-off-by: Etienne Carriere
> ---
>
> drivers/firmware/scmi.c| 3 ++
> drivers/reset/Kconfig | 8
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-scmi.c | 86 ++
> 4 files changed, 98 insertions(+)
> create mode 100644 drivers/reset/reset-scmi.c
Reviewed-by: Simon Glass
>
> diff --git a/drivers/firmware/scmi.c b/drivers/firmware/scmi.c
> index 9f06718df51..9be53a9cf11 100644
> --- a/drivers/firmware/scmi.c
> +++ b/drivers/firmware/scmi.c
> @@ -402,6 +402,9 @@ static int scmi_bind(struct udevice *dev)
> case SCMI_PROTOCOL_ID_CLOCK:
> drv = DM_GET_DRIVER(scmi_clock);
> break;
> + case SCMI_PROTOCOL_ID_RESET_DOMAIN:
> + drv = DM_GET_DRIVER(scmi_reset_domain);
> + break;
> default:
> dev_info(dev, "Ignore unsupported SCMI protocol %u\n",
> protocol_id);
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 6d535612234..31bd4cd5b45 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -164,4 +164,12 @@ config RESET_RASPBERRYPI
> relevant. This driver provides a reset controller capable of
> interfacing with RPi4's co-processor and model these firmware
> initialization routines as reset lines.
> +
> +config RESET_SCMI
> + bool "Enable SCMI reset domain driver"
> + select SCMI_FIRMWARE
> + help
> + Enable this option if you want to support reset controller
> + devices exposed by a SCMI agent based on SCMI reset domain
> + protocol communication with a SCMI server.
> endmenu
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 8e0124b8dee..f3c0fbfd8f3 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -25,3 +25,4 @@ obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
> obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
> obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
> obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
> +obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
> diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c
> new file mode 100644
> index 000..e664d91d865
> --- /dev/null
> +++ b/drivers/reset/reset-scmi.c
> @@ -0,0 +1,86 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019-2020 Linaro Limited
> + */
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +enum scmi_reset_domain_message_id {
> + SCMI_RESET_DOMAIN_RESET = 0x4,
> +};
> +
> +#define SCMI_RD_RESET_FLAG_ASSERT BIT(1)
> +#define SCMI_RD_RESET_FLAG_DEASSERT0
> +
> +struct scmi_rd_reset_in {
> + u32 domain_id;
> + u32 flags;
> + u32 reset_state;
> +};
> +
> +struct scmi_rd_reset_out {
> + s32 status;
> +};
> +
> +static int scmi_reset_set_state(struct reset_ctl *rst, int
> assert_not_deassert)
> +{
> + struct scmi_rd_reset_in in = {
> + .domain_id = rst->id,
> + .flags = assert_not_deassert ? SCMI_RD_RESET_FLAG_ASSERT :
> +SCMI_RD_RESET_FLAG_DEASSERT,
> + .reset_state = 0,
> + };
> + struct scmi_rd_reset_out out;
> + struct scmi_msg scmi_msg = {
> + .protocol_id = SCMI_PROTOCOL_ID_RESET_DOMAIN,
> + .message_id = SCMI_RESET_DOMAIN_RESET,
> + .in_msg = (u8 *),
> + .in_msg_sz = sizeof(in),
> + .out_msg = (u8 *),
> + .out_msg_sz = sizeof(out),
> + };
> + int rc;
> +
> + rc = scmi_send_and_process_msg(rst->dev->parent, _msg);
> + if (rc)
> + return rc;
> +
> + return scmi_to_linux_errno(out.status);
> +}
> +
> +static int scmi_reset_assert(struct reset_ctl *rst)
> +{
> + return scmi_reset_set_state(rst, SCMI_RD_RESET_FLAG_ASSERT);
> +}
> +
> +static int scmi_reset_deassert(struct reset_ctl *rst)
> +{
> + return scmi_reset_set_state(rst, SCMI_RD_RESET_FLAG_DEASSERT);
> +}
> +
> +static int scmi_reset_request(struct reset_ctl *reset_ctl)
> +{
Do you actually need these two functions if they do nothing?
> + return 0;
> +}
> +
> +static int scmi_reset_rfree(struct reset_ctl *reset_ctl)
> +{
> + return 0;
> +}
> +
Re: [PATCH 2/2] arch: x86: apl: Update FSP parameters
On Wed, 22 Jul 2020 at 01:29, Bernhard Messerklinger wrote: > > Add missing parameters to support full configuration of the latest FSP > MR6 release. > > Signed-off-by: Bernhard Messerklinger > > --- > > arch/x86/cpu/apollolake/fsp_bindings.c| 23 +++ > .../asm/arch-apollolake/fsp/fsp_m_upd.h | 5 +++- > .../asm/arch-apollolake/fsp/fsp_s_upd.h | 9 +++- > .../fsp/fsp2/apollolake/fsp-m.txt | 3 +++ > .../fsp/fsp2/apollolake/fsp-s.txt | 6 + > 5 files changed, 44 insertions(+), 2 deletions(-) Reviewed-by: Simon Glass
Re: [PATCH v2 2/2] arch: arm: use dt and UCLASS_SYSCON to get gic lpi details
On Sat, 18 Jul 2020 at 08:45, Rayagonda Kokatanur
wrote:
>
> Use device tree and UCLASS_SYSCON driver to get
> Generic Interrupt Controller (GIC) lpi address and
> maximum GIC redistributors count.
>
> Also update Kconfig to select REGMAP and SYSCON when
> GIC_V3_ITS is enabled.
>
> Signed-off-by: Rayagonda Kokatanur
> ---
> arch/arm/Kconfig | 2 ++
> arch/arm/include/asm/gic-v3.h | 4 +--
> arch/arm/lib/gic-v3-its.c | 63 +++
> 3 files changed, 60 insertions(+), 9 deletions(-)
Reviewed-by: Simon Glass
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index f115fcdcc4..2fd20fc648 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -64,6 +64,8 @@ endif
>
> config GIC_V3_ITS
> bool "ARM GICV3 ITS"
> + select REGMAP
> + select SYSCON
> help
> ARM GICV3 Interrupt translation service (ITS).
> Basic support for programming locality specific peripheral
> diff --git a/arch/arm/include/asm/gic-v3.h b/arch/arm/include/asm/gic-v3.h
> index 5131fabec4..35efec78c3 100644
> --- a/arch/arm/include/asm/gic-v3.h
> +++ b/arch/arm/include/asm/gic-v3.h
> @@ -127,9 +127,9 @@
> #define GIC_REDISTRIBUTOR_OFFSET 0x2
>
> #ifdef CONFIG_GIC_V3_ITS
> -int gic_lpi_tables_init(u64 base, u32 max_redist);
> +int gic_lpi_tables_init(void);
> #else
> -int gic_lpi_tables_init(u64 base, u32 max_redist)
> +int gic_lpi_tables_init(void)
> {
> return 0;
> }
> diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
> index 5057cc5421..5e82bdf568 100644
> --- a/arch/arm/lib/gic-v3-its.c
> +++ b/arch/arm/lib/gic-v3-its.c
> @@ -4,6 +4,8 @@
> */
> #include
> #include
> +#include
> +#include
> #include
> #include
> #include
> @@ -16,15 +18,22 @@ static u32 lpi_id_bits;
> #define LPI_PROPBASE_SZALIGN(BIT(LPI_NRBITS), SZ_64K)
> #define LPI_PENDBASE_SZALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
>
> +/* Number of GIC re-distributors */
> +#define MAX_GIC_REDISTRIBUTORS 8
> +
> /*
> * gic_v3_its_priv - gic details
> *
> * @gicd_base: gicd base address
> * @gicr_base: gicr base address
> + * @lpi_base: gic lpi base address
> + * @num_redist: number of gic re-distributors
> */
> struct gic_v3_its_priv {
> u32 gicd_base;
> u32 gicr_base;
> + u32 lpi_base;
> + u32 num_redist;
If these are addresses I think they should be ulong
> };
>
> static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
> @@ -58,13 +67,39 @@ static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv
> *priv)
> return 0;
> }
>
> +static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv)
> +{
> + struct regmap *regmap;
> + struct udevice *dev;
> + int ret;
> +
> + ret = uclass_get_device_by_driver(UCLASS_SYSCON,
> + DM_GET_DRIVER(gic_lpi_syscon),
> );
> + if (ret) {
> + pr_err("%s: failed to get %s syscon device\n", __func__,
> + DM_GET_DRIVER(gic_lpi_syscon)->name);
> + return ret;
> + }
> +
> + regmap = syscon_get_regmap(dev);
> + if (!regmap) {
> + pr_err("%s: failed to regmap for %s syscon device\n",
> __func__,
> + DM_GET_DRIVER(gic_lpi_syscon)->name);
> + return -ENODEV;
> + }
> + priv->lpi_base = regmap->ranges[0].start;
> +
> + priv->num_redist = dev_read_u32_default(dev, "max-gic-redistributors",
> + MAX_GIC_REDISTRIBUTORS);
> +
> + return 0;
> +}
> +
> /*
> * Program the GIC LPI configuration tables for all
> * the re-distributors and enable the LPI table
> - * base: Configuration table address
> - * num_redist: number of redistributors
> */
> -int gic_lpi_tables_init(u64 base, u32 num_redist)
> +int gic_lpi_tables_init(void)
> {
> struct gic_v3_its_priv priv;
> u32 gicd_typer;
> @@ -77,6 +112,9 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
> if (gic_v3_its_get_gic_addr())
> return -EINVAL;
>
> + if (gic_v3_its_get_gic_lpi_addr())
> + return -EINVAL;
> +
> gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
> /* GIC support for Locality specific peripheral interrupts (LPI's) */
> if (!(gicd_typer & GICD_TYPER_LPIS)) {
> @@ -89,7 +127,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
> * Once the LPI table is enabled, can not program the
> * LPI configuration tables again, unless the GIC is reset.
> */
> - for (i = 0; i < num_redist; i++) {
> + for (i = 0; i < priv.num_redist; i++) {
> u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
>
> if ((readl((uintptr_t)(priv.gicr_base + offset))) &
> @@ -105,7 +143,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
>
Re: [PATCH 1/2] x86: apl: fsp_bindings: Add support for u64 parameters
On Wed, 22 Jul 2020 at 01:29, Bernhard Messerklinger wrote: > > Add FSP_UINT64 read support as preparation for FSP-M and FSP-S parameter > update. > > Signed-off-by: Bernhard Messerklinger > > --- > > arch/x86/cpu/apollolake/fsp_bindings.c| 28 +++ > .../asm/arch-apollolake/fsp_bindings.h| 1 + > 2 files changed, 29 insertions(+) Reviewed-by: Simon Glass
Re: [PATCH v3 2/2] arch: arm: use dt and UCLASS_SYSCON to get gic lpi details
On Sun, 19 Jul 2020 at 03:35, Rayagonda Kokatanur wrote: > > Use device tree and UCLASS_SYSCON driver to get > Generic Interrupt Controller (GIC) lpi address and > maximum GIC redistributors count. > > Also update Kconfig to select REGMAP and SYSCON when > GIC_V3_ITS is enabled. > > Signed-off-by: Rayagonda Kokatanur > --- > Changes from v2: > -Address review comments from Tom Rini, > Fix build errors messages. > > arch/arm/Kconfig| 2 + > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 28 +-- > arch/arm/include/asm/gic-v3.h | 4 +- > arch/arm/lib/gic-v3-its.c | 63 ++--- > 4 files changed, 61 insertions(+), 36 deletions(-) > Reviewed-by: Simon Glass
Re: [PATCH 02/31] mtd: spi-nor: Tidy up error handling / debug code
Hi Vignesh,
On Mon, 20 Jul 2020 at 00:26, Vignesh Raghavendra wrote:
>
> Hi Simon,
>
> On 19/07/20 9:45 pm, Simon Glass wrote:
> > The -ENODEV error value in spi_nor_read_id() is incorrect since there
> > clearly is a device - it just cannot be supported.
>
> Description 's not entirely accurate... If there is no flash on the SPI
> bus, then read ID would return all 0s or 0xFFs depending on the pullups
> on the board which would fail to match any flash in the spi-nor-ids table.
>
> So its not just the case of device IDs not recognized or supported by
> U-Boot, it maybe that flash is absent altogether.
But struct udevice * exists, so there is a device. Whether it is
connected to something is a separate issue.
The problem is that -ENODEV means that the device should not be
created or should not exist.
What happens if an invalid ID is returned? Does it unbind the device?
Regards,
Simon
>
> Regards
> Vignesh
>
> > Use -ENOMEDIUM instead
> > which has the virtue of being less common.
> >
> > Fix the return value in spi_nor_scan().
> >
> > Also there are a few printf() statements which should be debug() since
> > they bloat the code with unused strings at present. Fix those while here.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > drivers/mtd/spi/sf_probe.c | 2 +-
> > drivers/mtd/spi/spi-nor-core.c | 2 +-
> > drivers/mtd/spi/spi-nor-tiny.c | 4 ++--
> > 3 files changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
> > index 475f6c31db..b959e3453a 100644
> > --- a/drivers/mtd/spi/sf_probe.c
> > +++ b/drivers/mtd/spi/sf_probe.c
> > @@ -119,7 +119,7 @@ static int spi_flash_std_erase(struct udevice *dev, u32
> > offset, size_t len)
> > struct erase_info instr;
> >
> > if (offset % mtd->erasesize || len % mtd->erasesize) {
> > - printf("SF: Erase offset/length not multiple of erase
> > size\n");
> > + debug("SF: Erase offset/length not multiple of erase size\n");
> > return -EINVAL;
> > }
> >
> > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> > index fdcd830ce4..0113e70037 100644
> > --- a/drivers/mtd/spi/spi-nor-core.c
> > +++ b/drivers/mtd/spi/spi-nor-core.c
> > @@ -2470,7 +2470,7 @@ static int spi_nor_init(struct spi_nor *nor)
> >* designer) that this is bad.
> >*/
> > if (nor->flags & SNOR_F_BROKEN_RESET)
> > - printf("enabling reset hack; may not recover from
> > unexpected reboots\n");
> > + debug("enabling reset hack; may not recover from
> > unexpected reboots\n");
> > set_4byte(nor, nor->info, 1);
> > }
> >
> > diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c
> > index 9f676c649d..fa26ea33c8 100644
> > --- a/drivers/mtd/spi/spi-nor-tiny.c
> > +++ b/drivers/mtd/spi/spi-nor-tiny.c
> > @@ -377,7 +377,7 @@ static const struct flash_info *spi_nor_read_id(struct
> > spi_nor *nor)
> > }
> > dev_dbg(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
> > id[0], id[1], id[2]);
> > - return ERR_PTR(-ENODEV);
> > + return ERR_PTR(-EMEDIUMTYPE);
> > }
> >
> > static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
> > @@ -733,7 +733,7 @@ int spi_nor_scan(struct spi_nor *nor)
> >
> > info = spi_nor_read_id(nor);
> > if (IS_ERR_OR_NULL(info))
> > - return -ENOENT;
> > + return PTR_ERR(info);
> > /* Parse the Serial Flash Discoverable Parameters table. */
> > ret = spi_nor_init_params(nor, info, );
> > if (ret)
> >
Re: [PATCH 1/1] efi_loader: returning form UEFI FIT images
On Sat, 18 Jul 2020 at 03:17, Heinrich Schuchardt wrote: > > Do not reset the board when returning from an UEFI FIT image. > > For failed UEFI binary we already print the return status in efi_run_image. > Remove duplicate output. > > Signed-off-by: Heinrich Schuchardt > --- > common/bootm_os.c | 9 - > 1 file changed, 4 insertions(+), 5 deletions(-) > Reviewed-by: Simon Glass
Re: [PATCH 1/6] Convert CONFIG_SYS_DEVICE_NULLDEV to Kconfig
Hi Ovidiu, On Sat, 18 Jul 2020 at 12:04, Ovidiu Panait wrote: > > Hi Simon, > > On 18.07.2020 06:03, Simon Glass wrote: > > This converts the following to Kconfig: >CONFIG_SYS_DEVICE_NULLDEV > > Signed-off-by: Simon Glass > --- > > common/Kconfig | 16 > configs/M5249EVB_defconfig | 3 ++- > configs/colibri_pxa270_defconfig | 2 +- > doc/README.silent| 2 +- > include/configs/M5249EVB.h | 2 -- > include/configs/colibri_pxa270.h | 2 -- > scripts/config_whitelist.txt | 1 - > 7 files changed, 20 insertions(+), 8 deletions(-) > > diff --git a/common/Kconfig b/common/Kconfig > index 67b3818fde..4d5b3a9cfb 100644 > --- a/common/Kconfig > +++ b/common/Kconfig > @@ -634,6 +634,22 @@ config SYS_STDIO_DEREGISTER >removed (for example a USB keyboard) then this option can be >enabled to ensure this is handled correctly. > > +config SPL_SYS_STDIO_DEREGISTER > + bool "Allow deregistering stdio devices in SPL" > + help > + Generally there is no need to deregister stdio devices since they > + are never deactivated. But if a stdio device is used which can be > + removed (for example a USB keyboard) then this option can be > + enabled to ensure this is handled correctly. This is very rarely > + needed in SPL. > + > +config SYS_DEVICE_NULLDEV > + bool "Enable a null device for stdio" > + help > + Enable creation of a "nulldev" stdio device. This allows silent > + operation of the console by setting stdout to "nulldev". Enable > + this to use a serial console under board control. > + > endmenu > > menu "Logging" > diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig > index 12db389b69..8f8a4a6bad 100644 > --- a/configs/M5249EVB_defconfig > +++ b/configs/M5249EVB_defconfig > @@ -3,7 +3,9 @@ CONFIG_SYS_TEXT_BASE=0xFFE0 > CONFIG_ENV_SIZE=0x2000 > CONFIG_ENV_SECT_SIZE=0x2000 > CONFIG_TARGET_M5249EVB=y > +CONFIG_DEFAULT_DEVICE_TREE="M5249EVB" > CONFIG_SYS_CONSOLE_INFO_QUIET=y > +CONFIG_SYS_DEVICE_NULLDEV=y > # CONFIG_DISPLAY_BOARDINFO is not set > # CONFIG_CMDLINE_EDITING is not set > # CONFIG_AUTOBOOT is not set > @@ -12,7 +14,6 @@ CONFIG_LOOPW=y > CONFIG_CMD_MX_CYCLIC=y > # CONFIG_CMD_SETEXPR is not set > CONFIG_CMD_CACHE=y > -CONFIG_DEFAULT_DEVICE_TREE="M5249EVB" > CONFIG_ENV_ADDR=0xFFE04000 > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > # CONFIG_NET is not set > diff --git a/configs/colibri_pxa270_defconfig > b/configs/colibri_pxa270_defconfig > index 669b9dfe58..aff7b62639 100644 > --- a/configs/colibri_pxa270_defconfig > +++ b/configs/colibri_pxa270_defconfig > @@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=1 > CONFIG_ENV_VARS_UBOOT_CONFIG=y > CONFIG_USE_BOOTARGS=y > CONFIG_BOOTARGS="console=tty0 console=ttyS0,115200" > +CONFIG_SYS_DEVICE_NULLDEV=y > # CONFIG_DISPLAY_BOARDINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > # CONFIG_CMDLINE_EDITING is not set > @@ -43,6 +44,5 @@ CONFIG_SYS_FLASH_CFI=y > CONFIG_DM_SERIAL=y > CONFIG_PXA_SERIAL=y > CONFIG_USB=y > -CONFIG_USB_STORAGE=y > > Is this deletion intentional? It is not immediately obvious to me how it > relates to > > CONFIG_SYS_DEVICE_NULLDEV getting converted to Kconfig. I suppose this is caused by a resync of the defconfig. > > > Reviewed-by: Ovidiu Panait > > > Thanks! > > Ovidiu > > # CONFIG_REGEX is not set > CONFIG_OF_LIBFDT=y > diff --git a/doc/README.silent b/doc/README.silent > index 6d90a0ec40..00288e03b0 100644 > --- a/doc/README.silent > +++ b/doc/README.silent > @@ -19,7 +19,7 @@ The following actions are taken if "silent" is set at boot > time: > - When the console devices have been initialized, "stdout" and > "stderr" are set to "nulldev", so subsequent messages are > suppressed automatically. Make sure to enable "nulldev" by > - #defining CONFIG_SYS_DEVICE_NULLDEV in your board config file. > + enabling CONFIG_SYS_DEVICE_NULLDEV in your board defconfig file. > > - When booting a linux kernel, the "bootargs" are fixed up so that > the argument "console=" will be in the command line, no matter how > diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h > index de7132940c..1a1a110765 100644 > --- a/include/configs/M5249EVB.h > +++ b/include/configs/M5249EVB.h > @@ -31,8 +31,6 @@ > */ > #undef CONFIG_BOOTP_BOOTFILESIZE > > -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ > - > #define CONFIG_SYS_LOAD_ADDR 0x20 /* default load address */ > > /* > diff --git a/include/configs/colibri_pxa270.h > b/include/configs/colibri_pxa270.h > index 29827f1ee8..3bbef55ec3 100644 > --- a/include/configs/colibri_pxa270.h > +++ b/include/configs/colibri_pxa270.h > @@ -70,8 +70,6 @@ > #define CONFIG_BOOTP_BOOTFILESIZE > #endif > > -#define CONFIG_SYS_DEVICE_NULLDEV 1 > - > /* > * Clock Configuration > */ > diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt > index 1c7946fb65..2da34a5d23 100644 > --- a/scripts/config_whitelist.txt > +++
Re: [PATCH 2/4] dt-bindings: arm: SCMI bindings documentation
On Fri, 17 Jul 2020 at 09:43, Etienne Carriere wrote: > > Dump SCMI DT bindings documentation from Linux kernel source > tree v5.8-rc1. > > Signed-off-by: Etienne Carriere > --- > > doc/device-tree-bindings/arm/arm,scmi.txt | 197 ++ > 1 file changed, 197 insertions(+) > create mode 100644 doc/device-tree-bindings/arm/arm,scmi.txt Reviewed-by: Simon Glass
Re: [PATCH 1/1] test/dm: check if devices exist
Hi,
On Fri, 17 Jul 2020 at 06:41, Philippe REYNES
wrote:
>
> Hi Heinrich
>
> > Running 'ut dm' on the sandbox without -D or -d results in segmentation
> > faults due to NULL pointer dereferences.
> >
> > Check that device pointers are non-NULL before using them.
> >
> > Use ut_assertnonnull() for pointers instead of ut_assert().
>
> Tested-by: Philippe Reynes
>
> > Signed-off-by: Heinrich Schuchardt
> > ---
> > test/dm/acpi.c | 3 +++
> > test/dm/core.c | 10 +-
> > test/dm/devres.c | 1 +
> > test/dm/test-fdt.c | 2 ++
> > test/dm/virtio.c | 7 +++
> > 5 files changed, 18 insertions(+), 5 deletions(-)
> >
> > diff --git a/test/dm/acpi.c b/test/dm/acpi.c
> > index 4c46dd83a6..ece7993cf3 100644
> > --- a/test/dm/acpi.c
> > +++ b/test/dm/acpi.c
> > @@ -96,7 +96,10 @@ DM_TEST(dm_test_acpi_get_table_revision,
> > static int dm_test_acpi_create_dmar(struct unit_test_state *uts)
> > {
> > struct acpi_dmar dmar;
> > + struct udevice *cpu;
> >
> > + ut_assertok(uclass_first_device(UCLASS_CPU, ));
> > + ut_assertnonnull(cpu);
Here the fix should be in acpi_create_dmar() - calling
uclass_first_device_err().
> > ut_assertok(acpi_create_dmar(, DMAR_INTR_REMAP));
> > ut_asserteq(DMAR_INTR_REMAP, dmar.flags);
> > ut_asserteq(32 - 1, dmar.host_address_width);
[...]
Reviewed-by: Simon Glass
Re: [PATCH v2 6/6] mx6cuboxi: enable OF_PLATDATA
On Wed, 22 Jul 2020 at 07:15, Walter Lozano wrote: > > As both MMC and GPIO driver now supports OF_PLATDATA, enable it in > defconfig in order to reduce the SPL footprint. After applying this > setting the SPL reduction is 5 KB, which partially compensates the > increment due to DM. > > Signed-off-by: Walter Lozano > --- > > Changes in v2: > - Improve commit message with footprint reduction > > configs/mx6cuboxi_defconfig | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Simon Glass
Re: [PATCH 2/2] fdt_support: skip MTD node with "disabled" in fdt_fixup_mtdparts()
Hi Masahiro, On Thu, 16 Jul 2020 at 19:36, Masahiro Yamada wrote: > > On Fri, Jul 17, 2020 at 12:44 AM Simon Glass wrote: > > > > On Wed, 15 Jul 2020 at 04:57, Masahiro Yamada > > wrote: > > > > > > Currently, fdt_fixup_mtdparts() only checks the compatible property. > > > It is pointless to fix up the disabled node. > > > > > > Skip the node if it has the property: > > > > > > status = "disabled" > > > > > > Signed-off-by: Masahiro Yamada > > > --- > > > > > > common/fdt_support.c | 17 ++--- > > > 1 file changed, 10 insertions(+), 7 deletions(-) > > > > Reviewed-by: Simon Glass > > > > Are there any tests for this code? > > No test code. > > It makes more effort since > testing this would need to probe an MTD device > as well as parsing DT. > > > > > I am thinking we should migrate fdt_support to use livetree... > > One important thing we should notice is we have > two different DT instances: > > [1] DT blob for U-Boot - used for U-Boot driver model > [2] DT blob for Linux- passed when booting Linux > > > In my understanding, the livetree > is supposed to unflatten [1]. > > fdt_fixup_mtdparts() is obviously fixing [2]. > > > I do not know how livetree would work > for this function. We need an implementation of livetree for [2]. Regards, Simon
Re: [PATCH 3/4] clk: add clock driver for SCMI agents
Hi Etienne,
On Fri, 17 Jul 2020 at 09:43, Etienne Carriere
wrote:
>
> This change introduces a clock driver for SCMI agent devices. When
> SCMI agent and SCMI clock drivers are enabled, SCMI agent binds a
> clock device for each SCMI clock protocol devices enabled in the FDT.
>
> SCMI clock driver is embedded upon CONFIG_CLK_SCMI=y. If enabled,
> CONFIG_SCMI_AGENT is also enabled.
>
> SCMI Clock protocol is defined in the SCMI specification [1].
>
> Links: [1]
> https://developer.arm.com/architectures/system-architectures/software-standards/scmi
That doesn't seem to work for me (404 error)
> Signed-off-by: Etienne Carriere
> ---
>
> drivers/clk/Kconfig | 8 +++
> drivers/clk/Makefile| 1 +
> drivers/clk/clk_scmi.c | 152
> drivers/firmware/scmi.c | 3 +
> 4 files changed, 164 insertions(+)
> create mode 100644 drivers/clk/clk_scmi.c
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 82cb1874e19..234d6035202 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -152,6 +152,14 @@ config CLK_CDCE9XX
>Enable the clock synthesizer driver for CDCE913/925/937/949
>series of chips.
>
> +config CLK_SCMI
> + bool "Enable SCMI clock driver"
> + select SCMI_FIRMWARE
perhaps 'depends on' would be better?
> + help
> + Enable this option if you want to support clock devices exposed
> + by a SCMI agent based on SCMI clock protocol communication
> + with a SCMI server.
> +
> source "drivers/clk/analogbits/Kconfig"
> source "drivers/clk/at91/Kconfig"
> source "drivers/clk/exynos/Kconfig"
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index d9119545810..76bba77d1f0 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -31,6 +31,7 @@ obj-$(CONFIG_CLK_K210) += kendryte/
> obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
> obj-$(CONFIG_CLK_OWL) += owl/
> obj-$(CONFIG_CLK_RENESAS) += renesas/
> +obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
> obj-$(CONFIG_CLK_SIFIVE) += sifive/
> obj-$(CONFIG_ARCH_SUNXI) += sunxi/
> obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
> diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c
> new file mode 100644
> index 000..efe64a6a38f
> --- /dev/null
> +++ b/drivers/clk/clk_scmi.c
> @@ -0,0 +1,152 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019-2020 Linaro Limited
> + */
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +enum scmi_clock_message_id {
> + SCMI_CLOCK_RATE_SET = 0x5,
> + SCMI_CLOCK_RATE_GET = 0x6,
> + SCMI_CLOCK_CONFIG_SET = 0x7,
> +};
> +
> +#define SCMI_CLK_RATE_ASYNC_NOTIFY BIT(0)
> +#define SCMI_CLK_RATE_ASYNC_NORESP (BIT(0) | BIT(1))
> +#define SCMI_CLK_RATE_ROUND_DOWN 0
> +#define SCMI_CLK_RATE_ROUND_UP BIT(2)
> +#define SCMI_CLK_RATE_ROUND_CLOSESTBIT(3)
> +
> +struct scmi_clk_state_in {
> + u32 clock_id;
> + u32 attributes;
> +};
> +
> +struct scmi_clk_state_out {
> + s32 status;
> +};
> +
> +static int scmi_clk_gate(struct clk *clk, int enable)
> +{
> + struct scmi_clk_state_in in = {
> + .clock_id = clk->id,
> + .attributes = enable,
> + };
> + struct scmi_clk_state_out out;
> + struct scmi_msg scmi_msg = {
> + .protocol_id = SCMI_PROTOCOL_ID_CLOCK,
> + .message_id = SCMI_CLOCK_CONFIG_SET,
> + .in_msg = (u8 *),
> + .in_msg_sz = sizeof(in),
> + .out_msg = (u8 *),
> + .out_msg_sz = sizeof(out),
> + };
> + int rc;
Again please use 'ret'.
> +
> + rc = scmi_send_and_process_msg(clk->dev->parent, _msg);
> + if (rc)
> + return rc;
> +
> + return scmi_to_linux_errno(out.status);
> +}
> +
> +static int scmi_clk_enable(struct clk *clk)
> +{
> + return scmi_clk_gate(clk, 1);
> +}
> +
> +static int scmi_clk_disable(struct clk *clk)
> +{
> + return scmi_clk_gate(clk, 0);
> +}
> +
> +struct scmi_clk_rate_get_in {
> + u32 clock_id;
> +};
> +
> +struct scmi_clk_rate_get_out {
> + s32 status;
> + u32 rate_lsb;
> + u32 rate_msb;
> +};
> +
> +static ulong scmi_clk_get_rate(struct clk *clk)
> +{
> + struct scmi_clk_rate_get_in in = {
> + .clock_id = clk->id,
> + };
> + struct scmi_clk_rate_get_out out;
> + struct scmi_msg scmi_msg = {
> + .protocol_id = SCMI_PROTOCOL_ID_CLOCK,
> + .message_id = SCMI_CLOCK_RATE_GET,
> + .in_msg = (u8 *),
> + .in_msg_sz = sizeof(in),
> + .out_msg = (u8 *),
> + .out_msg_sz = sizeof(out),
> + };
> + int rc;
> +
> + rc = scmi_send_and_process_msg(clk->dev->parent, _msg);
> + if (rc)
> + return 0;
Why not rc?
> +
> + rc = scmi_to_linux_errno(out.status);
> + if (rc)
> +
Re: [PATCH v2 2/6] mmc: fsl_esdhc_imx: add OF_PLATDATA support
On Wed, 22 Jul 2020 at 07:14, Walter Lozano wrote: > > In order to reduce the footprint of SPL by removing dtb and library > overhead add OF_PLATDATA support to fsl_esdhc_imx. This initial overhead, add > approach does not support card detection, which will be enabled after > adding OF_PLATDATA support to GPIO. > > Signed-off-by: Walter Lozano > --- > > (no changes since v1) > > drivers/mmc/fsl_esdhc_imx.c | 67 + > 1 file changed, 53 insertions(+), 14 deletions(-) Reviewed-by: Simon Glass
