Aw: [PATCH 11/11] usb: xhci: convet to readx_poll_sleep_timeout()
> Gesendet: Donnerstag, 13. August 2020 um 05:25 Uhr > Von: "Chunfeng Yun" > Betreff: [PATCH 11/11] usb: xhci: convet to readx_poll_sleep_timeout() just a small typo "convet" maybe it can be fixed while applying? regards Frank
Re: [RESEND PATCH v2 09/18] lib: sscanf: add sscanf implementation
On Thu, Aug 6, 2020 at 12:45 PM Anastasiia Lukianenko wrote: > +++ b/lib/sscanf.c > @@ -0,0 +1,823 @@ > +// SPDX-License-Identifier: BSD-3-Clause Hmm... Tom, can you point out to the possibility of using this code in U-Boot? Can we call it from the GPL only code or can it call GPL code (is malloc() GPL? Or what all these #include are doing there? -- With Best Regards, Andy Shevchenko
[PATCH v1 01/10] arm: dts: mt7622: add SATA reset constants
From: Frank Wunderlich add reset constants used for SATA to header file Signed-off-by: Frank Wunderlich --- include/dt-bindings/reset/mt7629-reset.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h index 8f1634f7a6..311a5cb3d0 100644 --- a/include/dt-bindings/reset/mt7629-reset.h +++ b/include/dt-bindings/reset/mt7629-reset.h @@ -6,7 +6,10 @@ #ifndef _DT_BINDINGS_MTK_RESET_H_ #define _DT_BINDINGS_MTK_RESET_H_ -/* PCIe Subsystem resets */ +/* PCIe/SATA Subsystem resets */ +#define MT7622_SATA_PHY_REG_RST12 +#define MT7622_SATA_PHY_SW_RST 13 +#define MT7622_SATA_AXI_BUS_RST15 #define PCIE1_CORE_RST 19 #define PCIE1_MMIO_RST 20 #define PCIE1_HRST 21 -- 2.25.1
[PATCH v1 05/10] clk: mt7622: add needed clocks for ssusb-node
From: Frank Wunderlich
MT7622 needs additional clock definitions to work properly
Signed-off-by: Frank Wunderlich
---
drivers/clk/mediatek/clk-mt7622.c | 42 +++
1 file changed, 42 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt7622.c
b/drivers/clk/mediatek/clk-mt7622.c
index d53ed69189..ebb45498db 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -521,6 +521,20 @@ static const struct mtk_gate_regs sgmii_cg_regs = {
.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
}
+static const struct mtk_gate_regs ssusb_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+#define GATE_SSUSB(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &ssusb_cg_regs, \
+ .shift = _shift,\
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+}
+
static const struct mtk_gate sgmii_cgs[] = {
GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
@@ -528,6 +542,15 @@ static const struct mtk_gate sgmii_cgs[] = {
GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
};
+static const struct mtk_gate ssusb_cgs[] = {
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
+ GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
+ GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
+ GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
+ GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
+};
+
static const struct mtk_clk_tree mt7622_clk_tree = {
.xtal_rate = 25 * MHZ,
.xtal2_rate = 25 * MHZ,
@@ -631,6 +654,11 @@ static int mt7622_sgmiisys_probe(struct udevice *dev)
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
}
+static int mt7622_ssusbsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs);
+}
+
static const struct udevice_id mt7622_apmixed_compat[] = {
{ .compatible = "mediatek,mt7622-apmixedsys" },
{ }
@@ -671,6 +699,11 @@ static const struct udevice_id mt7622_mcucfg_compat[] = {
{ }
};
+static const struct udevice_id mt7622_ssusbsys_compat[] = {
+ { .compatible = "mediatek,mt7622-ssusbsys" },
+ { }
+};
+
U_BOOT_DRIVER(mtk_mcucfg) = {
.name = "mt7622-mcucfg",
.id = UCLASS_SYSCON,
@@ -747,3 +780,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
+
+U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
+ .name = "mt7622-clock-ssusbsys",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_ssusbsys_compat,
+ .probe = mt7622_ssusbsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
--
2.25.1
[PATCH v1 06/10] arm: dts: add watchdog-reboot node for mt7622
From: Frank Wunderlich
adding a wdt-reboot node to mt7622 dtsi
Signed-off-by: Frank Wunderlich
---
arch/arm/dts/mt7622.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index d0783bc9ff..fec071643e 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -142,6 +142,11 @@
reg = <0x10212000 0x800>;
};
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&watchdog>;
+ };
+
gic: interrupt-controller@1030 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.25.1
[PATCH v1 00/10] Add MTK AHCI driver, BPI-R64 dts and USB-Nodes for mt7622/mt7623
From: Frank Wunderlich Hi, i rebased (2020-10-rc2) my latest patches together to make it easier to maintain (dts depencies) Add DTS for BananaPi-R64: https://patchwork.ozlabs.org/project/uboot/list/?series=194922 add SATA/AHCI support for BananaPi R64 (v3) https://patchwork.ozlabs.org/project/uboot/list/?series=195365 Add USB for MT7622/MT7623 https://patchwork.ozlabs.org/project/uboot/list/?series=195547 arm: dts: mt7622: add USB nodes to rfb https://patchwork.ozlabs.org/project/uboot/patch/20200814090425.13533-1-li...@fw-web.de/ they are based on top of this: Add PCIe and its clock support for mt7622 https://patchwork.ozlabs.org/project/uboot/list/?series=194888 and to get USB working (no hard depency, ports get enumerated without it): usb: xhci: add a member hci_version in xhci_ctrl struct https://patchwork.ozlabs.org/project/uboot/list/?series=195331 changes since first Patches: - renamed mt7622-bpi-r64.dts to mt7622-bananapi-bpi-r64.dts - reordered to make code-patches first and then dts-patches - squashed rfb-patch into the mt7622 USB-patch Frank Wunderlich (10): arm: dts: mt7622: add SATA reset constants phy: mtk-tphy: add PHY_TYPE_SATA reset: add basic reset controller for pciesys ahci: mediatek: add ahci driver clk: mt7622: add needed clocks for ssusb-node arm: dts: add watchdog-reboot node for mt7622 arm: dts: add dts for Bananapi-R64 dts: r64: add sata- and asm_sel nodes arm: dts: mt7622: add USB nodes arm: dts: mt7623: add USB nodes arch/arm/dts/Makefile| 1 + arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 223 +++ arch/arm/dts/mt7622-rfb.dts | 8 + arch/arm/dts/mt7622.dtsi | 101 ++ arch/arm/dts/mt7623.dtsi | 46 + arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 ++ drivers/ata/Kconfig | 8 + drivers/ata/Makefile | 1 + drivers/ata/mtk_ahci.c | 130 + drivers/clk/mediatek/clk-mt7622.c| 57 ++ drivers/phy/phy-mtk-tphy.c | 105 +++ include/dt-bindings/reset/mt7629-reset.h | 5 +- 12 files changed, 700 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/mt7622-bananapi-bpi-r64.dts create mode 100644 drivers/ata/mtk_ahci.c -- 2.25.1
[PATCH v1 04/10] ahci: mediatek: add ahci driver
From: Frank Wunderlich
add AHCI driver ported from linux
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/ata/ahci_mtk.c
Signed-off-by: Frank Wunderlich
---
drivers/ata/Kconfig| 8 +++
drivers/ata/Makefile | 1 +
drivers/ata/mtk_ahci.c | 130 +
3 files changed, 139 insertions(+)
create mode 100644 drivers/ata/mtk_ahci.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index d8c9756c2a..f2f8275aec 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -130,4 +130,12 @@ config AHCI_MVEBU
onboard AHCI SATA.
If unsure, say N.
+
+config MTK_AHCI
+ bool "Enable Mediatek AHCI driver support"
+ depends on AHCI
+ help
+ Enable this driver to support Sata devices through
+ Mediatek AHCI controller (e.g. MT7622).
+
endmenu
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index a69edb10f7..98fb480700 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_SATA_SIL) += sata_sil.o
obj-$(CONFIG_SANDBOX) += sata_sandbox.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o
obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o
+obj-$(CONFIG_MTK_AHCI) += mtk_ahci.o
diff --git a/drivers/ata/mtk_ahci.c b/drivers/ata/mtk_ahci.c
new file mode 100644
index 00..8e09c5f9e6
--- /dev/null
+++ b/drivers/ata/mtk_ahci.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * MTK SATA platform driver
+ *
+ * (C) Copyright 2020
+ * Mediatek
+ *
+ * Author: Frank Wunderlich
+ * based on
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/ata/ahci_mtk.c
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SYS_CFG0x14
+#define SYS_CFG_SATA_MSK GENMASK(31, 30)
+#define SYS_CFG_SATA_ENBIT(31)
+
+struct mtk_ahci_priv {
+ void *base;
+
+ struct ahci_uc_priv ahci_priv;
+ struct regmap *mode;
+ struct reset_ctl_bulk rst_bulk;
+};
+
+static int mtk_ahci_bind(struct udevice *dev)
+{
+ struct udevice *scsi_dev;
+
+ return ahci_bind_scsi(dev, &scsi_dev);
+}
+
+static int mtk_ahci_ofdata_to_platdata(struct udevice *dev)
+{
+ struct mtk_ahci_priv *priv = dev_get_priv(dev);
+
+ priv->base = devfdt_remap_addr_index(dev, 0);
+
+ return 0;
+}
+
+static int mtk_ahci_parse_property(struct ahci_uc_priv *hpriv,
+ struct udevice *dev)
+{
+ struct mtk_ahci_priv *plat = dev_get_priv(dev);
+ const void *fdt = gd->fdt_blob;
+
+ /* enable SATA function if needed */
+ if (fdt_get_property(fdt, dev_of_offset(dev),
+"mediatek,phy-mode", NULL)) {
+ plat->mode = syscon_regmap_lookup_by_phandle(dev,
+ "mediatek,phy-mode");
+ if (IS_ERR(plat->mode)) {
+ dev_err(dev, "missing phy-mode phandle\n");
+ return PTR_ERR(plat->mode);
+ }
+ regmap_update_bits(plat->mode, SYS_CFG,
+ SYS_CFG_SATA_MSK, SYS_CFG_SATA_EN);
+ }
+
+ ofnode_read_u32(dev->node, "ports-implemented", &hpriv->port_map);
+ return 0;
+}
+
+static int mtk_ahci_probe(struct udevice *dev)
+{
+ struct mtk_ahci_priv *priv = dev_get_priv(dev);
+ int ret;
+ struct phy phy;
+
+ ret = mtk_ahci_parse_property(&priv->ahci_priv, dev);
+ if (ret)
+ return ret;
+
+ ret = reset_get_bulk(dev, &priv->rst_bulk);
+ if (!ret) {
+ reset_assert_bulk(&priv->rst_bulk);
+ reset_deassert_bulk(&priv->rst_bulk);
+ } else {
+ dev_err(dev, "Failed to get reset: %d\n", ret);
+ }
+
+ ret = generic_phy_get_by_name(dev, "sata-phy", &phy);
+ if (ret) {
+ pr_err("can't get the phy from DT\n");
+ return ret;
+ }
+
+ ret = generic_phy_init(&phy);
+ if (ret) {
+ pr_err("unable to initialize the sata phy\n");
+ return ret;
+ }
+
+ ret = generic_phy_power_on(&phy);
+ if (ret) {
+ pr_err("unable to power on the sata phy\n");
+ return ret;
+ }
+
+ return ahci_probe_scsi(dev, (ulong)priv->base);
+}
+
+static const struct udevice_id mtk_ahci_ids[] = {
+ { .compatible = "mediatek,mtk-ahci" },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_ahci) = {
+ .name = "mtk_ahci",
+ .id = UCLASS_AHCI,
+ .of_match = mtk_ahci_ids,
+ .bind = mtk_ahci_bind,
+ .ofdata_to_platdata = mtk_ahci_ofdata_to_platdata,
+ .ops= &scsi_ops,
+ .probe = mtk_ahci_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_ahci_priv),
+};
--
2.25.1
[PATCH v1 03/10] reset: add basic reset controller for pciesys
From: Frank Wunderlich
bind reset controller to pciesys
Signed-off-by: Frank Wunderlich
---
drivers/clk/mediatek/clk-mt7622.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt7622.c
b/drivers/clk/mediatek/clk-mt7622.c
index bd86b5b974..d53ed69189 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -594,6 +594,20 @@ static int mt7622_pciesys_probe(struct udevice *dev)
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs);
}
+static int mt7622_pciesys_bind(struct udevice *dev)
+{
+ int ret = 0;
+
+ if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
+// PCIESYS uses in linux also 0x34 = ETHSYS reset controller
+ ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+ if (ret)
+ debug("Warning: failed to bind reset controller\n");
+ }
+
+ return ret;
+}
+
static int mt7622_ethsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
@@ -710,6 +724,7 @@ U_BOOT_DRIVER(mtk_clk_pciesys) = {
.id = UCLASS_CLK,
.of_match = mt7622_pciesys_compat,
.probe = mt7622_pciesys_probe,
+ .bind = mt7622_pciesys_bind,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
--
2.25.1
[PATCH v1 02/10] phy: mtk-tphy: add PHY_TYPE_SATA
From: Frank Wunderlich
add support for PHY_TYPE_SATA to Mediateks TPHY driver
Signed-off-by: Frank Wunderlich
Reviewed-by: Chunfeng Yun
---
drivers/phy/phy-mtk-tphy.c | 105 +
1 file changed, 105 insertions(+)
diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c
index 1e65c24356..326227a30d 100644
--- a/drivers/phy/phy-mtk-tphy.c
+++ b/drivers/phy/phy-mtk-tphy.c
@@ -175,6 +175,65 @@
#define XC3_RG_U3_XTAL_RX_PWD BIT(9)
#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
+/* SATA register setting */
+#define PHYD_CTRL_SIGNAL_MODE4 0x1c
+/* CDR Charge Pump P-path current adjustment */
+#define RG_CDR_BICLTD1_GEN1_MSKGENMASK(23, 20)
+#define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20)
+#define RG_CDR_BICLTD0_GEN1_MSKGENMASK(11, 8)
+#define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8)
+
+#define PHYD_DESIGN_OPTION20x24
+/* Symbol lock count selection */
+#define RG_LOCK_CNT_SEL_MSKGENMASK(5, 4)
+#define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4)
+
+#define PHYD_DESIGN_OPTION90x40
+/* COMWAK GAP width window */
+#define RG_TG_MAX_MSK GENMASK(20, 16)
+#define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16)
+/* COMINIT GAP width window */
+#define RG_T2_MAX_MSK GENMASK(13, 8)
+#define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8)
+/* COMWAK GAP width window */
+#define RG_TG_MIN_MSK GENMASK(7, 5)
+#define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5)
+/* COMINIT GAP width window */
+#define RG_T2_MIN_MSK GENMASK(4, 0)
+#define RG_T2_MIN_VAL(x) (0x1f & (x))
+
+#define ANA_RG_CTRL_SIGNAL10x4c
+/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
+#define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8)
+#define RG_IDRV_0DB_GEN1_VAL(x)((0x3f & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL40x58
+#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20)
+#define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20)
+/* Loop filter R1 resistance adjustment for Gen1 speed */
+#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8)
+#define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL60x60
+/* I-path capacitance adjustment for Gen1 */
+#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24)
+#define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24)
+#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0)
+#define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x))
+
+#define ANA_EQ_EYE_CTRL_SIGNAL10x6c
+/* RX Gen1 LEQ tuning step */
+#define RG_EQ_DLEQ_LFI_GEN1_MSKGENMASK(11, 8)
+#define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL40xd8
+#define RG_CDR_BIRLTD0_GEN1_MSKGENMASK(20, 16)
+#define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL50xdc
+#define RG_CDR_BIRLTD0_GEN3_MSKGENMASK(4, 0)
+#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x))
+
enum mtk_phy_version {
MTK_TPHY_V1 = 1,
MTK_TPHY_V2,
@@ -372,6 +431,45 @@ static void pcie_phy_instance_init(struct mtk_tphy *tphy,
udelay(3000);
}
+static void sata_phy_instance_init(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
+
+ clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL6,
+ RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK,
+ RG_CDR_BIRLTR_GEN1_VAL(0x6) |
+ RG_CDR_BC_GEN1_VAL(0x1a));
+ clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL4,
+ RG_CDR_BIRLTD0_GEN1_MSK,
+ RG_CDR_BIRLTD0_GEN1_VAL(0x18));
+ clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL5,
+ RG_CDR_BIRLTD0_GEN3_MSK,
+ RG_CDR_BIRLTD0_GEN3_VAL(0x06));
+ clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL4,
+ RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK,
+ RG_CDR_BICLTR_GEN1_VAL(0x0c) |
+ RG_CDR_BR_GEN2_VAL(0x07));
+ clrsetbits_le32(u3_banks->phyd + PHYD_CTRL_SIGNAL_MODE4,
+ RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK,
+ RG_CDR_BICLTD0_GEN1_VAL(0x08) |
+ RG_CDR_BICLTD1_GEN1_VAL(0x02));
+ clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION2,
+ RG_LOCK_CNT_SEL_MSK,
+ RG_LOCK_CNT_SEL_VAL(0x02));
+ clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION9,
+ RG_T2_MIN_MSK | RG_TG_MIN_MSK |
+ RG_T2_MAX_MSK | RG_TG_MAX_MSK,
+ RG_T2_MIN_VAL(0
[PATCH v1 09/10] arm: dts: mt7622: add USB nodes
From: Frank Wunderlich
Add DTS nodes for MT7622/BPI-R64
Signed-off-by: Frank Wunderlich
---
v1->v2:
- add USB nodes to MT7622 reference board
---
arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 8 +++
arch/arm/dts/mt7622-rfb.dts | 8 +++
arch/arm/dts/mt7622.dtsi | 64
3 files changed, 80 insertions(+)
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
index c36ec8f8d0..7cd581cf7d 100644
--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
@@ -213,3 +213,11 @@
output-low;
};
};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
index 317fc78abd..ef7d0f0270 100644
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -222,3 +222,11 @@
full-duplex;
};
};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index c43ad65702..c69f9d7d73 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -81,6 +81,12 @@
#clock-cells = <0>;
};
+ clk25m: dummy25m {
+ compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ #clock-cells = <0>;
+ };
+
infracfg: infracfg@1000 {
compatible = "mediatek,mt7622-infracfg",
"syscon";
@@ -192,6 +198,14 @@
status = "disabled";
};
+ ssusbsys: ssusbsys@1a00 {
+ compatible = "mediatek,mt7622-ssusbsys",
+"syscon";
+ reg = <0x1a00 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0x1a100800 0x1000>;
@@ -302,6 +316,56 @@
};
};
+ ssusb: usb@1a0c {
+ compatible = "mediatek,mt7622-xhci",
+"mediatek,mtk-xhci";
+ reg = <0x1a0c 0x01000>,
+ <0x1a0c4700 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = ;
+ power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
+ clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
+<&ssusbsys CLK_SSUSB_REF_EN>,
+<&ssusbsys CLK_SSUSB_MCU_EN>,
+<&ssusbsys CLK_SSUSB_DMA_EN>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
+ status = "disabled";
+ };
+
+ u3phy: usb-phy@1a0c4000 {
+ compatible = "mediatek,mt7622-u3phy",
+"mediatek,generic-tphy-v1";
+ reg = <0x1a0c4000 0x700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy@1a0c4800 {
+ reg = <0x1a0c4800 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
+ clock-names = "ref";
+ };
+
+ u3port0: usb-phy@1a0c4900 {
+ reg = <0x1a0c4900 0x0700>;
+ #phy-cells = <1>;
+ clocks = <&clk25m>;
+ clock-names = "ref";
+ };
+
+ u2port1: usb-phy@1a0c5000 {
+ reg = <0x1a0c5000 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
+ clock-names = "ref";
+ };
+ };
+
ethsys: syscon@1b00 {
compatible = "mediatek,mt7622-ethsys", "syscon";
reg = <0x1b00 0x1000>;
--
2.25.1
[PATCH v1 10/10] arm: dts: mt7623: add USB nodes
From: Frank Wunderlich
This adds USB nodes for MT7623/BPI-R2
Signed-off-by: Frank Wunderlich
---
arch/arm/dts/mt7623.dtsi | 46
arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 +
2 files changed, 62 insertions(+)
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 0452889ef8..e753e08545 100644
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -352,6 +352,52 @@
};
};
+ usb1: usb@1a1c {
+ compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
+ reg = <0x1a1c 0x1000>, <0x1a1c4700 0x0100>;
+ reg-names = "mac", "ippc";
+ power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+ clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen
CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "ref_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
+ u3phy1: usb-phy1@1a1c4000 {
+ compatible = "mediatek,mt7623-tphy", "mediatek,generic-tphy-v1";
+
+ reg = <0x1a1c4000 0x0700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy@1a1c4800 {
+ reg = <0x1a1c4800 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ };
+
+ u3port0: usb-phy@1a1c4900 {
+ reg = <0x1a1c4900 0x0700>;
+ #phy-cells = <1>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ };
+ };
+
+ usb2: usb@1a24 {
+ compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
+ reg = <0x1a24 0x1000>, <0x1a244700 0x0100>;
+ reg-names = "mac", "ippc";
+ power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+ clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen
CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "ref_ck";
+ phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
u3phy2: usb-phy@1a244000 {
compatible = "mediatek,generic-tphy-v1";
reg = <0x1a244000 0x0700>;
diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
index bcedcf20f1..ef07369627 100644
--- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
@@ -248,3 +248,19 @@
pinctrl-0 = <&uart2_pins_a>;
status = "okay";
};
+
+&usb1 {
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&u3phy2 {
+ status = "okay";
+};
--
2.25.1
[PATCH v1 07/10] arm: dts: add dts for Bananapi-R64
From: Frank Wunderlich
add a separate DTS for BananaPi R64 because it has 1GB RAM and SATA-Support
Signed-off-by: Frank Wunderlich
---
v1->v2:
- changed name
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 206 +++
2 files changed, 207 insertions(+)
create mode 100644 arch/arm/dts/mt7622-bananapi-bpi-r64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8ecf63e988..ff0e76f808 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -959,6 +959,7 @@ dtb-$(CONFIG_SOC_K3_J721E) +=
k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
+ mt7622-bananapi-bpi-r64.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
new file mode 100644
index 00..768f15bc2c
--- /dev/null
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih
+ */
+
+/dts-v1/;
+#include "mt7622.dtsi"
+#include "mt7622-u-boot.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "mt7622-bpi-r64";
+ compatible = "mediatek,mt7622", "mediatek,mt7622-rfb";
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer0;
+ };
+
+ aliases {
+ spi0 = &snfi;
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0x4000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+
+&pinctrl {
+ snfi_pins: snfi-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ snor_pins: snor-pins {
+ mux {
+ function = "flash";
+ groups = "spi_nor";
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_tx_rx" ;
+ };
+ };
+
+ pwm_pins: pwm1 {
+ mux {
+ function = "pwm";
+ groups = "pwm_ch1_0" ;
+ };
+ };
+
+ watchdog_pins: watchdog-default {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "emmc";
+ groups = "emmc";
+ };
+
+ /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
+* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
+* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
+*/
+ conf-cmd-dat {
+ pins = "NDL0", "NDL1", "NDL2",
+ "NDL3", "NDL4", "NDL5",
+ "NDL6", "NDL7", "NRB";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "NCLE";
+ bias-pull-down;
+ };
+
+ };
+
+ mmc1_pins_default: mmc1default {
+ mux {
+ function = "sd";
+ groups = "sd_0";
+ };
+ /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
+* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
+* DAT2, DAT3, CMD, CLK for SD respectively.
+*/
+ conf-cmd-data {
+ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+ "I2S2_IN","I2S4_OUT";
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ conf-clk {
+ pins = "I2S3_OUT";
+ drive-strength = <12>;
+ bias-pull-down;
+ };
+ conf-cd {
+ pins = "TXD3";
+ bias-pull-up
[PATCH v1 08/10] dts: r64: add sata- and asm_sel nodes
From: Frank Wunderlich
asm_sel is for switching between sata and pcie mode
on r64 there is GPIO90 connected to ASM1480 which
switches RX/TX pairs to PCIe/SATA connector
output-low means sata-controller is active
with 2020-10 now reg is also needed for the phy itself
Signed-off-by: Frank Wunderlich
---
arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 9 +++
arch/arm/dts/mt7622.dtsi | 32
2 files changed, 41 insertions(+)
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
index 768f15bc2c..c36ec8f8d0 100644
--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
@@ -204,3 +204,12 @@
full-duplex;
};
};
+
+&gpio {
+ /*gpio 90 for setting mode to sata*/
+ asm_sel {
+ gpio-hog;
+ gpios = <90 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+};
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index fec071643e..c43ad65702 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
/ {
compatible = "mediatek,mt7622";
@@ -270,6 +271,37 @@
};
};
+ sata: sata@1a20 {
+ compatible = "mediatek,mtk-ahci";
+ reg = <0x1a20 0x1100>;
+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+ <&pciesys MT7622_SATA_PHY_SW_RST>,
+ <&pciesys MT7622_SATA_PHY_REG_RST>;
+ reset-names = "axi", "sw", "reg";
+ mediatek,phy-mode = <&pciesys>;
+ ports-implemented = <0x1>;
+ phys = <&sata_port PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ status = "okay";
+ };
+
+ sata_phy: sata-phy@1a243000 {
+ compatible = "mediatek,generic-tphy-v1";
+ reg = <0x1a243000 0x0100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "okay";
+
+ sata_port: sata-phy@1a243000 {
+ reg = <0x1a243000 0x0100>;
+ clocks = <&topckgen CLK_TOP_ETH_500M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
ethsys: syscon@1b00 {
compatible = "mediatek,mt7622-ethsys", "syscon";
reg = <0x1b00 0x1000>;
--
2.25.1
Re: [PATCH 1/1] riscv: riscv_get_time() implementation for SMODE
On 8/15/20 5:55 PM, Anup Patel wrote:
> On Sat, Aug 15, 2020 at 8:37 PM Heinrich Schuchardt
> wrote:
>>
>> Am 15. August 2020 16:06:41 MESZ schrieb Anup Patel :
>>> On Sat, Aug 15, 2020 at 12:57 AM Heinrich Schuchardt
>>> wrote:
On 8/14/20 8:38 PM, Anup Patel wrote:
> On Fri, Aug 14, 2020 at 11:35 PM Heinrich Schuchardt
>>> wrote:
>>
>> On 14.08.20 19:52, Anup Patel wrote:
>>> On Fri, Aug 14, 2020 at 11:15 PM Heinrich Schuchardt
>>> wrote:
On the Kendryte K210 OpenBSI cannot emulate the rdtime
>>> instruction. So we
have to use the Sifive CLINT driver to provide riscv_get_time()
>>> in SMODE.
>>>
>>> Can you elaborate why ?
>>>
>>> The rdtime instruction should generate an illegal instruction
>>> fault which
>>> OpenSBI will emulate.
>>
>> The RISC-V Instruction Set Manual Volume II Privileged architectur
>>> 1.11
>> has incompatible changes relative to version 1.9.1
>>
>> mtval on the Kendryte K210 delivers the bad virtual address and
>>> not the
>> instruction:
>
> Ahh, I see. The MTVAL CSR is actually legacy MBADADDR CSR and this
> CSR.
>
> The S-mode software always has working rdtime instruction for all
> RISC-V systems. If HW does not implement TIME CSR then OpenSBI
> emulates it. Please don't break this convention for U-Boot S-mode
> because we do have RISC-V systems where TIME CSR is implemeted
> in HW so this will patch will break U-Boot S-mode system because
> on those system we are supposed to use TIME CSR from S-mode.
This patch does not change anything for existing systems. It only
>>> allows
me to customize U-Boot for the K210 differently. I understand that
fixing OpenSBI is a better approach.
>>>
>>> Currently, on most RISC-V systems the CLINT timer interrupts and IPI
>>> interrupts are hard-wired to M-mode timer and software interrupt lines.
>>> In other words, the CLINT is integrated as M-mode only device on most
>>> RISC-V systems.
>>>
>>> Due to above reason, CLINT driver is M-mode only driver for Linux
>>> kernel
>>>
>>> The Linux S-mode will use:
>>> 1. TIME CSR as free running counter
>>> 2. SBI calls for timer interrupts
>>> 3. SBI calls for injecting IPIs
>>>
>>> For #1 above, the M-mode firmware will trap-n-emulate TIME CSR
>>> for S-mode if HW does not implement TIME CSR.
>>>
>>> Based on above mentioned convention, the U-Boot CLINT driver
>>> should be M-mode only and U-Boot S-mode should use TIME CSR
>>> as a free running counter.
>>>
>
>>
>> lib/sbi/sbi_illegal_insn.c(123) sbi_illegal_insn_handler:
>> insn 0x4114121602, epc 0x8058c168.
>>
>> The illegal instruction being
>> c01027f3rdtime a5
>>
>> In the long run it may make sense to provide backwards
>>> compatibility in
>> OpenSBI.
>
> Yes, let's try to explore possible fixes in OpenSBI.
>
> Instead of this patch, try the following change in OpenSBI ...
>
> diff --git a/lib/sbi/sbi_illegal_insn.c
>>> b/lib/sbi/sbi_illegal_insn.c
> index 0e5523f..c8f2e4a 100644
> --- a/lib/sbi/sbi_illegal_insn.c
> +++ b/lib/sbi/sbi_illegal_insn.c
> @@ -119,12 +119,10 @@ int sbi_illegal_insn_handler(ulong insn,
>>> struct
> sbi_trap_regs *regs)
> struct sbi_trap_info uptrap;
>
> if (unlikely((insn & 3) != 3)) {
Why do put sbi_get_insn() behind this if and not before it?
>>>
>>> Currently, OpenSBI only deals with 32bit (or longer) illegal
>>> instructions. If we see insn == 0 OR insn is 16bit then we
>>> double-check instruction encoding using unprivileged access.
>>>
>>> The PC in RISC-V is always 2-byte aligned address so if MTVAL
>>> has fault instruction address instead of instruction encoding then
>>> "(insn & 3) != 3" will be TRUE and we will be forced to double-check.
>>> The "insn == 0" check below is causing problem RISC-V v1.9 spec
>>> (i.e. MTVAL having instruction address) and it is totally harmless to
>>> remove the "insn == 0" check for RISC-V v1.10 (or higher) hence
>>> my suggestion to remove the check.
>>>
>>
>> Thank you for your detailed explanation. Maybe you can add a comment to the
>> code.
>
> Sure will do.
>
>>
> - if (insn == 0) {
> - insn = sbi_get_insn(regs->mepc, &uptrap);
> - if (uptrap.cause) {
> - uptrap.epc = regs->mepc;
> - return sbi_trap_redirect(regs,
>>> &uptrap);
> - }
> + insn = sbi_get_insn(regs->mepc, &uptrap);
> + if (uptrap.cause) {
> + uptrap.epc = regs->mepc;
> + return sbi_trap_redirect(regs, &uptrap);
> }
> if ((insn & 3) != 3)
> return truly_illegal_insn(insn, regs);
>
For this
[PATCH 1/1] doc: update UEFI documentation
* UEFI variables can be persisted
* describe that the sequence of files loaded before bootefi matters
Signed-off-by: Heinrich Schuchardt
---
doc/uefi/uefi.rst | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/doc/uefi/uefi.rst b/doc/uefi/uefi.rst
index a72e729cc8..728f7bf4e0 100644
--- a/doc/uefi/uefi.rst
+++ b/doc/uefi/uefi.rst
@@ -59,6 +59,10 @@ Below you find the output of an example session starting
GRUB::
120832 bytes read in 7 ms (16.5 MiB/s)
=> bootefi ${kernel_addr_r} ${fdt_addr_r}
+The bootefi command uses the device, the file name, and the file size
+(environment variable 'filesize') of the most recently loaded file when setting
+up the binary for execution. So the UEFI binary should be loaded last.
+
The environment variable 'bootargs' is passed as load options in the UEFI
system
table. The Linux kernel EFI stub uses the load options as command line
arguments.
@@ -217,13 +221,13 @@ which has to be enabled via CONFIG_SUPPORT_EMMC_RPMB=y.
Executing the boot manager
~~
-The UEFI specification foresees to define boot entries and boot sequence via
UEFI
-variables. Booting according to these variables is possible via::
+The UEFI specification foresees to define boot entries and boot sequence via
+UEFI variables. Booting according to these variables is possible via::
bootefi bootmgr [fdt address]
-As of U-Boot v2018.03 UEFI variables are not persisted and cannot be set at
-runtime.
+As of U-Boot v2020.10 UEFI variables cannot be set at runtime. The U-Boot
+command 'efidebug' can be used to set the variables.
Executing the built in hello world application
~~
--
2.28.0
[Xilinx Zynq]: spurious UART receive on startup
Hi,
I am running into a problem with U-Boot v2020.07 on Xilinx Zynq
(Zedboard). If I build U-Boot with the default config
(xilinx_zynq_virt_defconfig, DEVICE_TREE=zynq-zed), autoboot will abort,
even if no key is pressed. This happens regardless of whether the USB
UART is even connected to a PC.
I am using boot.bin as generated by U-Boot as the SPL (plus u-boot.img
for U-Boot proper).
While debugging this, I noticed two things:
1. The Zynq TRM [1] notes in section 19.2.3 ("Baud generator"):
IMPORTANT: It is essential to disable the transmitter and receiver
before writing to the Baud Rate Generator register
(uart.Baud_rate_gen_reg0), or the baud rate divider register
(uart.Baud_rate_divider_reg0). A soft reset must be issued to both
the transmitter and receiver before they are re-enabled.
However, the code in _uart_zynq_serial_setbrg() (in
drivers/serial/serial_zynq.c) does not seem to do that.
2. It seems that the Zynq BootROM actually touches the registers for
UART1. I have no idea why it does that, but table 6-22 ("BootROM
Modified Registers") in the TRM lists several UART1 registers that have
been modified from their reset value. In particular, the control
register at 0xE0001000 contains the value 0x0114 after the BootROM ran.
As zynq_serial_probe() checks if TX is enabled (bit 4 in the control
register), and only writes to the control register if it is not, the end
result is that U-Boot never really initializes UART1 or resets its TX or
RX path.
If the debug UART functionality (CONFIG_DEBUG_UART_ZYNQ) is enabled,
_debug_uart_init() writes to the control register unconditionally and
resets the TX/RX path. Indeed, enabling the debug UART functionality
makes my problem disappear. The debug UART was enabled by default in
zynq_zed_defconfig (in v2019.10), but this changed when switching to a
single Zynq configuration (xilinx_zynq_virt_defconfig) for v2020.07.
Note that the above workaround fixes the problem for me, but I wanted to
report it in case other people run into the same issue.
Best regards,
Norbert
[1]:
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
[PATCH] net: smc911x: Automatically Update ethaddr with MAC
The ethernet controller can read the MAC from EEPROM and display it,
but if ethaddr is not set, the ethernet is still unavailable.
This patch checks will automatically set the MAC address if it has
not already been set.
Signed-off-by: Adam Ford
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 9c5dc46483..f028bfba18 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -6,6 +6,7 @@
*/
#include
+#include
#include
#include
#include
@@ -185,6 +186,8 @@ static void smc911x_handle_mac_address(struct smc911x_priv
*priv)
smc911x_set_mac_csr(priv, ADDRH, addrh);
printf(DRIVERNAME ": MAC %pM\n", m);
+ if (!env_get("ethaddr"))
+ env_set("fdt_file", (const char *)m);
}
static bool smc911x_read_mac_address(struct smc911x_priv *priv)
--
2.25.1
[PATCH 1/1] cmd: provide command sbi
Provide a command to display information about the SBI implementation.
The output might look like:
=> sbi
SBI 0.2
OpenSBI
Extensions:
sbi_set_timer
sbi_console_putchar
sbi_console_getchar
sbi_clear_ipi
sbi_send_ipi
sbi_remote_fence_i
sbi_remote_sfence_vma
sbi_remote_sfence_vma_asid
sbi_shutdown
SBI Base Functionality
Timer Extension
IPI Extension
RFENCE Extension
Hart State Management Extension
The command can be used to construct a unit test checking that the
communication with the SEE is working.
Signed-off-by: Heinrich Schuchardt
---
arch/riscv/include/asm/sbi.h | 2 +
arch/riscv/lib/sbi.c | 36
cmd/Kconfig | 6 +++
cmd/riscv/Makefile | 1 +
cmd/riscv/sbi.c | 80
5 files changed, 125 insertions(+)
create mode 100644 cmd/riscv/sbi.c
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 08e1ac0c0e..53ca316180 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -115,6 +115,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long
*hart_mask,
unsigned long asid);
#endif
void sbi_set_timer(uint64_t stime_value);
+long sbi_get_spec_version(void);
+int sbi_get_impl_id(void);
int sbi_probe_extension(int ext);
#endif
diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
index 8fbc23839d..920889ed13 100644
--- a/arch/riscv/lib/sbi.c
+++ b/arch/riscv/lib/sbi.c
@@ -53,6 +53,42 @@ void sbi_set_timer(uint64_t stime_value)
#endif
}
+/**
+ * sbi_get_spec_version() - get current SBI specification version
+ *
+ * Return: version id
+ */
+long sbi_get_spec_version(void)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION,
+ 0, 0, 0, 0, 0, 0);
+ if (!ret.error)
+ if (ret.value)
+ return ret.value;
+
+ return -ENOTSUPP;
+}
+
+/**
+ * sbi_get_impl_id() - get SBI implemenation ID
+ *
+ * Return: implementation ID
+ */
+int sbi_get_impl_id(void)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID,
+ 0, 0, 0, 0, 0, 0);
+ if (!ret.error)
+ if (ret.value)
+ return ret.value;
+
+ return -ENOTSUPP;
+}
+
/**
* sbi_probe_extension() - Check if an SBI extension ID is supported or not.
* @extid: The extension ID to be probed.
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 23d7e27dc8..7a9fab51c5 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -270,6 +270,12 @@ config SPL_CMD_TLV_EEPROM
help
Read system EEPROM data block in ONIE Tlvinfo format from SPL.
+config CMD_SBI
+ bool "SBI information"
+ depends on RISCV_SMODE
+ help
+ Display information about the SBI implementation.
+
endmenu
menu "Boot commands"
diff --git a/cmd/riscv/Makefile b/cmd/riscv/Makefile
index 24df023ece..1e6ac364e3 100644
--- a/cmd/riscv/Makefile
+++ b/cmd/riscv/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_CMD_EXCEPTION) += exception.o
+obj-$(CONFIG_CMD_SBI) += sbi.o
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
new file mode 100644
index 00..559d950ffb
--- /dev/null
+++ b/cmd/riscv/sbi.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'sbi' command displays information about the SBI implementation.
+ *
+ * Copyright (c) 2020, Heinrich Schuchardt
+ */
+
+#include
+#include
+#include
+
+struct sbi_ext {
+ const u32 id;
+ const char *name;
+};
+
+static struct sbi_ext extensions[] = {
+ { 0x, "sbi_set_timer" },
+ { 0x0001, "sbi_console_putchar" },
+ { 0x0002, "sbi_console_getchar" },
+ { 0x0003, "sbi_clear_ipi" },
+ { 0x0004, "sbi_send_ipi" },
+ { 0x0005, "sbi_remote_fence_i" },
+ { 0x0006, "sbi_remote_sfence_vma" },
+ { 0x0007, "sbi_remote_sfence_vma_asid" },
+ { 0x0008, "sbi_shutdown" },
+ { 0x0010, "SBI Base Functionality" },
+ { 0x54494D45, "Timer Extension" },
+ { 0x00735049, "IPI Extension" },
+ { 0x52464E43, "RFENCE Extension" },
+ { 0x0048534D, "Hart State Management Extension" },
+};
+
+static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int i;
+ long ret;
+
+ ret = sbi_get_spec_version();
+ if (ret >= 0)
+ printf("SBI %ld.%ld\n", ret >> 24, ret &0xff);
+ ret = sbi_get_impl_id();
+ if (ret >= 0) {
+ switch (ret) {
+ case 0:
+ printf("Berkeley Boot Loader (BBL)\n");
+ break;
+ case 1:
+ printf("OpenSBI\n");
+ break;
+ case 2:
+ printf("Xvisor\n");
+ break;
+
Re: [PATCH 1/1] riscv: riscv_get_time() implementation for SMODE
On Sun, Aug 16, 2020 at 3:49 PM Heinrich Schuchardt wrote:
>
> On 8/15/20 5:55 PM, Anup Patel wrote:
> > On Sat, Aug 15, 2020 at 8:37 PM Heinrich Schuchardt
> > wrote:
> >>
> >> Am 15. August 2020 16:06:41 MESZ schrieb Anup Patel :
> >>> On Sat, Aug 15, 2020 at 12:57 AM Heinrich Schuchardt
> >>> wrote:
>
> On 8/14/20 8:38 PM, Anup Patel wrote:
> > On Fri, Aug 14, 2020 at 11:35 PM Heinrich Schuchardt
> >>> wrote:
> >>
> >> On 14.08.20 19:52, Anup Patel wrote:
> >>> On Fri, Aug 14, 2020 at 11:15 PM Heinrich Schuchardt
> >>> wrote:
>
> On the Kendryte K210 OpenBSI cannot emulate the rdtime
> >>> instruction. So we
> have to use the Sifive CLINT driver to provide riscv_get_time()
> >>> in SMODE.
> >>>
> >>> Can you elaborate why ?
> >>>
> >>> The rdtime instruction should generate an illegal instruction
> >>> fault which
> >>> OpenSBI will emulate.
> >>
> >> The RISC-V Instruction Set Manual Volume II Privileged architectur
> >>> 1.11
> >> has incompatible changes relative to version 1.9.1
> >>
> >> mtval on the Kendryte K210 delivers the bad virtual address and
> >>> not the
> >> instruction:
> >
> > Ahh, I see. The MTVAL CSR is actually legacy MBADADDR CSR and this
> > CSR.
> >
> > The S-mode software always has working rdtime instruction for all
> > RISC-V systems. If HW does not implement TIME CSR then OpenSBI
> > emulates it. Please don't break this convention for U-Boot S-mode
> > because we do have RISC-V systems where TIME CSR is implemeted
> > in HW so this will patch will break U-Boot S-mode system because
> > on those system we are supposed to use TIME CSR from S-mode.
>
> This patch does not change anything for existing systems. It only
> >>> allows
> me to customize U-Boot for the K210 differently. I understand that
> fixing OpenSBI is a better approach.
> >>>
> >>> Currently, on most RISC-V systems the CLINT timer interrupts and IPI
> >>> interrupts are hard-wired to M-mode timer and software interrupt lines.
> >>> In other words, the CLINT is integrated as M-mode only device on most
> >>> RISC-V systems.
> >>>
> >>> Due to above reason, CLINT driver is M-mode only driver for Linux
> >>> kernel
> >>>
> >>> The Linux S-mode will use:
> >>> 1. TIME CSR as free running counter
> >>> 2. SBI calls for timer interrupts
> >>> 3. SBI calls for injecting IPIs
> >>>
> >>> For #1 above, the M-mode firmware will trap-n-emulate TIME CSR
> >>> for S-mode if HW does not implement TIME CSR.
> >>>
> >>> Based on above mentioned convention, the U-Boot CLINT driver
> >>> should be M-mode only and U-Boot S-mode should use TIME CSR
> >>> as a free running counter.
> >>>
>
> >
> >>
> >> lib/sbi/sbi_illegal_insn.c(123) sbi_illegal_insn_handler:
> >> insn 0x4114121602, epc 0x8058c168.
> >>
> >> The illegal instruction being
> >> c01027f3rdtime a5
> >>
> >> In the long run it may make sense to provide backwards
> >>> compatibility in
> >> OpenSBI.
> >
> > Yes, let's try to explore possible fixes in OpenSBI.
> >
> > Instead of this patch, try the following change in OpenSBI ...
> >
> > diff --git a/lib/sbi/sbi_illegal_insn.c
> >>> b/lib/sbi/sbi_illegal_insn.c
> > index 0e5523f..c8f2e4a 100644
> > --- a/lib/sbi/sbi_illegal_insn.c
> > +++ b/lib/sbi/sbi_illegal_insn.c
> > @@ -119,12 +119,10 @@ int sbi_illegal_insn_handler(ulong insn,
> >>> struct
> > sbi_trap_regs *regs)
> > struct sbi_trap_info uptrap;
> >
> > if (unlikely((insn & 3) != 3)) {
>
> Why do put sbi_get_insn() behind this if and not before it?
> >>>
> >>> Currently, OpenSBI only deals with 32bit (or longer) illegal
> >>> instructions. If we see insn == 0 OR insn is 16bit then we
> >>> double-check instruction encoding using unprivileged access.
> >>>
> >>> The PC in RISC-V is always 2-byte aligned address so if MTVAL
> >>> has fault instruction address instead of instruction encoding then
> >>> "(insn & 3) != 3" will be TRUE and we will be forced to double-check.
> >>> The "insn == 0" check below is causing problem RISC-V v1.9 spec
> >>> (i.e. MTVAL having instruction address) and it is totally harmless to
> >>> remove the "insn == 0" check for RISC-V v1.10 (or higher) hence
> >>> my suggestion to remove the check.
> >>>
> >>
> >> Thank you for your detailed explanation. Maybe you can add a comment to
> >> the code.
> >
> > Sure will do.
> >
> >>
>
> > - if (insn == 0) {
> > - insn = sbi_get_insn(regs->mepc, &uptrap);
> > - if (uptrap.cause) {
> > - uptrap.epc = regs->mepc;
> > - return sbi_trap_redirect(regs,
> >>> &uptrap);
> > - }
> > + insn = sbi_get_insn(regs->mepc, &uptrap);
> >
Re: Aw: [PATCH 11/11] usb: xhci: convet to readx_poll_sleep_timeout()
On Sun, 2020-08-16 at 09:56 +0200, Frank Wunderlich wrote: > > Gesendet: Donnerstag, 13. August 2020 um 05:25 Uhr > > Von: "Chunfeng Yun" > > Betreff: [PATCH 11/11] usb: xhci: convet to readx_poll_sleep_timeout() > > just a small typo "convet" Will fix it, thanks > > maybe it can be fixed while applying? > > regards Frank
Re: Aw: [PATCH 03/11] usb: xhci: add quirks flag to support MediaTek xHCI 0.96
On Thu, 2020-08-13 at 12:35 +0200, Frank Wunderlich wrote: > > Gesendet: Donnerstag, 13. August 2020 um 05:25 Uhr > > Von: "Chunfeng Yun" > > Betreff: [PATCH 03/11] usb: xhci: add quirks flag to support MediaTek xHCI > > 0.96 > > > > There some vendor quirks for MTK xHCI 0.96 host controller: > > 1. It defines some extra SW scheduling parameters for HW > >to minimize the scheduling effort for synchronous and > >interrupt endpoints. The parameters are put into reseved > >DWs of slot context and endpoint context. > > 2. Its TDS in Normal TRB defines a number of packets that > >remains to be transferred for a TD after processing all > >Max packets in all previous TRBs. > > Tested full series on Bananapi-R2 and R64 (can post DTS-nodes later or can be > found here [1]) > > BPI-R2> usb start > starting USB... > Bus usb@1a1c: hcd: 0x1a1c, ippc: 0x1a1c4700 > u2p:1, u3p:1 > Register 200010f NbrPorts 2 > Starting the controller > USB XHCI 0.96 > Bus usb@1a24: hcd: 0x1a24, ippc: 0x1a244700 > u2p:1, u3p:1 > Register 200010f NbrPorts 2 > Starting the controller > USB XHCI 0.96 > scanning bus usb@1a1c for devices... 1 USB Device(s) found > scanning bus usb@1a24 for devices... 2 USB Device(s) found >scanning usb for storage devices... 1 Storage Device(s) found > BPI-R2> usb tree > USB device tree: > 1 Hub (5 Gb/s, 0mA) > U-Boot XHCI Host Controller > > 1 Hub (5 Gb/s, 0mA) > | U-Boot XHCI Host Controller > | > +-2 Mass Storage (480 Mb/s, 200mA) >USB Flash Disk 906B030002F4 > > BPI-R2> ls usb 0:1 > efi/ > 4767728 kernel > > 1 file(s), 1 dir(s) > > = > > BPI-R64> usb start > starting USB... > Bus usb@1a0c: hcd: 0x1a0c, ippc: 0x1a0c4700 > u2p:2, u3p:1 > Register 300010f NbrPorts 3 > Starting the controller > USB XHCI 0.96 > scanning bus usb@1a0c for devices... 2 USB Device(s) found >scanning usb for storage devices... 1 Storage Device(s) found > BPI-R64> ls usb 0:1 >91 mcurom.md5 > System Volume Information/ > > 1 file(s), 1 dir(s) > > BPI-R64> > > Tested-By: Frank Wunderlich Thanks a lot > > [1] https://github.com/frank-w/u-boot/commits/2020-10-bpi
Re: [PATCH v1 10/10] arm: dts: mt7623: add USB nodes
On Sun, 2020-08-16 at 10:24 +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich
>
> This adds USB nodes for MT7623/BPI-R2
>
> Signed-off-by: Frank Wunderlich
> ---
> arch/arm/dts/mt7623.dtsi | 46
> arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 +
> 2 files changed, 62 insertions(+)
>
> diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
> index 0452889ef8..e753e08545 100644
> --- a/arch/arm/dts/mt7623.dtsi
> +++ b/arch/arm/dts/mt7623.dtsi
> @@ -352,6 +352,52 @@
> };
> };
>
> + usb1: usb@1a1c {
> + compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
> + reg = <0x1a1c 0x1000>, <0x1a1c4700 0x0100>;
> + reg-names = "mac", "ippc";
> + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
> + clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen
> CLK_TOP_ETHIF_SEL>;
> + clock-names = "sys_ck", "ref_ck";
> + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
> + status = "disabled";
> + };
> +
> + u3phy1: usb-phy1@1a1c4000 {
use usb-phy, no need add 1
> + compatible = "mediatek,mt7623-tphy", "mediatek,generic-tphy-v1";
> +
> + reg = <0x1a1c4000 0x0700>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + u2port0: usb-phy@1a1c4800 {
> + reg = <0x1a1c4800 0x0100>;
> + #phy-cells = <1>;
> + clocks = <&topckgen CLK_TOP_USB_PHY48M>;
> + clock-names = "ref";
> + };
> +
> + u3port0: usb-phy@1a1c4900 {
> + reg = <0x1a1c4900 0x0700>;
> + #phy-cells = <1>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + };
> + };
> +
> + usb2: usb@1a24 {
> + compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
> + reg = <0x1a24 0x1000>, <0x1a244700 0x0100>;
> + reg-names = "mac", "ippc";
> + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
> + clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen
> CLK_TOP_ETHIF_SEL>;
> + clock-names = "sys_ck", "ref_ck";
> + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
> + status = "disabled";
> + };
> +
> u3phy2: usb-phy@1a244000 {
> compatible = "mediatek,generic-tphy-v1";
> reg = <0x1a244000 0x0700>;
> diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> index bcedcf20f1..ef07369627 100644
> --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> @@ -248,3 +248,19 @@
> pinctrl-0 = <&uart2_pins_a>;
> status = "okay";
> };
> +
> +&usb1 {
> + status = "okay";
> +};
> +
> +&u3phy1 {
> + status = "okay";
> +};
> +
> +&usb2 {
> + status = "okay";
> +};
> +
> +&u3phy2 {
> + status = "okay";
> +};
RE: [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images
> -Original Message- > From: Westergreen, Dalon > Sent: Saturday, August 15, 2020 3:24 AM > To: u-boot@lists.denx.de; Ang, Chee Hong > Cc: See, Chin Liang ; Tan, Ley Foon > ; Chee, Tien Fong ; > Lim, Elly Siew Chin > Subject: Re: [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp > with 4 SPL images > > Can you explain why this x4 image is needed? the top level u-boot-with- > spl.sfp or whatever it is called already creates four spl entries. what are > you > generating the x4 image for? If we put u-boot.img in FAT partition, then we don't need u-boot-with- spl.sfp. Just 4 x SPL images. Regards Ley Foon > > On Wed, 2020-08-05 at 16:15 +0800, Chee Hong Ang wrote: > > Generate spl/u-boot-splx4.sfp which consist of 4 SPL images required > > for booting up Cyclone5/Arria10. > > > > Signed-off-by: Chee Hong Ang > > --- > > Makefile | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > > > > diff --git a/Makefile b/Makefile > > index 2629a74..13429a0 100644 > > --- a/Makefile > > +++ b/Makefile > > @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img > FORCE > > ifneq ($(CONFIG_ARCH_SOCFPGA),) quiet_cmd_socboot = SOCBOOT $@ > > cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ > > - spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ > > - u-boot.img > $@ || rm -f $@ > > + spl/u-boot-spl.sfp \ > > + spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \ > > + cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@ > > u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE > > $(call if_changed,socboot) > >
Re: [PATCH v1 09/10] arm: dts: mt7622: add USB nodes
On Sun, 2020-08-16 at 10:24 +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich
>
> Add DTS nodes for MT7622/BPI-R64
>
> Signed-off-by: Frank Wunderlich
> ---
> v1->v2:
> - add USB nodes to MT7622 reference board
> ---
> arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 8 +++
> arch/arm/dts/mt7622-rfb.dts | 8 +++
> arch/arm/dts/mt7622.dtsi | 64
> 3 files changed, 80 insertions(+)
>
> diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
> b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
> index c36ec8f8d0..7cd581cf7d 100644
> --- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
> +++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
> @@ -213,3 +213,11 @@
> output-low;
> };
> };
> +
> +&ssusb {
> + status = "okay";
> +};
> +
> +&u3phy {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
> index 317fc78abd..ef7d0f0270 100644
> --- a/arch/arm/dts/mt7622-rfb.dts
> +++ b/arch/arm/dts/mt7622-rfb.dts
> @@ -222,3 +222,11 @@
> full-duplex;
> };
> };
> +
> +&ssusb {
> + status = "okay";
> +};
> +
> +&u3phy {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
> index c43ad65702..c69f9d7d73 100644
> --- a/arch/arm/dts/mt7622.dtsi
> +++ b/arch/arm/dts/mt7622.dtsi
> @@ -81,6 +81,12 @@
> #clock-cells = <0>;
> };
>
> + clk25m: dummy25m {
> + compatible = "fixed-clock";
> + clock-frequency = <2500>;
> + #clock-cells = <0>;
> + };
> +
> infracfg: infracfg@1000 {
> compatible = "mediatek,mt7622-infracfg",
>"syscon";
> @@ -192,6 +198,14 @@
> status = "disabled";
> };
>
> + ssusbsys: ssusbsys@1a00 {
> + compatible = "mediatek,mt7622-ssusbsys",
> + "syscon";
> + reg = <0x1a00 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> pciesys: pciesys@1a100800 {
> compatible = "mediatek,mt7622-pciesys", "syscon";
> reg = <0x1a100800 0x1000>;
> @@ -302,6 +316,56 @@
> };
> };
>
> + ssusb: usb@1a0c {
> + compatible = "mediatek,mt7622-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0x1a0c 0x01000>,
> + <0x1a0c4700 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts = ;
> + power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
> + clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
> + <&ssusbsys CLK_SSUSB_REF_EN>,
> + <&ssusbsys CLK_SSUSB_MCU_EN>,
> + <&ssusbsys CLK_SSUSB_DMA_EN>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
> + phys = <&u2port0 PHY_TYPE_USB2>,
> +<&u3port0 PHY_TYPE_USB3>,
> +<&u2port1 PHY_TYPE_USB2>;
> + status = "disabled";
> + };
> +
> + u3phy: usb-phy@1a0c4000 {
> + compatible = "mediatek,mt7622-u3phy",
> + "mediatek,generic-tphy-v1";
> + reg = <0x1a0c4000 0x700>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + u2port0: usb-phy@1a0c4800 {
> + reg = <0x1a0c4800 0x0100>;
> + #phy-cells = <1>;
> + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
> + clock-names = "ref";
> + };
> +
> + u3port0: usb-phy@1a0c4900 {
> + reg = <0x1a0c4900 0x0700>;
> + #phy-cells = <1>;
> + clocks = <&clk25m>;
> + clock-names = "ref";
clock is optional, if we can't control it, skip it is also fine.
> + };
> +
> + u2port1: usb-phy@1a0c5000 {
> + reg = <0x1a0c5000 0x0100>;
> + #phy-cells = <1>;
> + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
> + clock-names = "ref";
> + };
> + };
Reviewed-by: Chunfeng Yun
Thank you
> +
> ethsys: syscon@1b00 {
> compatible = "mediatek,mt7622-ethsys", "syscon";
> reg = <0x1b00 0x1000>;
Re: [PATCH v1 10/10] arm: dts: mt7623: add USB nodes
On Sun, 2020-08-16 at 10:24 +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich
>
> This adds USB nodes for MT7623/BPI-R2
>
> Signed-off-by: Frank Wunderlich
> ---
> arch/arm/dts/mt7623.dtsi | 46
> arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 +
> 2 files changed, 62 insertions(+)
>
> diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
> index 0452889ef8..e753e08545 100644
> --- a/arch/arm/dts/mt7623.dtsi
> +++ b/arch/arm/dts/mt7623.dtsi
> @@ -352,6 +352,52 @@
> };
> };
>
> + usb1: usb@1a1c {
> + compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
> + reg = <0x1a1c 0x1000>, <0x1a1c4700 0x0100>;
> + reg-names = "mac", "ippc";
> + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
> + clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen
> CLK_TOP_ETHIF_SEL>;
> + clock-names = "sys_ck", "ref_ck";
> + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
> + status = "disabled";
> + };
> +
> + u3phy1: usb-phy1@1a1c4000 {
after change usb-phy1 as usb-phy
Reveiwed-by Chunfeng Yun
Thanks
> + compatible = "mediatek,mt7623-tphy", "mediatek,generic-tphy-v1";
> +
> + reg = <0x1a1c4000 0x0700>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + u2port0: usb-phy@1a1c4800 {
> + reg = <0x1a1c4800 0x0100>;
> + #phy-cells = <1>;
> + clocks = <&topckgen CLK_TOP_USB_PHY48M>;
> + clock-names = "ref";
> + };
> +
> + u3port0: usb-phy@1a1c4900 {
> + reg = <0x1a1c4900 0x0700>;
> + #phy-cells = <1>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + };
> + };
> +
> + usb2: usb@1a24 {
> + compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
> + reg = <0x1a24 0x1000>, <0x1a244700 0x0100>;
> + reg-names = "mac", "ippc";
> + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
> + clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen
> CLK_TOP_ETHIF_SEL>;
> + clock-names = "sys_ck", "ref_ck";
> + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
> + status = "disabled";
> + };
> +
> u3phy2: usb-phy@1a244000 {
> compatible = "mediatek,generic-tphy-v1";
> reg = <0x1a244000 0x0700>;
> diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> index bcedcf20f1..ef07369627 100644
> --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> @@ -248,3 +248,19 @@
> pinctrl-0 = <&uart2_pins_a>;
> status = "okay";
> };
> +
> +&usb1 {
> + status = "okay";
> +};
> +
> +&u3phy1 {
> + status = "okay";
> +};
> +
> +&usb2 {
> + status = "okay";
> +};
> +
> +&u3phy2 {
> + status = "okay";
> +};
Re: [PATCH v2 3/3] doc: verified-boot: add required-mode information
On 7/28/2020 11:58 AM, Simon Glass wrote: > Hi Thirupathaiah, > > On Fri, 17 Jul 2020 at 21:20, Thirupathaiah Annapureddy > wrote: >> >> Signed-off-by: Thirupathaiah Annapureddy >> --- >> >> Changes in v2: >> - New >> >> doc/uImage.FIT/signature.txt | 14 ++ >> 1 file changed, 14 insertions(+) >> > > Reviewed-by: Simon Glass > > But I think we need a new mkimage option to set the required-mode Is it okay if I do mkimage option change as part of a different patch/ patch series? > > >> diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt >> index d4afd755e9..a3455889ed 100644 >> --- a/doc/uImage.FIT/signature.txt >> +++ b/doc/uImage.FIT/signature.txt >> @@ -386,6 +386,20 @@ that might be used by the target needs to be signed >> with 'required' keys. >> >> This happens automatically as part of a bootm command when FITs are used. >> >> +For Signed Configurations, the default verification behavior can be changed >> by >> +the following optional property in /signature node in U-Boot's control FDT. >> + >> +- required-mode: Valid values are "any" to allow verified boot to succeed if >> +the selected configuration is signed by any of the 'required' keys, and >> "all" >> +to allow verified boot to succeed if the selected configuration is signed by >> +all of the 'required' keys. >> + >> +This property can be added to a binary device tree using fdtput as shown in >> +below examples:: >> + >> + fdtput -t s control.dtb /signature required-mode any >> + fdtput -t s control.dtb /signature required-mode all >> + >> >> Enabling FIT Verification >> - >> -- >> 2.25.2 >>
[PATCH v1 01/16] arm: socfpga: soc64: Remove CONFIG_OF_EMBED
CONFIG_OF_EMBED was primarily enabled to support the S10/Agilex spl hex file requirements. Since this option now produces a warning during build, and the spl hex can be created using alternate methods, CONFIG_OF_EMBED is no longer needed. Signed-off-by: Chee Hong Ang --- configs/socfpga_agilex_defconfig| 1 - configs/socfpga_stratix10_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index f45cdd18b3..feaab00249 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 20ffca89ad..e7c7550112 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -37,7 +37,6 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y -- 2.19.0
[PATCH v1 00/16] Enable ARM Trusted Firmware for U-Boot
Repost of the following patchs:
https://lists.denx.de/pipermail/u-boot/2020-March/402705.html
New U-boot flow with ARM Trusted Firmware (ATF) support:
SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
SPL loads the u-boot.itb which consist of:
1) u-boot-nodtb.bin (U-Boot Proper image)
2) u-boot.dtb (U-Boot Proper DTB)
3) bl31.bin (ATF-BL31 image)
Supported Platform: Intel SoCFPGA 64bits (Stratix10 & Agilex)
Now, U-Boot Proper is running in non-secure mode (EL2), it invokes
SMC/PSCI calls provided by ATF to perform COLD reset, System Manager
register accesses and mailbox communications with Secure Device Manager
(SDM).
Steps to build the U-Boot with ATF support:
1) Build U-Boot
2) Build ATF BL31
3) Copy ATF BL31 binary image into U-Boot's root folder
4) "make u-boot.itb" to generate u-boot.itb
These patchsets have dependency on:
arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
https://lists.denx.de/pipermail/u-boot/2020-August/423029.html
Rename Stratix10 FPGA driver and support Agilex
https://lists.denx.de/pipermail/u-boot/2020-August/422798.html
SoCFPGA mailbox driver fixes and enhancements
https://lists.denx.de/pipermail/u-boot/2020-August/423140.html
arm: socfpga: soc64: Initialize timer in SPL only
https://lists.denx.de/pipermail/u-boot/2020-July/419692.html
arm: socfpga: soc64: Remove PHY interface setup from misc arch init
https://lists.denx.de/pipermail/u-boot/2020-July/419690.html
Enable sysreset support for SoCFPGA SoC64 platforms
https://lists.denx.de/pipermail/u-boot/2020-August/422509.html
arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
https://lists.denx.de/pipermail/u-boot/2020-August/423373.html
Chee Hong Ang (16):
arm: socfpga: soc64: Remove CONFIG_OF_EMBED
arm: socfpga: soc64: Add FIT generator script for pack itb with ATF
arm: socfpga: Add function for checking description from FIT image
arm: socfpga: soc64: Load FIT image with ATF support
arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
arm: socfpga: Disable "spin-table" method for booting Linux
arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA
(64bits)
arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP
services
mmc: dwmmc: socfpga: Add ATF support for MMC driver
net: designware: socfpga: Add ATF support for MAC driver
arm: socfpga: soc64: Add ATF support for Reset Manager driver
arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
mbox_reset_cold()
arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
arm: socfpga: soc64: Skip handoff data access in SSBL
configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
support
arch/arm/mach-socfpga/Kconfig | 2 -
arch/arm/mach-socfpga/Makefile| 4 +
arch/arm/mach-socfpga/board.c | 12 +-
arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +
arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
arch/arm/mach-socfpga/reset_manager_s10.c | 10 +
arch/arm/mach-socfpga/smc_api.c | 56 ++
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 +-
board/altera/soc64/fit_spl_atf.sh | 91 +++
...defconfig => socfpga_agilex_atf_defconfig} | 25 +-
configs/socfpga_agilex_defconfig | 1 -
...config => socfpga_stratix10_atf_defconfig} | 25 +-
configs/socfpga_stratix10_defconfig | 1 -
drivers/fpga/intel_sdm_mb.c | 139 +
drivers/mmc/socfpga_dw_mmc.c | 20 +
drivers/net/dwmac_socfpga.c | 43 +-
include/configs/socfpga_soc64_common.h| 9 +
include/linux/intel-smc.h | 573 ++
19 files changed, 1078 insertions(+), 30 deletions(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S
create mode 100644 arch/arm/mach-socfpga/smc_api.c
create mode 100755 board/altera/soc64/fit_spl_atf.sh
copy configs/{socfpga_agilex_defconfig => socfpga_agilex_atf_defconfig} (77%)
copy configs/{socfpga_stratix10_defconfig => socfpga_stratix10_atf_defconfig}
(80%)
create mode 100644 include/linux/intel-smc.h
--
2.19.0
[PATCH v1 02/16] arm: socfpga: soc64: Add FIT generator script for pack itb with ATF
Generate a FIT image for Intel SOCFPGA (64bits) which
include U-boot proper, ATF and DTB for U-boot proper.
Signed-off-by: Chee Hong Ang
---
board/altera/soc64/fit_spl_atf.sh | 91 +++
1 file changed, 91 insertions(+)
create mode 100755 board/altera/soc64/fit_spl_atf.sh
diff --git a/board/altera/soc64/fit_spl_atf.sh
b/board/altera/soc64/fit_spl_atf.sh
new file mode 100755
index 00..482ca36f9b
--- /dev/null
+++ b/board/altera/soc64/fit_spl_atf.sh
@@ -0,0 +1,91 @@
+#!/bin/sh
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for Agilex boards with
+# U-Boot proper, ATF and device tree for U-Boot proper.
+#
+# usage: $0
+
+BL31="bl31.bin"
+if [ ! -f $BL31 ]; then
+ echo "BL31 file \"$BL31\" NOT found!" >&2
+ exit 1
+fi
+
+BL33="u-boot-nodtb.bin"
+if [ ! -f $BL33 ]; then
+ echo "BL33 file \"$BL33\" NOT found!" >&2
+ exit 1
+fi
+
+if [ -f "$1" ] ; then
+ DT_NAME="$1"
+else
+ echo "File not found: \"$1\"" >&2
+ exit 1
+fi
+
+cat << __PREAMBLE_EOF
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with U-Boot proper, ATF bl31, U-Boot DTB";
+ #address-cells = <1>;
+
+__PREAMBLE_EOF
+
+cat << __IMAGES_EOF
+ images {
+ uboot {
+ description = "U-Boot SoC64";
+ data = /incbin/("$BL33");
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x0020>;
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ data = /incbin/("$BL31");
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x1000>;
+ entry = <0x1000>;
+ };
+
+ fdt {
+ description = "U-Boot SoC64 flat device-tree";
+ data = /incbin/("$DT_NAME");
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+
+__IMAGES_EOF
+
+cat << __CONFIGS_EOF
+ configurations {
+ default = "conf";
+ conf {
+ description = "Intel SoC64 FPGA";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt";
+ };
+ };
+__CONFIGS_EOF
+
+cat << __END_EOF
+};
+__END_EOF
--
2.19.0
[PATCH v1 03/16] arm: socfpga: Add function for checking description from FIT image
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/board.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 340abf9305..7993c27646 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -13,7 +13,7 @@
#include
#include
#include
-
+#include
#include
#include
@@ -87,3 +87,13 @@ int g_dnl_board_usb_cable_connected(void)
return 1;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+__weak int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
--
2.19.0
[PATCH v1 04/16] arm: socfpga: soc64: Load FIT image with ATF support
Instead of loading u-boot proper image (u-boot.img), SPL now loads FIT image (u-boot.itb) which includes u-boot proper, ATF and u-boot proper's DTB. Signed-off-by: Chee Hong Ang --- include/configs/socfpga_soc64_common.h | 4 1 file changed, 4 insertions(+) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index fb5e2e8aaf..cb9bb21597 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -193,6 +193,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); - CONFIG_SYS_SPL_MALLOC_SIZE) /* SPL SDMMC boot support */ +#ifdef CONFIG_SPL_LOAD_FIT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.itb" +#else #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img" +#endif #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */ -- 2.19.0
[PATCH v1 07/16] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)
invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.
smc_send_mailbox() is a send mailbox command helper function which invokes
the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD)
to send mailbox messages to Secure Device Manager (SDM).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +
arch/arm/mach-socfpga/smc_api.c | 56
3 files changed, 71 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
create mode 100644 arch/arm/mach-socfpga/smc_api.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index c63162a5c6..0b05283a7a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -72,6 +72,8 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += firewall.o
obj-y += spl_agilex.o
endif
+else
+obj-$(CONFIG_SPL_ATF) += smc_api.o
endif
ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/smc_api.h
b/arch/arm/mach-socfpga/include/mach/smc_api.h
new file mode 100644
index 00..bbefdd8dd9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/smc_api.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#ifndef _SMC_API_H_
+#define _SMC_API_H_
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+u32 *resp_buf);
+
+#endif /* _SMC_API_H_ */
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
new file mode 100644
index 00..085daba162
--- /dev/null
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len)
+{
+ struct pt_regs regs;
+
+ memset(®s, 0, sizeof(regs));
+ regs.regs[0] = func_id;
+
+ if (args)
+ memcpy(®s.regs[1], args, arg_len * sizeof(*args));
+
+ smc_call(®s);
+
+ if (ret_arg)
+ memcpy(ret_arg, ®s.regs[1], ret_len * sizeof(*ret_arg));
+
+ return regs.regs[0];
+}
+
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+u32 *resp_buf)
+{
+ int ret;
+ u64 args[6];
+ u64 resp[3];
+
+ args[0] = cmd;
+ args[1] = (u64)arg;
+ args[2] = len;
+ args[3] = urgent;
+ args[4] = (u64)resp_buf;
+ if (resp_buf_len)
+ args[5] = *resp_buf_len;
+ else
+ args[5] = 0;
+
+ ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
+resp, ARRAY_SIZE(resp));
+
+ if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) {
+ if (!resp[0])
+ *resp_buf_len = resp[1];
+ }
+
+ return (int)resp[0];
+}
--
2.19.0
[PATCH v1 09/16] mmc: dwmmc: socfpga: Add ATF support for MMC driver
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang
---
drivers/mmc/socfpga_dw_mmc.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 0022f943bd..a58ea472b9 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -13,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -46,6 +48,20 @@ static void socfpga_dwmci_reset(struct udevice *dev)
reset_deassert_bulk(&reset_bulk);
}
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+static void socfpga_dwmci_fw_clksel(u32 sdmmc_mask)
+{
+ u64 args[2];
+
+ /* drvsel */
+ args[0] = (sdmmc_mask >> SYSMGR_SDMMC_DRVSEL_SHIFT) & 0x7;
+ /* smplsel */
+ args[1] = (sdmmc_mask >> SYSMGR_SDMMC_SMPLSEL_SHIFT) & 0x7;
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK, args, 2, NULL, 0))
+ dev_err(host->dev, "SMC call failed in %s\n", __func__);
+}
+#endif
+
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
@@ -58,10 +74,14 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ socfpga_dwmci_fw_clksel(sdmmc_mask);
+#else
writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+#endif
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
--
2.19.0
[PATCH v1 05/16] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
Override 'lowlevel_init' to make sure secondary CPUs trapped in ATF instead of SPL. After ATF is initialized, it will signal the secondary CPUs to jump from SPL to ATF waiting to be 'activated' by Linux OS via PSCI call. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Makefile | 2 + arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 + 2 files changed, 78 insertions(+) create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 418f543b20..c63162a5c6 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -29,6 +29,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o @@ -41,6 +42,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S new file mode 100644 index 00..612ea8a037 --- /dev/null +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include +#include +#include +#include + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +wait_for_atf: + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, slave_wait_atf + br x5 +slave_wait_atf: + branch_if_slave x0, wait_for_atf +#else + branch_if_slave x0, 1f +#endif + ldr x0, =GICD_BASE + bl gic_init_secure +1: +#if defined(CONFIG_GICV3) + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + +#ifdef CONFIG_ARMV8_MULTIENTRY + branch_if_master x0, x1, 2f + + /* +* Slave should wait for master clearing spin table. +* This sync prevent slaves observing incorrect +* value of spin table and jumping to wrong place. +*/ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_GICV2 + ldr x0, =GICC_BASE +#endif + bl gic_wait_for_interrupt +#endif + + /* +* All slaves will enter EL2 and optionally EL1. +*/ + adr x4, lowlevel_in_el2 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el2 + +lowlevel_in_el2: +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + adr x4, lowlevel_in_el1 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el1 + +lowlevel_in_el1: +#endif + +#endif /* CONFIG_ARMV8_MULTIENTRY */ + +2: + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) -- 2.19.0
[PATCH v1 08/16] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services
This header file defines the Secure Monitor Call (SMC) message protocol for ATF (BL31) PSCI runtime services. It includes all the PSCI SiP function identifiers for the secure runtime services provided by ATF. The secure runtime services include System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. Signed-off-by: Chee Hong Ang --- include/linux/intel-smc.h | 573 ++ 1 file changed, 573 insertions(+) create mode 100644 include/linux/intel-smc.h diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h new file mode 100644 index 00..fa7d1dff56 --- /dev/null +++ b/include/linux/intel-smc.h @@ -0,0 +1,573 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2018, Intel Corporation + */ + +#ifndef __INTEL_SMC_H +#define __INTEL_SMC_H + +#include +#include + +/* + * This file defines the Secure Monitor Call (SMC) message protocol used for + * service layer driver in normal world (EL1) to communicate with secure + * monitor software in Secure Monitor Exception Level 3 (EL3). + * + * This file is shared with secure firmware (FW) which is out of kernel tree. + * + * An ARM SMC instruction takes a function identifier and up to 6 64-bit + * register values as arguments, and can return up to 4 64-bit register + * value. The operation of the secure monitor is determined by the parameter + * values passed in through registers. + + * EL1 and EL3 communicates pointer as physical address rather than the + * virtual address. + */ + +/* + * Functions specified by ARM SMC Calling convention: + * + * FAST call executes atomic operations, returns when the requested operation + * has completed. + * STD call starts a operation which can be preempted by a non-secure + * interrupt. The call can return before the requested operation has + * completed. + * + * a0..a7 is used as register names in the descriptions below, on arm32 + * that translates to r0..r7 and on arm64 to w0..w7. + */ + +#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +/* + * Return values in INTEL_SIP_SMC_* call + * + * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: + * Secure monitor software doesn't recognize the request. + * + * INTEL_SIP_SMC_STATUS_OK: + * FPGA configuration completed successfully, + * In case of FPGA configuration write operation, it means secure monitor + * software can accept the next chunk of FPGA configuration data. + * + * INTEL_SIP_SMC_STATUS_BUSY: + * In case of FPGA configuration write operation, it means secure monitor + * software is still processing previous data & can't accept the next chunk + * of data. Service driver needs to issue + * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the + * completed block(s). + * + * INTEL_SIP_SMC_STATUS_ERROR: + * There is error during the FPGA configuration process. + * + * INTEL_SIP_SMC_REG_ERROR: + * There is error during a read or write operation of the protected + * registers. + */ +#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0x +#define INTEL_SIP_SMC_STATUS_OK0x0 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 +#define INTEL_SIP_SMC_REG_ERROR0x5 +#define INTEL_SIP_SMC_RSU_ERROR0x7 + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_START + * + * Sync call used by service driver at EL1 to request the FPGA in EL3 to + * be prepare to receive a new configuration. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. + * a1: flag for full or partial configuration + *0 full reconfiguration. + *1 partial reconfiguration. + * a2-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 +#define INTEL_SIP_SMC_FPGA_CONFIG_START \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE + * + * Async call used by service driver at EL1 to provide FPGA configuration data + * to secure world. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. + * a1: 64bit physical address of the configuration data memory block + * a2: Size of configuration data block. + * a3-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY, + * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR. + * a1: 64bit physical address of 1st completed memory block if any completed + * block, otherwise zero value. + * a2: 64bit physic
[PATCH v1 06/16] arm: socfpga: Disable "spin-table" method for booting Linux
Standard PSCI function "CPU_ON" provided by ATF is now used by Linux kernel to bring up the secondary CPUs to enable SMP booting in Linux on SoC 64bits platform. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 26f2cf8e47..01f5a1fc41 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -33,7 +33,6 @@ config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select CLK select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE @@ -79,7 +78,6 @@ config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select FPGA_INTEL_SDM_MAILBOX choice -- 2.19.0
[PATCH v1 10/16] net: designware: socfpga: Add ATF support for MAC driver
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang
---
drivers/net/dwmac_socfpga.c | 43 +
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561dffa..0dd5a54405 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -17,7 +17,9 @@
#include
#include
+#include
#include
+#include
struct dwmac_socfpga_platdata {
struct dw_eth_pdata dw_eth_pdata;
@@ -64,6 +66,35 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice
*dev)
return designware_eth_ofdata_to_platdata(dev);
}
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+static int dwmac_socfpga_fw_setphy(struct udevice *dev, u32 modereg)
+{
+ struct ofnode_phandle_args pargs;
+ u64 args[2];
+ int ret;
+
+ ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
+1, 0, &pargs);
+ if (ret) {
+ dev_err(dev, "Failed to get syscon: %d\n", ret);
+ return ret;
+ }
+
+ if (pargs.args_count < 1) {
+ dev_err(dev, "No syscon args found\n");
+ return -EINVAL;
+ }
+
+ args[0] = ((u64)pargs.args[0] - SYSMGR_SOC64_EMAC0) >> 2;
+ args[1] = modereg;
+
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_PHYINTF, args, 2, NULL, 0))
+ return -EIO;
+
+ return 0;
+}
+#endif
+
static int dwmac_socfpga_probe(struct udevice *dev)
{
struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
@@ -71,7 +102,6 @@ static int dwmac_socfpga_probe(struct udevice *dev)
struct reset_ctl_bulk reset_bulk;
int ret;
u32 modereg;
- u32 modemask;
switch (edata->phy_interface) {
case PHY_INTERFACE_MODE_MII:
@@ -97,9 +127,14 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(&reset_bulk);
- modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
- clrsetbits_le32(pdata->phy_intf, modemask,
- modereg << pdata->reg_shift);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ ret = dwmac_socfpga_fw_setphy(dev, modereg);
+ if (ret)
+ return ret;
+#else
+ clrsetbits_le32(pdata->phy_intf, SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
+ pdata->reg_shift, modereg << pdata->reg_shift);
+#endif
reset_release_bulk(&reset_bulk);
--
2.19.0
[PATCH v1 11/16] arm: socfpga: soc64: Add ATF support for Reset Manager driver
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/reset_manager_s10.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index e5eb7f4aeb..79b8044aa0 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,11 +5,14 @@
*/
#include
+#include
#include
#include
+#include
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +58,12 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 arg = enable;
+
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0))
+ hang();
+#else
u32 reg;
if (enable) {
@@ -101,6 +110,7 @@ void socfpga_bridges_reset(int enable)
/* Disable NOC timeout */
writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
}
+#endif
}
/*
--
2.19.0
[PATCH v1 13/16] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index 18d44924e6..429444f069 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -398,6 +399,9 @@ error:
int mbox_reset_cold(void)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ psci_system_reset();
+#else
int ret;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
@@ -406,6 +410,7 @@ int mbox_reset_cold(void)
/* mailbox sent failure, wait for watchdog to kick in */
hang();
}
+#endif
return 0;
}
--
2.19.0
[PATCH v1 15/16] arm: socfpga: soc64: Skip handoff data access in SSBL
SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index 3da85791a1..049c5711a8 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -12,6 +12,7 @@
const struct cm_config * const cm_get_default_config(void)
{
+#ifdef CONFIG_SPL_BUILD
struct cm_config *cm_handoff_cfg = (struct cm_config *)
(S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
u32 *conversion = (u32 *)cm_handoff_cfg;
@@ -26,7 +27,7 @@ const struct cm_config * const cm_get_default_config(void)
} else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
return cm_handoff_cfg;
}
-
+#endif
return NULL;
}
--
2.19.0
[PATCH v1 14/16] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
Since SSBL is running in DRAM, it shall setup the stack in DRAM instead of OCRAM which is occupied by SPL and handoff data. Signed-off-by: Chee Hong Ang --- include/configs/socfpga_soc64_common.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index cb9bb21597..dadd21b0ba 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -40,9 +40,14 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE0 #define CONFIG_SYS_INIT_RAM_SIZE 0x4 +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_INIT_RAM_ADDR \ + CONFIG_SYS_INIT_RAM_SIZE \ - S10_HANDOFF_SIZE) +#else +#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_TEXT_BASE \ + + 0x10) +#endif #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) -- 2.19.0
[PATCH v1 12/16] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/intel_sdm_mb.c | 139
1 file changed, 139 insertions(+)
diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index 9a1dc2c0c8..f5fd9a14c2 100644
--- a/drivers/fpga/intel_sdm_mb.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -8,11 +8,149 @@
#include
#include
#include
+#include
#include
+#include
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 6
#define RECONFIG_STATUS_INTERVAL_DELAY_US 100
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#define BITSTREAM_CHUNK_SIZE 0x0
+#define RECONFIG_STATUS_POLL_RETRY_MAX 100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+ int ret;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+NULL, 0);
+
+ if (!ret)
+ return 0; /* configuration success */
+
+ if (ret != INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+
+ if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+ return -ETIMEDOUT; /* time out */
+
+ puts(".");
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+ WATCHDOG_RESET();
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int send_bitstream(const void *rbf_data, size_t rbf_size)
+{
+ int i;
+ u64 res_buf[3];
+ u64 args[2];
+ u32 xfer_count = 0;
+ int ret, wr_ret = 0, retry = 0;
+ size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+ BITSTREAM_CHUNK_SIZE : rbf_size;
+
+ while (rbf_size || xfer_count) {
+ if (!wr_ret && rbf_size) {
+ args[0] = (u64)rbf_data;
+ args[1] = buf_size;
+ wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+ args, 2, NULL, 0);
+
+ debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+ wr_ret, rbf_data, buf_size);
+
+ if (wr_ret)
+ continue;
+
+ rbf_size -= buf_size;
+ rbf_data += buf_size;
+
+ if (buf_size >= rbf_size)
+ buf_size = rbf_size;
+
+ xfer_count++;
+ puts(".");
+ } else {
+ ret = invoke_smc(
+ INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+ NULL, 0, res_buf, ARRAY_SIZE(res_buf));
+ if (!ret) {
+ for (i = 0; i < ARRAY_SIZE(res_buf); i++) {
+ if (!res_buf[i])
+ break;
+ xfer_count--;
+ wr_ret = 0;
+ retry = 0;
+ }
+ } else if (ret !=
+ INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+ else if (!xfer_count)
+ return INTEL_SIP_SMC_STATUS_ERROR;
+
+ if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+ return -ETIMEDOUT;
+
+ udelay(2);
+ }
+ WATCHDOG_RESET();
+ }
+
+ return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ int ret;
+ u64 arg = 1;
+
+ debug("Invoking FPGA_CONFIG_START...\n");
+
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
+
+ if (ret) {
+ puts("Failure in RECONFIG mailbox command!\n");
+ return ret;
+ }
+
+ ret = send_bitstream(rbf_data, rbf_size);
+ if (ret) {
+ puts("Error sending bitstream!\n");
+ return ret;
+ }
+
+ /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+ debug("Polling with MBOX_RECONFIG_STATUS...\n");
+ ret = reconfig_status_polling_resp();
+ if (ret) {
+ puts("FPGA reconfiguration failed!");
+ return ret;
+ }
+
+ puts("FPGA reconfiguration OK!\n");
+
+
[PATCH v1 16/16] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
Booting Agilex and Stratix 10 with ATF support. SPL now loads ATF (BL31), U-Boot proper and DTB from FIT image. The new boot flow with ATF support is as follow: SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux) U-Boot proper now starts at 0x20 (CONFIG_SYS_TEXT_BASE). ATF will occupy the address range starting from 0x1000. Signed-off-by: Chee Hong Ang --- configs/socfpga_agilex_atf_defconfig| 71 configs/socfpga_stratix10_atf_defconfig | 73 + 2 files changed, 144 insertions(+) create mode 100644 configs/socfpga_agilex_atf_defconfig create mode 100644 configs/socfpga_stratix10_atf_defconfig diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig new file mode 100644 index 00..4af1021809 --- /dev/null +++ b/configs/socfpga_agilex_atf_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x20 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="board/altera/soc64/fit_spl_atf.sh" +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon" +CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig new file mode 100644 index 00..f50d5030fb --- /dev/null +++ b/configs/socfpga_stratix10_atf_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x20 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="board/altera/soc64/fit_spl_atf.sh" +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon" +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y -- 2.19.0
Re: [PATCH] ARM: bootm: take into account gd->ram_top
Hi Patrick, all,
On Thu, Feb 13 2020, Patrick Delaunay wrote:
> From: Patrice Chotard
>
> If gd->ram_top has been tuned using board_get_usable_ram_top(),
> it must be taken into account when reserving arch lmb.
>
> Signed-off-by: Patrice Chotard
> Reviewed-by: Patrick DELAUNAY
> Signed-off-by: Patrick Delaunay
[snip]
> diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
> index a135bcfc7b..f4b5ca6de0 100644
> --- a/arch/arm/lib/bootm.c
> +++ b/arch/arm/lib/bootm.c
> @@ -75,6 +75,9 @@ void arch_lmb_reserve(struct lmb *lmb)
> gd->bd->bi_dram[bank].size - 1;
> if (sp > bank_end)
> continue;
> + if (bank_end > gd->ram_top)
> + bank_end = gd->ram_top - 1;
> +
This patch (now committed as 8ce1f10cf2b1) breaks kernel boot on Armada
8040 based Clearfog GT-8K with 16GB RAM. See below the console output of
v2020.10-rc2 with a few added prints.
The first memory bank (bi_dram[0]) goes from 0 to 3GB. The rest
(4GB-17GB) is on bi_dram[1] (see a8k_dram_init_banksize()). ram_top is
set to 2GB on
arch/arm/mach-mvebu/arm64-common.c:board_get_usable_ram_top().
Reverting commit 8ce1f10cf2b1 on top of v2020.10-rc2 fixes boot.
Any Idea?
Found /extlinux/extlinux.conf
Retrieving file: /extlinux/extlinux.conf
## Current stack ends at 0x7fb24300
arch_lmb_reserve: bank_end: bfff ram_top: 8000
62 bytes read in 21 ms (2 KiB/s)
1: linux
Retrieving file: /extlinux/Image
## Current stack ends at 0x7fb23960
arch_lmb_reserve: bank_end: bfff ram_top: 8000
13740544 bytes read in 1266 ms (10.4 MiB/s)
Retrieving file: /extlinux/armada-8040-clearfog-gt-8k.dtb
## Current stack ends at 0x7fb23960
arch_lmb_reserve: bank_end: bfff ram_top: 8000
33368 bytes read in 31 ms (1 MiB/s)
## Current stack ends at 0x7fb23cd0
arch_lmb_reserve: bank_end: bfff ram_top: 8000
## Flattened Device Tree blob at 04f0
Booting using the fdt blob at 0x4f0
Loading Device Tree to bfff4000, end b257 ...
"Synchronous Abort" handler, esr 0x9645
elr: 0006e1cc lr : 00068fd8 (reloc)
elr: 7ffa91cc lr : 7ffa3fd8
x0 : x1 : bfffc258
x2 : x3 : 7da7
x4 : 04f08258 x5 : bfff4000
x6 : bfff4000 x7 : 000f
x8 : 7fb23bf8 x9 : 0008
x10: b257 x11: b257
x12: x13: f000
x14: bfff4000 x15: 0021
x16: 7ff7bc38 x17:
x18: 7fb2add0 x19: bfff4000
x20: 04f0 x21: b258
x22: 5882 x23: 0010
x24: 7ffe3c40 x25: 7fb23cb8
x26: c000 x27:
x28: 7fc3fd50 x29: 7fb23bd0
Code: 5461 aa0603e0 d65f03c0 38606882 (38206822)
Resetting CPU ...
Thanks,
baruch
> lmb_reserve(lmb, sp, bank_end - sp + 1);
> break;
> }
--
~. .~ Tk Open Systems
=}ooO--U--Ooo{=
- bar...@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
Re: [PATCH v1 00/16] Enable ARM Trusted Firmware for U-Boot
Chee Hong Ang schrieb am Mo., 17. Aug. 2020,
06:34:
> Repost of the following patchs:
> https://lists.denx.de/pipermail/u-boot/2020-March/402705.html
If this is a repost, please send as such instead of sending as a new series
v1.
Regards,
Simon
>
> New U-boot flow with ARM Trusted Firmware (ATF) support:
> SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
>
> SPL loads the u-boot.itb which consist of:
> 1) u-boot-nodtb.bin (U-Boot Proper image)
> 2) u-boot.dtb (U-Boot Proper DTB)
> 3) bl31.bin (ATF-BL31 image)
>
> Supported Platform: Intel SoCFPGA 64bits (Stratix10 & Agilex)
>
> Now, U-Boot Proper is running in non-secure mode (EL2), it invokes
> SMC/PSCI calls provided by ATF to perform COLD reset, System Manager
> register accesses and mailbox communications with Secure Device Manager
> (SDM).
>
> Steps to build the U-Boot with ATF support:
> 1) Build U-Boot
> 2) Build ATF BL31
> 3) Copy ATF BL31 binary image into U-Boot's root folder
> 4) "make u-boot.itb" to generate u-boot.itb
>
> These patchsets have dependency on:
> arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
> https://lists.denx.de/pipermail/u-boot/2020-August/423029.html
>
> Rename Stratix10 FPGA driver and support Agilex
> https://lists.denx.de/pipermail/u-boot/2020-August/422798.html
>
> SoCFPGA mailbox driver fixes and enhancements
> https://lists.denx.de/pipermail/u-boot/2020-August/423140.html
>
> arm: socfpga: soc64: Initialize timer in SPL only
> https://lists.denx.de/pipermail/u-boot/2020-July/419692.html
>
> arm: socfpga: soc64: Remove PHY interface setup from misc arch init
> https://lists.denx.de/pipermail/u-boot/2020-July/419690.html
>
> Enable sysreset support for SoCFPGA SoC64 platforms
> https://lists.denx.de/pipermail/u-boot/2020-August/422509.html
>
> arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
> https://lists.denx.de/pipermail/u-boot/2020-August/423373.html
>
> Chee Hong Ang (16):
> arm: socfpga: soc64: Remove CONFIG_OF_EMBED
> arm: socfpga: soc64: Add FIT generator script for pack itb with ATF
> arm: socfpga: Add function for checking description from FIT image
> arm: socfpga: soc64: Load FIT image with ATF support
> arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
> arm: socfpga: Disable "spin-table" method for booting Linux
> arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA
> (64bits)
> arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP
> services
> mmc: dwmmc: socfpga: Add ATF support for MMC driver
> net: designware: socfpga: Add ATF support for MAC driver
> arm: socfpga: soc64: Add ATF support for Reset Manager driver
> arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
> arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
> mbox_reset_cold()
> arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
> arm: socfpga: soc64: Skip handoff data access in SSBL
> configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
> support
>
> arch/arm/mach-socfpga/Kconfig | 2 -
> arch/arm/mach-socfpga/Makefile| 4 +
> arch/arm/mach-socfpga/board.c | 12 +-
> arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +
> arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++
> arch/arm/mach-socfpga/mailbox_s10.c | 5 +
> arch/arm/mach-socfpga/reset_manager_s10.c | 10 +
> arch/arm/mach-socfpga/smc_api.c | 56 ++
> arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 +-
> board/altera/soc64/fit_spl_atf.sh | 91 +++
> ...defconfig => socfpga_agilex_atf_defconfig} | 25 +-
> configs/socfpga_agilex_defconfig | 1 -
> ...config => socfpga_stratix10_atf_defconfig} | 25 +-
> configs/socfpga_stratix10_defconfig | 1 -
> drivers/fpga/intel_sdm_mb.c | 139 +
> drivers/mmc/socfpga_dw_mmc.c | 20 +
> drivers/net/dwmac_socfpga.c | 43 +-
> include/configs/socfpga_soc64_common.h| 9 +
> include/linux/intel-smc.h | 573 ++
> 19 files changed, 1078 insertions(+), 30 deletions(-)
> create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
> create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S
> create mode 100644 arch/arm/mach-socfpga/smc_api.c
> create mode 100755 board/altera/soc64/fit_spl_atf.sh
> copy configs/{socfpga_agilex_defconfig => socfpga_agilex_atf_defconfig}
> (77%)
> copy configs/{socfpga_stratix10_defconfig =>
> socfpga_stratix10_atf_defconfig} (80%)
> create mode 100644 include/linux/intel-smc.h
>
> --
> 2.19.0
>
>
Re: [PATCH v2 0/5] powerpc, mpc83xx: add DM_ETH support
Hello Mario, Am 27.05.2020 um 14:43 schrieb Heiko Schocher: This patch series adds DM ethernet support for mpc83xx based keymile boards. Travis build: https://travis-ci.org/github/hsdenx/u-boot-test/builds/691607214 Changes in v2: - new in v2 - remove RFC - fixed Codingstyle errors, therefore new patch powerpc, mpc83xx: fix codingstyle issues for qe_io.c - moved DM part to drivers/pinctrl - add comments from Qiang Zhao: - add device node documentation - I did not drop the dm_qe_uec_phy.c and use drivers/net/fsl_mdio.c because using drivers/net/fsl_mdio.c leads in none existent udevice mdio@3320 instead boards with DM ETH support should use now this driver. - remove RFC tag - add patch which fixes Codingstyle errors in drivers/qe - add patch which converts the mpc83xx based boards from keymile to DM_ETH Heiko Schocher (5): mpc83xx: remove unneeded extern declaration in cpu_init powerpc, qe: fix codingstyle issues for drivers/qe powerpc, qe: add DTS support for parallel I/O ports net, qe: add DM support for QE UEC ethernet mpc83xx, keymile boards: enable DM_ETH and add DTS arch/powerpc/cpu/mpc83xx/Kconfig |8 + arch/powerpc/cpu/mpc83xx/Makefile |2 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 11 +- arch/powerpc/cpu/mpc83xx/qe_io.c | 98 +- arch/powerpc/dts/Makefile |8 + arch/powerpc/dts/km8309-uboot.dtsi| 33 + arch/powerpc/dts/km8321-uboot.dtsi| 67 + arch/powerpc/dts/km8321.dtsi | 220 arch/powerpc/dts/km836x-uboot.dtsi| 61 + arch/powerpc/dts/km836x.dtsi | 182 +++ arch/powerpc/dts/kmcoge5ne-uboot.dtsi | 22 + arch/powerpc/dts/kmcoge5ne.dts| 320 + arch/powerpc/dts/kmeter1-uboot.dtsi | 42 + arch/powerpc/dts/kmeter1.dts | 480 +++ arch/powerpc/dts/kmopti2.dts | 161 +++ arch/powerpc/dts/kmsupc5.dts | 139 ++ arch/powerpc/dts/kmsupm5.dts | 129 ++ arch/powerpc/dts/kmtegr1.dts | 392 ++ arch/powerpc/dts/kmtepr2.dts | 142 ++ arch/powerpc/dts/kmtuge1.dts | 100 ++ arch/powerpc/dts/kmtuxa1.dts | 100 ++ board/keymile/km83xx/Kconfig | 17 + board/keymile/km83xx/MAINTAINERS | 23 +- board/keymile/km83xx/km83xx.c | 64 - configs/kmcoge5ne_defconfig | 11 +- configs/kmeter1_defconfig | 10 +- configs/kmopti2_defconfig | 11 +- configs/kmsupx5_defconfig | 10 +- configs/kmtegr1_defconfig | 12 +- configs/kmtepr2_defconfig | 10 +- configs/tuge1_defconfig | 10 +- configs/tuxx1_defconfig | 11 +- .../soc/fsl/cpm_qe/qe/ucc.txt | 53 + drivers/net/Kconfig |2 + drivers/net/Makefile |1 + drivers/net/qe/Kconfig|9 + drivers/net/qe/Makefile |5 + drivers/net/qe/dm_qe_uec.c| 1167 + drivers/net/qe/dm_qe_uec.h| 22 + drivers/net/qe/dm_qe_uec_phy.c| 163 +++ drivers/net/qe/uccf.c | 507 +++ drivers/net/qe/uccf.h | 119 ++ drivers/net/qe/uec.h | 693 ++ drivers/pinctrl/Kconfig |7 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/pinctrl-qe-io.c | 255 drivers/qe/qe.c | 96 +- drivers/qe/uccf.c | 449 --- drivers/qe/uccf.h | 90 +- drivers/qe/uec.c | 598 - drivers/qe/uec.h | 381 +++--- drivers/qe/uec_phy.c | 334 ++--- drivers/qe/uec_phy.h | 71 +- include/configs/km/km-mpc832x.h | 14 - include/configs/km/km-mpc8360.h | 14 - include/configs/km/km-mpc83xx.h | 10 - include/fsl_qe.h |3 + 57 files changed, 6826 insertions(+), 1144 deletions(-) create mode 100644 arch/powerpc/dts/km8309-uboot.dtsi create mode 100644 arch/powerpc/dts/km8321-uboot.dtsi create mode 100644 arch/powerpc/dts/km8321.dtsi create mode 100644 arch/powerpc/dts/km836x-uboot.dtsi create mode 100644 arch/powerpc/dts/km836x.dtsi create mode 100644 arch/powerpc/dts/kmcoge5ne-uboot.dtsi create mode 100644 arch/powerpc/dts/kmcoge5ne.dts create mode 100644 arch/powerpc/dts/kmeter1-uboot.dtsi create mo
[PATCH 1/3] firmware: ti_sci: drop the device ids to resource id translation table
With ABI 3.0, sysfw deprecated special resource types used for AM65x
SoC. Instead started using device id as resource type similar to the
convention used in J721E SOC.
Signed-off-by: Lokesh Vutla
---
drivers/firmware/ti_sci.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 15f5b0b14c..a784b4ea29 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -3175,16 +3175,6 @@ static const struct ti_sci_desc ti_sci_pmmc_k2g_desc = {
.rm_type_map = NULL,
};
-static struct ti_sci_rm_type_map ti_sci_am654_rm_type_map[] = {
- {.dev_id = 56, .type = 0x00b}, /* GIC_IRQ */
- {.dev_id = 179, .type = 0x000}, /* MAIN_NAV_UDMASS_IA0 */
- {.dev_id = 187, .type = 0x009}, /* MAIN_NAV_RA */
- {.dev_id = 188, .type = 0x006}, /* MAIN_NAV_UDMAP */
- {.dev_id = 194, .type = 0x007}, /* MCU_NAV_UDMAP */
- {.dev_id = 195, .type = 0x00a}, /* MCU_NAV_RA */
- {.dev_id = 0, .type = 0x000}, /* end of table */
-};
-
/* Description for AM654 */
static const struct ti_sci_desc ti_sci_pmmc_am654_desc = {
.default_host_id = 12,
@@ -3193,7 +3183,7 @@ static const struct ti_sci_desc ti_sci_pmmc_am654_desc = {
/* Limited by MBOX_TX_QUEUE_LEN. K2G can handle upto 128 messages! */
.max_msgs = 20,
.max_msg_size = 60,
- .rm_type_map = ti_sci_am654_rm_type_map,
+ .rm_type_map = NULL,
};
static const struct udevice_id ti_sci_ids[] = {
--
2.27.0
[PATCH 2/3] firmware: ti_sci: Drop unused structure ti_sci_rm_type_map
struct ti_sci_rm_type_map is no longer used. Drop its definition and its
declarations.
Signed-off-by: Lokesh Vutla
---
drivers/firmware/ti_sci.c | 52 +++
1 file changed, 3 insertions(+), 49 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index a784b4ea29..e311f55ef8 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -60,14 +60,12 @@ struct ti_sci_rm_type_map {
* @max_msgs: Maximum number of messages that can be pending
* simultaneously in the system
* @max_msg_size: Maximum size of data per message that can be handled.
- * @rm_type_map: RM resource type mapping structure.
*/
struct ti_sci_desc {
u8 default_host_id;
int max_rx_timeout_ms;
int max_msgs;
int max_msg_size;
- struct ti_sci_rm_type_map *rm_type_map;
};
/**
@@ -1605,33 +1603,6 @@ static int ti_sci_cmd_core_reboot(const struct
ti_sci_handle *handle)
return ret;
}
-static int ti_sci_get_resource_type(struct ti_sci_info *info, u16 dev_id,
- u16 *type)
-{
- struct ti_sci_rm_type_map *rm_type_map = info->desc->rm_type_map;
- bool found = false;
- int i;
-
- /* If map is not provided then assume dev_id is used as type */
- if (!rm_type_map) {
- *type = dev_id;
- return 0;
- }
-
- for (i = 0; rm_type_map[i].dev_id; i++) {
- if (rm_type_map[i].dev_id == dev_id) {
- *type = rm_type_map[i].type;
- found = true;
- break;
- }
- }
-
- if (!found)
- return -EINVAL;
-
- return 0;
-}
-
/**
* ti_sci_get_resource_range - Helper to get a range of resources assigned
*to a host. Resource is uniquely identified by
@@ -1654,7 +1625,6 @@ static int ti_sci_get_resource_range(const struct
ti_sci_handle *handle,
struct ti_sci_msg_req_get_resource_range req;
struct ti_sci_xfer *xfer;
struct ti_sci_info *info;
- u16 type;
int ret = 0;
if (IS_ERR(handle))
@@ -1673,14 +1643,8 @@ static int ti_sci_get_resource_range(const struct
ti_sci_handle *handle,
return ret;
}
- ret = ti_sci_get_resource_type(info, dev_id, &type);
- if (ret) {
- dev_err(dev, "rm type lookup failed for %u\n", dev_id);
- goto fail;
- }
-
req.secondary_host = s_host;
- req.type = type & MSG_RM_RESOURCE_TYPE_MASK;
+ req.type = dev_id & MSG_RM_RESOURCE_TYPE_MASK;
req.subtype = subtype & MSG_RM_RESOURCE_SUBTYPE_MASK;
ret = ti_sci_do_xfer(info, xfer);
@@ -3096,7 +3060,6 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle
*handle,
struct udevice *dev, u32 dev_id, char *of_prop)
{
u32 resource_subtype;
- u16 resource_type;
struct ti_sci_resource *res;
bool valid_set = false;
int sets, i, ret;
@@ -3120,13 +3083,6 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle
*handle,
if (!res->desc)
return ERR_PTR(-ENOMEM);
- ret = ti_sci_get_resource_type(handle_to_ti_sci_info(handle), dev_id,
- &resource_type);
- if (ret) {
- dev_err(dev, "No valid resource type for %u\n", dev_id);
- return ERR_PTR(-EINVAL);
- }
-
ret = dev_read_u32_array(dev, of_prop, temp, res->sets);
if (ret)
return ERR_PTR(-EINVAL);
@@ -3139,7 +3095,7 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle
*handle,
&res->desc[i].num);
if (ret) {
dev_dbg(dev, "type %d subtype %d not allocated for host
%d\n",
- resource_type, resource_subtype,
+ dev_id, resource_subtype,
handle_to_ti_sci_info(handle)->host_id);
res->desc[i].start = 0;
res->desc[i].num = 0;
@@ -3148,7 +3104,7 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle
*handle,
valid_set = true;
dev_dbg(dev, "res type = %d, subtype = %d, start = %d, num =
%d\n",
- resource_type, resource_subtype, res->desc[i].start,
+ dev_id, resource_subtype, res->desc[i].start,
res->desc[i].num);
res->desc[i].res_map =
@@ -3172,7 +3128,6 @@ static const struct ti_sci_desc ti_sci_pmmc_k2g_desc = {
/* Limited by MBOX_TX_QUEUE_LEN. K2G can handle upto 128 messages! */
.max_msgs = 20,
.max_msg_size = 64,
- .rm_type_map = NULL,
};
/* Description for AM654 */
@@ -3183,7 +3138,6 @@ static const struct ti_sci_desc ti_sci_pmmc
[PATCH 0/3] arm: k3: Update to SYFW ABI 3.0 changes
Update the ti_sci driver and am65x dts to support SYSFW ABI 3.0. This series is meant to be merged only after sysfw releases 2020.02 binaries. Corresponding kernel changes are applied to linux-next[0] [0] https://patchwork.kernel.org/cover/11703313/ Lokesh Vutla (3): firmware: ti_sci: drop the device ids to resource id translation table firmware: ti_sci: Drop unused structure ti_sci_rm_type_map arm: dts: k3-am65: Update the RM resource types arch/arm/dts/k3-am65-mcu.dtsi | 12 +++ drivers/firmware/ti_sci.c | 62 ++- 2 files changed, 9 insertions(+), 65 deletions(-) -- 2.27.0
[PATCH 3/3] arm: dts: k3-am65: Update the RM resource types
Update the ringacc and udma dt nodes to use the latest RM resource types similar to the ones used in k3-j721e dt nodes. Signed-off-by: Lokesh Vutla --- arch/arm/dts/k3-am65-mcu.dtsi | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi index 9717cae0a8..0b07e188b5 100644 --- a/arch/arm/dts/k3-am65-mcu.dtsi +++ b/arch/arm/dts/k3-am65-mcu.dtsi @@ -135,7 +135,7 @@ <0x0 0x2a50 0x0 0x4>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,dma-ring-reset-quirk; ti,sci = <&dmsc>; ti,sci-dev-id = <195>; @@ -153,11 +153,11 @@ ti,sci-dev-id = <194>; ti,ringacc = <&mcu_ringacc>; - ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */ - <0x2>; /* TX_CHAN */ - ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */ - <0x4>; /* RX_CHAN */ - ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */ + ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ + <0xd>; /* TX_CHAN */ + ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ + <0xa>; /* RX_CHAN */ + ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ }; }; -- 2.27.0
RE: [PATCH v1 00/16] Enable ARM Trusted Firmware for U-Boot
Chee Hong Ang mailto:chee.hong@intel.com>> schrieb
am Mo., 17. Aug. 2020, 06:34:
Repost of the following patchs:
https://lists.denx.de/pipermail/u-boot/2020-March/402705.html
> If this is a repost, please send as such instead of sending as a new series
> v1.
Sorry, please ignore the repost. This patch series has some new changes which I
think should be new series itself.
> Regards,
> Simon
New U-boot flow with ARM Trusted Firmware (ATF) support:
SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
SPL loads the u-boot.itb which consist of:
1) u-boot-nodtb.bin (U-Boot Proper image)
2) u-boot.dtb (U-Boot Proper DTB)
3) bl31.bin (ATF-BL31 image)
Supported Platform: Intel SoCFPGA 64bits (Stratix10 & Agilex)
Now, U-Boot Proper is running in non-secure mode (EL2), it invokes
SMC/PSCI calls provided by ATF to perform COLD reset, System Manager
register accesses and mailbox communications with Secure Device Manager
(SDM).
Steps to build the U-Boot with ATF support:
1) Build U-Boot
2) Build ATF BL31
3) Copy ATF BL31 binary image into U-Boot's root folder
4) "make u-boot.itb" to generate u-boot.itb
These patchsets have dependency on:
arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
https://lists.denx.de/pipermail/u-boot/2020-August/423029.html
Rename Stratix10 FPGA driver and support Agilex
https://lists.denx.de/pipermail/u-boot/2020-August/422798.html
SoCFPGA mailbox driver fixes and enhancements
https://lists.denx.de/pipermail/u-boot/2020-August/423140.html
arm: socfpga: soc64: Initialize timer in SPL only
https://lists.denx.de/pipermail/u-boot/2020-July/419692.html
arm: socfpga: soc64: Remove PHY interface setup from misc arch init
https://lists.denx.de/pipermail/u-boot/2020-July/419690.html
Enable sysreset support for SoCFPGA SoC64 platforms
https://lists.denx.de/pipermail/u-boot/2020-August/422509.html
arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
https://lists.denx.de/pipermail/u-boot/2020-August/423373.html
Chee Hong Ang (16):
arm: socfpga: soc64: Remove CONFIG_OF_EMBED
arm: socfpga: soc64: Add FIT generator script for pack itb with ATF
arm: socfpga: Add function for checking description from FIT image
arm: socfpga: soc64: Load FIT image with ATF support
arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
arm: socfpga: Disable "spin-table" method for booting Linux
arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA
(64bits)
arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP
services
mmc: dwmmc: socfpga: Add ATF support for MMC driver
net: designware: socfpga: Add ATF support for MAC driver
arm: socfpga: soc64: Add ATF support for Reset Manager driver
arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
mbox_reset_cold()
arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
arm: socfpga: soc64: Skip handoff data access in SSBL
configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
support
arch/arm/mach-socfpga/Kconfig | 2 -
arch/arm/mach-socfpga/Makefile| 4 +
arch/arm/mach-socfpga/board.c | 12 +-
arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +
arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
arch/arm/mach-socfpga/reset_manager_s10.c | 10 +
arch/arm/mach-socfpga/smc_api.c | 56 ++
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 +-
board/altera/soc64/fit_spl_atf.sh | 91 +++
...defconfig => socfpga_agilex_atf_defconfig} | 25 +-
configs/socfpga_agilex_defconfig | 1 -
...config => socfpga_stratix10_atf_defconfig} | 25 +-
configs/socfpga_stratix10_defconfig | 1 -
drivers/fpga/intel_sdm_mb.c | 139 +
drivers/mmc/socfpga_dw_mmc.c | 20 +
drivers/net/dwmac_socfpga.c | 43 +-
include/configs/socfpga_soc64_common.h| 9 +
include/linux/intel-smc.h | 573 ++
19 files changed, 1078 insertions(+), 30 deletions(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S
create mode 100644 arch/arm/mach-socfpga/smc_api.c
create mode 100755 board/altera/soc64/fit_spl_atf.sh
copy configs/{socfpga_agilex_defconfig => socfpga_agilex_atf_defconfig} (77%)
copy configs/{socfpga_stratix10_defconfig => socfpga_stratix10_atf_defconfig}
(80%)
create mode 100644 include/linux/intel-smc.h
--
2.19.0
RE: [PATCH v1 14/15] x86: intel: slimbootloader: Remove dead code
> -Original Message- > From: Andy Shevchenko > Sent: Thursday, August 6, 2020 7:55 AM > To: Simon Glass ; Bin Meng ; u- > b...@lists.denx.de > Cc: Andy Shevchenko ; Park, Aiden > > Subject: [PATCH v1 14/15] x86: intel: slimbootloader: Remove dead code > > start.S does nothing and can be safely removed. Makefile is still being used > by > the build system, so simply drop the rule from it. > > Cc: Aiden Park > Signed-off-by: Andy Shevchenko > --- > board/intel/slimbootloader/Makefile | 2 +- > board/intel/slimbootloader/start.S > | 9 - > 2 files changed, 1 insertion(+), 10 deletions(-) delete mode 100644 > board/intel/slimbootloader/start.S > > diff --git a/board/intel/slimbootloader/Makefile > b/board/intel/slimbootloader/Makefile > index fd8fa98a8d39..50330cc6e5db 100644 > --- a/board/intel/slimbootloader/Makefile > +++ b/board/intel/slimbootloader/Makefile > @@ -2,4 +2,4 @@ > # > # Copyright (C) 2019 Intel Corporation > > -obj-y+= start.o slimbootloader.o > +obj-y+= slimbootloader.o > diff --git a/board/intel/slimbootloader/start.S > b/board/intel/slimbootloader/start.S > deleted file mode 100644 > index 5c3f3df09eb0.. > --- a/board/intel/slimbootloader/start.S > +++ /dev/null > @@ -1,9 +0,0 @@ > -/* SPDX-License-Identifier: GPL-2.0+ */ > -/* > - * Copyright (C) 2019 Intel Corporation > - */ > - > -/* board early initialization */ > -.globl early_board_init > -early_board_init: > - jmp early_board_init_ret > -- > 2.27.0 Reviewed-by: Aiden Park
RE: [PATCH v1 01/15] x86: Introduce USE_EARLY_BOARD_INIT option
> -Original Message- > From: Andy Shevchenko > Sent: Thursday, August 6, 2020 7:54 AM > To: Simon Glass ; Bin Meng ; u- > b...@lists.denx.de > Cc: Andy Shevchenko ; Park, Aiden > ; Stefan Roese ; George McCollister > > Subject: [PATCH v1 01/15] x86: Introduce USE_EARLY_BOARD_INIT option > > Introduce USE_EARLY_BOARD_INIT option and select it by the actual users. > > Cc: Aiden Park > Cc: Stefan Roese > Cc: George McCollister > Signed-off-by: Andy Shevchenko > --- > arch/x86/Kconfig | 3 +++ > arch/x86/cpu/start.S | 3 +++ > board/google/chromebook_coral/Kconfig | 1 + > board/google/chromebook_link/Kconfig | 1 + > board/google/chromebook_samus/Kconfig | 1 + > 5 files changed, 9 insertions(+) > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index > ff4f06ed79cc..167cc96205c5 100644 > --- a/arch/x86/Kconfig > +++ b/arch/x86/Kconfig > @@ -203,6 +203,9 @@ config SPL_X86_32BIT_INIT > help > This is enabled when 32-bit init is in SPL > > +config USE_EARLY_BOARD_INIT > + bool > + > config RESET_SEG_START > hex > depends on X86_RESET_VECTOR > diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index > 4ad515ce0856..8d00c97db42c 100644 > --- a/arch/x86/cpu/start.S > +++ b/arch/x86/cpu/start.S > @@ -88,6 +88,7 @@ _start: > /* Clear the interrupt vectors */ > lidtblank_idt_ptr > > +#ifdef USE_EARLY_BOARD_INIT > /* >* Critical early platform init - generally not used, we prefer init >* to happen later when we have a console, in case something goes @@ > -96,6 +97,8 @@ _start: > jmp early_board_init > .globl early_board_init_ret > early_board_init_ret: > +#endif > + > post_code(POST_START) > > /* Initialise Cache-As-RAM */ > diff --git a/board/google/chromebook_coral/Kconfig > b/board/google/chromebook_coral/Kconfig > index 940bee89b0b6..27671958e146 100644 > --- a/board/google/chromebook_coral/Kconfig > +++ b/board/google/chromebook_coral/Kconfig > @@ -18,6 +18,7 @@ config SYS_TEXT_BASE > config BOARD_SPECIFIC_OPTIONS # dummy > def_bool y > select X86_RESET_VECTOR > + select USE_EARLY_BOARD_INIT > select INTEL_APOLLOLAKE > select BOARD_ROMSIZE_KB_16384 > > diff --git a/board/google/chromebook_link/Kconfig > b/board/google/chromebook_link/Kconfig > index 944716d002c9..dd29ddf694be 100644 > --- a/board/google/chromebook_link/Kconfig > +++ b/board/google/chromebook_link/Kconfig > @@ -19,6 +19,7 @@ config SYS_TEXT_BASE > config BOARD_SPECIFIC_OPTIONS # dummy > def_bool y > select X86_RESET_VECTOR > + select USE_EARLY_BOARD_INIT > select NORTHBRIDGE_INTEL_IVYBRIDGE > select HAVE_INTEL_ME > select BOARD_ROMSIZE_KB_8192 > diff --git a/board/google/chromebook_samus/Kconfig > b/board/google/chromebook_samus/Kconfig > index 90c23cba1bed..9f66d7998870 100644 > --- a/board/google/chromebook_samus/Kconfig > +++ b/board/google/chromebook_samus/Kconfig > @@ -19,6 +19,7 @@ config SYS_TEXT_BASE > config BOARD_SPECIFIC_OPTIONS # dummy > def_bool y > select X86_RESET_VECTOR > + select USE_EARLY_BOARD_INIT > select INTEL_BROADWELL > select HAVE_INTEL_ME > select BOARD_ROMSIZE_KB_8192 > -- > 2.27.0 Reviewed-by: Aiden Park
[PATCH v3 3/3] doc: verified-boot: add required-mode information
Add documentation about 'required-mode' property in /signature node in U-Boot's control FDT. Signed-off-by: Thirupathaiah Annapureddy Reviewed-by: Simon Glass --- Changes in v3: - Added commit description to address checkpatch warning. Changes in v2: - New. doc/uImage.FIT/signature.txt | 14 ++ 1 file changed, 14 insertions(+) diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt index d4afd755e9..a3455889ed 100644 --- a/doc/uImage.FIT/signature.txt +++ b/doc/uImage.FIT/signature.txt @@ -386,6 +386,20 @@ that might be used by the target needs to be signed with 'required' keys. This happens automatically as part of a bootm command when FITs are used. +For Signed Configurations, the default verification behavior can be changed by +the following optional property in /signature node in U-Boot's control FDT. + +- required-mode: Valid values are "any" to allow verified boot to succeed if +the selected configuration is signed by any of the 'required' keys, and "all" +to allow verified boot to succeed if the selected configuration is signed by +all of the 'required' keys. + +This property can be added to a binary device tree using fdtput as shown in +below examples:: + + fdtput -t s control.dtb /signature required-mode any + fdtput -t s control.dtb /signature required-mode all + Enabling FIT Verification - -- 2.25.2
[PATCH v3 0/3] Add support for multiple required keys
This patch series adds the support for multiple required keys in U-Boot DTB with test support. Changes in v3: - Replaced 'u-boot' with 'U-Boot' in commit messages. - Added an explicit print message to indicate that no required signature was verified. Changes in v2 (thanks for the feedback Simon and Rasmus): - Introduce a policy variable in U-boot DTB to control whether any or all required keys must have signed configuration. - Added tests to cover any or all required keys policy. - Updated signature.txt to include required-mode policy information. Thirupathaiah Annapureddy (3): vboot: add DTB policy for supporting multiple required conf keys test: vboot: add tests for multiple required keys doc: verified-boot: add required-mode information common/image-fit-sig.c | 32 ++--- doc/uImage.FIT/signature.txt | 14 +++ test/py/tests/test_vboot.py | 46 ++-- 3 files changed, 87 insertions(+), 5 deletions(-) -- 2.25.2
[PATCH v3 2/3] test: vboot: add tests for multiple required keys
This patch adds vboot tests to verify the support for multiple
required keys using new required-mode DTB policy.
This patch also fixes existing test where dev
key is assumed to be marked as not required, although
it is marked as required.
Note that this patch re-added sign_fit_norequire().
sign_fit_norequire() was removed as part of the following:
commit b008677daf2a ("test: vboot: Fix pylint errors").
This patch leverages sign_fit_norequire() to fix the
existing bug.
Signed-off-by: Thirupathaiah Annapureddy
Reviewed-by: Simon Glass
---
Changes in v3:
- Modified commit message to reference earlier commit the right way.
Changes in v2:
- Added tests to cover any or all required keys policy.
test/py/tests/test_vboot.py | 46 +++--
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
index 6b998cfd70..e45800d94c 100644
--- a/test/py/tests/test_vboot.py
+++ b/test/py/tests/test_vboot.py
@@ -126,6 +126,23 @@ def test_vboot(u_boot_console, sha_algo, padding,
sign_options, required):
cons.log.action('%s: Sign images' % sha_algo)
util.run_and_log(cons, args)
+def sign_fit_norequire(sha_algo, options):
+"""Sign the FIT
+
+Signs the FIT and writes the signature into it. It also writes the
+public key into the dtb. It does not mark key as 'required' in dtb.
+
+Args:
+sha_algo: Either 'sha1' or 'sha256', to select the algorithm to
+use.
+options: Options to provide to mkimage.
+"""
+args = [mkimage, '-F', '-k', tmpdir, '-K', dtb, fit]
+if options:
+args += options.split(' ')
+cons.log.action('%s: Sign images' % sha_algo)
+util.run_and_log(cons, args)
+
def replace_fit_totalsize(size):
"""Replace FIT header's totalsize with something greater.
@@ -279,15 +296,40 @@ def test_vboot(u_boot_console, sha_algo, padding,
sign_options, required):
# Build the FIT with dev key (keys NOT required). This adds the
# signature into sandbox-u-boot.dtb, NOT marked 'required'.
make_fit('sign-configs-%s%s.its' % (sha_algo, padding))
-sign_fit(sha_algo, sign_options)
+sign_fit_norequire(sha_algo, sign_options)
# So now sandbox-u-boot.dtb two signatures, for the prod and dev keys.
# Only the prod key is set as 'required'. But FIT we just built has
-# a dev signature only (sign_fit() overwrites the FIT).
+# a dev signature only (sign_fit_norequire() overwrites the FIT).
# Try to boot the FIT with dev key. This FIT should not be accepted by
# U-Boot because the prod key is required.
run_bootm(sha_algo, 'required key', '', False)
+# Build the FIT with dev key (keys required) and sign it. This puts the
+# signature into sandbox-u-boot.dtb, marked 'required'.
+make_fit('sign-configs-%s%s.its' % (sha_algo, padding))
+sign_fit(sha_algo, sign_options)
+
+# Set the required-mode policy to "any".
+# So now sandbox-u-boot.dtb two signatures, for the prod and dev keys.
+# Both the dev and prod key are set as 'required'. But FIT we just
built has
+# a dev signature only (sign_fit() overwrites the FIT).
+# Try to boot the FIT with dev key. This FIT should be accepted by
+# U-Boot because the dev key is required and policy is "any" required
key.
+util.run_and_log(cons, 'fdtput -t s %s /signature required-mode any' %
+ (dtb))
+run_bootm(sha_algo, 'multi required key', 'dev+', True)
+
+# Set the required-mode policy to "all".
+# So now sandbox-u-boot.dtb two signatures, for the prod and dev keys.
+# Both the dev and prod key are set as 'required'. But FIT we just
built has
+# a dev signature only (sign_fit() overwrites the FIT).
+# Try to boot the FIT with dev key. This FIT should not be accepted by
+# U-Boot because the prod key is required and policy is "all" required
key
+util.run_and_log(cons, 'fdtput -t s %s /signature required-mode all' %
+ (dtb))
+run_bootm(sha_algo, 'multi required key', '', False)
+
cons = u_boot_console
tmpdir = cons.config.result_dir + '/'
datadir = cons.config.source_dir + '/test/py/tests/vboot/'
--
2.25.2
[PATCH v3 1/3] vboot: add DTB policy for supporting multiple required conf keys
Currently FIT image must be signed by all required conf keys. This means
Verified Boot fails if there is a signature verification failure
using any required key in U-Boot DTB.
This patch introduces a new policy in DTB that can be set to any required
conf key. This means if verified boot passes with one of the required
keys, U-Boot will continue the OS hand off.
There were prior attempts to address this:
https://lists.denx.de/pipermail/u-boot/2019-April/366047.html
The above patch was failing "make tests".
https://lists.denx.de/pipermail/u-boot/2020-January/396629.html
Signed-off-by: Thirupathaiah Annapureddy
Reviewed-by: Simon Glass
---
Changes in v3:
- Replaced 'u-boot' with 'U-Boot' in commit message.
- Added an explicit print message to indicate that no required signature
was verified.
Changes in v2:
- Modify fit_config_verify_required_sigs() to process required-mode
policy variable in U-boot DTB.
common/image-fit-sig.c | 32 +---
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/common/image-fit-sig.c b/common/image-fit-sig.c
index cc1967109e..5401d9411b 100644
--- a/common/image-fit-sig.c
+++ b/common/image-fit-sig.c
@@ -416,6 +416,10 @@ int fit_config_verify_required_sigs(const void *fit, int
conf_noffset,
{
int noffset;
int sig_node;
+ int verified = 0;
+ int reqd_sigs = 0;
+ bool reqd_policy_all = true;
+ const char *reqd_mode;
/* Work out what we need to verify */
sig_node = fdt_subnode_offset(sig_blob, 0, FIT_SIG_NODENAME);
@@ -425,6 +429,14 @@ int fit_config_verify_required_sigs(const void *fit, int
conf_noffset,
return 0;
}
+ /* Get required-mode policy property from DTB */
+ reqd_mode = fdt_getprop(sig_blob, sig_node, "required-mode", NULL);
+ if (reqd_mode && !strcmp(reqd_mode, "any"))
+ reqd_policy_all = false;
+
+ debug("%s: required-mode policy set to '%s'\n", __func__,
+ reqd_policy_all ? "all" : "any");
+
fdt_for_each_subnode(noffset, sig_blob, sig_node) {
const char *required;
int ret;
@@ -433,15 +445,29 @@ int fit_config_verify_required_sigs(const void *fit, int
conf_noffset,
NULL);
if (!required || strcmp(required, "conf"))
continue;
+
+ reqd_sigs++;
+
ret = fit_config_verify_sig(fit, conf_noffset, sig_blob,
noffset);
if (ret) {
- printf("Failed to verify required signature '%s'\n",
- fit_get_name(sig_blob, noffset, NULL));
- return ret;
+ if (reqd_policy_all) {
+ printf("Failed to verify required signature
'%s'\n",
+ fit_get_name(sig_blob, noffset, NULL));
+ return ret;
+ }
+ } else {
+ verified++;
+ if (!reqd_policy_all)
+ break;
}
}
+ if (reqd_sigs && !verified) {
+ printf("Failed to verify 'any' of the required signature(s)\n");
+ return -EPERM;
+ }
+
return 0;
}
--
2.25.2
Re: [PATCH v1 09/10] arm: dts: mt7622: add USB nodes
Am 17. August 2020 04:59:05 MESZ schrieb Chunfeng Yun
:
>> +u3port0: usb-phy@1a0c4900 {
>> +reg = <0x1a0c4900 0x0700>;
>> +#phy-cells = <1>;
>> +clocks = <&clk25m>;
>> +clock-names = "ref";
>clock is optional, if we can't control it, skip it is also fine.
Tested without the clock,still works...i'll remove it (and clk25m above) in v2
Can you review the other patches from this series too?
regards Frank
[PATCH v2 04/11] usb: xhci: convert to HCS_MAX_PORTS()
Use HCS_MAX_PORTS(p) instead of
((p & HCS_MAX_PORTS_MASK) >> HCS_MAX_PORTS_SHIFT)
Signed-off-by: Chunfeng Yun
---
v2: no changes
---
drivers/usb/host/xhci.c | 3 +--
include/usb/xhci.h | 2 --
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 51edeb2..5f3a0fb 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -1257,8 +1257,7 @@ static int xhci_lowlevel_init(struct xhci_ctrl *ctrl)
return -ENOMEM;
reg = xhci_readl(&hccr->cr_hcsparams1);
- descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
- HCS_MAX_PORTS_SHIFT);
+ descriptor.hub.bNbrPorts = HCS_MAX_PORTS(reg);
printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
/* Port Indicators */
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 3de46cd..cf4c020 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -101,8 +101,6 @@ struct xhci_hccr {
/* bits 8:18, Max Interrupters */
#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
-#define HCS_MAX_PORTS_SHIFT24
-#define HCS_MAX_PORTS_MASK (0xff << HCS_MAX_PORTS_SHIFT)
#define HCS_MAX_PORTS(p) (((p) >> 24) & 0xff)
/* HCSPARAMS2 - hcs_params2 - bitmasks */
--
1.9.1
[PATCH v2 02/11] usb: xhci: create one unified function to calculate TRB TD remainder.
xhci versions 1.0 and later report the untransferred data remaining in a
TD a bit differently than older hosts.
We used to have separate functions for these, and needed to check host
version before calling the right function.
Now Mediatek host has an additional quirk on how it uses the TD Size
field for remaining data. To prevent yet another function for calculating
remainder we instead want to make one quirk friendly unified function.
Porting from the Linux:
c840d6ce772d("xhci: create one unified function to calculate TRB TD remainder.")
124c39371114("xhci: use boolean to indicate last trb in td remainder
calculation")
Signed-off-by: Chunfeng Yun
---
v2: no changes
---
drivers/usb/host/xhci-ring.c | 105 +--
include/usb/xhci.h | 2 +
2 files changed, 52 insertions(+), 55 deletions(-)
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 79bfc34..0f86b01 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -298,55 +298,52 @@ void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr,
u32 slot_id,
xhci_writel(&ctrl->dba->doorbell[0], DB_VALUE_HOST);
}
-/**
- * The TD size is the number of bytes remaining in the TD (including this TRB),
- * right shifted by 10.
- * It must fit in bits 21:17, so it can't be bigger than 31.
+/*
+ * For xHCI 1.0 host controllers, TD size is the number of max packet sized
+ * packets remaining in the TD (*not* including this TRB).
*
- * @param remainderremaining packets to be sent
- * @return remainder if remainder is less than max else max
- */
-static u32 xhci_td_remainder(unsigned int remainder)
-{
- u32 max = (1 << (21 - 17 + 1)) - 1;
-
- if ((remainder >> 10) >= max)
- return max << 17;
- else
- return (remainder >> 10) << 17;
-}
-
-/**
- * Finds out the remanining packets to be sent
+ * Total TD packet count = total_packet_count =
+ * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
+ *
+ * Packets transferred up to and including this TRB = packets_transferred =
+ * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
+ *
+ * TD size = total_packet_count - packets_transferred
*
- * @param running_totaltotal size sent so far
+ * For xHCI 0.96 and older, TD size field should be the remaining bytes
+ * including this TRB, right shifted by 10
+ *
+ * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
+ * This is taken care of in the TRB_TD_SIZE() macro
+ *
+ * The last TRB in a TD must have the TD size set to zero.
+ *
+ * @param ctrl host controller data structure
+ * @param transferred total size sent so far
* @param trb_buff_len length of the TRB Buffer
- * @param total_packet_count total packet count
- * @param maxpacketsizemax packet size of current pipe
- * @param num_trbs_leftnumber of TRBs left to be processed
- * @return 0 if running_total or trb_buff_len is 0, else remainder
+ * @param td_total_len total packet count
+ * @param maxp max packet size of current pipe
+ * @param more_trbs_coming indicate last trb in TD
+ * @return remainder
*/
-static u32 xhci_v1_0_td_remainder(int running_total,
- int trb_buff_len,
- unsigned int total_packet_count,
- int maxpacketsize,
- unsigned int num_trbs_left)
+static u32 xhci_td_remainder(struct xhci_ctrl *ctrl, int transferred,
+int trb_buff_len, unsigned int td_total_len,
+int maxp, bool more_trbs_coming)
{
- int packets_transferred;
+ u32 total_packet_count;
+
+ if (ctrl->hci_version < 0x100)
+ return ((td_total_len - transferred) >> 10);
/* One TRB with a zero-length data packet. */
- if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
+ if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
+ trb_buff_len == td_total_len)
return 0;
- /*
-* All the TRB queueing functions don't count the current TRB in
-* running_total.
-*/
- packets_transferred = (running_total + trb_buff_len) / maxpacketsize;
+ total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
- if ((total_packet_count - packets_transferred) > 31)
- return 31 << 17;
- return (total_packet_count - packets_transferred) << 17;
+ /* Queueing functions don't count the current TRB into transferred */
+ return (total_packet_count - ((transferred + trb_buff_len) / maxp));
}
/**
@@ -572,7 +569,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
pipe,
union xhci_trb *event;
int running_total, trb_buff_len;
- unsigned int total_packet_count;
+ bool more_trbs_coming = true;
int maxpacketsize;
[PATCH v2 07/11] usb: xhci: convert to TRB_LEN()
Use TRB_LEN(x) instead of ((x) & TRB_LEN_MASK)
Signed-off-by: Chunfeng Yun
---
v2: no changes
---
drivers/usb/host/xhci-ring.c | 8
include/usb/xhci.h | 1 -
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 16d2e02..99c84f9 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -688,7 +688,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
pipe,
length, maxpacketsize,
more_trbs_coming);
- length_field = ((trb_buff_len & TRB_LEN_MASK) |
+ length_field = (TRB_LEN(trb_buff_len) |
TRB_TD_SIZE(remainder) |
TRB_INTR_TARGET(0));
@@ -848,7 +848,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long
pipe,
trb_fields[1] = le16_to_cpu(req->index) |
le16_to_cpu(req->length) << 16;
/* TRB_LEN | (TRB_INTR_TARGET) */
- trb_fields[2] = (8 | TRB_INTR_TARGET(0));
+ trb_fields[2] = (TRB_LEN(8) | TRB_INTR_TARGET(0));
/* Immediate data in pointer */
trb_fields[3] = field;
queue_trb(ctrl, ep_ring, true, trb_fields);
@@ -864,11 +864,11 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long
pipe,
remainder = xhci_td_remainder(ctrl, 0, length, length,
usb_maxpacket(udev, pipe), 1);
- length_field = (length & TRB_LEN_MASK) | TRB_TD_SIZE(remainder) |
+ length_field = TRB_LEN(length) | TRB_TD_SIZE(remainder) |
TRB_INTR_TARGET(0);
debug("length_field = %d, length = %d,"
"xhci_td_remainder(length) = %d , TRB_INTR_TARGET(0) = %d\n",
- length_field, (length & TRB_LEN_MASK),
+ length_field, TRB_LEN(length),
TRB_TD_SIZE(remainder), 0);
if (length > 0) {
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index ca3d99b..35c6604 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -847,7 +847,6 @@ struct xhci_event_cmd {
/* Normal TRB fields */
/* transfer_len bitmasks - bits 0:16 */
#defineTRB_LEN(p) ((p) & 0x1)
-#defineTRB_LEN_MASK(0x1)
/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
/* Interrupter Target - which MSI-X vector to target the completion event at */
--
1.9.1
[PATCH v2 05/11] usb: xhci: convert to TRB_TYPE()
Use TRB_TYPE(p) instead of ((p) << TRB_TYPE_SHIFT)
Signed-off-by: Chunfeng Yun
---
v2: no changes
---
drivers/usb/host/xhci-mem.c | 3 +--
drivers/usb/host/xhci-ring.c | 11 +--
include/usb/xhci.h | 1 -
3 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 1da0524..d627aa5 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -236,8 +236,7 @@ static void xhci_link_segments(struct xhci_segment *prev,
*/
val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
val &= ~TRB_TYPE_BITMASK;
- val |= (TRB_LINK << TRB_TYPE_SHIFT);
-
+ val |= TRB_TYPE(TRB_LINK);
prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
}
}
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index cf8b9d2..87891fd 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -696,7 +696,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
pipe,
trb_fields[0] = lower_32_bits(addr);
trb_fields[1] = upper_32_bits(addr);
trb_fields[2] = length_field;
- trb_fields[3] = field | (TRB_NORMAL << TRB_TYPE_SHIFT);
+ trb_fields[3] = field | TRB_TYPE(TRB_NORMAL);
queue_trb(ctrl, ring, (num_trbs > 1), trb_fields);
@@ -823,7 +823,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long
pipe,
/* Queue setup TRB - see section 6.4.1.2.1 */
/* FIXME better way to translate setup_packet into two u32 fields? */
field = 0;
- field |= TRB_IDT | (TRB_SETUP << TRB_TYPE_SHIFT);
+ field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
if (start_cycle == 0)
field |= 0x1;
@@ -860,9 +860,9 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long
pipe,
/* If there's data, queue data TRBs */
/* Only set interrupt on short packet for IN endpoints */
if (usb_pipein(pipe))
- field = TRB_ISP | (TRB_DATA << TRB_TYPE_SHIFT);
+ field = TRB_ISP | TRB_TYPE(TRB_DATA);
else
- field = (TRB_DATA << TRB_TYPE_SHIFT);
+ field = TRB_TYPE(TRB_DATA);
remainder = xhci_td_remainder(ctrl, 0, length, length,
usb_maxpacket(udev, pipe), 1);
@@ -904,8 +904,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long
pipe,
trb_fields[2] = ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT);
/* Event on completion */
trb_fields[3] = field | TRB_IOC |
- (TRB_STATUS << TRB_TYPE_SHIFT) |
- ep_ring->cycle_state;
+ TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state;
queue_trb(ctrl, ep_ring, false, trb_fields);
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index cf4c020..bdba51d 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -903,7 +903,6 @@ union xhci_trb {
/* TRB bit mask */
#defineTRB_TYPE_BITMASK(0xfc00)
#define TRB_TYPE(p)((p) << 10)
-#define TRB_TYPE_SHIFT (10)
#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
/* TRB type IDs */
--
1.9.1
[PATCH v2 03/11] usb: xhci: add quirks flag to support MediaTek xHCI 0.96
There some vendor quirks for MTK xHCI 0.96 host controller:
1. It defines some extra SW scheduling parameters for HW
to minimize the scheduling effort for synchronous and
interrupt endpoints. The parameters are put into reseved
DWs of slot context and endpoint context.
2. Its TDS in Normal TRB defines a number of packets that
remains to be transferred for a TD after processing all
Max packets in all previous TRBs.
Signed-off-by: Chunfeng Yun
Tested-by: Frank Wunderlich
---
v2: add Tested-by Frank
---
drivers/usb/host/xhci-mtk.c | 1 +
drivers/usb/host/xhci-ring.c | 9 +++--
drivers/usb/host/xhci.c | 2 +-
include/usb/xhci.h | 2 ++
4 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 8ff7185..f3f181d 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -258,6 +258,7 @@ static int xhci_mtk_probe(struct udevice *dev)
if (ret)
goto ssusb_init_err;
+ mtk->ctrl.quirks = XHCI_MTK_HOST;
hcor = (struct xhci_hcor *)((uintptr_t)mtk->hcd +
HC_LENGTH(xhci_readl(&mtk->hcd->cr_capbase)));
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 0f86b01..cf8b9d2 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -332,7 +332,8 @@ static u32 xhci_td_remainder(struct xhci_ctrl *ctrl, int
transferred,
{
u32 total_packet_count;
- if (ctrl->hci_version < 0x100)
+ /* MTK xHCI 0.96 contains some features from 1.0 */
+ if (ctrl->hci_version < 0x100 && !(ctrl->quirks & XHCI_MTK_HOST))
return ((td_total_len - transferred) >> 10);
/* One TRB with a zero-length data packet. */
@@ -340,6 +341,10 @@ static u32 xhci_td_remainder(struct xhci_ctrl *ctrl, int
transferred,
trb_buff_len == td_total_len)
return 0;
+ /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
+ if ((ctrl->quirks & XHCI_MTK_HOST) && (ctrl->hci_version < 0x100))
+ trb_buff_len = 0;
+
total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
/* Queueing functions don't count the current TRB into transferred */
@@ -823,7 +828,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long
pipe,
field |= 0x1;
/* xHCI 1.0 6.4.1.2.1: Transfer Type field */
- if (ctrl->hci_version >= 0x100) {
+ if (ctrl->hci_version >= 0x100 || ctrl->quirks & XHCI_MTK_HOST) {
if (length > 0) {
if (req->requesttype & USB_DIR_IN)
field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT);
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 4be1411..51edeb2 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -650,7 +650,7 @@ static int xhci_set_configuration(struct usb_device *udev)
* are put into reserved DWs in Slot and Endpoint Contexts
* for synchronous endpoints.
*/
- if (IS_ENABLED(CONFIG_USB_XHCI_MTK)) {
+ if (ctrl->quirks & XHCI_MTK_HOST) {
ep_ctx[ep_index]->reserved[0] =
cpu_to_le32(EP_BPKTS(1) | EP_BBM(1));
}
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 15926eb..3de46cd 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -1230,6 +1230,8 @@ struct xhci_ctrl {
struct xhci_virt_device *devs[MAX_HC_SLOTS];
int rootdev;
u16 hci_version;
+ u32 quirks;
+#define XHCI_MTK_HOST BIT(0)
};
unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb);
--
1.9.1
[PATCH v2 01/11] usb: xhci: add a member hci_version in xhci_ctrl struct
Add a member to save xHCI version, it's used some times.
Signed-off-by: Chunfeng Yun
---
v2: no changes
---
drivers/usb/host/xhci-ring.c | 4 ++--
drivers/usb/host/xhci.c | 1 +
include/usb/xhci.h | 1 +
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 092ed6e..79bfc34 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -682,7 +682,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
pipe,
field |= TRB_ISP;
/* Set the TRB length, TD size, and interrupter fields. */
- if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) < 0x100)
+ if (ctrl->hci_version < 0x100)
remainder = xhci_td_remainder(length - running_total);
else
remainder = xhci_v1_0_td_remainder(running_total,
@@ -830,7 +830,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long
pipe,
field |= 0x1;
/* xHCI 1.0 6.4.1.2.1: Transfer Type field */
- if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) >= 0x100) {
+ if (ctrl->hci_version >= 0x100) {
if (length > 0) {
if (req->requesttype & USB_DIR_IN)
field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT);
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 126dabc..4be1411 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -1283,6 +1283,7 @@ static int xhci_lowlevel_init(struct xhci_ctrl *ctrl)
reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
+ ctrl->hci_version = reg;
return 0;
}
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 7d34103..a3e5914 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -1227,6 +1227,7 @@ struct xhci_ctrl {
struct xhci_scratchpad *scratchpad;
struct xhci_virt_device *devs[MAX_HC_SLOTS];
int rootdev;
+ u16 hci_version;
};
unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb);
--
1.9.1
[PATCH v2 10/11] usb: xhci: use macros with parameter to fill ep_info2
Use macros with parameter to fill ep_info2, then some macros
for MASK and SHIFT can be removed
Signed-off-by: Chunfeng Yun
---
v2: no changes
---
drivers/usb/host/xhci-mem.c | 13 -
drivers/usb/host/xhci.c | 3 +--
include/usb/xhci.h | 5 -
3 files changed, 5 insertions(+), 16 deletions(-)
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 6292542..0b49614 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -830,20 +830,17 @@ void xhci_setup_addressable_virt_dev(struct xhci_ctrl
*ctrl,
switch (speed) {
case USB_SPEED_SUPER:
- ep0_ctx->ep_info2 |= cpu_to_le32(((512 & MAX_PACKET_MASK) <<
- MAX_PACKET_SHIFT));
+ ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
debug("Setting Packet size = 512bytes\n");
break;
case USB_SPEED_HIGH:
/* USB core guesses at a 64-byte max packet first for FS devices */
case USB_SPEED_FULL:
- ep0_ctx->ep_info2 |= cpu_to_le32(((64 & MAX_PACKET_MASK) <<
- MAX_PACKET_SHIFT));
+ ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
debug("Setting Packet size = 64bytes\n");
break;
case USB_SPEED_LOW:
- ep0_ctx->ep_info2 |= cpu_to_le32(((8 & MAX_PACKET_MASK) <<
- MAX_PACKET_SHIFT));
+ ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
debug("Setting Packet size = 8bytes\n");
break;
default:
@@ -852,9 +849,7 @@ void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
}
/* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
- ep0_ctx->ep_info2 |=
- cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |
- ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT));
+ ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
trb_64 = virt_to_phys(virt_dev->eps[0].ring->first_seg->trbs);
ep0_ctx->deq = cpu_to_le64(trb_64 | virt_dev->eps[0].ring->cycle_state);
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 6244f25..fe30101 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -831,8 +831,7 @@ int xhci_check_maxpacket(struct usb_device *udev)
ctrl->devs[slot_id]->out_ctx, ep_index);
in_ctx = ctrl->devs[slot_id]->in_ctx;
ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
- ep_ctx->ep_info2 &= cpu_to_le32(~((0x & MAX_PACKET_MASK)
- << MAX_PACKET_SHIFT));
+ ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET(MAX_PACKET_MASK));
ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
/*
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index c534297..e1d3823 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -632,8 +632,6 @@ struct xhci_ep_ctx {
*/
#defineFORCE_EVENT (0x1)
#define ERROR_COUNT(p) (((p) & 0x3) << 1)
-#define ERROR_COUNT_SHIFT (1)
-#define ERROR_COUNT_MASK (0x3)
#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
#define EP_TYPE(p) ((p) << 3)
#define ISOC_OUT_EP1
@@ -646,13 +644,10 @@ struct xhci_ep_ctx {
/* bit 6 reserved */
/* bit 7 is Host Initiate Disable - for disabling stream selection */
#define MAX_BURST(p) (((p)&0xff) << 8)
-#define MAX_BURST_MASK (0xff)
-#define MAX_BURST_SHIFT(8)
#define CTX_TO_MAX_BURST(p)(((p) >> 8) & 0xff)
#define MAX_PACKET(p) (((p)&0x) << 16)
#define MAX_PACKET_MASK(0x)
#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0x)
-#define MAX_PACKET_SHIFT (16)
/* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
* USB2.0 spec 9.6.6.
--
1.9.1
[PATCH v2 08/11] usb: xhci: convert to TRB_TX_TYPE()
Use TRB_TX_TYPE() instead of (TRB_DATA_OUT/IN << TRB_TX_TYPE_SHIFT)
Signed-off-by: Chunfeng Yun
---
v2: no changes
---
drivers/usb/host/xhci-ring.c | 4 ++--
include/usb/xhci.h | 1 -
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 99c84f9..ccf2a35 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -830,9 +830,9 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long
pipe,
if (ctrl->hci_version >= 0x100 || ctrl->quirks & XHCI_MTK_HOST) {
if (length > 0) {
if (req->requesttype & USB_DIR_IN)
- field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT);
+ field |= TRB_TX_TYPE(TRB_DATA_IN);
else
- field |= (TRB_DATA_OUT << TRB_TX_TYPE_SHIFT);
+ field |= TRB_TX_TYPE(TRB_DATA_OUT);
}
}
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 35c6604..07b1aeb 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -879,7 +879,6 @@ struct xhci_event_cmd {
/* Control transfer TRB specific fields */
#define TRB_DIR_IN (1<<16)
#defineTRB_TX_TYPE(p) ((p) << 16)
-#defineTRB_TX_TYPE_SHIFT (16)
#defineTRB_DATA_OUT2
#defineTRB_DATA_IN 3
--
1.9.1
[PATCH v2 11/11] usb: xhci: convert to readx_poll_sleep_timeout()
Use readx_poll_sleep_timeout() to poll the register status
Change-Id: If05a68baf52c54ab30029279e349be6076f1d0ca
Signed-off-by: Chunfeng Yun
---
v2: fix typo of title suggested by Frank
---
drivers/usb/host/xhci.c | 25 +++--
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index fe30101..3547a9b 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
@@ -143,23 +144,19 @@ struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
* @param usec time to wait till
* @return 0 if handshake is success else < 0 on failure
*/
-static int handshake(uint32_t volatile *ptr, uint32_t mask,
- uint32_t done, int usec)
+static int
+handshake(uint32_t volatile *ptr, uint32_t mask, uint32_t done, int usec)
{
uint32_t result;
+ int ret;
+
+ ret = readx_poll_sleep_timeout(xhci_readl, ptr, result,
+(result & mask) == done || result == U32_MAX,
+1, usec);
+ if (result == U32_MAX) /* card removed */
+ return -ENODEV;
- do {
- result = xhci_readl(ptr);
- if (result == ~(uint32_t)0)
- return -ENODEV;
- result &= mask;
- if (result == done)
- return 0;
- usec--;
- udelay(1);
- } while (usec > 0);
-
- return -ETIMEDOUT;
+ return ret;
}
/**
--
1.9.1
[PATCH v2 06/11] usb: xhci: convert to TRB_INTR_TARGET()
Use TRB_INTR_TARGET(x) instead of
(((x) & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT)
Signed-off-by: Chunfeng Yun
---
v2: no changes
---
drivers/usb/host/xhci-ring.c | 10 --
include/usb/xhci.h | 2 --
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 87891fd..16d2e02 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -690,8 +690,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
pipe,
length_field = ((trb_buff_len & TRB_LEN_MASK) |
TRB_TD_SIZE(remainder) |
- ((0 & TRB_INTR_TARGET_MASK) <<
- TRB_INTR_TARGET_SHIFT));
+ TRB_INTR_TARGET(0));
trb_fields[0] = lower_32_bits(addr);
trb_fields[1] = upper_32_bits(addr);
@@ -849,8 +848,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long
pipe,
trb_fields[1] = le16_to_cpu(req->index) |
le16_to_cpu(req->length) << 16;
/* TRB_LEN | (TRB_INTR_TARGET) */
- trb_fields[2] = (8 | ((0 & TRB_INTR_TARGET_MASK) <<
- TRB_INTR_TARGET_SHIFT));
+ trb_fields[2] = (8 | TRB_INTR_TARGET(0));
/* Immediate data in pointer */
trb_fields[3] = field;
queue_trb(ctrl, ep_ring, true, trb_fields);
@@ -867,7 +865,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long
pipe,
remainder = xhci_td_remainder(ctrl, 0, length, length,
usb_maxpacket(udev, pipe), 1);
length_field = (length & TRB_LEN_MASK) | TRB_TD_SIZE(remainder) |
- ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT);
+ TRB_INTR_TARGET(0);
debug("length_field = %d, length = %d,"
"xhci_td_remainder(length) = %d , TRB_INTR_TARGET(0) = %d\n",
length_field, (length & TRB_LEN_MASK),
@@ -901,7 +899,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long
pipe,
trb_fields[0] = 0;
trb_fields[1] = 0;
- trb_fields[2] = ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT);
+ trb_fields[2] = TRB_INTR_TARGET(0);
/* Event on completion */
trb_fields[3] = field | TRB_IOC |
TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state;
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index bdba51d..ca3d99b 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -851,8 +851,6 @@ struct xhci_event_cmd {
/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
/* Interrupter Target - which MSI-X vector to target the completion event at */
-#defineTRB_INTR_TARGET_SHIFT (22)
-#defineTRB_INTR_TARGET_MASK(0x3ff)
#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
#define TRB_TBC(p) (((p) & 0x3) << 7)
--
1.9.1
[PATCH v2 09/11] usb: xhci: convert to EP_TYPE()
Use EP_TYPE(type) macro instead of ((type) << EP_TYPE_SHIFT)
Signed-off-by: Chunfeng Yun
---
v2: no changes
---
drivers/usb/host/xhci-mem.c | 2 +-
drivers/usb/host/xhci.c | 3 +--
include/usb/xhci.h | 1 -
3 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index d627aa5..6292542 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -825,7 +825,7 @@ void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
/* Step 4 - ring already allocated */
/* Step 5 */
- ep0_ctx->ep_info2 = cpu_to_le32(CTRL_EP << EP_TYPE_SHIFT);
+ ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
debug("SPEED = %d\n", speed);
switch (speed) {
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 5f3a0fb..6244f25 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -618,8 +618,7 @@ static int xhci_set_configuration(struct usb_device *udev)
cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
EP_INTERVAL(interval) | EP_MULT(mult));
- ep_ctx[ep_index]->ep_info2 =
- cpu_to_le32(ep_type << EP_TYPE_SHIFT);
+ ep_ctx[ep_index]->ep_info2 = cpu_to_le32(EP_TYPE(ep_type));
ep_ctx[ep_index]->ep_info2 |=
cpu_to_le32(MAX_PACKET
(get_unaligned(&endpt_desc->wMaxPacketSize)));
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 07b1aeb..c534297 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -636,7 +636,6 @@ struct xhci_ep_ctx {
#define ERROR_COUNT_MASK (0x3)
#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
#define EP_TYPE(p) ((p) << 3)
-#define EP_TYPE_SHIFT (3)
#define ISOC_OUT_EP1
#define BULK_OUT_EP2
#define INT_OUT_EP 3
--
1.9.1
[PATCH v6 02/10] image: Use gd->ram_base/_size in env_get_bootm_size()
Use only gd->ram_base/_size in env_get_bootm_size() instead of bi_dram[]
in some cases and bi_memstart in others.
Signed-off-by: Stefan Roese
---
(no changes since v4)
Changes in v4:
- New patch
common/image.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/common/image.c b/common/image.c
index 2ed46f7685..6f68b13fce 100644
--- a/common/image.c
+++ b/common/image.c
@@ -685,13 +685,8 @@ phys_size_t env_get_bootm_size(void)
return tmp;
}
-#if defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)
- start = gd->bd->bi_dram[0].start;
- size = gd->bd->bi_dram[0].size;
-#else
- start = gd->bd->bi_memstart;
- size = gd->bd->bi_memsize;
-#endif
+ start = gd->ram_base;
+ size = gd->ram_size;
s = env_get("bootm_low");
if (s)
--
2.28.0
[PATCH v6 06/10] xtensa: Remove local no-op dram_init_banksize()
When this no-op dram_init_banksize() is removed, the weak default will
be used instead, which correctly sets the bi_dram[] banksize values.
Signed-off-by: Stefan Roese
---
(no changes since v5)
Changes in v5:
- New patch to fix the failing "test.py xtfpga" CI test
board/cadence/xtfpga/xtfpga.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c
index 4b49b6e5c8..5811c43142 100644
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c
@@ -49,11 +49,6 @@ int checkboard(void)
return 0;
}
-int dram_init_banksize(void)
-{
- return 0;
-}
-
int board_postclk_init(void)
{
/*
--
2.28.0
[PATCH v6 04/10] global: Move from bi_memstart/memsize -> gd->ram_base/ram_size
With the removal of bi_memstart & bi_memsize, this patch now moves the
references to the better suiting gd->ram_base/ram_size variables.
Signed-off-by: Stefan Roese
---
(no changes since v5)
Changes in v5:
- Use PHYSADDR() for xtensa, as the bi_memstart value was originally
defined this way
Changes in v4:
- New patch
api/api_platform-mips.c | 3 +--
api/api_platform-powerpc.c | 2 +-
arch/mips/lib/boot.c | 2 +-
arch/mips/lib/bootm.c| 2 +-
arch/powerpc/cpu/mpc83xx/fdt.c | 2 +-
arch/powerpc/cpu/mpc83xx/traps.c | 2 +-
arch/powerpc/cpu/mpc85xx/fdt.c | 4 ++--
arch/powerpc/cpu/mpc85xx/traps.c | 2 +-
arch/powerpc/cpu/mpc86xx/fdt.c | 4 +++-
arch/powerpc/cpu/mpc86xx/traps.c | 2 +-
arch/powerpc/cpu/mpc8xx/fdt.c| 2 +-
arch/powerpc/lib/bootm.c | 4 ++--
arch/xtensa/lib/bootm.c | 5 ++---
cmd/bedbug.c | 2 +-
14 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/api/api_platform-mips.c b/api/api_platform-mips.c
index 51cd328b3d..e1509663af 100644
--- a/api/api_platform-mips.c
+++ b/api/api_platform-mips.c
@@ -24,8 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
int platform_sys_info(struct sys_info *si)
{
- platform_set_mr(si, gd->bd->bi_memstart,
- gd->bd->bi_memsize, MR_ATTR_DRAM);
+ platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
return 1;
}
diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c
index 15930cfdb6..847a4a3015 100644
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -42,7 +42,7 @@ int platform_sys_info(struct sys_info *si)
si->bar = 0;
#endif
- platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize,
MR_ATTR_DRAM);
+ platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize,
MR_ATTR_FLASH);
platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize,
MR_ATTR_SRAM);
diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c
index db862f6379..6ef9109022 100644
--- a/arch/mips/lib/boot.c
+++ b/arch/mips/lib/boot.c
@@ -17,7 +17,7 @@ unsigned long do_go_exec(ulong (*entry)(int, char * const []),
* whole SDRAM area, since we don't know the size of the image
* that was loaded.
*/
- flush_cache(gd->bd->bi_memstart, gd->ram_top - gd->bd->bi_memstart);
+ flush_cache(gd->ram_base, gd->ram_top - gd->ram_base);
return entry(argc, argv);
}
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 0a13f6edb7..d5c99d891c 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -242,7 +242,7 @@ static int boot_reloc_fdt(bootm_headers_t *images)
#if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
int arch_fixup_fdt(void *blob)
{
- u64 mem_start = virt_to_phys((void *)gd->bd->bi_memstart);
+ u64 mem_start = virt_to_phys((void *)gd->ram_base);
u64 mem_size = gd->ram_size;
return fdt_fixup_memory_banks(blob, &mem_start, &mem_size, 1);
diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c
index ebdedb2888..4ea7b27ef4 100644
--- a/arch/powerpc/cpu/mpc83xx/fdt.c
+++ b/arch/powerpc/cpu/mpc83xx/fdt.c
@@ -121,7 +121,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
"clock-frequency", get_serial_clock(), 1);
#endif
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+ fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c
index c3cc119d65..ea8bc6c152 100644
--- a/arch/powerpc/cpu/mpc83xx/traps.c
+++ b/arch/powerpc/cpu/mpc83xx/traps.c
@@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);
-#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
+#define END_OF_MEM (gd->ram_base + gd->ram_size)
/*
* Trap & Exception support
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 9569c1a64b..0d8353ceb2 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -672,10 +672,10 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
"clock-frequency", get_bus_freq(0), 1);
#endif
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+ fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#ifdef CONFIG_MP
- ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
+ ft_fixup_cpu(blob, (u64)gd->ram_base + (u64)gd->ram_size);
ft_fixup_num_cores(blob);
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c
index f37a45e269..db6ed1fc92 100644
--- a/arch/po
[PATCH v6 03/10] board_f: Add default values for bi_dram[] in dram_init_banksize()
Remove the bi_memstart / bi_memsize assignment in setup_bdinfo() and
make sure, that bd_dram[] is always configured in the weak default
implementation of dram_init_banksize(), when CONFIG_SYS_SDRAM_BASE is
not set.
Signed-off-by: Stefan Roese
---
Changes in v6:
- Simplify dram_init_banksize() even more as suggested by Daniel
Changes in v4:
- New patch
common/board_f.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/common/board_f.c b/common/board_f.c
index d1f0f9af08..8a43df97e4 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -237,10 +237,8 @@ static int show_dram_config(void)
__weak int dram_init_banksize(void)
{
-#if defined(CONFIG_SYS_SDRAM_BASE)
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = gd->ram_base;
gd->bd->bi_dram[0].size = get_effective_memsize();
-#endif
return 0;
}
@@ -602,9 +600,6 @@ int setup_bdinfo(void)
{
struct bd_info *bd = gd->bd;
- bd->bi_memstart = gd->ram_base; /* start of memory */
- bd->bi_memsize = gd->ram_size; /* size in bytes */
-
if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
--
2.28.0
[PATCH v6 07/10] video: cfb_console.c: Use bi_dram[] values on all platforms
All platforms support bi_dram[] since quite some time. Lets remove the
and bi_memsize values completely.
Signed-off-by: Stefan Roese
---
(no changes since v4)
Changes in v4:
- New patch
drivers/video/cfb_console.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index badade353e..3f07f4eb29 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -1983,8 +1983,6 @@ static void *video_logo(void)
static int cfb_fb_is_in_dram(void)
{
struct bd_info *bd = gd->bd;
-#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || \
-defined(CONFIG_SANDBOX) || defined(CONFIG_X86)
ulong start, end;
int i;
@@ -1995,11 +1993,7 @@ defined(CONFIG_SANDBOX) || defined(CONFIG_X86)
(ulong)video_fb_address < end)
return 1;
}
-#else
- if ((ulong)video_fb_address >= bd->bi_memstart &&
- (ulong)video_fb_address < bd->bi_memstart + bd->bi_memsize)
- return 1;
-#endif
+
return 0;
}
--
2.28.0
[PATCH v6 09/10] cmd: bdinfo: Remove print of superseeded bi_memstart / bi_memsize values
Remove printing of the superseeded (by bi_dram[]) memory values from the
bdinfo command.
Signed-off-by: Stefan Roese
---
(no changes since v4)
Changes in v4:
- New patch
cmd/bdinfo.c | 8
1 file changed, 8 deletions(-)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 9e230f23cb..0229846d3e 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -34,12 +34,6 @@ static void print_eth(int idx)
printf("%-12s= %s\n", name, val);
}
-static void print_phys_addr(const char *name, phys_addr_t value)
-{
- printf("%-12s= 0x%.*llx\n", name, 2 * (int)sizeof(ulong),
- (unsigned long long)value);
-}
-
void bdinfo_print_mhz(const char *name, unsigned long hz)
{
char buf[32];
@@ -73,8 +67,6 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char
*const argv[])
#endif
bdinfo_print_num("boot_params", (ulong)bd->bi_boot_params);
print_bi_dram(bd);
- bdinfo_print_num("memstart", (ulong)bd->bi_memstart);
- print_phys_addr("memsize", bd->bi_memsize);
if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
bdinfo_print_num("sramstart", (ulong)bd->bi_sramstart);
bdinfo_print_num("sramsize", (ulong)bd->bi_sramsize);
--
2.28.0
[PATCH v6 01/10] CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always defined
Since commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") &
commit 999a772d9f24 ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"),
CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default).
It makes no sense to still carry code that is guarded with
"#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes
all these unreferenced code paths.
Signed-off-by: Stefan Roese
Reviewed-by: Pali Rohár
Reviewed-by: Andy Shevchenko
---
(no changes since v5)
Changes in v5:
- Add Reviewed-by tag from Pali & Andy
- Move "bd" assignment as suggested by Andy
Changes in v4:
- Only remove dead code with CONFIG_NR_DRAM_BANKS always defined
arch/x86/cpu/broadwell/cpu_from_spl.c | 2 --
board/xilinx/zynqmp/zynqmp.c | 2 --
cmd/bdinfo.c | 2 --
common/board_f.c | 7 +-
common/image.c| 3 +--
common/init/handoff.c | 33 +++
drivers/pci/pci-uclass.c | 18 ++-
include/asm-generic/u-boot.h | 2 --
include/handoff.h | 2 --
lib/fdtdec.c | 5
lib/lmb.c | 9 ++--
11 files changed, 19 insertions(+), 66 deletions(-)
diff --git a/arch/x86/cpu/broadwell/cpu_from_spl.c
b/arch/x86/cpu/broadwell/cpu_from_spl.c
index 6567d50653..4d4cdafa2b 100644
--- a/arch/x86/cpu/broadwell/cpu_from_spl.c
+++ b/arch/x86/cpu/broadwell/cpu_from_spl.c
@@ -53,14 +53,12 @@ void board_debug_uart_init(void)
int dram_init_banksize(void)
{
-#ifdef CONFIG_NR_DRAM_BANKS
struct spl_handoff *ho;
ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho));
if (!ho)
return log_msg_ret("Missing SPL hand-off info", -ENOENT);
handoff_load_dram_banks(ho);
-#endif
return 0;
}
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index ebb7172908..4cc5cb6fd7 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -467,10 +467,8 @@ int dram_init(void)
#else
int dram_init_banksize(void)
{
-#if defined(CONFIG_NR_DRAM_BANKS)
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
-#endif
mem_map_fill();
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 9593b345a3..9e230f23cb 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -49,7 +49,6 @@ void bdinfo_print_mhz(const char *name, unsigned long hz)
static void print_bi_dram(const struct bd_info *bd)
{
-#ifdef CONFIG_NR_DRAM_BANKS
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
@@ -59,7 +58,6 @@ static void print_bi_dram(const struct bd_info *bd)
bdinfo_print_num("-> size", bd->bi_dram[i].size);
}
}
-#endif
}
__weak void arch_print_bdinfo(void)
diff --git a/common/board_f.c b/common/board_f.c
index 3932e0c69d..d1f0f9af08 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -215,8 +215,6 @@ static int announce_dram_init(void)
static int show_dram_config(void)
{
unsigned long long size;
-
-#ifdef CONFIG_NR_DRAM_BANKS
int i;
debug("\nRAM Configuration:\n");
@@ -229,9 +227,6 @@ static int show_dram_config(void)
#endif
}
debug("\nDRAM: ");
-#else
- size = gd->ram_size;
-#endif
print_size(size, "");
board_add_ram_info(0);
@@ -242,7 +237,7 @@ static int show_dram_config(void)
__weak int dram_init_banksize(void)
{
-#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
+#if defined(CONFIG_SYS_SDRAM_BASE)
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
#endif
diff --git a/common/image.c b/common/image.c
index 9d7d5c17d1..2ed46f7685 100644
--- a/common/image.c
+++ b/common/image.c
@@ -685,8 +685,7 @@ phys_size_t env_get_bootm_size(void)
return tmp;
}
-#if (defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)) && \
- defined(CONFIG_NR_DRAM_BANKS)
+#if defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)
start = gd->bd->bi_dram[0].start;
size = gd->bd->bi_dram[0].size;
#else
diff --git a/common/init/handoff.c b/common/init/handoff.c
index e00b43e6a7..62071bd017 100644
--- a/common/init/handoff.c
+++ b/common/init/handoff.c
@@ -12,18 +12,15 @@ DECLARE_GLOBAL_DATA_PTR;
void handoff_save_dram(struct spl_handoff *ho)
{
+ struct bd_info *bd = gd->bd;
+ int i;
+
ho->ram_size = gd->ram_size;
-#ifdef CONFIG_NR_DRAM_BANKS
- {
- struct bd_info *bd = gd->bd;
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- ho->ram_bank[i].start = bd->bi_dram[i].start;
- ho->ram_bank[i].size = bd->bi_dram[i].size;
- }
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ ho->ram_bank[i].start = bd->bi_d
[PATCH v6 05/10] xtensa: Remove arch_setup_bdinfo()
arch_setup_bdinfo() only configures the deprecated bi_memstart &
bi_memsize values, which should not be needed any more. Lets remove
this file completely.
Signed-off-by: Stefan Roese
---
(no changes since v4)
Changes in v4:
- New patch
arch/xtensa/lib/Makefile | 2 +-
arch/xtensa/lib/bdinfo.c | 22 --
2 files changed, 1 insertion(+), 23 deletions(-)
delete mode 100644 arch/xtensa/lib/bdinfo.c
diff --git a/arch/xtensa/lib/Makefile b/arch/xtensa/lib/Makefile
index ceee59b9bd..c59df7d372 100644
--- a/arch/xtensa/lib/Makefile
+++ b/arch/xtensa/lib/Makefile
@@ -5,4 +5,4 @@
obj-$(CONFIG_CMD_BOOTM) += bootm.o
-obj-y += cache.o misc.o relocate.o time.o bdinfo.o
+obj-y += cache.o misc.o relocate.o time.o
diff --git a/arch/xtensa/lib/bdinfo.c b/arch/xtensa/lib/bdinfo.c
deleted file mode 100644
index 4ec8529521..00
--- a/arch/xtensa/lib/bdinfo.c
+++ /dev/null
@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * XTENSA-specific information for the 'bd' command
- *
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- */
-
-#include
-#include
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int arch_setup_bdinfo(void)
-{
- struct bd_info *bd = gd->bd;
-
- bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
- bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-
- return 0;
-}
--
2.28.0
[PATCH v6 08/10] powerpc: Remove bi_memstart & bi_memsize assignments in spl.c
Most likely these deprecated (removed) variables are not needed. Lets remove the assignments completely from all spl.c files. Signed-off-by: Stefan Roese Tested-by: Oleksandr Zhadan and Michael Durrant --- (no changes since v5) Changes in v5: - Add Tested-by tag from Oleksandr & Michael Changes in v4: - New patch board/Arcturus/ucp1020/spl.c | 2 -- board/freescale/p1010rdb/spl.c | 2 -- board/freescale/p1_p2_rdb_pc/spl.c | 2 -- board/freescale/t102xrdb/spl.c | 2 -- board/freescale/t104xrdb/spl.c | 2 -- board/freescale/t208xqds/spl.c | 2 -- board/freescale/t208xrdb/spl.c | 2 -- board/freescale/t4rdb/spl.c| 2 -- 8 files changed, 16 deletions(-) diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c index 5416a5b663..0fd9532d74 100644 --- a/board/Arcturus/ucp1020/spl.c +++ b/board/Arcturus/ucp1020/spl.c @@ -83,8 +83,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; - bd->bi_memsize = CONFIG_SYS_L2_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index 4ee4573d2b..fbaa6a6514 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -69,8 +69,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; - bd->bi_memsize = CONFIG_SYS_L2_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index e76c3e82c3..8aceceb56a 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -75,8 +75,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; - bd->bi_memsize = CONFIG_SYS_L2_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index da442fcc18..09dd88ac4e 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -103,8 +103,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(gd + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index f83d69ba15..e7922954de 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -94,8 +94,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(gd + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c index c197884421..d8c2bbe28d 100644 --- a/board/freescale/t208xqds/spl.c +++ b/board/freescale/t208xqds/spl.c @@ -102,8 +102,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(gd + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index 07aab6349c..c64bd87115 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -72,8 +72,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(gd + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c index 64d2753da8..9aa0a9b052 100644 --- a/board/freescale/t4rdb/spl.c +++ b/board/freescale/t4rdb/spl.c @@ -75,8 +75,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(gd + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; arch_cpu_init(); get_clocks(); -- 2.28.0
[PATCH v6 10/10] asm-generic/u-boot.h: Remove bi_memstart & bi_memsize from bd_info
bi_memstart & bi_memsize are now not referenced any more. This patch
removes their definitions from the bd_info struct.
Signed-off-by: Stefan Roese
---
(no changes since v4)
Changes in v4:
- New patch
include/asm-generic/u-boot.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 99d3fe33ad..637de0c455 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -27,8 +27,6 @@
#include
struct bd_info {
- unsigned long bi_memstart;/* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
--
2.28.0
Re: [PATCH v4 20/27] Makefile: Warn against using CONFIG_SPL_FIT_GENERATOR
Hi Simon, On 16. 08. 20 5:39, Simon Glass wrote: > Hi Michal, > > On Fri, 14 Aug 2020 at 07:28, Michal Simek wrote: >> >> Hi Simon, >> >> ne 19. 7. 2020 v 22:06 odesílatel Simon Glass napsal: >>> >>> This option is used to run arch-specific shell scripts which produce .its >>> files which are used to produce FIT images. We already have binman which >>> is designed to produce firmware images. It is more powerful and has tests. >>> >>> So this option should be deprecated and not used. Existing uses should be >>> migrated. >>> >>> Mentions of this in code reviews over the last year or so do not seem to >>> have resulted in action, and things are getting worse. >>> >>> So let's add a warning. >>> >>> Signed-off-by: Simon Glass >>> Reviewed-by: Bin Meng >>> --- >>> >>> (no changes since v1) >>> >>> Makefile | 9 + >>> 1 file changed, 9 insertions(+) >>> >>> diff --git a/Makefile b/Makefile >>> index f1b5be1882..d73c10a973 100644 >>> --- a/Makefile >>> +++ b/Makefile >>> @@ -1148,6 +1148,13 @@ ifneq ($(CONFIG_DM_ETH),y) >>> @echo >&2 "See doc/driver-model/migration.rst for more info." >>> @echo >&2 "" >>> endif >>> +endif >>> +ifneq ($(CONFIG_SPL_FIT_GENERATOR),) >>> + @echo >&2 "= WARNING ==" >>> + @echo >&2 "This board uses CONFIG_SPL_FIT_GENERATOR. Please migrate" >>> + @echo >&2 "to binman instead, to avoid the proliferation of" >>> + @echo >&2 "arch-specific scripts with no tests." >>> + @echo >&2 "" >>> endif >>> @# Check that this build does not use CONFIG options that we do not >>> @# know about unless they are in Kconfig. All the existing CONFIG >>> @@ -1345,6 +1352,8 @@ endif >>> >>> # Boards with more complex image requirements can provide an .its source >>> file >>> # or a generator script >>> +# NOTE: Please do not use this. We are migrating away from Makefile rules >>> to use >>> +# binman instead. >>> ifneq ($(CONFIG_SPL_FIT_SOURCE),"") >>> U_BOOT_ITS := u-boot.its >>> $(U_BOOT_ITS): $(subst ",,$(CONFIG_SPL_FIT_SOURCE)) >>> -- >>> 2.28.0.rc0.105.gf9edc3c819-goog >>> >> >> I just got to this conversion and I am curious how that transition >> should look like. >> I found how FIT image is created which is fine but I didn't find any >> reference on how to generate images based on CONFIG_OF_LIST. >> If you look at arch/arm/mach-zynqmp/mkimage_fit_atf.sh you will see >> that I loop over this entry and create multiple DT nodes and the same >> amount of configurations to cover it. Is this supported by binman? >> If yes, what's the syntax for it? > > The easiest way is probably to create a new entry type, like zynq-fit. > Then you can generate the DT using the sequence writer functions. See > _ReadSubNodes() in fit.py for an example. > > You can perhaps have a template subnode and use that in a for loop to > generate the nodes. > >> >> I tried several configurations and we can use that for generating qspi >> images and also images with different configurations to have them >> ready >> but first I need to be able to handle the case above. > > I was thinking of converting sunxi which has the same need, but it > sounds like you are on the case. Let me know if you need help. Nope. I just saw that message and started to play with it to find out what needs to be done and how this fits to bigger picture. If this doesn't work directly then the work needs to be planned which will take time especially when this utility is new for us and we could have issues with writing code in python. Would be good if you can do the first shot because you know this utility and I am more than happy to test it, try and adopt if needed for our case. Sunxi is very similar case as is zynqmp. Difference is they hardcode default configuration to config_1. ZynqMP is setting up default based on default DT configured at that time. In connection to binman I see that there would be a need to generate images with ATF and without ATF in configuration node and with different default configuration. There could be also a need to add additional loadable entry such as bitstreams. Back to zynq-fit new entry type. I don't think it should be zynq/zynqmp type because as was state in commit message u-boot.itb generation is very similar for all these boards that's why name for this new entry should be generic. Thanks, Michal
Re: [PATCH v1 08/10] dts: r64: add sata- and asm_sel nodes
On Sun, 2020-08-16 at 10:24 +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich
>
> asm_sel is for switching between sata and pcie mode
> on r64 there is GPIO90 connected to ASM1480 which
> switches RX/TX pairs to PCIe/SATA connector
> output-low means sata-controller is active
>
> with 2020-10 now reg is also needed for the phy itself
>
> Signed-off-by: Frank Wunderlich
> ---
> arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 9 +++
> arch/arm/dts/mt7622.dtsi | 32
> 2 files changed, 41 insertions(+)
>
> diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
> b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
> index 768f15bc2c..c36ec8f8d0 100644
> --- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
> +++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
> @@ -204,3 +204,12 @@
> full-duplex;
> };
> };
> +
> +&gpio {
> + /*gpio 90 for setting mode to sata*/
> + asm_sel {
> + gpio-hog;
> + gpios = <90 GPIO_ACTIVE_HIGH>;
> + output-low;
> + };
> +};
> diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
> index fec071643e..c43ad65702 100644
> --- a/arch/arm/dts/mt7622.dtsi
> +++ b/arch/arm/dts/mt7622.dtsi
> @@ -10,6 +10,7 @@
> #include
> #include
> #include
> +#include
>
> / {
> compatible = "mediatek,mt7622";
> @@ -270,6 +271,37 @@
> };
> };
>
> + sata: sata@1a20 {
> + compatible = "mediatek,mtk-ahci";
> + reg = <0x1a20 0x1100>;
> + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
> + <&pciesys MT7622_SATA_PHY_SW_RST>,
> + <&pciesys MT7622_SATA_PHY_REG_RST>;
> + reset-names = "axi", "sw", "reg";
> + mediatek,phy-mode = <&pciesys>;
> + ports-implemented = <0x1>;
> + phys = <&sata_port PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + status = "okay";
> + };
> +
> + sata_phy: sata-phy@1a243000 {
> + compatible = "mediatek,generic-tphy-v1";
> + reg = <0x1a243000 0x0100>;
Would you please change the tphy driver to make the shared reg optional
when version is v1 for sata, as Linux kernel does.
then we can remove "reg" property here.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "okay";
> +
> + sata_port: sata-phy@1a243000 {
> + reg = <0x1a243000 0x0100>;
> + clocks = <&topckgen CLK_TOP_ETH_500M>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> ethsys: syscon@1b00 {
> compatible = "mediatek,mt7622-ethsys", "syscon";
> reg = <0x1b00 0x1000>;
