Re: [PATCH v4 00/59] dm: Add programatic generation of ACPI tables (part D)
On Wed, Sep 23, 2020 at 2:46 AM Simon Glass wrote: > > Note: This is part D of this effort. With this, Coral includes all > required ACPI tables. > > At present on x86 U-Boot supports creating ACPI (Advanced Configuration > and Power Interface) tables using the Intel ACPI Source Language (ASL) > compiler. > > This is good enough for basic operation but some devices need to add > their information dynamically at runtime. An example is a device that > needs to report its enable GPIO. This is described in the device tree, > so we want to add code in the driver to convert that device-tree > description into an ACPI description for use on Linux. > > This series adds support for generation of ACPI tables and fragments by > devices. The core support is built into driver model. > > Several files are brought over from coreboot to do the actual generation. > > As an example of using this new feature, chromebook_coral is updated to > write out a wide array of ACPI tables including DSDT and SSDT. > > This initial version of the series lays out the general approach. More > work is needed to figure out the difference between CONFIG_ACPIGEN and > CONFIG_GENERATE_ACPI_TABLE with respect to what is built. > > Changes in v4: > - Add Andy's documentation to struct acpi_gpio > - Add logging when writinge NHLT > - Add new patch to use I2cSerialBusV2() instead of I2cSerialBus() > - Change table version to 3 > - Correct DPTF enable property > - Correct comment for dm_test_acpi_write_prw() > - Correct compatible string for gma device > Drop extra acpi_align() in apl_acpi_hb_write_tables() v4 has been applied to u-boot-x86/next, thanks!
Re: [PATCH] cfi_flash: Fix devicetree address determination
Hi Simon,
On 22.09.20 15:51, Simon Glass wrote:
Hi Stefan,
On Mon, 21 Sep 2020 at 07:28, Stefan Roese wrote:
Hi Andre,
(added Simon)
On 18.09.20 19:45, Andre Przywara wrote:
The cfi-flash driver uses an open-coded version of the generic
algorithm to decode and translate multiple frames of a "reg" property.
This starts off the wrong foot by using the address-cells and size-cells
properties of *this* very node, and not of the parent. This somewhat
happened to work back when we were using a wrong default size of 2,
but broke about a year ago with commit 0ba41ce1b781 ("libfdt: return
correct value if #size-cells property is not present").
Instead of fixing the reinvented wheel, just use the generic function
that does all of this properly.
This fixes U-Boot on QEMU (outside of EL1), which was crashing due to
decoding a wrong start address:
DRAM: 1 GiB
Flash: "Synchronous Abort" handler, esr 0x9644
elr: 000211dc lr : 000211b0 (reloc)
elr: 7ff5e1dc lr : 7ff5e1b0
x0 : 00f0 x1 : 7ff5e1d8
x2 : 7edfbc48 x3 :
x4 : x5 : 00f0
x6 : 7edfbc2c x7 :
x8 : 7ffd8d70 x9 : 000c
x10: 0403 x11: 0055
Signed-off-by: Andre Przywara
---
drivers/mtd/cfi_flash.c | 25 +++--
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index b7289ba5394..656ff326e17 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -2468,29 +2468,18 @@ unsigned long flash_init(void)
#ifdef CONFIG_CFI_FLASH /* for driver model */
static int cfi_flash_probe(struct udevice *dev)
{
- const fdt32_t *cell;
- int addrc, sizec;
- int len, idx;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int idx;
- addrc = dev_read_addr_cells(dev);
- sizec = dev_read_size_cells(dev);
-
- /* decode regs; there may be multiple reg tuples. */
- cell = dev_read_prop(dev, "reg", );
- if (!cell)
- return -ENOENT;
- idx = 0;
- len /= sizeof(fdt32_t);
- while (idx < len) {
- phys_addr_t addr;
-
- addr = dev_translate_address(dev, cell + idx);
+ for (idx = 0; idx < CFI_MAX_FLASH_BANKS; idx++) {
+ addr = devfdt_get_addr_size_index(dev, idx, );
+ if (addr == FDT_ADDR_T_NONE)
+ break;
flash_info[cfi_flash_num_flash_banks].dev = dev;
flash_info[cfi_flash_num_flash_banks].base = addr;
cfi_flash_num_flash_banks++;
-
- idx += addrc + sizec;
}
gd->bd->bi_flashstart = flash_info[0].base;
This fails on my Octeon MIPS64 platform "octeon_ebb7304". I did some
debugging and found that here "of_offset" is a 64 bit value (type long)
which gets truncated in dev_of_offset() to 32 bit (type int).
This problem only arises when of_live_active() is set. Here, "of_offset"
holds a pointer AFACT and truncating it to 32 bits breaks things.
I'm wondering why this did not hit me earlier on this 64bit platform.
Simon, do you have a quick idea how to solve this?
Well I don't think ofnode should use long for of_offset, since int
should be enough.
ofnode_to_offset() converts an ofnode to a DT offset but only if it is
not using livetree. With livetree there are no offsets so this is not
going to work. If you define OF_CHECKS you will see that.
This does not work right now. I'll send a patch fixing compiling with
OF_CHECK enabled shortly.
Note that an ofnode can either hold a pointer or an offset. There are
detailed comments on ofnode_union to explain how it is supposed to
work.
Right. Thanks for all the detailed infos in the header. The main issue
seems to be, that this CFI patch uses a function from fdtaddr.c
(devfdt_get_addr_size_index), which unconditionally uses dev_of_offset()
without checking if livetree is enabled or not. This breaks on my
64 bit platform (see below).
This patch looks correct to me, but perhaps there is something else going on?
Making this change below, works for me:
- addr = devfdt_get_addr_size_index(dev, idx, );
+ addr = dev_read_addr_index(dev, idx);
Maybe we should make sure, that all functions from fdtaddr.c are not
used with livetree active? To prevent similar issues using devfdt_foo()
functions with livetree active.
Thanks,
Stefan
Re: [PATCH v3 5/5] x86: video: Show information about each video device
On Wed, Sep 23, 2020 at 11:16 AM Simon Glass wrote: > > At present the 'bdinfo' command shows the framebuffer address, but not the > address of the copy framebuffer, if present. Add support for this. > > Signed-off-by: Simon Glass > Reviewed-by: Bin Meng > --- > > Changes in v3: > - Update header file to avoid build error with !DM_VIDEO > > cmd/bdinfo.c| 26 +- > include/video.h | 6 ++ > 2 files changed, 27 insertions(+), 5 deletions(-) > applied to u-boot-x86/next, thanks!
Re: [PATCH v2 0/5] x86: Updates to some commands
On Wed, Sep 23, 2020 at 4:54 AM Simon Glass wrote: > > This series adds a few more features to some x86-specific commands. > > Changes in v2: > - Fix '93' typo > - Capitalise 'System' > > Simon Glass (5): > x86: hob: Add way to show a single hob entry > x86: hob: Try to show a name instead of a GUID > x86: Allow showing details about a HOB entry > x86: Add support for more than 8 MTRRs > x86: video: Show information about each video device > > arch/x86/cpu/mtrr.c| 12 ++-- > arch/x86/include/asm/fsp/fsp_hob.h | 25 > arch/x86/include/asm/mtrr.h| 15 - > cmd/bdinfo.c | 26 +++- > cmd/x86/hob.c | 100 +++-- > cmd/x86/mtrr.c | 9 +-- > 6 files changed, 167 insertions(+), 20 deletions(-) > > -- applied to u-boot-x86/next, thanks!
Re: [PATCH v2 0/5] powerpc, mpc83xx: add DM_ETH support
Hi Rasmus,
Am 22.09.2020 um 16:34 schrieb Rasmus Villemoes:
Hi Heiko
I'm struggling somewhat with getting our mpc8309-derived board converted
to DM_ETH. I just get
Net: No ethernet found.
where I used to get
Net: UEC0, UEC1, UEC2
:-(
Ok, I currently have no access to the hardware, I wait for the customer
to give me access, will take until next week ... so I can only review
currently code changes...
BTW: I hope to get daily access, so I can add at least one board to
my daily U-Boot tbot tests, see:
http://xeidos.ddns.net/ubtestresults/home
and there's no errors or other diagnostics printed (I've also tried
adding #define DEBUG 1 to the .c files under drivers/net/qe/, still
nothing).
The board already used OF_CONTROL, so I've tried extending the
device-tree based partly on you changes for the km boards, partly from
our linux device tree - the two mostly agree:
@@ -25,6 +25,8 @@
i2c0 =
i2c1 =
spi0 =
+ ethernet0 =
+ ethernet2 =
};
chosen {
@@ -315,6 +317,95 @@
clocks = < MPC83XX_CLK_SDHC>;
clock-names = "per";
};
+
+ ipic: pic@700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x700 0x100>;
+ device_type = "ipic";
+ };
};
-};
+ qe: qe@e010 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe";
+ ranges = <0x0 0xe010 0x0010>;
+ reg = <0xe010 0x480>;
+ brg-frequency = <0>;
+ bus-frequency = <39600>;
+
+ muram@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x0001 0x4000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+"fsl,cpm-muram-data";
+ reg = <0x0 0x4000>;
+ };
+ };
+
+ qeic: interrupt-controller@80 {
+ interrupt-controller;
+ compatible = "fsl,qe-ic";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x80 0x80>;
+ big-endian;
+ interrupts = <32 8 33 8>;
+ interrupt-parent = <>;
+ };
+
+ enet0: ethernet@2000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "clk9";
+ tx-clock-name = "clk10";
+ fixed-link = <1 1 100 0 0>;
+ };
+
+ enet2: ethernet@2200 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "clk11";
+ tx-clock-name = "clk12";
+ phy-handle = <>;
+ phy-connection-type = "mii";
+ };
+
+ mdio0: mdio@2120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2120 0x18>;
+ compatible = "fsl,ucc-mdio";
+
+ phy0: ethernet-phy@00 {
+ reg = <0x01>;
+ device_type = "ethernet-phy";
+ };
+ phy1: ethernet-phy@01 {
+ reg = <0x02>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+
+ };
+
+};
Does this work with linux? If so, it should be OK
I miss something like:
https://gitlab.denx.de/u-boot/u-boot/-/commit/7bdfe8592956439743cad3c2d3ff5f24c4dd5aa9#8fd63f1c0ee54bb5ed6e0446595997296ab56205
Important here:
{
compatible = "fsl,qe", "simple-bus";
};
The defconfig is updated with
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
Re: [PATCH v2 5/5] x86: video: Show information about each video device
Hi Bin, On Tue, 22 Sep 2020 at 14:55, Simon Glass wrote: > > At present the 'bdinfo' command shows the framebuffer address, but not the > address of the copy framebuffer, if present. Add support for this. > > Signed-off-by: Simon Glass > Reviewed-by: Bin Meng > --- > > (no changes since v1) > > cmd/bdinfo.c | 26 +- > 1 file changed, 25 insertions(+), 1 deletion(-) > This one breaks with other archs so I sent v3. Regards, Simon
[PATCH v3 0/5] x86: Updates to some commands
This series adds a few more features to some x86-specific commands. Changes in v3: - Update header file to avoid build error with !DM_VIDEO Changes in v2: - Fix '93' typo - Capitalise 'System' Simon Glass (5): x86: hob: Add way to show a single hob entry x86: hob: Try to show a name instead of a GUID x86: Allow showing details about a HOB entry x86: Add support for more than 8 MTRRs x86: video: Show information about each video device arch/x86/cpu/mtrr.c| 12 ++-- arch/x86/include/asm/fsp/fsp_hob.h | 25 arch/x86/include/asm/mtrr.h| 15 - cmd/bdinfo.c | 26 +++- cmd/x86/hob.c | 100 +++-- cmd/x86/mtrr.c | 9 +-- include/video.h| 6 +- 7 files changed, 169 insertions(+), 24 deletions(-) -- 2.28.0.681.g6f77f65b4e-goog
[PATCH v3 5/5] x86: video: Show information about each video device
At present the 'bdinfo' command shows the framebuffer address, but not the
address of the copy framebuffer, if present. Add support for this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3:
- Update header file to avoid build error with !DM_VIDEO
cmd/bdinfo.c| 26 +-
include/video.h | 6 ++
2 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 9593b345a3d..2d88eb18ba7 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -8,9 +8,11 @@
#include
#include
+#include
#include
#include
#include
+#include
#include
#include
@@ -66,6 +68,26 @@ __weak void arch_print_bdinfo(void)
{
}
+static void show_video_info(void)
+{
+ const struct udevice *dev;
+ struct uclass *uc;
+
+ uclass_id_foreach_dev(UCLASS_VIDEO, dev, uc) {
+ printf("%-12s= %s %sactive\n", "Video", dev->name,
+ device_active(dev) ? "" : "in");
+ if (device_active(dev)) {
+ struct video_priv *upriv = dev_get_uclass_priv(dev);
+
+ print_phys_addr("FB base", (ulong)upriv->fb);
+ if (upriv->copy_fb)
+ print_phys_addr("FB copy",
(ulong)upriv->copy_fb);
+ printf("%-12s= %dx%dx%d\n", "FB size", upriv->xsize,
+ upriv->ysize, 1 << upriv->bpix);
+ }
+ }
+}
+
int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
struct bd_info *bd = gd->bd;
@@ -96,7 +118,9 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
bdinfo_print_num("fdt_blob", (ulong)gd->fdt_blob);
bdinfo_print_num("new_fdt", (ulong)gd->new_fdt);
bdinfo_print_num("fdt_size", (ulong)gd->fdt_size);
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
+ if (IS_ENABLED(CONFIG_DM_VIDEO))
+ show_video_info();
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
bdinfo_print_num("FB base ", gd->fb_base);
#endif
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
diff --git a/include/video.h b/include/video.h
index 1a0ffd80379..9d09d2409af 100644
--- a/include/video.h
+++ b/include/video.h
@@ -13,8 +13,6 @@
#ifndef _VIDEO_H_
#define _VIDEO_H_
-#ifdef CONFIG_DM_VIDEO
-
#include
struct udevice;
@@ -140,6 +138,7 @@ struct video_ops {
*/
int video_reserve(ulong *addrp);
+#ifdef CONFIG_DM_VIDEO
/**
* video_clear() - Clear a device's frame buffer to background color.
*
@@ -147,6 +146,7 @@ int video_reserve(ulong *addrp);
* @return 0
*/
int video_clear(struct udevice *dev);
+#endif /* CONFIG_DM_VIDEO */
/**
* video_sync() - Sync a device's frame buffer with its hardware
@@ -243,8 +243,6 @@ static inline int video_sync_copy(struct udevice *dev, void
*from, void *to)
}
#endif
-#endif /* CONFIG_DM_VIDEO */
-
#ifndef CONFIG_DM_VIDEO
/* Video functions */
--
2.28.0.681.g6f77f65b4e-goog
[PULL] u-boot-mips fixes for v2020.10
Hi Tom, this contains some small fixes isolated to two MIPS boards which are currently broken. Gitlab CI: https://gitlab.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/4758 The following changes since commit 5949f36f083515e2bb55f1a9c9110b287fbab587: Merge branch '2020-09-22-assorted-bugfixes' (2020-09-22 16:47:48 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-mips.git tags/mips-fixes-for-2020.10 for you to fetch changes up to 7d1538cc9bb87d12dcd8c9f9b07c17bb510042ef: mips: vocore2: fix various issues (2020-09-23 00:14:56 +0200) - mips: vocore2: fix SPL image generation - mips: vocore2: fix LZMA decompression errors - mips: vocore2: fix console output - mips: pic32mzda: fix DTC warnings and GPIO nodes - mips: pic32mzda: make GPIO and MMC working again John Robertson (7): mmc: pic32: Refresh PIC32 MMC driver pinmux: pic32: add SDHCI pin config mips: pic32mzdask: disable SDHCI SDCD signal workaround mips: pic32mzdask: enable CONFIG_BLK mips: dts: Fix device tree warnings for PIC32MZDA mips: dts: Fix PIC32MZDA GPIO register definitions mips: dts: Fix PIC32MZDA GPIO register definitions Mauro Condarelli (1): mips: vocore2: fix various issues arch/mips/dts/pic32mzda.dtsi | 56 +++--- arch/mips/dts/pic32mzda_sk.dts | 1 + arch/mips/dts/vocore_vocore2.dts | 2 +- configs/pic32mzdask_defconfig| 1 - configs/vocore2_defconfig| 2 +- drivers/mmc/pic32_sdhci.c| 86 +++- drivers/pinctrl/pinctrl_pic32.c | 28 + include/configs/vocore2.h| 4 +- 8 files changed, 117 insertions(+), 63 deletions(-)
Re: [PATCH 3/3] doc: global data pointer
Am Samstag, den 19.09.2020, 18:03 +0200 schrieb Heinrich Schuchardt: > Add the description of the global data pointer to the generated HTML > documentation. > > Signed-off-by: Heinrich Schuchardt > --- > doc/develop/global_data.rst | 53 + > doc/develop/index.rst | 1 + > 2 files changed, 54 insertions(+) > create mode 100644 doc/develop/global_data.rst > > diff --git a/doc/develop/global_data.rst b/doc/develop/global_data.rst > new file mode 100644 > index 00..9e7c8a24da > --- /dev/null > +++ b/doc/develop/global_data.rst > @@ -0,0 +1,53 @@ > +.. SPDX-License-Identifier: GPL-2.0+ > + > +Global data > +=== > + > +Globally required fields are held in the global data structure. A pointer to > the > +structure is available as symbol gd. The symbol is made available by the > macro > +%DECLARE_GLOBAL_DATA_PTR. > + > +Register pointing to global data > + > + > +On most architectures the global data pointer is stored in a register. > + > +++--+ > +| ARC| r25 | > +++--+ > +| ARM 32bit | r9 | > +++--+ > +| ARM 64bit | x18 | > +++--+ > +| M68000 | d7 | > +++--+ > +| MicroBlaze | r31 | > +++--+ > +| NDS32 | r10 | > +++--+ > +| Nios II| gp | > +++--+ > +| PowerPC| r2 | > +++--+ > +| RISC-V | gp (x3) | > +++--+ > +| SuperH | r13 | > +++--+ if you want to add MIPS to the list, the register is: $26 (k0) > + > +The sandbox, x86, and Xtensa are notable exceptions. > + > +Clang for ARM does not support assigning a global register. When using Clang > +gd is defined as an inline function using assembly code. This adds a few > bytes > +to the code size. > + > +Binaries called by U-Boot are not aware of the register usage and will not > +conserve gd. UEFI binaries call the API provided by U-Boot and may return to > +U-Boot. The value of gd has to be saved every time U-Boot is left and > restored > +whenever U-Boot is reentered. This is also relevant for the implementation of > +function tracing. For setting the value of gd function set_gd() can be used. > + > +Global data structure > +- > + > +.. kernel-doc:: include/asm-generic/global_data.h > + :internal: > diff --git a/doc/develop/index.rst b/doc/develop/index.rst > index 98a95ad434..89e80eab94 100644 > --- a/doc/develop/index.rst > +++ b/doc/develop/index.rst > @@ -9,4 +9,5 @@ Develop U-Boot > > coccinelle > crash_dumps > + global_data > logging > -- > 2.28.0 > -- - Daniel
Re: [PATCH 0/3] Patches to allow running u-boot on vocore2 board
Am Sonntag, den 20.09.2020, 18:28 +0200 schrieb Mauro Condarelli: > There are two distinct things here: > - a few small fixes specific to vocore2 board. > - fixes to SquashFS to allow compilation on 32-bit architectures. > > Mauro Condarelli (3): > Small fixes to reduce size and ensure correct console output. > Enlarge SPL malloc area to prevent failure in lzma decompression. > Fix missing __udivdi3 in SquashFS implementation. > > arch/mips/dts/vocore_vocore2.dts | 2 +- > configs/vocore2_defconfig| 2 +- > fs/squashfs/sqfs.c | 45 > fs/squashfs/sqfs_inode.c | 8 +++--- > include/configs/vocore2.h| 4 ++- > 5 files changed, 38 insertions(+), 23 deletions(-) > all vocore2 patches applied to u-boot-mips/fixes, thanks. Next time please prefix the commit subjects with the subsystem you're changing e.g. "mips: vocore2: XXX" or "squashfs: XXX". I've taken all vocore2 changes and squashed them into one commit to save another patch submission round and to squeeze the fixes into v2020.10. -- - Daniel
Re: [PATCH 3/3] Fix missing __udivdi3 in SquashFS implementation.
Am Sonntag, den 20.09.2020, 21:21 -0400 schrieb Tom Rini:
> On Sun, Sep 20, 2020 at 06:29:01PM +0200, Mauro Condarelli wrote:
>
> > Signed-off-by: Mauro Condarelli
> > ---
> > fs/squashfs/sqfs.c| 45 +--
> > fs/squashfs/sqfs_inode.c | 8 +++
> > include/configs/vocore2.h | 2 +-
remove that file which is unrelated to this patch
> > 3 files changed, 34 insertions(+), 21 deletions(-)
> >
> > diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
> > index 15208b4dab..b49331ce93 100644
> > --- a/fs/squashfs/sqfs.c
> > +++ b/fs/squashfs/sqfs.c
> > @@ -18,6 +18,8 @@
> > #include
> > #include
> > #include
> > +#include
> > +#include
> >
> > #include "sqfs_decompressor.h"
> > #include "sqfs_filesystem.h"
> > @@ -82,13 +84,16 @@ static int sqfs_count_tokens(const char *filename)
> > */
> > static int sqfs_calc_n_blks(__le64 start, __le64 end, u64 *offset)
> > {
> > - u64 start_, table_size;
> > + u64 start_, table_size, blks;
> >
> > table_size = le64_to_cpu(end) - le64_to_cpu(start);
> > - start_ = le64_to_cpu(start) / ctxt.cur_dev->blksz;
> > + start_ = le64_to_cpu(start);
> > + do_div(start_, ctxt.cur_dev->blksz);
have you tried with lldiv() which returns the 64bit result? Also it
would be a little cleaner:
start_ = lldiv(le64_to_cpu(start), ctxt.cur_dev->blksz);
> > *offset = le64_to_cpu(start) - (start_ * ctxt.cur_dev->blksz);
> >
> > - return DIV_ROUND_UP(table_size + *offset, ctxt.cur_dev->blksz);
> > + blks = table_size + *offset;
> > + if (do_div(blks, ctxt.cur_dev->blksz)) blks++;
> > + return blks;
maybe define something like this and use that instead of DIV_ROUND_UP:
#define lldiv_round_up(n, d) lldiv((n) + (d) - 1, (d))
> > }
> >
> > /*
> > @@ -109,8 +114,8 @@ static int sqfs_frag_lookup(u32 inode_fragment_index,
> > if (inode_fragment_index >= get_unaligned_le32(>fragments))
> > return -EINVAL;
> >
> > - start = get_unaligned_le64(>fragment_table_start) /
> > - ctxt.cur_dev->blksz;
> > + start = get_unaligned_le64(>fragment_table_start);
> > + do_div(start, ctxt.cur_dev->blksz);
> > n_blks = sqfs_calc_n_blks(sblk->fragment_table_start,
> > sblk->export_table_start,
> > _offset);
> > @@ -135,7 +140,8 @@ static int sqfs_frag_lookup(u32 inode_fragment_index,
> > start_block = get_unaligned_le64(table + table_offset + block *
> > sizeof(u64));
> >
> > - start = start_block / ctxt.cur_dev->blksz;
> > + start = start_block;
> > + do_div(start, ctxt.cur_dev->blksz);
> > n_blks = sqfs_calc_n_blks(cpu_to_le64(start_block),
> > sblk->fragment_table_start, _offset);
> >
> > @@ -641,8 +647,8 @@ static int sqfs_read_inode_table(unsigned char
> > **inode_table)
> >
> > table_size = get_unaligned_le64(>directory_table_start) -
> > get_unaligned_le64(>inode_table_start);
> > - start = get_unaligned_le64(>inode_table_start) /
> > - ctxt.cur_dev->blksz;
> > + start = get_unaligned_le64(>inode_table_start);
> > + do_div(start, ctxt.cur_dev->blksz);
> > n_blks = sqfs_calc_n_blks(sblk->inode_table_start,
> > sblk->directory_table_start, _offset);
> >
> > @@ -725,8 +731,8 @@ static int sqfs_read_directory_table(unsigned char
> > **dir_table, u32 **pos_list)
> > /* DIRECTORY TABLE */
> > table_size = get_unaligned_le64(>fragment_table_start) -
> > get_unaligned_le64(>directory_table_start);
> > - start = get_unaligned_le64(>directory_table_start) /
> > - ctxt.cur_dev->blksz;
> > + start = get_unaligned_le64(>directory_table_start);
> > + do_div(start, ctxt.cur_dev->blksz);
> > n_blks = sqfs_calc_n_blks(sblk->directory_table_start,
> > sblk->fragment_table_start, _offset);
> >
> > @@ -1158,6 +1164,7 @@ static int sqfs_get_regfile_info(struct
> > squashfs_reg_inode *reg,
> >fentry);
> > if (ret < 0)
> > return -EINVAL;
> > +
> > finfo->comp = true;
> > if (fentry->size < 1 || fentry->start == 0x7FFF)
> > return -EINVAL;
> > @@ -1328,17 +1335,19 @@ int sqfs_read(const char *filename, void *buf,
> > loff_t offset, loff_t len,
> > data_offset = finfo.start;
> > datablock = malloc(get_unaligned_le32(>block_size));
> > if (!datablock) {
> > + printf("Error: malloc(%u) failed.\n",
> > get_unaligned_le32(>block_size));
> > ret = -ENOMEM;
> > goto free_paths;
> > }
> > }
> >
> > for (j = 0; j < datablk_count; j++) {
> > - start = data_offset / ctxt.cur_dev->blksz;
> > + start = data_offset;
> > + do_div(start, ctxt.cur_dev->blksz);
>
Re: [PATCH 1/2] log: allow for message continuation
Hi Heinrich,
On Tue, 22 Sep 2020 at 13:10, Heinrich Schuchardt wrote:
>
> On 9/22/20 8:48 PM, Simon Glass wrote:
> > Hi Heinrich,
> >
> > On Thu, 17 Sep 2020 at 06:19, Heinrich Schuchardt
> > wrote:
> >>
> >> Some drivers use macro pr_cont() for continuing a message sent via printk.
> >> Hence if we want to convert printk messaging to using the logging system,
> >> we must support continuation of log messages too.
> >>
> >> As pr_cont() does not provide a message level we need a means of
> >> remembering the last log level.
> >>
> >> With the patch a pseudo log level LOGL_CONT as well as a pseudo log
> >> category LOGC_CONT are introduced. Using these results in the application
> >> of the same log level and category as in the previous log message.
> >>
> >> Signed-off-by: Heinrich Schuchardt
> >> ---
> >> common/log.c| 23 ++-
> >> doc/develop/logging.rst | 6 ++
> >> include/log.h | 2 ++
> >> 3 files changed, 26 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/common/log.c b/common/log.c
> >> index 9a5f100da3..bafc09f263 100644
> >> --- a/common/log.c
> >> +++ b/common/log.c
> >> @@ -183,10 +183,12 @@ static bool log_passes_filters(struct log_device
> >> *ldev, struct log_rec *rec)
> >> * log_dispatch() - Send a log record to all log devices for processing
> >> *
> >> * The log record is sent to each log device in turn, skipping those
> >> which have
> >> - * filters which block the record
> >> + * filters which block the record.
> >> *
> >> - * @rec: Log record to dispatch
> >> - * @return 0 (meaning success)
> >> + * All log messages created while processing log record @rec are ignored.
> >> + *
> >> + * @rec: log record to dispatch
> >> + * Return: 0 msg sent, 1 msg not sent while already dispatching
> >> another msg
> >> */
> >> static int log_dispatch(struct log_rec *rec)
> >> {
> >> @@ -199,7 +201,7 @@ static int log_dispatch(struct log_rec *rec)
> >> * as this might result in infinite recursion.
> >> */
> >> if (processing_msg)
> >> - return 0;
> >> + return 1;
> >>
> >> /* Emit message */
> >> processing_msg = 1;
> >> @@ -214,10 +216,18 @@ static int log_dispatch(struct log_rec *rec)
> >> int _log(enum log_category_t cat, enum log_level_t level, const char
> >> *file,
> >> int line, const char *func, const char *fmt, ...)
> >> {
> >> + static enum log_category_t logc_prev = LOGC_NONE;
> >> + static enum log_level_t logl_prev = LOGL_INFO;
> >
> > I don't think we can use static variables in logging. Perhaps we can
> > use gobal_data?
>
> Are you worried about relocation?
Yes, and SPL.
>
> The initialization of the global data fields should be done in
> log_init() before gd->flags |= GD_FLG_LOG_READY; I assume.
Yes.
>
> Is the rest ok for you?
Yes. If you are adding new things to global_data you could convert
default_log_level to a char to avoid using more space.
>
> Best regards
>
> Heinrich
>
> >
> >
> >> char buf[CONFIG_SYS_CBSIZE];
> >> struct log_rec rec;
> >> va_list args;
> >>
> >> + /* Check for message continuation */
> >> + if (cat == LOGC_CONT)
> >
> > Regards,
> > Simon
> >
>
Re: [PATCH 0/5] edison: Support for writing an xFSTK image
Hi Bin, On Tue, 22 Sep 2020 at 01:11, Bin Meng wrote: > > Hi Simon, > > On Fri, Sep 4, 2020 at 9:28 AM Simon Glass wrote: > > > > At present it is painful to put Edison in a hardware lab because it has > > two separate recovery modes. When the board has a functioning U-Boot, DFU > > can be used. Otherwise an xFSTK image must be used. > > > > This series converts Andy's script to a binman description so that U-Boot > > can produce an xFSTK image directly. > > > > With this, I can put an Edison in my lab fairly easily. > > > > The series is available at u-boot-dm/edison-working and is based on the > > reset binman series for sunxi. > > > > [1] https://gist.github.com/andy-shev/2c388310f2773ead647d9c1a3f1c813f > > > > > > This series does not apply on u-boot-x86/next. > > Is this due to "the reset binman series for sunxi" not applied yet? Yes. It's in dm/next but I'll send a pull request upstream. Regards, Simon
Please pull u-boot-dm/next into 'next'
Hi Tom, This is for upstream/next Build here: https://gitlab.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/4750 The following changes since commit 2512b3b88ba6b193c3cada7e29e386613e8f9a6b: Merge branch '2020-09-14-generic-phy-error-trace' into next (2020-09-21 16:44:16 -0400) are available in the Git repository at: git://git.denx.de/u-boot-dm.git tags/dm-pull-22sep20 for you to fetch changes up to e5b35f706d13c8c0fffcf7b2af9c6df4f4190c5d: log: mute messages generated by log drivers (2020-09-22 12:54:13 -0600) binman enhancements for FIT sunxi64 conversion to use binman New 'no-map' property for reserved memory Alper Nebi Yasak (8): binman: Ignore hash*, signature* nodes in sections binman: Respect pad-before property of section subentries binman: Build FIT image subentries with the section etype buildman: Use git worktrees instead of git clones when possible binman: Support cross-compiling test files to x86 binman: Use target-specific tools when cross-compiling binman: Allow resolving host-specific tools from env vars binman: Document how CROSS_COMPILE, CC, HOSTCC etc. are used in README Etienne Carriere (2): fdtdec: optionally add property no-map to created reserved memory node optee: add property no-map to secure reserved memory Heinrich Schuchardt (2): dm: syscon: typo alerady log: mute messages generated by log drivers Patrice Chotard (1): test: fdtdec: Add test for new no-map fdtdec_add_reserved_memory() parameter Patrick Delaunay (1): dm: add cells_count parameter in live DT APIs of_parse_phandle_with_args Simon Glass (14): binman: Use pkg_resources to find resources tools: Drop unnecessary use of __file__ binman: Allow entry args to be required binman: Fix up a few missing comments libfdt: Detected out-of-space with fdt_finish() binman: Move 'external' support into base class binman: Add support for ATF BL31 binman: Support generating FITs with multiple dtbs Makefile: Support missing external blobs always sunxi: Convert 64-bit boards to use binman sunxi: Drop the FIT-generator script binman: Allow selecting default FIT configuration binman: Support help messages for missing blobs binman: sunxi: Add help message for missing sunxi ATF BL31 Walter Lozano (1): core: improve of_match_ptr with OF_PLATDATA Kconfig | 3 +- Makefile| 23 +--- arch/arm/dts/sunxi-u-boot.dtsi | 62 - arch/riscv/lib/fdt_fixup.c | 2 +- board/sunxi/mksunxi_fit_atf.sh | 87 common/log.c| 13 +- common/log_syslog.c | 8 -- drivers/core/of_access.c| 7 +- drivers/core/ofnode.c | 3 +- drivers/core/syscon-uclass.c| 10 +- include/dm/device.h | 2 +- include/dm/of_access.h | 4 +- include/fdtdec.h| 5 +- lib/fdtdec.c| 10 +- lib/optee/optee.c | 2 +- scripts/dtc/pylibfdt/libfdt.i_shipped | 3 +- test/dm/fdtdec.c| 9 +- tools/binman/README | 30 + tools/binman/README.entries | 73 ++- tools/binman/control.py | 80 +++- tools/binman/elf.py | 6 +- tools/binman/elf_test.py| 4 +- tools/binman/entry.py | 25 +++- tools/binman/etype/atf_bl31.py | 24 tools/binman/etype/blob.py | 8 +- tools/binman/etype/blob_ext.py | 11 -- tools/binman/etype/blob_named_by_arg.py | 10 +- tools/binman/etype/cros_ec_rw.py| 3 +- tools/binman/etype/fit.py | 176 + tools/binman/etype/section.py | 18 +-- tools/binman/ftest.py | 247 +-- tools/binman/missing-blob-help | 15 +++ tools/binman/test/165_section_ignore_hash_signature.dts | 40 ++ tools/binman/test/166_pad_in_sections.dts | 26 tools/binman/test/167_fit_image_subentry_alignment.dts | 57
[PATCH v2 3/5] x86: Allow showing details about a HOB entry
Some HOBs include information that can be decoded. Add a -v option to the
hob command, to allow this to be displayed. Add the ability to decode a
resource descriptor.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
- Capitalise 'System'
cmd/x86/hob.c | 49 +
1 file changed, 45 insertions(+), 4 deletions(-)
diff --git a/cmd/x86/hob.c b/cmd/x86/hob.c
index 98a67600086..9e555c778c2 100644
--- a/cmd/x86/hob.c
+++ b/cmd/x86/hob.c
@@ -27,6 +27,16 @@ static char *hob_type[] = {
"Capsule",
};
+static char *res_type[] = {
+ "System",
+ "Memory-mapped I/O",
+ "I/O",
+ "Firmware device",
+ "Memory-mapped I/O port",
+ "Reserved",
+ "I/O reserved",
+};
+
static struct guid_name {
efi_guid_t guid;
const char *name;
@@ -58,6 +68,26 @@ static const char *guid_to_name(const efi_guid_t *guid)
return NULL;
}
+static void show_hob_details(const struct hob_header *hdr)
+{
+ const void *ptr = hdr;
+
+ switch (hdr->type) {
+ case HOB_TYPE_RES_DESC: {
+ const struct hob_res_desc *res = ptr;
+ const char *typename;
+
+ typename = res->type > 0 && res->type <= RES_MAX_MEM_TYPE ?
+ res_type[res->type] : "unknown";
+
+ printf(" base = %08llx, len = %08llx, end = %08llx, type =
%d (%s)\n\n",
+ res->phys_start, res->len, res->phys_start + res->len,
+ res->type, typename);
+ break;
+ }
+ }
+}
+
static int do_hob(struct cmd_tbl *cmdtp, int flag, int argc, char *const
argv[])
{
const struct hob_header *hdr;
@@ -66,12 +96,20 @@ static int do_hob(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
int i = 0;
efi_guid_t *guid;
char uuid[UUID_STR_LEN + 1];
+ bool verbose = false;
int seq = -1; /* Show all by default */
argc--;
argv++;
- if (argc)
- seq = simple_strtol(*argv, NULL, 16);
+ if (argc) {
+ if (!strcmp("-v", *argv)) {
+ verbose = true;
+ argc--;
+ argv++;
+ }
+ if (argc)
+ seq = simple_strtol(*argv, NULL, 16);
+ }
hdr = gd->arch.hob_list;
printf("HOB list address: 0x%08x\n\n", (unsigned int)hdr);
@@ -111,13 +149,16 @@ static int do_hob(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
printf("%36s", "Not Available");
}
printf("\n");
+ if (verbose)
+ show_hob_details(hdr);
}
return 0;
}
-U_BOOT_CMD(hob, 2, 1, do_hob,
- "[seq] Print Hand-Off Block (HOB) information"
+U_BOOT_CMD(hob, 3, 1, do_hob,
+ "[-v] [seq] Print Hand-Off Block (HOB) information"
+ " -v - Show detailed HOB information where available"
" seq - Record # to show (all by default)",
""
);
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v2 2/5] x86: hob: Try to show a name instead of a GUID
GUIDs are one of the seven evils of the computer world. They obfuscate the
meaning and require people to look up long hex strings to decode it.
Luckily only a miniscule fraction of the 10^38 possible GUIDs are in use.
Add a way to decode the GUIDs known to U-Boot. Add a few more to the list
for good measure.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
- Fix '93' typo
arch/x86/include/asm/fsp/fsp_hob.h | 25 +
cmd/x86/hob.c | 43 --
2 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/fsp/fsp_hob.h
b/arch/x86/include/asm/fsp/fsp_hob.h
index d248520e972..ea3983e04ff 100644
--- a/arch/x86/include/asm/fsp/fsp_hob.h
+++ b/arch/x86/include/asm/fsp/fsp_hob.h
@@ -99,4 +99,29 @@ struct __packed hob_graphics_info {
EFI_GUID(0x39f62cce, 0x6825, 0x4669, \
0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07)
+/* The following GUIDs are observed with FSP 2.1 / Apollo Lake */
+#define FSP_HOB_RESOURCE_OWNER_SMM_PEI_SMRAM_GUID \
+ EFI_GUID(0x6dadf1d1, 0xd4cc, 0x4910, \
+ 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d)
+
+#define FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID1 \
+ EFI_GUID(0xea296d92, 0x0b69, 0x423c, \
+ 0x8c, 0x28, 0x33, 0xb4, 0xe0, 0xa9, 0x12, 0x68)
+
+#define FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID2 \
+ EFI_GUID(0x9b3ada4f, 0xae56, 0x4c24, \
+ 0x8d, 0xea, 0xf0, 0x3b, 0x75, 0x58, 0xae, 0x50)
+
+#define FSP_HOB_RESOURCE_OWNER_PEIM_DXE_GUID \
+ EFI_GUID(0x86d70125, 0xbaa3, 0x4296, \
+ 0xa6, 0x2f, 0x60, 0x2b, 0xeb, 0xbb, 0x90, 0x81)
+
+#define FSP_HOB_RESOURCE_OWNER_ALLOC_STACK_GUID \
+ EFI_GUID(0x4ed4bf27, 0x4092, 0x42e9, \
+ 0x80, 0x7d, 0x52, 0x7b, 0x1d, 0x00, 0xc9, 0xbd)
+
+#define FSP_HOB_RESOURCE_OWNER_SMBIOS_MEMORY_GUID \
+ EFI_GUID(0x01a1108c, 0x9dee, 0x4984, \
+ 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89)
+
#endif
diff --git a/cmd/x86/hob.c b/cmd/x86/hob.c
index e3f512beee8..98a67600086 100644
--- a/cmd/x86/hob.c
+++ b/cmd/x86/hob.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -26,6 +27,37 @@ static char *hob_type[] = {
"Capsule",
};
+static struct guid_name {
+ efi_guid_t guid;
+ const char *name;
+} guid_name[] = {
+ { FSP_HOB_RESOURCE_OWNER_TSEG_GUID, "TSEG" },
+ { FSP_HOB_RESOURCE_OWNER_FSP_GUID, "FSP" },
+ { FSP_HOB_RESOURCE_OWNER_SMM_PEI_SMRAM_GUID, "SMM PEI SMRAM" },
+ { FSP_NON_VOLATILE_STORAGE_HOB_GUID, "NVS" },
+ { FSP_VARIABLE_NV_DATA_HOB_GUID, "Variable NVS" },
+ { FSP_GRAPHICS_INFO_HOB_GUID, "Graphics info" },
+ { FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID1, "PCD database ea" },
+ { FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID2, "PCD database 9b" },
+ { FSP_HOB_RESOURCE_OWNER_PEIM_DXE_GUID, "PEIM Init DXE" },
+ { FSP_HOB_RESOURCE_OWNER_ALLOC_STACK_GUID, "Alloc stack" },
+ { FSP_HOB_RESOURCE_OWNER_SMBIOS_MEMORY_GUID, "SMBIOS memory" },
+ { {}, "zero-guid" },
+ {}
+};
+
+static const char *guid_to_name(const efi_guid_t *guid)
+{
+ struct guid_name *entry;
+
+ for (entry = guid_name; entry->name; entry++) {
+ if (!guidcmp(guid, >guid))
+ return entry->name;
+ }
+
+ return NULL;
+}
+
static int do_hob(struct cmd_tbl *cmdtp, int flag, int argc, char *const
argv[])
{
const struct hob_header *hdr;
@@ -65,9 +97,16 @@ static int do_hob(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC ||
type == HOB_TYPE_GUID_EXT) {
+ const char *name;
+
guid = (efi_guid_t *)(hdr + 1);
- uuid_bin_to_str(guid->b, uuid, UUID_STR_FORMAT_GUID);
- printf("%s", uuid);
+ name = guid_to_name(guid);
+ if (!name) {
+ uuid_bin_to_str(guid->b, uuid,
+ UUID_STR_FORMAT_GUID);
+ name = uuid;
+ }
+ printf("%36s", name);
} else {
printf("%36s", "Not Available");
}
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v2 1/5] x86: hob: Add way to show a single hob entry
The 'hob' command currently lists all HOB entries. Add way to list a
single entry, by index.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v1)
cmd/x86/hob.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/cmd/x86/hob.c b/cmd/x86/hob.c
index 6b1f7bda5b8..e3f512beee8 100644
--- a/cmd/x86/hob.c
+++ b/cmd/x86/hob.c
@@ -34,7 +34,12 @@ static int do_hob(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
int i = 0;
efi_guid_t *guid;
char uuid[UUID_STR_LEN + 1];
+ int seq = -1; /* Show all by default */
+ argc--;
+ argv++;
+ if (argc)
+ seq = simple_strtol(*argv, NULL, 16);
hdr = gd->arch.hob_list;
printf("HOB list address: 0x%08x\n\n", (unsigned int)hdr);
@@ -43,7 +48,9 @@ static int do_hob(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
printf("%36s\n", "GUID");
printf("---|--|---|--|-");
printf("\n");
- while (!end_of_hob(hdr)) {
+ for (i = 0; !end_of_hob(hdr); i++, hdr = get_next_hob(hdr)) {
+ if (seq != -1 && seq != i)
+ continue;
printf("%02x | %08x | ", i, (unsigned int)hdr);
type = hdr->type;
if (type == HOB_TYPE_UNUSED)
@@ -65,14 +72,13 @@ static int do_hob(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
printf("%36s", "Not Available");
}
printf("\n");
- hdr = get_next_hob(hdr);
- i++;
}
return 0;
}
-U_BOOT_CMD(hob, 1, 1, do_hob,
- "Print Hand-Off Block (HOB) information",
+U_BOOT_CMD(hob, 2, 1, do_hob,
+ "[seq] Print Hand-Off Block (HOB) information"
+ " seq - Record # to show (all by default)",
""
);
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v2 4/5] x86: Add support for more than 8 MTRRs
At present the mtrr command only support 8 MTRRs. Some SoCs have more than
that. Update the implementation to support up to 10. Read the number of
MTRRs dynamically instead.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v1)
arch/x86/cpu/mtrr.c | 12 +++-
arch/x86/include/asm/mtrr.h | 15 ---
cmd/x86/mtrr.c | 9 +
3 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index 2468d88a80a..aed4c411367 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c
@@ -66,9 +66,10 @@ static void set_var_mtrr(uint reg, uint type, uint64_t
start, uint64_t size)
void mtrr_read_all(struct mtrr_info *info)
{
+ int reg_count = mtrr_get_var_count();
int i;
- for (i = 0; i < MTRR_COUNT; i++) {
+ for (i = 0; i < reg_count; i++) {
info->mtrr[i].base = native_read_msr(MTRR_PHYS_BASE_MSR(i));
info->mtrr[i].mask = native_read_msr(MTRR_PHYS_MASK_MSR(i));
}
@@ -76,10 +77,11 @@ void mtrr_read_all(struct mtrr_info *info)
void mtrr_write_all(struct mtrr_info *info)
{
+ int reg_count = mtrr_get_var_count();
struct mtrr_state state;
int i;
- for (i = 0; i < MTRR_COUNT; i++) {
+ for (i = 0; i < reg_count; i++) {
mtrr_open(, true);
wrmsrl(MTRR_PHYS_BASE_MSR(i), info->mtrr[i].base);
wrmsrl(MTRR_PHYS_MASK_MSR(i), info->mtrr[i].mask);
@@ -144,7 +146,7 @@ int mtrr_commit(bool do_caches)
/* Clear the ones that are unused */
debug("clear\n");
- for (; i < MTRR_COUNT; i++)
+ for (; i < MTRR_MAX_COUNT; i++)
wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
debug("close\n");
mtrr_close(, do_caches);
@@ -184,7 +186,7 @@ int mtrr_add_request(int type, uint64_t start, uint64_t
size)
return 0;
}
-static int get_var_mtrr_count(void)
+int mtrr_get_var_count(void)
{
return msr_read(MSR_MTRR_CAP_MSR).lo & MSR_MTRR_CAP_VCNT;
}
@@ -195,7 +197,7 @@ static int get_free_var_mtrr(void)
int vcnt;
int i;
- vcnt = get_var_mtrr_count();
+ vcnt = mtrr_get_var_count();
/* Identify the first var mtrr which is not valid */
for (i = 0; i < vcnt; i++) {
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index 48db1dd82f7..3a98aacdef5 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -36,8 +36,8 @@
#define MTRR_BASE_TYPE_MASK0x7
-/* Number of MTRRs supported */
-#define MTRR_COUNT 8
+/* Maximum number of MTRRs supported - see also mtrr_get_var_count() */
+#define MTRR_MAX_COUNT 10
#define NUM_FIXED_MTRRS11
#define RANGES_PER_FIXED_MTRR 8
@@ -87,7 +87,7 @@ struct mtrr {
* @mtrr: Information about each mtrr
*/
struct mtrr_info {
- struct mtrr mtrr[MTRR_COUNT];
+ struct mtrr mtrr[MTRR_MAX_COUNT];
};
/**
@@ -180,6 +180,15 @@ int mtrr_set_valid(int cpu_select, int reg, bool valid);
*/
int mtrr_set(int cpu_select, int reg, u64 base, u64 mask);
+/**
+ * mtrr_get_var_count() - Get the number of variable MTRRs
+ *
+ * Some CPUs have more than 8 MTRRs. This function returns the actual number
+ *
+ * @return number of variable MTRRs
+ */
+int mtrr_get_var_count(void);
+
#endif
#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c
index 99efecb9d8e..fc61a549b02 100644
--- a/cmd/x86/mtrr.c
+++ b/cmd/x86/mtrr.c
@@ -27,7 +27,7 @@ static void read_mtrrs(void *arg)
mtrr_read_all(info);
}
-static int do_mtrr_list(int cpu_select)
+static int do_mtrr_list(int reg_count, int cpu_select)
{
struct mtrr_info info;
int ret;
@@ -39,7 +39,7 @@ static int do_mtrr_list(int cpu_select)
ret = mp_run_on_cpus(cpu_select, read_mtrrs, );
if (ret)
return log_msg_ret("run", ret);
- for (i = 0; i < MTRR_COUNT; i++) {
+ for (i = 0; i < reg_count; i++) {
const char *type = "Invalid";
uint64_t base, mask, size;
bool valid;
@@ -98,6 +98,7 @@ static int do_mtrr_set(int cpu_select, uint reg, int argc,
char *const argv[])
static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
+ int reg_count = mtrr_get_var_count();
int cmd;
int cpu_select;
uint reg;
@@ -126,7 +127,7 @@ static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int
argc,
if (argc < 2)
return CMD_RET_USAGE;
reg = simple_strtoul(argv[1], NULL, 16);
- if (reg >= MTRR_COUNT) {
+ if (reg >= reg_count) {
printf("Invalid register number\n");
return CMD_RET_USAGE;
}
@@ -145,7 +146,7 @@ static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int
[PATCH v2 5/5] x86: video: Show information about each video device
At present the 'bdinfo' command shows the framebuffer address, but not the
address of the copy framebuffer, if present. Add support for this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v1)
cmd/bdinfo.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 9593b345a3d..2d88eb18ba7 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -8,9 +8,11 @@
#include
#include
+#include
#include
#include
#include
+#include
#include
#include
@@ -66,6 +68,26 @@ __weak void arch_print_bdinfo(void)
{
}
+static void show_video_info(void)
+{
+ const struct udevice *dev;
+ struct uclass *uc;
+
+ uclass_id_foreach_dev(UCLASS_VIDEO, dev, uc) {
+ printf("%-12s= %s %sactive\n", "Video", dev->name,
+ device_active(dev) ? "" : "in");
+ if (device_active(dev)) {
+ struct video_priv *upriv = dev_get_uclass_priv(dev);
+
+ print_phys_addr("FB base", (ulong)upriv->fb);
+ if (upriv->copy_fb)
+ print_phys_addr("FB copy",
(ulong)upriv->copy_fb);
+ printf("%-12s= %dx%dx%d\n", "FB size", upriv->xsize,
+ upriv->ysize, 1 << upriv->bpix);
+ }
+ }
+}
+
int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
struct bd_info *bd = gd->bd;
@@ -96,7 +118,9 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
bdinfo_print_num("fdt_blob", (ulong)gd->fdt_blob);
bdinfo_print_num("new_fdt", (ulong)gd->new_fdt);
bdinfo_print_num("fdt_size", (ulong)gd->fdt_size);
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
+ if (IS_ENABLED(CONFIG_DM_VIDEO))
+ show_video_info();
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
bdinfo_print_num("FB base ", gd->fb_base);
#endif
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v2 0/5] x86: Updates to some commands
This series adds a few more features to some x86-specific commands. Changes in v2: - Fix '93' typo - Capitalise 'System' Simon Glass (5): x86: hob: Add way to show a single hob entry x86: hob: Try to show a name instead of a GUID x86: Allow showing details about a HOB entry x86: Add support for more than 8 MTRRs x86: video: Show information about each video device arch/x86/cpu/mtrr.c| 12 ++-- arch/x86/include/asm/fsp/fsp_hob.h | 25 arch/x86/include/asm/mtrr.h| 15 - cmd/bdinfo.c | 26 +++- cmd/x86/hob.c | 100 +++-- cmd/x86/mtrr.c | 9 +-- 6 files changed, 167 insertions(+), 20 deletions(-) -- 2.28.0.681.g6f77f65b4e-goog
Re: [PATCH] gpio/mpc83xx_spisel_boot.c: include log.h
On Mon, Sep 21, 2020 at 09:48:24AM +0200, Rasmus Villemoes wrote: > Fix build failure, it used to get this implicitly through common.h > until f7ae49fc4f (common: Drop log.h from common header). > > Signed-off-by: Rasmus Villemoes > Reviewed-by: Heiko Schocher Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] doc/build/gcc.rst: add missing apt-get *install*
On Sun, Sep 20, 2020 at 12:31:47PM +0200, Heinrich Schuchardt wrote: > The install command is missing for an apt-get command. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] spi: mpc8xxx_spi.c: fix cs activate/deactivate
On Fri, Sep 18, 2020 at 04:26:06PM +0200, Rasmus Villemoes wrote:
> Somewhere between v2020.04 and v2020.07 the mpc8xxx_spi driver broke,
> I'm guessing due to this hunk
>
> @@ -559,6 +560,8 @@ int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong
> flags)
> if (ret)
> return ret;
>
> + /* combine the requested flags (for IN/OUT) and the descriptor flags
> */
> + flags |= desc->flags;
> ret = _dm_gpio_set_dir_flags(desc, flags);
>
> from commit 695e5fd5469a ("gpio: update dir_flags management"). But
> the blame is mostly on the driver itself which seems rather confused:
> The chip select gpios are requested with GPIOD_ACTIVE_LOW, but then in
> each activate/deactivate, dm_gpio_set_dir_flags() is called with
> merely GPIOD_IS_OUT, and then the driver call set_value(0) for
> activate.
>
> That used to work, but with the above hunk, the ACTIVE_LOW setting
> from the request becomes persistent, so the gpio driver ends up being
> asked to set the value to 1 in mpc8xxx_spi_cs_activate().
>
> So drop the dm_gpio_set_dir_flags() calls in the activate/deactivate
> functions, and use a value of 1 to mean "logically enabled".
>
> Ideally, I think we should also drop the GPIOD_ACTIVE_LOW from the
> request and make it up to the list of gpio cs in DT to indicate
> whether that CS is enabled when driven low (as is of course usually
> the case), but that requires changing
> arch/powerpc/dts/gdsys/gazerbeam-base.dtsi among others, and I don't
> have that hardware to test on. I have, however, tested our
> own (mpc8309-based) hardware with this change, and I have also tested
> that removing the GPIOD_ACTIVE_LOW from the request and updating our
> DT as
>
> - gpios = < 0 0>;
> + gpios = < 0 GPIO_ACTIVE_LOW>;
>
> still works.
>
> Signed-off-by: Rasmus Villemoes
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH v2] configs: powerpc: Don't set CONFIG_ENV_ADDR for QorIQ SPIFLASH
On Mon, Sep 07, 2020 at 10:37:35AM +1200, Chris Packham wrote: > Setting CONFIG_ENV_ADDR to something other than 0 stops gd->env_addr > from being allocated dynamically. When the environment is in SPI we need > it to be allocated as we can't use a direct memory mapped address. > > Signed-off-by: Chris Packham Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] disk: typo Terra Bytes
On Thu, Sep 17, 2020 at 05:57:21PM +0200, Heinrich Schuchardt wrote: > 512 * 2^32 bytes equals 2 tebibytes. > > Signed-off-by: Heinrich Schuchardt > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] examples: make examples customizable
On Tue, Sep 22, 2020 at 08:49:20PM +0200, Heinrich Schuchardt wrote: > On 9/22/20 8:42 PM, Tom Rini wrote: > > On Tue, Sep 22, 2020 at 08:03:49PM +0200, Heinrich Schuchardt wrote: > > > >> Most users don't need the standalone API examples. Distributions like Suse > >> do not supply libgcc for cross-compiling and we cannot do without on ARMv8 > >> for building examples/. > >> > >> Make examples customizable via symbol CONFIG_EXAMPLES. It only defaults to > >> yes to ensure that we compile it on Gitlab CI. > > > > In this case we should not make it "default y" but instead enable it in > > some specific cases that go through CI. Probably once per arch/ > > directory on the QEMU / virtual target for that arch. > > default y if ARCH_QEMU would compile it OK, lets do that in v2 please. > >> Cc: Matthias Brugger > >> Signed-off-by: Heinrich Schuchardt > >> --- > >> I wonder if we should not completely drop the standalone API. The UEFI API > >> has enough to run a standalone application. > > > > I'm certainly in favor of NOT adding support there for new > > architectures. I don't believe however we can drop it for existing > > architectures without some fairly large notice, and only then when UEFI > > is available as a reasonable replacement (ARM? Yes. MIPS? No idea). > > > > UEFI is low endian only. Right, so we can't just remove the standalone API but we can encourage new architectures to see if UEFI is right for them. -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/2] log: allow for message continuation
On 9/22/20 8:48 PM, Simon Glass wrote:
> Hi Heinrich,
>
> On Thu, 17 Sep 2020 at 06:19, Heinrich Schuchardt wrote:
>>
>> Some drivers use macro pr_cont() for continuing a message sent via printk.
>> Hence if we want to convert printk messaging to using the logging system,
>> we must support continuation of log messages too.
>>
>> As pr_cont() does not provide a message level we need a means of
>> remembering the last log level.
>>
>> With the patch a pseudo log level LOGL_CONT as well as a pseudo log
>> category LOGC_CONT are introduced. Using these results in the application
>> of the same log level and category as in the previous log message.
>>
>> Signed-off-by: Heinrich Schuchardt
>> ---
>> common/log.c| 23 ++-
>> doc/develop/logging.rst | 6 ++
>> include/log.h | 2 ++
>> 3 files changed, 26 insertions(+), 5 deletions(-)
>>
>> diff --git a/common/log.c b/common/log.c
>> index 9a5f100da3..bafc09f263 100644
>> --- a/common/log.c
>> +++ b/common/log.c
>> @@ -183,10 +183,12 @@ static bool log_passes_filters(struct log_device
>> *ldev, struct log_rec *rec)
>> * log_dispatch() - Send a log record to all log devices for processing
>> *
>> * The log record is sent to each log device in turn, skipping those which
>> have
>> - * filters which block the record
>> + * filters which block the record.
>> *
>> - * @rec: Log record to dispatch
>> - * @return 0 (meaning success)
>> + * All log messages created while processing log record @rec are ignored.
>> + *
>> + * @rec: log record to dispatch
>> + * Return: 0 msg sent, 1 msg not sent while already dispatching another
>> msg
>> */
>> static int log_dispatch(struct log_rec *rec)
>> {
>> @@ -199,7 +201,7 @@ static int log_dispatch(struct log_rec *rec)
>> * as this might result in infinite recursion.
>> */
>> if (processing_msg)
>> - return 0;
>> + return 1;
>>
>> /* Emit message */
>> processing_msg = 1;
>> @@ -214,10 +216,18 @@ static int log_dispatch(struct log_rec *rec)
>> int _log(enum log_category_t cat, enum log_level_t level, const char *file,
>> int line, const char *func, const char *fmt, ...)
>> {
>> + static enum log_category_t logc_prev = LOGC_NONE;
>> + static enum log_level_t logl_prev = LOGL_INFO;
>
> I don't think we can use static variables in logging. Perhaps we can
> use gobal_data?
Are you worried about relocation?
The initialization of the global data fields should be done in
log_init() before gd->flags |= GD_FLG_LOG_READY; I assume.
Is the rest ok for you?
Best regards
Heinrich
>
>
>> char buf[CONFIG_SYS_CBSIZE];
>> struct log_rec rec;
>> va_list args;
>>
>> + /* Check for message continuation */
>> + if (cat == LOGC_CONT)
>
> Regards,
> Simon
>
Re: [PATCH 1/3] global_data.h: convert GD_FLG_* to enum
On 9/22/20 8:49 PM, Simon Glass wrote: > Hi Heinrich, > > On Sat, 19 Sep 2020 at 10:05, Heinrich Schuchardt wrote: >> >> Sphinx documentation is only available for enums not for #defines. >> Anyway it is better to keep related definitions in an enum. >> >> Signed-off-by: Heinrich Schuchardt >> --- >> include/asm-generic/global_data.h | 104 -- >> 1 file changed, 83 insertions(+), 21 deletions(-) >> > > Does this work with assembly files? > > Regards, > Simon > Hello Simon, I sent a v2 of the series that #ifdef excludes the enum. Best regards Heinrich
Re: [PATCH 2/3] global_data.h: add Sphinx documentation
On Sat, 19 Sep 2020 at 10:10, Heinrich Schuchardt wrote: > > Add the missing Sphinx documentation for struct global_data and > gd_board_type(). > > Signed-off-by: Heinrich Schuchardt > --- > include/asm-generic/global_data.h | 357 ++ > 1 file changed, 309 insertions(+), 48 deletions(-) Reviewed-by: Simon Glass
Re: [PATCH 3/3] doc: global data pointer
On Sat, 19 Sep 2020 at 10:10, Heinrich Schuchardt wrote: > > Add the description of the global data pointer to the generated HTML > documentation. > > Signed-off-by: Heinrich Schuchardt > --- > doc/develop/global_data.rst | 53 + > doc/develop/index.rst | 1 + > 2 files changed, 54 insertions(+) > create mode 100644 doc/develop/global_data.rst > Reviewed-by: Simon Glass
Re: [PATCH 2/2] test: log: test message continuation
On Thu, 17 Sep 2020 at 06:19, Heinrich Schuchardt wrote: > > Provide a unit test checking that a continuation message will use the same > log level and log category as the previous message. > > Signed-off-by: Heinrich Schuchardt > --- > test/log/Makefile| 4 +++- > test/log/cont_test.c | 52 > 2 files changed, 55 insertions(+), 1 deletion(-) > create mode 100644 test/log/cont_test.c Reviewed-by: Simon Glass
Re: [PATCH 2/4] treewide: configs: fold CONFIG_DEFAULT_CONSOLE
On Thu, 17 Sep 2020 at 00:52, Andre Heider wrote: > > In prepartion to remove CONFIG_DEFAULT_CONSOLE, fold the current users. > > Signed-off-by: Andre Heider > --- > include/configs/odroid.h| 7 +-- > include/configs/odroid_xu3.h| 6 +- > include/configs/s5p_goni.h | 8 +--- > include/configs/s5pc210_universal.h | 7 +-- > include/configs/trats.h | 5 + > include/configs/trats2.h| 7 +-- > 6 files changed, 6 insertions(+), 34 deletions(-) > Reviewed-by: Simon Glass
Re: [PATCH 1/3] global_data.h: convert GD_FLG_* to enum
Hi Heinrich, On Sat, 19 Sep 2020 at 10:05, Heinrich Schuchardt wrote: > > Sphinx documentation is only available for enums not for #defines. > Anyway it is better to keep related definitions in an enum. > > Signed-off-by: Heinrich Schuchardt > --- > include/asm-generic/global_data.h | 104 -- > 1 file changed, 83 insertions(+), 21 deletions(-) > Does this work with assembly files? Regards, Simon
Re: [PATCH 3/4] Remove whitelist entry CONFIG_DEFAULT_CONSOLE
On Thu, 17 Sep 2020 at 00:52, Andre Heider wrote: > > There're no users left. > > Signed-off-by: Andre Heider > --- > scripts/config_whitelist.txt | 1 - > 1 file changed, 1 deletion(-) Reviewed-by: Simon Glass
Re: [PATCH 1/1] doc/arch/sandbox.rst: reformat command line options
On Sat, 19 Sep 2020 at 12:05, Heinrich Schuchardt wrote: > > Reformat the command line options chapter so that the command line options > clearly stand out. > > Signed-off-by: Heinrich Schuchardt > --- > doc/arch/sandbox.rst | 57 +--- > 1 file changed, 33 insertions(+), 24 deletions(-) > Reviewed-by: Simon Glass
Re: [PATCH 1/1] MAINTAINERS: assign doc/arch/sandbox.rst
On Sat, 19 Sep 2020 at 12:05, Heinrich Schuchardt wrote: > > Add doc/arch/sandbox.rst to the scope of SANDBOX. > > Signed-off-by: Heinrich Schuchardt > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Simon Glass
Re: [PATCH 1/2] log: allow for message continuation
Hi Heinrich,
On Thu, 17 Sep 2020 at 06:19, Heinrich Schuchardt wrote:
>
> Some drivers use macro pr_cont() for continuing a message sent via printk.
> Hence if we want to convert printk messaging to using the logging system,
> we must support continuation of log messages too.
>
> As pr_cont() does not provide a message level we need a means of
> remembering the last log level.
>
> With the patch a pseudo log level LOGL_CONT as well as a pseudo log
> category LOGC_CONT are introduced. Using these results in the application
> of the same log level and category as in the previous log message.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> common/log.c| 23 ++-
> doc/develop/logging.rst | 6 ++
> include/log.h | 2 ++
> 3 files changed, 26 insertions(+), 5 deletions(-)
>
> diff --git a/common/log.c b/common/log.c
> index 9a5f100da3..bafc09f263 100644
> --- a/common/log.c
> +++ b/common/log.c
> @@ -183,10 +183,12 @@ static bool log_passes_filters(struct log_device *ldev,
> struct log_rec *rec)
> * log_dispatch() - Send a log record to all log devices for processing
> *
> * The log record is sent to each log device in turn, skipping those which
> have
> - * filters which block the record
> + * filters which block the record.
> *
> - * @rec: Log record to dispatch
> - * @return 0 (meaning success)
> + * All log messages created while processing log record @rec are ignored.
> + *
> + * @rec: log record to dispatch
> + * Return: 0 msg sent, 1 msg not sent while already dispatching another
> msg
> */
> static int log_dispatch(struct log_rec *rec)
> {
> @@ -199,7 +201,7 @@ static int log_dispatch(struct log_rec *rec)
> * as this might result in infinite recursion.
> */
> if (processing_msg)
> - return 0;
> + return 1;
>
> /* Emit message */
> processing_msg = 1;
> @@ -214,10 +216,18 @@ static int log_dispatch(struct log_rec *rec)
> int _log(enum log_category_t cat, enum log_level_t level, const char *file,
> int line, const char *func, const char *fmt, ...)
> {
> + static enum log_category_t logc_prev = LOGC_NONE;
> + static enum log_level_t logl_prev = LOGL_INFO;
I don't think we can use static variables in logging. Perhaps we can
use gobal_data?
> char buf[CONFIG_SYS_CBSIZE];
> struct log_rec rec;
> va_list args;
>
> + /* Check for message continuation */
> + if (cat == LOGC_CONT)
Regards,
Simon
Re: [PATCH 4/4] configs: smdkv310: get rid of unused EXYNOS4_DEFAULT_UART_OFFSET
On Thu, 17 Sep 2020 at 00:52, Andre Heider wrote: > > Unused. > > Signed-off-by: Andre Heider > --- > include/configs/smdkv310.h | 3 --- > 1 file changed, 3 deletions(-) > Reviewed-by: Simon Glass
Re: [PATCH 1/4] treewide: configs: get rid of unused CONFIG_DEFAULT_CONSOLE
On Thu, 17 Sep 2020 at 00:52, Andre Heider wrote: > > These are all unused. > > Signed-off-by: Andre Heider > --- > This sets completely removes CONFIG_DEFAULT_CONSOLE from the tree. > Only compile time tested. > > include/configs/arndale.h | 2 -- > include/configs/espresso7420.h | 3 --- > include/configs/origen.h | 5 - > include/configs/peach-pi.h | 3 --- > include/configs/peach-pit.h| 3 --- > include/configs/smdk5250.h | 2 -- > include/configs/smdk5420.h | 5 - > include/configs/smdkv310.h | 2 -- > include/configs/snow.h | 2 -- > include/configs/spring.h | 2 -- > 10 files changed, 29 deletions(-) > Reviewed-by: Simon Glass
Re: [RFC PATCH] dm: add cells_count parameter in *_count_phandle_with_args
On Thu, 10 Sep 2020 at 10:44, Patrick Delaunay wrote: > > The cell_count argument is required when cells_name is NULL. > > This patch adds this parameter in live tree API > - of_count_phandle_with_args > - ofnode_count_phandle_with_args > - dev_count_phandle_with_args > > This parameter solves issue when these API is used to count > the number of element of a cell without cell name. This parameter > allow to force the size cell. > > For example: > count = dev_count_phandle_with_args(dev, "array", NULL, 3); > > Signed-off-by: Patrick Delaunay > --- > I push today this RFC. > > It is linked to previous serie [1] but it is not a blocking point today > as no user use this API with cells_name = NULL > + dev_count_phandle_with_args > + ofnode_count_phandle_with_args > > But I think it is the good time to modify these functions as they are not > hugely used: it is the proposition in this RFC. > > It is just a RFC because I don't sure if I can modify the existing API > even if parameters are aligned with *_parse_phandle_with_args. > > I can also to add new APIs to use when cells_name is NULL: > + dev_count_phandle_with_cell_count(node, list_name, cell_count); > + ofnode_count_phandle_with_cell_count(node, list_name, cell_count); > > and raise a error if cells_name == NULL in existing function > + dev_count_phandle_with_args > + ofnode_count_phandle_with_args > > [1] http://patchwork.ozlabs.org/project/uboot/list/?series=200899 > "dm: add cells_count parameter in live DT APIs of_parse_phandle_with_args" > > > board/st/stm32mp1/stm32mp1.c| 2 +- > drivers/clk/clk-uclass.c| 4 ++-- > drivers/core/of_access.c| 7 --- > drivers/core/ofnode.c | 6 +++--- > drivers/core/read.c | 5 +++-- > drivers/phy/phy-uclass.c| 2 +- > drivers/reset/reset-uclass.c| 2 +- > drivers/usb/host/ehci-generic.c | 4 ++-- > include/dm/of_access.h | 4 +++- > include/dm/ofnode.h | 3 ++- > include/dm/read.h | 8 +--- > 11 files changed, 27 insertions(+), 20 deletions(-)' Reviewed-by: Simon Glass A test would go a long way here.
Re: [PATCH 1/1] examples: make examples customizable
On 9/22/20 8:42 PM, Tom Rini wrote: > On Tue, Sep 22, 2020 at 08:03:49PM +0200, Heinrich Schuchardt wrote: > >> Most users don't need the standalone API examples. Distributions like Suse >> do not supply libgcc for cross-compiling and we cannot do without on ARMv8 >> for building examples/. >> >> Make examples customizable via symbol CONFIG_EXAMPLES. It only defaults to >> yes to ensure that we compile it on Gitlab CI. > > In this case we should not make it "default y" but instead enable it in > some specific cases that go through CI. Probably once per arch/ > directory on the QEMU / virtual target for that arch. default y if ARCH_QEMU would compile it > >> Cc: Matthias Brugger >> Signed-off-by: Heinrich Schuchardt >> --- >> I wonder if we should not completely drop the standalone API. The UEFI API >> has enough to run a standalone application. > > I'm certainly in favor of NOT adding support there for new > architectures. I don't believe however we can drop it for existing > architectures without some fairly large notice, and only then when UEFI > is available as a reasonable replacement (ARM? Yes. MIPS? No idea). > UEFI is low endian only. Best regards Heinrich
Re: [PATCH v2 1/3] global_data.h: convert GD_FLG_* to enum
On Sun, 20 Sep 2020 at 02:04, Heinrich Schuchardt wrote: > > Sphinx documentation is only available for enums not for #defines. > Anyway it is better to keep related definitions in an enum. > > Signed-off-by: Heinrich Schuchardt > --- > v2: > enum gd_flags must not be exposed to assembler code > --- > include/asm-generic/global_data.h | 106 +++--- > 1 file changed, 84 insertions(+), 22 deletions(-) Reviewed-by: Simon Glass
Re: Question: Chromebook Flip C100p Uboot build and flash
Hi Ning, On Mon, 14 Sep 2020 at 13:26, zhangn1...@outlook.com wrote: > > Hi, Simon > > I find a guide in mainline uboot code, which updated by you. > This guide is for chromebook_jerry, can it apply to Flip C100p (minnie)? > > If it can apply to minnie, my understanding are: > Build u-boot-spl-dtb.bin and u-boot-dtb.img from mainline uboot, and > replace jerry binary in the command line. > Then flash it to minnie’s SPI flash with dediprog. > when reboot minnie, I will get uboot command line interface, and can > access it by uart port. > Then boot mainline linux kernel, from external storage. And finally > repartition emmc, and build a Linux OS to emmc. > > Are they right? Yes I think so. Regards, Simon
[PATCH v4 59/59] acpi: Use I2cSerialBusV2() instead of I2cSerialBus()
Use the correct name of the ACPI structure being created.
Signed-off-by: Simon Glass
---
Changes in v4:
- Add new patch to use I2cSerialBusV2() instead of I2cSerialBus()
include/acpi/acpi_device.h | 2 +-
lib/acpi/acpi_device.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h
index 007b7e7caf1..ed4acd912a1 100644
--- a/include/acpi/acpi_device.h
+++ b/include/acpi/acpi_device.h
@@ -413,7 +413,7 @@ int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx,
/**
* acpi_device_write_i2c_dev() - Write an I2C device to ACPI
*
- * This creates a I2cSerialBus descriptor for an I2C device, including
+ * This creates a I2cSerialBusV2 descriptor for an I2C device, including
* information ACPI needs to use it.
*
* @ctx: ACPI context pointer
diff --git a/lib/acpi/acpi_device.c b/lib/acpi/acpi_device.c
index 8248664a10a..95dfac583fc 100644
--- a/lib/acpi/acpi_device.c
+++ b/lib/acpi/acpi_device.c
@@ -530,7 +530,7 @@ int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx,
return 0;
}
-/* ACPI 6.3 section 6.4.3.8.2.1 - I2cSerialBus() */
+/* ACPI 6.3 section 6.4.3.8.2.1 - I2cSerialBusV2() */
static void acpi_device_write_i2c(struct acpi_ctx *ctx,
const struct acpi_i2c *i2c)
{
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 53/59] x86: fsp: Show FSP-S or FSP-M address in fsp_get_header()
At present this function only supports FSP-M but it is also used to read
FSP-S, in which case FSP-M may be zero. Add support for showing whichever
address is present in the FSP binary.
Also change the debug() statements to log_debug() while here.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v1)
arch/x86/lib/fsp2/fsp_support.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/x86/lib/fsp2/fsp_support.c b/arch/x86/lib/fsp2/fsp_support.c
index 3f2ca840dc9..f220ef498b0 100644
--- a/arch/x86/lib/fsp2/fsp_support.c
+++ b/arch/x86/lib/fsp2/fsp_support.c
@@ -35,7 +35,8 @@ int fsp_get_header(ulong offset, ulong size, bool
use_spi_flash,
*
* You are in a maze of twisty little headers all alike.
*/
- debug("offset=%x buf=%x\n", (uint)offset, (uint)buf);
+ log_debug("offset=%x buf=%x, use_spi_flash=%d\n", (uint)offset,
+ (uint)buf, use_spi_flash);
if (use_spi_flash) {
ret = uclass_first_device_err(UCLASS_SPI_FLASH, );
if (ret)
@@ -52,16 +53,16 @@ int fsp_get_header(ulong offset, ulong size, bool
use_spi_flash,
fv = ptr;
/* Check the FV signature, _FVH */
- debug("offset=%x sign=%x\n", (uint)offset, (uint)fv->sign);
+ log_debug("offset=%x sign=%x\n", (uint)offset, (uint)fv->sign);
if (fv->sign != EFI_FVH_SIGNATURE)
return log_msg_ret("Base FV signature", -EINVAL);
/* Go to the end of the FV header and align the address */
- debug("fv->ext_hdr_off = %x\n", fv->ext_hdr_off);
+ log_debug("fv->ext_hdr_off = %x\n", fv->ext_hdr_off);
ptr += fv->ext_hdr_off;
exhdr = ptr;
ptr += ALIGN(exhdr->ext_hdr_size, 8);
- debug("ptr=%x\n", ptr - (void *)buf);
+ log_debug("ptr=%x\n", ptr - (void *)buf);
/* Check the FFS GUID */
file_hdr = ptr;
@@ -71,7 +72,7 @@ int fsp_get_header(ulong offset, ulong size, bool
use_spi_flash,
ptr = file_hdr + 1;
raw = ptr;
- debug("raw->type = %x\n", raw->type);
+ log_debug("raw->type = %x\n", raw->type);
if (raw->type != EFI_SECTION_RAW)
return log_msg_ret("Section type not RAW", -ENOEXEC);
@@ -80,13 +81,18 @@ int fsp_get_header(ulong offset, ulong size, bool
use_spi_flash,
fsp = ptr;
/* Check the FSPH header */
- debug("fsp %x\n", (uint)fsp);
+ log_debug("fsp %x, fsp-buf=%x, si=%x\n", (uint)fsp, ptr - (void *)buf,
+ (void *)>fsp_silicon_init - (void *)buf);
if (fsp->sign != EFI_FSPH_SIGNATURE)
return log_msg_ret("Base FSPH signature", -EACCES);
base = (void *)fsp->img_base;
- debug("Image base %x\n", (uint)base);
- debug("Image addr %x\n", (uint)fsp->fsp_mem_init);
+ log_debug("image base %x\n", (uint)base);
+ if (fsp->fsp_mem_init)
+ log_debug("mem_init offset %x\n", (uint)fsp->fsp_mem_init);
+ else if (fsp->fsp_silicon_init)
+ log_debug("silicon_init offset %x\n",
+ (uint)fsp->fsp_silicon_init);
if (use_spi_flash) {
ret = spi_flash_read_dm(dev, offset, size, base);
if (ret)
--
2.28.0.681.g6f77f65b4e-goog
Re: [PATCH 1/1] examples: make examples customizable
Hi Heinrich, On Tue, 22 Sep 2020 at 12:04, Heinrich Schuchardt wrote: > > Most users don't need the standalone API examples. Distributions like Suse > do not supply libgcc for cross-compiling and we cannot do without on ARMv8 > for building examples/. > > Make examples customizable via symbol CONFIG_EXAMPLES. It only defaults to > yes to ensure that we compile it on Gitlab CI. > > Cc: Matthias Brugger > Signed-off-by: Heinrich Schuchardt > --- > I wonder if we should not completely drop the standalone API. The UEFI API > has enough to run a standalone application. I am not sure. I don't like UEFI at all and it doesn't expose U-Boot devices, etc. Reviewed-by: Simon Glass
[PATCH v4 58/59] acpi: Add more documentation for struct acpi_gpio
Add some documentation provided by Andy Shevchenko to describe how to
use struct acpi_gpio.
Signed-off-by: Simon Glass
---
Changes in v4:
- Add Andy's documentation to struct acpi_gpio
include/acpi/acpi_device.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h
index 1b838fcb857..007b7e7caf1 100644
--- a/include/acpi/acpi_device.h
+++ b/include/acpi/acpi_device.h
@@ -170,6 +170,28 @@ enum acpi_gpio_polarity {
* @io_shared; true if GPIO is shared
* @io_restrict: I/O restriction setting
* @polarity: GPIO polarity
+ *
+ * Note that GpioIo doesn't have any means of Active Low / High setting, so a
+ * _DSD must be provided to mitigate this.
+ *
+ * GpioIo doesn't properly communicate the initial state of the output pin,
+ * thus Linux assumes the simple rule:
+ *
+ * Pull Bias Polarity Requested...
+ *
+ * Implicitx AS IS (assumed firmware configured for us)
+ * Explicitx (no _DSD) as Pull Bias (Up == High, Down == Low),
+ * assuming non-active (Polarity = !Pull Bias)
+ *
+ * DownLow as low, assuming active
+ * DownHigh as high, assuming non-active
+ * Up Low as high, assuming non-active
+ * Up High as high, assuming active
+ *
+ * GpioIo() can be used as interrupt and in this case the IoRestriction mustn't
+ * be OutputOnly. It also requires active_low flag from _DSD in cases where
it's
+ * needed (better to always provide than rely on above assumption made on OS
+ * level).
*/
struct acpi_gpio {
int pin_count;
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 57/59] x86: coral: Update config and device tree for ACPI
Enable new features and provide require device-tree config so that U-Boot
produces the correct ACPI tables on Coral.
Signed-off-by: Simon Glass
---
Changes in v4:
- Correct DPTF enable property
- Correct compatible string for gma device
Changes in v3:
- Rebase to master
Changes in v2:
- Rebase to master
Changes in v1:
- Add NHLT information
- Fix i2c PCI addresses
- Rename acpi-probed to linux,probed
- Rename cpi,hid-desc-reg-offset to hid-desc-addr
- UIse hid-over-i2 compatible string
- Update ACPI ordering to include multiple CPUs
- Use acpi,ddn instead of acpi,desc
arch/x86/dts/chromebook_coral.dts | 226 +++--
configs/chromebook_coral_defconfig | 11 +-
2 files changed, 221 insertions(+), 16 deletions(-)
diff --git a/arch/x86/dts/chromebook_coral.dts
b/arch/x86/dts/chromebook_coral.dts
index a17a9c28003..893a59b1620 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -15,14 +15,20 @@
#include "flashmap-16mb-rw.dtsi"
#endif
+#include
+#include
+#include
+#include
#include
#include
+#include
#include
#include
#include
#include
#include
#include
+#include
/ {
model = "Google Coral";
@@ -40,6 +46,14 @@
i2c5 = _5;
i2c6 = _6;
i2c7 = _7;
+ mmc1 =
+ };
+
+ board: board {
+ compatible = "google,coral";
+ recovery-gpios = <_nw (-1) GPIO_ACTIVE_LOW>;
+ write-protect-gpios = <_nw GPIO_75 GPIO_ACTIVE_HIGH>;
+ phase-enforce-gpios = <_n GPIO_10 GPIO_ACTIVE_HIGH>;
};
config {
@@ -48,6 +62,15 @@
chosen {
stdout-path =
+ e820-entries = /bits/ 64 <
+ IOMAP_P2SB_BAR IOMAP_P2SB_SIZE E820_RESERVED
+ MCH_BASE_ADDRESS MCH_SIZE E820_RESERVED>;
+ u-boot,acpi-ssdt-order = <_0 _1 _2 _3
+ _0 _1 _2 _3 _4 _5
+_codec _codec
+ _touchscreen _touchscreen
+ _touchpad _touchpad _digitizer>;
+ u-boot,acpi-dsdt-order = < >;
};
clk: clock {
@@ -60,7 +83,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu_0: cpu@0 {
u-boot,dm-pre-reloc;
device_type = "cpu";
compatible = "intel,apl-cpu";
@@ -68,21 +91,21 @@
intel,apic-id = <0>;
};
- cpu@1 {
+ cpu_1: cpu@1 {
device_type = "cpu";
compatible = "intel,apl-cpu";
reg = <1>;
intel,apic-id = <2>;
};
- cpu@2 {
+ cpu_2: cpu@2 {
device_type = "cpu";
compatible = "intel,apl-cpu";
reg = <2>;
intel,apic-id = <4>;
};
- cpu@3 {
+ cpu_3: cpu@3 {
device_type = "cpu";
compatible = "intel,apl-cpu";
reg = <3>;
@@ -128,6 +151,10 @@
*/
fsp_s: fsp-s {
};
+
+ nhlt {
+ intel,dmic-channels = <4>;
+ };
};
punit@0,1 {
@@ -136,21 +163,29 @@
compatible = "intel,apl-punit";
};
+ gma@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ compatible = "fsp-fb";
+ };
+
p2sb: p2sb@d,0 {
u-boot,dm-pre-reloc;
reg = <0x02006810 0 0 0 0>;
compatible = "intel,p2sb";
early-regs = ;
+ pci,no-autoconfig;
n {
compatible = "intel,apl-pinctrl";
u-boot,dm-pre-reloc;
intel,p2sb-port-id = ;
+ acpi,path = "\\_SB.GPO0";
gpio_n: gpio-n {
compatible = "intel,gpio";
u-boot,dm-pre-reloc;
gpio-controller;
#gpio-cells = <2>;
+ linux-name = "INT3452:00";
};
};
@@ -159,11 +194,13 @@
compatible = "intel,apl-pinctrl";
intel,p2sb-port-id = ;
#gpio-cells = <2>;
+
[PATCH v4 54/59] acpi: Use defines for field lengths
A few fields have an open-coded length. Use the defines for this purpose
instead.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v1)
include/acpi/acpi_table.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index 9fba6536f50..3a243bf19ce 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -13,6 +13,7 @@
#ifndef __ACPI_TABLE_H__
#define __ACPI_TABLE_H__
+#include
#include
#define RSDP_SIG "RSD PTR " /* RSDP pointer signature */
@@ -48,7 +49,7 @@ struct acpi_rsdp {
/* Generic ACPI header, provided by (almost) all tables */
struct __packed acpi_table_header {
- char signature[4]; /* ACPI signature (4 ASCII characters) */
+ char signature[ACPI_NAME_LEN]; /* ACPI signature (4 ASCII chars) */
u32 length; /* Table length in bytes (incl. header) */
u8 revision;/* Table version (not ACPI version!) */
volatile u8 checksum; /* To make sum of entire table == 0 */
@@ -263,7 +264,7 @@ struct __packed acpi_fadt {
/* FACS (Firmware ACPI Control Structure) */
struct acpi_facs {
- char signature[4]; /* "FACS" */
+ char signature[ACPI_NAME_LEN]; /* "FACS" */
u32 length; /* Length in bytes (>= 64) */
u32 hardware_signature; /* Hardware signature */
u32 firmware_waking_vector; /* Firmware waking vector */
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 55/59] x86: Add a way to add to the e820 memory table
Some boards want to reserve extra regions of memory. Add a 'chosen'
property to support this.
Reviewed-by: Bin Meng
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/lib/fsp/fsp_dram.c | 17 +
doc/device-tree-bindings/chosen.txt | 18 ++
2 files changed, 35 insertions(+)
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index faa819fab4b..a76497d4e01 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -92,6 +93,8 @@ unsigned int install_e820_map(unsigned int max_entries,
unsigned int num_entries = 0;
const struct hob_header *hdr;
struct hob_res_desc *res_desc;
+ const fdt64_t *prop;
+ int size;
hdr = gd->arch.hob_list;
@@ -133,6 +136,20 @@ unsigned int install_e820_map(unsigned int max_entries,
num_entries++;
}
+ prop = ofnode_read_chosen_prop("e820-entries", );
+ if (prop) {
+ int count = size / (sizeof(u64) * 3);
+ int i;
+
+ if (num_entries + count >= max_entries)
+ return -ENOSPC;
+ for (i = 0; i < count; i++, num_entries++, prop += 3) {
+ entries[num_entries].addr = fdt64_to_cpu(prop[0]);
+ entries[num_entries].size = fdt64_to_cpu(prop[1]);
+ entries[num_entries].type = fdt64_to_cpu(prop[2]);
+ }
+ }
+
return num_entries;
}
diff --git a/doc/device-tree-bindings/chosen.txt
b/doc/device-tree-bindings/chosen.txt
index d4dfc05847b..e5ba6720ce1 100644
--- a/doc/device-tree-bindings/chosen.txt
+++ b/doc/device-tree-bindings/chosen.txt
@@ -143,3 +143,21 @@ This provides the ordering to use when writing device data
to the ACPI SSDT
node to add. The ACPI information is written in this order.
If the ordering does not include all nodes, an error is generated.
+
+e820-entries
+
+
+This provides a way to add entries to the e820 table which tells the OS about
+the memory map. The property contains three sets of 64-bit values:
+
+ address - Start address of region
+ size - Size of region
+ flags - Flags (E820_...)
+
+Example:
+
+chosen {
+ e820-entries = /bits/ 64 <
+ IOMAP_P2SB_BAR IOMAP P2SB_SIZE E820_RESERVED
+ MCH_BASE_ADDRESS MCH_SIZE E820_RESERVED>;
+};
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 56/59] x86: Move include of bitops out of ACPI region
At present linux/bitops.h is included in ACPI code. This is not needed and can cause a problem in fls64.h since BITS_PER_LONG is not defined. Move the #include into the part not used by ACPI. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Add new patch to move include of bitops out of ACPI region include/acpi/acpi_table.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index 3a243bf19ce..abbca6530db 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -14,7 +14,6 @@ #define __ACPI_TABLE_H__ #include -#include #define RSDP_SIG "RSD PTR " /* RSDP pointer signature */ #define OEM_ID "U-BOOT"/* U-Boot */ @@ -29,6 +28,8 @@ #if !defined(__ACPI__) +#include + struct acpi_ctx; /* -- 2.28.0.681.g6f77f65b4e-goog
[PATCH v4 49/59] x86: acpi: Set the log category for x86 table generation
This file doesn't currently have a log category. Add one so that items are logged correctly. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) arch/x86/lib/acpi_table.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 10cf3b70945..6d405b09fde 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -6,6 +6,8 @@ * Copyright (C) 2016, Bin Meng */ +#define LOG_CATEGORY LOGC_ACPI + #include #include #include -- 2.28.0.681.g6f77f65b4e-goog
[PATCH v4 52/59] x86: fsp: Add more debugging for silicon init
If locating the FSP header hangs for whatever reason it is useful to see
where it got stuck. Add a debug print. Also show the address of the FSP-S
entry point as a sanity check.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v1)
arch/x86/lib/fsp2/fsp_silicon_init.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/lib/fsp2/fsp_silicon_init.c
b/arch/x86/lib/fsp2/fsp_silicon_init.c
index 0f221a864fb..ead3493de82 100644
--- a/arch/x86/lib/fsp2/fsp_silicon_init.c
+++ b/arch/x86/lib/fsp2/fsp_silicon_init.c
@@ -26,8 +26,10 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash)
struct binman_entry entry;
struct udevice *dev;
ulong rom_offset = 0;
+ u32 init_addr;
int ret;
+ log_debug("Locating FSP\n");
ret = fsp_locate_fsp(FSP_S, , use_spi_flash, , ,
_offset);
if (ret)
@@ -44,7 +46,7 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash)
ret = fsps_update_config(dev, rom_offset, );
if (ret)
return log_msg_ret("Could not setup config", ret);
- log_debug("Silicon init...");
+ log_debug("Silicon init @ %x...", init_addr);
bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_S, "fsp-s");
func = (fsp_silicon_init_func)(hdr->img_base + hdr->fsp_silicon_init);
ret = func();
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 51/59] x86: apl: Check low-level init in FSP-S pre-init
If U-Boot is not running FSP-S it should not do the pre-init either. Add a
condition to handle this.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/cpu/apollolake/fsp_s.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index e54b0ac1047..715ceab6ac7 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -157,6 +157,8 @@ int arch_fsps_preinit(void)
struct udevice *itss;
int ret;
+ if (!ll_boot_init())
+ return 0;
ret = irq_first_device_type(X86_IRQT_ITSS, );
if (ret)
return log_msg_ret("no itss", ret);
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 50/59] x86: coral: Add audio descriptor files
Add files describing the various audio configurations supported on coral.
These are passed to Linux in the ACPI tables.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Add new patch with coral audio descriptor files
.../chromebook_coral/dialog-2ch-48khz-24b.dat| Bin 0 -> 100 bytes
.../chromebook_coral/dmic-1ch-48khz-16b.dat | Bin 0 -> 3048 bytes
.../chromebook_coral/dmic-2ch-48khz-16b.dat | Bin 0 -> 3048 bytes
.../chromebook_coral/dmic-4ch-48khz-16b.dat | Bin 0 -> 3048 bytes
.../max98357-render-2ch-48khz-24b.dat| Bin 0 -> 116 bytes
5 files changed, 0 insertions(+), 0 deletions(-)
create mode 100644 board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
create mode 100644 board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
create mode 100644 board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
create mode 100644 board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
create mode 100644
board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
diff --git a/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
b/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
new file mode 100644
index
..46c0efbd0adc0883564cf8404503fa1de7c4cc33
GIT binary patch
literal 100
zcmZQzU|?WnWOx?=qy_%}|8E4u0zd*AHfO)k$iPr=0H_oQW->7YNf2go01_a;&(5v@
Oq?n-iKR*Kl2m=7w%Nqy)
literal 0
HcmV?d1
diff --git a/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
b/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
new file mode 100644
index
..6a7f2cef4efea7707f4b2c57f8278962a53ca7c6
GIT binary patch
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literal 0
HcmV?d1
diff --git a/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
b/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
new file mode 100644
index
..71d7648202154b6e8116dcf99cb7336f92731ac9
GIT binary patch
literal 3048
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literal 0
HcmV?d1
diff --git a/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
b/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
new file mode 100644
index
..142ab353f3736f110f30e9befbd72f7e8ae4264b
GIT binary patch
literal 3048
zcmeH{?Q7O$6vw~6dv`V;cAq_zX!*jirU{F1M)RR%C94#}biJ`c>xHeMrWsrHW~B)h
z)rSg%;;f7Sg5UX6m5l?v!=dBlH)mel!P0(0>3P$482}`6!e}?vEL-%lh;X~wogY;}?=)Si@8x}~}Mv~^tU`yyh{B^fVOUkA1
z*OJp)p;6CBpKOrEbc9~64}Cx!R~<$RVy>tT-M*Fhx};5v)cVl8!q82XXgeuU%e~Td
zr!pF@3QhV{di<_L$)V6YPiM69vCzBA5Or;$<_AJgo-5Lui$kNk6V>0GQVn_Tsx8vK
z6-7FYpPJSJ?d?sgvm~vKr77J#AZ6xCvkE0b0Ucswe20z=j4U;5rbay%L%q~z7rHi}
z|0;AJOKrBE2`%6|2YnW^Hy69-IoAds?^D+o@tb7~^M5~UL+s_SIZT}c`#MGwervho
z7-=lTZu4lQB#0e+r!vnG@>ggI_x5mKCoz<;HV(Ej*saS*-@rp7T-?FgMXcY7
z-^s*x=6CpE)SiY(?%TrNfg%_l51ZFW%SrlS+h%oALWbU+57SD*Z9^+%KVzxNj<~
ze0#OjULhTwCT*M|y$(-1VYLgM%8#M>7jX7jsP9N<5BJR^@9ETV_Z)2M&;y+hakd>+
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n_n-Ta5Jvja{YeP<_ub5)SN?s^zwi0?Jw5W?=im4L$NT;dsY=};
literal 0
HcmV?d1
diff --git a/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
b/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
new file
[PATCH v4 48/59] acpi: tpm: Add a TPM1 table
This provides information about a v1 TPM in the system. Generate this
table if the TPM is present.
Add a required new bloblist type and correct the header order of one
header file.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/lib/acpi_table.c | 54 ++-
include/acpi/acpi_table.h | 7 +
include/bloblist.h| 1 +
3 files changed, 61 insertions(+), 1 deletion(-)
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index c31cc923c9c..10cf3b70945 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -215,6 +215,47 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
header->checksum = table_compute_checksum((void *)mcfg, header->length);
}
+/**
+ * acpi_create_tcpa() - Create a TCPA table
+ *
+ * @tcpa: Pointer to place to put table
+ *
+ * Trusted Computing Platform Alliance Capabilities Table
+ * TCPA PC Specific Implementation SpecificationTCPA is defined in the PCI
+ * Firmware Specification 3.0
+ */
+static int acpi_create_tcpa(struct acpi_tcpa *tcpa)
+{
+ struct acpi_table_header *header = >header;
+ u32 current = (u32)tcpa + sizeof(struct acpi_tcpa);
+ int size = 0x1; /* Use this as the default size */
+ void *log;
+ int ret;
+
+ if (!CONFIG_IS_ENABLED(BLOBLIST))
+ return -ENXIO;
+ memset(tcpa, '\0', sizeof(struct acpi_tcpa));
+
+ /* Fill out header fields */
+ acpi_fill_header(header, "TCPA");
+ header->length = sizeof(struct acpi_tcpa);
+ header->revision = 1;
+
+ ret = bloblist_ensure_size_ret(BLOBLISTT_TCPA_LOG, , );
+ if (ret)
+ return log_msg_ret("blob", ret);
+
+ tcpa->platform_class = 0;
+ tcpa->laml = size;
+ tcpa->lasa = (ulong)log;
+
+ /* (Re)calculate length and checksum */
+ header->length = current - (u32)tcpa;
+ header->checksum = table_compute_checksum((void *)tcpa, header->length);
+
+ return 0;
+}
+
static int get_tpm2_log(void **ptrp, int *sizep)
{
const int tpm2_default_log_len = 0x1;
@@ -457,11 +498,13 @@ ulong write_acpi_tables(ulong start_addr)
struct acpi_fadt *fadt;
struct acpi_table_header *ssdt;
struct acpi_mcfg *mcfg;
+ struct acpi_tcpa *tcpa;
struct acpi_madt *madt;
struct acpi_csrt *csrt;
struct acpi_spcr *spcr;
void *start;
ulong addr;
+ int ret;
int i;
start = map_sysmem(start_addr, 0);
@@ -560,7 +603,6 @@ ulong write_acpi_tables(ulong start_addr)
if (IS_ENABLED(CONFIG_TPM_V2)) {
struct acpi_tpm2 *tpm2;
- int ret;
debug("ACPI:* TPM2\n");
tpm2 = (struct acpi_tpm2 *)ctx->current;
@@ -579,6 +621,16 @@ ulong write_acpi_tables(ulong start_addr)
acpi_inc_align(ctx, madt->header.length);
acpi_add_table(ctx, madt);
+ debug("ACPI:* TCPA\n");
+ tcpa = (struct acpi_tcpa *)ctx->current;
+ ret = acpi_create_tcpa(tcpa);
+ if (ret) {
+ log_warning("Failed to create TCPA table (err=%d)\n", ret);
+ } else {
+ acpi_inc_align(ctx, tcpa->header.length);
+ acpi_add_table(ctx, tcpa);
+ }
+
debug("ACPI:* CSRT\n");
csrt = ctx->current;
if (!acpi_create_csrt(csrt)) {
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index c7ee8b55da4..9fba6536f50 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -104,6 +104,13 @@ struct __packed acpi_tpm2 {
u64 lasa;
};
+struct __packed acpi_tcpa {
+ struct acpi_table_header header;
+ u16 platform_class;
+ u32 laml;
+ u64 lasa;
+};
+
/* FADT Preferred Power Management Profile */
enum acpi_pm_profile {
ACPI_PM_UNSPECIFIED = 0,
diff --git a/include/bloblist.h b/include/bloblist.h
index dc7d80bd851..5784c2226e7 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -34,6 +34,7 @@ enum bloblist_tag_t {
BLOBLISTT_ACPI_GNVS,
BLOBLISTT_INTEL_VBT,/* Intel Video-BIOS table */
BLOBLISTT_TPM2_TCG_LOG, /* TPM v2 log space */
+ BLOBLISTT_TCPA_LOG, /* TPM log space */
};
/**
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 47/59] acpi: tpm: Add a TPM2 table
This provides information about a v2 TPM in the system. Generate this
table if the TPM is present.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/lib/acpi_table.c | 74 +++
include/acpi/acpi_table.h | 11 ++
include/bloblist.h| 1 +
3 files changed, 86 insertions(+)
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 5876355afe2..c31cc923c9c 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -7,6 +7,7 @@
*/
#include
+#include
#include
#include
#include
@@ -214,6 +215,64 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
header->checksum = table_compute_checksum((void *)mcfg, header->length);
}
+static int get_tpm2_log(void **ptrp, int *sizep)
+{
+ const int tpm2_default_log_len = 0x1;
+ int size;
+ int ret;
+
+ *sizep = 0;
+ size = tpm2_default_log_len;
+ ret = bloblist_ensure_size_ret(BLOBLISTT_TPM2_TCG_LOG, , ptrp);
+ if (ret)
+ return log_msg_ret("blob", ret);
+ *sizep = size;
+
+ return 0;
+}
+
+static int acpi_create_tpm2(struct acpi_tpm2 *tpm2)
+{
+ struct acpi_table_header *header = >header;
+ int tpm2_log_len;
+ void *lasa;
+ int ret;
+
+ memset((void *)tpm2, 0, sizeof(struct acpi_tpm2));
+
+ /*
+* Some payloads like SeaBIOS depend on log area to use TPM2.
+* Get the memory size and address of TPM2 log area or initialize it.
+*/
+ ret = get_tpm2_log(, _log_len);
+ if (ret)
+ return ret;
+
+ /* Fill out header fields. */
+ acpi_fill_header(header, "TPM2");
+ memcpy(header->aslc_id, ASLC_ID, 4);
+
+ header->length = sizeof(struct acpi_tpm2);
+ header->revision = acpi_get_table_revision(ACPITAB_TPM2);
+
+ /* Hard to detect for coreboot. Just set it to 0 */
+ tpm2->platform_class = 0;
+
+ /* Must be set to 0 for FIFO-interface support */
+ tpm2->control_area = 0;
+ tpm2->start_method = 6;
+ memset(tpm2->msp, 0, sizeof(tpm2->msp));
+
+ /* Fill the log area size and start address fields. */
+ tpm2->laml = tpm2_log_len;
+ tpm2->lasa = (uintptr_t)lasa;
+
+ /* Calculate checksum. */
+ header->checksum = table_compute_checksum((void *)tpm2, header->length);
+
+ return 0;
+}
+
__weak u32 acpi_fill_csrt(u32 current)
{
return 0;
@@ -499,6 +558,21 @@ ulong write_acpi_tables(ulong start_addr)
acpi_inc_align(ctx, mcfg->header.length);
acpi_add_table(ctx, mcfg);
+ if (IS_ENABLED(CONFIG_TPM_V2)) {
+ struct acpi_tpm2 *tpm2;
+ int ret;
+
+ debug("ACPI:* TPM2\n");
+ tpm2 = (struct acpi_tpm2 *)ctx->current;
+ ret = acpi_create_tpm2(tpm2);
+ if (!ret) {
+ acpi_inc_align(ctx, tpm2->header.length);
+ acpi_add_table(ctx, tpm2);
+ } else {
+ log_warning("TPM2 table creation failed\n");
+ }
+ }
+
debug("ACPI:* MADT\n");
madt = ctx->current;
acpi_create_madt(madt);
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index a2e510cf56e..c7ee8b55da4 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -93,6 +93,17 @@ struct __packed acpi_hpet {
u8 attributes;
};
+struct __packed acpi_tpm2 {
+ struct acpi_table_header header;
+ u16 platform_class;
+ u8 reserved[2];
+ u64 control_area;
+ u32 start_method;
+ u8 msp[12];
+ u32 laml;
+ u64 lasa;
+};
+
/* FADT Preferred Power Management Profile */
enum acpi_pm_profile {
ACPI_PM_UNSPECIFIED = 0,
diff --git a/include/bloblist.h b/include/bloblist.h
index 7d8480548e0..dc7d80bd851 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -33,6 +33,7 @@ enum bloblist_tag_t {
*/
BLOBLISTT_ACPI_GNVS,
BLOBLISTT_INTEL_VBT,/* Intel Video-BIOS table */
+ BLOBLISTT_TPM2_TCG_LOG, /* TPM v2 log space */
};
/**
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 46/59] x86: Correct handling of MADT table CPUs
At present if hyperthreading is disabled the CPU numbering is not
sequential. Fix this.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/lib/acpi_table.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 86a9a35cb25..5876355afe2 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -66,14 +66,17 @@ int acpi_create_madt_lapics(u32 current)
{
struct udevice *dev;
int total_length = 0;
+ int cpu_num = 0;
for (uclass_find_first_device(UCLASS_CPU, );
dev;
uclass_find_next_device()) {
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
- int length = acpi_create_madt_lapic(
- (struct acpi_madt_lapic *)current,
- plat->cpu_id, plat->cpu_id);
+ int length;
+
+ length = acpi_create_madt_lapic(
+ (struct acpi_madt_lapic *)current, cpu_num++,
+ plat->cpu_id);
current += length;
total_length += length;
}
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 45/59] x86: Add a header guard to asm/acpi_table.h
This file cannot currently be included in ASL files. Add a header guard to permit this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) arch/x86/include/asm/acpi_table.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index faf31730730..1b49ccadc0c 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -9,6 +9,8 @@ #ifndef __ASM_ACPI_TABLE_H__ #define __ASM_ACPI_TABLE_H__ +#ifndef __ACPI__ + struct acpi_facs; struct acpi_fadt; struct acpi_global_nvs; @@ -213,4 +215,6 @@ void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs, */ void intel_acpi_fill_fadt(struct acpi_fadt *fadt); +#endif /* !__ACPI__ */ + #endif /* __ASM_ACPI_TABLE_H__ */ -- 2.28.0.681.g6f77f65b4e-goog
[PATCH v4 43/59] x86: Notify the FSP of the 'end firmware' event
Send this notification when U-Boot is about to boot into Linux, as
requested by the FSP.
Currently this causes a crash with the APL FSP, so leave it disabled for
now.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/cpu/cpu.c| 15 +++
arch/x86/lib/fsp/fsp_common.c | 16
2 files changed, 31 insertions(+)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 69c14189d1f..f8692753963 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -189,6 +189,14 @@ __weak void board_final_init(void)
{
}
+/*
+ * Implement a weak default function for boards that need to do some final
+ * processing before booting the OS.
+ */
+__weak void board_final_cleanup(void)
+{
+}
+
int last_stage_init(void)
{
struct acpi_fadt __maybe_unused *fadt;
@@ -218,6 +226,13 @@ int last_stage_init(void)
}
}
+ /*
+* TODO(s...@chromium.org): Move this to bootm_announce_and_cleanup()
+* once APL FSP-S at 0x20 does not overlap with the bzimage at
+* 0x10.
+*/
+ board_final_cleanup();
+
return 0;
}
#endif
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index ea529547254..4061fa244c4 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -60,6 +60,22 @@ void board_final_init(void)
debug("OK\n");
}
+void board_final_cleanup(void)
+{
+ u32 status;
+
+ /* TODO(s...@chromium.org): This causes Linux to crash */
+ return;
+
+ /* call into FspNotify */
+ debug("Calling into FSP (notify phase INIT_PHASE_END_FIRMWARE): ");
+ status = fsp_notify(NULL, INIT_PHASE_END_FIRMWARE);
+ if (status)
+ debug("fail, error code %x\n", status);
+ else
+ debug("OK\n");
+}
+
int fsp_save_s3_stack(void)
{
struct udevice *dev;
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 44/59] x86: Correct the assembly guard in e820.h
This is currently in the wrong place, so including the file in the device
tree fails. Fix it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v1)
Changes in v1:
- Update commit message with a comma
arch/x86/include/asm/e820.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h
index d7f8a4ba1df..a66c0d24891 100644
--- a/arch/x86/include/asm/e820.h
+++ b/arch/x86/include/asm/e820.h
@@ -22,10 +22,9 @@ struct e820_entry {
#define ISA_START_ADDRESS 0xa
#define ISA_END_ADDRESS0x10
-#endif /* __ASSEMBLY__ */
-
/* Implementation defined function to install an e820 map */
unsigned int install_e820_map(unsigned int max_entries,
struct e820_entry *);
+#endif /* __ASSEMBLY__ */
#endif /* _ASM_X86_E820_H */
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 42/59] x86: Sort the MTRR table
At present the MTRR registers are programmed with the list the U-Boot
builds up in the same order. In some cases this list may be out of order.
It looks better in Linux to have the registers in order, so sort them,
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/cpu/mtrr.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index 2468d88a80a..08fa80f8bc7 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -124,6 +125,16 @@ static int mtrr_copy_to_aps(void)
return 0;
}
+static int h_comp_mtrr(const void *p1, const void *p2)
+{
+ const struct mtrr_request *req1 = p1;
+ const struct mtrr_request *req2 = p2;
+
+ s64 diff = req1->start - req2->start;
+
+ return diff < 0 ? -1 : diff > 0 ? 1 : 0;
+}
+
int mtrr_commit(bool do_caches)
{
struct mtrr_request *req = gd->arch.mtrr_req;
@@ -139,6 +150,7 @@ int mtrr_commit(bool do_caches)
debug("open\n");
mtrr_open(, do_caches);
debug("open done\n");
+ qsort(req, gd->arch.mtrr_req_count, sizeof(*req), h_comp_mtrr);
for (i = 0; i < gd->arch.mtrr_req_count; i++, req++)
set_var_mtrr(i, req->type, req->start, req->size);
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 39/59] tpm: cr50: Add ACPI support
Generate ACPI information for this device so that Linux can use it
correctly.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Capitalise ACPI_OPS_PTR
- Update for acpi_device_write_i2c_dev() return-value change
- Use acpi,ddn instead of acpi,desc
drivers/tpm/cr50_i2c.c | 55 ++
1 file changed, 55 insertions(+)
diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c
index 1942c07c605..64831a42232 100644
--- a/drivers/tpm/cr50_i2c.c
+++ b/drivers/tpm/cr50_i2c.c
@@ -14,11 +14,14 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
#include
#include
+#include
enum {
TIMEOUT_INIT_MS = 3, /* Very long timeout for TPM init */
@@ -581,6 +584,53 @@ static int cr50_i2c_cleanup(struct udevice *dev)
return 0;
}
+static int cr50_acpi_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ char scope[ACPI_PATH_MAX];
+ char name[ACPI_NAME_MAX];
+ const char *hid;
+ int ret;
+
+ ret = acpi_device_scope(dev, scope, sizeof(scope));
+ if (ret)
+ return log_msg_ret("scope", ret);
+ ret = acpi_get_name(dev, name);
+ if (ret)
+ return log_msg_ret("name", ret);
+
+ hid = dev_read_string(dev, "acpi,hid");
+ if (!hid)
+ return log_msg_ret("hid", ret);
+
+ /* Device */
+ acpigen_write_scope(ctx, scope);
+ acpigen_write_device(ctx, name);
+ acpigen_write_name_string(ctx, "_HID", hid);
+ acpigen_write_name_integer(ctx, "_UID",
+ dev_read_u32_default(dev, "acpi,uid", 0));
+ acpigen_write_name_string(ctx, "_DDN",
+ dev_read_string(dev, "acpi,ddn"));
+ acpigen_write_sta(ctx, acpi_device_status(dev));
+
+ /* Resources */
+ acpigen_write_name(ctx, "_CRS");
+ acpigen_write_resourcetemplate_header(ctx);
+ ret = acpi_device_write_i2c_dev(ctx, dev);
+ if (ret < 0)
+ return log_msg_ret("i2c", ret);
+ ret = acpi_device_write_interrupt_or_gpio(ctx, (struct udevice *)dev,
+ "ready-gpios");
+ if (ret < 0)
+ return log_msg_ret("irq_gpio", ret);
+
+ acpigen_write_resourcetemplate_footer(ctx);
+
+ acpigen_pop_len(ctx); /* Device */
+ acpigen_pop_len(ctx); /* Scope */
+
+ return 0;
+}
+
enum {
TPM_TIMEOUT_MS = 5,
SHORT_TIMEOUT_MS= 750,
@@ -653,6 +703,10 @@ static int cr50_i2c_probe(struct udevice *dev)
return 0;
}
+struct acpi_ops cr50_acpi_ops = {
+ .fill_ssdt = cr50_acpi_fill_ssdt,
+};
+
static const struct tpm_ops cr50_i2c_ops = {
.open = cr50_i2c_open,
.get_desc = cr50_i2c_get_desc,
@@ -675,5 +729,6 @@ U_BOOT_DRIVER(cr50_i2c) = {
.probe = cr50_i2c_probe,
.remove = cr50_i2c_cleanup,
.priv_auto_alloc_size = sizeof(struct cr50_priv),
+ ACPI_OPS_PTR(_acpi_ops)
.flags = DM_FLAG_OS_PREPARE,
};
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 40/59] x86: fsp: Update the FSP API with the end-firmware method
This new method is intended to be called when UEFI shuts down the 'boot
services', i.e. any lingering code in the boot loader that might be used
by the OS.
Add a definition for this new method and update the comments a little.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v1)
arch/x86/include/asm/fsp/fsp_api.h | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/fsp/fsp_api.h
b/arch/x86/include/asm/fsp/fsp_api.h
index 4941e2d74f0..3a9b61903c0 100644
--- a/arch/x86/include/asm/fsp/fsp_api.h
+++ b/arch/x86/include/asm/fsp/fsp_api.h
@@ -10,9 +10,18 @@
enum fsp_phase {
/* Notification code for post PCI enuermation */
- INIT_PHASE_PCI = 0x20,
- /* Notification code before transferring control to the payload */
- INIT_PHASE_BOOT = 0x40
+ INIT_PHASE_PCI = 0x20,
+ /*
+* Notification code before transferring control to the payload.
+* This is issued at the end of init before starting main(), i.e.
+* the command line / boot script.
+*/
+ INIT_PHASE_BOOT = 0x40,
+ /*
+* Notification code before existing boot services. This is issued
+* just before removing devices and booting the kernel.
+*/
+ INIT_PHASE_END_FIRMWARE = 0xf0,
};
struct fsp_notify_params {
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 36/59] x86: apl: Generate CPU tables
Add ACPI generation to the APL CPU driver.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Capitalise ACPI_OPS_PTR
- Handle table generation without callbacks
arch/x86/cpu/apollolake/cpu.c | 77 ++
arch/x86/lib/Makefile | 3 +-
configs/chromebook_coral_defconfig | 1 +
3 files changed, 80 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c
index 0a6d2ad7a4a..8da2e64e226 100644
--- a/arch/x86/cpu/apollolake/cpu.c
+++ b/arch/x86/cpu/apollolake/cpu.c
@@ -6,14 +6,90 @@
#include
#include
#include
+#include
+#include
+#include
#include
#include
+#include
+#include
+#include
+
+#define CSTATE_RES(address_space, width, offset, address) \
+ { \
+ .space_id = address_space, \
+ .bit_width = width, \
+ .bit_offset = offset, \
+ .addrl = address, \
+ }
+
+static struct acpi_cstate cstate_map[] = {
+ {
+ /* C1 */
+ .ctype = 1, /* ACPI C1 */
+ .latency = 1,
+ .power = 1000,
+ .resource = {
+ .space_id = ACPI_ADDRESS_SPACE_FIXED,
+ },
+ }, {
+ .ctype = 2, /* ACPI C2 */
+ .latency = 50,
+ .power = 10,
+ .resource = {
+ .space_id = ACPI_ADDRESS_SPACE_IO,
+ .bit_width = 8,
+ .addrl = 0x415,
+ },
+ }, {
+ .ctype = 3, /* ACPI C3 */
+ .latency = 150,
+ .power = 10,
+ .resource = {
+ .space_id = ACPI_ADDRESS_SPACE_IO,
+ .bit_width = 8,
+ .addrl = 0x419,
+ },
+ },
+};
static int apl_get_info(const struct udevice *dev, struct cpu_info *info)
{
return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
}
+static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ uint core_id = dev->req_seq;
+ int cores_per_package;
+ int ret;
+
+ cores_per_package = cpu_get_cores_per_package();
+ ret = acpi_generate_cpu_header(ctx, core_id, cstate_map,
+ ARRAY_SIZE(cstate_map));
+
+ /* Generate P-state tables */
+ generate_p_state_entries(ctx, core_id, cores_per_package);
+
+ /* Generate T-state tables */
+ generate_t_state_entries(ctx, core_id, cores_per_package, NULL, 0);
+
+ acpigen_pop_len(ctx);
+
+ if (device_is_last_sibling(dev)) {
+ ret = acpi_generate_cpu_package_final(ctx, cores_per_package);
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+struct acpi_ops apl_cpu_acpi_ops = {
+ .fill_ssdt = acpi_cpu_fill_ssdt,
+};
+
static const struct cpu_ops cpu_x86_apl_ops = {
.get_desc = cpu_x86_get_desc,
.get_info = apl_get_info,
@@ -32,5 +108,6 @@ U_BOOT_DRIVER(cpu_x86_apl_drv) = {
.of_match = cpu_x86_apl_ids,
.bind = cpu_x86_bind,
.ops= _x86_apl_ops,
+ ACPI_OPS_PTR(_cpu_acpi_ops)
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index f04d275dd9a..1bcbb49a61f 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -38,7 +38,8 @@ obj-y += sfi.o
obj-y += acpi.o
obj-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.o
ifndef CONFIG_QEMU
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o acpigen.o
+obj-y += acpigen.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
endif
obj-y += tables.o
ifndef CONFIG_SPL_BUILD
diff --git a/configs/chromebook_coral_defconfig
b/configs/chromebook_coral_defconfig
index c9006e2f934..ef4dabbe26e 100644
--- a/configs/chromebook_coral_defconfig
+++ b/configs/chromebook_coral_defconfig
@@ -72,6 +72,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_INTEL_ACPIGEN=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 41/59] x86: cpu: Report address width from cpu_get_info()
Add support for this new field in the common code used by most x86 CPU
drivers.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/cpu/i386/cpu.c | 23 +++
arch/x86/cpu/intel_common/cpu.c | 1 +
arch/x86/cpu/x86_64/cpu.c | 5 +
arch/x86/include/asm/cpu.h | 9 +
4 files changed, 38 insertions(+)
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 8f342dd06e2..7517b756f43 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -34,6 +34,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#define CPUID_FEATURE_PAE BIT(6)
+#define CPUID_FEATURE_PSE36BIT(17)
+#define CPUID_FEAURE_HTT BIT(28)
+
/*
* Constructor for a conventional segment GDT (or LDT) entry
* This is a macro so it can be used in initialisers
@@ -388,6 +392,25 @@ static void setup_identity(void)
}
}
+static uint cpu_cpuid_extended_level(void)
+{
+ return cpuid_eax(0x8000);
+}
+
+int cpu_phys_address_size(void)
+{
+ if (!has_cpuid())
+ return 32;
+
+ if (cpu_cpuid_extended_level() >= 0x8008)
+ return cpuid_eax(0x8008) & 0xff;
+
+ if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+ return 36;
+
+ return 32;
+}
+
/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
static void setup_pci_ram_top(void)
{
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index d8a3d60ae72..39aa0f63c65 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -127,6 +127,7 @@ int cpu_intel_get_info(struct cpu_info *info, int bclk)
info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 100;
info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
+ info->address_width = cpu_phys_address_size();
return 0;
}
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 1b4d3971b04..90a766c3c57 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -70,3 +70,8 @@ int x86_cpu_reinit_f(void)
{
return 0;
}
+
+int cpu_phys_address_size(void)
+{
+ return CONFIG_CPU_ADDR_BITS;
+}
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 21a05dab7de..5b001bbee21 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -288,4 +288,13 @@ u32 cpu_get_family_model(void);
*/
u32 cpu_get_stepping(void);
+/**
+ * cpu_phys_address_size() - Get the physical address size in bits
+ *
+ * This is 32 for older CPUs but newer ones may support 36.
+ *
+ * @return address size (typically 32 or 36)
+ */
+int cpu_phys_address_size(void);
+
#endif
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 35/59] x86: apl: Add support for hostbridge ACPI generation
Support generating a DMAR table and add a few helper routines as well.
Also set up NHLT so that audio works.
Signed-off-by: Simon Glass
---
Changes in v4:
Drop extra acpi_align() in apl_acpi_hb_write_tables()
Changes in v1:
- Add support for NHLT table
- Capitalise ACPI_OPS_PTR
- Move the acpi.h header file to this commit
- Update commit message
arch/x86/cpu/apollolake/hostbridge.c | 220 +--
1 file changed, 211 insertions(+), 9 deletions(-)
diff --git a/arch/x86/cpu/apollolake/hostbridge.c
b/arch/x86/cpu/apollolake/hostbridge.c
index 056f7e57a9a..7fd67dcfb6e 100644
--- a/arch/x86/cpu/apollolake/hostbridge.c
+++ b/arch/x86/cpu/apollolake/hostbridge.c
@@ -1,17 +1,45 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Google LLC
+ * Copyright (C) 2015 - 2017 Intel Corp.
+ * Copyright (C) 2017 - 2019 Siemens AG
+ * (Written by Alexandru Gagniuc for Intel
Corp.)
+ * (Written by Andrey Petrov for Intel Corp.)
+ *
+ * Portions from coreboot soc/intel/apollolake/chip.c
*/
+#define LOG_CATEGORY UCLASS_NORTHBRIDGE
+
#include
#include
#include
#include
#include
+#include
+#include
+#include
#include
#include
+#include
#include
+#include
#include
+#include
+#include
+
+enum {
+ PCIEXBAR= 0x60,
+ PCIEXBAR_LENGTH_256MB = 0,
+ PCIEXBAR_LENGTH_128MB,
+ PCIEXBAR_LENGTH_64MB,
+
+ PCIEXBAR_PCIEXBAREN = 1 << 0,
+
+ BGSM= 0xb4, /* Base GTT Stolen Memory */
+ TSEG= 0xb8, /* TSEG base */
+ TOLUD = 0xbc,
+};
/**
* struct apl_hostbridge_platdata - platform data for hostbridge
@@ -32,17 +60,100 @@ struct apl_hostbridge_platdata {
pci_dev_t bdf;
};
-enum {
- PCIEXBAR= 0x60,
- PCIEXBAR_LENGTH_256MB = 0,
- PCIEXBAR_LENGTH_128MB,
- PCIEXBAR_LENGTH_64MB,
+static const struct nhlt_format_config dmic_1ch_formats[] = {
+ /* 48 KHz 16-bits per sample. */
+ {
+ .num_channels = 1,
+ .sample_freq_khz = 48,
+ .container_bits_per_sample = 16,
+ .valid_bits_per_sample = 16,
+ .settings_file = "dmic-1ch-48khz-16b.dat",
+ },
+};
- PCIEXBAR_PCIEXBAREN = 1 << 0,
+static const struct nhlt_dmic_array_config dmic_1ch_mic_config = {
+ .tdm_config = {
+ .config_type = NHLT_TDM_MIC_ARRAY,
+ },
+ .array_type = NHLT_MIC_ARRAY_VENDOR_DEFINED,
+};
- BGSM= 0xb4, /* Base GTT Stolen Memory */
- TSEG= 0xb8, /* TSEG base */
- TOLUD = 0xbc,
+static const struct nhlt_endp_descriptor dmic_1ch_descriptors[] = {
+ {
+ .link = NHLT_LINK_PDM,
+ .device = NHLT_PDM_DEV,
+ .direction = NHLT_DIR_CAPTURE,
+ .vid = NHLT_VID,
+ .did = NHLT_DID_DMIC,
+ .cfg = _1ch_mic_config,
+ .cfg_size = sizeof(dmic_1ch_mic_config),
+ .formats = dmic_1ch_formats,
+ .num_formats = ARRAY_SIZE(dmic_1ch_formats),
+ },
+};
+
+static const struct nhlt_format_config dmic_2ch_formats[] = {
+ /* 48 KHz 16-bits per sample. */
+ {
+ .num_channels = 2,
+ .sample_freq_khz = 48,
+ .container_bits_per_sample = 16,
+ .valid_bits_per_sample = 16,
+ .settings_file = "dmic-2ch-48khz-16b.dat",
+ },
+};
+
+static const struct nhlt_dmic_array_config dmic_2ch_mic_config = {
+ .tdm_config = {
+ .config_type = NHLT_TDM_MIC_ARRAY,
+ },
+ .array_type = NHLT_MIC_ARRAY_2CH_SMALL,
+};
+
+static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = {
+ {
+ .link = NHLT_LINK_PDM,
+ .device = NHLT_PDM_DEV,
+ .direction = NHLT_DIR_CAPTURE,
+ .vid = NHLT_VID,
+ .did = NHLT_DID_DMIC,
+ .cfg = _2ch_mic_config,
+ .cfg_size = sizeof(dmic_2ch_mic_config),
+ .formats = dmic_2ch_formats,
+ .num_formats = ARRAY_SIZE(dmic_2ch_formats),
+ },
+};
+
+static const struct nhlt_format_config dmic_4ch_formats[] = {
+ /* 48 KHz 16-bits per sample. */
+ {
+ .num_channels = 4,
+ .sample_freq_khz = 48,
+ .container_bits_per_sample = 16,
+ .valid_bits_per_sample = 16,
+ .settings_file = "dmic-4ch-48khz-16b.dat",
+ },
+};
+
+static const struct nhlt_dmic_array_config dmic_4ch_mic_config = {
+ .tdm_config = {
+ .config_type = NHLT_TDM_MIC_ARRAY,
+ },
+ .array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED,
+};
+
+static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = {
+ {
+ .link = NHLT_LINK_PDM,
+ .device = NHLT_PDM_DEV,
+
[PATCH v4 38/59] x86: apl: Drop unnecessary code in PMC driver
We don't have CONFIG_PCI in TPL but it is present in SPL, etc. So this
code is not needed. Drop it, and fix a code-style nit just above.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/cpu/apollolake/pmc.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c
index 192dec7109a..576d0187570 100644
--- a/arch/x86/cpu/apollolake/pmc.c
+++ b/arch/x86/cpu/apollolake/pmc.c
@@ -118,7 +118,8 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
int size;
int ret;
- ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
+ ret = dev_read_u32_array(dev, "early-regs", base,
+ARRAY_SIZE(base));
if (ret)
return log_msg_ret("Missing/short early-regs", ret);
if (spl_phase() == PHASE_TPL) {
@@ -133,11 +134,6 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
}
upriv->acpi_base = base[4];
- /* Since PCI is not enabled, we must get the BDF manually */
- plat->bdf = pci_get_devfn(dev);
- if (plat->bdf < 0)
- return log_msg_ret("Cannot get PMC PCI address", plat->bdf);
-
/* Get the dwX values for pmc gpe settings */
size = dev_read_size(dev, "gpe0-dw");
if (size < 0)
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 34/59] x86: apl: Generate required ACPI tables
Add support for generating various ACPI tables for Apollo Lake. Add a few
S3 definitions that are needed.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Drop unnecessary callbacks
arch/x86/cpu/apollolake/Makefile| 1 +
arch/x86/cpu/apollolake/acpi.c | 211
arch/x86/include/asm/arch-apollolake/acpi.h | 18 ++
include/acpi/acpi_s3.h | 4 +
4 files changed, 234 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/acpi.c
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 3aa2a556765..2ddf4af62c5 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -16,6 +16,7 @@ obj-y += fsp_m.o
endif
endif
ifndef CONFIG_SPL_BUILD
+obj-y += acpi.o
obj-y += fsp_s.o
endif
diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c
new file mode 100644
index 000..69b544f0d98
--- /dev/null
+++ b/arch/x86/cpu/apollolake/acpi.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2017-2019 Siemens AG
+ * (Written by Lance Zhao for Intel Corp.)
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot apollolake/acpi.c
+ */
+
+#define LOG_CATEGORY LOGC_ACPI
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+int arch_read_sci_irq_select(void)
+{
+ struct acpi_pmc_upriv *upriv;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_ACPI_PMC, );
+ if (ret)
+ return log_msg_ret("pmc", ret);
+ upriv = dev_get_uclass_priv(dev);
+
+ return readl(upriv->pmc_bar0 + IRQ_REG);
+}
+
+int arch_write_sci_irq_select(uint scis)
+{
+ struct acpi_pmc_upriv *upriv;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_ACPI_PMC, );
+ if (ret)
+ return log_msg_ret("pmc", ret);
+ upriv = dev_get_uclass_priv(dev);
+ writel(scis, upriv->pmc_bar0 + IRQ_REG);
+
+ return 0;
+}
+
+int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
+{
+ struct udevice *cpu;
+ int ret;
+
+ /* Clear out GNV */
+ memset(gnvs, '\0', sizeof(*gnvs));
+
+ /* TODO(s...@chromium.org): Add the console log to gnvs->cbmc */
+
+#ifdef CONFIG_CHROMEOS
+ /* Initialise Verified Boot data */
+ chromeos_init_acpi(>chromeos);
+ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+#endif
+ /* Set unknown wake source */
+ gnvs->pm1i = ~0ULL;
+
+ /* CPU core count */
+ gnvs->pcnt = 1;
+ ret = uclass_find_first_device(UCLASS_CPU, );
+ if (cpu) {
+ ret = cpu_get_count(cpu);
+ if (ret > 0)
+ gnvs->pcnt = ret;
+ }
+
+ return 0;
+}
+
+uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en)
+{
+ /*
+* WAK_STS bit is set when the system is in one of the sleep states
+* (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
+* this bit, the PMC will transition the system to the ON state and
+* can only be set by hardware and can only be cleared by writing a one
+* to this bit position.
+*/
+ generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
+
+ return generic_pm1_en;
+}
+
+int arch_madt_sci_irq_polarity(int sci)
+{
+ return MP_IRQ_POLARITY_LOW;
+}
+
+void fill_fadt(struct acpi_fadt *fadt)
+{
+ fadt->pm_tmr_blk = IOMAP_ACPI_BASE + PM1_TMR;
+
+ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+
+ fadt->pm_tmr_len = 4;
+ fadt->duty_width = 3;
+
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+ fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR;
+}
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt)
+{
+ struct acpi_table_header *header = >header;
+
+ acpi_fadt_common(fadt, facs, dsdt);
+ intel_acpi_fill_fadt(fadt);
+ fill_fadt(fadt);
+ header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+int apl_acpi_fill_dmar(struct acpi_ctx *ctx)
+{
+ struct udevice *dev, *sa_dev;
+ u64 gfxvtbar = readq(MCHBAR_REG(GFXVTBAR)) & VTBAR_MASK;
+ u64 defvtbar = readq(MCHBAR_REG(DEFVTBAR)) & VTBAR_MASK;
+ bool gfxvten = readl(MCHBAR_REG(GFXVTBAR)) & VTBAR_ENABLED;
+ bool defvten = readl(MCHBAR_REG(DEFVTBAR)) & VTBAR_ENABLED;
+ void *tmp;
+ int ret;
+
+
[PATCH v4 37/59] x86: apl: Generate ACPI table for LPC
Add an ACPI table for the LPC on Apollo Lake.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Capitalise ACPI_OPS_PTR
arch/x86/cpu/apollolake/lpc.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c
index b81a458f2eb..a29832c879a 100644
--- a/arch/x86/cpu/apollolake/lpc.c
+++ b/arch/x86/cpu/apollolake/lpc.c
@@ -9,10 +9,14 @@
#include
#include
#include
+#include
+#include
+#include
#include
#include
#include
#include
+#include
#include
void lpc_enable_fixed_io_ranges(uint io_enables)
@@ -110,6 +114,19 @@ void lpc_io_setup_comm_a_b(void)
lpc_enable_fixed_io_ranges(com_enable);
}
+static int apl_acpi_lpc_get_name(const struct udevice *dev, char *out_name)
+{
+ return acpi_copy_name(out_name, "LPCB");
+}
+
+struct acpi_ops apl_lpc_acpi_ops = {
+ .get_name = apl_acpi_lpc_get_name,
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+ .write_tables = intel_southbridge_write_acpi_tables,
+#endif
+ .inject_dsdt= southbridge_inject_dsdt,
+};
+
static const struct udevice_id apl_lpc_ids[] = {
{ .compatible = "intel,apl-lpc" },
{ }
@@ -120,4 +137,5 @@ U_BOOT_DRIVER(apl_lpc_drv) = {
.name = "intel_apl_lpc",
.id = UCLASS_LPC,
.of_match = apl_lpc_ids,
+ ACPI_OPS_PTR(_lpc_acpi_ops)
};
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 31/59] x86: acpi: Add support for additional Intel tables
Apollo Lake needs to generate a few more table types used on Intel SoCs.
Add support for these into the x86 ACPI code.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Move this code into an x86-specific file
- Update commit message
- Use OEM_TABLE_ID instead of ACPI_TABLE_CREATOR
arch/x86/include/asm/acpi_table.h | 115 ++
arch/x86/lib/acpi_table.c | 111
include/acpi/acpi_table.h | 43 +++
3 files changed, 269 insertions(+)
diff --git a/arch/x86/include/asm/acpi_table.h
b/arch/x86/include/asm/acpi_table.h
index 3245e447813..faf31730730 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -98,4 +98,119 @@ int arch_write_sci_irq_select(uint scis);
*/
int arch_madt_sci_irq_polarity(int sci);
+/**
+ * acpi_create_dmar_drhd() - Create a table for DMA remapping with the IOMMU
+ *
+ * See here for the specification
+ *
https://software.intel.com/sites/default/files/managed/c5/15/vt-directed-io-spec.pdf
+ *
+ * @ctx: ACPI context pointer
+ * @flags: (DRHD_INCLUDE_...)
+ * @segment: PCI segment asscociated with this unit
+ * @bar: Base address of remapping hardware register-set for this unit
+ */
+void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment,
+ u64 bar);
+
+/**
+ * acpi_create_dmar_rmrr() - Set up an RMRR
+ *
+ * This sets up a Reserved-Memory Region Reporting structure, used to allow
+ * DMA to regions used by devices that the BIOS controls.
+ *
+ * @ctx: ACPI context pointer
+ * @segment: PCI segment asscociated with this unit
+ * @bar: Base address of mapping
+ * @limit: End address of mapping
+ */
+void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar,
+ u64 limit);
+
+/**
+ * acpi_dmar_drhd_fixup() - Set the length of an DRHD
+ *
+ * This sets the DRHD length field based on the current ctx->current
+ *
+ * @ctx: ACPI context pointer
+ * @base: Address of the start of the DRHD
+ */
+void acpi_dmar_drhd_fixup(struct acpi_ctx *ctx, void *base);
+
+/**
+ * acpi_dmar_rmrr_fixup() - Set the length of an RMRR
+ *
+ * This sets the RMRR length field based on the current ctx->current
+ *
+ * @ctx: ACPI context pointer
+ * @base: Address of the start of the RMRR
+ */
+void acpi_dmar_rmrr_fixup(struct acpi_ctx *ctx, void *base);
+
+/**
+ * acpi_create_dmar_ds_pci() - Set up a DMAR scope for a PCI device
+ *
+ * @ctx: ACPI context pointer
+ * @bdf: PCI device to add
+ * @return length of mapping in bytes
+ */
+int acpi_create_dmar_ds_pci(struct acpi_ctx *ctx, pci_dev_t bdf);
+
+/**
+ * acpi_create_dmar_ds_pci_br() - Set up a DMAR scope for a PCI bridge
+ *
+ * This is used to provide a mapping for a PCI bridge
+ *
+ * @ctx: ACPI context pointer
+ * @bdf: PCI device to add
+ * @return length of mapping in bytes
+ */
+int acpi_create_dmar_ds_pci_br(struct acpi_ctx *ctx, pci_dev_t bdf);
+
+/**
+ * acpi_create_dmar_ds_ioapic() - Set up a DMAR scope for an IOAPIC device
+ *
+ * @ctx: ACPI context pointer
+ * @enumeration_id: Enumeration ID (typically 2)
+ * @bdf: PCI device to add
+ * @return length of mapping in bytes
+ */
+int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id,
+ pci_dev_t bdf);
+
+/**
+ * acpi_create_dmar_ds_msi_hpet() - Set up a DMAR scope for an HPET
+ *
+ * Sets up a scope for a High-Precision Event Timer that supports
+ * Message-Signalled Interrupts
+ *
+ * @ctx: ACPI context pointer
+ * @enumeration_id: Enumeration ID (typically 0)
+ * @bdf: PCI device to add
+ * @return length of mapping in bytes
+ */
+int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id,
+pci_dev_t bdf);
+
+/**
+ * acpi_fadt_common() - Handle common parts of filling out an FADT
+ *
+ * This sets up the Fixed ACPI Description Table
+ *
+ * @fadt: Pointer to place to put FADT
+ * @facs: Pointer to the FACS
+ * @dsdt: Pointer to the DSDT
+ */
+void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt);
+
+/**
+ * intel_acpi_fill_fadt() - Set up the contents of the FADT
+ *
+ * This sets up parts of the Fixed ACPI Description Table that are common to
+ * Intel chips
+ *
+ * @fadt: Pointer to place to put FADT
+ */
+void intel_acpi_fill_fadt(struct acpi_fadt *fadt);
+
#endif /* __ASM_ACPI_TABLE_H__ */
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index e257c789838..86a9a35cb25 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -629,3 +629,114 @@ int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct
udevice *dev,
return 0;
}
+
+void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt)
+{
+ struct acpi_table_header *header = >header;
+
+ memset((void *)fadt, '\0', sizeof(struct acpi_fadt));
+
+ acpi_fill_header(header,
[PATCH v4 33/59] p2sb: Add some definitions used for ACPI
Allow this header to be included in ASL files by adding a header guard and a few definitions that are needed. Signed-off-by: Simon Glass --- (no changes since v1) include/p2sb.h | 8 1 file changed, 8 insertions(+) diff --git a/include/p2sb.h b/include/p2sb.h index 93e1155dca6..a25170e3d11 100644 --- a/include/p2sb.h +++ b/include/p2sb.h @@ -10,6 +10,12 @@ /* Port Id lives in bits 23:16 and register offset lives in 15:0 of address */ #define PCR_PORTID_SHIFT 16 +#if !defined(__ACPI__) + +/* These registers contain IOAPIC and HPET devfn */ +#define PCH_P2SB_IBDF 0x6c +#define PCH_P2SB_HBDF 0x70 + /** * struct p2sb_child_platdata - Information about each child of a p2sb device * @@ -164,4 +170,6 @@ int p2sb_get_port_id(struct udevice *dev); */ void *pcr_reg_address(struct udevice *dev, uint offset); +#endif /* !__ACPI__ */ + #endif -- 2.28.0.681.g6f77f65b4e-goog
[PATCH v4 27/59] x86: acpi: Add PCT and PTC tables
These are needed for the CPU tables. Add them into an x86-specific file
since we do not support them on sandbox, or include tests.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Split PCT and PTC tables into a separate patch
arch/x86/include/asm/acpigen.h | 35 +
arch/x86/lib/Makefile | 2 +-
arch/x86/lib/acpigen.c | 96 ++
3 files changed, 132 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/include/asm/acpigen.h
create mode 100644 arch/x86/lib/acpigen.c
diff --git a/arch/x86/include/asm/acpigen.h b/arch/x86/include/asm/acpigen.h
new file mode 100644
index 000..c531dd61d53
--- /dev/null
+++ b/arch/x86/include/asm/acpigen.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Generation of x86-specific ACPI tables
+ *
+ * Copyright 2020 Google LLC
+ */
+
+#ifndef __ASM_ACPIGEN_H__
+#define __ASM_ACPIGEN_H__
+
+struct acpi_ctx;
+
+/**
+ * acpigen_write_empty_pct() - Write an empty PCT
+ *
+ * See ACPI v6.3 section 8.4.6.1: _PCT (Performance Control)
+ *
+ * This writes an empty table so that CPU performance works as expected
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_empty_pct(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_empty_ptc() - Write an empty PTC
+ *
+ * See ACPI v6.3 section 8.4.5.1: _PTC (Processor Throttling Control)
+ *
+ * This writes an empty table so that CPU performance works as expected
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_empty_ptc(struct acpi_ctx *ctx);
+
+#endif /* __ASM_ACPI_H__ */
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 1185a88c27c..f04d275dd9a 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -38,7 +38,7 @@ obj-y += sfi.o
obj-y += acpi.o
obj-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.o
ifndef CONFIG_QEMU
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o acpigen.o
endif
obj-y += tables.o
ifndef CONFIG_SPL_BUILD
diff --git a/arch/x86/lib/acpigen.c b/arch/x86/lib/acpigen.c
new file mode 100644
index 000..ea2ec2a9083
--- /dev/null
+++ b/arch/x86/lib/acpigen.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+
+void acpigen_write_empty_pct(struct acpi_ctx *ctx)
+{
+ /*
+* Name (_PCT, Package (0x02)
+* {
+* ResourceTemplate ()
+* {
+* Register (FFixedHW,
+* 0x00, // Bit Width
+* 0x00, // Bit Offset
+* 0x, // Address
+* ,)
+* },
+*
+* ResourceTemplate ()
+* {
+* Register (FFixedHW,
+* 0x00, // Bit Width
+* 0x00, // Bit Offset
+* 0x, // Address
+* ,)
+* }
+* })
+*/
+ static char stream[] = {
+ /* 0030"0._PCT.," */
+ 0x08, 0x5f, 0x50, 0x43, 0x54, 0x12, 0x2c,
+ /* 0038"" */
+ 0x02, 0x11, 0x14, 0x0a, 0x11, 0x82, 0x0c, 0x00,
+ /* 0040"" */
+ 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0048"y..." */
+ 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14,
+ /* 0050"" */
+ 0x0a, 0x11, 0x82, 0x0c, 0x00, 0x7f, 0x00, 0x00,
+ /* 0058"" */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x79, 0x00
+ };
+ acpigen_emit_stream(ctx, stream, ARRAY_SIZE(stream));
+}
+
+void acpigen_write_empty_ptc(struct acpi_ctx *ctx)
+{
+ /*
+* Name (_PTC, Package (0x02)
+* {
+* ResourceTemplate ()
+* {
+* Register (FFixedHW,
+* 0x00, // Bit Width
+* 0x00, // Bit Offset
+* 0x, // Address
+* ,)
+* },
+*
+* ResourceTemplate ()
+* {
+* Register (FFixedHW,
+* 0x00, // Bit Width
+* 0x00, // Bit Offset
+* 0x, // Address
+* ,)
+* }
+* })
+*/
+ struct acpi_gen_regaddr addr = {
+ .space_id= ACPI_ADDRESS_SPACE_FIXED,
+ .bit_width = 0,
+ .bit_offset = 0,
+
[PATCH v4 29/59] x86: acpi: Add common Intel ACPI tables
Add various tables that are common to Intel CPUs. These functions can be
used by arch-specific CPU code.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/cpu/intel_common/Makefile | 2 +
arch/x86/cpu/intel_common/acpi.c | 377 +
arch/x86/cpu/intel_common/cpu.c| 14 ++
arch/x86/include/asm/acpi_table.h | 22 ++
arch/x86/include/asm/cpu_common.h | 7 +
arch/x86/include/asm/intel_acpi.h | 52
drivers/core/Kconfig | 9 +
7 files changed, 483 insertions(+)
create mode 100644 arch/x86/cpu/intel_common/acpi.c
create mode 100644 arch/x86/include/asm/intel_acpi.h
diff --git a/arch/x86/cpu/intel_common/Makefile
b/arch/x86/cpu/intel_common/Makefile
index f1d1513a981..4a5cf17e41d 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -2,6 +2,8 @@
#
# Copyright (c) 2016 Google, Inc
+obj-$(CONFIG_INTEL_ACPIGEN) += acpi.o
+
ifdef CONFIG_HAVE_MRC
obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o
diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c
new file mode 100644
index 000..a4d5fbd38a7
--- /dev/null
+++ b/arch/x86/cpu/intel_common/acpi.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generic Intel ACPI table generation
+ *
+ * Copyright (C) 2017 Intel Corp.
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot src/soc/intel/common/block/acpi.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+u32 acpi_fill_mcfg(u32 current)
+{
+ /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
+ current += acpi_create_mcfg_mmconfig((void *)current,
+CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
+(CONFIG_SA_PCIEX_LENGTH >> 20)
+- 1);
+ return current;
+}
+
+static int acpi_sci_irq(void)
+{
+ int sci_irq = 9;
+ uint scis;
+ int ret;
+
+ ret = arch_read_sci_irq_select();
+ if (IS_ERR_VALUE(ret))
+ return log_msg_ret("sci_irq", ret);
+ scis = ret;
+ scis &= SCI_IRQ_MASK;
+ scis >>= SCI_IRQ_SHIFT;
+
+ /* Determine how SCI is routed. */
+ switch (scis) {
+ case SCIS_IRQ9:
+ case SCIS_IRQ10:
+ case SCIS_IRQ11:
+ sci_irq = scis - SCIS_IRQ9 + 9;
+ break;
+ case SCIS_IRQ20:
+ case SCIS_IRQ21:
+ case SCIS_IRQ22:
+ case SCIS_IRQ23:
+ sci_irq = scis - SCIS_IRQ20 + 20;
+ break;
+ default:
+ log_warning("Invalid SCI route! Defaulting to IRQ9\n");
+ sci_irq = 9;
+ break;
+ }
+
+ log_debug("SCI is IRQ%d\n", sci_irq);
+
+ return sci_irq;
+}
+
+static unsigned long acpi_madt_irq_overrides(unsigned long current)
+{
+ int sci = acpi_sci_irq();
+ u16 flags = MP_IRQ_TRIGGER_LEVEL;
+
+ if (sci < 0)
+ return log_msg_ret("sci irq", sci);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0);
+
+ flags |= arch_madt_sci_irq_polarity(sci);
+
+ /* SCI */
+ current +=
+ acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags);
+
+ return current;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+ /* Local APICs */
+ current += acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0);
+
+ return acpi_madt_irq_overrides(current);
+}
+
+void intel_acpi_fill_fadt(struct acpi_fadt *fadt)
+{
+ const u16 pmbase = IOMAP_ACPI_BASE;
+
+ /* Use ACPI 3.0 revision. */
+ fadt->header.revision = acpi_get_table_revision(ACPITAB_FADT);
+
+ fadt->sci_int = acpi_sci_irq();
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase + PM1_STS;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
+ fadt->pm1b_cnt_blk = 0x0;
+
+ fadt->gpe0_blk = pmbase + GPE0_STS;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+
+ /* GPE0 STS/EN pairs each 32 bits wide. */
+ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
+
+ fadt->flush_size = 0x400; /* twice of cache size */
+ fadt->flush_stride = 0x10; /* Cache line width */
+ fadt->duty_offset = 1;
+ fadt->day_alrm = 0xd;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+
[PATCH v4 28/59] acpi: Add more support for generating processor tables
This adds tables relating to P-States and C-States.
Signed-off-by: Simon Glass
---
(no changes since v1)
include/acpi/acpigen.h | 162 +++
lib/acpi/acpigen.c | 167 +++
test/dm/acpigen.c | 294 +
3 files changed, 623 insertions(+)
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 3a2c6339d5e..976f4dbb9af 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -10,8 +10,10 @@
#ifndef __ACPI_ACPIGEN_H
#define __ACPI_ACPIGEN_H
+#include
#include
+struct acpi_cstate;
struct acpi_ctx;
struct acpi_gen_regaddr;
struct acpi_gpio;
@@ -87,6 +89,53 @@ enum psd_coord {
HW_ALL = 0xfe
};
+/**
+ * enum csd_coord - Coordination types for C-states
+ *
+ * The type of coordination that exists (hardware) or is required (software) as
+ * a result of the underlying hardware dependency
+ */
+enum csd_coord {
+ CSD_HW_ALL = 0xfe,
+};
+
+/**
+ * struct acpi_cstate - Information about a C-State
+ *
+ * @ctype: C State type (1=C1, 2=C2, 3=C3)
+ * @latency: Worst-case latency to enter and exit the C State (in uS)
+ * @power: Average power consumption of the processor when in this C-State (mW)
+ * @resource: Register to read to place the processor in this state
+ */
+struct acpi_cstate {
+ uint ctype;
+ uint latency;
+ uint power;
+ struct acpi_gen_regaddr resource;
+};
+
+/**
+ * struct acpi_tstate - Information about a Throttling Supported State
+ *
+ * See ACPI v6.3 section 8.4.5.2: _TSS (Throttling Supported States)
+ *
+ * @percent: Percent of the core CPU operating frequency that will be
+ * available when this throttling state is invoked
+ * @power: Throttling state’s maximum power dissipation (mw)
+ * @latency: Worst-case latency (uS) that the CPU is unavailable during a
+ * transition from any throttling state to this throttling state
+ * @control: Value to be written to the Processor Control Register
+ * (THROTTLE_CTRL) to initiate a transition to this throttling state
+ * @status: Value in THROTTLE_STATUS when in this state
+ */
+struct acpi_tstate {
+ uint percent;
+ uint power;
+ uint latency;
+ uint control;
+ uint status;
+};
+
/**
* acpigen_get_current() - Get the current ACPI code output pointer
*
@@ -816,4 +865,117 @@ void acpigen_write_processor_package(struct acpi_ctx
*ctx, const char *name,
*/
void acpigen_write_processor_cnot(struct acpi_ctx *ctx, const uint num_cores);
+/**
+ * acpigen_write_ppc() - generates a function returning max P-states
+ *
+ * @ctx: ACPI context pointer
+ * @num_pstates: Number of pstates to return
+ */
+void acpigen_write_ppc(struct acpi_ctx *ctx, uint num_pstates);
+
+/**
+ * acpigen_write_ppc() - generates a function returning PPCM
+ *
+ * This returns the maximum number of supported P-states, as saved in the
+ * variable PPCM
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_ppc_nvs(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_tpc() - Write a _TPC method that returns the TPC limit
+ *
+ * @ctx: ACPI context pointer
+ * @gnvs_tpc_limit: Variable that holds the TPC limit
+ */
+void acpigen_write_tpc(struct acpi_ctx *ctx, const char *gnvs_tpc_limit);
+
+/**
+ * acpigen_write_pss_package() - Write a PSS package
+ *
+ * See ACPI v6.3 section 8.4.6: Processor Performance Control
+ *
+ * @ctx: ACPI context pointer
+ * @corefreq: CPU core frequency in MHz
+ * @translat: worst-case latency in uS that the CPU is unavailable during a
+ * transition from any performance state to this performance state
+ * @busmlat: worst-case latency in microseconds that Bus Masters are prevented
+ * from accessing memory during a transition from any performance state to
+ * this performance state
+ * @control: Value to write to PERF_CTRL to move to this performance state
+ * @status: Expected PERF_STATUS value when in this state
+ */
+void acpigen_write_pss_package(struct acpi_ctx *ctx, uint corefreq, uint power,
+ uint translat, uint busmlat, uint control,
+ uint status);
+
+/**
+ * acpigen_write_psd_package() - Write a PSD package
+ *
+ * Writes a P-State dependency package
+ *
+ * See ACPI v6.3 section 8.4.6.5: _PSD (P-State Dependency)
+ *
+ * @ctx: ACPI context pointer
+ * @domain: Dependency domain number to which this P state entry belongs
+ * @numprocs: Number of processors belonging to the domain for this logical
+ * processor’s P-states
+ * @coordtype: Coordination type
+ */
+void acpigen_write_psd_package(struct acpi_ctx *ctx, uint domain, uint
numprocs,
+ enum psd_coord coordtype);
+
+/**
+ * acpigen_write_cst_package() - Write a _CST package
+ *
+ * See ACPI v6.3 section 8.4.2.1: _CST (C States)
+ *
+ * @ctx: ACPI context pointer
+ * @entry: Array of entries
+ * @nentries; Number of entries
+ */
+void acpigen_write_cst_package(struct acpi_ctx *ctx,
+
[PATCH v4 30/59] x86: Support Atom SoCs using SWSMISCI rather than the SWSCI
Some Atom SoCs use SWSMISCI for SMI control. Add a Kconfig to select this. It is used on Apollo Lake. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/Kconfig| 6 ++ arch/x86/cpu/apollolake/Kconfig | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 495629d32ed..eddf2a774ef 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1017,4 +1017,10 @@ config INTEL_GENERIC_WIFI network functionality. It is only here to generate the ACPI tables required by Linux. +config INTEL_GMA_SWSMISCI + bool + help + Select this option for Atom-based platforms which use the SWSMISCI + register (0xe0) rather than the SWSCI register (0xe8). + endmenu diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index 319f12684b7..35a425cd1bc 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -17,6 +17,7 @@ config INTEL_APOLLOLAKE select PCH_SUPPORT select P2SB select SMP_AP_WORK + select INTEL_GMA_SWSMISCI select ACPI_GNVS_EXTERNAL imply ENABLE_MRC_CACHE imply AHCI_PCI -- 2.28.0.681.g6f77f65b4e-goog
[PATCH v4 32/59] x86: apl: Allow reading hostbridge base addresses
Add a few functions to permit reading of various useful base addresses
provided by the hostbridge.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Add comments
arch/x86/cpu/apollolake/hostbridge.c | 27
.../include/asm/arch-apollolake/systemagent.h | 31 +++
2 files changed, 58 insertions(+)
diff --git a/arch/x86/cpu/apollolake/hostbridge.c
b/arch/x86/cpu/apollolake/hostbridge.c
index cb46ec6c0bb..056f7e57a9a 100644
--- a/arch/x86/cpu/apollolake/hostbridge.c
+++ b/arch/x86/cpu/apollolake/hostbridge.c
@@ -40,7 +40,9 @@ enum {
PCIEXBAR_PCIEXBAREN = 1 << 0,
+ BGSM= 0xb4, /* Base GTT Stolen Memory */
TSEG= 0xb8, /* TSEG base */
+ TOLUD = 0xbc,
};
static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
@@ -165,6 +167,31 @@ static int apl_hostbridge_probe(struct udevice *dev)
return 0;
}
+static ulong sa_read_reg(struct udevice *dev, int reg)
+{
+ u32 val;
+
+ /* All regions concerned for have 1 MiB alignment */
+ dm_pci_read_config32(dev, BGSM, );
+
+ return ALIGN_DOWN(val, 1 << 20);
+}
+
+ulong sa_get_tolud_base(struct udevice *dev)
+{
+ return sa_read_reg(dev, TOLUD);
+}
+
+ulong sa_get_gsm_base(struct udevice *dev)
+{
+ return sa_read_reg(dev, BGSM);
+}
+
+ulong sa_get_tseg_base(struct udevice *dev)
+{
+ return sa_read_reg(dev, TSEG);
+}
+
static const struct udevice_id apl_hostbridge_ids[] = {
{ .compatible = "intel,apl-hostbridge" },
{ }
diff --git a/arch/x86/include/asm/arch-apollolake/systemagent.h
b/arch/x86/include/asm/arch-apollolake/systemagent.h
index 9e7bd62751a..788a63d7999 100644
--- a/arch/x86/include/asm/arch-apollolake/systemagent.h
+++ b/arch/x86/include/asm/arch-apollolake/systemagent.h
@@ -35,4 +35,35 @@
*/
void enable_bios_reset_cpl(void);
+/**
+ * sa_get_tolud_base() - Get the TOLUD base address
+ *
+ * This returns the Top Of Low Useable DRAM, marking the top of usable DRAM
+ * below 4GB
+ *
+ * @dev: hostbridge device
+ * @return TOLUD address
+ */
+ulong sa_get_tolud_base(struct udevice *dev);
+
+/**
+ * sa_get_gsm_base() - Get the GSM base address
+ *
+ * This returns the base of GTT Stolen Memory, marking the start of memory used
+ * for Graphics Translation Tables.
+ *
+ * @dev: hostbridge device
+ * @return GSM address
+ */
+ulong sa_get_gsm_base(struct udevice *dev);
+
+/**
+ * sa_get_tseg_base() - Get the TSEG base address
+ *
+ * This returns the top address of DRAM available below 4GB
+ *
+ * @return TSEG base
+ */
+ulong sa_get_tseg_base(struct udevice *dev);
+
#endif
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 26/59] acpi: Add support for generating processor tables
ACPI has a number of CPU-related tables. Add utility functions to write
out the basic packages.
Signed-off-by: Simon Glass
---
(no changes since v1)
include/acpi/acpigen.h | 39 +++
lib/acpi/acpigen.c | 55 +
test/dm/acpigen.c | 106 +
3 files changed, 200 insertions(+)
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index c412898169e..3a2c6339d5e 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -64,7 +64,9 @@ enum {
OR_OP = 0x7d,
NOT_OP = 0x80,
DEVICE_OP = 0x82,
+ PROCESSOR_OP= 0x83,
POWER_RES_OP= 0x84,
+ NOTIFY_OP = 0x86,
LEQUAL_OP = 0x93,
TO_BUFFER_OP= 0x96,
TO_INTEGER_OP = 0x99,
@@ -777,4 +779,41 @@ void acpigen_write_dsm_uuid_end(struct acpi_ctx *ctx);
*/
void acpigen_write_dsm_end(struct acpi_ctx *ctx);
+/**
+ * acpigen_write_processor() - Write a Processor package
+ *
+ * This emits a Processor package header with the required information. The
+ * caller must complete the information and call acpigen_pop_len() at the end
+ *
+ * @ctx: ACPI context pointer
+ * @cpuindex: CPU number
+ * @pblock_addr: PBlk system IO address
+ * @pblock_len: PBlk length
+ */
+void acpigen_write_processor(struct acpi_ctx *ctx, uint cpuindex,
+u32 pblock_addr, uint pblock_len);
+
+/**
+ * acpigen_write_processor_package() - Write a package containing the
processors
+ *
+ * The package containins the name of each processor in the SoC
+ *
+ * @ctx: ACPI context pointer
+ * @name: Package name (.e.g "PPKG")
+ * @first_core: Number of the first core (e.g. 0)
+ * @core_count: Number of cores (e.g. 4)
+ */
+void acpigen_write_processor_package(struct acpi_ctx *ctx, const char *name,
+uint first_core, uint core_count);
+
+/**
+ * acpigen_write_processor_cnot() - Write a processor notification method
+ *
+ * This writes a method that notifies all CPU cores
+ *
+ * @ctx: ACPI context pointer
+ * @num_cores: Number of CPU cores
+ */
+void acpigen_write_processor_cnot(struct acpi_ctx *ctx, const uint num_cores);
+
#endif
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index d859f378413..b9985075cde 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -17,6 +17,9 @@
#include
#include
+/* CPU path format */
+#define ACPI_CPU_STRING "\\_PR.CP%02d"
+
u8 *acpigen_get_current(struct acpi_ctx *ctx)
{
return ctx->current;
@@ -340,6 +343,58 @@ void acpigen_write_method_serialized(struct acpi_ctx *ctx,
const char *name,
ACPI_METHOD_SERIALIZED_MASK);
}
+void acpigen_write_processor(struct acpi_ctx *ctx, uint cpuindex,
+u32 pblock_addr, uint pblock_len)
+{
+ /*
+* Processor (\_PR.CPnn, cpuindex, pblock_addr, pblock_len)
+* {
+*/
+ char pscope[16];
+
+ acpigen_emit_ext_op(ctx, PROCESSOR_OP);
+ acpigen_write_len_f(ctx);
+
+ snprintf(pscope, sizeof(pscope), ACPI_CPU_STRING, cpuindex);
+ acpigen_emit_namestring(ctx, pscope);
+ acpigen_emit_byte(ctx, cpuindex);
+ acpigen_emit_dword(ctx, pblock_addr);
+ acpigen_emit_byte(ctx, pblock_len);
+}
+
+void acpigen_write_processor_package(struct acpi_ctx *ctx,
+const char *const name,
+const uint first_core,
+const uint core_count)
+{
+ uint i;
+ char pscope[16];
+
+ acpigen_write_name(ctx, name);
+ acpigen_write_package(ctx, core_count);
+ for (i = first_core; i < first_core + core_count; ++i) {
+ snprintf(pscope, sizeof(pscope), ACPI_CPU_STRING, i);
+ acpigen_emit_namestring(ctx, pscope);
+ }
+ acpigen_pop_len(ctx);
+}
+
+void acpigen_write_processor_cnot(struct acpi_ctx *ctx, const uint num_cores)
+{
+ int core_id;
+
+ acpigen_write_method(ctx, "\\_PR.CNOT", 1);
+ for (core_id = 0; core_id < num_cores; core_id++) {
+ char buffer[30];
+
+ snprintf(buffer, sizeof(buffer), ACPI_CPU_STRING, core_id);
+ acpigen_emit_byte(ctx, NOTIFY_OP);
+ acpigen_emit_namestring(ctx, buffer);
+ acpigen_emit_byte(ctx, ARG0_OP);
+ }
+ acpigen_pop_len(ctx);
+}
+
void acpigen_write_device(struct acpi_ctx *ctx, const char *name)
{
acpigen_emit_ext_op(ctx, DEVICE_OP);
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 381fcb97022..74b7e23aab3 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -1344,3 +1344,109 @@ static int dm_test_acpi_write_i2c_dsm(struct
unit_test_state *uts)
}
DM_TEST(dm_test_acpi_write_i2c_dsm, 0);
+/* Test emitting a processor */
+static int
[PATCH v4 25/59] x86: acpi: Support generation of the DBG2 table
Add an implementation of the DBG2 (Debug Port Table 2) ACPI table.
Adjust one of the header includes to be in the correct order, before
adding more.
Note that the DBG2 table is generic but the PCI UART is x86-specific at
present since it assumes an ns16550 UART. It can be generalised later
if necessary.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Move ASL_REVISION define into this patch
- Move acpi_create_dbg2() into generic code
- Update commit message
arch/x86/include/asm/acpi_table.h | 11 ++
arch/x86/lib/acpi_table.c | 41
include/acpi/acpi_table.h | 40 +++
lib/acpi/acpi_table.c | 64 +++
4 files changed, 156 insertions(+)
diff --git a/arch/x86/include/asm/acpi_table.h
b/arch/x86/include/asm/acpi_table.h
index 7047ee6c772..1b7ff509516 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -46,6 +46,17 @@ u32 acpi_fill_csrt(u32 current);
*/
int acpi_write_hpet(struct acpi_ctx *ctx);
+/**
+ * acpi_write_dbg2_pci_uart() - Write out a DBG2 table
+ *
+ * @ctx: Current ACPI context
+ * @dev: Debug UART device to describe
+ * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS)
+ * @return 0 if OK, -ve on error
+ */
+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
+uint access_size);
+
/**
* acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table
*
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 0080c96cfe7..e257c789838 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -588,3 +589,43 @@ int acpi_write_hpet(struct acpi_ctx *ctx)
return 0;
}
+
+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
+uint access_size)
+{
+ struct acpi_dbg2_header *dbg2 = ctx->current;
+ char path[ACPI_PATH_MAX];
+ struct acpi_gen_regaddr address;
+ phys_addr_t addr;
+ int ret;
+
+ if (!device_active(dev)) {
+ log_info("Device not enabled\n");
+ return -EACCES;
+ }
+ /*
+* PCI devices don't remember their resource allocation information in
+* U-Boot at present. We assume that MMIO is used for the UART and that
+* the address space is 32 bytes: ns16550 uses 8 registers of up to
+* 32-bits each. This is only for debugging so it is not a big deal.
+*/
+ addr = dm_pci_read_bar32(dev, 0);
+ printf("UART addr %lx\n", (ulong)addr);
+
+ memset(, '\0', sizeof(address));
+ address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
+ address.addrl = (uint32_t)addr;
+ address.addrh = (uint32_t)((addr >> 32) & 0x);
+ address.access_size = access_size;
+
+ ret = acpi_device_path(dev, path, sizeof(path));
+ if (ret)
+ return log_msg_ret("path", ret);
+ acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
+ACPI_DBG2_16550_COMPATIBLE, , 0x1000, path);
+
+ acpi_inc_align(ctx, dbg2->header.length);
+ acpi_add_table(ctx, dbg2);
+
+ return 0;
+}
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index f8140446a59..c826a797f5b 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -448,6 +448,29 @@ struct __packed acpi_dmar {
#define ACPI_DBG2_UNKNOWN 0x00FF
+/* DBG2: Microsoft Debug Port Table 2 header */
+struct __packed acpi_dbg2_header {
+ struct acpi_table_header header;
+ u32 devices_offset;
+ u32 devices_count;
+};
+
+/* DBG2: Microsoft Debug Port Table 2 device entry */
+struct __packed acpi_dbg2_device {
+ u8 revision;
+ u16 length;
+ u8 address_count;
+ u16 namespace_string_length;
+ u16 namespace_string_offset;
+ u16 oem_data_length;
+ u16 oem_data_offset;
+ u16 port_type;
+ u16 port_subtype;
+ u8 reserved[2];
+ u16 base_address_offset;
+ u16 address_size_offset;
+};
+
/* SPCR (Serial Port Console Redirection table) */
struct __packed acpi_spcr {
struct acpi_table_header header;
@@ -522,6 +545,23 @@ int acpi_get_table_revision(enum acpi_tables table);
*/
int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags);
+/**
+ * acpi_create_dbg2() - Create a DBG2 table
+ *
+ * This table describes how to access the debug UART
+ *
+ * @dbg2: Place to put information
+ * @port_type: Serial port type (see ACPI_DBG2_...)
+ * @port_subtype: Serial port sub-type (see ACPI_DBG2_...)
+ * @address: ACPI address of port
+ * @address_size: Size of address space
+ * @device_path: Path of device (created using acpi_device_path())
+ */
+void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,
+ int
[PATCH v4 24/59] x86: acpi: Support generation of the HPET table
Add an implementation of the HPET (High Precision Event Timer) ACPI
table. Since this is x86-specific, put it in an x86-specific file
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Put this code in an x86-specific place and update commit message
arch/x86/include/asm/acpi_table.h | 10 ++
arch/x86/lib/acpi_table.c | 59 +++
include/acpi/acpi_table.h | 31 +++-
3 files changed, 91 insertions(+), 9 deletions(-)
diff --git a/arch/x86/include/asm/acpi_table.h
b/arch/x86/include/asm/acpi_table.h
index 733085c1785..7047ee6c772 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -36,6 +36,16 @@ int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig
*mmconfig, u32 base,
u32 acpi_fill_mcfg(u32 current);
u32 acpi_fill_csrt(u32 current);
+/**
+ * acpi_write_hpet() - Write out a HPET table
+ *
+ * Write out the table for High-Precision Event Timers
+ *
+ * @ctx: Current ACPI context
+ * @return 0 if OK, -ve on error
+ */
+int acpi_write_hpet(struct acpi_ctx *ctx);
+
/**
* acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table
*
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 36ef3e5f0b7..0080c96cfe7 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -529,3 +529,62 @@ ulong acpi_get_rsdp_addr(void)
{
return acpi_rsdp_addr;
}
+
+/**
+ * acpi_write_hpet() - Write out a HPET table
+ *
+ * Write out the table for High-Precision Event Timers
+ *
+ * @hpet: Place to put HPET table
+ */
+static int acpi_create_hpet(struct acpi_hpet *hpet)
+{
+ struct acpi_table_header *header = >header;
+ struct acpi_gen_regaddr *addr = >addr;
+
+ /*
+* See IA-PC HPET (High Precision Event Timers) Specification v1.0a
+*
https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/software-developers-hpet-spec-1-0a.pdf
+*/
+ memset((void *)hpet, '\0', sizeof(struct acpi_hpet));
+
+ /* Fill out header fields. */
+ acpi_fill_header(header, "HPET");
+
+ header->aslc_revision = ASL_REVISION;
+ header->length = sizeof(struct acpi_hpet);
+ header->revision = acpi_get_table_revision(ACPITAB_HPET);
+
+ /* Fill out HPET address */
+ addr->space_id = 0; /* Memory */
+ addr->bit_width = 64;
+ addr->bit_offset = 0;
+ addr->addrl = CONFIG_HPET_ADDRESS & 0x;
+ addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32;
+
+ hpet->id = *(u32 *)CONFIG_HPET_ADDRESS;
+ hpet->number = 0;
+ hpet->min_tick = 0; /* HPET_MIN_TICKS */
+
+ header->checksum = table_compute_checksum(hpet,
+ sizeof(struct acpi_hpet));
+
+ return 0;
+}
+
+int acpi_write_hpet(struct acpi_ctx *ctx)
+{
+ struct acpi_hpet *hpet;
+ int ret;
+
+ log_debug("ACPI:* HPET\n");
+
+ hpet = ctx->current;
+ acpi_inc_align(ctx, sizeof(struct acpi_hpet));
+ acpi_create_hpet(hpet);
+ ret = acpi_add_table(ctx, hpet);
+ if (ret)
+ return log_msg_ret("add", ret);
+
+ return 0;
+}
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index fe9b29f3f82..f8140446a59 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -20,6 +20,9 @@
#define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */
#define ASLC_ID"INTL" /* Intel ASL Compiler */
+/* TODO(s...@chromium.org): Figure out how to get compiler revision */
+#define ASL_REVISION 0
+
#define ACPI_RSDP_REV_ACPI_1_0 0
#define ACPI_RSDP_REV_ACPI_2_0 2
@@ -56,6 +59,15 @@ struct __packed acpi_table_header {
u32 aslc_revision; /* ASL compiler revision number */
};
+struct acpi_gen_regaddr {
+ u8 space_id;/* Address space ID */
+ u8 bit_width; /* Register size in bits */
+ u8 bit_offset; /* Register bit offset */
+ u8 access_size; /* Access size */
+ u32 addrl; /* Register address, low 32 bits */
+ u32 addrh; /* Register address, high 32 bits */
+};
+
/* A maximum number of 32 ACPI tables ought to be enough for now */
#define MAX_ACPI_TABLES32
@@ -71,6 +83,16 @@ struct acpi_xsdt {
u64 entry[MAX_ACPI_TABLES];
};
+/* HPET timers */
+struct __packed acpi_hpet {
+ struct acpi_table_header header;
+ u32 id;
+ struct acpi_gen_regaddr addr;
+ u8 number;
+ u16 min_tick;
+ u8 attributes;
+};
+
/* FADT Preferred Power Management Profile */
enum acpi_pm_profile {
ACPI_PM_UNSPECIFIED = 0,
@@ -138,15 +160,6 @@ enum acpi_address_space_size {
ACPI_ACCESS_SIZE_QWORD_ACCESS
};
-struct acpi_gen_regaddr {
- u8 space_id;/* Address space ID */
- u8 bit_width; /* Register size in bits */
- u8 bit_offset; /* Register bit
[PATCH v4 20/59] x86: Add some definitions for SMM
U-Boot does not support SMM (System Management Mode) at present, but needs a few definitions to correctly set up the ACPI table. Add these. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/include/asm/smm.h | 27 +++ 1 file changed, 27 insertions(+) create mode 100644 arch/x86/include/asm/smm.h diff --git a/arch/x86/include/asm/smm.h b/arch/x86/include/asm/smm.h new file mode 100644 index 000..1e539fda067 --- /dev/null +++ b/arch/x86/include/asm/smm.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SMM definitions (U-Boot does not support SMM itself) + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2019 Google LLC + * + * Modified from coreboot smm.h + */ + +#ifndef _ASM_SMM_H +#define _ASM_SMM_H + +#define APM_CNT0xb2 +#define APM_CNT_CST_CONTROL0x85 +#define APM_CNT_PST_CONTROL0x80 +#define APM_CNT_ACPI_DISABLE 0x1e +#define APM_CNT_ACPI_ENABLE0xe1 +#define APM_CNT_MBI_UPDATE 0xeb +#define APM_CNT_GNVS_UPDATE0xea +#define APM_CNT_FINALIZE 0xcb +#define APM_CNT_LEGACY 0xcc +#define APM_CNT_SMMSTORE 0xed +#define APM_CNT_ELOG_GSMI 0xef +#define APM_STS0xb3 + +#endif /* _ASM_SMM_H */ -- 2.28.0.681.g6f77f65b4e-goog
[PATCH v4 23/59] x86: Add a few common Intel CPU functions
Add functions to query CPU information, needed for ACPI.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Add more comments and rename cpu_get_bus_clock to cpu_get_bus_clock_khz()
arch/x86/cpu/intel_common/cpu.c | 64 +++
arch/x86/include/asm/cpu_common.h | 49 +++
include/acpi/acpigen.h| 12 ++
3 files changed, 125 insertions(+)
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index 509730aea96..cb4ef84013a 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -227,3 +228,66 @@ void cpu_set_eist(bool eist_status)
msr.lo &= ~MISC_ENABLE_ENHANCED_SPEEDSTEP;
msr_write(MSR_IA32_MISC_ENABLE, msr);
}
+
+int cpu_get_coord_type(void)
+{
+ return HW_ALL;
+}
+
+int cpu_get_min_ratio(void)
+{
+ msr_t msr;
+
+ /* Get bus ratio limits and calculate clock speeds */
+ msr = msr_read(MSR_PLATFORM_INFO);
+
+ return (msr.hi >> 8) & 0xff;/* Max Efficiency Ratio */
+}
+
+int cpu_get_max_ratio(void)
+{
+ u32 ratio_max;
+ msr_t msr;
+
+ if (cpu_config_tdp_levels()) {
+ /* Set max ratio to nominal TDP ratio */
+ msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+ ratio_max = msr.lo & 0xff;
+ } else {
+ msr = msr_read(MSR_PLATFORM_INFO);
+ /* Max Non-Turbo Ratio */
+ ratio_max = (msr.lo >> 8) & 0xff;
+ }
+
+ return ratio_max;
+}
+
+int cpu_get_bus_clock_khz(void)
+{
+ /*
+* CPU bus clock is set by default here to 100MHz. This function returns
+* the bus clock in KHz.
+*/
+ return INTEL_BCLK_MHZ * 1000;
+}
+
+int cpu_get_power_max(void)
+{
+ int power_unit;
+ msr_t msr;
+
+ msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
+ power_unit = 2 << ((msr.lo & 0xf) - 1);
+ msr = msr_read(MSR_PKG_POWER_SKU);
+
+ return (msr.lo & 0x7fff) * 1000 / power_unit;
+}
+
+int cpu_get_max_turbo_ratio(void)
+{
+ msr_t msr;
+
+ msr = msr_read(MSR_TURBO_RATIO_LIMIT);
+
+ return msr.lo & 0xff;
+}
diff --git a/arch/x86/include/asm/cpu_common.h
b/arch/x86/include/asm/cpu_common.h
index cdd99a90b76..a7b7112d417 100644
--- a/arch/x86/include/asm/cpu_common.h
+++ b/arch/x86/include/asm/cpu_common.h
@@ -128,4 +128,53 @@ void cpu_set_eist(bool eist_status);
*/
void cpu_set_p_state_to_turbo_ratio(void);
+/**
+ * cpu_get_coord_type() - Get the type of coordination for P-State transition
+ *
+ * See ACPI spec v6.3 section 8.4.6.5 _PSD (P-State Dependency)
+ *
+ * @return HW_ALL (always)
+ */
+int cpu_get_coord_type(void);
+
+/**
+ * cpu_get_min_ratio() - get minimum support frequency ratio for CPU
+ *
+ * @return minimum ratio
+ */
+int cpu_get_min_ratio(void);
+
+/**
+ * cpu_get_max_ratio() - get nominal TDP ration or max non-turbo ratio
+ *
+ * If a nominal TDP ratio is available, it is returned. Otherwise this returns
+ * the maximum non-turbo frequency ratio for this processor
+ *
+ * @return max ratio
+ */
+int cpu_get_max_ratio(void);
+
+/**
+ * cpu_get_bus_clock_khz() - Get the bus clock frequency in KHz
+ *
+ * This is the value the clock ratio is multiplied with
+ *
+ * @return bus-block frequency in KHz
+ */
+int cpu_get_bus_clock_khz(void);
+
+/**
+ * cpu_get_power_max() - Get maximum CPU TDP
+ *
+ * @return maximum CPU TDP (Thermal-design power) in mW
+ */
+int cpu_get_power_max(void);
+
+/**
+ * cpu_get_max_turbo_ratio() - Get maximum turbo ratio
+ *
+ * @return maximum ratio
+ */
+int cpu_get_max_turbo_ratio(void);
+
#endif
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 34b3115bc9c..c412898169e 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -73,6 +73,18 @@ enum {
RETURN_OP = 0xa4,
};
+/**
+ * enum psd_coord - Coordination types for P-states
+ *
+ * The type of coordination that exists (hardware) or is required (software) as
+ * a result of the underlying hardware dependency
+ */
+enum psd_coord {
+ SW_ALL = 0xfc,
+ SW_ANY = 0xfd,
+ HW_ALL = 0xfe
+};
+
/**
* acpigen_get_current() - Get the current ACPI code output pointer
*
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 22/59] x86: apl: Update iomap for ACPI
Add some more definitions to the iomap. These will be used by ACPI-generation code as well as the device tree. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/include/asm/arch-apollolake/iomap.h | 16 1 file changed, 16 insertions(+) diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h index 4ce10170558..21c5f33021a 100644 --- a/arch/x86/include/asm/arch-apollolake/iomap.h +++ b/arch/x86/include/asm/arch-apollolake/iomap.h @@ -11,11 +11,27 @@ /* Put p2sb at 0xd000 in TPL */ #define IOMAP_P2SB_BAR 0xd000 +#define IOMAP_P2SB_SIZE0x1000 #define IOMAP_SPI_BASE 0xfe01 #define IOMAP_ACPI_BASE0x400 #define IOMAP_ACPI_SIZE0x100 +#define ACPI_BASE_ADDRESS IOMAP_ACPI_BASE + +#define PMC_BAR0 0xfe042000 + +#define MCH_BASE_ADDRESS 0xfed1 +#define MCH_SIZE 0x8000 + +#ifdef __ACPI__ +#define HPET_BASE_ADDRESS 0xfed0 + +#define SRAM_BASE_00xfe90 +#define SRAM_SIZE_0(8 * KiB) +#define SRAM_BASE_20xfe902000 +#define SRAM_SIZE_2(4 * KiB) +#endif /* * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial -- 2.28.0.681.g6f77f65b4e-goog
[PATCH v4 21/59] x86: apl: Add power-management definitions
Add SCI and power-state definitions required by ACPI tables. Fix the
license to match the original source file.
Als update the guard on acpi_pmc.h to avoid an error when buiding ASL.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Use SHIFT and MASK for defines
arch/x86/include/asm/arch-apollolake/pm.h | 40 ++-
include/power/acpi_pmc.h | 4 +--
2 files changed, 41 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/arch-apollolake/pm.h
b/arch/x86/include/asm/arch-apollolake/pm.h
index 6718290c4fe..9a8d971e910 100644
--- a/arch/x86/include/asm/arch-apollolake/pm.h
+++ b/arch/x86/include/asm/arch-apollolake/pm.h
@@ -1,12 +1,15 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015-2016 Intel Corp.
* (Written by Lance Zhao for Intel Corp.)
+ * Copyright 2019 Google LLC
*/
#ifndef _ASM_ARCH_PM_H
#define _ASM_ARCH_PM_H
+#include
+
#define PMC_GPE_SW_31_00
#define PMC_GPE_SW_63_32 1
#define PMC_GPE_NW_31_03
@@ -16,4 +19,39 @@
#define PMC_GPE_N_63_327
#define PMC_GPE_W_31_0 9
+#define IRQ_REG0x106c
+#define SCI_IRQ_SHIFT 24
+#define SCI_IRQ_MASK (0xff << SCI_IRQ_SHIFT)
+#define SCIS_IRQ9 9
+#define SCIS_IRQ10 10
+#define SCIS_IRQ11 11
+#define SCIS_IRQ20 20
+#define SCIS_IRQ21 21
+#define SCIS_IRQ22 22
+#define SCIS_IRQ23 23
+
+/* P-state configuration */
+#define PSS_MAX_ENTRIES8
+#define PSS_RATIO_STEP 2
+#define PSS_LATENCY_TRANSITION 10
+#define PSS_LATENCY_BUSMASTER 10
+
+#ifndef __ASSEMBLY__
+/* Track power state from reset to log events */
+struct __packed chipset_power_state {
+ u16 pm1_sts;
+ u16 pm1_en;
+ u32 pm1_cnt;
+ u32 gpe0_sts[GPE0_REG_MAX];
+ u32 gpe0_en[GPE0_REG_MAX];
+ u16 tco1_sts;
+ u16 tco2_sts;
+ u32 prsts;
+ u32 gen_pmcon1;
+ u32 gen_pmcon2;
+ u32 gen_pmcon3;
+ u32 prev_sleep_state;
+};
+#endif /* !__ASSEMBLY__ */
+
#endif
diff --git a/include/power/acpi_pmc.h b/include/power/acpi_pmc.h
index 5fbf7451369..88b71a4 100644
--- a/include/power/acpi_pmc.h
+++ b/include/power/acpi_pmc.h
@@ -6,7 +6,7 @@
#ifndef __ACPI_PMC_H
#define __ACPI_PMC_H
-#ifndef __ACPI__
+#ifndef __ASSEMBLY__
enum {
GPE0_REG_MAX= 4,
@@ -194,6 +194,6 @@ void pmc_dump_info(struct udevice *dev);
*/
int pmc_gpe_init(struct udevice *dev);
-#endif /* !__ACPI__ */
+#endif /* !__ASSEMBLY__ */
#endif
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 14/59] dm: acpi: Use correct GPIO polarity type in acpi_dp_add_gpio()
This function currently accepts the IRQ-polarity type. Fix it to use the
GPIO type instead.
Signed-off-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- add new patch to fix polarity type in acpi_dp_add_gpio()
drivers/sound/max98357a.c | 2 +-
include/acpi/acpi_dp.h| 2 +-
lib/acpi/acpi_dp.c| 4 ++--
test/dm/acpi_dp.c | 4 ++--
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c
index 841bc6ef682..827262d235c 100644
--- a/drivers/sound/max98357a.c
+++ b/drivers/sound/max98357a.c
@@ -81,7 +81,7 @@ static int max98357a_acpi_fill_ssdt(const struct udevice *dev,
dp = acpi_dp_new_table("_DSD");
acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0,
priv->sdmode_gpio.flags & GPIOD_ACTIVE_LOW ?
-ACPI_IRQ_ACTIVE_LOW : ACPI_IRQ_ACTIVE_HIGH);
+ACPI_GPIO_ACTIVE_LOW : ACPI_GPIO_ACTIVE_HIGH);
acpi_dp_add_integer(dp, "sdmode-delay",
dev_read_u32_default(dev, "sdmode-delay", 0));
acpi_dp_write(ctx, dp);
diff --git a/include/acpi/acpi_dp.h b/include/acpi/acpi_dp.h
index 0b514bce59c..5e539b1d218 100644
--- a/include/acpi/acpi_dp.h
+++ b/include/acpi/acpi_dp.h
@@ -221,7 +221,7 @@ struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const
char *name,
*/
struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name,
const char *ref, int index, int pin,
-enum acpi_irq_polarity polarity);
+enum acpi_gpio_polarity polarity);
/**
* acpi_dp_write() - Write Device Property hierarchy and clean up resources
diff --git a/lib/acpi/acpi_dp.c b/lib/acpi/acpi_dp.c
index 579cab47715..7e3e3259d8d 100644
--- a/lib/acpi/acpi_dp.c
+++ b/lib/acpi/acpi_dp.c
@@ -324,7 +324,7 @@ struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp
*dp, const char *name,
struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name,
const char *ref, int index, int pin,
-enum acpi_irq_polarity polarity)
+enum acpi_gpio_polarity polarity)
{
struct acpi_dp *gpio;
@@ -336,7 +336,7 @@ struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const
char *name,
if (!acpi_dp_add_reference(gpio, NULL, ref) ||
!acpi_dp_add_integer(gpio, NULL, index) ||
!acpi_dp_add_integer(gpio, NULL, pin) ||
- !acpi_dp_add_integer(gpio, NULL, polarity == ACPI_IRQ_ACTIVE_LOW))
+ !acpi_dp_add_integer(gpio, NULL, polarity == ACPI_GPIO_ACTIVE_LOW))
return NULL;
if (!acpi_dp_add_array(dp, gpio))
diff --git a/test/dm/acpi_dp.c b/test/dm/acpi_dp.c
index e0fa61263c8..44bcabda6bc 100644
--- a/test/dm/acpi_dp.c
+++ b/test/dm/acpi_dp.c
@@ -398,9 +398,9 @@ static int dm_test_acpi_dp_gpio(struct unit_test_state *uts)
/* Try a few different parameters */
ut_assertnonnull(acpi_dp_add_gpio(dp, "reset", TEST_REF, 0x23, 0x24,
- ACPI_IRQ_ACTIVE_HIGH));
+ ACPI_GPIO_ACTIVE_HIGH));
ut_assertnonnull(acpi_dp_add_gpio(dp, "allow", TEST_REF, 0, 0,
- ACPI_IRQ_ACTIVE_LOW));
+ ACPI_GPIO_ACTIVE_LOW));
ptr = acpigen_get_current(ctx);
ut_assertok(acpi_dp_write(ctx, dp));
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 19/59] x86: acpi: Add a common routine to write WiFi info
Intel WiFi chips can use a common routine to write the information needed
by linux. Add an implementation of this.
Enable it for coral.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Capitalise ACPI_OPS_PTR
- Use acpi,ddn instead of acpi,desc
arch/x86/Kconfig | 8 ++
arch/x86/cpu/intel_common/Makefile | 1 +
arch/x86/cpu/intel_common/generic_wifi.c | 120 +++
configs/chromebook_coral_defconfig | 1 +
4 files changed, 130 insertions(+)
create mode 100644 arch/x86/cpu/intel_common/generic_wifi.c
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 675a43e3b60..495629d32ed 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1009,4 +1009,12 @@ config INTEL_GMA_ACPI
connected to the device. Enable this option to create this
table so that graphics works correctly.
+config INTEL_GENERIC_WIFI
+ bool "Enable generation of ACPI tables for Intel WiFi"
+ help
+ Select this option to provide code to a build generic WiFi ACPI table
+ for Intel WiFi devices. This is not a WiFi driver and offers no
+ network functionality. It is only here to generate the ACPI tables
+ required by Linux.
+
endmenu
diff --git a/arch/x86/cpu/intel_common/Makefile
b/arch/x86/cpu/intel_common/Makefile
index 207d5413965..f1d1513a981 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -24,6 +24,7 @@ obj-y += cpu.o
obj-y += fast_spi.o
obj-y += lpc.o
obj-y += lpss.o
+obj-$(CONFIG_INTEL_GENERIC_WIFI) += generic_wifi.o
ifndef CONFIG_TARGET_EFI_APP
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
ifndef CONFIG_$(SPL_)X86_64
diff --git a/arch/x86/cpu/intel_common/generic_wifi.c
b/arch/x86/cpu/intel_common/generic_wifi.c
new file mode 100644
index 000..61ec5391b09
--- /dev/null
+++ b/arch/x86/cpu/intel_common/generic_wifi.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generic WiFi ACPI info
+ *
+ * Copyright 2019 Google LLC
+ * Modified from coreboot src/drivers/wifi/generic.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* WRDS Spec Revision */
+#define WRDS_REVISION 0x0
+
+/* EWRD Spec Revision */
+#define EWRD_REVISION 0x0
+
+/* WRDS Domain type */
+#define WRDS_DOMAIN_TYPE_WIFI 0x7
+
+/* EWRD Domain type */
+#define EWRD_DOMAIN_TYPE_WIFI 0x7
+
+/* WGDS Domain type */
+#define WGDS_DOMAIN_TYPE_WIFI 0x7
+
+/*
+ * WIFI ACPI NAME = "WF" + hex value of last 8 bits of dev_path_encode + '\0'
+ * The above representation returns unique and consistent name every time
+ * generate_wifi_acpi_name is invoked. The last 8 bits of dev_path_encode is
+ * chosen since it contains the bus address of the device.
+ */
+#define WIFI_ACPI_NAME_MAX_LEN 5
+
+/**
+ * struct generic_wifi_config - Data structure to contain common wifi config
+ * @wake: Wake pin for ACPI _PRW
+ * @maxsleep: Maximum sleep state to wake from
+ */
+struct generic_wifi_config {
+ unsigned int wake;
+ unsigned int maxsleep;
+};
+
+static int generic_wifi_fill_ssdt(struct acpi_ctx *ctx,
+ const struct udevice *dev,
+ const struct generic_wifi_config *config)
+{
+ char name[ACPI_NAME_MAX];
+ char path[ACPI_PATH_MAX];
+ pci_dev_t bdf;
+ u32 address;
+ int ret;
+
+ ret = acpi_device_path(dev_get_parent(dev), path, sizeof(path));
+ if (ret)
+ return log_msg_ret("path", ret);
+ ret = acpi_get_name(dev, name);
+ if (ret)
+ return log_msg_ret("name", ret);
+
+ /* Device */
+ acpigen_write_scope(ctx, path);
+ acpigen_write_device(ctx, name);
+ acpigen_write_name_integer(ctx, "_UID", 0);
+ acpigen_write_name_string(ctx, "_DDN",
+ dev_read_string(dev, "acpi,ddn"));
+
+ /* Address */
+ bdf = dm_pci_get_bdf(dev);
+ address = (PCI_DEV(bdf) << 16) | PCI_FUNC(bdf);
+ acpigen_write_name_dword(ctx, "_ADR", address);
+
+ /* Wake capabilities */
+ if (config)
+ acpigen_write_prw(ctx, config->wake, config->maxsleep);
+
+ acpigen_pop_len(ctx); /* Device */
+ acpigen_pop_len(ctx); /* Scope */
+
+ return 0;
+}
+
+static int intel_wifi_acpi_fill_ssdt(const struct udevice *dev,
+struct acpi_ctx *ctx)
+{
+ struct generic_wifi_config config;
+ bool have_config;
+ int ret;
+
+ ret = dev_read_u32(dev, "acpi,wake", );
+ have_config = !ret;
+ /* By default, all intel wifi chips wake from S3 */
+ config.maxsleep = 3;
+ ret = generic_wifi_fill_ssdt(ctx, dev, have_config ? : NULL);
+ if (ret)
+ return log_msg_ret("wifi", ret);
+
+ return 0;
+}
+
+struct acpi_ops wifi_acpi_ops = {
+ .fill_ssdt = intel_wifi_acpi_fill_ssdt,
+};
+
+static const struct
[PATCH v4 18/59] x86: apl: Support writing the IntelGraphicsMem table
This table is needed by the Linux graphics driver to handle graphics
correctly. Write it to ACPI.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Capitalise ACPI_OPS_PTR
- Don't build for SPL
arch/x86/Kconfig | 8 +
arch/x86/cpu/apollolake/Kconfig| 1 +
arch/x86/cpu/intel_common/Makefile | 4 +
arch/x86/cpu/intel_common/intel_opregion.c | 168 ++
arch/x86/include/asm/intel_opregion.h | 247 +
arch/x86/lib/fsp/fsp_graphics.c| 32 +++
include/bloblist.h | 1 +
7 files changed, 461 insertions(+)
create mode 100644 arch/x86/cpu/intel_common/intel_opregion.c
create mode 100644 arch/x86/include/asm/intel_opregion.h
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 680f26f1b8e..675a43e3b60 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1001,4 +1001,12 @@ config PCIEX_LENGTH_128MB
config PCIEX_LENGTH_64MB
bool
+config INTEL_GMA_ACPI
+ bool "Generate ACPI table for Intel GMA graphics"
+ help
+ The Intel GMA graphics driver in Linux expects an ACPI table
+ which describes the layout of the registers and the display
+ connected to the device. Enable this option to create this
+ table so that graphics works correctly.
+
endmenu
diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
index 16ac2b3f504..319f12684b7 100644
--- a/arch/x86/cpu/apollolake/Kconfig
+++ b/arch/x86/cpu/apollolake/Kconfig
@@ -48,6 +48,7 @@ config INTEL_APOLLOLAKE
imply CMD_CLK
imply CLK_INTEL
imply ACPI_GPE
+ imply INTEL_GMA_ACPI
if INTEL_APOLLOLAKE
diff --git a/arch/x86/cpu/intel_common/Makefile
b/arch/x86/cpu/intel_common/Makefile
index 374803b8760..207d5413965 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -9,6 +9,10 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
endif
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_INTEL_GMA_ACPI) += intel_opregion.o
+endif
+
ifdef CONFIG_INTEL_CAR_CQOS
obj-$(CONFIG_TPL_BUILD) += car2.o
ifndef CONFIG_SPL_BUILD
diff --git a/arch/x86/cpu/intel_common/intel_opregion.c
b/arch/x86/cpu/intel_common/intel_opregion.c
new file mode 100644
index 000..4e6c64d9aaa
--- /dev/null
+++ b/arch/x86/cpu/intel_common/intel_opregion.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Writing IntelGraphicsMem table for ACPI
+ *
+ * Copyright 2019 Google LLC
+ * Modified from coreboot src/soc/intel/gma/opregion.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+static char vbt_data[8 << 10];
+
+static int locate_vbt(char **vbtp, int *sizep)
+{
+ struct binman_entry vbt;
+ struct udevice *dev;
+ u32 vbtsig = 0;
+ int size;
+ int ret;
+
+ ret = binman_entry_find("intel-vbt", );
+ if (ret)
+ return log_msg_ret("find VBT", ret);
+ ret = uclass_first_device_err(UCLASS_SPI_FLASH, );
+ if (ret)
+ return log_msg_ret("find flash", ret);
+ size = vbt.size;
+ if (size > sizeof(vbt_data))
+ return log_msg_ret("vbt", -E2BIG);
+ ret = spi_flash_read_dm(dev, vbt.image_pos, size, vbt_data);
+ if (ret)
+ return log_msg_ret("read", ret);
+
+ memcpy(, vbt_data, sizeof(vbtsig));
+ if (vbtsig != VBT_SIGNATURE) {
+ log_err("Missing/invalid signature in VBT data file!\n");
+ return -EINVAL;
+ }
+
+ log_info("Found a VBT of %u bytes\n", size);
+ *sizep = size;
+ *vbtp = vbt_data;
+
+ return 0;
+}
+
+/* Write ASLS PCI register and prepare SWSCI register */
+static int intel_gma_opregion_register(struct udevice *dev, ulong opregion)
+{
+ int sci_reg;
+
+ if (!device_active(dev))
+ return -ENOENT;
+
+ /*
+* Intel BIOS Specification
+* Chapter 5.3.7 "Initialise Hardware State"
+*/
+ dm_pci_write_config32(dev, ASLS, opregion);
+
+ /*
+* Atom-based platforms use a combined SMI/SCI register,
+* whereas non-Atom platforms use a separate SCI register
+*/
+ if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI))
+ sci_reg = SWSMISCI;
+ else
+ sci_reg = SWSCI;
+
+ /*
+* Intel's Windows driver relies on this:
+* Intel BIOS Specification
+* Chapter 5.4 "ASL Software SCI Handler"
+*/
+ dm_pci_clrset_config16(dev, sci_reg, GSSCIE, SMISCISEL);
+
+ return 0;
+}
+
+int intel_gma_init_igd_opregion(struct udevice *dev,
+ struct igd_opregion *opregion)
+{
+ struct optionrom_vbt *vbt = NULL;
+ char *vbt_buf;
+ int vbt_size;
+ int ret;
+
+ ret = locate_vbt(_buf, _size);
+ if (ret) {
+
[PATCH v4 16/59] i2c: Add a generic driver to generate ACPI info
Many I2C devices produce roughly the same ACPI data with just things like
the GPIO/interrupt information being different.
This can be handled by a generic driver along with some information in the
device tree.
Add a generic i2c driver for this purpose.
Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
---
(no changes since v2)
Changes in v2:
- Fix incorrect space in enable-off-delay-ms
Changes in v1:
- Adjust implementation to match new ACPI GPIO generation
- Capitalise ACPI_OPS_PTR
- Rename acpi-probed to linux,probed
- Support hid-over-i2c separately as well
- Use acpi,ddn instead of acpi,desc
- Use updated acpi_device_write_dsm_i2c_hid() function
doc/device-tree-bindings/i2c/generic-acpi.txt | 42
drivers/i2c/Makefile | 3 +
drivers/i2c/acpi_i2c.c| 226 ++
drivers/i2c/acpi_i2c.h| 15 ++
drivers/i2c/i2c-uclass.c | 17 ++
include/acpi/acpi_device.h| 55 +
include/i2c.h | 23 ++
7 files changed, 381 insertions(+)
create mode 100644 doc/device-tree-bindings/i2c/generic-acpi.txt
create mode 100644 drivers/i2c/acpi_i2c.c
create mode 100644 drivers/i2c/acpi_i2c.h
diff --git a/doc/device-tree-bindings/i2c/generic-acpi.txt
b/doc/device-tree-bindings/i2c/generic-acpi.txt
new file mode 100644
index 000..3510a71b570
--- /dev/null
+++ b/doc/device-tree-bindings/i2c/generic-acpi.txt
@@ -0,0 +1,42 @@
+I2C generic device
+==
+
+This is used only to generate ACPI tables for an I2C device.
+
+Required properties :
+
+ - compatible : "i2c-chip";
+ - reg : I2C chip address
+ - acpi,hid : HID name for the device
+
+Optional properies in addition to device.txt:
+
+ - reset-gpios : GPIO used to assert reset to the device
+ - irq-gpios : GPIO used for interrupt (if Interrupt is not used)
+ - stop-gpios : GPIO used to stop the device
+ - interrupts-extended : Interrupt to use for the device
+ - reset-delay-ms : Delay after de-asserting reset, in ms
+ - reset-off-delay-ms : Delay after asserting reset (during power off)
+ - enable-delay-ms : Delay after asserting enable
+ - enable-off-delay-ms : Delay after de-asserting enable (during power off)
+ - stop-delay-ms : Delay after de-aserting stop
+ - stop-off-delay-ms : Delay after asserting stop (during power off)
+ - hid-descr-addr : HID register offset (for Human Interface Devices)
+
+Example
+---
+
+ elan-touchscreen@10 {
+ compatible = "i2c-chip";
+ reg = <0x10>;
+ acpi,hid = "ELAN0001";
+ acpi,ddn = "ELAN Touchscreen";
+ interrupts-extended = <_gpe GPIO_21_IRQ
+ IRQ_TYPE_EDGE_FALLING>;
+ linux,probed;
+ reset-gpios = <_n GPIO_36 GPIO_ACTIVE_HIGH>;
+ reset-delay-ms = <20>;
+ enable-gpios = <_n GPIO_152 GPIO_ACTIVE_HIGH>;
+ enable-delay-ms = <1>;
+ acpi,has-power-resource;
+ };
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index f7b27864488..bd248cbf52b 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -3,6 +3,9 @@
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
obj-$(CONFIG_DM_I2C) += i2c-uclass.o
+ifdef CONFIG_ACPIGEN
+obj-$(CONFIG_DM_I2C) += acpi_i2c.o
+endif
obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
diff --git a/drivers/i2c/acpi_i2c.c b/drivers/i2c/acpi_i2c.c
new file mode 100644
index 000..57d29683cbf
--- /dev/null
+++ b/drivers/i2c/acpi_i2c.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#ifdef CONFIG_X86
+#include
+#endif
+#include
+#include
+
+static bool acpi_i2c_add_gpios_to_crs(struct acpi_i2c_priv *priv)
+{
+ /*
+* Return false if:
+* 1. Request to explicitly disable export of GPIOs in CRS, or
+* 2. Both reset and enable GPIOs are not provided.
+*/
+ if (priv->disable_gpio_export_in_crs ||
+ (!dm_gpio_is_valid(>reset_gpio) &&
+!dm_gpio_is_valid(>enable_gpio)))
+ return false;
+
+ return true;
+}
+
+static int acpi_i2c_write_gpio(struct acpi_ctx *ctx, struct gpio_desc *gpio,
+ int *curindex)
+{
+ int ret;
+
+ if (!dm_gpio_is_valid(gpio))
+ return -ENOENT;
+
+ acpi_device_write_gpio_desc(ctx, gpio);
+ ret = *curindex;
+ (*curindex)++;
+
+ return ret;
+}
+
+int acpi_i2c_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ int reset_gpio_index = -1, enable_gpio_index = -1, irq_gpio_index = -1;
+ enum i2c_device_t type = dev_get_driver_data(dev);
+ struct
[PATCH v4 17/59] x86: Add wake sources for the acpi_gpe driver
Some devices can wake the system from sleep, e.g opening the lid on a clamshell or moving a USB mouse. Add a wake to specify this for USB devices and add the settings for Apollo Lake. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/include/asm/arch-apollolake/gpe.h | 135 arch/x86/include/asm/arch-apollolake/gpio.h | 3 + doc/device-tree-bindings/device.txt | 3 + 3 files changed, 141 insertions(+) create mode 100644 arch/x86/include/asm/arch-apollolake/gpe.h diff --git a/arch/x86/include/asm/arch-apollolake/gpe.h b/arch/x86/include/asm/arch-apollolake/gpe.h new file mode 100644 index 000..f5792960bee --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/gpe.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Intel Corporation + * Copyright 2020 Google LLC + * + * Taken from coreboot apl gpe.h + */ + +#ifndef _ASM_ARCH_GPE_H_ +#define _ASM_ARCH_GPE_H_ + +/* bit position in GPE0a_STS register */ +#define GPE0A_PCIE_SCI_STS 0 +#define GPE0A_SWGPE_STS2 +#define GPE0A_PCIE_WAKE0_STS 3 +#define GPE0A_PUNIT_SCI_STS4 +#define GPE0A_PCIE_WAKE1_STS 6 +#define GPE0A_PCIE_WAKE2_STS 7 +#define GPE0A_PCIE_WAKE3_STS 8 +#define GPE0A_PCIE_GPE_STS 9 +#define GPE0A_BATLOW_STS 10 +#define GPE0A_CSE_PME_STS 11 +#define GPE0A_XDCI_PME_STS 12 +#define GPE0A_XHCI_PME_STS 13 +#define GPE0A_AVS_PME_STS 14 +#define GPE0A_GPIO_TIER1_SCI_STS 15 +#define GPE0A_SMB_WAK_STS 16 +#define GPE0A_SATA_PME_STS 17 +#define GPE0A_CNVI_PME_STS 18 + +/* Group DW0 is reserved in Apollolake */ + +/* GPE_63_32 */ +#define GPE0_DW1_0032 +#define GPE0_DW1_0133 +#define GPE0_DW1_0234 +#define GPE0_DW1_0336 +#define GPE0_DW1_0436 +#define GPE0_DW1_0537 +#define GPE0_DW1_0638 +#define GPE0_DW1_0739 +#define GPE0_DW1_0840 +#define GPE0_DW1_0941 +#define GPE0_DW1_1042 +#define GPE0_DW1_1143 +#define GPE0_DW1_1244 +#define GPE0_DW1_1345 +#define GPE0_DW1_1446 +#define GPE0_DW1_1547 +#define GPE0_DW1_1648 +#define GPE0_DW1_1749 +#define GPE0_DW1_1850 +#define GPE0_DW1_1951 +#define GPE0_DW1_2052 +#define GPE0_DW1_2153 +#define GPE0_DW1_2254 +#define GPE0_DW1_2355 +#define GPE0_DW1_2456 +#define GPE0_DW1_2557 +#define GPE0_DW1_2658 +#define GPE0_DW1_2759 +#define GPE0_DW1_2860 +#define GPE0_DW1_2961 +#define GPE0_DW1_3062 +#define GPE0_DW1_3163 +/* GPE_95_64 */ +#define GPE0_DW2_0064 +#define GPE0_DW2_0165 +#define GPE0_DW2_0266 +#define GPE0_DW2_0367 +#define GPE0_DW2_0468 +#define GPE0_DW2_0569 +#define GPE0_DW2_0670 +#define GPE0_DW2_0771 +#define GPE0_DW2_0872 +#define GPE0_DW2_0973 +#define GPE0_DW2_1074 +#define GPE0_DW2_1175 +#define GPE0_DW2_1276 +#define GPE0_DW2_1377 +#define GPE0_DW2_1478 +#define GPE0_DW2_1579 +#define GPE0_DW2_1680 +#define GPE0_DW2_1781 +#define GPE0_DW2_1882 +#define GPE0_DW2_1983 +#define GPE0_DW2_2084 +#define GPE0_DW2_2185 +#define GPE0_DW2_2286 +#define GPE0_DW2_2387 +#define GPE0_DW2_2488 +#define GPE0_DW2_2589 +#define GPE0_DW2_2690 +#define GPE0_DW2_2791 +#define GPE0_DW2_2892 +#define GPE0_DW2_2993 +#define GPE0_DW2_3094 +#define GPE0_DW2_3195 +/* GPE_127_96 */ +#define GPE0_DW3_0096 +#define GPE0_DW3_0197 +#define GPE0_DW3_0298 +#define GPE0_DW3_0399 +#define GPE0_DW3_04100 +#define GPE0_DW3_05101 +#define GPE0_DW3_06102 +#define GPE0_DW3_07103 +#define GPE0_DW3_08104 +#define GPE0_DW3_09105 +#define GPE0_DW3_10106 +#define GPE0_DW3_11107 +#define GPE0_DW3_12108 +#define GPE0_DW3_13109 +#define GPE0_DW3_14110 +#define GPE0_DW3_15111 +#define GPE0_DW3_16112 +#define GPE0_DW3_17113 +#define GPE0_DW3_18114 +#define GPE0_DW3_19115 +#define GPE0_DW3_20116 +#define GPE0_DW3_21117 +#define GPE0_DW3_22118 +#define GPE0_DW3_23119 +#define GPE0_DW3_24120 +#define GPE0_DW3_25
[PATCH v4 11/59] acpi: Add support for writing a _PRW
A 'Power Resource for Wake' list the resources a device depends on for
wake. Add a function to generate this.
Signed-off-by: Simon Glass
---
Changes in v4:
- Correct comment for dm_test_acpi_write_prw()
include/acpi/acpigen.h | 10 ++
lib/acpi/acpigen.c | 10 ++
test/dm/acpigen.c | 30 ++
3 files changed, 50 insertions(+)
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 228ac9c404b..a9b70123c0a 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -563,4 +563,14 @@ int acpigen_set_enable_tx_gpio(struct acpi_ctx *ctx, u32
tx_state_val,
const char *dw0_read, const char *dw0_write,
struct acpi_gpio *gpio, bool enable);
+/**
+ * acpigen_write_prw() - Write a power resource for wake (_PRW)
+ *
+ * @ctx: ACPI context pointer
+ * @wake: GPE that wakes up the device
+ * @level: Deepest power system sleeping state that can be entered while still
+ * providing wake functionality
+ */
+void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level);
+
#endif
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index c609ef4daa4..527de89b1e1 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -426,6 +426,16 @@ void acpigen_write_register_resource(struct acpi_ctx *ctx,
acpigen_write_resourcetemplate_footer(ctx);
}
+void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level)
+{
+ /* Name (_PRW, Package () { wake, level } */
+ acpigen_write_name(ctx, "_PRW");
+ acpigen_write_package(ctx, 2);
+ acpigen_write_integer(ctx, wake);
+ acpigen_write_integer(ctx, level);
+ acpigen_pop_len(ctx);
+}
+
/*
* ToUUID(uuid)
*
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 1b2767e732d..1dc064ffbcf 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -1097,3 +1097,33 @@ static int dm_test_acpi_write_name(struct
unit_test_state *uts)
return 0;
}
DM_TEST(dm_test_acpi_write_name, 0);
+
+/* Test emitting a _PRW component */
+static int dm_test_acpi_write_prw(struct unit_test_state *uts)
+{
+ struct acpi_ctx *ctx;
+ u8 *ptr;
+
+ ut_assertok(alloc_context());
+
+ ptr = acpigen_get_current(ctx);
+ acpigen_write_prw(ctx, 5, 3);
+ ut_asserteq(NAME_OP, *ptr++);
+
+ ut_asserteq_strn("_PRW", (char *)ptr);
+ ptr += 4;
+ ut_asserteq(PACKAGE_OP, *ptr++);
+ ut_asserteq(8, acpi_test_get_length(ptr));
+ ptr += 3;
+ ut_asserteq(2, *ptr++);
+ ut_asserteq(BYTE_PREFIX, *ptr++);
+ ut_asserteq(5, *ptr++);
+ ut_asserteq(BYTE_PREFIX, *ptr++);
+ ut_asserteq(3, *ptr++);
+ ut_asserteq_ptr(ptr, ctx->current);
+
+ free_context();
+
+ return 0;
+}
+DM_TEST(dm_test_acpi_write_prw, 0);
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 15/59] x86: link: Allow more space for U-Boot
The extra ACPI code increases U-Boot above it current size limit. Move the start earlier to provide space. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Add new patch to allow more space for U-Boot on link configs/chromebook_link_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 82485a5a3f7..c59a7f3c994 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -1,5 +1,5 @@ CONFIG_X86=y -CONFIG_SYS_TEXT_BASE=0xFFF0 +CONFIG_SYS_TEXT_BASE=0xFFEF CONFIG_SYS_MALLOC_F_LEN=0x2400 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x1000 -- 2.28.0.681.g6f77f65b4e-goog
[PATCH v4 13/59] acpi: Support generating a multi-function _DSM for devices
Add a function to generate ACPI code for a _DSM method for a device.
This includes functions for starting and ending each part of the _DSM.
Signed-off-by: Simon Glass
---
(no changes since v1)
include/acpi/acpi_device.h | 14 +
include/acpi/acpigen.h | 99 +
lib/acpi/acpi_device.c | 43 +
lib/acpi/acpigen.c | 54
test/dm/acpigen.c | 126 +
5 files changed, 336 insertions(+)
diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h
index 11461e168d3..a5b12217820 100644
--- a/include/acpi/acpi_device.h
+++ b/include/acpi/acpi_device.h
@@ -28,6 +28,9 @@ struct udevice;
/* Length of a full path to an ACPI device */
#define ACPI_PATH_MAX 30
+/* UUID for an I2C _DSM method */
+#define ACPI_DSM_I2C_HID_UUID "3cdff6f7-4267-4555-ad05-b30a3d8938de"
+
/* Values that can be returned for ACPI device _STA method */
enum acpi_dev_status {
ACPI_DSTATUS_PRESENT= BIT(0),
@@ -319,6 +322,17 @@ int acpi_device_write_gpio_desc(struct acpi_ctx *ctx,
int acpi_device_write_interrupt_or_gpio(struct acpi_ctx *ctx,
struct udevice *dev, const char *prop);
+/**
+ * acpi_device_write_dsm_i2c_hid() - Write a device-specific method for HID
+ *
+ * This writes a DSM for an I2C Human-Interface Device based on the config
+ * provided
+ *
+ * @hid_desc_reg_offset: HID register offset
+ */
+int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx,
+ int hid_desc_reg_offset);
+
/**
* acpi_device_write_i2c_dev() - Write an I2C device to ACPI
*
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index fa9409e3528..34b3115bc9c 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -666,4 +666,103 @@ void acpigen_write_return_singleton_buffer(struct
acpi_ctx *ctx, uint arg);
*/
void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg);
+/**
+ * acpigen_write_dsm_start() - Start a _DSM method
+ *
+ * Generate ACPI AML code to start the _DSM method.
+ *
+ * The functions need to be called in the correct sequence as below.
+ *
+ * Within the region, Local0 and Local1 must be are left
+ * untouched, but Local2-Local7 can be used
+ *
+ * Arguments passed into _DSM method:
+ * Arg0 = UUID
+ * Arg1 = Revision
+ * Arg2 = Function index
+ * Arg3 = Function-specific arguments
+ *
+ * AML code generated looks like this:
+ * Method (_DSM, 4, Serialized) { -- acpigen_write_dsm_start)
+ * ToBuffer (Arg0, Local0)
+ * If (LEqual (Local0, ToUUID(uuid))) { -- acpigen_write_dsm_uuid_start
+ * ToInteger (Arg2, Local1)
+ * If (LEqual (Local1, 0)) { -- acpigen_write_dsm_uuid_start_cond
+ *
+ * } -- acpigen_write_dsm_uuid_end_cond
+ * ...
+ * If (LEqual (Local1, n)) { -- acpigen_write_dsm_uuid_start_cond
+ *
+ * } -- acpigen_write_dsm_uuid_end_cond
+ * Return (Buffer (One) { 0x0 })
+ * } -- acpigen_write_dsm_uuid_end
+ * ...
+ * If (LEqual (Local0, ToUUID(uuidn))) {
+ * ...
+ * }
+ * Return (Buffer (One) { 0x0 }) -- acpigen_write_dsm_end
+ * }
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_start(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_dsm_uuid_start() - Start a new UUID block
+ *
+ * This starts generation of code to handle a particular UUID:
+ *
+ * If (LEqual (Local0, ToUUID(uuid))) {
+ * ToInteger (Arg2, Local1)
+ *
+ * @ctx: ACPI context pointer
+ */
+int acpigen_write_dsm_uuid_start(struct acpi_ctx *ctx, const char *uuid);
+
+/**
+ * acpigen_write_dsm_uuid_start_cond() - Start a new condition block
+ *
+ * This starts generation of condition-checking code to handle a particular
+ * function:
+ *
+ * If (LEqual (Local1, i))
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_uuid_start_cond(struct acpi_ctx *ctx, int seq);
+
+/**
+ * acpigen_write_dsm_uuid_end_cond() - Start a new condition block
+ *
+ * This ends generation of condition-checking code to handle a particular
+ * function:
+ *
+ * }
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_uuid_end_cond(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_dsm_uuid_end() - End a UUID block
+ *
+ * This ends generation of code to handle a particular UUID:
+ *
+ * Return (Buffer (One) { 0x0 })
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_uuid_end(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_dsm_end() - End a _DSM method
+ *
+ * This ends generates of the _DSM block:
+ *
+ * Return (Buffer (One) { 0x0 })
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_end(struct acpi_ctx *ctx);
+
#endif
diff --git a/lib/acpi/acpi_device.c b/lib/acpi/acpi_device.c
[PATCH v4 12/59] acpi: Add support for conditions and return values
Add functions to support generating ACPI code for condition checks and
return values.
Signed-off-by: Simon Glass
---
(no changes since v1)
include/acpi/acpigen.h | 93 ++
lib/acpi/acpigen.c | 68 ++
test/dm/acpigen.c | 91 +
3 files changed, 252 insertions(+)
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index a9b70123c0a..fa9409e3528 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -52,12 +52,24 @@ enum {
LOCAL5_OP = 0x65,
LOCAL6_OP = 0x66,
LOCAL7_OP = 0x67,
+ ARG0_OP = 0x68,
+ ARG1_OP = 0x69,
+ ARG2_OP = 0x6a,
+ ARG3_OP = 0x6b,
+ ARG4_OP = 0x6c,
+ ARG5_OP = 0x6d,
+ ARG6_OP = 0x6e,
STORE_OP= 0x70,
AND_OP = 0x7b,
OR_OP = 0x7d,
NOT_OP = 0x80,
DEVICE_OP = 0x82,
POWER_RES_OP= 0x84,
+ LEQUAL_OP = 0x93,
+ TO_BUFFER_OP= 0x96,
+ TO_INTEGER_OP = 0x99,
+ IF_OP = 0xa0,
+ ELSE_OP = 0xa1,
RETURN_OP = 0xa4,
};
@@ -573,4 +585,85 @@ int acpigen_set_enable_tx_gpio(struct acpi_ctx *ctx, u32
tx_state_val,
*/
void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level);
+/**
+ * acpigen_write_if() - Write an If block
+ *
+ * This requires a call to acpigen_pop_len() to complete the block
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_if(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_if_lequal_op_int() - Write comparison between op and integer
+ *
+ * Generates ACPI code for checking if operand1 and operand2 are equal
+ *
+ * If (Lequal (op, val))
+ *
+ * @ctx: ACPI context pointer
+ * @op: Operand to check
+ * @val: Value to check against
+ */
+void acpigen_write_if_lequal_op_int(struct acpi_ctx *ctx, uint op, u64 val);
+
+/**
+ * acpigen_write_else() - Write an Ef block
+ *
+ * This requires a call to acpigen_pop_len() to complete the block
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_else(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_to_buffer() - Write a ToBuffer operation
+ *
+ * E.g.: to generate: ToBuffer (Arg0, Local0)
+ * use acpigen_write_to_buffer(ctx, ARG0_OP, LOCAL0_OP)
+ *
+ * @ctx: ACPI context pointer
+ * @src: Source argument
+ * @dst: Destination argument
+ */
+void acpigen_write_to_buffer(struct acpi_ctx *ctx, uint src, uint dst);
+
+/**
+ * acpigen_write_to_integer() - Write a ToInteger operation
+ *
+ * E.g.: to generate: ToInteger (Arg0, Local0)
+ * use acpigen_write_to_integer(ctx, ARG0_OP, LOCAL0_OP)
+ *
+ * @ctx: ACPI context pointer
+ * @src: Source argument
+ * @dst: Destination argument
+ */
+void acpigen_write_to_integer(struct acpi_ctx *ctx, uint src, uint dst);
+
+/**
+ * acpigen_write_return_byte_buffer() - Write a return of a byte buffer
+ *
+ * @ctx: ACPI context pointer
+ * @arr: Array of bytes to return
+ * @size: Number of bytes
+ */
+void acpigen_write_return_byte_buffer(struct acpi_ctx *ctx, u8 *arr,
+ size_t size);
+
+/**
+ * acpigen_write_return_singleton_buffer() - Write a return of a 1-byte buffer
+ *
+ * @ctx: ACPI context pointer
+ * @arg: Byte to return
+ */
+void acpigen_write_return_singleton_buffer(struct acpi_ctx *ctx, uint arg);
+
+/**
+ * acpigen_write_return_byte() - Write a return of a byte
+ *
+ * @ctx: ACPI context pointer
+ * @arg: Byte to return
+ */
+void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg);
+
#endif
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index 527de89b1e1..2518bf83dda 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -541,6 +541,74 @@ void acpigen_write_debug_string(struct acpi_ctx *ctx,
const char *str)
acpigen_emit_ext_op(ctx, DEBUG_OP);
}
+void acpigen_write_if(struct acpi_ctx *ctx)
+{
+ acpigen_emit_byte(ctx, IF_OP);
+ acpigen_write_len_f(ctx);
+}
+
+void acpigen_write_if_lequal_op_int(struct acpi_ctx *ctx, uint op, u64 val)
+{
+ acpigen_write_if(ctx);
+ acpigen_emit_byte(ctx, LEQUAL_OP);
+ acpigen_emit_byte(ctx, op);
+ acpigen_write_integer(ctx, val);
+}
+
+void acpigen_write_else(struct acpi_ctx *ctx)
+{
+ acpigen_emit_byte(ctx, ELSE_OP);
+ acpigen_write_len_f(ctx);
+}
+
+void acpigen_write_to_buffer(struct acpi_ctx *ctx, uint src, uint dst)
+{
+ acpigen_emit_byte(ctx, TO_BUFFER_OP);
+ acpigen_emit_byte(ctx, src);
+ acpigen_emit_byte(ctx, dst);
+}
+
+void acpigen_write_to_integer(struct acpi_ctx *ctx, uint src, uint dst)
+{
+ acpigen_emit_byte(ctx, TO_INTEGER_OP);
+ acpigen_emit_byte(ctx, src);
+
[PATCH v4 10/59] x86: coral: Add ACPI tables for coral
This device has a large set of ACPI tables. Bring these in from coreboot
so that full functionality is available (apart from SMI).
Signed-off-by: Simon Glass
---
Changes in v4:
- Add logging when writinge NHLT
- Change table version to 3
Changes in v1:
- Add NHLT audio support
- Capitalise ACPI_OPS_PTR
- Use OEM_TABLE_ID instead of ACPI_TABLE_CREATOR
board/google/chromebook_coral/Makefile| 1 +
.../chromebook_coral/baseboard_dptf.asl | 71 +
board/google/chromebook_coral/coral.c | 136 ++
board/google/chromebook_coral/dsdt.asl| 60
.../google/chromebook_coral/variant_dptf.asl | 6 +
board/google/chromebook_coral/variant_ec.h| 75 ++
board/google/chromebook_coral/variant_gpio.h | 63
include/bloblist.h| 5 +
8 files changed, 417 insertions(+)
create mode 100644 board/google/chromebook_coral/baseboard_dptf.asl
create mode 100644 board/google/chromebook_coral/dsdt.asl
create mode 100644 board/google/chromebook_coral/variant_dptf.asl
create mode 100644 board/google/chromebook_coral/variant_ec.h
create mode 100644 board/google/chromebook_coral/variant_gpio.h
diff --git a/board/google/chromebook_coral/Makefile
b/board/google/chromebook_coral/Makefile
index 6a27ce3da1b..f7a0ca6cc0a 100644
--- a/board/google/chromebook_coral/Makefile
+++ b/board/google/chromebook_coral/Makefile
@@ -3,3 +3,4 @@
# Copyright 2019 Google LLC
obj-y += coral.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/google/chromebook_coral/baseboard_dptf.asl
b/board/google/chromebook_coral/baseboard_dptf.asl
new file mode 100644
index 000..5da963a6705
--- /dev/null
+++ b/board/google/chromebook_coral/baseboard_dptf.asl
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ */
+
+#define DPTF_CPU_PASSIVE 95
+#define DPTF_CPU_CRITICAL 105
+
+#define DPTF_TSR0_SENSOR_ID0
+#define DPTF_TSR0_SENSOR_NAME "Battery"
+#define DPTF_TSR0_PASSIVE 120
+#define DPTF_TSR0_CRITICAL 125
+
+#define DPTF_TSR1_SENSOR_ID1
+#define DPTF_TSR1_SENSOR_NAME "Ambient"
+#define DPTF_TSR1_PASSIVE 46
+#define DPTF_TSR1_CRITICAL 75
+
+#define DPTF_TSR2_SENSOR_ID2
+#define DPTF_TSR2_SENSOR_NAME "Charger"
+#define DPTF_TSR2_PASSIVE 58
+#define DPTF_TSR2_CRITICAL 90
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 2 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2,/* Revision */
+ Package () {/* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 3000, /* PowerLimitMinimum */
+ 12000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () {/* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 8000, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000/* StepSize */
+ }
+})
diff --git a/board/google/chromebook_coral/coral.c
b/board/google/chromebook_coral/coral.c
index 12d4fe63cb0..f5ae48290f4 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c
@@ -4,7 +4,24 @@
*/
#include
+#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "variant_gpio.h"
+
+struct cros_gpio_info {
+ const char *linux_name;
+ enum cros_gpio_t type;
+ int gpio_num;
+ int flags;
+};
int arch_misc_init(void)
{
@@ -18,3 +35,122 @@ int board_run_command(const char *cmdline)
return 0;
}
+
+int chromeos_get_gpio(const struct udevice *dev, const char *prop,
+ enum cros_gpio_t
[PATCH v4 09/59] x86: acpi: Expand the GNVS
Expand this to 4KB so that it is possible to add custom information to it.
On Chromebooks this is used to pass verified-boot information.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/include/asm/acpi/global_nvs.h | 2 +-
arch/x86/include/asm/intel_gnvs.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/acpi/global_nvs.h
b/arch/x86/include/asm/acpi/global_nvs.h
index a552cf6374f..46383629cc5 100644
--- a/arch/x86/include/asm/acpi/global_nvs.h
+++ b/arch/x86/include/asm/acpi/global_nvs.h
@@ -16,6 +16,6 @@
* DSDT, since it is created by code, so ACPI_GNVS_ADDR is unused.
*/
#define ACPI_GNVS_ADDR 0xdeadbeef
-#define ACPI_GNVS_SIZE 0x100
+#define ACPI_GNVS_SIZE 0x1000
#endif /* _ACPI_GNVS_H_ */
diff --git a/arch/x86/include/asm/intel_gnvs.h
b/arch/x86/include/asm/intel_gnvs.h
index e2d479d4f32..c1e9d65779f 100644
--- a/arch/x86/include/asm/intel_gnvs.h
+++ b/arch/x86/include/asm/intel_gnvs.h
@@ -36,6 +36,7 @@ struct __packed acpi_global_nvs {
u8 unused2[0x1000 - 0x100];/* Pad out to 4096 bytes */
#endif
};
+
#ifdef CONFIG_CHROMEOS
check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 07/59] x86: Add a common global NVS structure
Add the definition of this structure common to Intel devices. It includes
some optional Chrome OS pieces which are used when vboot is integrated.
Drop the APL version as it is basically the same.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Use this file in APL
.../include/asm/arch-apollolake/global_nvs.h | 23 +-
arch/x86/include/asm/intel_gnvs.h | 43 +++
2 files changed, 44 insertions(+), 22 deletions(-)
create mode 100644 arch/x86/include/asm/intel_gnvs.h
diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h
b/arch/x86/include/asm/arch-apollolake/global_nvs.h
index fe62194b02e..ef8eb228dbe 100644
--- a/arch/x86/include/asm/arch-apollolake/global_nvs.h
+++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h
@@ -10,27 +10,6 @@
#ifndef _GLOBAL_NVS_H_
#define _GLOBAL_NVS_H_
-struct __packed acpi_global_nvs {
- /* Miscellaneous */
- u8 pcnt; /* 0x00 - Processor Count */
- u8 ppcm; /* 0x01 - Max PPC State */
- u8 lids; /* 0x02 - LID State */
- u8 pwrs; /* 0x03 - AC Power State */
- u8 dpte; /* 0x04 - Enable DPTF */
- u32 cbmc; /* 0x05 - 0x08 - U-Boot Console */
- u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
- u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */
- u64 nhla; /* 0x19 - 0x20 - NHLT Address */
- u32 nhll; /* 0x21 - 0x24 - NHLT Length */
- u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */
- u8 scdp; /* 0x29 - SD_CD GPIO portid */
- u8 scdo; /* 0x2a - GPIO pad offset relative to the community */
- u8 uior; /* 0x2b - UART debug controller init on S3 resume */
- u8 ecps; /* 0x2c - SGX Enabled status */
- u64 emna; /* 0x2d - 0x34 EPC base address */
- u64 elng; /* 0x35 - 0x3c EPC Length */
- u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */
- u8 unused2[0x1000 - 0x100];/* Pad out to 4096 bytes */
-};
+#include
#endif /* _GLOBAL_NVS_H_ */
diff --git a/arch/x86/include/asm/intel_gnvs.h
b/arch/x86/include/asm/intel_gnvs.h
new file mode 100644
index 000..e2d479d4f32
--- /dev/null
+++ b/arch/x86/include/asm/intel_gnvs.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * Taken from coreboot intelblocks/nvs.h
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _INTEL_GNVS_H_
+#define _INTEL_GNVS_H_
+
+struct __packed acpi_global_nvs {
+ /* Miscellaneous */
+ u8 pcnt; /* 0x00 - Processor Count */
+ u8 ppcm; /* 0x01 - Max PPC State */
+ u8 lids; /* 0x02 - LID State */
+ u8 pwrs; /* 0x03 - AC Power State */
+ u8 dpte; /* 0x04 - Enable DPTF */
+ u32 cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
+ u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
+ u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */
+ u64 nhla; /* 0x19 - 0x20 - NHLT Address */
+ u32 nhll; /* 0x21 - 0x24 - NHLT Length */
+ u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */
+ u8 scdp; /* 0x29 - SD_CD GPIO portid */
+ u8 scdo; /* 0x2a - GPIO pad offset relative to the community */
+ u8 uior; /* 0x2b - UART debug controller init on S3 resume */
+ u8 ecps; /* 0x2c - SGX Enabled status */
+ u64 emna; /* 0x2d - 0x34 EPC base address */
+ u64 elng; /* 0x35 - 0x3C EPC Length */
+ u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */
+#ifdef CONFIG_CHROMEOS
+ /* ChromeOS-specific (0x100 - 0xfff) */
+ struct chromeos_acpi chromeos;
+#else
+ u8 unused2[0x1000 - 0x100];/* Pad out to 4096 bytes */
+#endif
+};
+#ifdef CONFIG_CHROMEOS
+check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+#endif
+
+#endif /* _INTEL_GNVS_H_ */
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 03/59] x86: acpi: apl: Add asl files for Apollo Lake
Add Apollo Lake ASL files, taken from coreboot.
Signed-off-by: Simon Glass
---
(no changes since v1)
.../include/asm/arch-apollolake/acpi/dptf.asl | 35
.../asm/arch-apollolake/acpi/globalnvs.asl| 41
.../include/asm/arch-apollolake/acpi/gpio.asl | 191 ++
.../asm/arch-apollolake/acpi/gpiolib.asl | 109 ++
.../include/asm/arch-apollolake/acpi/lpss.asl | 105 ++
.../asm/arch-apollolake/acpi/northbridge.asl | 120 +++
.../asm/arch-apollolake/acpi/pch_hda.asl | 77 +++
.../asm/arch-apollolake/acpi/pci_irqs.asl | 52 +
.../include/asm/arch-apollolake/acpi/pcie.asl | 22 ++
.../asm/arch-apollolake/acpi/pcie_port.asl| 113 +++
.../asm/arch-apollolake/acpi/platform.asl | 10 +
.../asm/arch-apollolake/acpi/pmc_ipc.asl | 49 +
.../include/asm/arch-apollolake/acpi/scs.asl | 173
.../asm/arch-apollolake/acpi/soc_int.asl | 50 +
.../asm/arch-apollolake/acpi/southbridge.asl | 34
.../include/asm/arch-apollolake/acpi/xhci.asl | 33 +++
.../arch-apollolake/acpi/xhci_apl_ports.asl | 23 +++
.../arch-apollolake/acpi/xhci_glk_ports.asl | 24 +++
18 files changed, 1261 insertions(+)
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/gpio.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/lpss.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pcie.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/platform.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/scs.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl
create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
b/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
new file mode 100644
index 000..4c50bb45c0f
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+#define DPTF_CPU_DEVICETCPU
+#define DPTF_CPU_ADDR 0x0001
+
+#ifndef DPTF_CPU_PASSIVE
+#define DPTF_CPU_PASSIVE 80
+#endif
+
+#ifndef DPTF_CPU_CRITICAL
+#define DPTF_CPU_CRITICAL 90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC0
+#define DPTF_CPU_ACTIVE_AC090
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC1
+#define DPTF_CPU_ACTIVE_AC180
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC2
+#define DPTF_CPU_ACTIVE_AC270
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC3
+#define DPTF_CPU_ACTIVE_AC360
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC4
+#define DPTF_CPU_ACTIVE_AC450
+#endif
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
b/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
new file mode 100644
index 000..7854f7e1c5d
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Alexandru Gagniuc for Intel
Corp.)
+ */
+
+/*
+ * NOTE: The layout of the GNVS structure below must match the layout in
+ * soc/intel/apollolake/include/soc/nvs.h !!!
+ *
+ */
+
+External (NVSA)
+
+OperationRegion (GNVS, SystemMemory, NVSA, ACPI_GNVS_SIZE)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+ /* Miscellaneous */
+ Offset (0x00),
+ PCNT, 8, // 0x00 - Processor Count
+ PPCM, 8, // 0x01 - Max PPC State
+ LIDS, 8, // 0x02 - LID State
+ PWRS, 8, // 0x03 - AC Power State
+ DPTE, 8, // 0x04 - Enable DPTF
+ CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console
+ PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
+ GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
+ NHLA, 64, // 0x19 - 0x20 - NHLT Address
+ NHLL, 32, // 0x21 - 0x24 - NHLT Length
+ PRT0, 32, // 0x25 - 0x28 - PERST_0 Address
+ SCDP, 8, // 0x29 - SD_CD GPIO portid
+ SCDO, 8, // 0x2A - GPIO pad offset relative to the community
+ UIOR, 8,
[PATCH v4 08/59] x86: acpi: Support external GNVS tables
At present U-Boot puts a magic number in the ASL for the GNVS table and
searches for it later.
Add a Kconfig option to use a different approach, where the ASL files
declare the table as an external symbol. U-Boot can then put it wherever
it likes, without any magic numbers or searching.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/Kconfig | 7 ++
arch/x86/cpu/apollolake/Kconfig| 1 +
arch/x86/include/asm/acpi/global_nvs.h | 3 +++
arch/x86/lib/acpi_table.c | 35 +-
4 files changed, 34 insertions(+), 12 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 256a1100bd3..680f26f1b8e 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -788,6 +788,13 @@ config GENERATE_ACPI_TABLE
by the operating system. It defines platform-independent interfaces
for configuration and power management monitoring.
+config ACPI_GNVS_EXTERNAL
+ bool
+ help
+ Put the GNVS (Global Non-Volatile Sleeping) table separate from the
+ DSDT and add a pointer to the table from the DSDT. This allows
+ U-Boot to better control the address of the GNVS.
+
endmenu
config HAVE_ACPI_RESUME
diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
index 37d6289ee41..16ac2b3f504 100644
--- a/arch/x86/cpu/apollolake/Kconfig
+++ b/arch/x86/cpu/apollolake/Kconfig
@@ -17,6 +17,7 @@ config INTEL_APOLLOLAKE
select PCH_SUPPORT
select P2SB
select SMP_AP_WORK
+ select ACPI_GNVS_EXTERNAL
imply ENABLE_MRC_CACHE
imply AHCI_PCI
imply SCSI
diff --git a/arch/x86/include/asm/acpi/global_nvs.h
b/arch/x86/include/asm/acpi/global_nvs.h
index d56d35ca533..a552cf6374f 100644
--- a/arch/x86/include/asm/acpi/global_nvs.h
+++ b/arch/x86/include/asm/acpi/global_nvs.h
@@ -11,6 +11,9 @@
* ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file
* to declare the GNVS OperationRegion, as well as write_acpi_tables()
* for the GNVS address runtime fix up.
+ *
+ * If using CONFIG_ACPI_GNVS_EXTERNAL, we don't need to locate the GNVS in
+ * DSDT, since it is created by code, so ACPI_GNVS_ADDR is unused.
*/
#define ACPI_GNVS_ADDR 0xdeadbeef
#define ACPI_GNVS_SIZE 0x100
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index c445aa68703..36ef3e5f0b7 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -430,17 +430,31 @@ ulong write_acpi_tables(ulong start_addr)
dsdt->length - sizeof(struct acpi_table_header));
acpi_inc(ctx, dsdt->length - sizeof(struct acpi_table_header));
+ dsdt->length = ctx->current - (void *)dsdt;
+ acpi_align(ctx);
- /* Pack GNVS into the ACPI table area */
- for (i = 0; i < dsdt->length; i++) {
- u32 *gnvs = (u32 *)((u32)dsdt + i);
- if (*gnvs == ACPI_GNVS_ADDR) {
- ulong addr = (ulong)map_to_sysmem(ctx->current);
-
- debug("Fix up global NVS in DSDT to %#08lx\n", addr);
- *gnvs = addr;
- break;
+ if (!IS_ENABLED(CONFIG_ACPI_GNVS_EXTERNAL)) {
+ /* Pack GNVS into the ACPI table area */
+ for (i = 0; i < dsdt->length; i++) {
+ u32 *gnvs = (u32 *)((u32)dsdt + i);
+
+ if (*gnvs == ACPI_GNVS_ADDR) {
+ *gnvs = map_to_sysmem(ctx->current);
+ debug("Fix up global NVS in DSDT to %#08x\n",
+ *gnvs);
+ break;
+ }
}
+
+ /*
+* Fill in platform-specific global NVS variables. If this fails
+* we cannot return the error but this should only happen while
+* debugging.
+*/
+ addr = acpi_create_gnvs(ctx->current);
+ if (IS_ERR_VALUE(addr))
+ printf("Error: Gailed to create GNVS\n");
+ acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));
}
/*
@@ -448,12 +462,9 @@ ulong write_acpi_tables(ulong start_addr)
* the GNVS address. Set the checksum to zero since it is part of the
* region being checksummed.
*/
- dsdt->length = ctx->current - (void *)dsdt;
dsdt->checksum = 0;
dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);
- acpi_align(ctx);
-
/*
* Fill in platform-specific global NVS variables. If this fails we
* cannot return the error but this should only happen while debugging.
--
2.28.0.681.g6f77f65b4e-goog
[PATCH v4 02/59] x86: acpi: Add base asl files for common x86 devices
Add common x86 ASL files, taken from coreboot.
Signed-off-by: Simon Glass
Tested-by: Wolfgang Wallner
---
(no changes since v1)
arch/x86/include/asm/acpi/chromeos.asl| 108 +
arch/x86/include/asm/acpi/cpu.asl | 25
arch/x86/include/asm/acpi/cros_gnvs.asl | 29 +
arch/x86/include/asm/acpi/lpc.asl | 141 ++
arch/x86/include/asm/acpi/pci_osc.asl | 21
arch/x86/include/asm/acpi/pcr.asl | 80
arch/x86/include/asm/acpi/ramoops.asl | 32 +
arch/x86/include/asm/acpi/sleepstates.asl | 12 +-
8 files changed, 443 insertions(+), 5 deletions(-)
create mode 100644 arch/x86/include/asm/acpi/chromeos.asl
create mode 100644 arch/x86/include/asm/acpi/cpu.asl
create mode 100644 arch/x86/include/asm/acpi/cros_gnvs.asl
create mode 100644 arch/x86/include/asm/acpi/lpc.asl
create mode 100644 arch/x86/include/asm/acpi/pci_osc.asl
create mode 100644 arch/x86/include/asm/acpi/pcr.asl
create mode 100644 arch/x86/include/asm/acpi/ramoops.asl
diff --git a/arch/x86/include/asm/acpi/chromeos.asl
b/arch/x86/include/asm/acpi/chromeos.asl
new file mode 100644
index 000..2a0fd33265d
--- /dev/null
+++ b/arch/x86/include/asm/acpi/chromeos.asl
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ */
+
+#ifdef CONFIG_CHROMEOS
+
+#define CONFIG_VBOOT_VBNV_OFFSET 0x26
+
+#include
+
+/* GPIO package generated at run time. */
+External (OIPG)
+
+Device (CRHW)
+{
+ Name(_HID, EISAID("GGL0001"))
+
+ Method(_STA, 0, Serialized)
+ {
+ Return (0xb)
+ }
+
+ Method(CHSW, 0, Serialized)
+ {
+ Name (WSHC, Package() { VBT3 })
+ Return (WSHC)
+ }
+
+ Method(FWID, 0, Serialized)
+ {
+ Name (DIW1, "")
+ ToString(VBT5, 63, DIW1)
+ Name (DIWF, Package() { DIW1 })
+ Return(DIWF)
+ }
+
+ Method(FRID, 0, Serialized)
+ {
+ Name (DIR1, "")
+ ToString(VBT6, 63, DIR1)
+ Name (DIRF, Package() { DIR1 })
+ Return (DIRF)
+ }
+
+ Method(HWID, 0, Serialized)
+ {
+ Name (DIW0, "")
+ ToString(VBT4, 255, DIW0)
+ Name (DIWH, Package() { DIW0 })
+ Return (DIWH)
+ }
+
+ Method(BINF, 0, Serialized)
+ {
+ Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
+ Return (FNIB)
+ }
+
+ Method(GPIO, 0, Serialized)
+ {
+ Return (OIPG)
+
+ }
+
+ Method(VBNV, 0, Serialized)
+ {
+ Name(VNBV, Package() {
+ // See src/vendorcode/google/chromeos/Kconfig
+ // for the definition of these:
+ CONFIG_VBOOT_VBNV_OFFSET,
+ VBOOT_VBNV_BLOCK_SIZE
+ })
+ Return(VNBV)
+ }
+
+ Method(VDAT, 0, Serialized)
+ {
+ Name(TAD0,"")
+ ToBuffer(CHVD, TAD0)
+ Name (TADV, Package() { TAD0 })
+ Return (TADV)
+ }
+
+ Method(FMAP, 0, Serialized)
+ {
+ Name(PAMF, Package() { VBT9 })
+ Return(PAMF)
+ }
+
+ Method(MECK, 0, Serialized)
+ {
+ Name(HASH, Package() { MEHH })
+ Return(HASH)
+ }
+
+ Method(MLST, 0, Serialized)
+ {
+ Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
+ "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
+ })
+ Return (TSLM)
+ }
+}
+
+#include "ramoops.asl"
+
+#endif
diff --git a/arch/x86/include/asm/acpi/cpu.asl
b/arch/x86/include/asm/acpi/cpu.asl
new file mode 100644
index 000..b20b3572f2b
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cpu.asl
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+/* These come from the dynamically created CPU SSDT */
+External (\_PR.CNOT, MethodObj)
+
+/* Notify OS to re-read CPU tables */
+Method (PNOT)
+{
+ \_PR.CNOT (0x81)
+}
+
+/* Notify OS to re-read CPU _PPC limit */
+Method (PPCN)
+{
+ \_PR.CNOT (0x80)
+}
+
+/* Notify OS to re-read Throttle Limit tables */
+Method (TNOT)
+{
+ \_PR.CNOT (0x82)
+}
diff --git a/arch/x86/include/asm/acpi/cros_gnvs.asl
b/arch/x86/include/asm/acpi/cros_gnvs.asl
new file mode 100644
index 000..c20b64565e0
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_gnvs.asl
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+/* This is the ChromeOS specific ACPI information needed by
+ * the mainboard's chromeos.asl
+ */
+
+VBT0, 32,// 0x000 - Boot Reason
+VBT1, 32,// 0x004 - Active Main Firmware
+VBT2, 32,// 0x008 -
