Re: [PATCH 1/2] efi_loader: move load options to new module
On 1/18/21 3:17 AM, AKASHI Takahiro wrote:
On Fri, Jan 15, 2021 at 07:02:49PM +0100, Heinrich Schuchardt wrote:
Move all load options related functions to a new module. So that they can
be compiled independently.
Signed-off-by: Heinrich Schuchardt
---
lib/efi_loader/efi_load_options.c | 151 ++
1 file changed, 151 insertions(+)
create mode 100644 lib/efi_loader/efi_load_options.c
diff --git a/lib/efi_loader/efi_load_options.c
b/lib/efi_loader/efi_load_options.c
new file mode 100644
index 00..9f0e25b6e9
--- /dev/null
+++ b/lib/efi_loader/efi_load_options.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * EFI boot manager
+ *
+ * Copyright (c) 2017 Rob Clark
Some part of the code in this file was originally written by me.
I will add your name. Other projects simply say don't put names into the
text because their will be further contributors anyways.
Best regards
Heinrich
-Takahiro Akashi
+ */
+
+#define LOG_CATEGORY LOGC_EFI
+
+#include
+#include
+#include
+#include
+#include
+//#include
+#include
+
+/**
+ * efi_set_load_options() - set the load options of a loaded image
+ *
+ * @handle:the image handle
+ * @load_options_size: size of load options
+ * @load_options: pointer to load options
+ * Return: status code
+ */
+efi_status_t efi_set_load_options(efi_handle_t handle,
+ efi_uintn_t load_options_size,
+ void *load_options)
+{
+ struct efi_loaded_image *loaded_image_info;
+ efi_status_t ret;
+
+ ret = EFI_CALL(systab.boottime->open_protocol(
+ handle,
+ _guid_loaded_image,
+ (void **)_image_info,
+ efi_root, NULL,
+ EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL));
+ if (ret != EFI_SUCCESS)
+ return EFI_INVALID_PARAMETER;
+
+ loaded_image_info->load_options = load_options;
+ loaded_image_info->load_options_size = load_options_size;
+
+ return EFI_CALL(systab.boottime->close_protocol(handle,
+ _guid_loaded_image,
+ efi_root, NULL));
+}
+
+/**
+ * efi_deserialize_load_option() - parse serialized data
+ *
+ * Parse serialized data describing a load option and transform it to the
+ * efi_load_option structure.
+ *
+ * @lo:pointer to target
+ * @data: serialized data
+ * @size: size of the load option, on return size of the optional data
+ * Return: status code
+ */
+efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8 *data,
+efi_uintn_t *size)
+{
+ efi_uintn_t len;
+
+ len = sizeof(u32);
+ if (*size < len + 2 * sizeof(u16))
+ return EFI_INVALID_PARAMETER;
+ lo->attributes = get_unaligned_le32(data);
+ data += len;
+ *size -= len;
+
+ len = sizeof(u16);
+ lo->file_path_length = get_unaligned_le16(data);
+ data += len;
+ *size -= len;
+
+ lo->label = (u16 *)data;
+ len = u16_strnlen(lo->label, *size / sizeof(u16) - 1);
+ if (lo->label[len])
+ return EFI_INVALID_PARAMETER;
+ len = (len + 1) * sizeof(u16);
+ if (*size < len)
+ return EFI_INVALID_PARAMETER;
+ data += len;
+ *size -= len;
+
+ len = lo->file_path_length;
+ if (*size < len)
+ return EFI_INVALID_PARAMETER;
+ lo->file_path = (struct efi_device_path *)data;
+ if (efi_dp_check_length(lo->file_path, len) < 0)
+ return EFI_INVALID_PARAMETER;
+ data += len;
+ *size -= len;
+
+ lo->optional_data = data;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ * efi_serialize_load_option() - serialize load option
+ *
+ * Serialize efi_load_option structure into byte stream for Boot.
+ *
+ * @data: buffer for serialized data
+ * @lo:load option
+ * Return: size of allocated buffer
+ */
+unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data)
+{
+ unsigned long label_len;
+ unsigned long size;
+ u8 *p;
+
+ label_len = (u16_strlen(lo->label) + 1) * sizeof(u16);
+
+ /* total size */
+ size = sizeof(lo->attributes);
+ size += sizeof(lo->file_path_length);
+ size += label_len;
+ size += lo->file_path_length;
+ if (lo->optional_data)
+ size += (utf8_utf16_strlen((const char *)lo->optional_data)
+ + 1) * sizeof(u16);
+ p = malloc(size);
+ if (!p)
+ return 0;
+
+ /* copy data */
+ *data = p;
+ memcpy(p, >attributes, sizeof(lo->attributes));
+ p +=
Re: [PATCH] autoboot: fix illegal memory access when stop key and delay key are empty
On 1/18/21 6:38 AM, andy...@sony.com wrote:
You could avoid the subtraction instead of changing the type:
-for (i = 0; i < presskey_max - 1; i++)
+for (i = 0; i + 1 < presskey_max; i++)
This style seems not typically way for for loop, how do you think?
I found one similar for loop style in u-boot source code, it seems aim to fix
the similar issue.
$ grep -rn "i = 0; i + 1 < " . | grep for
drivers/i2c/meson_i2c.c:132:for (i = 0; i + 1 < i2c->count; i++)
This for loop style just 1 place compared with common style 3926 in u-boot.
$ grep -rn "i = 0; i + 1 < " . | grep for | wc -l
1
$ grep -rn "i = 0; i < " . | grep for | wc -l
3926
Best Regards
Andy Wu
-Original Message-
From: U-Boot On Behalf Of
andy...@sony.com
Sent: Monday, January 18, 2021 1:22 PM
To: xypron.g...@gmx.de; Mo, Yuezhang ;
u-boot@lists.denx.de
Cc: s...@chromium.org; h...@denx.de
Subject: RE: [PATCH] autoboot: fix illegal memory access when stop key and
delay key are empty
Both indices cannot be negative. So it is understandable that u_int was chosen.
Yes, u_int is understandable that the length is never be negative, but define
the
length parameter as "int" also usable.
Some example in current u-boot source code:
$ grep -rn length common/ | grep "int "
common/usb_storage.c:363:static int us_one_transfer(struct us_data *us, int
pipe, char *buf, int length) common/lcd.c:52:int lcd_line_length;
common/lcd.c:66:int line_length;
common/lcd.c:143:__weak int lcd_get_size(int *line_length)
common/lcd.c:283: int line_length;
common/usb.c:275: void *data, int len, int
*actual_length, int timeout)
common/usb.c:600:unsigned char *buffer, int
length)
common/usb.c:751:static void usb_try_string_workarounds(unsigned char *buf,
int *length)
common/usb.c:753: int newlength, oldlength = *length;
common/kgdb.c:319: int length;
common/cli_hush.c:318: int length;
common/usb_hub.c:613: int i, length;
You could avoid the subtraction instead of changing the type:
-for (i = 0; i < presskey_max - 1; i++)
+for (i = 0; i + 1 < presskey_max; i++)
This style seems not typically way for for loop, how do you think?
I found 3 of these:
common/usb.c:757:
for (newlength = 2; newlength + 1 < oldlength; newlength += 2)
drivers/i2c/meson_i2c.c:135:
for (i = 0; i + 1 < i2c->count; i++)
drivers/usb/emul/usb-emul-uclass.c:21:
for (ptr = 2, i = 0; ptr + 1 < length && *str; i++, ptr += 2) {
As
presskey_max < MAX_DELAY_STOP_STR < INT_MAX
your suggested code will work correctly. It is just a matter of taste.
Best regards
Heinrich
Best Regards
Andy Wu
-Original Message-
From: U-Boot On Behalf Of Heinrich
Schuchardt
Sent: Friday, January 15, 2021 8:19 PM
To: Mo, Yuezhang ; u-boot@lists.denx.de
Cc: s...@chromium.org; h...@denx.de
Subject: Re: [PATCH] autoboot: fix illegal memory access when stop key
and delay key are empty
On 15.01.21 04:11, yuezhang...@sony.com wrote:
If both stop key and delay key are empty, the length of these keys
is 0. The subtraction operation will cause the u_int type variable
to overflow, will cause illegal memory access in key input loop.
This commit fixes this bug by using int type instead of u_init.
---
common/autoboot.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/common/autoboot.c b/common/autoboot.c index
e628baffb8..61fb09f910 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -156,9 +156,9 @@ static int passwd_abort_key(uint64_t etime)
};
char presskey[MAX_DELAY_STOP_STR];
- u_int presskey_len = 0;
- u_int presskey_max = 0;
- u_int i;
+ int presskey_len = 0;
+ int presskey_max = 0;
Both indices cannot be negative. So it is understandable that u_int was chosen.
You could avoid the subtraction instead of changing the type:
-for (i = 0; i < presskey_max - 1; i++)
+for (i = 0; i + 1 < presskey_max; i++)
Acked-by: Heinrich Schuchardt
+ int i;
# ifdef CONFIG_AUTOBOOT_DELAY_STR
if (delaykey[0].str == NULL)
RE: [v2 6/6] configs: socfpga: Add defconfig for Agilex with VAB support
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Thursday, January 7, 2021 6:04 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v2 6/6] configs: socfpga: Add defconfig for Agilex with VAB support
>
> Booting Agilex with Vendor Authorized Boot.
>
> Signed-off-by: Siew Chin Lim
>
> ---
> v2
> ---
> - Renamed CONFIG_SECURE_VAB_AUTH to
> CONFIG_SOCFPGA_SECURE_VAB_AUTH
> - Add BOOTCOMMAND macro in defconfig
> ---
> .../{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig} | 5
> +++--
> 1 file changed, 3 insertions(+), 2 deletions(-) copy
> configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}
> (92%)
>
> diff --git a/configs/socfpga_agilex_atf_defconfig
> b/configs/socfpga_agilex_vab_defconfig
> similarity index 92%
> copy from configs/socfpga_agilex_atf_defconfig
> copy to configs/socfpga_agilex_vab_defconfig
> index 704a9d56b9..1e28efea5e 100644
> --- a/configs/socfpga_agilex_atf_defconfig
> +++ b/configs/socfpga_agilex_vab_defconfig
> @@ -1,5 +1,4 @@
> CONFIG_ARM=y
> -CONFIG_ARM_SMCCC=y
> CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
> CONFIG_ARCH_SOCFPGA=y
> CONFIG_SYS_TEXT_BASE=0x20
> @@ -8,6 +7,7 @@ CONFIG_ENV_SIZE=0x1000
> CONFIG_ENV_OFFSET=0x200
> CONFIG_DM_GPIO=y
> CONFIG_NR_DRAM_BANKS=2
> +CONFIG_SOCFPGA_SECURE_VAB_AUTH=y
> CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
> CONFIG_IDENT_STRING="socfpga_agilex"
> CONFIG_SPL_FS_FAT=y
> @@ -15,12 +15,13 @@ CONFIG_SPL_TEXT_BASE=0xFFE0
> CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y
> CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
> +# CONFIG_LEGACY_IMAGE_FORMAT is not set
> # CONFIG_USE_SPL_FIT_GENERATOR is not set
> CONFIG_BOOTDELAY=5
> CONFIG_USE_BOOTARGS=y
> CONFIG_BOOTARGS="earlycon"
> CONFIG_USE_BOOTCOMMAND=y
> -CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run
> linux_qspi_enable; run mmcfitboot"
> +CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
Don't need "run linux_qspi_enable"?
Regards
Ley Foon
RE: [v2 5/6] configs: socfpga: soc64: Move CONFIG_BOOTCOMMAND to defconfig
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Thursday, January 7, 2021 6:04 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v2 5/6] configs: socfpga: soc64: Move CONFIG_BOOTCOMMAND > to defconfig > > CONFIG_BOOTCOMMAND have been moved to Kconfig.boot. This patch > move the CONFIG_BOOTCOMMAND macro from socfpga_soc64_common.h > to *_defconfig file for both Stratix 10 and Agilex. > > Signed-off-by: Siew Chin Lim > Reviewed-by: Ley Foon Tan
RE: [v2 2/6] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Thursday, January 7, 2021 6:04 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v2 2/6] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
>
> Vendor Authorized Boot is a security feature for authenticating the images
> such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and
> etc loaded from FIT. After those images are loaded from FIT, the VAB
> certificate and signature block appended at the end of each image are sent
> to Secure Device Manager (SDM) for authentication. U-Boot will validate the
> SHA384 of the image against the SHA384 hash stored in the VAB certificate
> before sending the image to SDM for authentication.
>
> Signed-off-by: Siew Chin Lim
>
> ---
> v2
> ---
> - Renamed SECURE_VAB_AUTH* to SOCFPGA_SECURE_VAB_AUTH*
> - Changes in secure_vab.c
> - Changed to use SZ_1K for 1024
> - Updated comment in secure_vab.c of "... the certificate for T"
> - The code will report error before end of the function if reach
> maximum retry.
> - In board_prep_linux function, only execute linux_qspi_enable
> command if it exists in enviroment variable. It is optional.
> ---
> arch/arm/mach-socfpga/Kconfig| 15 ++
> arch/arm/mach-socfpga/Makefile | 2 +
> arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 +
> arch/arm/mach-socfpga/include/mach/secure_vab.h | 63
> arch/arm/mach-socfpga/secure_vab.c | 193
> +++
> common/Kconfig.boot | 2 +-
> 6 files changed, 275 insertions(+), 1 deletion(-) create mode 100644
> arch/arm/mach-socfpga/include/mach/secure_vab.h
> create mode 100644 arch/arm/mach-socfpga/secure_vab.c
>
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
> socfpga/Kconfig index 9b1abdaabd..0c35406232 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -6,6 +6,21 @@ config ERR_PTR_OFFSET
> config NR_DRAM_BANKS
> default 1
>
> +config SOCFPGA_SECURE_VAB_AUTH
> + bool "Enable boot image authentication with Secure Device
> Manager"
> + depends on TARGET_SOCFPGA_AGILEX
> + select FIT_IMAGE_POST_PROCESS
> + select SHA384
> + select SHA512_ALGO
> + select SPL_FIT_IMAGE_POST_PROCESS
> + help
> + All images loaded from FIT will be authenticated by Secure Device
> + Manager.
> +
> +config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
> + bool "Allow non-FIT VAB signed images"
> + depends on SOCFPGA_SECURE_VAB_AUTH
> +
> config SPL_SIZE_LIMIT
> default 0x1 if TARGET_SOCFPGA_GEN5
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> socfpga/Makefile index 82b681d870..1f1e21766d 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -4,6 +4,7 @@
> # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
> #
> # Copyright (C) 2012-2017 Altera Corporation
> +# Copyright (C) 2017-2020 Intel Corporation
>
> obj-y+= board.o
> obj-y+= clock_manager.o
> @@ -47,6 +48,7 @@ obj-y += mailbox_s10.o
> obj-y+= misc_s10.o
> obj-y+= mmu-arm64_s10.o
> obj-y+= reset_manager_s10.o
> +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)+= secure_vab.o
> obj-y+= system_manager_s10.o
> obj-y+= timer_s10.o
> obj-y+= wrap_pinmux_config_s10.o
> diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> index 4d783119ea..fbaf11597e 100644
> --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> @@ -118,6 +118,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
> #define MBOX_RECONFIG_MSEL 7
> #define MBOX_RECONFIG_DATA 8
> #define MBOX_RECONFIG_STATUS 9
> +#define MBOX_VAB_SRC_CERT11
> #define MBOX_QSPI_OPEN 50
> #define MBOX_QSPI_CLOSE 51
> #define MBOX_QSPI_DIRECT 59
> diff --git a/arch/arm/mach-socfpga/include/mach/secure_vab.h
> b/arch/arm/mach-socfpga/include/mach/secure_vab.h
> new file mode 100644
> index 00..42588588e8
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/secure_vab.h
> @@ -0,0 +1,63 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2020 Intel Corporation
> + *
> + */
> +
> +#ifndef _SECURE_VAB_H_
> +#define _SECURE_VAB_H_
> +
> +#include
> +#include
> +#include
> +
> +#define VAB_DATA_SZ 64
> +
> +#define SDM_CERT_MAGIC_NUM 0x25D04E7F
> +#define FCS_HPS_VAB_MAGIC_NUM0xD0564142
> +
> +#define MAX_CERT_SIZE(SZ_4K)
> +
> +/*
> + * struct fcs_hps_vab_certificate_data
> + * @vab_cert_magic_num: VAB Certificate Magic Word
Re: [PATCH] mtd: spi-nor-ids: add support for Micron mt25ql02g
+Michal from Xilinx
Hi Brandon,
On Sun, Jan 17, 2021 at 4:26 AM Brandon Maier wrote:
>
> On Sat, Jan 16, 2021 at 3:27 AM Bin Meng wrote:
> >
> > Hi Brandon,
> >
> > On Sat, Jan 16, 2021 at 5:54 AM Brandon Maier
> > wrote:
> > >
> > > From: Taylor Burton
> > >
> > > Micron's mt25ql02g is not currently supported in
> > > U-Boot, but is in Linux. Linux already has this flash
> > > present in its table. A snippet below:
> > >
> > > { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096...},
> > >
> > > Signed-off-by: Taylor Burton
> > > Signed-off-by: Brandon Maier
> > > CC: Jagan Teki
> > > CC: Vignesh R
> > > ---
> > > drivers/mtd/spi/spi-nor-ids.c | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> > > index 5bd5dd3003..b1f7a1cf81 100644
> > > --- a/drivers/mtd/spi/spi-nor-ids.c
> > > +++ b/drivers/mtd/spi/spi-nor-ids.c
> > > @@ -187,6 +187,7 @@ const struct flash_info spi_nor_ids[] = {
> > > { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K |
> > > USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> > > { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K |
> > > USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> > > { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K |
> > > USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> > > + { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K |
> > > USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >
> > nits: please insert this entry after "mt25ql01g"
>
> Makes sense, if a maintainer applies this could you swap these? Else I
> can send a v2 if needed.
>
> >
> > > { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR |
> > > SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
> > > { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR |
> > > SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
> > > #endif
> >
> > I believe you have tested this flash with the updated Xilinx GQSPI
> > controller driver below.
> > patchwork.ozlabs.org/project/uboot/patch/20210115213020.41897-1-brandon.ma...@rockwellcollins.com/
>
> Correct, those driver changes were needed to make this chip work.
>
> > Did you test the flash with Extended SPI mode (1-1-2 or 1-1-4)? If so,
> > would you mind taking a look at the following question regarding the
> > dummy cycle bus width question for the Dual/Quad Output Fast Read?
> > https://lists.denx.de/pipermail/u-boot/2021-January/437213.html
>
> The way I have U-Boot configured, it's using the Quad I/O Fast Read
> 1-4-4 (EBh). I was also having problems with dummy cycles. I had
> attempted to use the zynqmp_gqspi.c driver from Xilinx/u-boot-xlnx,
> but their version of dual/quad mode works by inferring the buswidth
> for specific commands by either snooping the NOR commands and hard
> coding the width, or for dummy cycles it assumes dummy buswidth ==
> data buswidth. So Xilinx's version probably only works for specific
> flash chips and configurations where it only uses supported NOR
> commands.
Yes, Xilinx's version of the U-Boot driver has hardcoded the dummy
buswdith to the value of "spi-rx-bus-width" from device tree which is
4. That's why I suspect the dummy cycle buswdith for 6Bh should also
be 4.
> If your question is if the driver should send the dummy cycles in
> Single/Dual/Quad width, I don't think the flash chip cares, as it
> ignores the data lines during the dummy cycles. Only the Linux/U-Boot
> spi-mem framework cares, as it has to pick a width so it can convert
> dummy cycles -> dummy bytes. And probably it's simpler to assume dummy
> width == addr width as the dummy cycles immediately follow the address
> anyway.
I once had the same thoughts as you, but looks only setting the dummy
cycle buswidth to 4 for command 6Bh can work on the ZCU102 board.
>
> I would guess you are having the same problem as me, U-Boot is trying
> to use certain NOR commands that Xilinx's driver hasn't hard coded a
> fix for, and so the dummy cycles get calculated wrong. If you have a
> chance maybe try my patch and see if that fixes it for you too?
>
Here is my testing result:
U-Boot 2018.01-dirty (Apr 03 2019 - 15:00:40 -0400) Xilinx ZynqMP ZCU102 rev1.0
I2C: ready
DRAM: 4 GiB
EL Level: EL2
Chip ID:zu9eg
MMC: sdhci@ff17: 0 (SD)
reading uboot.env
In:serial@ff00
Out: serial@ff00
Err: serial@ff00
Net: ZYNQ GEM: ff0e, phyaddr c, interface rgmii-id
eth0: ethernet@ff0e
Hit any key to stop autoboot: 0
ZynqMP>
ZynqMP> sf probe;sf read 10 1 1;md 10
SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB,
total 128 MiB
device 0 offset 0x1, size 0x1
SF: 65536 bytes @ 0x1 Read: OK
0010:
00100010:
00100020:
00100030:
Pull request: u-boot-riscv/master
Hi Tom, Please pull some riscv updates: - Update qemu-riscv.rst build instructions. - Add support for SPI on Kendryte K210. - Add Microchip PolarFire SoC Icicle Kit support. - Add support for an early timer. - select TIMER_EARLY to avoid infinite recursion for Trace. Thanks Rick CI: passed https://gitlab.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/5918 The following changes since commit 14ea1b3635b4af8d9e283e3671f7ee872d50b859: Merge branch '2021-01-15-assorted-improvements' (2021-01-16 11:14:21 -0500) are available in the Git repository at: g...@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 9e550e18305fb31af83bfb72d16e86d8c054fb65: doc: board: Add Microchip MPFS Icicle Kit doc (2021-01-18 11:06:39 +0800) Atish Patra (1): doc: qemu-riscv: Fix opensbi build instructions Padmarao Begari (7): riscv: Add DMA 64-bit address support net: macb: Add DMA 64-bit address support for macb net: macb: Add phy address to read it from device tree clk: Add Microchip PolarFire SoC clock driver riscv: dts: Add device tree for Microchip Icicle Kit riscv: Add Microchip MPFS Icicle Kit support doc: board: Add Microchip MPFS Icicle Kit doc Pragnesh Patel (2): trace: select TIMER_EARLY to avoid infinite recursion riscv: timer: Add support for an early timer Sean Anderson (1): riscv: Add support for SPI on Kendryte K210 arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +++ arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 arch/riscv/include/asm/types.h | 4 + board/microchip/mpfs_icicle/Kconfig | 23 + board/microchip/mpfs_icicle/mpfs_icicle.c| 99 +- board/sipeed/maix/Kconfig| 16 +++ configs/microchip_mpfs_icicle_defconfig | 9 +- configs/sipeed_maix_bitm_defconfig | 11 ++ doc/board/emulation/qemu-riscv.rst | 2 +- doc/board/index.rst | 1 + doc/board/microchip/index.rst| 9 ++ doc/board/microchip/mpfs_icicle.rst | 810 ++ doc/board/sipeed/maix.rst| 315 - drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig| 5 + drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/mpfs_clk.c | 123 +++ drivers/clk/microchip/mpfs_clk.h | 44 drivers/clk/microchip/mpfs_clk_cfg.c | 152 drivers/clk/microchip/mpfs_clk_periph.c | 187 ++ drivers/net/macb.c | 144 ++ drivers/net/macb.h | 6 ++ drivers/timer/andes_plmt_timer.c | 21 +++- drivers/timer/riscv_timer.c | 21 +++- drivers/timer/sifive_clint_timer.c | 21 +++- include/configs/ax25-ae350.h | 5 + include/configs/microchip_mpfs_icicle.h | 59 --- include/configs/qemu-riscv.h | 5 + include/configs/sifive-fu540.h | 5 + include/configs/sipeed-maix.h| 7 +- include/dt-bindings/clock/microchip-mpfs-clock.h | 45 + lib/Kconfig | 1 + 35 files changed, 2477 insertions(+), 116 deletions(-) create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts create mode 100644 doc/board/microchip/index.rst create mode 100644 doc/board/microchip/mpfs_icicle.rst create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/mpfs_clk.c create mode 100644 drivers/clk/microchip/mpfs_clk.h create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c create mode 100644 include/dt-bindings/clock/microchip-mpfs-clock.h
RE: [v2 1/6] arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Thursday, January 7, 2021 6:04 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v2 1/6] arm: socfpga: Move Stratix10 and Agilex to use > TARGET_SOCFPGA_SOC64 > > Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. > > Signed-off-by: Siew Chin Lim > Reviewed-by: Ley Foon Tan Regards Ley Foon
RE: [PATCH] autoboot: fix illegal memory access when stop key and delay key are empty
> > You could avoid the subtraction instead of changing the type: > > > > -for (i = 0; i < presskey_max - 1; i++) > > +for (i = 0; i + 1 < presskey_max; i++) > This style seems not typically way for for loop, how do you think? I found one similar for loop style in u-boot source code, it seems aim to fix the similar issue. $ grep -rn "i = 0; i + 1 < " . | grep for drivers/i2c/meson_i2c.c:132:for (i = 0; i + 1 < i2c->count; i++) This for loop style just 1 place compared with common style 3926 in u-boot. $ grep -rn "i = 0; i + 1 < " . | grep for | wc -l 1 $ grep -rn "i = 0; i < " . | grep for | wc -l 3926 Best Regards Andy Wu > -Original Message- > From: U-Boot On Behalf Of > andy...@sony.com > Sent: Monday, January 18, 2021 1:22 PM > To: xypron.g...@gmx.de; Mo, Yuezhang ; > u-boot@lists.denx.de > Cc: s...@chromium.org; h...@denx.de > Subject: RE: [PATCH] autoboot: fix illegal memory access when stop key and > delay key are empty > > > Both indices cannot be negative. So it is understandable that u_int was > > chosen. > Yes, u_int is understandable that the length is never be negative, but define > the > length parameter as "int" also usable. > Some example in current u-boot source code: > > $ grep -rn length common/ | grep "int " > common/usb_storage.c:363:static int us_one_transfer(struct us_data *us, int > pipe, char *buf, int length) common/lcd.c:52:int lcd_line_length; > common/lcd.c:66:int line_length; > common/lcd.c:143:__weak int lcd_get_size(int *line_length) > common/lcd.c:283: int line_length; > common/usb.c:275: void *data, int len, int > *actual_length, int timeout) > common/usb.c:600:unsigned char *buffer, int > length) > common/usb.c:751:static void usb_try_string_workarounds(unsigned char *buf, > int *length) > common/usb.c:753: int newlength, oldlength = *length; > common/kgdb.c:319: int length; > common/cli_hush.c:318: int length; > common/usb_hub.c:613: int i, length; > > > You could avoid the subtraction instead of changing the type: > > > > -for (i = 0; i < presskey_max - 1; i++) > > +for (i = 0; i + 1 < presskey_max; i++) > This style seems not typically way for for loop, how do you think? > > Best Regards > Andy Wu > > > -Original Message- > > From: U-Boot On Behalf Of Heinrich > > Schuchardt > > Sent: Friday, January 15, 2021 8:19 PM > > To: Mo, Yuezhang ; u-boot@lists.denx.de > > Cc: s...@chromium.org; h...@denx.de > > Subject: Re: [PATCH] autoboot: fix illegal memory access when stop key > > and delay key are empty > > > > On 15.01.21 04:11, yuezhang...@sony.com wrote: > > > If both stop key and delay key are empty, the length of these keys > > > is 0. The subtraction operation will cause the u_int type variable > > > to overflow, will cause illegal memory access in key input loop. > > > > > > This commit fixes this bug by using int type instead of u_init. > > > --- > > > common/autoboot.c | 6 +++--- > > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > > > diff --git a/common/autoboot.c b/common/autoboot.c index > > > e628baffb8..61fb09f910 100644 > > > --- a/common/autoboot.c > > > +++ b/common/autoboot.c > > > @@ -156,9 +156,9 @@ static int passwd_abort_key(uint64_t etime) > > > }; > > > > > > char presskey[MAX_DELAY_STOP_STR]; > > > - u_int presskey_len = 0; > > > - u_int presskey_max = 0; > > > - u_int i; > > > + int presskey_len = 0; > > > + int presskey_max = 0; > > > > Both indices cannot be negative. So it is understandable that u_int was > > chosen. > > You could avoid the subtraction instead of changing the type: > > > > -for (i = 0; i < presskey_max - 1; i++) > > +for (i = 0; i + 1 < presskey_max; i++) > > > > Acked-by: Heinrich Schuchardt > > > > > + int i; > > > > > > # ifdef CONFIG_AUTOBOOT_DELAY_STR > > > if (delaykey[0].str == NULL) > > >
RE: [PATCH] autoboot: fix illegal memory access when stop key and delay key are empty
> Both indices cannot be negative. So it is understandable that u_int was > chosen. Yes, u_int is understandable that the length is never be negative, but define the length parameter as "int" also usable. Some example in current u-boot source code: $ grep -rn length common/ | grep "int " common/usb_storage.c:363:static int us_one_transfer(struct us_data *us, int pipe, char *buf, int length) common/lcd.c:52:int lcd_line_length; common/lcd.c:66:int line_length; common/lcd.c:143:__weak int lcd_get_size(int *line_length) common/lcd.c:283: int line_length; common/usb.c:275: void *data, int len, int *actual_length, int timeout) common/usb.c:600:unsigned char *buffer, int length) common/usb.c:751:static void usb_try_string_workarounds(unsigned char *buf, int *length) common/usb.c:753: int newlength, oldlength = *length; common/kgdb.c:319: int length; common/cli_hush.c:318: int length; common/usb_hub.c:613: int i, length; > You could avoid the subtraction instead of changing the type: > > -for (i = 0; i < presskey_max - 1; i++) > +for (i = 0; i + 1 < presskey_max; i++) This style seems not typically way for for loop, how do you think? Best Regards Andy Wu > -Original Message- > From: U-Boot On Behalf Of Heinrich > Schuchardt > Sent: Friday, January 15, 2021 8:19 PM > To: Mo, Yuezhang ; u-boot@lists.denx.de > Cc: s...@chromium.org; h...@denx.de > Subject: Re: [PATCH] autoboot: fix illegal memory access when stop key and > delay key are empty > > On 15.01.21 04:11, yuezhang...@sony.com wrote: > > If both stop key and delay key are empty, the length of these keys is > > 0. The subtraction operation will cause the u_int type variable to > > overflow, will cause illegal memory access in key input loop. > > > > This commit fixes this bug by using int type instead of u_init. > > --- > > common/autoboot.c | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/common/autoboot.c b/common/autoboot.c index > > e628baffb8..61fb09f910 100644 > > --- a/common/autoboot.c > > +++ b/common/autoboot.c > > @@ -156,9 +156,9 @@ static int passwd_abort_key(uint64_t etime) > > }; > > > > char presskey[MAX_DELAY_STOP_STR]; > > - u_int presskey_len = 0; > > - u_int presskey_max = 0; > > - u_int i; > > + int presskey_len = 0; > > + int presskey_max = 0; > > Both indices cannot be negative. So it is understandable that u_int was > chosen. > You could avoid the subtraction instead of changing the type: > > -for (i = 0; i < presskey_max - 1; i++) > +for (i = 0; i + 1 < presskey_max; i++) > > Acked-by: Heinrich Schuchardt > > > + int i; > > > > # ifdef CONFIG_AUTOBOOT_DELAY_STR > > if (delaykey[0].str == NULL) > >
Re: Invitation: Regular U-Boot video call (Tuesday 19th)
Hi Simon, On Sat, Jan 16, 2021 at 3:24 PM Peng Fan wrote: > > Hi Simon, > > > Subject: Re: Invitation: Regular U-Boot video call (Tuesday 19th) > > > > Hi Peng, > > > > On Thu, 14 Jan 2021 at 18:33, Peng Fan wrote: > > > > > > Hi Simon, > > > > > > > Subject: Invitation: Regular U-Boot video call (Tuesday 19th) > > > > > > > > Hi, > > > > > > > > (This has been discussed for a while now so I thought I would just > > > > try it) > > > > > > > > As an experiment I'd like to set up a regular 30-minute U-Boot call > > > > for people to discuss features, bugs, patches, etc. > > > > > > > > The meeting notes and details are here[1]. > > > > > > The url is blocked by China. Do you have a direct google meet link, not > > > using > > bit.ly? > > > I am in UTC + 8 timezone, not sure I am able to join, but please invite > > > me. > > > > Yes the link is here: > > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdocs.g > > oogle.com%2Fdocument%2Fd%2F1YBOMsbM19uSFyoJWnt7-PsOLBaevzQUg > > V-hiR88a5-o%2Feditdata=04%7C01%7Cpeng.fan%40nxp.com%7Cee2d > > 255017d84f89a04308d8b95f0c8a%7C686ea1d3bc2b4c6fa92cd99c5c301635 > > %7C0%7C0%7C637463165315330931%7CUnknown%7CTWFpbGZsb3d8eyJW > > IjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C > > 1000sdata=R7G%2B4iXtS%2F5qndSYHJ7L%2FzwmWfMJ5%2B%2FAWB > > RW1x2dB0s%3Dreserved=0 > > > > I don't know why it would be blocked in China. Can you access that one? > > I could access this one and including the meet link using NXP VPN. Sorry I did the wrong conversion before. So the meeting time is 0:30 am UTC +8. I am afraid I could not join. Not sure if Peng could stay that late :) Regards, Bin
Re: [PATCH 0/4] LEGO MINDSTORMS EV3 updates
On 12/01/21 12:54 am, David Lechner wrote: > This is a collection of a few updates/cleanups for LEGO MINDSTORMS EV3. Applied to u-boot-ti/for-next branch. Thanks and regards, Lokesh > > David Lechner (4): > ARM: legoev3: set serial# env var > ARM: legoev3: drop bi_arch_number > configs: legoev3: disable CONFIG_NET > configs: legoev3: disable non-Linux boot options > > board/lego/ev3/legoev3.c | 89 +-- > configs/legoev3_defconfig | 8 +++- > include/configs/legoev3.h | 2 - > 3 files changed, 46 insertions(+), 53 deletions(-) >
Re: [PATCH] configs: am65x_evm_a53: Enable config for phandle check while getting sequence number
On 13/01/21 1:06 pm, Aswath Govindraju wrote: > AM65x SoC has two USB subsystems and their corresponding device tree nodes > have the same name but different path. While allocating sequence numbers > for these device tree nodes using alias, phandles can be used to > distinguish them. > > Enable config for phandle check while getting sequence number to > distinguish the USB device tree nodes. > > Signed-off-by: Aswath Govindraju Applied to u-boot-ti/for-next branch. Thanks and regards, Lokesh
Re: [PATCH 0/2] efi_loader: make the UEFI boot manager configurable
Heinrich, On Fri, Jan 15, 2021 at 07:02:48PM +0100, Heinrich Schuchardt wrote: > Some boards are very tight on the binary size. Booting via UEFI is possible > without using the boot manager. > > Provide a configuration option to make the boot manager available. > > Heinrich Schuchardt (2): > efi_loader: move load options to new module > efi_loader: make the UEFI boot manager configurable > > cmd/bootefi.c | 13 ++- > cmd/efidebug.c| 8 +- > lib/efi_loader/Kconfig| 8 ++ > lib/efi_loader/Makefile | 3 +- > lib/efi_loader/efi_bootmgr.c | 135 -- "efidebug" command also has some related code in that "Boot" variables are handled solely by boot manager. You can opt it out for the sake of consistency. -Takahiro Akashi > lib/efi_loader/efi_load_options.c | 151 ++ > 6 files changed, 176 insertions(+), 142 deletions(-) > create mode 100644 lib/efi_loader/efi_load_options.c > > -- > 2.29.2 >
Re: [PATCH 1/2] efi_loader: move load options to new module
On Fri, Jan 15, 2021 at 07:02:49PM +0100, Heinrich Schuchardt wrote:
> Move all load options related functions to a new module. So that they can
> be compiled independently.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> lib/efi_loader/efi_load_options.c | 151 ++
> 1 file changed, 151 insertions(+)
> create mode 100644 lib/efi_loader/efi_load_options.c
>
> diff --git a/lib/efi_loader/efi_load_options.c
> b/lib/efi_loader/efi_load_options.c
> new file mode 100644
> index 00..9f0e25b6e9
> --- /dev/null
> +++ b/lib/efi_loader/efi_load_options.c
> @@ -0,0 +1,151 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * EFI boot manager
> + *
> + * Copyright (c) 2017 Rob Clark
Some part of the code in this file was originally written by me.
-Takahiro Akashi
> + */
> +
> +#define LOG_CATEGORY LOGC_EFI
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +//#include
> +#include
> +
> +/**
> + * efi_set_load_options() - set the load options of a loaded image
> + *
> + * @handle: the image handle
> + * @load_options_size: size of load options
> + * @load_options:pointer to load options
> + * Return: status code
> + */
> +efi_status_t efi_set_load_options(efi_handle_t handle,
> + efi_uintn_t load_options_size,
> + void *load_options)
> +{
> + struct efi_loaded_image *loaded_image_info;
> + efi_status_t ret;
> +
> + ret = EFI_CALL(systab.boottime->open_protocol(
> + handle,
> + _guid_loaded_image,
> + (void **)_image_info,
> + efi_root, NULL,
> + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL));
> + if (ret != EFI_SUCCESS)
> + return EFI_INVALID_PARAMETER;
> +
> + loaded_image_info->load_options = load_options;
> + loaded_image_info->load_options_size = load_options_size;
> +
> + return EFI_CALL(systab.boottime->close_protocol(handle,
> + _guid_loaded_image,
> + efi_root, NULL));
> +}
> +
> +/**
> + * efi_deserialize_load_option() - parse serialized data
> + *
> + * Parse serialized data describing a load option and transform it to the
> + * efi_load_option structure.
> + *
> + * @lo: pointer to target
> + * @data:serialized data
> + * @size:size of the load option, on return size of the optional data
> + * Return: status code
> + */
> +efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8
> *data,
> + efi_uintn_t *size)
> +{
> + efi_uintn_t len;
> +
> + len = sizeof(u32);
> + if (*size < len + 2 * sizeof(u16))
> + return EFI_INVALID_PARAMETER;
> + lo->attributes = get_unaligned_le32(data);
> + data += len;
> + *size -= len;
> +
> + len = sizeof(u16);
> + lo->file_path_length = get_unaligned_le16(data);
> + data += len;
> + *size -= len;
> +
> + lo->label = (u16 *)data;
> + len = u16_strnlen(lo->label, *size / sizeof(u16) - 1);
> + if (lo->label[len])
> + return EFI_INVALID_PARAMETER;
> + len = (len + 1) * sizeof(u16);
> + if (*size < len)
> + return EFI_INVALID_PARAMETER;
> + data += len;
> + *size -= len;
> +
> + len = lo->file_path_length;
> + if (*size < len)
> + return EFI_INVALID_PARAMETER;
> + lo->file_path = (struct efi_device_path *)data;
> + if (efi_dp_check_length(lo->file_path, len) < 0)
> + return EFI_INVALID_PARAMETER;
> + data += len;
> + *size -= len;
> +
> + lo->optional_data = data;
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + * efi_serialize_load_option() - serialize load option
> + *
> + * Serialize efi_load_option structure into byte stream for Boot.
> + *
> + * @data:buffer for serialized data
> + * @lo: load option
> + * Return: size of allocated buffer
> + */
> +unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8
> **data)
> +{
> + unsigned long label_len;
> + unsigned long size;
> + u8 *p;
> +
> + label_len = (u16_strlen(lo->label) + 1) * sizeof(u16);
> +
> + /* total size */
> + size = sizeof(lo->attributes);
> + size += sizeof(lo->file_path_length);
> + size += label_len;
> + size += lo->file_path_length;
> + if (lo->optional_data)
> + size += (utf8_utf16_strlen((const char *)lo->optional_data)
> ++ 1) * sizeof(u16);
> + p = malloc(size);
> + if (!p)
> + return 0;
> +
> + /* copy data */
> + *data = p;
> + memcpy(p, >attributes, sizeof(lo->attributes));
> + p += sizeof(lo->attributes);
> +
> + memcpy(p, >file_path_length,
Re: [PATCH 1/1] efi_loader: provide initrddump test tool
Heinrich,
On Sun, Jan 17, 2021 at 07:48:18AM +0100, Heinrich Schuchardt wrote:
> Provide an UEFI application to save the initial RAM disk provided by U-Boot
> via the Load File2 protocol.
I don't have any specific comments on this "app," but
as the size of efi selftest grows and even more app's are added,
it would be worth thinking of moving the whole directory to 'test'
under the top for better structure of source tree.
-Takahiro Akashi
> Signed-off-by: Heinrich Schuchardt
> ---
> lib/efi_selftest/Makefile | 6 +
> lib/efi_selftest/initrddump.c | 378 ++
> 2 files changed, 384 insertions(+)
> create mode 100644 lib/efi_selftest/initrddump.c
>
> diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
> index fa3dc66baa..7d6ea30102 100644
> --- a/lib/efi_selftest/Makefile
> +++ b/lib/efi_selftest/Makefile
> @@ -14,6 +14,8 @@ CFLAGS_efi_selftest_miniapp_exit.o := $(CFLAGS_EFI) -Os
> -ffreestanding
> CFLAGS_REMOVE_efi_selftest_miniapp_exit.o := $(CFLAGS_NON_EFI)
> CFLAGS_efi_selftest_miniapp_return.o := $(CFLAGS_EFI) -Os -ffreestanding
> CFLAGS_REMOVE_efi_selftest_miniapp_return.o := $(CFLAGS_NON_EFI)
> +CFLAGS_initrddump_exit.o := $(CFLAGS_EFI) -Os -ffreestanding
> +CFLAGS_REMOVE_initrddump.o := $(CFLAGS_NON_EFI)
>
> obj-y += \
> efi_selftest.o \
> @@ -82,6 +84,10 @@ ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
> always += dtbdump.efi
> endif
>
> +ifdef CONFIG_EFI_LOAD_FILE2_INITRD
> +always += initrddump.efi
> +endif
> +
> $(obj)/efi_miniapp_file_image_exception.h:
> $(obj)/efi_selftest_miniapp_exception.efi
> $(obj)/../../tools/file2include
> $(obj)/efi_selftest_miniapp_exception.efi > \
> $(obj)/efi_miniapp_file_image_exception.h
> diff --git a/lib/efi_selftest/initrddump.c b/lib/efi_selftest/initrddump.c
> new file mode 100644
> index 00..e0d578d440
> --- /dev/null
> +++ b/lib/efi_selftest/initrddump.c
> @@ -0,0 +1,378 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2020, Heinrich Schuchardt
> + *
> + * initrddump.efi saves the initial RAM disk provided via the
> + * EFI_LOAD_FILE2_PROTOCOL.
> + */
> +
> +#include
> +#include
> +#include
> +
> +#define BUFFER_SIZE 64
> +#define ESC 0x17
> +
> +#define efi_size_in_pages(size) (((size) + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT)
> +
> +static struct efi_system_table *systable;
> +static struct efi_boot_services *bs;
> +static struct efi_simple_text_output_protocol *cerr;
> +static struct efi_simple_text_output_protocol *cout;
> +static struct efi_simple_text_input_protocol *cin;
> +static const efi_guid_t loaded_image_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID;
> +static const efi_guid_t guid_simple_file_system_protocol =
> + EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID;
> +static const efi_guid_t load_file2_guid = EFI_LOAD_FILE2_PROTOCOL_GUID;
> +static efi_handle_t handle;
> +
> +/*
> + * Device path defined by Linux to identify the handle providing the
> + * EFI_LOAD_FILE2_PROTOCOL used for loading the initial ramdisk.
> + */
> +static const struct efi_initrd_dp initrd_dp = {
> + .vendor = {
> + {
> +DEVICE_PATH_TYPE_MEDIA_DEVICE,
> +DEVICE_PATH_SUB_TYPE_VENDOR_PATH,
> +sizeof(initrd_dp.vendor),
> + },
> + EFI_INITRD_MEDIA_GUID,
> + },
> + .end = {
> + DEVICE_PATH_TYPE_END,
> + DEVICE_PATH_SUB_TYPE_END,
> + sizeof(initrd_dp.end),
> + }
> +};
> +
> +/**
> + * error() - print error string
> + *
> + * @string: error text
> + */
> +static void error(u16 *string)
> +{
> + cout->set_attribute(cout, EFI_LIGHTRED | EFI_BACKGROUND_BLACK);
> + cout->output_string(cout, string);
> + cout->set_attribute(cout, EFI_LIGHTBLUE | EFI_BACKGROUND_BLACK);
> +}
> +
> +/**
> + * efi_input_yn() - get answer to yes/no question
> + *
> + * Return:
> + * y or Y
> + * EFI_SUCCESS
> + * n or N
> + * EFI_ACCESS_DENIED
> + * ESC
> + * EFI_ABORTED
> + */
> +static efi_status_t efi_input_yn(void)
> +{
> + struct efi_input_key key = {0};
> + efi_uintn_t index;
> + efi_status_t ret;
> +
> + /* Drain the console input */
> + ret = cin->reset(cin, true);
> + for (;;) {
> + ret = bs->wait_for_event(1, >wait_for_key, );
> + if (ret != EFI_SUCCESS)
> + continue;
> + ret = cin->read_key_stroke(cin, );
> + if (ret != EFI_SUCCESS)
> + continue;
> + switch (key.scan_code) {
> + case 0x17: /* Escape */
> + return EFI_ABORTED;
> + default:
> + break;
> + }
> + /* Convert to lower case */
> + switch (key.unicode_char | 0x20) {
> + case 'y':
> + return EFI_SUCCESS;
> + case 'n':
> + return EFI_ACCESS_DENIED;
> + default:
> +
RE: [NXP-IMX] please pull nxp-imx-2021-1-16
> Subject: Re: [NXP-IMX] please pull nxp-imx-2021-1-16 > > Hi Peng, > > On 16.01.21 08:18, Peng Fan wrote: > > Hi Stefano, > > > > Please pull nxp-imx-2021-1-16 > > --- > > nandbcb update/fix > > sync i.MX8M dts from Linux kernel > > add i.MX8MN LPDDR4 evk board > > eth support for i.MX8MP evk > > ddr fix for i.MX8M > > --- > > > > CI: > > My github ci not work. > > I run buildman local and not see failure. > > > > No problem, I will start the runner on gitlab before PR. Appreciate. Not sure why my github travis CI not work as before (: Thanks, Peng. > > Regards, > Stefano > > > Thanks, > > Peng. > > > > > > The following changes since commit > 21e1cae7902e6a9b1d7cf47cf4764e6fe7d3452a: > > > >Merge tag 'efi-2021-01-rc5-2' of > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitl > > > ab.denx.de%2Fu-boot%2Fcustodians%2Fu-boot-efidata=04%7C01%7C > peng. > > > fan%40nxp.com%7Ce620a4773aeb4348de9508d8ba2555aa%7C686ea1d3bc > 2b4c6fa92 > > > cd99c5c301635%7C0%7C0%7C637464016805560765%7CUnknown%7CTWF > pbGZsb3d8eyJ > > > WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D% > 7C1000 > > > sdata=y5%2BOewaXTpNU0qCzLZ2RwEkgKrFGpkpJ4vPNC5Tx%2Byw%3 > Drese > > rved=0 (2020-12-29 10:23:58 -0500) > > > > are available in the Git repository at: > > > > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith > > > ub.com%2FMrVan%2Fu-boot.gitdata=04%7C01%7Cpeng.fan%40nxp.c > om%7Ce6 > > > 20a4773aeb4348de9508d8ba2555aa%7C686ea1d3bc2b4c6fa92cd99c5c301 > 635%7C0% > > > 7C0%7C637464016805560765%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC > 4wLjAwMDAiL > > > CJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=8 > UD55C9 > > RvwJnoj4mnvvr2yvqQDXQnuJcWdaoPD2VqAU%3Dreserved=0 > > tags/nxp-imx-2021-1-16 > > > > for you to fetch changes up to > e02b2ca34b58131cb64b19887af007adb389f7bd: > > > >imx: timer: Modify GPT timer driver for mx7 (2021-01-15 18:22:44 > > +0800) > > > > > > Han Xu (1): > >nandbcb: nand support for i.MX8MP > > > > Peng Fan (12): > >imx: imx8mp_evk: enable eth support > >imx: imx8mn_ddr4_evk: Use > CONFIG_TARGET_IMX8MN_DDR4_EVK for DDR4 EVK board > >imx: imx8mn_evk: correct stack/malloc adress > >arm: dts: imx8mn: sync dts from Linux Kernel > >imx: imx8mn: add i.MX8MN LPDDR4 EVK support > >imx8m: clock: add type of set_clk_eqos > >arm: dts: imx8mp: sync dts from Linux Kernel > >arm: dts: imx8mm: sync dts from Linux Kernel > >arm: dts: imx8mq: sync dts from Linux Kernel > >imx8m: lowlevel_init: tune alignment > >imx: imx8mn/p: drop CONFIG_SYS_[I,D]CACHE_OFF > >imx8m: add QSPI boot dev > > > > Ye Li (9): > >imx: ddr: imx8m: Move selfref_en after DDR scrub > >nandbcb: Fix uninitialized variable > >imx: nandbcb: Fix resource leak > >imx: nandbcb: Fix resource leak in read_fcb > >imx: nandbcb: Fix potential overflow in fill_dbbt_data > >imx: nandbcb: Fix potential overflow in nandbcb_set_boot_config > >imx: Fix market segment fuse offset on iMX8MP > >imx6: Remove AHCI device before boot OS > >imx: timer: Modify GPT timer driver for mx7 > > > > arch/arm/dts/Makefile |1 + > > arch/arm/dts/imx8mm-evk.dts | 534 > ++ > > arch/arm/dts/imx8mm-evk.dtsi| 489 > ++ > > arch/arm/dts/imx8mm.dtsi| 53 - > > arch/arm/dts/imx8mn-ddr4-evk.dts| 321 > ++--- > > arch/arm/dts/imx8mn-evk-u-boot.dtsi |6 + > > arch/arm/dts/imx8mn-evk.dts | 128 > ++ > > arch/arm/dts/imx8mn-evk.dtsi| 360 > > > arch/arm/dts/imx8mn-pinfunc.h | 1266 > + > - > > arch/arm/dts/imx8mn.dtsi| 411 > +++- > > arch/arm/dts/imx8mp-evk-u-boot.dtsi |4 + > > arch/arm/dts/imx8mp-evk.dts | 117 > +- > > arch/arm/dts/imx8mp-pinfunc.h | 360 > +--- > > arch/arm/dts/imx8mp.dtsi| 234 > +-- > > arch/arm/dts/imx8mq-evk.dts | 186 > --- > > arch/arm/dts/imx8mq-pinfunc.h | 623 > > > arch/arm/dts/imx8mq.dtsi| 302 > ++-- > > arch/arm/include/asm/arch-imx8m/clock.h |1 + > > arch/arm/include/asm/arch-imx8m/imx-regs.h |2 + > >
Re: [PATCH 1/3] efi_loader: print boot device and file path in helloworld
On Fri, Jan 15, 2021 at 01:02:51PM +0100, Heinrich Schuchardt wrote: > On 15.01.21 05:29, AKASHI Takahiro wrote: > > On Fri, Jan 15, 2021 at 04:12:18AM +0100, Heinrich Schuchardt wrote: > >> Am 15. Januar 2021 02:56:03 MEZ schrieb AKASHI Takahiro > >> : > >>> Heinrich, > >>> > >>> On Tue, Jan 12, 2021 at 08:58:40PM +0100, Heinrich Schuchardt wrote: > Let helloworld.efi print the device path of the boot device and the > >>> file > path as provided by the loaded image protocol. > > Signed-off-by: Heinrich Schuchardt > --- > lib/efi_loader/helloworld.c | 167 > >>> +--- > > > > >>> > >>> If this kind of information is quite useful for users, why not add > >>> that (printing) feature as an option of bootefi (or efidebug)? > >>> I'm afraid that most users who are irritated as you said won't be able > >>> to imagine such information be printed by helloworld app. > >>> > >> > >> The file path is written in > >> > >> https://github.com/trini/u-boot/blob/master/cmd/bootefi.c#L471 > >> > >> Device paths are not really user friendly. > > > > So why do you want to print such info at helloworld? > > > > I guess that, according to your cover letter, you have in your mind > > some cases where an user may get in trouble relating to the boot device. > > Right? > > > >> So I would not like to write it there. > > > > What I meant to suggest is to add an option, -v or -h, to bootefi, > > which prints verbose (and helpful) information for users to identify a > > cause. > > I can easily imagine users may blindly try to add -[v|h] when > > they see an error message even if they don't know there is such an option:) > > To me helloworld.efi is a tool for a developer to see if an EFI binary > is correctly invoked. My point is that most users (developers?) don't intuitively imagine such information will be printed with helloworld app. > The normal U-Boot code we want to keep as slim as possible. (I doubt this in terms of UEFI) > According to the spec UEFI boots from the ESP and typically there is > only one. So printing the file path in cmd/bootefi should be enough. So again, > > So why do you want to print such info at helloworld? -Takahiro Akashi > Best regards > > Heinrich
Re: [PATCH 1/2] timer: mtk_timer: initialize the timer before use
On Fri, 2021-01-15 at 17:36 +0100, Matthias Brugger wrote: > On Tue, Jan 12, 2021 at 01:44:02PM +0800, Weijie Gao wrote: > > The timer being used by this driver may have already been used by first > > stage bootloader (e.g. ATF/preloader), and it's settings may differ from > > what this driver is going to use. > > > > This may cause issues, such as inaccurate timer frequency due to > > incorrect clock divider. > > > > This patch adds the initialization code to avoid them. > > > > Signed-off-by: Weijie Gao > > --- > > drivers/timer/mtk_timer.c | 10 ++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c > > index 448a76a7e1..f6b97f868c 100644 > > --- a/drivers/timer/mtk_timer.c > > +++ b/drivers/timer/mtk_timer.c > > @@ -61,6 +61,16 @@ static int mtk_timer_probe(struct udevice *dev) > > if (!uc_priv->clock_rate) > > return -EINVAL; > > > > + /* > > +* Initialize the timer: > > +* 1. set clock source to system clock with clock divider setting to 1 > > +* 2. set timer mode to free running > > +* 3. reset timer counter to 0 then enable the timer > > +*/ > > + writel(GPT4_CLK_SYS | GPT4_CLK_DIV1, priv->base + MTK_GPT4_CLK); > > + writel(GPT4_FREERUN | GPT4_CLEAR | GPT4_ENABLE, > > GPT4_FREERUN is defined as GENMASK(5,4) while in the Linux kernel it has > the value of 3. Can you explain where this difference comes from? GENMASK(5,4) == 3 << 4, which is exactly the same as what's being used in kernel: #define GPT_CTRL_OP(val)(((val) & 0x3) << 4) #define GPT_CTRL_OP_FREERUN (3) > > Regards, > Matthias > > > + priv->base + MTK_GPT4_CTRL); > > + > > return 0; > > } > > > > -- > > 2.17.1
MTD UBI undefined reference failed to build OE gatesgarth branch
Hi Tom and Lauren, I failed to build mx6ull with MTD and UBI in OE and meta-freescahe gatesgarth branch, please be aware that I was able to build it in zeus branch, it seems something broken in gatesgarth branch. My apology I am not clear if it is the issue for MTD or u-boot or meta-freescale or OE so that I posted messages to several mailing lists for help. Andrey Zhizhikin was very unhappy about it, he believes it is your responsibility. Could you please kindly respond if it is your jurisdiction and if you tested and passed mx6ull with MTD UBI in gatesgarth branch or not? My apology again for crossing mailing lists. Kind regards, - jupiter On 1/16/21, Andrey Zhizhikin wrote: > Hello Jupiter, > > On Fri, Jan 15, 2021 at 8:32 PM JH wrote: >> >> Hello, >> >> The mtd build was fine, what could be missing not to link mtd? >> >> $ ls 2020.04-r0/build/mx6ull_14x14_evk_nand_config/drivers/mtd > > From all the build logs you have, it look to me that you're trying to > build the U-Boot delivered by NXP as a part of their BSP release. > > In this case, I suggest you'd rather contact NXP support in order to > address this failure, since it is a vendor BSP you're trying to > upgrade. > > In addition, I do not think that all mailing lists you've cross-posted > your question to would be able to help you here: > - linux-mtd list is not really appropriate to solve U-Boot build issues; > - u-boot list is for upstream U-Boot patches and discussions, which is > way past over 2020.04 version (not even considering that you're > building U-Boot from NXP fork); > - oe-core is not a proper list to post questions specific to one SOC > vendor; > - meta-freescale 'gatesgarth' branch does not have any U-Boot build > configuration for mx6ull_14x14_evk_nand_config, the only available > build config provided is for sd card; > > Having all those points above, I'd suggest you contact NXP support at > first to see if they can solve those build errors for you. > > If you would find a solution, you can send a PR to meta-freescale to > address it - this would be much appreciated. > >> >> built-in.o mtdcore.su mtdpart.o mtd_uboot.o mtd-uclass.o nand >> spi >> mtdcore.o mtd.o mtdpart.su mtd_uboot.su mtd-uclass.su onenand >> ubi >> >> >> >> On 1/15/21, Jupiter wrote: >> > Hello, >> > >> > I was able to build MTD, UBI and u-boot on OE version Zeus branch, but >> > failed in gatesgarth branch. Here are errors, what could I be missing? >> > >> > u-boot-imx/2020.04-r0/git/cmd/ubi.c:478: undefined reference to >> > `mtd_probe_devices' >> > u-boot-imx/2020.04-r0/git/cmd/ubi.c:484: undefined reference to >> > `put_mtd_device' >> > u-boot-imx/2020.04-r0/git/drivers/mtd/ubi/build.c:1161: undefined >> > reference to `put_mtd_device' >> > u-boot-imx/2020.04-r0/git/drivers/mtd/ubi/build.c:1229: undefined >> > reference to `get_mtd_device_nm' >> > u-boot-imx/2020.04-r0/git/drivers/mtd/ubi/io.c:1407: undefined >> > reference to `mtd_read' >> > u-boot-imx/2020.04-r0/git/drivers/mtd/ubi/io.c:279: undefined >> > reference to `mtd_write' >> > >> > u-boot-imx/2020.04-r0/git/drivers/video/cfb_console.c:2025: undefined >> > reference to `video_hw_init' >> > u-boot-imx/2020.04-r0/git/drivers/gpio/74x164_gpio.c:51: undefined >> > reference to `dm_spi_claim_bus' >> > u-boot-imx/2020.04-r0/git/drivers/gpio/74x164_gpio.c:55: undefined >> > reference to `dm_spi_xfer' >> > u-boot-imx/2020.04-r0/git/drivers/gpio/74x164_gpio.c:58: undefined >> > reference to `dm_spi_release_bus' >> > u-boot-imx/2020.04-r0/git/Makefile:1701: recipe for target 'u-boot' >> > failed >> > make[1]: *** [u-boot] Error 1 >> > WARNING: exit code 1 from a shell command. >> > >> > There are a couple of warning messages I am not sure if they are >> > important or just nonsense, like CONFIG_DEFAULT_DEVICE_TREE has >> > already been defined but it complained: >> > >> > Device Tree Source is not correctly specified. >> > Please define 'CONFIG_DEFAULT_DEVICE_TREE' >> > or build with 'DEVICE_TREE=' argument >> > >> > u-boot-imx/2020.04-r0/git/drivers/gpio/74x164_gpio.c:51:8: warning: >> > implicit declaration of function 'dm_spi_claim_bus'; did you mean >> > 'spi_claim_bus'? [-Wimplicit-function-declaration] >> >51 | ret = dm_spi_claim_bus(dev); >> > |^~~~ >> > |spi_claim_bus >> > @ >> > u-boot-imx/2020.04-r0/git/drivers/gpio/74x164_gpio.c:55:8: warning: >> > implicit declaration of function 'dm_spi_xfer'; did you mean >> > 'spi_xfer'? [-Wimplicit-function-declaration] >> >55 | ret = dm_spi_xfer(dev, priv->nregs * 8, priv->buffer, NULL, >> > |^~~ >> > |spi_xfer >> > u-boot-imx/2020.04-r0/git/drivers/gpio/74x164_gpio.c:58:2: warning: >> > implicit declaration of function 'dm_spi_release_bus'; did you mean >> > 'spi_release_bus'? [-Wimplicit-function-declaration] >> >58 | dm_spi_release_bus(dev); >> > | ^~ >> > | spi_release_bus >> > >> > Appreciate your
[PATCH] sunxi: don't define MACPWR and SATAPWR to empty strings
There's checks in board/sunxi/board.c if either MACPWR or SATAPWR are defined and they are defined by default to a empty string which means on vast majority of AllWinner boards when they're not required the code is still run and with SATAPWR we even get an unnecessary 500ms delay booting. So let's not define a default for these options so the code is only run for boards that need it. Signed-off-by: Peter Robinson --- arch/arm/mach-sunxi/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 49ef217f08..a566e10315 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -578,7 +578,6 @@ config OLD_SUNXI_KERNEL_COMPAT config MACPWR string "MAC power pin" - default "" help Set the pin used to power the MAC. This takes a string in the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. @@ -969,7 +968,6 @@ endchoice config SATAPWR string "SATA power pin" - default "" help Set the pins used to power the SATA. This takes a string in the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of -- 2.29.2
[PATCH 3/3] test: missing build dependency for test_print.c
test_print.c requires CONFIG_CONSOLE_RECORD=y. Signed-off-by: Heinrich Schuchardt --- test/lib/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/lib/Makefile b/test/lib/Makefile index 98a9abf40e..97c11e35a8 100644 --- a/test/lib/Makefile +++ b/test/lib/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_EFI_LOADER) += efi_device_path.o obj-$(CONFIG_EFI_SECURE_BOOT) += efi_image_region.o obj-y += hexdump.o obj-y += lmb.o -obj-y += test_print.o +obj-$(CONFIG_CONSOLE_RECORD) += test_print.o obj-$(CONFIG_SSCANF) += sscanf.o obj-y += string.o obj-$(CONFIG_ERRNO_STR) += test_errno_str.o -- 2.29.2
[PATCH 2/3] test: inconsistent string tests
Excluding ut str in test/cmd_ut.c but compiling test/str_ut.c results in
failure of the Python test invoking the C unit tests as observed on
sipeed_riscv_smode_defconfig:
FAILED test/py/tests/test_ut.py::test_ut[ut_str_upper]
Allow to compile test/str_ut.c on all boards.
Signed-off-by: Heinrich Schuchardt
---
test/cmd_ut.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/test/cmd_ut.c b/test/cmd_ut.c
index fad1c899a4..90674d5de5 100644
--- a/test/cmd_ut.c
+++ b/test/cmd_ut.c
@@ -89,9 +89,8 @@ static struct cmd_tbl cmd_ut_sub[] = {
U_BOOT_CMD_MKENT(bloblist, CONFIG_SYS_MAXARGS, 1, do_ut_bloblist,
"", ""),
U_BOOT_CMD_MKENT(bootm, CONFIG_SYS_MAXARGS, 1, do_ut_bootm, "", ""),
- U_BOOT_CMD_MKENT(str, CONFIG_SYS_MAXARGS, 1, do_ut_str,
-"", ""),
#endif
+ U_BOOT_CMD_MKENT(str, CONFIG_SYS_MAXARGS, 1, do_ut_str, "", ""),
};
static int do_ut_all(struct cmd_tbl *cmdtp, int flag, int argc,
--
2.29.2
[PATCH 1/3] test: inconsistent bootm tests
Excluding ut bootm in test/cmd_ut.c but compiling test/bootm.c results in
failure of the Python test invoking the C unit tests as observed on
sipeed_riscv_smode_defconfig:
FAILED test/py/tests/test_ut.py::test_ut[ut_bootm_nop]
FAILED test/py/tests/test_ut.py::test_ut[ut_bootm_nospace]
FAILED test/py/tests/test_ut.py::test_ut[ut_bootm_silent]
FAILED test/py/tests/test_ut.py::test_ut[ut_bootm_silent_var]
FAILED test/py/tests/test_ut.py::test_ut[ut_bootm_subst]
FAILED test/py/tests/test_ut.py::test_ut[ut_bootm_subst_both]
FAILED test/py/tests/test_ut.py::test_ut[ut_bootm_subst_var]
Only compile test/bootm.c on the sandbox.
Fixes: f158ba15ee0f ("bootm: Add tests for fixup_silent_linux()")
Signed-off-by: Heinrich Schuchardt
---
test/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/test/Makefile b/test/Makefile
index d4323f9963..7d3fc29493 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -4,8 +4,8 @@
ifneq ($(CONFIG_SANDBOX),)
obj-$(CONFIG_$(SPL_)CMDLINE) += bloblist.o
-endif
obj-$(CONFIG_$(SPL_)CMDLINE) += bootm.o
+endif
obj-$(CONFIG_$(SPL_)CMDLINE) += cmd/
obj-$(CONFIG_$(SPL_)CMDLINE) += cmd_ut.o
obj-$(CONFIG_$(SPL_)CMDLINE) += command_ut.o
--
2.29.2
Re: [PATCH 4/5] log: convert pr_*() to logging
On 1/17/21 11:27 PM, Sean Anderson wrote:
On 1/17/21 2:26 AM, Heinrich Schuchardt wrote:
On 1/17/21 1:37 AM, Sean Anderson wrote:
On 1/4/21 2:02 AM, Heinrich Schuchardt wrote:
In drivers we use a family of printing functions including pr_err() and
pr_cont(). CONFIG_LOGLEVEL is used to control which of these lead to
output
via printf().
Our logging functions allow finer grained control of output. So replace
printf() by the matching logging functions. The usage of
CONFIG_LOGLEVEL
remains unchanged.
Signed-off-by: Heinrich Schuchardt
---
include/linux/bitops.h | 4 ++-
include/linux/printk.h | 82
+++---
2 files changed, 48 insertions(+), 38 deletions(-)
diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index 16f28993f5..d2e5ca026e 100644
--- a/include/linux/bitops.h
+++ b/include/linux/bitops.h
@@ -6,7 +6,6 @@
#include
#include
#include
-#include
#ifdef __KERNEL__
#define BIT(nr) (1UL << (nr))
@@ -19,6 +18,9 @@
#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE *
sizeof(long))
#endif
+/* kernel.h includes log.h which include bitops.h */
+#include
+
/*
* Create a contiguous bitmask starting at bit position @l and
ending at
* position @h. For example
diff --git a/include/linux/printk.h b/include/linux/printk.h
index 088513ad29..5e85513853 100644
--- a/include/linux/printk.h
+++ b/include/linux/printk.h
@@ -1,6 +1,7 @@
#ifndef __KERNEL_PRINTK__
#define __KERNEL_PRINTK__
+#include
#include
#include
@@ -28,49 +29,56 @@
0; \
})
-#define __printk(level, fmt, ...) \
-({ \
- level < CONFIG_LOGLEVEL ? printk(fmt, ##__VA_ARGS__) : 0; \
Couldn't we just do
#define __printk(level, fmt, ...) log(LOG_CATEGORY, level, fmt,
##__VA_ARGS__)
Dear Sean,
Thanks for reviewing.
As of today log() does not print anything if CONFIG_LOG is not enabled.
#if CONFIG_IS_ENABLED(LOG)
#define _LOG_MAX_LEVEL CONFIG_VAL(LOG_MAX_LEVEL)
#define log_err(_fmt...) log(LOG_CATEGORY, LOGL_ERR, ##_fmt)
#define log_warning(_fmt...) log(LOG_CATEGORY, LOGL_WARNING, ##_fmt)
#define log_notice(_fmt...) log(LOG_CATEGORY, LOGL_NOTICE, ##_fmt)
#define log_info(_fmt...) log(LOG_CATEGORY, LOGL_INFO, ##_fmt)
#define log_debug(_fmt...) log(LOG_CATEGORY, LOGL_DEBUG, ##_fmt)
#define log_content(_fmt...) log(LOG_CATEGORY, LOGL_DEBUG_CONTENT,
##_fmt)
#define log_io(_fmt...) log(LOG_CATEGORY, LOGL_DEBUG_IO, ##_fmt)
#else
#define _LOG_MAX_LEVEL LOGL_INFO
#define log_err(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
#define log_warning(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
#define log_notice(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
#define log_info(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
#define log_debug(_fmt, ...) debug(_fmt, ##__VA_ARGS__)
#define log_content(_fmt...) log_nop(LOG_CATEGORY, \
LOGL_DEBUG_CONTENT, ##_fmt)
#define log_io(_fmt...) log_nop(LOG_CATEGORY, LOGL_DEBUG_IO,
##_fmt)
#endif
If CONFIG_LOG is not enabled, then log statements are converted to
debug and printf.
Only the ones you cited, not the function log() referenced in your proposal.
A patch by Simon to change this behavior is pending. If it gets
merged, we can do the suggested simplification.
log: Convert log values to printf() if not enabled
https://patchwork.ozlabs.org/project/uboot/patch/20210114033051.483560-5-...@chromium.org/
-})
-
#ifndef pr_fmt
#define pr_fmt(fmt) fmt
#endif
-#define pr_emerg(fmt, ...) \
- __printk(0, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_alert(fmt, ...) \
- __printk(1, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_crit(fmt, ...) \
- __printk(2, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_err(fmt, ...) \
- __printk(3, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_warning(fmt, ...) \
- __printk(4, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_warn pr_warning
-#define pr_notice(fmt, ...) \
- __printk(5, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_info(fmt, ...) \
- __printk(6, pr_fmt(fmt), ##__VA_ARGS__)
-
-#define pr_cont(fmt, ...) \
- printk(fmt, ##__VA_ARGS__)
-
-/* pr_devel() should produce zero code unless DEBUG is defined */
-#ifdef DEBUG
-#define pr_devel(fmt, ...) \
- __printk(7, pr_fmt(fmt), ##__VA_ARGS__)
-#else
-#define pr_devel(fmt, ...) \
- no_printk(pr_fmt(fmt), ##__VA_ARGS__)
-#endif
+#define pr_emerg(fmt, ...) \
+({ \
+ CONFIG_LOGLEVEL > 0 ? log_emerg(fmt, ##__VA_ARGS__) : 0; \
+})
There is also an off-by-one mismatch between the numbers here and the
log level constants. E.g. LOGL_INFO is 6, but pr_info only gets emitted
if CONFIG_LOGLEVEL is >= 7.
The Kconfig for CONFIG_LOGLEVEL description reads:
"All Messages with a loglevel *smaller than* the console loglevel will
be compiled in."
Ok then, perhaps that should be rectified.
The current definition allows
CRASH caused by: [PATCH 06/10] setexpr: Add some tests for buffer overflow and backref
On 11/1/20 10:15 PM, Simon Glass wrote:
Add tests to check for buffer overflow using simple replacement as well
as back references. At present these don't fully pass.
Signed-off-by: Simon Glass
---
cmd/setexpr.c | 21 +++
include/command.h | 17 +
test/cmd/setexpr.c | 89 ++
3 files changed, 110 insertions(+), 17 deletions(-)
diff --git a/cmd/setexpr.c b/cmd/setexpr.c
index fe3435b4d99..dbb43b3be2f 100644
--- a/cmd/setexpr.c
+++ b/cmd/setexpr.c
@@ -134,22 +134,8 @@ static char *substitute(char *string, int *slen, int ssize,
return p + nlen;
}
-/**
- * regex_sub() - Replace a regex pattern with a string
- *
- * @data: Buffer containing the string to update
- * @data_size: Size of buffer (must be large enough for the new string)
- * @nbuf: Back-reference buffer
- * @nbuf_size: Size of back-reference buffer (must be larger enough for @s plus
- * all back-reference expansions)
- * @r: Regular expression to find
- * @s: String to replace with
- * @global: true to replace all matches in @data, false to replace just the
- * first
- * @return 0 if OK, 1 on error
- */
-static int regex_sub(char *data, uint data_size, char *nbuf, uint nbuf_size,
-const char *r, const char *s, bool global)
+int setexpr_regex_sub(char *data, uint data_size, char *nbuf, uint nbuf_size,
+ const char *r, const char *s, bool global)
{
struct slre slre;
char *datap = data;
@@ -325,7 +311,8 @@ static int regex_sub_var(const char *name, const char *r,
const char *s,
strcpy(data, t);
- ret = regex_sub(data, SLRE_BUFSZ, nbuf, SLRE_PATSZ, r, s, global);
+ ret = setexpr_regex_sub(data, SLRE_BUFSZ, nbuf, SLRE_PATSZ, r, s,
+ global);
if (ret)
return 1;
diff --git a/include/command.h b/include/command.h
index e900f97df33..e229bf2825c 100644
--- a/include/command.h
+++ b/include/command.h
@@ -183,6 +183,23 @@ extern int do_env_set_efi(struct cmd_tbl *cmdtp, int flag,
int argc,
char *const argv[]);
#endif
+/**
+ * setexpr_regex_sub() - Replace a regex pattern with a string
+ *
+ * @data: Buffer containing the string to update
+ * @data_size: Size of buffer (must be large enough for the new string)
+ * @nbuf: Back-reference buffer
+ * @nbuf_size: Size of back-reference buffer (must be larger enough for @s plus
+ * all back-reference expansions)
+ * @r: Regular expression to find
+ * @s: String to replace with
+ * @global: true to replace all matches in @data, false to replace just the
+ * first
+ * @return 0 if OK, 1 on error
+ */
+int setexpr_regex_sub(char *data, uint data_size, char *nbuf, uint nbuf_size,
+ const char *r, const char *s, bool global);
+
/*
* Error codes that commands return to cmd_process(). We use the standard 0
* and 1 for success and failure, but add one more case - failure with a
diff --git a/test/cmd/setexpr.c b/test/cmd/setexpr.c
index de54561917c..a6940fd82dd 100644
--- a/test/cmd/setexpr.c
+++ b/test/cmd/setexpr.c
@@ -209,6 +209,95 @@ static int setexpr_test_regex_inc(struct unit_test_state
*uts)
}
SETEXPR_TEST(setexpr_test_regex_inc, UT_TESTF_CONSOLE_REC);
+/* Test setexpr_regex_sub() directly to check buffer usage */
+static int setexpr_test_sub(struct unit_test_state *uts)
+{
+ char *buf, *nbuf;
+ int i;
+
+ buf = map_sysmem(0, BUF_SIZE);
+ nbuf = map_sysmem(0x1000, BUF_SIZE);
+
+ /* Add a pattern so we can check the buffer limits */
+ memset(buf, '\xff', BUF_SIZE);
+ memset(nbuf, '\xff', BUF_SIZE);
+ for (i = BUF_SIZE; i < 0x1000; i++) {
+ buf[i] = i & 0xff;
+ nbuf[i] = i & 0xff;
+ }
+ strcpy(buf, "this is a test");
+
+ /*
+* This is a regression test, since a bug was found in the use of
+* memmove() in setexpr
+*/
+ ut_assertok(setexpr_regex_sub(buf, BUF_SIZE, nbuf, BUF_SIZE, "is",
+ "us it is longer", true));
+ ut_asserteq_str("thus it is longer us it is longer a test", buf);
+
+ /* The following checks fail at present due to a bug in setexpr */
+ return 0;
+ for (i = BUF_SIZE; i < 0x1000; i++) {
+ ut_assertf(buf[i] == (char)i,
+ "buf byte at %x should be %02x, got %02x)\n",
+ i, i & 0xff, (u8)buf[i]);
+ ut_assertf(nbuf[i] == (char)i,
+ "nbuf byte at %x should be %02x, got %02x)\n",
+ i, i & 0xff, (u8)nbuf[i]);
+ }
+
+ unmap_sysmem(buf);
+
+ return 0;
+}
+SETEXPR_TEST(setexpr_test_sub, UT_TESTF_CONSOLE_REC);
+
+/* Test setexpr_regex_sub() with back references */
+static int setexpr_test_backref(struct unit_test_state *uts)
+{
+ char *buf, *nbuf;
+ int i;
+
+ buf = map_sysmem(0,
Re: [PATCH 4/5] log: convert pr_*() to logging
On 1/17/21 2:26 AM, Heinrich Schuchardt wrote:
On 1/17/21 1:37 AM, Sean Anderson wrote:
On 1/4/21 2:02 AM, Heinrich Schuchardt wrote:
In drivers we use a family of printing functions including pr_err() and
pr_cont(). CONFIG_LOGLEVEL is used to control which of these lead to output
via printf().
Our logging functions allow finer grained control of output. So replace
printf() by the matching logging functions. The usage of CONFIG_LOGLEVEL
remains unchanged.
Signed-off-by: Heinrich Schuchardt
---
include/linux/bitops.h | 4 ++-
include/linux/printk.h | 82 +++---
2 files changed, 48 insertions(+), 38 deletions(-)
diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index 16f28993f5..d2e5ca026e 100644
--- a/include/linux/bitops.h
+++ b/include/linux/bitops.h
@@ -6,7 +6,6 @@
#include
#include
#include
-#include
#ifdef__KERNEL__
#define BIT(nr)(1UL << (nr))
@@ -19,6 +18,9 @@
#define BITS_TO_LONGS(nr)DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
#endif
+/* kernel.h includes log.h which include bitops.h */
+#include
+
/*
* Create a contiguous bitmask starting at bit position @l and ending at
* position @h. For example
diff --git a/include/linux/printk.h b/include/linux/printk.h
index 088513ad29..5e85513853 100644
--- a/include/linux/printk.h
+++ b/include/linux/printk.h
@@ -1,6 +1,7 @@
#ifndef __KERNEL_PRINTK__
#define __KERNEL_PRINTK__
+#include
#include
#include
@@ -28,49 +29,56 @@
0;\
})
-#define __printk(level, fmt, ...)\
-({\
-level < CONFIG_LOGLEVEL ? printk(fmt, ##__VA_ARGS__) : 0;\
Couldn't we just do
#define __printk(level, fmt, ...) log(LOG_CATEGORY, level, fmt, ##__VA_ARGS__)
Dear Sean,
Thanks for reviewing.
As of today log() does not print anything if CONFIG_LOG is not enabled.
#if CONFIG_IS_ENABLED(LOG)
#define _LOG_MAX_LEVEL CONFIG_VAL(LOG_MAX_LEVEL)
#define log_err(_fmt...)log(LOG_CATEGORY, LOGL_ERR, ##_fmt)
#define log_warning(_fmt...)log(LOG_CATEGORY, LOGL_WARNING, ##_fmt)
#define log_notice(_fmt...) log(LOG_CATEGORY, LOGL_NOTICE, ##_fmt)
#define log_info(_fmt...) log(LOG_CATEGORY, LOGL_INFO, ##_fmt)
#define log_debug(_fmt...) log(LOG_CATEGORY, LOGL_DEBUG, ##_fmt)
#define log_content(_fmt...)log(LOG_CATEGORY, LOGL_DEBUG_CONTENT, ##_fmt)
#define log_io(_fmt...) log(LOG_CATEGORY, LOGL_DEBUG_IO, ##_fmt)
#else
#define _LOG_MAX_LEVEL LOGL_INFO
#define log_err(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
#define log_warning(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
#define log_notice(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
#define log_info(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
#define log_debug(_fmt, ...)debug(_fmt, ##__VA_ARGS__)
#define log_content(_fmt...)log_nop(LOG_CATEGORY, \
LOGL_DEBUG_CONTENT, ##_fmt)
#define log_io(_fmt...) log_nop(LOG_CATEGORY, LOGL_DEBUG_IO, ##_fmt)
#endif
If CONFIG_LOG is not enabled, then log statements are converted to
debug and printf.
A patch by Simon to change this behavior is pending. If it gets merged, we can
do the suggested simplification.
log: Convert log values to printf() if not enabled
https://patchwork.ozlabs.org/project/uboot/patch/20210114033051.483560-5-...@chromium.org/
-})
-
#ifndef pr_fmt
#define pr_fmt(fmt) fmt
#endif
-#define pr_emerg(fmt, ...) \
-__printk(0, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_alert(fmt, ...) \
-__printk(1, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_crit(fmt, ...) \
-__printk(2, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_err(fmt, ...) \
-__printk(3, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_warning(fmt, ...) \
-__printk(4, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_warn pr_warning
-#define pr_notice(fmt, ...) \
-__printk(5, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_info(fmt, ...) \
-__printk(6, pr_fmt(fmt), ##__VA_ARGS__)
-
-#define pr_cont(fmt, ...) \
-printk(fmt, ##__VA_ARGS__)
-
-/* pr_devel() should produce zero code unless DEBUG is defined */
-#ifdef DEBUG
-#define pr_devel(fmt, ...) \
-__printk(7, pr_fmt(fmt), ##__VA_ARGS__)
-#else
-#define pr_devel(fmt, ...) \
-no_printk(pr_fmt(fmt), ##__VA_ARGS__)
-#endif
+#define pr_emerg(fmt, ...)\
+({\
+CONFIG_LOGLEVEL > 0 ? log_emerg(fmt, ##__VA_ARGS__) : 0;\
+})
There is also an off-by-one mismatch between the numbers here and the
log level constants. E.g. LOGL_INFO is 6, but pr_info only gets emitted
if CONFIG_LOGLEVEL is >= 7.
The Kconfig for CONFIG_LOGLEVEL description reads:
"All Messages with a loglevel *smaller than* the console loglevel will be compiled
in."
Ok then, perhaps that should be rectified.
--Sean
I did not intend to change this definition.
Best regards
Heinrich
--Sean
+#define pr_alert(fmt, ...)
Re: [RFC PATCH] common: board_f: add print_archinfo to display arch information
Hi Tom, On 1/16/21 3:11 AM, Tom Rini wrote: > On Fri, Jan 15, 2021 at 01:46:54PM +0900, Jaehoon Chung wrote: > >> Current U-boot doesn't display a message about which architecture is >> used. So Developer is difficult to know it by intuition. >> This patch is displaying to CPU information with CONFIG_SYS_CPU. >> >> CPU: armv8 >> DARM: 3.9 GiB >> >> Signed-off-by: Jaehoon Chung > > We have a large number of "CPU: " prints today, under > CONFIG_DISPLAY_CPUINFO which is what I think you're looking for. Thanks for sharing it. Frankly, i had found CONFIG_DISPLAY_CPUINFO, but i have misunderstood about it. So That's why i sent RFC patch. Thanks! Best Regards, Jaehoon Chung >
[PATCH 1/1] cmd/riscv/sbi: support System Reset Extension
Let the sbi command detect the 'System Reset Extension'
(EID #0x53525354 "SRST").
Cf. https://github.com/riscv/riscv-sbi-doc
Signed-off-by: Heinrich Schuchardt
---
cmd/riscv/sbi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index e66fc8e41d..9897483eb6 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -29,6 +29,7 @@ static struct sbi_ext extensions[] = {
{ 0x00735049, "IPI Extension" },
{ 0x52464E43, "RFENCE Extension" },
{ 0x0048534D, "Hart State Management Extension" },
+ { 0x53525354, "System Reset Extension" },
};
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
--
2.28.0
[PATCH v3] arm: rmobile: Add HopeRun HiHope RZ/G2H board support
The HiHope RZ/G2H board from HopeRun consists of main board (HopeRun HiHope RZ/G2H main board) and sub board(HopeRun HiHope RZ/G2H sub board). The HiHope RZ/G2H sub board sits below the HiHope RZ/G2H main board. This patch adds the required board support to boot HopeRun HiHope RZ/G2H board. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- This patch series depend on [1] and [2] [1]https://patchwork.ozlabs.org/project/uboot/list/?series=224837 [2]https://patchwork.ozlabs.org/project/uboot/patch/20210117163013.6702-3-biju.das...@bp.renesas.com/ v3: * Separated DT patches v1->v2: * No Change. rebased on u-boot-sh/next v1: * New patch --- arch/arm/dts/Makefile | 1 + arch/arm/mach-rmobile/Kconfig.64| 1 + board/hoperun/hihope-rzg2/hihope-rzg2.c | 6 +- configs/hihope_rzg2_defconfig | 2 +- 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 12943776a7..41e067b373 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -804,6 +804,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \ r8a774a1-beacon-rzg2m-kit.dtb \ r8a774a1-hihope-rzg2m-u-boot.dtb \ r8a774b1-hihope-rzg2n-u-boot.dtb \ + r8a774e1-hihope-rzg2h-u-boot.dtb \ r8a77950-ulcb-u-boot.dtb \ r8a77950-salvator-x-u-boot.dtb \ r8a77960-ulcb-u-boot.dtb \ diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 18153a809e..56c522596a 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -95,6 +95,7 @@ config TARGET_HIHOPE_RZG2 bool "HiHope RZ/G2 board" imply R8A774A1 imply R8A774B1 + imply R8A774E1 imply SYS_MALLOC_F imply MULTI_DTB_FIT imply MULTI_DTB_FIT_USER_DEFINED_AREA diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c index 66854bcadc..cb3dcf8db2 100644 --- a/board/hoperun/hihope-rzg2/hihope-rzg2.c +++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * board/hoperun/hihope-rzg2/hihope-rzg2.c - * This file is HiHope RZ/G2[MN] board support. + * This file is HiHope RZ/G2[HMN] board support. * * Copyright (C) 2020 Renesas Electronics Corporation */ @@ -90,6 +90,10 @@ int board_fit_config_name_match(const char *name) !strcmp(name, "r8a774b1-hihope-rzg2n-u-boot")) return 0; + if (soc_id == SOC_ID_R8A774E1 && + !strcmp(name, "r8a774e1-hihope-rzg2h-u-boot")) + return 0; + return -1; } #endif diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index 3c37a80405..57eab4519e 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot r8a774b1-hihope-rzg2n-u-boot" +CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot r8a774b1-hihope-rzg2n-u-boot r8a774e1-hihope-rzg2h-u-boot" CONFIG_MULTI_DTB_FIT_LZO=y CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y CONFIG_ENV_OVERWRITE=y -- 2.17.1
[PATCH v3] arm: rmobile: Add HopeRun HiHope RZ/G2N board support
The HiHope RZ/G2N board from HopeRun consists of main board (HopeRun HiHope RZ/G2N main board) and sub board(HopeRun HiHope RZ/G2N sub board). The HiHope RZ/G2N sub board sits below the HiHope RZ/G2N main board. This patch adds the required board support to boot HopeRun HiHope RZ/G2N board. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- This patch series depend on [1] and [2] [1]https://patchwork.ozlabs.org/project/uboot/list/?series=224837 [2]https://patchwork.ozlabs.org/project/uboot/patch/20210117163013.6702-2-biju.das...@bp.renesas.com/ v3: * Seperated DT patches v1->v2: * No Change. rebased on u-boot-sh/next v1: * New patch --- arch/arm/dts/Makefile | 1 + arch/arm/mach-rmobile/Kconfig.64| 1 + board/hoperun/hihope-rzg2/hihope-rzg2.c | 6 +- configs/hihope_rzg2_defconfig | 2 +- 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dc4bc90019..12943776a7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -803,6 +803,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \ dtb-$(CONFIG_RCAR_GEN3) += \ r8a774a1-beacon-rzg2m-kit.dtb \ r8a774a1-hihope-rzg2m-u-boot.dtb \ + r8a774b1-hihope-rzg2n-u-boot.dtb \ r8a77950-ulcb-u-boot.dtb \ r8a77950-salvator-x-u-boot.dtb \ r8a77960-ulcb-u-boot.dtb \ diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 47ca4bfb2e..18153a809e 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -94,6 +94,7 @@ config TARGET_EBISU config TARGET_HIHOPE_RZG2 bool "HiHope RZ/G2 board" imply R8A774A1 + imply R8A774B1 imply SYS_MALLOC_F imply MULTI_DTB_FIT imply MULTI_DTB_FIT_USER_DEFINED_AREA diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c index d49ad78871..66854bcadc 100644 --- a/board/hoperun/hihope-rzg2/hihope-rzg2.c +++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * board/hoperun/hihope-rzg2/hihope-rzg2.c - * This file is HiHope RZ/G2M board support. + * This file is HiHope RZ/G2[MN] board support. * * Copyright (C) 2020 Renesas Electronics Corporation */ @@ -86,6 +86,10 @@ int board_fit_config_name_match(const char *name) !strcmp(name, "r8a774a1-hihope-rzg2m-u-boot")) return 0; + if (soc_id == SOC_ID_R8A774B1 && + !strcmp(name, "r8a774b1-hihope-rzg2n-u-boot")) + return 0; + return -1; } #endif diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index 5e568ab8ed..3c37a80405 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot" +CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot r8a774b1-hihope-rzg2n-u-boot" CONFIG_MULTI_DTB_FIT_LZO=y CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y CONFIG_ENV_OVERWRITE=y -- 2.17.1
[PATCH v8] arm: rmobile: Add HopeRun HiHope RZ/G2M board support
The HiHope RZ/G2M board from HopeRun consists of main board (HopeRun HiHope RZ/G2M main board) and sub board(HopeRun HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits below the HiHope RZ/G2M main board. This patch adds the required board support to boot HopeRun HiHope RZ/G2M board. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- This patch depend on [1] and [2] [1]https://patchwork.ozlabs.org/project/uboot/patch/20210117163013.6702-1-biju.das...@bp.renesas.com/ [2]https://patchwork.ozlabs.org/project/uboot/list/?series=224837 v7->v8 * Seperated DT patches V6->V7 * Seperated driver patches from board support patches. v5->v6 * Rebased to U-boot-sh/master * Changed the logic for USB0 channel0 Host support. * Enabled CONFIG_SOC_DEVICE_RENESAS option V4->V5 * Rebased to U-boot-sh/next (Ref: https://patchwork.ozlabs.org/project/uboot/patch/20201012151616.5384-4-biju.das.jz@.../) V3->V4 * Added USB0 channel0 Host support (Ref: https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-2-biju.das.jz@.../) V2->V3 * Reworked as per Marek's suggestion * Added rzg2_get_cpu_type function to get cpu_type by matching TFA compatible string * Removed SoC family type Enum Ref: https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-3-biju.das.jz@.../ V1->V2 * Fixed indentation for R8A774A1 config * Used GPIO hog for setting WLAN/BT REG ON * Removed USB related initialization Ref: https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-2-biju.das.jz@.../ V1:- * New Patch Ref: https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-5-biju.das.jz@.../ --- arch/arm/dts/Makefile | 1 + arch/arm/mach-rmobile/Kconfig.64| 14 board/hoperun/hihope-rzg2/Kconfig | 15 board/hoperun/hihope-rzg2/MAINTAINERS | 6 ++ board/hoperun/hihope-rzg2/Makefile | 9 +++ board/hoperun/hihope-rzg2/hihope-rzg2.c | 91 + configs/hihope_rzg2_defconfig | 79 + include/configs/hihope-rzg2.h | 20 ++ 8 files changed, 235 insertions(+) create mode 100644 board/hoperun/hihope-rzg2/Kconfig create mode 100644 board/hoperun/hihope-rzg2/MAINTAINERS create mode 100644 board/hoperun/hihope-rzg2/Makefile create mode 100644 board/hoperun/hihope-rzg2/hihope-rzg2.c create mode 100644 configs/hihope_rzg2_defconfig create mode 100644 include/configs/hihope-rzg2.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a9d36e0e9c..dc4bc90019 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -802,6 +802,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \ dtb-$(CONFIG_RCAR_GEN3) += \ r8a774a1-beacon-rzg2m-kit.dtb \ + r8a774a1-hihope-rzg2m-u-boot.dtb \ r8a77950-ulcb-u-boot.dtb \ r8a77950-salvator-x-u-boot.dtb \ r8a77960-ulcb-u-boot.dtb \ diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 0ef6cf619b..47ca4bfb2e 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -4,6 +4,8 @@ menu "Select Target SoC" config R8A774A1 bool "Renesas SoC R8A774A1" + imply CLK_R8A774A1 + imply PINCTRL_PFC_R8A774A1 config R8A774B1 bool "Renesas SoC R8A774B1" @@ -89,6 +91,15 @@ config TARGET_EBISU help Support for Renesas R-Car Gen3 Ebisu platform +config TARGET_HIHOPE_RZG2 + bool "HiHope RZ/G2 board" + imply R8A774A1 + imply SYS_MALLOC_F + imply MULTI_DTB_FIT + imply MULTI_DTB_FIT_USER_DEFINED_AREA + help + Support for RZG2 HiHope platform + config TARGET_SALVATOR_X bool "Salvator-X board" imply R8A7795 @@ -123,12 +134,15 @@ source "board/renesas/ebisu/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" source "board/beacon/beacon-rzg2m/Kconfig" +source "board/hoperun/hihope-rzg2/Kconfig" config MULTI_DTB_FIT_UNCOMPRESS_SZ + default 0x8 if TARGET_HIHOPE_RZG2 default 0x8 if TARGET_SALVATOR_X default 0x8 if TARGET_ULCB config MULTI_DTB_FIT_USER_DEF_ADDR + default 0x4900 if TARGET_HIHOPE_RZG2 default 0x4900 if TARGET_SALVATOR_X default 0x4900 if TARGET_ULCB diff --git a/board/hoperun/hihope-rzg2/Kconfig b/board/hoperun/hihope-rzg2/Kconfig new file mode 100644 index 00..ee422ba6c8 --- /dev/null +++ b/board/hoperun/hihope-rzg2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_HIHOPE_RZG2 + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "hihope-rzg2" + +config SYS_VENDOR + default "hoperun" + +config SYS_CONFIG_NAME + default "hihope-rzg2" + +endif diff --git a/board/hoperun/hihope-rzg2/MAINTAINERS b/board/hoperun/hihope-rzg2/MAINTAINERS new file mode 100644 index 00..e3702fd12e --- /dev/null +++ b/board/hoperun/hihope-rzg2/MAINTAINERS @@ -0,0 +1,6 @@ +HIHOPE_RZG2
Re: [PATCH v2] Nokia RX-51: Convert to CONFIG_DM_MMC
On 16/01/21 9:51 pm, Tom Rini wrote: > On Sat, Jan 16, 2021 at 01:04:54AM +0100, Pali Rohár wrote: > >> Move twl4030_power_mmc_init() from board_mmc_power_init() to misc_init_r() >> and disable CONFIG_SYS_MALLOC_F. Otherwise U-Boot cannot initialize MMC. >> Also disable CONFIG_CMD_SLEEP CONFIG_DM_DEVICE_REMOVE CONFIG_MMC_VERBOSE to >> free some space. >> >> Signed-off-by: Pali Rohár >> > > Reviewed-by: Tom Rini > Applied to u-boot-ti/for-rc branch. Thanks and regards, Lokesh
Re: [PATCH 1/1] am335x, guardian: software update available status is stored in AM3352 RTC scracth register
On 06/01/21 9:02 pm, gireesh.hirem...@in.bosch.com wrote: > From: Gireesh Hiremath > > RTC second scratch register[32-bit]: > -zero byte hold boot count value > -first byte hold update available state > -second byte hold version > -third byte hold magic number > > Signed-off-by: Gireesh Hiremath > > Gbp-Pq: Topic apertis/guardian > Gbp-Pq: Name am335x-guardian-software-update-available-status-is-store.patch Hmm..not sure what this is.. Cover letter is not needed for a single patch btw. > --- > configs/am335x_guardian_defconfig | 1 + > drivers/bootcount/Kconfig | 27 -- > drivers/bootcount/Makefile | 1 + > drivers/bootcount/bootcount_nvmem.c | 57 + Please split driver and defconfig changes. > 4 files changed, 83 insertions(+), 3 deletions(-) > create mode 100644 drivers/bootcount/bootcount_nvmem.c > > diff --git a/configs/am335x_guardian_defconfig > b/configs/am335x_guardian_defconfig > index b5d8d80d14..c8336a8256 100644 > --- a/configs/am335x_guardian_defconfig > +++ b/configs/am335x_guardian_defconfig > @@ -71,6 +71,7 @@ CONFIG_VERSION_VARIABLE=y > CONFIG_BOOTP_SEND_HOSTNAME=y > CONFIG_SPL_DM=y > CONFIG_BOOTCOUNT_LIMIT=y > +CONFIG_BOOTCOUNT_AM33XX_NVMEM=y > CONFIG_LED=y > CONFIG_LED_GPIO=y > CONFIG_MISC=y > diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig > index b5ccea0d9c..d543061233 100644 > --- a/drivers/bootcount/Kconfig > +++ b/drivers/bootcount/Kconfig > @@ -42,6 +42,25 @@ config BOOTCOUNT_AM33XX > This requires the RTC clocks, etc, to be enabled prior to use and > not all boards with this IP block on it will have the RTC in use. > > +config BOOTCOUNT_AM33XX_NVMEM > + bool "Boot counter in AM33XX RTC IP block with upgrade_available flag" > + depends on AM33XX > +select SPL_AM33XX_ENABLE_RTC32K_OSC if AM33XX > + help > + Add support for maintaining bootcount,upgrade_available, > + version and BOOTMAGIC in a AM33xx RTC IP block > + scratch register2. > + > + A bootcount driver for the RTC IP block found on many TI platforms. > + This requires the RTC clocks, etc, to be enabled prior to use and > + not all boards with this IP block on it will have the RTC in use. > + > + If there is upgrade in software then "upgrade_available" is 1, > + "bootcount" is incremented otherwise "upgrade_available" and > + "bootcount" is always 0. So the Userspace Application must set > + the "upgrade_available" and "bootcount" variable to 0, if a boot > + was successfully. > + Isn't it possible to re-use drivers/bootcount/bootcount_davinci.c? Thanks and regards, Lokesh > config BOOTCOUNT_ENV > bool "Boot counter in environment" > help > @@ -177,16 +196,18 @@ config SYS_BOOTCOUNT_EXT_NAME > > config SYS_BOOTCOUNT_ADDR > hex "RAM address used for reading and writing the boot counter" > - default 0x44E3E000 if BOOTCOUNT_AM33XX > + default 0x44E3E000 if BOOTCOUNT_AM33XX || BOOTCOUNT_AM33XX_NVMEM > default 0xE0115FF8 if ARCH_LS1043A || ARCH_LS1021A > depends on BOOTCOUNT_AM33XX || BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \ > -BOOTCOUNT_I2C > +BOOTCOUNT_I2C || BOOTCOUNT_AM33XX_NVMEM > help > Set the address used for reading and writing the boot counter. > > config SYS_BOOTCOUNT_MAGIC > hex "Magic value for the boot counter" > - default 0xB001C041 > + default 0xB001C041 if BOOTCOUNT_AM33XX > + default 0xB0 if BOOTCOUNT_AM33XX_NVMEM > + depends on BOOTCOUNT_AM33XX || BOOTCOUNT_AM33XX_NVMEM > help > Set the magic value used for the boot counter. > > diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile > index 51d860b00e..12658ffdce 100644 > --- a/drivers/bootcount/Makefile > +++ b/drivers/bootcount/Makefile > @@ -8,6 +8,7 @@ obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o > obj-$(CONFIG_BOOTCOUNT_ENV) += bootcount_env.o > obj-$(CONFIG_BOOTCOUNT_I2C) += bootcount_i2c.o > obj-$(CONFIG_BOOTCOUNT_EXT) += bootcount_ext.o > +obj-$(CONFIG_BOOTCOUNT_AM33XX_NVMEM) += bootcount_nvmem.o > > obj-$(CONFIG_DM_BOOTCOUNT) += bootcount-uclass.o > obj-$(CONFIG_DM_BOOTCOUNT_RTC) += rtc.o > diff --git a/drivers/bootcount/bootcount_nvmem.c > b/drivers/bootcount/bootcount_nvmem.c > new file mode 100644 > index 00..5f266d5ec8 > --- /dev/null > +++ b/drivers/bootcount/bootcount_nvmem.c > @@ -0,0 +1,57 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * (C) Copyright 2011 > + * Heiko Schocher, DENX Software Engineering, h...@denx.de. > + * (C) Copyright 2018 Robert Bosch Power Tools GmbH. > + * > + * A bootcount driver for the RTC IP block found on many TI platforms. > + * This requires the RTC clocks, etc, to be enabled prior to use and > + * not all boards with this IP block on it will have the RTC in use. > + */ > + > +#include > +#include > + > +#define
[PATCH] arm: dts: rmobile: r8a774e1: Synchronize DTs with Linux 5.10
DTS files apart from r8a774e1-hihope-rzg2h-u-boot.dts and
r8a774e1-u-boot.dtsi have been imported from linux 5.10
commit 2c85ebc57b3e1817b6 ("Linux 5.10").
Signed-off-by: Biju Das
---
arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts | 20 +
arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts | 27 +
arch/arm/dts/r8a774e1-hihope-rzg2h.dts| 41 +
arch/arm/dts/r8a774e1-u-boot.dtsi | 59 +
arch/arm/dts/r8a774e1.dtsi| 1342 -
5 files changed, 1461 insertions(+), 28 deletions(-)
create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h.dts
create mode 100644 arch/arm/dts/r8a774e1-u-boot.dtsi
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
new file mode 100644
index 00..a0f98fd62c
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H sub board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2H with sub board";
+ compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
+"renesas,r8a774e1";
+};
+
+/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
new file mode 100644
index 00..d7afb55d8b
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2H board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h-ex.dts"
+#include "r8a774e1-u-boot.dtsi"
+
+ {
+ bt_reg_on{
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "bt-reg-on";
+ };
+};
+
+ {
+ wlan_reg_on{
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "wlan-reg-on";
+ };
+};
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
new file mode 100644
index 00..e3a78c9c58
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H main board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774e1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
+ compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
+
+ memory@4800 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x4800 0x0 0x7800>;
+ };
+
+ memory@5 {
+ device_type = "memory";
+ reg = <0x5 0x 0x0 0x8000>;
+ };
+};
+
+ {
+ clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+< CPG_MOD 721>,
+< 1>,
+<_clk>,
+< 2>;
+ clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
+
+ {
+ mmc-hs400-1_8v;
+};
diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi
b/arch/arm/dts/r8a774e1-u-boot.dtsi
new file mode 100644
index 00..5fe432c3f7
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-u-boot.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RZ/G2 R8A774E1 SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+_clk {
+ u-boot,dm-pre-reloc;
+};
+
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/ _sound;
+/delete-node/
+/delete-node/ _card;
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+
+/ {
+ /delete-node/ hdmi0-out;
+};
+
+/ {
+ soc {
+ /delete-node/ fdp1@fe94;
+ /delete-node/ fdp1@fe944000;
+ };
+};
diff --git a/arch/arm/dts/r8a774e1.dtsi b/arch/arm/dts/r8a774e1.dtsi
index 0f86cfd524..213f186092 100644
--- a/arch/arm/dts/r8a774e1.dtsi
+++ b/arch/arm/dts/r8a774e1.dtsi
@@ -2,7 +2,7 @@
/*
*
[PATCH] arm: dts: rmobile: r8a774a1: Synchronize DTs with Linux 5.10
DTS files apart from r8a774a1-hihope-rzg2m-u-boot.dts and
r8a774a1-u-boot.dtsi have been imported from linux 5.10
commit 2c85ebc57b3e1817 ("Linux 5.10").
Signed-off-by: Biju Das
---
arch/arm/dts/hihope-common.dtsi | 377 ++
arch/arm/dts/hihope-rev4.dtsi | 124 ++
arch/arm/dts/hihope-rzg2-ex.dtsi | 92 +
arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts | 21 +
arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts | 27 ++
arch/arm/dts/r8a774a1-hihope-rzg2m.dts| 37 ++
arch/arm/dts/r8a774a1-u-boot.dtsi | 55 +++
7 files changed, 733 insertions(+)
create mode 100644 arch/arm/dts/hihope-common.dtsi
create mode 100644 arch/arm/dts/hihope-rev4.dtsi
create mode 100644 arch/arm/dts/hihope-rzg2-ex.dtsi
create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts
create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts
create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m.dts
create mode 100644 arch/arm/dts/r8a774a1-u-boot.dtsi
diff --git a/arch/arm/dts/hihope-common.dtsi b/arch/arm/dts/hihope-common.dtsi
new file mode 100644
index 00..b1eb6a0802
--- /dev/null
+++ b/arch/arm/dts/hihope-common.dtsi
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
+ * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include
+
+/ {
+ aliases {
+ serial0 =
+ serial1 =
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ hdmi0-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi0_con: endpoint {
+ remote-endpoint = <_dw_hdmi0_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ gpios = < 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ led2 {
+ gpios = < 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ led3 {
+ gpios = < 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ led4 {
+ gpios = < 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_1p8v: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sound_card: sound {
+ compatible = "audio-graph-card";
+
+ label = "rcar-sound";
+
+ dais = <_port>;
+ };
+
+ vbus0_usb2: regulator-vbus0-usb2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB20_VBUS0";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+
+ gpio = < 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+
+ gpios = < 30 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <330 1>, <180 0>;
+ };
+
+ x302_clk: x302-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <3300>;
+ };
+
+ x304_clk: x304-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2500>;
+ };
+};
+
+_clk_a {
+ clock-frequency = <22579200>;
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_clk {
+ clock-frequency = <1666>;
+};
+
+_clk {
+ clock-frequency = <32768>;
+};
+
+ {
+ usb1-reset {
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "usb1-reset";
+ };
+};
+
+ {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <_con>;
+
[PATCH] arm: dts: rmobile: r8a774b1: Synchronize DTs with Linux 5.10
DTS files apart from r8a774b1-hihope-rzg2n-u-boot.dts and
r8a774b1-u-boot.dtsi have been imported from linux 5.10
commit 2c85ebc57b3e1817b6c ("Linux 5.10").
Signed-off-by: Biju Das
---
arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts | 21
arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts | 27 ++
arch/arm/dts/r8a774b1-hihope-rzg2n.dts| 41 ++
arch/arm/dts/r8a774b1-u-boot.dtsi | 53 +++
4 files changed, 142 insertions(+)
create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n.dts
create mode 100644 arch/arm/dts/r8a774b1-u-boot.dtsi
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
new file mode 100644
index 00..58812b41ac
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to
+ * sub board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2N with sub board";
+ compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
+"renesas,r8a774b1";
+};
+
+/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
new file mode 100644
index 00..0bdc6909bf
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n-ex.dts"
+#include "r8a774b1-u-boot.dtsi"
+
+ {
+ bt_reg_on{
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "bt-reg-on";
+ };
+};
+
+ {
+ wlan_reg_on{
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "wlan-reg-on";
+ };
+};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
new file mode 100644
index 00..b90790a95b
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774b1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
+ compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
+
+ memory@4800 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x4800 0x0 0x7800>;
+ };
+
+ memory@48000 {
+ device_type = "memory";
+ reg = <0x4 0x8000 0x0 0x8000>;
+ };
+};
+
+ {
+ clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+< CPG_MOD 721>,
+< 1>,
+<_clk>,
+< 2>;
+ clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
+
+ {
+ mmc-hs400-1_8v;
+};
diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi
b/arch/arm/dts/r8a774b1-u-boot.dtsi
new file mode 100644
index 00..6fab78e776
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-u-boot.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RZ/G2 R8A774B1 SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+_clk {
+ u-boot,dm-pre-reloc;
+};
+
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/ _sound;
+/delete-node/
+/delete-node/ _card;
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+/delete-node/
+
+/ {
+ /delete-node/ hdmi0-out;
+};
+
+/ {
+ soc {
+ /delete-node/ fdp1@fe94;
+ };
+};
--
2.17.1
[PATCH v9 4/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H
Add SDHI quirks for R-Car H3 and RZ/G2H SoC.
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
Reviewed-by: Jaehoon chung
---
v9:
* No Change.
v8:
* Added Jaehoon chung's Rb tag.
v7:
* No Change.
v6:
* New patch. quirks using soc_device_match.
---
drivers/mmc/renesas-sdhi.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 055fdbbc99..6b3cb02a3e 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -879,6 +879,16 @@ static const struct renesas_sdhi_quirks
sdhi_quirks_4tap_nohs400 = {
.hs400_4taps = true,
};
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
+ .hs400_4taps = true,
+ .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7795_es30 = {
+ .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+ .hs400_calib_table = r8a7795_calib_table,
+};
+
static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
.hs400_4taps = true,
.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
@@ -920,6 +930,26 @@ static const struct soc_attr sdhi_quirks_match[] = {
{ .soc_id = "r8a774b1",
.data = _quirks_r8a77965
},
+ { .soc_id = "r8a774e1",
+ .revision = "ES3.0",
+ .data = _quirks_r8a7795_es30
+ },
+ { .soc_id = "r8a7795",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+ },
+ { .soc_id = "r8a7795",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+ },
+ { .soc_id = "r8a7795",
+ .revision = "ES2.0",
+ .data = _quirks_4tap
+ },
+ { .soc_id = "r8a7795",
+ .revision = "ES3.0",
+ .data = _quirks_r8a7795_es30
+ },
{ .soc_id = "r8a7796",
.revision = "ES1.0",
.data = _quirks_4tap_nohs400_b17_dtrend
@@ -971,7 +1001,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat
*plat,
if (quirks == _quirks_r8a7796_es12 ||
quirks == _quirks_r8a77965)
priv->adjust_hs400_offset = 3;
- else if (quirks == _quirks_r8a7796_es13)
+ else if (quirks == _quirks_r8a7796_es13 ||
+quirks == _quirks_r8a7795_es30)
priv->adjust_hs400_offset = 0;
}
}
--
2.17.1
[PATCH v9 3/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N
Add SDHI quirks for R-Car M3-N and RZ/G2N SoC.
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
Reviewed-by: Jaehoon chung
---
v9:
* No Change
v7->v8:
* Added Jaehoon chung's Rb tag
v6->v7:
* No Change. rebased on u-boot-sh/next
v6:
* New patch
---
drivers/mmc/renesas-sdhi.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index d17134d27b..055fdbbc99 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -890,6 +890,11 @@ static const struct renesas_sdhi_quirks
sdhi_quirks_r8a7796_es13 = {
.hs400_calib_table = r8a7796_rev3_calib_table,
};
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
+ .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+ .hs400_calib_table = r8a77965_calib_table,
+};
+
/*
* Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
* So, we want to treat them equally and only have a match for ES1.2 to enforce
@@ -912,6 +917,9 @@ static const struct soc_attr sdhi_quirks_match[] = {
.revision = "ES1.3",
.data = _quirks_r8a7796_es13
},
+ { .soc_id = "r8a774b1",
+ .data = _quirks_r8a77965
+ },
{ .soc_id = "r8a7796",
.revision = "ES1.0",
.data = _quirks_4tap_nohs400_b17_dtrend
@@ -928,6 +936,9 @@ static const struct soc_attr sdhi_quirks_match[] = {
.revision = "ES1.3",
.data = _quirks_r8a7796_es13
},
+ { .soc_id = "r8a77965",
+ .data = _quirks_r8a77965
+ },
{ /* Sentinel. */ },
};
@@ -957,7 +968,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat
*plat,
priv->adjust_hs400_enable = true;
priv->adjust_hs400_calib_table =
quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
- if (quirks == _quirks_r8a7796_es12)
+ if (quirks == _quirks_r8a7796_es12 ||
+ quirks == _quirks_r8a77965)
priv->adjust_hs400_offset = 3;
else if (quirks == _quirks_r8a7796_es13)
priv->adjust_hs400_offset = 0;
--
2.17.1
[PATCH v9 2/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
Reviewed-by: Jaehoon chung
---
v9:
* No Change.
v8:
* Added Jaehoon Chung's Rb tag
v7:
* Incorporated Jaehoon Chung's review comments.
* Fixed the build error on Renesas ARM32 platforms.
v6:
* New patch. quirks using soc_device_match.
---
drivers/mmc/renesas-sdhi.c | 117 +
1 file changed, 117 insertions(+)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 24130e620b..d17134d27b 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include "tmio-common.h"
@@ -855,6 +856,115 @@ static ulong renesas_sdhi_clk_get_rate(struct
tmio_sd_priv *priv)
return clk_get_rate(>clk);
}
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+
+#define SDHI_CALIB_TABLE_MAX 32
+
+struct renesas_sdhi_quirks {
+ bool hs400_disabled;
+ bool hs400_4taps;
+ u32 hs400_bad_taps;
+ const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_b17_dtrend = {
+ .hs400_disabled = true,
+ .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
+ .hs400_disabled = true,
+ .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
+ .hs400_4taps = true,
+ .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+ .hs400_calib_table = r8a7796_rev1_calib_table,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
+ .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
+ .hs400_calib_table = r8a7796_rev3_calib_table,
+};
+
+/*
+ * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
+ * So, we want to treat them equally and only have a match for ES1.2 to enforce
+ * this if there ever will be a way to distinguish ES1.2.
+ */
+static const struct soc_attr sdhi_quirks_match[] = {
+ { .soc_id = "r8a774a1",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+ },
+ { .soc_id = "r8a774a1",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400
+ },
+ { .soc_id = "r8a774a1",
+ .revision = "ES1.2",
+ .data = _quirks_r8a7796_es12
+ },
+ { .soc_id = "r8a774a1",
+ .revision = "ES1.3",
+ .data = _quirks_r8a7796_es13
+ },
+ { .soc_id = "r8a7796",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+ },
+ { .soc_id = "r8a7796",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400
+ },
+ { .soc_id = "r8a7796",
+ .revision = "ES1.2",
+ .data = _quirks_r8a7796_es12
+ },
+ { .soc_id = "r8a7796",
+ .revision = "ES1.3",
+ .data = _quirks_r8a7796_es13
+ },
+ { /* Sentinel. */ },
+};
+
+static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
+ struct tmio_sd_priv *priv,
+ const struct renesas_sdhi_quirks *quirks)
+{
+ priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
+ priv->nrtaps = 8;
+
+ if (!quirks)
+ return;
+
+ if (quirks->hs400_disabled) {
+ plat->cfg.host_caps &= ~MMC_MODE_HS400;
+ if (quirks == _quirks_4tap_nohs400_b17_dtrend)
+ priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
+ }
+
+ if (quirks->hs400_4taps)
+ priv->nrtaps = 4;
+
+ if (quirks->hs400_bad_taps)
+ priv->hs400_bad_tap = quirks->hs400_bad_taps;
+
+ if (quirks->hs400_calib_table) {
+ priv->adjust_hs400_enable = true;
+ priv->adjust_hs400_calib_table =
+ quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
+ if (quirks == _quirks_r8a7796_es12)
+ priv->adjust_hs400_offset = 3;
+ else if (quirks == _quirks_r8a7796_es13)
+ priv->adjust_hs400_offset = 0;
+ }
+}
+#endif
+
static void renesas_sdhi_filter_caps(struct udevice *dev)
{
struct tmio_sd_priv *priv = dev_get_priv(dev);
@@ -866,6 +976,13 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
struct tmio_sd_plat *plat = dev_get_plat(dev);
+ const struct soc_attr *attr;
+
+ attr = soc_device_match(sdhi_quirks_match);
+ if (attr) {
+ renesas_sdhi_add_quirks(plat, priv, attr->data);
+ return;
+ }
/* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
if
[PATCH v9 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support
RZ/G2 SoC's are identical to R-Car Gen3 SoC's apart from some
automotive peripherals.
RZ/G2H (R8A774E1) = R-Car H3-N (R8A77951).
RZ/G2M (R8A774A1) = R-Car M3-W (R8A77960).
RZ/G2N (R8A774B1) = R-Car M3-N (R8A77965).
RZ/G2E (R8A774C0) = R-Car E3 (R8A77990).
As the devices are the same they also have the same SoC PRR
register values. SoC driver is used to distinguish the
cpu type based on the family.
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
---
v8-->v9
* Fixed make file to use default family type function for SPL builds
for both R-Car Gen{2,3} family's.
v7->v8
* Optimized the cpu detection image size, when Renesas SoC identification
driver is disabled for R-Car Gen2 SPL builds
with v8:
$ size spl/arch/arm/mach-rmobile/cpu_info.o
textdata bss dec hex filename
330 0 0 330 14a spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9176 Jan 16 18:10
spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6244 Jan 16 18:30
spl/arch/arm/mach-rmobile/cpu_info-rcar.o
$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
textdata bss dec hex filename
120 0 0 120 78
spl/arch/arm/mach-rmobile/cpu_info-rcar.o
with v7:
$ size spl/arch/arm/mach-rmobile/cpu_info.o
textdata bss dec hex filename
462 0 0 462 1ce spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9308 Jan 16 17:28
spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6864 Jan 16 18:28
spl/arch/arm/mach-rmobile/cpu_info-rcar.o
$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
textdata bss dec hex filename
154 0 0 154 9a
spl/arch/arm/mach-rmobile/cpu_info-rcar.o
v6->v7
* Seperated driver patch series from board support patches.
v5->v6
* Optimized the unique CPU identification method by using Renesas SoC
identification driver.
v4->v5
* Add support for unique identification of RZ/G2 CPU types
(Ref:
https://patchwork.ozlabs.org/project/uboot/patch/20201008085941.3600-1-biju.das...@bp.renesas.com/)
v3->v4
* Dropped CPU info reporting logic for RZ/G2. Will address this later.
* Added PRRID's for RZG2[HMNE]
(Ref:
https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-1-biju.das...@bp.renesas.com/)
v2->v3
* Reworked as per Marek's suggestion
* Added rzg2_get_cpu_type function to get cpu_type by matching TFA compatible
string
* Removed SoC family type Enum
(Ref:
https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-2-biju.das...@bp.renesas.com/)
v1->v2:
* Add comment's related to loop logic
(ref:
https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-1-biju.das...@bp.renesas.com/)
v1:
* New patch
(ref:https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-4-biju.das...@bp.renesas.com/
---
arch/arm/mach-rmobile/Makefile | 5 ++
arch/arm/mach-rmobile/cpu_info-rcar.c| 20 ++-
arch/arm/mach-rmobile/cpu_info.c | 12 +++-
arch/arm/mach-rmobile/include/mach/rmobile.h | 63 +++-
arch/arm/mach-rmobile/soc_family-info.c | 21 +++
5 files changed, 100 insertions(+), 21 deletions(-)
create mode 100644 arch/arm/mach-rmobile/soc_family-info.c
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 3206bce722..25636699f4 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -14,6 +14,11 @@ obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o
pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_RCAR_GEN2) += soc_family-info.o
+obj-$(CONFIG_RCAR_GEN3) += soc_family-info.o
+endif
+
OBJCOPYFLAGS_u-boot-spl.srec := -O srec
quiet_cmd_objcopy = OBJCOPY $@
cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \
diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c
b/arch/arm/mach-rmobile/cpu_info-rcar.c
index 5bde24ae0e..4483363f6b 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
+ * arch/arm/mach-rmobile/cpu_info-rcar.c
*
- * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ * Copyright (C) 2013-2021 Renesas Electronics Corporation
*/
#include
#include
@@ -12,6 +12,15 @@
#define R8A7796_REV_1_10x5210
#define R8A7796_REV_1_30x5211
+#if defined(CONFIG_SPL_BUILD)
+static bool __is_rzg_family(void)
+{
+ return false;
+}
+bool
[PATCH v9 0/4] Add CPU identification support for RZ/G2 SoC's
This patch series aims to add CPU identification support for RZ/G2 SoC's
and adding SDHI quirks using SoC identification driver.
This patch series depend on SoC identification driver[1]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=224764
v9:
* Fixed make file to use default family type function for SPL builds
for both R-Car Gen{2,3} family's.
v8:
* Added Jaehoon Chung's Rb tag
* Optimized the cpu detection image size, when Renesas SoC identification
driver is disabled for R-Car Gen2 SPL builds
with v8:
$ size spl/arch/arm/mach-rmobile/cpu_info.o
textdata bss dec hex filename
330 0 0 330 14a spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9176 Jan 16 18:10
spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6244 Jan 16 18:30
spl/arch/arm/mach-rmobile/cpu_info-rcar.o
$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
textdata bss dec hex filename
120 0 0 120 78
spl/arch/arm/mach-rmobile/cpu_info-rcar.o
with v7:
$ size spl/arch/arm/mach-rmobile/cpu_info.o
textdata bss dec hex filename
462 0 0 462 1ce spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9308 Jan 16 17:28
spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6864 Jan 16 18:28
spl/arch/arm/mach-rmobile/cpu_info-rcar.o
$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
textdata bss dec hex filename
154 0 0 154 9a
spl/arch/arm/mach-rmobile/cpu_info-rcar.o
v7:
* Incorporated Jaehoon Chung's review comments.
* Fixed the build error on Renesas ARM32 platforms.
* Seperated driver patch series from board support patches.
v6:
* Optimized the unique CPU identification method by using Renesas SoC
identification driver.
* quirks using soc_device_match.
Biju Das (4):
arm: rmobile: Add RZ/G2[HMNE] SoC support
mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N
mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H
arch/arm/mach-rmobile/Makefile | 5 +
arch/arm/mach-rmobile/cpu_info-rcar.c| 20 ++-
arch/arm/mach-rmobile/cpu_info.c | 12 +-
arch/arm/mach-rmobile/include/mach/rmobile.h | 63 ++--
arch/arm/mach-rmobile/soc_family-info.c | 21 +++
drivers/mmc/renesas-sdhi.c | 160 +++
6 files changed, 260 insertions(+), 21 deletions(-)
create mode 100644 arch/arm/mach-rmobile/soc_family-info.c
--
2.17.1
[PATCH v4 2/2] riscv: timer: Add support for an early timer
Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.
Signed-off-by: Pragnesh Patel
Reviewed-by: Rick Chen
---
Changes in v4:
- Rebase on master
Changes in v3:
- Add IS_ENABLED(CONFIG_TIMER_EARLY) for timer_early_get_rate()
and timer_early_get_count() functions.
Changes in v2:
- make u-boot compile for qemu (include/configs/qemu-riscv.h)
drivers/timer/andes_plmt_timer.c | 21 -
drivers/timer/riscv_timer.c| 21 -
drivers/timer/sifive_clint_timer.c | 21 -
include/configs/ax25-ae350.h | 5 +
include/configs/qemu-riscv.h | 5 +
include/configs/sifive-fu540.h | 5 +
6 files changed, 75 insertions(+), 3 deletions(-)
diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
index db2cf86f63..a3797b22c7 100644
--- a/drivers/timer/andes_plmt_timer.c
+++ b/drivers/timer/andes_plmt_timer.c
@@ -18,11 +18,30 @@
/* mtime register */
#define MTIME_REG(base)((ulong)(base))
-static u64 andes_plmt_get_count(struct udevice *dev)
+static u64 notrace andes_plmt_get_count(struct udevice *dev)
{
return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
}
+#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+ return RISCV_MMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+ return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
+}
+#endif
+
static const struct timer_ops andes_plmt_ops = {
.get_count = andes_plmt_get_count,
};
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 21ae184057..3627ed79b8 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -16,7 +16,7 @@
#include
#include
-static u64 riscv_timer_get_count(struct udevice *dev)
+static u64 notrace riscv_timer_get_count(struct udevice *dev)
{
__maybe_unused u32 hi, lo;
@@ -31,6 +31,25 @@ static u64 riscv_timer_get_count(struct udevice *dev)
return ((u64)hi << 32) | lo;
}
+#if CONFIG_IS_ENABLED(RISCV_SMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+ return RISCV_SMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+ return riscv_timer_get_count(NULL);
+}
+#endif
+
static int riscv_timer_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
diff --git a/drivers/timer/sifive_clint_timer.c
b/drivers/timer/sifive_clint_timer.c
index de23b85404..de7b4b95c9 100644
--- a/drivers/timer/sifive_clint_timer.c
+++ b/drivers/timer/sifive_clint_timer.c
@@ -15,11 +15,30 @@
/* mtime register */
#define MTIME_REG(base)((ulong)(base) + 0xbff8)
-static u64 sifive_clint_get_count(struct udevice *dev)
+static u64 notrace sifive_clint_get_count(struct udevice *dev)
{
return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
}
+#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+ return RISCV_MMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+ return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
+}
+#endif
+
static const struct timer_ops sifive_clint_ops = {
.get_count = sifive_clint_get_count,
};
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index b2606e794d..bd9c371f83 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h
@@ -17,6 +17,11 @@
#endif
#endif
+#define RISCV_MMODE_TIMERBASE 0xe600
+#define RISCV_MMODE_TIMER_FREQ 6000
+
+#define RISCV_SMODE_TIMER_FREQ 6000
+
/*
* CPU and Board Configuration Options
*/
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index a2f33587c2..5291de83f8 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -29,6 +29,11 @@
#define CONFIG_STANDALONE_LOAD_ADDR0x8020
+#define RISCV_MMODE_TIMERBASE 0x200
+#define RISCV_MMODE_TIMER_FREQ 100
+
+#define RISCV_SMODE_TIMER_FREQ 100
+
/* Environment options */
#ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index c1c79db147..0d69d1c548 100644
--- a/include/configs/sifive-fu540.h
+++
[PATCH v4 1/2] trace: select TIMER_EARLY to avoid infinite recursion
When tracing functions is enabled this adds calls to __cyg_profile_func_enter() and __cyg_profile_func_exit() to the traced functions. __cyg_profile_func_enter() and __cyg_profile_func_exit() invoke timer_get_us() to record the entry and exit time. initr_dm() will make gd->dm_root = NULL and gd->timer = NULL, so timer_get_us() -> get_ticks() -> dm_timer_init() will lead to an indefinite recursion. So select TIMER_EARLY when tracing got enabled. Signed-off-by: Pragnesh Patel Reviewed-by: Simon Glass Reviewed-by: Rick Chen --- Changes in v4: - no change Changes in v3: - no change Changes in v2: - new patch lib/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/Kconfig b/lib/Kconfig index a704568443..9b9177f2aa 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -210,6 +210,7 @@ config BITREVERSE config TRACE bool "Support for tracing of function calls and timing" imply CMD_TRACE + select TIMER_EARLY help Enables function tracing within U-Boot. This allows recording of call traces including timing information. The command can write data to -- 2.17.1
Re: [PATCH v3 2/2] riscv: timer: Add support for an early timer
Hi Rick On Tue, Jan 12, 2021 at 7:30 AM Rick Chen wrote: > > Hi Pragnesh > > > > From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com] > > > Sent: Sunday, January 10, 2021 8:43 PM > > > To: u-boot@lists.denx.de > > > Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com; > > > paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com; > > > Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; Palmer Dabbelt; Sean Anderson; > > > Simon Glass > > > Subject: [PATCH v3 2/2] riscv: timer: Add support for an early timer > > > > > > Added support for timer_early_get_count() and timer_early_get_rate() > > > This is mostly useful in tracing. > > > > > > Signed-off-by: Pragnesh Patel > > > --- > > > > > > Changes in v3: > > > - Add IS_ENABLED(CONFIG_TIMER_EARLY) for timer_early_get_rate() > > > and timer_early_get_count() functions. > > > > Reviewed-by: Rick Chen > > I am trying to merge to mainline, but it conflict with master. > Please rebase again, > > Applying: trace: select TIMER_EARLY to avoid infinite recursion > Applying: riscv: timer: Add support for an early timer > error: patch failed: drivers/timer/andes_plmt_timer.c:17 > error: drivers/timer/andes_plmt_timer.c: patch does not apply > error: patch failed: drivers/timer/sifive_clint_timer.c:14 > error: drivers/timer/sifive_clint_timer.c: patch does not apply > Patch failed at 0002 riscv: timer: Add support for an early timer > The copy of the patch that failed is found in: .git/rebase-apply/patch > When you have resolved this problem, run "git am --continue". > If you prefer to skip this patch, run "git am --skip" instead. > To restore the original branch and stop patching, run "git am --abort". Will rebase and send again. > > Thanks, > Rick
Re: [PATCH v4] cmd: Add a pwm command
On 12/22/20 7:00 AM, Pragnesh Patel wrote:
Add the command "pwm" for controlling the pwm channels. This
command provides pwm invert/config/enable/disable functionalities
via PWM uclass drivers
Signed-off-by: Pragnesh Patel
Reviewed-by: Simon Glass
Dear Pragnesh,
Users should be pointed to the existence of the command.
Could you, please, provide a further patch to add a documentation of the
pwm command under /doc/usage/. You can use /doc/usage/button.rst as
template.
Best regards
Heinrich
---
Changes in v4:
- Add ut_assertok() for every run_command()
Changes in v3:
- Replace goto with return
- Print return value for error
- Change the assert condition for success
Changes in v2:
- Add test for pwm command
README| 1 +
cmd/Kconfig | 6 ++
cmd/Makefile | 1 +
cmd/pwm.c | 117 ++
configs/sandbox_defconfig | 1 +
test/cmd/Makefile | 1 +
test/cmd/pwm.c| 47 +++
7 files changed, 174 insertions(+)
create mode 100644 cmd/pwm.c
create mode 100644 test/cmd/pwm.c
diff --git a/README b/README
index cb49aa15da..dab291e0d0 100644
--- a/README
+++ b/README
@@ -3160,6 +3160,7 @@ i2c - I2C sub-system
sspi - SPI utility commands
base - print or set address offset
printenv- print environment variables
+pwm- control pwm channels
setenv- set environment variables
saveenv - save environment variables to persistent storage
protect - enable or disable FLASH write protection
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 1595de999b..0d085108f4 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -918,6 +918,12 @@ config CMD_GPIO
help
GPIO support.
+config CMD_PWM
+ bool "pwm"
+ depends on DM_PWM
+ help
+ Control PWM channels, this allows invert/config/enable/disable PWM
channels.
+
config CMD_GPT
bool "GPT (GUID Partition Table) command"
select EFI_PARTITION
diff --git a/cmd/Makefile b/cmd/Makefile
index dd86675bf2..75df3c136c 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -120,6 +120,7 @@ endif
obj-$(CONFIG_CMD_PINMUX) += pinmux.o
obj-$(CONFIG_CMD_PMC) += pmc.o
obj-$(CONFIG_CMD_PSTORE) += pstore.o
+obj-$(CONFIG_CMD_PWM) += pwm.o
obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
obj-$(CONFIG_CMD_WOL) += wol.o
obj-$(CONFIG_CMD_QFW) += qfw.o
diff --git a/cmd/pwm.c b/cmd/pwm.c
new file mode 100644
index 00..5849fc57b6
--- /dev/null
+++ b/cmd/pwm.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Control PWM channels
+ *
+ * Copyright (c) 2020 SiFive, Inc
+ * author: Pragnesh Patel
+ */
+
+#include
+#include
+#include
+
+enum pwm_cmd {
+ PWM_SET_INVERT,
+ PWM_SET_CONFIG,
+ PWM_SET_ENABLE,
+ PWM_SET_DISABLE,
+};
+
+static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
+ const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
+ enum pwm_cmd sub_cmd;
+ struct udevice *dev;
+ u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0;
+ int ret;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ str_cmd = argv[1];
+ argc -= 2;
+ argv += 2;
+
+ if (argc > 0) {
+ str_pwm = *argv;
+ argc--;
+ argv++;
+ }
+
+ if (!str_pwm)
+ return CMD_RET_USAGE;
+
+ switch (*str_cmd) {
+ case 'i':
+ sub_cmd = PWM_SET_INVERT;
+ break;
+ case 'c':
+ sub_cmd = PWM_SET_CONFIG;
+ break;
+ case 'e':
+ sub_cmd = PWM_SET_ENABLE;
+ break;
+ case 'd':
+ sub_cmd = PWM_SET_DISABLE;
+ break;
+ default:
+ return CMD_RET_USAGE;
+ }
+
+ pwm_dev = simple_strtoul(str_pwm, NULL, 10);
+ ret = uclass_get_device(UCLASS_PWM, pwm_dev, );
+ if (ret) {
+ printf("pwm: '%s' not found\n", str_pwm);
+ return cmd_process_error(cmdtp, ret);
+ }
+
+ if (argc > 0) {
+ str_channel = *argv;
+ channel = simple_strtoul(str_channel, NULL, 10);
+ argc--;
+ argv++;
+ } else {
+ return CMD_RET_USAGE;
+ }
+
+ if (sub_cmd == PWM_SET_INVERT && argc > 0) {
+ str_enable = *argv;
+ pwm_enable = simple_strtoul(str_enable, NULL, 10);
+ ret = pwm_set_invert(dev, channel, pwm_enable);
+ } else if (sub_cmd == PWM_SET_CONFIG && argc == 2) {
+ str_period = *argv;
+ argc--;
+ argv++;
+ period_ns = simple_strtoul(str_period, NULL, 10);
+
+ if (argc > 0) {
+ str_duty = *argv;
+
[PATCH v2] mmc: mmc_spi: Print verbose debug output when crc16 check fails
Add some verbose debug output when crc16 check fails.
Signed-off-by: Bin Meng
Reviewed-by: Jaehoon Chung
---
Changes in v2:
- do the crc_ok assignment at the the same line where it's defined
drivers/mmc/mmc_spi.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c
index 46800bbed2..b1edb6ad7c 100644
--- a/drivers/mmc/mmc_spi.c
+++ b/drivers/mmc/mmc_spi.c
@@ -181,8 +181,10 @@ static int mmc_spi_readdata(struct udevice *dev,
if (ret)
return ret;
#ifdef CONFIG_MMC_SPI_CRC_ON
- if (be16_to_cpu(crc16_ccitt(0, buf, bsize)) != crc) {
- debug("%s: data crc error\n", __func__);
+ u16 crc_ok = be16_to_cpu(crc16_ccitt(0, buf, bsize));
+ if (crc_ok != crc) {
+ debug("%s: data crc error, expect %04x get
%04x\n",
+ __func__, crc_ok, crc);
r1 = R1_SPI_COM_CRC;
break;
}
--
2.25.1
Re: [PATCH v4] cmd: Add a pwm command
Hi Tom,
Any comment on this ?
On Tue, Dec 22, 2020 at 11:30 AM Pragnesh Patel
wrote:
>
> Add the command "pwm" for controlling the pwm channels. This
> command provides pwm invert/config/enable/disable functionalities
> via PWM uclass drivers
>
> Signed-off-by: Pragnesh Patel
> Reviewed-by: Simon Glass
> ---
>
> Changes in v4:
> - Add ut_assertok() for every run_command()
>
> Changes in v3:
> - Replace goto with return
> - Print return value for error
> - Change the assert condition for success
>
> Changes in v2:
> - Add test for pwm command
>
> README| 1 +
> cmd/Kconfig | 6 ++
> cmd/Makefile | 1 +
> cmd/pwm.c | 117 ++
> configs/sandbox_defconfig | 1 +
> test/cmd/Makefile | 1 +
> test/cmd/pwm.c| 47 +++
> 7 files changed, 174 insertions(+)
> create mode 100644 cmd/pwm.c
> create mode 100644 test/cmd/pwm.c
>
> diff --git a/README b/README
> index cb49aa15da..dab291e0d0 100644
> --- a/README
> +++ b/README
> @@ -3160,6 +3160,7 @@ i2c - I2C sub-system
> sspi - SPI utility commands
> base - print or set address offset
> printenv- print environment variables
> +pwm- control pwm channels
> setenv - set environment variables
> saveenv - save environment variables to persistent storage
> protect - enable or disable FLASH write protection
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index 1595de999b..0d085108f4 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -918,6 +918,12 @@ config CMD_GPIO
> help
> GPIO support.
>
> +config CMD_PWM
> + bool "pwm"
> + depends on DM_PWM
> + help
> + Control PWM channels, this allows invert/config/enable/disable PWM
> channels.
> +
> config CMD_GPT
> bool "GPT (GUID Partition Table) command"
> select EFI_PARTITION
> diff --git a/cmd/Makefile b/cmd/Makefile
> index dd86675bf2..75df3c136c 100644
> --- a/cmd/Makefile
> +++ b/cmd/Makefile
> @@ -120,6 +120,7 @@ endif
> obj-$(CONFIG_CMD_PINMUX) += pinmux.o
> obj-$(CONFIG_CMD_PMC) += pmc.o
> obj-$(CONFIG_CMD_PSTORE) += pstore.o
> +obj-$(CONFIG_CMD_PWM) += pwm.o
> obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
> obj-$(CONFIG_CMD_WOL) += wol.o
> obj-$(CONFIG_CMD_QFW) += qfw.o
> diff --git a/cmd/pwm.c b/cmd/pwm.c
> new file mode 100644
> index 00..5849fc57b6
> --- /dev/null
> +++ b/cmd/pwm.c
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Control PWM channels
> + *
> + * Copyright (c) 2020 SiFive, Inc
> + * author: Pragnesh Patel
> + */
> +
> +#include
> +#include
> +#include
> +
> +enum pwm_cmd {
> + PWM_SET_INVERT,
> + PWM_SET_CONFIG,
> + PWM_SET_ENABLE,
> + PWM_SET_DISABLE,
> +};
> +
> +static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
> + char *const argv[])
> +{
> + const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
> + const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
> + enum pwm_cmd sub_cmd;
> + struct udevice *dev;
> + u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0;
> + int ret;
> +
> + if (argc < 4)
> + return CMD_RET_USAGE;
> +
> + str_cmd = argv[1];
> + argc -= 2;
> + argv += 2;
> +
> + if (argc > 0) {
> + str_pwm = *argv;
> + argc--;
> + argv++;
> + }
> +
> + if (!str_pwm)
> + return CMD_RET_USAGE;
> +
> + switch (*str_cmd) {
> + case 'i':
> + sub_cmd = PWM_SET_INVERT;
> + break;
> + case 'c':
> + sub_cmd = PWM_SET_CONFIG;
> + break;
> + case 'e':
> + sub_cmd = PWM_SET_ENABLE;
> + break;
> + case 'd':
> + sub_cmd = PWM_SET_DISABLE;
> + break;
> + default:
> + return CMD_RET_USAGE;
> + }
> +
> + pwm_dev = simple_strtoul(str_pwm, NULL, 10);
> + ret = uclass_get_device(UCLASS_PWM, pwm_dev, );
> + if (ret) {
> + printf("pwm: '%s' not found\n", str_pwm);
> + return cmd_process_error(cmdtp, ret);
> + }
> +
> + if (argc > 0) {
> + str_channel = *argv;
> + channel = simple_strtoul(str_channel, NULL, 10);
> + argc--;
> + argv++;
> + } else {
> + return CMD_RET_USAGE;
> + }
> +
> + if (sub_cmd == PWM_SET_INVERT && argc > 0) {
> + str_enable = *argv;
> + pwm_enable = simple_strtoul(str_enable, NULL, 10);
> + ret = pwm_set_invert(dev, channel, pwm_enable);
> + } else if (sub_cmd == PWM_SET_CONFIG && argc == 2) {
> + str_period = *argv;
> + argc--;
> + argv++;
> + period_ns = simple_strtoul(str_period, NULL, 10);
> +
> +
Re: [PATCH 08/10] am335x, guardian: Update pinmux configuration
On 06/01/21 9:01 pm, gireesh.hirem...@in.bosch.com wrote:
> From: Moses Christopher
>
> pinmux update for guardian board
Please specify what this pinmux update is about.
Thanks and regards,
Lokesh
>
> Signed-off-by: Moses Christopher
> ---
> arch/arm/dts/am335x-guardian.dts | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/dts/am335x-guardian.dts
> b/arch/arm/dts/am335x-guardian.dts
> index 93ee2e6c09..69bee45848 100644
> --- a/arch/arm/dts/am335x-guardian.dts
> +++ b/arch/arm/dts/am335x-guardian.dts
> @@ -407,12 +407,12 @@
>
> guardian_interface_pins: pinmux_guardian_interface_pins {
> pinctrl-single,pins = <
> - AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7)
> - AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7)
> + AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7)
> AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
> + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
> AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7)
> AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7)
> - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP | MUX_MODE7)
> + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7)
> AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
> AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
> AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7)
>
Re: [PATCH 02/10] am335x, guardian: Enable splash screen
On 06/01/21 9:01 pm, gireesh.hirem...@in.bosch.com wrote:
> From: Gireesh Hiremath
>
> - Display splash screen
> - Print "U-Boot" on display when bmp fails to load due to any reason
>
> Signed-off-by: Gireesh Hiremath > ---
> board/bosch/guardian/board.c | 77 ++-
> configs/am335x_guardian_defconfig | 5 +-
Can you split board changes and defconfig changes into separate patches? This
applies to other patches in rest of the series.
Thanks and regards,
Lokesh
> include/configs/am335x_guardian.h | 11 +
> 3 files changed, 91 insertions(+), 2 deletions(-)
>
> diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
> index a34262bd13..394c56d72e 100644
> --- a/board/bosch/guardian/board.c
> +++ b/board/bosch/guardian/board.c
> @@ -29,12 +29,16 @@
> #include
> #include
> #include
> -#include
> #include
> #include
> #include
> #include
> #include
> +#include
> +#include
> +#include
> +#include
> +#include
> #include "board.h"
>
> DECLARE_GLOBAL_DATA_PTR;
> @@ -270,6 +274,74 @@ void lcdbacklight_en(void)
> brightness != 0 ? 0x0A : 0x02, 0xFF);
> }
>
> +#if IS_ENABLED(CONFIG_AM335X_LCD)
> +static void splash_screen(void)
> +{
> + struct udevice *video_dev;
> + struct udevice *console_dev;
> + struct video_priv *vid_priv;
> + struct mtd_info *mtd;
> + size_t len;
> + int ret;
> +
> + struct mtd_device *mtd_dev;
> + struct part_info *part;
> + u8 pnum;
> +
> + ret = uclass_get_device(UCLASS_VIDEO, 0, _dev);
> + if (ret != 0) {
> + debug("video device not found\n");
> + goto exit;
> + }
> +
> + vid_priv = dev_get_uclass_priv(video_dev);
> + mtdparts_init();
> +
> + if (find_dev_and_part(SPLASH_SCREEN_NAND_PART, _dev, , ))
> {
> + debug("Could not find nand partition\n");
> + goto splash_screen_text;
> + }
> +
> + mtd = get_nand_dev_by_index(mtd_dev->id->num);
> + if (!mtd) {
> + debug("MTD partition is not valid\n");
> + goto splash_screen_text;
> + }
> +
> + len = SPLASH_SCREEN_BMP_FILE_SIZE;
> + ret = nand_read_skip_bad(mtd, part->offset, , NULL,
> + SPLASH_SCREEN_BMP_FILE_SIZE,
> + (u_char *)SPLASH_SCREEN_BMP_LOAD_ADDR);
> + if (ret != 0) {
> + debug("Reading NAND partition failed\n");
> + goto splash_screen_text;
> + }
> +
> + ret = video_bmp_display(video_dev, SPLASH_SCREEN_BMP_LOAD_ADDR, 0, 0,
> false);
> + if (ret != 0) {
> + debug("No valid bmp image found!!\n");
> + goto splash_screen_text;
> + } else {
> + goto exit;
> + }
> +
> +splash_screen_text:
> + vid_priv->colour_fg = CONSOLE_COLOR_RED;
> + vid_priv->colour_bg = CONSOLE_COLOR_BLACK;
> +
> + if (!uclass_first_device_err(UCLASS_VIDEO_CONSOLE, _dev)) {
> + debug("Found console\n");
> + vidconsole_position_cursor(console_dev, 17, 7);
> + vidconsole_put_string(console_dev, SPLASH_SCREEN_TEXT);
> + } else {
> + debug("No console device found\n");
> + }
> +
> +exit:
> + return;
> +}
> +#endif /* CONFIG_AM335X_LCD */
> +
> int board_late_init(void)
> {
> int ret;
> @@ -287,6 +359,9 @@ int board_late_init(void)
> }
>
> lcdbacklight_en();
> +#if IS_ENABLED(CONFIG_AM335X_LCD)
> + splash_screen();
> +#endif
> return 0;
> }
> #endif /* CONFIG_BOARD_LATE_INIT */
> diff --git a/configs/am335x_guardian_defconfig
> b/configs/am335x_guardian_defconfig
> index b7170cd79e..48b9bf45a4 100644
> --- a/configs/am335x_guardian_defconfig
> +++ b/configs/am335x_guardian_defconfig
> @@ -1,7 +1,7 @@
> CONFIG_ARM=y
> CONFIG_ARCH_CPU_INIT=y
> CONFIG_ARCH_OMAP2PLUS=y
> -CONFIG_SPL_GPIO_SUPPORT=y
> +# CONFIG_SPL_GPIO_SUPPORT is not set
> CONFIG_SPL_LIBCOMMON_SUPPORT=y
> CONFIG_SPL_LIBGENERIC_SUPPORT=y
> CONFIG_ENV_SIZE=0x4
> @@ -50,6 +50,7 @@ CONFIG_CMD_MTD=y
> CONFIG_CMD_NAND=y
> CONFIG_CMD_USB=y
> # CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_BMP=y
> CONFIG_CMD_EXT4_WRITE=y
> CONFIG_CMD_MTDPARTS=y
>
> CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(SPL),256k(SPL.backup1),256k(SPL.backup2),256k(SPL.backup3),1m(u-boot),1m(u-boot.backup1),1m(u-boot-2),1m(u-boot-2.backup1),256k(u-boot-env),256k(u-boot-env.backup1),256k(splash-screen),-(UBI)"
> @@ -100,6 +101,8 @@ CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
> CONFIG_USB_GADGET_VENDOR_NUM=0x0451
> CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
> CONFIG_USB_ETHER=y
> +CONFIG_VIDEO_BPP16=y
> +CONFIG_SYS_WHITE_ON_BLACK=y
> CONFIG_AM335X_LCD=y
> CONFIG_SPL_WDT=y
> # CONFIG_SPL_USE_TINY_PRINTF is not set
> diff --git a/include/configs/am335x_guardian.h
> b/include/configs/am335x_guardian.h
> index 236be1a093..1a14b4249d 100644
> --- a/include/configs/am335x_guardian.h
> +++
Re: [PATCH 2/2] am335x, guardian: Enable panel driver Himax HX8238D
On 06/01/21 9:01 pm, gireesh.hirem...@in.bosch.com wrote:
> From: Gireesh Hiremath
>
> Enable lcd controller related clocks, pinmux, config,
> interface and port
>
> Signed-off-by: Gireesh Hiremath
> ---
> arch/arm/dts/am335x-guardian-u-boot.dtsi | 15 +++
> arch/arm/dts/am335x-guardian.dts | 8 +++-
> arch/arm/mach-omap2/am33xx/Kconfig | 2 ++
> board/bosch/guardian/board.c | 22 ++
> board/bosch/guardian/mux.c | 3 ++-
> configs/am335x_guardian_defconfig| 7 +--
> drivers/video/Makefile | 1 +
> 7 files changed, 54 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/dts/am335x-guardian-u-boot.dtsi
> b/arch/arm/dts/am335x-guardian-u-boot.dtsi
> index 705ef335bf..2c355e583c 100644
> --- a/arch/arm/dts/am335x-guardian-u-boot.dtsi
> +++ b/arch/arm/dts/am335x-guardian-u-boot.dtsi
> @@ -18,6 +18,10 @@
> u-boot,dm-pre-reloc;
> };
>
> + {
> + u-boot,dm-pre-reloc;
> +};
> +
> {
> u-boot,dm-pre-reloc;
> };
> @@ -35,6 +39,17 @@
> u-boot,dm-pre-reloc;
> };
>
> + {
> + lcd0: display@0 {
> + compatible = "himax,hx8238d";
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> + reg = <0>;
> + label = "lcd";
> + spi-max-frequency = <10>;
> + };
> +};
> +
> {
> u-boot,dm-pre-reloc;
> };
> diff --git a/arch/arm/dts/am335x-guardian.dts
> b/arch/arm/dts/am335x-guardian.dts
> index 7e70a96d25..93ee2e6c09 100644
> --- a/arch/arm/dts/am335x-guardian.dts
> +++ b/arch/arm/dts/am335x-guardian.dts
> @@ -87,7 +87,7 @@
> ac-bias = <255>;
> ac-bias-intrpt= <0>;
> dma-burst-sz = <16>;
> - bpp = <24>;
> + bpp = <16>;
> bus-width = <16>;
> fdd = <0x80>;
> sync-edge = <0>;
> @@ -247,6 +247,12 @@
> {
> blue-and-red-wiring = "crossed";
> status = "okay";
> +
> + port {
> + lcdc_0: endpoint@0 {
> + remote-endpoint = <0>;
> + };
> + };
> };
>
> {
> diff --git a/arch/arm/mach-omap2/am33xx/Kconfig
> b/arch/arm/mach-omap2/am33xx/Kconfig
> index 9a98e8a0a9..204975092a 100644
> --- a/arch/arm/mach-omap2/am33xx/Kconfig
> +++ b/arch/arm/mach-omap2/am33xx/Kconfig
> @@ -94,6 +94,8 @@ config TARGET_AM335X_GUARDIAN
> select DM_SERIAL
> select DM_GPIO
> select DM_USB
> + select DM_VIDEO
> + select DM_PANEL_HX8238D
>
> config TARGET_AM335X_SL50
> bool "Support am335x_sl50"
> diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
> index 8b3c82cafd..f3e616d21c 100644
> --- a/board/bosch/guardian/board.c
> +++ b/board/bosch/guardian/board.c
> @@ -79,6 +79,18 @@ void am33xx_spl_board_init(void)
> int mpu_vdd;
> int usb_cur_lim;
>
> + struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
> +
> + /*enable lcd controller related clocks*/
> + u32 *const clk_domains[] = { 0 };
> +
> + u32 *const clk_modules_xre1specific[] = {
> + >lcdclkctrl,
> + >lcdcclkstctrl,
> + 0
> + };
> + do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
I am worried this is going to effect other platforms. Recently CLK support is
introduced for am33 platforms. Can you use that and get clocks info from DT.
Thanks and regards,
Lokesh
> +
> /* Get the frequency */
> dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
>
> @@ -235,10 +247,20 @@ err:
>
> int board_late_init(void)
> {
> + int ret;
> + struct udevice *cdev;
> +
> #ifdef CONFIG_LED_GPIO
> led_default_state();
> #endif
> set_bootmode_env();
> +
> + ret = uclass_get_device(UCLASS_PANEL, 0, );
> + if (ret) {
> + debug("video panel not found: %d\n", ret);
> + return ret;
> + }
> +
> return 0;
> }
> #endif /* CONFIG_BOARD_LATE_INIT */
> diff --git a/board/bosch/guardian/mux.c b/board/bosch/guardian/mux.c
> index 9c81f29f9f..12c3eb666f 100644
> --- a/board/bosch/guardian/mux.c
> +++ b/board/bosch/guardian/mux.c
> @@ -28,8 +28,9 @@ static struct module_pin_mux i2c0_pin_mux[] = {
>
> static struct module_pin_mux guardian_interfaces_pin_mux[] = {
> {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLDOWN_EN)},
> + {OFFSET(mii1_txen), (MODE(7) | PULLDOWN_EN)},
> {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUP_EN)},
> - {OFFSET(mii1_txd0), (MODE(7) | PULLUP_EN)},
> + {OFFSET(mdio_clk), (MODE(7) | PULLUP_EN)},
> {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
> {OFFSET(uart1_txd), (MODE(7) | PULLUDDIS)},
> {OFFSET(mii1_crs), (MODE(7) | PULLDOWN_EN)},
> diff --git
Re: [PATCH] am335x, guardian: mem: Add board dependent mem values
On 06/01/21 9:01 pm, gireesh.hirem...@in.bosch.com wrote: > From: Moses Christopher > > - Add mem-guardian.h derived from am33xx/mem.h > > * Add GPMC config values optimized for Bosch Guardian Board > * NAND Chip used by Bosch Guardian Board is Micron MT29F4G08ABBFA > > Signed-off-by: Moses Christopher Just wondering, Isn't NAND framework moved to Driver model and Device-tree model? In that case, these values should be obtained from DT. Thanks and regards, Lokesh > --- > .../include/asm/arch-am33xx/mem-guardian.h| 63 +++ > arch/arm/mach-omap2/am33xx/board.c| 4 ++ > arch/arm/mach-omap2/mem-common.c | 4 ++ > board/bosch/guardian/board.c | 2 +- > 4 files changed, 72 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/include/asm/arch-am33xx/mem-guardian.h > > diff --git a/arch/arm/include/asm/arch-am33xx/mem-guardian.h > b/arch/arm/include/asm/arch-am33xx/mem-guardian.h > new file mode 100644 > index 00..e864a0fd36 > --- /dev/null > +++ b/arch/arm/include/asm/arch-am33xx/mem-guardian.h > @@ -0,0 +1,63 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * (C) Copyright 2006-2008 > + * Texas Instruments, > + * > + * (C) Copyright 2020 > + * Robert Bosch Power Tools GmbH > + * > + * Author > + * Moses Christopher > + * > + * Copied from: > + * arch/arm/include/asm/arch-am33xx/mem.h > + * > + * Initial Code from: > + * Mansoor Ahamed > + * Richard Woodruff > + */ > + > +#ifndef _MEM_GUARDIAN_H_ > +#define _MEM_GUARDIAN_H_ > + > +/* > + * GPMC settings - > + * Definitions is as per the following format > + * #define _GPMC_CONFIG > + * Where: > + * PART is the part name e.g. M_NAND - Micron Nand Flash > + * x is GPMC config registers from 1 to 7 (there will be 7 macros) > + * Value is corresponding value > + * > + * For every valid PRCM configuration there should be only one definition of > + * the same. > + * > + * The following values are optimized for improving the NAND Read speed > + * They are applicable and tested for Bosch Guardian Board. > + * Read Speeds rose from 1.5MiBs to over 7.6MiBs > + * > + * Currently valid part Names are (PART): > + * M_NAND - Micron NAND > + */ > +#define GPMC_SIZE_256M 0x0 > +#define GPMC_SIZE_128M 0x8 > +#define GPMC_SIZE_64M0xC > +#define GPMC_SIZE_32M0xE > +#define GPMC_SIZE_16M0xF > + > +#define M_NAND_GPMC_CONFIG1 0x0800 > +#define M_NAND_GPMC_CONFIG2 0x00030300 > +#define M_NAND_GPMC_CONFIG3 0x00030300 > +#define M_NAND_GPMC_CONFIG4 0x02000201 > +#define M_NAND_GPMC_CONFIG5 0x00030303 > +#define M_NAND_GPMC_CONFIG6 0x00C0 > +#define M_NAND_GPMC_CONFIG7 0x0008 > + > +/* max number of GPMC Chip Selects */ > +#define GPMC_MAX_CS 8 > +/* max number of GPMC regs */ > +#define GPMC_MAX_REG 7 > + > +#define DBG_MPDB 6 > + > +#endif /* endif _MEM_GUARDIAN_H_ */ > diff --git a/arch/arm/mach-omap2/am33xx/board.c > b/arch/arm/mach-omap2/am33xx/board.c > index 2888390d24..a87ecaf12a 100644 > --- a/arch/arm/mach-omap2/am33xx/board.c > +++ b/arch/arm/mach-omap2/am33xx/board.c > @@ -23,7 +23,11 @@ > #include > #include > #include > +#if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN) > +#include > +#else > #include > +#endif > #include > #include > #include > diff --git a/arch/arm/mach-omap2/mem-common.c > b/arch/arm/mach-omap2/mem-common.c > index 50d5f3e9eb..2dcf0cf9c3 100644 > --- a/arch/arm/mach-omap2/mem-common.c > +++ b/arch/arm/mach-omap2/mem-common.c > @@ -15,7 +15,11 @@ > #include > #include > #include > +#if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN) > +#include > +#else > #include > +#endif > #include > #include > #include > diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c > index 1d8fa78154..8b3c82cafd 100644 > --- a/board/bosch/guardian/board.c > +++ b/board/bosch/guardian/board.c > @@ -28,7 +28,7 @@ > #include > #include > #include > -#include > +#include > #include > #include > #include >
Re: [PATCH] Include support for dev_xxx macros
Hi, On 06/01/21 9:00 pm, gireesh.hirem...@in.bosch.com wrote: > From: Gireesh Hiremath > > Now that linux/compat.h does not define dev_xxx macros, we need > to include dm/device_compat.h to use dev_xxx macros > > Signed-off-by: Gireesh Hiremath I did not get the complete intention of this patch. Are there any build warnings that are fixed with including the relevant #include. If not this patch should be squashed with the patch that introduces the usage of dev_xxx macros. Thanks and regards, Lokesh > --- > drivers/video/am335x-fb.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c > index f4ccdc3b05..e802b3bb83 100644 > --- a/drivers/video/am335x-fb.c > +++ b/drivers/video/am335x-fb.c > @@ -13,6 +13,7 @@ > */ > #include > #include > +#include > #include > #include > #include >
Re: [PATCH 00/13] Nokia RX-51: Fix USB TTY console and enable it
Hi Lukasz, On 29/11/20 10:16 pm, Pali Rohár wrote: > This patch series fix usbtty code (serial console via USB peripheral > mode), fix underlying musb peripheral code, fix compilation of > CONFIG_USB_DEVICE (used by usbtty), remove unused Nokia RX-51 code to > decrease size of U-Boot binary and finally enable usbtty serial console > for Nokia RX-51. > > With this patch series debugging of Nokia RX-51 can be done also via USB > serial console. > > On computer this serial console is accessible via /dev/ttyACM0 device. > > With current implementation there is an issue in musb driver that it > loose receiving bytes from USB bus when too many a characters are send > over USB tty from computer. Typing on keyboard to kermit terminal > connected to /dev/ttyACM0 is working fine. But pasting more more bytes > to terminal cause data lost on receiving side. I do not know where is > the issue or how to fix it (it looks like that data are lost at low > level when reading them from msub FIFO hardware) but typing on keyboard > is working fine. This is rather issue for sending files via x/y/z-modem > or kermit protocol. Currently U-Boot is not able to receive any file > via usbtty with musb driver due to this issue. Can you take a look at usb related patches and merge them if you are okay with it? Thanks and regards, Lokesh > > Pali Rohár (13): > serial: usbtty: Fix puts function > usb: musb: Fix compilation of gadget code > usb: musb: Always clear the data toggle bit when configuring ep > usb: musb: Fix configuring FIFO for endpoints > usb: musb: Read value of PERI_RXCSR to 16bit variable > usb: musb: Fix transmission of bigger buffers > usb: gadget: Do not export usbd_device_* arrays > usb: gadget: Use dbg_ep0() macro instead of serial_printf() > arm: omap3: Compile lowlevel_init() function only when it is used > arm: omap3: Compile s_init() function only when it is used > Nokia RX-51: Remove function set_muxconf_regs() > Nokia RX-51: Move content of rx51.h to rx51.c > Nokia RX-51: Enable usbtty serial console by default > > Makefile | 1 + > arch/arm/mach-omap2/omap3/board.c | 3 + > arch/arm/mach-omap2/omap3/lowlevel_init.S | 6 +- > board/nokia/rx51/rx51.c | 28 +- > board/nokia/rx51/rx51.h | 377 -- > configs/nokia_rx51_defconfig | 6 +- > doc/README.nokia_rx51 | 15 +- > drivers/serial/usbtty.c | 4 +- > drivers/usb/gadget/core.c | 38 +-- > drivers/usb/gadget/ep0.c | 47 ++- > drivers/usb/musb/musb_core.c | 10 +- > drivers/usb/musb/musb_udc.c | 19 +- > include/configs/nokia_rx51.h | 16 +- > include/usbdevice.h | 15 - > 14 files changed, 92 insertions(+), 493 deletions(-) > delete mode 100644 board/nokia/rx51/rx51.h >
RE: [PATCH v8 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support
Hi All, There is a typo in comments in original commit message. The correct values are as follows. with v8: $ size spl/arch/arm/mach-rmobile/cpu_info.o text data bss dec hex filename 330 0 0 330 14a spl/arch/arm/mach-rmobile/cpu_info.o $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o -rw-r--r-- 1 biju biju 9176 Jan 16 18:10 spl/arch/arm/mach-rmobile/cpu_info.o $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o -rw-r--r-- 1 biju biju 6244 Jan 16 18:30 spl/arch/arm/mach-rmobile/cpu_info-rcar.o $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o text data bss dec hex filename 120 0 0 120 78 spl/arch/arm/mach-rmobile/cpu_info-rcar.o with v7: $ size spl/arch/arm/mach-rmobile/cpu_info.o text data bss dec hex filename 462 0 0 462 1ce spl/arch/arm/mach-rmobile/cpu_info.o $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o -rw-r--r-- 1 biju biju 9308 Jan 16 17:28 spl/arch/arm/mach-rmobile/cpu_info.o $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o -rw-r--r-- 1 biju biju 6864 Jan 16 18:28 spl/arch/arm/mach-rmobile/cpu_info-rcar.o $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o text data bss dec hex filename 154 0 0 154 9a spl/arch/arm/mach-rmobile/cpu_info-rcar.o Regards, Biju > Subject: [PATCH v8 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support > > RZ/G2 SoC's are identical to R-Car Gen3 SoC's apart from some automotive > peripherals. > > RZ/G2H (R8A774E1) = R-Car H3-N (R8A77951). > RZ/G2M (R8A774A1) = R-Car M3-W (R8A77960). > RZ/G2N (R8A774B1) = R-Car M3-N (R8A77965). > RZ/G2E (R8A774C0) = R-Car E3 (R8A77990). > > As the devices are the same they also have the same SoC PRR register > values. SoC driver is used to distinguish the cpu type based on the > family. > > Signed-off-by: Biju Das > Reviewed-by: Lad Prabhakar > --- > v7->v8 > * Optimized the cpu detection image size, when Renesas SoC identification >driver is disabled for R-Car Gen2 SPL builds > > with v8: > > $ size spl/arch/arm/mach-rmobile/cpu_info.o >text data bss dec hex filename > 462 0 0 462 1ce > spl/arch/arm/mach-rmobile/cpu_info.o > > $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o > -rw-r--r-- 1 biju biju 9308 Jan 16 17:28 spl/arch/arm/mach- > rmobile/cpu_info.o > > $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o > -rw-r--r-- 1 biju biju 6864 Jan 16 18:28 spl/arch/arm/mach- > rmobile/cpu_info-rcar.o > > $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o >text data bss dec hex filename > 154 0 0 154 9a > spl/arch/arm/mach-rmobile/cpu_info-rcar.o > > with v7: > > $ size spl/arch/arm/mach-rmobile/cpu_info.o >text data bss dec hex filename > 330 0 0 330 14a > spl/arch/arm/mach-rmobile/cpu_info.o > > $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o > -rw-r--r-- 1 biju biju 9176 Jan 16 18:10 spl/arch/arm/mach- > rmobile/cpu_info.o > > $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o > -rw-r--r-- 1 biju biju 6244 Jan 16 18:30 spl/arch/arm/mach- > rmobile/cpu_info-rcar.o > > $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o >text data bss dec hex filename > 120 0 0 120 78 > spl/arch/arm/mach-rmobile/cpu_info-rcar.o > > v6->v7 > * Seperated driver patch series from board support patches. > v5->v6 > * Optimized the unique CPU identification method by using Renesas SoC > identification driver. > v4->v5 > * Add support for unique identification of RZ/G2 CPU types >(Ref: > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor > k.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201008085941.3600-1- > biju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.renesa > s.com%7Cf359d4ea30294c1866b008d8ba5e79d4%7C53d82571da1947e49cb4625a166a4a2 > a%7C0%7C0%7C637464262268730689%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA > iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=s2xAHTFxU > JuB%2FQwRRMVoQ37EDOgqvZqceenB6v3RFp8%3Dreserved=0) > v3->v4 > * Dropped CPU info reporting logic for RZ/G2. Will address this later. > * Added PRRID's for RZG2[HMNE] >(Ref: > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor > k.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201001103658.4835-1- > biju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.renesa > s.com%7Cf359d4ea30294c1866b008d8ba5e79d4%7C53d82571da1947e49cb4625a166a4a2 >
RE: [PATCH v8 0/4] Add CPU identification support for RZ/G2 SoC's
Hi All, There is a typo in comments in original commit message. The correct values are as follows. with v8: $ size spl/arch/arm/mach-rmobile/cpu_info.o text data bss dec hex filename 330 0 0 330 14a spl/arch/arm/mach-rmobile/cpu_info.o $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o -rw-r--r-- 1 biju biju 9176 Jan 16 18:10 spl/arch/arm/mach-rmobile/cpu_info.o $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o -rw-r--r-- 1 biju biju 6244 Jan 16 18:30 spl/arch/arm/mach-rmobile/cpu_info-rcar.o $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o text data bss dec hex filename 120 0 0 120 78 spl/arch/arm/mach-rmobile/cpu_info-rcar.o with v7: $ size spl/arch/arm/mach-rmobile/cpu_info.o text data bss dec hex filename 462 0 0 462 1ce spl/arch/arm/mach-rmobile/cpu_info.o $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o -rw-r--r-- 1 biju biju 9308 Jan 16 17:28 spl/arch/arm/mach-rmobile/cpu_info.o $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o -rw-r--r-- 1 biju biju 6864 Jan 16 18:28 spl/arch/arm/mach-rmobile/cpu_info-rcar.o $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o text data bss dec hex filename 154 0 0 154 9a spl/arch/arm/mach-rmobile/cpu_info-rcar.o Regards, Biju > -Original Message- > From: Biju Das > Sent: 16 January 2021 20:37 > To: Nobuhiro Iwamatsu ; Marek Vasut > > Cc: Biju Das ; Prabhakar Mahadev Lad > ; Adam Ford ; > Tom Rini ; Peng Fan ; u- > b...@lists.denx.de; Chris Paterson > Subject: [PATCH v8 0/4] Add CPU identification support for RZ/G2 SoC's > > This patch series aims to add CPU identification support for RZ/G2 SoC's > and adding SDHI quirks using SoC identification driver. > > This patch series depend on SoC identification driver[1] [1] > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor > k.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D224764data=04%7C0 > 1%7Cbiju.das.jz%40bp.renesas.com%7C1af7124c5afd4820c86a08d8ba5e786d%7C53d8 > 2571da1947e49cb4625a166a4a2a%7C0%7C0%7C637464262217814550%7CUnknown%7CTWFp > bGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D > %7C1000sdata=bnuDAT37%2FWPaTtu226Z3NCTInny%2B3CIormHcdAwYWMo%3Dr > eserved=0 > > v8: > * Added Jaehoon Chung's Rb tag > * Optimized the cpu detection image size, when Renesas SoC identification >driver is disabled for R-Car Gen2 SPL builds > > with v8: > > $ size spl/arch/arm/mach-rmobile/cpu_info.o >text data bss dec hex filename > 462 0 0 462 1ce > spl/arch/arm/mach-rmobile/cpu_info.o > > $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o > -rw-r--r-- 1 biju biju 9308 Jan 16 17:28 spl/arch/arm/mach- > rmobile/cpu_info.o > > $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o > -rw-r--r-- 1 biju biju 6864 Jan 16 18:28 spl/arch/arm/mach- > rmobile/cpu_info-rcar.o > > $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o >text data bss dec hex filename > 154 0 0 154 9a > spl/arch/arm/mach-rmobile/cpu_info-rcar.o > > with v7: > > $ size spl/arch/arm/mach-rmobile/cpu_info.o >text data bss dec hex filename > 330 0 0 330 14a > spl/arch/arm/mach-rmobile/cpu_info.o > > $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o > -rw-r--r-- 1 biju biju 9176 Jan 16 18:10 spl/arch/arm/mach- > rmobile/cpu_info.o > > $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o > -rw-r--r-- 1 biju biju 6244 Jan 16 18:30 spl/arch/arm/mach- > rmobile/cpu_info-rcar.o > > $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o >text data bss dec hex filename > 120 0 0 120 78 > spl/arch/arm/mach-rmobile/cpu_info-rcar.o > > v7: > * Incorporated Jaehoon Chung's review comments. > * Fixed the build error on Renesas ARM32 platforms. > * Seperated driver patch series from board support patches. > v6: > * Optimized the unique CPU identification method by using Renesas SoC > identification driver. > * quirks using soc_device_match. > > Biju Das (4): > arm: rmobile: Add RZ/G2[HMNE] SoC support > mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M > mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N > mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H > > arch/arm/mach-rmobile/Makefile | 7 + > arch/arm/mach-rmobile/cpu_info-rcar.c| 20 ++- > arch/arm/mach-rmobile/cpu_info.c | 12
