[PATCH] mmc: fsl_esdhc_imx: fix the DTOCV to 0xE

[Ye Li]

From: Haibo Chen 

On imx6Q/imx6DL, we find if config the DTOCV to 0~3, it will impact
cmd6 behavior, after cmd6 get transfer complete interrupt, the data0
line will keep low over 5 seconds. This should be a IC bug on imx6Q/DL.
For other platforms, do not has this issue.

To fix this issue, fix the DTOCV to 0xE, the max setting, this also align
with Linux configuration.

Signed-off-by: Haibo Chen 
Reviewed-by: Ye Li 
---
 drivers/mmc/fsl_esdhc_imx.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index e0e1326..7b31ed8 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -43,6 +43,12 @@
 #include "mmc_private.h"
 #endif
 
+#ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#ifdef CONFIG_FSL_USDHC
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE  1
+#endif
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #define SDHCI_IRQ_EN_BITS  (IRQSTATEN_CC | IRQSTATEN_TC | \
-- 
2.7.4

Re: [PATCH v2 1/1] arm: x86: qemu: move qfw to DM, include Arm support

[Asherah Connor]

On 21/02/20 04:02:p, Asherah Connor wrote:
> Updates the QFW driver to use the driver model, and adds support for QFW
> on Arm platforms by configuring from the device tree and using MMIO
> accordingly.
> 
> Signed-off-by: Asherah Connor 
> ---
> 
> (no changes since v1)

"no changes since v1" is my mistake, first (well, second) time using
patman :)

[PATCH v2 1/1] arm: x86: qemu: move qfw to DM, include Arm support

[Asherah Connor]

Updates the QFW driver to use the driver model, and adds support for QFW
on Arm platforms by configuring from the device tree and using MMIO
accordingly.

Signed-off-by: Asherah Connor 
---

(no changes since v1)

 arch/arm/Kconfig |   1 +
 arch/x86/cpu/qemu/cpu.c  |   7 +-
 arch/x86/cpu/qemu/qemu.c |  54 ++--
 arch/x86/cpu/qfw_cpu.c   |  11 +-
 cmd/qfw.c|  44 +++---
 drivers/misc/Kconfig |   1 +
 drivers/misc/qfw.c   | 287 +++
 include/qfw.h|  63 +
 8 files changed, 291 insertions(+), 177 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d51abbeaf0..3841ae3ba2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -937,6 +937,7 @@ config ARCH_QEMU
imply DM_RNG
imply DM_RTC
imply RTC_PL031
+   imply QFW
 
 config ARCH_RMOBILE
bool "Renesas ARM SoCs"
diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c
index 9ce86b379c..ab1b797f9a 100644
--- a/arch/x86/cpu/qemu/cpu.c
+++ b/arch/x86/cpu/qemu/cpu.c
@@ -22,7 +22,12 @@ int cpu_qemu_get_desc(const struct udevice *dev, char *buf, 
int size)
 
 static int cpu_qemu_get_count(const struct udevice *dev)
 {
-   return qemu_fwcfg_online_cpus();
+   struct udevice *qfw_dev = qemu_fwcfg_dev();
+
+   if (!qfw_dev)
+   return -ENODEV;
+
+   return qemu_fwcfg_online_cpus(qfw_dev);
 }
 
 static const struct cpu_ops cpu_qemu_ops = {
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 044a429c13..e255af9a4a 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -19,45 +20,20 @@ static bool i440fx;
 #ifdef CONFIG_QFW
 
 /* on x86, the qfw registers are all IO ports */
-#define FW_CONTROL_PORT0x510
-#define FW_DATA_PORT   0x511
-#define FW_DMA_PORT_LOW0x514
-#define FW_DMA_PORT_HIGH   0x518
-
-static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
-   uint32_t size, void *address)
-{
-   uint32_t i = 0;
-   uint8_t *data = address;
-
-   /*
-* writting FW_CFG_INVALID will cause read operation to resume at
-* last offset, otherwise read will start at offset 0
-*
-* Note: on platform where the control register is IO port, the
-* endianness is little endian.
-*/
-   if (entry != FW_CFG_INVALID)
-   outw(cpu_to_le16(entry), FW_CONTROL_PORT);
-
-   /* the endianness of data register is string-preserving */
-   while (size--)
-   data[i++] = inb(FW_DATA_PORT);
-}
-
-static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
-{
-   /* the DMA address register is big endian */
-   outl(cpu_to_be32((uintptr_t)dma), FW_DMA_PORT_HIGH);
-
-   while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
-   __asm__ __volatile__ ("pause");
-}
+static const struct qfw_plat x86_qfw_plat = {
+   .io = {
+   .control_port   = 0x510,
+   .data_port  = 0x511,
+   .dma_port_low   = 0x514,
+   .dma_port_high  = 0x518,
+   },
+};
 
-static struct fw_cfg_arch_ops fwcfg_x86_ops = {
-   .arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
-   .arch_read_dma = qemu_x86_fwcfg_read_entry_dma
+U_BOOT_DRVINFO(x86_qfw) = {
+   .name = "qfw",
+   .plat = _qfw_plat,
 };
+
 #endif
 
 static void enable_pm_piix(void)
@@ -132,10 +108,6 @@ static void qemu_chipset_init(void)
 
enable_pm_ich9();
}
-
-#ifdef CONFIG_QFW
-   qemu_fwcfg_init(_x86_ops);
-#endif
 }
 
 #if !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
diff --git a/arch/x86/cpu/qfw_cpu.c b/arch/x86/cpu/qfw_cpu.c
index b959eaddde..c8fb918494 100644
--- a/arch/x86/cpu/qfw_cpu.c
+++ b/arch/x86/cpu/qfw_cpu.c
@@ -18,7 +18,7 @@ int qemu_cpu_fixup(void)
int cpu_num;
int cpu_online;
struct uclass *uc;
-   struct udevice *dev, *pdev;
+   struct udevice *dev, *pdev, *qfwdev;
struct cpu_plat *plat;
char *cpu;
 
@@ -39,6 +39,13 @@ int qemu_cpu_fixup(void)
return -ENODEV;
}
 
+   /* get qfw dev */
+   qfwdev = qemu_fwcfg_dev();
+   if (!qfwdev) {
+   printf("unable to find qfw device\n");
+   return -ENODEV;
+   }
+
/* calculate cpus that are already bound */
cpu_num = 0;
for (uclass_find_first_device(UCLASS_CPU, );
@@ -48,7 +55,7 @@ int qemu_cpu_fixup(void)
}
 
/* get actual cpu number */
-   cpu_online = qemu_fwcfg_online_cpus();
+   cpu_online = qemu_fwcfg_online_cpus(qfwdev);
if (cpu_online < 0) {
printf("unable to get online cpu number: %d\n", cpu_online);
return cpu_online;
diff --git a/cmd/qfw.c b/cmd/qfw.c
index bb571487f0..ec80a9a3b5 100644
--- a/cmd/qfw.c
+++ b/cmd/qfw.c
@@ -8,19 +8,22 @@
 #include 

[PATCH v2 0/1] Move qfw to DM, add preliminary on Arm

[Asherah Connor]

Version 2 of this series explores moving the QFW driver to the driver
model.  We configure QFW on Arm from the device tree, while x86 uses a
U_BOOT_DRVINFO.  All the logic for talking PIO/MMIO/DMA now lives in the
QFW driver.

I've moved all the static variables from the qfw driver into its priv
data section.  Is this preferable?  It adds some complexity to callers,
as they need to obtain and then pass the `struct udevice *' around.

I haven't changed much of the calling convention into the driver yet,
and so for the most part we still "skip" the device model, instead
relying on it just to help us bring the device up and locate it again
later.  Where we go from here depends on whether we keep it in
UCLASS_MISC and whether we feel like it's useful to change the way we
call into it further.

There are some #ifdef hacks surrounding pause/yield and use of
outw/inb/etc. in the driver.  It feels like these should still be in
arch-specific parts somehow.

This is tested as building and working correctly on arm64 and x86_64
qemu.

To view the main driver file as of this change in a non-diffed format,
see:
https://git.src.kameliya.ee/~kameliya/u-boot/tree/qfw-priv/item/drivers/misc/qfw.c

(no changes since v1)

Asherah Connor (1):
  arm: x86: qemu: move qfw to DM, include Arm support

 arch/arm/Kconfig |   1 +
 arch/x86/cpu/qemu/cpu.c  |   7 +-
 arch/x86/cpu/qemu/qemu.c |  54 ++--
 arch/x86/cpu/qfw_cpu.c   |  11 +-
 cmd/qfw.c|  44 +++---
 drivers/misc/Kconfig |   1 +
 drivers/misc/qfw.c   | 287 +++
 include/qfw.h|  63 +
 8 files changed, 291 insertions(+), 177 deletions(-)

-- 
2.20.1

Re: [PATCH 4/5] sun7i: add support for Micronova srl s027_3 board

[Andre Przywara]

On Fri, 19 Feb 2021 16:27:41 +0100
Giulio Benetti  wrote:

Hi Giulio,

> On 2/19/21 12:37 PM, Andre Przywara wrote:
> > On Fri, 19 Feb 2021 11:12:08 +0100
> > Giulio Benetti  wrote:
> > 
> > Hi,
> >   
> >> On 2/19/21 2:44 AM, Andre Przywara wrote:  
> >>> On Fri, 19 Feb 2021 00:26:19 +0100
> >>> Giulio Benetti  wrote:
> >>>
> >>> Hi Giulio,
> >>>  
>  From: Giulio Benetti 
> 
>  Add support for Micronova srl s027_3 board by adding new vendor/board
>  folders and using in local Makefile the already present
>  board/sunxi/Makefile. The reason is that s027_3 needs a pin to be 
>  asserted
>  to enable lcd before setting controller up and sunxi board doesn't 
>  provide
>  a way to do this customization.  
> >>>
> >>> Have you tried CONFIG_VIDEO_LCD_POWER?  
> >>
> >> Yes, I already use that for DISPONOFF.  
> > 
> > So what are these pins for, exactly? Backlight? A regulator to provide
> > power to the LCD?  
> 
> It's the power rail for LCD.
> 
> > If you grep for "gpio.CONFIG" in sunxi_display.c, there are more GPIOs
> > that we set, for various reasons. Can you pick some from there, and set
> > them in your defconfig?  
> 
> Unfortunately my LCD_PWR drives a P-MOS so it must be inverted, while 
> LCD0_DISPONOFF can be meant as a lcd reset.
> 
> So I introduce CONFIG_VIDEO_LCD_POWER_ACTIVE_LOW for my board to work
> locally.
> 
> Would it make sense to send a patch for this for supporting my board?
> Or do I wait for you patchset [1] to be applied?
> 
> >>> I am strongly against introducing per-board code files, and we
> >>> definitely won't introduce them just for one GPIO.  
> >>
> >> I knew it was a strange hack, but I have 2 different pins to be set high
> >> before init video controller. Another idea that comes into my mind is to
> >> handle CONFIG_VIDEO_LCD_POWER as a gpio list and iterate/enable, what
> >> about that?  
> > 
> > Do you really need *two* pins to switch the LCD power supply?  
> 
> I've messed up names, I need only one pin for LCD power supply(the on 
> with P-MOS) but another to enable it(DISPONOFF). But here the problem 
> was that LCD power supply is active low.
> 
> > If yes,
> > this might be an option. But I guess at this point we want to go more a
> > DT route.  
> 
> Yes, agree.
> 
> > Speaking of which, I don't see any video output device in the DT, I
> > guess you just rely on simplefb.  
> 
> Yes, simplefb for u-boot while...
> 
> > But given that there is no bridge or
> > it seems to be transparent, at least, you might be able to describe
> > this in the DT as well, so Linux can use its own display driver?  
> 
> for Linux I use 4 different fdt overlays using fe,be,tcon and simple-panel.

I see that the simple-panel binding has a generic enable-gpios
property, so that sounds fine.
Can you share the DT snippets? Just to get an idea what is what and how
we can shortcut it, if needed?
There is also drivers/video/simple_panel.c in U-Boot, which would
handle the power-supply *and* enable-gpios properties already, can you
check if we can use that?
I am a bit reluctant to add just another set of CONFIG_GPIO_... options,
if everything is in the DT already.

How do you plan to handle the overlays? Is the LCD an option, or is it
always connected? You want to always enable it in the U-Boot
defconfig, don't you?

> > Then we might be able to find a more sustainable solution, based on
> > pins in the DT.  
> 
> Yes
> 
> > 
> > Cheers,
> > Andre
> > 
> > P.S. Can you please try to apply  
> 
> [1]:
> 
> > https://patchwork.ozlabs.org/project/uboot/patch/20210205010748.2646-1-andre.przyw...@arm.com/
> > This would be merged around the same time, and I am curious if this
> > still works with an LCD.  
> 
> For sure I will, I was waiting for this and I've also started to port it 
> a bit but I have not much time and then you added a patch. I'm going to 
> test it and report. If it doesn't work I'll try to fix it for having 
> s027_3 board added using DT then.

As you have surely noticed, we currently see a warning when compiling
boards with the old display engine, so this patch is needed to stop
that and to avoid removal of video support. I will send a slightly
fixed version soonish and then queue this for the next merge window,
opening in April. So it would be wise if you base any work on that
patch.

Cheers,
Andre

Re: [PATCH 0/1] Add preliminary support for QFW on Arm

[Asherah Connor]

Hello Heinrich,

On 21/02/19 06:02:p, Heinrich Schuchardt wrote:
> virtio-gpu is an alternative to ramfb. Why are you targeting ramfb and
> not virtio-gpu? Which impact does it have on the guest OS?

It happens to be what I'm already using, and the interface appears quite
simple.  I am hacking on an Arm OS, and using U-Boot's UEFI support to
provide a framebuffer to the booted target.  This works very well on
hardware (a ROCKPro64 in my case).  I've been using EDK2 in QEMU until
now, but am experimenting with using U-Boot in QEMU instead to minimise
differences between the hardware target and virtualised one.

virtio-gpu could work just as well, but in either case there is no
U-Boot support.  I figure keeping it very simple maximises my chance of
success here.

Best,

Asherah

Re: [PATCH 1/1] arm: qemu: support qfw

[Asherah Connor]

On 21/02/19 06:02:p, Heinrich Schuchardt wrote:
> drivers/misc/qfw.c should be converted to the driver model instead of
> initializing the driver in arch_early_init_r() on qemu-arm and
> qemu_chipset_init() on qemu-x86.
> 
> Cf. https://u-boot.readthedocs.io/en/latest/driver-model/index.html
> 
> Please, coordinate the change with Simon.

Understood.  I've played around a little bit with the DM and it
shouldn't be too hard to convert.  Probably the biggest question in my
mind is, should it be slotted into UCLASS_MISC?  Or do we create a qfw
uclass?

I am also a little unsure on the division of responsibilities and
configuration as we move this to DM.

Right now, drivers/misc/qfw.c handles the QFW "protocol" entirely on its
own, and it's the responsibility of arch/x86/cpu/qemu/qemu.c (and
arch/arm/mach-qemu/qemu.c in this patch series) to mediate the
communication between the QFW handler and the actual platform; i.e. on
x86 we use PIO (and we simply must assume it is present if the config is
enabled), and on Arm we use MMIO (and we use DT to detect and
configure).

In other words, on x86 including QFW means we need to just try PIO,
whereas on Arm including QFW means we let the DM handle it if the node
appears.  I'll try to make this work in code and hopefully someone can
guide me a little on the Kconfig.


> Should cmd/qfw.c be enhanced to show if the ramfb device is present?

Yes, once ramfb support is implemented, but I think that should come in
a later patch series.  We will initialise ramfb if we detect an
"etc/ramfb" entry in the qfw list, like here:

=> qfw list
bios-geometry
bootorder
etc/acpi/rsdp
etc/acpi/tables
etc/boot-fail-wait
etc/ramfb
etc/smbios/smbios-anchor
etc/smbios/smbios-tables
etc/table-loader
etc/tpm/log
opt/test
vgaroms/vgabios-ramfb.bin
=>

Including information on how much we allocated for the ramfb, where we
placed it, etc. will be a job for a future "qfw ramfb" command.

Best,

Asherah

Pull request: u-boot-sunxi/master for v2021.04

[Andre Przywara]

Hi Tom,

please pull the master branch from u-boot-sunxi, containing some fixes
for 2021.04:
-
- H616 clock fix to enable video PLL
- sunxi-common.h cleanups
- support for UART1 as the console on sun8i
- removing wrong linux,stdout-path from DTs
-

Build-tested on all 156 sunxi boards, boot tested on some of them.

Thanks,
Andre

==
The following changes since commit a1a652e8016426e2d67148cab225cd5ec45189fb:

  Merge tag 'mmc-2021-2-19' of 
https://gitlab.denx.de/u-boot/custodians/u-boot-mmc (2021-02-19 11:56:14 -0500)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi.git 

for you to fetch changes up to e036a1d227112565cdf32b5558ac6ccaf5d1633f:

  fdt/sunxi: Remove OF_STDOUT_PATH (2021-02-19 23:29:47 +)


Andre Przywara (1):
  fdt/sunxi: Remove OF_STDOUT_PATH

Jernej Skrabec (1):
  sunxi: spl: Fix H616 clock initialization

Samuel Holland (1):
  sunxi: Remove dead ifdefs in sunxi-common.h

Tobias Schramm (1):
  sunxi: support boot console on uart1 for sun8i

 README |  1 -
 arch/arm/include/asm/arch-sunxi/gpio.h |  1 +
 arch/arm/mach-sunxi/board.c|  5 +
 arch/arm/mach-sunxi/clock_sun50i_h6.c  |  5 +
 common/fdt_support.c   |  9 +
 include/configs/sunxi-common.h | 33 -
 scripts/config_whitelist.txt   |  1 -
 7 files changed, 12 insertions(+), 43 deletions(-)

Marvell PHY Support

[Marr, Hayden (Platform COE - Software)]

Hello,

I need to know if u-boot currently supports the Marvell PHY 88X3540 device. 
(Product brief here: 
https://jp.marvell.com/content/dam/marvell/en/public-collateral/phys-transceivers/marvell-phys-transcievers-alaska-x-88x3540-product-brief-2020-05.pdf)

We will be using u-boot on LX2160A-based hardware, containing this PHY chip.

Please reach out with any information/guidance.

Thanks!

Hayden Marr
Engineer I Software
Honeywell | Aerospace | Platform COE
2 N. 19th Ave (Deer Valley)
Phoenix, AZ 85027

Office: 602.436.0216

hayden.m...@honeywell.com
Honeywell.com

Re: Please pull mmc-2021-2-19

[Tom Rini]

On Fri, Feb 19, 2021 at 07:05:53AM +, Peng Fan (OSS) wrote:

> Hi Tom,
> 
> Please pull mmc-2021-2-19
> 
> Sorry for delay, I have been quite busy in the past days.
> =
> mmc_spi improvement
> added mmc-pwrseq to remove duplicated code
> fix response timeout after switch command
> sdhci: skip cache invalidation if DMA is not used
> =
> 
> Thanks,
> Peng.
> 
> The following changes since commit 2dddc1bb296308b48f89f31e711965fa2c8091a0:
> 
>   net: tftp: Avoid sending extra ack on completion (2021-02-18 08:20:34 -0500)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-mmc.git tags/mmc-2021-2-19
> 
> for you to fetch changes up to 144d0574d5f3652008ef400e86cc66db5ef88736:
> 
>   configs: enable CONFIG_MMC_PWRSEQ configuration (2021-02-19 15:11:33 +0800)
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature

[PATCH] arm: bootm: wrong lmb region reservation when PRAM is used

[Aleksandar Gerasimovski]

This is a draft patch to describe the problem and to initiate
a discussion for solution.

PRAM usage is not taken into account when reserving lmb for ARM
architecture, this means that predefined PRAM region is reserved
by the u-boot and cannot be used by the u-boot users.

In our case this bug leads to non functional ramfs boot, as the PRAM and
ram rootfs address ranges are getting reserved by the u-boot.

It is obvious that here PRAM region is ignored, but my question is is this
clear to everyone and expected?

Taking  board_f.c as reference, when calculating relocation address PRAM
area is taken into account so I would expect that to be case here.
Here the intention is to reserve unused space at the end of the effective
RAM but PRAM is not part of that.

Possible solution would be to introduce something like
get_effective_memsize here e.g powerpc/lib/bootm.c but then also
NR_DRAM_BANKS has to be considered?

Signed-off-by: Aleksandar Gerasimovski 

---
 arch/arm/lib/bootm.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 11af9e2..4b06d25 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -54,7 +54,7 @@ static ulong get_sp(void)
 
 void arch_lmb_reserve(struct lmb *lmb)
 {
-   ulong sp, bank_end;
+   ulong sp, bank_end, pram = 0;
int bank;
 
/*
@@ -69,6 +69,11 @@ void arch_lmb_reserve(struct lmb *lmb)
sp = get_sp();
debug("## Current stack ends at 0x%08lx ", sp);
 
+#ifdef CONFIG_PRAM
+   pram = env_get_ulong("pram", 10, CONFIG_PRAM);
+   pram = pram << 10;  /* size is in kB */
+#endif
+
/* adjust sp by 4K to be safe */
sp -= 4096;
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
@@ -76,8 +81,9 @@ void arch_lmb_reserve(struct lmb *lmb)
sp < gd->bd->bi_dram[bank].start)
continue;
/* Watch out for RAM at end of address space! */
+   /* @todo: pram obviously wrong if NR_DRAM_BANKS > 1 */
bank_end = gd->bd->bi_dram[bank].start +
-   gd->bd->bi_dram[bank].size - 1;
+  gd->bd->bi_dram[bank].size - pram - 1;
if (sp > bank_end)
continue;
if (bank_end > gd->ram_top)
-- 
1.8.3.1

Re: Frustrations of running testing

[Tom Rini]

On Fri, Feb 19, 2021 at 12:28:16PM -0600, Alex G. wrote:

> Hi,
> 
> I keep being hit by two frustrating issues when trying to run tests. My
> expectation is that I can run a test at any time when working on something
> -- usually to check the correctness of that something. That's not the case
> today.
> 
> 
> The first one is an error message about mrproper:
> 
>   $ ./test/py/test.py --bd sandbox_spl
>   .. is not clean, please run 'make mrproper'
> 
> I don't think this message is very useful. Running 'mrproper' is out of the
> question, as it would wipe out the branch I'm currently working on. So what
> I end up doing is deleting the mrimproper check from the Makefile. And while
> it's a fast workaround, it dirties the tree and gets in the way of rebasing
> patches or working with git.
> 
> I can continue just fine without 'mrproper death' so I really don't
> understand the over-abundance of caution in breaking the build.

So, I looked a bit here.  The problem is that our logic in the top-level
Makefile for "Is this a separate srctree/objtree build?" is very out of
date / wrong.  Re-syncing this with a current Linux Makefile should
resolve this problem.

> The second issue is the how the tests are trying to build graphics:
> 
>   $ ./test/py/test.py --bd sandbox_spl -k "whatever"
>   make[1]: sdl2-config: Command not found
>   ../arch/sandbox/cpu/sdl.c:10:10: fatal error: SDL2/SDL.h:
>   No such file or directory
>  10 | #include 
> 
> The solution is to set NO_SDL=1, but this is far from obvious. The first
> instinct is always to look up the command help:
> 
>   $ ./test/py/test.py --help
> 
> But this really isn't at all useful. A simple grep for sdl2-config also
> doesn't immediately reveal the solution. Most u-boot tools get their
> arguments via the commandline. Thus, a reasonably competent u-boot developer
> will not think that environment variables are the solution. Ergo,
> environment variables are not the ideal way to solve this.
> 
> Maybe we could have a commandline option, and at the very least, catch this
> error and print something useful on the console.
> 
> 
> I'm not sure what the preferred way would be to solve the above. For me,
> these issues cause a significant enough disruption to my workflow, that I am
> very likely to not run tests regularly. I suspect I'm not alone.

Part of the problem is that if you don't have graphics enabled in
sandbox, you in turn don't get other tests run I believe.  A check in
arch/sandbox/config.mk for NO_SDL being unset AND not having
$(SDL_CONFIG) exist would provide a better user experience, yes.

Thanks for the feedback!

-- 
Tom


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Re: [PATCH] Makefile: Add target to generate hex output for combined spl and dtb

[Tom Rini]

On Fri, Feb 19, 2021 at 01:55:44PM +0800, Siew Chin Lim wrote:

> From: Dalon Westergreen 
> 
> Some architectures, Stratix10/Agilex, require a hex formatted spl that
> combines the spl image and dtb.  This adds a target to create said hex
> file with and offset of SPL_TEXT_BASE.
> 
> Signed-off-by: Dalon Westergreen 
> Signed-off-by: Siew Chin Lim 
> ---
>  Makefile   | 11 ++-
>  include/configs/socfpga_soc64_common.h |  2 +-
>  scripts/Makefile.spl   |  8 
>  3 files changed, 15 insertions(+), 6 deletions(-)
> 
> diff --git a/Makefile b/Makefile
> index 4da46dea39..f1adc9aa23 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1263,11 +1263,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
>   $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
>   $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R 
> .resetvec)
>  
> -OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
> -
> -spl/u-boot-spl.hex: spl/u-boot-spl FORCE
> - $(call if_changed,objcopy)
> -
>  binary_size_check: u-boot-nodtb.bin FORCE
>   @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
>   map_size=$(shell cat u-boot.map | \
> @@ -1935,6 +1930,12 @@ spl/u-boot-spl.bin: spl/u-boot-spl
>   @:
>   $(SPL_SIZE_CHECK)
>  
> +spl/u-boot-spl-dtb.bin: spl/u-boot-spl
> + @:
> +
> +spl/u-boot-spl-dtb.hex: spl/u-boot-spl
> + @:
> +
>  spl/u-boot-spl: tools prepare \
>   $(if 
> $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
>   $(if 
> $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
> diff --git a/include/configs/socfpga_soc64_common.h 
> b/include/configs/socfpga_soc64_common.h
> index fdcd7d3e9a..1af359466c 100644
> --- a/include/configs/socfpga_soc64_common.h
> +++ b/include/configs/socfpga_soc64_common.h
> @@ -200,7 +200,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
>   * 0x8000_ .. End of SDRAM_1 (assume 2GB)
>   *
>   */
> -#define CONFIG_SPL_TARGET"spl/u-boot-spl.hex"
> +#define CONFIG_SPL_TARGET"spl/u-boot-spl-dtb.hex"
>  #define CONFIG_SPL_MAX_SIZE  CONFIG_SYS_INIT_RAM_SIZE
>  #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
>  #define CONFIG_SPL_BSS_MAX_SIZE  0x10/* 1 MB */
> diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
> index ea4e045769..625e06d0d9 100644
> --- a/scripts/Makefile.spl
> +++ b/scripts/Makefile.spl
> @@ -229,6 +229,9 @@ ifneq 
> ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),)
>  INPUTS-y += $(obj)/$(SPL_BIN).sfp
>  endif
>  
> +INPUTS-$(CONFIG_TARGET_SOCFPGA_STRATIX10)+= $(obj)/u-boot-spl-dtb.hex
> +INPUTS-$(CONFIG_TARGET_SOCFPGA_AGILEX)   += 
> $(obj)/u-boot-spl-dtb.hex
> +
>  ifdef CONFIG_ARCH_SUNXI
>  INPUTS-y += $(obj)/sunxi-spl.bin
>  
> @@ -389,6 +392,11 @@ $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
>  MKIMAGEFLAGS_sunxi-spl.bin = -T sunxi_egon \
>   -n $(CONFIG_DEFAULT_DEVICE_TREE)
>  
> +OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex 
> --change-address=$(CONFIG_SPL_TEXT_BASE)
> +
> +$(obj)/u-boot-spl-dtb.hex: $(obj)/u-boot-spl-dtb.bin FORCE
> + $(call if_changed,objcopy)
> +
>  $(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE
>   $(call if_changed,mkimage)

The commit message / subject doesn't make it clear that you're doing
something for SoCFPGA here, and I seem to recall this change being
proposed a while ago and it wasn't clear that this is really the best
default path forward I thought?

>  
> -- 
> 2.13.0
> 

-- 
Tom


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Re: [PATCH] rng: iProc rng200: Rename ..._platdata variables to just ..._plat

[Tom Rini]

On Thu, Feb 18, 2021 at 08:39:42PM +, Peter Robinson wrote:
> On Thu, Feb 18, 2021 at 8:36 PM Heinrich Schuchardt  
> wrote:
> >
> > On 18.02.21 21:06, Peter Robinson wrote:
> > > In 8a8d24bd Simon dropped data from all the various _platdata calls
> > > but it seems this wasn't caught for the RNG200 driver from when it
> > > was posted to merged. This fixes that issue.
> > >
> > > Fixes: 537f0018 (rng: Add iProc RNG200 driver)
> > > Signed-off-by: Peter Robinson 
> > > ---
> > >  drivers/rng/iproc_rng200.c | 20 ++--
> > >  1 file changed, 10 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/drivers/rng/iproc_rng200.c b/drivers/rng/iproc_rng200.c
> > > index f71f285f53..1126bbd797 100644
> > > --- a/drivers/rng/iproc_rng200.c
> > > +++ b/drivers/rng/iproc_rng200.c
> > > @@ -33,11 +33,11 @@
> > >  #define RNG_FIFO_COUNT_OFFSET0x24
> > >  #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK   0x00FF
> > >
> > > -struct iproc_rng200_platdata {
> > > +struct iproc_rng200_plat {
> >
> > The renaming of the structure seems to be unrelated to the commit message.
> >
> > You are moving from allocating via plat_auto to priv_auto. So a
> > reasonable name for the structure would be iproc_rng200_priv.
> >
> > >   fdt_addr_t base;
> > >  };
> > >
> > > -static void iproc_rng200_enable(struct iproc_rng200_platdata *pdata, 
> > > bool enable)
> > > +static void iproc_rng200_enable(struct iproc_rng200_plat *pdata, bool 
> > > enable)
> > >  {
> > >   fdt_addr_t rng_base = pdata->base;
> > >   u32 val;
> > > @@ -52,7 +52,7 @@ static void iproc_rng200_enable(struct 
> > > iproc_rng200_platdata *pdata, bool enable
> > >   writel(val, rng_base + RNG_CTRL_OFFSET);
> > >  }
> > >
> > > -static void iproc_rng200_restart(struct iproc_rng200_platdata *pdata)
> > > +static void iproc_rng200_restart(struct iproc_rng200_plat *pdata)
> > >  {
> > >   fdt_addr_t rng_base = pdata->base;
> > >   u32 val;
> > > @@ -84,7 +84,7 @@ static void iproc_rng200_restart(struct 
> > > iproc_rng200_platdata *pdata)
> > >
> > >  static int iproc_rng200_read(struct udevice *dev, void *data, size_t len)
> > >  {
> > > - struct iproc_rng200_platdata *priv = dev_get_plat(dev);
> > > + struct iproc_rng200_plat *priv = dev_get_plat(dev);
> >
> > At the end of the patch you move from plat_auto to priv_auto. So
> > shouldn't you call dev_get_priv(dev)?
> >
> > >   char *buf = (char *)data;
> > >   u32 num_remaining = len;
> > >   u32 status;
> > > @@ -136,7 +136,7 @@ static int iproc_rng200_read(struct udevice *dev, 
> > > void *data, size_t len)
> > >
> > >  static int iproc_rng200_probe(struct udevice *dev)
> > >  {
> > > - struct iproc_rng200_platdata *priv = dev_get_plat(dev);
> > > + struct iproc_rng200_plat *priv = dev_get_plat(dev);
> > >
> > >   iproc_rng200_enable(priv, true);
> > >
> > > @@ -145,16 +145,16 @@ static int iproc_rng200_probe(struct udevice *dev)
> > >
> > >  static int iproc_rng200_remove(struct udevice *dev)
> > >  {
> > > - struct iproc_rng200_platdata *priv = dev_get_plat(dev);
> > > + struct iproc_rng200_plat *priv = dev_get_plat(dev);
> > >
> > >   iproc_rng200_enable(priv, false);
> > >
> > >   return 0;
> > >  }
> > >
> > > -static int iproc_rng200_ofdata_to_platdata(struct udevice *dev)
> > > +static int iproc_rng200_of_to_plat(struct udevice *dev)
> > >  {
> > > - struct iproc_rng200_platdata *pdata = dev_get_plat(dev);
> > > + struct iproc_rng200_plat *pdata = dev_get_plat(dev);
> > >
> > >   pdata->base = dev_read_addr(dev);
> > >   if (!pdata->base)
> > > @@ -180,6 +180,6 @@ U_BOOT_DRIVER(iproc_rng200_rng) = {
> > >   .ops = _rng200_ops,
> > >   .probe = iproc_rng200_probe,
> > >   .remove = iproc_rng200_remove,
> > > - .plat_auto = sizeof(struct iproc_rng200_platdata),
> > > - .of_to_plat = iproc_rng200_ofdata_to_platdata,
> > > + .priv_auto = sizeof(struct iproc_rng200_plat),
> > > + .of_to_plat = iproc_rng200_of_to_plat,
> >
> > Why do you set of_to_plat if you are using priv_auto data?
> > I would have expected the probe function to fill the auto allocated
> > private data.
> 
> I based the change on Simon's changes

Yeah, this is fine, it was generally a global search and replace on all
the structs and funcs.  I'll pick this up (and some similar patches)
soon, and just be a little annoyed at all the code that's clearly not
getting built somehow today.  It'd be great to figure out if it should
be in some defconfig or what.

-- 
Tom


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RAM test Uboot

[Fariya F]

Hi,

I would like to perform a RAM test at the bootloader level. My board is a
beaglebone board.  The problem is that my beaglebone board isn't booting
successfully. The kernel is crashing with "Unable to handle kernel paging
request at virtual address" I suspect it could be something to do with
RAM/MMU and hence would want to perform a RAM test.

Could someone help me with commands via which I can write to memory
locations starting from xx to yy and read back and see if the content
matches with what I wrote. The intent is to save these commands by
'saveenv' and execute it using the 'run' command on the bootloader prompt.
FYI, my bootloader version read from the source code Makefile is (Version:
2016, Patch 03). [I tried just the bare command mtest and it takes forever
to complete - not sure why so I thought I would do a memory write and
memory read and compare and determine if everything is OK with the RAM or
not]

#2: In addition when I check the eMMC partition map using mmc commands on
the bootloader prompt - everything looks ok. Is it possible to determine if
some corruption happened to the eMMC due to which the kernel wouldn't boot?

Regards,
FF

[PATCH v6 09/11] lib/rsa: Use the 'keyfile' argument from mkimage

[Alexandru Gagniuc]

Keys can be derived from keydir, and the "key-name-hint" property of
the FIT. They can also be specified ad-literam via 'keyfile'. Update
the RSA signing path to use the appropriate one.

Signed-off-by: Alexandru Gagniuc 
Reviewed-by: Simon Glass 
---
 lib/rsa/rsa-sign.c | 34 ++
 1 file changed, 26 insertions(+), 8 deletions(-)

diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
index 557c690a6d..65c6d4490c 100644
--- a/lib/rsa/rsa-sign.c
+++ b/lib/rsa/rsa-sign.c
@@ -210,14 +210,20 @@ static int rsa_get_pub_key(const char *keydir, const char 
*name,
  * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL)
  */
 static int rsa_pem_get_priv_key(const char *keydir, const char *name,
-   RSA **rsap)
+   const char *keyfile, RSA **rsap)
 {
char path[1024];
RSA *rsa;
FILE *f;
 
*rsap = NULL;
-   snprintf(path, sizeof(path), "%s/%s.key", keydir, name);
+   if (keydir && name)
+   snprintf(path, sizeof(path), "%s/%s.key", keydir, name);
+   else if (keyfile)
+   snprintf(path, sizeof(path), "%s", keyfile);
+   else
+   return -EINVAL;
+
f = fopen(path, "r");
if (!f) {
fprintf(stderr, "Couldn't open RSA private key: '%s': %s\n",
@@ -247,6 +253,7 @@ static int rsa_pem_get_priv_key(const char *keydir, const 
char *name,
  * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL)
  */
 static int rsa_engine_get_priv_key(const char *keydir, const char *name,
+  const char *keyfile,
   ENGINE *engine, RSA **rsap)
 {
const char *engine_id;
@@ -260,6 +267,10 @@ static int rsa_engine_get_priv_key(const char *keydir, 
const char *name,
engine_id = ENGINE_get_id(engine);
 
if (engine_id && !strcmp(engine_id, "pkcs11")) {
+   if (!keydir && !name) {
+   fprintf(stderr, "Please use 'keydir' with PKCS11\n");
+   return -EINVAL;
+   }
if (keydir)
if (strstr(keydir, "object="))
snprintf(key_id, sizeof(key_id),
@@ -274,14 +285,19 @@ static int rsa_engine_get_priv_key(const char *keydir, 
const char *name,
 "pkcs11:object=%s;type=private",
 name);
} else if (engine_id) {
-   if (keydir)
+   if (keydir && name)
snprintf(key_id, sizeof(key_id),
 "%s%s",
 keydir, name);
-   else
+   else if (keydir)
snprintf(key_id, sizeof(key_id),
 "%s",
 name);
+   else if (keyfile)
+   snprintf(key_id, sizeof(key_id), "%s", keyfile);
+   else
+   return -EINVAL;
+
} else {
fprintf(stderr, "Engine not supported\n");
return -ENOTSUP;
@@ -319,11 +335,12 @@ err_rsa:
  * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL)
  */
 static int rsa_get_priv_key(const char *keydir, const char *name,
-   ENGINE *engine, RSA **rsap)
+   const char *keyfile, ENGINE *engine, RSA **rsap)
 {
if (engine)
-   return rsa_engine_get_priv_key(keydir, name, engine, rsap);
-   return rsa_pem_get_priv_key(keydir, name, rsap);
+   return rsa_engine_get_priv_key(keydir, name, keyfile, engine,
+  rsap);
+   return rsa_pem_get_priv_key(keydir, name, keyfile, rsap);
 }
 
 static int rsa_init(void)
@@ -534,7 +551,8 @@ int rsa_sign(struct image_sign_info *info,
goto err_engine;
}
 
-   ret = rsa_get_priv_key(info->keydir, info->keyname, e, );
+   ret = rsa_get_priv_key(info->keydir, info->keyname, info->keyfile,
+  e, );
if (ret)
goto err_priv;
ret = rsa_sign_with_key(rsa, info->padding, info->checksum, region,
-- 
2.26.2

[PATCH v6 10/11] lib/ecdsa: Use the 'keydir' argument from mkimage if appropriate

[Alexandru Gagniuc]

Keys can be derived from keydir, and the "key-name-hint" property of
the FIT. They can also be specified ad-literam via 'keyfile'. Update
the ECDSA signing path to use the appropriate one.

Signed-off-by: Alexandru Gagniuc 
Reviewed-by: Simon Glass 
---
 lib/ecdsa/ecdsa-libcrypto.c | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/lib/ecdsa/ecdsa-libcrypto.c b/lib/ecdsa/ecdsa-libcrypto.c
index 322880963f..1757a14562 100644
--- a/lib/ecdsa/ecdsa-libcrypto.c
+++ b/lib/ecdsa/ecdsa-libcrypto.c
@@ -140,8 +140,20 @@ static int read_key(struct signer *ctx, const char 
*key_name)
 /* Prepare a 'signer' context that's ready to sign and verify. */
 static int prepare_ctx(struct signer *ctx, const struct image_sign_info *info)
 {
-   const char *kname = info->keydir;
int key_len_bytes, ret;
+   char kname[1024];
+
+   memset(ctx, 0, sizeof(*ctx));
+
+   if (info->keyfile) {
+   snprintf(kname,  sizeof(kname), "%s", info->keyfile);
+   } else if (info->keydir && info->keyname) {
+   snprintf(kname, sizeof(kname), "%s/%s.pem", info->keydir,
+info->keyname);
+   } else {
+   fprintf(stderr, "keyfile, keyname, or key-name-hint missing\n");
+   return -EINVAL;
+   }
 
ret = alloc_ctx(ctx, info);
if (ret)
-- 
2.26.2

[PATCH v6 11/11] test/py: ecdsa: Use mkimage keyfile instead of keydir argument

[Alexandru Gagniuc]

Originally, the ECDSA code path used 'keydir' as the key filename.
mkimage has since been updated to include a new 'keyfile' argument.
Use the new argument for passing in the key.

Signed-off-by: Alexandru Gagniuc 
---
 test/py/tests/test_fit_ecdsa.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/test/py/tests/test_fit_ecdsa.py b/test/py/tests/test_fit_ecdsa.py
index f597570281..87b6081222 100644
--- a/test/py/tests/test_fit_ecdsa.py
+++ b/test/py/tests/test_fit_ecdsa.py
@@ -52,7 +52,7 @@ class SignableFitImage(object):
 self.__fdt_set(f'{image}/signature', algo='sha256,ecdsa256')
 
 def sign(self, mkimage, key_file):
-util.run_and_log(self.cons, [mkimage, '-F', self.fit, f'-k{key_file}'])
+util.run_and_log(self.cons, [mkimage, '-F', self.fit, f'-G{key_file}'])
 
 def check_signatures(self, key):
 for image in self.signable_nodes:
-- 
2.26.2

[PATCH v6 08/11] mkimage: Add a 'keyfile' argument for image signing

[Alexandru Gagniuc]

It's not always desirable to use 'keydir' and some ad-hoc heuristics
to get the filename of the signing key. More often, just passing the
filename is the simpler, easier, and logical thing to do.

Since mkimage doesn't use long options, we're slowly running out of
letters. I've chosen '-G' because it was available.

Signed-off-by: Alexandru Gagniuc 
Reviewed-by: Simon Glass 
---
 include/image.h| 16 +
 tools/fit_image.c  |  3 ++-
 tools/image-host.c | 58 +-
 tools/imagetool.h  |  1 +
 tools/mkimage.c|  6 -
 5 files changed, 52 insertions(+), 32 deletions(-)

diff --git a/include/image.h b/include/image.h
index 37feb5d56f..5bb7922a66 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1131,9 +1131,10 @@ int fit_cipher_data(const char *keydir, void *keydest, 
void *fit,
  * 0, on success
  * libfdt error code, on failure
  */
-int fit_add_verification_data(const char *keydir, void *keydest, void *fit,
- const char *comment, int require_keys,
- const char *engine_id, const char *cmdname);
+int fit_add_verification_data(const char *keydir, const char *keyfile,
+ void *keydest, void *fit, const char *comment,
+ int require_keys, const char *engine_id,
+ const char *cmdname);
 
 int fit_image_verify_with_data(const void *fit, int image_noffset,
   const void *data, size_t size);
@@ -1251,10 +1252,17 @@ void image_set_host_blob(void *host_blob);
 #endif
 #endif /* IMAGE_ENABLE_FIT */
 
-/* Information passed to the signing routines */
+/*
+ * Information passed to the signing routines
+ *
+ * Either 'keydir',  'keyname', or 'keyfile' can be NULL. However, either
+ * 'keyfile', or both 'keydir' and 'keyname' should have valid values. If
+ * neither are valid, some operations might fail with EINVAL.
+ */
 struct image_sign_info {
const char *keydir; /* Directory conaining keys */
const char *keyname;/* Name of key to use */
+   const char *keyfile;/* Filename of private or public key */
void *fit;  /* Pointer to FIT blob */
int node_offset;/* Offset of signature node */
const char *name;   /* Algorithm name */
diff --git a/tools/fit_image.c b/tools/fit_image.c
index d440d143c6..ae30f80783 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -68,7 +68,8 @@ static int fit_add_file_data(struct image_tool_params 
*params, size_t size_inc,
}
 
if (!ret) {
-   ret = fit_add_verification_data(params->keydir, dest_blob, ptr,
+   ret = fit_add_verification_data(params->keydir,
+   params->keyfile, dest_blob, ptr,
params->comment,
params->require_keys,
params->engine_id,
diff --git a/tools/image-host.c b/tools/image-host.c
index 33a224129a..270d36fe45 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -153,8 +153,9 @@ static int fit_image_write_sig(void *fit, int noffset, 
uint8_t *value,
 }
 
 static int fit_image_setup_sig(struct image_sign_info *info,
-   const char *keydir, void *fit, const char *image_name,
-   int noffset, const char *require_keys, const char *engine_id)
+   const char *keydir, const char *keyfile, void *fit,
+   const char *image_name, int noffset, const char *require_keys,
+   const char *engine_id)
 {
const char *node_name;
char *algo_name;
@@ -171,6 +172,7 @@ static int fit_image_setup_sig(struct image_sign_info *info,
 
memset(info, '\0', sizeof(*info));
info->keydir = keydir;
+   info->keyfile = keyfile;
info->keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL);
info->fit = fit;
info->node_offset = noffset;
@@ -207,8 +209,8 @@ static int fit_image_setup_sig(struct image_sign_info *info,
  * @engine_id: Engine to use for signing
  * @return 0 if ok, -1 on error
  */
-static int fit_image_process_sig(const char *keydir, void *keydest,
-   void *fit, const char *image_name,
+static int fit_image_process_sig(const char *keydir, const char *keyfile,
+   void *keydest, void *fit, const char *image_name,
int noffset, const void *data, size_t size,
const char *comment, int require_keys, const char *engine_id,
const char *cmdname)
@@ -220,8 +222,9 @@ static int fit_image_process_sig(const char *keydir, void 
*keydest,
uint value_len;
int ret;
 
-   if (fit_image_setup_sig(, keydir, fit, image_name, noffset,
-   require_keys ? "image" : NULL, engine_id))
+  

[PATCH v6 03/11] lib: Add support for ECDSA image signing

[Alexandru Gagniuc]

mkimage supports rsa2048, and rsa4096 signatures. With newer silicon
now supporting hardware-accelerated ECDSA, it makes sense to expand
signing support to elliptic curves.

Implement host-side ECDSA signing and verification with libcrypto.
Device-side implementation of signature verification is beyond the
scope of this patch.

Signed-off-by: Alexandru Gagniuc 
Reviewed-by: Simon Glass 
---
 common/image-sig.c  |  11 +-
 include/image.h |   3 +
 include/u-boot/ecdsa.h  |  94 +++
 lib/ecdsa/ecdsa-libcrypto.c | 306 
 tools/Makefile  |   3 +
 5 files changed, 415 insertions(+), 2 deletions(-)
 create mode 100644 include/u-boot/ecdsa.h
 create mode 100644 lib/ecdsa/ecdsa-libcrypto.c

diff --git a/common/image-sig.c b/common/image-sig.c
index 54f0eb2019..0f8e592aba 100644
--- a/common/image-sig.c
+++ b/common/image-sig.c
@@ -16,6 +16,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif /* !USE_HOSTCC*/
 #include 
+#include 
 #include 
 #include 
 
@@ -83,8 +84,14 @@ struct crypto_algo crypto_algos[] = {
.sign = rsa_sign,
.add_verify_data = rsa_add_verify_data,
.verify = rsa_verify,
-   }
-
+   },
+   {
+   .name = "ecdsa256",
+   .key_len = ECDSA256_BYTES,
+   .sign = ecdsa_sign,
+   .add_verify_data = ecdsa_add_verify_data,
+   .verify = ecdsa_verify,
+   },
 };
 
 struct padding_algo padding_algos[] = {
diff --git a/include/image.h b/include/image.h
index fbe9537c00..37feb5d56f 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1219,16 +1219,19 @@ int calculate_hash(const void *data, int data_len, 
const char *algo,
 # if defined(CONFIG_FIT_SIGNATURE)
 #  define IMAGE_ENABLE_SIGN1
 #  define IMAGE_ENABLE_VERIFY  1
+#  define IMAGE_ENABLE_VERIFY_ECDSA1
 #  define FIT_IMAGE_ENABLE_VERIFY  1
 #  include 
 # else
 #  define IMAGE_ENABLE_SIGN0
 #  define IMAGE_ENABLE_VERIFY  0
+# define IMAGE_ENABLE_VERIFY_ECDSA 0
 #  define FIT_IMAGE_ENABLE_VERIFY  0
 # endif
 #else
 # define IMAGE_ENABLE_SIGN 0
 # define IMAGE_ENABLE_VERIFY   CONFIG_IS_ENABLED(RSA_VERIFY)
+# define IMAGE_ENABLE_VERIFY_ECDSA 0
 # define FIT_IMAGE_ENABLE_VERIFY   CONFIG_IS_ENABLED(FIT_SIGNATURE)
 #endif
 
diff --git a/include/u-boot/ecdsa.h b/include/u-boot/ecdsa.h
new file mode 100644
index 00..979690d966
--- /dev/null
+++ b/include/u-boot/ecdsa.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020, Alexandru Gagniuc .
+ */
+
+#ifndef _ECDSA_H
+#define _ECDSA_H
+
+#include 
+#include 
+#include 
+
+/**
+ * crypto_algo API impementation for ECDSA;
+ * @see "struct crypto_algo"
+ * @{
+ */
+#if IMAGE_ENABLE_SIGN
+/**
+ * sign() - calculate and return signature for given input data
+ *
+ * @info:  Specifies key and FIT information
+ * @data:  Pointer to the input data
+ * @data_len:  Data length
+ * @sigp:  Set to an allocated buffer holding the signature
+ * @sig_len:   Set to length of the calculated hash
+ *
+ * This computes input data signature according to selected algorithm.
+ * Resulting signature value is placed in an allocated buffer, the
+ * pointer is returned as *sigp. The length of the calculated
+ * signature is returned via the sig_len pointer argument. The caller
+ * should free *sigp.
+ *
+ * @return: 0, on success, -ve on error
+ */
+int ecdsa_sign(struct image_sign_info *info, const struct image_region 
region[],
+  int region_count, uint8_t **sigp, uint *sig_len);
+
+/**
+ * add_verify_data() - Add verification information to FDT
+ *
+ * Add public key information to the FDT node, suitable for
+ * verification at run-time. The information added depends on the
+ * algorithm being used. I just copypasted this from rsa.h.
+ *
+ * @info:  Specifies key and FIT information
+ * @keydest:   Destination FDT blob for public key data
+ * @return: 0, on success, -ENOSPC if the keydest FDT blob ran out of space,
+ * other -ve value on error
+ */
+int ecdsa_add_verify_data(struct image_sign_info *info, void *keydest);
+#else
+static inline
+int ecdsa_sign(struct image_sign_info *info, const struct image_region 
region[],
+  int region_count, uint8_t **sigp, uint *sig_len)
+{
+   return -ENXIO;
+}
+
+static inline
+int ecdsa_add_verify_data(struct image_sign_info *info, void *keydest)
+{
+   return -ENXIO;
+}
+#endif
+
+#if IMAGE_ENABLE_VERIFY_ECDSA
+/**
+ * verify() - Verify a signature against some data
+ *
+ * @info:  Specifies key and FIT information
+ * @data:  Pointer to the input data
+ * @data_len:  Data length
+ * @sig:   Signature
+ * @sig_len:   Number of bytes in signature
+ * @return 0 if verified, -ve on error
+ */
+int ecdsa_verify(struct image_sign_info *info,
+const struct image_region region[], int region_count,
+uint8_t *sig, uint sig_len);
+#else
+static 

[PATCH v6 07/11] doc: signature.txt: Document the keydir and keyfile arguments

[Alexandru Gagniuc]

After lots of debating, this documents how we'd like mkimage to treat
'keydir' and 'keyfile' arguments. The rest is in the docs.

Signed-off-by: Alexandru Gagniuc 
Reviewed-by: Simon Glass 
---
 doc/uImage.FIT/signature.txt | 13 +
 1 file changed, 13 insertions(+)

diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt
index 0139295d33..d9a9121190 100644
--- a/doc/uImage.FIT/signature.txt
+++ b/doc/uImage.FIT/signature.txt
@@ -472,6 +472,19 @@ Test Verified Boot Run: signed config with bad hash: OK
 Test passed
 
 
+Software signing: keydir vs keyfile
+---
+
+In the simplest case, signing is done by giving mkimage the 'keyfile'. This is
+the path to a file containing the signing key.
+
+The alternative is to pass the 'keydir' argument. In this case the filename of
+the key is derived from the 'keydir' and the "key-name-hint" property in the
+FIT. In this case the "key-name-hint" property is mandatory, and the key must
+exist in "/." Here the extension "ext" is
+specific to the signing algorithm.
+
+
 Hardware Signing with PKCS#11 or with HSM
 -
 
-- 
2.26.2

[PATCH v6 06/11] test/py: ecdsa: Add test for mkimage ECDSA signing

[Alexandru Gagniuc]

Add a test to make sure that the ECDSA signatures generated by
mkimage can be verified successfully. pyCryptodomex was chosen as the
crypto library because it integrates much better with python code.
Using openssl would have been unnecessarily painful.

Signed-off-by: Alexandru Gagniuc 
Reviewed-by: Simon Glass 
---
 test/py/tests/test_fit_ecdsa.py | 111 
 1 file changed, 111 insertions(+)
 create mode 100644 test/py/tests/test_fit_ecdsa.py

diff --git a/test/py/tests/test_fit_ecdsa.py b/test/py/tests/test_fit_ecdsa.py
new file mode 100644
index 00..f597570281
--- /dev/null
+++ b/test/py/tests/test_fit_ecdsa.py
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2020,2021 Alexandru Gagniuc 
+
+"""
+Test ECDSA signing of FIT images
+
+This test uses mkimage to sign an existing FIT image with an ECDSA key. The
+signature is then extracted, and verified against pyCryptodome.
+This test doesn't run the sandbox. It only checks the host tool 'mkimage'
+"""
+
+import pytest
+import u_boot_utils as util
+from Cryptodome.Hash import SHA256
+from Cryptodome.PublicKey import ECC
+from Cryptodome.Signature import DSS
+
+class SignableFitImage(object):
+""" Helper to manipulate a FIT image on disk """
+def __init__(self, cons, file_name):
+self.fit = file_name
+self.cons = cons
+self.signable_nodes = set()
+
+def __fdt_list(self, path):
+return util.run_and_log(self.cons, f'fdtget -l {self.fit} {path}')
+
+def __fdt_set(self, node, **prop_value):
+for prop, value in prop_value.items():
+util.run_and_log(self.cons, f'fdtput -ts {self.fit} {node} {prop} 
{value}')
+
+def __fdt_get_binary(self, node, prop):
+numbers = util.run_and_log(self.cons, f'fdtget -tbi {self.fit} {node} 
{prop}')
+
+bignum = bytearray()
+for little_num in numbers.split():
+bignum.append(int(little_num))
+
+return bignum
+
+def find_signable_image_nodes(self):
+for node in self.__fdt_list('/images').split():
+image = f'/images/{node}'
+if 'signature' in self.__fdt_list(image):
+self.signable_nodes.add(image)
+
+return self.signable_nodes
+
+def change_signature_algo_to_ecdsa(self):
+for image in self.signable_nodes:
+self.__fdt_set(f'{image}/signature', algo='sha256,ecdsa256')
+
+def sign(self, mkimage, key_file):
+util.run_and_log(self.cons, [mkimage, '-F', self.fit, f'-k{key_file}'])
+
+def check_signatures(self, key):
+for image in self.signable_nodes:
+raw_sig = self.__fdt_get_binary(f'{image}/signature', 'value')
+raw_bin = self.__fdt_get_binary(image, 'data')
+
+sha = SHA256.new(raw_bin)
+verifier = DSS.new(key, 'fips-186-3')
+verifier.verify(sha, bytes(raw_sig))
+
+
+@pytest.mark.buildconfigspec('fit_signature')
+@pytest.mark.requiredtool('dtc')
+@pytest.mark.requiredtool('fdtget')
+@pytest.mark.requiredtool('fdtput')
+def test_fit_ecdsa(u_boot_console):
+""" Test that signatures generated by mkimage are legible. """
+def generate_ecdsa_key():
+return ECC.generate(curve='prime256v1')
+
+def assemble_fit_image(dest_fit, its, destdir):
+dtc_args = f'-I dts -O dtb -i {destdir}'
+util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f', its, dest_fit])
+
+def dtc(dts):
+dtb = dts.replace('.dts', '.dtb')
+util.run_and_log(cons, f'dtc {datadir}/{dts} -O dtb -o 
{tempdir}/{dtb}')
+
+cons = u_boot_console
+mkimage = cons.config.build_dir + '/tools/mkimage'
+datadir = cons.config.source_dir + '/test/py/tests/vboot/'
+tempdir = cons.config.result_dir
+key_file = f'{tempdir}/ecdsa-test-key.pem'
+fit_file = f'{tempdir}/test.fit'
+dtc('sandbox-kernel.dts')
+
+key = generate_ecdsa_key()
+
+# Create a fake kernel image -- zeroes will do just fine
+with open(f'{tempdir}/test-kernel.bin', 'w') as fd:
+fd.write(500 * chr(0))
+
+# invocations of mkimage expect to read the key from disk
+with open(key_file, 'w') as f:
+f.write(key.export_key(format='PEM'))
+
+assemble_fit_image(fit_file, f'{datadir}/sign-images-sha256.its', tempdir)
+
+fit = SignableFitImage(cons, fit_file)
+nodes = fit.find_signable_image_nodes()
+if len(nodes) == 0:
+raise ValueError('FIT image has no "/image" nodes with "signature"')
+
+fit.change_signature_algo_to_ecdsa()
+fit.sign(mkimage, key_file)
+fit.check_signatures(key)
-- 
2.26.2

[PATCH v6 02/11] lib/rsa: Make fdt_add_bignum() available outside of RSA code

[Alexandru Gagniuc]

fdt_add_bignum() is useful for algorithms other than just RSA. To
allow its use for ECDSA, move it to a common file under lib/.

The new file is suffixed with '-libcrypto' because it has a direct
dependency on openssl. This is due to the use of the "BIGNUM *" type.

Signed-off-by: Alexandru Gagniuc 
Reviewed-by: Simon Glass 
---
 include/u-boot/fdt-libcrypto.h | 27 +
 lib/fdt-libcrypto.c| 72 ++
 lib/rsa/rsa-sign.c | 65 +-
 tools/Makefile |  5 +++
 4 files changed, 105 insertions(+), 64 deletions(-)
 create mode 100644 include/u-boot/fdt-libcrypto.h
 create mode 100644 lib/fdt-libcrypto.c

diff --git a/include/u-boot/fdt-libcrypto.h b/include/u-boot/fdt-libcrypto.h
new file mode 100644
index 00..5142f37039
--- /dev/null
+++ b/include/u-boot/fdt-libcrypto.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020, Alexandru Gagniuc 
+ * Copyright (c) 2013, Google Inc.
+ */
+
+#ifndef _FDT_LIBCRYPTO_H
+#define _FDT_LIBCRYPTO_H
+
+#include 
+
+/**
+ * fdt_add_bignum() - Write a libcrypto BIGNUM as an FDT property
+ *
+ * Convert a libcrypto BIGNUM * into a big endian array of integers.
+ *
+ * @blob:  FDT blob to modify
+ * @noffset:   Offset of the FDT node
+ * @prop_name: What to call the property in the FDT
+ * @num:   pointer to a libcrypto big number
+ * @num_bits:  How big is 'num' in bits?
+ * @return 0 if all good all working, -ve on horror
+ */
+int fdt_add_bignum(void *blob, int noffset, const char *prop_name,
+  BIGNUM *num, int num_bits);
+
+#endif /* _FDT_LIBCRYPTO_H */
diff --git a/lib/fdt-libcrypto.c b/lib/fdt-libcrypto.c
new file mode 100644
index 00..ecb0344c8f
--- /dev/null
+++ b/lib/fdt-libcrypto.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020, Alexandru Gagniuc 
+ * Copyright (c) 2013, Google Inc.
+ */
+
+#include 
+#include 
+
+int fdt_add_bignum(void *blob, int noffset, const char *prop_name,
+  BIGNUM *num, int num_bits)
+{
+   int nwords = num_bits / 32;
+   int size;
+   uint32_t *buf, *ptr;
+   BIGNUM *tmp, *big2, *big32, *big2_32;
+   BN_CTX *ctx;
+   int ret;
+
+   tmp = BN_new();
+   big2 = BN_new();
+   big32 = BN_new();
+   big2_32 = BN_new();
+
+   /*
+* Note: This code assumes that all of the above succeed, or all fail.
+* In practice memory allocations generally do not fail (unless the
+* process is killed), so it does not seem worth handling each of these
+* as a separate case. Technicaly this could leak memory on failure,
+* but a) it won't happen in practice, and b) it doesn't matter as we
+* will immediately exit with a failure code.
+*/
+   if (!tmp || !big2 || !big32 || !big2_32) {
+   fprintf(stderr, "Out of memory (bignum)\n");
+   return -ENOMEM;
+   }
+   ctx = BN_CTX_new();
+   if (!ctx) {
+   fprintf(stderr, "Out of memory (bignum context)\n");
+   return -ENOMEM;
+   }
+   BN_set_word(big2, 2L);
+   BN_set_word(big32, 32L);
+   BN_exp(big2_32, big2, big32, ctx); /* B = 2^32 */
+
+   size = nwords * sizeof(uint32_t);
+   buf = malloc(size);
+   if (!buf) {
+   fprintf(stderr, "Out of memory (%d bytes)\n", size);
+   return -ENOMEM;
+   }
+
+   /* Write out modulus as big endian array of integers */
+   for (ptr = buf + nwords - 1; ptr >= buf; ptr--) {
+   BN_mod(tmp, num, big2_32, ctx); /* n = N mod B */
+   *ptr = cpu_to_fdt32(BN_get_word(tmp));
+   BN_rshift(num, num, 32); /*  N = N/B */
+   }
+
+   /*
+* We try signing with successively increasing size values, so this
+* might fail several times
+*/
+   ret = fdt_setprop(blob, noffset, prop_name, buf, size);
+   free(buf);
+   BN_free(tmp);
+   BN_free(big2);
+   BN_free(big32);
+   BN_free(big2_32);
+
+   return ret ? -FDT_ERR_NOSPACE : 0;
+}
diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
index 1f0d81bd7a..557c690a6d 100644
--- a/lib/rsa/rsa-sign.c
+++ b/lib/rsa/rsa-sign.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -680,70 +681,6 @@ int rsa_get_params(RSA *key, uint64_t *exponent, uint32_t 
*n0_invp,
return ret;
 }
 
-static int fdt_add_bignum(void *blob, int noffset, const char *prop_name,
- BIGNUM *num, int num_bits)
-{
-   int nwords = num_bits / 32;
-   int size;
-   uint32_t *buf, *ptr;
-   BIGNUM *tmp, *big2, *big32, *big2_32;
-   BN_CTX *ctx;
-   int ret;
-
-   tmp = BN_new();
-   big2 = BN_new();
-   big32 = BN_new();
-   big2_32 = BN_new();
-
-   /*
-* Note: This code assumes that all of the above succeed, or all 

[PATCH v6 04/11] doc: signature.txt: Document devicetree format for ECDSA keys

[Alexandru Gagniuc]

Signed-off-by: Alexandru Gagniuc 
Reviewed-by: Simon Glass 
---
 doc/uImage.FIT/signature.txt | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt
index a3455889ed..0139295d33 100644
--- a/doc/uImage.FIT/signature.txt
+++ b/doc/uImage.FIT/signature.txt
@@ -142,7 +142,7 @@ public key in U-Boot's control FDT (using 
CONFIG_OF_CONTROL).
 Public keys should be stored as sub-nodes in a /signature node. Required
 properties are:
 
-- algo: Algorithm name (e.g. "sha1,rsa2048")
+- algo: Algorithm name (e.g. "sha1,rsa2048" or "sha256,ecdsa256")
 
 Optional properties are:
 
@@ -167,6 +167,11 @@ For RSA the following are mandatory:
 - rsa,r-squared: (2^num-bits)^2 as a big-endian multi-word integer
 - rsa,n0-inverse: -1 / modulus[0] mod 2^32
 
+For ECDSA the following are mandatory:
+- ecdsa,curve: Name of ECDSA curve (e.g. "prime256v1")
+- ecdsa,x-point: Public key X coordinate as a big-endian multi-word integer
+- ecdsa,y-point: Public key Y coordinate as a big-endian multi-word integer
+
 These parameters can be added to a binary device tree using parameter -K of the
 mkimage command::
 
-- 
2.26.2

[PATCH v6 05/11] test/py: Add pycryptodomex to list of required pakages

[Alexandru Gagniuc]

We wish to use pycryptodomex to verify code paths involving ECDSA
signatures. Add it to requirements.txt so that they get picked up
automatically .gitlab and .azure tasks

Signed-off-by: Alexandru Gagniuc 
Reviewed-by: Simon Glass 
---
 test/py/requirements.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/test/py/requirements.txt b/test/py/requirements.txt
index 926bccad69..9dea9415a7 100644
--- a/test/py/requirements.txt
+++ b/test/py/requirements.txt
@@ -10,6 +10,7 @@ packaging==19.2
 pbr==5.4.3
 pluggy==0.13.0
 py==1.8.0
+pycryptodomex==3.9.8
 pyelftools==0.27
 pygit2==1.4.0
 pyparsing==2.4.2
-- 
2.26.2

[PATCH v6 01/11] lib: Rename rsa-checksum.c to hash-checksum.c

[Alexandru Gagniuc]

rsa-checksum.c sontains the hash_calculate() implementations. Despite
the "rsa-" file prefix, this function is useful for other algorithms.

To prevent confusion, move this file to lib/, and rename it to
hash-checksum.c, to give it a more "generic" feel.

Signed-off-by: Alexandru Gagniuc 
Reviewed-by: Simon Glass 
---
 common/image-fit-sig.c | 2 +-
 common/image-sig.c | 2 +-
 include/image.h| 2 +-
 include/u-boot/{rsa-checksum.h => hash-checksum.h} | 0
 lib/Makefile   | 1 +
 lib/crypto/pkcs7_verify.c  | 2 +-
 lib/crypto/x509_public_key.c   | 2 +-
 lib/{rsa/rsa-checksum.c => hash-checksum.c}| 3 ++-
 lib/rsa/Makefile   | 2 +-
 tools/Makefile | 3 ++-
 10 files changed, 11 insertions(+), 8 deletions(-)
 rename include/u-boot/{rsa-checksum.h => hash-checksum.h} (100%)
 rename lib/{rsa/rsa-checksum.c => hash-checksum.c} (96%)

diff --git a/common/image-fit-sig.c b/common/image-fit-sig.c
index 34ebb8edfe..55ddf1879e 100644
--- a/common/image-fit-sig.c
+++ b/common/image-fit-sig.c
@@ -16,7 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #include 
 #include 
 #include 
-#include 
+#include 
 
 #define IMAGE_MAX_HASHED_NODES 100
 
diff --git a/common/image-sig.c b/common/image-sig.c
index 4abd3c080f..54f0eb2019 100644
--- a/common/image-sig.c
+++ b/common/image-sig.c
@@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #endif /* !USE_HOSTCC*/
 #include 
 #include 
-#include 
+#include 
 
 #define IMAGE_MAX_HASHED_NODES 100
 
diff --git a/include/image.h b/include/image.h
index d5a940313a..fbe9537c00 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1278,7 +1278,7 @@ struct image_region {
 };
 
 #if IMAGE_ENABLE_VERIFY
-# include 
+# include 
 #endif
 struct checksum_algo {
const char *name;
diff --git a/include/u-boot/rsa-checksum.h b/include/u-boot/hash-checksum.h
similarity index 100%
rename from include/u-boot/rsa-checksum.h
rename to include/u-boot/hash-checksum.h
diff --git a/lib/Makefile b/lib/Makefile
index edc1c3dd4f..1d4b7d3aad 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -60,6 +60,7 @@ endif
 obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi/
 obj-$(CONFIG_$(SPL_)MD5) += md5.o
 obj-$(CONFIG_$(SPL_)RSA) += rsa/
+obj-$(CONFIG_FIT_SIGNATURE) += hash-checksum.o
 obj-$(CONFIG_SHA1) += sha1.o
 obj-$(CONFIG_SHA256) += sha256.o
 obj-$(CONFIG_SHA512_ALGO) += sha512.o
diff --git a/lib/crypto/pkcs7_verify.c b/lib/crypto/pkcs7_verify.c
index 58683ef614..82c5c745d4 100644
--- a/lib/crypto/pkcs7_verify.c
+++ b/lib/crypto/pkcs7_verify.c
@@ -15,7 +15,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 #else
diff --git a/lib/crypto/x509_public_key.c b/lib/crypto/x509_public_key.c
index 91810a8640..d557ab27ae 100644
--- a/lib/crypto/x509_public_key.c
+++ b/lib/crypto/x509_public_key.c
@@ -19,7 +19,7 @@
 #include 
 #ifdef __UBOOT__
 #include 
-#include 
+#include 
 #else
 #include 
 #include 
diff --git a/lib/rsa/rsa-checksum.c b/lib/hash-checksum.c
similarity index 96%
rename from lib/rsa/rsa-checksum.c
rename to lib/hash-checksum.c
index e60debb7df..d732ecc38f 100644
--- a/lib/rsa/rsa-checksum.c
+++ b/lib/hash-checksum.c
@@ -13,7 +13,8 @@
 #else
 #include "fdt_host.h"
 #endif
-#include 
+#include 
+#include 
 
 int hash_calculate(const char *name,
const struct image_region region[],
diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile
index 8b75d41f04..c9ac72c1e2 100644
--- a/lib/rsa/Makefile
+++ b/lib/rsa/Makefile
@@ -5,6 +5,6 @@
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 
-obj-$(CONFIG_$(SPL_TPL_)RSA_VERIFY) += rsa-verify.o rsa-checksum.o
+obj-$(CONFIG_$(SPL_TPL_)RSA_VERIFY) += rsa-verify.o
 obj-$(CONFIG_$(SPL_TPL_)RSA_VERIFY_WITH_PKEY) += rsa-keyprop.o
 obj-$(CONFIG_RSA_SOFTWARE_EXP) += rsa-mod-exp.o
diff --git a/tools/Makefile b/tools/Makefile
index 2d550432ba..96316ed729 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -67,7 +67,7 @@ LIBFDT_OBJS := $(addprefix libfdt/, fdt.o fdt_ro.o fdt_wip.o 
fdt_sw.o fdt_rw.o \
fdt_strerror.o fdt_empty_tree.o fdt_addresses.o fdt_overlay.o)
 
 RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \
-   rsa-sign.o rsa-verify.o rsa-checksum.o \
+   rsa-sign.o rsa-verify.o \
rsa-mod-exp.o)
 
 AES_OBJS-$(CONFIG_FIT_CIPHER) := $(addprefix lib/aes/, \
@@ -106,6 +106,7 @@ dumpimage-mkimage-objs := aisimage.o \
socfpgaimage.o \
sunxi_egon.o \
lib/crc16.o \
+   lib/hash-checksum.o \
lib/sha1.o \
lib/sha256.o \
lib/sha512.o \
-- 
2.26.2

[PATCH v6 00/11] Add support for ECDSA image signing

[Alexandru Gagniuc]

## Purpose and intent

The purpose of this series is to enable ECDSA as an alternative to RSA
for FIT signing. As new chips have built-in support for ECDSA verified
boot, it makes sense to stick to one signing algorithm, instead of
resorting to RSA for u-boot images.

The focus of this series is signing an existing FIT image:

mkimage -F some-existing.fit -G some/key.pem

Signing while assembling a FIT is not a tested use case.
This concatenates two series:

  * Add support for ECDSA image signing (with test)
  * mkimage: Add a 'keyfile' argument for image signing


# Testing

test/py/tests/test_fit_ecdsa.py is implemented withe the goal to check
that the signing is done correctly, and that the signature is encoded
in the proper raw format. Verification is done with pyCryptodomex, so
this test will catch both coding errors and openssl bugs. This is the
only scope of testing proposed here.


Changes since v5:
 - Include "mkimage: Add a 'keyfile' argument for image signing" series
 - Update python test to use 'keyfile' (-G) mkinage argument
 - document which strings can be null in image.h
 - Fix typo in python test (invokations -> invocations)

Changes since v4:
 - Fixed tools/ build issue with # FIT_SIGNATURE is not selected

Changes since v3:
 - Don't use 'log_msg_ret()', as it's not available host-side

Changes since v1 and v2:
 - Added lots of function comments
 - Replaced hardcoded error numbers with more meaningful errno numbers
 - Changed some error paths to use 'return log_msg_ret'

Alexandru Gagniuc (11):
  lib: Rename rsa-checksum.c to hash-checksum.c
  lib/rsa: Make fdt_add_bignum() available outside of RSA code
  lib: Add support for ECDSA image signing
  doc: signature.txt: Document devicetree format for ECDSA keys
  test/py: Add pycryptodomex to list of required pakages
  test/py: ecdsa: Add test for mkimage ECDSA signing
  doc: signature.txt: Document the keydir and keyfile arguments
  mkimage: Add a 'keyfile' argument for image signing
  lib/rsa: Use the 'keyfile' argument from mkimage
  lib/ecdsa: Use the 'keydir' argument from mkimage if appropriate
  test/py: ecdsa: Use mkimage keyfile instead of keydir argument

 common/image-fit-sig.c|   2 +-
 common/image-sig.c|  13 +-
 doc/uImage.FIT/signature.txt  |  20 +-
 include/image.h   |  21 +-
 include/u-boot/ecdsa.h|  94 ++
 include/u-boot/fdt-libcrypto.h|  27 ++
 .../{rsa-checksum.h => hash-checksum.h}   |   0
 lib/Makefile  |   1 +
 lib/crypto/pkcs7_verify.c |   2 +-
 lib/crypto/x509_public_key.c  |   2 +-
 lib/ecdsa/ecdsa-libcrypto.c   | 318 ++
 lib/fdt-libcrypto.c   |  72 
 lib/{rsa/rsa-checksum.c => hash-checksum.c}   |   3 +-
 lib/rsa/Makefile  |   2 +-
 lib/rsa/rsa-sign.c|  99 ++
 test/py/requirements.txt  |   1 +
 test/py/tests/test_fit_ecdsa.py   | 111 ++
 tools/Makefile|  11 +-
 tools/fit_image.c |   3 +-
 tools/image-host.c|  58 ++--
 tools/imagetool.h |   1 +
 tools/mkimage.c   |   6 +-
 22 files changed, 752 insertions(+), 115 deletions(-)
 create mode 100644 include/u-boot/ecdsa.h
 create mode 100644 include/u-boot/fdt-libcrypto.h
 rename include/u-boot/{rsa-checksum.h => hash-checksum.h} (100%)
 create mode 100644 lib/ecdsa/ecdsa-libcrypto.c
 create mode 100644 lib/fdt-libcrypto.c
 rename lib/{rsa/rsa-checksum.c => hash-checksum.c} (96%)
 create mode 100644 test/py/tests/test_fit_ecdsa.py

-- 
2.26.2

Frustrations of running testing

[Alex G.]

Hi,

I keep being hit by two frustrating issues when trying to run tests. My 
expectation is that I can run a test at any time when working on 
something -- usually to check the correctness of that something. That's 
not the case today.



The first one is an error message about mrproper:

$ ./test/py/test.py --bd sandbox_spl
.. is not clean, please run 'make mrproper'

I don't think this message is very useful. Running 'mrproper' is out of 
the question, as it would wipe out the branch I'm currently working on. 
So what I end up doing is deleting the mrimproper check from the 
Makefile. And while it's a fast workaround, it dirties the tree and gets 
in the way of rebasing patches or working with git.


I can continue just fine without 'mrproper death' so I really don't 
understand the over-abundance of caution in breaking the build.




The second issue is the how the tests are trying to build graphics:

$ ./test/py/test.py --bd sandbox_spl -k "whatever"
make[1]: sdl2-config: Command not found
../arch/sandbox/cpu/sdl.c:10:10: fatal error: SDL2/SDL.h:
No such file or directory
   10 | #include 

The solution is to set NO_SDL=1, but this is far from obvious. The first 
instinct is always to look up the command help:


$ ./test/py/test.py --help

But this really isn't at all useful. A simple grep for sdl2-config also 
doesn't immediately reveal the solution. Most u-boot tools get their 
arguments via the commandline. Thus, a reasonably competent u-boot 
developer will not think that environment variables are the solution. 
Ergo, environment variables are not the ideal way to solve this.


Maybe we could have a commandline option, and at the very least, catch 
this error and print something useful on the console.



I'm not sure what the preferred way would be to solve the above. For me, 
these issues cause a significant enough disruption to my workflow, that 
I am very likely to not run tests regularly. I suspect I'm not alone.


Alex

[PATCH 2/2] efi: ESRT creation tests

[Jose Marinho]

This commmit exercises the ESRT creation -- introduced in the previous
commit -- in two tests.

test 1:
 A fake FMP, with TEST_ESRT_NUM_ENTRIES FW images, is installed in the
 system leading to the corresponding ESRT entries being populated.
 The ESRT entries are checked against the datastructure used to
 initialize the FMP.

test 1 invocation:
 make sandbox_capsule_defconfig all
 ./u-boot -d arch/sandbox/dts/test.dtb
 ut lib

test 2:
 The test is part of test_efi_capsule_fw3.

 In order to run the test the following must be added to
 sandbox_defconfig:
  +CONFIG_CMD_SF=y
  +CONFIG_CMD_MEMORY=y
  +CONFIG_CMD_FAT=y
  +CONFIG_DFU=y

 The ESRT is printed in the u-boot shell by calling efidebug esrt.
 The test ensures that, after the capsule is installed, the  ESRT
 contains entries with the GUIDs:
  - EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID;
  - EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID;

test 2 invocation:
 sudo ./test/py/test.py --bd sandbox -k capsule_fw3 -l --build

Signed-off-by: Jose Marinho 

CC: Heinrich Schuchardt 
CC: Sughosh Ganu 
CC: AKASHI Takahiro 
CC: Ilias Apalodimas 
CC: Andre Przywara 
CC: Alexander Graf 
CC: n...@arm.com

---
 cmd/efidebug.c|  64 ++
 test/lib/Makefile |   1 +
 test/lib/efi_esrt.c   | 191 ++
 .../test_efi_capsule/test_capsule_firmware.py |   4 +
 4 files changed, 260 insertions(+)
 create mode 100644 test/lib/efi_esrt.c

diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index a7dace2f80..5a9ff2bd9a 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -129,6 +129,61 @@ static int do_efi_capsule_show(struct cmd_tbl *cmdtp, int 
flag,
return CMD_RET_SUCCESS;
 }
 
+#ifdef CONFIG_EFI_ESRT
+/**
+ * do_efi_capsule_esrt() - manage UEFI capsules
+ *
+ * @cmdtp: Command table
+ * @flag:  Command flag
+ * @argc:  Number of arguments
+ * @argv:  Argument array
+ * Return: CMD_RET_SUCCESS on success,
+ * CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "capsule esrt" sub-command.
+ * The prints the current ESRT table.
+ *
+ * efidebug capsule esrt
+ */
+static int do_efi_capsule_esrt(struct cmd_tbl *cmdtp, int flag,
+  int argc, char * const argv[])
+{
+   struct efi_system_resource_table *esrt = NULL;
+
+   if (argc != 1)
+   return CMD_RET_USAGE;
+
+   for (int idx = 0; idx < systab.nr_tables; idx++)
+   if (!guidcmp(_esrt_guid, [idx].guid))
+   esrt = (struct efi_system_resource_table 
*)systab.tables[idx].table;
+
+   if (!esrt)
+   return CMD_RET_FAILURE;
+
+   printf("\n");
+   printf("ESRT: fw_resource_count=%d\n", esrt->fw_resource_count);
+   printf("ESRT: fw_resource_count_max=%d\n", esrt->fw_resource_count_max);
+   printf("ESRT: fw_resource_version=%lld\n", esrt->fw_resource_version);
+
+   for (int idx = 0; idx < esrt->fw_resource_count; idx++) {
+   printf("[entry %d]==\n", idx);
+   printf("ESRT: fw_class=%pUL\n", >entries[idx].fw_class);
+   printf("ESRT: fw_type=%d\n", esrt->entries[idx].fw_type);
+   printf("ESRT: fw_version=%d\n", esrt->entries[idx].fw_version);
+   printf("ESRT: lowest_supported_fw_version=%d\n",
+  esrt->entries[idx].lowest_supported_fw_version);
+   printf("ESRT: capsule_flags=%d\n",
+  esrt->entries[idx].capsule_flags);
+   printf("ESRT: last_attempt_version=%d\n",
+  esrt->entries[idx].last_attempt_version);
+   printf("ESRT: last_attempt_status=%d\n",
+  esrt->entries[idx].last_attempt_status);
+   }
+   printf("\n");
+
+   return CMD_RET_SUCCESS;
+}
+#endif /*  CONFIG_EFI_ESRT */
 /**
  * do_efi_capsule_res() - show a capsule update result
  *
@@ -221,6 +276,10 @@ static struct cmd_tbl cmd_efidebug_capsule_sub[] = {
 "", ""),
U_BOOT_CMD_MKENT(show, CONFIG_SYS_MAXARGS, 1, do_efi_capsule_show,
 "", ""),
+#ifdef CONFIG_EFI_ESRT
+   U_BOOT_CMD_MKENT(esrt, CONFIG_SYS_MAXARGS, 1, do_efi_capsule_esrt,
+"", ""),
+#endif
U_BOOT_CMD_MKENT(disk-update, 0, 0, do_efi_capsule_on_disk_update,
 "", ""),
U_BOOT_CMD_MKENT(result, CONFIG_SYS_MAXARGS, 1, do_efi_capsule_res,
@@ -256,6 +315,7 @@ static int do_efi_capsule(struct cmd_tbl *cmdtp, int flag,
 
return cp->cmd(cmdtp, flag, argc, argv);
 }
+
 #endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT */
 
 /**
@@ -1580,6 +1640,10 @@ static char efidebug_help_text[] =
"  - show capsule information\n"
"efidebug capsule result []\n"
"  - show a capsule update result\n"
+#ifdef CONFIG_EFI_ESRT
+   

[PATCH 1/2] efi: Add ESRT to the EFI system table

[Jose Marinho]

The ESRT is initialised during efi_init_objlist after
efi_initialize_system_table().

The ESRT is initially created with size for 50 FW image entries.
The ESRT is resized when it runs out of space. Every resize adds 50
additional entries.
The ESRT is populated from information provided by FMP instances only.

Signed-off-by: Jose Marinho 

CC: Heinrich Schuchardt 
CC: Sughosh Ganu 
CC: AKASHI Takahiro 
CC: Ilias Apalodimas 
CC: Andre Przywara 
CC: Alexander Graf 
CC: n...@arm.com

---
 cmd/efidebug.c   |   4 +
 include/efi_api.h|  21 ++
 include/efi_loader.h |  20 ++
 lib/efi_loader/Kconfig   |   7 +
 lib/efi_loader/Makefile  |   1 +
 lib/efi_loader/efi_capsule.c |   8 +
 lib/efi_loader/efi_esrt.c| 522 +++
 lib/efi_loader/efi_setup.c   |   6 +
 8 files changed, 589 insertions(+)
 create mode 100644 lib/efi_loader/efi_esrt.c

diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index bbbcb0a546..a7dace2f80 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -459,6 +459,10 @@ static const struct {
"Block IO",
EFI_BLOCK_IO_PROTOCOL_GUID,
},
+   {
+   "EFI System Resource Table",
+   EFI_SYSTEM_RESOURCE_TABLE_GUID,
+   },
{
"Simple File System",
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID,
diff --git a/include/efi_api.h b/include/efi_api.h
index 48e48a6263..fb53637419 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -1722,6 +1722,23 @@ struct efi_load_file_protocol {
 void *buffer);
 };
 
+struct efi_system_resource_entry {
+   efi_guid_t fw_class;
+   u32 fw_type;
+   u32 fw_version;
+   u32 lowest_supported_fw_version;
+   u32 capsule_flags;
+   u32 last_attempt_version;
+   u32 last_attempt_status;
+} __packed;
+
+struct efi_system_resource_table {
+   u32 fw_resource_count;
+   u32 fw_resource_count_max;
+   u64 fw_resource_version;
+   struct efi_system_resource_entry entries[];
+} __packed;
+
 /* Boot manager load options */
 #define LOAD_OPTION_ACTIVE 0x0001
 #define LOAD_OPTION_FORCE_RECONNECT0x0002
@@ -1740,6 +1757,10 @@ struct efi_load_file_protocol {
 #define ESRT_FW_TYPE_DEVICEFIRMWARE0x0002
 #define ESRT_FW_TYPE_UEFIDRIVER0x0003
 
+#define EFI_SYSTEM_RESOURCE_TABLE_GUID\
+   EFI_GUID(0xb122a263, 0x3661, 0x4f68,\
+   0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80)
+
 /* Last Attempt Status Values */
 #define LAST_ATTEMPT_STATUS_SUCCESS0x
 #define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL 0x0001
diff --git a/include/efi_loader.h b/include/efi_loader.h
index f470bbd636..c2720f2823 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -214,6 +214,8 @@ extern const efi_guid_t efi_guid_rng_protocol;
 extern const efi_guid_t efi_guid_capsule_report;
 /* GUID of firmware management protocol */
 extern const efi_guid_t efi_guid_firmware_management_protocol;
+/* GUID for the ESRT */
+extern const efi_guid_t efi_esrt_guid;
 
 extern unsigned int __efi_runtime_start, __efi_runtime_stop;
 extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
@@ -884,4 +886,22 @@ static inline efi_status_t efi_launch_capsules(void)
 
 #endif /* CONFIG_IS_ENABLED(EFI_LOADER) */
 
+/**
+ * Install the ESRT system table.
+ *
+ * @return status code
+ */
+efi_status_t efi_esrt_register(void);
+
+/**
+ * efi_esrt_populate() - Populates the ESRT entries from the FMP instances
+ * present in the system.
+ * If an ESRT already exists, the old ESRT is replaced in the system table.
+ * The memory of the old ESRT is deallocated.
+ *
+ * Return:
+ * - EFI_SUCCESS if the ESRT is correctly created
+ * - error code otherwise.
+ */
+efi_status_t efi_esrt_populate(void);
 #endif /* _EFI_LOADER_H */
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index e729f727df..a96014ce18 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -347,4 +347,11 @@ config EFI_SECURE_BOOT
  it is signed with a trusted key. To do that, you need to install,
  at least, PK, KEK and db.
 
+config EFI_ESRT
+   bool "Enable the UEFI ESRT generation"
+   depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT
+   default y
+   help
+ Enabling this option creates the ESRT UEFI system table.
+
 endif
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 10b42e8847..9a8127846f 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -52,6 +52,7 @@ obj-y += efi_variable.o
 obj-$(CONFIG_EFI_VARIABLES_PRESEED) += efi_var_seed.o
 endif
 obj-y += efi_watchdog.o
+obj-$(CONFIG_EFI_ESRT) += efi_esrt.o
 obj-$(CONFIG_LCD) += efi_gop.o
 obj-$(CONFIG_DM_VIDEO) += efi_gop.o
 obj-$(CONFIG_PARTITIONS) += efi_disk.o
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index b57f0302c5..a1a69e619d 

[PATCHv2 0/2] Add ESRT and test ESRT creation

[Jose Marinho]

The following 2 commits add the ESRT and provide a test of the
functionality.

The first commit adds the ESRT as defined in the UEFI 2.8 specification.
An empty ESRT is created during the execution of the efi_init_obj_list().
The ESRT is updated when:
  1) a FMP protocol is installed in the system: this will add the
corresponding entries to the ESRT.
  2) a capsule is installed via UpdateCapsule: this should update
entries already present in the ESRT.

This implementation of the ESRT creation takes input from FMP only.
It is assumed that the FMP will maintain the following values across
reboot:
 - LastAttemptVersion.
 - LastAttemptStatus.


The second commit enables testing the ESRT creation in the sandbox
platform. That commit is composed of 2 tests.
- Test 1 executes from the u-boot shell with "ut lib".
- Test 2 executes in the pytest environment.


Patch v2:
- The ESRT is now regenerated from scratch at every FMP EVT_NOTIFY_SIGNAL
  and whenever a capsule is updated.
- Extended TestEfiCapsuleFirmwareFit::test_efi_capsule_fw3 to verify
  that the ESRT is correctly populated after an UpdateCapsule.
- Addressed v1 comments.

Patch v1:
- reworked the ESRT creation code, allowing table to resize as
FMPs are installed.
- registered a callback for the FMP protocol install.
- Created a unit test running on the sandbox platform.

rfc: initial patch submission

CC: Heinrich Schuchardt 
CC: Sughosh Ganu 
CC: AKASHI Takahiro 
CC: Ilias Apalodimas 
CC: Andre Przywara 
CC: Alexander Graf 
CC: n...@arm.com

Jose Marinho (2):
  efi: Add ESRT to the EFI system table
  efi: ESRT cration unit test

 cmd/efidebug.c|   4 +
 include/efi_api.h |  21 ++
 include/efi_loader.h  |  19 ++
 lib/efi_loader/Kconfig|   7 +
 lib/efi_loader/Makefile   |   1 +
 lib/efi_loader/efi_boottime.c |   2 -
 lib/efi_loader/efi_capsule.c  |   7 +
 lib/efi_loader/efi_esrt.c | 439 ++
 lib/efi_loader/efi_setup.c|   6 +
 test/lib/Makefile |   1 +
 test/lib/efi_esrt.c   | 188 +++
 11 files changed, 693 insertions(+), 2 deletions(-)
 create mode 100644 lib/efi_loader/efi_esrt.c
 create mode 100644 test/lib/efi_esrt.c

-- 
2.17.1

Re: [PATCH] sunxi: board: Splitting CHIP defconfig for nand.

[André Przywara]

On 24/01/2021 16:19, Alexandre GRIVEAUX wrote:

Hi Alexandre,

(CCing: Kory, plus using Maxime's and Boris' newer emails)

> This patch split CHIP defconfig to add nand 4G and 8G support.
> 
> Some CONFIG was put at the end of defconfig to ease comparison between:
> - CHIP Pro
> - CHIP with Toshiba 4G
> - CHIP with Hynix 8G
> 
> Witch are essentialy the same board with differents nand and memory.
> 
> Values was taken from now defunct compagny script "chip-update-firmware.sh"

Mmh, I am puzzled how this is supposed to work? I thought that the NAND
in the non-Pro version was not supported (MLC?). So booting via USB was
the only option?
Has this changed?

Can someone confirm that this works?

Cheers,
Andre

> Signed-off-by: Alexandre GRIVEAUX 
> ---
>  ...CHIP_defconfig => CHIP_Hynix_8G_defconfig} | 21 +---
>  configs/CHIP_Toshiba_4G_defconfig | 32 +++
>  2 files changed, 49 insertions(+), 4 deletions(-)
>  rename configs/{CHIP_defconfig => CHIP_Hynix_8G_defconfig} (50%)
>  create mode 100644 configs/CHIP_Toshiba_4G_defconfig
> 
> diff --git a/configs/CHIP_defconfig b/configs/CHIP_Hynix_8G_defconfig
> similarity index 50%
> rename from configs/CHIP_defconfig
> rename to configs/CHIP_Hynix_8G_defconfig
> index a70ee31d40..4d04a2798e 100644
> --- a/configs/CHIP_defconfig
> +++ b/configs/CHIP_Hynix_8G_defconfig
> @@ -4,16 +4,29 @@ CONFIG_SPL=y
>  CONFIG_MACH_SUN5I=y
>  CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
>  CONFIG_USB0_VBUS_PIN="PB10"
> -CONFIG_VIDEO_COMPOSITE=y
>  CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
>  CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_CMD_DFU=y
> -CONFIG_CMD_USB_MASS_STORAGE=y
> -CONFIG_DFU_RAM=y
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_MTDPARTS=y
> +CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0"
> +CONFIG_MTDPARTS_DEFAULT="mtdparts=sunxi-nand.0:256k(spl),256k(spl-backup),2m(uboot),2m(uboot-backup),-(UBI)"
> +CONFIG_ENV_IS_IN_UBI=y
> +CONFIG_ENV_UBI_PART="UBI"
> +CONFIG_ENV_UBI_VOLUME="uboot-env"
>  # CONFIG_MMC is not set
> +CONFIG_MTD=y
> +CONFIG_MTD_RAW_NAND=y
> +CONFIG_SYS_NAND_BLOCK_SIZE=0x40
> +CONFIG_SYS_NAND_PAGE_SIZE=0x4000
> +CONFIG_SYS_NAND_OOBSIZE=0x680
>  CONFIG_AXP_ALDO3_VOLT=3300
>  CONFIG_AXP_ALDO4_VOLT=3300
>  CONFIG_CONS_INDEX=2
>  CONFIG_USB_EHCI_HCD=y
>  CONFIG_USB_OHCI_HCD=y
>  CONFIG_USB_MUSB_GADGET=y
> +CONFIG_USB_FUNCTION_MASS_STORAGE=y
> +CONFIG_VIDEO_COMPOSITE=y
> +CONFIG_CMD_DFU=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_DFU_RAM=y
> diff --git a/configs/CHIP_Toshiba_4G_defconfig 
> b/configs/CHIP_Toshiba_4G_defconfig
> new file mode 100644
> index 00..bbc6cd9744
> --- /dev/null
> +++ b/configs/CHIP_Toshiba_4G_defconfig
> @@ -0,0 +1,32 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_SUNXI=y
> +CONFIG_SPL=y
> +CONFIG_MACH_SUN5I=y
> +CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
> +CONFIG_USB0_VBUS_PIN="PB10"
> +CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
> +CONFIG_SPL_I2C_SUPPORT=y
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_MTDPARTS=y
> +CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0"
> +CONFIG_MTDPARTS_DEFAULT="mtdparts=sunxi-nand.0:256k(spl),256k(spl-backup),2m(uboot),2m(uboot-backup),-(UBI)"
> +CONFIG_ENV_IS_IN_UBI=y
> +CONFIG_ENV_UBI_PART="UBI"
> +CONFIG_ENV_UBI_VOLUME="uboot-env"
> +# CONFIG_MMC is not set
> +CONFIG_MTD=y
> +CONFIG_MTD_RAW_NAND=y
> +CONFIG_SYS_NAND_BLOCK_SIZE=0x40
> +CONFIG_SYS_NAND_PAGE_SIZE=0x4000
> +CONFIG_SYS_NAND_OOBSIZE=0x500
> +CONFIG_AXP_ALDO3_VOLT=3300
> +CONFIG_AXP_ALDO4_VOLT=3300
> +CONFIG_CONS_INDEX=2
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_OHCI_HCD=y
> +CONFIG_USB_MUSB_GADGET=y
> +CONFIG_USB_FUNCTION_MASS_STORAGE=y
> +CONFIG_VIDEO_COMPOSITE=y
> +CONFIG_CMD_DFU=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_DFU_RAM=y
> 

Re: [PATCH 08/10] sun5i: add support for DIP detection to CHIP board

[Andre Przywara]

On Fri, 19 Feb 2021 11:54:54 -0500
Tom Rini  wrote:

Hi,

> On Thu, Feb 18, 2021 at 02:29:36PM +0100, Kory Maincent wrote:
> 
> > Add the extension_board_scan specific function to scan the information
> > of the EEPROM on one-wire and fill the extension struct.
> > 
> > Signed-off-by: Kory Maincent 
> > ---
> >  arch/arm/mach-sunxi/Kconfig |   2 +
> >  board/sunxi/Makefile|   1 +
> >  board/sunxi/chip.c  | 104 
> >  3 files changed, 107 insertions(+)
> >  create mode 100644 board/sunxi/chip.c
> > 
> > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> > index 37a4294d88..3bb8a08b34 100644
> > --- a/arch/arm/mach-sunxi/Kconfig
> > +++ b/arch/arm/mach-sunxi/Kconfig
> > @@ -6,10 +6,12 @@ choice
> >  
> >  config TARGET_CHIP
> > bool "CHIP board"
> > +   select SUPPORT_EXTENSION_SCAN
> > select W1
> > select W1_GPIO
> > select W1_EEPROM
> > select W1_EEPROM_DS24XXX
> > +   imply CMD_EXTENSION  
> 
> And then based on my comment in the previous patch, similar to
> PINEPHONE_DT_SELECTION and other board-specific options, add a
> CHIP_DIP_SCAN option or similar.

Yes, indeed, thanks Tom.

The idea of making this extension scheme generic is great, it's just
that sunxi is using a different approach to board specific code here.
Normally we expect U-Boot-proper board specific code to be DT driven,
and where this does not really work, use those symbols that Tom pointed
to.

Thanks,
Andre

Re: [PATCH u-boot-marvell 0/5] pci_mvebu changes

[Marek Behún]

And also pinging this series, since we had our answer from Thomas
Petazzoni :)

Re: [PATCH u-boot-marvell 1/4] rtc: add armada38x driver

[Marek Behún]

Just pinging this series :)

Re: [PATCH v4 8/8] spl: fit: Load devicetree when a Linux payload is found

[Tom Rini]

On Wed, Jan 20, 2021 at 10:46:56AM -0600, Alexandru Gagniuc wrote:

> When a FIT config specifies a devicetree, we should load it, no
> questions asked. In the case of the "simple" FIT loading path, a
> difficulty arises in selecting the load address of the FDT.
> 
> The default FDT location is right after the "kernel" or "firmware"
> image. However, if that is an OP-TEE image, then the FDT may end up in
> secure DRAM, and not be accessible to normal world kernels.
> 
> Although the best solution is to be more careful about the FDT
> address, a viable workaround is to only append the FDT after a u-boot
> or Linux image. This is identical to the previous logic, except that
> FDT loading is extended to IH_OS_LINUX images.
> 
> Signed-off-by: Alexandru Gagniuc 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v4 7/8] spl: fit: Replace #ifdef blocks with more readable constructs

[Tom Rini]

On Wed, Jan 20, 2021 at 10:46:55AM -0600, Alexandru Gagniuc wrote:

> Use the IS_ENABLED() macro to control code flow, instead of the
> caveman approach of sprinkling #ifdefs. Code size is not affected, as
> the linker garbage-collects unused functions. However, readability is
> improved significantly.
> 
> Signed-off-by: Alexandru Gagniuc 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v4 6/8] image: Do not #if guard board_fit_image_post_process() prototype

[Tom Rini]

On Wed, Jan 20, 2021 at 10:46:54AM -0600, Alexandru Gagniuc wrote:

> There's no point in guarding function prototypes with #ifdefs. If a
> function is not defined, the linker will notice. Having the prototype
> does not affect code size.
> 
> What the #if guard takes away is the ability to use IS_ENABLED:
> 
>   if (CONFIG_IS ENABLED(FIT_IMAGE_POST_PROCESS))
>   board_fit_image_post_process(...)
> 
> When the prototype is guarded, the above form cannot be used. This
> leads to the proliferation of #ifdefs, and unreadable code. The
> opportunity cost of the #if guard outweighs any benefits. Remove it.
> 
> Since the original version of this patch, an empty definition was
> added by commit f14e6eec6c7f ("image: cleanup pre-processor usage").
> The empty definition can cause silent failures, when an implementation
> of board_fit_image_post_process() is expected because the linker will
> not catch the missing function. Thus this patch removes this empty
> inline declaration.
> 
> Fixes: f14e6eec6c7f ("image: cleanup pre-processor usage")
> Signed-off-by: Alexandru Gagniuc 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v4 5/8] spl: fit: Only look up FIT configuration node once

[Tom Rini]

On Wed, Jan 20, 2021 at 10:46:53AM -0600, Alexandru Gagniuc wrote:

> The configuration node a sub node under "/configurations", which
> describes the components to load from "/images". We only need to
> locate this node once.
> 
> However, for each component, spl_fit_get_image_name() would parse the
> FIT image, looking for the correct node. Such work duplication is not
> necessary. Instead, once the node is found, cache it, and re-use it.
> 
> Signed-off-by: Alexandru Gagniuc 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v4 4/8] spl: fit: Remove useless loop in spl_fit_get_image_name()

[Tom Rini]

On Wed, Jan 20, 2021 at 10:46:52AM -0600, Alexandru Gagniuc wrote:

> When a desired configuration is not found, conf_node will have a
> negative value. Thus the for loop will start at the root "/" node of
> the image, print the "/description" property, and stop.
> 
> It appears the intent of the loop was to print the names of the
> subnodes under "/configurations". We would need the offset to the
> "/configurations" node, which is abstracted by fit_find_config_node().
> 
> This change agrees that abstracting the node offset is the correct
> design, and we shouldn't be parsing the configurations manually. Thus
> the loop in spl_fit_get_image_name() is useless. Remove it.
> 
> Signed-off-by: Alexandru Gagniuc 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v4 3/8] spl: fit: Pass FIT context via a structure pointer

[Tom Rini]

On Wed, Jan 20, 2021 at 10:46:51AM -0600, Alexandru Gagniuc wrote:

> Several loose arguments describe the FIT image. They are thus related,
> and it makes sense to pass them together, in a structure. Examples
> include the FIT blob pointer, offset to FDT nodes, and the offset to
> external data.
> 
> Use a spl_fit_info structure to group these parameters.
> 
> Signed-off-by: Alexandru Gagniuc 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v4 2/8] spl: fit: Factor out FIT parsing and use a context struct

[Tom Rini]

On Wed, Jan 20, 2021 at 10:46:50AM -0600, Alexandru Gagniuc wrote:

> The logical steps in spl_load_simple_fit() are difficult to follow.
> I think the long comments, ifdefs, and ungodly number of variables
> seriously affect the readability. In particular, it violates section 6
> of the coding style, paragraphs (3), and (4).
> 
> The purpose of this patch is to improve the situation by
>   - Factoring out initialization and parsing to separate functions
>   - Reduce the number of variables by using a context structure
> This change introduces no functional changes.
> 
> Signed-off-by: Alexandru Gagniuc 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH 10/10] am335x: add support for cape detect functionality

[Tom Rini]

On Thu, Feb 18, 2021 at 02:29:38PM +0100, Kory Maincent wrote:

> Update the Kconfig and the board file to make the am335x board compatible
> with cape detection.
> 
> Signed-off-by: Kory Maincent 
> ---
>  arch/arm/mach-omap2/am33xx/Kconfig | 1 +
>  board/ti/am335x/board.c| 1 +
>  include/configs/am335x_evm.h   | 2 ++
>  3 files changed, 4 insertions(+)
[snip]
> +#define CONFIG_CAPE_EEPROM_BUS_NUM   2

You can't add new CONFIG options like that outside of Kconfig.

-- 
Tom


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Re: [PATCH v4 1/8] spl: fit: Drop 'length' argument to board_spl_fit_post_load()

[Tom Rini]

On Wed, Jan 20, 2021 at 10:46:49AM -0600, Alexandru Gagniuc wrote:

> The size is derived from the FIT image itself. Any alignment
> requirements are machine-specific and known by the board code. Thus
> the total length can be derived from the FIT image and knowledge of
> the platform. The 'length' argument is redundant. Remove it.
> 
> Signed-off-by: Alexandru Gagniuc 
> Reviewed-by: Peng Fan 
> Reviewed-by: Simon Glass 
> CC: Matt Porter 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH 08/10] sun5i: add support for DIP detection to CHIP board

[Tom Rini]

On Thu, Feb 18, 2021 at 02:29:36PM +0100, Kory Maincent wrote:

> Add the extension_board_scan specific function to scan the information
> of the EEPROM on one-wire and fill the extension struct.
> 
> Signed-off-by: Kory Maincent 
> ---
>  arch/arm/mach-sunxi/Kconfig |   2 +
>  board/sunxi/Makefile|   1 +
>  board/sunxi/chip.c  | 104 
>  3 files changed, 107 insertions(+)
>  create mode 100644 board/sunxi/chip.c
> 
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 37a4294d88..3bb8a08b34 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -6,10 +6,12 @@ choice
>  
>  config TARGET_CHIP
>   bool "CHIP board"
> + select SUPPORT_EXTENSION_SCAN
>   select W1
>   select W1_GPIO
>   select W1_EEPROM
>   select W1_EEPROM_DS24XXX
> + imply CMD_EXTENSION

And then based on my comment in the previous patch, similar to
PINEPHONE_DT_SELECTION and other board-specific options, add a
CHIP_DIP_SCAN option or similar.

-- 
Tom


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Re: [PATCH 07/10] arm: mach-sunxi: add CHIP board target

[Tom Rini]

On Thu, Feb 18, 2021 at 02:29:35PM +0100, Kory Maincent wrote:
> The CHIP board use one-wire EEPROM to discover and identify extension
> boards (called "DIPs").
> 
> This commit add the configuration for the CHIP board target to enable the
> EEPROM one-wire driver.
> 
> Signed-off-by: Kory Maincent 
> ---
> 
> Need the following patches series to fix a one-wire gpio issue.
> https://lists.denx.de/pipermail/u-boot/2021-February/440073.html
> 
>  arch/arm/mach-sunxi/Kconfig | 14 ++
>  configs/CHIP_defconfig  |  1 +
>  2 files changed, 15 insertions(+)
> 
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 49ef217f08..37a4294d88 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -1,5 +1,19 @@
>  if ARCH_SUNXI
>  
> +choice
> + prompt "Sunxi board select"
> + optional
> +
> +config TARGET_CHIP
> + bool "CHIP board"
> + select W1
> + select W1_GPIO
> + select W1_EEPROM
> + select W1_EEPROM_DS24XXX
> +
> +endchoice
> +
> +
>  config SPL_LDSCRIPT
>   default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
>  
> diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
> index a70ee31d40..6810797b19 100644
> --- a/configs/CHIP_defconfig
> +++ b/configs/CHIP_defconfig
> @@ -1,6 +1,7 @@
>  CONFIG_ARM=y
>  CONFIG_ARCH_SUNXI=y
>  CONFIG_SPL=y
> +CONFIG_TARGET_CHIP=y
>  CONFIG_MACH_SUN5I=y
>  CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
>  CONFIG_USB0_VBUS_PIN="PB10"

I think you should really just be adding options to the defconfig
directly, sunxi has been avoiding adding TARGET_xxx options.

-- 
Tom


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Re: [PATCH 06/10] arm: dts: sun5i: enable one-wire on the CHIP

[Tom Rini]

On Thu, Feb 18, 2021 at 02:29:34PM +0100, Kory Maincent wrote:
> Add the EEPROM description in the devicetree for the CHIP board.
> 
> Signed-off-by: Kory Maincent 
> ---
>  arch/arm/dts/sun5i-r8-chip.dts | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm/dts/sun5i-r8-chip.dts b/arch/arm/dts/sun5i-r8-chip.dts
> index 879a4b0f3b..d915eb3eb7 100644
> --- a/arch/arm/dts/sun5i-r8-chip.dts
> +++ b/arch/arm/dts/sun5i-r8-chip.dts
> @@ -89,6 +89,12 @@
>   gpios = < 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
>   pinctrl-names = "default";
>   pinctrl-0 = <_w1_pin>;
> +
> + w1_eeprom: w1_eeprom@0 {
> + compatible = "maxim,ds2431";
> + status = "okay";
> + };
> +
>   };
>  };

This should be in, or re-synced from, the Linux dts file.

-- 
Tom


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Re: [PATCH 02/10] cmd: add support for a new "extension" command

[Tom Rini]

On Thu, Feb 18, 2021 at 02:29:30PM +0100, Kory Maincent wrote:

> This patch adds a new "extension" command, which aims at detecting
> extension boards connected to the hardware platform, and apply the
> Device Tree overlays that describe the hardware present on those
> extension boards.
> 
> In order to enable this mechanism, board-specific code must implement
> the extension_board_scan() function that fills in a linked list of
> "struct extension", each describing one extension board. In addition,
> the board-specific code must select the SUPPORT_EXTENSION_SCAN Kconfig
> boolean.
[snip]
>  doc/README.extension  |  80 ++

This should be rST and under docs/ somewhere.

[snip]
> + puts(
> + "No FDT memory address configured. Please configure\n"
> + "the FDT address via \"fdt addr \" 
> command.\n");

This should be a printf() and line-formatted correctly so checkpatch.pl
doesn't complain.  Thanks!

-- 
Tom


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Re: [PATCH 01/10] fdt_support: move fdt_valid from cmd_fdt.c to fdt_support.c

[Tom Rini]

On Thu, Feb 18, 2021 at 02:29:29PM +0100, Kory Maincent wrote:

> Move the fdt_valid function to fdt_support.
> This changes allow to be able to test the validity of a devicetree in
> other c files.
> 
> Update code syntax.
> 
> Signed-off-by: Kory Maincent 

Reviewed-by: Tom Rini 

-- 
Tom


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Re: [PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Stefan Roese]

Hi Marek,

On 19.02.21 17:13, Marek Behún wrote:

On Fri, 19 Feb 2021 08:38:48 +0100
Stefan Roese  wrote:


Hi Marek,

On 18.02.21 20:56, Marek Behun wrote:

Chris put his Tested-by on this series and noone else replyied to
it. What do you think about this?


How about the issue of size increase in the SPL? IIRC, then one patch
resulted in a too big image for one of the MVEBU boards.


The only thing that may be problematic is that this series does not
preserve original commit authors (the ones who authored these
commitsin mv-ddr) in the From header, only in the first
Signed-off-by's. It's because I forgot to add correct From: tags.

Shall I fix this and resend it?


Yes, please do. This will help me a bit.

Thanks,
Stefan


I have sent v2 with From headers now containing original authors.


Thanks.


As for SPL, I have just tested these for all A38x boards, the results
are in the cover letter. In short for those boards where SPL is too
big, it is too big even before this series.


Okay. I'll queue this patchset for the upcoming merge window, or will
commit into next soon.

Thanks,
Stefan

Re: [PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Marek Behún]

On Fri, 19 Feb 2021 08:38:48 +0100
Stefan Roese  wrote:

> Hi Marek,
> 
> On 18.02.21 20:56, Marek Behun wrote:
> > Chris put his Tested-by on this series and noone else replyied to
> > it. What do you think about this?  
> 
> How about the issue of size increase in the SPL? IIRC, then one patch
> resulted in a too big image for one of the MVEBU boards.
> 
> > The only thing that may be problematic is that this series does not
> > preserve original commit authors (the ones who authored these
> > commitsin mv-ddr) in the From header, only in the first
> > Signed-off-by's. It's because I forgot to add correct From: tags.
> > 
> > Shall I fix this and resend it?  
> 
> Yes, please do. This will help me a bit.
> 
> Thanks,
> Stefan

I have sent v2 with From headers now containing original authors.

As for SPL, I have just tested these for all A38x boards, the results
are in the cover letter. In short for those boards where SPL is too
big, it is too big even before this series.

Marek

[PATCH u-boot-marvell v2 17/18] ddr: marvell: a38x: bump version to 14.0.0

[Marek Behún]

Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the
version in the mv-ddr-devel branch of upstream repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.

There is a new version numbering system, where after 18.12.0 came
1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0.

Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/mv_ddr_build_message.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c 
b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
index cc6234fd40..a2bb8a96a6 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
@@ -1,3 +1,3 @@
 // SPDX-License-Identifier: GPL-2.0
 const char mv_ddr_build_message[] = "";
-const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-18.09.2";
+const char mv_ddr_version_string[] = "mv_ddr: 14.0.0";
-- 
2.26.2

[PATCH u-boot-marvell v2 18/18] ddr: marvell: a38x: fix comment in conditional macro

[Marek Behún]

The code was processed with unifdef utility to omit portions not
relevant to A38x and DDR3. This removes usage of many macros, including
A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove
the macros from #else comment.

Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/ddr3_training.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c 
b/drivers/ddr/marvell/a38x/ddr3_training.c
index 0358f6287a..2b3af23202 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -219,7 +219,7 @@ static int ddr3_tip_pad_inv(void)
   DDR_PHY_CONTROL,
   PHY_CTRL_PHY_REG,
   data, data);
-#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X && !A70X0 && !A80X0 && 
!A3900 */
+#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X */
 #pragma message "unknown platform to configure ddr clock swap"
 #endif
}
-- 
2.26.2

[PATCH u-boot-marvell v2 16/18] ddr: marvell: a38x: enum mv_ddr_twin_die: change order

[Marek Behún]

From: heaterC 

commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream.

@pali suggested this change
In commit 6285efb ("mv_ddr: add support for twin-die combined memory
device") was added support for twin-die combined memory device and
default value for explicitly uninitialized structure members is zero, s
also twin_die_combined is initialized to zero. Which means COMBINED
value.
As prior this commit there was no support for twin-die combined memory
device, default value for twin_die_combined should be NOT_COMBINED. This
change change order of enum mv_ddr_twin_die to ensure that NOT_COMBINED
has value zero.

Signed-off-by: heaterC 
Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/ddr_topology_def.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h 
b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 2cca5676a0..7f2317edfa 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -15,8 +15,8 @@
 #define MV_DDR_MAX_IFACE_NUM   1
 
 enum mv_ddr_twin_die {
-   COMBINED,
NOT_COMBINED,
+   COMBINED,
 };
 
 struct bus_params {
-- 
2.26.2

[PATCH u-boot-marvell v2 14/18] ddr: marvell: a38x: fix memory cs size function

[Marek Behún]

From: Moti Buskila 

commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream.

The funtion returnd cs size in byte instead of MB, that cause
calculation error since the caller was expected to get u32 and when he
got above 4G it refers it as 0.
The fix was to get the cs memory size from function as in MB and then
multiply it by 1MB.

Signed-off-by: Moti Buskila 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/mv_ddr_plat.c | 9 +++--
 drivers/ddr/marvell/a38x/xor.c | 6 +++---
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c 
b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
index 72f0df..0d1df189e8 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
@@ -4,6 +4,7 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_common.h"
 #include "mv_ddr_training_db.h"
 #include "mv_ddr_regs.h"
 #include "mv_ddr_sys_env_lib.h"
@@ -1016,7 +1017,7 @@ int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size)
return MV_BAD_VALUE;
}
 
-   *cs_size = cs_mem_size << 20; /* write cs size in bytes */
+   *cs_size = cs_mem_size;
 
return MV_OK;
 }
@@ -1025,9 +1026,11 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 
cs_ena)
 {
u32 reg, cs;
uint64_t mem_total_size = 0;
+   uint64_t cs_mem_size_mb = 0;
uint64_t cs_mem_size = 0;
uint64_t mem_total_size_c, cs_mem_size_c;
 
+
 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
u32 physical_mem_size;
u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
@@ -1038,8 +1041,9 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 
cs_ena)
for (cs = 0; cs < MAX_CS_NUM; cs++) {
if (cs_ena & (1 << cs)) {
/* get CS size */
-   if (ddr3_calc_mem_cs_size(cs, _mem_size) != MV_OK)
+   if (ddr3_calc_mem_cs_size(cs, _mem_size_mb) != MV_OK)
return MV_FAIL;
+   cs_mem_size = cs_mem_size_mb * _1M;
 
 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
/*
@@ -1088,6 +1092,7 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 
cs_ena)
 */
mem_total_size_c = (mem_total_size >> 16) & 
0x;
cs_mem_size_c = (cs_mem_size >> 16) & 0x;
+
/* if the sum less than 2 G - calculate the value */
if (mem_total_size_c + cs_mem_size_c < 0x1)
mem_total_size += cs_mem_size;
diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c
index 5fb9e216d3..98fb39eaf0 100644
--- a/drivers/ddr/marvell/a38x/xor.c
+++ b/drivers/ddr/marvell/a38x/xor.c
@@ -340,7 +340,7 @@ void ddr3_new_tip_ecc_scrub(void)
 {
u32 cs_c, max_cs;
u32 cs_ena = 0;
-   uint64_t total_mem_size, cs_mem_size = 0;
+   uint64_t total_mem_size, cs_mem_size_mb = 0, cs_mem_size = 0;
 
printf("DDR Training Sequence - Start scrubbing\n");
max_cs = mv_ddr_cs_num_get();
@@ -349,9 +349,9 @@ void ddr3_new_tip_ecc_scrub(void)
 
 #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
/* all chip-selects are of same size */
-   ddr3_calc_mem_cs_size(0, _mem_size);
+   ddr3_calc_mem_cs_size(0, _mem_size_mb);
 #endif
-
+   cs_mem_size = cs_mem_size_mb * _1M;
mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0);
total_mem_size = max_cs * cs_mem_size;
mv_xor_mem_init(0, 0, total_mem_size, 0xdeadbeef, 0xdeadbeef);
-- 
2.26.2

[PATCH u-boot-marvell v2 09/18] ddr: marvell: a38x: allow board specific ODT configuration

[Marek Behún]

From: Baruch Siach 

commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream.

The ODT enable heuristic based on active chip-selects is not always
correct. Some board might use two chip-selects, but have only one ODT
line connected. Allow board specific mv_ddr_topology_map to directly set
the ODT configuration register value.

Signed-off-by: Baruch Siach 
Reviewed-by: Moti Buskila 
Reviewed-by: Nadav Haklai 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/ddr3_init.c| 5 +
 drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 +++
 2 files changed, 8 insertions(+)

diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c 
b/drivers/ddr/marvell/a38x/ddr3_init.c
index a971cc155a..7488770268 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -104,6 +104,7 @@ int ddr3_init(void)
 static int mv_ddr_training_params_set(u8 dev_num)
 {
struct tune_train_params params;
+   struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
int status;
u32 cs_num;
int ck_delay;
@@ -136,6 +137,10 @@ static int mv_ddr_training_params_set(u8 dev_num)
if (ck_delay > 0)
params.ck_delay = ck_delay;
 
+   /* Use platform specific override ODT value */
+   if (tm->odt_config)
+   params.g_odt_config = tm->odt_config;
+
status = ddr3_tip_tune_training_params(dev_num, );
if (MV_OK != status) {
printf("%s Training Sequence - FAILED\n", ddr_type);
diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h 
b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 342c2cf451..3991fec272 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -125,6 +125,9 @@ struct mv_ddr_topology_map {
/* electrical parameters */
unsigned int electrical_data[MV_DDR_EDATA_LAST];
 
+   /* ODT configuration */
+   u32 odt_config;
+
/* Clock enable mask */
u32 clk_enable;
 
-- 
2.26.2

[PATCH u-boot-marvell v2 10/18] ddr: marvell: a38x: add 16Gbit memory devices support

[Marek Behún]

From: Moti Buskila 

commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream.

Signed-off-by: Moti Buskila 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/ddr3_training_ip_def.h | 2 ++
 drivers/ddr/marvell/a38x/mv_ddr_topology.c  | 3 ++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h 
b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
index 2a68669f36..8765df7cfb 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
@@ -80,6 +80,8 @@
 #define ADDR_SIZE_2GB  0x1000
 #define ADDR_SIZE_4GB  0x2000
 #define ADDR_SIZE_8GB  0x4000
+#define ADDR_SIZE_16GB 0x8000
+
 
 enum hws_edge_compare {
EDGE_PF,
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c 
b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index 31711fdd49..c4c3ab72b2 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -248,7 +248,8 @@ static unsigned int mem_size[] = {
ADDR_SIZE_1GB,
ADDR_SIZE_2GB,
ADDR_SIZE_4GB,
-   ADDR_SIZE_8GB
+   ADDR_SIZE_8GB,
+   ADDR_SIZE_16GB
/* TODO: add capacity up to 256GB */
 };
 
-- 
2.26.2

[PATCH u-boot-marvell v2 12/18] ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bit

[Marek Behún]

From: Moti Buskila 

commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream.

WL phase correcion stage is failing while using bus_width of 16bit, not
to be fix this stage is un-necessary when working with bus_width of 16
bit.

Signed-off-by: Moti Buskila 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/ddr3_training_db.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c 
b/drivers/ddr/marvell/a38x/ddr3_training_db.c
index b2f11a8399..6aa7b6069e 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_db.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c
@@ -833,6 +833,9 @@ u32 pattern_table_get_word(u32 dev_num, enum hws_pattern 
type, u8 index)
pattern = pattern_table_get_isi_word16(index);
break;
default:
+   if (((int)type == 29) || ((int)type == 30))
+   break;
+
printf("error: %s: unsupported pattern type [%d] 
found\n",
   __func__, (int)type);
pattern = 0;
-- 
2.26.2

[PATCH u-boot-marvell v2 15/18] ddr: marvell: a38x: import code change from upstream

[Marek Behún]

commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes code in ddr3_training.c.

Import this change to remain consistent with upstream.

Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/ddr3_training.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c 
b/drivers/ddr/marvell/a38x/ddr3_training.c
index 34cc170910..0358f6287a 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -143,6 +143,7 @@ static struct reg_data odpg_default_value[] = {
{0x15a4, 0x0, MASK_ALL_BITS},
{0x15a8, 0x0, MASK_ALL_BITS},
{0x15ac, 0x0, MASK_ALL_BITS},
+   {0x1600, 0x0, MASK_ALL_BITS},
{0x1604, 0x0, MASK_ALL_BITS},
{0x1608, 0x0, MASK_ALL_BITS},
{0x160c, 0x0, MASK_ALL_BITS},
@@ -1569,6 +1570,8 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type 
access_type,
val = ((cl_mask_table[cl_value] & 0x1) << 2) |
((cl_mask_table[cl_value] & 0xe) << 3);
 
+   cs_mask[0] = 0xc;
+
CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0,
val, (0x7 << 4) | (0x1 << 2)));
 
-- 
2.26.2

[PATCH u-boot-marvell v2 13/18] ddr: marvell: a38x: import header change from upstream

[Marek Behún]

commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h 
b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 461f091472..2cca5676a0 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -52,9 +52,6 @@ struct if_params {
/* The DDR frequency for each interfaces */
enum mv_ddr_freq memory_freq;
 
-/* ddr twin-die */
-   enum mv_ddr_twin_die twin_die_combined;
-
/*
 * delay CAS Write Latency
 * - 0 for using default value (jedec suggested)
-- 
2.26.2

[PATCH u-boot-marvell v2 11/18] ddr: marvell: a38x: add support for twin-die combined memory device

[Marek Behún]

From: Moti Buskila 

commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream.

the twin-die combined memory device should be treatened as X8
device and not as X16 one

Signed-off-by: Moti Buskila 
Reviewed-by: Kostya Porotchkin 
[ - the default value for twin_die_combined is set to NOT_COMBINED for
all boards, as this was default behaviour prior this change ]
Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 board/CZ.NIC/turris_omnia/turris_omnia.c  |  2 ++
 board/Marvell/db-88f6820-amc/db-88f6820-amc.c |  1 +
 board/Marvell/db-88f6820-gp/db-88f6820-gp.c   |  1 +
 board/alliedtelesis/x530/x530.c   |  1 +
 board/gdsys/a38x/controlcenterdc.c|  1 +
 board/kobol/helios4/helios4.c |  1 +
 board/solidrun/clearfog/clearfog.c|  1 +
 drivers/ddr/marvell/a38x/ddr_topology_def.h   | 12 
 drivers/ddr/marvell/a38x/mv_ddr_topology.c|  6 +-
 9 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c 
b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 0353d58a36..1d3cefe703 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -286,6 +286,7 @@ static struct mv_ddr_topology_map board_topology_map_1g = {
MV_DDR_TIM_2T} },   /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+   NOT_COMBINED,   /* ddr twin-die combined */
{ {0} },/* raw spd data */
{0} /* timing parameters */
 };
@@ -308,6 +309,7 @@ static struct mv_ddr_topology_map board_topology_map_2g = {
MV_DDR_TIM_2T} },   /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+   NOT_COMBINED,   /* ddr twin-die combined */
{ {0} },/* raw spd data */
{0} /* timing parameters */
 };
diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c 
b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
index 163a1b3de9..122c63d11f 100644
--- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
+++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
@@ -73,6 +73,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TIM_DEFAULT} },  /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+   NOT_COMBINED,   /* ddr twin-die combined */
{ {0} },/* raw spd data */
{0} /* timing parameters */
 };
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c 
b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index 06307e582c..1edc1cb651 100644
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -94,6 +94,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TIM_DEFAULT} },  /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+   NOT_COMBINED,   /* ddr twin-die combined */
{ {0} },/* raw spd data */
{0} /* timing parameters */
 };
diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c
index d602092d73..7bcfa828d7 100644
--- a/board/alliedtelesis/x530/x530.c
+++ b/board/alliedtelesis/x530/x530.c
@@ -68,6 +68,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TIM_2T} },   /* timing */
BUS_MASK_32BIT_ECC, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+   NOT_COMBINED,   /* ddr twin-die combined */
{ {0} },/* raw spd data */
{0},/* timing parameters */
{ {0} },/* electrical configuration */
diff --git a/board/gdsys/a38x/controlcenterdc.c 
b/board/gdsys/a38x/controlcenterdc.c
index ba57a27218..4f1dc3b431 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -71,6 +71,7 @@ static struct mv_ddr_topology_map ddr_topology_map = {
MV_DDR_TIM_DEFAULT} },  /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+   NOT_COMBINED,   /* ddr twin-die combined */
{ {0} },/* raw spd data */
{0} /* timing parameters */
 
diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c
index 

[PATCH u-boot-marvell v2 08/18] ddr: marvell: a38x: import header change from upstream

[Marek Behún]

commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/ddr_topology_def.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h 
b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index c55e3b57e4..342c2cf451 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -152,6 +152,11 @@ enum mv_ddr_validation {
MV_DDR_MEMORY_CHECK
 };
 
+enum mv_ddr_sscg {
+   SSCG_EN,
+   SSCG_DIS,
+};
+
 struct mv_ddr_iface {
/* base addr of ap ddr interface belongs to */
unsigned int ap_base;
@@ -180,6 +185,9 @@ struct mv_ddr_iface {
/* ddr interface validation mode */
enum mv_ddr_validation validation;
 
+   /* ddr interface validation mode */
+   enum mv_ddr_sscg sscg;
+
/* ddr interface topology map */
struct mv_ddr_topology_map tm;
 };
-- 
2.26.2

[PATCH u-boot-marvell v2 07/18] ddr: marvell: a38x: fix memory size calculation using 32bit bus width

[Marek Behún]

From: Moti Buskila 

commit ab9240402a70cc02496683971779e75eff410ab4 upstream.

- function mv_ddr_spd_die_capacity_user_get() has a bug,
  since it insert a user memory enum to it,
  instead of SPD memory enum (which are different)
- fix: remove mv_ddr_spd_die_capacity_user_get() function.
- memory size with 64 and 32 bit already calculated correctly
  at mv_ddr_mem_sz_per_cs_get() function

Signed-off-by: Moti Buskila 
Reviewed-by: Stefan Chulski 
Reviewed-by: Alex Leibovich 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/mv_ddr_spd.c  | 5 -
 drivers/ddr/marvell/a38x/mv_ddr_spd.h  | 1 -
 drivers/ddr/marvell/a38x/mv_ddr_topology.c | 4 
 3 files changed, 10 deletions(-)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.c 
b/drivers/ddr/marvell/a38x/mv_ddr_spd.c
index cb90d30a6a..04dbfe94d6 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_spd.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.c
@@ -217,11 +217,6 @@ enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union 
mv_ddr_spd_data *spd_
return ret_val;
 }
 
-void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum 
mv_ddr_die_capacity capacity)
-{
-   spd_data->byte_fields.byte_4.bit_fields.die_capacity = capacity;
-}
-
 unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data)
 {
unsigned char mem_mirror = 
spd_data->byte_fields.byte_131.bit_fields.rank_1_mapping;
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.h 
b/drivers/ddr/marvell/a38x/mv_ddr_spd.h
index ee35377af5..b4bfef3103 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_spd.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.h
@@ -277,7 +277,6 @@ union mv_ddr_spd_data {
 int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int 
timing_data[]);
 enum mv_ddr_dev_width mv_ddr_spd_dev_width_get(union mv_ddr_spd_data 
*spd_data);
 enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data 
*spd_data);
-void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum 
mv_ddr_die_capacity capacity);
 unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data);
 unsigned char mv_ddr_spd_cs_bit_mask_get(union mv_ddr_spd_data *spd_data);
 unsigned char mv_ddr_spd_dev_type_get(union mv_ddr_spd_data *spd_data);
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c 
b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index 3feb65ea46..31711fdd49 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -74,10 +74,6 @@ int mv_ddr_topology_map_update(void)
/* update device width in topology map */
iface_params->bus_width = 
mv_ddr_spd_dev_width_get(>spd_data);
 
-   /* overwrite SPD configuration, with what the user set */
-   if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
-   mv_ddr_spd_die_capacity_user_get(>spd_data, 
tm->interface_params[0].memory_size);
-
/* update die capacity in topology map */
iface_params->memory_size = 
mv_ddr_spd_die_capacity_get(>spd_data);
 
-- 
2.26.2

[PATCH u-boot-marvell v2 06/18] ddr: marvell: a38x: fix 32bit

[Marek Behún]

From: Moti Buskila 

commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream.

Signed-off-by: Moti Buskila 
Reviewed-by: Alex Leibovich 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/mv_ddr_topology.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c 
b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index 0cbe8d3d1e..3feb65ea46 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -149,7 +149,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
 
if (tm->cfg_src == MV_DDR_CFG_SPD) {
if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
-   tm->spd_data.byte_fields.byte_13.all_bits = 
MV_DDR_PRI_BUS_WIDTH_32;
+   
tm->spd_data.byte_fields.byte_13.bit_fields.primary_bus_width = 
MV_DDR_PRI_BUS_WIDTH_32;
 
enum mv_ddr_pri_bus_width pri_bus_width = 
mv_ddr_spd_pri_bus_width_get(>spd_data);
enum mv_ddr_bus_width_ext bus_width_ext = 
mv_ddr_spd_bus_width_ext_get(>spd_data);
-- 
2.26.2

[PATCH u-boot-marvell v2 04/18] ddr: marvell: a38x: add ddr 32bit ECC support

[Marek Behún]

From: Alex Leibovich 

commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream.

Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c

Signed-off-by: Alex Leibovich 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/mv_ddr_spd.c  | 5 +
 drivers/ddr/marvell/a38x/mv_ddr_spd.h  | 1 +
 drivers/ddr/marvell/a38x/mv_ddr_topology.c | 6 +-
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.c 
b/drivers/ddr/marvell/a38x/mv_ddr_spd.c
index 04dbfe94d6..cb90d30a6a 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_spd.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.c
@@ -217,6 +217,11 @@ enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union 
mv_ddr_spd_data *spd_
return ret_val;
 }
 
+void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum 
mv_ddr_die_capacity capacity)
+{
+   spd_data->byte_fields.byte_4.bit_fields.die_capacity = capacity;
+}
+
 unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data)
 {
unsigned char mem_mirror = 
spd_data->byte_fields.byte_131.bit_fields.rank_1_mapping;
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.h 
b/drivers/ddr/marvell/a38x/mv_ddr_spd.h
index b4bfef3103..ee35377af5 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_spd.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.h
@@ -277,6 +277,7 @@ union mv_ddr_spd_data {
 int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int 
timing_data[]);
 enum mv_ddr_dev_width mv_ddr_spd_dev_width_get(union mv_ddr_spd_data 
*spd_data);
 enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data 
*spd_data);
+void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum 
mv_ddr_die_capacity capacity);
 unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data);
 unsigned char mv_ddr_spd_cs_bit_mask_get(union mv_ddr_spd_data *spd_data);
 unsigned char mv_ddr_spd_dev_type_get(union mv_ddr_spd_data *spd_data);
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c 
b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index f2cd7c0ef3..0cbe8d3d1e 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -74,6 +74,10 @@ int mv_ddr_topology_map_update(void)
/* update device width in topology map */
iface_params->bus_width = 
mv_ddr_spd_dev_width_get(>spd_data);
 
+   /* overwrite SPD configuration, with what the user set */
+   if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
+   mv_ddr_spd_die_capacity_user_get(>spd_data, 
tm->interface_params[0].memory_size);
+
/* update die capacity in topology map */
iface_params->memory_size = 
mv_ddr_spd_die_capacity_get(>spd_data);
 
@@ -144,7 +148,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, 
MV_ATTR_OCTET_PER_INTERFACE);
 
if (tm->cfg_src == MV_DDR_CFG_SPD) {
-   if (tm->bus_act_mask == BUS_MASK_32BIT)
+   if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
tm->spd_data.byte_fields.byte_13.all_bits = 
MV_DDR_PRI_BUS_WIDTH_32;
 
enum mv_ddr_pri_bus_width pri_bus_width = 
mv_ddr_spd_pri_bus_width_get(>spd_data);
-- 
2.26.2

[PATCH u-boot-marvell v2 05/18] ddr: marvell: a38x: import header change from upstream

[Marek Behún]

commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header mv_ddr_topology.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/mv_ddr_topology.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.h 
b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
index 4fca47689f..1cb69ad085 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
@@ -179,7 +179,9 @@ enum mv_ddr_dic_evalue {
 
 /* phy electrical configuration values */
 enum mv_ddr_ohm_evalue {
+   MV_DDR_OHM_20 = 20,/*relevant for Synopsys C/A Drive strength only*/
MV_DDR_OHM_30 = 30,
+   MV_DDR_OHM_40 = 40,/*relevant for Synopsys C/A Drive strength only*/
MV_DDR_OHM_48 = 48,
MV_DDR_OHM_60 = 60,
MV_DDR_OHM_80 = 80,
-- 
2.26.2

[PATCH u-boot-marvell v2 01/18] ddr: marvell: a38x: fix write leveling suplementary algo

[Marek Behún]

From: Moti Buskila 

commit ce62bef8fac559e27245259882e45f19cdc293ad upstream.

- fix JIRA A7K8K-5056
- remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage
- the WL SUP stage already writes this pattern to the memory, if the pattern 
exist at the memory
  then the algorithm will fail, since it think that there are no phase to 
correct

Signed-off-by: Moti Buskila 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c 
b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
index 979f3530b7..5fd9a052fa 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
@@ -864,8 +864,11 @@ int ddr3_tip_load_all_pattern_to_mem(u32 dev_num)
  DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3)));
}
 
-   for (pattern = 0; pattern < PATTERN_LAST; pattern++)
+   for (pattern = 0; pattern < PATTERN_LAST; pattern++) {
+   if (pattern == PATTERN_TEST)
+   continue;
ddr3_tip_load_pattern_to_mem(dev_num, pattern);
+   }
 
return MV_OK;
 }
-- 
2.26.2

[PATCH u-boot-marvell v2 03/18] ddr: marvell: a38x: add ddr32 support

[Marek Behún]

From: Alex Leibovich 

commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream.

Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c

Signed-off-by: Alex Leibovich 
Reviewed-by: Nadav Haklai 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/mv_ddr_topology.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c 
b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index 09840b1e70..f2cd7c0ef3 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -144,6 +144,9 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, 
MV_ATTR_OCTET_PER_INTERFACE);
 
if (tm->cfg_src == MV_DDR_CFG_SPD) {
+   if (tm->bus_act_mask == BUS_MASK_32BIT)
+   tm->spd_data.byte_fields.byte_13.all_bits = 
MV_DDR_PRI_BUS_WIDTH_32;
+
enum mv_ddr_pri_bus_width pri_bus_width = 
mv_ddr_spd_pri_bus_width_get(>spd_data);
enum mv_ddr_bus_width_ext bus_width_ext = 
mv_ddr_spd_bus_width_ext_get(>spd_data);
 
@@ -151,7 +154,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
case MV_DDR_PRI_BUS_WIDTH_16:
pri_and_ext_bus_width = BUS_MASK_16BIT;
break;
-   case MV_DDR_PRI_BUS_WIDTH_32:
+   case MV_DDR_PRI_BUS_WIDTH_32: /*each bit represents byte, so 
0xf-is means 4 bytes-32 bit*/
pri_and_ext_bus_width = BUS_MASK_32BIT;
break;
case MV_DDR_PRI_BUS_WIDTH_64:
-- 
2.26.2

[PATCH u-boot-marvell v2 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Marek Behún]

Hi Stefan,

this is v2 of series that syncs drivers/ddr/marvell/a38x/ with the
mv-ddr-devel branch of
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.

I have tested how the SPL image increases for all a38x boards.
Here are sizes of spl/u-boot-spl.bin before applying this series
(in bytes, hexadecimal), by how much these files are increased
after applying this series (in bytes, decimal).

   beforeinc
   -----
clearfog   0x1f9c928
 controlcenterdc   0x2263c   108
  db-88f6820-amc   0x241d0   108  SPL too big (before and after)
   db-88f6820-gp   0x23c14   108
 helios4   0x1f68d28
turris_omnia   0x1c93236
x530   0x249ed   108  SPL too big (before and after)

As can be seen, these patches do not increase the size of SPL
much, and the only boards where SPL is too big after the series
have the same problem even before applying this series.

For these boards I recommend increasing in include/configs/*.h
  CONFIG_SPL_SIZE from (140 << 10) to (160 << 10)
and in configs/*_defconfig
  CONFIG_SYS_SPI_U_BOOT_OFFS from 0x24000 to 0x29000

Changes from v1:
- original author names are now in the From headers
- added Chris' Tested-by

Marek

Alex Leibovich (2):
  ddr: marvell: a38x: add ddr32 support
  ddr: marvell: a38x: add ddr 32bit ECC support

Baruch Siach (1):
  ddr: marvell: a38x: allow board specific ODT configuration

Marek Behún (7):
  ddr: marvell: a38x: import header change from upstream
  ddr: marvell: a38x: import header change from upstream
  ddr: marvell: a38x: import header change from upstream
  ddr: marvell: a38x: import header change from upstream
  ddr: marvell: a38x: import code change from upstream
  ddr: marvell: a38x: bump version to 14.0.0
  ddr: marvell: a38x: fix comment in conditional macro

Moti Buskila (7):
  ddr: marvell: a38x: fix write leveling suplementary algo
  ddr: marvell: a38x: fix 32bit
  ddr: marvell: a38x: fix memory size calculation using 32bit bus width
  ddr: marvell: a38x: add 16Gbit memory devices support
  ddr: marvell: a38x: add support for twin-die combined memory device
  ddr: marvell: a38x: disable WL phase correction stage in case of
bus_width=16bit
  ddr: marvell: a38x: fix memory cs size function

heaterC (1):
  ddr: marvell: a38x: enum mv_ddr_twin_die: change order

 board/CZ.NIC/turris_omnia/turris_omnia.c  |  2 ++
 board/Marvell/db-88f6820-amc/db-88f6820-amc.c |  1 +
 board/Marvell/db-88f6820-gp/db-88f6820-gp.c   |  1 +
 board/alliedtelesis/x530/x530.c   |  1 +
 board/gdsys/a38x/controlcenterdc.c|  1 +
 board/kobol/helios4/helios4.c |  1 +
 board/solidrun/clearfog/clearfog.c|  1 +
 drivers/ddr/marvell/a38x/ddr3_init.c  |  5 
 drivers/ddr/marvell/a38x/ddr3_training.c  |  5 +++-
 drivers/ddr/marvell/a38x/ddr3_training_db.c   |  3 +++
 .../ddr/marvell/a38x/ddr3_training_ip_def.h   |  2 ++
 .../marvell/a38x/ddr3_training_ip_engine.c|  5 +++-
 drivers/ddr/marvell/a38x/ddr_topology_def.h   | 23 ++-
 .../ddr/marvell/a38x/mv_ddr_build_message.c   |  2 +-
 drivers/ddr/marvell/a38x/mv_ddr_plat.c|  9 ++--
 drivers/ddr/marvell/a38x/mv_ddr_topology.c| 14 ---
 drivers/ddr/marvell/a38x/mv_ddr_topology.h|  2 ++
 drivers/ddr/marvell/a38x/xor.c|  6 ++---
 18 files changed, 72 insertions(+), 12 deletions(-)

-- 
2.26.2

[PATCH u-boot-marvell v2 02/18] ddr: marvell: a38x: import header change from upstream

[Marek Behún]

commit a165037ec26f301be75e1fabc263643683e85255 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún 
Tested-by: Chris Packham 
---
 drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h 
b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 34196b1662..c55e3b57e4 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -148,7 +148,8 @@ enum mv_ddr_validation {
MV_DDR_VAL_DIS,
MV_DDR_VAL_RX,
MV_DDR_VAL_TX,
-   MV_DDR_VAL_RX_TX
+   MV_DDR_VAL_RX_TX,
+   MV_DDR_MEMORY_CHECK
 };
 
 struct mv_ddr_iface {
-- 
2.26.2

Re: [PATCH 4/5] sun7i: add support for Micronova srl s027_3 board

[Giulio Benetti]

Hi Andre,

On 2/19/21 12:37 PM, Andre Przywara wrote:

On Fri, 19 Feb 2021 11:12:08 +0100
Giulio Benetti  wrote:

Hi,


On 2/19/21 2:44 AM, Andre Przywara wrote:

On Fri, 19 Feb 2021 00:26:19 +0100
Giulio Benetti  wrote:

Hi Giulio,
   

From: Giulio Benetti 

Add support for Micronova srl s027_3 board by adding new vendor/board
folders and using in local Makefile the already present
board/sunxi/Makefile. The reason is that s027_3 needs a pin to be asserted
to enable lcd before setting controller up and sunxi board doesn't provide
a way to do this customization.


Have you tried CONFIG_VIDEO_LCD_POWER?


Yes, I already use that for DISPONOFF.


So what are these pins for, exactly? Backlight? A regulator to provide
power to the LCD?


It's the power rail for LCD.


If you grep for "gpio.CONFIG" in sunxi_display.c, there are more GPIOs
that we set, for various reasons. Can you pick some from there, and set
them in your defconfig?


Unfortunately my LCD_PWR drives a P-MOS so it must be inverted, while 
LCD0_DISPONOFF can be meant as a lcd reset.


So I introduce CONFIG_VIDEO_LCD_POWER_ACTIVE_LOW for my board to work
locally.

Would it make sense to send a patch for this for supporting my board?
Or do I wait for you patchset [1] to be applied?


I am strongly against introducing per-board code files, and we
definitely won't introduce them just for one GPIO.


I knew it was a strange hack, but I have 2 different pins to be set high
before init video controller. Another idea that comes into my mind is to
handle CONFIG_VIDEO_LCD_POWER as a gpio list and iterate/enable, what
about that?


Do you really need *two* pins to switch the LCD power supply?


I've messed up names, I need only one pin for LCD power supply(the on 
with P-MOS) but another to enable it(DISPONOFF). But here the problem 
was that LCD power supply is active low.



If yes,
this might be an option. But I guess at this point we want to go more a
DT route.


Yes, agree.


Speaking of which, I don't see any video output device in the DT, I
guess you just rely on simplefb.


Yes, simplefb for u-boot while...


But given that there is no bridge or
it seems to be transparent, at least, you might be able to describe
this in the DT as well, so Linux can use its own display driver?


for Linux I use 4 different fdt overlays using fe,be,tcon and simple-panel.


Then we might be able to find a more sustainable solution, based on
pins in the DT.


Yes



Cheers,
Andre

P.S. Can you please try to apply


[1]:


https://patchwork.ozlabs.org/project/uboot/patch/20210205010748.2646-1-andre.przyw...@arm.com/
This would be merged around the same time, and I am curious if this
still works with an LCD.


For sure I will, I was waiting for this and I've also started to port it 
a bit but I have not much time and then you added a patch. I'm going to 
test it and report. If it doesn't work I'll try to fix it for having 
s027_3 board added using DT then.


Best regards!
--
Giulio Benetti
Benetti Engineering sas






Signed-off-by: Giulio Benetti 
Signed-off-by: Giulio Benetti 


Please choose one email address, there is no point in having two
S-o-b's from the same person.


I missed this as well as the repeated patch in patchset.

Thank you
Best regards

Re: Can’t boot FIT kernel image

[Sean Anderson]

On 2/19/21 3:47 AM, Алексей Беляев wrote:

Hello!

I'm trying to make FIT Kernel+dtb image for U-Boot.
```
mkimage -E -f Image.its Image.new
```

Image.its:
```
/dts-v1/;

/ {
     description = "ARM64 OpenWrt FIT (Flattened Image Tree)";
     #address-cells = <1>;

     images {
     kernel@1 {
     description = "ARM64 OpenWrt Linux-5.4.60";
     data = /incbin/("arch/arm64/boot/Image.lzma");
     type = "kernel";
     arch = "arm64";
     os = "linux";
     compression = "lzma";
     load = <0x40008000>;
     entry = <0x40008000>;
     hash@1 {
     algo = "crc32";
     };
     hash@2 {
     algo = "sha1";
     };
     };

     fdt@1 {
     description = "ARM64 OpenWrt xunlong_orangepi-zero-plus2 
device tree blob";
     data = /incbin/("sun50i-h5-orangepi-zero-plus2.dtb");
     type = "flat_dt";
     arch = "arm64";
     compression = "none";
     load = <0x4FA0>;
     hash@1 {
     algo = "crc32";
     };
     hash@2 {
     algo = "sha1";
     };
     };

     };

     configurations {
     default = "config@1";
     config@1 {
     description = "OpenWRT";
     kernel = "kernel@1";
     fdt = "fdt@1";
     };
     };
};
```

and it Look like good. U-boot print correct Information about it.

```
U-Boot 2020.04 (Aug 28 2020 - 09:44:29 +) Allwinner Technology

CPU:   Allwinner H5 (SUN50I)
Model: OrangePi Zero Plus2
DRAM:  512 MiB
MMC:   Device 'mmc@1c11000': seq 1 is in use by 'mmc@1c1'
mmc@1c0f000: 0, mmc@1c1: 2, mmc@1c11000: 1

In:    serial
Out:   serial
Err:   serial
Hit any key to stop autoboot:  0
=> fatload mmc 0 53E0 Image.new
3561732 bytes read in 513 ms (6.6 MiB/s)
=> setenv bootargs console=ttyS0,115200 earlyprintk root=PARTUUID=5452574f-02 
rootwait earlycon=uart,mmio32,0x01c28000
=> bootm 53E0
## Loading kernel from FIT Image at 53e0 ...
    Using 'config@1' configuration
    Trying 'kernel@1' kernel subimage
  Description:  ARM64 OpenWrt Linux-5.4.60
  Type: Kernel Image
  Compression:  lzma compressed
  Data Start:   0x53e0043c
  Data Size:    3537003 Bytes = 3.4 MiB
  Architecture: AArch64
  OS:   Linux
  Load Address: 0x40008000


Here it is 40008000


  Entry Point:  0x40008000
  Hash algo:    crc32
  Hash value:   1003b68e
  Hash algo:    sha1
  Hash value:   94d9ea6a0f543649d294b50bd2a7bba1857cf538
    Verifying Hash Integrity ... crc32+ sha1+ OK
## Loading fdt from FIT Image at 53e0 ...
    Using 'config@1' configuration
    Trying 'fdt@1' fdt subimage
  Description:  ARM64 OpenWrt xunlong_orangepi-zero-plus2 device tree blob
  Type: Flat Device Tree
  Compression:  uncompressed
  Data Start:   0x5415fca8
  Data Size:    23641 Bytes = 23.1 KiB
  Architecture: AArch64
  Load Address: 0x4fa0
  Hash algo:    crc32
  Hash value:   fc8daabb
  Hash algo:    sha1
  Hash value:   6c18b66e1c9bb6dfb289701e1a478e294cb3568c
    Verifying Hash Integrity ... crc32+ sha1+ OK
    Loading fdt from 0x5415fca8 to 0x4fa0
    Booting using the fdt blob at 0x4fa0
    Uncompressing Kernel Image
    Loading Device Tree to 49ff7000, end 49fffc58 ... OK

Starting kernel ...
```
And device has freeze.

Kernel and dtb is fine. I have Image.lzma and "dtb" files distinctly and their 
work fine:
```
U-Boot 2020.04 (Aug 28 2020 - 09:44:29 +) Allwinner Technology

CPU:   Allwinner H5 (SUN50I)
Model: OrangePi Zero Plus2
DRAM:  512 MiB
MMC:   Device 'mmc@1c11000': seq 1 is in use by 'mmc@1c1'
mmc@1c0f000: 0, mmc@1c1: 2, mmc@1c11000: 1

In:    serial
Out:   serial
Err:   serial
Hit any key to stop autoboot:  0
=> load mmc 0 53E0 Image.lzma
3537067 bytes read in 506 ms (6.7 MiB/s)
=> fatload mmc 0 0x4FA0 sun50i-h5-orangepi-zero-plus2.dtb
23641 bytes read in 5 ms (4.5 MiB/s)
=> setenv bootargs console=ttyS0,115200 earlyprintk root=PARTUUID=5452574f-02 
rootwait earlycon=uart,mmio32,0x01c28000
=bootm 0x53E0 - 0x4FA0
## Booting kernel from Legacy Image at 53e0 ...
    Image Name:   Linux
    Image Type:   AArch64 Linux Kernel Image (lzma compressed)
    Data Size:    3537003 Bytes = 3.4 MiB
    Load Address: 4008


but here it is 4008. Which one is correct?

--Sean


    Entry Point:  4008
  

Re: [PATCH btrfs-progs] btrfs-progs: do not fail when offset of a ROOT_ITEM is not -1

[David Sterba]

On Tue, Feb 09, 2021 at 06:34:06PM +0100, Marek Behún wrote:
> When the btrfs_read_fs_root() function is searching a ROOT_ITEM with
> location key offset other than -1, it currently fails via BUG_ON.
> 
> The offset can have other value than -1, though. This can happen for
> example if a subvolume is renamed:
> 
>   $ btrfs subvolume create X && sync
>   Create subvolume './X'
>   $ btrfs inspect-internal dump-tree /dev/root | grep -B 2 'name: X$
> location key (270 ROOT_ITEM 18446744073709551615) type DIR
> transid 283 data_len 0 name_len 1
> name: X
>   $ mv X Y && sync
>   $ btrfs inspect-internal dump-tree /dev/root | grep -B 2 'name: Y$
> location key (270 ROOT_ITEM 0) type DIR
> transid 285 data_len 0 name_len 1
> name: Y
> 
> As can be seen the offset changed from -1ULL to 0.
> 
> Do not fail in this case.
> 
> Signed-off-by: Marek Behún 
> Cc: David Sterba 
> Cc: Qu Wenruo 
> Cc: Tom Rini 

Added to devel, thanks.

USB3 XHCI crashing with USB 3 hub on Octeon

[Aaron Williams]

Hi all,

While backporting the latest USB support in U-Boot to support USB 3 hubs I 
decided to try the latest U-Boot for Octeon which should contain everything. 
When I start USB, however, with a USB 3 thumb drive plugged into a USB 3 hub, 
I am seeing a crash. I have enabled all of the debugging support for usb.c, 
usb_hub.c, xhci.c, xhci-ring.c and xhci_mem.c

In my backported code which is a bit hacked up due to the lack of DT support, 
I am seeing it fail when it attempts to set the hub depth. Note that 
everything works fine with a USB 2 hub. I was hoping to compare the stock U-
Boot with my hacked up code to track down the issue.

-Aaron

Here are the logs:

=> usb start
starting USB...
Bus xhci@16800: xhci_register: dev='xhci@16800', 
ctrl=8eea1aa0, hccr=80016800, hcor=80016820
// Halt the HC: 80016820
// Reset the HC
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.00
Bus xhci@16900: xhci_register: dev='xhci@16900', 
ctrl=8eeab040, hccr=80016900, hcor=80016920
// Halt the HC: 80016920
// Reset the HC
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus xhci@16800 for devices... xhci_alloc_device: 
dev='xhci@16800', udev=8ee9c280
set address 1
usb_control_msg: request: 0x5, requesttype: 0x0, value 0x1 index 0x0 length 
0x0
xhci_submit_control_msg: dev='xhci@16800', udev=8ee9c280, 
udev->dev='xhci@16800', portnr=0
USB_REQ_SET_ADDRESS
scrlen = 0
 req->length = 0
Len is 0
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 
0x12
xhci_submit_control_msg: dev='xhci@16800', udev=8ee9c280, 
udev->dev='xhci@16800', portnr=0
USB_DT_DEVICE request
scrlen = 18
 req->length = 18
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 
0x9
xhci_submit_control_msg: dev='xhci@16800', udev=8ee9c280, 
udev->dev='xhci@16800', portnr=0
USB_DT_CONFIG config
scrlen = 25
 req->length = 9
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 
0x1F
xhci_submit_control_msg: dev='xhci@16800', udev=8ee9c280, 
udev->dev='xhci@16800', portnr=0
USB_DT_CONFIG config
scrlen = 25
 req->length = 31
get_conf_no 0 Result 25, wLength 31
if 0, ep 0
##EP epmaxpacketin[1] = 2048
set configuration 1
usb_control_msg: request: 0x9, requesttype: 0x0, value 0x1 index 0x0 length 
0x0
xhci_submit_control_msg: dev='xhci@16800', udev=8ee9c280, 
udev->dev='xhci@16800', portnr=0
scrlen = 0
 req->length = 0
Len is 0
new device strings: Mfr=1, Product=2, SerialNumber=0
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x300 index 0x0 length 
0xFF
xhci_submit_control_msg: dev='xhci@16800', udev=8ee9c280, 
udev->dev='xhci@16800', portnr=0
USB_DT_STRING config
scrlen = 4
 req->length = 255
USB device number 1 default language ID 0x409
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x301 index 0x409 
length 0xFF
xhci_submit_control_msg: dev='xhci@16800', udev=8ee9c280, 
udev->dev='xhci@16800', portnr=0
USB_DT_STRING config
scrlen = 14
 req->length = 255
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x302 index 0x409 
length 0xFF
xhci_submit_control_msg: dev='xhci@16800', udev=8ee9c280, 
udev->dev='xhci@16800', portnr=0
USB_DT_STRING config
scrlen = 42
 req->length = 255
Manufacturer U-Boot
Product  XHCI Host Controller
SerialNumber 
usb_hub_post_probe
usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2A00 index 0x0 
length 0x4
xhci_submit_control_msg: dev='xhci@16800', udev=8eeae040, 
udev->dev='usb_hub', portnr=0
USB_DT_HUB config
scrlen = 8
 req->length = 4
usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2A00 index 0x0 
length 0xC
xhci_submit_control_msg: dev='xhci@16800', udev=8eeae040, 
udev->dev='usb_hub', portnr=0
USB_DT_HUB config
scrlen = 8
 req->length = 12
2 ports detected
ganged power switching
standalone hub
individual port over-current protection
TT requires at most 8 FS bit times (666 ns)
power on to power good time: 20ms
hub controller current requirement: 0mA
port 1 is removable
port 2 is removable
usb_control_msg: request: 0x0, requesttype: 0xA0, value 0x0 index 0x0 length 
0x4
xhci_submit_control_msg: dev='xhci@16800', udev=8eeae040, 
udev->dev='usb_hub', portnr=0
scrlen = 2
 req->length = 4
get_hub_status returned status 1, change 802
local power source is lost (inactive)
no over-current condition exists
xhci_update_hub_device: dev='xhci@16800', udev=8eeae040
enabling power on all ports
usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x1 length 
0x0
xhci_submit_control_msg: dev='xhci@16800', udev=8eeae040, 
udev->dev='usb_hub', portnr=0
scrlen = 0
 req->length = 0
Len is 0

Re: [PATCH] arm: dts: imx7d-sdb: Fix enet by setting soft spi mode to 3 for extended io

[Fabio Estevam]

Hi Christian,

On Fri, Feb 19, 2021 at 10:32 AM Christian Bräuner Sørensen
 wrote:
>
> This patch sets SPI MODE 3 for the fairchild 74HC595 device that is used
> to reset the ethernet device, which fixes ethernet.
>
> Reasoning:
> The imx7dsabresd board uses SPI for setting the extended IO.
> One of the purposes of this extended IO, is having the ability to set
> ENET_RST i.e. reset the ethernet PHY. Without proper reset of the PHY,
> ethernet does not work.
>
> commit 0e146993bb3d ("spi: add support for all spi modes with soft spi")
> broke network support for boards using imx7d-sdb, since it actually

Shouldn't this commit be reverted then?

I suppose it introduced regressions on other boards too.

> corrected default SPI mode setting for the software emulated soft_spi to 0,
> i.e. CPHA to 0 and CPOL to 0.
> Previously, the driver defaulted to CPHA 1 and CPOL 1 (i.e. spi mode 3).
> After the default SPI mode is now 0 (which is the correct default value)
> we now need to actively set CPHA and CPOL to 1 for the specific devices
> that actually needs this.
>
> Signed-off-by: Christian Bräuner Sørensen 
> ---
>
>  arch/arm/dts/imx7d-sdb.dts | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts
> index 8191ac7c33..6ed21ce8b0 100644
> --- a/arch/arm/dts/imx7d-sdb.dts
> +++ b/arch/arm/dts/imx7d-sdb.dts
> @@ -58,6 +58,8 @@
> reg = <0>;
> registers-number = <1>;
> spi-max-frequency = <10>;
> +   spi-cpha
> +   spi-cpol;

It is not good that we deviate from the devicetree used in Linux.

Johannes/Jagan,

Any suggestions as to how to properly fix the regression?

Thanks

[PATCH v2 3/3] firmware: scmi: fix inline comments and minor coding style issues

[Etienne Carriere]

Fix inline comments and empty line in scmi driver and test files.

Remove test on IS_ENABLED(CONFIG_*_SCMI) in test/dm/scmi.c since these
configuration are expected enabled when CONFIG_FIRMWARE_SCMI is enabled
in sandbox configuration.

Signed-off-by: Etienne Carriere 
---
Changes in v2:
 - discard adding tests on IS_ENABLED(CONFIG_*_SCMI) in test/dm/scmi.c
   for the reason stated in commit log.
---
 arch/sandbox/include/asm/scmi_test.h   |  5 +++--
 drivers/firmware/scmi/sandbox-scmi_agent.c |  4 ++--
 test/dm/scmi.c | 15 ++-
 3 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/arch/sandbox/include/asm/scmi_test.h 
b/arch/sandbox/include/asm/scmi_test.h
index 9b7031531..2930e686d 100644
--- a/arch/sandbox/include/asm/scmi_test.h
+++ b/arch/sandbox/include/asm/scmi_test.h
@@ -24,6 +24,7 @@ struct sandbox_scmi_clk {
 
 /**
  * struct sandbox_scmi_reset - Simulated reset controller exposed by SCMI
+ * @id:Identifier of the reset controller used in the SCMI 
protocol
  * @asserted:  Reset control state: true if asserted, false if desasserted
  */
 struct sandbox_scmi_reset {
@@ -48,8 +49,8 @@ struct sandbox_scmi_voltd {
  * @idx:   Identifier for the SCMI agent, its index
  * @clk:   Simulated clocks
  * @clk_count: Simulated clocks array size
- * @clk:   Simulated reset domains
- * @clk_count: Simulated reset domains array size
+ * @reset: Simulated reset domains
+ * @reset_count: Simulated reset domains array size
  * @voltd:  Simulated voltage domains (regulators)
  * @voltd_count: Simulated voltage domains array size
  */
diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c 
b/drivers/firmware/scmi/sandbox-scmi_agent.c
index 3eafc49bd..56125a57b 100644
--- a/drivers/firmware/scmi/sandbox-scmi_agent.c
+++ b/drivers/firmware/scmi/sandbox-scmi_agent.c
@@ -18,7 +18,7 @@
  * processing. It simulates few of the SCMI services for some of the
  * SCMI protocols embedded in U-Boot. Currently:
  * - SCMI clock protocol: emulate 2 agents each exposing few clocks
- * - SCMI reset protocol: emulate 1 agents each exposing a reset
+ * - SCMI reset protocol: emulate 1 agent exposing a reset controller
  * - SCMI voltage domain protocol: emulate 1 agent exposing 2 regulators
  *
  * Agent #0 simulates 2 clocks, 1 reset domain and 1 voltage domain.
@@ -29,7 +29,7 @@
  *
  * All clocks and regulators are default disabled and reset controller down.
  *
- * This Driver exports sandbox_scmi_service_ct() for the test sequence to
+ * This Driver exports sandbox_scmi_service_ctx() for the test sequence to
  * get the state of the simulated services (clock state, rate, ...) and
  * check back-end device state reflects the request send through the
  * various uclass devices, as clocks and reset controllers.
diff --git a/test/dm/scmi.c b/test/dm/scmi.c
index 792410338..2eaf06392 100644
--- a/test/dm/scmi.c
+++ b/test/dm/scmi.c
@@ -44,10 +44,8 @@ static int ut_assert_scmi_state_postprobe(struct 
unit_test_state *uts,
scmi_devices = sandbox_scmi_devices_ctx(dev);
 
ut_assertnonnull(scmi_devices);
-   if (IS_ENABLED(CONFIG_CLK_SCMI))
-   ut_asserteq(3, scmi_devices->clk_count);
-   if (IS_ENABLED(CONFIG_RESET_SCMI))
-   ut_asserteq(1, scmi_devices->reset_count);
+   ut_asserteq(3, scmi_devices->clk_count);
+   ut_asserteq(1, scmi_devices->reset_count);
ut_asserteq(2, scmi_devices->regul_count);
 
/* State of the simulated SCMI server exposed */
@@ -110,7 +108,6 @@ static int dm_test_scmi_sandbox_agent(struct 
unit_test_state *uts)
 
return ret;
 }
-
 DM_TEST(dm_test_scmi_sandbox_agent, UT_TESTF_SCAN_FDT);
 
 static int dm_test_scmi_clocks(struct unit_test_state *uts)
@@ -121,9 +118,6 @@ static int dm_test_scmi_clocks(struct unit_test_state *uts)
int ret_dev;
int ret;
 
-   if (!IS_ENABLED(CONFIG_CLK_SCMI))
-   return 0;
-
ret = load_sandbox_scmi_test_devices(uts, );
if (ret)
return ret;
@@ -172,7 +166,6 @@ static int dm_test_scmi_clocks(struct unit_test_state *uts)
 
return release_sandbox_scmi_test_devices(uts, dev);
 }
-
 DM_TEST(dm_test_scmi_clocks, UT_TESTF_SCAN_FDT);
 
 static int dm_test_scmi_resets(struct unit_test_state *uts)
@@ -182,9 +175,6 @@ static int dm_test_scmi_resets(struct unit_test_state *uts)
struct udevice *dev = NULL;
int ret;
 
-   if (!IS_ENABLED(CONFIG_RESET_SCMI))
-   return 0;
-
ret = load_sandbox_scmi_test_devices(uts, );
if (ret)
return ret;
@@ -203,7 +193,6 @@ static int dm_test_scmi_resets(struct unit_test_state *uts)
 
return release_sandbox_scmi_test_devices(uts, dev);
 }
-
 DM_TEST(dm_test_scmi_resets, UT_TESTF_SCAN_FDT);
 
 static int dm_test_scmi_voltage_domains(struct unit_test_state *uts)
-- 
2.17.1

[PATCH v2 2/3] firmware: scmi: sandbox test for voltage regulator

[Etienne Carriere]

Implement sandbox regulator devices for SCMI voltage domains
and test them in DM scmi tests.

Signed-off-by: Etienne Carriere 
---
Changes in v2:
 - don't test IS_ENABLED(CONFIG_DM_REGULATOR_SCMI) in test/dm/scmi.c,
   it's expected enabled when CONFIG_FIRMWARE_SCMI is enabled in sandbox.
---
 arch/sandbox/dts/test.dts|  23 +++
 arch/sandbox/include/asm/scmi_test.h |  20 ++
 configs/sandbox_defconfig|   1 +
 drivers/firmware/scmi/sandbox-scmi_agent.c   | 203 ++-
 drivers/firmware/scmi/sandbox-scmi_devices.c |  25 ++-
 test/dm/scmi.c   |  58 ++
 6 files changed, 327 insertions(+), 3 deletions(-)

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index e95f4631b..14d6983e7 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -451,6 +451,27 @@
reg = <0x16>;
#reset-cells = <1>;
};
+
+   protocol@17 {
+   reg = <0x17>;
+
+   regulators {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   regul0_scmi0: reg@0 {
+   reg = <0>;
+   regulator-name = 
"sandbox-voltd0";
+   regulator-min-microvolt = 
<110>;
+   regulator-max-microvolt = 
<330>;
+   };
+   regul1_scmi0: reg@1 {
+   reg = <0x1>;
+   regulator-name = 
"sandbox-voltd1";
+   regulator-min-microvolt = 
<180>;
+   };
+   };
+   };
};
 
sandbox-scmi-agent@1 {
@@ -1217,6 +1238,8 @@
compatible = "sandbox,scmi-devices";
clocks = <_scmi0 7>, <_scmi0 3>, <_scmi1 1>;
resets = <_scmi0 3>;
+   regul0-supply = <_scmi0>;
+   regul1-supply = <_scmi0>;
};
 
pinctrl {
diff --git a/arch/sandbox/include/asm/scmi_test.h 
b/arch/sandbox/include/asm/scmi_test.h
index 3e8b0068f..9b7031531 100644
--- a/arch/sandbox/include/asm/scmi_test.h
+++ b/arch/sandbox/include/asm/scmi_test.h
@@ -31,6 +31,18 @@ struct sandbox_scmi_reset {
bool asserted;
 };
 
+/**
+ * struct sandbox_scmi_voltd - Simulated voltage regulator exposed by SCMI
+ * @id:Identifier of the voltage domain used in the SCMI 
protocol
+ * @enabled:   Regulator state: true if on, false if off
+ * @voltage_uv:Regulator current voltage in microvoltd (uV)
+ */
+struct sandbox_scmi_voltd {
+   uint id;
+   bool enabled;
+   int voltage_uv;
+};
+
 /**
  * struct sandbox_scmi_agent - Simulated SCMI service seen by SCMI agent
  * @idx:   Identifier for the SCMI agent, its index
@@ -38,6 +50,8 @@ struct sandbox_scmi_reset {
  * @clk_count: Simulated clocks array size
  * @clk:   Simulated reset domains
  * @clk_count: Simulated reset domains array size
+ * @voltd:  Simulated voltage domains (regulators)
+ * @voltd_count: Simulated voltage domains array size
  */
 struct sandbox_scmi_agent {
uint idx;
@@ -45,6 +59,8 @@ struct sandbox_scmi_agent {
size_t clk_count;
struct sandbox_scmi_reset *reset;
size_t reset_count;
+   struct sandbox_scmi_voltd *voltd;
+   size_t voltd_count;
 };
 
 /**
@@ -63,12 +79,16 @@ struct sandbox_scmi_service {
  * @clk_count: Number of clock devices probed
  * @reset: Array the reset controller devices
  * @reset_count:   Number of reset controller devices probed
+ * @regul: Array regulator devices
+ * @regul_count:   Number of regulator devices probed
  */
 struct sandbox_scmi_devices {
struct clk *clk;
size_t clk_count;
struct reset_ctl *reset;
size_t reset_count;
+   struct udevice **regul;
+   size_t regul_count;
 };
 
 #ifdef CONFIG_SCMI_FIRMWARE
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 0c7674efc..790158445 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -214,6 +214,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_REGULATOR_S5M8767=y
 CONFIG_DM_REGULATOR_SANDBOX=y
+CONFIG_DM_REGULATOR_SCMI=y
 CONFIG_REGULATOR_TPS65090=y
 CONFIG_DM_PWM=y
 CONFIG_PWM_SANDBOX=y
diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c 
b/drivers/firmware/scmi/sandbox-scmi_agent.c
index 35de68c75..3eafc49bd 100644
--- a/drivers/firmware/scmi/sandbox-scmi_agent.c
+++ 

[PATCH v2 1/3] firmware: scmi: voltage regulator

[Etienne Carriere]

Implement voltage regulators interfaced by the SCMI voltage domain
protocol. The DT bindings are defined in the Linux kernel since
SCMI voltage domain and regulators patches [1] and [2] integration
in v5.11-rc7.

Link: [1] 
https://github.com/torvalds/linux/commit/0f80fcec08e9c50b8d2992cf26495673765ebaba
Link: [2] 
https://github.com/torvalds/linux/commit/2add5cacff3531e54c50b0832128299faa9f0563

Signed-off-by: Etienne Carriere 
---
Changes in v2:
- no change
---
 doc/device-tree-bindings/arm/arm,scmi.txt |  34 +
 drivers/firmware/scmi/scmi_agent-uclass.c |  35 -
 drivers/power/regulator/Kconfig   |   8 +
 drivers/power/regulator/Makefile  |   1 +
 drivers/power/regulator/scmi_regulator.c  | 170 ++
 include/scmi_protocols.h  | 113 ++
 6 files changed, 359 insertions(+), 2 deletions(-)
 create mode 100644 drivers/power/regulator/scmi_regulator.c

diff --git a/doc/device-tree-bindings/arm/arm,scmi.txt 
b/doc/device-tree-bindings/arm/arm,scmi.txt
index 1f293ea24..a76124f4a 100644
--- a/doc/device-tree-bindings/arm/arm,scmi.txt
+++ b/doc/device-tree-bindings/arm/arm,scmi.txt
@@ -62,6 +62,20 @@ Required properties:
  - #power-domain-cells : Should be 1. Contains the device or the power
 domain ID value used by SCMI commands.
 
+Regulator bindings for the SCMI Regulator based on SCMI Message Protocol
+
+An SCMI Regulator is permanently bound to a well defined SCMI Voltage Domain,
+and should be always positioned as a root regulator.
+It does not support any current operation.
+
+SCMI Regulators are grouped under a 'regulators' node which in turn is a child
+of the SCMI Voltage protocol node inside the desired SCMI instance node.
+
+This binding uses the common regulator binding[6].
+
+Required properties:
+ - reg : shall identify an existent SCMI Voltage Domain.
+
 Sensor bindings for the sensors based on SCMI Message Protocol
 --
 SCMI provides an API to access the various sensors on the SoC.
@@ -105,6 +119,7 @@ Required sub-node properties:
 [3] Documentation/devicetree/bindings/thermal/thermal.txt
 [4] Documentation/devicetree/bindings/sram/sram.yaml
 [5] Documentation/devicetree/bindings/reset/reset.txt
+[6] Documentation/devicetree/bindings/regulator/regulator.yaml
 
 Example:
 
@@ -169,6 +184,25 @@ firmware {
reg = <0x16>;
#reset-cells = <1>;
};
+
+   scmi_voltage: protocol@17 {
+   reg = <0x17>;
+
+   regulators {
+   regulator_devX: regulator@0 {
+   reg = <0x0>;
+   regulator-max-microvolt = <330>;
+   };
+
+   regulator_devY: regulator@9 {
+   reg = <0x9>;
+   regulator-min-microvolt = <50>;
+   regulator-max-microvolt = <420>;
+   };
+
+   ...
+   };
+   };
};
 };
 
diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c 
b/drivers/firmware/scmi/scmi_agent-uclass.c
index 516e690ac..03d236426 100644
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
@@ -50,6 +50,29 @@ int scmi_to_linux_errno(s32 scmi_code)
return -EPROTO;
 }
 
+static int regulator_devices_bind(struct udevice *dev, struct driver *drv,
+ ofnode protocol_node)
+{
+   ofnode regulators_node;
+   ofnode node;
+   int ret;
+
+   regulators_node = ofnode_find_subnode(protocol_node, "regulators");
+   if (!ofnode_valid(regulators_node)) {
+   dev_err(dev, "regulators subnode not found\n");
+   return -ENXIO;
+   }
+
+   ofnode_for_each_subnode(node, regulators_node) {
+   ret = device_bind(dev, drv, ofnode_get_name(node), NULL, node,
+ NULL);
+   if (ret)
+   return ret;
+   }
+
+   return 0;
+}
+
 /*
  * SCMI agent devices binds devices of various uclasses depeding on
  * the FDT description. scmi_bind_protocol() is a generic bind sequence
@@ -79,6 +102,10 @@ static int scmi_bind_protocols(struct udevice *dev)
if (IS_ENABLED(CONFIG_RESET_SCMI))
drv = DM_DRIVER_GET(scmi_reset_domain);
break;
+   case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
+   if (IS_ENABLED(CONFIG_DM_REGULATOR_SCMI))
+   drv = DM_DRIVER_GET(scmi_voltage_domain);
+   break;
default:
 

[PATCH 1/2] clk: imx8mp Enable SPI clock

[Arendt, Steffen]

Enable SPI clock for imx8mp

Signed-off-by: Steffen Arendt 
---

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index c77500bcce..b31afb31c0 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -116,6 +116,20 @@ static const char *imx8mp_i2c6_sels[] = "clock-osc-24m", 
"sys_pll1_160m", "sys_
 "sys_pll3_out", "audio_pll1_out", 
"video_pll1_out",
 "audio_pll2_out", "sys_pll1_133m", ;

+#if CONFIG_IS_ENABLED(DM_SPI)
+static const char *imx8mp_ecspi1_sels[] = "osc_24m", "sys_pll2_200m", 
"sys_pll1_40m",
+  "sys_pll1_160m", "sys_pll1_800m", 
"sys_pll3_out",
+  "sys_pll2_250m", "audio_pll2_out", ;
+
+static const char *imx8mp_ecspi2_sels[] = "osc_24m", "sys_pll2_200m", 
"sys_pll1_40m",
+  "sys_pll1_160m", "sys_pll1_800m", 
"sys_pll3_out",
+  "sys_pll2_250m", "audio_pll2_out", ;
+
+static const char *imx8mp_ecspi3_sels[] = "osc_24m", "sys_pll2_200m", 
"sys_pll1_40m",
+  "sys_pll1_160m", "sys_pll1_800m", 
"sys_pll3_out",
+  "sys_pll2_250m", "audio_pll2_out", ;
+#endif
+
 static const char *imx8mp_usdhc1_sels[] = "clock-osc-24m", "sys_pll1_400m", 
"sys_pll1_800m",
   "sys_pll2_500m", "sys_pll3_out", 
"sys_pll1_266m",
   "audio_pll2_out", "sys_pll1_100m", ;
@@ -397,6 +411,21 @@ static int imx8mp_clk_probe(struct udevice *dev)

clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", 
"usdhc3", base + 0x45e0, 0));

+#if CONFIG_IS_ENABLED(DM_SPI)
+   clk_dm(IMX8MP_CLK_ECSPI1,
+  imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + 
0xb280));
+   clk_dm(IMX8MP_CLK_ECSPI2,
+  imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + 
0xb300));
+   clk_dm(IMX8MP_CLK_ECSPI3,
+  imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + 
0xc180));
+   clk_dm(IMX8MP_CLK_ECSPI1_ROOT,
+  imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+   clk_dm(IMX8MP_CLK_ECSPI2_ROOT,
+  imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+   clk_dm(IMX8MP_CLK_ECSPI3_ROOT,
+  imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+#endif
+
return 0;



_

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[PATCH 2/2] clk: imx8mp Enable EQOS clock

[Arendt, Steffen]

Enable SPI clock for imx8mp

Signed-off-by: Steffen Arendt 
---

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index b31afb31c0..c8a0b4549b 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -130,6 +130,15 @@ static const char *imx8mp_ecspi3_sels[] = {"osc_24m", 
"sys_pll2_200m", "sys_pll1
   "sys_pll2_250m", "audio_pll2_out", };
 #endif

+static const char *imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", 
"sys_pll2_50m",
+"sys_pll2_100m", "sys_pll1_160m", 
"audio_pll1_out",
+"video_pll1_out", "clk_ext4", };
+
+static const char *imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", 
"audio_pll1_out",
+  "clk_ext1", "clk_ext2", 
"clk_ext3",
+  "clk_ext4", 
"video_pll1_out", };
+
+
 static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll1_800m",
   "sys_pll2_500m", "sys_pll3_out", 
"sys_pll1_266m",
   "audio_pll2_out", "sys_pll1_100m", };
@@ -426,6 +435,12 @@ static int imx8mp_clk_probe(struct udevice *dev)
   imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
 #endif

+   clk_dm(IMX8MP_CLK_ENET_QOS,
+   imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, 
base + 0xa880));
+   clk_dm(IMX8MP_CLK_ENET_QOS_TIMER,
+   imx8m_clk_composite("enet_qos_timer", 
imx8mp_enet_qos_timer_sels, base + 0xa900));
+
+
return 0;
 }

[PATCH] arm: dts: imx7d-sdb: Fix enet by setting soft spi mode to 3 for extended io

[Christian Bräuner Sørensen]

This patch sets SPI MODE 3 for the fairchild 74HC595 device that is used
to reset the ethernet device, which fixes ethernet.

Reasoning:
The imx7dsabresd board uses SPI for setting the extended IO.
One of the purposes of this extended IO, is having the ability to set
ENET_RST i.e. reset the ethernet PHY. Without proper reset of the PHY,
ethernet does not work.

commit 0e146993bb3d ("spi: add support for all spi modes with soft spi")
broke network support for boards using imx7d-sdb, since it actually
corrected default SPI mode setting for the software emulated soft_spi to 0,
i.e. CPHA to 0 and CPOL to 0.
Previously, the driver defaulted to CPHA 1 and CPOL 1 (i.e. spi mode 3).
After the default SPI mode is now 0 (which is the correct default value)
we now need to actively set CPHA and CPOL to 1 for the specific devices
that actually needs this.

Signed-off-by: Christian Bräuner Sørensen 
---

 arch/arm/dts/imx7d-sdb.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts
index 8191ac7c33..6ed21ce8b0 100644
--- a/arch/arm/dts/imx7d-sdb.dts
+++ b/arch/arm/dts/imx7d-sdb.dts
@@ -58,6 +58,8 @@
reg = <0>;
registers-number = <1>;
spi-max-frequency = <10>;
+   spi-cpha;
+   spi-cpol;
};
};
 
-- 
2.25.1

Re: [PATCH 05/16] arm: Remove highbank board

[Tom Rini]

On Fri, Feb 19, 2021 at 01:04:22PM +, André Przywara wrote:
> On 10/02/2021 02:42, Tom Rini wrote:
> 
> Hi Tom,
> 
> > This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  
> > The
> > deadline for this conversion was the v2019.07 release.  The use of 
> > CONFIG_AHCI
> > requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
> > this board.
> 
> So I made a series a few months ago to bring highbank up to speed, it
> converts everything over to DM, also starts using the DT provided by the
> board for its own purposes.
> I was facing one issue with SATA though, which made me drop the ball
> there :-(
> This is for the 2014.07 merge window, I guess? So if I manage to send
> something before April, would you consider dropping this patch then?
> Or do I need to start the series with a revert?

Good question.  I'm not likely to get everything dropped that I want to
drop for v2021.04.  Since you have everything but SATA/etc converted
(which I guess is a driver needs conversion?) I'd like to see the base
converted and you picking up the MAINTAINERS entry for it soon so I can
review and take that.  Thanks!

-- 
Tom


signature.asc
Description: PGP signature

Re: [Uboot-stm32] [PATCH] usb: dwc2: change compatible st, stm32mp1-hsotg to st, stm32mp15-hsotg

[Patrick DELAUNAY]

Hi Ahmad,

On 2/11/21 12:14 PM, Ahmad Fatoum wrote:

Hi,

On 10.02.21 20:59, Tom Rini wrote:

On Tue, Feb 09, 2021 at 08:51:26PM +0100, Patrick DELAUNAY wrote:

On 2/9/21 11:39 AM, Marek Vasut wrote:

On 2/9/21 11:14 AM, Patrick Delaunay wrote:
Hi,

[...]


diff --git a/drivers/usb/gadget/dwc2_udc_otg.c
b/drivers/usb/gadget/dwc2_udc_otg.c
index e3871e381e..ecac80fc11 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -1176,7 +1176,7 @@ static int dwc2_udc_otg_remove(struct udevice
*dev)
   static const struct udevice_id dwc2_udc_otg_ids[] = {
   { .compatible = "snps,dwc2" },
   { .compatible = "brcm,bcm2835-usb" },
-    { .compatible = "st,stm32mp1-hsotg",
+    { .compatible = "st,stm32mp15-hsotg",
     .data = (ulong)dwc2_set_stm32mp1_hsotg_params },

I have to point out the obvious, DT is ABI, this breaks ABI. However, do
we care about out-of-tree DTs here ?


I know that the binding backward compatibility and "binary compatible" the
is a key element of DT

for the Linux kernel (for example the latest kernel image should work with a
old device tree).

The way we use DTs in U-Boot we don't enforce ABI because we allow for
DTS and bindings to come in before they're fully stabilized in
linux-next/similar and then it's required to re-sync them once they are
final.

I think platforms like the STM32MP1 should be handled specially, because
they support having an external device tree passed from the FSBL at runtime.
See 
https://github.com/trini/u-boot/blob/master/arch/arm/mach-stm32mp/boot_params.c#L32

@Patrick, wouldn't this change break booting newer U-Boot with older TF-A in
some configurations? Or is this reusing-fsbl-fdt feature unused?



Cheers,
Ahmad


I introduce this patch to prepare the FIP support in STM32MP15x TF-A

but it is not yet ready today in downstream or in upstream (STOpenLinux 
v2.1).



In this FIP use-case, the DT provided by TF-A to U-Boot is the "u-boot.dtb"

generated by U-Boot compilation (including the required 
"u-boot,dm-pre-reloc"


add-on).


The files "u-boot-nodtb.bin" and "u-boot.dtb" are provided to TF-A makefile

when the FIP is create; I hope these files are aligned as resulting of the

U-Boot compilation.


And update of existing FIP is possible with command:

 PC $> fiptool update --nt-fw u-boot-nodtb.bin --hw-config u-boot.dtb 
fip.bin



Here I hope the DT and U-Boot binary are updated at the same time

to avoid any dependency issue  (even if it is not mandatory).


But as this FIP feature is not yet used, I don't break the current or 
the FIP STM32MP1


configurations, except if I miss something,  as the 2 U-Boot files in FIP

are updated at the same time.


Regards,

Patrick

Re: [PATCH 05/16] arm: Remove highbank board

[André Przywara]

On 10/02/2021 02:42, Tom Rini wrote:

Hi Tom,

> This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
> requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
> this board.

So I made a series a few months ago to bring highbank up to speed, it
converts everything over to DM, also starts using the DT provided by the
board for its own purposes.
I was facing one issue with SATA though, which made me drop the ball
there :-(
This is for the 2014.07 merge window, I guess? So if I manage to send
something before April, would you consider dropping this patch then?
Or do I need to start the series with a revert?

Cheers,
Andre

> 
> Cc: Rob Herring 
> Signed-off-by: Tom Rini 
> ---
>  arch/arm/Kconfig|   7 --
>  arch/arm/Makefile   |   1 -
>  arch/arm/mach-highbank/Kconfig  |  12 --
>  arch/arm/mach-highbank/Makefile |   6 -
>  arch/arm/mach-highbank/timer.c  |  34 --
>  board/highbank/MAINTAINERS  |   6 -
>  board/highbank/Makefile |   6 -
>  board/highbank/ahci.c   | 207 
>  board/highbank/highbank.c   | 148 ---
>  configs/highbank_defconfig  |  28 -
>  include/configs/highbank.h  |  60 -
>  11 files changed, 515 deletions(-)
>  delete mode 100644 arch/arm/mach-highbank/Kconfig
>  delete mode 100644 arch/arm/mach-highbank/Makefile
>  delete mode 100644 arch/arm/mach-highbank/timer.c
>  delete mode 100644 board/highbank/MAINTAINERS
>  delete mode 100644 board/highbank/Makefile
>  delete mode 100644 board/highbank/ahci.c
>  delete mode 100644 board/highbank/highbank.c
>  delete mode 100644 configs/highbank_defconfig
>  delete mode 100644 include/configs/highbank.h
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 95557d6ed6bd..6fa69d39be5b 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -750,11 +750,6 @@ config ARCH_S5PC1XX
>   select DM_SERIAL
>   imply CMD_DM
>  
> -config ARCH_HIGHBANK
> - bool "Calxeda Highbank"
> - select CPU_V7A
> - select PL011_SERIAL
> -
>  config ARCH_INTEGRATOR
>   bool "ARM Ltd. Integrator family"
>   select DM
> @@ -1873,8 +1868,6 @@ source "arch/arm/mach-davinci/Kconfig"
>  
>  source "arch/arm/mach-exynos/Kconfig"
>  
> -source "arch/arm/mach-highbank/Kconfig"
> -
>  source "arch/arm/mach-integrator/Kconfig"
>  
>  source "arch/arm/mach-ipq40xx/Kconfig"
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 28b523b37c70..e1d266c3a4d8 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -57,7 +57,6 @@ machine-$(CONFIG_ARCH_BCM283X)  += bcm283x
>  machine-$(CONFIG_ARCH_BCMSTB)+= bcmstb
>  machine-$(CONFIG_ARCH_DAVINCI)   += davinci
>  machine-$(CONFIG_ARCH_EXYNOS)+= exynos
> -machine-$(CONFIG_ARCH_HIGHBANK)  += highbank
>  machine-$(CONFIG_ARCH_IPQ40XX)   += ipq40xx
>  machine-$(CONFIG_ARCH_K3)+= k3
>  machine-$(CONFIG_ARCH_KEYSTONE)  += keystone
> diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
> deleted file mode 100644
> index 0e73c0414293..
> --- a/arch/arm/mach-highbank/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if ARCH_HIGHBANK
> -
> -config SYS_BOARD
> - default "highbank"
> -
> -config SYS_SOC
> - default "highbank"
> -
> -config SYS_CONFIG_NAME
> - default "highbank"
> -
> -endif
> diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
> deleted file mode 100644
> index 029e266bedce..
> --- a/arch/arm/mach-highbank/Makefile
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# (C) Copyright 2000-2006
> -# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
> -
> -obj-y:= timer.o
> diff --git a/arch/arm/mach-highbank/timer.c b/arch/arm/mach-highbank/timer.c
> deleted file mode 100644
> index 2423a0e37855..
> --- a/arch/arm/mach-highbank/timer.c
> +++ /dev/null
> @@ -1,34 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2010-2011 Calxeda, Inc.
> - *
> - * Based on arm926ejs/mx27/timer.c
> - */
> -
> -#include 
> -#include 
> -#include 
> -#include 
> -
> -#undef SYSTIMER_BASE
> -#define SYSTIMER_BASE0xFFF34000  /* Timer 0 and 1 base   
> */
> -
> -static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
> -
> -/*
> - * Start the timer
> - */
> -int timer_init(void)
> -{
> - /*
> -  * Setup timer0
> -  */
> - writel(0, _base->timer0control);
> - writel(SYSTIMER_RELOAD, _base->timer0load);
> - writel(SYSTIMER_RELOAD, _base->timer0value);
> - writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256,
> - _base->timer0control);
> -
> - return 0;
> -
> -}
> diff --git a/board/highbank/MAINTAINERS 

[PATCH] mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support

[Stefan Roese]

This patch enables USB storage support with the necessary partition
support on the MIPS Octeon EBB7304.

Signed-off-by: Stefan Roese 
Cc: Aaron Williams 
Cc: Chandrakala Chavva 
---
 configs/octeon_ebb7304_defconfig | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig
index a98d73a268..b8670c9165 100644
--- a/configs/octeon_ebb7304_defconfig
+++ b/configs/octeon_ebb7304_defconfig
@@ -24,7 +24,9 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-# CONFIG_DOS_PARTITION is not set
+CONFIG_AMIGA_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0x1FBFE000
 CONFIG_BLK=y
@@ -59,6 +61,7 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
-- 
2.30.1

Re: sunxi/pinephone suggestions and fixes

[André Przywara]

On 17/02/2021 16:19, Nicolas Boulenguez wrote:

Hi Nicolas,

> Please consider the attached suggestions for the sunxi/pinephone
> platform.
> Among commits written for and by Mobian users, these ones may be of
> interest for all pinephone owners.
> Each header mentions the original motivation and author.

Please send this as a proper series, with each patch in a separate
email. That makes it possible to look at and discuss the individual patches.
git send-email should help you with that, it looks like the patches are
already in mbox format, so just enumerating them on the command line
should do the trick. Sending to yourself only first (--to 
--suppress-cc=all) helps to get this right ;-)

And please address maintainers directly, scripts/get_maintainer.pl
should give you some idea who to address (feel free to filter that list,
the output is sometimes quite verbose).

Cheers,
Andre

[PATCH v5] imx: support for conga-QMX8 board

[Oliver Graute]

Add i.MX8QM qmx8 congatec board support

U-Boot 2021.04-rc1-00070-gcc181a2ad4 (Feb 19 2021 - 13:15:49 +0100)

CPU:   NXP i.MX8QM RevB A53 at 1200 MHz

Model: Congatec QMX8 Qseven series
Board: conga-QMX8
Build: SCFW 494c97f3, SECO-FW d7523fe8, ATF 09c5cc9
Boot:  SD2
DRAM:  6 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:serial@5a06
Out:   serial@5a06
Err:   serial@5a06
switch to partitions #0, OK
mmc2 is current device
Net:
Error: ethernet@5b04 address not set.
No ethernet found.

Hit any key to stop autoboot:  0

Signed-off-by: Oliver Graute 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Simon Glass 
Cc: Ye Li 
Cc: uboot-imx 
---

These changes are based on this vendor tree:
git.congatec.com/imx8_early_access/imx8_uboot_internal.git

Changes for v5:
 - fixed checkpatch errors
 - fixed some checkpatch warnings

Changes for v4:
 - fixed missing DTS file in MAINTAINERS
 - replaced bd_t with struct bd_info
 - replaced README with imx8qm-dmsse20-a1.rst
 - move CMD_FUSE to Kconfig
 - replaced power_domain_lookup_name with imx8_power_domain_lookup_name

Changes for v3:
 - include log.h
 - include delay.h
 - improved README
 - set phy register to six
 - Remove 'fdt_high' and 'initrd_high' environment variables
 - set CONFIG_SYS_BOOTMAPSZ to 256MB
 - increased CONFIG_SYS_FSL_USDHC_NUM to 3

Changes for v2:
 - added USDHC3_BASE_ADDR
 - replaced CONFIG_FSL_ESDHC with CONFIG_FSL_ESDHC_IMX
 - set CONFIG_FEC_MXC_PHYADDR to -1
 - moved CONFIG_ENV_SIZE and CONFIG_ENV_OFFSET to defconfig

 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/imx8qm-cgtqmx8.dts | 404 
 arch/arm/mach-imx/imx8/Kconfig  |   7 +
 board/congatec/cgtqmx8/Kconfig  |  14 +
 board/congatec/cgtqmx8/MAINTAINERS  |   7 +
 board/congatec/cgtqmx8/Makefile |  11 +
 board/congatec/cgtqmx8/cgtqmx8.c| 456 
 board/congatec/cgtqmx8/imximage.cfg |  21 ++
 board/congatec/cgtqmx8/spl.c|  77 +
 board/congatec/common/Kconfig   |  48 +++
 board/congatec/common/Makefile  |  23 ++
 board/congatec/common/mmc.c |  50 +++
 configs/cgtqmx8_defconfig   |  86 ++
 doc/board/congatec/cgtqmx8.rst  |  70 +
 doc/board/congatec/index.rst|   9 +
 include/configs/cgtqmx8.h   | 181 +++
 16 files changed, 1465 insertions(+)
 create mode 100644 arch/arm/dts/imx8qm-cgtqmx8.dts
 create mode 100644 board/congatec/cgtqmx8/Kconfig
 create mode 100644 board/congatec/cgtqmx8/MAINTAINERS
 create mode 100644 board/congatec/cgtqmx8/Makefile
 create mode 100644 board/congatec/cgtqmx8/cgtqmx8.c
 create mode 100644 board/congatec/cgtqmx8/imximage.cfg
 create mode 100644 board/congatec/cgtqmx8/spl.c
 create mode 100644 board/congatec/common/Kconfig
 create mode 100644 board/congatec/common/Makefile
 create mode 100644 board/congatec/common/mmc.c
 create mode 100644 configs/cgtqmx8_defconfig
 create mode 100644 doc/board/congatec/cgtqmx8.rst
 create mode 100644 doc/board/congatec/index.rst
 create mode 100644 include/configs/cgtqmx8.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 858b79ac97..23f5a59a08 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -773,6 +773,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
 dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qm-apalis.dtb \
fsl-imx8qm-mek.dtb \
+   imx8qm-cgtqmx8.dtb \
imx8qm-rom7720-a1.dtb \
fsl-imx8qxp-ai_ml.dtb \
fsl-imx8qxp-colibri.dtb \
diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts
new file mode 100644
index 00..555c357f6f
--- /dev/null
+++ b/arch/arm/dts/imx8qm-cgtqmx8.dts
@@ -0,0 +1,404 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ * Copyright 2017 congatec AG
+ * Copyright (C) 2019 Oliver Graute 
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x8000 0x0002;
+
+#include "fsl-imx8qm.dtsi"
+
+/ {
+   model = "Congatec QMX8 Qseven series";
+   compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm";
+
+   chosen {
+   bootargs = "console=ttyLP0,115200 
earlycon=lpuart32,0x5a06,115200";
+   stdout-path = 
+   };
+
+   regulators {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   reg_usdhc2_vmmc: usdhc2_vmmc {
+   compatible = "regulator-fixed";
+   regulator-name = "sw-3p3-sd1";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = < 7 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   off-on-delay-us = <3000>;
+   };
+
+   reg_usdhc3_vmmc: 

Re: [PATCH] sunxi: Use kconfig instead define CONFIG_I2C_EDID

[André Przywara]

On 16/02/2021 08:31, Игорь Юрасов wrote:

Hi,

> Signed-off-by: Igor Iurasov 

This will be superseded by the switch to DM_VIDEO:
https://patchwork.ozlabs.org/project/uboot/patch/20210205010748.2646-1-andre.przyw...@arm.com/

Cheers,
Andre

P.S. Please CC: maintainers directly, scripts/get_maintainer.pl tells
you who to send the mail to.

> ---
>  arch/arm/mach-sunxi/Kconfig| 1 +
>  include/configs/sunxi-common.h | 1 -
>  2 files changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 0135575ca1..1ffdc3de1d 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -818,6 +818,7 @@ config VIDEO_SUNXI
>   depends on !SUN50I_GEN_H6
>   select VIDEO
>   imply VIDEO_DT_SIMPLEFB
> + imply I2C_EDID
>   default y
>   ---help---
>   Say Y here to add support for using a cfb console on the HDMI, LCD
> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
> index 000f386470..068aef2f5a 100644
> --- a/include/configs/sunxi-common.h
> +++ b/include/configs/sunxi-common.h
> @@ -265,7 +265,6 @@ extern int soft_i2c_gpio_scl;
> 
>  #define CONFIG_VIDEO_LOGO
>  #define CONFIG_VIDEO_STD_TIMINGS
> -#define CONFIG_I2C_EDID
>  #define VIDEO_LINE_LEN (pGD->plnSizeX)
> 
>  /* allow both serial and cfb console. */
> 

[PATCH 13/14] board: lx2160a: Update MAINTAINERS

[Priyanka Jain]

Update LX2160AQDS BOARD MAINTAINER entry to
current MAINTAINER.

Signed-off-by: Priyanka Jain 
---
 board/freescale/lx2160a/MAINTAINERS | 1 -
 1 file changed, 1 deletion(-)

diff --git a/board/freescale/lx2160a/MAINTAINERS 
b/board/freescale/lx2160a/MAINTAINERS
index c627417cf7..cc69de2970 100644
--- a/board/freescale/lx2160a/MAINTAINERS
+++ b/board/freescale/lx2160a/MAINTAINERS
@@ -16,7 +16,6 @@ F:configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
 
 LX2160AQDS BOARD
 M: Meenakshi Aggarwal 
-M: Pankaj Bansal 
 S: Maintained
 F: board/freescale/lx2160a/eth_lx2160aqds.h
 F: include/configs/lx2160aqds.h
-- 
2.17.1

[PATCH 12/14] board: ls1046ardb: Update MAINTAINERS

[Priyanka Jain]

Update LS1046ARDB BOARD MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain 
---
 board/freescale/ls1046ardb/MAINTAINERS | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/board/freescale/ls1046ardb/MAINTAINERS 
b/board/freescale/ls1046ardb/MAINTAINERS
index 8b4b45e9ed..efdea22bde 100644
--- a/board/freescale/ls1046ardb/MAINTAINERS
+++ b/board/freescale/ls1046ardb/MAINTAINERS
@@ -11,13 +11,6 @@ F:   configs/ls1046ardb_sdcard_defconfig
 F: configs/ls1046ardb_emmc_defconfig
 F: configs/ls1046ardb_tfa_defconfig
 F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
-
-LS1046A_SECURE_BOOT BOARD
-M: Ruchika Gupta 
-S: Maintained
 F: configs/ls1046ardb_SECURE_BOOT_defconfig
 F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
-
-M: Sumit Garg 
-S: Maintained
 F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
-- 
2.17.1

[PATCH 14/14] board: ls1012aqds: Update MAINTAINERS

[Priyanka Jain]

Update LS1012AQDS Board MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain 
---
 board/freescale/ls1012aqds/MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/ls1012aqds/MAINTAINERS 
b/board/freescale/ls1012aqds/MAINTAINERS
index dbd4670c3b..c1bb8d5150 100644
--- a/board/freescale/ls1012aqds/MAINTAINERS
+++ b/board/freescale/ls1012aqds/MAINTAINERS
@@ -1,6 +1,6 @@
 LS1012AQDS BOARD
-M: Prabhakar Kushwaha 
 M: Rajesh Bhagat 
+M: Pramod Kumar 
 S: Maintained
 F: board/freescale/ls1012aqds/
 F: include/configs/ls1012aqds.h
-- 
2.17.1

[PATCH 11/14] board: ls1046aqds: Update MAINTAINERS

[Priyanka Jain]

Update LS1046AQDS BOARD MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain 
---
 board/freescale/ls1046aqds/MAINTAINERS | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/board/freescale/ls1046aqds/MAINTAINERS 
b/board/freescale/ls1046aqds/MAINTAINERS
index 39a48da95a..72c4253fcf 100644
--- a/board/freescale/ls1046aqds/MAINTAINERS
+++ b/board/freescale/ls1046aqds/MAINTAINERS
@@ -12,7 +12,4 @@ F:configs/ls1046aqds_qspi_defconfig
 F: configs/ls1046aqds_lpuart_defconfig
 F: configs/ls1046aqds_tfa_defconfig
 F: configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
-
-M: Sumit Garg 
-S: Maintained
 F: configs/ls1046aqds_SECURE_BOOT_defconfig
-- 
2.17.1

[PATCH 10/14] board: ls2080ardb: Update MAINTAINERS

[Priyanka Jain]

Update LS2080ARDB BOARD MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain 
---
 board/freescale/ls2080ardb/MAINTAINERS | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/board/freescale/ls2080ardb/MAINTAINERS 
b/board/freescale/ls2080ardb/MAINTAINERS
index 113b7ab3fd..6e25b82db5 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M: Prabhakar Kushwaha , Priyanka Jain 

+M: Priyanka Jain 
 S: Maintained
 F: board/freescale/ls2080ardb/
 F: board/freescale/ls2080a/ls2080ardb.c
@@ -21,8 +21,8 @@ S:Maintained
 F: configs/ls2081ardb_defconfig
 
 LS2080A_SECURE_BOOT BOARD
-#M:Saksham Jain 
-S: Orphan (since 2018-05)
+M: Udit Agarwal 
+S: Maintained
 F: configs/ls2080ardb_SECURE_BOOT_defconfig
 
 LS2088A_QSPI_SECURE_BOOT BOARD
-- 
2.17.1

[PATCH 09/14] board: ls2080aqds: Update MAINTAINERS

[Priyanka Jain]

Update LS2080AQDS BOARD MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain 
---
 board/freescale/ls2080aqds/MAINTAINERS | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/board/freescale/ls2080aqds/MAINTAINERS 
b/board/freescale/ls2080aqds/MAINTAINERS
index e3d7635476..84735dce28 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M: Prabhakar Kushwaha , Priyanka Jain 

+M: Priyanka Jain 
 M: Rajesh Bhagat 
 S: Maintained
 F: board/freescale/ls2080aqds/
@@ -10,8 +10,4 @@ F:configs/ls2080aqds_nand_defconfig
 F: configs/ls2080aqds_qspi_defconfig
 F: configs/ls2080aqds_sdcard_defconfig
 F: configs/ls2088aqds_tfa_defconfig
-
-LS2080A_SECURE_BOOT BOARD
-#M:Saksham Jain 
-S: Orphan (since 2018-05)
 F: configs/ls2080aqds_SECURE_BOOT_defconfig
-- 
2.17.1

[PATCH 08/14] board: ls1088a: Update MAINTAINERS

[Priyanka Jain]

Update LS1088ARDB, LS1088AQDS BOARD MAINTAINERS
entries to current MAINTAINERS.

Signed-off-by: Priyanka Jain 
---
 board/freescale/ls1088a/MAINTAINERS | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/board/freescale/ls1088a/MAINTAINERS 
b/board/freescale/ls1088a/MAINTAINERS
index 98ecb88e3b..5c7925a95f 100644
--- a/board/freescale/ls1088a/MAINTAINERS
+++ b/board/freescale/ls1088a/MAINTAINERS
@@ -1,5 +1,4 @@
 LS1088ARDB BOARD
-M: Prabhakar Kushwaha 
 M: Ashish Kumar 
 M: Rajesh Bhagat 
 S: Maintained
@@ -11,7 +10,6 @@ F:configs/ls1088ardb_tfa_defconfig
 F: configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
 
 LS1088AQDS BOARD
-M: Prabhakar Kushwaha 
 M: Ashish Kumar 
 M: Rajesh Bhagat 
 S: Maintained
@@ -25,17 +23,15 @@ F:  configs/ls1088aqds_tfa_defconfig
 
 LS1088AQDS_QSPI_SECURE_BOOT BOARD
 M: Udit Agarwal 
-M: Vinitha Pillai-B57223 
 S: Maintained
 F: configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
 
 LS1088ARDB_QSPI_SECURE_BOOT BOARD
 M: Udit Agarwal 
-M: Vinitha Pillai-B57223 
 S: Maintained
 F: configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
 
 LS1088ARDB_SD_SECURE_BOOT BOARD
-M: Sumit Garg 
+M: Udit Agarwal 
 S: Maintained
 F: configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
-- 
2.17.1

[PATCH 07/14] board: ls1043ardb: Update MAINTAINERS

[Priyanka Jain]

Update LS1043ARDB BOARD MAINTAINERS entries
to current MAINTAINERS.

Signed-off-by: Priyanka Jain 
---
 board/freescale/ls1043ardb/MAINTAINERS | 4 
 1 file changed, 4 deletions(-)

diff --git a/board/freescale/ls1043ardb/MAINTAINERS 
b/board/freescale/ls1043ardb/MAINTAINERS
index ed62396760..36e7331538 100644
--- a/board/freescale/ls1043ardb/MAINTAINERS
+++ b/board/freescale/ls1043ardb/MAINTAINERS
@@ -10,10 +10,6 @@ F:   configs/ls1043ardb_nand_defconfig
 F: configs/ls1043ardb_sdcard_defconfig
 F: configs/ls1043ardb_tfa_defconfig
 F: configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
-
-LS1043A_SECURE_BOOT BOARD
-M: Ruchika Gupta 
-S: Maintained
 F: configs/ls1043ardb_SECURE_BOOT_defconfig
 F: configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
 F: configs/ls1043ardb_nand_SECURE_BOOT_defconfig
-- 
2.17.1

[PATCH 06/14] board: ls1028a: Update MAINTAINERS

[Priyanka Jain]

Update LS1028AQDS, LS10128ARDB board MAINTAINERS
entries to current MAINTAINERS.

Signed-off-by: Priyanka Jain 
---
 board/freescale/ls1028a/MAINTAINERS | 4 
 1 file changed, 4 deletions(-)

diff --git a/board/freescale/ls1028a/MAINTAINERS 
b/board/freescale/ls1028a/MAINTAINERS
index 5b7a8db2fa..9e7b0697ff 100644
--- a/board/freescale/ls1028a/MAINTAINERS
+++ b/board/freescale/ls1028a/MAINTAINERS
@@ -1,6 +1,4 @@
 LS1028AQDS BOARD
-M: Sudhanshu Gupta 
-M: Rai Harninder 
 M: Rajesh Bhagat 
 M: Tang Yuantian 
 S: Maintained
@@ -11,8 +9,6 @@ F: configs/ls1028aqds_tfa_defconfig
 F: configs/ls1028aqds_tfa_lpuart_defconfig
 
 LS1028ARDB BOARD
-M: Sudhanshu Gupta 
-M: Rai Harninder 
 M: Rajesh Bhagat 
 M: Tang Yuantian 
 S: Maintained
-- 
2.17.1

[PATCH 05/14] board: ls1021atwr: Update MAINTAINERS

[Priyanka Jain]

Update LS1021ATWR BOARD MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain 
---
 board/freescale/ls1021atwr/MAINTAINERS | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/board/freescale/ls1021atwr/MAINTAINERS 
b/board/freescale/ls1021atwr/MAINTAINERS
index c8b93c6469..7ab8347e9e 100644
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -9,7 +9,4 @@ F:  configs/ls1021atwr_nor_lpuart_defconfig
 F: configs/ls1021atwr_sdcard_ifc_defconfig
 F: configs/ls1021atwr_sdcard_qspi_defconfig
 F: configs/ls1021atwr_qspi_defconfig
-
-M: Sumit Garg 
-S: Maintained
 F: configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
-- 
2.17.1

[PATCH 04/14] board: ls1021aiot: Update MAINTAINERS

[Priyanka Jain]

Update LS1021AIOT BOARD MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain 
---
 board/freescale/ls1021aiot/MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/ls1021aiot/MAINTAINERS 
b/board/freescale/ls1021aiot/MAINTAINERS
index 2dab7988ee..65f21bee34 100644
--- a/board/freescale/ls1021aiot/MAINTAINERS
+++ b/board/freescale/ls1021aiot/MAINTAINERS
@@ -1,5 +1,5 @@
 LS1021AIOT BOARD
-M: Feng Li 
+M: Alison Wang 
 S: Maintained
 F: board/freescale/ls1021aiot/
 F: include/configs/ls1021aiot.h
-- 
2.17.1

[PATCH 03/14] board: ls1012ardb: Update MAINTAINERS

[Priyanka Jain]

Update LS1012ARDB BOARD MAINTAINERS entries
to current MAINTAINERS.

Signed-off-by: Priyanka Jain 
---
 board/freescale/ls1012ardb/MAINTAINERS | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/board/freescale/ls1012ardb/MAINTAINERS 
b/board/freescale/ls1012ardb/MAINTAINERS
index 60e184d10f..b0c008b5fc 100644
--- a/board/freescale/ls1012ardb/MAINTAINERS
+++ b/board/freescale/ls1012ardb/MAINTAINERS
@@ -1,6 +1,6 @@
 LS1012ARDB BOARD
-M: Prabhakar Kushwaha 
 M: Rajesh Bhagat 
+M: Pramod Kumar 
 S: Maintained
 F: board/freescale/ls1012ardb/
 F: include/configs/ls1012ardb.h
@@ -8,13 +8,10 @@ F:configs/ls1012ardb_qspi_defconfig
 F: configs/ls1012ardb_tfa_defconfig
 F: configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
 F: configs/ls1012a2g5rdb_tfa_defconfig
-
-M: Sumit Garg 
-S: Maintained
 F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
 
 LS1012A2G5RDB BOARD
-M:  Bhaskar Upadhaya 
+M: Pramod Kumar 
 S:  Maintained
 F:  board/freescale/ls1012ardb/
 F:  include/configs/ls1012a2g5rdb.h
-- 
2.17.1