[PATCH 2/2] configs: imx8mn_beacon: Enable QSPI Support
There is a QSPI chip connected to the FSPI. Enable the defconfig to support it. Signed-off-by: Adam Ford diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index d6a3385d8d..567a6e5e1e 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -49,6 +49,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -90,11 +91,14 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=4000 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y @@ -116,6 +120,7 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_DM_THERMAL=y -- 2.25.1
[PATCH 1/2] arm: dts: imx8mn, imx8mn-beacon: Sync dts files with Kernel 5.12-rc5
There have been a few updates including flexspi, so it's necessary
to re-sync.
Signed-off-by: Adam Ford
diff --git a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
index 49bff19a78..376ca8ff72 100644
--- a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
@@ -34,6 +34,15 @@
};
};
+ reg_audio: regulator-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_aud";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "vsd_3v3";
@@ -53,6 +62,20 @@
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ sound {
+ compatible = "fsl,imx-audio-wm8962";
+ model = "wm8962-audio";
+ audio-cpu = <&sai3>;
+ audio-codec = <&wm8962>;
+ audio-routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "Ext Spk", "SPKOUTL",
+ "Ext Spk", "SPKOUTR",
+ "AMIC", "MICBIAS",
+ "IN3R", "AMIC";
+ };
};
&ecspi2 {
@@ -98,6 +121,44 @@
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
+
+ wm8962: audio-codec@1a {
+ compatible = "wlf,wm8962";
+ reg = <0x1a>;
+ clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
+ clock-names = "xclk";
+ DCVDD-supply = <®_audio>;
+ DBVDD-supply = <®_audio>;
+ AVDD-supply = <®_audio>;
+ CPVDD-supply = <®_audio>;
+ MICVDD-supply = <®_audio>;
+ PLLVDD-supply = <®_audio>;
+ SPKVDD1-supply = <®_audio>;
+ SPKVDD2-supply = <®_audio>;
+ gpio-cfg = <
+ 0x /* 0:Default */
+ 0x /* 1:Default */
+ 0x /* 2:FN_DMICCLK */
+ 0x /* 3:Default */
+ 0x /* 4:FN_DMICCDAT */
+ 0x /* 5:Default */
+ >;
+ };
+};
+
+&easrc {
+ fsl,asrc-rate = <48000>;
+ status = "okay";
+};
+
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
};
&snvs_pwrkey {
@@ -177,6 +238,16 @@
>;
};
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
+ MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
+ MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK0xd6
+ MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
+ MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
diff --git a/arch/arm/dts/imx8mn-beacon-som.dtsi
b/arch/arm/dts/imx8mn-beacon-som.dtsi
index 52a50d97e0..de2cd0e320 100644
--- a/arch/arm/dts/imx8mn-beacon-som.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-som.dtsi
@@ -4,6 +4,12 @@
*/
/ {
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &snvs_rtc;
+ spi0 = &flexspi;
+ };
+
usdhc1_pwrseq: usdhc1_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
@@ -36,11 +42,39 @@
cpu-supply = <&buck2_reg>;
};
+/* DDR controller is running LPDDR at 800MHz which requires 0.95V */
+&a53_opp_table {
+ opp-12 {
+ opp-microvolt = <95>;
+ };
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <2500>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <1>;
+ };
+
+ opp-800M {
+ opp-hz = /bits/ 64 <8>;
+ };
+ };
+};
+
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
+ phy-supply = <&buck6_reg>;
phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
Re: Locking down U-Boot env with ENV_WRITEABLE_LIST
On Fri, Mar 26, 2021 at 11:34 AM Marek Vasut wrote:
>
> On 3/26/21 7:15 PM, Tim Harvey wrote:
> > Greetings,
>
> Hi,
>
> > I'm trying to understand best how to lock down a U-Boot environment
> > using ENV_WRITEABLE_LIST=y.
> >
> > My understanding is that I should define all vars that I wish to be
> > able to be loaded from a FLASH env in CONFIG_ENV_FLAGS_LIST_DEFAULT. I
> > would think this would be something in Kconfig but it's not so I
> > wonder if I'm misunderstanding something or if I truly need to patch a
> > config.h when using this feature.
>
> You do need to patch board config in include/configs/ , since the flags
> were note converted to Kconfig. And make sure you only use integer or
> bool vars, since strings might contain scripts, which you want to avoid.
>
> > What is the best way to actively see your static U-Boot env that gets
> > linked into U-Boot? I can see it with a hexdump but there must be a
> > better way by looking at an include file?
>
> From running u-boot, => env print
>
> > What is the best way to set the list of vars that you wish to be
> > allowed to be imported from a FLASH env?
>
> Ideally none, and if you really want to make sure something can be
> pulled in from external env, then:
> #define CONFIG_ENV_FLAGS_LIST_STATIC "var1:dw,var2:dw"
Marek,
I can't seem to understand CONFIG_ENV_FLAGS_LIST_STATIC vs
CONFIG_ENF_FLAGS_LIST_DEFAULT. The code seems convoluted and
experimentally I am just as confused.
It seems that as soon as you define CONFIG_ENV_WRITEABLE_LIST=y then
all variables defined elsewhere (ie CONFIG_EXTRA_ENV_SETTINGS
CONFIG_BOOTCOMMAND) can no longer be imported from an env (they are
present if you clobber your flash env but not if anything is written
to it).
I quite simply want only the following environment:
kernel_addr_r=0x0200
mmcbootpart=4
ustate=1
bootcmd setenv bootargs root=/dev/mmcblk0p${mmcbootpart} rootwait rw;
load mmc 0:${mmcbootpart} ${kernel_addr_r} boot/kernel.itb && bootm
${kernel_addr_r} - ${fdtcontroladdr}
and the only variables with flags I want to be able to be overridden
from MMC_ENV are:
mmcbootpart:dw
usate:dw
It is too bad this can't be done via defconfig - perhaps when I
finally understand it I can submit a patch to move it to Kconfig.
>
> And those config options I had enabled in u-boot defconfig:
>
> CONFIG_CMD_ENV_CALLBACK=y
> CONFIG_CMD_ENV_FLAGS=y
> CONFIG_ENV_IS_NOWHERE=y
> CONFIG_ENV_IS_IN_MMC=y
> CONFIG_ENV_APPEND=y
> CONFIG_ENV_WRITEABLE_LIST=y
> CONFIG_ENV_ACCESS_IGNORE_FORCE=y
Do you really define both ENV_IS_NOWHERE and ENV_IS_IN_MMC? From what
I see if you define ENV_IS_NOWHERE none of the others will be used.
Best regards,
Tim
Re: [PATCH v2 00/10] spi: dw: Add support for DUAL/QUAD/OCTAL modes
On 4/2/21 7:05 PM, Sean Anderson wrote:
This series adds support for enhanced SPI modes. It was tested on a K210 (DWC
SSI with QSPI flash).
If anyone has a designware device with QSPI flash attached (especially a DW SSI
APB device), I'd greatly appreciate them testing out this patch series. Given
that there has been no testing of v2 over the past month, I don't think lack of
testing should hold up this series.
Changes in v3:
- Dropped merged patches
- Rebased on u-boot/master
Changes in v2:
- Add more information to exec_op debug message
- Actually mask interrupts
- Merge CAP_{DUAL,QUAD,OCTAL} into CAP_ENHANCED
- Fix some inconsistencies in register naming and usage
- Moved some hunks between commits so things make more sense
Sean Anderson (10):
mtd: spi-mem: Export spi_mem_default_supports_op
spi: spi-mem: Add debug message for spi-mem ops
spi: dw: Log status register on timeout
spi: dw: Actually mask interrupts
spi: dw: Switch to capabilities
spi: dw: Rewrite poll_transfer logic
spi: dw: Add ENHANCED cap
spi: dw: Define registers for enhanced mode
spi: dw: Support enhanced SPI
spi: dw: Support clock stretching
drivers/spi/designware_spi.c | 647 ---
drivers/spi/spi-mem.c| 7 +
include/spi-mem.h| 3 +
3 files changed, 451 insertions(+), 206 deletions(-)
Looks like I forgot to bump the version. This should be v3. I can resend if
necessary.
--Sean
[PATCH v2 09/10] spi: dw: Support enhanced SPI
This adds support for DUAL/QUAD/OCTAL transfers. This adds
dw_spi_supports_op to do some sanity checks which would otherwise live in
exec_op. We only support byte transfers, but as far as I could tell only
bytes are supported by mem_ops (e.g. every part of the opcode has nbytes).
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/spi/designware_spi.c | 136 ++-
1 file changed, 119 insertions(+), 17 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index e110c5bca1..64a3a8556b 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -218,7 +218,8 @@ static u32 dw_spi_update_cr0(struct dw_spi_priv *priv)
priv->bits_per_word - 1)
| FIELD_PREP(DWC_SSI_CTRLR0_FRF_MASK, priv->type)
| FIELD_PREP(DWC_SSI_CTRLR0_MODE_MASK, priv->mode)
- | FIELD_PREP(DWC_SSI_CTRLR0_TMOD_MASK, priv->tmode);
+ | FIELD_PREP(DWC_SSI_CTRLR0_TMOD_MASK, priv->tmode)
+ | FIELD_PREP(DWC_SSI_CTRLR0_SPI_FRF_MASK, priv->spi_frf);
} else {
if (priv->caps & DW_SPI_CAP_DFS32)
cr0 = FIELD_PREP(CTRLR0_DFS_32_MASK,
@@ -229,12 +230,36 @@ static u32 dw_spi_update_cr0(struct dw_spi_priv *priv)
cr0 |= FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
| FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
- | FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
+ | FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode)
+ | FIELD_PREP(CTRLR0_SPI_FRF_MASK, priv->spi_frf);
}
return cr0;
}
+static u32 dw_spi_update_spi_cr0(const struct spi_mem_op *op)
+{
+ uint trans_type, wait_cycles;
+
+ /* This assumes support_op has filtered invalid types */
+ if (op->addr.buswidth == 1)
+ trans_type = SPI_CTRLR0_TRANS_TYPE_1_1_X;
+ else if (op->cmd.buswidth == 1)
+ trans_type = SPI_CTRLR0_TRANS_TYPE_1_X_X;
+ else
+ trans_type = SPI_CTRLR0_TRANS_TYPE_X_X_X;
+
+ if (op->dummy.buswidth)
+ wait_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
+ else
+ wait_cycles = 0;
+
+ return FIELD_PREP(SPI_CTRLR0_TRANS_TYPE_MASK, trans_type)
+ | FIELD_PREP(SPI_CTRLR0_ADDR_L_MASK, op->addr.nbytes * 2)
+ | FIELD_PREP(SPI_CTRLR0_INST_L_MASK, INST_L_8)
+ | FIELD_PREP(SPI_CTRLR0_WAIT_CYCLES_MASK, wait_cycles)
+}
+
static int request_gpio_cs(struct udevice *bus)
{
#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
@@ -619,6 +644,13 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int
bitlen,
u32 val, cs;
uint frames;
+ /* DUAL/QUAD/OCTAL only supported by exec_op for now */
+ if (priv->mode & (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
+ SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL))
+ return -1;
+
+ priv->spi_frf = CTRLR0_SPI_FRF_BYTE;
+
/* spi core configured to do 8 bit transfers */
if (bitlen % priv->bits_per_word) {
dev_err(dev, "Non byte aligned SPI transfer.\n");
@@ -697,6 +729,9 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int
bitlen,
/*
* This function is necessary for reading SPI flash with the native CS
* c.f. https://lkml.org/lkml/2015/12/23/132
+ *
+ * It also lets us handle DUAL/QUAD/OCTAL transfers in a much more idiomatic
+ * way.
*/
static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
{
@@ -707,37 +742,72 @@ static int dw_spi_exec_op(struct spi_slave *slave, const
struct spi_mem_op *op)
struct spi_mem_op *mut_op = (struct spi_mem_op *)op;
u8 op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
u8 op_buf[op_len];
- u32 cr0, val;
+ u32 cr0, spi_cr0, val;
+
+ /* Only bytes are supported for spi-mem transfers */
+ if (priv->bits_per_word != 8)
+ return -EINVAL;
+
+ switch (op->data.buswidth) {
+ case 0:
+ case 1:
+ priv->spi_frf = CTRLR0_SPI_FRF_BYTE;
+ break;
+ case 2:
+ priv->spi_frf = CTRLR0_SPI_FRF_DUAL;
+ break;
+ case 4:
+ priv->spi_frf = CTRLR0_SPI_FRF_QUAD;
+ break;
+ case 8:
+ priv->spi_frf = CTRLR0_SPI_FRF_OCTAL;
+ break;
+ /* BUG: should have been filtered out by supports_op */
+ default:
+ return -EINVAL;
+ }
if (read)
- priv->tmode = CTRLR0_TMOD_EPROMREAD;
+ if (priv->spi_frf == CTRLR0_SPI_FRF_BYTE)
+ priv->tmode = CTRLR0_TMOD_EPROMREAD;
+ else
+ priv->tmode = CTRLR0_TMOD_RO;
else
priv->tmode = CTRLR0_TMOD_TO;
c
[PATCH v2 10/10] spi: dw: Support clock stretching
We don't always read/write to the FIFO fast enough. Enable clock stretching for enhanced SPI transfers. This is only possible with DWC SSI devices more recent than 1.01a. We also need to set the RXFTLR register to tell the device when to start reciving again. In particular, the default of 0 will result in the device never restarting reception if there is an overflow. On the transmit side, we need to set CTRL1 so that the device knows when to keep stretching the clock if the FIFO is empty. Signed-off-by: Sean Anderson --- (no changes since v1) drivers/spi/designware_spi.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 64a3a8556b..44fb679fdb 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -258,6 +258,7 @@ static u32 dw_spi_update_spi_cr0(const struct spi_mem_op *op) | FIELD_PREP(SPI_CTRLR0_ADDR_L_MASK, op->addr.nbytes * 2) | FIELD_PREP(SPI_CTRLR0_INST_L_MASK, INST_L_8) | FIELD_PREP(SPI_CTRLR0_WAIT_CYCLES_MASK, wait_cycles) + | SPI_CTRLR0_CLK_STRETCH_EN; } static int request_gpio_cs(struct udevice *bus) @@ -360,6 +361,9 @@ static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv) priv->fifo_len = (fifo == 1) ? 0 : fifo; dw_write(priv, DW_SPI_TXFTLR, 0); } + + /* Set receive fifo interrupt level register for clock stretching */ + dw_write(priv, DW_SPI_RXFTLR, priv->fifo_len - 1); } /* @@ -782,8 +786,7 @@ static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) dw_write(priv, DW_SPI_SSIENR, 0); dw_write(priv, DW_SPI_CTRLR0, cr0); - if (read) - dw_write(priv, DW_SPI_CTRLR1, op->data.nbytes - 1); + dw_write(priv, DW_SPI_CTRLR1, op->data.nbytes - 1); if (priv->spi_frf != CTRLR0_SPI_FRF_BYTE) dw_write(priv, DW_SPI_SPI_CTRL0, spi_cr0); dw_write(priv, DW_SPI_SSIENR, 1); -- 2.31.0
[PATCH v2 08/10] spi: dw: Define registers for enhanced mode
This adds some registers needed for DUAL/QUAD/OCTAL modes. It also adds the
fields in (R)ISR so we can check for over-/under-flow.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- Fix some inconsistencies in register naming and usage
drivers/spi/designware_spi.c | 60 ++--
1 file changed, 57 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index c2639141c6..e110c5bca1 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -56,6 +56,8 @@
#define DW_SPI_IDR 0x58
#define DW_SPI_VERSION 0x5c
#define DW_SPI_DR 0x60
+#define DW_SPI_RX_SAMPLE_DLY 0xf0
+#define DW_SPI_SPI_CTRL0 0xf4
/* Bit fields in CTRLR0 */
/*
@@ -80,8 +82,8 @@
#define CTRLR0_TMOD_RO 0x2 /* recv only */
#define CTRLR0_TMOD_EPROMREAD 0x3 /* eeprom read mode */
-#define CTRLR0_SLVOE_OFFSET10
-#define CTRLR0_SRL_OFFSET 11
+#define CTRLR0_SLVOE_OFFSETBIT(10)
+#define CTRLR0_SRL BIT(11)
#define CTRLR0_CFS_MASKGENMASK(15, 12)
/* Only present when SSI_MAX_XFER_SIZE=32 */
@@ -92,13 +94,15 @@
#define CTRLR0_SPI_FRF_BYTE0x0
#defineCTRLR0_SPI_FRF_DUAL 0x1
#defineCTRLR0_SPI_FRF_QUAD 0x2
+#defineCTRLR0_SPI_FRF_OCTAL0x3
/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
#define DWC_SSI_CTRLR0_DFS_MASKGENMASK(4, 0)
#define DWC_SSI_CTRLR0_FRF_MASKGENMASK(7, 6)
#define DWC_SSI_CTRLR0_MODE_MASK GENMASK(9, 8)
#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
-#define DWC_SSI_CTRLR0_SRL_OFFSET 13
+#define DWC_SSI_CTRLR0_SRL BIT(13)
+#define DWC_SSI_CTRLR0_SSTEBIT(14)
#define DWC_SSI_CTRLR0_SPI_FRF_MASKGENMASK(23, 22)
/* Bit fields in SR, 7 bits */
@@ -111,6 +115,56 @@
#define SR_TX_ERR BIT(5)
#define SR_DCOLBIT(6)
+/* Bit fields in (R)ISR */
+
+/* TX FIFO Empty */
+#define ISR_TXEI BIT(0)
+/* TX FIFO Overflow */
+#define ISR_TXOI BIT(1)
+/* RX FIFO Underflow */
+#define ISR_RXUI BIT(2)
+/* RX FIFO Overflow */
+#define ISR_RXOI BIT(3)
+/* RX FIFO Full */
+#define ISR_RXFI BIT(4)
+/* Multi-master contention */
+#define ISR_MSTI BIT(5)
+/* XIP Receive FIFO Overflow */
+#define ISR_XRXOI BIT(6)
+/* TX FIFO Underflow */
+#define ISR_TXUI BIT(7)
+/* AXI Error */
+#define ISR_AXIE BIT(8)
+/* SPI TX Error */
+#define ISR_SPITE BIT(10)
+/* SSI Done */
+#define ISR_DONE BIT(11)
+
+/* Bit fields in SPI_CTRLR0 */
+
+/*
+ * Whether the instruction or address use the value of SPI_FRF or use
+ * FRF_BYTE
+ */
+#define SPI_CTRLR0_TRANS_TYPE_MASK GENMASK(1, 0)
+#define SPI_CTRLR0_TRANS_TYPE_1_1_X0x0
+#define SPI_CTRLR0_TRANS_TYPE_1_X_X0x1
+#define SPI_CTRLR0_TRANS_TYPE_X_X_X0x2
+/* Address length in 4-bit units */
+#define SPI_CTRLR0_ADDR_L_MASK GENMASK(5, 2)
+/* Enable mode bits after address in XIP mode */
+#define SPI_CTRLR0_XIP_MD_BIT_EN BIT(7)
+/* Instruction length */
+#define SPI_CTRLR0_INST_L_MASK GENMASK(9, 8)
+#define INST_L_0 0x0
+#define INST_L_4 0x1
+#define INST_L_8 0x2
+#define INST_L_16 0x3
+/* Number of "dummy" cycles */
+#define SPI_CTRLR0_WAIT_CYCLES_MASKGENMASK(15, 11)
+/* Stretch the clock if the FIFO over/underflows */
+#define SPI_CTRLR0_CLK_STRETCH_EN BIT(30)
+
#define RX_TIMEOUT 1000/* timeout in ms */
struct dw_spi_plat {
--
2.31.0
[PATCH v2 07/10] spi: dw: Add ENHANCED cap
This capability corresponds to an SSIC_SPI_MODE of 1, 2, or 3. This
doesn't do much yet, but it does add support for detection and for
disallowing unsupported modes. Unfortunately, we cannot discriminate
between these modes (only that SSIC_SPI_MODE != 0), so we just pretend to
have DUAL+QUAD+OCTAL and let the slave determine what we actually use.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- Merge CAP_{DUAL,QUAD,OCTAL} into CAP_ENHANCED
drivers/spi/designware_spi.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 72cca14887..c2639141c6 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -129,6 +129,7 @@ struct dw_spi_priv {
#define DW_SPI_CAP_KEEMBAY_MST BIT(1) /* Unimplemented */
#define DW_SPI_CAP_DWC_SSI BIT(2)
#define DW_SPI_CAP_DFS32 BIT(3)
+#define DW_SPI_CAP_ENHANCEDBIT(4)
unsigned long caps;
unsigned long bus_clk_rate;
unsigned int freq; /* Default frequency */
@@ -141,6 +142,7 @@ struct dw_spi_priv {
u8 cs; /* chip select pin */
u8 tmode; /* TR/TO/RO/EEPROM */
u8 type;/* SPI/SSP/MicroWire */
+ u8 spi_frf; /* BYTE/DUAL/QUAD/OCTAL */
};
static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
@@ -249,6 +251,18 @@ static void spi_hw_init(struct udevice *bus, struct
dw_spi_priv *priv)
if (priv->caps & DW_SPI_CAP_DWC_SSI || !FIELD_GET(CTRLR0_DFS_MASK, cr0))
priv->caps |= DW_SPI_CAP_DFS32;
+ /*
+* If SPI_FRF exists that means we have DUAL, QUAD, or OCTAL. Since we
+* can't differentiate, just set a general ENHANCED cap and let the
+* slave decide what to use.
+*/
+ if (priv->caps & DW_SPI_CAP_DWC_SSI) {
+ if (FIELD_GET(DWC_SSI_CTRLR0_SPI_FRF_MASK, cr0))
+ priv->caps |= DW_SPI_CAP_ENHANCED;
+ } else if (FIELD_GET(CTRLR0_SPI_FRF_MASK, cr0)) {
+ priv->caps |= DW_SPI_CAP_ENHANCED;
+ }
+
dw_write(priv, DW_SPI_SSIENR, 1);
/*
@@ -746,13 +760,19 @@ static int dw_spi_set_mode(struct udevice *bus, uint mode)
{
struct dw_spi_priv *priv = dev_get_priv(bus);
+ if (!(priv->caps & DW_SPI_CAP_ENHANCED) &&
+ (mode & (SPI_RX_DUAL | SPI_TX_DUAL |
+SPI_RX_QUAD | SPI_TX_QUAD |
+SPI_RX_OCTAL | SPI_TX_OCTAL)))
+ return -EINVAL;
+
/*
* Can't set mode yet. Since this depends on if rx, tx, or
* rx & tx is requested. So we have to defer this to the
* real transfer function.
*/
priv->mode = mode;
- dev_dbg(bus, "mode=%d\n", priv->mode);
+ dev_dbg(bus, "mode=%x\n", mode);
return 0;
}
--
2.31.0
[PATCH v2 06/10] spi: dw: Rewrite poll_transfer logic
This rewrites poll_transfer, dw_writer, and dw_reader.
* We now use RO transfers (instead of always using TR). This eliminates the
need to send out dummy words, and simplifies the transmit logic.
* All parameters (except regs and bits_per_word) are passed explicitly.
* Most parameters have been made explicit (instead of being recalculated on
every loop).
* Transfers are measured in units of frames instead of bytes. This matches
the measurements used by the device and eliminates several divisions by
bits_per_word.
* We now check if we have over-/under-flowed the FIFO. This should help
prevent hangs when the device stops the transfer and U-Boot doesn't
realize it (and then waits for the remaining data forever). TXUI is not
present in DW_APB_SSI, but in the worst case we just don't write data.
Unfortunately, this doesn't seem to solve all problems, and there are
some remaining bugs (such as some transfers containing all 1s or all 0s)
when we have many fifo overflows. This is solved for DWC devices by
enabling clock stretching.
* poll_transfer is now used by dw_spi_exec_op as well as xfer.
* There are separate inner loops for 8-, 16-, and 32-bit frame sizes. This
should hopefully reduce the amount of over-/under-flows. However, I
haven't done exhaustive testing to ensure this is really necessary. In
particular, I was never able to prevent read overflows at 50MHz clock
speed.
These changes should probably have been split up into several commits, but
several depend on each other, and it would be difficult to break this up
while preserving bisectability.
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/spi/designware_spi.c | 284 +--
1 file changed, 171 insertions(+), 113 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 6375e6d778..72cca14887 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -134,14 +134,10 @@ struct dw_spi_priv {
unsigned int freq; /* Default frequency */
unsigned int mode;
- const void *tx;
- const void *tx_end;
- void *rx;
- void *rx_end;
u32 fifo_len; /* depth of the FIFO buffer */
int bits_per_word;
- int len;
+ int frames; /* Number of frames in the transfer */
u8 cs; /* chip select pin */
u8 tmode; /* TR/TO/RO/EEPROM */
u8 type;/* SPI/SSP/MicroWire */
@@ -372,14 +368,24 @@ static int dw_spi_probe(struct udevice *bus)
return 0;
}
-/* Return the max entries we can fill into tx fifo */
-static inline u32 tx_max(struct dw_spi_priv *priv)
+/**
+ * dw_writer() - Write data frames to the tx fifo
+ * @priv: Driver private info
+ * @tx: The tx buffer
+ * @idx: The number of data frames already transmitted
+ * @tx_frames: The number of data frames left to transmit
+ * @rx_frames: The number of data frames left to receive (0 if only
+ * transmitting)
+ * @frame_bytes: The number of bytes taken up by one data frame
+ *
+ * This function writes up to @tx_frames data frames using data from @tx[@idx].
+ *
+ * Return: The number of frames read
+ */
+static uint dw_writer(struct dw_spi_priv *priv, const void *tx, uint idx,
+ uint tx_frames, uint rx_frames, uint frame_bytes)
{
- u32 tx_left, tx_room, rxtx_gap;
-
- tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
- tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
-
+ u32 tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
/*
* Another concern is about the tx/rx mismatch, we
* thought about using (priv->fifo_len - rxflr - txflr) as
@@ -388,67 +394,131 @@ static inline u32 tx_max(struct dw_spi_priv *priv)
* shift registers. So a control from sw point of
* view is taken.
*/
- rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
- (priv->bits_per_word >> 3);
+ u32 rxtx_gap = rx_frames - tx_frames;
+ u32 count = min3(tx_frames, tx_room, (u32)(priv->fifo_len - rxtx_gap));
+ u32 *dr = priv->regs + DW_SPI_DR;
- return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
-}
+ if (!count)
+ return 0;
-/* Return the max entries we should read out of rx fifo */
-static inline u32 rx_max(struct dw_spi_priv *priv)
-{
- u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
-
- return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
-}
-
-static void dw_writer(struct dw_spi_priv *priv)
-{
- u32 max = tx_max(priv);
- u32 txw = 0x;
-
- while (max--) {
- /* Set the tx word if the transfer's original "tx" is not null
*/
- if (priv->tx_end - priv->len) {
- if (priv->bits_p
[PATCH v2 05/10] spi: dw: Switch to capabilities
Since Linux commit cc760f3143f5 ("spi: dw: Convert CS-override to DW SPI
capabilities"), the Linux driver has used capability flags instead of
using ad-hoc flags and functions. This is a great idea, and we should use
it as well.
The .data field in the compatible array has switched from being an
initialization function to being a set of default capabilities. This is
necessary since some capabilities cannot be determined at runtime.
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/spi/designware_spi.c | 151 +--
1 file changed, 73 insertions(+), 78 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 4ef948a0b9..6375e6d778 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -123,9 +123,13 @@ struct dw_spi_priv {
struct reset_ctl_bulk resets;
struct gpio_desc cs_gpio; /* External chip-select gpio */
- u32 (*update_cr0)(struct dw_spi_priv *priv);
-
void __iomem *regs;
+/* DW SPI capabilities */
+#define DW_SPI_CAP_CS_OVERRIDE BIT(0) /* Unimplemented */
+#define DW_SPI_CAP_KEEMBAY_MST BIT(1) /* Unimplemented */
+#define DW_SPI_CAP_DWC_SSI BIT(2)
+#define DW_SPI_CAP_DFS32 BIT(3)
+ unsigned long caps;
unsigned long bus_clk_rate;
unsigned int freq; /* Default frequency */
unsigned int mode;
@@ -135,7 +139,6 @@ struct dw_spi_priv {
void *rx;
void *rx_end;
u32 fifo_len; /* depth of the FIFO buffer */
- u32 max_xfer; /* Maximum transfer size (in bits) */
int bits_per_word;
int len;
@@ -154,51 +157,30 @@ static inline void dw_write(struct dw_spi_priv *priv, u32
offset, u32 val)
__raw_writel(val, priv->regs + offset);
}
-static u32 dw_spi_dw16_update_cr0(struct dw_spi_priv *priv)
+static u32 dw_spi_update_cr0(struct dw_spi_priv *priv)
{
- return FIELD_PREP(CTRLR0_DFS_MASK, priv->bits_per_word - 1)
-| FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
-| FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
-| FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
-}
+ u32 cr0;
-static u32 dw_spi_dw32_update_cr0(struct dw_spi_priv *priv)
-{
- return FIELD_PREP(CTRLR0_DFS_32_MASK, priv->bits_per_word - 1)
-| FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
-| FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
-| FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
-}
-
-static u32 dw_spi_dwc_update_cr0(struct dw_spi_priv *priv)
-{
- return FIELD_PREP(DWC_SSI_CTRLR0_DFS_MASK, priv->bits_per_word - 1)
-| FIELD_PREP(DWC_SSI_CTRLR0_FRF_MASK, priv->type)
-| FIELD_PREP(DWC_SSI_CTRLR0_MODE_MASK, priv->mode)
-| FIELD_PREP(DWC_SSI_CTRLR0_TMOD_MASK, priv->tmode);
-}
-
-static int dw_spi_apb_init(struct udevice *bus, struct dw_spi_priv *priv)
-{
- /* If we read zeros from DFS, then we need to use DFS_32 instead */
- dw_write(priv, DW_SPI_SSIENR, 0);
- dw_write(priv, DW_SPI_CTRLR0, 0x);
- if (FIELD_GET(CTRLR0_DFS_MASK, dw_read(priv, DW_SPI_CTRLR0))) {
- priv->max_xfer = 16;
- priv->update_cr0 = dw_spi_dw16_update_cr0;
+ if (priv->caps & DW_SPI_CAP_DWC_SSI) {
+ cr0 = FIELD_PREP(DWC_SSI_CTRLR0_DFS_MASK,
+priv->bits_per_word - 1)
+ | FIELD_PREP(DWC_SSI_CTRLR0_FRF_MASK, priv->type)
+ | FIELD_PREP(DWC_SSI_CTRLR0_MODE_MASK, priv->mode)
+ | FIELD_PREP(DWC_SSI_CTRLR0_TMOD_MASK, priv->tmode);
} else {
- priv->max_xfer = 32;
- priv->update_cr0 = dw_spi_dw32_update_cr0;
+ if (priv->caps & DW_SPI_CAP_DFS32)
+ cr0 = FIELD_PREP(CTRLR0_DFS_32_MASK,
+priv->bits_per_word - 1);
+ else
+ cr0 = FIELD_PREP(CTRLR0_DFS_MASK,
+priv->bits_per_word - 1);
+
+ cr0 |= FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
+ | FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
+ | FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
}
- return 0;
-}
-
-static int dw_spi_dwc_init(struct udevice *bus, struct dw_spi_priv *priv)
-{
- priv->max_xfer = 32;
- priv->update_cr0 = dw_spi_dwc_update_cr0;
- return 0;
+ return cr0;
}
static int request_gpio_cs(struct udevice *bus)
@@ -251,8 +233,26 @@ static int dw_spi_of_to_plat(struct udevice *bus)
/* Restart the controller, disable all interrupts, clean rx fifo */
static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv)
{
+ u32 cr0;
+
dw_write(priv, DW_SPI_SSIENR, 0);
dw_write(priv, DW_SPI_IMR, 0);
+
+ /*
+* Detect features by writing CTRLR0 and seeing which fie
[PATCH v2 04/10] spi: dw: Actually mask interrupts
Writing 1s to this register *unmasks* interrupts. Mask them instead.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- Actually mask interrupts
drivers/spi/designware_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 519d6e32bd..4ef948a0b9 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -252,7 +252,7 @@ static int dw_spi_of_to_plat(struct udevice *bus)
static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv)
{
dw_write(priv, DW_SPI_SSIENR, 0);
- dw_write(priv, DW_SPI_IMR, 0xff);
+ dw_write(priv, DW_SPI_IMR, 0);
dw_write(priv, DW_SPI_SSIENR, 1);
/*
--
2.31.0
[PATCH v2 02/10] spi: spi-mem: Add debug message for spi-mem ops
This prints some basic metadata about the SPI memory op. This information may be used to debug SPI drivers (e.g. determining the expected SPI mode). It is also helpful for verifying that the data on the wire matches the data intended to be transmitted (e.g. with a logic analyzer). The opcode is printed with a format of %02Xh to match the notation commonly used in flash datasheets. Signed-off-by: Sean Anderson Reviewed-by: Pratyush Yadav --- (no changes since v2) Changes in v2: - Add more information to exec_op debug message drivers/spi/spi-mem.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index c095ae9505..6772367ef7 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -220,6 +220,13 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) int ret; int i; + dev_dbg(slave->dev, + "exec %02Xh %u-%u-%u addr=%llx dummy cycles=%u data bytes=%u\n", + op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, + op->data.buswidth, op->addr.val, + op->dummy.buswidth ? op->dummy.nbytes * 8 / op->dummy.buswidth : 0, + op->data.nbytes); + if (!spi_mem_supports_op(slave, op)) return -ENOTSUPP; -- 2.31.0
[PATCH v2 03/10] spi: dw: Log status register on timeout
This logs the status register on timeout, so it is easier to determine the
cause of the failure.
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/spi/designware_spi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 742121140d..519d6e32bd 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -552,6 +552,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int
bitlen,
if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
(val & SR_TF_EMPT) && !(val & SR_BUSY),
RX_TIMEOUT * 1000)) {
+ dev_dbg(bus, "timed out; sr=%x\n", dw_read(priv, DW_SPI_SR));
ret = -ETIMEDOUT;
}
@@ -639,6 +640,8 @@ static int dw_spi_exec_op(struct spi_slave *slave, const
struct spi_mem_op *op)
if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
(val & SR_TF_EMPT) && !(val & SR_BUSY),
RX_TIMEOUT * 1000)) {
+ dev_dbg(bus, "timed out; sr=%x\n",
+ dw_read(priv, DW_SPI_SR));
ret = -ETIMEDOUT;
}
}
--
2.31.0
[PATCH v2 01/10] mtd: spi-mem: Export spi_mem_default_supports_op
This is useful for extending the default functionality. This mirrors the
change in Linux commit 46109648052f ("spi: spi-mem: export
spi_mem_default_supports_op()").
Signed-off-by: Sean Anderson
Reviewed-by: Bin Meng
Reviewed-by: Pratyush Yadav
---
(no changes since v1)
include/spi-mem.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/spi-mem.h b/include/spi-mem.h
index 8be3e2bf6b..a404d3bbee 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -236,6 +236,9 @@ spi_controller_dma_unmap_mem_op_data(struct spi_controller
*ctlr,
int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op);
+bool spi_mem_default_supports_op(struct spi_slave *slave,
+const struct spi_mem_op *op);
+
bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op);
int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op);
--
2.31.0
[PATCH v2 00/10] spi: dw: Add support for DUAL/QUAD/OCTAL modes
This series adds support for enhanced SPI modes. It was tested on a K210 (DWC
SSI with QSPI flash).
If anyone has a designware device with QSPI flash attached (especially a DW SSI
APB device), I'd greatly appreciate them testing out this patch series. Given
that there has been no testing of v2 over the past month, I don't think lack of
testing should hold up this series.
Changes in v3:
- Dropped merged patches
- Rebased on u-boot/master
Changes in v2:
- Add more information to exec_op debug message
- Actually mask interrupts
- Merge CAP_{DUAL,QUAD,OCTAL} into CAP_ENHANCED
- Fix some inconsistencies in register naming and usage
- Moved some hunks between commits so things make more sense
Sean Anderson (10):
mtd: spi-mem: Export spi_mem_default_supports_op
spi: spi-mem: Add debug message for spi-mem ops
spi: dw: Log status register on timeout
spi: dw: Actually mask interrupts
spi: dw: Switch to capabilities
spi: dw: Rewrite poll_transfer logic
spi: dw: Add ENHANCED cap
spi: dw: Define registers for enhanced mode
spi: dw: Support enhanced SPI
spi: dw: Support clock stretching
drivers/spi/designware_spi.c | 647 ---
drivers/spi/spi-mem.c| 7 +
include/spi-mem.h| 3 +
3 files changed, 451 insertions(+), 206 deletions(-)
--
2.31.0
Re: [PATCH v6 0/6] wdt: Add support for watchdogs on Kendryte K210
On 3/10/21 9:02 PM, Sean Anderson wrote: Please merge! I don't want to have to keep rebasing. Changes in v6: - Rebase on u-boot/master Changes in v5: - Note dependency on "time: Fix get_ticks being non-monotonic" - Add a few signed-off-bys which were sent for version 1 - Rebase on u-boot/master Changes in v4: - Fix build error without CONFIG_CLK Changes in v2: - Fix fls being off-by-one when compared to log_2_n_round_up - Move watchdog enable to k210.dtsi as it does not depend on anything board-specific. Sean Anderson (6): wdt: dw: Switch to using fls for log2 wdt: dw: Switch to if(CONFIG()) instead of using #if wdt: dw: Enable the clock before using it wdt: dw: Free the clock on error riscv: Add watchdog bindings for the k210 riscv: Enable watchdog for the k210 arch/riscv/dts/k210.dtsi | 1 - board/sipeed/maix/Kconfig | 2 ++ drivers/watchdog/designware_wdt.c | 37 --- 3 files changed, 26 insertions(+), 14 deletions(-) Rick, can you pick this up for v2021.07? I would like to note that there have been no functional changes since v4, which I sent last September. --Sean
Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
On 3/30/21 1:26 AM, Green Wan wrote:
Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
allow different riscv hart perform setup code for each hart as early
as possible. Since all the harts enter the callback, they must be able
to run the same setup.
Signed-off-by: Green Wan
---
arch/riscv/cpu/cpu.c | 15 +++
arch/riscv/cpu/start.S | 14 ++
2 files changed, 29 insertions(+)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 85592f5bee..1652e51137 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -140,3 +140,18 @@ int arch_early_init_r(void)
{
return riscv_cpu_probe();
}
+
+/**
+ * riscv_hart_early_init() - A dummy function called by
+ * ./arch/riscv/cpu/start.S to allow to disable/enable features of each core.
+ * For example, turn on or off the functional block of CPU harts.
+ *
+ * In a multi-core system, this function must not access shared resources.
+ *
+ * Any access to such resources would probably be better done with
+ * available_harts_lock held. However, I doubt that any such access will be
+ * necessary.
+ */
+__weak void riscv_hart_early_init(void)
+{
+}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 8589509e01..ab73008f23 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -117,6 +117,20 @@ call_board_init_f_0:
mv sp, a0
#endif
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+ /*
+* Jump to riscv_hart_early_init() to perform init for each core. Not
+* expect to access gd since gd is not initialized. All operations in
the
+* function should affect core itself only. In multi-core system, any
access
+* to common resource or registers outside core should be avoided or
need a
+* protection for multicore.
+*
+* A dummy implementation is provided in ./arch/riscv/cpu/cpu.c.
+*/
+call_riscv_hart_early_init:
+ jal riscv_hart_early_init
+#endif
+
I wonder if we could move the calls to icache_enable and dcache_enable
into this function. Though this would have the consequence of enabling
caches on all harts for CPUs which previously only enabled them for the
boot hart. I think ax25 is the only CPU which currently does this. Bin,
would this be an issue?
--Sean
#ifndef CONFIG_XIP
/*
* Pick hart to initialize global data and run U-Boot. The other harts
Re: [PATCH v8 04/28] spi: spi-mem: add spi_mem_dtr_supports_op()
On 4/1/21 3:31 PM, Pratyush Yadav wrote:
spi_mem_default_supports_op() rejects DTR ops by default to ensure that
the controller drivers that haven't been updated with DTR support
continue to reject them. It also makes sure that controllers that don't
support DTR mode at all (which is most of them at the moment) also
reject them.
This means that controller drivers that want to support DTR mode can't
use spi_mem_default_supports_op(). Driver authors have to roll their own
supports_op() function and mimic the buswidth checks. See
spi-cadence-quadspi.c for example. Or even worse, driver authors might
skip it completely or get it wrong.
Add spi_mem_dtr_supports_op(). It provides a basic sanity check for DTR
ops and performs the buswidth requirement check. Move the logic for
checking buswidth in spi_mem_default_supports_op() to a separate
function so the logic is not repeated twice.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 22 +++---
include/spi-mem.h | 2 ++
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 541cd0e5a7..be1737a2c6 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -145,8 +145,8 @@ static int spi_check_buswidth_req(struct spi_slave *slave,
u8 buswidth, bool tx)
return -ENOTSUPP;
}
-bool spi_mem_default_supports_op(struct spi_slave *slave,
-const struct spi_mem_op *op)
+static bool spi_mem_check_buswidth(struct spi_slave *slave,
+ const struct spi_mem_op *op)
{
if (spi_check_buswidth_req(slave, op->cmd.buswidth, true))
return false;
@@ -164,13 +164,29 @@ bool spi_mem_default_supports_op(struct spi_slave *slave,
op->data.dir == SPI_MEM_DATA_OUT))
return false;
+ return true;
+}
+
+bool spi_mem_dtr_supports_op(struct spi_slave *slave,
+const struct spi_mem_op *op)
+{
+ if (op->cmd.nbytes != 2)
+ return false;
Why does the command bytes need to be 2?
--Sean
+
+ return spi_mem_check_buswidth(slave, op);
+}
+EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op);
+
+bool spi_mem_default_supports_op(struct spi_slave *slave,
+const struct spi_mem_op *op)
+{
if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
return false;
if (op->cmd.nbytes != 1)
return false;>
- return true;
+ return spi_mem_check_buswidth(slave, op);
}
EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
diff --git a/include/spi-mem.h b/include/spi-mem.h
index dc53b517c1..37a9128c5b 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -249,6 +249,8 @@ spi_controller_dma_unmap_mem_op_data(struct spi_controller
*ctlr,
int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op);
bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op);
+bool spi_mem_dtr_supports_op(struct spi_slave *slave,
+const struct spi_mem_op *op);
bool spi_mem_default_supports_op(struct spi_slave *slave,
const struct spi_mem_op *op);
Re: [PATCH v8 02/28] spi: spi-mem: allow specifying a command's extension
On 4/1/21 3:31 PM, Pratyush Yadav wrote:
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the opcode. When it is "hex" an additional opcode byte based
is sent with the command whose value can be anything.
So, make opcode a 16-bit value and add a 'nbytes', similar to how
multiple address widths are handled.
All usages of sizeof(op->cmd.opcode) also need to be changed to be
op->cmd.nbytes because that is the actual indicator of opcode size.
Signed-off-by: Pratyush Yadav
---
drivers/spi/mtk_snfi_spi.c | 3 +--
drivers/spi/spi-mem-nodm.c | 4 ++--
drivers/spi/spi-mem.c | 13 +++--
include/spi-mem.h | 6 +-
4 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/mtk_snfi_spi.c b/drivers/spi/mtk_snfi_spi.c
index b6ab5fa3ad..65d0ce0981 100644
--- a/drivers/spi/mtk_snfi_spi.c
+++ b/drivers/spi/mtk_snfi_spi.c
@@ -64,8 +64,7 @@ static int mtk_snfi_adjust_op_size(struct spi_slave *slave,
* or the output+input data must not exceed the GPRAM size.
*/
- nbytes = sizeof(op->cmd.opcode) + op->addr.nbytes +
- op->dummy.nbytes;
+ nbytes = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
if (nbytes + op->data.nbytes <= SNFI_GPRAM_SIZE)
return 0;
diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c
index 765f05fe54..db54101383 100644
--- a/drivers/spi/spi-mem-nodm.c
+++ b/drivers/spi/spi-mem-nodm.c
@@ -27,7 +27,7 @@ int spi_mem_exec_op(struct spi_slave *slave,
tx_buf = op->data.buf.out;
}
- op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
op_buf = calloc(1, op_len);
ret = spi_claim_bus(slave);
@@ -89,7 +89,7 @@ int spi_mem_adjust_op_size(struct spi_slave *slave,
{
unsigned int len;
- len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
if (slave->max_write_size && len > slave->max_write_size)
return -EINVAL;
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 427f7c13c5..541cd0e5a7 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -167,6 +167,9 @@ bool spi_mem_default_supports_op(struct spi_slave *slave,
if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
return false;
+ if (op->cmd.nbytes != 1)
+ return false;
+
return true;
}
EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
@@ -273,8 +276,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
}
#ifndef __UBOOT__
- tmpbufsize = sizeof(op->cmd.opcode) + op->addr.nbytes +
-op->dummy.nbytes;
+ tmpbufsize = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
/*
* Allocate a buffer to transmit the CMD, ADDR cycles with kmalloc() so
@@ -289,7 +291,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
tmpbuf[0] = op->cmd.opcode;
xfers[xferpos].tx_buf = tmpbuf;
- xfers[xferpos].len = sizeof(op->cmd.opcode);
+ xfers[xferpos].len = op->cmd.nbytes;
xfers[xferpos].tx_nbits = op->cmd.buswidth;
spi_message_add_tail(&xfers[xferpos], &msg);
xferpos++;
@@ -353,7 +355,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
tx_buf = op->data.buf.out;
}
- op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
/*
* Avoid using malloc() here so that we can use this code in SPL where
@@ -442,8 +444,7 @@ int spi_mem_adjust_op_size(struct spi_slave *slave, struct
spi_mem_op *op)
if (!ops->mem_ops || !ops->mem_ops->exec_op) {
unsigned int len;
- len = sizeof(op->cmd.opcode) + op->addr.nbytes +
- op->dummy.nbytes;
+ len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
if (slave->max_write_size && len > slave->max_write_size)
return -EINVAL;
diff --git a/include/spi-mem.h b/include/spi-mem.h
index 9e6b044548..3e5b771045 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -17,6 +17,7 @@ struct udevice;
{ \
.buswidth = __buswidth, \
.opcode = __opcode, \
+ .nbytes = 1,\
}
#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \
Re: [PATCH v8 00/28] mtd: spi-nor-core: add xSPI Octal DTR support
On 4/1/21 3:31 PM, Pratyush Yadav wrote:
Hi,
This series adds support for octal DTR flashes in the SPI NOR framework,
As an overall question, is this the same as "DDR" mode?
--Sean
and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA
flashes. Reviving this series after a long hiatus.
The Cadence QSPI controller driver is also updated to run in Octal DTR
mode.
Tested on TI J721E for MT35XU512ABA and J7200 for S28HS512T. Also tested
on MT25QU512A for regressions.
Changes in v8:
- Rebase on latest master, fixing merge conflicts.
- Fix a regression related to address width that was discovered on
Linux.
- Port spi_mem_dtr_supports_op() from Linux and use it in Cadence qspi
driver.
- Do not set non-volatile Uniform Sector mode bit on S28HS512T. Instead
use Takahiro's non-uniform erase patch to enable non-uniform erases.
- Make sure spi_nor_write_reg() does not set data direction to out when
there is no data to write, like in write enable.
- Set buswidths to 0 before calling spi_nor_setup_op(), like how it is
done in Linux.
Changes in v7:
- Port back changes requested on the Linux series.
- Introduce the flag SPI_NOR_OCTAL_DTR_PP to indicate 8D page program
support since it can't be detected from SFDP.
- Re-order Profile 1.0 related defines by DWORD order.
- Drop local variables addr_width and dummy in spi_nor_read_sr()
spi_nor_read_fsr().
- Do not make having command opcode extension as a reserved field fatal.
- Update doc comment for spi_nor_parse_profile1() and
spi_nor_cypress_octal_dtr_enable() to add missing fields.
- Move rdsr parameter parsing to where opcode is parsed because it is
from the same DWORD.
- Convert a comment in Profile 1.0 parsing from multi-line to one line.
- Rename 'table' to 'dwords' in xSPI Profile 1.0 parsing.
- Update spi_nor_check_readop() and spi_nor_check_pp() to use
spi_nor_setup_op() so the buswidths are properly set up for DTR ops.
- Do not set Uniform Sector bit on the Cypress S28HS512T flash if it is
already set. It will avoid wearing out the non-volatile bit.
- Enable DQS for Micron MT35XU512ABA. No reason not to.
- Avoid enabling 4-byte addressing mode for all DTR ops instead of just
Octal DTR ops. This is based on the assumption that DTR ops can only
use 4-byte addressing.
- Make spi_nor_set_fixups() static.
- Add flag SPI_NOR_OCTAL_DTR_PP to both Cypress S28HS512T and Micron
MT35XU512ABA.
- Use values set up by spi-{rx,tx}-bus-width via device tree to
determine if the controller supports the op or not. Gives more
flexibility to choose protocol per-board.
- Use tiny SPI NOR on x530 because of size constraints.
Changes in v6:
- Use "# CONFIG_SPI_FLASH_SMART_HWCAPS is not set" instead of
"CONFIG_SPI_FLASH_SMART_HWCAPS=n" in x530_defconfig.
Changes in v5:
- Fix build breaking when CONFIG_SPL_SPI_FLASH_TINY is enabled because
spi-nor-tiny did not have spi_nor_remove().
- The build was breaking in x530 because of SPL size too big. Fix it by
the below changes.
- Re-introduce old hwcaps selection logic and put the new one behind a
config. This lets boards with size restrictions use the old logic
which takes up less space. The code was getting hard to manage with
the old code behind ifdefs. So, re-structure the old hwcaps selection
logic and move it into one function: spi_nor_adjust_hwcaps(). This
way, the common code just calls spi_nor_adjust_hwcaps(), but the old
or new hwcaps selection is used based on the config option selected.
- Put spi_nor_soft_reset() behind the config option SPI_NOR_SOFT_RESET.
- Rename the config option used for soft resetting on boot to
SPI_NOR_SOFT_RESET_ON_BOOT to make its intention clearer.
- Put the fixup hooks of MT35XU512ABA and S28HS512T flashes behind
config options to reduce code size on platforms that don't need them.
- Introduce spi_nor_set_fixups(). Earlier, the fixup members of each
flash was specified in spi-nor-ids.c. This meant they had to be
declared as extern in sf_internal.h. But since spi-nor-tiny.c also
uses it, and it doesn't have those fixups, they had to be put behind
in an ifdef. The ".fixups = " assignment in spi-nor-ids.c also had to
be put in an ifdef to account for spi-nor-tiny.c not having the fixup
hooks. On top of this, the fixup of each flash is behind the flash's
config.
All this lead to a soup of ifdefs that wasn't easy to digest. So don't
set the fixups in the common code. Instead, add a function in
spi-nor-core.c that sets the fixups of each flash. This isn't ideal,
but its the best compromise I could figure out.
- Build were breaking with boards that use spi-mem-nodm.c because it
doesn't have spi_mem_supports_op() which is needed for smart hwcaps
selection. Add an equivalent to spi_mem_default_supports_op() there.
- Replace uses of sizeof(op->cmd.opcode) with op->cmd.nbytes.
- Do not set quad_enable to NULL if the value is set to reserved
Re: [PATCH v8 01/28] spi: spi-mem: allow specifying whether an op is DTR or not
On 4/1/21 3:31 PM, Pratyush Yadav wrote:
Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 3 +++
include/spi-mem.h | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index c095ae9505..427f7c13c5 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -164,6 +164,9 @@ bool spi_mem_default_supports_op(struct spi_slave *slave,
op->data.dir == SPI_MEM_DATA_OUT))
return false;
+ if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
+ return false;
+
return true;
}
EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
diff --git a/include/spi-mem.h b/include/spi-mem.h
index 8be3e2bf6b..9e6b044548 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -71,6 +71,7 @@ enum spi_mem_data_dir {
* struct spi_mem_op - describes a SPI memory operation
* @cmd.buswidth: number of IO lines used to transmit the command
* @cmd.opcode: operation opcode
+ * @cmd.dtr: whether the command opcode should be sent in DTR mode or not
* @addr.nbytes: number of address bytes to send. Can be zero if the operation
* does not need to send an address
* @addr.buswidth: number of IO lines used to transmit the address cycles
@@ -78,10 +79,13 @@ enum spi_mem_data_dir {
* Note that only @addr.nbytes are taken into account in this
* address value, so users should make sure the value fits in the
* assigned number of bytes.
+ * @addr.dtr: whether the address should be sent in DTR mode or not
* @dummy.nbytes: number of dummy bytes to send after an opcode or address.
Can
* be zero if the operation does not require dummy bytes
* @dummy.buswidth: number of IO lanes used to transmit the dummy bytes
+ * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
* @data.buswidth: number of IO lanes used to send/receive the data
+ * @data.dtr: whether the data should be sent in DTR mode or not
* @data.dir: direction of the transfer
* @data.buf.in: input buffer
* @data.buf.out: output buffer
@@ -90,21 +94,25 @@ struct spi_mem_op {
struct {
u8 buswidth;
u8 opcode;
+ u8 dtr : 1;
} cmd;
struct {
u8 nbytes;
u8 buswidth;
+ u8 dtr : 1;
u64 val;
} addr;
struct {
u8 nbytes;
u8 buswidth;
+ u8 dtr : 1;
} dummy;
struct {
u8 buswidth;
+ u8 dtr : 1;
enum spi_mem_data_dir dir;
unsigned int nbytes;
/* buf.{in,out} must be DMA-able. */
I know this is following the Linux code, but are bitfields kosher for
U-Boot? This is more of a general question than a specific critique of
this code.
--Sean
Re: [PATCH v8 03/28] spi: spi-mem: export spi_mem_default_supports_op()
On 4/1/21 3:31 PM, Pratyush Yadav wrote: Controllers can use this function to perform basic sanity checking on the spi-mem op. Signed-off-by: Pratyush Yadav --- include/spi-mem.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/spi-mem.h b/include/spi-mem.h index 3e5b771045..dc53b517c1 100644 --- a/include/spi-mem.h +++ b/include/spi-mem.h @@ -250,6 +250,9 @@ int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op); bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op); +bool spi_mem_default_supports_op(struct spi_slave *slave, +const struct spi_mem_op *op); + int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op); bool spi_mem_default_supports_op(struct spi_slave *mem, Reviewed-by: Sean Anderson c.f. https://patchwork.ozlabs.org/project/uboot/patch/20210205041119.145784-5-sean...@gmail.com/
[PATCH 2/2] binman: Support adding sections to FMAPs
When used with hierarchical images, use the Chromium OS convention of
adding a section before all the subentries it contains.
Signed-off-by: Simon Glass
---
tools/binman/entries.rst | 13 +--
tools/binman/etype/fmap.py | 20 +++--
tools/binman/ftest.py | 25 ++
tools/binman/test/095_fmap_x86_section.dts | 2 +-
4 files changed, 51 insertions(+), 9 deletions(-)
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index a91211e93ed..f1c3b7de7ab 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -461,8 +461,12 @@ see www.flashrom.org/Flashrom for more information.
When used, this entry will be populated with an FMAP which reflects the
entries in the current image. Note that any hierarchy is squashed, since
-FMAP does not support this. Also, CBFS entries appear as a single entry -
-the sub-entries are ignored.
+FMAP does not support this. Sections are represented as an area appearing
+before its contents, so that it is possible to reconstruct the hierarchy
+from the FMAP by using the offset information. This convention does not
+seem to be documented, but is used in Chromium OS.
+
+CBFS entries appear as a single entry, i.e. the sub-entries are ignored.
@@ -804,6 +808,11 @@ Properties:
missing their contents. The second will produce an image but of
course it will not work.
+Properties:
+_allow_missing: True if this section permits external blobs to be
+missing their contents. The second will produce an image but of
+course it will not work.
+
Since a section is also an entry, it inherits all the properies of entries
too.
diff --git a/tools/binman/etype/fmap.py b/tools/binman/etype/fmap.py
index fe81c6f64a5..fc490292786 100644
--- a/tools/binman/etype/fmap.py
+++ b/tools/binman/etype/fmap.py
@@ -28,8 +28,12 @@ class Entry_fmap(Entry):
When used, this entry will be populated with an FMAP which reflects the
entries in the current image. Note that any hierarchy is squashed, since
-FMAP does not support this. Also, CBFS entries appear as a single entry -
-the sub-entries are ignored.
+FMAP does not support this. Sections are represented as an area appearing
+before its contents, so that it is possible to reconstruct the hierarchy
+from the FMAP by using the offset information. This convention does not
+seem to be documented, but is used in Chromium OS.
+
+CBFS entries appear as a single entry, i.e. the sub-entries are ignored.
"""
def __init__(self, section, etype, node):
super().__init__(section, etype, node)
@@ -45,6 +49,18 @@ class Entry_fmap(Entry):
tout.Debug("fmap: Add entry '%s' type '%s' (%s subentries)" %
(entry.GetPath(), entry.etype, ToHexSize(entries)))
if entries and entry.etype != 'cbfs':
+# Create an area for the section, which encompasses all entries
+# within it
+if entry.image_pos is None:
+pos = 0
+else:
+pos = entry.image_pos - entry.GetRootSkipAtStart()
+
+# Drop @ symbols in name
+name = entry.name.replace('@', '')
+areas.append(
+fmap_util.FmapArea(pos, entry.size or 0,
+ tools.FromUnicode(name), 0))
for subentry in entries.values():
_AddEntries(areas, subentry)
else:
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 217cd0a4249..1f94d99bcfb 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -1594,18 +1594,30 @@ class TestFunctional(unittest.TestCase):
self.assertEqual(1, fhdr.ver_major)
self.assertEqual(0, fhdr.ver_minor)
self.assertEqual(0, fhdr.base)
-expect_size = fmap_util.FMAP_HEADER_LEN + fmap_util.FMAP_AREA_LEN * 3
+expect_size = fmap_util.FMAP_HEADER_LEN + fmap_util.FMAP_AREA_LEN * 5
self.assertEqual(16 + 16 + expect_size, fhdr.image_size)
self.assertEqual(b'FMAP', fhdr.name)
-self.assertEqual(3, fhdr.nareas)
+self.assertEqual(5, fhdr.nareas)
fiter = iter(fentries)
+fentry = next(fiter)
+self.assertEqual(b'SECTION0', fentry.name)
+self.assertEqual(0, fentry.offset)
+self.assertEqual(16, fentry.size)
+self.assertEqual(0, fentry.flags)
+
fentry = next(fiter)
self.assertEqual(b'RO_U_BOOT', fentry.name)
self.assertEqual(0, fentry.offset)
self.assertEqual(4, fentry.size)
self.assertEqual(0, fentry.flags)
+fentry = next(fiter)
+self.assertEqual(b'SECTION1', fentry.name)
+self.assertEqual(16, fentry.offset)
+self.assertEqual(16, fentry.size)
+self.assertEqual(0, fentry.flags)
+
fentry = next(fi
[PATCH 1/2] binman: Tweak implementation of fmap
Use an interator in two of the fmap tests so it is easier to add new items. Also check the name first since that is the first indication that something is wrong. Use a variable for the expected size of the fmap to avoid repeating the code. Signed-off-by: Simon Glass --- tools/binman/ftest.py | 69 --- 1 file changed, 38 insertions(+), 31 deletions(-) diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 89fe6612e1b..217cd0a4249 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -1594,26 +1594,29 @@ class TestFunctional(unittest.TestCase): self.assertEqual(1, fhdr.ver_major) self.assertEqual(0, fhdr.ver_minor) self.assertEqual(0, fhdr.base) -self.assertEqual(16 + 16 + - fmap_util.FMAP_HEADER_LEN + - fmap_util.FMAP_AREA_LEN * 3, fhdr.image_size) +expect_size = fmap_util.FMAP_HEADER_LEN + fmap_util.FMAP_AREA_LEN * 3 +self.assertEqual(16 + 16 + expect_size, fhdr.image_size) self.assertEqual(b'FMAP', fhdr.name) self.assertEqual(3, fhdr.nareas) -for fentry in fentries: -self.assertEqual(0, fentry.flags) - -self.assertEqual(0, fentries[0].offset) -self.assertEqual(4, fentries[0].size) -self.assertEqual(b'RO_U_BOOT', fentries[0].name) - -self.assertEqual(16, fentries[1].offset) -self.assertEqual(4, fentries[1].size) -self.assertEqual(b'RW_U_BOOT', fentries[1].name) - -self.assertEqual(32, fentries[2].offset) -self.assertEqual(fmap_util.FMAP_HEADER_LEN + - fmap_util.FMAP_AREA_LEN * 3, fentries[2].size) -self.assertEqual(b'FMAP', fentries[2].name) +fiter = iter(fentries) + +fentry = next(fiter) +self.assertEqual(b'RO_U_BOOT', fentry.name) +self.assertEqual(0, fentry.offset) +self.assertEqual(4, fentry.size) +self.assertEqual(0, fentry.flags) + +fentry = next(fiter) +self.assertEqual(b'RW_U_BOOT', fentry.name) +self.assertEqual(16, fentry.offset) +self.assertEqual(4, fentry.size) +self.assertEqual(0, fentry.flags) + +fentry = next(fiter) +self.assertEqual(b'FMAP', fentry.name) +self.assertEqual(32, fentry.offset) +self.assertEqual(expect_size, fentry.size) +self.assertEqual(0, fentry.flags) def testBlobNamedByArg(self): """Test we can add a blob with the filename coming from an entry arg""" @@ -2064,19 +2067,23 @@ class TestFunctional(unittest.TestCase): fhdr, fentries = fmap_util.DecodeFmap(data[36:]) self.assertEqual(0x100, fhdr.image_size) - -self.assertEqual(0, fentries[0].offset) -self.assertEqual(4, fentries[0].size) -self.assertEqual(b'U_BOOT', fentries[0].name) - -self.assertEqual(4, fentries[1].offset) -self.assertEqual(3, fentries[1].size) -self.assertEqual(b'INTEL_MRC', fentries[1].name) - -self.assertEqual(36, fentries[2].offset) -self.assertEqual(fmap_util.FMAP_HEADER_LEN + - fmap_util.FMAP_AREA_LEN * 3, fentries[2].size) -self.assertEqual(b'FMAP', fentries[2].name) +expect_size = fmap_util.FMAP_HEADER_LEN + fmap_util.FMAP_AREA_LEN * 3 +fiter = iter(fentries) + +fentry = next(fiter) +self.assertEqual(b'U_BOOT', fentry.name) +self.assertEqual(0, fentry.offset) +self.assertEqual(4, fentry.size) + +fentry = next(fiter) +self.assertEqual(b'INTEL_MRC', fentry.name) +self.assertEqual(4, fentry.offset) +self.assertEqual(3, fentry.size) + +fentry = next(fiter) +self.assertEqual(b'FMAP', fentry.name) +self.assertEqual(36, fentry.offset) +self.assertEqual(expect_size, fentry.size) def testElf(self): """Basic test of ELF entries""" -- 2.31.0.208.g409f899ff0-goog
[PATCH 7/8] ARM: sheep-rk3368: Enable the rk3368 network driver
There's currently no network enabled in the sheep but we now have all the bits in place so enable the driver and DM_ETH to fix the warning. Signed-off-by: Peter Robinson Cc: Andy Yan --- configs/sheep-rk3368_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig index 90e3fff3fb..182fe7dee4 100644 --- a/configs/sheep-rk3368_defconfig +++ b/configs/sheep-rk3368_defconfig @@ -21,6 +21,8 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_RAM=y +CONFIG_DM_ETH=y +CONFIG_GMAC_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y -- 2.31.1
[PATCH 8/8] ARM: CHIP: Enable DM_USB
The CHIP devices doesn't enable distro defaults due to primary storage being NAND so it doesn't get DM_USB by default so enable it and a few other useful USB bits. Signed-off-by: Peter Robinson --- configs/CHIP_defconfig | 2 ++ configs/CHIP_pro_defconfig | 3 +++ 2 files changed, 5 insertions(+) diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index a70ee31d40..f423cfc143 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -8,12 +8,14 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip" CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y +CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_DFU_RAM=y # CONFIG_MMC is not set CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 CONFIG_CONS_INDEX=2 +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 7f10fd2b88..08b091fde9 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-gr8-chip-pro" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=sunxi-nand.0:256k(spl),256k(spl-backup),2m(uboot),2m(uboot-backup),-(UBI)" CONFIG_ENV_IS_IN_UBI=y @@ -22,6 +24,7 @@ CONFIG_SYS_NAND_OOBSIZE=0x100 CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 CONFIG_CONS_INDEX=2 +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -- 2.31.1
[PATCH 6/8] ARM: geekbox: Enable the rk3368 network driver
There's currently no network enabled in the geekbox but we now have all the bits in place so enable the driver and DM_ETH to fix the warning. Signed-off-by: Peter Robinson Cc: "Andreas Färber" --- configs/geekbox_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig index 4f0191cc00..94df408d09 100644 --- a/configs/geekbox_defconfig +++ b/configs/geekbox_defconfig @@ -19,6 +19,8 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_CLK=y CONFIG_PINCTRL=y CONFIG_RAM=y +CONFIG_DM_ETH=y +CONFIG_GMAC_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y -- 2.31.1
[PATCH 5/8] ARM: Rock: Disable network support
There's not currently any network support on the rock but the minor network config still triggers the DM_ETH warning even though there's no even a USB network interface so lets disable network support to mitigate the warning. Signed-off-by: Peter Robinson Cc: Heiko Stuebner --- configs/rock_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/rock_defconfig b/configs/rock_defconfig index cf23a10455..63a9b5c05a 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -39,6 +39,7 @@ CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +# CONFIG_NET is not set CONFIG_LED=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y -- 2.31.1
[PATCH 4/8] ARM: odroid: Enable DM_ETH
The odroid has USB ethernet so enable DM Ethernet support. Signed-off-by: Peter Robinson Jaehoon Chung --- configs/odroid_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index 9f2b0b205d..1d7949b6d0 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -41,6 +41,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y +CONFIG_DM_ETH=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_SYS_I2C_S3C24X0=y CONFIG_MMC_DW=y -- 2.31.1
[PATCH 3/8] ARM: odroid-xu3: Enable DM_ETH
The odroid-xu3 has USB ethernet so enable DM Ethernet support. Signed-off-by: Peter Robinson Cc: Jaehoon Chung Cc: Lukasz Majewski --- configs/odroid-xu3_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 755a2ca9ad..cbf13983de 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ADC=y CONFIG_ADC_EXYNOS=y +CONFIG_DM_ETH=y CONFIG_DFU_MMC=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_SUPPORT_EMMC_BOOT=y -- 2.31.1
[PATCH 2/8] ARM: dragonboard820c: Disable network support
There's not currently any network support on the 820c but the minor network config still triggers the DM_ETH warning even though there's no even a USB network interface so lets disable network support to mitigate the warning. Signed-off-by: Peter Robinson Cc: Jorge Ramirez-Ortiz --- configs/dragonboard820c_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig index 13cffd9713..6489376a34 100644 --- a/configs/dragonboard820c_defconfig +++ b/configs/dragonboard820c_defconfig @@ -14,6 +14,7 @@ CONFIG_BOOTARGS="console=ttyMSM0,115200n8" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="dragonboard820c => " +# CONFIG_NET is not set CONFIG_CMD_BOOTEFI_HELLO=y CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y -- 2.31.1
[PATCH 1/8] ARM: dragonboard410c: Enable DM_ETH
The dragonboard410c only uses USB ethernet interfaces so just enable DM_ETH. Signed-off-by: Peter Robinson Cc: Ramon Fried --- configs/dragonboard410c_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index f5db4720b7..9c4311aa45 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -33,6 +33,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_MSM_GPIO=y CONFIG_PM8916_GPIO=y +CONFIG_DM_ETH=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MMC=y -- 2.31.1
[PATCH 1/1] efi_loader: EFI_UNACCEPTED_MEMORY_TYPE
* UEFI spec 2.9 introduced a new memory type EFI_UNACCEPTED_MEMORY_TYPE.
Add it to enum EFI_MEMORY_TYPE.
* Add missing EFI_MEMORY_CPU_CRYPTO constant
* Improve description of EFI_PERSISTENT_MEMORY_TYPE
Signed-off-by: Heinrich Schuchardt
---
include/efi.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/include/efi.h b/include/efi.h
index 503fbf060b..6417a9b8c5 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -180,9 +180,13 @@ enum efi_mem_type {
*/
EFI_PAL_CODE,
/*
-* Non-volatile memory.
+* Byte addressable non-volatile memory.
*/
EFI_PERSISTENT_MEMORY_TYPE,
+ /*
+* Unaccepted memory must be accepted by boot target before usage.
+*/
+ EFI_UNACCEPTED_MEMORY_TYPE,
EFI_MAX_MEMORY_TYPE,
};
@@ -201,6 +205,7 @@ enum efi_mem_type {
((u64)0x0001ULL)/* higher
reliability */
#define EFI_MEMORY_RO ((u64)0x0002ULL)/* read-only */
#define EFI_MEMORY_SP ((u64)0x0004ULL)/*
specific-purpose memory (SPM) */
+#define EFI_MEMORY_CPU_CRYPTO ((u64)0x0008ULL)/*
cryptographically protectable */
#define EFI_MEMORY_RUNTIME ((u64)0x8000ULL)/* range
requires runtime mapping */
#define EFI_MEM_DESC_VERSION 1
--
2.30.2
[PATCH 4/5] ARM: board: warp: convert to DM_USB
Convert Warp to use DM USB. Signed-off-by: Peter Robinson Cc: Otavio Salvador Cc: Fabio Estevam Cc: Stefano Babic --- configs/warp_defconfig | 1 + include/configs/warp.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/warp_defconfig b/configs/warp_defconfig index 6efe400dd1..223436c86e 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -45,6 +45,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" diff --git a/include/configs/warp.h b/include/configs/warp.h index f17eea117f..8cde52f634 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -45,7 +45,6 @@ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT1 /* Only OTG2 port enabled */ #endif #define CONFIG_USBD_HS -- 2.31.1
[PATCH 3/5] ARM: board: warp: convert to DM_MMC
Convert Warp to use DM MMC.
Signed-off-by: Peter Robinson
Cc: Otavio Salvador
Cc: Fabio Estevam
Cc: Stefano Babic
---
arch/arm/dts/imx6sl-warp-u-boot.dtsi | 7 ++
board/warp/warp.c| 33
configs/warp_defconfig | 1 +
3 files changed, 8 insertions(+), 33 deletions(-)
create mode 100644 arch/arm/dts/imx6sl-warp-u-boot.dtsi
diff --git a/arch/arm/dts/imx6sl-warp-u-boot.dtsi
b/arch/arm/dts/imx6sl-warp-u-boot.dtsi
new file mode 100644
index 00..daf2489cfd
--- /dev/null
+++ b/arch/arm/dts/imx6sl-warp-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+ aliases {
+ mmc0 = &usdhc2;
+ };
+};
diff --git a/board/warp/warp.c b/board/warp/warp.c
index 0f1d038fab..417f0e7507 100644
--- a/board/warp/warp.c
+++ b/board/warp/warp.c
@@ -21,9 +21,7 @@
#include
#include
#include
-#include
#include
-#include
#include
#include
#include
@@ -62,37 +60,6 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC2_BASE_ADDR, 0, 0, 0, 1},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- return 1; /* Assume boot SD always present */
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_RST__USDHC2_RST | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-
int board_usb_phy_mode(int port)
{
return USB_INIT_DEVICE;
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index 68ad71c27c..6efe400dd1 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -39,6 +39,7 @@ CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_DFU_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
--
2.31.1
[PATCH 5/5] ARM: board: warp7: Minor cleanups and DM_ETH
We don't need a random MAC as the only network that's supported is over USB and that has a hardcoded MAC, enable DM_ETH for the USB, and the device doesn't have MTD storage so drop that. Signed-off-by: Peter Robinson Cc: Fabio Estevam Cc: Stefano Babic --- configs/warp7_bl33_defconfig | 3 +-- configs/warp7_defconfig | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 4b45fcd50a..98d370754a 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -32,14 +32,13 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y +CONFIG_DM_ETH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y -CONFIG_MTD=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 3d11196080..8fa1981207 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -38,14 +38,13 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y +CONFIG_DM_ETH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y -CONFIG_MTD=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y -- 2.31.1
[PATCH 2/5] ARM: board: warp: Enable OF_CONTROL and DM gpio/pin control
Enable OF_CONTROL and DM for gpio and pin control support on the i.MX6SL based Warp. Signed-off-by: Peter Robinson Cc: Otavio Salvador Cc: Fabio Estevam Cc: Stefano Babic --- configs/warp_defconfig | 7 +++ 1 file changed, 7 insertions(+) diff --git a/configs/warp_defconfig b/configs/warp_defconfig index 34acc9e6c8..68ad71c27c 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -2,10 +2,12 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x8780 CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6sl-warp" CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x6 CONFIG_MX6SL=y CONFIG_TARGET_WARP=y +CONFIG_OF_CONTROL=y # CONFIG_CMD_BMODE is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp/imximage.cfg" @@ -18,6 +20,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set @@ -32,9 +35,13 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set CONFIG_BOUNCE_BUFFER=y +CONFIG_DM=y +CONFIG_DM_GPIO=y CONFIG_DFU_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_USB_STORAGE=y -- 2.31.1
[PATCH 1/5] ARM: board: warp: Import dts files
Import the i.MX6 based Warp dts files from Linux 5.12-rc1.
Signed-off-by: Peter Robinson
Cc: Fabio Estevam
Cc: Stefano Babic
---
arch/arm/dts/Makefile| 4 +-
arch/arm/dts/imx6sl-warp.dts | 234 +++
2 files changed, 237 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx6sl-warp.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 116f75192f..1481a6ec46 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -734,7 +734,9 @@ dtb-y += \
endif
-dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
+dtb-$(CONFIG_MX6SL) += \
+ imx6sl-evk.dtb \
+ imx6sl-warp.dtb
dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb
diff --git a/arch/arm/dts/imx6sl-warp.dts b/arch/arm/dts/imx6sl-warp.dts
new file mode 100644
index 00..9d7c888489
--- /dev/null
+++ b/arch/arm/dts/imx6sl-warp.dts
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2014, 2015 O.S. Systems Software LTDA.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include
+#include "imx6sl.dtsi"
+
+/ {
+ model = "Revotics WaRP Board";
+ compatible = "revotics,imx6sl-warp", "fsl,imx6sl";
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x2000>;
+ };
+
+ usdhc3_pwrseq: usdhc3_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
+ <&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE
*/
+ <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */
+ <&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE
*/
+ <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */
+ <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "peripheral";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+
RE: Ethernet Gadget on STM32MP1 not working
Hi Herbert I will have a look at this issue. Thanks for the information and start of debug. Patrice De : Herbert Poetzl Envoyé : jeudi 1 avril 2021 12:58 À : u-boot@lists.denx.de Cc : Patrick DELAUNAY ; Patrice CHOTARD Objet : Ethernet Gadget on STM32MP1 not working When testing the USB Ethernet Gadget I encountered some issues on STM32MP1 which prevented the bind to work as expected. Basically running ... bind /soc/usb-otg@4900 usb_ether ... results in an additional entry in 'dm uclass' like: uclass 104: usb 0 usb-otg@4900 @ ddf2f458, seq 0 1 usb-otg@4900 @ ddf39de0, seq 1 2 usb-otg@4900 @ ddf3a188, seq 2 ... but no working ethernet gadget. Marek Vasut tracked the issue down to commit 84f8e36f03fafa7e2e2ff822db90fefa6bd5f350 which when reverted allows to get one step further ... drivers/usb/gadget/ether.c:2064-eth_bind() controller 'dwc2-udc' not recognizeddrivers/usb/gadget/udc/udc-core.c:317-udc_bind_to_driver() failed to start : -19 ... and finally when commenting out the return -ENODEV; ... in drivers/usb/gadget/ether.c line 2066, the ethernet gadget finally works on STM32MP1. Hope this helps, Herbert
[PATCH] lib/rsa: Use EVP_PKEY instead of RSA
Most modern OpenSSL engines have methods overridden at the EVP level rather
than at RSA level, to make these engines work properly with mkimage, the RSA
signing code needs to switch to using EVP_* APIs as much as possible.
Signed-off-by: Donald Chan
---
lib/rsa/rsa-sign.c | 168 +
1 file changed, 66 insertions(+), 102 deletions(-)
diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
index 1f0d81b..0eb480b 100644
--- a/lib/rsa/rsa-sign.c
+++ b/lib/rsa/rsa-sign.c
@@ -51,19 +51,21 @@ static int rsa_err(const char *msg)
*
* @keydir:Directory containins the key
* @name Name of key file (will have a .crt extension)
- * @rsap Returns RSA object, or NULL on failure
- * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL)
+ * @evpp Returns EVP_PKEY object, or NULL on failure
+ * @return 0 if ok, -ve on error (in which case *evpp will be set to NULL)
*/
-static int rsa_pem_get_pub_key(const char *keydir, const char *name, RSA
**rsap)
+static int rsa_pem_get_pub_key(const char *keydir, const char *name, EVP_PKEY
**evpp)
{
char path[1024];
- EVP_PKEY *key;
+ EVP_PKEY *key = NULL;
X509 *cert;
- RSA *rsa;
FILE *f;
int ret;
- *rsap = NULL;
+ if (!evpp)
+ return -EINVAL;
+
+ *evpp = NULL;
snprintf(path, sizeof(path), "%s/%s.crt", keydir, name);
f = fopen(path, "r");
if (!f) {
@@ -88,22 +90,12 @@ static int rsa_pem_get_pub_key(const char *keydir, const
char *name, RSA **rsap)
goto err_pubkey;
}
- /* Convert to a RSA_style key. */
- rsa = EVP_PKEY_get1_RSA(key);
- if (!rsa) {
- rsa_err("Couldn't convert to a RSA style key");
- ret = -EINVAL;
- goto err_rsa;
- }
fclose(f);
- EVP_PKEY_free(key);
+ *evpp = key;
X509_free(cert);
- *rsap = rsa;
return 0;
-err_rsa:
- EVP_PKEY_free(key);
err_pubkey:
X509_free(cert);
err_cert:
@@ -117,19 +109,20 @@ err_cert:
* @keydir:Key prefix
* @name Name of key
* @engine Engine to use
- * @rsap Returns RSA object, or NULL on failure
- * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL)
+ * @evpp Returns EVP_PKEY object, or NULL on failure
+ * @return 0 if ok, -ve on error (in which case *evpp will be set to NULL)
*/
static int rsa_engine_get_pub_key(const char *keydir, const char *name,
- ENGINE *engine, RSA **rsap)
+ ENGINE *engine, EVP_PKEY **evpp)
{
const char *engine_id;
char key_id[1024];
- EVP_PKEY *key;
- RSA *rsa;
- int ret;
+ EVP_PKEY *key = NULL;
+
+ if (!evpp)
+ return -EINVAL;
- *rsap = NULL;
+ *evpp = NULL;
engine_id = ENGINE_get_id(engine);
@@ -165,22 +158,9 @@ static int rsa_engine_get_pub_key(const char *keydir,
const char *name,
if (!key)
return rsa_err("Failure loading public key from engine");
- /* Convert to a RSA_style key. */
- rsa = EVP_PKEY_get1_RSA(key);
- if (!rsa) {
- rsa_err("Couldn't convert to a RSA style key");
- ret = -EINVAL;
- goto err_rsa;
- }
-
- EVP_PKEY_free(key);
- *rsap = rsa;
+ *evpp = key;
return 0;
-
-err_rsa:
- EVP_PKEY_free(key);
- return ret;
}
/**
@@ -189,15 +169,15 @@ err_rsa:
* @keydir:Directory containing the key (PEM file) or key prefix (engine)
* @name Name of key file (will have a .crt extension)
* @engine Engine to use
- * @rsap Returns RSA object, or NULL on failure
- * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL)
+ * @evpp Returns EVP_PKEY object, or NULL on failure
+ * @return 0 if ok, -ve on error (in which case *evpp will be set to NULL)
*/
static int rsa_get_pub_key(const char *keydir, const char *name,
- ENGINE *engine, RSA **rsap)
+ ENGINE *engine, EVP_PKEY **evpp)
{
if (engine)
- return rsa_engine_get_pub_key(keydir, name, engine, rsap);
- return rsa_pem_get_pub_key(keydir, name, rsap);
+ return rsa_engine_get_pub_key(keydir, name, engine, evpp);
+ return rsa_pem_get_pub_key(keydir, name, evpp);
}
/**
@@ -205,17 +185,19 @@ static int rsa_get_pub_key(const char *keydir, const char
*name,
*
* @keydir:Directory containing the key
* @name Name of key file (will have a .key extension)
- * @rsap Returns RSA object, or NULL on failure
- * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL)
+ * @evpp Returns EVP_PKEY object, or NULL on failure
+ * @return 0 if ok, -ve on error (in which case *evpp will be set to NULL)
*/
stat
Re: SAMA5D3 Xplained: SPL broken after panic added to /lib/time.c:94
FYI: the output from serial port: board_init_f spl_atmel.c 130 mem_init 182 ddr2_init mpddr.c 66udelay lib time.c 196__udelay lib time.c 177Could not initialize timer (err -11) udelay lib time.c 196__udelay lib time.c 177Could not initialize timer (err -11) udelay lib time.c 196__udelay lib time.c 177Could not initialize timer (err -11) ... On Fri, 2 Apr 2021 at 18:12, Manuel Luís Reis wrote: > > > As it seems from the dump of dm_dump_all() the atmel_pit_timer is not > > probed. I did a bit of debug and the dm_timer_init() -> > > uclass_first_device() -> uclass_find_first_device() found zero timers > > registered for UCLASS_TIMER. The driver is compiled. Also checked that > > atmel_pit_timer probe function is not called at all. The question should be > > why it is not probed at all? > > Hi, > > So, I put objdump and puts to some good use and could backtrace the > initial error to a udelay call in ddr2_init function on mpddr.c file. > This function is called from mem_init on > sama5d3_xplained/sama5d3_xplained.c, which in turn is called from > board_init_f on spl_atmel.c. > I couldn't, however, find which timer_init function is being called > here. I still have a few to try, but disassembly gives me a pretty > empty function: > > 00303690 : > 303690: e3a0mov r0, #0 > 303694: e12fff1ebx lr > > This work didn't give me many answers, but I got a couple of newbie questions: > > Why is it calling board_init_f from spl_atmel.c and not spl_at91.c? > Isn't the latter the appropriate architecture for this board? > Do you know which timer_init function it is getting here? Could this > be the reason timer isn't getting probed? > > Cheers,
Re: SAMA5D3 Xplained: SPL broken after panic added to /lib/time.c:94
> As it seems from the dump of dm_dump_all() the atmel_pit_timer is not > probed. I did a bit of debug and the dm_timer_init() -> > uclass_first_device() -> uclass_find_first_device() found zero timers > registered for UCLASS_TIMER. The driver is compiled. Also checked that > atmel_pit_timer probe function is not called at all. The question should be > why it is not probed at all? Hi, So, I put objdump and puts to some good use and could backtrace the initial error to a udelay call in ddr2_init function on mpddr.c file. This function is called from mem_init on sama5d3_xplained/sama5d3_xplained.c, which in turn is called from board_init_f on spl_atmel.c. I couldn't, however, find which timer_init function is being called here. I still have a few to try, but disassembly gives me a pretty empty function: 00303690 : 303690: e3a0mov r0, #0 303694: e12fff1ebx lr This work didn't give me many answers, but I got a couple of newbie questions: Why is it calling board_init_f from spl_atmel.c and not spl_at91.c? Isn't the latter the appropriate architecture for this board? Do you know which timer_init function it is getting here? Could this be the reason timer isn't getting probed? Cheers,
[PATCH 4/5] ARM: imx: udoo: Convert block devices to DM
Enable DM block, DM MMC and DM SATA support on iMX6 Udoo
convert board code to match the DM support.
Signed-off-by: Peter Robinson
Cc: Fabio Estevam
Cc: Stefano Babic
---
arch/arm/dts/imx6qdl-udoo-u-boot.dtsi | 7 +++
board/udoo/udoo.c | 30 ---
configs/udoo_defconfig| 3 +++
include/configs/udoo.h| 6 --
4 files changed, 10 insertions(+), 36 deletions(-)
create mode 100644 arch/arm/dts/imx6qdl-udoo-u-boot.dtsi
diff --git a/arch/arm/dts/imx6qdl-udoo-u-boot.dtsi
b/arch/arm/dts/imx6qdl-udoo-u-boot.dtsi
new file mode 100644
index 00..749791a13f
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-udoo-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+ aliases {
+ mmc0 = &usdhc3;
+ };
+};
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index d83f23dd35..c1acc25a9d 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -19,8 +19,6 @@
#include
#include
#include
-#include
-#include
#include
#include
#include
@@ -56,15 +54,6 @@ static iomux_v3_cfg_t const uart2_pads[] = {
IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
@@ -176,13 +165,6 @@ static void setup_iomux_wdog(void)
gpio_direction_input(WDT_TRG);
}
-static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- return 1; /* Always present */
-}
-
int board_eth_init(struct bd_info *bis)
{
uint32_t base = IMX_FEC_BASE;
@@ -217,15 +199,6 @@ free_bus:
return ret;
}
-int board_mmc_init(struct bd_info *bis)
-{
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg.max_bus_width = 4;
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg);
-}
-
int board_early_init_f(void)
{
setup_iomux_wdog();
@@ -248,9 +221,6 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-#ifdef CONFIG_SATA
- setup_sata();
-#endif
return 0;
}
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index deec4bc82f..2735f02af3 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -17,6 +17,7 @@ CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
@@ -38,8 +39,10 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_MMC=y
CONFIG_DWC_AHSATA=y
CONFIG_FSL_USDHC=y
+CONFIG_DM_SCSI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_PHYLIB=y
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index b4fbf8c638..25f40074c5 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -21,13 +21,7 @@
#define CONFIG_MXC_UART_BASE UART2_BASE
/* SATA Configs */
-
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_DWC_AHSATA_PORT_ID 0
-#define CONFIG_DWC_AHSATA_BASE_ADDRSATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#endif
/* Network support */
--
2.31.1
[PATCH 5/5] ARM: imx: udoo: convert to DM_ETH
Convert the UDOO board to use DM_ETH.
Signed-off-by: Peter Robinson
Cc: Fabio Estevam
Cc: Stefano Babic
---
board/udoo/udoo.c | 75 ++
configs/udoo_defconfig | 2 ++
include/configs/udoo.h | 8 -
3 files changed, 4 insertions(+), 81 deletions(-)
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index c1acc25a9d..5c49388cbf 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -88,45 +88,8 @@ int mx6_rgmii_rework(struct phy_device *phydev)
return 0;
}
-static iomux_v3_cfg_t const enet_pads1[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK|
MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* RGMII reset */
- IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 |
MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* Ethernet power supply */
- IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 |
MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 32 - 1 - (MODE0) all */
- IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25|
MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 31 - 1 - (MODE1) all */
- IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27|
MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 28 - 1 - (MODE2) all */
- IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28|
MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 27 - 1 - (MODE3) all */
- IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29|
MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
- IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const enet_pads2[] = {
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
-};
-
static void setup_iomux_enet(void)
{
- SETUP_IOMUX_PADS(enet_pads1);
- udelay(20);
gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
@@ -148,8 +111,6 @@ static void setup_iomux_enet(void)
gpio_free(IMX_GPIO_NR(6, 27));
gpio_free(IMX_GPIO_NR(6, 28));
gpio_free(IMX_GPIO_NR(6, 29));
-
- SETUP_IOMUX_PADS(enet_pads2);
}
static void setup_iomux_uart(void)
@@ -165,40 +126,6 @@ static void setup_iomux_wdog(void)
gpio_direction_input(WDT_TRG);
}
-int board_eth_init(struct bd_info *bis)
-{
- uint32_t base = IMX_FEC_BASE;
- struct mii_dev *bus = NULL;
- struct phy_device *phydev = NULL;
- int ret;
-
- setup_iomux_enet();
-
-#ifdef CONFIG_FEC_MXC
- bus = fec_get_miibus(base, -1);
- if (!bus)
- return -EINVAL;
- /* scan phy 4,5,6,7 */
- phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
-
- if (!phydev) {
- ret = -EINVAL;
- goto free_bus;
- }
- printf("using phy at %d\n", phydev->addr);
- ret = fec_probe(bis, -1, base, bus, phydev);
- if (ret)
- goto free_phydev;
-#endif
- return 0;
-
-free_phydev:
- free(phydev);
-free_bus:
- free(bus);
- return ret;
-}
-
int board_early_init_f(void)
{
setup_iomux_wdog();
@@ -232,6 +159,8 @@ int board_late_init(void)
else
env_set("board_rev", "MX6DL");
#endif
+ setup_iomux_enet();
+
return 0;
}
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 2735f02af3..064d545e34 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -48,6 +48,8 @@ CONFIG_PINCTRL_IMX6=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index 25f40074c5..298369373a 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -23,14 +23,6 @@
/* SATA Configs */
#define CONFIG_LBA48
-/* Network support */
-
-#define CONF
[PATCH 3/5] ARM: imx: udoo: drop MTD config
The UDOO doesn't have any MTD storage so drop the config. Signed-off-by: Peter Robinson Cc: Fabio Estevam Cc: Stefano Babic --- configs/udoo_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index bcc88356ce..deec4bc82f 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -42,7 +42,6 @@ CONFIG_DWC_AHSATA=y CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y -CONFIG_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y -- 2.31.1
[PATCH 1/5] ARM: board: udoo: Import UDOO dts files
Import the i.MX6 based UDOO dts files from Linux 5.12-rc1.
Signed-off-by: Peter Robinson
Cc: Fabio Estevam
Cc: Stefano Babic
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imx6dl-udoo.dts | 14 ++
arch/arm/dts/imx6q-udoo.dts| 18 ++
arch/arm/dts/imx6qdl-udoo.dtsi | 324 +
4 files changed, 358 insertions(+)
create mode 100644 arch/arm/dts/imx6dl-udoo.dts
create mode 100644 arch/arm/dts/imx6q-udoo.dts
create mode 100644 arch/arm/dts/imx6qdl-udoo.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 88cf85596f..116f75192f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -686,6 +686,7 @@ dtb-y += \
imx6dl-mamoj.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-pico.dtb \
+ imx6dl-udoo.dtb \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
@@ -721,6 +722,7 @@ dtb-y += \
imx6q-novena.dtb \
imx6q-pico.dtb \
imx6q-phytec-mira-rdk-nand.dtb \
+ imx6q-udoo.dtb \
imx6q-sabreauto.dtb \
imx6q-sabrelite.dtb \
imx6q-sabresd.dtb \
diff --git a/arch/arm/dts/imx6dl-udoo.dts b/arch/arm/dts/imx6dl-udoo.dts
new file mode 100644
index 00..d871cac171
--- /dev/null
+++ b/arch/arm/dts/imx6dl-udoo.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam
+ */
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-udoo.dtsi"
+
+/ {
+ model = "Udoo i.MX6 Dual-lite Board";
+ compatible = "udoo,imx6dl-udoo", "fsl,imx6dl";
+};
diff --git a/arch/arm/dts/imx6q-udoo.dts b/arch/arm/dts/imx6q-udoo.dts
new file mode 100644
index 00..52e9f4a211
--- /dev/null
+++ b/arch/arm/dts/imx6q-udoo.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-udoo.dtsi"
+
+/ {
+ model = "Udoo i.MX6 Quad Board";
+ compatible = "udoo,imx6q-udoo", "fsl,imx6q";
+};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6qdl-udoo.dtsi b/arch/arm/dts/imx6qdl-udoo.dtsi
new file mode 100644
index 00..d07d8f8345
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-udoo.dtsi
@@ -0,0 +1,324 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam
+ */
+
+/ {
+ aliases {
+ backlight = &backlight;
+ panelchan = &panelchan;
+ panel7 = &panel7;
+ touchscreenp7 = &touchscreenp7;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ backlight: backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpio1 4 0>;
+ default-on;
+ status = "disabled";
+ };
+
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio2 4 0>;
+ pinctrl-0 = <&pinctrl_power_off>;
+ pinctrl-names = "default";
+ };
+
+ memory@1000 {
+ device_type = "memory";
+ reg = <0x1000 0x4000>;
+ };
+
+ panel7: panel7 {
+ /*
+* in reality it is a -20t (parallel) model,
+* but with LVDS bridge chip attached,
+* so it is equivalent to -19t model in drive
+* characteristics
+*/
+ compatible = "urt,umsh-8596md-19t";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_panel>;
+ power-supply = <®_panel>;
+ backlight = <&backlight>;
+ status = "disabled";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usb_h1_vbus: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ enable-active-high;
+ startup-delay-us = <2>; /* USB2415 requires a POR of 1
us minimum */
+ gpio = <&gpio7 12 0>;
+ };
+
+ reg_panel: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "lcd_panel";
+ enable-active-high;
+ gpio = <&gpio1 2 0>;
+ };
+ };
+
+ sound {
+
[PATCH 2/5] ARM: imx: udoo: Enable OF_CONTROL and DM gpio/pin control
Enable OF_CONTROL and DM for gpio and pin control support on the i.MX6 based Udoo boards. Signed-off-by: Peter Robinson Cc: Fabio Estevam Cc: Stefano Babic --- configs/udoo_defconfig | 7 +++ 1 file changed, 7 insertions(+) diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index f72b9645da..bcc88356ce 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -5,10 +5,13 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6q-udoo" +CONFIG_OF_LIST="imx6q-udoo imx6dl-udoo" CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x6 CONFIG_MX6QDL=y CONFIG_TARGET_UDOO=y +CONFIG_OF_CONTROL=y CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y @@ -24,6 +27,7 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_SATA=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y @@ -32,9 +36,12 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y +CONFIG_DM_GPIO=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y -- 2.31.1
Re: Pull request for efi-2021-04-rc6
On Wed, Mar 31, 2021 at 06:52:53PM +0200, Heinrich Schuchardt wrote: > Hello Tom, > > this fixes the Coverity issue that you reported. > > The following changes since commit d8eafb16c85bc3b5d85d7ba8ebb1438cc0ae168f: > > Prepare v2021.04-rc5 (2021-03-29 17:20:13 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-efi.git > tags/efi-2021-04-rc6 > > for you to fetch changes up to d084f20233b1ca1fe1330e1aedb614b2a0c59abf: > > efi_loader: typo 'devide path' (2021-03-31 06:34:33 +) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH 8/8] ARM: embestmx6boards: convert the mars/riot boards to DM SPI
Enable DM_SPI and DM_SPI_FLASH on the mars/riot boards. Signed-off-by: Peter Robinson Cc: "Eric Bénard" Cc: Fabio Estevam Cc: Stefano Babic --- configs/marsboard_defconfig | 2 ++ configs/riotboard_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 2759c291da..551d09bece 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -34,6 +34,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=2000 @@ -45,6 +46,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 12af407400..d41b4ba070 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -46,6 +46,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=2000 @@ -57,6 +58,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y -- 2.31.1
[PATCH 7/8] ARM: embestmx6boards: convert mars/riot boards to DM_ETH
Convert the boards to use DM_ETH.
Signed-off-by: Peter Robinson
Cc: "Eric Bénard"
Cc: Fabio Estevam
Cc: Stefano Babic
---
board/embest/mx6boards/mx6boards.c | 26 +-
configs/marsboard_defconfig| 2 ++
configs/riotboard_defconfig| 2 ++
include/configs/embestmx6boards.h | 6 --
4 files changed, 5 insertions(+), 31 deletions(-)
diff --git a/board/embest/mx6boards/mx6boards.c
b/board/embest/mx6boards/mx6boards.c
index c3bbcff0cf..dda8502c6f 100644
--- a/board/embest/mx6boards/mx6boards.c
+++ b/board/embest/mx6boards/mx6boards.c
@@ -91,24 +91,6 @@ static void setup_iomux_uart(void)
}
iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- /* GPIO16 -> AR8035 25MHz */
- MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
/* AR8035 PHY Reset */
MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
/* AR8035 PHY Interrupt */
@@ -376,13 +358,6 @@ int overwrite_console(void)
return 1;
}
-int board_eth_init(struct bd_info *bis)
-{
- setup_iomux_enet();
-
- return cpu_eth_init(bis);
-}
-
int board_early_init_f(void)
{
u32 cputype = cpu_type(get_cpu_rev());
@@ -460,6 +435,7 @@ int board_late_init(void)
else if (board_type == BOARD_IS_RIOTBOARD)
add_board_boot_modes(marsboard_boot_modes);
#endif
+ setup_iomux_enet();
return 0;
}
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 3e7b8ef0f5..2759c291da 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -40,6 +40,8 @@ CONFIG_SF_DEFAULT_SPEED=2000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index 1e5dc39318..12af407400 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -52,6 +52,8 @@ CONFIG_SF_DEFAULT_SPEED=2000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
diff --git a/include/configs/embestmx6boards.h
b/include/configs/embestmx6boards.h
index c49d4dc0e4..a29eec00ae 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -36,12 +36,6 @@
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPERGMII
-#define CONFIG_ETHPRIME"FEC"
-#define CONFIG_FEC_MXC_PHYADDR 4
-
#define CONFIG_ARP_TIMEOUT 200UL
/* Physical Memory Map */
--
2.31.1
[PATCH 5/8] ARM: embestmx6boards: convert the mars/riot boards to DM_MMC
Convert the two Embest boards to use DM MMC.
Signed-off-by: Peter Robinson
Cc: "Eric Bénard"
Cc: Fabio Estevam
Cc: Stefano Babic
---
arch/arm/dts/imx6dl-riotboard-u-boot.dtsi | 8 ++
arch/arm/dts/imx6q-marsboard-u-boot.dtsi | 8 ++
board/embest/mx6boards/mx6boards.c| 137 --
configs/marsboard_defconfig | 1 +
configs/riotboard_defconfig | 1 +
5 files changed, 18 insertions(+), 137 deletions(-)
create mode 100644 arch/arm/dts/imx6dl-riotboard-u-boot.dtsi
create mode 100644 arch/arm/dts/imx6q-marsboard-u-boot.dtsi
diff --git a/arch/arm/dts/imx6dl-riotboard-u-boot.dtsi
b/arch/arm/dts/imx6dl-riotboard-u-boot.dtsi
new file mode 100644
index 00..e51cd24d7e
--- /dev/null
+++ b/arch/arm/dts/imx6dl-riotboard-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+ aliases {
+ mmc0 = &usdhc2;
+ mmc1 = &usdhc3;
+ };
+};
diff --git a/arch/arm/dts/imx6q-marsboard-u-boot.dtsi
b/arch/arm/dts/imx6q-marsboard-u-boot.dtsi
new file mode 100644
index 00..e51cd24d7e
--- /dev/null
+++ b/arch/arm/dts/imx6q-marsboard-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+ aliases {
+ mmc0 = &usdhc2;
+ mmc1 = &usdhc3;
+ };
+};
diff --git a/board/embest/mx6boards/mx6boards.c
b/board/embest/mx6boards/mx6boards.c
index 65b3942e39..c3bbcff0cf 100644
--- a/board/embest/mx6boards/mx6boards.c
+++ b/board/embest/mx6boards/mx6boards.c
@@ -31,8 +31,6 @@
#include
#include
#include
-#include
-#include
#include
#include
#include
@@ -150,141 +148,6 @@ int board_phy_config(struct phy_device *phydev)
return 0;
}
-iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
- MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
- MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
- MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
- MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
- MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- /* eMMC RST */
- MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-struct fsl_esdhc_cfg usdhc_cfg[3] = {
- {USDHC2_BASE_ADDR},
- {USDHC3_BASE_ADDR},
- {USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- break;
- case USDHC3_BASE_ADDR:
- if (board_type == BOARD_IS_RIOTBOARD)
- ret = !gpio_get_value(USDHC3_CD_GPIO);
- else if (board_type == BOARD_IS_MARSBOARD)
- ret = 1; /* eMMC/uSDHC3 is always present */
- break;
- case USDHC4_BASE_ADDR:
- ret = 1; /* eMMC/uSDHC4 is always present */
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- int ret;
- int i;
-
- /*
-* According to the board_mmc_init() the following map is done:
-* (U-Boot device node)(Physical Port)
-* ** RiOTboard :
-* mmc0SDCard slot (bottom)
-* mmc1uSDCard slot (top)
-* mmc2eMMC
-* ** MarSBoard :
-* mmc0uSDCard slot (bottom)
-* mmc1
[PATCH 6/8] ARM: embestmx6boards: convert mars/riot boards to DM_USB
Convert the marsboard/riotboard to use DM_USB. Signed-off-by: Peter Robinson Cc: "Eric Bénard" Cc: Fabio Estevam Cc: Stefano Babic --- configs/marsboard_defconfig | 1 + configs/riotboard_defconfig | 1 + include/configs/embestmx6boards.h | 1 - 3 files changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 63fc60a884..3e7b8ef0f5 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -47,6 +47,7 @@ CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 4f86a08e78..1e5dc39318 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -59,6 +59,7 @@ CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index ff3a849a14..c49d4dc0e4 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -29,7 +29,6 @@ #define CONFIG_SYS_I2C_SPEED 10 /* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -- 2.31.1
[PATCH 4/8] ARM: riotboard: Enable OF_CONTROL and DM gpio/pin control
Enable OF_CONTROL and DM for gpio and pin control support on the i.MX6D based riotboard. Signed-off-by: Peter Robinson Cc: "Eric Bénard" Cc: Fabio Estevam Cc: Stefano Babic --- configs/riotboard_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 074c0d5b44..0284f86405 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -5,10 +5,12 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-riotboard" CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x6 CONFIG_MX6S=y CONFIG_TARGET_EMBESTMX6BOARDS=y +CONFIG_OF_CONTROL=y CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y @@ -27,6 +29,7 @@ CONFIG_SPL_OS_BOOT=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y @@ -36,9 +39,12 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_DM=y +CONFIG_DM_GPIO=y CONFIG_BOUNCE_BUFFER=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=2000 -- 2.31.1
[PATCH 3/8] ARM: embestmx6boards: merge the riotboard's configs together
It doesn't make much sense to have two separate configs for the riotboard so let's merge the SPL config into the main one for less duplication. Signed-off-by: Peter Robinson Cc: "Eric Bénard" Cc: Fabio Estevam Cc: Stefano Babic --- configs/riotboard_defconfig | 14 ++- configs/riotboard_spl_defconfig | 70 - 2 files changed, 13 insertions(+), 71 deletions(-) delete mode 100644 configs/riotboard_spl_defconfig diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index b652057d74..074c0d5b44 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -1,18 +1,29 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x1780 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x6 CONFIG_MX6S=y CONFIG_TARGET_EMBESTMX6BOARDS=y +CONFIG_SPL_TEXT_BASE=0x00908000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,DDR_MB=1024" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SPL,DDR_MB=1024" CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_OS_BOOT=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -57,3 +68,4 @@ CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y CONFIG_BMP_16BPP=y CONFIG_OF_LIBFDT=y +CONFIG_SPL_OF_LIBFDT=y diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig deleted file mode 100644 index 95549ff5b7..00 --- a/configs/riotboard_spl_defconfig +++ /dev/null @@ -1,70 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x1780 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x6 -CONFIG_MX6S=y -CONFIG_TARGET_EMBESTMX6BOARDS=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SPL,DDR_MB=1024" -CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_RAW_IMAGE_SUPPORT=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_OS_BOOT=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_DM=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_USDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=2000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_ATHEROS=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_THERMAL=y -CONFIG_USB=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_DM_VIDEO=y -# CONFIG_BACKLIGHT is not set -# CONFIG_CMD_VIDCONSOLE is not set -# CONFIG_VIDEO_BPP8 is not set -# CONFIG_VIDEO_BPP32 is not set -# CONFIG_VIDEO_ANSI is not set -CONFIG_SYS_WHITE_ON_BLACK=y -# CONFIG_PANEL is not set -CONFIG_VIDEO_IPUV3=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_BMP_16BPP=y -CONFIG_OF_LIBFDT=y -CONFIG_SPL_OF_LIBFDT=y -- 2.31.1
[PATCH 1/8] ARM: embestmx6boards: Import the marsboard/riotboard. dts files
Import the iMX6 based marsboard and riotboard. dts files from Linux 5.12-rc1
Signed-off-by: Peter Robinson
Cc: Fabio Estevam
Cc: Stefano Babic
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imx6dl-riotboard.dts | 594 ++
arch/arm/dts/imx6q-marsboard.dts | 417 +
3 files changed, 1013 insertions(+)
create mode 100644 arch/arm/dts/imx6dl-riotboard.dts
create mode 100644 arch/arm/dts/imx6q-marsboard.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aaf005e6d9..88cf85596f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -686,6 +686,7 @@ dtb-y += \
imx6dl-mamoj.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-pico.dtb \
+ imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6dl-wandboard-revd1.dtb \
@@ -712,6 +713,7 @@ dtb-y += \
imx6q-icore-rqs.dtb \
imx6q-kp.dtb \
imx6q-logicpd.dtb \
+ imx6q-marsboard.dtb \
imx6q-mba6a.dtb \
imx6q-mba6b.dtb \
imx6q-mccmon6.dtb\
diff --git a/arch/arm/dts/imx6dl-riotboard.dts
b/arch/arm/dts/imx6dl-riotboard.dts
new file mode 100644
index 00..065d3ab0f5
--- /dev/null
+++ b/arch/arm/dts/imx6dl-riotboard.dts
@@ -0,0 +1,594 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2014 Iain Paton
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include
+
+/ {
+ model = "RIoTboard i.MX6S";
+ compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
+
+ memory@1000 {
+ device_type = "memory";
+ reg = <0x1000 0x4000>;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+
+ led0: user1 {
+ label = "user1";
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1: user2 {
+ label = "user2";
+ gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-sgtl5000";
+ model = "imx6-riotboard-sgtl5000";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <3>;
+ };
+
+ reg_2p5v: regulator-2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <250>;
+ regulator-max-microvolt = <250>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ reg_usb_otg_vbus: regulator-usbotgvbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&clks {
+ fsl,pmic-stby-poweroff;
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&rgmii_phy>;
+ interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,err006687-workaround-present;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Atheros AR8035 PHY */
+ rgmii_phy: ethernet-phy@4 {
+ reg = <4>;
+ interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <1>;
+ reset-deassert-us = <1000>;
+ };
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL",
+ "I2C3_SDA", "I2C4_SCL",
+ "I2C4_SDA", "", "", "", "", "", "", "",
+ "", "PWM3", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+
[PATCH 2/8] ARM: marsboard: Enable OF_CONTROL and DM gpio/pin control
Enable OF_CONTROL and DM for gpio and pin control support on the i.MX6Q based embestmx6boards marsboard. Signed-off-by: Peter Robinson Cc: "Eric Bénard" Cc: Fabio Estevam Cc: Stefano Babic --- configs/marsboard_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index d2bd9c46d2..4d15f0432e 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -2,11 +2,13 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x1780 CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6q-marsboard" CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_MX6Q=y CONFIG_TARGET_EMBESTMX6BOARDS=y +CONFIG_OF_CONTROL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,DDR_MB=1024" CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" @@ -17,6 +19,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y @@ -25,8 +28,11 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_GPIO=y CONFIG_BOUNCE_BUFFER=y CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=2000 -- 2.31.1
[PATCH v4 7/7] board: Add rt-thread art-pi board support
From: dillon min
All these files are add for support rt-thread art-pi board
- add board/st/stm32h750-art-pi, defconfig, header support for u-boot
for more information about art-pi, please goto:
https://art-pi.gitee.io/website/
Signed-off-by: dillon min
---
v4: update CONFIG_BOOTARGS, remove rdinit=/linuxrc, to use kernel's devtmpfs
arch/arm/mach-stm32/stm32h7/Kconfig | 4 ++
board/st/stm32h750-art-pi/Kconfig| 19 +
board/st/stm32h750-art-pi/MAINTAINERS| 7
board/st/stm32h750-art-pi/Makefile | 6 +++
board/st/stm32h750-art-pi/stm32h750-art-pi.c | 58
configs/stm32h750-art-pi_defconfig | 51
include/configs/stm32h750-art-pi.h | 48 +++
7 files changed, 193 insertions(+)
create mode 100644 board/st/stm32h750-art-pi/Kconfig
create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS
create mode 100644 board/st/stm32h750-art-pi/Makefile
create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c
create mode 100644 configs/stm32h750-art-pi_defconfig
create mode 100644 include/configs/stm32h750-art-pi.h
diff --git a/arch/arm/mach-stm32/stm32h7/Kconfig
b/arch/arm/mach-stm32/stm32h7/Kconfig
index 55e6217..70233a4 100644
--- a/arch/arm/mach-stm32/stm32h7/Kconfig
+++ b/arch/arm/mach-stm32/stm32h7/Kconfig
@@ -6,7 +6,11 @@ config TARGET_STM32H743_DISCO
config TARGET_STM32H743_EVAL
bool "STM32H743 Evaluation board"
+config TARGET_STM32H750_ART_PI
+ bool "STM32H750 ART Pi board"
+
source "board/st/stm32h743-eval/Kconfig"
source "board/st/stm32h743-disco/Kconfig"
+source "board/st/stm32h750-art-pi/Kconfig"
endif
diff --git a/board/st/stm32h750-art-pi/Kconfig
b/board/st/stm32h750-art-pi/Kconfig
new file mode 100644
index 000..c31b984
--- /dev/null
+++ b/board/st/stm32h750-art-pi/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM32H750_ART_PI
+
+config SYS_BOARD
+ string
+ default "stm32h750-art-pi"
+
+config SYS_VENDOR
+ string
+ default "st"
+
+config SYS_SOC
+ string
+ default "stm32h7"
+
+config SYS_CONFIG_NAME
+ string
+ default "stm32h750-art-pi"
+
+endif
diff --git a/board/st/stm32h750-art-pi/MAINTAINERS
b/board/st/stm32h750-art-pi/MAINTAINERS
new file mode 100644
index 000..9578833
--- /dev/null
+++ b/board/st/stm32h750-art-pi/MAINTAINERS
@@ -0,0 +1,7 @@
+STM32H750 ART PI BOARD
+M: Dillon Min
+S: Maintained
+F: board/st/stm32h750-art-pi
+F: include/configs/stm32h750-art-pi.h
+F: configs/stm32h750-art-pi_defconfig
+F: arch/arm/dts/stm32h7*
diff --git a/board/st/stm32h750-art-pi/Makefile
b/board/st/stm32h750-art-pi/Makefile
new file mode 100644
index 000..a06de87
--- /dev/null
+++ b/board/st/stm32h750-art-pi/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021, RT-Thread - All Rights Reserved
+# Author(s): Dillon Min, for RT-Thread.
+
+obj-y := stm32h750-art-pi.o
diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c
b/board/st/stm32h750-art-pi/stm32h750-art-pi.c
new file mode 100644
index 000..c374dd3
--- /dev/null
+++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, STMicroelectronics - All Rights Reserved
+ * Author(s): Dillon Min for STMicroelectronics.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ if (fdtdec_setup_mem_size_base() != 0)
+ ret = -EINVAL;
+
+ return ret;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+ return 0;
+}
diff --git a/configs/stm32h750-art-pi_defconfig
b/configs/stm32h750-art-pi_defconfig
new file mode 100644
index 000..447af5b
--- /dev/null
+++ b/configs/stm32h750-art-pi_defconfig
@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32=y
+CONFIG_SYS_TEXT_BASE=0x9000
+CONFIG_SYS_MALLOC_F_LEN=0xF00
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_STM32H7=y
+CONFIG_TARGET_STM32H750_ART_PI=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=3
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_DEFAULT_FDT_FILE="stm32h750i-art-pi"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_
[PATCH v4 6/7] ram: stm32: fix strsep failed on read only memory
From: dillon min
strsep will change data from original memory address,
in case the memory is in non-sdram/sram place, will
run into a bug(hang at SDRAM: )
just add a temporary array to store bank_name[] to fix this
bug.
Signed-off-by: dillon min
---
v4: use strlcpy suggested by Patrice CHOTARD
drivers/ram/stm32_sdram.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
index 540ad85..3e25cc7 100644
--- a/drivers/ram/stm32_sdram.c
+++ b/drivers/ram/stm32_sdram.c
@@ -268,6 +268,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
u32 swp_fmc;
ofnode bank_node;
char *bank_name;
+ char _bank_name[128] = {0};
u8 bank = 0;
int ret;
@@ -300,6 +301,8 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
dev_for_each_subnode(bank_node, dev) {
/* extract the bank index from DT */
bank_name = (char *)ofnode_get_name(bank_node);
+ strlcpy(_bank_name, bank_name, sizeof(_bank_name));
+ bank_name = (char *)_bank_name;
strsep(&bank_name, "@");
if (!bank_name) {
pr_err("missing sdram bank index");
--
2.7.4
[PATCH v4 5/7] ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6
From: dillon min
This patchset has following changes:
- introduce stm32h750.dtsi to support stm32h750 value line
- add pin groups for usart3/uart4/spi1/sdmmc2
- add stm32h750i-art-pi.dtb (arch/arm/boot/dts/Makefile)
- add stm32h750i-art-pi.dts to support art-pi board
- add stm32h750i-art-pi-u-boot.dtsi to support art-pi board (u-boot)
art-pi board component:
- 8MiB qspi flash
- 16MiB spi flash
- 32MiB sdram
- ap6212 wifi&bt&fm
the detail board information can be found at:
https://art-pi.gitee.io/website/
Signed-off-by: dillon min
---
v4: no changes
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/stm32h7-pinctrl.dtsi | 89 ++
arch/arm/dts/stm32h750.dtsi| 5 +
arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi | 81 +
arch/arm/dts/stm32h750i-art-pi.dts | 188 +
include/dt-bindings/memory/stm32-sdram.h | 2 +
6 files changed, 367 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/stm32h750.dtsi
create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c671082..0f54801 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -454,7 +454,8 @@ dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
stm32f769-disco.dtb \
stm32746g-eval.dtb
dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
- stm32h743i-eval.dtb
+ stm32h743i-eval.dtb \
+ stm32h750i-art-pi.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
diff --git a/arch/arm/dts/stm32h7-pinctrl.dtsi
b/arch/arm/dts/stm32h7-pinctrl.dtsi
index f6968b5..aefa324 100644
--- a/arch/arm/dts/stm32h7-pinctrl.dtsi
+++ b/arch/arm/dts/stm32h7-pinctrl.dtsi
@@ -137,6 +137,80 @@
};
};
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+ pins {
+ pinmux = , /* SDMMC1_D0 */
+, /* SDMMC1_D1 */
+, /* SDMMC1_D2 */
+, /* SDMMC1_D3 */
+, /* SDMMC1_CK */
+; /* SDMMC1_CMD */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
+ pins1 {
+ pinmux = , /* SDMMC2_D0 */
+, /* SDMMC1_D1 */
+, /* SDMMC1_D2 */
+, /* SDMMC1_D3 */
+; /* SDMMC1_CK */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2{
+ pinmux = ; /* SDMMC1_CMD */
+ slew-rate = <3>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
+ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
+ pins {
+ pinmux = , /* SDMMC1_D0
*/
+, /* SDMMC1_D1
*/
+, /* SDMMC1_D2 */
+, /* SDMMC1_D3 */
+, /* SDMMC1_CK */
+; /* SDMMC1_CMD
*/
+ };
+ };
+
+ spi1_pins: spi1-0 {
+ pins1 {
+ pinmux = ,
+ /* SPI1_CLK */
+;
+ /* SPI1_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = ;
+ /* SPI1_MISO */
+ bias-disable;
+ };
+ };
+
+ uart4_pins: uart4-0 {
+ pins1 {
+ pinmux = ; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = ; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
usart1_pins: usart1-0 {
pins1 {
pinmux = ; /* USART1_TX */
@@ -163,6 +237,21 @@
};
};
+ usart3_pins: usart3-0 {
+ pins1 {
+ pinmux = , /* USART3_TX */
+; /* USART3_RTS_DE
*/
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = , /* USART3_RX */
+; /*
USART3_CT
[PATCH v4 4/7] ARM: dts: stm32: fix i2c node typo in stm32h743, update dmamux1 register
From: dillon min
Replace upper case by lower case in i2c nodes name.
update dmamux1 register range.
Signed-off-by: dillon min
---
v4: sync with kernel side commit
link:
https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git/commit/?h=stm32-dt-for-v5.13&id=978783f90ab71f830207b7e9b49ab819cfd89dd4
arch/arm/dts/stm32h743.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index 77a8aef..ed68575 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -139,7 +139,7 @@
status = "disabled";
};
- i2c3: i2c@40005C00 {
+ i2c3: i2c@40005c00 {
compatible = "st,stm32f7-i2c";
#address-cells = <1>;
#size-cells = <0>;
@@ -254,7 +254,7 @@
dmamux1: dma-router@40020800 {
compatible = "st,stm32h7-dmamux";
- reg = <0x40020800 0x1c>;
+ reg = <0x40020800 0x40>;
#dma-cells = <3>;
dma-channels = <16>;
dma-requests = <128>;
@@ -386,7 +386,7 @@
status = "disabled";
};
- i2c4: i2c@58001C00 {
+ i2c4: i2c@58001c00 {
compatible = "st,stm32f7-i2c";
#address-cells = <1>;
#size-cells = <0>;
--
2.7.4
[PATCH v4 3/7] ARM: dts: stm32: add new instances for stm32h743 MCU
From: dillon min
Some instances are missing in current support of stm32h743 MCU. This commit
adds usart3/uart4 and sdmmc2 support.
Signed-off-by: dillon min
---
v4: sync with kernel side commit
link:
https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git/commit/?h=stm32-dt-for-v5.13&id=4e1593391fa38c0a8ec0f314f37ec5543475bf9d
arch/arm/dts/stm32h743.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index 8c96698..77a8aef 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -99,6 +99,22 @@
clocks = <&rcc USART2_CK>;
};
+ usart3: serial@40004800 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40004800 0x400>;
+ interrupts = <39>;
+ status = "disabled";
+ clocks = <&rcc USART3_CK>;
+ };
+
+ uart4: serial@40004c00 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40004c00 0x400>;
+ interrupts = <52>;
+ status = "disabled";
+ clocks = <&rcc UART4_CK>;
+ };
+
i2c1: i2c@40005400 {
compatible = "st,stm32f7-i2c";
#address-cells = <1>;
@@ -332,6 +348,20 @@
max-frequency = <12000>;
};
+ sdmmc2: sdmmc@48022400 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x10153180>;
+ reg = <0x48022400 0x400>;
+ interrupts = <124>;
+ interrupt-names = "cmd_irq";
+ clocks = <&rcc SDMMC2_CK>;
+ clock-names = "apb_pclk";
+ resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <12000>;
+ };
+
exti: interrupt-controller@5800 {
compatible = "st,stm32h7-exti";
interrupt-controller;
--
2.7.4
[PATCH v4 2/7] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750
From: dillon min
This patch is intend to add support stm32h750 value line,
just add stm32h7-pinctrl.dtsi for extending, with following changes:
- rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi
- move 'pin-controller' from stm32h7-pinctrl.dtsi to stm32h743.dtsi
- update stm32h743i-{disco, eval}.dts to include stm32h7-pinctrl.dtsi
Signed-off-by: dillon min
---
v4: sync with kernel side commit
link:
https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git/commit/?h=stm32-dt-for-v5.13&id=d3f715e63f2d6ff98fd4426015847f3442b8805f
arch/arm/dts/stm32h7-pinctrl.dtsi | 185 ++
arch/arm/dts/stm32h743-pinctrl.dtsi | 306
arch/arm/dts/stm32h743.dtsi | 142 +
arch/arm/dts/stm32h743i-disco.dts | 2 +-
arch/arm/dts/stm32h743i-eval.dts| 2 +-
5 files changed, 329 insertions(+), 308 deletions(-)
create mode 100644 arch/arm/dts/stm32h7-pinctrl.dtsi
delete mode 100644 arch/arm/dts/stm32h743-pinctrl.dtsi
diff --git a/arch/arm/dts/stm32h7-pinctrl.dtsi
b/arch/arm/dts/stm32h7-pinctrl.dtsi
new file mode 100644
index 000..f6968b5
--- /dev/null
+++ b/arch/arm/dts/stm32h7-pinctrl.dtsi
@@ -0,0 +1,185 @@
+/*
+ * Copyright 2017 - Alexandre Torgue
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+
+&pinctrl {
+
+ i2c1_pins_a: i2c1-0 {
+ pins {
+ pinmux = , /* I2C1_SCL */
+; /* I2C1_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ ethernet_rmii: rmii-0 {
+ pins {
+ pinmux = ,
+,
+,
+,
+,
+,
+,
+,
+;
+ slew-rate = <2>;
+ };
+ };
+
+ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+ pins {
+ pinmux = , /* SDMMC1_D0 */
+, /* SDMMC1_D1 */
+, /* SDMMC1_D2 */
+, /* SDMMC1_D3 */
+, /* SDMMC1_CK */
+; /* SDMMC1_CMD */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+ pins1 {
+ pinmux = , /* SDMMC1_D0 */
+, /* SDMMC1_D1 */
+, /* SDMMC1_D2 */
+, /* SDMMC1_D3 */
+; /* SDMMC1_CK */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-disable;
+ };
+
[PATCH v4 1/7] ARM: dts: stm32: split sdram pin & timing parameter into specific board dts
From: dillon min
As different boards has their own sdram hw connection, mount different
sdram modules, so move sdram timing parameter and pin configuration
to their board device tree.
Signed-off-by: dillon min
Reviewed-by: Patrice Chotard
---
v4: no changes
arch/arm/dts/stm32h7-u-boot.dtsi | 100 ++
arch/arm/dts/stm32h743i-disco-u-boot.dtsi | 98 +
arch/arm/dts/stm32h743i-eval-u-boot.dtsi | 98 +
3 files changed, 201 insertions(+), 95 deletions(-)
diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
index 54dd406..84dc765 100644
--- a/arch/arm/dts/stm32h7-u-boot.dtsi
+++ b/arch/arm/dts/stm32h7-u-boot.dtsi
@@ -20,6 +20,7 @@
gpio9 = &gpioj;
gpio10 = &gpiok;
mmc0 = &sdmmc1;
+ pinctrl0 = &pinctrl;
};
soc {
@@ -36,30 +37,6 @@
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
status = "okay";
-
- /*
-* Memory configuration from sdram datasheet
IS42S32800G-6BLI
-* first bank is bank@0
-* second bank is bank@1
-*/
- bank1: bank@1 {
- st,sdram-control = /bits/ 8 ;
- st,sdram-timing = /bits/ 8 ;
- st,sdram-refcount = <1539>;
- };
};
};
};
@@ -136,77 +113,6 @@
compatible = "st,stm32-gpio";
};
-&pinctrl {
- fmc_pins: fmc@0 {
- pins {
- pinmux = ,
-,
-,
-,
-,
-,
-,
-
-,
-,
-,
-,
-,
-,
-,
-,
-,
-,
-,
-
-,
-,
-,
-,
-,
-,
-,
-,
-,
-,
-,
-
-,
-,
-,
-,
-,
-,
-,
-
-,
-,
-,
-,
-,
-,
-,
-,
-,
-,
-,
-
-,
-,
-,
-,
-,
-,
-,
-,
-,
-;
-
- slew-rate = <3>;
- };
- };
-};
-
&pwrcfg {
u-boot,dm-pre-reloc;
};
@@ -222,3 +128,7 @@
&timer5 {
u-boot,dm-pre-reloc;
};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
index 5965afc..02e28c6 100644
--- a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
@@ -1,3 +1,101 @@
// SPDX-License-Identifier: GPL-2.0+
#include
+
+&fmc {
+
+ /*
+* Memory configuration from sdram datasheet IS42S32800G-6BLI
+* first bank is bank@0
+* second bank is bank@1
+*/
+ bank1: bank@1 {
+ st,sdram-control = /bits/ 8 ;
+ st,sdram-timing = /bits/ 8 ;
+ st,sdram-refcount = <1539>;
+ };
+};
+
+&pinctrl {
+ fmc_pins: fmc@0 {
+ pins {
+ pinmux = ,
+,
+,
+,
+,
+,
+,
+
+,
+,
+
[PATCH v4 0/7] Add rt-thread art-pi board support
From: dillon min These patches aim to adds u-boot support on art-pi board. the board resources: - stm32h750xbh6 128k flash, 1024k sram - 32MiB sdram - 16MiB spi flash - 8MiB qspi flash - onboard wifi, bt, fm the detail board information can be found at: https://art-pi.gitee.io/website/ --- changes in v4: - sync with kernel side device tree submit - use strlcpy in stm32_sdram.c - update CONFIG_BOOTARGS, remove rdinit=/linuxrc, to use kernel's devtmpfs - remove unused st,stm32h750-pinctrl from patch v3 changes in v3: two mirror changes in [PATCH v3 2/6], others same to version 2 - remove "for STMicroelectronics." from arch/arm/dts/stm32h750-pinctrl.dtsi - correct misspelling parameters you can found detail patch v2 information at link: https://patchwork.ozlabs.org/project/uboot/list/?series=236009 changes in v2: - fix wrong author/date in previous submit - sync with kernel device tree files - add st,stm32h750-pinctrl in doc and pinctrl driver *** BLURB HERE *** dillon min (7): ARM: dts: stm32: split sdram pin & timing parameter into specific board dts ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750 ARM: dts: stm32: add new instances for stm32h743 MCU ARM: dts: stm32: fix i2c node typo in stm32h743, update dmamux1 register ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6 ram: stm32: fix strsep failed on read only memory board: Add rt-thread art-pi board support arch/arm/dts/Makefile| 3 +- arch/arm/dts/stm32h7-pinctrl.dtsi| 274 arch/arm/dts/stm32h7-u-boot.dtsi | 100 + arch/arm/dts/stm32h743-pinctrl.dtsi | 306 --- arch/arm/dts/stm32h743.dtsi | 178 +++- arch/arm/dts/stm32h743i-disco-u-boot.dtsi| 98 + arch/arm/dts/stm32h743i-disco.dts| 2 +- arch/arm/dts/stm32h743i-eval-u-boot.dtsi | 98 + arch/arm/dts/stm32h743i-eval.dts | 2 +- arch/arm/dts/stm32h750.dtsi | 5 + arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi | 81 +++ arch/arm/dts/stm32h750i-art-pi.dts | 188 arch/arm/mach-stm32/stm32h7/Kconfig | 4 + board/st/stm32h750-art-pi/Kconfig| 19 ++ board/st/stm32h750-art-pi/MAINTAINERS| 7 + board/st/stm32h750-art-pi/Makefile | 6 + board/st/stm32h750-art-pi/stm32h750-art-pi.c | 58 + configs/stm32h750-art-pi_defconfig | 51 + drivers/ram/stm32_sdram.c| 3 + include/configs/stm32h750-art-pi.h | 48 + include/dt-bindings/memory/stm32-sdram.h | 2 + 21 files changed, 1126 insertions(+), 407 deletions(-) create mode 100644 arch/arm/dts/stm32h7-pinctrl.dtsi delete mode 100644 arch/arm/dts/stm32h743-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32h750.dtsi create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts create mode 100644 board/st/stm32h750-art-pi/Kconfig create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS create mode 100644 board/st/stm32h750-art-pi/Makefile create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c create mode 100644 configs/stm32h750-art-pi_defconfig create mode 100644 include/configs/stm32h750-art-pi.h -- 2.7.4
[PATCH v2 1/2] dm: core: Add size operations on device tree references
Add functions to add size of addresses in the device tree using ofnode
references.
Signed-off-by: Chen Guanqiao
---
drivers/core/ofnode.c | 9 +
include/dm/ofnode.h | 10 ++
2 files changed, 19 insertions(+)
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index fa0bd2a9c4..952c3cf9dd 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -347,6 +347,15 @@ fdt_addr_t ofnode_get_addr(ofnode node)
return ofnode_get_addr_index(node, 0);
}
+fdt_size_t ofnode_get_size(ofnode node)
+{
+ fdt_size_t size;
+
+ ofnode_get_addr_size_index(node, 0, &size);
+
+ return size;
+}
+
int ofnode_stringlist_search(ofnode node, const char *property,
const char *string)
{
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 2c0597c407..e91f81282b 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -510,6 +510,16 @@ phys_addr_t ofnode_get_addr_index(ofnode node, int index);
*/
phys_addr_t ofnode_get_addr(ofnode node);
+/**
+ * ofnode_get_size() - get size from a node
+ *
+ * This reads the register size from a node
+ *
+ * @node: node to read from
+ * @return size of the address
+ */
+fdt_size_t ofnode_get_size(ofnode node);
+
/**
* ofnode_stringlist_search() - find a string in a string list and return index
*
--
2.25.1
[PATCH v2 2/2] test: dm: add test item for ofnode_get_addr() and ofnode_get_size()
Add test item for getting address and size functions
Test the following function:
- ofnode_get_addr()
- ofnode_get_size()
Signed-off-by: Chen Guanqiao
---
test/dm/ofnode.c | 24
1 file changed, 24 insertions(+)
diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c
index c539134296..0d958b4900 100644
--- a/test/dm/ofnode.c
+++ b/test/dm/ofnode.c
@@ -261,3 +261,27 @@ static int dm_test_ofnode_is_enabled(struct
unit_test_state *uts)
return 0;
}
DM_TEST(dm_test_ofnode_is_enabled, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+static int dm_test_ofnode_get_reg(struct unit_test_state *uts)
+{
+ ofnode node;
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ node = ofnode_path("/translation-test@8000");
+ ut_assert(ofnode_valid(node));
+ addr = ofnode_get_addr(node);
+ size = ofnode_get_size(node);
+ ut_asserteq(0x8000, addr);
+ ut_asserteq(0x4000, size);
+
+ node = ofnode_path("/translation-test@8000/dev@1,100");
+ ut_assert(ofnode_valid(node));
+ addr = ofnode_get_addr(node);
+ size = ofnode_get_size(node);
+ ut_asserteq(0x9000, addr);
+ ut_asserteq(0x1000, size);
+
+ return 0;
+}
+DM_TEST(dm_test_ofnode_get_reg, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
--
2.25.1
[PATCH v2 0/2] dm: core: Add size operations on device tree references
Currently, there is only an interface for obtaining address from node, and if you want to get the size, you need to traverse the node. So I added the function to get the size ,and added related test case. Changes for v2: - Add a test to test/dm/ofnode.c Chen Guanqiao (2): dm: core: Add size operations on device tree references test: dm: add test item for ofnode_get_addr() and ofnode_get_size() drivers/core/ofnode.c | 9 + include/dm/ofnode.h | 10 ++ test/dm/ofnode.c | 24 3 files changed, 43 insertions(+) -- 2.25.1
RK1808 DDR3 test uboot
Hi everyone, hope is the right place to ask but we are running out of ideas hehe, we need some help with a problem we have for a rockchip rk1808 based pcb we designed related with our DDR memory: So the problem is that we are not able to go further from the execution of the ddr init code from psram, and we need to figure out a way to see if there is a problem with the ddr (we are using LPDDR3 2G). There seems to be possible to run some tests, from firefly chinese forum we found `Rockchip Platform DDR Test Tool` https://dev.t-firefly.com/thread-13005-1-1.html the tool provides cfg files to run a solder test ie: 1GB LPDDR3(128Mbx32bit x 2CS)soldering Test.cfg they published the tool recently for rk3399 too, but it doesn't work for rk1808, do you know of any way to run this kind of test from u-boot? or by chance do you know how to modify or generate a DDR init binary to run a DDR memory test too? So far we have been able to change the frequencies and test all of them for our DDR with ` ddrbin_tool` from rockchip rkbin repository, but we always get only this output on UART, ``` DDR Version V1.04 20191121 LPDDR3 333MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=32 Size=1024MB out ``` Any help deeply appreciated, also if there is another place i should ask, please let me know, we also tried to reach out rockchip team without luck. I also send the question to linux-rockchip mail list.
[PATCH 19/19] ARM: imx8m: verdin-imx8mm: Enable USB Host support
Enable USB host support on MX8MM Verdin. Signed-off-by: Marek Vasut Cc: Marcel Ziswiler Cc: Max Krummenacher Cc: Oleksandr Suvorov --- configs/verdin-imx8mm_defconfig | 8 +++- include/configs/verdin-imx8mm.h | 6 ++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index ea0b5978f1f..c8c3420b6a5 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -37,7 +37,6 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SYS_PROMPT="Verdin iMX8MM # " # CONFIG_BOOTM_NETBSD is not set @@ -50,6 +49,7 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_CMD_REGULATOR=y @@ -89,6 +89,8 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_PMIC=y CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_PMIC_PFUZE100=y @@ -101,5 +103,9 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_EHCI_HCD=y CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 4751bf5a5af..e3ba08dc69c 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -117,5 +117,11 @@ #define FEC_QUIRK_ENET_MAC #define IMX_FEC_BASE 0x30BE +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + #endif /*_VERDIN_IMX8MM_H */ -- 2.30.2
[PATCH 18/19] usb: ehci-mx6: Add iMX8M support
The iMX8M uses nop PHY, select PHY and NOP_PHY automatically. Otherwise, the DM capable driver is now perfectly compatible. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Cc: Ye Li Cc: uboot-imx --- drivers/usb/host/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0971a7c8139..a51183d4d3c 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -156,7 +156,9 @@ config USB_EHCI_MX6 config USB_EHCI_MX7 bool "Support for i.MX7 on-chip EHCI USB controller" - depends on ARCH_MX7 + depends on ARCH_MX7 || IMX8MM + select PHY if IMX8MM + select NOP_PHY if IMX8MM default y ---help--- Enables support for the on-chip EHCI controller on i.MX7 SoCs. -- 2.30.2
[PATCH 17/19] usb: ehci-mx6: Add fsl,imx7d-usb compatible string
Add new compatible string, used by some more up-to-date DTs.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
drivers/usb/host/ehci-mx6.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 855a1bdaaa2..c218bdc0574 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -736,6 +736,7 @@ int ehci_usb_remove(struct udevice *dev)
static const struct udevice_id mx6_usb_ids[] = {
{ .compatible = "fsl,imx27-usb" },
+ { .compatible = "fsl,imx7d-usb" },
{ }
};
--
2.30.2
[PATCH 16/19] usb: ehci-mx6: Add generic EHCI PHY support
In case PHY support is enabled, use the generic EHCI PHY support
to start and stop the PHY.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
drivers/usb/host/ehci-mx6.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index b1cc62fcc37..855a1bdaaa2 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -413,6 +413,7 @@ struct ehci_mx6_priv_data {
struct usb_ehci *ehci;
struct udevice *vbus_supply;
struct clk clk;
+ struct phy phy;
enum usb_init_type init_type;
#if !defined(CONFIG_PHY)
/* Legacy iMX6/iMX7/iMX7ULP compat, they do not use PHY framework yet */
@@ -676,16 +677,26 @@ static int ehci_usb_probe(struct udevice *dev)
mdelay(10);
+#if defined(CONFIG_PHY)
+ ret = ehci_setup_phy(dev, &priv->phy, 0);
+ if (ret)
+ goto err_regulator;
+#endif
+
hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
hcor = (struct ehci_hcor *)((uint32_t)hccr +
HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
ret = ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
if (ret)
- goto err_regulator;
+ goto err_phy;
return ret;
+err_phy:
+#if defined(CONFIG_PHY)
+ ehci_shutdown_phy(dev, &priv->phy);
+#endif
err_regulator:
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply)
@@ -707,6 +718,10 @@ int ehci_usb_remove(struct udevice *dev)
ehci_deregister(dev);
+#if defined(CONFIG_PHY)
+ ehci_shutdown_phy(dev, &priv->phy);
+#endif
+
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply)
regulator_set_enable(priv->vbus_supply, false);
--
2.30.2
[PATCH 15/19] usb: ehci-mx6: Use portnr in DM only if PHY is disabled
In case of legacy platforms which do not implement PHY support,
determine portnr from PHY node DT aliases, just like Linux does.
This is not necessary in case PHY support is enabled and a PHY
driver is available, so only enable the portnr handling for the
legacy platforms.
Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
drivers/usb/host/ehci-mx6.c | 54 ++---
1 file changed, 8 insertions(+), 46 deletions(-)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 345be528739..b1cc62fcc37 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -414,12 +414,12 @@ struct ehci_mx6_priv_data {
struct udevice *vbus_supply;
struct clk clk;
enum usb_init_type init_type;
- int portnr;
#if !defined(CONFIG_PHY)
/* Legacy iMX6/iMX7/iMX7ULP compat, they do not use PHY framework yet */
void __iomem *phy_addr;
void __iomem *misc_addr;
void __iomem *anatop_addr;
+ int portnr;
#endif
};
@@ -541,49 +541,6 @@ static int ehci_usb_of_to_plat(struct udevice *dev)
return 0;
}
-static int ehci_usb_bind(struct udevice *dev)
-{
- /*
-* TODO:
-* This driver is only partly converted to DT probing and still uses
-* a tremendous amount of hard-coded addresses. To make things worse,
-* the driver depends on specific sequential indexing of controllers,
-* from which it derives offsets in the PHY and ANATOP register sets.
-*
-* Here we attempt to calculate these indexes from DT information as
-* well as we can. The USB controllers on all existing iMX6 SoCs
-* are placed next to each other, at addresses incremented by 0x200,
-* and iMX7 their addresses are shifted by 0x1.
-* Thus, the index is derived from the multiple of 0x200 (0x1 for
-* iMX7) offset from the first controller address.
-*
-* However, to complete conversion of this driver to DT probing, the
-* following has to be done:
-* - DM clock framework support for iMX must be implemented
-* - usb_power_config() has to be converted to clock framework
-* -> Thus, the ad-hoc "index" variable goes away.
-* - USB PHY handling has to be factored out into separate driver
-* -> Thus, the ad-hoc "index" variable goes away from the PHY
-* code, the PHY driver must parse it's address from DT. This
-* USB driver must find the PHY driver via DT phandle.
-* -> usb_power_config() shall be moved to PHY driver
-* With these changes in place, the ad-hoc indexing goes away and
-* the driver is fully converted to DT probing.
-*/
-
- /*
-* FIXME: This cannot work with the new sequence numbers.
-* Please complete the DM conversion.
-*
-* u32 controller_spacing = is_mx7() ? 0x1 : 0x200;
-* fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
-*
-* dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing;
-*/
-
- return 0;
-}
-
static int mx6_parse_dt_addrs(struct udevice *dev)
{
#if !defined(CONFIG_PHY)
@@ -596,11 +553,17 @@ static int mx6_parse_dt_addrs(struct udevice *dev)
const void *blob = gd->fdt_blob;
int offset = dev_of_offset(dev);
void *__iomem addr;
+ int ret, devnump;
phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy");
if (phy_off < 0)
return -EINVAL;
+ ret = fdtdec_get_alias_seq(blob, dev->uclass->uc_drv->name,
+ phy_off, &devnump);
+ if (ret < 0)
+ return ret;
+
misc_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbmisc");
if (misc_off < 0)
return -EINVAL;
@@ -610,6 +573,7 @@ static int mx6_parse_dt_addrs(struct udevice *dev)
return -EINVAL;
priv->phy_addr = addr;
+ priv->portnr = devnump;
addr = (void __iomem *)fdtdec_get_addr(blob, misc_off, "reg");
if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
@@ -656,7 +620,6 @@ static int ehci_usb_probe(struct udevice *dev)
return ret;
priv->ehci = ehci;
- priv->portnr = dev_seq(dev);
priv->init_type = type;
#if CONFIG_IS_ENABLED(CLK)
@@ -766,7 +729,6 @@ U_BOOT_DRIVER(usb_mx6) = {
.id = UCLASS_USB,
.of_match = mx6_usb_ids,
.of_to_plat = ehci_usb_of_to_plat,
- .bind = ehci_usb_bind,
.probe = ehci_usb_probe,
.remove = ehci_usb_remove,
.ops= &ehci_usb_ops,
--
2.30.2
[PATCH 14/19] usb: ehci-mx6: Pass MISC address to usb_oc_config()
Instead of passing ad-hoc sequence number to usb_oc_config(), pass in
the USB MISC address itself. The USB MISC address comes from DT in DM
case, and from the old method using controller index in non-DM case.
Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
drivers/usb/host/ehci-mx6.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 5001a8e74fb..345be528739 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -248,15 +248,8 @@ int usb_phy_mode(int port)
}
#endif
-static void usb_oc_config(int index)
+static void usb_oc_config(struct usbnc_regs *usbnc, int index)
{
-#if defined(CONFIG_MX6)
- struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
- USB_OTHERREGS_OFFSET);
-#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
- struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
- (0x1 * index) + USBNC_OFFSET);
-#endif
void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
@@ -331,6 +324,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
u32 controller_spacing = 0x200;
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+ struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+ USB_OTHERREGS_OFFSET);
#elif defined(CONFIG_MX7)
u32 controller_spacing = 0x1;
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
@@ -339,6 +334,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
u32 controller_spacing = 0x1;
struct usbphy_regs __iomem *usbphy =
(struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
+ struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+ (0x1 * index) + USBNC_OFFSET);
#endif
struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
(controller_spacing * index));
@@ -373,7 +370,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
usb_power_config_mx7ulp(usbphy);
#endif
- usb_oc_config(index);
+ usb_oc_config(usbnc, index);
#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
if (index < ARRAY_SIZE(phy_bases)) {
@@ -438,7 +435,7 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
usb_power_config_mx7(priv->misc_addr);
usb_power_config_mx7ulp(priv->phy_addr);
- usb_oc_config(priv->portnr);
+ usb_oc_config(priv->misc_addr, priv->portnr);
#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(priv->phy_addr, 1);
@@ -688,7 +685,7 @@ static int ehci_usb_probe(struct udevice *dev)
usb_power_config_mx7(priv->usbnc);
usb_power_config_mx7ulp(priv->usbphy);
- usb_oc_config(priv->portnr);
+ usb_oc_config(priv->misc_addr, priv->portnr);
#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(priv->phy_addr, 1);
--
2.30.2
[PATCH 13/19] usb: ehci-mx6: Split usb_power_config()
Split usb_power_config() per SoC and pass in USB PHY, USBNC and ANATOP
addresses instead of ad-hoc sequence numbers. This is only applicable
on legacy systems which do not implement proper PHY support. Once PHY
support is available, parts of this can be removed altogether and moved
to the PHY driver, similar to Linux phy-mxs-usb.c .
Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
drivers/usb/host/ehci-mx6.c | 127 ++--
1 file changed, 78 insertions(+), 49 deletions(-)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 800a25d1d9d..5001a8e74fb 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -86,43 +86,17 @@ struct usbnc_regs {
u32 adp_status;
};
-#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
-static const unsigned phy_bases[] = {
- USB_PHY0_BASE_ADDR,
-#if defined(USB_PHY1_BASE_ADDR)
- USB_PHY1_BASE_ADDR,
-#endif
-};
-
-static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
-{
- phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
- writel(USBPHY_CTRL_CLKGATE, phy_reg);
-}
-
-static void usb_power_config(int index)
+#if defined(CONFIG_MX6)
+static void usb_power_config_mx6(void __iomem *anatop, int anatop_bits_index)
{
-#if defined(CONFIG_MX7ULP)
- struct usbphy_regs __iomem *usbphy =
- (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
-
- if (index > 0)
- return;
-
- writel(ANADIG_USB2_CHRG_DETECT_EN_B |
- ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
- &usbphy->usb1_chrg_detect);
-
- scg_enable_usb_pll(true);
-
-#else
- struct anatop_regs __iomem *anatop =
- (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
void __iomem *chrg_detect;
void __iomem *pll_480_ctrl_clr;
void __iomem *pll_480_ctrl_set;
- switch (index) {
+ if (!is_mx6())
+ return;
+
+ switch (anatop_bits_index) {
case 0:
chrg_detect = &anatop->usb1_chrg_detect;
pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
@@ -155,8 +129,51 @@ static void usb_power_config(int index)
ANADIG_USB2_PLL_480_CTRL_POWER |
ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
pll_480_ctrl_set);
+}
+#endif
+
+#if defined(CONFIG_MX7)
+static void usb_power_config_mx7(struct usbnc_regs *usbnc)
+{
+ void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
+
+ if (!is_mx7())
+ return;
+
+ /*
+* Clear the ACAENB to enable usb_otg_id detection,
+* otherwise it is the ACA detection enabled.
+*/
+ clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
+}
+#endif
+
+#if defined(CONFIG_MX7ULP)
+static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
+{
+ if (!is_mx7ulp())
+ return;
+
+ writel(ANADIG_USB2_CHRG_DETECT_EN_B |
+ ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
+ &usbphy->usb1_chrg_detect);
+
+ scg_enable_usb_pll(true);
+}
+#endif
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
+static const unsigned phy_bases[] = {
+ USB_PHY0_BASE_ADDR,
+#if defined(USB_PHY1_BASE_ADDR)
+ USB_PHY1_BASE_ADDR,
#endif
+};
+
+static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
+{
+ phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
+ writel(USBPHY_CTRL_CLKGATE, phy_reg);
}
/* Return 0 : host node, <>0 : device mode */
@@ -215,19 +232,6 @@ int usb_phy_mode(int port)
}
#elif defined(CONFIG_MX7)
-static void usb_power_config(int index)
-{
- struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
- (0x1 * index) + USBNC_OFFSET);
- void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
-
- /*
-* Clear the ACAENB to enable usb_otg_id detection,
-* otherwise it is the ACA detection enabled.
-*/
- clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
-}
-
int usb_phy_mode(int port)
{
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
@@ -325,8 +329,16 @@ int ehci_hcd_init(int index, enum usb_init_type init,
enum usb_init_type type;
#if defined(CONFIG_MX6)
u32 controller_spacing = 0x200;
-#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
+ struct anatop_regs __iomem *anatop =
+ (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+#elif defined(CONFIG_MX7)
+ u32 controller_spacing = 0x1;
+ struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+ (0x1 * index) + USBNC_OFFSET);
+#elif defined(CONFIG_MX7ULP)
u32 controller_spacing = 0x1;
+ struct usbphy_regs __iomem *usbphy =
+ (struct usbphy_reg
[PATCH 12/19] usb: ehci-mx6: Pass PHY address to usb_*_phy*()
Instead of passing ad-hoc index to USB PHY handling functions and then
try and figure out the PHY address, pass in the PHY address itself. For
DM case, this address comes easily from DT. For non-DM case, the previous
method is still present, however the non-DM case will soon be removed.
Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
drivers/usb/host/ehci-mx6.c | 29 ++---
1 file changed, 10 insertions(+), 19 deletions(-)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index b195ba4c89b..800a25d1d9d 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -94,14 +94,8 @@ static const unsigned phy_bases[] = {
#endif
};
-static void usb_internal_phy_clock_gate(int index, int on)
+static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
{
- void __iomem *phy_reg;
-
- if (index >= ARRAY_SIZE(phy_bases))
- return;
-
- phy_reg = (void __iomem *)phy_bases[index];
phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
writel(USBPHY_CTRL_CLKGATE, phy_reg);
}
@@ -166,17 +160,12 @@ static void usb_power_config(int index)
}
/* Return 0 : host node, <>0 : device mode */
-static int usb_phy_enable(int index, struct usb_ehci *ehci)
+static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg)
{
- void __iomem *phy_reg;
void __iomem *phy_ctrl;
void __iomem *usb_cmd;
int ret;
- if (index >= ARRAY_SIZE(phy_bases))
- return 0;
-
- phy_reg = (void __iomem *)phy_bases[index];
phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
usb_cmd = (void __iomem *)&ehci->usbcmd;
@@ -368,8 +357,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
usb_oc_config(index);
#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
- usb_internal_phy_clock_gate(index, 1);
- usb_phy_enable(index, ehci);
+ if (index < ARRAY_SIZE(phy_bases)) {
+ usb_internal_phy_clock_gate((void __iomem *)phy_bases[index],
1);
+ usb_phy_enable(ehci, (void __iomem *)phy_bases[index]);
+ }
#endif
type = board_usb_phy_mode(index);
@@ -427,8 +418,8 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
usb_oc_config(priv->portnr);
#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
- usb_internal_phy_clock_gate(priv->portnr, 1);
- usb_phy_enable(priv->portnr, ehci);
+ usb_internal_phy_clock_gate(priv->phy_addr, 1);
+ usb_phy_enable(ehci, priv->phy_addr);
#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
@@ -672,8 +663,8 @@ static int ehci_usb_probe(struct udevice *dev)
usb_oc_config(priv->portnr);
#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
- usb_internal_phy_clock_gate(priv->portnr, 1);
- usb_phy_enable(priv->portnr, ehci);
+ usb_internal_phy_clock_gate(priv->phy_addr, 1);
+ usb_phy_enable(ehci, priv->phy_addr);
#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
--
2.30.2
[PATCH 11/19] usb: ehci-mx6: Split ehci_mx6_common_init()
In order to pass component addresses around easily instead of passing
ad-hoc sequence numbers, it is necessary to split ehci_mx6_common_init().
Make it so and call the separate functions instead.
Since board_ehci_hcd_init() makes no sense in DM case, do not call it
in DM case.
Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
drivers/usb/host/ehci-mx6.c | 58 ++---
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 008dca9bae7..b195ba4c89b 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -283,6 +283,7 @@ static void usb_oc_config(int index)
#endif
}
+#if !CONFIG_IS_ENABLED(DM_USB)
/**
* board_usb_phy_mode - override usb phy mode
* @port: usb host/otg port
@@ -329,27 +330,6 @@ int __weak board_ehci_power(int port, int on)
return 0;
}
-int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
-{
- int ret;
-
- /* Do board specific initialization */
- ret = board_ehci_hcd_init(index);
- if (ret)
- return ret;
-
- usb_power_config(index);
- usb_oc_config(index);
-
-#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
- usb_internal_phy_clock_gate(index, 1);
- usb_phy_enable(index, ehci);
-#endif
-
- return 0;
-}
-
-#if !CONFIG_IS_ENABLED(DM_USB)
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
@@ -377,9 +357,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
enable_usboh3_clk(1);
mdelay(1);
- ret = ehci_mx6_common_init(ehci, index);
- if (ret)
+ /* Do board specific initialization */
+ ret = board_ehci_hcd_init(index);
+ if (ret) {
+ enable_usboh3_clk(0);
return ret;
+ }
+
+ usb_power_config(index);
+ usb_oc_config(index);
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
+ usb_internal_phy_clock_gate(index, 1);
+ usb_phy_enable(index, ehci);
+#endif
type = board_usb_phy_mode(index);
@@ -432,9 +423,13 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
struct usb_ehci *ehci = priv->ehci;
int ret;
- ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
- if (ret)
- return ret;
+ usb_power_config(priv->portnr);
+ usb_oc_config(priv->portnr);
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
+ usb_internal_phy_clock_gate(priv->portnr, 1);
+ usb_phy_enable(priv->portnr, ehci);
+#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
@@ -672,9 +667,14 @@ static int ehci_usb_probe(struct udevice *dev)
if (ret)
debug("%s: No vbus supply\n", dev->name);
#endif
- ret = ehci_mx6_common_init(ehci, priv->portnr);
- if (ret)
- goto err_clk;
+
+ usb_power_config(priv->portnr);
+ usb_oc_config(priv->portnr);
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
+ usb_internal_phy_clock_gate(priv->portnr, 1);
+ usb_phy_enable(priv->portnr, ehci);
+#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
--
2.30.2
[PATCH 10/19] usb: ehci-mx6: Parse USB PHY and MISC offsets from DT
In case DM and OF controler is enabled, but PHY support is disabled,
parse USB PHY and MISC component addresses from DT manually. Those
component addresses will be used in subsequent patches to access the
ANATOP, PHY and MISC registers matching the controller and thus get
rid of the ad-hoc controller sequence number mapping.
Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
drivers/usb/host/ehci-mx6.c | 59 +
1 file changed, 59 insertions(+)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index b0703502db0..008dca9bae7 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -417,6 +417,12 @@ struct ehci_mx6_priv_data {
struct clk clk;
enum usb_init_type init_type;
int portnr;
+#if !defined(CONFIG_PHY)
+ /* Legacy iMX6/iMX7/iMX7ULP compat, they do not use PHY framework yet */
+ void __iomem *phy_addr;
+ void __iomem *misc_addr;
+ void __iomem *anatop_addr;
+#endif
};
static int mx6_init_after_reset(struct ehci_ctrl *dev)
@@ -571,6 +577,55 @@ static int ehci_usb_bind(struct udevice *dev)
return 0;
}
+static int mx6_parse_dt_addrs(struct udevice *dev)
+{
+#if !defined(CONFIG_PHY)
+ /*
+* Parse USB PHY/MISC/ANATOP addresses out of DT on platforms
+* which do not use PHY framework yet, that is MX6/MX7/MX7ULP.
+*/
+ struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
+ int phy_off, misc_off, anatop_off;
+ const void *blob = gd->fdt_blob;
+ int offset = dev_of_offset(dev);
+ void *__iomem addr;
+
+ phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy");
+ if (phy_off < 0)
+ return -EINVAL;
+
+ misc_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbmisc");
+ if (misc_off < 0)
+ return -EINVAL;
+
+ addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, "reg");
+ if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->phy_addr = addr;
+
+ addr = (void __iomem *)fdtdec_get_addr(blob, misc_off, "reg");
+ if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->misc_addr = addr;
+
+#if defined(CONFIG_MX6)
+ /* Resolve ANATOP offset through USB PHY node */
+ anatop_off = fdtdec_lookup_phandle(blob, phy_off, "fsl,anatop");
+ if (anatop_off < 0)
+ return -EINVAL;
+
+ addr = (void __iomem *)fdtdec_get_addr(blob, anatop_off, "reg");
+ if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->anatop_addr = addr;
+#endif
+#endif
+ return 0;
+}
+
static int ehci_usb_probe(struct udevice *dev)
{
struct usb_plat *plat = dev_get_plat(dev);
@@ -589,6 +644,10 @@ static int ehci_usb_probe(struct udevice *dev)
}
}
+ ret = mx6_parse_dt_addrs(dev);
+ if (ret)
+ return ret;
+
priv->ehci = ehci;
priv->portnr = dev_seq(dev);
priv->init_type = type;
--
2.30.2
[PATCH 06/19] imx: power-domain: Add fsl, imx8mm-gpc compatible string
The driver is compatible with iMX8MM, add missing compatible string.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
drivers/power/domain/imx8m-power-domain.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/power/domain/imx8m-power-domain.c
b/drivers/power/domain/imx8m-power-domain.c
index c4cd07ffaf4..ebac90d81c1 100644
--- a/drivers/power/domain/imx8m-power-domain.c
+++ b/drivers/power/domain/imx8m-power-domain.c
@@ -120,6 +120,7 @@ static int imx8m_power_domain_of_to_plat(struct udevice
*dev)
static const struct udevice_id imx8m_power_domain_ids[] = {
{ .compatible = "fsl,imx8mq-gpc" },
+ { .compatible = "fsl,imx8mm-gpc" },
{ }
};
--
2.30.2
[PATCH 09/19] usb: ehci-mx6: Unify USBNC registers
Merge USBNC register layout structure into a single one, instead of
having three separate structures and a lot of ifdeffery. No functional
change.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
drivers/usb/host/ehci-mx6.c | 53 +
1 file changed, 19 insertions(+), 34 deletions(-)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index ecc79cb54b6..b0703502db0 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -68,6 +68,24 @@ DECLARE_GLOBAL_DATA_PTR;
#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
#define UCMD_RESET (1 << 1) /* controller reset */
+/* Base address for this IP block is 0x02184800 */
+struct usbnc_regs {
+ u32 ctrl[4]; /* otg/host1-3 */
+ u32 uh2_hsic_ctrl;
+ u32 uh3_hsic_ctrl;
+ u32 otg_phy_ctrl_0;
+ u32 uh1_phy_ctrl_0;
+ u32 reserve1[4];
+ u32 phy_cfg1;
+ u32 phy_cfg2;
+ u32 reserve2;
+ u32 phy_status;
+ u32 reserve3[4];
+ u32 adp_cfg1;
+ u32 adp_cfg2;
+ u32 adp_status;
+};
+
#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
static const unsigned phy_bases[] = {
USB_PHY0_BASE_ADDR,
@@ -207,39 +225,7 @@ int usb_phy_mode(int port)
return USB_INIT_HOST;
}
-#if defined(CONFIG_MX7ULP)
-struct usbnc_regs {
- u32 ctrl1;
- u32 ctrl2;
- u32 reserve0[2];
- u32 hsic_ctrl;
-};
-#else
-/* Base address for this IP block is 0x02184800 */
-struct usbnc_regs {
- u32 ctrl[4];/* otg/host1-3 */
- u32 uh2_hsic_ctrl;
- u32 uh3_hsic_ctrl;
- u32 otg_phy_ctrl_0;
- u32 uh1_phy_ctrl_0;
-};
-#endif
-
#elif defined(CONFIG_MX7)
-struct usbnc_regs {
- u32 ctrl1;
- u32 ctrl2;
- u32 reserve1[10];
- u32 phy_cfg1;
- u32 phy_cfg2;
- u32 reserve2;
- u32 phy_status;
- u32 reserve3[4];
- u32 adp_cfg1;
- u32 adp_cfg2;
- u32 adp_status;
-};
-
static void usb_power_config(int index)
{
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
@@ -274,12 +260,11 @@ static void usb_oc_config(int index)
#if defined(CONFIG_MX6)
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
USB_OTHERREGS_OFFSET);
- void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
(0x1 * index) + USBNC_OFFSET);
- void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
#endif
+ void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
/* mx6qarm2 seems to required a different setting*/
--
2.30.2
[PATCH 08/19] usb: ehci-mx6: Add DM clock support
Add support for using DM clock framework to enable and disable all the
necessary clock for the USB controller.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
drivers/usb/host/ehci-mx6.c | 37 -
1 file changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 6fb596633a3..ecc79cb54b6 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -347,9 +348,6 @@ int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
{
int ret;
- enable_usboh3_clk(1);
- mdelay(1);
-
/* Do board specific initialization */
ret = board_ehci_hcd_init(index);
if (ret)
@@ -391,6 +389,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
}
}
+ enable_usboh3_clk(1);
+ mdelay(1);
+
ret = ehci_mx6_common_init(ehci, index);
if (ret)
return ret;
@@ -428,6 +429,7 @@ struct ehci_mx6_priv_data {
struct ehci_ctrl ctrl;
struct usb_ehci *ehci;
struct udevice *vbus_supply;
+ struct clk clk;
enum usb_init_type init_type;
int portnr;
};
@@ -606,6 +608,20 @@ static int ehci_usb_probe(struct udevice *dev)
priv->portnr = dev_seq(dev);
priv->init_type = type;
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret)
+ return ret;
+#else
+ /* Compatibility with DM_USB and !CLK */
+ enable_usboh3_clk(1);
+ mdelay(1);
+#endif
+
#if CONFIG_IS_ENABLED(DM_REGULATOR)
ret = device_get_supply_regulator(dev, "vbus-supply",
&priv->vbus_supply);
@@ -614,7 +630,7 @@ static int ehci_usb_probe(struct udevice *dev)
#endif
ret = ehci_mx6_common_init(ehci, priv->portnr);
if (ret)
- return ret;
+ goto err_clk;
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
@@ -623,7 +639,7 @@ static int ehci_usb_probe(struct udevice *dev)
false : true);
if (ret && ret != -ENOSYS) {
printf("Error enabling VBUS supply (ret=%i)\n", ret);
- return ret;
+ goto err_clk;
}
}
#endif
@@ -650,6 +666,13 @@ err_regulator:
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply)
regulator_set_enable(priv->vbus_supply, false);
+#endif
+err_clk:
+#if CONFIG_IS_ENABLED(CLK)
+ clk_disable(&priv->clk);
+#else
+ /* Compatibility with DM_USB and !CLK */
+ enable_usboh3_clk(0);
#endif
return ret;
}
@@ -665,6 +688,10 @@ int ehci_usb_remove(struct udevice *dev)
regulator_set_enable(priv->vbus_supply, false);
#endif
+#if CONFIG_IS_ENABLED(CLK)
+ clk_disable(&priv->clk);
+#endif
+
return 0;
}
--
2.30.2
[PATCH 07/19] usb: ehci-mx6: Turn off Vbus on probe failure
The driver turns on Vbus regulator in probe, but fails to turn it back
off in case of probe failure. Add the missing code.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
drivers/usb/host/ehci-mx6.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index aeea535..6fb596633a3 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -640,7 +640,32 @@ static int ehci_usb_probe(struct udevice *dev)
hcor = (struct ehci_hcor *)((uint32_t)hccr +
HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
- return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0,
priv->init_type);
+ ret = ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
+ if (ret)
+ goto err_regulator;
+
+ return ret;
+
+err_regulator:
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (priv->vbus_supply)
+ regulator_set_enable(priv->vbus_supply, false);
+#endif
+ return ret;
+}
+
+int ehci_usb_remove(struct udevice *dev)
+{
+ struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
+
+ ehci_deregister(dev);
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (priv->vbus_supply)
+ regulator_set_enable(priv->vbus_supply, false);
+#endif
+
+ return 0;
}
static const struct udevice_id mx6_usb_ids[] = {
@@ -655,7 +680,7 @@ U_BOOT_DRIVER(usb_mx6) = {
.of_to_plat = ehci_usb_of_to_plat,
.bind = ehci_usb_bind,
.probe = ehci_usb_probe,
- .remove = ehci_deregister,
+ .remove = ehci_usb_remove,
.ops= &ehci_usb_ops,
.plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct ehci_mx6_priv_data),
--
2.30.2
[PATCH 05/19] ARM: dts: imx8mm: Add power domain nodes
Add power domain nodes to DT.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
arch/arm/dts/imx8mm.dtsi | 73
include/dt-bindings/power/imx8mm-power.h | 22 +++
2 files changed, 95 insertions(+)
create mode 100644 include/dt-bindings/power/imx8mm-power.h
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
index fa2d73f1803..b142b80734d 100644
--- a/arch/arm/dts/imx8mm.dtsi
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -4,6 +4,8 @@
*/
#include
+#include
+#include
#include
#include
#include
@@ -592,6 +594,75 @@
interrupts = ;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a {
+ compatible = "fsl,imx8mm-gpc";
+ reg = <0x303a 0x1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_hsiomix: power-domain@0 {
+ #power-domain-cells = <0>;
+ reg =
;
+ clocks = <&clk
IMX8MM_CLK_USB_BUS>;
+ };
+
+ pgc_pcie: power-domain@1 {
+ #power-domain-cells = <0>;
+ reg =
;
+ power-domains = <&pgc_hsiomix>;
+ };
+
+ pgc_otg1: power-domain@2 {
+ #power-domain-cells = <0>;
+ reg =
;
+ power-domains = <&pgc_hsiomix>;
+ };
+
+ pgc_otg2: power-domain@3 {
+ #power-domain-cells = <0>;
+ reg =
;
+ power-domains = <&pgc_hsiomix>;
+ };
+
+ pgc_gpumix: power-domain@4 {
+ #power-domain-cells = <0>;
+ reg =
;
+ clocks = <&clk
IMX8MM_CLK_GPU_BUS_ROOT>,
+<&clk
IMX8MM_CLK_GPU_AHB>;
+ };
+
+ pgc_gpu: power-domain@5 {
+ #power-domain-cells = <0>;
+ reg = ;
+ clocks = <&clk
IMX8MM_CLK_GPU_AHB>,
+<&clk
IMX8MM_CLK_GPU_BUS_ROOT>,
+<&clk
IMX8MM_CLK_GPU2D_ROOT>,
+<&clk
IMX8MM_CLK_GPU3D_ROOT>;
+ resets = <&src
IMX8MQ_RESET_GPU_RESET>;
+ power-domains = <&pgc_gpumix>;
+ };
+
+ dispmix_pd: power-domain@10 {
+ #power-domain-cells = <0>;
+ reg =
;
+ clocks = <&clk
IMX8MM_CLK_DISP_ROOT>,
+<&clk
IMX8MM_CLK_DISP_AXI_ROOT>,
+<&clk
IMX8MM_CLK_DISP_APB_ROOT>;
+ };
+
+ mipi_pd: power-domain@11 {
+ #power-domain-cells = <0>;
+ reg =
;
+ power-domains = <&dispmix_pd>;
+ };
+ };
+ };
};
aips2: bus@3040 {
@@ -940,6 +1011,7 @@
assigned-clock-parents = <&clk
IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
+ power-domains = <&pgc_otg1>;
[PATCH 04/19] ARM: dts: imx8mm: Replace deprecated fsl, usbphy DT props with phys
The fsl,usbphy DT property is deprecated, replace it with phys DT
property and specify #phy-cells, so that the generic PHY framework
can parse the PHY bindings without any extra hacking.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
arch/arm/dts/imx8mm.dtsi | 6 --
arch/arm/dts/imx8mn.dtsi | 3 ++-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
index c824f2615fe..fa2d73f1803 100644
--- a/arch/arm/dts/imx8mm.dtsi
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -241,6 +241,7 @@
};
usbphynop1: usbphynop1 {
+ #phy-cells = <0>;
compatible = "usb-nop-xceiv";
clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
@@ -249,6 +250,7 @@
};
usbphynop2: usbphynop2 {
+ #phy-cells = <0>;
compatible = "usb-nop-xceiv";
clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
@@ -936,7 +938,7 @@
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
assigned-clock-parents = <&clk
IMX8MM_SYS_PLL2_500M>;
- fsl,usbphy = <&usbphynop1>;
+ phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
status = "disabled";
};
@@ -955,7 +957,7 @@
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
assigned-clock-parents = <&clk
IMX8MM_SYS_PLL2_500M>;
- fsl,usbphy = <&usbphynop2>;
+ phys = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
status = "disabled";
};
diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi
index ee179023049..f77b223682c 100644
--- a/arch/arm/dts/imx8mn.dtsi
+++ b/arch/arm/dts/imx8mn.dtsi
@@ -930,7 +930,7 @@
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
assigned-clock-parents = <&clk
IMX8MN_SYS_PLL2_500M>;
- fsl,usbphy = <&usbphynop1>;
+ phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
status = "disabled";
};
@@ -998,6 +998,7 @@
};
usbphynop1: usbphynop1 {
+ #phy-cells = <0>;
compatible = "usb-nop-xceiv";
clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
--
2.30.2
[PATCH 03/19] ARM: dts: k2g-evm: Use standard compatible string for USB no-op PHY
The standard compatible string is "usb-nop-xceiv", use it.
Note that keystone-k2g.dtsi already uses the aforementioned
compat string, so this patch can only remove the override.
Signed-off-by: Marek Vasut
Cc: Alexey Brodkin
Cc: Eugeniy Paltsev
Cc: Fabio Estevam
Cc: Jean-Jacques Hiblot
Cc: Murali Karicheri
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
arch/arm/dts/keystone-k2g-evm.dts | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/dts/keystone-k2g-evm.dts
b/arch/arm/dts/keystone-k2g-evm.dts
index 7c5deef8083..b5b511cbd61 100644
--- a/arch/arm/dts/keystone-k2g-evm.dts
+++ b/arch/arm/dts/keystone-k2g-evm.dts
@@ -38,7 +38,6 @@
&usb0_phy {
status = "okay";
- compatible = "nop-phy";
};
&usb0 {
@@ -51,7 +50,6 @@
};
&usb1_phy {
- compatible = "nop-phy";
status = "okay";
};
--
2.30.2
[PATCH 02/19] arc: emsdp/iotdk: Use standard compatible string for USB no-op PHY
The standard compatible string is "usb-nop-xceiv", use it.
Signed-off-by: Marek Vasut
Cc: Alexey Brodkin
Cc: Eugeniy Paltsev
Cc: Fabio Estevam
Cc: Jean-Jacques Hiblot
Cc: Murali Karicheri
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
arch/arc/dts/iot_devkit.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arc/dts/iot_devkit.dts b/arch/arc/dts/iot_devkit.dts
index c0173fa5ab4..2122827527e 100644
--- a/arch/arc/dts/iot_devkit.dts
+++ b/arch/arc/dts/iot_devkit.dts
@@ -39,7 +39,7 @@
};
usbphy: phy {
- compatible = "nop-phy";
+ compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
--
2.30.2
[PATCH 01/19] phy: nop-phy: Add standard usb-nop-xceiv compat string
The USB no-op PHY uses "usb-nop-xceiv" compatible string. This driver is
compatible with USB no-op PHY, so add the compatible string.
Signed-off-by: Marek Vasut
Cc: Alexey Brodkin
Cc: Eugeniy Paltsev
Cc: Fabio Estevam
Cc: Jean-Jacques Hiblot
Cc: Murali Karicheri
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
drivers/phy/nop-phy.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/nop-phy.c b/drivers/phy/nop-phy.c
index 84aac806230..9f12ebc0624 100644
--- a/drivers/phy/nop-phy.c
+++ b/drivers/phy/nop-phy.c
@@ -43,6 +43,7 @@ static int nop_phy_probe(struct udevice *dev)
static const struct udevice_id nop_phy_ids[] = {
{ .compatible = "nop-phy" },
+ { .compatible = "usb-nop-xceiv" },
{ }
};
--
2.30.2
Re: [PATCH 1/1] Azure/GitLab: bump OpenSBI version to 0.9
On Fri, Apr 2, 2021 at 5:42 PM Heinrich Schuchardt wrote: > > Version 0.9 of OpenSBI provides the system reset extension which allows us > to reset and power off boards without board specific code. > > Signed-off-by: Heinrich Schuchardt > --- > .azure-pipelines.yml | 8 > .gitlab-ci.yml | 8 > 2 files changed, 8 insertions(+), 8 deletions(-) > Reviewed-by: Bin Meng
[PATCH] stm32mp: stm32prog: add FIP header support
Add support of TF-A FIP header in command stm32prog for all the boot
partition and not only the STM32IMAGE.
This patch is a preliminary patch to support FIP as second boot stage
after TF-A BL2 when CONFIG_TFABOOT is activated for trusted boot chain.
The FIP is archive binary loaded by TF-A BL2, which contains the secure OS
= OP-TEE and the non secure firmware and device tree = U-Boot.
Signed-off-by: Patrick Delaunay
---
.../cmd_stm32prog/cmd_stm32prog.c | 19 +++---
.../mach-stm32mp/cmd_stm32prog/stm32prog.c| 59 +--
.../mach-stm32mp/cmd_stm32prog/stm32prog.h| 12 +++-
.../cmd_stm32prog/stm32prog_serial.c | 11 ++--
4 files changed, 64 insertions(+), 37 deletions(-)
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
index a7e2861764..e36501a86b 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
@@ -73,15 +73,16 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag,
int argc,
size = simple_strtoul(argv[4], NULL, 16);
/* check STM32IMAGE presence */
- if (size == 0 &&
- !stm32prog_header_check((struct raw_header_s *)addr, &header)) {
- size = header.image_length + BL_HEADER_SIZE;
-
- /* uImage detected in STM32IMAGE, execute the script */
- if (IMAGE_FORMAT_LEGACY ==
- genimg_get_format((void *)(addr + BL_HEADER_SIZE)))
- return image_source_script(addr + BL_HEADER_SIZE,
- "script@1");
+ if (size == 0) {
+ stm32prog_header_check((struct raw_header_s *)addr, &header);
+ if (header.type == HEADER_STM32IMAGE) {
+ size = header.image_length + BL_HEADER_SIZE;
+
+ /* uImage detected in STM32IMAGE, execute the script */
+ if (IMAGE_FORMAT_LEGACY ==
+ genimg_get_format((void *)(addr + BL_HEADER_SIZE)))
+ return image_source_script(addr +
BL_HEADER_SIZE, "script@1");
+ }
}
if (IS_ENABLED(CONFIG_DM_VIDEO))
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
index d0518d1223..4c4d8a7a69 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
@@ -60,8 +60,6 @@ static const efi_guid_t uuid_mmc[3] = {
ROOTFS_MMC2_UUID
};
-DECLARE_GLOBAL_DATA_PTR;
-
/* order of column in flash layout file */
enum stm32prog_col_t {
COL_OPTION,
@@ -73,6 +71,16 @@ enum stm32prog_col_t {
COL_NB_STM32
};
+#define FIP_TOC_HEADER_NAME0xAA640001
+
+struct fip_toc_header {
+ u32 name;
+ u32 serial_number;
+ u64 flags;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
/* partition handling routines : CONFIG_CMD_MTDPARTS */
int mtdparts_init(void);
int find_dev_and_part(const char *id, struct mtd_device **dev,
@@ -88,46 +96,57 @@ char *stm32prog_get_error(struct stm32prog_data *data)
return data->error;
}
-u8 stm32prog_header_check(struct raw_header_s *raw_header,
- struct image_header_s *header)
+static bool stm32prog_is_fip_header(struct fip_toc_header *header)
+{
+ return (header->name == FIP_TOC_HEADER_NAME) && header->serial_number;
+}
+
+void stm32prog_header_check(struct raw_header_s *raw_header,
+ struct image_header_s *header)
{
unsigned int i;
- header->present = 0;
+ if (!raw_header || !header) {
+ log_debug("%s:no header data\n", __func__);
+ return;
+ }
+
+ header->type = HEADER_NONE;
header->image_checksum = 0x0;
header->image_length = 0x0;
- if (!raw_header || !header) {
- log_debug("%s:no header data\n", __func__);
- return -1;
+ if (stm32prog_is_fip_header((struct fip_toc_header *)raw_header)) {
+ header->type = HEADER_FIP;
+ return;
}
+
if (raw_header->magic_number !=
(('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) {
log_debug("%s:invalid magic number : 0x%x\n",
__func__, raw_header->magic_number);
- return -2;
+ return;
}
/* only header v1.0 supported */
if (raw_header->header_version != 0x0001) {
log_debug("%s:invalid header version : 0x%x\n",
__func__, raw_header->header_version);
- return -3;
+ return;
}
if (raw_header->reserved1 != 0x0 || raw_header->reserved2) {
log_debug("%s:invalid reserved field\n", __func__);
- return -4;
+ retur
[PATCH 1/1] efi_loader: simplify efi_get_device_path_text()
Replace static function efi_get_device_handle_info() by a simplified
function efi_get_device_path_text() avoiding EFI_CALL().
Signed-off-by: Heinrich Schuchardt
---
cmd/efidebug.c | 31 ---
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 6e36575a94..0bf7b8856c 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -341,27 +341,27 @@ static int do_efi_capsule(struct cmd_tbl *cmdtp, int flag,
#endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT */
/**
- * efi_get_device_handle_info() - get information of UEFI device
+ * efi_get_device_path_text() - get device path text
*
- * @handle:Handle of UEFI device
- * @dev_path_text: Pointer to text of device path
- * Return: 0 on success, -1 on failure
+ * Return the text representation of the device path of a handle.
*
- * Currently return a formatted text of device path.
+ * @handle:handle of UEFI device
+ * Return:
+ * Pointer to the device path text or NULL.
+ * The caller is responsible for calling FreePool().
*/
-static int efi_get_device_handle_info(efi_handle_t handle, u16 **dev_path_text)
+static u16 *efi_get_device_path_text(efi_handle_t handle)
{
- struct efi_device_path *dp;
+ struct efi_handler *handler;
efi_status_t ret;
- ret = EFI_CALL(BS->open_protocol(handle, &efi_guid_device_path,
-(void **)&dp, NULL /* FIXME */, NULL,
-EFI_OPEN_PROTOCOL_GET_PROTOCOL));
- if (ret == EFI_SUCCESS) {
- *dev_path_text = efi_dp_str(dp);
- return 0;
+ ret = efi_search_protocol(handle, &efi_guid_device_path, &handler);
+ if (ret == EFI_SUCCESS && handler->protocol_interface) {
+ struct efi_device_path *dp = handler->protocol_interface;
+
+ return efi_dp_str(dp);
} else {
- return -1;
+ return NULL;
}
}
@@ -401,7 +401,8 @@ static int do_efi_show_devices(struct cmd_tbl *cmdtp, int
flag,
printf("Device%.*s Device Path\n", EFI_HANDLE_WIDTH - 6, spc);
printf("%.*s \n", EFI_HANDLE_WIDTH, sep);
for (i = 0; i < num; i++) {
- if (!efi_get_device_handle_info(handles[i], &dev_path_text)) {
+ dev_path_text = efi_get_device_path_text(handles[i]);
+ if (dev_path_text) {
printf("%p %ls\n", handles[i], dev_path_text);
efi_free_pool(dev_path_text);
}
--
2.30.2
[PATCH 1/1] Azure/GitLab: bump OpenSBI version to 0.9
Version 0.9 of OpenSBI provides the system reset extension which allows us
to reset and power off boards without board specific code.
Signed-off-by: Heinrich Schuchardt
---
.azure-pipelines.yml | 8
.gitlab-ci.yml | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index f358e468de..6254a458ed 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -304,12 +304,12 @@ jobs:
grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal
echo lsefimmap lsefi lsefisystab efinet tftp minicmd
grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal
echo lsefimmap lsefi lsefisystab efinet tftp minicmd
if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
- wget -O -
https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz
| tar -C /tmp -xJ;
- export
OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
+ wget -O -
https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz
| tar -C /tmp -xJ;
+ export
OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
- wget -O -
https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz
| tar -C /tmp -xJ;
- export
OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
+ wget -O -
https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz
| tar -C /tmp -xJ;
+ export
OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
# the below corresponds to .gitlab-ci.yml "script"
cd ${WORK_DIR}
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 64e341c262..22ec4929a0 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -21,12 +21,12 @@ stages:
- grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo
lsefimmap lsefi lsefisystab efinet tftp minicmd
- grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo
lsefimmap lsefi lsefisystab efinet tftp minicmd
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
-wget -O -
https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz
| tar -C /tmp -xJ;
-export
OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
+wget -O -
https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz
| tar -C /tmp -xJ;
+export
OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
-wget -O -
https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz
| tar -C /tmp -xJ;
-export
OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
+wget -O -
https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz
| tar -C /tmp -xJ;
+export
OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
after_script:
--
2.30.2
Re: [PATCH] configs: qemu-riscv64_spl_defconfig enable CMD_SBI
On Fri, Apr 2, 2021 at 4:35 PM Heinrich Schuchardt wrote: > > At least on one board we should compile the sbi command. > Enabling it on QEMU will allow to write a test for it. > > Signed-off-by: Heinrich Schuchardt > --- > configs/qemu-riscv64_spl_defconfig | 1 + > 1 file changed, 1 insertion(+) > Please enable 32-bit as well. Regards, Bin
[PATCH] configs: qemu-riscv64_spl_defconfig enable CMD_SBI
At least on one board we should compile the sbi command. Enabling it on QEMU will allow to write a test for it. Signed-off-by: Heinrich Schuchardt --- configs/qemu-riscv64_spl_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 897adf6a29..dc7046b2a3 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -10,6 +10,7 @@ CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x8020 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +CONFIG_CMD_SBI=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -- 2.30.2
Re: [PATCH V2] doc: mmc man-page
On 4/2/21 1:15 PM, Heinrich Schuchardt wrote: > On 4/2/21 2:15 AM, Jaehoon Chung wrote: >> Provide a man-pages for the mmc command. >> >> Signed-off-by: Jaehoon Chung >> --- >> Changelog on V2 >> - Add missing empty line >> - Add bootbus's arguments descriptions >> --- >> doc/usage/index.rst | 1 + >> doc/usage/mmc.rst | 212 >> 2 files changed, 213 insertions(+) >> create mode 100644 doc/usage/mmc.rst >> >> diff --git a/doc/usage/index.rst b/doc/usage/index.rst >> index 6c59bbadab45..15c682ceface 100644 >> --- a/doc/usage/index.rst >> +++ b/doc/usage/index.rst >> @@ -30,6 +30,7 @@ Shell commands >> load >> loady >> mbr >> + mmc >> pstore >> qfw >> sbi >> diff --git a/doc/usage/mmc.rst b/doc/usage/mmc.rst >> new file mode 100644 >> index ..57284ed6741e >> --- /dev/null >> +++ b/doc/usage/mmc.rst >> @@ -0,0 +1,212 @@ >> +.. SPDX-License-Identifier: GPL-2.0+: >> + >> +mmc command >> + >> + >> +Synopsis >> + >> + >> +:: >> + >> + mmc info >> + mmc read addr blk# cnt >> + mmc write addr blk# cnt >> + mmc erase blk# cnt >> + mmc rescan >> + mmc part >> + mmc dev [dev] [part] >> + mmc list >> + mmc wp >> + mmc bootbus >> + mmc bootpart-resize >> + mmc partconf [boot_ack boot_partition partition_access] >> + mmc rst-function > > Dear Jaehoon, > > thanks for updating the patch. > > I am missing the configurable sub-commands: > > mmc swrite addr blk# > mmc hwpartition > mmc rpmb read addr blk# cnt [address of auth-key] > mmc rpmb write addr blk# cnt > mmc rpmb key > mmc rpmb counter > mmc setdsr > mmc bkops-enable > > Will they go into a follow up patch? Right, i didn't add some commands. I will update them with another patch. I had been sent a patch about hwpartition command https://patchwork.ozlabs.org/project/uboot/patch/20210226070718.10720-1-jh80.ch...@samsung.com/ If you're ok, I want to update doc file based on its patch after applied it. And I want to send patch after checking exact behavior about other command. Best Regards, Jaehoon Chung > > Best regards > > Heinrich > >> + >> +Description >> +--- >> + >> +The mmc command is used to control MMC(eMMC/SD) device. >> + >> +The 'mmc info' command displays information (Manufacturer ID, OEM, Name, >> Bus Speed, Mode, ...) of MMC device. >> + >> +The 'mmc read' command reads raw data to memory address from MMC device >> with block offset and count. >> + >> +The 'mmc write' command writes raw data to MMC device from memory address >> with block offset and count. >> + >> + addr >> + memory address >> + blk# >> + start block offset >> + cnt >> + block count >> + >> +The 'mmc erase' command erases MMC device from block offset until count. >> + >> + blk# >> + start block offset >> + cnt >> + block count >> + >> +The 'mmc rescan' command scans the available MMC device. >> + >> +The 'mmc part' command displays the list available partition on current mmc >> device. >> + >> +The 'mmc dev' command shows or set current mmc device. >> + >> + dev >> + device number to change >> + part >> + partition number to change >> + >> +The 'mmc list' command displays the list available devices. >> + >> +The 'mmc wp' command enables "power on write protect" function for boot >> partitions. >> + >> +The 'mmc bootbus' command sets the BOOT_BUS_WIDTH field. (*Refer to eMMC >> specification*) >> + >> + boot_bus_width >> + 0x0 >> + x1 (sdr) or x4(ddr) buswidth in boot operation mode (default) >> + 0x1 >> + x4 (sdr/ddr) buswidth in boot operation mode >> + 0x2 >> + x8 (sdr/ddr) buswidth in boot operation mode >> + 0x3 >> + Reserved >> + >> + reset_boot_bus_width >> + 0x0 >> + Reset buswidth to x1, Single data reate and backward compatible >> timing after boot operation (default) >> + 0x1 >> + Retain BOOT_BUS_WIDTH and BOOT_MODE value after boot operation. >> This is relevant to Push-pull mode operation only >> + >> + boot_mode >> + 0x0 >> + Use single data rate + backward compatible timing in boot >> operation (default) >> + 0x1 >> + Use single data rate + High Speed timing in boot operation mode >> + 0x2 >> + Use dual data rate in boot operation >> + 0x3 >> + Reserved >> + >> +The 'mmc partconf' command shows or changes PARTITION_CONFIG field. >> + >> + boot_ack >> + boot acknowledge value >> + boot_partition >> + boot partition to enable for boot >> + 0x0 >> + Device not boot enabled(default) >> + 0x1 >> + Boot partition1 enabled for boot >> + 0x2 >> + Boot partition2 enabled for boot >> + 0x7 >> + User area ena
