[PATCH v2] power: regulator: Add support for regulator-force-boot-off

2021-04-09 Thread Stefan Roese
From: Konstantin Porotchkin 

Add support for regulator-force-boot-off DT property.
This property can be used by the board/device drivers for
turning off regulators on early init stages as pre-requisite
for the other components initialization.

Signed-off-by: Konstantin Porotchkin 
Signed-off-by: Stefan Roese 
Cc: Jaehoon Chung 
Cc: Simon Glass 
---
v2:
- Add check for uc_pdata in regulator_unset()

 drivers/power/regulator/regulator-uclass.c | 38 ++
 include/power/regulator.h  | 23 +
 2 files changed, 61 insertions(+)

diff --git a/drivers/power/regulator/regulator-uclass.c 
b/drivers/power/regulator/regulator-uclass.c
index 4d2e730271f9..fac960682331 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -311,6 +311,17 @@ int regulator_autoset(struct udevice *dev)
return ret;
 }
 
+int regulator_unset(struct udevice *dev)
+{
+   struct dm_regulator_uclass_plat *uc_pdata;
+
+   uc_pdata = dev_get_uclass_plat(dev);
+   if (uc_pdata && uc_pdata->force_off)
+   return regulator_set_enable(dev, false);
+
+   return -EMEDIUMTYPE;
+}
+
 static void regulator_show(struct udevice *dev, int ret)
 {
struct dm_regulator_uclass_plat *uc_pdata;
@@ -443,6 +454,7 @@ static int regulator_pre_probe(struct udevice *dev)
uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on");
uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay",
0);
+   uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off");
 
node = dev_read_subnode(dev, "regulator-state-mem");
if (ofnode_valid(node)) {
@@ -495,6 +507,32 @@ int regulators_enable_boot_on(bool verbose)
return ret;
 }
 
+int regulators_enable_boot_off(bool verbose)
+{
+   struct udevice *dev;
+   struct uclass *uc;
+   int ret;
+
+   ret = uclass_get(UCLASS_REGULATOR, &uc);
+   if (ret)
+   return ret;
+   for (uclass_first_device(UCLASS_REGULATOR, &dev);
+dev;
+uclass_next_device(&dev)) {
+   ret = regulator_unset(dev);
+   if (ret == -EMEDIUMTYPE) {
+   ret = 0;
+   continue;
+   }
+   if (verbose)
+   regulator_show(dev, ret);
+   if (ret == -ENOSYS)
+   ret = 0;
+   }
+
+   return ret;
+}
+
 UCLASS_DRIVER(regulator) = {
.id = UCLASS_REGULATOR,
.name   = "regulator",
diff --git a/include/power/regulator.h b/include/power/regulator.h
index da9a065bdde0..fad87c99e5db 100644
--- a/include/power/regulator.h
+++ b/include/power/regulator.h
@@ -151,6 +151,7 @@ enum regulator_flag {
  * @max_uA*- maximum amperage (micro Amps)
  * @always_on* - bool type, true or false
  * @boot_on*   - bool type, true or false
+ * @force_off* - bool type, true or false
  * TODO(s...@chromium.org): Consider putting the above two into @flags
  * @ramp_delay - Time to settle down after voltage change (unit: uV/us)
  * @flags: - flags value (see REGULATOR_FLAG_...)
@@ -176,6 +177,7 @@ struct dm_regulator_uclass_plat {
unsigned int ramp_delay;
bool always_on;
bool boot_on;
+   bool force_off;
const char *name;
int flags;
u8 ctrl_reg;
@@ -420,6 +422,15 @@ int regulator_set_mode(struct udevice *dev, int mode_id);
  */
 int regulators_enable_boot_on(bool verbose);
 
+/**
+ * regulators_enable_boot_off() - disable regulators needed for boot
+ *
+ * This disables all regulators which are marked to be off at boot time.
+ *
+ * This effectively calls regulator_unset() for every regulator.
+ */
+int regulators_enable_boot_off(bool verbose);
+
 /**
  * regulator_autoset: setup the voltage/current on a regulator
  *
@@ -439,6 +450,18 @@ int regulators_enable_boot_on(bool verbose);
  */
 int regulator_autoset(struct udevice *dev);
 
+/**
+ * regulator_unset: turn off a regulator
+ *
+ * The setup depends on constraints found in device's uclass's platform data
+ * (struct dm_regulator_uclass_platdata):
+ *
+ * - Disable - will set - if  'force_off' is set to true,
+ *
+ * The function returns on the first-encountered error.
+ */
+int regulator_unset(struct udevice *dev);
+
 /**
  * regulator_autoset_by_name: setup the regulator given by its uclass's
  * platform data name field. The setup depends on constraints found in device's
-- 
2.31.1



Re: [PATCH] power: regulator: Add support for regulator-force-boot-off

2021-04-09 Thread Jaehoon Chung
Hi Stefan,

On 4/9/21 2:20 PM, Stefan Roese wrote:
> Hi Jaehoon,
> 
> On 09.04.21 02:37, Jaehoon Chung wrote:
>> On 4/9/21 7:52 AM, Jaehoon Chung wrote:
>>> Hi Stefan,
>>>
>>> On 4/8/21 6:20 PM, Stefan Roese wrote:
 From: Konstantin Porotchkin 

 Add support for regulator-force-boot-off DT property.
 This property can be used by the board/device drivers for
 turning off regulators on early init stages as pre-requisite
 for the other components initialization.

 Signed-off-by: Konstantin Porotchkin 
 Signed-off-by: Stefan Roese 
 Cc: Jaehoon Chung 
 Cc: Simon Glass 
 ---
   drivers/power/regulator/regulator-uclass.c | 38 ++
   include/power/regulator.h  | 23 +
   2 files changed, 61 insertions(+)

 diff --git a/drivers/power/regulator/regulator-uclass.c 
 b/drivers/power/regulator/regulator-uclass.c
 index 4d2e730271f9..423867edced8 100644
 --- a/drivers/power/regulator/regulator-uclass.c
 +++ b/drivers/power/regulator/regulator-uclass.c
 @@ -311,6 +311,17 @@ int regulator_autoset(struct udevice *dev)
   return ret;
   }
   +int regulator_unset(struct udevice *dev)
 +{
 +    struct dm_regulator_uclass_plat *uc_pdata;
 +
 +    uc_pdata = dev_get_uclass_plat(dev);
 +    if (uc_pdata->force_off)
>>>
>>> Could you check whether uc_pdata is NULL or not?
>>> It can be returned to NULL.
>>>
 +    return regulator_set_enable(dev, false);
 +
 +    return -EMEDIUMTYPE;
 +}
 +
   static void regulator_show(struct udevice *dev, int ret)
   {
   struct dm_regulator_uclass_plat *uc_pdata;
 @@ -443,6 +454,7 @@ static int regulator_pre_probe(struct udevice *dev)
   uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on");
   uc_pdata->ramp_delay = dev_read_u32_default(dev, 
 "regulator-ramp-delay",
   0);
 +    uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off");
     node = dev_read_subnode(dev, "regulator-state-mem");
   if (ofnode_valid(node)) {
 @@ -495,6 +507,32 @@ int regulators_enable_boot_on(bool verbose)
   return ret;
   }
   +int regulators_enable_boot_off(bool verbose)
 +{
 +    struct udevice *dev;
 +    struct uclass *uc;
 +    int ret;
 +
 +    ret = uclass_get(UCLASS_REGULATOR, &uc);
 +    if (ret)
 +    return ret;
 +    for (uclass_first_device(UCLASS_REGULATOR, &dev);
 + dev;
>>>
>>> typo?
>>
>> I have checked that it was not typo. :)
>> how about making one line?
> 
> I could do this. But this would lead to a quite long line:
> 
> for (uclass_first_device(UCLASS_REGULATOR, &dev); dev; 
> uclass_next_device(&dev)) {
> 
> Only putting "dev;" into the same line is not appealing, at least not
> to me. Please note that this style of uclass looping is pretty
> common. It's also used a few lines above in regulators_enable_boot_on():
> 
> int regulators_enable_boot_on(bool verbose)
> {
> struct udevice *dev;
> struct uclass *uc;
> int ret;
> 
> ret = uclass_get(UCLASS_REGULATOR, &uc);
> if (ret)
>     return ret;
> for (uclass_first_device(UCLASS_REGULATOR, &dev);
>  dev;
>  uclass_next_device(&dev)) {
>     ret = regulator_autoset(dev);
> ...
> 
> So I would like to keep it as in v1.

Yes, If you prefer to it, keep it as in v1. 
I think that can be changed to below.

for (uclass_first_device(UCLASS_REGULATOR, &dev);
dev; uclass_next_device(&dev)) {
ret = reuglator_autoset(dev);
...
}

But it's not critical thing. Thanks!

Best Regards,
Jaehoon Chung

> 
> Thanks,
> Stefan
> 
>>
>> Best Regards,
>> Jaehoo Chung
>>
>>>
>>> Best Regards,
>>> Jaehoon Chung
>>>
 + uclass_next_device(&dev)) {
 +    ret = regulator_unset(dev);
 +    if (ret == -EMEDIUMTYPE) {
 +    ret = 0;
 +    continue;
 +    }
 +    if (verbose)
 +    regulator_show(dev, ret);
 +    if (ret == -ENOSYS)
 +    ret = 0;
 +    }
 +
 +    return ret;
 +}
 +
   UCLASS_DRIVER(regulator) = {
   .id    = UCLASS_REGULATOR,
   .name    = "regulator",
 diff --git a/include/power/regulator.h b/include/power/regulator.h
 index da9a065bdde0..fad87c99e5db 100644
 --- a/include/power/regulator.h
 +++ b/include/power/regulator.h
 @@ -151,6 +151,7 @@ enum regulator_flag {
    * @max_uA*    - maximum amperage (micro Amps)
    * @always_on* - bool type, true or false
    * @boot_on*   - bool type, true or false
 + * @force_off* - bool type, true or false
    * TODO(s...@chromium.org): Consider putting the above two into @flags
    * @ramp_delay - Time to settle down after voltage change (unit: uV/us)
    * @flags: - flags v

Re: [PATCH v9] Add support for stack-protector

2021-04-09 Thread Joel Peshkin
Hi Heinrich,

Has there been any progress in getting the EFI erors fixed so that this can
be committed?  There seems to be little point in my refreshing this patch
until that is done.

Thanks,

-Joel


On Mon, Mar 22, 2021 at 10:37 AM Heinrich Schuchardt 
wrote:

> On 09.02.21 04:36, Joel Peshkin wrote:
> > Add support for stack protector for UBOOT, SPL, and TPL
> > as well as new pytest for stackprotector
> >
> > Signed-off-by: Joel Peshkin 
> > ---
> > Cc: Simon Glass 
> > Cc: Heinrich Schuchardt 
> >
> > Changes for v9:
> >- Fix pytest script post-test reboot
> > Changes for v8:
> >- Fix commit message
> >- Force canary to UL type
> > Changes for v7:
> >- Fix commit message
> >- add __builtin_extract_return_addr() calls
> > Changes for v6:
> >- Fix commit message
> > Changes for v5:
> >- Rebase
> > Changes for v4:
> >- Exclude EFI from stackprotector
> >- Cleanups of extra includes and declaration
> > Changes for v3:
> >- Move test command to cmd/
> >- Update Kconfig names and depends
> >- clean up default canary initialization
> > Changes for v2:
> >- Add test command and corresponding config
> >- Fixed incorrect description in Kconfig
> >- Add unit test
> > ---
> >  MAINTAINERS  |  7 +++
> >  Makefile |  5 +
> >  cmd/Kconfig  | 10 ++
> >  cmd/Makefile |  1 +
> >  cmd/stackprot_test.c | 21 +
> >  common/Kconfig   | 17 +
> >  common/Makefile  |  2 ++
> >  common/stackprot.c   | 19 +++
> >  configs/sandbox_defconfig| 14 +++---
> >  scripts/Makefile.spl |  6 ++
> >  test/py/tests/test_stackprotector.py | 15 +++
> >  11 files changed, 110 insertions(+), 7 deletions(-)
> >  create mode 100644 cmd/stackprot_test.c
> >  create mode 100644 common/stackprot.c
> >  create mode 100644 test/py/tests/test_stackprotector.py
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 26dd254..d3971e8 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1024,6 +1024,13 @@ F: include/sqfs.h
> >  F:   cmd/sqfs.c
> >  F:   test/py/tests/test_fs/test_squashfs/
> >
> > +STACKPROTECTOR
> > +M:   Joel Peshkin 
> > +S:   Maintained
> > +F:   common/stackprot.c
> > +F:   cmd/stackprot_test.c
> > +F:   test/py/tests/test_stackprotector.py
> > +
> >  TARGET_BCMNS3
> >  M:   Bharat Gooty 
> >  M:   Rayagonda Kokatanur 
> > diff --git a/Makefile b/Makefile
> > index 902a976..65c5cb8 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -677,7 +677,12 @@ else
> >  KBUILD_CFLAGS+= -O2
> >  endif
> >
> > +ifeq ($(CONFIG_STACKPROTECTOR),y)
> > +KBUILD_CFLAGS += $(call cc-option,-fstack-protector-strong)
> > +CFLAGS_EFI += $(call cc-option,-fno-stack-protector)
> > +else
> >  KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
> > +endif
> >  KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
> >
> >  # disable stringop warnings in gcc 8+
> > diff --git a/cmd/Kconfig b/cmd/Kconfig
> > index da86a94..054b2f3 100644
> > --- a/cmd/Kconfig
> > +++ b/cmd/Kconfig
> > @@ -2280,6 +2280,16 @@ config CMD_AVB
> >   avb read_part_hex - read data from partition and output to
> stdout
> >   avb write_part - write data to partition
> >   avb verify - run full verification chain
> > +
> > +config CMD_STACKPROTECTOR_TEST
> > + bool "Test command for stack protector"
> > + depends on STACKPROTECTOR
> > + default n
> > + help
> > +   Enable stackprot_test command
> > +   The stackprot_test command will force a stack overrun to test
> > +   the stack smashing detection mechanisms.
> > +
> >  endmenu
> >
> >  config CMD_UBI
> > diff --git a/cmd/Makefile b/cmd/Makefile
> > index 5b3400a..1d7afea 100644
> > --- a/cmd/Makefile
> > +++ b/cmd/Makefile
> > @@ -142,6 +142,7 @@ obj-$(CONFIG_CMD_SPI) += spi.o
> >  obj-$(CONFIG_CMD_STRINGS) += strings.o
> >  obj-$(CONFIG_CMD_SMC) += smccc.o
> >  obj-$(CONFIG_CMD_SYSBOOT) += sysboot.o pxe_utils.o
> > +obj-$(CONFIG_CMD_STACKPROTECTOR_TEST) += stackprot_test.o
> >  obj-$(CONFIG_CMD_TERMINAL) += terminal.o
> >  obj-$(CONFIG_CMD_TIME) += time.o
> >  obj-$(CONFIG_CMD_TIMER) += timer.o
> > diff --git a/cmd/stackprot_test.c b/cmd/stackprot_test.c
> > new file mode 100644
> > index 000..6ad287e
> > --- /dev/null
> > +++ b/cmd/stackprot_test.c
> > @@ -0,0 +1,21 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + *  Copyright 2021 Broadcom
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
>
> Hello Joël,
>
> This line is not needed.
>
> > +
> > +static int do_test_stackprot_fail(struct cmd_tbl *cmdtp, int flag, int
> argc,
> > +   char *const argv[])
> > +{
> > + char a[128];
> > +
> > + memset(a, 0xa5, 512);
> > + re

Re: [PATCH 19/19] ARM: imx8m: verdin-imx8mm: Enable USB Host support

2021-04-09 Thread Marek Vasut

On 4/8/21 9:08 AM, Marcel Ziswiler wrote:

Hi Marek


Hi,


Upon compiling I noticed the following but I do realize that it is not this 
patch set which introduced this
issue.

drivers/usb/host/ehci-mx6.c: In function ‘ehci_usb_probe’:
drivers/usb/host/ehci-mx6.c:686:30: warning: cast from pointer to integer of 
different size [-Wpointer-to-int-
cast]
   686 |  hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);


That's easy enough to fix.

[...]


Then upon booting I noticed the following two issues. Did you also see that?

write error to device: 930f90 register: x!write error to device: 930f90 
register: x!write error to device:
930f90 register: x!write error to device: 930f90 register: x!Normal Boot

imx_wdt watchdog@3028: pinctrl_select_state_full: 
uclass_get_device_by_phandle_id: err=-19


I suspect this has nothing to do with USB, but rather PMIC and then WDT?


Anyway, the USB host stuff this patch is about works perfectly. Thanks!


Great. Except V2 as soon as I sort out a few remaining CI issues.


Re: [PATCH 06/11] imx: ventana: convert U-Boot to OF_CONTROL using FIT image

2021-04-09 Thread Tim Harvey
On Fri, Apr 9, 2021 at 1:14 PM Tim Harvey  wrote:
>
> On Fri, Apr 9, 2021 at 1:08 PM Tim Harvey  wrote:
> >
> > On Fri, Apr 9, 2021 at 1:00 PM Stefano Babic  wrote:
> > >
> > > Hi Tim,
> > >
> > > On 09.04.21 21:52, Tim Harvey wrote:
> > > > On Thu, Apr 8, 2021 at 1:57 PM  wrote:
> > > >>
> > > >>> In preparation for dm conversion convert to OF_CONTROL by adding FIT 
> > > >>> image
> > > >>> support and multi dtb.
> > > >>> Add a board_fit_config_name_match to match the dtb based off of EEPROM
> > > >>> model.
> > > >>> Signed-off-by: Tim Harvey 
> > > >> Applied to u-boot-imx, master, thanks !
> > > >>
> > > >> Best regards,
> > > >> Stefano Babic
> > > >>
> > > >
> > > > Stefano,
> > > >
> > > > Something broke apparently between the branch I had my patches on top
> > > > of and u-boot-imx/master that these got merged in. My board is hanging
> > > > at dram_init_banksize - did something change recently that you are
> > > > aware of that may require some changes on my end?
> > > >
> > >
> > > There are a lot of changes, but they are related to i.MX8. I have not
> > > merged something for i.MX6 that can justify this behavior. So I do not
> > > know - have you compared the two branches, at least for Ventana boards ?
> > >
> >
> > It's hanging at arch/arm/mach-imx/spl.c:dram_init_banksize on
> > 'gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE' so I suppose
> > something is wrong with gd.
>
> specifically gd->bd is NULL. I'll have to track down how that gets setup.
>

Stefano,

commit 38d6b7ebdaee ("spl: Drop bd_info in the data section") is the
culprit which breaks IMX boards using SPL that don't define
SPL_ALLOC_BD. There is another thread regarding if that commit should
be reverted or if instead it can be fixed (ie by defining
SPL_ALLOC_BD) so probably not worth discussing in this thread anymore.

Best regards,

Tim


Re: [PATCH] Revert "spl: Drop bd_info in the data section"

2021-04-09 Thread Tim Harvey
On Fri, Apr 9, 2021 at 1:53 PM Tom Rini  wrote:
>
> On Fri, Apr 09, 2021 at 03:24:41PM -0500, Adam Ford wrote:
> > On Fri, Apr 9, 2021 at 2:20 PM Alex G.  wrote:
> > >
> > > Hi Simon
> > >
> > > On 4/8/21 6:55 PM, Simon Glass wrote:
> > > > Hi Alexandru,
> > > >
> > > > On Fri, 9 Apr 2021 at 04:56, Alexandru Gagniuc  
> > > > wrote:
> > > >>
> > > >> This reverts commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75.
> > > >>
> > > >> struct global_data contains a pointer to the bd_info structure. This
> > > >> pointer was populated spl_set_bd() to a pre-allocated bd_info in the
> > > >> ".data" section. The referenced commit replaced this mechanism to one
> > > >> that uses malloc(). That new mechanism is only used if SPL_ALLOC_BD=y.
> > > >> which very few boards do.
> > > >>
> > > >> The result is that (struct global_data)->bd is NULL in SPL on most
> > > >> platforms. This breaks falcon mode, since arch_fixup_fdt() tries to
> > > >> access (struct global_data)->bd and set the "/memory" node in the
> > > >> devicetree. The result is that the "/memory" node contains garbage
> > > >> values, causing linux to panic() as it sets up the page table.
> > > >>
> > > >> Instead of trying to fix the mess, potentially causing other issues,
> > > >> revert to the code that worked, while this change is reworked.
> > > >
> > > > The goal here is to drop a feature that few boards use and reduce
> > > > memory usage in SPL. It has been in place for two releases now.
> > > >
> > > > If Falcon mode needs it, perhaps you could add an 'imply' in the
> > > > Kconfig for that feature? Is there one? Or perhaps
> > > > CONFIG_ARCH_FIXUP_FDT_MEMORY ?
> > > >
> > > > One option would be to return an error in arch_fixup_fdt(). In
> > > > general, fixups make things tricky because there is no way to
> > > > determine when they are used but at least this one has a CONFIG.
> > > >
> > >
> > > The argument that this has been in place for two releases is incorrect.
> > > Commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75 was only introduced with
> > > the v2021.04 release. It definitely was not in 2021.01. It's only in the
> > > last release, which is four days old t the time of this writing.
>
> Yes.  But another way of saying that is that we're 4 days in to the
> merge window.  That's a bit early to say we must revert the change.  If
> this was just before the release, yes, revert would be the right answer.
> It's also the case the original commit fixes some cases while also
> saving size, if I read it right.  So a strict revert isn't right, we'd
> need to also probably also default y SPL_ALLOC_BD in some cases.
>
> > > Although I was able to find one example, the reality is that we don't
> > > know the full extent of the breakage. The prudent thing at this point is
> > > to revert.
> > >
> > > The knowledge of how to init the platform is in the devicetree and code.
> > > Why should kconfig also be involved in storing this knowledge? By this
> > > model, as the number of boards increases without bounds, every "if"
> > > predicate tends to be Kconfig driven. That is not maintainable, and why
> > > I think the original change --and the proposed fixes-- are broken by 
> > > design.
> > >
> > > Furthermore, I'm happy to discuss what to do about Falcon mode, and if
> > > we should kill it entirely (I have an alternative proposal).  But we
> > > shouldn't have that discussion in a manner holding my platform hostage.
> > > To be fair to you, I don't think reverting a 64-byte savings in .data
> > > will hold your platform hostage either.
> >
> > That original patch broke a bunch of OMAP boards, but enabling
> > SPL_ALLOC_BD was the solution to fix the issue.
> > Can you try enabling SPL_ALLOC_BD and see if that fixes it?  Maybe we
> > can make falcon mode imply it.
>
> It would be "select" since it needs it rather than imply.
>

I just ran into this as well finding that commit 38d6b7ebdaee ("spl:
Drop bd_info in the data section") breaks Gateworks Ventana and
defining SPL_ALLOC_BD does resolve it. In this case, Falcon mode is
not being used and the breakage is because arch/arm/mach-imx/spl.c
dram_init_banksize() accesses gd->bd which is NULL.

So I would guess that this probably broke a whole lot of IMX based
boards that use SPL.

I don't quite know what the best solution is... we now have a v2021.04
that is broken for several or many boards and I dont' know if its
clear what cases break.

Best regards,

Tim


Re: [PATCH v2] cmd: net: Add the "arp" command

2021-04-09 Thread Heinrich Schuchardt

On 4/9/21 11:46 PM, lg...@hotmail.com wrote:

From: Joe Xue 

The command is to query and show mac address of a specific ipAddress.

Signed-off-by: Joe Xue 
---

  cmd/Kconfig   |  6 ++
  cmd/net.c | 36 
  doc/usage/arp.rst | 31 +++
  include/net.h |  5 +
  net/arp.c | 24 
  net/arp.h |  4 
  net/net.c |  8 
  7 files changed, 114 insertions(+)
  create mode 100644 doc/usage/arp.rst

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 9bf5e863e4..1da4cb67f6 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1587,6 +1587,12 @@ config CMD_PING
help
  Send ICMP ECHO_REQUEST to network host

+config CMD_ARP
+   bool "arp"
+   help
+ Sends ARP_REQUEST to network host and shows the result if there is arp
+ response.
+
  config CMD_CDP
bool "cdp"
help
diff --git a/cmd/net.c b/cmd/net.c
index beb2877dfd..369d15474c 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -479,4 +479,40 @@ U_BOOT_CMD(
""
  );



Have a look at the #ifdef above in the code. I assume that the
dependency on CONFIG_CMD_LINK_LOCAL was not your intention.


+#ifdef CONFIG_CMD_ARP
+static int do_arp(struct cmd_tbl *cmdtp, int flag, int argc, char *const 
argv[])
+{
+   u8 *ethaddr = arp_query_ethaddr;
+
+   if (argc < 2)
+   return CMD_RET_USAGE;
+
+   arp_query_ip = string_to_ip(argv[1]);
+   if (arp_query_ip.s_addr == 0)
+   return CMD_RET_USAGE;
+
+   if ((arp_query_ip.s_addr & net_netmask.s_addr) !=
+   (net_ip.s_addr & net_netmask.s_addr)) {
+   printf("The host %s is not in the same network\n", argv[1]);
+   return CMD_RET_SUCCESS;
+   }
+
+   if (net_loop(ARP) < 0) {
+   printf("arp failed; host %s is not alive\n", argv[1]);
+   return CMD_RET_FAILURE;
+   }
+
+   printf("%s\t%02x:%02x:%02x:%02x:%02x:%02x\n", argv[1], ethaddr[0],
+  ethaddr[1], ethaddr[2], ethaddr[3], ethaddr[4], ethaddr[5]);
+
+   return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+   arp,2,  1,  do_arp,
+   "send ARP ARP_REQUEST to network host",
+   "ipAddress"
+);
+#endif
+
  #endif  /* CONFIG_CMD_LINK_LOCAL */
diff --git a/doc/usage/arp.rst b/doc/usage/arp.rst
new file mode 100644
index 00..b1f08a2ae9
--- /dev/null
+++ b/doc/usage/arp.rst
@@ -0,0 +1,31 @@
+arp command
+===
+
+Synopis
+---
+
+::
+
+arp ipAddress
+
+Description
+---
+
+The arp command is used to send ARP_REQUEST to network host and show the 
result.
+
+ipAddress
+the host ip address


%s/ip/IP/

Why should the IP address be a required parameter? The most interesting
use case for the arp command is discovering neighbors.

On Linux 'arp -n' gives me the list of *all* devices in the same network
segment with both MAC address and IP address.

Can we do the same in U-Boot?

Best regards

Heinrich


+
+Example
+---
+
+::
+
+=> arp 192.168.0.1
+Using host_ens33 device
+192.168.0.1 84:94:8c:5f:e1:62
+
+Return value
+
+
+The return value $? is 0 if the comand running was successful else 1
diff --git a/include/net.h b/include/net.h
index b95d6a6f60..60b4bf610e 100644
--- a/include/net.h
+++ b/include/net.h
@@ -580,6 +580,11 @@ extern char *net_dns_env_var;  /* the env var 
to put the ip into */
  extern struct in_addr net_ping_ip;/* the ip address to ping */
  #endif

+#if defined(CONFIG_CMD_ARP)
+extern u8 arp_query_ethaddr[6];/* the arp query result */
+extern struct in_addr arp_query_ip; /* the ip address to arp query */
+#endif
+
  #if defined(CONFIG_CMD_CDP)
  /* when CDP completes these hold the return values */
  extern ushort cdp_native_vlan;/* CDP returned native VLAN */
diff --git a/net/arp.c b/net/arp.c
index 1d06ed2572..83c24072d7 100644
--- a/net/arp.c
+++ b/net/arp.c
@@ -220,11 +220,20 @@ void arp_receive(struct ethernet_hdr *et, struct 
ip_udp_hdr *ip, int len)
net_get_arp_handler()((uchar *)arp, 0, reply_ip_addr,
  0, len);

+#ifdef CONFIG_CMD_ARP
+   if (arp_query_ip.s_addr != 0) {
+   arp_query_ip.s_addr = 0;
+   net_set_state(NETLOOP_SUCCESS);
+   } else {
+#endif
/* set the mac address in the waiting packet's header
   and transmit it */
memcpy(((struct ethernet_hdr *)net_tx_packet)->et_dest,
   &arp->ar_sha, ARP_HLEN);
net_send_packet(net_tx_packet, arp_wait_tx_packet_size);
+#ifdef CONFIG_CMD_ARP
+   }
+#endif

/* no arp request pending now */
net_arp_wait_packet_ip.s_addr = 0;
@@ -243,3 +252,18 @

Re: [PATCH 0/5] Add support for embedding public key in platform's dtb

2021-04-09 Thread Simon Glass
Hi Sughosh,

On Fri, 9 Apr 2021 at 23:27, Sughosh Ganu  wrote:
>
> hi Simon,
>
> On Fri, 9 Apr 2021 at 05:26, Simon Glass  wrote:
>>
>> Hi Sughosh,
>>
>> On Thu, 8 Apr 2021 at 18:53, Sughosh Ganu  wrote:
>> >
>> > hi Simon,
>> >
>> > On Wed, 7 Apr 2021 at 21:44, Simon Glass  wrote:
>> >>
>> >> Hi,
>> >>
>> >> On Wed, 7 Apr 2021 at 23:54, Sughosh Ganu  wrote:
>> >> >
>> >> > Patch 1 fixes an issue of selection of IMAGE_SIGN_INFO config option
>> >> > when capsule authentication is enabled.
>> >> >
>> >> > Patch 2 add two config symbols, EFI_PKEY_DTB_EMBED and EFI_PKEY_FILE
>> >> > which are used for enabling embedding of the public key in the dtb,
>> >> > and specifying the esl file name.
>> >> >
>> >> > Patch 3 moves efi_capsule_auth_enabled as a weak function, which can
>> >> > be used as a default mechanism for checking if capsule authentication
>> >> > has been enabled.
>> >> >
>> >> > Patch 4 adds a default weak function for retrieving the public key
>> >> > from the platform's dtb.
>> >> >
>> >> > Patch 5 adds the functionality to embed the esl file into the
>> >> > platform's dtb during the platform build.
>> >> >
>> >> > I have tested this functionality on the STM32MP157C DK2 board.
>> >> >
>> >> > [1] - https://lists.denx.de/pipermail/u-boot/2021-March/442867.html
>> >> >
>> >> > Sughosh Ganu (5):
>> >> >   efi_loader: Kconfig: Select IMAGE_SIGN_INFO when capsule
>> >> > authentication is enabled
>> >> >   efi_loader: Kconfig: Add symbols for embedding the public key into the
>> >> > platform's dtb
>> >> >   efi_capsule: Add a weak function to check whether capsule
>> >> > authentication is enabled
>> >> >   efi_capsule: Add a weak function to get the public key needed for
>> >> > capsule authentication
>> >> >   Makefile: Add provision for embedding public key in platform's dtb
>> >> >
>> >> >  Makefile  | 10 ++
>> >> >  board/emulation/common/qemu_capsule.c |  6 
>> >> >  lib/efi_loader/Kconfig| 16 ++
>> >> >  lib/efi_loader/efi_capsule.c  | 44 ---
>> >> >  4 files changed, 66 insertions(+), 10 deletions(-)
>> >> >
>> >> > --
>> >> > 2.17.1
>> >> >
>> >>
>> >> We need to rethink the use of weak functions for this sort of thing,
>> >> or we will end up with an unnavigable mess at some point. If we need
>> >> to adjust the flow of boot, let's adjust the flow rather than adding
>> >> hooks everywhere.
>> >
>> >
>> > There are two weak functions being added. One is for retrieving the public 
>> > key to be used for the capsule authentication, and the other is for 
>> > checking for whether capsule authentication has been enabled. The reason 
>> > why a weak function is needed is because platforms can have other 
>> > mechanisms for retrieval of the public key or for testing if capsule 
>> > authentication has been enabled.
>> >
>> > If we consider the case of public key retrieval, the majority of platforms 
>> > would be built with the device tree concatenated with the u-boot binary. 
>> > The weak function would cater to all of those platforms -- having a weak 
>> > function would mean that we are not required to repeat the same 
>> > functionality for every platform that uses the same mechanism for 
>> > extracting the public key. However, there would be platforms where the 
>> > public key is obtained through a different mechanism which is platform 
>> > specific. Those platforms would have to define their own function to get 
>> > the public key. Same for checking whether capsule authentication feature 
>> > has been enabled or not.
>> >
>> > -sughosh
>>
>> Yes, I get it, but if this is to be a critical feature and part of the
>> grand new design for verified boot using UEFI, surely we should be
>> building a new front door, not digging a tunnel in the bathroom :-)
>>
>> We can either use drivers with driver model, or perhaps have a Kconfig
>> that enables calling the function (so we get a link error if not
>> provided). Or if there will be more than one handler, a linker_list.
>
>
> I will use the Kconfig symbol for selecting the function to use for 
> retrieving the public key. So, in the current scenario, the function would be 
> under the CONFIG_EFI_PKEY_DTB_EMBED symbol. This should cater to the majority 
> of the cases. If some platform wants to use a different method to get the 
> public key, it would need to define it's own function.

I wonder why another method would be needed, but if it, then someone
can turn your thing into a choice, I suppose.

Regards,
Simon


Re: [PATCH] board_f: cosmetic: change the debug trace to KB in reserve_video

2021-04-09 Thread Simon Glass
On Sat, 10 Apr 2021 at 04:02, Patrick Delaunay
 wrote:
>
> Update the debug trace for the reserved video memory to KB as indicated
> in the message with "%luk"; before the patch the computed size
> gd->relocaddr - addr is in bytes.
>
> This patch aligns the debug trace in reserve_video() with others
> functions, for example on stm32mp157c-dk2:
>
>   - Reserving 3080192k for video at: dfd0
>   + Reserving 3008k for video at: dfd0
> Reserving 873k for U-Boot at: dfc25000
> Reserving 32776k for malloc() at: ddc23000
> Reserving 72 Bytes for Board Info at: ddc22fb0
> Reserving 280 Bytes for Global Data at: ddc22e90
> Reserving 119072 Bytes for FDT at: ddc05d70
> Reserving 0x278 Bytes for bootstage at: ddc05af0
>
> Fixes: 5630d2fbc50f3035 ("board: Show memory for frame buffers")
> Signed-off-by: Patrick Delaunay 
> ---
>
>  common/board_f.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Simon Glass 


Re: [PATCH] Revert "spl: Drop bd_info in the data section"

2021-04-09 Thread Tom Rini
On Fri, Apr 09, 2021 at 03:24:41PM -0500, Adam Ford wrote:
> On Fri, Apr 9, 2021 at 2:20 PM Alex G.  wrote:
> >
> > Hi Simon
> >
> > On 4/8/21 6:55 PM, Simon Glass wrote:
> > > Hi Alexandru,
> > >
> > > On Fri, 9 Apr 2021 at 04:56, Alexandru Gagniuc  
> > > wrote:
> > >>
> > >> This reverts commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75.
> > >>
> > >> struct global_data contains a pointer to the bd_info structure. This
> > >> pointer was populated spl_set_bd() to a pre-allocated bd_info in the
> > >> ".data" section. The referenced commit replaced this mechanism to one
> > >> that uses malloc(). That new mechanism is only used if SPL_ALLOC_BD=y.
> > >> which very few boards do.
> > >>
> > >> The result is that (struct global_data)->bd is NULL in SPL on most
> > >> platforms. This breaks falcon mode, since arch_fixup_fdt() tries to
> > >> access (struct global_data)->bd and set the "/memory" node in the
> > >> devicetree. The result is that the "/memory" node contains garbage
> > >> values, causing linux to panic() as it sets up the page table.
> > >>
> > >> Instead of trying to fix the mess, potentially causing other issues,
> > >> revert to the code that worked, while this change is reworked.
> > >
> > > The goal here is to drop a feature that few boards use and reduce
> > > memory usage in SPL. It has been in place for two releases now.
> > >
> > > If Falcon mode needs it, perhaps you could add an 'imply' in the
> > > Kconfig for that feature? Is there one? Or perhaps
> > > CONFIG_ARCH_FIXUP_FDT_MEMORY ?
> > >
> > > One option would be to return an error in arch_fixup_fdt(). In
> > > general, fixups make things tricky because there is no way to
> > > determine when they are used but at least this one has a CONFIG.
> > >
> >
> > The argument that this has been in place for two releases is incorrect.
> > Commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75 was only introduced with
> > the v2021.04 release. It definitely was not in 2021.01. It's only in the
> > last release, which is four days old t the time of this writing.

Yes.  But another way of saying that is that we're 4 days in to the
merge window.  That's a bit early to say we must revert the change.  If
this was just before the release, yes, revert would be the right answer.
It's also the case the original commit fixes some cases while also
saving size, if I read it right.  So a strict revert isn't right, we'd
need to also probably also default y SPL_ALLOC_BD in some cases.

> > Although I was able to find one example, the reality is that we don't
> > know the full extent of the breakage. The prudent thing at this point is
> > to revert.
> >
> > The knowledge of how to init the platform is in the devicetree and code.
> > Why should kconfig also be involved in storing this knowledge? By this
> > model, as the number of boards increases without bounds, every "if"
> > predicate tends to be Kconfig driven. That is not maintainable, and why
> > I think the original change --and the proposed fixes-- are broken by design.
> >
> > Furthermore, I'm happy to discuss what to do about Falcon mode, and if
> > we should kill it entirely (I have an alternative proposal).  But we
> > shouldn't have that discussion in a manner holding my platform hostage.
> > To be fair to you, I don't think reverting a 64-byte savings in .data
> > will hold your platform hostage either.
> 
> That original patch broke a bunch of OMAP boards, but enabling
> SPL_ALLOC_BD was the solution to fix the issue.
> Can you try enabling SPL_ALLOC_BD and see if that fixes it?  Maybe we
> can make falcon mode imply it.

It would be "select" since it needs it rather than imply.

-- 
Tom


signature.asc
Description: PGP signature


Re: [PATCH] cmd: net: Add the "arp" command

2021-04-09 Thread Heinrich Schuchardt
Am 9. April 2021 20:45:36 MESZ schrieb lg...@hotmail.com:
>From: Joe Xue 
>
>The command is to query and show mac address of a specific ipAddress.

Dear Joe,

please, add a man-page for the command in /doc/usage/.

>
>Signed-off-by: Joe Xue 
>---
>
> cmd/Kconfig   |  6 ++
> cmd/net.c | 36 
> include/net.h |  5 +
> net/arp.c | 24 
> net/arp.h |  4 
> net/net.c |  8 
> 6 files changed, 83 insertions(+)
>
>diff --git a/cmd/Kconfig b/cmd/Kconfig
>index 9bf5e863e4..1da4cb67f6 100644
>--- a/cmd/Kconfig
>+++ b/cmd/Kconfig
>@@ -1587,6 +1587,12 @@ config CMD_PING
>   help
> Send ICMP ECHO_REQUEST to network host
> 
>+config CMD_ARP
>+  bool "arp"
>+  help
>+Sends ARP_REQUEST to network host and shows the result if there is
>arp

an arp response

Best regards

Heinrich

>+response.
>+
> config CMD_CDP
>   bool "cdp"
>   help
>diff --git a/cmd/net.c b/cmd/net.c
>index beb2877dfd..369d15474c 100644
>--- a/cmd/net.c
>+++ b/cmd/net.c
>@@ -479,4 +479,40 @@ U_BOOT_CMD(
>   ""
> );
> 
>+#ifdef CONFIG_CMD_ARP
>+static int do_arp(struct cmd_tbl *cmdtp, int flag, int argc, char
>*const argv[])
>+{
>+  u8 *ethaddr = arp_query_ethaddr;
>+
>+  if (argc < 2)
>+  return CMD_RET_USAGE;
>+
>+  arp_query_ip = string_to_ip(argv[1]);
>+  if (arp_query_ip.s_addr == 0)
>+  return CMD_RET_USAGE;
>+
>+  if ((arp_query_ip.s_addr & net_netmask.s_addr) !=
>+  (net_ip.s_addr & net_netmask.s_addr)) {
>+  printf("The host %s is not in the same network\n", argv[1]);
>+  return CMD_RET_SUCCESS;
>+  }
>+
>+  if (net_loop(ARP) < 0) {
>+  printf("arp failed; host %s is not alive\n", argv[1]);
>+  return CMD_RET_FAILURE;
>+  }
>+
>+  printf("%s\t%02x:%02x:%02x:%02x:%02x:%02x\n", argv[1], ethaddr[0],
>+ ethaddr[1], ethaddr[2], ethaddr[3], ethaddr[4], ethaddr[5]);
>+
>+  return CMD_RET_SUCCESS;
>+}
>+
>+U_BOOT_CMD(
>+  arp,2,  1,  do_arp,
>+  "send ARP ARP_REQUEST to network host",
>+  "ipAddress"
>+);
>+#endif
>+
> #endif  /* CONFIG_CMD_LINK_LOCAL */
>diff --git a/include/net.h b/include/net.h
>index b95d6a6f60..60b4bf610e 100644
>--- a/include/net.h
>+++ b/include/net.h
>@@ -580,6 +580,11 @@ extern char *net_dns_env_var; /* the env var 
>to
>put the ip into */
> extern struct in_addr net_ping_ip;/* the ip address to ping */
> #endif
> 
>+#if defined(CONFIG_CMD_ARP)
>+extern u8 arp_query_ethaddr[6];   /* the arp query result */
>+extern struct in_addr arp_query_ip; /* the ip address to arp query */
>+#endif
>+
> #if defined(CONFIG_CMD_CDP)
> /* when CDP completes these hold the return values */
> extern ushort cdp_native_vlan;/* CDP returned native VLAN */
>diff --git a/net/arp.c b/net/arp.c
>index 1d06ed2572..83c24072d7 100644
>--- a/net/arp.c
>+++ b/net/arp.c
>@@ -220,11 +220,20 @@ void arp_receive(struct ethernet_hdr *et, struct
>ip_udp_hdr *ip, int len)
>   net_get_arp_handler()((uchar *)arp, 0, reply_ip_addr,
> 0, len);
> 
>+#ifdef CONFIG_CMD_ARP
>+  if (arp_query_ip.s_addr != 0) {
>+  arp_query_ip.s_addr = 0;
>+  net_set_state(NETLOOP_SUCCESS);
>+  } else {
>+#endif
>   /* set the mac address in the waiting packet's header
>  and transmit it */
>   memcpy(((struct ethernet_hdr *)net_tx_packet)->et_dest,
>  &arp->ar_sha, ARP_HLEN);
>   net_send_packet(net_tx_packet, arp_wait_tx_packet_size);
>+#ifdef CONFIG_CMD_ARP
>+  }
>+#endif
> 
>   /* no arp request pending now */
>   net_arp_wait_packet_ip.s_addr = 0;
>@@ -243,3 +252,18 @@ bool arp_is_waiting(void)
> {
>   return !!net_arp_wait_packet_ip.s_addr;
> }
>+
>+#ifdef CONFIG_CMD_ARP
>+u8 arp_query_ethaddr[6];
>+struct in_addr arp_query_ip;
>+
>+void arp_query(void)
>+{
>+  arp_wait_packet_ethaddr = arp_query_ethaddr;
>+  net_arp_wait_packet_ip = arp_query_ip;
>+
>+  arp_wait_timer_start = get_timer(0);
>+  printf("Using %s device\n", eth_get_name());
>+  arp_request();
>+}
>+#endif
>diff --git a/net/arp.h b/net/arp.h
>index 25b3c00d5c..f3e5cb8504 100644
>--- a/net/arp.h
>+++ b/net/arp.h
>@@ -29,4 +29,8 @@ void arp_raw_request(struct in_addr source_ip, const
>uchar *targetEther,
> int arp_timeout_check(void);
>void arp_receive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int
>len);
> 
>+#ifdef CONFIG_CMD_ARP
>+void arp_query(void);
>+#endif
>+
> #endif /* __ARP_H__ */
>diff --git a/net/net.c b/net/net.c
>index b58f3062b2..21623562e8 100644
>--- a/net/net.c
>+++ b/net/net.c
>@@ -492,6 +492,11 @@ restart:
> 

Re: [PATCH] Revert "spl: Drop bd_info in the data section"

2021-04-09 Thread Adam Ford
On Fri, Apr 9, 2021 at 2:20 PM Alex G.  wrote:
>
> Hi Simon
>
> On 4/8/21 6:55 PM, Simon Glass wrote:
> > Hi Alexandru,
> >
> > On Fri, 9 Apr 2021 at 04:56, Alexandru Gagniuc  wrote:
> >>
> >> This reverts commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75.
> >>
> >> struct global_data contains a pointer to the bd_info structure. This
> >> pointer was populated spl_set_bd() to a pre-allocated bd_info in the
> >> ".data" section. The referenced commit replaced this mechanism to one
> >> that uses malloc(). That new mechanism is only used if SPL_ALLOC_BD=y.
> >> which very few boards do.
> >>
> >> The result is that (struct global_data)->bd is NULL in SPL on most
> >> platforms. This breaks falcon mode, since arch_fixup_fdt() tries to
> >> access (struct global_data)->bd and set the "/memory" node in the
> >> devicetree. The result is that the "/memory" node contains garbage
> >> values, causing linux to panic() as it sets up the page table.
> >>
> >> Instead of trying to fix the mess, potentially causing other issues,
> >> revert to the code that worked, while this change is reworked.
> >
> > The goal here is to drop a feature that few boards use and reduce
> > memory usage in SPL. It has been in place for two releases now.
> >
> > If Falcon mode needs it, perhaps you could add an 'imply' in the
> > Kconfig for that feature? Is there one? Or perhaps
> > CONFIG_ARCH_FIXUP_FDT_MEMORY ?
> >
> > One option would be to return an error in arch_fixup_fdt(). In
> > general, fixups make things tricky because there is no way to
> > determine when they are used but at least this one has a CONFIG.
> >
>
> The argument that this has been in place for two releases is incorrect.
> Commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75 was only introduced with
> the v2021.04 release. It definitely was not in 2021.01. It's only in the
> last release, which is four days old t the time of this writing.
>
> Although I was able to find one example, the reality is that we don't
> know the full extent of the breakage. The prudent thing at this point is
> to revert.
>
> The knowledge of how to init the platform is in the devicetree and code.
> Why should kconfig also be involved in storing this knowledge? By this
> model, as the number of boards increases without bounds, every "if"
> predicate tends to be Kconfig driven. That is not maintainable, and why
> I think the original change --and the proposed fixes-- are broken by design.
>
> Furthermore, I'm happy to discuss what to do about Falcon mode, and if
> we should kill it entirely (I have an alternative proposal).  But we
> shouldn't have that discussion in a manner holding my platform hostage.
> To be fair to you, I don't think reverting a 64-byte savings in .data
> will hold your platform hostage either.

That original patch broke a bunch of OMAP boards, but enabling
SPL_ALLOC_BD was the solution to fix the issue.
Can you try enabling SPL_ALLOC_BD and see if that fixes it?  Maybe we
can make falcon mode imply it.

adam
>
> Alex
>


Re: [PATCH 06/11] imx: ventana: convert U-Boot to OF_CONTROL using FIT image

2021-04-09 Thread Tim Harvey
On Fri, Apr 9, 2021 at 1:08 PM Tim Harvey  wrote:
>
> On Fri, Apr 9, 2021 at 1:00 PM Stefano Babic  wrote:
> >
> > Hi Tim,
> >
> > On 09.04.21 21:52, Tim Harvey wrote:
> > > On Thu, Apr 8, 2021 at 1:57 PM  wrote:
> > >>
> > >>> In preparation for dm conversion convert to OF_CONTROL by adding FIT 
> > >>> image
> > >>> support and multi dtb.
> > >>> Add a board_fit_config_name_match to match the dtb based off of EEPROM
> > >>> model.
> > >>> Signed-off-by: Tim Harvey 
> > >> Applied to u-boot-imx, master, thanks !
> > >>
> > >> Best regards,
> > >> Stefano Babic
> > >>
> > >
> > > Stefano,
> > >
> > > Something broke apparently between the branch I had my patches on top
> > > of and u-boot-imx/master that these got merged in. My board is hanging
> > > at dram_init_banksize - did something change recently that you are
> > > aware of that may require some changes on my end?
> > >
> >
> > There are a lot of changes, but they are related to i.MX8. I have not
> > merged something for i.MX6 that can justify this behavior. So I do not
> > know - have you compared the two branches, at least for Ventana boards ?
> >
>
> It's hanging at arch/arm/mach-imx/spl.c:dram_init_banksize on
> 'gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE' so I suppose
> something is wrong with gd.

specifically gd->bd is NULL. I'll have to track down how that gets setup.

Tim


Re: [PATCH 06/11] imx: ventana: convert U-Boot to OF_CONTROL using FIT image

2021-04-09 Thread Tim Harvey
On Fri, Apr 9, 2021 at 1:00 PM Stefano Babic  wrote:
>
> Hi Tim,
>
> On 09.04.21 21:52, Tim Harvey wrote:
> > On Thu, Apr 8, 2021 at 1:57 PM  wrote:
> >>
> >>> In preparation for dm conversion convert to OF_CONTROL by adding FIT image
> >>> support and multi dtb.
> >>> Add a board_fit_config_name_match to match the dtb based off of EEPROM
> >>> model.
> >>> Signed-off-by: Tim Harvey 
> >> Applied to u-boot-imx, master, thanks !
> >>
> >> Best regards,
> >> Stefano Babic
> >>
> >
> > Stefano,
> >
> > Something broke apparently between the branch I had my patches on top
> > of and u-boot-imx/master that these got merged in. My board is hanging
> > at dram_init_banksize - did something change recently that you are
> > aware of that may require some changes on my end?
> >
>
> There are a lot of changes, but they are related to i.MX8. I have not
> merged something for i.MX6 that can justify this behavior. So I do not
> know - have you compared the two branches, at least for Ventana boards ?
>

It's hanging at arch/arm/mach-imx/spl.c:dram_init_banksize on
'gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE' so I suppose
something is wrong with gd.

I'll have to compare branches as you suggest.

Tim


Re: [PATCH 06/11] imx: ventana: convert U-Boot to OF_CONTROL using FIT image

2021-04-09 Thread Stefano Babic

Hi Tim,

On 09.04.21 21:52, Tim Harvey wrote:

On Thu, Apr 8, 2021 at 1:57 PM  wrote:



In preparation for dm conversion convert to OF_CONTROL by adding FIT image
support and multi dtb.
Add a board_fit_config_name_match to match the dtb based off of EEPROM
model.
Signed-off-by: Tim Harvey 

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic



Stefano,

Something broke apparently between the branch I had my patches on top
of and u-boot-imx/master that these got merged in. My board is hanging
at dram_init_banksize - did something change recently that you are
aware of that may require some changes on my end?



There are a lot of changes, but they are related to i.MX8. I have not 
merged something for i.MX6 that can justify this behavior. So I do not 
know - have you compared the two branches, at least for Ventana boards ?


Stefano


Thanks,

Tim



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Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [PATCH 06/11] imx: ventana: convert U-Boot to OF_CONTROL using FIT image

2021-04-09 Thread Tim Harvey
On Thu, Apr 8, 2021 at 1:57 PM  wrote:
>
> > In preparation for dm conversion convert to OF_CONTROL by adding FIT image
> > support and multi dtb.
> > Add a board_fit_config_name_match to match the dtb based off of EEPROM
> > model.
> > Signed-off-by: Tim Harvey 
> Applied to u-boot-imx, master, thanks !
>
> Best regards,
> Stefano Babic
>

Stefano,

Something broke apparently between the branch I had my patches on top
of and u-boot-imx/master that these got merged in. My board is hanging
at dram_init_banksize - did something change recently that you are
aware of that may require some changes on my end?

Thanks,

Tim


Re: [PATCH] Revert "spl: Drop bd_info in the data section"

2021-04-09 Thread Alex G.

Hi Simon

On 4/8/21 6:55 PM, Simon Glass wrote:

Hi Alexandru,

On Fri, 9 Apr 2021 at 04:56, Alexandru Gagniuc  wrote:


This reverts commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75.

struct global_data contains a pointer to the bd_info structure. This
pointer was populated spl_set_bd() to a pre-allocated bd_info in the
".data" section. The referenced commit replaced this mechanism to one
that uses malloc(). That new mechanism is only used if SPL_ALLOC_BD=y.
which very few boards do.

The result is that (struct global_data)->bd is NULL in SPL on most
platforms. This breaks falcon mode, since arch_fixup_fdt() tries to
access (struct global_data)->bd and set the "/memory" node in the
devicetree. The result is that the "/memory" node contains garbage
values, causing linux to panic() as it sets up the page table.

Instead of trying to fix the mess, potentially causing other issues,
revert to the code that worked, while this change is reworked.


The goal here is to drop a feature that few boards use and reduce
memory usage in SPL. It has been in place for two releases now.

If Falcon mode needs it, perhaps you could add an 'imply' in the
Kconfig for that feature? Is there one? Or perhaps
CONFIG_ARCH_FIXUP_FDT_MEMORY ?

One option would be to return an error in arch_fixup_fdt(). In
general, fixups make things tricky because there is no way to
determine when they are used but at least this one has a CONFIG.



The argument that this has been in place for two releases is incorrect. 
Commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75 was only introduced with 
the v2021.04 release. It definitely was not in 2021.01. It's only in the 
last release, which is four days old t the time of this writing.


Although I was able to find one example, the reality is that we don't 
know the full extent of the breakage. The prudent thing at this point is 
to revert.


The knowledge of how to init the platform is in the devicetree and code. 
Why should kconfig also be involved in storing this knowledge? By this 
model, as the number of boards increases without bounds, every "if" 
predicate tends to be Kconfig driven. That is not maintainable, and why 
I think the original change --and the proposed fixes-- are broken by design.


Furthermore, I'm happy to discuss what to do about Falcon mode, and if 
we should kill it entirely (I have an alternative proposal).  But we 
shouldn't have that discussion in a manner holding my platform hostage. 
To be fair to you, I don't think reverting a 64-byte savings in .data 
will hold your platform hostage either.


Alex



Re: Running u-boot 2021.04 on Raspberry Pi 4

2021-04-09 Thread Roman Shaposhnik
On Fri, Apr 9, 2021 at 3:15 AM Matthias Brugger  wrote:

>
>
> On 09/04/2021 10:14, Nicolas Saenz Julienne wrote:
> > [ Adding Matthias for the SMBIOS part ]
> >
> > On Fri, 2021-04-09 at 00:00 -0700, Roman Shaposhnik wrote:
> >> On Thu, Apr 8, 2021 at 8:59 PM Sean Anderson  wrote:
> >>> On 4/8/21 8:18 PM, Roman Shaposhnik wrote:
>  Hi!
> 
>  first time poster, long time lurker here. Over at Project EVE
>  https://github.com/lf-edge/eve I've been trying to migrate
>  from our current u-boot v2020.07 + patches:
> 
> 
> https://github.com/lf-edge/eve/tree/master/pkg/u-boot/patches/patches-v2020.07
>  to the latest u-boot 2021.04.
> 
>  Great news is that most of the patches we dependent
>  on seem to have been pulled upstream. However, this
>  single *chunk* of one patchset wasn't:
> 
> 
> https://github.com/lf-edge/eve/blob/master/pkg/u-boot/patches/patches-v2020.07/0001-usb-xhci-Load-Raspberry-Pi-4-VL805-s-firmware.patch#L293
> 
>  I'm wondering what was the reason for leaving it behind,
> >>>
> >>> +CC Nicolas
> >>>
>    - Get rid of PCI core patch as not needed with correct DT PCI
> topology
> >>>
> >>> also from the cover letter
> >>>
>  This also depends on a DT/bindings patch available on the
> linux-mailing lists:
>  https://www.mail-archive.com/linux-kernel@.../msg2205783.html
> >>>
> >>> The merged version of this series is
> >>>
> >>>
> https://patchwork.kernel.org/project/linux-usb/list/?series=310015&state=%2A&archive=both
> >>>
>  Here is the relevant bit for reference/discussion:
> 
>   &pcie0 {
>  pci@1,0 {
>  #address-cells = <3>;
>  #size-cells = <2>;
>  ranges;
> 
>  reg = <0 0 0 0 0>;
> 
>  usb@1,0 {
>  reg = <0x1 0 0 0 0>;
>  resets = <&reset
> RASPBERRYPI_FIRMWARE_RESET_ID_USB>;
>  };
>  };
>   };
> >>>
> >
> > Yes, instead of using a PCI quirk we settled on a reset controller. All
> in all
> > it is less hacky. But needs changes in DT.
> >
> >> Aha! Thank you so much -- this is super helpful!
> >>
>  since without it I don't seem to have functioning USB
>  devices on my  Raspberry Pi 4. In fact, adding it back:
> 
> 
> https://github.com/rvs/eve/tree/u-boot/pkg/u-boot/patches/patches-v2021.04
>  (just that one chunk -- 'cuz the reset got upstreamed)
>  seems to solve the issue for me.
> 
>  Another question I have is that the new u-boot seems to have
>  some kind of a regression that I can't quite debug. The SMBIOS
>  tables that it constructs during EFI boot sequence seem to be
>  broken (see the dmidecode output below). Again, this seems
>  to be a regression compared to  v2020.07. Any ideas on what
>  could be wrong or how can I start debugging it would be
> >>>
>
> Yes, that's not working right now. I'm working on a fix for the tables:
>
> https://patchwork.ozlabs.org/project/uboot/patch/20210406090435.19357-1-matthias@kernel.org/
>
> This will fix the error en dmidecode but the tables will be basically
> empty.
> Before that there was some information that helped you to identify that
> you are
> running on a RaspberryPi.
>
> A quick fix would be to add that information to the DTS. Like for example
> done here:
>
> https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/rk3328-rock64-u-boot.dtsi#L13


Thanks! Works like a charm:

https://github.com/lf-edge/eve/blob/master/pkg/u-boot/rpi/overlays/raspberrypi-rpi.dts

But yes -- it would be nice to fix the default behaviour. Speaking of
tables being empty
(once your fix above makes it in) it may also make sense to document it
someplace,
but I honestly don't know what a good place for that would be ;-)


> On the long run we want to add a sysinfo driver to read the information
> for the
> mailbox driver and use that. But my understanding is that for that we
> would need
> to create a SPL for the mailbox driver to provide that info in a shared
> data
> structure. It's still on my list for investigation.
>

That sounds pretty useful too -- although my usecase is much more limited
-- I just
need to be able to provide quick DT overlays to reliably identify various
HATs on RPi
at the SMBIOS level.

Where it gets interesting, of course, are the HATs that provide their OWN
DTs via
EEPROM I2C.

Thanks,
Roman.


Re: mkimage regression when building ARCH=mips defconfig Linux kernel

2021-04-09 Thread Tom Rini
On Fri, Apr 09, 2021 at 11:55:52AM +1200, Simon Glass wrote:
> +Tom Rini
> 
> Hi Nathan,
> 
> On Fri, 9 Apr 2021 at 06:23, Nathan Chancellor  wrote:
> >
> > Hi Simon,
> >
> > Apologies if this is not the proper way to report a regression, this is my 
> > first
> > time interacting with the U-Boot community.
> >
> > My distribution updated the uboot-tools package to 2021.04, which broke my
> > Linux kernel builds for ARCH=mips:
> >
> > $ make -skj"$(nproc)" ARCH=mips CROSS_COMPILE=mips-linux- defconfig all
> > ...
> > /usr/bin/mkimage: verify_header failed for FIT Image support with exit code 
> > 1
> > make[2]: *** [arch/mips/boot/Makefile:173: arch/mips/boot/vmlinux.gz.itb] 
> > Error 1
> > ...
> >
> > I bisected this down to your commit:
> >
> > 3f04db891a353f4b127ed57279279f851c6b4917 is the first bad commit
> > commit 3f04db891a353f4b127ed57279279f851c6b4917
> > Author: Simon Glass 
> > Date:   Mon Feb 15 17:08:12 2021 -0700
> >
> > image: Check for unit addresses in FITs
> >
> > Using unit addresses in a FIT is a security risk. Add a check for this
> > and disallow it.
> >
> > CVE-2021-27138
> >
> > Signed-off-by: Simon Glass 
> > Reported-by: Bruce Monroe 
> > Reported-by: Arie Haenel 
> > Reported-by: Julien Lenoir 
> >
> >  common/image-fit.c  | 56 
> > +
> >  test/py/tests/test_vboot.py |  9 
> >  2 files changed, 57 insertions(+), 8 deletions(-)
> > bisect run success
> >
> > $ git bisect log
> > # bad: [e9c99db7787e3b5c2ef05701177c43ed1c023c27] Merge branch 
> > '2021-04-07-CI-improvements'
> > # good: [c4fddedc48f336eabc4ce3f74940e6aa372de18c] Prepare v2021.01
> > git bisect start 'e9c99db7787e3b5c2ef05701177c43ed1c023c27' 'v2021.01'
> > # good: [b2c86f596cfb1ea9f7f5138f72f1c5c49e3ae3f1] arm: dts: r8a774a1: 
> > Import DTS queued for Linux 5.12-rc1
> > git bisect good b2c86f596cfb1ea9f7f5138f72f1c5c49e3ae3f1
> > # bad: [74f4929c2c73beb595faf7d5d9bb6a78d710c2fd] ddr: marvell: axp: fix 
> > array types have different bounds warning
> > git bisect bad 74f4929c2c73beb595faf7d5d9bb6a78d710c2fd
> > # bad: [cbe607b920bc0827d8fe379ed4f5ae4e2058513e] Merge tag 
> > 'xilinx-for-v2021.04-rc3' of 
> > https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
> > git bisect bad cbe607b920bc0827d8fe379ed4f5ae4e2058513e
> > # good: [d5f3aadacbc63df3b690d6fd9f0aa3f575b43356] test: Add tests for the 
> > 'evil' vboot attacks
> > git bisect good d5f3aadacbc63df3b690d6fd9f0aa3f575b43356
> > # bad: [a1a652e8016426e2d67148cab225cd5ec45189fb] Merge tag 'mmc-2021-2-19' 
> > of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
> > git bisect bad a1a652e8016426e2d67148cab225cd5ec45189fb
> > # bad: [aeedeae40733131467de72c68e639cf9d795e059] spl: fit: Replace #ifdef 
> > blocks with more readable constructs
> > git bisect bad aeedeae40733131467de72c68e639cf9d795e059
> > # bad: [eb5fd9e46c11ea41430d9c5bcc81d4583424216e] usb: kbd: destroy device 
> > after console is stopped
> > git bisect bad eb5fd9e46c11ea41430d9c5bcc81d4583424216e
> > # bad: [99cb2b996bd649d98069a95941beaaade0a4447a] stdio: Split out 
> > nulldev_register() and move it under #if
> > git bisect bad 99cb2b996bd649d98069a95941beaaade0a4447a
> > # bad: [3f04db891a353f4b127ed57279279f851c6b4917] image: Check for unit 
> > addresses in FITs
> > git bisect bad 3f04db891a353f4b127ed57279279f851c6b4917
> > # good: [6f3c2d8aa5e6cbd80b5e869bbbddecb66c329d01] image: Add an option to 
> > do a full check of the FIT
> > git bisect good 6f3c2d8aa5e6cbd80b5e869bbbddecb66c329d01
> > # good: [124c255731c76a2b09587378b2bcce561bcd3f2d] libfdt: Check for 
> > multiple/invalid root nodes
> > git bisect good 124c255731c76a2b09587378b2bcce561bcd3f2d
> > # first bad commit: [3f04db891a353f4b127ed57279279f851c6b4917] image: Check 
> > for unit addresses in FITs
> >
> > Is this an actual regression or is this now the expected behavior? I have 
> > added
> > Thomas and the linux-mips mailing list to take a look and see if the Linux
> > kernel needs to have its sources updated.
> 
> It is expected. See the code in that commit:
> 
>   /*
>* U-Boot stopped using unit addressed in 2017. Since libfdt
>* can match nodes ignoring any unit address, signature
>* verification can see the wrong node if one is inserted with
>* the same name as a valid node but with a unit address
>* attached. Protect against this by disallowing unit addresses.
>*/
>   if (!ret && CONFIG_IS_ENABLED(FIT_SIGNATURE)) {
>  ret = fdt_check_no_at(fit, 0);
> 
>  if (ret) {
> log_debug("FIT check error %d\n", ret);
> return ret;
>  }
>   }
> 
> Possibly you are using @ nodes in your FIT files in the kernel. Is it
> possible to use a hyphen instead?

Yeah, it looks like arch/mips/generic/*.its.S in the kernel will need to
be updated.

-- 
Tom


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Re: Pull request: u-boot-imx u-boot-imx-20210409

2021-04-09 Thread Tom Rini
On Fri, Apr 09, 2021 at 01:40:08PM +0200, Stefano Babic wrote:

> Hi Tom,
> 
> please pull from u-boot-imx, thanks !
> 
> The following changes since commit e9c99db7787e3b5c2ef05701177c43ed1c023c27:
> 
>   Merge branch '2021-04-07-CI-improvements' (2021-04-07 15:54:07 -0400)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
> tags/u-boot-imx-20210409
> 
> for you to fetch changes up to 2fc93e5bafdae7cf6373479e054e9f3943fde23c:
> 
>   imx: bootaux fix elf loading (2021-04-08 23:59:50 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core

2021-04-09 Thread Green Wan
Hi folks,

Correct me if I'm wrong, like Rick mentioned, i/dcache
enable/disable() is only called on the main hart. Right now the dummy
i/dcache enable/disable are empty and shared among all riscv CPU. The
ax25 is the only one that has its own implementation for now.

FU540/FU740 also leverages the dummy i/dcache enable/disable()
functions (only main hart calls them). L2 cache on FU540/FU740 is
enabled as SRAM purpose. And according to the HW design behavior, once
L2 is enabled, it can't be disabled unless doing a reset.[1] The Linux
L2$ driver will handle that according to the configuration of L2
registers.

[1] https://static.dev.sifive.com/FU540-C000-v1.0.pdf

Thanks,

On Fri, Apr 9, 2021 at 9:18 PM Sean Anderson  wrote:
>
> On 4/9/21 4:16 AM, Rick Chen wrote:
> > Hi Sean ,Bin
> >
> >> From: Bin Meng [mailto:bmeng...@gmail.com]
> >> Sent: Tuesday, April 06, 2021 5:16 PM
> >> To: Sean Anderson
> >> Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh Patel; Bin 
> >> Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad Kim; U-Boot 
> >> Mailing List
> >> Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init 
> >> each core
> >>
> >> On Sat, Apr 3, 2021 at 6:53 AM Sean Anderson  wrote:
> >>>
> >>> On 3/30/21 1:26 AM, Green Wan wrote:
>  Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
>  allow different riscv hart perform setup code for each hart as early
>  as possible. Since all the harts enter the callback, they must be able
>  to run the same setup.
> 
>  Signed-off-by: Green Wan 
>  ---
> arch/riscv/cpu/cpu.c   | 15 +++
> arch/riscv/cpu/start.S | 14 ++
> 2 files changed, 29 insertions(+)
> 
>  diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
>  index 85592f5bee..1652e51137 100644
>  --- a/arch/riscv/cpu/cpu.c
>  +++ b/arch/riscv/cpu/cpu.c
>  @@ -140,3 +140,18 @@ int arch_early_init_r(void)
> {
> return riscv_cpu_probe();
> }
>  +
>  +/**
>  + * riscv_hart_early_init() - A dummy function called by
>  + * ./arch/riscv/cpu/start.S to allow to disable/enable features of each 
>  core.
>  + * For example, turn on or off the functional block of CPU harts.
>  + *
>  + * In a multi-core system, this function must not access shared 
>  resources.
>  + *
>  + * Any access to such resources would probably be better done with
>  + * available_harts_lock held. However, I doubt that any such access 
>  will be
>  + * necessary.
>  + */
>  +__weak void riscv_hart_early_init(void)
>  +{
>  +}
>  diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
>  index 8589509e01..ab73008f23 100644
>  --- a/arch/riscv/cpu/start.S
>  +++ b/arch/riscv/cpu/start.S
>  @@ -117,6 +117,20 @@ call_board_init_f_0:
> mv  sp, a0
> #endif
> 
>  +#if CONFIG_IS_ENABLED(RISCV_MMODE)
>  + /*
>  +  * Jump to riscv_hart_early_init() to perform init for each core. 
>  Not
>  +  * expect to access gd since gd is not initialized. All operations 
>  in the
>  +  * function should affect core itself only. In multi-core system, 
>  any access
>  +  * to common resource or registers outside core should be avoided 
>  or need a
>  +  * protection for multicore.
>  +  *
>  +  * A dummy implementation is provided in ./arch/riscv/cpu/cpu.c.
>  +  */
>  +call_riscv_hart_early_init:
>  + jal riscv_hart_early_init
>  +#endif
>  +
> >>>
> >>> I wonder if we could move the calls to icache_enable and dcache_enable
> >>> into this function. Though this would have the consequence of enabling
> >>> caches on all harts for CPUs which previously only enabled them for the
> >>> boot hart. I think ax25 is the only CPU which currently does this. Bin,
> >>> would this be an issue?
> >
> > No, they are functions shall be called in different stage about lottery.
> > riscv_hart_early_init() is called before lottery for all harts.
> > It shall not move icache_enable() and dcache_enable() into
> > riscv_hart_early_init(), they are belong to the stage after lottery
> > only for main hart.
> >
> >>
> >> Good catch. I believe AX25 cache support is currently somehow broken?
> >
> > No, AX25 cache support is currently work well.
> >
> >>
> >> I think Rick has to comment on this as he added this via commit:
> >>
> >> commit 52923c6db7f00e0197ec894c8c1bb8a7681974bb
> >> Author: Rick Chen 
> >> Date:   Wed Nov 7 09:34:06 2018 +0800
> >>
> >>  riscv: cache: Implement i/dcache [status, enable, disable]
> >>
> >>  AndeStar RISC-V(V5) provide mcache_ctl register which
> >>  can configure I/D cache as enabled or disabled.
> >>
> >>  This CSR will be encapsulated by CONFIG_RISCV_NDS.
> >>  If you want to configure cache on AndeStar V5
> >>

[PATCH] board_f: cosmetic: change the debug trace to KB in reserve_video

2021-04-09 Thread Patrick Delaunay
Update the debug trace for the reserved video memory to KB as indicated
in the message with "%luk"; before the patch the computed size
gd->relocaddr - addr is in bytes.

This patch aligns the debug trace in reserve_video() with others
functions, for example on stm32mp157c-dk2:

  - Reserving 3080192k for video at: dfd0
  + Reserving 3008k for video at: dfd0
Reserving 873k for U-Boot at: dfc25000
Reserving 32776k for malloc() at: ddc23000
Reserving 72 Bytes for Board Info at: ddc22fb0
Reserving 280 Bytes for Global Data at: ddc22e90
Reserving 119072 Bytes for FDT at: ddc05d70
Reserving 0x278 Bytes for bootstage at: ddc05af0

Fixes: 5630d2fbc50f3035 ("board: Show memory for frame buffers")
Signed-off-by: Patrick Delaunay 
---

 common/board_f.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/board_f.c b/common/board_f.c
index 0cddf0359d..203e965799 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -394,7 +394,7 @@ static int reserve_video(void)
if (ret)
return ret;
debug("Reserving %luk for video at: %08lx\n",
- (unsigned long)gd->relocaddr - addr, addr);
+ ((unsigned long)gd->relocaddr - addr) >> 10, addr);
gd->relocaddr = addr;
 #elif defined(CONFIG_LCD)
 #  ifdef CONFIG_FB_ADDR
-- 
2.17.1



Re: [PATCH] powerpc, wdt: disable ratelimiting when disabling interrupts

2021-04-09 Thread Christophe Leroy




Le 09/04/2021 à 16:12, Rasmus Villemoes a écrit :

On powerpc, time as measured by get_timer() ceases to pass when
interrupts are disabled (since on powerpc get_timer() returns the
value of a volatile variable that gets updated via a timer
interrupt). That in turn means the watchdog_reset() function provided
by CONFIG_WDT ceases to work due to the ratelimiting it imposes.

Normally, interrupts are just disabled very briefly. However, during
bootm, they are disabled for good prior to decompressing the kernel
image, which can be a somewhat time-consuming operation. Even when we
manage to decompress the kernel and do the other preparation steps and
hand over control to the kernel, the kernel also takes some time
before it is ready to assume responsibility for handling the
watchdog. The end result is that the board gets reset prematurely.

The ratelimiting isn't really strictly needed (prior to DM WDT, no
such thing existed), so just disable it when we know that time no
longer passes and have watchdog_reset() (e.g. called from
decompression loop) unconditionally reset the watchdog timer.



Do we need to make it that complicated ? I think before the generic implementation, powerpc didn't 
have a rate limitation at all for pinging the watchdog, why not go back this direction, all the time ?


I mean we could simply set reset_period to 0 at all time for powerpc ( and change the test to 
time_after_eq() instead of time_after() ).





Signed-off-by: Rasmus Villemoes 
---

I previously sent a patch to change the ratelimiting to be based on
get_ticks() instead of get_timer(), but that has gone nowhere
[1]. This is an alternative which only affects powerpc (and only
boards that have enabled CONFIG_WDT). I hope the watchdog maintainers
will accept at least one of these, or suggest a third alternative, so
I don't have to keep some out-of-tree patch applied without knowing if
that's the direction upstream will take.

[1] 
https://patchwork.ozlabs.org/project/uboot/patch/20200605111657.28773-1-rasmus.villem...@prevas.dk/




Re: [PATCH v1 1/2] cmd: bind: Fix driver binding on a device

2021-04-09 Thread Patrice CHOTARD



On 4/9/21 3:41 PM, Andy Shevchenko wrote:
> On Fri, Apr 09, 2021 at 09:13:12AM -0400, Sean Anderson wrote:
>> On 4/9/21 8:05 AM, Patrice CHOTARD wrote:
>>> On 4/9/21 1:01 PM, Andy Shevchenko wrote:
 On Fri, Apr 9, 2021 at 1:32 PM Patrice CHOTARD
  wrote:
> On 4/9/21 11:48 AM, Andy Shevchenko wrote:
>> On Fri, Apr 9, 2021 at 12:28 PM Patrice CHOTARD
>>  wrote:
>>> On 4/9/21 11:16 AM, Andy Shevchenko wrote:
 On Fri, Apr 9, 2021 at 10:37 AM Patrice Chotard
  wrote:
> 
> ...
> 
> +   if (drv) {
> +   if (drv == entry)
> +   break;

> +   } else {
> +   if (!ret)
> +   break;
> +   }

 This can be simplified to
 } else if (!ret)
break;
>>>
>>> I know but checkpatch.pl requested it ;-)
>>
>> You mean it doesn't recognize 'else if' construction? Then it's a bug
>> there for sure.
>>
>
> No, i mean checkpath.pl request to put {} on all statements as shown 
> below :
>
> ./scripts/checkpatch.pl 0001-cmd-bind-Fix-driver-binding-on-a-device.patch
> CHECK: braces {} should be used on all arms of this statement
> #83: FILE: drivers/core/lists.c:228:
> +   if (drv) {
> [...]
> +   } else if (!ret)

 So, you still can put else and if on one line, right?

>>>
>>> No, if i put else and if on one line as you suggested, checkpatch.pl is 
>>> complaining as shown above.
>>>
>>> Patrice
>>>
>>
>> } else if (!ret) {
>>  break;
>> }
>>
>> ?
> 
> Thanks, that's fine for me. Does checkpatch.pl complain on this?
> 

This implementation is OK too, checkpatch is happy with it.



[PATCH 11/11] configs: T1042D4RDB: enable DM_ETH

2021-04-09 Thread Camelia Groza
From: Camelia Groza 

Enable DM_ETH and DM_MDIO for the T1042D4RDB.

Signed-off-by: Camelia Groza 
---
 configs/T1042D4RDB_NAND_defconfig| 3 +++
 configs/T1042D4RDB_SDCARD_defconfig  | 3 +++
 configs/T1042D4RDB_SECURE_BOOT_defconfig | 4 +++-
 configs/T1042D4RDB_SPIFLASH_defconfig| 3 +++
 configs/T1042D4RDB_defconfig | 3 +++
 5 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/configs/T1042D4RDB_NAND_defconfig 
b/configs/T1042D4RDB_NAND_defconfig
index bdfd0ef71b71..54bcc2f0821c 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -33,6 +33,7 @@ CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -66,6 +67,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig 
b/configs/T1042D4RDB_SDCARD_defconfig
index 9094327edeaa..853a3d65ae1c 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -31,6 +31,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -63,6 +64,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig 
b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index ef097bab8979..a59082c49a16 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -17,6 +17,7 @@ CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
@@ -45,8 +46,9 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig 
b/configs/T1042D4RDB_SPIFLASH_defconfig
index bc59866b551e..cef5295748a1 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -33,6 +33,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -65,6 +66,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index f968a448e927..85e2beab0200 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -18,6 +18,7 @@ CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -51,6 +52,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
-- 
2.17.1



[PATCH 10/11] powerpc: dts: t1042d4rdb: add FMan v3 nodes

2021-04-09 Thread Camelia Groza
From: Camelia Groza 

Add the FMan v3 nodes for the T1042D4RDB. The nodes are copied over with
little modification from the Linux kernel source code.

Signed-off-by: Camelia Groza 
---
 arch/powerpc/dts/t1042d4rdb.dts | 55 -
 1 file changed, 54 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts
index 3584c06aa8d6..5e9fab7a1057 100644
--- a/arch/powerpc/dts/t1042d4rdb.dts
+++ b/arch/powerpc/dts/t1042d4rdb.dts
@@ -3,7 +3,7 @@
  * T1042D4RDB Device Tree Source
  *
  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2021 NXP
  */
 
 /include/ "t104x.dtsi"
@@ -20,6 +20,57 @@
};
 };
 
+&soc {
+   fman0: fman@40 {
+   ethernet@e {
+   phy-handle = <&phy_sgmii_0>;
+   phy-connection-type = "sgmii";
+   };
+
+   ethernet@e2000 {
+   phy-handle = <&phy_sgmii_1>;
+   phy-connection-type = "sgmii";
+   };
+
+   ethernet@e4000 {
+   phy-handle = <&phy_sgmii_2>;
+   phy-connection-type = "sgmii";
+   };
+
+   ethernet@e6000 {
+   phy-handle = <&phy_rgmii_0>;
+   phy-connection-type = "rgmii";
+   };
+
+   ethernet@e8000 {
+   phy-handle = <&phy_rgmii_1>;
+   phy-connection-type = "rgmii";
+   };
+
+   mdio0: mdio@fc000 {
+   phy_sgmii_0: ethernet-phy@2 {
+   reg = <0x02>;
+   };
+
+   phy_sgmii_1: ethernet-phy@3 {
+   reg = <0x03>;
+   };
+
+   phy_sgmii_2: ethernet-phy@1 {
+   reg = <0x01>;
+   };
+
+   phy_rgmii_0: ethernet-phy@4 {
+   reg = <0x04>;
+   };
+
+   phy_rgmii_1: ethernet-phy@5 {
+   reg = <0x05>;
+   };
+   };
+   };
+};
+
 &espi0 {
status = "okay";
flash@0 {
@@ -30,3 +81,5 @@
spi-max-frequency = <1000>; /* input clock */
};
 };
+
+/include/ "t1042si-post.dtsi"
-- 
2.17.1



[PATCH 09/11] powerpc: dts: t1042: add QorIQ DPAA 1 FMan v3 nodes

2021-04-09 Thread Camelia Groza
From: Camelia Groza 

Add the QorIQ DPAA 1 FMan v3 device tree nodes for the T1042 SoC.
The device tree nodes are copied over with little modification
from the Linux kernel source code.

Signed-off-by: Camelia Groza 
---
 arch/powerpc/dts/t1042si-post.dtsi | 46 ++
 1 file changed, 46 insertions(+)
 create mode 100644 arch/powerpc/dts/t1042si-post.dtsi

diff --git a/arch/powerpc/dts/t1042si-post.dtsi 
b/arch/powerpc/dts/t1042si-post.dtsi
new file mode 100644
index ..5c60944e607b
--- /dev/null
+++ b/arch/powerpc/dts/t1042si-post.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * T1042 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 - 2014 Freescale Semiconductor Inc.
+ * Copyright 2021 NXP
+ *
+ */
+&soc {
+/include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-gpio-1.dtsi"
+/include/ "qoriq-gpio-2.dtsi"
+/include/ "qoriq-gpio-3.dtsi"
+
+/include/ "qoriq-fman3l-0.dtsi"
+/include/ "qoriq-fman3-0-1g-0.dtsi"
+/include/ "qoriq-fman3-0-1g-1.dtsi"
+/include/ "qoriq-fman3-0-1g-2.dtsi"
+/include/ "qoriq-fman3-0-1g-3.dtsi"
+/include/ "qoriq-fman3-0-1g-4.dtsi"
+   fman@40 {
+   enet0: ethernet@e {
+   };
+
+   enet1: ethernet@e2000 {
+   };
+
+   enet2: ethernet@e4000 {
+   };
+
+   enet3: ethernet@e6000 {
+   };
+
+   enet4: ethernet@e8000 {
+   };
+
+   mdio@fc000 {
+   interrupts = <100 1 0 0>;
+   };
+
+   mdio@fd000 {
+   status = "disabled";
+   };
+   };
+};
-- 
2.17.1



[PATCH 08/11] configs: T4240RDB: enable DM_ETH

2021-04-09 Thread Camelia Groza
From: Camelia Groza 

Enable DM_ETH and DM_MDIO for the T4240RDB.

Signed-off-by: Camelia Groza 
---
 configs/T4240RDB_SDCARD_defconfig | 3 +++
 configs/T4240RDB_defconfig| 3 +++
 2 files changed, 6 insertions(+)

diff --git a/configs/T4240RDB_SDCARD_defconfig 
b/configs/T4240RDB_SDCARD_defconfig
index 61670fa3d14d..2def90140f2e 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -28,6 +28,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -59,6 +60,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_CORTINA=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 2c8a2f0ef271..8a0c122833f5 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -15,6 +15,7 @@ CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -47,6 +48,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_CORTINA=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
-- 
2.17.1



[PATCH 06/11] powerpc: dts: t4240rdb: add FMan v3 nodes

2021-04-09 Thread Camelia Groza
From: Camelia Groza 

Add the FMan v3 nodes for the T4240RDB. The nodes are copied over with
little modification from the Linux kernel source code.

Signed-off-by: Camelia Groza 
---
 arch/powerpc/dts/t4240rdb.dts | 142 +-
 1 file changed, 141 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/dts/t4240rdb.dts b/arch/powerpc/dts/t4240rdb.dts
index 635065a03685..6d31675c5ead 100644
--- a/arch/powerpc/dts/t4240rdb.dts
+++ b/arch/powerpc/dts/t4240rdb.dts
@@ -3,7 +3,7 @@
  * T4240RDB Device Tree Source
  *
  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2021 NXP
  */
 
 /include/ "t4240.dtsi"
@@ -20,6 +20,144 @@
};
 };
 
+&soc {
+   fman@40 {
+   ethernet@e {
+   phy-handle = <&sgmiiphy21>;
+   phy-connection-type = "sgmii";
+   };
+
+   ethernet@e2000 {
+   phy-handle = <&sgmiiphy22>;
+   phy-connection-type = "sgmii";
+   };
+
+   ethernet@e4000 {
+   phy-handle = <&sgmiiphy23>;
+   phy-connection-type = "sgmii";
+   };
+
+   ethernet@e6000 {
+   phy-handle = <&sgmiiphy24>;
+   phy-connection-type = "sgmii";
+   };
+
+   ethernet@e8000 {
+   status = "disabled";
+   };
+
+   ethernet@ea000 {
+   status = "disabled";
+   };
+
+   ethernet@f {
+   phy-handle = <&xfiphy1>;
+   phy-connection-type = "xgmii";
+   };
+
+   ethernet@f2000 {
+   phy-handle = <&xfiphy2>;
+   phy-connection-type = "xgmii";
+   };
+   };
+
+   fman@50 {
+   ethernet@e {
+   phy-handle = <&sgmiiphy41>;
+   phy-connection-type = "sgmii";
+   };
+
+   ethernet@e2000 {
+   phy-handle = <&sgmiiphy42>;
+   phy-connection-type = "sgmii";
+   };
+
+   ethernet@e4000 {
+   phy-handle = <&sgmiiphy43>;
+   phy-connection-type = "sgmii";
+   };
+
+   ethernet@e6000 {
+   phy-handle = <&sgmiiphy44>;
+   phy-connection-type = "sgmii";
+   };
+
+   ethernet@e8000 {
+   status = "disabled";
+   };
+
+   ethernet@ea000 {
+   status = "disabled";
+   };
+
+   ethernet@f {
+   phy-handle = <&xfiphy3>;
+   phy-connection-type = "xgmii";
+   };
+
+   ethernet@f2000 {
+   phy-handle = <&xfiphy4>;
+   phy-connection-type = "xgmii";
+   };
+
+   mdio@fc000 {
+   sgmiiphy21: ethernet-phy@0 {
+   reg = <0x0>;
+   };
+
+   sgmiiphy22: ethernet-phy@1 {
+   reg = <0x1>;
+   };
+
+   sgmiiphy23: ethernet-phy@2 {
+   reg = <0x2>;
+   };
+
+   sgmiiphy24: ethernet-phy@3 {
+   reg = <0x3>;
+   };
+
+   sgmiiphy41: ethernet-phy@4 {
+   reg = <0x4>;
+   };
+
+   sgmiiphy42: ethernet-phy@5 {
+   reg = <0x5>;
+   };
+
+   sgmiiphy43: ethernet-phy@6 {
+   reg = <0x6>;
+   };
+
+   sgmiiphy44: ethernet-phy@7 {
+   reg = <0x7>;
+   };
+   };
+
+   mdio@fd000 {
+   xfiphy1: ethernet-phy@10 {
+   compatible = "ethernet-phy-id13e5.1002";
+   reg = <0x10>;
+   };
+
+   xfiphy2: ethernet-phy@11 {
+   compatible = "ethernet-phy-id13e5.1002";
+   reg = <0x11>;
+   };
+
+   xfiphy3: ethernet-phy@13 {
+   compatible = "ethernet-phy-id13e5.1002";
+   reg = <0x13>;
+   };
+
+   xfiphy4: ethernet-phy@12 {
+   compatible = "ethernet-phy-id13e5.1002";
+   reg = <0x12>;
+   };
+ 

[PATCH 07/11] powerpc: dts: qoriq: update the mdio offsets under the second FMan v3

2021-04-09 Thread Camelia Groza
From: Camelia Groza 

When two FMan's are present on a board, the MDIO nodes are found at the
same offsets inside each FMan. This causes "non unique device name"
errors when registering the MDIO nodes under the second FMan. Fix this
by updating the offsets of the MDIO nodes to include the parent FMan's
offset.

Signed-off-by: Camelia Groza 
---
 arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi | 2 +-
 arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi | 2 +-
 arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi  | 2 +-
 arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi  | 2 +-
 arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi  | 2 +-
 arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi  | 2 +-
 arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi  | 2 +-
 arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi  | 2 +-
 arch/powerpc/dts/qoriq-fman3-1.dtsi   | 4 ++--
 arch/powerpc/dts/t4240rdb.dts | 4 ++--
 arch/powerpc/dts/t4240si-post.dtsi| 4 ++--
 11 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi 
b/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi
index 889c8d450e09..65bb8a4b0b63 100644
--- a/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi
+++ b/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi
@@ -30,7 +30,7 @@ fman@50 {
pcsphy-handle = <&pcsphy14>;
};
 
-   mdio@f1000 {
+   mdio@5f1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
diff --git a/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi 
b/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi
index 2e456983372c..eb39d29b39fa 100644
--- a/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi
+++ b/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi
@@ -30,7 +30,7 @@ fman@50 {
pcsphy-handle = <&pcsphy15>;
};
 
-   mdio@f3000 {
+   mdio@5f3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi 
b/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi
index b4ff19bf495a..2f2209dbc9bb 100644
--- a/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi
+++ b/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi
@@ -29,7 +29,7 @@ fman@50 {
pcsphy-handle = <&pcsphy8>;
};
 
-   mdio@e1000 {
+   mdio@5e1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi 
b/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi
index 239c56ad1f62..11653c58b5f0 100644
--- a/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi
+++ b/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi
@@ -29,7 +29,7 @@ fman@50 {
pcsphy-handle = <&pcsphy9>;
};
 
-   mdio@e3000 {
+   mdio@5e3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi 
b/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi
index 6e2bb009d9aa..ae27c7bc6df2 100644
--- a/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi
+++ b/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi
@@ -29,7 +29,7 @@ fman@50 {
pcsphy-handle = <&pcsphy10>;
};
 
-   mdio@e5000 {
+   mdio@5e5000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi 
b/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi
index 29dd94ba7498..55ae5499176e 100644
--- a/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi
+++ b/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi
@@ -29,7 +29,7 @@ fman@50 {
pcsphy-handle = <&pcsphy11>;
};
 
-   mdio@e7000 {
+   mdio@5e7000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi 
b/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi
index a5b493582703..833cf3e23d8e 100644
--- a/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi
+++ b/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi
@@ -29,7 +29,7 @@ fman@50 {
pcsphy-handle = <&pcsphy12>;
};
 
-   mdio@e9000 {
+   mdio@5e9000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi 
b/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi
index 486c84bf9810..81da55dfbe26 100644
--- a/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi
+++ b/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi
@@ -29,7 +29,7 @@ fman@50 {
pcsphy-handle = <&pcsphy13>;
};
 
-   mdio@eb000 {
+   mdio@5eb000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-mem

[PATCH 05/11] powerpc: dts: t4240: add QorIQ DPAA 1 FMan v3 nodes

2021-04-09 Thread Camelia Groza
From: Camelia Groza 

Add the QorIQ DPAA 1 FMan v3 device tree nodes for the T4240 SoC.
The device tree nodes are copied over with little modification
from the Linux kernel source code.

Signed-off-by: Camelia Groza 
---
 arch/powerpc/dts/t4240si-post.dtsi | 101 +
 1 file changed, 101 insertions(+)
 create mode 100644 arch/powerpc/dts/t4240si-post.dtsi

diff --git a/arch/powerpc/dts/t4240si-post.dtsi 
b/arch/powerpc/dts/t4240si-post.dtsi
new file mode 100644
index ..f614d19965d3
--- /dev/null
+++ b/arch/powerpc/dts/t4240si-post.dtsi
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * T4240 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2021 NXP
+ *
+ */
+&soc {
+/include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-gpio-1.dtsi"
+/include/ "qoriq-gpio-2.dtsi"
+/include/ "qoriq-gpio-3.dtsi"
+
+/include/ "qoriq-fman3-0.dtsi"
+/include/ "qoriq-fman3-0-1g-0.dtsi"
+/include/ "qoriq-fman3-0-1g-1.dtsi"
+/include/ "qoriq-fman3-0-1g-2.dtsi"
+/include/ "qoriq-fman3-0-1g-3.dtsi"
+/include/ "qoriq-fman3-0-1g-4.dtsi"
+/include/ "qoriq-fman3-0-1g-5.dtsi"
+/include/ "qoriq-fman3-0-10g-0.dtsi"
+/include/ "qoriq-fman3-0-10g-1.dtsi"
+   fman@40 {
+   enet0: ethernet@e {
+   };
+
+   enet1: ethernet@e2000 {
+   };
+
+   enet2: ethernet@e4000 {
+   };
+
+   enet3: ethernet@e6000 {
+   };
+
+   enet4: ethernet@e8000 {
+   };
+
+   enet5: ethernet@ea000 {
+   };
+
+   enet6: ethernet@f {
+   };
+
+   enet7: ethernet@f2000 {
+   };
+
+   mdio@fc000 {
+   status = "disabled";
+   };
+
+   mdio@fd000 {
+   status = "disabled";
+   };
+   };
+
+/include/ "qoriq-fman3-1.dtsi"
+/include/ "qoriq-fman3-1-1g-0.dtsi"
+/include/ "qoriq-fman3-1-1g-1.dtsi"
+/include/ "qoriq-fman3-1-1g-2.dtsi"
+/include/ "qoriq-fman3-1-1g-3.dtsi"
+/include/ "qoriq-fman3-1-1g-4.dtsi"
+/include/ "qoriq-fman3-1-1g-5.dtsi"
+/include/ "qoriq-fman3-1-10g-0.dtsi"
+/include/ "qoriq-fman3-1-10g-1.dtsi"
+   fman@50 {
+   enet8: ethernet@e {
+   };
+
+   enet9: ethernet@e2000 {
+   };
+
+   enet10: ethernet@e4000 {
+   };
+
+   enet11: ethernet@e6000 {
+   };
+
+   enet12: ethernet@e8000 {
+   };
+
+   enet13: ethernet@ea000 {
+   };
+
+   enet14: ethernet@f {
+   };
+
+   enet15: ethernet@f2000 {
+   };
+
+   mdio@fc000 {
+   interrupts = <100 1 0 0>;
+   };
+
+   mdio@fd000 {
+   interrupts = <101 1 0 0>;
+   };
+   };
+};
-- 
2.17.1



[PATCH 04/11] configs: T2080RDB: enable DM_ETH

2021-04-09 Thread Camelia Groza
From: Camelia Groza 

Enable DM_ETH and DM_MDIO for the T2080RDB.

Signed-off-by: Camelia Groza 
---
 configs/T2080RDB_NAND_defconfig | 3 +++
 configs/T2080RDB_SDCARD_defconfig   | 3 +++
 configs/T2080RDB_SPIFLASH_defconfig | 3 +++
 configs/T2080RDB_defconfig  | 3 +++
 4 files changed, 12 insertions(+)

diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 543d34e24988..3bb74335bb47 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -33,6 +33,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -70,6 +71,8 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_NAND=y
 CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080RDB_SDCARD_defconfig 
b/configs/T2080RDB_SDCARD_defconfig
index d947846e6458..bcd67a05764e 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -31,6 +31,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -67,6 +68,8 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_MMC=y
 CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig 
b/configs/T2080RDB_SPIFLASH_defconfig
index 6f7b083bc623..198e926c32f6 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -33,6 +33,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -69,6 +70,8 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
 CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 9dd01bbe50a5..12aaccd1d509 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -18,6 +18,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -54,6 +55,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
-- 
2.17.1



[PATCH 03/11] board: freescale: t208xrdb: fdt fixups under DM_ETH

2021-04-09 Thread Camelia Groza
From: Camelia Groza 

Disable the FMan mEMAC 5 and 6 nodes from the fdt since they are not
available under the supported RCW. Also disable the associated
"fsl,dpa-ethernet" nodes that reference them.

This is a simplified version of the fdt_fixup_fman_ethernet call for
use under DM_ETH.

Signed-off-by: Camelia Groza 
---
 board/freescale/t208xrdb/eth_t208xrdb.c | 35 +
 board/freescale/t208xrdb/t208xrdb.c |  3 +++
 board/freescale/t208xrdb/t208xrdb.h |  2 ++
 3 files changed, 40 insertions(+)

diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c 
b/board/freescale/t208xrdb/eth_t208xrdb.c
index e77f3f7146f7..b0ff4b1f375a 100644
--- a/board/freescale/t208xrdb/eth_t208xrdb.c
+++ b/board/freescale/t208xrdb/eth_t208xrdb.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  *
  * Shengzhou Liu 
  */
@@ -104,6 +105,40 @@ int board_eth_init(struct bd_info *bis)
return pci_eth_init(bis);
 }
 
+/* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two
+ * "fsl,dpa-ethernet" nodes that reference them.
+ */
+void fdt_fixup_board_fman_ethernet(void *fdt)
+{
+   int mac_off, eth_off, i;
+   char mac_path[2][42] = {
+   "/soc@ffe00/fman@40/ethernet@e8000",
+   "/soc@ffe00/fman@40/ethernet@ea000",
+   };
+   u32 eth_ph;
+
+   for (i = 0; i < 2; i++) {
+   /* Disable the MAC node */
+   mac_off = fdt_path_offset(fdt, mac_path[i]);
+   if (mac_off < 0)
+   continue;
+   fdt_status_disabled(fdt, mac_off);
+
+   /* Disable the fsl,dpa-ethernet node that points to the MAC.
+* The fsl,fman-mac property refers to the MAC's phandle.
+*/
+   eth_ph = fdt_get_phandle(fdt, mac_off);
+   if (eth_ph <= 0)
+   continue;
+
+   eth_off = fdt_node_offset_by_prop_value(fdt, -1, "fsl,fman-mac",
+   ð_ph,
+   sizeof(eth_ph));
+   if (eth_off >= 0)
+   fdt_status_disabled(fdt, eth_off);
+   }
+}
+
 void fdt_fixup_board_enet(void *fdt)
 {
return;
diff --git a/board/freescale/t208xrdb/t208xrdb.c 
b/board/freescale/t208xrdb/t208xrdb.c
index a18459841c62..7ccb205c6473 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include 
@@ -137,6 +138,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 #ifdef CONFIG_SYS_DPAA_FMAN
 #ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
+#else
+   fdt_fixup_board_fman_ethernet(blob);
 #endif
fdt_fixup_board_enet(blob);
 #endif
diff --git a/board/freescale/t208xrdb/t208xrdb.h 
b/board/freescale/t208xrdb/t208xrdb.h
index 22a496fb8cf2..cd0a9f44da79 100644
--- a/board/freescale/t208xrdb/t208xrdb.h
+++ b/board/freescale/t208xrdb/t208xrdb.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #ifndef __CORENET_DS_H__
@@ -8,5 +9,6 @@
 
 void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, struct bd_info *bd);
+void fdt_fixup_board_fman_ethernet(void *blob);
 
 #endif
-- 
2.17.1



[PATCH 02/11] powerpc: dts: t2080rdb: add FMan v3 nodes

2021-04-09 Thread Camelia Groza
From: Camelia Groza 

Add the FMan v3 nodes for the T2080RDB. The nodes are copied over with
little modification from the Linux kernel source code.

Signed-off-by: Camelia Groza 
---
 arch/powerpc/dts/t2080rdb.dts | 69 ++-
 1 file changed, 68 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts
index 74bbb20e2a1e..25f8c978c6d1 100644
--- a/arch/powerpc/dts/t2080rdb.dts
+++ b/arch/powerpc/dts/t2080rdb.dts
@@ -3,7 +3,7 @@
  * T2080RDB Device Tree Source
  *
  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2021 NXP
  */
 
 /include/ "t2080.dtsi"
@@ -20,6 +20,71 @@
};
 };
 
+&soc {
+   fman@40 {
+   ethernet@e {
+   phy-handle = <&xg_aq1202_phy3>;
+   phy-connection-type = "xgmii";
+   };
+
+   ethernet@e2000 {
+   phy-handle = <&xg_aq1202_phy4>;
+   phy-connection-type = "xgmii";
+   };
+
+   ethernet@e4000 {
+   phy-handle = <&rgmii_phy1>;
+   phy-connection-type = "rgmii";
+   };
+
+   ethernet@e6000 {
+   phy-handle = <&rgmii_phy2>;
+   phy-connection-type = "rgmii";
+   };
+
+   ethernet@f {
+   phy-handle = <&xg_cs4315_phy2>;
+   phy-connection-type = "xgmii";
+   };
+
+   ethernet@f2000 {
+   phy-handle = <&xg_cs4315_phy1>;
+   phy-connection-type = "xgmii";
+   };
+
+   mdio@fc000 {
+   rgmii_phy1: ethernet-phy@1 {
+   reg = <0x1>;
+   };
+   rgmii_phy2: ethernet-phy@2 {
+   reg = <0x2>;
+   };
+   };
+
+   mdio@fd000 {
+   xg_cs4315_phy1: ethernet-phy@c {
+   compatible = "ethernet-phy-id13e5.1002";
+   reg = <0xc>;
+   };
+
+   xg_cs4315_phy2: ethernet-phy@d {
+   compatible = "ethernet-phy-id13e5.1002";
+   reg = <0xd>;
+   };
+
+   xg_aq1202_phy3: ethernet-phy@0 {
+   compatible = "ethernet-phy-ieee802.3-c45";
+   reg = <0x0>;
+   };
+
+   xg_aq1202_phy4: ethernet-phy@1 {
+   compatible = "ethernet-phy-ieee802.3-c45";
+   reg = <0x1>;
+   };
+   };
+   };
+};
+
 &espi0 {
status = "okay";
flash@0 {
@@ -38,3 +103,5 @@
reg = <0x68>;
};
 };
+
+/include/ "t2080si-post.dtsi"
-- 
2.17.1



[PATCH 01/11] powerpc: dts: t2080: add QorIQ DPAA 1 FMan v3 nodes

2021-04-09 Thread Camelia Groza
From: Camelia Groza 

Add the QorIQ DPAA 1 FMan v3 device tree nodes for the T2080 SoC.
The device tree nodes are copied over with little modification from
the Linux kernel source code.

Signed-off-by: Camelia Groza 
---
 arch/powerpc/dts/t2080si-post.dtsi | 51 ++
 1 file changed, 51 insertions(+)
 create mode 100644 arch/powerpc/dts/t2080si-post.dtsi

diff --git a/arch/powerpc/dts/t2080si-post.dtsi 
b/arch/powerpc/dts/t2080si-post.dtsi
new file mode 100644
index ..d8ef579cb7c0
--- /dev/null
+++ b/arch/powerpc/dts/t2080si-post.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * T2080 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2021 NXP
+ *
+ */
+&soc {
+
+/include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-gpio-1.dtsi"
+/include/ "qoriq-gpio-2.dtsi"
+/include/ "qoriq-gpio-3.dtsi"
+
+/include/ "qoriq-fman3-0.dtsi"
+/include/ "qoriq-fman3-0-10g-0-best-effort.dtsi"
+/include/ "qoriq-fman3-0-10g-1-best-effort.dtsi"
+/include/ "qoriq-fman3-0-1g-2.dtsi"
+/include/ "qoriq-fman3-0-1g-3.dtsi"
+/include/ "qoriq-fman3-0-10g-0.dtsi"
+/include/ "qoriq-fman3-0-10g-1.dtsi"
+   fman@40 {
+   enet0: ethernet@e {
+   };
+
+   enet1: ethernet@e2000 {
+   };
+
+   enet2: ethernet@e4000 {
+   };
+
+   enet3: ethernet@e6000 {
+   };
+
+   enet6: ethernet@f {
+   };
+
+   enet7: ethernet@f2000 {
+   };
+
+   mdio@fc000 {
+   interrupts = <100 1 0 0>;
+   };
+
+   mdio@fd000 {
+   interrupts = <101 1 0 0>;
+   };
+   };
+};
-- 
2.17.1



[PATCH 00/11] Enable DM_ETH for DPAA1 PowerPC T-series boards

2021-04-09 Thread Camelia Groza
Apologies to those who received this series twice off list due to an
e-mail misconfiguration.

This patch series enables DM_ETH and DM_MDIO on the T2080RDB, T4240RDB and
T1042D4RDB DPAA1 PowerPC boards. The necessary FMan v3 Ethernet and MDIO
nodes are added to each platform's SoC and board device tree.

On T2080RDB, fdt fixups are performed before booting into the OS using a
simplified new routine in order to avoid the legacy code path.

Camelia Groza (11):
  powerpc: dts: t2080: add QorIQ DPAA 1 FMan v3 nodes
  powerpc: dts: t2080rdb: add FMan v3 nodes
  board: freescale: t208xrdb: fdt fixups under DM_ETH
  configs: T2080RDB: enable DM_ETH
  powerpc: dts: t4240: add QorIQ DPAA 1 FMan v3 nodes
  powerpc: dts: t4240rdb: add FMan v3 nodes
  powerpc: dts: qoriq: update the mdio offsets under the second FMan v3
  configs: T4240RDB: enable DM_ETH
  powerpc: dts: t1042: add QorIQ DPAA 1 FMan v3 nodes
  powerpc: dts: t1042d4rdb: add FMan v3 nodes
  configs: T1042D4RDB: enable DM_ETH

 arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi |   2 +-
 arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi |   2 +-
 arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi  |   2 +-
 arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi  |   2 +-
 arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi  |   2 +-
 arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi  |   2 +-
 arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi  |   2 +-
 arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi  |   2 +-
 arch/powerpc/dts/qoriq-fman3-1.dtsi   |   4 +-
 arch/powerpc/dts/t1042d4rdb.dts   |  55 -
 arch/powerpc/dts/t1042si-post.dtsi|  46 +++
 arch/powerpc/dts/t2080rdb.dts |  69 ++-
 arch/powerpc/dts/t2080si-post.dtsi|  51 
 arch/powerpc/dts/t4240rdb.dts | 142 +-
 arch/powerpc/dts/t4240si-post.dtsi| 101 +++
 board/freescale/t208xrdb/eth_t208xrdb.c   |  35 ++
 board/freescale/t208xrdb/t208xrdb.c   |   3 +
 board/freescale/t208xrdb/t208xrdb.h   |   2 +
 configs/T1042D4RDB_NAND_defconfig |   3 +
 configs/T1042D4RDB_SDCARD_defconfig   |   3 +
 configs/T1042D4RDB_SECURE_BOOT_defconfig  |   4 +-
 configs/T1042D4RDB_SPIFLASH_defconfig |   3 +
 configs/T1042D4RDB_defconfig  |   3 +
 configs/T2080RDB_NAND_defconfig   |   3 +
 configs/T2080RDB_SDCARD_defconfig |   3 +
 configs/T2080RDB_SPIFLASH_defconfig   |   3 +
 configs/T2080RDB_defconfig|   3 +
 configs/T4240RDB_SDCARD_defconfig |   3 +
 configs/T4240RDB_defconfig|   3 +
 29 files changed, 544 insertions(+), 14 deletions(-)
 create mode 100644 arch/powerpc/dts/t1042si-post.dtsi
 create mode 100644 arch/powerpc/dts/t2080si-post.dtsi
 create mode 100644 arch/powerpc/dts/t4240si-post.dtsi

--
2.17.1



[PATCH] powerpc, wdt: disable ratelimiting when disabling interrupts

2021-04-09 Thread Rasmus Villemoes
On powerpc, time as measured by get_timer() ceases to pass when
interrupts are disabled (since on powerpc get_timer() returns the
value of a volatile variable that gets updated via a timer
interrupt). That in turn means the watchdog_reset() function provided
by CONFIG_WDT ceases to work due to the ratelimiting it imposes.

Normally, interrupts are just disabled very briefly. However, during
bootm, they are disabled for good prior to decompressing the kernel
image, which can be a somewhat time-consuming operation. Even when we
manage to decompress the kernel and do the other preparation steps and
hand over control to the kernel, the kernel also takes some time
before it is ready to assume responsibility for handling the
watchdog. The end result is that the board gets reset prematurely.

The ratelimiting isn't really strictly needed (prior to DM WDT, no
such thing existed), so just disable it when we know that time no
longer passes and have watchdog_reset() (e.g. called from
decompression loop) unconditionally reset the watchdog timer.

Signed-off-by: Rasmus Villemoes 
---

I previously sent a patch to change the ratelimiting to be based on
get_ticks() instead of get_timer(), but that has gone nowhere
[1]. This is an alternative which only affects powerpc (and only
boards that have enabled CONFIG_WDT). I hope the watchdog maintainers
will accept at least one of these, or suggest a third alternative, so
I don't have to keep some out-of-tree patch applied without knowing if
that's the direction upstream will take.

[1] 
https://patchwork.ozlabs.org/project/uboot/patch/20200605111657.28773-1-rasmus.villem...@prevas.dk/



 arch/powerpc/lib/interrupts.c | 3 +++
 drivers/watchdog/wdt-uclass.c | 8 +++-
 include/wdt.h | 6 ++
 3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/lib/interrupts.c b/arch/powerpc/lib/interrupts.c
index 73f270002c..5c5b5fd7ff 100644
--- a/arch/powerpc/lib/interrupts.c
+++ b/arch/powerpc/lib/interrupts.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #ifdef CONFIG_LED_STATUS
 #include 
 #endif
@@ -43,6 +44,7 @@ static __inline__ void set_dec (unsigned long val)
 void enable_interrupts(void)
 {
set_msr (get_msr () | MSR_EE);
+   watchdog_ratelimit(1);
 }
 
 /* returns flag if MSR_EE was set before */
@@ -50,6 +52,7 @@ int disable_interrupts(void)
 {
ulong msr = get_msr ();
 
+   watchdog_ratelimit(0);
set_msr (msr & ~MSR_EE);
return ((msr & MSR_EE) != 0);
 }
diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
index 0603ffbd36..b70a9d50b8 100644
--- a/drivers/watchdog/wdt-uclass.c
+++ b/drivers/watchdog/wdt-uclass.c
@@ -131,6 +131,12 @@ int wdt_expire_now(struct udevice *dev, ulong flags)
return ret;
 }
 
+static int ratelimit = 1;
+void watchdog_ratelimit(int on)
+{
+   ratelimit = on;
+}
+
 #if defined(CONFIG_WATCHDOG)
 /*
  * Called by macro WATCHDOG_RESET. This function be called *very* early,
@@ -148,7 +154,7 @@ void watchdog_reset(void)
 
/* Do not reset the watchdog too often */
now = get_timer(0);
-   if (time_after(now, next_reset)) {
+   if (!ratelimit || time_after(now, next_reset)) {
next_reset = now + reset_period;
wdt_reset(gd->watchdog_dev);
}
diff --git a/include/wdt.h b/include/wdt.h
index bc242c2eb2..9ba1e62dcf 100644
--- a/include/wdt.h
+++ b/include/wdt.h
@@ -107,4 +107,10 @@ struct wdt_ops {
 
 int initr_watchdog(void);
 
+#if CONFIG_IS_ENABLED(WDT)
+void watchdog_ratelimit(int on);
+#else
+static inline void watchdog_ratelimit(int on) { }
+#endif
+
 #endif  /* _WDT_H_ */
-- 
2.29.2



[PULL] Pull request for u-boot master / v2021.07 = u-boot-stm32-20210409

2021-04-09 Thread Patrice CHOTARD
Hi Tom

Please pull the STM32 related patches for u-boot/master, v2021.07: 
u-boot-stm32-20210409

CI status: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/7103

Thanks,
Patrice

The following changes since commit b46dd116ce03e235f2a7d4843c6278e1da44b5e1:

  Prepare v2021.04 (2021-04-05 11:03:29 -0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-stm.git 
tags/u-boot-stm32-20210409

for you to fetch changes up to 2c2d7d6a72ba4a4f9323f24b8caa3b1e05546d83:

  arm: stm32mp1: Set soc_type, soc_pkg, soc_rev env variables (2021-04-09 
14:45:25 +0200)


Add rt-thread art-pi board support based on STM32H750 SoC
Add Engicam i.Core STM32MP1 SoM
Add FIP header support for STM32programmer
Update uart number when no serial device found for STM32MP1
Remove board_check_usb_power function when ADC flag is not set
Update SPL size limitation for STM32MP1
Set soc_type, soc_pkg, soc_rev env variables for STM32MP1


Alexandru Gagniuc (3):
  configs: stm32mp1: stm32mp1: Increase SPL malloc() size
  configs: stm32mp1: Remove misleading CONFIG_SPL_BSS_START_ADDR
  configs: stm32mp1: Fix misleading SPL size limitations

Jagan Teki (8):
  ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM
  ARM: dts: stm32: Add Engicam i.Core STM32MP1 1X4Gb DDR3
  ARM: stm32: Imply SPL_SPI_LOAD
  board: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
  board: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0
  ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 Micro SoM
  board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board
  board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

Marek Vasut (1):
  arm: stm32mp1: Set soc_type, soc_pkg, soc_rev env variables

Patrick Delaunay (4):
  stm32mp: stm32prog: add FIP header support
  stm32mp: update uart number in trace of serial device not found
  stm32mp: replace printf by log macro in setup_boot_mode
  stm32mp1: remove the board_check_usb_power function when ADC is not 
activated

dillon min (7):
  ARM: dts: stm32: split sdram pin & timing parameter into specific board 
dts
  ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750
  ARM: dts: stm32: add new instances for stm32h743 MCU
  ARM: dts: stm32: fix i2c node typo in stm32h743, update dmamux1 register
  ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6
  ram: stm32: fix strsep failed on read only memory
  board: Add rt-thread art-pi board support

 arch/arm/dts/Makefile  |   7 +-
 arch/arm/dts/stm32h7-pinctrl.dtsi  | 274 ++
 arch/arm/dts/stm32h7-u-boot.dtsi   | 100 +--
 arch/arm/dts/stm32h743-pinctrl.dtsi| 306 -
 arch/arm/dts/stm32h743.dtsi| 178 +++-
 arch/arm/dts/stm32h743i-disco-u-boot.dtsi  |  98 +++
 arch/arm/dts/stm32h743i-disco.dts  |   2 +-
 arch/arm/dts/stm32h743i-eval-u-boot.dtsi   |  98 +++
 arch/arm/dts/stm32h743i-eval.dts   |   2 +-
 arch/arm/dts/stm32h750.dtsi|   5 +
 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi |  81 ++
 arch/arm/dts/stm32h750i-art-pi.dts | 188 +
 .../dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi  | 119 
 .../stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi |  51 
 .../arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts |  47 
 ...stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi |  51 
 .../dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts|  47 
 .../arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi | 146 ++
 arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi   | 196 +
 ...a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi |  51 
 ...m32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 154 +++
 ...p157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi |  51 
 .../stm32mp157a-microgea-stm32mp1-microdev2.0.dts  |  55 
 .../dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi  | 118 
 arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi| 148 ++
 arch/arm/mach-stm32/stm32h7/Kconfig|   4 +
 arch/arm/mach-stm32mp/Kconfig  |  56 +++-
 .../arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c |  19 +-
 arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c|  59 ++--
 arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h|  12 +-
 .../mach-stm32mp/cmd_stm32prog/stm32prog_serial.c  |  11 +-
 arch/arm/mach-stm32mp/cpu.c| 115 
 board/engicam/stm32mp1/Kconfig |  12 +
 board/engicam/stm32mp1/MAINTAINERS |  26 ++
 board/engicam/stm32mp1/Makefile|  10 +
 board/engicam/stm32

Re: [PATCH v1 1/2] cmd: bind: Fix driver binding on a device

2021-04-09 Thread Andy Shevchenko
On Fri, Apr 09, 2021 at 09:13:12AM -0400, Sean Anderson wrote:
> On 4/9/21 8:05 AM, Patrice CHOTARD wrote:
> > On 4/9/21 1:01 PM, Andy Shevchenko wrote:
> > > On Fri, Apr 9, 2021 at 1:32 PM Patrice CHOTARD
> > >  wrote:
> > > > On 4/9/21 11:48 AM, Andy Shevchenko wrote:
> > > > > On Fri, Apr 9, 2021 at 12:28 PM Patrice CHOTARD
> > > > >  wrote:
> > > > > > On 4/9/21 11:16 AM, Andy Shevchenko wrote:
> > > > > > > On Fri, Apr 9, 2021 at 10:37 AM Patrice Chotard
> > > > > > >  wrote:

...

> > > > > > > > +   if (drv) {
> > > > > > > > +   if (drv == entry)
> > > > > > > > +   break;
> > > > > > > 
> > > > > > > > +   } else {
> > > > > > > > +   if (!ret)
> > > > > > > > +   break;
> > > > > > > > +   }
> > > > > > > 
> > > > > > > This can be simplified to
> > > > > > > } else if (!ret)
> > > > > > >break;
> > > > > > 
> > > > > > I know but checkpatch.pl requested it ;-)
> > > > > 
> > > > > You mean it doesn't recognize 'else if' construction? Then it's a bug
> > > > > there for sure.
> > > > > 
> > > > 
> > > > No, i mean checkpath.pl request to put {} on all statements as shown 
> > > > below :
> > > > 
> > > > ./scripts/checkpatch.pl 
> > > > 0001-cmd-bind-Fix-driver-binding-on-a-device.patch
> > > > CHECK: braces {} should be used on all arms of this statement
> > > > #83: FILE: drivers/core/lists.c:228:
> > > > +   if (drv) {
> > > > [...]
> > > > +   } else if (!ret)
> > > 
> > > So, you still can put else and if on one line, right?
> > > 
> > 
> > No, if i put else and if on one line as you suggested, checkpatch.pl is 
> > complaining as shown above.
> > 
> > Patrice
> > 
> 
> } else if (!ret) {
>   break;
> }
> 
> ?

Thanks, that's fine for me. Does checkpatch.pl complain on this?

-- 
With Best Regards,
Andy Shevchenko




Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core

2021-04-09 Thread Sean Anderson

On 4/9/21 4:16 AM, Rick Chen wrote:

Hi Sean ,Bin


From: Bin Meng [mailto:bmeng...@gmail.com]
Sent: Tuesday, April 06, 2021 5:16 PM
To: Sean Anderson
Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh Patel; Bin 
Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad Kim; U-Boot Mailing 
List
Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core

On Sat, Apr 3, 2021 at 6:53 AM Sean Anderson  wrote:


On 3/30/21 1:26 AM, Green Wan wrote:

Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
allow different riscv hart perform setup code for each hart as early
as possible. Since all the harts enter the callback, they must be able
to run the same setup.

Signed-off-by: Green Wan 
---
   arch/riscv/cpu/cpu.c   | 15 +++
   arch/riscv/cpu/start.S | 14 ++
   2 files changed, 29 insertions(+)

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 85592f5bee..1652e51137 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -140,3 +140,18 @@ int arch_early_init_r(void)
   {
   return riscv_cpu_probe();
   }
+
+/**
+ * riscv_hart_early_init() - A dummy function called by
+ * ./arch/riscv/cpu/start.S to allow to disable/enable features of each core.
+ * For example, turn on or off the functional block of CPU harts.
+ *
+ * In a multi-core system, this function must not access shared resources.
+ *
+ * Any access to such resources would probably be better done with
+ * available_harts_lock held. However, I doubt that any such access will be
+ * necessary.
+ */
+__weak void riscv_hart_early_init(void)
+{
+}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 8589509e01..ab73008f23 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -117,6 +117,20 @@ call_board_init_f_0:
   mv  sp, a0
   #endif

+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+ /*
+  * Jump to riscv_hart_early_init() to perform init for each core. Not
+  * expect to access gd since gd is not initialized. All operations in the
+  * function should affect core itself only. In multi-core system, any 
access
+  * to common resource or registers outside core should be avoided or need 
a
+  * protection for multicore.
+  *
+  * A dummy implementation is provided in ./arch/riscv/cpu/cpu.c.
+  */
+call_riscv_hart_early_init:
+ jal riscv_hart_early_init
+#endif
+


I wonder if we could move the calls to icache_enable and dcache_enable
into this function. Though this would have the consequence of enabling
caches on all harts for CPUs which previously only enabled them for the
boot hart. I think ax25 is the only CPU which currently does this. Bin,
would this be an issue?


No, they are functions shall be called in different stage about lottery.
riscv_hart_early_init() is called before lottery for all harts.
It shall not move icache_enable() and dcache_enable() into
riscv_hart_early_init(), they are belong to the stage after lottery
only for main hart.



Good catch. I believe AX25 cache support is currently somehow broken?


No, AX25 cache support is currently work well.



I think Rick has to comment on this as he added this via commit:

commit 52923c6db7f00e0197ec894c8c1bb8a7681974bb
Author: Rick Chen 
Date:   Wed Nov 7 09:34:06 2018 +0800

 riscv: cache: Implement i/dcache [status, enable, disable]

 AndeStar RISC-V(V5) provide mcache_ctl register which
 can configure I/D cache as enabled or disabled.

 This CSR will be encapsulated by CONFIG_RISCV_NDS.
 If you want to configure cache on AndeStar V5
 AE350 platform. YOu can enable [*] AndeStar V5 ISA support
 by make menuconfig.

 This approach also provide the expansion when the
 vender specific features are going to join in.

 Signed-off-by: Rick Chen 
 Cc: Greentime Hu 

The original commit has i/d cache enabled on all harts. But it was
later moved to boot hart due to SMP support.


Not all harts will enable i/d cache during startup currently, only
main hart will enable i/d cache here.
So only main hart will disable i/d cache in cleanup_before_linux().


Ok, so we have ax25 where cache is disabled on all harts before Linux,
and fu740 where cache will be enabled on all harts. Is there any
guidance from Linux on what should be happening here?

--Sean


Thanks,
Rick



However on the cleanup side, it looks only the boot hart calls i/d
cache disable?




See arch/riscv/cpu/ax25/cpu.c:: cleanup_before_linux()

Regards,
Bin





Re: [PATCH 2/2] configs: rpi: Enable SMBIOS sysinfo driver

2021-04-09 Thread Fabian Vogt
Am Freitag, 9. April 2021, 14:35:11 CEST schrieb matthias@kernel.org:
> From: Matthias Brugger 
> 
> Enalbe this driver to allow U-Boot to get SMBIOS table information from
 ^ typo

Other than that,
Acked-by: Fabian Vogt 

Cheers,
Fabian

> a device tree node.
> 
> Signed-off-by: Matthias Brugger 
> 
> ---
> 
>  configs/rpi_0_w_defconfig  | 2 ++
>  configs/rpi_2_defconfig| 2 ++
>  configs/rpi_3_32b_defconfig| 2 ++
>  configs/rpi_3_b_plus_defconfig | 2 ++
>  configs/rpi_3_defconfig| 2 ++
>  configs/rpi_4_32b_defconfig| 2 ++
>  configs/rpi_4_defconfig| 2 ++
>  configs/rpi_arm64_defconfig| 2 ++
>  configs/rpi_defconfig  | 2 ++
>  9 files changed, 18 insertions(+)
> 
> diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
> index c0a9b6c788..206be1590c 100644
> --- a/configs/rpi_0_w_defconfig
> +++ b/configs/rpi_0_w_defconfig
> @@ -28,6 +28,8 @@ CONFIG_DM_ETH=y
>  CONFIG_PINCTRL=y
>  # CONFIG_PINCTRL_GENERIC is not set
>  # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
> +CONFIG_SYSINFO=y
> +CONFIG_SYSINFO_SMBIOS=y
>  CONFIG_USB=y
>  CONFIG_DM_USB=y
>  CONFIG_USB_DWC2=y
> diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
> index 33e0ef6989..d3d62f3028 100644
> --- a/configs/rpi_2_defconfig
> +++ b/configs/rpi_2_defconfig
> @@ -28,6 +28,8 @@ CONFIG_DM_ETH=y
>  CONFIG_PINCTRL=y
>  # CONFIG_PINCTRL_GENERIC is not set
>  # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
> +CONFIG_SYSINFO=y
> +CONFIG_SYSINFO_SMBIOS=y
>  CONFIG_USB=y
>  CONFIG_DM_USB=y
>  CONFIG_USB_DWC2=y
> diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
> index 15c62adc69..b69bc05833 100644
> --- a/configs/rpi_3_32b_defconfig
> +++ b/configs/rpi_3_32b_defconfig
> @@ -30,6 +30,8 @@ CONFIG_DM_ETH=y
>  CONFIG_PINCTRL=y
>  # CONFIG_PINCTRL_GENERIC is not set
>  # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
> +CONFIG_SYSINFO=y
> +CONFIG_SYSINFO_SMBIOS=y
>  CONFIG_USB=y
>  CONFIG_DM_USB=y
>  CONFIG_USB_DWC2=y
> diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig
> index ebab0b4f86..8316a43116 100644
> --- a/configs/rpi_3_b_plus_defconfig
> +++ b/configs/rpi_3_b_plus_defconfig
> @@ -30,6 +30,8 @@ CONFIG_DM_ETH=y
>  CONFIG_PINCTRL=y
>  # CONFIG_PINCTRL_GENERIC is not set
>  # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
> +CONFIG_SYSINFO=y
> +CONFIG_SYSINFO_SMBIOS=y
>  CONFIG_USB=y
>  CONFIG_DM_USB=y
>  CONFIG_USB_DWC2=y
> diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
> index daeb6d1b64..bdfac3f31a 100644
> --- a/configs/rpi_3_defconfig
> +++ b/configs/rpi_3_defconfig
> @@ -30,6 +30,8 @@ CONFIG_DM_ETH=y
>  CONFIG_PINCTRL=y
>  # CONFIG_PINCTRL_GENERIC is not set
>  # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
> +CONFIG_SYSINFO=y
> +CONFIG_SYSINFO_SMBIOS=y
>  CONFIG_USB=y
>  CONFIG_DM_USB=y
>  CONFIG_USB_DWC2=y
> diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
> index 0cbdd5fee1..7a10d4b0d4 100644
> --- a/configs/rpi_4_32b_defconfig
> +++ b/configs/rpi_4_32b_defconfig
> @@ -39,6 +39,8 @@ CONFIG_DM_RESET=y
>  CONFIG_DM_RNG=y
>  CONFIG_RNG_IPROC200=y
>  # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
> +CONFIG_SYSINFO=y
> +CONFIG_SYSINFO_SMBIOS=y
>  CONFIG_USB=y
>  CONFIG_DM_USB=y
>  CONFIG_DM_USB_GADGET=y
> diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
> index 3f21f99edb..5d889df794 100644
> --- a/configs/rpi_4_defconfig
> +++ b/configs/rpi_4_defconfig
> @@ -39,6 +39,8 @@ CONFIG_DM_RESET=y
>  CONFIG_DM_RNG=y
>  CONFIG_RNG_IPROC200=y
>  # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
> +CONFIG_SYSINFO=y
> +CONFIG_SYSINFO_SMBIOS=y
>  CONFIG_USB=y
>  CONFIG_DM_USB=y
>  CONFIG_DM_USB_GADGET=y
> diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
> index d282d509ce..af45178962 100644
> --- a/configs/rpi_arm64_defconfig
> +++ b/configs/rpi_arm64_defconfig
> @@ -36,6 +36,8 @@ CONFIG_DM_RESET=y
>  CONFIG_DM_RNG=y
>  CONFIG_RNG_IPROC200=y
>  # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
> +CONFIG_SYSINFO=y
> +CONFIG_SYSINFO_SMBIOS=y
>  CONFIG_USB=y
>  CONFIG_DM_USB=y
>  CONFIG_USB_XHCI_HCD=y
> diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
> index 06b390d907..af084c8505 100644
> --- a/configs/rpi_defconfig
> +++ b/configs/rpi_defconfig
> @@ -28,6 +28,8 @@ CONFIG_DM_ETH=y
>  CONFIG_PINCTRL=y
>  # CONFIG_PINCTRL_GENERIC is not set
>  # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
> +CONFIG_SYSINFO=y
> +CONFIG_SYSINFO_SMBIOS=y
>  CONFIG_USB=y
>  CONFIG_DM_USB=y
>  CONFIG_USB_DWC2=y
> 




Re: [PATCH 1/2] arm: dts: bcm283x: Add minimal smbios information

2021-04-09 Thread Fabian Vogt
Am Freitag, 9. April 2021, 14:35:10 CEST schrieb matthias@kernel.org:
> From: Matthias Brugger 
> 
> At present SMBIOS tables are emtpy,
 ^ typo

> which breaks some use-cases that rely on that.
Can you give an example?

> Add some minimal information to
Isn't it possible to get the complete information from the firmware here?
That would allow to have the correct product and serial at least.
If that's not possible or too complex, then I suggest to use the proper
strings, e.g. "Raspberry Pi", as those are user visible.

> fullfill this.
^ typo
 
> Signed-off-by: Matthias Brugger 
> ---
> 
>  arch/arm/dts/bcm283x-u-boot.dtsi | 20 
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm/dts/bcm283x-u-boot.dtsi 
> b/arch/arm/dts/bcm283x-u-boot.dtsi
> index 68d03627f4..f5235cb083 100644
> --- a/arch/arm/dts/bcm283x-u-boot.dtsi
> +++ b/arch/arm/dts/bcm283x-u-boot.dtsi
> @@ -6,6 +6,26 @@
>   * (C) Copyright 2016 Fabian Vogt 
>   */
>  
> +/ {
> + smbios {
> + compatible = "u-boot,sysinfo-smbios";
> + smbios {
> + system {
> + manufacturer = "raspberrypi";
> + product = "rpi";
> + };
> + baseboard {
> + manufacturer = "raspberrypi";
> + product = "rpi";
> + };
> + chassis {
> + manufacturer = "raspberrypi";
> + product = "rpi";

According to doc/device-tree-bindings/sysinfo/smbios.txt, "chassis"
doesn't have a "product".

Cheers,
Fabian

> + };
> + };
> + };
> +};
> +
>  &uart0 {
>   skip-init;
>   u-boot,dm-pre-reloc;
> 




Re: [PATCH v1 1/2] cmd: bind: Fix driver binding on a device

2021-04-09 Thread Sean Anderson

On 4/9/21 8:05 AM, Patrice CHOTARD wrote:



On 4/9/21 1:01 PM, Andy Shevchenko wrote:

On Fri, Apr 9, 2021 at 1:32 PM Patrice CHOTARD
 wrote:

On 4/9/21 11:48 AM, Andy Shevchenko wrote:

On Fri, Apr 9, 2021 at 12:28 PM Patrice CHOTARD
 wrote:

On 4/9/21 11:16 AM, Andy Shevchenko wrote:

On Fri, Apr 9, 2021 at 10:37 AM Patrice Chotard
 wrote:


...


+   if (drv) {
+   if (drv == entry)
+   break;



+   } else {
+   if (!ret)
+   break;
+   }


This can be simplified to
} else if (!ret)
   break;


I know but checkpatch.pl requested it ;-)


You mean it doesn't recognize 'else if' construction? Then it's a bug
there for sure.



No, i mean checkpath.pl request to put {} on all statements as shown below :

./scripts/checkpatch.pl 0001-cmd-bind-Fix-driver-binding-on-a-device.patch
CHECK: braces {} should be used on all arms of this statement
#83: FILE: drivers/core/lists.c:228:
+   if (drv) {
[...]
+   } else if (!ret)


So, you still can put else and if on one line, right?



No, if i put else and if on one line as you suggested, checkpatch.pl is 
complaining as shown above.

Patrice



} else if (!ret) {
break;
}

?


Re: [PATCH V2] arm: stm32mp1: Set soc_type, soc_pkg, soc_rev env variables

2021-04-09 Thread Patrice CHOTARD
Hi Marek

On 4/9/21 2:43 PM, Patrick DELAUNAY wrote:
> Hi Marek,
> 
> On 3/31/21 2:15 PM, Marek Vasut wrote:
>> Split up get_soc_name(), clean the decoding up a bit, and set up
>> environment variables which contain the SoC type, package, revision.
>> This is useful on SoMs, where multiple SoC options are populated.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Patrick Delaunay 
>> Cc: Patrice Chotard 
>> ---
>> V2: Fix pkg = 0 , which should be *pkg = 0
>> ---
>>   arch/arm/mach-stm32mp/cpu.c | 105 ++--
>>   1 file changed, 53 insertions(+), 52 deletions(-)
>>
> 
> Reviewed-by: Patrick Delaunay 
> 
> Thanks
> Patrick
> 

Applied to u-boot-stm/master

Thanks
Patrice


Re: [PATCH V2] arm: stm32mp1: Set soc_type, soc_pkg, soc_rev env variables

2021-04-09 Thread Patrick DELAUNAY

Hi Marek,

On 3/31/21 2:15 PM, Marek Vasut wrote:

Split up get_soc_name(), clean the decoding up a bit, and set up
environment variables which contain the SoC type, package, revision.
This is useful on SoMs, where multiple SoC options are populated.

Signed-off-by: Marek Vasut 
Cc: Patrick Delaunay 
Cc: Patrice Chotard 
---
V2: Fix pkg = 0 , which should be *pkg = 0
---
  arch/arm/mach-stm32mp/cpu.c | 105 ++--
  1 file changed, 53 insertions(+), 52 deletions(-)



Reviewed-by: Patrick Delaunay 

Thanks
Patrick



[PATCH 2/2] configs: rpi: Enable SMBIOS sysinfo driver

2021-04-09 Thread matthias . bgg
From: Matthias Brugger 

Enalbe this driver to allow U-Boot to get SMBIOS table information from
a device tree node.

Signed-off-by: Matthias Brugger 

---

 configs/rpi_0_w_defconfig  | 2 ++
 configs/rpi_2_defconfig| 2 ++
 configs/rpi_3_32b_defconfig| 2 ++
 configs/rpi_3_b_plus_defconfig | 2 ++
 configs/rpi_3_defconfig| 2 ++
 configs/rpi_4_32b_defconfig| 2 ++
 configs/rpi_4_defconfig| 2 ++
 configs/rpi_arm64_defconfig| 2 ++
 configs/rpi_defconfig  | 2 ++
 9 files changed, 18 insertions(+)

diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
index c0a9b6c788..206be1590c 100644
--- a/configs/rpi_0_w_defconfig
+++ b/configs/rpi_0_w_defconfig
@@ -28,6 +28,8 @@ CONFIG_DM_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index 33e0ef6989..d3d62f3028 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -28,6 +28,8 @@ CONFIG_DM_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index 15c62adc69..b69bc05833 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -30,6 +30,8 @@ CONFIG_DM_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig
index ebab0b4f86..8316a43116 100644
--- a/configs/rpi_3_b_plus_defconfig
+++ b/configs/rpi_3_b_plus_defconfig
@@ -30,6 +30,8 @@ CONFIG_DM_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index daeb6d1b64..bdfac3f31a 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -30,6 +30,8 @@ CONFIG_DM_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 0cbdd5fee1..7a10d4b0d4 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -39,6 +39,8 @@ CONFIG_DM_RESET=y
 CONFIG_DM_RNG=y
 CONFIG_RNG_IPROC200=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_USB_GADGET=y
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index 3f21f99edb..5d889df794 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -39,6 +39,8 @@ CONFIG_DM_RESET=y
 CONFIG_DM_RNG=y
 CONFIG_RNG_IPROC200=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_USB_GADGET=y
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index d282d509ce..af45178962 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -36,6 +36,8 @@ CONFIG_DM_RESET=y
 CONFIG_DM_RNG=y
 CONFIG_RNG_IPROC200=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index 06b390d907..af084c8505 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -28,6 +28,8 @@ CONFIG_DM_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
-- 
2.30.2



[PATCH 1/2] arm: dts: bcm283x: Add minimal smbios information

2021-04-09 Thread matthias . bgg
From: Matthias Brugger 

At present SMBIOS tables are emtpy, which breaks some use-cases that
rely on that. Add some minimal information to fullfill this.

Signed-off-by: Matthias Brugger 
---

 arch/arm/dts/bcm283x-u-boot.dtsi | 20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/dts/bcm283x-u-boot.dtsi b/arch/arm/dts/bcm283x-u-boot.dtsi
index 68d03627f4..f5235cb083 100644
--- a/arch/arm/dts/bcm283x-u-boot.dtsi
+++ b/arch/arm/dts/bcm283x-u-boot.dtsi
@@ -6,6 +6,26 @@
  * (C) Copyright 2016 Fabian Vogt 
  */
 
+/ {
+   smbios {
+   compatible = "u-boot,sysinfo-smbios";
+   smbios {
+   system {
+   manufacturer = "raspberrypi";
+   product = "rpi";
+   };
+   baseboard {
+   manufacturer = "raspberrypi";
+   product = "rpi";
+   };
+   chassis {
+   manufacturer = "raspberrypi";
+   product = "rpi";
+   };
+   };
+   };
+};
+
 &uart0 {
skip-init;
u-boot,dm-pre-reloc;
-- 
2.30.2



Re: [PATCH] net: dwc_eth_qos: add support of device tree configuration for reset delay

2021-04-09 Thread Marek Vasut

On 4/9/21 10:00 AM, Patrick Delaunay wrote:

The gpio reset assert/deassert delay are today harcoded in U-Boot driver
but the value should be read from DT.

STM32 use the generic binding defined in linux:
Documentation/devicetree/bindings/net/ethernet-phy.yaml

   reset-gpios:
 maxItems: 1
 description:
   The GPIO phandle and specifier for the PHY reset signal.

   reset-assert-us:
 description:
   Delay after the reset was asserted in microseconds. If this
   property is missing the delay will be skipped.

   reset-deassert-us:
 description:
   Delay after the reset was deasserted in microseconds. If
   this property is missing the delay will be skipped.

See also U-Boot: doc/device-tree-bindings/net/phy.txt


Since this is a PHY property, shouldn't that be handled in 
drivers/net/phy/ instead of MAC driver ?


Re: [PATCH v1 1/2] cmd: bind: Fix driver binding on a device

2021-04-09 Thread Patrice CHOTARD



On 4/9/21 1:01 PM, Andy Shevchenko wrote:
> On Fri, Apr 9, 2021 at 1:32 PM Patrice CHOTARD
>  wrote:
>> On 4/9/21 11:48 AM, Andy Shevchenko wrote:
>>> On Fri, Apr 9, 2021 at 12:28 PM Patrice CHOTARD
>>>  wrote:
 On 4/9/21 11:16 AM, Andy Shevchenko wrote:
> On Fri, Apr 9, 2021 at 10:37 AM Patrice Chotard
>  wrote:
> 
> ...
> 
>> +   if (drv) {
>> +   if (drv == entry)
>> +   break;
>
>> +   } else {
>> +   if (!ret)
>> +   break;
>> +   }
>
> This can be simplified to
> } else if (!ret)
>   break;

 I know but checkpatch.pl requested it ;-)
>>>
>>> You mean it doesn't recognize 'else if' construction? Then it's a bug
>>> there for sure.
>>>
>>
>> No, i mean checkpath.pl request to put {} on all statements as shown below :
>>
>> ./scripts/checkpatch.pl 0001-cmd-bind-Fix-driver-binding-on-a-device.patch
>> CHECK: braces {} should be used on all arms of this statement
>> #83: FILE: drivers/core/lists.c:228:
>> +   if (drv) {
>> [...]
>> +   } else if (!ret)
> 
> So, you still can put else and if on one line, right?
> 

No, if i put else and if on one line as you suggested, checkpatch.pl is 
complaining as shown above.

Patrice


[PATCH v5 7/7] board: Add rt-thread art-pi board support

2021-04-09 Thread dillon . minfei
From: dillon min 

All these files are add for support rt-thread art-pi board
- add board/st/stm32h750-art-pi, defconfig, header support for u-boot

for more information about art-pi, please goto:
https://art-pi.gitee.io/website/

Signed-off-by: dillon min 
Reviewed-by: Patrice Chotard 
---
v5: remove "for STMicroelectronics." from Author(s) description

 arch/arm/mach-stm32/stm32h7/Kconfig  |  4 ++
 board/st/stm32h750-art-pi/Kconfig| 19 +
 board/st/stm32h750-art-pi/MAINTAINERS|  7 
 board/st/stm32h750-art-pi/Makefile   |  6 +++
 board/st/stm32h750-art-pi/stm32h750-art-pi.c | 58 
 configs/stm32h750-art-pi_defconfig   | 51 
 include/configs/stm32h750-art-pi.h   | 48 +++
 7 files changed, 193 insertions(+)
 create mode 100644 board/st/stm32h750-art-pi/Kconfig
 create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS
 create mode 100644 board/st/stm32h750-art-pi/Makefile
 create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c
 create mode 100644 configs/stm32h750-art-pi_defconfig
 create mode 100644 include/configs/stm32h750-art-pi.h

diff --git a/arch/arm/mach-stm32/stm32h7/Kconfig 
b/arch/arm/mach-stm32/stm32h7/Kconfig
index 55e6217..70233a4 100644
--- a/arch/arm/mach-stm32/stm32h7/Kconfig
+++ b/arch/arm/mach-stm32/stm32h7/Kconfig
@@ -6,7 +6,11 @@ config TARGET_STM32H743_DISCO
 config TARGET_STM32H743_EVAL
bool "STM32H743 Evaluation board"
 
+config TARGET_STM32H750_ART_PI
+   bool "STM32H750 ART Pi board"
+
 source "board/st/stm32h743-eval/Kconfig"
 source "board/st/stm32h743-disco/Kconfig"
+source "board/st/stm32h750-art-pi/Kconfig"
 
 endif
diff --git a/board/st/stm32h750-art-pi/Kconfig 
b/board/st/stm32h750-art-pi/Kconfig
new file mode 100644
index 000..c31b984
--- /dev/null
+++ b/board/st/stm32h750-art-pi/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM32H750_ART_PI
+
+config SYS_BOARD
+   string
+   default "stm32h750-art-pi"
+
+config SYS_VENDOR
+   string
+   default "st"
+
+config SYS_SOC
+   string
+   default "stm32h7"
+
+config SYS_CONFIG_NAME
+   string
+   default "stm32h750-art-pi"
+
+endif
diff --git a/board/st/stm32h750-art-pi/MAINTAINERS 
b/board/st/stm32h750-art-pi/MAINTAINERS
new file mode 100644
index 000..9578833
--- /dev/null
+++ b/board/st/stm32h750-art-pi/MAINTAINERS
@@ -0,0 +1,7 @@
+STM32H750 ART PI BOARD
+M: Dillon Min 
+S: Maintained
+F: board/st/stm32h750-art-pi
+F: include/configs/stm32h750-art-pi.h
+F: configs/stm32h750-art-pi_defconfig
+F: arch/arm/dts/stm32h7*
diff --git a/board/st/stm32h750-art-pi/Makefile 
b/board/st/stm32h750-art-pi/Makefile
new file mode 100644
index 000..a06de87
--- /dev/null
+++ b/board/st/stm32h750-art-pi/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021, RT-Thread - All Rights Reserved
+# Author(s): Dillon Min,  for RT-Thread.
+
+obj-y  := stm32h750-art-pi.o
diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c 
b/board/st/stm32h750-art-pi/stm32h750-art-pi.c
new file mode 100644
index 000..5785b2e
--- /dev/null
+++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, STMicroelectronics - All Rights Reserved
+ * Author(s): Dillon Min 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+   struct udevice *dev;
+   int ret;
+
+   ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+   if (ret) {
+   debug("DRAM init failed: %d\n", ret);
+   return ret;
+   }
+
+   if (fdtdec_setup_mem_size_base() != 0)
+   ret = -EINVAL;
+
+   return ret;
+}
+
+int dram_init_banksize(void)
+{
+   fdtdec_setup_memory_banksize();
+
+   return 0;
+}
+
+int board_early_init_f(void)
+{
+   return 0;
+}
+
+u32 get_board_rev(void)
+{
+   return 0;
+}
+
+int board_late_init(void)
+{
+   return 0;
+}
+
+int board_init(void)
+{
+   gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+   return 0;
+}
diff --git a/configs/stm32h750-art-pi_defconfig 
b/configs/stm32h750-art-pi_defconfig
new file mode 100644
index 000..447af5b
--- /dev/null
+++ b/configs/stm32h750-art-pi_defconfig
@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32=y
+CONFIG_SYS_TEXT_BASE=0x9000
+CONFIG_SYS_MALLOC_F_LEN=0xF00
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_STM32H7=y
+CONFIG_TARGET_STM32H750_ART_PI=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=3
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_DEFAULT_FDT_FILE="stm32h750i-art-pi"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SYS_PRO

[PATCH v5 6/7] ram: stm32: fix strsep failed on read only memory

2021-04-09 Thread dillon . minfei
From: dillon min 

strsep will change data from original memory address,
in case the memory is in non-sdram/sram place, will
run into a bug(hang at SDRAM: )

just add a temporary array to store bank_name[] to fix this
bug.

Signed-off-by: dillon min 
Reviewed-by: Patrice Chotard 
---
v5: no changes

 drivers/ram/stm32_sdram.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
index 540ad85..3e25cc7 100644
--- a/drivers/ram/stm32_sdram.c
+++ b/drivers/ram/stm32_sdram.c
@@ -268,6 +268,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
u32 swp_fmc;
ofnode bank_node;
char *bank_name;
+   char _bank_name[128] = {0};
u8 bank = 0;
int ret;
 
@@ -300,6 +301,8 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
dev_for_each_subnode(bank_node, dev) {
/* extract the bank index from DT */
bank_name = (char *)ofnode_get_name(bank_node);
+   strlcpy(_bank_name, bank_name, sizeof(_bank_name));
+   bank_name = (char *)_bank_name;
strsep(&bank_name, "@");
if (!bank_name) {
pr_err("missing sdram bank index");
-- 
2.7.4



[PATCH v5 5/7] ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6

2021-04-09 Thread dillon . minfei
From: dillon min 

This patchset has following changes:

- introduce stm32h750.dtsi to support stm32h750 value line
- add pin groups for usart3/uart4/spi1/sdmmc2
- add stm32h750i-art-pi.dtb (arch/arm/boot/dts/Makefile)
- add stm32h750i-art-pi.dts to support art-pi board
- add stm32h750i-art-pi-u-boot.dtsi to support art-pi board (u-boot)

art-pi board component:
- 8MiB qspi flash
- 16MiB spi flash
- 32MiB sdram
- ap6212 wifi&bt&fm

the detail board information can be found at:
https://art-pi.gitee.io/website/

Signed-off-by: dillon min 
Reviewed-by: Patrice Chotard 
---
v5: no changes

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/stm32h7-pinctrl.dtsi  |  89 ++
 arch/arm/dts/stm32h750.dtsi|   5 +
 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi |  81 +
 arch/arm/dts/stm32h750i-art-pi.dts | 188 +
 include/dt-bindings/memory/stm32-sdram.h   |   2 +
 6 files changed, 367 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/stm32h750.dtsi
 create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c671082..0f54801 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -454,7 +454,8 @@ dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
stm32f769-disco.dtb \
stm32746g-eval.dtb
 dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
-   stm32h743i-eval.dtb
+   stm32h743i-eval.dtb \
+   stm32h750i-art-pi.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
diff --git a/arch/arm/dts/stm32h7-pinctrl.dtsi 
b/arch/arm/dts/stm32h7-pinctrl.dtsi
index f6968b5..aefa324 100644
--- a/arch/arm/dts/stm32h7-pinctrl.dtsi
+++ b/arch/arm/dts/stm32h7-pinctrl.dtsi
@@ -137,6 +137,80 @@
};
};
 
+   sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+   pins {
+   pinmux = , /* SDMMC1_D0 */
+, /* SDMMC1_D1 */
+, /* SDMMC1_D2 */
+, /* SDMMC1_D3 */
+, /* SDMMC1_CK */
+; /* SDMMC1_CMD */
+   slew-rate = <3>;
+   drive-push-pull;
+   bias-disable;
+   };
+   };
+
+   sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
+   pins1 {
+   pinmux = , /* SDMMC2_D0 */
+, /* SDMMC1_D1 */
+, /* SDMMC1_D2 */
+, /* SDMMC1_D3 */
+; /* SDMMC1_CK */
+   slew-rate = <3>;
+   drive-push-pull;
+   bias-disable;
+   };
+   pins2{
+   pinmux = ; /* SDMMC1_CMD */
+   slew-rate = <3>;
+   drive-open-drain;
+   bias-disable;
+   };
+   };
+
+   sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
+   pins {
+   pinmux = , /* SDMMC1_D0 
*/
+, /* SDMMC1_D1 
*/
+, /* SDMMC1_D2 */
+, /* SDMMC1_D3 */
+, /* SDMMC1_CK */
+; /* SDMMC1_CMD 
*/
+   };
+   };
+
+   spi1_pins: spi1-0 {
+   pins1 {
+   pinmux = ,
+   /* SPI1_CLK */
+;
+   /* SPI1_MOSI */
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <2>;
+   };
+   pins2 {
+   pinmux = ;
+   /* SPI1_MISO */
+   bias-disable;
+   };
+   };
+
+   uart4_pins: uart4-0 {
+   pins1 {
+   pinmux = ; /* UART4_TX */
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <0>;
+   };
+   pins2 {
+   pinmux = ; /* UART4_RX */
+   bias-disable;
+   };
+   };
+
usart1_pins: usart1-0 {
pins1 {
pinmux = ; /* USART1_TX */
@@ -163,6 +237,21 @@
};
};
 
+   usart3_pins: usart3-0 {
+   pins1 {
+   pinmux = , /* USART3_TX */
+; /* USART3_RTS_DE 
*/
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <0>;
+   };
+   pins2 {
+   pinmux = , /* USART3_RX */
+ 

[PATCH v5 4/7] ARM: dts: stm32: fix i2c node typo in stm32h743, update dmamux1 register

2021-04-09 Thread dillon . minfei
From: dillon min 

Replace upper case by lower case in i2c nodes name.
update dmamux1 register range.

Signed-off-by: dillon min 
Reviewed-by: Patrice Chotard 
---
v5: no changes

 arch/arm/dts/stm32h743.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index 77a8aef..ed68575 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -139,7 +139,7 @@
status = "disabled";
};
 
-   i2c3: i2c@40005C00 {
+   i2c3: i2c@40005c00 {
compatible = "st,stm32f7-i2c";
#address-cells = <1>;
#size-cells = <0>;
@@ -254,7 +254,7 @@
 
dmamux1: dma-router@40020800 {
compatible = "st,stm32h7-dmamux";
-   reg = <0x40020800 0x1c>;
+   reg = <0x40020800 0x40>;
#dma-cells = <3>;
dma-channels = <16>;
dma-requests = <128>;
@@ -386,7 +386,7 @@
status = "disabled";
};
 
-   i2c4: i2c@58001C00 {
+   i2c4: i2c@58001c00 {
compatible = "st,stm32f7-i2c";
#address-cells = <1>;
#size-cells = <0>;
-- 
2.7.4



[PATCH v5 3/7] ARM: dts: stm32: add new instances for stm32h743 MCU

2021-04-09 Thread dillon . minfei
From: dillon min 

Some instances are missing in current support of stm32h743 MCU. This commit
adds usart3/uart4 and sdmmc2 support.

Signed-off-by: dillon min 
Reviewed-by: Patrice Chotard 
---
v5: no changes

 arch/arm/dts/stm32h743.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index 8c96698..77a8aef 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -99,6 +99,22 @@
clocks = <&rcc USART2_CK>;
};
 
+   usart3: serial@40004800 {
+   compatible = "st,stm32h7-uart";
+   reg = <0x40004800 0x400>;
+   interrupts = <39>;
+   status = "disabled";
+   clocks = <&rcc USART3_CK>;
+   };
+
+   uart4: serial@40004c00 {
+   compatible = "st,stm32h7-uart";
+   reg = <0x40004c00 0x400>;
+   interrupts = <52>;
+   status = "disabled";
+   clocks = <&rcc UART4_CK>;
+   };
+
i2c1: i2c@40005400 {
compatible = "st,stm32f7-i2c";
#address-cells = <1>;
@@ -332,6 +348,20 @@
max-frequency = <12000>;
};
 
+   sdmmc2: sdmmc@48022400 {
+   compatible = "arm,pl18x", "arm,primecell";
+   arm,primecell-periphid = <0x10153180>;
+   reg = <0x48022400 0x400>;
+   interrupts = <124>;
+   interrupt-names = "cmd_irq";
+   clocks = <&rcc SDMMC2_CK>;
+   clock-names = "apb_pclk";
+   resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
+   cap-sd-highspeed;
+   cap-mmc-highspeed;
+   max-frequency = <12000>;
+   };
+
exti: interrupt-controller@5800 {
compatible = "st,stm32h7-exti";
interrupt-controller;
-- 
2.7.4



Re: [PATCH 1/2] clk: zynq: Add clock wizard driver

2021-04-09 Thread zhengxunli
Hi,

> On 4/7/21 11:05 AM, zhengxunli wrote:
> > The Clocking Wizard IP supports clock circuits customized
> > to your clocking requirements. The wizard support for
> > dynamically reconfiguring the clocking primitives for
> > Multiply, Divide, Phase Shift/Offset, or Duty Cycle.
> > 
> > Limited by uboot clk uclass without set_phase API, this
> > patch only provides set_rate to modify the frequency and
> > set 50% duty cycle by default.
> > 
> > Signed-off-by: zhengxunli 
> 
> Please use full name.

Okay, got it.

> 
> > ---
> >  drivers/clk/Kconfig  |   7 ++
> >  drivers/clk/Makefile |   1 +
> >  drivers/clk/clk_wizard.c | 180 ++
> +
> >  3 files changed, 188 insertions(+)
> >  create mode 100644 drivers/clk/clk_wizard.c
> > 
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index 4aeaa0c..4ebeccc 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -136,6 +136,13 @@ config CLK_ZYNQMP
> >   This clock driver adds support for clock realted settings for
> >   ZynqMP platform.
> > 
> > +config CLK_WIZARD
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
> tree/drivers/staging/clocking-wizard/Kconfig?h=v5.12-rc6
> 
> Small alignment with kernel would be useful.
> At least CLK_XLNX_CLKWZRD.
>
> > +   bool "Enable clock wizard driver support for zynq"
> > +   depends on CLK && ARCH_ZYNQ
> 
> Clocking wizard is standard PL based IP not just related to Zynq. It can
> be used by Microblaze, ARM cores, etc. It means no need to have
> dependency on ZYNQ here.
> 
> > +   help
> > + This clock driver adds support for clock wizard setting for
> > + Zynq platform.
> 
> ditto
>

Okay, I will fix in the next version.
 
> > +
> >  config CLK_STM32MP1
> > bool "Enable RCC clock driver for STM32MP1"
> > depends on ARCH_STM32MP && CLK
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index 645709b..d8b878c 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
> >  obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
> >  obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
> >  obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
> > +obj-$(CONFIG_CLK_WIZARD) += clk_wizard.o
> >  obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
> >  obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
> >  obj-$(CONFIG_SANDBOX) += clk_sandbox.o
> > diff --git a/drivers/clk/clk_wizard.c b/drivers/clk/clk_wizard.c
> > new file mode 100644
> > index 000..f5c2387
> > --- /dev/null
> > +++ b/drivers/clk/clk_wizard.c
> 
> name could be also aligned with kernel to have easier match with the 
kernel.

Okay, got it.

> 
> > @@ -0,0 +1,180 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Xilinx 'Clocking Wizard' driver
> > + *
> > + * Copyright (c) 2021 Macronix Inc.
> > + *
> > + * Author: Zhengxun Li 
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define SRR 0x0
> > +
> > +#define SR 0x4
> > +#define SR_LOCKED  BIT(0)
> > +
> > +#define CCR(x) (0x200 + ((x) * 4))
> > +
> > +#define FBOUT_CFG  CCR(0)
> > +#define FBOUT_DIV(x)  (x)
> > +#define FBOUT_GET_DIV(x)   ((x) & GENMASK(7, 0))
> > +#define FBOUT_MUL(x)  ((x) << 8)
> > +#define FBOUT_GET_MUL(x)   (((x) & GENMASK(15, 8)) >> 8)
> > +#define FBOUT_FRAC(x)  ((x) << 16)
> > +#define FBOUT_GET_FRAC(x)   (((x) & GENMASK(25, 16)) >> 16)
> > +#define FBOUT_FRAC_EN  BIT(26)
> > +
> > +#define FBOUT_PHASE  CCR(1)
> > +
> > +#define OUT_CFG(x)  CCR(2 + ((x) * 3))
> > +#define OUT_DIV(x)  (x)
> > +#define OUT_GET_DIV(x)  ((x) & GENMASK(7, 0))
> > +#define OUT_FRAC(x)  ((x) << 8)
> > +#define OUT_GET_FRAC(x)  (((x) & GENMASK(17, 8)) >> 8)
> > +#define OUT_FRAC_EN  BIT(18)
> > +
> > +#define OUT_PHASE(x)  CCR(3 + ((x) * 3))
> > +#define OUT_DUTY(x)  CCR(4 + ((x) * 3))
> > +
> > +#define CTRL CCR(23)
> > +#define CTRL_SEN  BIT(2)
> > +#define CTRL_SADDR  BIT(1)
> > +#define CTRL_LOAD  BIT(0)
> > +
> > +/*
> 
> /** for kernel-doc as noted below.
> 
> > + *  MMCM Block Diagram
> > + *
> > + *  ++  +-+
> > + * input ->| vco_clk_div_hw |->| vco_clk_mul_hw  |--+
> > + * rate| (int divide)   |  | (frac multiply) |  |
> > + *  ++  +-+  |
> > + *  |
> > + *   +VCO-rate---+
> > + *   |
> > + *   |  ++
> > + *   +->| clkout[0]   |-> output0 rate
> > + *   |  | (frac divide)  |
> > + *   |  ++
> > + *   |
> > + *   |  ++
> > + *   +->| clkout[1]   |-> output1 rate
> > + *   |  | (int divide)   |
> > + *   |  ++
> > + *   |
> > + * ...
> > + *   |
> > + *   |  ++
> > + *   +->| clkout[1]   |-> output6 rate
> > + *  | (int divide)   |
> > + *  +

Re: [PATCH 2/2] board: Add Zynq Mxic picozed development board support

2021-04-09 Thread zhengxunli
Hi Michal, 

Thank you for your quick reply!


"Michal Simek"  wrote on 2021/04/07 下午 
08:35:18:

> "Michal Simek"  
> 2021/04/07 下午 08:35
> 
> To
> 
> "zhengxunli" , , 
> 
> cc
> 
> , , 
> 
> Subject
> 
> Re: [PATCH 2/2] board: Add Zynq Mxic picozed development board support
> 
> Hi,
> 
> On 4/7/21 11:05 AM, zhengxunli wrote:
> > Add the Zynq Mxic picozed development board support.
> > 
> > Signed-off-by: zhengxunli 
> > ---
> >  arch/arm/dts/Makefile  |  3 +-
> >  arch/arm/dts/zynq-mxic-picozed.dts | 66 +
> +
> >  2 files changed, 68 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/arm/dts/zynq-mxic-picozed.dts
> > 
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 9a8de46..059bb3b 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -286,7 +286,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
> > zynq-zturn.dtb \
> > zynq-zturn-v5.dtb \
> > zynq-zybo.dtb \
> > -   zynq-zybo-z7.dtb
> > +   zynq-zybo-z7.dtb \
> > +   zynq-mxic-picozed.dtb
> >  dtb-$(CONFIG_ARCH_ZYNQMP) += \
> > avnet-ultra96-rev1.dtb \
> > avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb   \
> > diff --git a/arch/arm/dts/zynq-mxic-picozed.dts b/arch/arm/dts/
> zynq-mxic-picozed.dts
> > new file mode 100644
> > index 000..d2ff358
> > --- /dev/null
> > +++ b/arch/arm/dts/zynq-mxic-picozed.dts
> > @@ -0,0 +1,66 @@
> > +/dts-v1/;
> > +/include/ "zynq-7000.dtsi"
> > +
> > +/ {
> > +   model = "Zynq MXIC PicoZed Development Board";
> > +   compatible = "mxicy,zynq-mxic-picozed", "xlnx,zynq-7000";
> > +
> > +   aliases {
> > +  ethernet0 = &gem0;
> > +  serial0 = &uart1;
> > +  spi0 = &spi_controller;
> > +   };
> > +
> > +   memory@0 {
> > +  device_type = "memory";
> > +  reg = <0x0 0x3000>;
> > +   };
> > +
> > +   chosen {
> > +  bootargs = "";
> > +  stdout-path = "serial0:115200n8";
> > +   };
> > +};
> > +
> > +&amba {
> > +   clkwizard: clkwizard@43c2 {
> > +  compatible = "xlnx,clk-wizard-5.1";
> > +  reg = <0x43c2 0x1>;
> > +  clocks = <&clkc 18>, <&clkc 18>;
> > +  clock-names = "aclk", "clk_in1";
> > +  #clock-cells = <1>;
> > +  clock-frequency = <13330>;
> > +  xlnx,clk-wizard-num-outputs = <2>;
> > +   };
> 
> This is definitely PL IP.

What is the PL?

> > +
> > +   spi_controller: spi@43c3 {
> > +  compatible = "mxicy,mx25f0a-spi";
> 
> 
> And I expect this is also PL based IP.
> And we have agreement that for upstream project we won't be accepting
> any description for PL.
> But there is not a problem with accepting driver for clocking wizard or
> this IP.
 
It sounds like we can move on.

> And picozed board is already supported in u-boot.

Thanks,
Zhengxun


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Re: [PATCH v3 05/11] clk: k210: Move the clint clock to under aclk

2021-04-09 Thread Damien Le Moal
On 2021/04/09 11:58, Sean Anderson wrote:
> 
> On 4/8/21 10:54 PM, Damien Le Moal wrote:
>> On 2021/04/09 11:13, Sean Anderson wrote:
>>> No other (real) clocks have the cpu clock as their parent; instead they are
>>> children of aclk. Move the clint clock under aclk to match them.
>>>
>>> Signed-off-by: Sean Anderson 
>>> ---
>>>
>>> (no changes since v2)
>>>
>>> Changes in v2:
>>> - New
>>>
>>>   drivers/clk/kendryte/clk.c | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
>>> index ab86533bb4..5091f07eb0 100644
>>> --- a/drivers/clk/kendryte/clk.c
>>> +++ b/drivers/clk/kendryte/clk.c
>>> @@ -643,7 +643,7 @@ static int k210_clk_probe(struct udevice *dev)
>>>   
>>> /* The MTIME register in CLINT runs at one 50th the CPU clock speed */
>>> clk_dm(K210_CLK_CLINT,
>>> -  clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50));
>>> +  clk_register_fixed_factor(NULL, "clint", "aclk", 0, 1, 50));
>>>   
>>> return 0;
>>>   }
>>>
>>
>> Looks good, but representing this clock is in fact useless, at least in 
>> Linux,
>> since the clint driver does not use it directly and derives its rate from
>> riscv_timebase which is set from the timebase-frequency DT property.
>>
>> Not sure how u-boot handles that though. Since your code allows changing the
>> PLLs frequency, the timebase-frequency property may end up being buggy if it 
>> is
>> not changed too.
>>
> 
> U-Boot uses the clocks property since 47d7e3b5eb ("riscv: Move timer
> portions of SiFive CLINT to drivers/timer") :)

I remember that adding the clock property to Linux DT gave warning with make
dtb_check. Hence I removed it. driver/clocksoure/timer-riscv.c also make the
timebase-frequency DT property mandatory. Time for some more patching on Linux
side I guess :)


> 
> --Sean
> 


-- 
Damien Le Moal
Western Digital Research


Re: [PATCH v3 05/11] clk: k210: Move the clint clock to under aclk

2021-04-09 Thread Damien Le Moal
On 2021/04/09 11:54, Damien Le Moal wrote:
> On 2021/04/09 11:13, Sean Anderson wrote:
>> No other (real) clocks have the cpu clock as their parent; instead they are
>> children of aclk. Move the clint clock under aclk to match them.
>>
>> Signed-off-by: Sean Anderson 
>> ---
>>
>> (no changes since v2)
>>
>> Changes in v2:
>> - New
>>
>>  drivers/clk/kendryte/clk.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
>> index ab86533bb4..5091f07eb0 100644
>> --- a/drivers/clk/kendryte/clk.c
>> +++ b/drivers/clk/kendryte/clk.c
>> @@ -643,7 +643,7 @@ static int k210_clk_probe(struct udevice *dev)
>>  
>>  /* The MTIME register in CLINT runs at one 50th the CPU clock speed */
>>  clk_dm(K210_CLK_CLINT,
>> -   clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50));
>> +   clk_register_fixed_factor(NULL, "clint", "aclk", 0, 1, 50));
>>  
>>  return 0;
>>  }
>>
> 
> Looks good, but representing this clock is in fact useless, at least in Linux,
> since the clint driver does not use it directly and derives its rate from
> riscv_timebase which is set from the timebase-frequency DT property.
> 
> Not sure how u-boot handles that though. Since your code allows changing the
> PLLs frequency, the timebase-frequency property may end up being buggy if it 
> is
> not changed too.

Actually, thinking about this some more, the clint DT node should have an
optional clock entry and use that clock rate to set riscv_timebase if the clock
entry is present. riscv_timebase can be set using timebase-frequency DT property
if the clock is not set.

> 


-- 
Damien Le Moal
Western Digital Research


Re: [PATCH v3 05/11] clk: k210: Move the clint clock to under aclk

2021-04-09 Thread Damien Le Moal
On 2021/04/09 11:13, Sean Anderson wrote:
> No other (real) clocks have the cpu clock as their parent; instead they are
> children of aclk. Move the clint clock under aclk to match them.
> 
> Signed-off-by: Sean Anderson 
> ---
> 
> (no changes since v2)
> 
> Changes in v2:
> - New
> 
>  drivers/clk/kendryte/clk.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
> index ab86533bb4..5091f07eb0 100644
> --- a/drivers/clk/kendryte/clk.c
> +++ b/drivers/clk/kendryte/clk.c
> @@ -643,7 +643,7 @@ static int k210_clk_probe(struct udevice *dev)
>  
>   /* The MTIME register in CLINT runs at one 50th the CPU clock speed */
>   clk_dm(K210_CLK_CLINT,
> -clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50));
> +clk_register_fixed_factor(NULL, "clint", "aclk", 0, 1, 50));
>  
>   return 0;
>  }
> 

Looks good, but representing this clock is in fact useless, at least in Linux,
since the clint driver does not use it directly and derives its rate from
riscv_timebase which is set from the timebase-frequency DT property.

Not sure how u-boot handles that though. Since your code allows changing the
PLLs frequency, the timebase-frequency property may end up being buggy if it is
not changed too.

-- 
Damien Le Moal
Western Digital Research


[PATCH v5 2/7] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750

2021-04-09 Thread dillon . minfei
From: dillon min 

This patch is intend to add support stm32h750 value line,
just add stm32h7-pinctrl.dtsi for extending, with following changes:

- rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi
- move 'pin-controller' from stm32h7-pinctrl.dtsi to stm32h743.dtsi
- update stm32h743i-{disco, eval}.dts to include stm32h7-pinctrl.dtsi

Signed-off-by: dillon min 
Reviewed-by: Patrice Chotard 
---
v5: no changes

 arch/arm/dts/stm32h7-pinctrl.dtsi   | 185 ++
 arch/arm/dts/stm32h743-pinctrl.dtsi | 306 
 arch/arm/dts/stm32h743.dtsi | 142 +
 arch/arm/dts/stm32h743i-disco.dts   |   2 +-
 arch/arm/dts/stm32h743i-eval.dts|   2 +-
 5 files changed, 329 insertions(+), 308 deletions(-)
 create mode 100644 arch/arm/dts/stm32h7-pinctrl.dtsi
 delete mode 100644 arch/arm/dts/stm32h743-pinctrl.dtsi

diff --git a/arch/arm/dts/stm32h7-pinctrl.dtsi 
b/arch/arm/dts/stm32h7-pinctrl.dtsi
new file mode 100644
index 000..f6968b5
--- /dev/null
+++ b/arch/arm/dts/stm32h7-pinctrl.dtsi
@@ -0,0 +1,185 @@
+/*
+ * Copyright 2017 - Alexandre Torgue 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+
+&pinctrl {
+
+   i2c1_pins_a: i2c1-0 {
+   pins {
+   pinmux = , /* I2C1_SCL */
+; /* I2C1_SDA */
+   bias-disable;
+   drive-open-drain;
+   slew-rate = <0>;
+   };
+   };
+
+   ethernet_rmii: rmii-0 {
+   pins {
+   pinmux = ,
+,
+,
+,
+,
+,
+,
+,
+;
+   slew-rate = <2>;
+   };
+   };
+
+   sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+   pins {
+   pinmux = , /* SDMMC1_D0 */
+, /* SDMMC1_D1 */
+, /* SDMMC1_D2 */
+, /* SDMMC1_D3 */
+, /* SDMMC1_CK */
+; /* SDMMC1_CMD */
+   slew-rate = <3>;
+   drive-push-pull;
+   bias-disable;
+   };
+   };
+
+   sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+   pins1 {
+   pinmux = , /* SDMMC1_D0 */
+, /* SDMMC1_D1 */
+, /* SDMMC1_D2 */
+, /* SDMMC1_D3 */
+; /* SDMMC1_CK */
+   slew-rate = <3>;
+   drive-push-pull;
+   bias-disable;
+   };
+   pins2{
+   pinmux = ; /* SDMMC1_CMD */
+   slew-rate = <3>;
+

[PATCH v5 1/7] ARM: dts: stm32: split sdram pin & timing parameter into specific board dts

2021-04-09 Thread dillon . minfei
From: dillon min 

As different boards has their own sdram hw connection, mount different
sdram modules, so move sdram timing parameter and pin configuration
to their board device tree.

Signed-off-by: dillon min 
Reviewed-by: Patrice Chotard 
---
v5: no changes

 arch/arm/dts/stm32h7-u-boot.dtsi  | 100 ++
 arch/arm/dts/stm32h743i-disco-u-boot.dtsi |  98 +
 arch/arm/dts/stm32h743i-eval-u-boot.dtsi  |  98 +
 3 files changed, 201 insertions(+), 95 deletions(-)

diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
index 54dd406..84dc765 100644
--- a/arch/arm/dts/stm32h7-u-boot.dtsi
+++ b/arch/arm/dts/stm32h7-u-boot.dtsi
@@ -20,6 +20,7 @@
gpio9 = &gpioj;
gpio10 = &gpiok;
mmc0 = &sdmmc1;
+   pinctrl0 = &pinctrl;
};
 
soc {
@@ -36,30 +37,6 @@
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
status = "okay";
-
-   /*
-* Memory configuration from sdram datasheet 
IS42S32800G-6BLI
-* first bank is bank@0
-* second bank is bank@1
-*/
-   bank1: bank@1 {
-   st,sdram-control = /bits/ 8 ;
-   st,sdram-timing = /bits/ 8 ;
-   st,sdram-refcount = <1539>;
-   };
};
};
 };
@@ -136,77 +113,6 @@
compatible = "st,stm32-gpio";
 };
 
-&pinctrl {
-   fmc_pins: fmc@0 {
-   pins {
-   pinmux = ,
-,
-,
-,
-,
-,
-,
-
-,
-,
-,
-,
-,
-,
-,
-,
-,
-,
-,
-
-,
-,
-,
-,
-,
-,
-,
-,
-,
-,
-,
-
-,
-,
-,
-,
-,
-,
-,
-
-,
-,
-,
-,
-,
-,
-,
-,
-,
-,
-,
-
-,
-,
-,
-,
-,
-,
-,
-,
-,
-;
-
-   slew-rate = <3>;
-   };
-   };
-};
-
 &pwrcfg {
u-boot,dm-pre-reloc;
 };
@@ -222,3 +128,7 @@
 &timer5 {
u-boot,dm-pre-reloc;
 };
+
+&pinctrl {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi 
b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
index 5965afc..02e28c6 100644
--- a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
@@ -1,3 +1,101 @@
 // SPDX-License-Identifier: GPL-2.0+
 
 #include 
+
+&fmc {
+
+   /*
+* Memory configuration from sdram datasheet IS42S32800G-6BLI
+* first bank is bank@0
+* second bank is bank@1
+*/
+   bank1: bank@1 {
+   st,sdram-control = /bits/ 8 ;
+   st,sdram-timing = /bits/ 8 ;
+   st,sdram-refcount = <1539>;
+   };
+};
+
+&pinctrl {
+   fmc_pins: fmc@0 {
+   pins {
+   pinmux = ,
+,
+,
+,
+,
+,
+,
+
+,
+,
+ 

[PATCH v5 0/7] Add rt-thread art-pi board support

2021-04-09 Thread dillon . minfei
From: dillon min 

These patches aim to adds u-boot support on art-pi board.

the board resources:
- stm32h750xbh6 128k flash, 1024k sram
- 32MiB sdram
- 16MiB spi flash
- 8MiB qspi flash
- onboard wifi, bt, fm

the detail board information can be found at:
https://art-pi.gitee.io/website/

---
changes in v5:
- remove "for STMicroelectronics." from Author(s) description

changes in v4:
- sync with kernel side device tree submit
- use strlcpy in stm32_sdram.c
- update CONFIG_BOOTARGS, remove rdinit=/linuxrc, to use kernel's devtmpfs
- remove unused st,stm32h750-pinctrl from patch v3

changes in v3:
two mirror changes in [PATCH v3 2/6], others same to version 2
- remove "for STMicroelectronics." from arch/arm/dts/stm32h750-pinctrl.dtsi
- correct misspelling parameters
you can found detail patch v2 information at link:
https://patchwork.ozlabs.org/project/uboot/list/?series=236009

changes in v2:
- fix wrong author/date in previous submit
- sync with kernel device tree files
- add st,stm32h750-pinctrl in doc and pinctrl driver

*** BLURB HERE ***

dillon min (7):
  ARM: dts: stm32: split sdram pin & timing parameter into specific
board dts
  ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750
  ARM: dts: stm32: add new instances for stm32h743 MCU
  ARM: dts: stm32: fix i2c node typo in stm32h743, update dmamux1
register
  ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6
  ram: stm32: fix strsep failed on read only memory
  board: Add rt-thread art-pi board support

 arch/arm/dts/Makefile|   3 +-
 arch/arm/dts/stm32h7-pinctrl.dtsi| 274 
 arch/arm/dts/stm32h7-u-boot.dtsi | 100 +
 arch/arm/dts/stm32h743-pinctrl.dtsi  | 306 ---
 arch/arm/dts/stm32h743.dtsi  | 178 +++-
 arch/arm/dts/stm32h743i-disco-u-boot.dtsi|  98 +
 arch/arm/dts/stm32h743i-disco.dts|   2 +-
 arch/arm/dts/stm32h743i-eval-u-boot.dtsi |  98 +
 arch/arm/dts/stm32h743i-eval.dts |   2 +-
 arch/arm/dts/stm32h750.dtsi  |   5 +
 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi   |  81 +++
 arch/arm/dts/stm32h750i-art-pi.dts   | 188 
 arch/arm/mach-stm32/stm32h7/Kconfig  |   4 +
 board/st/stm32h750-art-pi/Kconfig|  19 ++
 board/st/stm32h750-art-pi/MAINTAINERS|   7 +
 board/st/stm32h750-art-pi/Makefile   |   6 +
 board/st/stm32h750-art-pi/stm32h750-art-pi.c |  58 +
 configs/stm32h750-art-pi_defconfig   |  51 +
 drivers/ram/stm32_sdram.c|   3 +
 include/configs/stm32h750-art-pi.h   |  48 +
 include/dt-bindings/memory/stm32-sdram.h |   2 +
 21 files changed, 1126 insertions(+), 407 deletions(-)
 create mode 100644 arch/arm/dts/stm32h7-pinctrl.dtsi
 delete mode 100644 arch/arm/dts/stm32h743-pinctrl.dtsi
 create mode 100644 arch/arm/dts/stm32h750.dtsi
 create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts
 create mode 100644 board/st/stm32h750-art-pi/Kconfig
 create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS
 create mode 100644 board/st/stm32h750-art-pi/Makefile
 create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c
 create mode 100644 configs/stm32h750-art-pi_defconfig
 create mode 100644 include/configs/stm32h750-art-pi.h

-- 
2.7.4



Re: [PATCH v3 02/11] clk: k210: Fix PLLs not being enabled

2021-04-09 Thread Damien Le Moal
On 2021/04/09 11:13, Sean Anderson wrote:
> After starting or setting the rate of a PLL, the enable bit must be set.
> 
> This fixes a bug where the AI ram would not be accessible, because it
> requires PLL1 to be running.
> 
> Signed-off-by: Sean Anderson 
> ---
> 
> (no changes since v1)
> 
>  drivers/clk/kendryte/pll.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c
> index ab6d75d585..f198920113 100644
> --- a/drivers/clk/kendryte/pll.c
> +++ b/drivers/clk/kendryte/pll.c
> @@ -531,6 +531,7 @@ static int k210_pll_enable(struct clk *clk)
>   k210_pll_waitfor_lock(pll);
>  
>   reg &= ~K210_PLL_BYPASS;
> + reg |= K210_PLL_EN;
>   writel(reg, pll->reg);
>  
>   return 0;
> @@ -550,6 +551,7 @@ static int k210_pll_disable(struct clk *clk)
>   writel(reg, pll->reg);
>  
>   reg &= ~K210_PLL_PWRD;
> + reg &= ~K210_PLL_EN;
>   writel(reg, pll->reg);
>   return 0;
>  }
> 

Looks good. That matches what the linux driver is doing.

Reviewed-by: Damien Le Moal 


-- 
Damien Le Moal
Western Digital Research


Pull request: u-boot-imx u-boot-imx-20210409

2021-04-09 Thread Stefano Babic

Hi Tom,

please pull from u-boot-imx, thanks !

The following changes since commit e9c99db7787e3b5c2ef05701177c43ed1c023c27:

  Merge branch '2021-04-07-CI-improvements' (2021-04-07 15:54:07 -0400)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git 
tags/u-boot-imx-20210409


for you to fetch changes up to 2fc93e5bafdae7cf6373479e054e9f3943fde23c:

  imx: bootaux fix elf loading (2021-04-08 23:59:50 +0200)


u-boot-imx-20210409
---

- Secure Boot :
- HAB for MX8M / MX7ULP
- CAAM fixes
- Fixes for imxrt1020
- Fixes for USDHC driver
- Fixes for Toradex (Colibri / Apalis)
- Switch to DM for several boards
- mx23 olinuxo
- usbarmory
- marsboard / riotboard
- Gateworks GW Ventana
- NXP upstream patches (LPDDR / CAAM / HAB)

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7089


Adam Ford (2):
  arm: dts: imx8mn, imx8mn-beacon: Sync dts files with Kernel 5.12-rc5
  configs: imx8mn_beacon: Enable QSPI Support

Aymen Sghaier (5):
  crypto: caam: Add CAAM support to i.MX8M platforms
  crypto: caam: Fix build warnings pointer casting
  crypto: Add blob command support for i.MX8M platforms
  crypto: caam: Fix pointer size to 32bit for i.MX8M
  crypto: caam: Add secure memory vid 3 support

Breno Lima (13):
  imx: imx7 Support for Manufacturing Protection
  imx: Avoid hardcoded output ring size register offset (ORSR)
  imx: Ensure CAAM clock is enabled prior getting out_jr_size
  imx: Avoid hardcoded Job Ring Max size
  imx: hab: Enable hab.c to authenticate additional images in open 
configuration

  imx: hab: Check if IVT header is HABv4
  mx7ulp: hab: Add hab_status command for HABv4 M4 boot
  imx: hab: Fix build warnings in 32-bit targets
  crypto: fsl: blob: Flush dcache range for destination address
  mx6dq: hab: Fix chip version in hab.h code
  cmd: blob: Add IMX_HAB and CAAM supported SoCs as dependency
  cmd: blob: Instantiate RNG before running CMD_BLOB
  fsl_mfgprot: Fix typo in sign_mppubk()

Clement Faure (2):
  imx8m: Add DEK blob encapsulation for imx8m
  imx8: Add DEK blob encapsulation

Clement Le Marquis (1):
  imx: caam: new u-boot command to set PRIBLOB bitfield from CAAM 
SCFGR register to 0x3


Fabio Estevam (2):
  MAINTAINERS: Use my personal e-mail address
  pico-imx6ul: Pass the PMIC I2C address in pmic_get()

Franck LENORMAND (3):
  crypto: caam: change JR running loop
  caam: enable support for iMX7ULP
  imx7ulp: Enable support for cmd blob

Giulio Benetti (3):
  board: freescale: imxrt1020-evk: fix console is not enabled while 
init dram
  board: freescale: imxrt1050-evk: fix console is not enabled while 
init dram
  board: st: stm32f746-disco: fix console is not enabled while init 
dram


Haibo Chen (3):
  mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card 
clock output

  mmc: fsl_esdhc_imx: remove redundant cmd11 related code.
  mmc: fsl_esdhc_imx: add extra delay for IO voltage switch if 
necessary


Heinrich Schuchardt (1):
  imx6: icorem6: chmod 644 enigcam.bmp

Igor Opaniuk (1):
  colibri_imx6: adjust boot order

Jacky Bai (1):
  imx8mn: Update the DDR4 timing script on imx8mn ddr4 evk

Marek Vasut (2):
  ARM: imx: Add OCRAM_S into iMX8M MMU tables
  doc: imx: psb: Document usage of SRC_GPR10 PERSIST_SECONDARY_BOOT 
for A/B switching


Max Krummenacher (1):
  imx: bootaux fix elf loading

Niel Fourie (1):
  ARM: pcm058: Match mainline Linux NAND ECC layout/behaviour

Oleksandr Suvorov (2):
  apalis/colibri_imx6: remove video= settings
  board: toradex: apalis-imx8x: fix build instructions

Peng (1):
  imx8mn: evk: update MAINTAINERS

Peng Fan (20):
  tools: imx image: fix write warning
  imx8mm/p: remove boot.cmd
  imx8mm_evk: add/cleanup variable for distro
  imx8mp_evk: add/cleanup variable for distro
  imx8mp_evk: spl: clean up including headers
  imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage
  power: pca9450: add a new parameter for power_pca9450_init
  imx8mn_evk: drop duplicated code
  imx8mn: Add LPDDR4 EVK board support
  imx8m: soc: update fuse path
  arch: mach-imx: imx8m: fix unique_id read error for imx8mp
  imx8m: add regs used by CAAM
  imx: HAB: Update hab codes to support ARM64 and i.MX8M
  imx8mm_evk: switch to use binman to pack images
  doc: imx8mm_evk: update doc after using binman
  imx8mn-ddr4-evk: switch to use binman
  imx8mn-evk: switch to use binman
  doc: imx8mn_evk: update doc after using binman
  imx8mp-evk: switch to use binman
  doc: imx8mp-evk: update after using binman

Peter Robinson (15):
  ARM: board:

Re: [PATCH] board: novtech: meerkat96: Add environment variables

2021-04-09 Thread Stefano Babic

Hi Carl,

do you used git send-email for this ? It looks like the patch was 
changed by your mailer, I cannot applied it with git am ("malformed 
patch"). Can you check and resend, maybe with git send-email ?


Best regards,
SAtefano Babic

On 04.04.21 21:47, Carl Gelfand wrote:

Add environment variables for booting Linux on  imx7d-meerkat96.

Signed-off-by: Carl Gelfand 
---
  include/configs/meerkat96.h | 16 +++-
  1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h
index f43a8415e1..f3a6906054 100644
--- a/include/configs/meerkat96.h
+++ b/include/configs/meerkat96.h
@@ -33,7 +33,21 @@
 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

  /* Environment configs */
-
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "image=zImage\0" \
+   "console=ttymxc5\0" \
+   "bootcmd=mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan;
then if run loadimage; then run mmcboot; else run netboot; fi; else
run netboot; fi\0" \
+   "fdt_addr=0x8300\0" \
+   "fdt_file=imx7d-meerkat96.dtb\0" \
+   "loadaddr=0x8080\0" \
+   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+   "mmcargs=setenv bootargs console=${console},${baudrate}
root=${mmcroot}\0" \
+   "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+   "boot_fdt=try\0" \
+   "mmcboot=echo Booting from mmc ...; run mmcargs; if test
${boot_fdt} = yes || test ${boot_fdt} = try; then if run loadfdt; then
bootz ${loadaddr} - ${fdt_addr}; else if test ${boot_fdt} = try; then
bootz; else echo WARN: Cannot load the DT; fi; fi; else bootz; fi;\0"
\
+   "mmcdev=0\0" \
+   "mmcpart=1\0" \
  /* USB configs */
  #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
--
2.20.1




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Re: [PATCH 0/5] Add support for embedding public key in platform's dtb

2021-04-09 Thread Sughosh Ganu
hi Simon,

On Fri, 9 Apr 2021 at 05:26, Simon Glass  wrote:

> Hi Sughosh,
>
> On Thu, 8 Apr 2021 at 18:53, Sughosh Ganu  wrote:
> >
> > hi Simon,
> >
> > On Wed, 7 Apr 2021 at 21:44, Simon Glass  wrote:
> >>
> >> Hi,
> >>
> >> On Wed, 7 Apr 2021 at 23:54, Sughosh Ganu 
> wrote:
> >> >
> >> > Patch 1 fixes an issue of selection of IMAGE_SIGN_INFO config option
> >> > when capsule authentication is enabled.
> >> >
> >> > Patch 2 add two config symbols, EFI_PKEY_DTB_EMBED and EFI_PKEY_FILE
> >> > which are used for enabling embedding of the public key in the dtb,
> >> > and specifying the esl file name.
> >> >
> >> > Patch 3 moves efi_capsule_auth_enabled as a weak function, which can
> >> > be used as a default mechanism for checking if capsule authentication
> >> > has been enabled.
> >> >
> >> > Patch 4 adds a default weak function for retrieving the public key
> >> > from the platform's dtb.
> >> >
> >> > Patch 5 adds the functionality to embed the esl file into the
> >> > platform's dtb during the platform build.
> >> >
> >> > I have tested this functionality on the STM32MP157C DK2 board.
> >> >
> >> > [1] - https://lists.denx.de/pipermail/u-boot/2021-March/442867.html
> >> >
> >> > Sughosh Ganu (5):
> >> >   efi_loader: Kconfig: Select IMAGE_SIGN_INFO when capsule
> >> > authentication is enabled
> >> >   efi_loader: Kconfig: Add symbols for embedding the public key into
> the
> >> > platform's dtb
> >> >   efi_capsule: Add a weak function to check whether capsule
> >> > authentication is enabled
> >> >   efi_capsule: Add a weak function to get the public key needed for
> >> > capsule authentication
> >> >   Makefile: Add provision for embedding public key in platform's dtb
> >> >
> >> >  Makefile  | 10 ++
> >> >  board/emulation/common/qemu_capsule.c |  6 
> >> >  lib/efi_loader/Kconfig| 16 ++
> >> >  lib/efi_loader/efi_capsule.c  | 44
> ---
> >> >  4 files changed, 66 insertions(+), 10 deletions(-)
> >> >
> >> > --
> >> > 2.17.1
> >> >
> >>
> >> We need to rethink the use of weak functions for this sort of thing,
> >> or we will end up with an unnavigable mess at some point. If we need
> >> to adjust the flow of boot, let's adjust the flow rather than adding
> >> hooks everywhere.
> >
> >
> > There are two weak functions being added. One is for retrieving the
> public key to be used for the capsule authentication, and the other is for
> checking for whether capsule authentication has been enabled. The reason
> why a weak function is needed is because platforms can have other
> mechanisms for retrieval of the public key or for testing if capsule
> authentication has been enabled.
> >
> > If we consider the case of public key retrieval, the majority of
> platforms would be built with the device tree concatenated with the u-boot
> binary. The weak function would cater to all of those platforms -- having a
> weak function would mean that we are not required to repeat the same
> functionality for every platform that uses the same mechanism for
> extracting the public key. However, there would be platforms where the
> public key is obtained through a different mechanism which is platform
> specific. Those platforms would have to define their own function to get
> the public key. Same for checking whether capsule authentication feature
> has been enabled or not.
> >
> > -sughosh
>
> Yes, I get it, but if this is to be a critical feature and part of the
> grand new design for verified boot using UEFI, surely we should be
> building a new front door, not digging a tunnel in the bathroom :-)
>
> We can either use drivers with driver model, or perhaps have a Kconfig
> that enables calling the function (so we get a link error if not
> provided). Or if there will be more than one handler, a linker_list.
>

I will use the Kconfig symbol for selecting the function to use for
retrieving the public key. So, in the current scenario, the function would
be under the CONFIG_EFI_PKEY_DTB_EMBED symbol. This should cater to the
majority of the cases. If some platform wants to use a different method to
get the public key, it would need to define it's own function.

-sughosh


>
> Perhaps it is time to consider a 'hook' system, with a command to let
> us see what hooks are active for any particular event?
>
> Regards,
> Simon
>


[PATCH] pico-imx6ul: Pass the PMIC I2C address in pmic_get()

2021-04-09 Thread sbabic
> Pass "pfuze3000@8" in pmic_get() so that the PMIC node can
> be found in the devicetree.
> Signed-off-by: Fabio Estevam 
> Reviewed-by: Jaehoon Chung 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH 1/1] imx6: icorem6: chmod 644 enigcam.bmp

2021-04-09 Thread sbabic
> Bitmap files should not be executable.
> Signed-off-by: Heinrich Schuchardt 
> Reviewed-by: Michael Trimarchi 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH] doc: imx: psb: Document usage of SRC_GPR10 PERSIST_SECONDARY_BOOT for A/B switching

2021-04-09 Thread sbabic
> Document SRC_GPR10 PERSIST_SECONDARY_BOOT functionality. This is useful for
> reliable bootloader A/B updates, as it permits switching between two copies
> of bootloader at different offsets of the same storage. The switch happens
> in case one copy is corrupted OR can be enforced by user. This functionality
> is present at least since i.MX53, however is poorly documented in all known
> SoC datasheets, hence this document aims to clarify the usage, currently on
> i.MX7D and i.MX8MM.
> Signed-off-by: Marek Vasut  # Original MX7D work, this document
> Signed-off-by: Igor Opaniuk  # All the MX8M work
> Cc: Christoph Niedermaier 
> Cc: Fabio Estevam 
> Cc: Harald Seiler 
> Cc: Igor Opaniuk 
> Cc: Jan Kiszka 
> Cc: Ludwig Zenz 
> Cc: Marcel Ziswiler 
> Cc: Peng Fan 
> Cc: Stefano Babic 
> Cc: Ye Li 
> Cc: uboot-imx 
> Reviewed-by: Peng Fan 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH] imx: imx6ull: fix pinmux sel_input value for uart5 pins

2021-04-09 Thread sbabic
> sel_input value for the following uart5 pins is
> different between i.MX6UL and i.MX6ULL:
> MX6_PAD_UART5_TX_DATA__UART5_DTE_RX
> MX6_PAD_UART5_RX_DATA__UART5_DCE_RX
> MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS
> MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS
> MX6_PAD_CSI_DATA02__UART5_DCE_RTS
> As sel_input value for the second one is fixed by
> the previous commit, fix the rest.
> Signed-off-by: Yuichiro Goto 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH v2 2/2] mx23_olinuxino: convert MMC to driver model

2021-04-09 Thread sbabic
> Convert the Olimex Olinuxino board's support for MMC to driver model following
> Fabio Estevam's excellent example from:
>   commit: 23013aa9619881290dbeb6217f1fab863869050e:
>   mx23evk: Convert to driver model
> Signed-off-by: Trevor Woerner 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH 2/2] mmc: fsl_esdhc_imx: add extra delay for IO voltage switch if necessary

2021-04-09 Thread sbabic
> From: Haibo Chen 
> Some board like imx8mm-evkb, IO voltage switch from 3.3v to 1.8v need
> around 18ms, common code only delay 10ms, so need to delay extra 8ms.
> Otherwise voltage switch will timeout when wait for data0 line.
> This IO voltage switch time depends on board design, depend on the
> PMIC and capacitance. imx8mm-evkb board use PCA9450(PMIC) and 10uF
> capacitance.
> Signed-off-by: Haibo Chen 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH v1] imx: bootaux fix elf loading

2021-04-09 Thread sbabic
> This reverts the arch/arm/mach-imx/imx_bootaux.c changes of commit
> 805b3cac1e0c. The loader function name was changed so that it does
> not clash with the generically available function in lib/elf.c.
> imx-bootaux loads an elf file linked for an auxilary core. Thus the
> loader function requires address translation from the auxilary core's
> address space to where those are mapped into U-Boot's address space.
> So the elf loader is specific and must not be replaced with a generic
> loader which doesn't provide the address translation functionality.
> Fixes commit 805b3cac1e0c ("lib: elf: Move the generic elf
> loading/validating functions to lib")
> Signed-off-by: Max Krummenacher 
> Acked-by: Oleksandr Suvorov 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH v2 1/2] mx23_olinuxino: enable device tree

2021-04-09 Thread sbabic
> Add the dts file for the Olimex Olinuxino from the linux kernel, and enable
> its use in this machine's defconfig.
> Signed-off-by: Trevor Woerner 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH 1/2] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output

2021-04-09 Thread sbabic
> From: Haibo Chen 
> For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these
> are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the
> card clock output.
> After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"),
> we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because
> the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during
> voltage switch, need to gate off/on the card clock. If not set the 
> FRC_SDCLK_ON,
> after CMD11, hardware will gate off the card clock automatically, so card do
> not detect the clock off/on behavior, so will draw the data0 line low until
> next command.
> Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support")
> Tested-by: Tim Harvey 
> Signed-off-by: Haibo Chen 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH] ARM: pcm058: Match mainline Linux NAND ECC layout/behaviour

2021-04-09 Thread sbabic
> Enabled "fsl,legacy-bch-geometry" in U-Boot device tree overlay
> to match the legacy BCH geometry layout, which mainline Linux
> applies when "fsl,use-minimum-ecc" is not specified in the device
> tree.
> Reinstated SYS_NAND_ONFI_DETECTION, which when disabled, masked
> the mismatch on SOMs with Winbond NAND flash chips.
> Signed-off-by: Niel Fourie 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH 1/2] mmc: fsl_esdhc_imx: remove redundant cmd11 related code.

2021-04-09 Thread sbabic
> From: Haibo Chen 
> Common code already handle the voltage switch sequence based on spec,
> so remove the redundant voltage switch code.
> Signed-off-by: Haibo Chen 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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Re: [PATCH v1 1/2] cmd: bind: Fix driver binding on a device

2021-04-09 Thread Andy Shevchenko
On Fri, Apr 9, 2021 at 1:32 PM Patrice CHOTARD
 wrote:
> On 4/9/21 11:48 AM, Andy Shevchenko wrote:
> > On Fri, Apr 9, 2021 at 12:28 PM Patrice CHOTARD
> >  wrote:
> >> On 4/9/21 11:16 AM, Andy Shevchenko wrote:
> >>> On Fri, Apr 9, 2021 at 10:37 AM Patrice Chotard
> >>>  wrote:

...

>  +   if (drv) {
>  +   if (drv == entry)
>  +   break;
> >>>
>  +   } else {
>  +   if (!ret)
>  +   break;
>  +   }
> >>>
> >>> This can be simplified to
> >>> } else if (!ret)
> >>>   break;
> >>
> >> I know but checkpatch.pl requested it ;-)
> >
> > You mean it doesn't recognize 'else if' construction? Then it's a bug
> > there for sure.
> >
>
> No, i mean checkpath.pl request to put {} on all statements as shown below :
>
> ./scripts/checkpatch.pl 0001-cmd-bind-Fix-driver-binding-on-a-device.patch
> CHECK: braces {} should be used on all arms of this statement
> #83: FILE: drivers/core/lists.c:228:
> +   if (drv) {
> [...]
> +   } else if (!ret)

So, you still can put else and if on one line, right?

-- 
With Best Regards,
Andy Shevchenko


[PATCH 1/1] cmd/exception: support ebreak exception on RISC-V

2021-04-09 Thread Heinrich Schuchardt
The ebreak instruction should generate a breakpoint exception.

Signed-off-by: Heinrich Schuchardt 
---
 cmd/riscv/exception.c   | 10 ++
 doc/usage/exception.rst |  3 +++
 2 files changed, 13 insertions(+)

diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c
index 9687cec812..7a08061d12 100644
--- a/cmd/riscv/exception.c
+++ b/cmd/riscv/exception.c
@@ -8,6 +8,13 @@
 #include 
 #include 

+static int do_ebreak(struct cmd_tbl *cmdtp, int flag, int argc,
+   char *const argv[])
+{
+   asm volatile ("ebreak\n");
+   return CMD_RET_FAILURE;
+}
+
 static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
 {
@@ -28,6 +35,8 @@ static int do_undefined(struct cmd_tbl *cmdtp, int flag, int 
argc,
 }

 static struct cmd_tbl cmd_sub[] = {
+   U_BOOT_CMD_MKENT(ebreak, CONFIG_SYS_MAXARGS, 1, do_ebreak,
+"", ""),
U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned,
 "", ""),
U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
@@ -37,6 +46,7 @@ static struct cmd_tbl cmd_sub[] = {
 static char exception_help_text[] =
"\n"
"  The following exceptions are available:\n"
+   "  ebreak- breakpoint\n"
"  undefined - illegal instruction\n"
"  unaligned - load address misaligned\n"
;
diff --git a/doc/usage/exception.rst b/doc/usage/exception.rst
index db1490f005..27df88bd5c 100644
--- a/doc/usage/exception.rst
+++ b/doc/usage/exception.rst
@@ -31,6 +31,9 @@ type

   **RISC-V:**

+  ebreak
+breakpoint exception
+
   unaligned
 load address misaligned

--
2.31.0



Re: [PATCH v1 1/2] cmd: bind: Fix driver binding on a device

2021-04-09 Thread Patrice CHOTARD



On 4/9/21 11:48 AM, Andy Shevchenko wrote:
> On Fri, Apr 9, 2021 at 12:28 PM Patrice CHOTARD
>  wrote:
>> On 4/9/21 11:16 AM, Andy Shevchenko wrote:
>>> On Fri, Apr 9, 2021 at 10:37 AM Patrice Chotard
>>>  wrote:
> 
> ...
> 
 +   if (drv) {
 +   if (drv == entry)
 +   break;
>>>
 +   } else {
 +   if (!ret)
 +   break;
 +   }
>>>
>>> This can be simplified to
>>> } else if (!ret)
>>>   break;
>>
>> I know but checkpatch.pl requested it ;-)
> 
> You mean it doesn't recognize 'else if' construction? Then it's a bug
> there for sure.
> 

No, i mean checkpath.pl request to put {} on all statements as shown below :

./scripts/checkpatch.pl 0001-cmd-bind-Fix-driver-binding-on-a-device.patch 
CHECK: braces {} should be used on all arms of this statement
#83: FILE: drivers/core/lists.c:228:
+   if (drv) {
[...]
+   } else if (!ret)
[...]

total: 0 errors, 0 warnings, 1 checks, 100 lines checked




Re: Running u-boot 2021.04 on Raspberry Pi 4

2021-04-09 Thread Matthias Brugger



On 09/04/2021 10:14, Nicolas Saenz Julienne wrote:
> [ Adding Matthias for the SMBIOS part ]
> 
> On Fri, 2021-04-09 at 00:00 -0700, Roman Shaposhnik wrote:
>> On Thu, Apr 8, 2021 at 8:59 PM Sean Anderson  wrote:
>>> On 4/8/21 8:18 PM, Roman Shaposhnik wrote:
 Hi!

 first time poster, long time lurker here. Over at Project EVE
 https://github.com/lf-edge/eve I've been trying to migrate
 from our current u-boot v2020.07 + patches:

 https://github.com/lf-edge/eve/tree/master/pkg/u-boot/patches/patches-v2020.07
 to the latest u-boot 2021.04.

 Great news is that most of the patches we dependent
 on seem to have been pulled upstream. However, this
 single *chunk* of one patchset wasn't:

 https://github.com/lf-edge/eve/blob/master/pkg/u-boot/patches/patches-v2020.07/0001-usb-xhci-Load-Raspberry-Pi-4-VL805-s-firmware.patch#L293

 I'm wondering what was the reason for leaving it behind,
>>>
>>> +CC Nicolas
>>>
   - Get rid of PCI core patch as not needed with correct DT PCI topology 
>>>
>>> also from the cover letter
>>>
 This also depends on a DT/bindings patch available on the linux-mailing 
 lists:
 https://www.mail-archive.com/linux-kernel@.../msg2205783.html
>>>
>>> The merged version of this series is
>>>
>>> https://patchwork.kernel.org/project/linux-usb/list/?series=310015&state=%2A&archive=both
>>>
 Here is the relevant bit for reference/discussion:

          &pcie0 {
                 pci@1,0 {
                         #address-cells = <3>;
                         #size-cells = <2>;
                         ranges;

                         reg = <0 0 0 0 0>;

                         usb@1,0 {
                                 reg = <0x1 0 0 0 0>;
                                 resets = <&reset 
 RASPBERRYPI_FIRMWARE_RESET_ID_USB>;
                         };
                 };
          };
>>>
> 
> Yes, instead of using a PCI quirk we settled on a reset controller. All in all
> it is less hacky. But needs changes in DT.
> 
>> Aha! Thank you so much -- this is super helpful!
>>  
 since without it I don't seem to have functioning USB
 devices on my  Raspberry Pi 4. In fact, adding it back:

 https://github.com/rvs/eve/tree/u-boot/pkg/u-boot/patches/patches-v2021.04
 (just that one chunk -- 'cuz the reset got upstreamed)
 seems to solve the issue for me.

 Another question I have is that the new u-boot seems to have
 some kind of a regression that I can't quite debug. The SMBIOS
 tables that it constructs during EFI boot sequence seem to be
 broken (see the dmidecode output below). Again, this seems
 to be a regression compared to  v2020.07. Any ideas on what
 could be wrong or how can I start debugging it would be
>>>

Yes, that's not working right now. I'm working on a fix for the tables:
https://patchwork.ozlabs.org/project/uboot/patch/20210406090435.19357-1-matthias@kernel.org/

This will fix the error en dmidecode but the tables will be basically empty.
Before that there was some information that helped you to identify that you are
running on a RaspberryPi.

A quick fix would be to add that information to the DTS. Like for example done 
here:
https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/rk3328-rock64-u-boot.dtsi#L13

On the long run we want to add a sysinfo driver to read the information for the
mailbox driver and use that. But my understanding is that for that we would need
to create a SPL for the mailbox driver to provide that info in a shared data
structure. It's still on my list for investigation.

Regards,
Matthias

>>> You can always bisect it ;)
>>>
>>
>>
>> LOL -- true! I was just hoping someone would recognize the issue perhaps.
>>
>> Thanks,
>> Roman. 
> 
> 



Re: [PATCH 2/2] stm32mp: replace printf by log macro in setup_boot_mode

2021-04-09 Thread Patrice CHOTARD
Hi Patrick

On 4/6/21 9:27 AM, Patrick Delaunay wrote:
> Replace the remaining printf in setup_boot_mode() by log macro
> to handle filtering for log features.
> 
> Signed-off-by: Patrick Delaunay 
> ---
> 
>  arch/arm/mach-stm32mp/cpu.c | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
> index 2f05c5e91b..621a6b7c89 100644
> --- a/arch/arm/mach-stm32mp/cpu.c
> +++ b/arch/arm/mach-stm32mp/cpu.c
> @@ -502,8 +502,8 @@ static void setup_boot_mode(void)
>   if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
>   gd->flags &= ~(GD_FLG_SILENT |
>  GD_FLG_DISABLE_CONSOLE);
> - printf("uart%d = %s not found in device tree!\n",
> -instance + 1, cmd);
> + log_err("uart%d = %s not found in device tree!\n",
> + instance + 1, cmd);
>   break;
>   }
>   sprintf(cmd, "%d", dev_seq(dev));
> @@ -514,7 +514,7 @@ static void setup_boot_mode(void)
>   if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && 
> gd->cur_serial_dev != dev) {
>   gd->flags &= ~(GD_FLG_SILENT |
>  GD_FLG_DISABLE_CONSOLE);
> - printf("serial boot with console enabled!\n");
> + log_info("serial boot with console enabled!\n");
>   }
>   break;
>   case BOOT_SERIAL_USB:
> @@ -546,7 +546,7 @@ static void setup_boot_mode(void)
>  
>   switch (forced_mode) {
>   case BOOT_FASTBOOT:
> - printf("Enter fastboot!\n");
> + log_info("Enter fastboot!\n");
>   env_set("preboot", "env set preboot; fastboot 0");
>   break;
>   case BOOT_STM32PROG:
> @@ -556,7 +556,7 @@ static void setup_boot_mode(void)
>   case BOOT_UMS_MMC0:
>   case BOOT_UMS_MMC1:
>   case BOOT_UMS_MMC2:
> - printf("Enter UMS!\n");
> + log_info("Enter UMS!\n");
>   instance = forced_mode - BOOT_UMS_MMC0;
>   sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
>   env_set("preboot", cmd);
> 
Applied to u-boot-stm/master

Thanks
Patrice


Re: [PATCH 1/2] stm32mp: update uart number in trace of serial device not found

2021-04-09 Thread Patrice CHOTARD
Hi Patrick

On 4/6/21 9:27 AM, Patrick Delaunay wrote:
> Align the uart number in the trace of setup_boot_mode() with the name of
> the uart/usart device (start at 1) and not with the instance value
> (start at 0), i.e. the serial device sequence number and the index in
> serial_addr[].
> 
> Fixes: f49eb16c17e2c ("stm32mp: stm32prog: replace alias by serial
> device sequence number")
> 
> Signed-off-by: Patrick Delaunay 
> ---
> 
>  arch/arm/mach-stm32mp/cpu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
> index 897ec13ad8..2f05c5e91b 100644
> --- a/arch/arm/mach-stm32mp/cpu.c
> +++ b/arch/arm/mach-stm32mp/cpu.c
> @@ -503,7 +503,7 @@ static void setup_boot_mode(void)
>   gd->flags &= ~(GD_FLG_SILENT |
>  GD_FLG_DISABLE_CONSOLE);
>   printf("uart%d = %s not found in device tree!\n",
> -instance, cmd);
> +instance + 1, cmd);
>   break;
>   }
>   sprintf(cmd, "%d", dev_seq(dev));
> 
Applied to u-boot-stm/master

Thanks
Patrice


Re: [PATCH] stm32mp: stm32prog: add FIP header support

2021-04-09 Thread Patrice CHOTARD
Hi Patrick

On 4/2/21 2:05 PM, Patrick Delaunay wrote:
> Add support of TF-A FIP header in command stm32prog for all the boot
> partition and not only the STM32IMAGE.
> 
> This patch is a preliminary patch to support FIP as second boot stage
> after TF-A BL2 when CONFIG_TFABOOT is activated for trusted boot chain.
> 
> The FIP is archive binary loaded by TF-A BL2, which contains the secure OS
> = OP-TEE and the non secure firmware and device tree = U-Boot.
> 
> Signed-off-by: Patrick Delaunay 
> ---
> 
>  .../cmd_stm32prog/cmd_stm32prog.c | 19 +++---
>  .../mach-stm32mp/cmd_stm32prog/stm32prog.c| 59 +--
>  .../mach-stm32mp/cmd_stm32prog/stm32prog.h| 12 +++-
>  .../cmd_stm32prog/stm32prog_serial.c  | 11 ++--
>  4 files changed, 64 insertions(+), 37 deletions(-)
> 
> diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c 
> b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
> index a7e2861764..e36501a86b 100644
> --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
> +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
> @@ -73,15 +73,16 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, 
> int argc,
>   size = simple_strtoul(argv[4], NULL, 16);
>  
>   /* check STM32IMAGE presence */
> - if (size == 0 &&
> - !stm32prog_header_check((struct raw_header_s *)addr, &header)) {
> - size = header.image_length + BL_HEADER_SIZE;
> -
> - /* uImage detected in STM32IMAGE, execute the script */
> - if (IMAGE_FORMAT_LEGACY ==
> - genimg_get_format((void *)(addr + BL_HEADER_SIZE)))
> - return image_source_script(addr + BL_HEADER_SIZE,
> -"script@1");
> + if (size == 0) {
> + stm32prog_header_check((struct raw_header_s *)addr, &header);
> + if (header.type == HEADER_STM32IMAGE) {
> + size = header.image_length + BL_HEADER_SIZE;
> +
> + /* uImage detected in STM32IMAGE, execute the script */
> + if (IMAGE_FORMAT_LEGACY ==
> + genimg_get_format((void *)(addr + BL_HEADER_SIZE)))
> + return image_source_script(addr + 
> BL_HEADER_SIZE, "script@1");
> + }
>   }
>  
>   if (IS_ENABLED(CONFIG_DM_VIDEO))
> diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c 
> b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
> index d0518d1223..4c4d8a7a69 100644
> --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
> +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
> @@ -60,8 +60,6 @@ static const efi_guid_t uuid_mmc[3] = {
>   ROOTFS_MMC2_UUID
>  };
>  
> -DECLARE_GLOBAL_DATA_PTR;
> -
>  /* order of column in flash layout file */
>  enum stm32prog_col_t {
>   COL_OPTION,
> @@ -73,6 +71,16 @@ enum stm32prog_col_t {
>   COL_NB_STM32
>  };
>  
> +#define FIP_TOC_HEADER_NAME  0xAA640001
> +
> +struct fip_toc_header {
> + u32 name;
> + u32 serial_number;
> + u64 flags;
> +};
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
>  /* partition handling routines : CONFIG_CMD_MTDPARTS */
>  int mtdparts_init(void);
>  int find_dev_and_part(const char *id, struct mtd_device **dev,
> @@ -88,46 +96,57 @@ char *stm32prog_get_error(struct stm32prog_data *data)
>   return data->error;
>  }
>  
> -u8 stm32prog_header_check(struct raw_header_s *raw_header,
> -   struct image_header_s *header)
> +static bool stm32prog_is_fip_header(struct fip_toc_header *header)
> +{
> + return (header->name == FIP_TOC_HEADER_NAME) && header->serial_number;
> +}
> +
> +void stm32prog_header_check(struct raw_header_s *raw_header,
> + struct image_header_s *header)
>  {
>   unsigned int i;
>  
> - header->present = 0;
> + if (!raw_header || !header) {
> + log_debug("%s:no header data\n", __func__);
> + return;
> + }
> +
> + header->type = HEADER_NONE;
>   header->image_checksum = 0x0;
>   header->image_length = 0x0;
>  
> - if (!raw_header || !header) {
> - log_debug("%s:no header data\n", __func__);
> - return -1;
> + if (stm32prog_is_fip_header((struct fip_toc_header *)raw_header)) {
> + header->type = HEADER_FIP;
> + return;
>   }
> +
>   if (raw_header->magic_number !=
>   (('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) {
>   log_debug("%s:invalid magic number : 0x%x\n",
> __func__, raw_header->magic_number);
> - return -2;
> + return;
>   }
>   /* only header v1.0 supported */
>   if (raw_header->header_version != 0x0001) {
>   log_debug("%s:invalid header version : 0x%x\n",
> __func__, raw_header->header_version);
> - return -3;
> + return;
>   

Re: [PATCH 3/3] configs: stm32mp1: Fix misleading SPL size limitations

2021-04-09 Thread Patrice CHOTARD
Hi Alexandru

On 3/22/21 2:20 PM, Alexandru Gagniuc wrote:
> A now removed comment promises to "limit SYSRAM usage to first 128 KB".
> This would imply that only SYSRAM from 0x2ffc - 0x2ffe would be
> used. This is not what happens at all.
> 
> First, SPL_MAX_SIZE is referenced from SPL_TEXT_BASE, which on all
> existing configs is set to 0x2ffc2500, not SYSRAM_BASE (0x2ffc).
> Some of it is in the first 128 KiB and some of it is in the second
> 128 KiB chunk of SYSRAM.
> 
> Second, SPL_MAX_SIZE, does not restrict the BSS size. While a valiant
> attempt is made via SPL_BSS_MAX_SIZE, the value of 0x0010 is much
> larger than SYSRAM, and doesn't account for the non-BSS sections.
> 
> Because we're putting the .text and .bss in the same boat, the correct
> way to limit them together is via SPL_MAX_FOOTPRINT. With the current
> SPL_TEXT_BASE, we couldn't limit even a very basic SPL to the first
> 128 KiB, and there is no technical reason to do so. Because of this,
> simply allow the SPL to use all SYSRAM.
> 
> Signed-off-by: Alexandru Gagniuc 
> ---
>  include/configs/stm32mp1.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
> index 56a70cb584..440efa1a55 100644
> --- a/include/configs/stm32mp1.h
> +++ b/include/configs/stm32mp1.h
> @@ -50,12 +50,12 @@
>  /* SPL support */
>  #ifdef CONFIG_SPL
>  /* SPL use DDR */
> -#define CONFIG_SPL_BSS_MAX_SIZE  0x0010
>  #define CONFIG_SYS_SPL_MALLOC_START  0xC030
>  #define CONFIG_SYS_SPL_MALLOC_SIZE   0x01D0
>  
> -/* limit SYSRAM usage to first 128 KB */
> -#define CONFIG_SPL_MAX_SIZE  0x0002
> +/* Restrict SPL to fit within SYSRAM */
> +#define STM32_SYSRAM_END (STM32_SYSRAM_BASE + STM32_SYSRAM_SIZE)
> +#define CONFIG_SPL_MAX_FOOTPRINT (STM32_SYSRAM_END - 
> CONFIG_SPL_TEXT_BASE)
>  #define CONFIG_SPL_STACK (STM32_SYSRAM_BASE + \
>STM32_SYSRAM_SIZE)
>  #endif /* #ifdef CONFIG_SPL */
> 
Applied to u-boot-stm/master

Thanks
Patrice


Re: [PATCH 2/3] configs: stm32mp1: Remove misleading CONFIG_SPL_BSS_START_ADDR

2021-04-09 Thread Patrice CHOTARD
Hi Alexandru

On 3/22/21 2:20 PM, Alexandru Gagniuc wrote:
> CONFIG_SPL_BSS_START_ADDR is only used on a few mach- linker scripts.
> stm32mp1 uses the generic script under arch/arm/cpu/u-boot-spl.lds,
> which does not make use of this definition.
> 
> The SPL BSS starts in SRAM, right after .text, .rodata, .data, and
> .u_boot_list. A very short version of the STM32MP1 memory map is:
>   * SYSRAM: 2ffc - 3000 <- all of SPL is here
>   * DRAM:   c000+
> 
> 0xC020 is a DRAM address, and has nothing to do with SPL. It is
> just very misleading to have it next to CONFIG_SPL_BSS_MAX_SIZE, or to
> have it at all.
> 
> Signed-off-by: Alexandru Gagniuc 
> ---
>  include/configs/stm32mp1.h | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
> index 7fdb3ffce4..56a70cb584 100644
> --- a/include/configs/stm32mp1.h
> +++ b/include/configs/stm32mp1.h
> @@ -50,7 +50,6 @@
>  /* SPL support */
>  #ifdef CONFIG_SPL
>  /* SPL use DDR */
> -#define CONFIG_SPL_BSS_START_ADDR0xC020
>  #define CONFIG_SPL_BSS_MAX_SIZE  0x0010
>  #define CONFIG_SYS_SPL_MALLOC_START  0xC030
>  #define CONFIG_SYS_SPL_MALLOC_SIZE   0x01D0
> 
Applied to u-boot-stm/master

Thanks
Patrice


Re: [PATCH 1/3] configs: stm32mp1: stm32mp1: Increase SPL malloc() size

2021-04-09 Thread Patrice CHOTARD
Hi Alexandru

On 3/22/21 2:19 PM, Alexandru Gagniuc wrote:
> Since commit 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer for
> loading images"), FIT images must be malloc()'d before being loaded.
> The old size of 1 MiB is suitable for FIT images with u-boot and an
> FDT, but something containing a linux kernel is almost sure to fail.
> 
> It's safe to extend malloc all the way to 0xc200, but no further.
> Linux likes to be loaded at 0xc200, so we use that as our cutoff
> point. This gives us 29 MiB of malloc() space, which suited for more
> complex FIT images including several DTBs, kernel, and OP-TEE images.
> 
> Signed-off-by: Alexandru Gagniuc 
> ---
>  include/configs/stm32mp1.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
> index db2117a3d7..7fdb3ffce4 100644
> --- a/include/configs/stm32mp1.h
> +++ b/include/configs/stm32mp1.h
> @@ -53,7 +53,7 @@
>  #define CONFIG_SPL_BSS_START_ADDR0xC020
>  #define CONFIG_SPL_BSS_MAX_SIZE  0x0010
>  #define CONFIG_SYS_SPL_MALLOC_START  0xC030
> -#define CONFIG_SYS_SPL_MALLOC_SIZE   0x0010
> +#define CONFIG_SYS_SPL_MALLOC_SIZE   0x01D0
>  
>  /* limit SYSRAM usage to first 128 KB */
>  #define CONFIG_SPL_MAX_SIZE  0x0002
> 

Applied to u-boot-stm/master

Thanks
Patrice


Re: [PATCH v3 8/8] board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

2021-04-09 Thread Patrice CHOTARD
Hi Jagan

On 3/16/21 5:22 PM, Jagan Teki wrote:
> 7" OF is a capacitive touch 7" Open Frame panel solutions with
> - 7" AUO B101AW03 LVDS panel
> - EDT, FT5526 Touch
> 
> MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.
> 
> MicroDev 2.0 is a general purpose miniature carrier board with CAN,
> LTE and LVDS panel interfaces.
> 
> MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
> pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0
> 7" Open Frame Solution board.
> 
> Linux dts commit details:
> 
> commit <1d278204cbaa> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
> MicroDev 2.0 7" OF")
> 
> Add support for it.
> 
> Reviewed-by: Patrick Delaunay 
> Reviewed-by: Patrice Chotard 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v3:
> - collect Patrice r-b
> Changes for v2:
> - collect Patrice r-b
> - add linux dts commit
> - drop CONFIG_BOARD_EARLY_INIT_F
> 
>  arch/arm/dts/Makefile |   1 +
>  ...rogea-stm32mp1-microdev2.0-of7-u-boot.dtsi |  51 ++
>  ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 154 ++
>  arch/arm/mach-stm32mp/Kconfig |   7 +
>  board/engicam/stm32mp1/MAINTAINERS|   6 +
>  ...-microgea-stm32mp1-microdev2-of7_defconfig |  79 +
>  6 files changed, 298 insertions(+)
>  create mode 100644 
> arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi
>  create mode 100644 
> arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
>  create mode 100644 
> configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 64d73b96ef..43c604f2f8 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -993,6 +993,7 @@ dtb-$(CONFIG_STM32MP15x) += \
>   stm32mp157a-icore-stm32mp1-ctouch2.dtb \
>   stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
>   stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
> + stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
>   stm32mp157c-dk2.dtb \
>   stm32mp157c-ed1.dtb \
>   stm32mp157c-ev1.dtb \
> diff --git 
> a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi 
> b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi
> new file mode 100644
> index 00..e4bd215812
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
> + * Copyright (c) 2020 Amarula Solutions(India)
> + * Author: Jagan Teki 
> + */
> +
> +#include "stm32mp157a-microgea-stm32mp1-u-boot.dtsi"
> +
> +/{
> + aliases {
> + mmc0 = &sdmmc1;
> + };
> +
> + chosen {
> + stdout-path = &uart4;
> + };
> +};
> +
> +&sdmmc1 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&sdmmc1_b4_pins_a {
> + u-boot,dm-pre-reloc;
> +
> + pins1 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + pins2 {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> +&uart4 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&uart4_pins_a {
> + u-boot,dm-pre-reloc;
> +
> + pins1 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + pins2 {
> + u-boot,dm-pre-reloc;
> + bias-pull-up;
> + };
> +};
> diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts 
> b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
> new file mode 100644
> index 00..674b2d330d
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
> @@ -0,0 +1,154 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
> + * Copyright (c) 2020 Engicam srl
> + * Copyright (c) 2020 Amarula Solutons(India)
> + */
> +
> +/dts-v1/;
> +#include "stm32mp157.dtsi"
> +#include "stm32mp157a-microgea-stm32mp1.dtsi"
> +#include "stm32mp15-pinctrl.dtsi"
> +#include "stm32mp15xxaa-pinctrl.dtsi"
> +#include 
> +
> +/ {
> + model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame";
> + compatible = "engicam,microgea-stm32mp1-microdev2.0-of7",
> +  "engicam,microgea-stm32mp1", "st,stm32mp157";
> +
> + aliases {
> + serial0 = &uart4;
> + serial1 = &uart8;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + backlight: backlight {
> + compatible = "gpio-backlight";
> + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>;
> + default-on;
> + };
> +
> + lcd_3v3: regulator-lcd-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "lcd_3v3";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>;
> + enable-active-hig

Re: [PATCH v3 7/8] board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board

2021-04-09 Thread Patrice CHOTARD
Hi Jagan

On 3/16/21 5:22 PM, Jagan Teki wrote:
> MicroDev 2.0 is a general purpose miniature carrier board with CAN,
> LTE and LVDS panel interfaces.
> 
> Genaral features:
> - Ethernet 10/100
> - USB Type A
> - Audio Out
> - microSD
> - LVDS panel connector
> - Wifi/BT (option)
> - UMTS LTE with sim connector (option)
> 
> MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.
> 
> MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
> for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.
> 
> Linux dts commit details:
> 
> commit  ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
> MicroDev 2.0 board")
> 
> Add support for it.
> 
> Reviewed-by: Patrick Delaunay 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v3:
> - include stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
> - include dts files in MAINTAINERS
> - collect Patrice r-b
> Changes for v2:
> - collect Patrice r-b
> - add linux dts commit
> - drop CONFIG_BOARD_EARLY_INIT_F
> 
>  arch/arm/dts/Makefile |   1 +
>  ...-microgea-stm32mp1-microdev2.0-u-boot.dtsi |  51 
>  ...32mp157a-microgea-stm32mp1-microdev2.0.dts |  55 
>  .../stm32mp157a-microgea-stm32mp1-u-boot.dtsi | 118 ++
>  arch/arm/mach-stm32mp/Kconfig |  20 +++
>  board/engicam/stm32mp1/Kconfig|   2 +-
>  board/engicam/stm32mp1/MAINTAINERS|   7 ++
>  ...mp15-microgea-stm32mp1-microdev2_defconfig |  79 
>  8 files changed, 332 insertions(+), 1 deletion(-)
>  create mode 100644 
> arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi
>  create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
>  create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi
>  create mode 100644 configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ce4521b891..64d73b96ef 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -992,6 +992,7 @@ dtb-$(CONFIG_STM32MP15x) += \
>   stm32mp157a-avenger96.dtb \
>   stm32mp157a-icore-stm32mp1-ctouch2.dtb \
>   stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
> + stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
>   stm32mp157c-dk2.dtb \
>   stm32mp157c-ed1.dtb \
>   stm32mp157c-ev1.dtb \
> diff --git 
> a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi 
> b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi
> new file mode 100644
> index 00..e4bd215812
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
> + * Copyright (c) 2020 Amarula Solutions(India)
> + * Author: Jagan Teki 
> + */
> +
> +#include "stm32mp157a-microgea-stm32mp1-u-boot.dtsi"
> +
> +/{
> + aliases {
> + mmc0 = &sdmmc1;
> + };
> +
> + chosen {
> + stdout-path = &uart4;
> + };
> +};
> +
> +&sdmmc1 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&sdmmc1_b4_pins_a {
> + u-boot,dm-pre-reloc;
> +
> + pins1 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + pins2 {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> +&uart4 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&uart4_pins_a {
> + u-boot,dm-pre-reloc;
> +
> + pins1 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + pins2 {
> + u-boot,dm-pre-reloc;
> + bias-pull-up;
> + };
> +};
> diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts 
> b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
> new file mode 100644
> index 00..7a75868164
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
> @@ -0,0 +1,55 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
> + * Copyright (c) 2020 Engicam srl
> + * Copyright (c) 2020 Amarula Solutons(India)
> + */
> +
> +/dts-v1/;
> +#include "stm32mp157.dtsi"
> +#include "stm32mp157a-microgea-stm32mp1.dtsi"
> +#include "stm32mp15-pinctrl.dtsi"
> +#include "stm32mp15xxaa-pinctrl.dtsi"
> +#include 
> +
> +/ {
> + model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board";
> + compatible = "engicam,microgea-stm32mp1-microdev2.0",
> +  "engicam,microgea-stm32mp1", "st,stm32mp157";
> +
> + aliases {
> + serial0 = &uart4;
> + serial1 = &uart8;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&sdmmc1 {
> + bus-width = <4>;
> + disable-wp;
> + pinctrl-names = "default", "opendrain", "sleep";
> + pinctrl-0 = <&sdmmc1_b4_pins_a>;
> + pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
> + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
> + st,neg-edge;
> + vmmc-

Re: [PATCH v3 6/8] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 Micro SoM

2021-04-09 Thread Patrice CHOTARD
Hi Jagan

On 3/16/21 5:22 PM, Jagan Teki wrote:
> MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.
> 
> General features:
> - STM32MP157AAC
> - Up to 1GB DDR3L-800
> - 512MB Nand flash
> - I2S
> 
> MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier
> boards for creating complete platform solutions.
> 
> Linux dts commit details:
> 
> commit <0be81dfaeaf8> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
> SoM")
> 
> Add support for it.
> 
> Reviewed-by: Patrick Delaunay 
> Reviewed-by: Patrice Chotard 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v3:
> - collect Patrice r-b
> Changes for v2:
> - collect Patrice r-b
> - add linux dts commit
> - drop CONFIG_BOARD_EARLY_INIT_F
> 
>  .../dts/stm32mp157a-microgea-stm32mp1.dtsi| 148 ++
>  1 file changed, 148 insertions(+)
>  create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi
> 
> diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi 
> b/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi
> new file mode 100644
> index 00..0b85175f15
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi
> @@ -0,0 +1,148 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
> + * Copyright (c) 2020 Engicam srl
> + * Copyright (c) 2020 Amarula Solutons(India)
> + */
> +
> +/ {
> + compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
> +
> + memory@c000 {
> + device_type = "memory";
> + reg = <0xc000 0x1000>;
> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + mcuram2: mcuram2@1000 {
> + compatible = "shared-dma-pool";
> + reg = <0x1000 0x4>;
> + no-map;
> + };
> +
> + vdev0vring0: vdev0vring0@1004 {
> + compatible = "shared-dma-pool";
> + reg = <0x1004 0x1000>;
> + no-map;
> + };
> +
> + vdev0vring1: vdev0vring1@10041000 {
> + compatible = "shared-dma-pool";
> + reg = <0x10041000 0x1000>;
> + no-map;
> + };
> +
> + vdev0buffer: vdev0buffer@10042000 {
> + compatible = "shared-dma-pool";
> + reg = <0x10042000 0x4000>;
> + no-map;
> + };
> +
> + mcuram: mcuram@3000 {
> + compatible = "shared-dma-pool";
> + reg = <0x3000 0x4>;
> + no-map;
> + };
> +
> + retram: retram@3800 {
> + compatible = "shared-dma-pool";
> + reg = <0x3800 0x1>;
> + no-map;
> + };
> + };
> +
> + vin: regulator-vin {
> + compatible = "regulator-fixed";
> + regulator-name = "vin";
> + regulator-min-microvolt = <500>;
> + regulator-max-microvolt = <500>;
> + regulator-always-on;
> + };
> +
> + vddcore: regulator-vddcore {
> + compatible = "regulator-fixed";
> + regulator-name = "vddcore";
> + regulator-min-microvolt = <120>;
> + regulator-max-microvolt = <120>;
> + regulator-always-on;
> + vin-supply = <&vin>;
> + };
> +
> + vdd: regulator-vdd {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-always-on;
> + vin-supply = <&vin>;
> + };
> +
> + vddq_ddr: regulator-vddq-ddr {
> + compatible = "regulator-fixed";
> + regulator-name = "vddq_ddr";
> + regulator-min-microvolt = <135>;
> + regulator-max-microvolt = <135>;
> + regulator-always-on;
> + vin-supply = <&vin>;
> + };
> +};
> +
> +&dts {
> + status = "okay";
> +};
> +
> +&fmc {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&fmc_pins_a>;
> + pinctrl-1 = <&fmc_sleep_pins_a>;
> + status = "okay";
> +
> + nand-controller@4,0 {
> + status = "okay";
> +
> + nand@0 {
> + reg = <0>;
> + nand-on-flash-bbt;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> + };
> +};
> +
> +&ipcc {
> + status = "okay";
> +};
> +
> +&iwdg2{
> + timeout-sec = <32>;
> + status = "okay";
> +};
> +
> +&m4_rproc{
> + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
> + <&vdev0vring1>, <&vdev0buffer>;
> 

Re: [PATCH v3 5/8] board: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0

2021-04-09 Thread Patrice CHOTARD
Hi Jagan

On 3/16/21 5:22 PM, Jagan Teki wrote:
> Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
> board.
> 
> Genaral features:
> - Ethernet 10/100
> - Wifi/BT
> - USB Type A/OTG
> - Audio Out
> - CAN
> - LVDS panel connector
> 
> i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
> 
> i.Core STM32MP1 needs to mount on top of this Carrier board for
> creating complete i.Core STM32MP1 C.TOUCH 2.0 board.
> 
> Linux dts commit details:
> 
> commit <6ca2898df59f> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
> C.TOUCH 2.0")
> 
> Add support for it.
> 
> Reviewed-by: Patrick Delaunay 
> Reviewed-by: Patrice Chotard 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v3:
> - collect Patrice r-b
> Changes for v2:
> - collect Patrice r-b
> - add linux dts commit
> - drop CONFIG_BOARD_EARLY_INIT_F
> 
>  arch/arm/dts/Makefile |  1 +
>  ...2mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi | 51 
>  .../stm32mp157a-icore-stm32mp1-ctouch2.dts| 47 +++
>  arch/arm/mach-stm32mp/Kconfig |  5 ++
>  board/engicam/stm32mp1/MAINTAINERS|  6 ++
>  ...stm32mp15-icore-stm32mp1-ctouch2_defconfig | 79 +++
>  6 files changed, 189 insertions(+)
>  create mode 100644 
> arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi
>  create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
>  create mode 100644 configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 9d13045f21..ce4521b891 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -990,6 +990,7 @@ dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
>  dtb-$(CONFIG_STM32MP15x) += \
>   stm32mp157a-dk1.dtb \
>   stm32mp157a-avenger96.dtb \
> + stm32mp157a-icore-stm32mp1-ctouch2.dtb \
>   stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
>   stm32mp157c-dk2.dtb \
>   stm32mp157c-ed1.dtb \
> diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi 
> b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi
> new file mode 100644
> index 00..96fe461235
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
> + * Copyright (c) 2020 Amarula Solutions(India)
> + * Author: Jagan Teki 
> + */
> +
> +#include "stm32mp157a-icore-stm32mp1-u-boot.dtsi"
> +
> +/{
> + aliases {
> + mmc0 = &sdmmc1;
> + };
> +
> + chosen {
> + stdout-path = &uart4;
> + };
> +};
> +
> +&sdmmc1 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&sdmmc1_b4_pins_a {
> + u-boot,dm-pre-reloc;
> +
> + pins1 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + pins2 {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> +&uart4 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&uart4_pins_a {
> + u-boot,dm-pre-reloc;
> +
> + pins1 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + pins2 {
> + u-boot,dm-pre-reloc;
> + bias-pull-up;
> + };
> +};
> diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts 
> b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
> new file mode 100644
> index 00..d3058a036c
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
> @@ -0,0 +1,47 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
> + * Copyright (c) 2020 Engicam srl
> + * Copyright (c) 2020 Amarula Solutons(India)
> + */
> +
> +/dts-v1/;
> +#include "stm32mp157.dtsi"
> +#include "stm32mp157a-icore-stm32mp1.dtsi"
> +#include "stm32mp15-pinctrl.dtsi"
> +#include "stm32mp15xxaa-pinctrl.dtsi"
> +#include 
> +
> +/ {
> + model = "Engicam i.Core STM32MP1 C.TOUCH 2.0";
> + compatible = "engicam,icore-stm32mp1-ctouch2",
> +  "engicam,icore-stm32mp1", "st,stm32mp157";
> +
> + aliases {
> + serial0 = &uart4;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&sdmmc1 {
> + bus-width = <4>;
> + disable-wp;
> + pinctrl-names = "default", "opendrain", "sleep";
> + pinctrl-0 = <&sdmmc1_b4_pins_a>;
> + pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
> + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
> + st,neg-edge;
> + vmmc-supply = <&v3v3>;
> + status = "okay";
> +};
> +
> +&uart4 {
> + pinctrl-names = "default", "sleep", "idle";
> + pinctrl-0 = <&uart4_pins_a>;
> + pinctrl-1 = <&uart4_sleep_pins_a>;
> + pinctrl-2 = <&uart4_idle_pins_a>;
> + status = "okay";
> +};
> diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
> index 8d1db70cc3..b809488ca3 100644
> --- a/arch/arm/mach-stm32mp/Kconfig
> +++ b/arch/arm/mach-stm32mp/Kconfig
> @@ -96,6 +96,11 @@ co

Re: [PATCH v3 4/8] board: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit

2021-04-09 Thread Patrice CHOTARD
Hi Jagan

On 3/16/21 5:22 PM, Jagan Teki wrote:
> Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
> Evaluation Board.
> 
> Genaral features:
> - LCD 7" C.Touch
> - microSD slot
> - Ethernet 1Gb
> - Wifi/BT
> - 2x LVDS Full HD interfaces
> - 3x USB 2.0
> - 1x USB 3.0
> - HDMI Out
> - Mini PCIe
> - MIPI CSI
> - 2x CAN
> - Audio Out
> 
> i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
> 
> i.Core STM32MP1 needs to mount on top of this Evaluation board for
> creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.
> 
> Linux dts commit details:
> 
> commit  ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
> EDIMM2.2 Starter Kit")
> 
> Add support for it.
> 
> Reviewed-by: Patrick Delaunay 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v3:
> - include dts in MAINTAINERS
> - collect Patrice r-b
> Changes for v2:
> - collect Patrice r-b
> - add linux dts commit
> - drop CONFIG_BOARD_EARLY_INIT_F
> 
>  arch/arm/dts/Makefile |   1 +
>  ...mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi |  51 ++
>  .../stm32mp157a-icore-stm32mp1-edimm2.2.dts   |  47 ++
>  .../stm32mp157a-icore-stm32mp1-u-boot.dtsi| 146 ++
>  arch/arm/mach-stm32mp/Kconfig |  20 +++
>  board/engicam/stm32mp1/Kconfig|  12 ++
>  board/engicam/stm32mp1/MAINTAINERS|   7 +
>  board/engicam/stm32mp1/Makefile   |  10 ++
>  board/engicam/stm32mp1/spl.c  |  48 ++
>  board/engicam/stm32mp1/stm32mp1.c | 125 +++
>  ...tm32mp15-icore-stm32mp1-edimm2.2_defconfig |  79 ++
>  11 files changed, 546 insertions(+)
>  create mode 100644 
> arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi
>  create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
>  create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi
>  create mode 100644 board/engicam/stm32mp1/Kconfig
>  create mode 100644 board/engicam/stm32mp1/MAINTAINERS
>  create mode 100644 board/engicam/stm32mp1/Makefile
>  create mode 100644 board/engicam/stm32mp1/spl.c
>  create mode 100644 board/engicam/stm32mp1/stm32mp1.c
>  create mode 100644 configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 17cf936a1f..9d13045f21 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -990,6 +990,7 @@ dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
>  dtb-$(CONFIG_STM32MP15x) += \
>   stm32mp157a-dk1.dtb \
>   stm32mp157a-avenger96.dtb \
> + stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
>   stm32mp157c-dk2.dtb \
>   stm32mp157c-ed1.dtb \
>   stm32mp157c-ev1.dtb \
> diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi 
> b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi
> new file mode 100644
> index 00..96fe461235
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
> + * Copyright (c) 2020 Amarula Solutions(India)
> + * Author: Jagan Teki 
> + */
> +
> +#include "stm32mp157a-icore-stm32mp1-u-boot.dtsi"
> +
> +/{
> + aliases {
> + mmc0 = &sdmmc1;
> + };
> +
> + chosen {
> + stdout-path = &uart4;
> + };
> +};
> +
> +&sdmmc1 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&sdmmc1_b4_pins_a {
> + u-boot,dm-pre-reloc;
> +
> + pins1 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + pins2 {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> +&uart4 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&uart4_pins_a {
> + u-boot,dm-pre-reloc;
> +
> + pins1 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + pins2 {
> + u-boot,dm-pre-reloc;
> + bias-pull-up;
> + };
> +};
> diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts 
> b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
> new file mode 100644
> index 00..ec9f1d1cd5
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
> @@ -0,0 +1,47 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
> + * Copyright (c) 2020 Engicam srl
> + * Copyright (c) 2020 Amarula Solutons(India)
> + */
> +
> +/dts-v1/;
> +#include "stm32mp157.dtsi"
> +#include "stm32mp157a-icore-stm32mp1.dtsi"
> +#include "stm32mp15-pinctrl.dtsi"
> +#include "stm32mp15xxaa-pinctrl.dtsi"
> +#include 
> +
> +/ {
> + model = "Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit";
> + compatible = "engicam,icore-stm32mp1-edimm2.2",
> +  "engicam,icore-stm32mp1", "st,stm32mp157";
> +
> + aliases {
> + serial0 = &uart4;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&

Re: [PATCH v3 3/8] ARM: stm32: Imply SPL_SPI_LOAD

2021-04-09 Thread Patrice CHOTARD
Hi Jagan

On 3/16/21 5:22 PM, Jagan Teki wrote:
> SPI Load isn't mandatory for STM32 builds.
> 
> Let's imply instead of select it to get rid of build
> issues for non-SPI defconfigs.
> 
> Reviewed-by: Patrick Delaunay 
> Reviewed-by: Patrice Chotard 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v3:
> - add if SPL_SPI_SUPPORT
> - collect Patrice r-b
> Changes for v2:
> - collect Patrice r-b
> 
>  arch/arm/mach-stm32mp/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
> index f538d7cb83..c61eb424c1 100644
> --- a/arch/arm/mach-stm32mp/Kconfig
> +++ b/arch/arm/mach-stm32mp/Kconfig
> @@ -16,13 +16,13 @@ config SPL
>   select SPL_REGMAP
>   select SPL_DM_RESET
>   select SPL_SERIAL_SUPPORT
> - select SPL_SPI_LOAD
>   select SPL_SYSCON
>   select SPL_WATCHDOG_SUPPORT if WATCHDOG
>   imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
>   imply SPL_BOOTSTAGE if BOOTSTAGE
>   imply SPL_DISPLAY_PRINT
>   imply SPL_LIBDISK_SUPPORT
> + imply SPL_SPI_LOAD if SPL_SPI_SUPPORT
>  
>  config SYS_SOC
>   default "stm32mp"
> 
Applied to u-boot-stm/master

Thanks
Patrice


Re: [PATCH v3 2/8] ARM: dts: stm32: Add Engicam i.Core STM32MP1 1X4Gb DDR3

2021-04-09 Thread Patrice CHOTARD
Hi Jagan

On 3/16/21 5:22 PM, Jagan Teki wrote:
> Engicam i.Core STM32MP1 SODIMM SoM has mounted 1x4Gb DDR3
> which has 32bits width 528000Khz frequency.
> 
> Add DDR configuration via dtsi.
> 
> Reviewed-by: Patrick Delaunay 
> Reviewed-by: Patrice Chotard 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v3:
> - fixed cosmetic s/Khz/kHz 
> - collect Patrice r-b
> Changes for v2:
> - collect Patrice r-b
> 
>  .../stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 119 ++
>  1 file changed, 119 insertions(+)
>  create mode 100644 arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi
> 
> diff --git a/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi 
> b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi
> new file mode 100644
> index 00..24c81269b0
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi
> @@ -0,0 +1,119 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved
> + */
> +
> +/*
> + * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
> + * DDR type: DDR3 / DDR3L
> + * DDR width: 32bits
> + * DDR density: 4Gb
> + * System frequency: 528000Khz
> + * Relaxed Timing Mode: false
> + * Address mapping type: RBC
> + *
> + * Save Date: 2019.05.14, save Time: 11:25:16
> + */
> +#define DDR_MEM_COMPATIBLE ddr3-icore-1066-888-bin-g-1x4gb-528mhz
> +#define DDR_MEM_NAME "DDR3-DDR3L 32bits 528000kHz"
> +#define DDR_MEM_SPEED528000
> +#define DDR_MEM_SIZE 0x2000
> +
> +#define DDR_MSTR 0x00040401
> +#define DDR_MRCTRL0 0x0010
> +#define DDR_MRCTRL1 0x
> +#define DDR_DERATEEN 0x
> +#define DDR_DERATEINT 0x0080
> +#define DDR_PWRCTL 0x
> +#define DDR_PWRTMG 0x00400010
> +#define DDR_HWLPCTL 0x
> +#define DDR_RFSHCTL0 0x0021
> +#define DDR_RFSHCTL3 0x
> +#define DDR_RFSHTMG 0x0080008A
> +#define DDR_CRCPARCTL0 0x
> +#define DDR_DRAMTMG0 0x121B2414
> +#define DDR_DRAMTMG1 0x000A041B
> +#define DDR_DRAMTMG2 0x0607080F
> +#define DDR_DRAMTMG3 0x0050400C
> +#define DDR_DRAMTMG4 0x07040607
> +#define DDR_DRAMTMG5 0x06060403
> +#define DDR_DRAMTMG6 0x02020002
> +#define DDR_DRAMTMG7 0x0202
> +#define DDR_DRAMTMG8 0x1005
> +#define DDR_DRAMTMG14 0x00A0
> +#define DDR_ZQCTL0 0xC240
> +#define DDR_DFITMG0 0x02050105
> +#define DDR_DFITMG1 0x0202
> +#define DDR_DFILPCFG0 0x0700
> +#define DDR_DFIUPD0 0xC043
> +#define DDR_DFIUPD1 0x
> +#define DDR_DFIUPD2 0x
> +#define DDR_DFIPHYMSTR 0x
> +#define DDR_ODTCFG 0x06000600
> +#define DDR_ODTMAP 0x0001
> +#define DDR_SCHED 0x0C01
> +#define DDR_SCHED1 0x
> +#define DDR_PERFHPR1 0x0101
> +#define DDR_PERFLPR1 0x08000200
> +#define DDR_PERFWR1 0x08000400
> +#define DDR_DBG0 0x
> +#define DDR_DBG1 0x
> +#define DDR_DBGCMD 0x
> +#define DDR_POISONCFG 0x
> +#define DDR_PCCFG 0x0010
> +#define DDR_PCFGR_0 0x0001
> +#define DDR_PCFGW_0 0x
> +#define DDR_PCFGQOS0_0 0x02100C03
> +#define DDR_PCFGQOS1_0 0x00800100
> +#define DDR_PCFGWQOS0_0 0x01100C03
> +#define DDR_PCFGWQOS1_0 0x01000200
> +#define DDR_PCFGR_1 0x0001
> +#define DDR_PCFGW_1 0x
> +#define DDR_PCFGQOS0_1 0x02100C03
> +#define DDR_PCFGQOS1_1 0x00800040
> +#define DDR_PCFGWQOS0_1 0x01100C03
> +#define DDR_PCFGWQOS1_1 0x01000200
> +#define DDR_ADDRMAP1 0x00080808
> +#define DDR_ADDRMAP2 0x
> +#define DDR_ADDRMAP3 0x
> +#define DDR_ADDRMAP4 0x1F1F
> +#define DDR_ADDRMAP5 0x07070707
> +#define DDR_ADDRMAP6 0x0F0F0707
> +#define DDR_ADDRMAP9 0x
> +#define DDR_ADDRMAP10 0x
> +#define DDR_ADDRMAP11 0x
> +#define DDR_PGCR 0x01442E02
> +#define DDR_PTR0 0x0022A41B
> +#define DDR_PTR1 0x047C0740
> +#define DDR_PTR2 0x042D9C80
> +#define DDR_ACIOCR 0x10400812
> +#define DDR_DXCCR 0x0C40
> +#define DDR_DSGCR 0xF21F
> +#define DDR_DCR 0x000B
> +#define DDR_DTPR0 0x36D477D0
> +#define DDR_DTPR1 0x098A00D8
> +#define DDR_DTPR2 0x10023600
> +#define DDR_MR0 0x0830
> +#define DDR_MR1 0x
> +#define DDR_MR2 0x0208
> +#define DDR_MR3 0x
> +#define DDR_ODTCR 0x0001
> +#define DDR_ZQ0CR1 0x0038
> +#define DDR_DX0GCR 0xCE81
> +#define DDR_DX0DLLCR 0x4000
> +#define DDR_DX0DQTR 0x
> +#define DDR_DX0DQSTR 0x3DB02000
> +#define DDR_DX1GCR 0xCE81
> +#define DDR_DX1DLLCR 0x4000
> +#define DDR_DX1DQTR 0x
> +#define DDR_DX1DQSTR 0x3DB02000
> +#define DDR_DX2GCR 0xCE81
> +#define DDR_DX2DLLCR 0x4000
> +#define DDR_DX2DQTR 0x
> +#define DDR_DX2DQSTR 0x3DB02000
> +#define DDR_DX3GCR 0xCE81
> +#define DDR_DX3DLLCR 0x4000
> +#define DDR_DX3DQTR 0x
> +#define DDR_DX3DQSTR 0x3DB02000
> +
> +#include "stm32mp15-ddr.dtsi"
> 
Applied to u-boot-stm/master

Thanks
Patrice


Re: [PATCH v3 1/8] ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM

2021-04-09 Thread Patrice CHOTARD
Hi Jagan

On 3/16/21 5:22 PM, Jagan Teki wrote:
> i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
> 
> General features:
> - STM32MP157A
> - Up to 1GB DDR3L
> - 4GB eMMC
> - 10/100 Ethernet
> - USB 2.0 Host/OTG
> - I2S
> - MIPI DSI to LVDS
> - rest of STM32MP157A features
> 
> i.Core STM32MP1 needs to mount on top of Engicam baseboards
> for creating complete platform solutions.
> 
> Linux commit details:
> 
> commit <30f9a9da4ee1> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
> SoM")
> 
> Add support for it.
> 
> Reviewed-by: Patrick Delaunay 
> Reviewed-by: Patrice Chotard 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v3:
> - collect Patrice r-b
> Changes for v2:
> - collect Patrice r-b
> - add linux dts commit 
> 
>  arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi | 196 +++
>  1 file changed, 196 insertions(+)
>  create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi
> 
> diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi 
> b/arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi
> new file mode 100644
> index 00..01166ccacf
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi
> @@ -0,0 +1,196 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
> + * Copyright (c) 2020 Engicam srl
> + * Copyright (c) 2020 Amarula Solutons(India)
> + */
> +
> +/ {
> + compatible = "engicam,icore-stm32mp1", "st,stm32mp157";
> +
> + memory@c000 {
> + device_type = "memory";
> + reg = <0xc000 0x2000>;
> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + mcuram2: mcuram2@1000 {
> + compatible = "shared-dma-pool";
> + reg = <0x1000 0x4>;
> + no-map;
> + };
> +
> + vdev0vring0: vdev0vring0@1004 {
> + compatible = "shared-dma-pool";
> + reg = <0x1004 0x1000>;
> + no-map;
> + };
> +
> + vdev0vring1: vdev0vring1@10041000 {
> + compatible = "shared-dma-pool";
> + reg = <0x10041000 0x1000>;
> + no-map;
> + };
> +
> + vdev0buffer: vdev0buffer@10042000 {
> + compatible = "shared-dma-pool";
> + reg = <0x10042000 0x4000>;
> + no-map;
> + };
> +
> + mcuram: mcuram@3000 {
> + compatible = "shared-dma-pool";
> + reg = <0x3000 0x4>;
> + no-map;
> + };
> +
> + retram: retram@3800 {
> + compatible = "shared-dma-pool";
> + reg = <0x3800 0x1>;
> + no-map;
> + };
> + };
> +
> + vddcore: regulator-vddcore {
> + compatible = "regulator-fixed";
> + regulator-name = "vddcore";
> + regulator-min-microvolt = <120>;
> + regulator-max-microvolt = <120>;
> + regulator-always-on;
> + };
> +
> + vdd: regulator-vdd {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-always-on;
> + };
> +
> + vdd_usb: regulator-vdd-usb {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd_usb";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-always-on;
> + };
> +
> + vdda: regulator-vdda {
> + compatible = "regulator-fixed";
> + regulator-name = "vdda";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-always-on;
> + };
> +
> + vdd_ddr: regulator-vdd-ddr {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd_ddr";
> + regulator-min-microvolt = <135>;
> + regulator-max-microvolt = <135>;
> + regulator-always-on;
> + };
> +
> + vtt_ddr: regulator-vtt-ddr {
> + compatible = "regulator-fixed";
> + regulator-name = "vtt_ddr";
> + regulator-min-microvolt = <675000>;
> + regulator-max-microvolt = <675000>;
> + regulator-always-on;
> + vin-supply = <&vdd>;
> + };
> +
> + vref_ddr: regulator-vref-ddr {
> + compatible = "regulator-fixed";
> + regulator-name = "vref_ddr";
> + regulator-min-microvolt = <675000>;
> + regulator-max-microvolt = <675000>;
> +

Re: [PATCH v1 1/2] cmd: bind: Fix driver binding on a device

2021-04-09 Thread Andy Shevchenko
On Fri, Apr 9, 2021 at 12:28 PM Patrice CHOTARD
 wrote:
> On 4/9/21 11:16 AM, Andy Shevchenko wrote:
> > On Fri, Apr 9, 2021 at 10:37 AM Patrice Chotard
> >  wrote:

...

> >> +   if (drv) {
> >> +   if (drv == entry)
> >> +   break;
> >
> >> +   } else {
> >> +   if (!ret)
> >> +   break;
> >> +   }
> >
> > This can be simplified to
> > } else if (!ret)
> >   break;
>
> I know but checkpatch.pl requested it ;-)

You mean it doesn't recognize 'else if' construction? Then it's a bug
there for sure.

-- 
With Best Regards,
Andy Shevchenko


Re: [PATCH v5 5/7] ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6

2021-04-09 Thread Patrice CHOTARD
Hi Dillon

On 4/9/21 9:28 AM, dillon.min...@gmail.com wrote:
> From: dillon min 
> 
> This patchset has following changes:
> 
> - introduce stm32h750.dtsi to support stm32h750 value line
> - add pin groups for usart3/uart4/spi1/sdmmc2
> - add stm32h750i-art-pi.dtb (arch/arm/boot/dts/Makefile)
> - add stm32h750i-art-pi.dts to support art-pi board
> - add stm32h750i-art-pi-u-boot.dtsi to support art-pi board (u-boot)
> 
> art-pi board component:
> - 8MiB qspi flash
> - 16MiB spi flash
> - 32MiB sdram
> - ap6212 wifi&bt&fm
> 
> the detail board information can be found at:
> https://art-pi.gitee.io/website/
> 
> Signed-off-by: dillon min 
> Reviewed-by: Patrice Chotard 
> ---
> v5: no changes
> 
>  arch/arm/dts/Makefile  |   3 +-
>  arch/arm/dts/stm32h7-pinctrl.dtsi  |  89 ++
>  arch/arm/dts/stm32h750.dtsi|   5 +
>  arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi |  81 +
>  arch/arm/dts/stm32h750i-art-pi.dts | 188 
> +
>  include/dt-bindings/memory/stm32-sdram.h   |   2 +
>  6 files changed, 367 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/stm32h750.dtsi
>  create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
>  create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index c671082..0f54801 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -454,7 +454,8 @@ dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
>   stm32f769-disco.dtb \
>   stm32746g-eval.dtb
>  dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
> - stm32h743i-eval.dtb
> + stm32h743i-eval.dtb \
> + stm32h750i-art-pi.dtb
>  
>  dtb-$(CONFIG_MACH_SUN4I) += \
>   sun4i-a10-a1000.dtb \
> diff --git a/arch/arm/dts/stm32h7-pinctrl.dtsi 
> b/arch/arm/dts/stm32h7-pinctrl.dtsi
> index f6968b5..aefa324 100644
> --- a/arch/arm/dts/stm32h7-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32h7-pinctrl.dtsi
> @@ -137,6 +137,80 @@
>   };
>   };
>  
> + sdmmc2_b4_pins_a: sdmmc2-b4-0 {
> + pins {
> + pinmux = , /* SDMMC1_D0 */
> +  , /* SDMMC1_D1 */
> +  , /* SDMMC1_D2 */
> +  , /* SDMMC1_D3 */
> +  , /* SDMMC1_CK */
> +  ; /* SDMMC1_CMD */
> + slew-rate = <3>;
> + drive-push-pull;
> + bias-disable;
> + };
> + };
> +
> + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
> + pins1 {
> + pinmux = , /* SDMMC2_D0 */
> +  , /* SDMMC1_D1 */
> +  , /* SDMMC1_D2 */
> +  , /* SDMMC1_D3 */
> +  ; /* SDMMC1_CK */
> + slew-rate = <3>;
> + drive-push-pull;
> + bias-disable;
> + };
> + pins2{
> + pinmux = ; /* SDMMC1_CMD */
> + slew-rate = <3>;
> + drive-open-drain;
> + bias-disable;
> + };
> + };
> +
> + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
> + pins {
> + pinmux = , /* SDMMC1_D0 
> */
> +  , /* SDMMC1_D1 
> */
> +  , /* SDMMC1_D2 */
> +  , /* SDMMC1_D3 */
> +  , /* SDMMC1_CK */
> +  ; /* SDMMC1_CMD 
> */
> + };
> + };
> +
> + spi1_pins: spi1-0 {
> + pins1 {
> + pinmux = ,
> + /* SPI1_CLK */
> +  ;
> + /* SPI1_MOSI */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <2>;
> + };
> + pins2 {
> + pinmux = ;
> + /* SPI1_MISO */
> + bias-disable;
> + };
> + };
> +
> + uart4_pins: uart4-0 {
> + pins1 {
> + pinmux = ; /* UART4_TX */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <0>;
> + };
> + pins2 {
> + pinmux = ; /* UART4_RX */
> + bias-disable;
> + };
> + };
> +
>   usart1_pins: usart1-0 {
>   pins1 {
>   pinmux = ; /* USART1_TX */
> @@ -163,6 +237,21 @@
>   };
>   };
>  
> + usart3_pins: usart3-0 {
> + pins1 {
> + pinmux = , /* USART3_TX */
> +  ; /* USART3_RTS_DE 
> */
> + bias-disable;
> + 

Re: [PATCH v5 7/7] board: Add rt-thread art-pi board support

2021-04-09 Thread Patrice CHOTARD
Hi Dillon

On 4/9/21 9:28 AM, dillon.min...@gmail.com wrote:
> From: dillon min 
> 
> All these files are add for support rt-thread art-pi board
> - add board/st/stm32h750-art-pi, defconfig, header support for u-boot
> 
> for more information about art-pi, please goto:
> https://art-pi.gitee.io/website/
> 
> Signed-off-by: dillon min 
> Reviewed-by: Patrice Chotard 
> ---
> v5: remove "for STMicroelectronics." from Author(s) description
> 
>  arch/arm/mach-stm32/stm32h7/Kconfig  |  4 ++
>  board/st/stm32h750-art-pi/Kconfig| 19 +
>  board/st/stm32h750-art-pi/MAINTAINERS|  7 
>  board/st/stm32h750-art-pi/Makefile   |  6 +++
>  board/st/stm32h750-art-pi/stm32h750-art-pi.c | 58 
> 
>  configs/stm32h750-art-pi_defconfig   | 51 
>  include/configs/stm32h750-art-pi.h   | 48 +++
>  7 files changed, 193 insertions(+)
>  create mode 100644 board/st/stm32h750-art-pi/Kconfig
>  create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS
>  create mode 100644 board/st/stm32h750-art-pi/Makefile
>  create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c
>  create mode 100644 configs/stm32h750-art-pi_defconfig
>  create mode 100644 include/configs/stm32h750-art-pi.h
> 
> diff --git a/arch/arm/mach-stm32/stm32h7/Kconfig 
> b/arch/arm/mach-stm32/stm32h7/Kconfig
> index 55e6217..70233a4 100644
> --- a/arch/arm/mach-stm32/stm32h7/Kconfig
> +++ b/arch/arm/mach-stm32/stm32h7/Kconfig
> @@ -6,7 +6,11 @@ config TARGET_STM32H743_DISCO
>  config TARGET_STM32H743_EVAL
>   bool "STM32H743 Evaluation board"
>  
> +config TARGET_STM32H750_ART_PI
> + bool "STM32H750 ART Pi board"
> +
>  source "board/st/stm32h743-eval/Kconfig"
>  source "board/st/stm32h743-disco/Kconfig"
> +source "board/st/stm32h750-art-pi/Kconfig"
>  
>  endif
> diff --git a/board/st/stm32h750-art-pi/Kconfig 
> b/board/st/stm32h750-art-pi/Kconfig
> new file mode 100644
> index 000..c31b984
> --- /dev/null
> +++ b/board/st/stm32h750-art-pi/Kconfig
> @@ -0,0 +1,19 @@
> +if TARGET_STM32H750_ART_PI
> +
> +config SYS_BOARD
> + string
> + default "stm32h750-art-pi"
> +
> +config SYS_VENDOR
> + string
> + default "st"
> +
> +config SYS_SOC
> + string
> + default "stm32h7"
> +
> +config SYS_CONFIG_NAME
> + string
> + default "stm32h750-art-pi"
> +
> +endif
> diff --git a/board/st/stm32h750-art-pi/MAINTAINERS 
> b/board/st/stm32h750-art-pi/MAINTAINERS
> new file mode 100644
> index 000..9578833
> --- /dev/null
> +++ b/board/st/stm32h750-art-pi/MAINTAINERS
> @@ -0,0 +1,7 @@
> +STM32H750 ART PI BOARD
> +M:   Dillon Min 
> +S:   Maintained
> +F:   board/st/stm32h750-art-pi
> +F:   include/configs/stm32h750-art-pi.h
> +F:   configs/stm32h750-art-pi_defconfig
> +F:   arch/arm/dts/stm32h7*
> diff --git a/board/st/stm32h750-art-pi/Makefile 
> b/board/st/stm32h750-art-pi/Makefile
> new file mode 100644
> index 000..a06de87
> --- /dev/null
> +++ b/board/st/stm32h750-art-pi/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2021, RT-Thread - All Rights Reserved
> +# Author(s): Dillon Min,  for RT-Thread.
> +
> +obj-y:= stm32h750-art-pi.o
> diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c 
> b/board/st/stm32h750-art-pi/stm32h750-art-pi.c
> new file mode 100644
> index 000..5785b2e
> --- /dev/null
> +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c
> @@ -0,0 +1,58 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2021, STMicroelectronics - All Rights Reserved
> + * Author(s): Dillon Min 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + struct udevice *dev;
> + int ret;
> +
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + debug("DRAM init failed: %d\n", ret);
> + return ret;
> + }
> +
> + if (fdtdec_setup_mem_size_base() != 0)
> + ret = -EINVAL;
> +
> + return ret;
> +}
> +
> +int dram_init_banksize(void)
> +{
> + fdtdec_setup_memory_banksize();
> +
> + return 0;
> +}
> +
> +int board_early_init_f(void)
> +{
> + return 0;
> +}
> +
> +u32 get_board_rev(void)
> +{
> + return 0;
> +}
> +
> +int board_late_init(void)
> +{
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
> + return 0;
> +}
> diff --git a/configs/stm32h750-art-pi_defconfig 
> b/configs/stm32h750-art-pi_defconfig
> new file mode 100644
> index 000..447af5b
> --- /dev/null
> +++ b/configs/stm32h750-art-pi_defconfig
> @@ -0,0 +1,51 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_STM32=y
> +CONFIG_SYS_TEXT_BASE=0x9000
> +CONFIG_SYS_MALLOC_F_LEN=0xF00
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_ENV_SIZE=0x2000
> +CONFIG_STM32H7=y
> +CONFIG_TARGET_STM32H750_ART_PI=y
> +CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi

Re: [PATCH v5 6/7] ram: stm32: fix strsep failed on read only memory

2021-04-09 Thread Patrice CHOTARD
Hi Dillon

On 4/9/21 9:28 AM, dillon.min...@gmail.com wrote:
> From: dillon min 
> 
> strsep will change data from original memory address,
> in case the memory is in non-sdram/sram place, will
> run into a bug(hang at SDRAM: )
> 
> just add a temporary array to store bank_name[] to fix this
> bug.
> 
> Signed-off-by: dillon min 
> Reviewed-by: Patrice Chotard 
> ---
> v5: no changes
> 
>  drivers/ram/stm32_sdram.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
> index 540ad85..3e25cc7 100644
> --- a/drivers/ram/stm32_sdram.c
> +++ b/drivers/ram/stm32_sdram.c
> @@ -268,6 +268,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
>   u32 swp_fmc;
>   ofnode bank_node;
>   char *bank_name;
> + char _bank_name[128] = {0};
>   u8 bank = 0;
>   int ret;
>  
> @@ -300,6 +301,8 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
>   dev_for_each_subnode(bank_node, dev) {
>   /* extract the bank index from DT */
>   bank_name = (char *)ofnode_get_name(bank_node);
> + strlcpy(_bank_name, bank_name, sizeof(_bank_name));
> + bank_name = (char *)_bank_name;
>   strsep(&bank_name, "@");
>   if (!bank_name) {
>   pr_err("missing sdram bank index");
> 

Applied to u-boot-stm/master

Thanks
Patrice


Re: [PATCH v5 4/7] ARM: dts: stm32: fix i2c node typo in stm32h743, update dmamux1 register

2021-04-09 Thread Patrice CHOTARD
Hi Dillon

On 4/9/21 9:28 AM, dillon.min...@gmail.com wrote:
> From: dillon min 
> 
> Replace upper case by lower case in i2c nodes name.
> update dmamux1 register range.
> 
> Signed-off-by: dillon min 
> Reviewed-by: Patrice Chotard 
> ---
> v5: no changes
> 
>  arch/arm/dts/stm32h743.dtsi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
> index 77a8aef..ed68575 100644
> --- a/arch/arm/dts/stm32h743.dtsi
> +++ b/arch/arm/dts/stm32h743.dtsi
> @@ -139,7 +139,7 @@
>   status = "disabled";
>   };
>  
> - i2c3: i2c@40005C00 {
> + i2c3: i2c@40005c00 {
>   compatible = "st,stm32f7-i2c";
>   #address-cells = <1>;
>   #size-cells = <0>;
> @@ -254,7 +254,7 @@
>  
>   dmamux1: dma-router@40020800 {
>   compatible = "st,stm32h7-dmamux";
> - reg = <0x40020800 0x1c>;
> + reg = <0x40020800 0x40>;
>   #dma-cells = <3>;
>   dma-channels = <16>;
>   dma-requests = <128>;
> @@ -386,7 +386,7 @@
>   status = "disabled";
>   };
>  
> - i2c4: i2c@58001C00 {
> + i2c4: i2c@58001c00 {
>   compatible = "st,stm32f7-i2c";
>   #address-cells = <1>;
>   #size-cells = <0>;
> 

Applied to u-boot-stm/master

Thanks
Patrice


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