Please pull u-boot-marvell/master
Hi Tom,
please pull the next batch of Marvell Armada related patches. Here the
summary log:
- Add base support for Marvell OcteonTX2 CN9130 CRB (mostly done
by Kostya)
- Sync Armada 3k/7k/8k SERDES code with Marvell version (misc Marvell
authors)
- pci-aardvark: Fix processing PIO transfers (Pali)
Here the Azure build, without any issues:
https://dev.azure.com/sr0718/u-boot/_build/results?buildId=83&view=results
Thanks,
Stefan
The following changes since commit 939c4934c8e91b34b258c9487be6a889a6a43546:
configs: Resync with savedefconfig (2021-04-28 10:05:13 +0200)
are available in the Git repository at:
g...@source.denx.de:u-boot/custodians/u-boot-marvell.git
for you to fetch changes up to eccbd4ad8e4e182638eafbfb87ac139c04f24a01:
arm: a37xx: pci: Fix processing PIO transfers (2021-04-29 07:45:43 +0200)
Christine Gharzuzi (1):
phy: marvell: fix handling of unconnected comphy
Grzegorz Jaszczyk (8):
phy: marvell: cp110: let the firmware configure comphy for RXAUI
phy: marvell: cp110: let the firmware configure comphy for USB
phy: marvell: cp110: let the firmware perform training for XFI
phy: marvell: cp110: remove both phy and pipe selector configuration
phy: marvell: cp110: clean up driver after it was moved to atf
phy: marvell: allow to initialize up to 6 USB ports
phy: marvell: fix pll initialization for second utmi port
phy: marvell: utmi: update utmi config which fixes usb2.0 instability
Igal Liberman (11):
phy: marvell: rename comphy related definitions to COMPHY_XX
phy: marvell: add missing speed during info prints
phy: marvell: cp110: utmi: update analog parameters according to
latest ETP
phy: marvell: fix several minor bugs in comphy_probe
phy: marvell: save comphy_map_data priv structure
phy: marvell: add RX training command
phy: marvell: enable comphy info prints for all devices
phy: marvell: pass sgmii id to firmware
phy: marvell: cp110: mark u-boot power-off calls
phy: marvell: add support for SFI1
doc: dt-bindings: add Marvell comphy binding
Konstantin Porotchkin (7):
power: regulator: Add support for regulator-force-boot-off
cmd/mvebu: fix the bubt command
arm: armada: dts: Use a single dtsi for cp110 die description
arm: armada: dts: Add support for ap807-based platforms
arm: armada: configs: Move environment location for mvebu
arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN9130 CRB
arm: octeontx2: Add Octeon TX2 CN9130 CRB support
Marcin Wojtas (1):
phy: marvell: cp110: remove unused definitions
Omri Itach (1):
phy: marvell: cp110: initialize only enabled UTMI units
Pali Rohár (1):
arm: a37xx: pci: Fix processing PIO transfers
Stefan Roese (1):
arm: octeontx2: cn9130-crb.dtsi: Disable eth2 for now
jinghua (1):
phy: marvell: add comphy type PHY_TYPE_USB3
arch/arm/dts/Makefile | 4 +-
arch/arm/dts/armada-3720-db.dts| 8 +-
arch/arm/dts/armada-3720-espressobin.dts | 12 +-
arch/arm/dts/armada-3720-turris-mox.dts| 12 +-
arch/arm/dts/armada-3720-uDPU.dts | 23 +-
arch/arm/dts/armada-7040-db-nand.dts | 97 +--
arch/arm/dts/armada-7040-db.dts| 104 ++--
arch/arm/dts/armada-7040.dtsi | 91 +--
arch/arm/dts/armada-8020.dtsi | 56 --
arch/arm/dts/armada-8040-clearfog-gt-8k.dts| 104 ++--
arch/arm/dts/armada-8040-db.dts| 125 ++--
arch/arm/dts/armada-8040-mcbin.dts | 91 +--
arch/arm/dts/armada-8040-puzzle-m801.dts | 126 ++--
arch/arm/dts/armada-8040.dtsi | 116 ++--
arch/arm/dts/armada-8k.dtsi| 18 +
arch/arm/dts/armada-ap806-quad.dtsi| 82 ---
arch/arm/dts/armada-ap806.dtsi | 281 +
arch/arm/dts/armada-ap807.dtsi | 40 ++
arch/arm/dts/armada-ap80x-quad.dtsi| 52 ++
arch/arm/dts/armada-ap80x.dtsi | 211 +++
arch/arm/dts/armada-common.dtsi| 30 +
arch/arm/dts/armada-cp110-slave.dtsi | 368
...{armada-cp110-master.dtsi => armada-cp110.dtsi} | 315 +-
arch/arm/dts/cn9130-crb-A.dts | 57 ++
arch/arm/dts/cn9130-crb-B.dts | 61 ++
arch/arm/dts/cn9130-crb.dtsi | 257
arch/arm/dts/cn9130.dtsi | 73 +++
arch/arm/mach-mvebu/Kconfig| 10 +
board/CZ.NIC/turris_mox/turris_mox.c | 8 +-
board/Marvell/octeontx2_cn913x/MAINTAI
Re: [PATCH 2/4] arm: octeontx2: cn9130-crb.dtsi: Disable eth2 for now
On 27.04.21 11:48, Stefan Roese wrote:
Because of the incorrectly supported SGMII_2500 mode, this patch
disables eth2 for now until this issue will be fixed in mainline.
Also fix an incorrect comment.
Signed-off-by: Stefan Roese
Cc: Konstantin Porotchkin
Cc: Stefan Chulski
Cc: Nadav Haklai
Cc: Marek Behun
---
This patch is targeted on-top of the latest Marvell SERDES, mvpp2 and
PHY patches to resolve the ongoing discussion of the incorrect usage of
SGMII_2500 for now.
arch/arm/dts/cn9130-crb.dtsi | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
Applied to u-boot-marvell/master
Thanks,
Stefan
diff --git a/arch/arm/dts/cn9130-crb.dtsi b/arch/arm/dts/cn9130-crb.dtsi
index 657a934764ae..78b43b449b3e 100644
--- a/arch/arm/dts/cn9130-crb.dtsi
+++ b/arch/arm/dts/cn9130-crb.dtsi
@@ -232,7 +232,6 @@
};
&cp0_eth0 {
- /* Disable it for now, as mainline does not support this IF yet */
status = "okay";
phy-mode = "sfi";
};
@@ -247,7 +246,6 @@
&cp0_eth2 {
/* Disable it for now, as mainline does not support this IF yet */
- status = "okay";
+ status = "disabled";
phy = <&nbaset_phy0>;
- phy-mode = "sgmii-2500";
};
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH] arm: a37xx: pci: Fix processing PIO transfers
On 22.04.21 16:23, Pali Rohár wrote:
Trying to clear PIO_START register when it is non-zero (which indicates
that previous PIO transfer has not finished yet) causes an External
Abort with SError 0xbf02.
This bug is currently worked around in TF-A by handling External Aborts
in EL3 and ignoring this particular SError.
This workaround was also discussed at:
https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50
https://lore.kernel.org/linux-pci/20190316161243.29517-1-r...@triplefau.lt/
https://lore.kernel.org/linux-pci/971be151d24312cc533989a64bd45...@www.loen.fr/
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1541
Implement a proper fix to prevent this External Abort. As it is not
possible to cancel a pending PIO transfer, simply do not start a new one
if previous has not finished yet. In this case return an error to the
caller.
In most cases this SError happens when there is no PCIe card connected
or when PCIe link is down. The reason is that in these cases a PIO
transfer takes about 1.44 seconds. For this reason we also increase the
wait timeout in pcie_advk_wait_pio() to 1.5 seconds.
If PIO read transfer for PCI_VENDOR_ID register times out, or if it
isn't possible to read it yet because previous transfer is not finished,
return Completion Retry Status value instead of failing, to give the
caller a chance to send a new read request.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
drivers/pci/pci-aardvark.c | 42 +-
1 file changed, 28 insertions(+), 14 deletions(-)
Applied to u-boot-marvell/master
Thanks,
Stefan
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 3b9309f52c..c43d4f309b 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -132,8 +132,9 @@
PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
/* PCIe Retries & Timeout definitions */
-#define MAX_RETRIES10
-#define PIO_WAIT_TIMEOUT 100
+#define PIO_MAX_RETRIES1500
+#define PIO_WAIT_TIMEOUT 1000
+#define LINK_MAX_RETRIES 10
#define LINK_WAIT_TIMEOUT 10
#define CFG_RD_UR_VAL 0x
@@ -192,7 +193,7 @@ static int pcie_advk_addr_valid(pci_dev_t bdf, int
first_busno)
*
* @pcie: The PCI device to access
*
- * Wait up to 1 micro second for PIO access to be accomplished.
+ * Wait up to 1.5 seconds for PIO access to be accomplished.
*
* Return 1 (true) if PIO access is accomplished.
* Return 0 (false) if PIO access is timed out.
@@ -202,7 +203,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
uint start, isr;
uint count;
- for (count = 0; count < MAX_RETRIES; count++) {
+ for (count = 0; count < PIO_MAX_RETRIES; count++) {
start = advk_readl(pcie, PIO_START);
isr = advk_readl(pcie, PIO_ISR);
if (!start && isr)
@@ -214,7 +215,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
udelay(PIO_WAIT_TIMEOUT);
}
- dev_err(pcie->dev, "config read/write timed out\n");
+ dev_err(pcie->dev, "PIO read/write transfer time out\n");
return 0;
}
@@ -323,9 +324,14 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
return 0;
}
- /* Start PIO */
- advk_writel(pcie, 0, PIO_START);
- advk_writel(pcie, 1, PIO_ISR);
+ if (advk_readl(pcie, PIO_START)) {
+ dev_err(pcie->dev,
+ "Previous PIO read/write transfer is still running\n");
+ if (offset != PCI_VENDOR_ID)
+ return -EINVAL;
+ *valuep = CFG_RD_CRS_VAL;
+ return 0;
+ }
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
@@ -342,10 +348,15 @@ static int pcie_advk_read_config(const struct udevice
*bus, pci_dev_t bdf,
advk_writel(pcie, 0, PIO_ADDR_MS);
/* Start the transfer */
+ advk_writel(pcie, 1, PIO_ISR);
advk_writel(pcie, 1, PIO_START);
- if (!pcie_advk_wait_pio(pcie))
- return -EINVAL;
+ if (!pcie_advk_wait_pio(pcie)) {
+ if (offset != PCI_VENDOR_ID)
+ return -EINVAL;
+ *valuep = CFG_RD_CRS_VAL;
+ return 0;
+ }
/* Check PIO status and get the read result */
ret = pcie_advk_check_pio_status(pcie, true, ®);
@@ -420,9 +431,11 @@ static int pcie_advk_write_config(struct udevice *bus,
pci_dev_t bdf,
return 0;
}
- /* Start PIO */
- advk_writel(pcie, 0, PIO_START);
- advk_writel(pcie, 1, PIO_ISR);
+ if (advk_readl(pcie, PIO_START)) {
+ dev_err(pcie->dev,
+ "Previous PIO read/write transfer is still running\n");
+
Re: [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version
On 24.03.21 15:06, Stefan Roese wrote: This patchset adds the missing SERDES patches from the Marvell U-Boot SDK U-Boot version. This is done in preparation for the integration of the Octeon TX2 CN913x support, which uses the updated version of this code. Thanks, Stefan Christine Gharzuzi (1): phy: marvell: fix handling of unconnected comphy Grzegorz Jaszczyk (8): phy: marvell: cp110: let the firmware configure comphy for RXAUI phy: marvell: cp110: let the firmware configure comphy for USB phy: marvell: cp110: let the firmware perform training for XFI phy: marvell: cp110: remove both phy and pipe selector configuration phy: marvell: cp110: clean up driver after it was moved to atf phy: marvell: allow to initialize up to 6 USB ports phy: marvell: fix pll initialization for second utmi port phy: marvell: utmi: update utmi config which fixes usb2.0 instability Igal Liberman (11): phy: marvell: rename comphy related definitions to COMPHY_XX phy: marvell: add missing speed during info prints phy: marvell: cp110: utmi: update analog parameters according to latest ETP phy: marvell: fix several minor bugs in comphy_probe phy: marvell: save comphy_map_data priv structure phy: marvell: add RX training command phy: marvell: enable comphy info prints for all devices phy: marvell: pass sgmii id to firmware phy: marvell: cp110: mark u-boot power-off calls phy: marvell: add support for SFI1 doc: dt-bindings: add Marvell comphy binding Marcin Wojtas (1): phy: marvell: cp110: remove unused definitions Omri Itach (1): phy: marvell: cp110: initialize only enabled UTMI units jinghua (1): phy: marvell: add comphy type PHY_TYPE_USB3 arch/arm/dts/armada-3720-db.dts | 8 +- arch/arm/dts/armada-3720-espressobin.dts | 12 +- arch/arm/dts/armada-3720-turris-mox.dts | 12 +- arch/arm/dts/armada-3720-uDPU.dts | 23 +- arch/arm/dts/armada-7040-db-nand.dts | 24 +- arch/arm/dts/armada-7040-db.dts | 23 +- arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 32 +- arch/arm/dts/armada-8040-db.dts | 24 +- arch/arm/dts/armada-8040-mcbin.dts| 27 +- arch/arm/dts/armada-8040-puzzle-m801.dts | 32 +- arch/arm/dts/armada-cp110.dtsi| 36 +- arch/arm/dts/cn9130-crb-A.dts | 16 +- arch/arm/dts/cn9130-crb-B.dts | 16 +- board/CZ.NIC/turris_mox/turris_mox.c | 8 +- cmd/mvebu/Kconfig | 7 + cmd/mvebu/Makefile| 2 +- cmd/mvebu/rx_training.c | 57 ++ configs/mvebu_db_armada8k_defconfig | 1 + doc/device-tree-bindings/phy/mvebu_comphy.txt | 68 ++ drivers/phy/marvell/comphy_a3700.c| 70 +- drivers/phy/marvell/comphy_a3700.h| 1 - drivers/phy/marvell/comphy_core.c | 81 ++- drivers/phy/marvell/comphy_core.h | 67 +- drivers/phy/marvell/comphy_cp110.c| 621 drivers/phy/marvell/comphy_hpipe.h| 660 -- drivers/phy/marvell/comphy_mux.c | 11 +- drivers/phy/marvell/utmi_phy.h| 24 +- include/dt-bindings/comphy/comphy_data.h | 80 +-- include/mvebu/comphy.h| 2 +- 29 files changed, 591 insertions(+), 1454 deletions(-) create mode 100644 cmd/mvebu/rx_training.c create mode 100644 doc/device-tree-bindings/phy/mvebu_comphy.txt delete mode 100644 drivers/phy/marvell/comphy_hpipe.h Applied to u-boot-marvell/master Thanks, Stefan
Re: [PATCH v2] power: regulator: Add support for regulator-force-boot-off
On 10.04.21 08:42, Stefan Roese wrote:
From: Konstantin Porotchkin
Add support for regulator-force-boot-off DT property.
This property can be used by the board/device drivers for
turning off regulators on early init stages as pre-requisite
for the other components initialization.
Signed-off-by: Konstantin Porotchkin
Signed-off-by: Stefan Roese
Cc: Jaehoon Chung
Cc: Simon Glass
---
v2:
- Add check for uc_pdata in regulator_unset()
Applied to u-boot-marvell/master
Thanks,
Stefan
drivers/power/regulator/regulator-uclass.c | 38 ++
include/power/regulator.h | 23 +
2 files changed, 61 insertions(+)
diff --git a/drivers/power/regulator/regulator-uclass.c
b/drivers/power/regulator/regulator-uclass.c
index 4d2e730271f9..fac960682331 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -311,6 +311,17 @@ int regulator_autoset(struct udevice *dev)
return ret;
}
+int regulator_unset(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_pdata;
+
+ uc_pdata = dev_get_uclass_plat(dev);
+ if (uc_pdata && uc_pdata->force_off)
+ return regulator_set_enable(dev, false);
+
+ return -EMEDIUMTYPE;
+}
+
static void regulator_show(struct udevice *dev, int ret)
{
struct dm_regulator_uclass_plat *uc_pdata;
@@ -443,6 +454,7 @@ static int regulator_pre_probe(struct udevice *dev)
uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on");
uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay",
0);
+ uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off");
node = dev_read_subnode(dev, "regulator-state-mem");
if (ofnode_valid(node)) {
@@ -495,6 +507,32 @@ int regulators_enable_boot_on(bool verbose)
return ret;
}
+int regulators_enable_boot_off(bool verbose)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_REGULATOR, &uc);
+ if (ret)
+ return ret;
+ for (uclass_first_device(UCLASS_REGULATOR, &dev);
+dev;
+uclass_next_device(&dev)) {
+ ret = regulator_unset(dev);
+ if (ret == -EMEDIUMTYPE) {
+ ret = 0;
+ continue;
+ }
+ if (verbose)
+ regulator_show(dev, ret);
+ if (ret == -ENOSYS)
+ ret = 0;
+ }
+
+ return ret;
+}
+
UCLASS_DRIVER(regulator) = {
.id = UCLASS_REGULATOR,
.name = "regulator",
diff --git a/include/power/regulator.h b/include/power/regulator.h
index da9a065bdde0..fad87c99e5db 100644
--- a/include/power/regulator.h
+++ b/include/power/regulator.h
@@ -151,6 +151,7 @@ enum regulator_flag {
* @max_uA*- maximum amperage (micro Amps)
* @always_on* - bool type, true or false
* @boot_on* - bool type, true or false
+ * @force_off* - bool type, true or false
* TODO(s...@chromium.org): Consider putting the above two into @flags
* @ramp_delay - Time to settle down after voltage change (unit: uV/us)
* @flags: - flags value (see REGULATOR_FLAG_...)
@@ -176,6 +177,7 @@ struct dm_regulator_uclass_plat {
unsigned int ramp_delay;
bool always_on;
bool boot_on;
+ bool force_off;
const char *name;
int flags;
u8 ctrl_reg;
@@ -420,6 +422,15 @@ int regulator_set_mode(struct udevice *dev, int mode_id);
*/
int regulators_enable_boot_on(bool verbose);
+/**
+ * regulators_enable_boot_off() - disable regulators needed for boot
+ *
+ * This disables all regulators which are marked to be off at boot time.
+ *
+ * This effectively calls regulator_unset() for every regulator.
+ */
+int regulators_enable_boot_off(bool verbose);
+
/**
* regulator_autoset: setup the voltage/current on a regulator
*
@@ -439,6 +450,18 @@ int regulators_enable_boot_on(bool verbose);
*/
int regulator_autoset(struct udevice *dev);
+/**
+ * regulator_unset: turn off a regulator
+ *
+ * The setup depends on constraints found in device's uclass's platform data
+ * (struct dm_regulator_uclass_platdata):
+ *
+ * - Disable - will set - if 'force_off' is set to true,
+ *
+ * The function returns on the first-encountered error.
+ */
+int regulator_unset(struct udevice *dev);
+
/**
* regulator_autoset_by_name: setup the regulator given by its uclass's
* platform data name field. The setup depends on constraints found in
device's
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v1 0/6] arm: armada: Add Octeon TX2 CN9130 base support
On 08.04.21 11:27, Stefan Roese wrote:
This patchset adds the base support for the Marvell Octeon TX2 CN9130
CRB. This includes the necessary restructuring of the dtsi files to
support the AP807.
Thanks,
Stefan
Konstantin Porotchkin (6):
cmd/mvebu: fix the bubt command
arm: armada: dts: Use a single dtsi for cp110 die description
arm: armada: dts: Add support for ap807-based platforms
arm: armada: configs: Move environment location for mvebu
arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN9130 CRB
arm: octeontx2: Add Octeon TX2 CN9130 CRB support
arch/arm/dts/Makefile | 4 +-
arch/arm/dts/armada-7040-db-nand.dts | 73 +---
arch/arm/dts/armada-7040-db.dts | 81 ++--
arch/arm/dts/armada-7040.dtsi | 91 +++--
arch/arm/dts/armada-8020.dtsi | 56 ---
arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 72 ++--
arch/arm/dts/armada-8040-db.dts | 101 ++---
arch/arm/dts/armada-8040-mcbin.dts| 64 +--
arch/arm/dts/armada-8040-puzzle-m801.dts | 94 ++---
arch/arm/dts/armada-8040.dtsi | 116 --
arch/arm/dts/armada-8k.dtsi | 18 +
arch/arm/dts/armada-ap806-quad.dtsi | 82
arch/arm/dts/armada-ap806.dtsi| 281 ++---
arch/arm/dts/armada-ap807.dtsi| 40 ++
arch/arm/dts/armada-ap80x-quad.dtsi | 52 +++
arch/arm/dts/armada-ap80x.dtsi| 211 ++
arch/arm/dts/armada-common.dtsi | 30 ++
arch/arm/dts/armada-cp110-slave.dtsi | 368 --
...da-cp110-master.dtsi => armada-cp110.dtsi} | 282 ++
arch/arm/dts/cn9130-crb-A.dts | 57 +++
arch/arm/dts/cn9130-crb-B.dts | 61 +++
arch/arm/dts/cn9130-crb.dtsi | 253
arch/arm/dts/cn9130.dtsi | 73
arch/arm/mach-mvebu/Kconfig | 10 +
board/Marvell/octeontx2_cn913x/MAINTAINERS| 6 +
board/Marvell/octeontx2_cn913x/Makefile | 8 +
board/Marvell/octeontx2_cn913x/board.c| 45 +++
cmd/mvebu/Kconfig | 2 +-
cmd/mvebu/bubt.c | 2 +-
configs/mvebu_crb_cn9130_defconfig| 84
configs/mvebu_db-88f3720_defconfig| 2 +-
configs/mvebu_db_armada8k_defconfig | 2 +-
32 files changed, 1415 insertions(+), 1306 deletions(-)
delete mode 100644 arch/arm/dts/armada-8020.dtsi
create mode 100644 arch/arm/dts/armada-8k.dtsi
delete mode 100644 arch/arm/dts/armada-ap806-quad.dtsi
create mode 100644 arch/arm/dts/armada-ap807.dtsi
create mode 100644 arch/arm/dts/armada-ap80x-quad.dtsi
create mode 100644 arch/arm/dts/armada-ap80x.dtsi
create mode 100644 arch/arm/dts/armada-common.dtsi
delete mode 100644 arch/arm/dts/armada-cp110-slave.dtsi
rename arch/arm/dts/{armada-cp110-master.dtsi => armada-cp110.dtsi} (55%)
create mode 100644 arch/arm/dts/cn9130-crb-A.dts
create mode 100644 arch/arm/dts/cn9130-crb-B.dts
create mode 100644 arch/arm/dts/cn9130-crb.dtsi
create mode 100644 arch/arm/dts/cn9130.dtsi
create mode 100644 board/Marvell/octeontx2_cn913x/MAINTAINERS
create mode 100644 board/Marvell/octeontx2_cn913x/Makefile
create mode 100644 board/Marvell/octeontx2_cn913x/board.c
create mode 100644 configs/mvebu_crb_cn9130_defconfig
Applied to u-boot-marvell/master
Thanks,
Stefan
Re: [PATCH 6/6] net: octeontx: smi: fix mii probe
Hi Tim,
On 28.04.21 17:11, Tim Harvey wrote:
On Mon, Apr 26, 2021 at 10:19 PM Stefan Roese wrote:
Hi Tim,
On 26.03.21 16:55, Tim Harvey wrote:
On Thu, Mar 25, 2021 at 11:48 PM Stefan Roese wrote:
On 26.03.21 01:07, Tim Harvey wrote:
The fdt node offset is apparently not set properly when probed
causing no MDIO busses to be found. Fix this by obtaining the
offset.
Signed-off-by: Tim Harvey
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/net/octeontx/smi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/octeontx/smi.c b/drivers/net/octeontx/smi.c
index 91dcd05e4b..27f4423c6a 100644
--- a/drivers/net/octeontx/smi.c
+++ b/drivers/net/octeontx/smi.c
@@ -325,6 +325,8 @@ int octeontx_smi_probe(struct udevice *dev)
return -1;
}
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+ "cavium,thunder-8890-mdio-nexus");
fdt_for_each_subnode(subnode, gd->fdt_blob, node) {
ret = fdt_node_check_compatible(gd->fdt_blob, subnode,
"cavium,thunder-8890-mdio");
Honestly this is the wrong fix for this issue and I'm hoping someone
could educate me. I'm a bit confused at why there are several ways to
work with dt (int offsets vs ofnodes which are unions of int offsets
and node pointers???).
The above patch was not needed previously so something changed in the
ofnode field of struct udevice between v2019.10 and v2021.01.
Simon, could you explain what the proper way to work with dev->ofnode
in probe functions is to loop over subnodes?
This version is in mainline now. Tim, could you please re-visit this
and perhaps switch to using live tree API, as suggested by Suneel:
ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
ret = ofnode_device_is_compatible(subnode,
"cavium,thunder-8890-mdio");
Stefan,
Yes, I can submit this but I would really like to understand the
original issue. Do you or Simon perhaps know why the fdt node offset
in dev passed to probe is wrong? It's not null but it does not appear
to point to a device-tree (or perhaps I was using the wrong functions
on it not fully understanding the current state of this live tree
API).
I don't have an OcteonTX board installed right now, so it's not easy to
really verify this. AFAIU, fdt_for_each_subnode() etc is deprecated and
the use of e.g. this API seems "more modern":
ofnode subnode;
dev_for_each_subnode(subnode, dev) {
...
Does this work for you?
Thanks,
Stefan
Re: [linux-sunxi] [PATCH] sunxi: H616: Enable full 4GB of DRAM
Hi, On Thu, Apr 29, 2021 at 6:53 AM Andre Przywara wrote: > > The H616 is our first supported Allwinner SoC which goes beyond the 4GB > address space "barrier", by having more than 32 address bits. Nit: I wouldn't say it's the first. The A80 supports up to 8GB address space with LPAE. It just never shipped with more than 2GB DRAM. ChenYu
[PATCH] sunxi: H616: Enable full 4GB of DRAM
The H616 is our first supported Allwinner SoC which goes beyond the 4GB
address space "barrier", by having more than 32 address bits.
Lift the preliminary 3GB DRAM limit for the H616, and update the page
table setup on the way, to actually map that last GB as well.
This will presumably break the EMAC, as the DMA descriptors only hold
32 bits worth of addresses, but this is no problem for now, as all
boards with 4GB of DRAM cannot use the EMAC at the moment (missing
PHY support).
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/Kconfig | 4 ++--
arch/arm/mach-sunxi/board.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index b6463bca71d..4d71030e655 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -192,10 +192,10 @@ config MACH_SUNXI_H3_H5
select SUPPORT_SPL
# TODO: try out A80's 8GiB DRAM space
-# TODO: H616 supports 4 GiB DRAM space
config SUNXI_DRAM_MAX_SIZE
hex
- default 0xC000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
|| MACH_SUN50I_H616
+ default 0x1 if MACH_SUN50I_H616
+ default 0xC000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
default 0x8000
choice
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 8cbd926f51d..edcfaee187e 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -56,7 +56,7 @@ static struct mm_region sunxi_mem_map[] = {
/* RAM */
.virt = 0x4000UL,
.phys = 0x4000UL,
- .size = 0xC000UL,
+ .size = CONFIG_SUNXI_DRAM_MAX_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
--
2.17.5
[PULL] u-boot-usb/master
The following changes since commit 79b0f08d6af498e6fda8cd257d62e2095764410c: configs: Resync with savedefconfig (2021-04-27 08:28:38 -0400) are available in the Git repository at: git://source.denx.de/u-boot-usb.git master for you to fetch changes up to 53396d67baef4acbcc257c5f2c702935b62cc858: usb: ehci-mx6: Limit PHY address parsing to !CONFIG_PHY (2021-04-28 17:16:18 +0200) Marek Vasut (1): usb: ehci-mx6: Limit PHY address parsing to !CONFIG_PHY drivers/usb/host/ehci-mx6.c | 17 - 1 file changed, 12 insertions(+), 5 deletions(-)
Re: [PATCH V2 24/24] ARM: imx8m: verdin-imx8mm: Enable USB Host support
On Tue, Apr 27, 2021 at 10:50 AM Tim Harvey wrote:
>
> On Mon, Apr 26, 2021, 5:35 PM Marek Vasut wrote:
> >
> > On 4/27/21 2:01 AM, Tim Harvey wrote:
> > [...]
> > >>> Why would the power domain get probed/enabled for the usbotg2
> > >>> bus but not the usbotg1 bus? Here is some debugging:
> > >>> u-boot=> usb start
> > >>> starting USB...
> > >>> Bus usb@32e4: ehci_usb_phy_mode usb@32e4
> > >>> usb@32e4 probe ret=-22
> > >>> probe failed, error -22
> > >>> ^^^ probe fails here because ehci_usb_phy_mode returns EINVAL for
> > >>> dr_mode=otg but if we try to read the phy_status reg we will hang b/c
> > >>> power domain is not enabled yet
> > >>> Bus usb@32e5: imx8m_power_domain_probe gpc@303a
> > >>> imx8m_power_domain_probe pgc
> > >>> ^^^ why did power domain get probed on the 2nd bus and not the first?
> > >>
> > >> I don't know, can you have a look ?
> > >
> > > Marek,
> > >
> > > The reg domain does not get enabled for usbotg1 because
> > > device_of_to_plat gets called 'before' dev_power_domain_on in
> > > device_probe.
> > >
> > > The following will get imx8mm USB otg working:
> > >
> > > For OTG defer setting type until probe after clock and power have been
> > > brought up.
> > > index 06be9deaaa..2183ae4f9d 100644
> > > --- a/drivers/usb/host/ehci-mx6.c
> > > +++ b/drivers/usb/host/ehci-mx6.c
> > > @@ -523,7 +523,7 @@ static int ehci_usb_phy_mode(struct udevice *dev)
> > > plat->init_type = USB_INIT_DEVICE;
> > > else
> > > plat->init_type = USB_INIT_HOST;
> > > - } else if (is_mx7()) {
> > > + } else if (is_mx7() || is_imx8mm()) {
> > > phy_status = (void __iomem *)(addr +
> > >USBNC_PHY_STATUS_OFFSET);
> > > val = readl(phy_status);
> > > @@ -555,7 +555,10 @@ static int ehci_usb_of_to_plat(struct udevice *dev)
> > > break;
> > > case USB_DR_MODE_OTG:
> > > case USB_DR_MODE_UNKNOWN:
> > > - return ehci_usb_phy_mode(dev);
> > > + if (is_imx8mm())
> >
> > Does this mean OTG doesn't work on the 8MM then ?
>
> IMX8MM USB in general still doesn't work without your:
> usb: ehci-mx6: Limit PHY address parsing to !CONFIG_PHY
>
> With your patch, IMX8MM 'host' works but 'otg' will fail probe with
> -22 (due ehci_usb_phy_mode called from of_to_plat and it not having a
> case for imx8mm)
>
> >
> > > + plat->init_type = USB_INIT_HOST;
> > > + else
> > > + return ehci_usb_phy_mode(dev);
> > > };
> > >
> > > return 0;
> > > @@ -657,6 +660,13 @@ static int ehci_usb_probe(struct udevice *dev)
> > > mdelay(1);
> > > #endif
> > >
> > > + if (is_imx8mm() && (usb_get_dr_mode(dev_ofnode(dev)) ==
> > > USB_DR_MODE_OTG)) {
> > > + ret = ehci_usb_phy_mode(dev);
> > > + if (ret)
> > > + return ret;
> > > + priv->init_type = plat->init_type;
> > > + };
> >
> > I have to wonder, why not move the whole OTG/Host/Device detection to
> > probe then ?
>
> Yes, I think that is the right thing to do.
>
> >
> > Also, could you submit a regular patch ?
>
> Yes, I will post patches to fix IMX8MM OTG. Can you submit your 'usb:
> ehci-mx6: Limit PHY address parsing to !CONFIG_PHY' patch so I can go
> on top of that or can I just pull that into my series?
If you want me to test it on either a Mini or Nano, feel free to CC me
as well. I was out of town the last week, so I wasn't in a place to
do any work.
I am a little behind, so I might need some pointers to prerequisite
patches if they're necessary.
thanks,
adam
>
> Best regards,
>
> Tim
[PATCH 29/30] ARM: renesas: Add GICv3 initialization for V3U Falcon
From: Koji Matsuoka
Init GICv3 for V3U Falcon in early phase
Signed-off-by: Koji Matsuoka
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
board/renesas/falcon/falcon.c | 29 +
include/configs/falcon.h | 11 +++
2 files changed, 40 insertions(+)
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c
index c3241bc21d..3e74384716 100644
--- a/board/renesas/falcon/falcon.c
+++ b/board/renesas/falcon/falcon.c
@@ -40,6 +40,33 @@ static void init_generic_timer(void)
setbits_le32(CNTCR_BASE, CNTCR_EN);
}
+/* Distributor Registers */
+#define GICD_BASE 0xF100
+
+/* ReDistributor Registers for Control and Physical LPIs */
+#define GICR_LPI_BASE 0xF106
+#define GICR_WAKER 0x0014
+#define GICR_PWRR 0x0024
+#define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER)
+#define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR)
+
+/* ReDistributor Registers for SGIs and PPIs */
+#define GICR_SGI_BASE 0xF107
+#define GICR_IGROUPR0 0x0080
+
+static void init_gic_v3(void)
+{
+/* GIC v3 power on */
+ writel(0x0002, (GICR_LPI_PWRR));
+
+ /* Wait till the WAKER_CA_BIT changes to 0 */
+ writel(readl(GICR_LPI_WAKER) & ~0x0002, (GICR_LPI_WAKER));
+ while (readl(GICR_LPI_WAKER) & 0x0004)
+ ;
+
+ writel(0x, GICR_SGI_BASE + GICR_IGROUPR0);
+}
+
void s_init(void)
{
init_generic_timer();
@@ -59,6 +86,8 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x5;
+ init_gic_v3();
+
return 0;
}
diff --git a/include/configs/falcon.h b/include/configs/falcon.h
index b9c82a7674..5ecbd1d3ed 100644
--- a/include/configs/falcon.h
+++ b/include/configs/falcon.h
@@ -11,6 +11,17 @@
#include "rcar-gen3-common.h"
+/* Generic Interrupt Controller Definitions */
+#ifdef CONFIG_GICV2
+#undef CONFIG_GICV2
+#undef GICD_BASE
+#undef GICC_BASE
+#undef GICR_BASE
+#endif
+#define CONFIG_GICV3
+#define GICD_BASE 0xF100
+#define GICR_BASE 0xF106
+
/* Ethernet RAVB */
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
--
2.30.2
[PATCH 30/30] ARM: rmobile: Add basic PSCI support for R8A779A0 V3U Falcon
From: Hai Pham
Enable basic PSCI support for R8A779A0 V3U Falcon
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
arch/arm/mach-rmobile/Makefile| 4 +++
arch/arm/mach-rmobile/psci-r8a779a0.c | 49 +++
configs/r8a779a0_falcon_defconfig | 1 +
3 files changed, 54 insertions(+)
create mode 100644 arch/arm/mach-rmobile/psci-r8a779a0.c
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 81a0dedb41..195bbeb5c8 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -15,6 +15,10 @@ obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o
cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
+ifneq ($(CONFIG_R8A779A0),)
+obj-$(CONFIG_ARMV8_PSCI) += psci-r8a779a0.o
+endif
+
OBJCOPYFLAGS_u-boot-spl.srec := -O srec
quiet_cmd_objcopy = OBJCOPY $@
cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \
diff --git a/arch/arm/mach-rmobile/psci-r8a779a0.c
b/arch/arm/mach-rmobile/psci-r8a779a0.c
new file mode 100644
index 00..6a85eb22ca
--- /dev/null
+++ b/arch/arm/mach-rmobile/psci-r8a779a0.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This file implements basic PSCI support for Renesas r8a779a0 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+int __secure psci_features(u32 function_id, u32 psci_fid)
+{
+ switch (psci_fid) {
+ case ARM_PSCI_0_2_FN_PSCI_VERSION:
+ case ARM_PSCI_0_2_FN_SYSTEM_RESET:
+ return 0x0;
+ }
+ /* case ARM_PSCI_0_2_FN_CPU_ON: */
+ /* case ARM_PSCI_0_2_FN_CPU_OFF: */
+ /* case ARM_PSCI_0_2_FN_AFFINITY_INFO: */
+ /* case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE: */
+ /* case ARM_PSCI_0_2_FN_SYSTEM_OFF: */
+ return ARM_PSCI_RET_NI;
+}
+
+u32 __secure psci_version(void)
+{
+ return ARM_PSCI_VER_0_2;
+}
+
+#define RST_BASE 0xE616 /* Domain0 */
+#define RST_SRESCR0(RST_BASE + 0x18)
+#define RST_SPRES 0x5AA58000
+
+void __secure __noreturn psci_system_reset(void)
+{
+ writel(RST_SPRES, RST_SRESCR0);
+
+ while (1)
+ ;
+}
+
+int psci_update_dt(void *fdt)
+{
+ return 0;
+}
diff --git a/configs/r8a779a0_falcon_defconfig
b/configs/r8a779a0_falcon_defconfig
index dad8b77acf..8df647acfb 100644
--- a/configs/r8a779a0_falcon_defconfig
+++ b/configs/r8a779a0_falcon_defconfig
@@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_FALCON=y
# CONFIG_PSCI_RESET is not set
+CONFIG_ARMV8_PSCI=y
CONFIG_DEFAULT_DEVICE_TREE="r8a779a0-falcon-u-boot"
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
--
2.30.2
[PATCH 28/30] ARM: renesas: Add generic timer initialization for V3U Falcon
From: Koji Matsuoka
Init the Generic Timer for V3U Falcon in early phase
Signed-off-by: Koji Matsuoka
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
board/renesas/falcon/falcon.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c
index 3e591e4b42..c3241bc21d 100644
--- a/board/renesas/falcon/falcon.c
+++ b/board/renesas/falcon/falcon.c
@@ -20,6 +20,31 @@ DECLARE_GLOBAL_DATA_PTR;
#define CPGWPR 0xE615
#define CPGWPCR0xE6150004
+#define EXTAL_CLK 1600u
+#define CNTCR_BASE 0xE608
+#define CNTFID0(CNTCR_BASE + 0x020)
+#define CNTCR_EN BIT(0)
+
+static void init_generic_timer(void)
+{
+ u32 freq;
+
+ /* Set frequency data in CNTFID0 */
+ freq = EXTAL_CLK;
+
+ /* Update memory mapped and register based freqency */
+ asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
+ writel(freq, CNTFID0);
+
+ /* Enable counter */
+ setbits_le32(CNTCR_BASE, CNTCR_EN);
+}
+
+void s_init(void)
+{
+ init_generic_timer();
+}
+
int board_early_init_f(void)
{
/* Unlock CPG access */
--
2.30.2
[PATCH 27/30] ARM: renesas: Add R8A779A0 V3U Falcon board code
From: Hai Pham
Add board code for the R8A779A0 V3U Falcon board.
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
--
Marek: - various small rebase fixes and clean ups
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/r8a779a0-falcon-u-boot.dts | 32 +
arch/arm/mach-rmobile/Kconfig.64| 7 +++
board/renesas/falcon/Kconfig| 15 ++
board/renesas/falcon/MAINTAINERS| 6 +++
board/renesas/falcon/Makefile | 13 +
board/renesas/falcon/falcon.c | 47 ++
configs/r8a779a0_falcon_defconfig | 64 +
include/configs/falcon.h| 25 ++
9 files changed, 211 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/r8a779a0-falcon-u-boot.dts
create mode 100644 board/renesas/falcon/Kconfig
create mode 100644 board/renesas/falcon/MAINTAINERS
create mode 100644 board/renesas/falcon/Makefile
create mode 100644 board/renesas/falcon/falcon.c
create mode 100644 configs/r8a779a0_falcon_defconfig
create mode 100644 include/configs/falcon.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aec5020a0f..5b4ffc9ee6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -879,7 +879,8 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a77970-eagle-u-boot.dtb \
r8a77980-condor-u-boot.dtb \
r8a77990-ebisu-u-boot.dtb \
- r8a77995-draak-u-boot.dtb
+ r8a77995-draak-u-boot.dtb \
+ r8a779a0-falcon-u-boot.dtb
ifdef CONFIG_RCAR_GEN3
DTC_FLAGS += -R 4 -p 0x1000
diff --git a/arch/arm/dts/r8a779a0-falcon-u-boot.dts
b/arch/arm/dts/r8a779a0-falcon-u-boot.dts
new file mode 100644
index 00..06d3922a38
--- /dev/null
+++ b/arch/arm/dts/r8a779a0-falcon-u-boot.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Falcon board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a779a0-falcon.dts"
+#include "r8a779a0-u-boot.dtsi"
+
+/ {
+ aliases {
+ spi0 = &rpc;
+ };
+};
+
+&rpc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <1>;
+ spi-max-frequency = <5000>;
+ status = "okay";
+
+ spi-flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <5000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "okay";
+ };
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index e22012e3b8..8df90acb4e 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -110,6 +110,12 @@ config TARGET_EBISU
help
Support for Renesas R-Car Gen3 Ebisu platform
+config TARGET_FALCON
+ bool "Falcon board"
+ imply R8A779A0
+ help
+ Support for Renesas R-Car Gen3 Falcon platform
+
config TARGET_HIHOPE_RZG2
bool "HiHope RZ/G2 board"
imply R8A774A1
@@ -160,6 +166,7 @@ source "board/renesas/condor/Kconfig"
source "board/renesas/draak/Kconfig"
source "board/renesas/eagle/Kconfig"
source "board/renesas/ebisu/Kconfig"
+source "board/renesas/falcon/Kconfig"
source "board/renesas/salvator-x/Kconfig"
source "board/renesas/ulcb/Kconfig"
source "board/beacon/beacon-rzg2m/Kconfig"
diff --git a/board/renesas/falcon/Kconfig b/board/renesas/falcon/Kconfig
new file mode 100644
index 00..1fcefa7e3c
--- /dev/null
+++ b/board/renesas/falcon/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_FALCON
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "falcon"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "falcon"
+
+endif
diff --git a/board/renesas/falcon/MAINTAINERS b/board/renesas/falcon/MAINTAINERS
new file mode 100644
index 00..2cacc91494
--- /dev/null
+++ b/board/renesas/falcon/MAINTAINERS
@@ -0,0 +1,6 @@
+FALCON BOARD
+M: Marek Vasut
+S: Maintained
+F: board/renesas/falcon/
+F: include/configs/falcon.h
+F: configs/r8a779a0_falcon_defconfig
diff --git a/board/renesas/falcon/Makefile b/board/renesas/falcon/Makefile
new file mode 100644
index 00..3b202c24fb
--- /dev/null
+++ b/board/renesas/falcon/Makefile
@@ -0,0 +1,13 @@
+#
+# board/renesas/falcon/Makefile
+#
+# Copyright (C) 2020 Renesas Electronics Corp.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := ../rcar-common/gen3-spl.o
+else
+obj-y := falcon.o ../rcar-common/common.o
+endif
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c
new file mode 100644
index 00..3e591e4b42
--- /dev/null
+++ b/board/renesas/falcon/falcon.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/falcon/falcon.c
+ * This file is Falcon board support.
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+#i
[PATCH 22/30] ARM: dts: renesas: Add R8A779A0 V3U DTs and headers
Import R8A779A0 V3U DTs and headers from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a779a0.dtsi| 970 ++
include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 55 +
include/dt-bindings/power/r8a779a0-sysc.h | 59 ++
3 files changed, 1084 insertions(+)
create mode 100644 arch/arm/dts/r8a779a0.dtsi
create mode 100644 include/dt-bindings/clock/r8a779a0-cpg-mssr.h
create mode 100644 include/dt-bindings/power/r8a779a0-sysc.h
diff --git a/arch/arm/dts/r8a779a0.dtsi b/arch/arm/dts/r8a779a0.dtsi
new file mode 100644
index 00..dfd6ae8b56
--- /dev/null
+++ b/arch/arm/dts/r8a779a0.dtsi
@@ -0,0 +1,970 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the R-Car V3U (R8A779A0) SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+
+/ {
+ compatible = "renesas,r8a779a0";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ a76_0: cpu@0 {
+ compatible = "arm,cortex-a76";
+ reg = <0>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
+ next-level-cache = <&L3_CA76_0>;
+ };
+
+ L3_CA76_0: cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&sysc R8A779A0_PD_A2E0D0>;
+ cache-unified;
+ cache-level = <3>;
+ };
+ };
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ extalr_clk: extalr {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ pmu_a76 {
+ compatible = "arm,cortex-a76-pmu";
+ interrupts-extended = <&gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /* External SCIF clock - to be overridden by boards that provide it */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ rwdt: watchdog@e602 {
+ compatible = "renesas,r8a779a0-wdt",
+"renesas,rcar-gen3-wdt";
+ reg = <0 0xe602 0 0x0c>;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ status = "disabled";
+ };
+
+ pfc: pin-controller@e605 {
+ compatible = "renesas,pfc-r8a779a0";
+ reg = <0 0xe605 0 0x16c>, <0 0xe6050800 0 0x16c>,
+ <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
+ <0 0xe606 0 0x16c>, <0 0xe6060800 0 0x16c>,
+ <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
+ <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
+ };
+
+ gpio0: gpio@e6058180 {
+ compatible = "renesas,gpio-r8a779a0";
+ reg = <0 0xe6058180 0 0x54>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 916>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pfc 0 0 28>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@e6050180 {
+ compatible = "renesas,gpio-r8a779a0";
+ reg = <0 0xe6050180 0 0x54>;
+ interrupts = ;
+
[PATCH 26/30] ARM: renesas: Add R8A779A0 V3U platform code
From: Hai Pham
Add platform code to support R8A779A0 V3U SoC.
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
arch/arm/mach-rmobile/Kconfig.64 | 5 +
arch/arm/mach-rmobile/cpu_info.c | 1 +
arch/arm/mach-rmobile/include/mach/rmobile.h | 1 +
3 files changed, 7 insertions(+)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 3f7ec05379..e22012e3b8 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -57,6 +57,11 @@ config R8A77995
imply CLK_R8A77995
imply PINCTRL_PFC_R8A77995
+config R8A779A0
+ bool "Renesas SoC R8A779A0"
+ imply CLK_R8A779A0
+ imply PINCTRL_PFC_R8A779A0
+
config RZ_G2
bool "Renesas ARM SoCs RZ/G2 (64bit)"
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 9ec622bdb5..2bb6d502b8 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -76,6 +76,7 @@ static const struct {
{ RMOBILE_CPU_TYPE_R8A77980, "R8A77980" },
{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
+ { RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
{ 0x0, "CPU" },
};
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h
b/arch/arm/mach-rmobile/include/mach/rmobile.h
index a688636141..dc6f87631b 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -39,6 +39,7 @@
#define RMOBILE_CPU_TYPE_R8A77980 0x56
#define RMOBILE_CPU_TYPE_R8A77990 0x57
#define RMOBILE_CPU_TYPE_R8A77995 0x58
+#define RMOBILE_CPU_TYPE_R8A779A0 0x59
#ifndef __ASSEMBLY__
const u8 *rzg_get_cpu_name(void);
--
2.30.2
[PATCH 25/30] ARM: dts: renesas: Add RPC node to R8A779A0 V3U
The R-Car V3U does support RPC interface, however the support for it is
missing in upstream Linux DTs as of commit 9f4ad9e425a1 ("Linux 5.12"),
add the node into u-boot.dtsi to let U-Boot access the SPI NOR or HF.
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a779a0-u-boot.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/r8a779a0-u-boot.dtsi
b/arch/arm/dts/r8a779a0-u-boot.dtsi
index f6101289e8..83dbe3f20e 100644
--- a/arch/arm/dts/r8a779a0-u-boot.dtsi
+++ b/arch/arm/dts/r8a779a0-u-boot.dtsi
@@ -7,6 +7,19 @@
#include "r8a779x-u-boot.dtsi"
+/ {
+ soc {
+ rpc: spi@ee20 {
+ compatible = "renesas,rpc-r8a779a0",
"renesas,rcar-gen3-rpc";
+ reg = <0 0xee20 0 0x200>, <0 0x0800 0
0x0400>;
+ clocks = <&cpg CPG_MOD 629>;
+ bank-width = <2>;
+ num-cs = <1>;
+ status = "disabled";
+ };
+ };
+};
+
&extalr_clk {
u-boot,dm-pre-reloc;
};
--
2.30.2
[PATCH 23/30] ARM: dts: renesas: Add R8A779A0 V3U Falcon DTs
Import R8A779A0 V3U Falcon DTs from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a779a0-falcon-cpu.dtsi | 184 ++
arch/arm/dts/r8a779a0-falcon.dts | 28
2 files changed, 212 insertions(+)
create mode 100644 arch/arm/dts/r8a779a0-falcon-cpu.dtsi
create mode 100644 arch/arm/dts/r8a779a0-falcon.dts
diff --git a/arch/arm/dts/r8a779a0-falcon-cpu.dtsi
b/arch/arm/dts/r8a779a0-falcon-cpu.dtsi
new file mode 100644
index 00..fa284a7260
--- /dev/null
+++ b/arch/arm/dts/r8a779a0-falcon-cpu.dtsi
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Falcon CPU board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include
+#include "r8a779a0.dtsi"
+
+/ {
+ model = "Renesas Falcon CPU board";
+ compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
+
+ memory@4800 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x4800 0x0 0x7800>;
+ };
+
+ memory@5 {
+ device_type = "memory";
+ reg = <0x5 0x 0x0 0x8000>;
+ };
+
+ memory@6 {
+ device_type = "memory";
+ reg = <0x6 0x 0x0 0x8000>;
+ };
+
+ memory@7 {
+ device_type = "memory";
+ reg = <0x7 0x 0x0 0x8000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&avb0 {
+ pinctrl-0 = <&avb0_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy0>;
+ tx-internal-delay-ps = <2000>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <1666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <40>;
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <40>;
+};
+
+&i2c6 {
+ pinctrl-0 = <&i2c6_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <40>;
+};
+
+&mmc0 {
+ pinctrl-0 = <&mmc_pins>;
+ pinctrl-1 = <&mmc_pins>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ full-pwr-cycle-in-suspend;
+ status = "okay";
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ avb0_pins: avb0 {
+ mux {
+ groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
"avb0_txcrefclk";
+ function = "avb0";
+ };
+
+ pins_mdio {
+ groups = "avb0_mdio";
+ drive-strength = <21>;
+ };
+
+ pins_mii {
+ groups = "avb0_rgmii";
+ drive-strength = <21>;
+ };
+
+ };
+
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
+ i2c1_pins: i2c1 {
+ groups = "i2c1";
+ function = "i2c1";
+ };
+
+ i2c6_pins: i2c6 {
+ groups = "i2c6";
+ function = "i2c6";
+ };
+
+ mmc_pins: mmc {
+ groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
+ function = "mmc";
+ power-source = <1800>;
+ };
+
+ scif0_pins: scif0 {
+ groups = "scif0_data", "scif0_ctrl";
+ function = "scif0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk";
+ function = "scif_clk";
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+ status = "ok
[PATCH 24/30] ARM: dts: renesas: Add R8A779A0 V3U DT extras
From: Hai Pham
Add R8A779A0 V3U DT extras for U-Boot.
Based on "ARM: dts: renesas: Add R8A779A0 V3U DTs"
by Hai Pham
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a779a0-u-boot.dtsi | 12
1 file changed, 12 insertions(+)
create mode 100644 arch/arm/dts/r8a779a0-u-boot.dtsi
diff --git a/arch/arm/dts/r8a779a0-u-boot.dtsi
b/arch/arm/dts/r8a779a0-u-boot.dtsi
new file mode 100644
index 00..f6101289e8
--- /dev/null
+++ b/arch/arm/dts/r8a779a0-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on R-Car R8A779A0 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
--
2.30.2
[PATCH 20/30] pinctrl: renesas: Implement unlock register masks
The V3U SoC has several unlock registers, one per register group. They
reside at offset zero in each 0x200 bytes-sized block.
To avoid adding yet another table to the PFC implementation, this
patch adds the option to specify an address mask instead of the fixed
address in sh_pfc_soc_info::unlock_reg.
This is a direct port of Linux 5.12 commit e127ef2ed0a6
("pinctrl: renesas: Implement unlock register masks") by
Ulrich Hecht
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc.c| 39
drivers/pinctrl/renesas/sh_pfc.h | 2 +-
2 files changed, 20 insertions(+), 21 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 07fcc3d393..2498eb5716 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -131,14 +131,25 @@ u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
}
-void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
+static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
{
- void __iomem *unlock_reg =
- (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
+ u32 unlock;
+
+ if (!pfc->info->unlock_reg)
+ return;
- if (pfc->info->unlock_reg)
- sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
+ if (pfc->info->unlock_reg >= 0x8000UL)
+ unlock = pfc->info->unlock_reg;
+ else
+ /* unlock_reg is a mask */
+ unlock = reg & ~pfc->info->unlock_reg;
+
+ sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)unlock, 32, ~data);
+}
+void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
+{
+ sh_pfc_unlock_reg(pfc, reg, data);
sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
}
@@ -168,8 +179,6 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
unsigned int field, u32 value)
{
void __iomem *mapped_reg;
- void __iomem *unlock_reg =
- (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
unsigned int pos;
u32 mask, data;
@@ -186,9 +195,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
data &= mask;
data |= value;
- if (pfc->info->unlock_reg)
- sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
-
+ sh_pfc_unlock_reg(pfc, crp->reg, data);
sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}
@@ -679,8 +686,6 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc
*pfc,
unsigned int size;
unsigned int step;
void __iomem *reg;
- void __iomem *unlock_reg =
- (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
u32 val;
reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
@@ -701,9 +706,7 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc
*pfc,
val &= ~GENMASK(offset + 4 - 1, offset);
val |= strength << offset;
- if (unlock_reg)
- sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
-
+ sh_pfc_unlock_reg(pfc, (uintptr_t)reg, val);
sh_pfc_write_raw_reg(reg, 32, val);
return 0;
@@ -743,8 +746,6 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx,
unsigned _pin,
{
struct sh_pfc *pfc = pmx->pfc;
void __iomem *pocctrl;
- void __iomem *unlock_reg =
- (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
u32 addr, val;
int bit, ret;
@@ -790,9 +791,7 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx,
unsigned _pin,
else
val &= ~BIT(bit);
- if (unlock_reg)
- sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
-
+ sh_pfc_unlock_reg(pfc, addr, val);
sh_pfc_write_raw_reg(pocctrl, 32, val);
break;
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index 9d74f5fb4e..48d737a141 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -294,7 +294,7 @@ struct sh_pfc_soc_info {
const struct pinmux_irq *gpio_irq;
unsigned int gpio_irq_size;
- u32 unlock_reg;
+ u32 unlock_reg; /* can be literal address or mask */
};
u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
--
2.30.2
[PATCH 19/30] pinctrl: renesas: Fix R-Car Gen2 help text
The help text for Gen2 entries had a copy paste error, still containing the Gen3 string, while the description was correctly listing Gen2. Fix the help text. Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/Kconfig | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index c3a6594ebe..35f10e2c2b 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -15,31 +15,31 @@ config PINCTRL_PFC_R8A7790 bool "Renesas RCar Gen2 R8A7790 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7790 SoCs. + Support pin multiplexing control on Renesas RCar Gen2 R8A7790 SoCs. config PINCTRL_PFC_R8A7791 bool "Renesas RCar Gen2 R8A7791 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7791 SoCs. + Support pin multiplexing control on Renesas RCar Gen2 R8A7791 SoCs. config PINCTRL_PFC_R8A7792 bool "Renesas RCar Gen2 R8A7792 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7792 SoCs. + Support pin multiplexing control on Renesas RCar Gen2 R8A7792 SoCs. config PINCTRL_PFC_R8A7793 bool "Renesas RCar Gen2 R8A7793 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7793 SoCs. + Support pin multiplexing control on Renesas RCar Gen2 R8A7793 SoCs. config PINCTRL_PFC_R8A7794 bool "Renesas RCar Gen2 R8A7794 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7794 SoCs. + Support pin multiplexing control on Renesas RCar Gen2 R8A7794 SoCs. config PINCTRL_PFC_R8A774A1 bool "Renesas RZ/G2 R8A774A1 pin control driver" -- 2.30.2
[PATCH 14/30] clk: renesas: Add R8A779A0 clock tables
From: Hai Pham
Add clock tables for R8A779A0 V3U SoC from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12")
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
--
Marek: - Add .reset_modemr_offset
- Sync tables from Linux 5.12
- Rebase on latest u-boot
---
drivers/clk/renesas/Kconfig | 6 +
drivers/clk/renesas/Makefile| 1 +
drivers/clk/renesas/clk-rcar-gen3.c | 5 +
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 300
drivers/clk/renesas/rcar-gen3-cpg.h | 1 +
drivers/clk/renesas/renesas-cpg-mssr.c | 4 +
drivers/clk/renesas/renesas-cpg-mssr.h | 21 ++
7 files changed, 338 insertions(+)
create mode 100644 drivers/clk/renesas/r8a779a0-cpg-mssr.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 0c8b9eb47d..f4d6ef9f93 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -114,3 +114,9 @@ config CLK_R8A77995
depends on CLK_RCAR_GEN3
help
Enable this to support the clocks on Renesas R8A77995 SoC.
+
+config CLK_R8A779A0
+ bool "Renesas R8A779A0 clock driver"
+ depends on CLK_RCAR_GEN3
+ help
+ Enable this to support the clocks on Renesas R8A779A0 SoC.
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index ed1a1252c4..36a5ca65f4 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index c7dba341c1..6cf07fb418 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -418,6 +418,11 @@ int gen3_clk_probe(struct udevice *dev)
priv->info->control_regs = smstpcr;
priv->info->reset_regs = srcr;
priv->info->reset_clear_regs = srstclr;
+ } else if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
+ priv->info->status_regs = mstpsr_for_v3u;
+ priv->info->control_regs = mstpcr_for_v3u;
+ priv->info->reset_regs = srcr_for_v3u;
+ priv->info->reset_clear_regs = srstclr_for_v3u;
} else {
return -EINVAL;
}
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
new file mode 100644
index 00..bda6995236
--- /dev/null
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+
+#include
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A779A0_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL1,
+ CLK_PLL20,
+ CLK_PLL21,
+ CLK_PLL30,
+ CLK_PLL31,
+ CLK_PLL5,
+ CLK_PLL1_DIV2,
+ CLK_PLL20_DIV2,
+ CLK_PLL21_DIV2,
+ CLK_PLL30_DIV2,
+ CLK_PLL31_DIV2,
+ CLK_PLL5_DIV2,
+ CLK_PLL5_DIV4,
+ CLK_S1,
+ CLK_S3,
+ CLK_SDSRC,
+ CLK_RPCSRC,
+ CLK_OCO,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+#define DEF_PLL(_name, _id, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
+.offset = _offset)
+
+#define DEF_SD(_name, _id, _parent, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset)
+
+#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
+ DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \
+(_parent0) << 16 | (_parent1), \
+.div = (_div0) << 16 | (_div1), .offset = _md)
+
+#define DEF_OSC(_name, _id, _parent, _div) \
+ DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)
+
+static const struct cpg_core_clk r8a779a0_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
+ DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
+ DEF_PLL(".pll20", CLK_PLL20,0x0834),
+ DEF_PLL(".pll21", CLK_PLL21,0x0838),
+ DEF_PLL("
[PATCH 18/30] pinctrl: renesas: Deduplicate Kconfig
The help text in the Kconfig file was always a copy of the same thing. Move single copy into the common PFC driver entry instead. Also fix a copy-paste error in the PFC help text, which identified PFC as clock. Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/Kconfig | 74 +++-- 1 file changed, 5 insertions(+), 69 deletions(-) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 8fb9cba387..c3a6594ebe 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -5,7 +5,11 @@ config PINCTRL_PFC depends on DM && ARCH_RMOBILE default n if CPU_RZA1 help - Enable support for clock present on Renesas RCar SoCs. + Support pin multiplexing control on Renesas SoCs. + + These drivers are controlled by a device tree node which contains + both the GPIO definitions and pin control functions for each + available multiplex function. config PINCTRL_PFC_R8A7790 bool "Renesas RCar Gen2 R8A7790 pin control driver" @@ -13,160 +17,96 @@ config PINCTRL_PFC_R8A7790 help Support pin multiplexing control on Renesas RCar Gen3 R8A7790 SoCs. - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A7791 bool "Renesas RCar Gen2 R8A7791 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A7791 SoCs. - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A7792 bool "Renesas RCar Gen2 R8A7792 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A7792 SoCs. - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A7793 bool "Renesas RCar Gen2 R8A7793 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A7793 SoCs. - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A7794 bool "Renesas RCar Gen2 R8A7794 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A7794 SoCs. - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A774A1 bool "Renesas RZ/G2 R8A774A1 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RZ/G2M R8A774A1 SoCs. - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A774B1 bool "Renesas RZ/G2 R8A774B1 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RZ/G2N R8A774B1 SoCs. - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A774C0 bool "Renesas RZ/G2 R8A774C0 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RZ/G2E R8A774C0 SoCs. - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A774E1 bool "Renesas RZ/G2 R8A774E1 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs. - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A7795 bool "Renesas RCar Gen3 R8A7795 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs. - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config P
[PATCH 16/30] gpio: renesas: Handle R8A779A0 V3U INEN register
The R8A779A0 V3U GPIO block has additional "General Input Enable" INEN
register. Add new R8A779A0 compatible string with a new quirk and also
a handler for this quirk which toggles the INEN register in the right
place. INEN register handling is based on "gpio: renesas: Add R8A779A0
V3U support" by Hai Pham
Signed-off-by: Marek Vasut
---
drivers/gpio/gpio-rcar.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 5f1ec39a9b..76f47027a3 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -28,13 +28,17 @@
#define GPIO_EDGLEVEL 0x24/* Edge/level Select Register */
#define GPIO_FILONOFF 0x28/* Chattering Prevention On/Off Register */
#define GPIO_BOTHEDGE 0x4c/* One Edge/Both Edge Select Register */
+#define GPIO_INEN 0x50/* General Input Enable Register */
#define RCAR_MAX_GPIO_PER_BANK 32
+#define RCAR_GPIO_HAS_INEN BIT(0)
+
DECLARE_GLOBAL_DATA_PTR;
struct rcar_gpio_priv {
void __iomem*regs;
+ u32 quirks;
int pfc_offset;
};
@@ -81,6 +85,14 @@ static void rcar_gpio_set_direction(struct udevice *dev,
unsigned offset,
/* Configure postive logic in POSNEG */
clrbits_le32(regs + GPIO_POSNEG, BIT(offset));
+ /* Select "Input Enable/Disable" in INEN */
+ if (priv->quirks & RCAR_GPIO_HAS_INEN) {
+ if (output)
+ clrbits_le32(regs + GPIO_INEN, BIT(offset));
+ else
+ setbits_le32(regs + GPIO_INEN, BIT(offset));
+ }
+
/* Select "General Input/Output Mode" in IOINTSEL */
clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset));
@@ -149,6 +161,7 @@ static int rcar_gpio_probe(struct udevice *dev)
int ret;
priv->regs = dev_read_addr_ptr(dev);
+ priv->quirks = dev_get_driver_data(dev);
uc_priv->bank_name = dev->name;
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
@@ -179,6 +192,7 @@ static const struct udevice_id rcar_gpio_ids[] = {
{ .compatible = "renesas,gpio-r8a77970" },
{ .compatible = "renesas,gpio-r8a77990" },
{ .compatible = "renesas,gpio-r8a77995" },
+ { .compatible = "renesas,gpio-r8a779a0", .data = RCAR_GPIO_HAS_INEN },
{ .compatible = "renesas,rcar-gen2-gpio" },
{ .compatible = "renesas,rcar-gen3-gpio" },
{ /* sentinel */ }
--
2.30.2
[PATCH 12/30] clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling
Most of the PLLx, MAIN, FIXED clock handlers are calling very similar
code, which determines parent rate and then applies multiplication and
division. The only difference is whether multiplication is fixed factor
or coming from CRx register. Deduplicate the code into a single function.
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/clk-rcar-gen3.c | 86 ++---
1 file changed, 43 insertions(+), 43 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 49ab9134af..7b42e28e83 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -153,6 +153,30 @@ static int gen3_clk_disable(struct clk *clk)
return renesas_clk_endisable(clk, priv->base, priv->info, false);
}
+static u64 gen3_clk_get_rate64(struct clk *clk);
+
+static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
+ struct clk *parent,
+ const struct cpg_core_clk *core,
+ u32 mul_reg, u32 mult, u32 div,
+ char *name)
+{
+ u32 value;
+ u64 rate;
+
+ if (mul_reg) {
+ value = readl(priv->base + mul_reg);
+ mult = (((value >> 24) & 0x7f) + 1) * 2;
+ div = 1;
+ }
+
+ rate = (gen3_clk_get_rate64(parent) * mult) / div;
+
+ debug("%s[%i] %s clk: parent=%i mult=%u div=%u => rate=%llu\n",
+ __func__, __LINE__, name, core->parent, mult, div, rate);
+ return rate;
+}
+
static u64 gen3_clk_get_rate64(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
@@ -161,7 +185,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
const struct cpg_core_clk *core;
const struct rcar_gen3_cpg_pll_config *pll_config =
priv->cpg_pll_config;
- u32 value, mult, div, prediv, postdiv;
+ u32 value, div, prediv, postdiv;
u64 rate = 0;
int i, ret;
@@ -203,60 +227,36 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
return -EINVAL;
case CLK_TYPE_GEN3_MAIN:
- rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div;
- debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%llu\n",
- __func__, __LINE__,
- core->parent, pll_config->extal_div, rate);
- return rate;
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ 0, 1, pll_config->extal_div,
+ "MAIN");
case CLK_TYPE_GEN3_PLL0:
- value = readl(priv->base + CPG_PLL0CR);
- mult = (((value >> 24) & 0x7f) + 1) * 2;
- rate = gen3_clk_get_rate64(&parent) * mult;
- debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n",
- __func__, __LINE__, core->parent, mult, rate);
- return rate;
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ CPG_PLL0CR, 0, 0, "PLL0");
case CLK_TYPE_GEN3_PLL1:
- rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult;
- rate /= pll_config->pll1_div;
- debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",
- __func__, __LINE__,
- core->parent, pll_config->pll1_mult,
- pll_config->pll1_div, rate);
- return rate;
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ 0, pll_config->pll1_mult,
+ pll_config->pll1_div, "PLL1");
case CLK_TYPE_GEN3_PLL2:
- value = readl(priv->base + CPG_PLL2CR);
- mult = (((value >> 24) & 0x7f) + 1) * 2;
- rate = gen3_clk_get_rate64(&parent) * mult;
- debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n",
- __func__, __LINE__, core->parent, mult, rate);
- return rate;
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ CPG_PLL2CR, 0, 0, "PLL2");
case CLK_TYPE_GEN3_PLL3:
- rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult;
- rate /= pll_config->pll3_div;
- debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",
- __func__, __LINE__,
- core->parent, pll_config->pll3_mult,
- pll_config->pll3_div, rate);
- return rate;
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+
[PATCH 15/30] gpio: renesas: Pass struct udevice to rcar_gpio_set_direction()
Pass struct udevice to rcar_gpio_set_direction() in preparation of
quirk handling in rcar_gpio_set_direction(). No functional change.
Signed-off-by: Marek Vasut
---
drivers/gpio/gpio-rcar.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index daaac5e784..5f1ec39a9b 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -66,9 +66,12 @@ static int rcar_gpio_set_value(struct udevice *dev, unsigned
offset,
return 0;
}
-static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset,
+static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset,
bool output)
{
+ struct rcar_gpio_priv *priv = dev_get_priv(dev);
+ void __iomem *regs = priv->regs;
+
/*
* follow steps in the GPIO documentation for
* "Setting General Output Mode" and
@@ -90,9 +93,7 @@ static void rcar_gpio_set_direction(void __iomem *regs,
unsigned offset,
static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)
{
- struct rcar_gpio_priv *priv = dev_get_priv(dev);
-
- rcar_gpio_set_direction(priv->regs, offset, false);
+ rcar_gpio_set_direction(dev, offset, false);
return 0;
}
@@ -100,11 +101,9 @@ static int rcar_gpio_direction_input(struct udevice *dev,
unsigned offset)
static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
- struct rcar_gpio_priv *priv = dev_get_priv(dev);
-
/* write GPIO value to output before selecting output mode of pin */
rcar_gpio_set_value(dev, offset, value);
- rcar_gpio_set_direction(priv->regs, offset, true);
+ rcar_gpio_set_direction(dev, offset, true);
return 0;
}
--
2.30.2
[PATCH 13/30] clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code
On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value
from cpg_pll_configs table while PLL{20,21,30,31,4} use
different control offset. Introduce new types to handle
this and handle those types in the Gen3 clock code.
Based on "clk: renesas: Add support for R8A779A0 V3U PLLn"
by Hai Pham
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/clk-rcar-gen3.c | 24
drivers/clk/renesas/rcar-gen3-cpg.h | 9 +
2 files changed, 33 insertions(+)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 7b42e28e83..c7dba341c1 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -253,6 +253,28 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
CPG_PLL4CR, 0, 0, "PLL4");
+ case CLK_TYPE_R8A779A0_MAIN:
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ 0, 1, pll_config->extal_div,
+ "V3U_MAIN");
+
+ case CLK_TYPE_R8A779A0_PLL1:
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ 0, pll_config->pll1_mult,
+ pll_config->pll1_div,
+ "V3U_PLL1");
+
+ case CLK_TYPE_R8A779A0_PLL2X_3X:
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ core->offset, 0, 0,
+ "V3U_PLL2X_3X");
+
+ case CLK_TYPE_R8A779A0_PLL5:
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ 0, pll_config->pll5_mult,
+ pll_config->pll5_div,
+ "V3U_PLL5");
+
case CLK_TYPE_FF:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
0, core->mult, core->div,
@@ -268,6 +290,8 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
return rate;
case CLK_TYPE_GEN3_SD: /* FIXME */
+ fallthrough;
+ case CLK_TYPE_R8A779A0_SD:
value = readl(priv->base + core->offset);
value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h
b/drivers/clk/renesas/rcar-gen3-cpg.h
index 4fce0a9946..aa940a1ca2 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -27,6 +27,13 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_E3_RPCSRC,
CLK_TYPE_GEN3_RPC,
CLK_TYPE_GEN3_RPCD2,
+ CLK_TYPE_R8A779A0_MAIN,
+ CLK_TYPE_R8A779A0_PLL1,
+ CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */
+ CLK_TYPE_R8A779A0_PLL5,
+ CLK_TYPE_R8A779A0_SD,
+ CLK_TYPE_R8A779A0_MDSEL,/* Select parent/divider using mode pin
*/
+ CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
/* SoC specific definitions start here */
CLK_TYPE_GEN3_SOC_BASE,
@@ -69,6 +76,8 @@ struct rcar_gen3_cpg_pll_config {
u8 pll3_mult;
u8 pll3_div;
u8 osc_prediv;
+ u8 pll5_mult;
+ u8 pll5_div;
};
#define CPG_RST_MODEMR 0x060
--
2.30.2
[PATCH 11/30] clk: renesas: Add register pointers into struct cpg_mssr_info
From: Hai Pham
Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda
To support other register layouts in the future, add register pointers
of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/clk-rcar-gen3.c| 9 +
drivers/clk/renesas/renesas-cpg-mssr.c | 49 ++--
drivers/clk/renesas/renesas-cpg-mssr.h | 52 ++
3 files changed, 65 insertions(+), 45 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 27939d6318..49ab9134af 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -389,6 +389,15 @@ int gen3_clk_probe(struct udevice *dev)
priv->sscg = !(cpg_mode & BIT(12));
+ if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
+ priv->info->status_regs = mstpsr;
+ priv->info->control_regs = smstpcr;
+ priv->info->reset_regs = srcr;
+ priv->info->reset_clear_regs = srstclr;
+ } else {
+ return -EINVAL;
+ }
+
ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
if (ret < 0)
return ret;
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c
b/drivers/clk/renesas/renesas-cpg-mssr.c
index 0cf80a9866..b1cf7f599c 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -22,47 +22,6 @@
#include "renesas-cpg-mssr.h"
-/*
- * Module Standby and Software Reset register offets.
- *
- * If the registers exist, these are valid for SH-Mobile, R-Mobile,
- * R-Car Gen2, R-Car Gen3, and RZ/G1.
- * These are NOT valid for R-Car Gen1 and RZ/A1!
- */
-
-/*
- * Module Stop Status Register offsets
- */
-
-static const u16 mstpsr[] = {
- 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
- 0x9A0, 0x9A4, 0x9A8, 0x9AC,
-};
-
-#defineMSTPSR(i) mstpsr[i]
-
-
-/*
- * System Module Stop Control Register offsets
- */
-
-static const u16 smstpcr[] = {
- 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
- 0x990, 0x994, 0x998, 0x99C,
-};
-
-#defineSMSTPCR(i) smstpcr[i]
-
-
-/* Realtime Module Stop Control Register offsets */
-#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10)
-
-/* Modem Module Stop Control Register offsets (r8a73a4) */
-#define MMSTPCR(i) (smstpcr[i] + 0x20)
-
-/* Software Reset Clearing Register offsets */
-#defineSRSTCLR(i) (0x940 + (i) * 4)
-
bool renesas_clk_is_mod(struct clk *clk)
{
return (clk->id >> 16) == CPG_MOD;
@@ -147,11 +106,11 @@ int renesas_clk_endisable(struct clk *clk, void __iomem
*base,
clkid, reg, bit, enable ? "ON" : "OFF");
if (enable) {
- clrbits_le32(base + SMSTPCR(reg), bitmask);
- return wait_for_bit_le32(base + MSTPSR(reg),
+ clrbits_le32(base + info->control_regs[reg], bitmask);
+ return wait_for_bit_le32(base + info->status_regs[reg],
bitmask, 0, 100, 0);
} else {
- setbits_le32(base + SMSTPCR(reg), bitmask);
+ setbits_le32(base + info->control_regs[reg], bitmask);
return 0;
}
}
@@ -165,7 +124,7 @@ int renesas_clk_remove(void __iomem *base, struct
cpg_mssr_info *info)
/* Stop module clock */
for (i = 0; i < info->mstp_table_size; i++) {
- clrsetbits_le32(base + SMSTPCR(i),
+ clrsetbits_le32(base + info->control_regs[i],
info->mstp_table[i].sdis,
info->mstp_table[i].sen);
clrsetbits_le32(base + RMSTPCR(i),
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h
b/drivers/clk/renesas/renesas-cpg-mssr.h
index 3c3b128c4c..92421b15ee 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -37,6 +37,10 @@ struct cpg_mssr_info {
unsigned intclk_extal_usb_id;
unsigned intpll0_div;
const void *(*get_pll_config)(const u32 cpg_mode);
+ const u16 *status_regs;
+ const u16 *control_regs;
+ const u16 *reset_regs;
+ const u16 *reset_clear_regs;
};
/*
@@ -125,4 +129,52 @@ int renesas_clk_endisable(struct clk *clk, void __iomem
*base,
struct cpg_mssr_info *info, bool enable);
int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
+/*
+ * Module Standby and Software Reset register offets.
+ *
+ * If the registers exist, these are valid for SH-Mobile, R-Mobile,
+ * R-Car Gen2, R-Car Gen3, and RZ/G1.
+ * These are NOT valid for R-Car Gen1 and RZ/A1!
+ */
+
+/*
+ * Module Stop Status Register
[PATCH 09/30] clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable()
From: Hai Pham
CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC)
requires a different setting procedure. Make struct cpg_mssr_info
accessible to handle the clock setting in that case.
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/clk-rcar-gen2.c| 4 ++--
drivers/clk/renesas/clk-rcar-gen3.c| 4 ++--
drivers/clk/renesas/renesas-cpg-mssr.c | 3 ++-
drivers/clk/renesas/renesas-cpg-mssr.h | 3 ++-
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c
b/drivers/clk/renesas/clk-rcar-gen2.c
index b0164a6486..d2d0169dd8 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -61,14 +61,14 @@ static int gen2_clk_enable(struct clk *clk)
{
struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, true);
+ return renesas_clk_endisable(clk, priv->base, priv->info, true);
}
static int gen2_clk_disable(struct clk *clk)
{
struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, false);
+ return renesas_clk_endisable(clk, priv->base, priv->info, false);
}
static ulong gen2_clk_get_rate(struct clk *clk)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 938d98546b..27939d6318 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -143,14 +143,14 @@ static int gen3_clk_enable(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, true);
+ return renesas_clk_endisable(clk, priv->base, priv->info, true);
}
static int gen3_clk_disable(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, false);
+ return renesas_clk_endisable(clk, priv->base, priv->info, false);
}
static u64 gen3_clk_get_rate64(struct clk *clk)
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c
b/drivers/clk/renesas/renesas-cpg-mssr.c
index bed2a16448..0cf80a9866 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -132,7 +132,8 @@ int renesas_clk_get_parent(struct clk *clk, struct
cpg_mssr_info *info,
return 0;
}
-int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable)
+int renesas_clk_endisable(struct clk *clk, void __iomem *base,
+ struct cpg_mssr_info *info, bool enable)
{
const unsigned long clkid = clk->id & 0x;
const unsigned int reg = clkid / 100;
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h
b/drivers/clk/renesas/renesas-cpg-mssr.h
index ad5d269fc4..8c8a09b904 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -115,7 +115,8 @@ int renesas_clk_get_core(struct clk *clk, struct
cpg_mssr_info *info,
const struct cpg_core_clk **core);
int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
struct clk *parent);
-int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
+int renesas_clk_endisable(struct clk *clk, void __iomem *base,
+ struct cpg_mssr_info *info, bool enable);
int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
--
2.30.2
[PATCH 03/30] clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12
Synchronize R-Car Gen3 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 58 ++-
drivers/clk/renesas/r8a7796-cpg-mssr.c | 58 +++
drivers/clk/renesas/r8a77965-cpg-mssr.c | 58 +++
drivers/clk/renesas/r8a77970-cpg-mssr.c | 132
drivers/clk/renesas/r8a77990-cpg-mssr.c | 37 ---
drivers/clk/renesas/r8a77995-cpg-mssr.c | 16 +--
drivers/clk/renesas/rcar-gen3-cpg.h | 16 +--
7 files changed, 212 insertions(+), 163 deletions(-)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index b137564962..ca74250276 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -41,8 +41,8 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
- CLK_RPCSRC,
CLK_SSPSRC,
+ CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@@ -69,13 +69,18 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".rpcsrc",CLK_RPCSRC,CLK_PLL1, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
+CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+R8A7795_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
- DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
- DEF_BASE("z2", R8A7795_CLK_Z2,CLK_TYPE_GEN3_Z2, CLK_PLL2),
+ DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0,
2, 8),
+ DEF_GEN3_Z("z2",R8A7795_CLK_Z2,CLK_TYPE_GEN3_Z, CLK_PLL2,
2, 0),
DEF_FIXED("ztr",R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7795_CLK_ZT,CLK_PLL1_DIV2, 4, 1),
@@ -102,8 +107,6 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
- DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC,0x238),
-
DEF_FIXED("cl", R8A7795_CLK_CL,CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cr", R8A7795_CLK_CR,CLK_PLL1_DIV4, 2, 1),
DEF_FIXED("cp", R8A7795_CLK_CP,CLK_EXTAL, 2, 1),
@@ -132,14 +135,15 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("msiof2",209, R8A7795_CLK_MSO),
DEF_MOD("msiof1",210, R8A7795_CLK_MSO),
DEF_MOD("msiof0",211, R8A7795_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
- DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
+ DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
DEF_MOD("cmt3", 300, R8A7795_CLK_R),
DEF_MOD("cmt2", 301, R8A7795_CLK_R),
DEF_MOD("cmt1", 302, R8A7795_CLK_R),
DEF_MOD("cmt0", 303, R8A7795_CLK_R),
+ DEF_MOD("tpu0", 304, R8A7795_CLK_S3D4),
DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
@@ -156,16 +160,16 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("rwdt", 402, R8A7795_CLK_R),
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
- DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
- DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
- DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
- DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
- DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
- DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
- DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
- DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
- DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
+ DEF_MOD
[PATCH 08/30] clk: renesas: Make reset controller modemr register offset configurable
The MODEMR register offset changed on R8A779A0, make the MODEMR offset
configurable. Fill the offset in on all clock drivers. No functional
change.
Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from
struct cpg_mssr_info" by Hai Pham
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/clk-rcar-gen2.c | 2 --
drivers/clk/renesas/clk-rcar-gen3.c | 4 +---
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a774b1-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a774e1-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a7790-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a7791-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a7792-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a7794-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a77980-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 +
drivers/clk/renesas/rcar-gen2-cpg.h | 2 ++
drivers/clk/renesas/rcar-gen3-cpg.h | 2 ++
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
20 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c
b/drivers/clk/renesas/clk-rcar-gen2.c
index b423c9414b..b0164a6486 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -23,8 +23,6 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"
-#define CPG_RST_MODEMR 0x0060
-
#define CPG_PLL0CR 0x00d8
#define CPG_SDCKCR 0x0074
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 763e268937..938d98546b 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -25,8 +25,6 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
-#define CPG_RST_MODEMR 0x0060
-
#define CPG_PLL0CR 0x00d8
#define CPG_PLL2CR 0x002c
#define CPG_PLL4CR 0x01f4
@@ -382,7 +380,7 @@ int gen3_clk_probe(struct udevice *dev)
if (rst_base == FDT_ADDR_T_NONE)
return -EINVAL;
- cpg_mode = readl(rst_base + CPG_RST_MODEMR);
+ cpg_mode = readl(rst_base + info->reset_modemr_offset);
priv->cpg_pll_config =
(struct rcar_gen3_cpg_pll_config
*)info->get_pll_config(cpg_mode);
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index ef2bb6d777..48da65cd3d 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -321,6 +321,7 @@ static const struct cpg_mssr_info r8a774a1_cpg_mssr_info = {
.mstp_table = r8a774a1_mstp_table,
.mstp_table_size= ARRAY_SIZE(r8a774a1_mstp_table),
.reset_node = "renesas,r8a774a1-rst",
+ .reset_modemr_offset= CPG_RST_MODEMR,
.extalr_node= "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index a8b242dc47..418c393a20 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -318,6 +318,7 @@ static const struct cpg_mssr_info r8a774b1_cpg_mssr_info = {
.mstp_table = r8a774b1_mstp_table,
.mstp_table_size= ARRAY_SIZE(r8a774b1_mstp_table),
.reset_node = "renesas,r8a774b1-rst",
+ .reset_modemr_offset= CPG_RST_MODEMR,
.extalr_node= "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 6e9558a107..c1283d2614 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -292,6 +292,7 @@ const struct cpg_mssr_info r8a774c0_cpg_mssr_info = {
.mstp_table = r8a774c0_mstp_table,
.mstp_table_size= ARRAY_SIZE(r8a774c0_mstp_table),
.reset_node = "renesas,r8a774c0-rst",
+ .reset_modemr_offset= CPG_RST_MODEMR,
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = ~0,
diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
index c969ec6888..0cacd8d0c8 100644
--- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
@@ -332,6 +332,7 @@ static const struct cpg_mssr_info r8a774e1_cpg_mssr_info = {
.mstp_table = r8a774e1_mstp_table,
.mstp_table_size= ARRAY_SIZE(r8a774e1_mstp_table),
.reset_node = "renesas,r8a774e1-rst",
+
[PATCH 10/30] clk: renesas: Introduce enum clk_reg_layout
From: Hai Pham
>From Linux v5.10-rc2, commit ffbf9cf3f946 by Yoshihiro Shimoda
Introduce enum clk_reg_layout to support multiple register layout variants
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/renesas-cpg-mssr.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h
b/drivers/clk/renesas/renesas-cpg-mssr.h
index 8c8a09b904..3c3b128c4c 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -14,9 +14,15 @@
#define __DRIVERS_CLK_RENESAS_CPG_MSSR__
#include
+
+enum clk_reg_layout {
+ CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
+};
+
struct cpg_mssr_info {
const struct cpg_core_clk *core_clk;
unsigned intcore_clk_size;
+ enum clk_reg_layout reg_layout;
const struct mssr_mod_clk *mod_clk;
unsigned intmod_clk_size;
const struct mstp_stop_table*mstp_table;
--
2.30.2
[PATCH 05/30] clk: renesas: Fix incorrect return RPC clk_get_rate
From: Hai Pham RPC clk_get_rate will return error code instead of expected clock rate. Fix this. Signed-off-by: Hai Pham Signed-off-by: Marek Vasut --- drivers/clk/renesas/clk-rcar-gen3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 3223becd75..09d84c44e1 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -310,7 +310,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk) __func__, __LINE__, core->parent, prediv, postdiv, rate); - return -EINVAL; + return rate; } -- 2.30.2
[PATCH 06/30] clk: renesas: Fix Realtime Module Stop Control Register offsets
From: Hai Pham
This patch fixes Realtime Module Stop Control Register (RMSTPCR) offsets
based on R-Car Gen3, H2/M2/M2N/E2/E2X hardware user's manual.
The r8a73a4 only has RMSTPCR0 - RMSTPCR5 so this calculation change
doesn't affect it.
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/renesas-cpg-mssr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c
b/drivers/clk/renesas/renesas-cpg-mssr.c
index 7c1222f6c8..bed2a16448 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -55,7 +55,7 @@ static const u16 smstpcr[] = {
/* Realtime Module Stop Control Register offsets */
-#define RMSTPCR(i) (smstpcr[i] - 0x20)
+#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10)
/* Modem Module Stop Control Register offsets (r8a73a4) */
#define MMSTPCR(i) (smstpcr[i] + 0x20)
--
2.30.2
[PATCH 07/30] clk: renesas: Add support for RPCD2 clock
From: Hai Pham
This supports RPCD2 clock handling. While at it, add the check point
for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd
number
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/clk-rcar-gen3.c | 19 ++-
drivers/clk/renesas/rcar-gen3-cpg.h | 3 +++
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 09d84c44e1..763e268937 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -289,6 +289,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
return -EINVAL;
case CLK_TYPE_GEN3_RPC:
+ case CLK_TYPE_GEN3_RPCD2:
rate = gen3_clk_get_rate64(&parent);
value = readl(priv->base + core->offset);
@@ -304,13 +305,21 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
CPG_RPC_POSTDIV_MASK;
- rate /= postdiv + 1;
- debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i =>
rate=%llu\n",
- __func__, __LINE__,
- core->parent, prediv, postdiv, rate);
+ if (postdiv % 2 != 0) {
+ rate /= postdiv + 1;
- return rate;
+ if (core->type == CLK_TYPE_GEN3_RPCD2)
+ rate /= 2;
+
+ debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i
=> rate=%llu\n",
+ __func__, __LINE__,
+ core->parent, prediv, postdiv, rate);
+
+ return rate;
+ }
+
+ return -EINVAL;
}
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h
b/drivers/clk/renesas/rcar-gen3-cpg.h
index 8265c96cf6..52526a0cab 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -35,6 +35,9 @@ enum rcar_gen3_clk_types {
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
+#define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset)
+
#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
(_parent0) << 16 | (_parent1), \
--
2.30.2
[PATCH 04/30] clk: renesas: Reinstate RPC clock on R-Car D3/E3
Reinstate RPC clock on D3/E3 after Linux 5.12 synchronization.
The D3 and E3 clock drivers do not contain RPC clock entries
mainline Linux yet.
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a77990-cpg-mssr.c | 9 +
drivers/clk/renesas/r8a77995-cpg-mssr.c | 9 +
2 files changed, 18 insertions(+)
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c
b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 504dc871d1..d953c0b421 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -44,6 +44,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
CLK_OCO,
@@ -74,6 +75,13 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc",CLK_SDSRC, CLK_PLL1, 2, 1),
+ DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC,
+CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+R8A77990_CLK_RPC),
+
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO,8 * 1000 * 1000),
@@ -211,6 +219,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
DEF_MOD("can-fd",914, R8A77990_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4),
+ DEF_MOD("rpc", 917, R8A77990_CLK_RPC),
DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c
b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 58dc295d6a..0771c48964 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -42,6 +42,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
CLK_OCO,
@@ -70,6 +71,13 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc",CLK_SDSRC, CLK_PLL1, 2, 1),
+ DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC,
+CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+R8A77995_CLK_RPC),
+
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO,8 * 1000 * 1000),
@@ -171,6 +179,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
DEF_MOD("can-fd",914, R8A77995_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
+ DEF_MOD("rpc", 917, R8A77995_CLK_RPC),
DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
--
2.30.2
[PATCH 01/30] clk: renesas: Synchronize RZ/G2 tables with Linux 5.12
Synchronize RZ/G2 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 14 +-
drivers/clk/renesas/r8a774b1-cpg-mssr.c | 8
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 9 +
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 1c54eca6c0..ef2bb6d777 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -68,13 +68,18 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".rpcsrc",CLK_RPCSRC,CLK_PLL1, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,
+CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+R8A774A1_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
- DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0,
2, 8),
- DEF_GEN3_Z("z2",R8A774A1_CLK_Z2,CLK_TYPE_GEN3_Z, CLK_PLL2,
2, 0),
+ DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0,
2, 8),
+ DEF_GEN3_Z("z2",R8A774A1_CLK_Z2,CLK_TYPE_GEN3_Z, CLK_PLL2,
2, 0),
DEF_FIXED("ztr",R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774A1_CLK_ZT,CLK_PLL1_DIV2, 4, 1),
@@ -99,7 +104,6 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
- DEF_GEN3_RPC("rpc", R8A774A1_CLK_RPC, CLK_RPCSRC,0x238),
DEF_FIXED("cl", R8A774A1_CLK_CL,CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A774A1_CLK_CP,CLK_EXTAL, 2, 1),
@@ -203,7 +207,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] = {
DEF_MOD("can-fd",914, R8A774A1_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4),
- DEF_MOD("rpc", 917, R8A774A1_CLK_RPC),
+ DEF_MOD("rpc-if",917, R8A774A1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index 03851d0b5a..a8b242dc47 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -39,6 +39,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@@ -64,6 +65,12 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = {
DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
+CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+R8A774B1_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
@@ -195,6 +202,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] = {
DEF_MOD("can-fd",914, R8A774B1_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
+ DEF_MOD("rpc-if",917, R8A774B1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 37a7123f73..6e9558a107 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -44,6 +44,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
[PATCH 02/30] clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12
Synchronize R-Car Gen2 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a7790-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a7792-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a7794-cpg-mssr.c | 2 +-
drivers/clk/renesas/rcar-gen2-cpg.h| 5 +
5 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c
b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index d5079da3ff..8d616476c7 100644
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -108,8 +108,8 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] = {
DEF_MOD("tmu0", 125, R8A7790_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS),
- DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS),
- DEF_MOD("vsp1-sy", 131, R8A7790_CLK_ZS),
+ DEF_MOD("vspr", 130, R8A7790_CLK_ZS),
+ DEF_MOD("vsps", 131, R8A7790_CLK_ZS),
DEF_MOD("scifa2",202, R8A7790_CLK_MP),
DEF_MOD("scifa1",203, R8A7790_CLK_MP),
DEF_MOD("scifa0",204, R8A7790_CLK_MP),
diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c
b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index fa0e275afd..7a89613b32 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -106,7 +106,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] = {
DEF_MOD("tmu0", 125, R8A7791_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS),
- DEF_MOD("vsp1-sy", 131, R8A7791_CLK_ZS),
+ DEF_MOD("vsps", 131, R8A7791_CLK_ZS),
DEF_MOD("scifa2",202, R8A7791_CLK_MP),
DEF_MOD("scifa1",203, R8A7791_CLK_MP),
DEF_MOD("scifa0",204, R8A7791_CLK_MP),
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c
b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index d2225a3ff5..e18774dae4 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -88,7 +88,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] = {
DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
- DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS),
+ DEF_MOD("vsps", 131, R8A7792_CLK_ZS),
DEF_MOD("msiof1",208, R8A7792_CLK_MP),
DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c
b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index d05f89deb1..790bc1bbd9 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -97,7 +97,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] = {
DEF_MOD("cmt0", 124, R8A7794_CLK_R),
DEF_MOD("tmu0", 125, R8A7794_CLK_CP),
DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS),
- DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS),
+ DEF_MOD("vsps", 131, R8A7794_CLK_ZS),
DEF_MOD("scifa2",202, R8A7794_CLK_MP),
DEF_MOD("scifa1",203, R8A7794_CLK_MP),
DEF_MOD("scifa0",204, R8A7794_CLK_MP),
diff --git a/drivers/clk/renesas/rcar-gen2-cpg.h
b/drivers/clk/renesas/rcar-gen2-cpg.h
index 913c932620..2739480dad 100644
--- a/drivers/clk/renesas/rcar-gen2-cpg.h
+++ b/drivers/clk/renesas/rcar-gen2-cpg.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* R-Car Gen2 Clock Pulse Generator
*
* Copyright (C) 2016 Cogent Embedded Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation; version 2 of the License.
*/
#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
--
2.30.2
Re: [PATCH 1/5] clk: ti: add custom API for memory access
Hi Tero,
> Il 27/04/2021 09:01 Tero Kristo ha scritto:
>
>
> Hi Dario,
>
> One question below.
>
> On 25/04/2021 17:17, Dario Binacchi wrote:
> > As pointed by [1] and [2], commit
> > d64b9cdcd4 ("fdt: translate address if #size-cells = <0>") is wrong:
> > - It makes every 'reg' DT property translatable. It changes the address
> >translation so that for an I2C 'reg' address you'll get back as reg
> >the I2C controller address + reg value.
> > - The quirk must be fixed with platform code.
> >
> > The clk_ti_get_reg_addr() is the platform code able to make the correct
> > address translation for the AM33xx clocks registers. Its implementation
> > was inspired by the Linux Kernel code.
> >
> > [1]
> > https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng...@gmail.com/
> > [2]
> > https://lore.kernel.org/linux-clk/20210402192054.7934-1-dario...@libero.it/T/
> >
> > Signed-off-by: Dario Binacchi
> > ---
> >
> > drivers/clk/ti/clk.c | 92
> > drivers/clk/ti/clk.h | 13 +++
> > 2 files changed, 105 insertions(+)
> >
> > diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
> > index c999df213a..68abe053cb 100644
> > --- a/drivers/clk/ti/clk.c
> > +++ b/drivers/clk/ti/clk.c
> > @@ -6,10 +6,23 @@
> >*/
> >
> > #include
> > +#include
> > #include
> > +#include
> > #include
> > +#include
> > #include "clk.h"
> >
> > +#define CLK_MAX_MEMMAPS 10
> > +
> > +struct clk_iomap {
> > + struct regmap *regmap;
> > + ofnode node;
> > +};
> > +
> > +static unsigned int clk_memmaps_num;
> > +static struct clk_iomap clk_memmaps[CLK_MAX_MEMMAPS];
> > +
> > static void clk_ti_rmw(u32 val, u32 mask, fdt_addr_t reg)
> > {
> > u32 v;
> > @@ -33,3 +46,82 @@ void clk_ti_latch(fdt_addr_t reg, s8 shift)
> > clk_ti_rmw(0, latch, reg);
> > readl(reg); /* OCP barrier */
> > }
> > +
> > +void clk_ti_writel(u32 val, struct clk_ti_reg *reg)
> > +{
> > + struct clk_iomap *io = &clk_memmaps[reg->index];
> > +
> > + regmap_write(io->regmap, reg->offset, val);
> > +}
> > +
> > +u32 clk_ti_readl(struct clk_ti_reg *reg)
> > +{
> > + struct clk_iomap *io = &clk_memmaps[reg->index];
> > + u32 val;
> > +
> > + regmap_read(io->regmap, reg->offset, &val);
> > + return val;
> > +}
> > +
> > +#if CONFIG_IS_ENABLED(AM33XX)
>
> Why do you have this ifdef here? These drivers are not planned to be
> used by anything but am33xx, or they don't work on any other device?
>
The patch was developed and tested for the AM33XX SOC (beaglebone black).
The drivers in the clk/ti folder were added by my patches but can also be
used by boards based on different device trees. In those cases, if required,
platform versions of clk_ti_get_regmap_node() could be implemented.
Thanks and regards,
Dario
> -Tero
>
> > +static ofnode clk_ti_get_regmap_node(struct udevice *dev)
> > +{
> > + ofnode node = dev_ofnode(dev), parent;
> > +
> > + if (!ofnode_valid(node))
> > + return ofnode_null();
> > +
> > + parent = ofnode_get_parent(node);
> > + if (strcmp(ofnode_get_name(parent), "clocks"))
> > + return ofnode_null();
> > +
> > + return ofnode_get_parent(parent);
> > +}
> > +#else
> > +static ofnode clk_ti_get_regmap_node(struct udevice *dev)
> > +{
> > + return ofnode_null();
> > +}
> > +#endif
> > +
> > +int clk_ti_get_reg_addr(struct udevice *dev, int index, struct clk_ti_reg
> > *reg)
> > +{
> > + ofnode node;
> > + int i, ret;
> > + u32 val;
> > +
> > + ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", index, &val);
> > + if (ret) {
> > + dev_err(dev, "%s must have reg[%d]\n", ofnode_get_name(node),
> > + index);
> > + return ret;
> > + }
> > +
> > + /* parent = ofnode_get_parent(parent); */
> > + node = clk_ti_get_regmap_node(dev);
> > + if (!ofnode_valid(node)) {
> > + dev_err(dev, "failed to get regmap node\n");
> > + return -EFAULT;
> > + }
> > +
> > + for (i = 0; i < clk_memmaps_num; i++) {
> > + if (ofnode_equal(clk_memmaps[i].node, node))
> > + break;
> > + }
> > +
> > + if (i == clk_memmaps_num) {
> > + if (i == CLK_MAX_MEMMAPS)
> > + return -ENOMEM;
> > +
> > + ret = regmap_init_mem(node, &clk_memmaps[i].regmap);
> > + if (ret)
> > + return ret;
> > +
> > + clk_memmaps[i].node = node;
> > + clk_memmaps_num++;
> > + }
> > +
> > + reg->index = i;
> > + reg->offset = val;
> > + return 0;
> > +}
> > diff --git a/drivers/clk/ti/clk.h b/drivers/clk/ti/clk.h
> > index 601c3823f7..ea36d065ac 100644
> > --- a/drivers/clk/ti/clk.h
> > +++ b/drivers/clk/ti/clk.h
> > @@ -9,5 +9,18 @@
> > #define _CLK_TI_H
> >
> > void clk_ti_latch(fdt_addr_t reg, s8 shift);
> > +/**
> > + * struct clk_ti_reg - TI register declaration
> > + * @offset: offset f
RE: [PATCH 7/7] doc: imx8mp-evk: update after using binman
> -Original Message- > From: U-Boot On Behalf Of Peter Bergin > Sent: Tuesday, April 6, 2021 8:59 AM > To: u-boot@lists.denx.de > Subject: Re: [PATCH 7/7] doc: imx8mp-evk: update after using binman > > > Hi, > > On 2021-04-06 05:59, Peng Fan (OSS) wrote: > > Burn the flash.bin to the MicroSD card at offset 32KB: > > > > .. code-block:: bash > > > > $sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 > > conv=notrunc; sync > > + $sudo dd if=build/u-boot.itb of=/dev/sd[x] bs=1K seek=384 > > + conv=notrunc; sync > > Why is this changed to 'seek=384'? Comment still states 'offset 32KB' > and reference manual states that Primary Image Offset for SD card shall be > 32KB. > Can you explain a bit more around this? I'd also be interested in a more detailed explanation of this change, since the documentation is not quite descriptive about this added step. How the magic new offset is handled and why is it chosen to be 384? I see this change was made *exactly in the same way* across Mini, Nano and Plus SOCs of i.MX8M family, hence I believe it does deserve a good description. > > Thanks, > /Peter Thanks a lot! -- andrey
Re: [PATCH] net: phy: xilinx: Break while loop over ethernet phy
Hi Michal,
On Thu, Apr 29, 2021 at 12:17 AM Michal Simek wrote:
>
> Hi Bin,
>
> On 4/28/21 5:57 PM, Bin Meng wrote:
> > Hi Michal,
> >
> > On Wed, Apr 28, 2021 at 11:03 PM Michal Simek
> > wrote:
> >>
> >> Hi Bin,
> >>
> >> On 4/28/21 4:37 PM, Bin Meng wrote:
> >>> Hi Michal,
> >>>
> >>> On Tue, Apr 27, 2021 at 7:22 PM Michal Simek
> >>> wrote:
>
> Hi Bin,
>
> On 4/27/21 7:17 AM, Bin Meng wrote:
> > Hi Michal,
> >
> > On Mon, Apr 26, 2021 at 8:31 PM Michal Simek
> > wrote:
> >>
> >> The commit 6c993815bbea ("net: phy: xilinx: Be compatible with live OF
> >> tree") change driver behavior to while loop which wasn't correct
> >> because
> >> the driver was looping over again and again. The reason was that
> >> ofnode_valid() is taking 0 as correct value.
> >
> > I am still trying to understand the problem. The changes in
> > 6c993815bbea sound correct from an fdtdec <=> OF API mapping
> > perspective. If the new OF API does not work, the old fdtdec may fail
> > too. Could you please explain a little bit?
>
> here is behavior of origin code.
>
> ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id
> phy_connect_gmii2rgmii sn 11348
> phy_connect_gmii2rgmii 1off -1
> phy_connect_gmii2rgmii 2off -1
> phy_connect_gmii2rgmii sn2 11752
> phy_connect_gmii2rgmii 1off -1
> phy_connect_gmii2rgmii 2off -1
> phy_connect_gmii2rgmii sn2 -1
> phy_connect_gmii2rgmii phydev
> eth0: ethernet@ff0e
> Scanning disk m...@ff17.blk...
> Found 4 disks
> Hit any key to stop autoboot: 0
> ZynqMP>
>
>
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index 89e3076bfd25..d0960d93ae08 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -956,22 +956,28 @@ static struct phy_device
> *phy_connect_gmii2rgmii(struct mii_dev *bus,
> int sn = dev_of_offset(dev);
> int off;
>
> + printf("%s sn %d\n", __func__, sn);
> while (sn > 0) {
> off = fdt_node_offset_by_compatible(gd->fdt_blob, sn,
>
> "xlnx,gmii-to-rgmii-1.0");
> + printf("%s 1off %d\n", __func__, off);
> if (off > 0) {
> phydev = phy_device_create(bus, off,
> PHY_GMII2RGMII_ID,
> false,
> interface);
> break;
> }
> - if (off == -FDT_ERR_NOTFOUND)
> + printf("%s 2off %d\n", __func__, off);
> +
> + if (off == -FDT_ERR_NOTFOUND) {
> sn = fdt_first_subnode(gd->fdt_blob, sn);
> - else
> + printf("%s sn2 %d\n", __func__, sn);
> + } else
> printf("%s: Error finding compat string:%d\n",
> __func__, off);
> }
>
> + printf("%s phydev %p\n", __func__, phydev);
> return phydev;
> }
> #endif
>
>
> With latest code and some prints
> ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset 2952
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset -1
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset 11348
> phy_connect_gmii2rgmii 1valid 1 ethernet@ff0e
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset 11348
> phy_connect_gmii2rgmii 2valid 1 ethernet@ff0e
> ofnode_valid: node.of_offset -1
> ofnode_valid: node.of_offset -1
> ofnode_valid: node.of_offset 0
> ofnode_valid: node.of_offset 0
> phy_connect_gmii2rgmii 3valid 1
> ofnode_valid: node.of_offset 0
> ofnode_valid: node.of_offset 0
> ofnode_valid: node.of_offset 0
> phy_connect_gmii2rgmii 2valid 1
> ofnode_valid: node.of_offset -1
> ofnode_valid: node.of_offset -1
> ofnode_valid: node.of_offset 0
> ofnode_valid: node.of_offset 0
> phy_connect_gmii2rgmii 3valid 1
> ...
>
>
> [u-boot](debian-sent)$ git diff
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index dcdef9e661d6..56072ad55216 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -950,7 +950,10 @@ static struct phy_device
> *phy_connect_gmii2rgmii(struct mii_dev *bus,
> struct phy_device *phydev = NULL;
> ofnode node =
Re: [PATCH] net: phy: xilinx: Break while loop over ethernet phy
Hi Bin,
On 4/28/21 5:57 PM, Bin Meng wrote:
> Hi Michal,
>
> On Wed, Apr 28, 2021 at 11:03 PM Michal Simek wrote:
>>
>> Hi Bin,
>>
>> On 4/28/21 4:37 PM, Bin Meng wrote:
>>> Hi Michal,
>>>
>>> On Tue, Apr 27, 2021 at 7:22 PM Michal Simek
>>> wrote:
Hi Bin,
On 4/27/21 7:17 AM, Bin Meng wrote:
> Hi Michal,
>
> On Mon, Apr 26, 2021 at 8:31 PM Michal Simek
> wrote:
>>
>> The commit 6c993815bbea ("net: phy: xilinx: Be compatible with live OF
>> tree") change driver behavior to while loop which wasn't correct because
>> the driver was looping over again and again. The reason was that
>> ofnode_valid() is taking 0 as correct value.
>
> I am still trying to understand the problem. The changes in
> 6c993815bbea sound correct from an fdtdec <=> OF API mapping
> perspective. If the new OF API does not work, the old fdtdec may fail
> too. Could you please explain a little bit?
here is behavior of origin code.
ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id
phy_connect_gmii2rgmii sn 11348
phy_connect_gmii2rgmii 1off -1
phy_connect_gmii2rgmii 2off -1
phy_connect_gmii2rgmii sn2 11752
phy_connect_gmii2rgmii 1off -1
phy_connect_gmii2rgmii 2off -1
phy_connect_gmii2rgmii sn2 -1
phy_connect_gmii2rgmii phydev
eth0: ethernet@ff0e
Scanning disk m...@ff17.blk...
Found 4 disks
Hit any key to stop autoboot: 0
ZynqMP>
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 89e3076bfd25..d0960d93ae08 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -956,22 +956,28 @@ static struct phy_device
*phy_connect_gmii2rgmii(struct mii_dev *bus,
int sn = dev_of_offset(dev);
int off;
+ printf("%s sn %d\n", __func__, sn);
while (sn > 0) {
off = fdt_node_offset_by_compatible(gd->fdt_blob, sn,
"xlnx,gmii-to-rgmii-1.0");
+ printf("%s 1off %d\n", __func__, off);
if (off > 0) {
phydev = phy_device_create(bus, off,
PHY_GMII2RGMII_ID,
false,
interface);
break;
}
- if (off == -FDT_ERR_NOTFOUND)
+ printf("%s 2off %d\n", __func__, off);
+
+ if (off == -FDT_ERR_NOTFOUND) {
sn = fdt_first_subnode(gd->fdt_blob, sn);
- else
+ printf("%s sn2 %d\n", __func__, sn);
+ } else
printf("%s: Error finding compat string:%d\n",
__func__, off);
}
+ printf("%s phydev %p\n", __func__, phydev);
return phydev;
}
#endif
With latest code and some prints
ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id
ofnode_valid: node.of_offset 11348
ofnode_valid: node.of_offset 11348
ofnode_valid: node.of_offset 11348
ofnode_valid: node.of_offset 2952
ofnode_valid: node.of_offset 11348
ofnode_valid: node.of_offset -1
ofnode_valid: node.of_offset 11348
ofnode_valid: node.of_offset 11348
phy_connect_gmii2rgmii 1valid 1 ethernet@ff0e
ofnode_valid: node.of_offset 11348
ofnode_valid: node.of_offset 11348
ofnode_valid: node.of_offset 11348
phy_connect_gmii2rgmii 2valid 1 ethernet@ff0e
ofnode_valid: node.of_offset -1
ofnode_valid: node.of_offset -1
ofnode_valid: node.of_offset 0
ofnode_valid: node.of_offset 0
phy_connect_gmii2rgmii 3valid 1
ofnode_valid: node.of_offset 0
ofnode_valid: node.of_offset 0
ofnode_valid: node.of_offset 0
phy_connect_gmii2rgmii 2valid 1
ofnode_valid: node.of_offset -1
ofnode_valid: node.of_offset -1
ofnode_valid: node.of_offset 0
ofnode_valid: node.of_offset 0
phy_connect_gmii2rgmii 3valid 1
...
[u-boot](debian-sent)$ git diff
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index dcdef9e661d6..56072ad55216 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -950,7 +950,10 @@ static struct phy_device
*phy_connect_gmii2rgmii(struct mii_dev *bus,
struct phy_device *phydev = NULL;
ofnode node = dev_ofnode(dev);
+ printf("%s 1valid %d %s\n", __func__, ofnode_valid(node),
ofnode_get_name(node));
+
while (ofnode_valid(node)) {
+ printf("%s 2valid %d %s\n", __func__,
ofnode_valid(node), ofnode_get_name(node));
node = ofnode_by_compatible(node,
"xln
Re: [PATCH] net: phy: xilinx: Break while loop over ethernet phy
Hi Michal,
On Wed, Apr 28, 2021 at 11:03 PM Michal Simek wrote:
>
> Hi Bin,
>
> On 4/28/21 4:37 PM, Bin Meng wrote:
> > Hi Michal,
> >
> > On Tue, Apr 27, 2021 at 7:22 PM Michal Simek
> > wrote:
> >>
> >> Hi Bin,
> >>
> >> On 4/27/21 7:17 AM, Bin Meng wrote:
> >>> Hi Michal,
> >>>
> >>> On Mon, Apr 26, 2021 at 8:31 PM Michal Simek
> >>> wrote:
>
> The commit 6c993815bbea ("net: phy: xilinx: Be compatible with live OF
> tree") change driver behavior to while loop which wasn't correct because
> the driver was looping over again and again. The reason was that
> ofnode_valid() is taking 0 as correct value.
> >>>
> >>> I am still trying to understand the problem. The changes in
> >>> 6c993815bbea sound correct from an fdtdec <=> OF API mapping
> >>> perspective. If the new OF API does not work, the old fdtdec may fail
> >>> too. Could you please explain a little bit?
> >>
> >> here is behavior of origin code.
> >>
> >> ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id
> >> phy_connect_gmii2rgmii sn 11348
> >> phy_connect_gmii2rgmii 1off -1
> >> phy_connect_gmii2rgmii 2off -1
> >> phy_connect_gmii2rgmii sn2 11752
> >> phy_connect_gmii2rgmii 1off -1
> >> phy_connect_gmii2rgmii 2off -1
> >> phy_connect_gmii2rgmii sn2 -1
> >> phy_connect_gmii2rgmii phydev
> >> eth0: ethernet@ff0e
> >> Scanning disk m...@ff17.blk...
> >> Found 4 disks
> >> Hit any key to stop autoboot: 0
> >> ZynqMP>
> >>
> >>
> >> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> >> index 89e3076bfd25..d0960d93ae08 100644
> >> --- a/drivers/net/phy/phy.c
> >> +++ b/drivers/net/phy/phy.c
> >> @@ -956,22 +956,28 @@ static struct phy_device
> >> *phy_connect_gmii2rgmii(struct mii_dev *bus,
> >> int sn = dev_of_offset(dev);
> >> int off;
> >>
> >> + printf("%s sn %d\n", __func__, sn);
> >> while (sn > 0) {
> >> off = fdt_node_offset_by_compatible(gd->fdt_blob, sn,
> >>
> >> "xlnx,gmii-to-rgmii-1.0");
> >> + printf("%s 1off %d\n", __func__, off);
> >> if (off > 0) {
> >> phydev = phy_device_create(bus, off,
> >>PHY_GMII2RGMII_ID,
> >> false,
> >>interface);
> >> break;
> >> }
> >> - if (off == -FDT_ERR_NOTFOUND)
> >> + printf("%s 2off %d\n", __func__, off);
> >> +
> >> + if (off == -FDT_ERR_NOTFOUND) {
> >> sn = fdt_first_subnode(gd->fdt_blob, sn);
> >> - else
> >> + printf("%s sn2 %d\n", __func__, sn);
> >> + } else
> >> printf("%s: Error finding compat string:%d\n",
> >>__func__, off);
> >> }
> >>
> >> + printf("%s phydev %p\n", __func__, phydev);
> >> return phydev;
> >> }
> >> #endif
> >>
> >>
> >> With latest code and some prints
> >> ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id
> >> ofnode_valid: node.of_offset 11348
> >> ofnode_valid: node.of_offset 11348
> >> ofnode_valid: node.of_offset 11348
> >> ofnode_valid: node.of_offset 2952
> >> ofnode_valid: node.of_offset 11348
> >> ofnode_valid: node.of_offset -1
> >> ofnode_valid: node.of_offset 11348
> >> ofnode_valid: node.of_offset 11348
> >> phy_connect_gmii2rgmii 1valid 1 ethernet@ff0e
> >> ofnode_valid: node.of_offset 11348
> >> ofnode_valid: node.of_offset 11348
> >> ofnode_valid: node.of_offset 11348
> >> phy_connect_gmii2rgmii 2valid 1 ethernet@ff0e
> >> ofnode_valid: node.of_offset -1
> >> ofnode_valid: node.of_offset -1
> >> ofnode_valid: node.of_offset 0
> >> ofnode_valid: node.of_offset 0
> >> phy_connect_gmii2rgmii 3valid 1
> >> ofnode_valid: node.of_offset 0
> >> ofnode_valid: node.of_offset 0
> >> ofnode_valid: node.of_offset 0
> >> phy_connect_gmii2rgmii 2valid 1
> >> ofnode_valid: node.of_offset -1
> >> ofnode_valid: node.of_offset -1
> >> ofnode_valid: node.of_offset 0
> >> ofnode_valid: node.of_offset 0
> >> phy_connect_gmii2rgmii 3valid 1
> >> ...
> >>
> >>
> >> [u-boot](debian-sent)$ git diff
> >> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> >> index dcdef9e661d6..56072ad55216 100644
> >> --- a/drivers/net/phy/phy.c
> >> +++ b/drivers/net/phy/phy.c
> >> @@ -950,7 +950,10 @@ static struct phy_device
> >> *phy_connect_gmii2rgmii(struct mii_dev *bus,
> >> struct phy_device *phydev = NULL;
> >> ofnode node = dev_ofnode(dev);
> >>
> >> + printf("%s 1valid %d %s\n", __func__, ofnode_valid(node),
> >> ofnode_get_name(node));
> >> +
> >> while (ofnode_valid(node)) {
> >> + printf("%s 2valid %d %s\n", __func__,
> >> ofnode_valid(node), ofnode_get_name(node));
> >> node = ofnode_by_compatible(node,
> >> "xlnx,gmii-to-rgmii-1.0");
> >> if (ofnode_
[PULL u-boot] Please pull u-boot-amlogic-20210428
Hi Tom, A single patch to fix boot on (at least) Odroid-C4, where the MDIO bus reset used random sleep values instead of the proper pdata values. The CI job is at https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic/pipelines/7337 Thanks, Neil The following changes since commit 79b0f08d6af498e6fda8cd257d62e2095764410c: configs: Resync with savedefconfig (2021-04-27 08:28:38 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-amlogic.git tags/u-boot-amlogic-20210428 for you to fetch changes up to 98b8204626ac2837e927e79d3dfe77246e506c02: net: designware: fix PHY reset with DM_MDIO (2021-04-28 17:45:26 +0200) - net: designware: fix PHY reset with DM_MDIO, fixing boot of (at least) Odroid-C4 Neil Armstrong (1): net: designware: fix PHY reset with DM_MDIO drivers/net/designware.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-)
Re: [linux-sunxi] [PATCH] sunxi: clock: H6/H616: Fix PLL6 clock calculation
Hi! Dne sreda, 28. april 2021 ob 12:05:55 CEST je Andre Przywara napisal(a): > The "n" factor of the PLL_PERIPH0 clock is using the usual +1 encoding, > so we need to adjust the register value before doing the calculation. > > This fixes the MMC clock setup on those SoCs, which could be slightly off > due to the wrong parent frequency: > mmc 2 set mod-clk req 5200 parent 117600 n 2 m 12 rate 4900 > > Signed-off-by: Andre Przywara Good catch! Reviewed-by: Jernej Skrabec Best regards, Jernej
Re: [PATCH] usb: ehci-mx6: Limit PHY address parsing to !CONFIG_PHY
On 4/28/21 5:13 PM, Ying-Chun Liu (PaulLiu) wrote:
[...]
-#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(priv->phy_addr, 1);
usb_phy_enable(ehci, priv->phy_addr);
#endif
+#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
Tested-by: Ying-Chun Liu (PaulLiu)
Tested on IMX8M Compulab IoT gate
Nice, thanks.
Re: [PATCH] usb: ehci-mx6: Limit PHY address parsing to !CONFIG_PHY
Marek Vasut 於 2021/4/28 上午12:06 寫道:
> For systems which use generic PHY support and implement USB PHY driver,
> the parsing of PHY properties is unnecessary, disable it.
>
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> Cc: Tim Harvey
> Cc: Ye Li
> Cc: uboot-imx
> ---
> drivers/usb/host/ehci-mx6.c | 17 -
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
> index 7642a31b655..06be9deaaae 100644
> --- a/drivers/usb/host/ehci-mx6.c
> +++ b/drivers/usb/host/ehci-mx6.c
> @@ -265,6 +265,8 @@ int usb_phy_mode(int port)
> }
> #endif
>
> +#if !defined(CONFIG_PHY)
> +/* Should be done in the MXS PHY driver */
> static void usb_oc_config(struct usbnc_regs *usbnc, int index)
> {
> void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
> @@ -285,6 +287,7 @@ static void usb_oc_config(struct usbnc_regs *usbnc,
int index)
> clrbits_le32(ctrl, UCTRL_PWR_POL);
> #endif
> }
> +#endif
>
> #if !CONFIG_IS_ENABLED(DM_USB)
> /**
> @@ -432,10 +435,12 @@ struct ehci_mx6_priv_data {
> struct clk clk;
> struct phy phy;
> enum usb_init_type init_type;
> +#if !defined(CONFIG_PHY)
> int portnr;
> void __iomem *phy_addr;
> void __iomem *misc_addr;
> void __iomem *anatop_addr;
> +#endif
> };
>
> static int mx6_init_after_reset(struct ehci_ctrl *dev)
> @@ -448,14 +453,14 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
> usb_power_config_mx6(priv->anatop_addr, priv->portnr);
> usb_power_config_mx7(priv->misc_addr);
> usb_power_config_mx7ulp(priv->phy_addr);
> -#endif
>
> usb_oc_config(priv->misc_addr, priv->portnr);
>
> -#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
> +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
> usb_internal_phy_clock_gate(priv->phy_addr, 1);
> usb_phy_enable(ehci, priv->phy_addr);
> #endif
> +#endif
>
> #if CONFIG_IS_ENABLED(DM_REGULATOR)
> if (priv->vbus_supply) {
> @@ -558,6 +563,7 @@ static int ehci_usb_of_to_plat(struct udevice *dev)
>
> static int mx6_parse_dt_addrs(struct udevice *dev)
> {
> +#if !defined(CONFIG_PHY)
> struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
> int phy_off, misc_off;
> const void *blob = gd->fdt_blob;
> @@ -594,7 +600,7 @@ static int mx6_parse_dt_addrs(struct udevice *dev)
>
> priv->misc_addr = addr;
>
> -#if !defined(CONFIG_PHY) && defined(CONFIG_MX6)
> +#if defined(CONFIG_MX6)
> int anatop_off;
>
> /* Resolve ANATOP offset through USB PHY node */
> @@ -607,6 +613,7 @@ static int mx6_parse_dt_addrs(struct udevice *dev)
> return -EINVAL;
>
> priv->anatop_addr = addr;
> +#endif
> #endif
> return 0;
> }
> @@ -661,14 +668,14 @@ static int ehci_usb_probe(struct udevice *dev)
> usb_power_config_mx6(priv->anatop_addr, priv->portnr);
> usb_power_config_mx7(priv->misc_addr);
> usb_power_config_mx7ulp(priv->phy_addr);
> -#endif
>
> usb_oc_config(priv->misc_addr, priv->portnr);
>
> -#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
> +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
> usb_internal_phy_clock_gate(priv->phy_addr, 1);
> usb_phy_enable(ehci, priv->phy_addr);
> #endif
> +#endif
>
> #if CONFIG_IS_ENABLED(DM_REGULATOR)
> if (priv->vbus_supply) {
Tested-by: Ying-Chun Liu (PaulLiu)
Tested on IMX8M Compulab IoT gate
OpenPGP_signature
Description: OpenPGP digital signature
Re: [PATCH 6/6] net: octeontx: smi: fix mii probe
On Mon, Apr 26, 2021 at 10:19 PM Stefan Roese wrote:
>
> Hi Tim,
>
> On 26.03.21 16:55, Tim Harvey wrote:
> > On Thu, Mar 25, 2021 at 11:48 PM Stefan Roese wrote:
> >>
> >> On 26.03.21 01:07, Tim Harvey wrote:
> >>> The fdt node offset is apparently not set properly when probed
> >>> causing no MDIO busses to be found. Fix this by obtaining the
> >>> offset.
> >>>
> >>> Signed-off-by: Tim Harvey
> >>
> >> Reviewed-by: Stefan Roese
> >>
> >> Thanks,
> >> Stefan
> >>
> >>> ---
> >>>drivers/net/octeontx/smi.c | 2 ++
> >>>1 file changed, 2 insertions(+)
> >>>
> >>> diff --git a/drivers/net/octeontx/smi.c b/drivers/net/octeontx/smi.c
> >>> index 91dcd05e4b..27f4423c6a 100644
> >>> --- a/drivers/net/octeontx/smi.c
> >>> +++ b/drivers/net/octeontx/smi.c
> >>> @@ -325,6 +325,8 @@ int octeontx_smi_probe(struct udevice *dev)
> >>>return -1;
> >>>}
> >>>
> >>> + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
> >>> +
> >>> "cavium,thunder-8890-mdio-nexus");
> >>>fdt_for_each_subnode(subnode, gd->fdt_blob, node) {
> >>>ret = fdt_node_check_compatible(gd->fdt_blob, subnode,
> >>>
> >>> "cavium,thunder-8890-mdio");
> >>>
> >
> > Honestly this is the wrong fix for this issue and I'm hoping someone
> > could educate me. I'm a bit confused at why there are several ways to
> > work with dt (int offsets vs ofnodes which are unions of int offsets
> > and node pointers???).
> >
> > The above patch was not needed previously so something changed in the
> > ofnode field of struct udevice between v2019.10 and v2021.01.
> >
> > Simon, could you explain what the proper way to work with dev->ofnode
> > in probe functions is to loop over subnodes?
>
> This version is in mainline now. Tim, could you please re-visit this
> and perhaps switch to using live tree API, as suggested by Suneel:
>
> ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
> ret = ofnode_device_is_compatible(subnode,
> "cavium,thunder-8890-mdio");
>
Stefan,
Yes, I can submit this but I would really like to understand the
original issue. Do you or Simon perhaps know why the fdt node offset
in dev passed to probe is wrong? It's not null but it does not appear
to point to a device-tree (or perhaps I was using the wrong functions
on it not fully understanding the current state of this live tree
API).
Best regards,
Tim
Re: [PATCH] net: phy: xilinx: Break while loop over ethernet phy
Hi Bin,
On 4/28/21 4:37 PM, Bin Meng wrote:
> Hi Michal,
>
> On Tue, Apr 27, 2021 at 7:22 PM Michal Simek wrote:
>>
>> Hi Bin,
>>
>> On 4/27/21 7:17 AM, Bin Meng wrote:
>>> Hi Michal,
>>>
>>> On Mon, Apr 26, 2021 at 8:31 PM Michal Simek
>>> wrote:
The commit 6c993815bbea ("net: phy: xilinx: Be compatible with live OF
tree") change driver behavior to while loop which wasn't correct because
the driver was looping over again and again. The reason was that
ofnode_valid() is taking 0 as correct value.
>>>
>>> I am still trying to understand the problem. The changes in
>>> 6c993815bbea sound correct from an fdtdec <=> OF API mapping
>>> perspective. If the new OF API does not work, the old fdtdec may fail
>>> too. Could you please explain a little bit?
>>
>> here is behavior of origin code.
>>
>> ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id
>> phy_connect_gmii2rgmii sn 11348
>> phy_connect_gmii2rgmii 1off -1
>> phy_connect_gmii2rgmii 2off -1
>> phy_connect_gmii2rgmii sn2 11752
>> phy_connect_gmii2rgmii 1off -1
>> phy_connect_gmii2rgmii 2off -1
>> phy_connect_gmii2rgmii sn2 -1
>> phy_connect_gmii2rgmii phydev
>> eth0: ethernet@ff0e
>> Scanning disk m...@ff17.blk...
>> Found 4 disks
>> Hit any key to stop autoboot: 0
>> ZynqMP>
>>
>>
>> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
>> index 89e3076bfd25..d0960d93ae08 100644
>> --- a/drivers/net/phy/phy.c
>> +++ b/drivers/net/phy/phy.c
>> @@ -956,22 +956,28 @@ static struct phy_device
>> *phy_connect_gmii2rgmii(struct mii_dev *bus,
>> int sn = dev_of_offset(dev);
>> int off;
>>
>> + printf("%s sn %d\n", __func__, sn);
>> while (sn > 0) {
>> off = fdt_node_offset_by_compatible(gd->fdt_blob, sn,
>>
>> "xlnx,gmii-to-rgmii-1.0");
>> + printf("%s 1off %d\n", __func__, off);
>> if (off > 0) {
>> phydev = phy_device_create(bus, off,
>>PHY_GMII2RGMII_ID, false,
>>interface);
>> break;
>> }
>> - if (off == -FDT_ERR_NOTFOUND)
>> + printf("%s 2off %d\n", __func__, off);
>> +
>> + if (off == -FDT_ERR_NOTFOUND) {
>> sn = fdt_first_subnode(gd->fdt_blob, sn);
>> - else
>> + printf("%s sn2 %d\n", __func__, sn);
>> + } else
>> printf("%s: Error finding compat string:%d\n",
>>__func__, off);
>> }
>>
>> + printf("%s phydev %p\n", __func__, phydev);
>> return phydev;
>> }
>> #endif
>>
>>
>> With latest code and some prints
>> ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset 2952
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset -1
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset 11348
>> phy_connect_gmii2rgmii 1valid 1 ethernet@ff0e
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset 11348
>> phy_connect_gmii2rgmii 2valid 1 ethernet@ff0e
>> ofnode_valid: node.of_offset -1
>> ofnode_valid: node.of_offset -1
>> ofnode_valid: node.of_offset 0
>> ofnode_valid: node.of_offset 0
>> phy_connect_gmii2rgmii 3valid 1
>> ofnode_valid: node.of_offset 0
>> ofnode_valid: node.of_offset 0
>> ofnode_valid: node.of_offset 0
>> phy_connect_gmii2rgmii 2valid 1
>> ofnode_valid: node.of_offset -1
>> ofnode_valid: node.of_offset -1
>> ofnode_valid: node.of_offset 0
>> ofnode_valid: node.of_offset 0
>> phy_connect_gmii2rgmii 3valid 1
>> ...
>>
>>
>> [u-boot](debian-sent)$ git diff
>> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
>> index dcdef9e661d6..56072ad55216 100644
>> --- a/drivers/net/phy/phy.c
>> +++ b/drivers/net/phy/phy.c
>> @@ -950,7 +950,10 @@ static struct phy_device
>> *phy_connect_gmii2rgmii(struct mii_dev *bus,
>> struct phy_device *phydev = NULL;
>> ofnode node = dev_ofnode(dev);
>>
>> + printf("%s 1valid %d %s\n", __func__, ofnode_valid(node),
>> ofnode_get_name(node));
>> +
>> while (ofnode_valid(node)) {
>> + printf("%s 2valid %d %s\n", __func__,
>> ofnode_valid(node), ofnode_get_name(node));
>> node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0");
>> if (ofnode_valid(node)) {
>> phydev = phy_device_create(bus, 0,
>> @@ -962,6 +965,7 @@ static struct phy_device
>> *phy_connect_gmii2rgmii(struct mii_dev *bus,
>> }
>>
>> node = ofnode_first_subnode(node);
>> + printf("%s 3valid %d %s\n", __func__,
>> ofnode_valid(node), ofnode_get_name(
Re: Kirkwood: Fix tv sec/usec normalization in kwboot
On 28.04.21 13:24, Dagan Martinez wrote:
From a45340719110b8a8b5292f6353fda7509be81417 Mon Sep 17 00:00:00 2001
From: Property404
Date: Tue, 27 Apr 2021 15:48:31 -0400
Subject: [PATCH] Kirkwood: Fix tv sec/usec normalization in kwboot
`kwboot.c` had an issue where it failed to normalize the `tv` struct in
the case where the `tv_usec` field was 100, ie one second.
This caused issues on Fedora Linux 34, where `select` would return
`EINVAL`, preventing kwboot from communicating with the board.
Signed-off-by: Dagan Martinez
Thanks for re-submitting. I do have some more change requests - sorry
for being a bit strict here.
First, please change the subject to not reply on a message but also
mention the patch version in the subject (v2). And also please add
the patch history below the commit text. See here for more details
on submitting patch versions:
http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions
And also please change your "From:" line, so that it does not mention
"Property404" any more.
BTW: "git send-email" is very helpful for sending patches.
Thanks,
Stefan
---
tools/kwboot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/kwboot.c b/tools/kwboot.c
index 4be094c9c8..5d5d501d36 100644
--- a/tools/kwboot.c
+++ b/tools/kwboot.c
@@ -167,7 +167,7 @@ kwboot_tty_recv(int fd, void *buf, size_t len, int timeo)
tv.tv_sec = 0;
tv.tv_usec = timeo * 1000;
-if (tv.tv_usec > 100) {
+if (tv.tv_usec >= 100) {
tv.tv_sec += tv.tv_usec / 100;
tv.tv_usec %= 100;
}
Re: [PATCH] net: phy: xilinx: Break while loop over ethernet phy
Hi Michal,
On Tue, Apr 27, 2021 at 7:22 PM Michal Simek wrote:
>
> Hi Bin,
>
> On 4/27/21 7:17 AM, Bin Meng wrote:
> > Hi Michal,
> >
> > On Mon, Apr 26, 2021 at 8:31 PM Michal Simek
> > wrote:
> >>
> >> The commit 6c993815bbea ("net: phy: xilinx: Be compatible with live OF
> >> tree") change driver behavior to while loop which wasn't correct because
> >> the driver was looping over again and again. The reason was that
> >> ofnode_valid() is taking 0 as correct value.
> >
> > I am still trying to understand the problem. The changes in
> > 6c993815bbea sound correct from an fdtdec <=> OF API mapping
> > perspective. If the new OF API does not work, the old fdtdec may fail
> > too. Could you please explain a little bit?
>
> here is behavior of origin code.
>
> ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id
> phy_connect_gmii2rgmii sn 11348
> phy_connect_gmii2rgmii 1off -1
> phy_connect_gmii2rgmii 2off -1
> phy_connect_gmii2rgmii sn2 11752
> phy_connect_gmii2rgmii 1off -1
> phy_connect_gmii2rgmii 2off -1
> phy_connect_gmii2rgmii sn2 -1
> phy_connect_gmii2rgmii phydev
> eth0: ethernet@ff0e
> Scanning disk m...@ff17.blk...
> Found 4 disks
> Hit any key to stop autoboot: 0
> ZynqMP>
>
>
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index 89e3076bfd25..d0960d93ae08 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -956,22 +956,28 @@ static struct phy_device
> *phy_connect_gmii2rgmii(struct mii_dev *bus,
> int sn = dev_of_offset(dev);
> int off;
>
> + printf("%s sn %d\n", __func__, sn);
> while (sn > 0) {
> off = fdt_node_offset_by_compatible(gd->fdt_blob, sn,
>
> "xlnx,gmii-to-rgmii-1.0");
> + printf("%s 1off %d\n", __func__, off);
> if (off > 0) {
> phydev = phy_device_create(bus, off,
>PHY_GMII2RGMII_ID, false,
>interface);
> break;
> }
> - if (off == -FDT_ERR_NOTFOUND)
> + printf("%s 2off %d\n", __func__, off);
> +
> + if (off == -FDT_ERR_NOTFOUND) {
> sn = fdt_first_subnode(gd->fdt_blob, sn);
> - else
> + printf("%s sn2 %d\n", __func__, sn);
> + } else
> printf("%s: Error finding compat string:%d\n",
>__func__, off);
> }
>
> + printf("%s phydev %p\n", __func__, phydev);
> return phydev;
> }
> #endif
>
>
> With latest code and some prints
> ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset 2952
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset -1
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset 11348
> phy_connect_gmii2rgmii 1valid 1 ethernet@ff0e
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset 11348
> ofnode_valid: node.of_offset 11348
> phy_connect_gmii2rgmii 2valid 1 ethernet@ff0e
> ofnode_valid: node.of_offset -1
> ofnode_valid: node.of_offset -1
> ofnode_valid: node.of_offset 0
> ofnode_valid: node.of_offset 0
> phy_connect_gmii2rgmii 3valid 1
> ofnode_valid: node.of_offset 0
> ofnode_valid: node.of_offset 0
> ofnode_valid: node.of_offset 0
> phy_connect_gmii2rgmii 2valid 1
> ofnode_valid: node.of_offset -1
> ofnode_valid: node.of_offset -1
> ofnode_valid: node.of_offset 0
> ofnode_valid: node.of_offset 0
> phy_connect_gmii2rgmii 3valid 1
> ...
>
>
> [u-boot](debian-sent)$ git diff
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index dcdef9e661d6..56072ad55216 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -950,7 +950,10 @@ static struct phy_device
> *phy_connect_gmii2rgmii(struct mii_dev *bus,
> struct phy_device *phydev = NULL;
> ofnode node = dev_ofnode(dev);
>
> + printf("%s 1valid %d %s\n", __func__, ofnode_valid(node),
> ofnode_get_name(node));
> +
> while (ofnode_valid(node)) {
> + printf("%s 2valid %d %s\n", __func__,
> ofnode_valid(node), ofnode_get_name(node));
> node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0");
> if (ofnode_valid(node)) {
> phydev = phy_device_create(bus, 0,
> @@ -962,6 +965,7 @@ static struct phy_device
> *phy_connect_gmii2rgmii(struct mii_dev *bus,
> }
>
> node = ofnode_first_subnode(node);
> + printf("%s 3valid %d %s\n", __func__,
> ofnode_valid(node), ofnode_get_name(node));
> }
>
> return phydev;
>
>
> diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
> index 2c0597c40739..7bfc06165e92 100644
> --- a/include/dm/of
Re: [PATCH V2] efi_loader: loosen buffer parameter check in efi_file_read_int
On 28.04.21 15:54, Peng Fan (OSS) wrote:
> From: Peng Fan
>
> This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
> but that fix was wrongly partial reverted.
>
> When reading a directory, EFI_BUFFER_TOO_SMALL should be returned when
> the supplied buffer is too small, so a use-case is to call
> EFI_FILE_PROTOCOL.Read() with *buffer_size=0 and buffer=NULL to
> obtain the needed size before doing the actual read.
>
> So remove the check only for directory reading, file reading already
> do the check by itself.
>
> Fixes: db12f518edb0("efi_loader: implement non-blocking file services")
> Cc: Heinrich Schuchardt
> Cc: Stefan Sørensen
> Tested-by: Peter Robinson
> Signed-off-by: Peng Fan
Reviewed-by: Heinrich Schuchardt
> ---
>
> V2:
> Update commit log Per Heinrich's comments.
> Add T-b tag
>
> lib/efi_loader/efi_file.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
> index 204105e25a..6b3f5962be 100644
> --- a/lib/efi_loader/efi_file.c
> +++ b/lib/efi_loader/efi_file.c
> @@ -554,7 +554,7 @@ static efi_status_t efi_file_read_int(struct
> efi_file_handle *this,
> efi_status_t ret = EFI_SUCCESS;
> u64 bs;
>
> - if (!this || !buffer_size || !buffer)
> + if (!this || !buffer_size)
> return EFI_INVALID_PARAMETER;
>
> bs = *buffer_size;
>
[PATCH V2] efi_loader: loosen buffer parameter check in efi_file_read_int
From: Peng Fan
This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
but that fix was wrongly partial reverted.
When reading a directory, EFI_BUFFER_TOO_SMALL should be returned when
the supplied buffer is too small, so a use-case is to call
EFI_FILE_PROTOCOL.Read() with *buffer_size=0 and buffer=NULL to
obtain the needed size before doing the actual read.
So remove the check only for directory reading, file reading already
do the check by itself.
Fixes: db12f518edb0("efi_loader: implement non-blocking file services")
Cc: Heinrich Schuchardt
Cc: Stefan Sørensen
Tested-by: Peter Robinson
Signed-off-by: Peng Fan
---
V2:
Update commit log Per Heinrich's comments.
Add T-b tag
lib/efi_loader/efi_file.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
index 204105e25a..6b3f5962be 100644
--- a/lib/efi_loader/efi_file.c
+++ b/lib/efi_loader/efi_file.c
@@ -554,7 +554,7 @@ static efi_status_t efi_file_read_int(struct
efi_file_handle *this,
efi_status_t ret = EFI_SUCCESS;
u64 bs;
- if (!this || !buffer_size || !buffer)
+ if (!this || !buffer_size)
return EFI_INVALID_PARAMETER;
bs = *buffer_size;
--
2.30.0
Re: [PATCH v3 1/2] efi_loader: expose efi_image_parse() even if UEFI Secure Boot is disabled
On 28.04.21 14:19, Masahisa Kojima wrote:
> This is preparation for PE/COFF measurement support.
> PE/COFF image hash calculation is same in both
> UEFI Secure Boot image verification and measurement in
> measured boot. PE/COFF image parsing functions are
> gathered into efi_image_loader.c, and exposed even if
> UEFI Secure Boot is not enabled.
>
> This commit also adds the EFI_SIGNATURE_SUPPORT option
> to decide if efi_signature.c shall be compiled.
>
> Signed-off-by: Masahisa Kojima
> ---
>
> Changes in v3:
> - hide EFI_SIGNATURE_SUPPORT option
>
> Changes in v2:
> - Remove all #ifdef from efi_image_loader.c and efi_signature.c
> - Add EFI_SIGNATURE_SUPPORT option
> - Explicitly include
> - Gather PE/COFF parsing functions into efi_image_loader.c
> - Move efi_guid_t efi_guid_image_security_database in efi_var_common.c
>
>
> lib/efi_loader/Kconfig| 6 +++
> lib/efi_loader/Makefile | 2 +-
> lib/efi_loader/efi_image_loader.c | 73 +++
> lib/efi_loader/efi_signature.c| 67 +---
> lib/efi_loader/efi_var_common.c | 3 ++
> 5 files changed, 76 insertions(+), 75 deletions(-)
>
> diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
> index 0b99d7c774..b76e77180e 100644
> --- a/lib/efi_loader/Kconfig
> +++ b/lib/efi_loader/Kconfig
> @@ -174,6 +174,7 @@ config EFI_CAPSULE_AUTHENTICATE
> select PKCS7_MESSAGE_PARSER
> select PKCS7_VERIFY
> select IMAGE_SIGN_INFO
> + select EFI_SIGNATURE_SUPPORT
> default n
> help
> Select this option if you want to enable capsule
> @@ -336,6 +337,7 @@ config EFI_SECURE_BOOT
> select X509_CERTIFICATE_PARSER
> select PKCS7_MESSAGE_PARSER
> select PKCS7_VERIFY
> + select EFI_SIGNATURE_SUPPORT
> default n
> help
> Select this option to enable EFI secure boot support.
> @@ -343,6 +345,10 @@ config EFI_SECURE_BOOT
> it is signed with a trusted key. To do that, you need to install,
> at least, PK, KEK and db.
>
> +config EFI_SIGNATURE_SUPPORT
> + bool
> + depends on EFI_SECURE_BOOT || EFI_CAPSULE_AUTHENTICATE
> +
> config EFI_ESRT
> bool "Enable the UEFI ESRT generation"
> depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT
> diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
> index 8bd343e258..fd344cea29 100644
> --- a/lib/efi_loader/Makefile
> +++ b/lib/efi_loader/Makefile
> @@ -63,7 +63,7 @@ obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += efi_smbios.o
> obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_rng.o
> obj-$(CONFIG_EFI_TCG2_PROTOCOL) += efi_tcg2.o
> obj-$(CONFIG_EFI_LOAD_FILE2_INITRD) += efi_load_initrd.o
> -obj-y += efi_signature.o
> +obj-$(CONFIG_EFI_SIGNATURE_SUPPORT) += efi_signature.o
>
> EFI_VAR_SEED_FILE := $(subst $\",,$(CONFIG_EFI_VAR_SEED_FILE))
> $(obj)/efi_var_seed.o: $(srctree)/$(EFI_VAR_SEED_FILE)
> diff --git a/lib/efi_loader/efi_image_loader.c
> b/lib/efi_loader/efi_image_loader.c
> index f53ef367ec..b8a790bcb9 100644
> --- a/lib/efi_loader/efi_image_loader.c
> +++ b/lib/efi_loader/efi_image_loader.c
> @@ -213,7 +213,68 @@ static void efi_set_code_and_data_type(
> }
> }
>
> -#ifdef CONFIG_EFI_SECURE_BOOT
> +/**
> + * efi_image_region_add() - add an entry of region
> + * @regs:Pointer to array of regions
> + * @start: Start address of region (included)
> + * @end: End address of region (excluded)
> + * @nocheck: flag against overlapped regions
> + *
> + * Take one entry of region [@start, @end[ and insert it into the list.
> + *
> + * * If @nocheck is false, the list will be sorted ascending by address.
> + * Overlapping entries will not be allowed.
> + *
> + * * If @nocheck is true, the list will be sorted ascending by sequence
> + * of adding the entries. Overlapping is allowed.
> + *
> + * Return: status code
> + */
> +efi_status_t efi_image_region_add(struct efi_image_regions *regs,
> + const void *start, const void *end,
> + int nocheck)
> +{
> + struct image_region *reg;
> + int i, j;
> +
> + if (regs->num >= regs->max) {
> + EFI_PRINT("%s: no more room for regions\n", __func__);
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + if (end < start)
> + return EFI_INVALID_PARAMETER;
> +
> + for (i = 0; i < regs->num; i++) {
> + reg = ®s->reg[i];
> + if (nocheck)
> + continue;
> +
> + /* new data after registered region */
> + if (start >= reg->data + reg->size)
> + continue;
> +
> + /* new data preceding registered region */
> + if (end <= reg->data) {
> + for (j = regs->num - 1; j >= i; j--)
> + memcpy(®s->reg[j + 1], ®s->reg[j],
> +sizeof(*reg));
> + break;
> + }
> +
> + /* new data ove
Re: [PATCH] efi_loader: loosen buffer parameter check in efi_file_read_int
On 28.04.21 14:49, Heinrich Schuchardt wrote:
> On 28.04.21 10:15, Peng Fan (OSS) wrote:
>> From: Peng Fan
>>
>> This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
>> but that fix was wrongly partial reverted.
>>
>> To Fedora shim loader, when buffer is NULL, a use-case is to call
>> efi_file_read with *buffer_size=0 and buffer=NULL to obtain the needed
An EFI binary cannot directly call efi_file_read(). It calls
EFI_FILE_PROTOCOL.Read().
>> size before doing the actual read.
>>
>> Otherwise, we always met "Could not read \EFI\: Invalid Parameter"
Please, describe the problem in UEFI terms.
>
> The EFI specification does not require this behavior. EDK II does not
> implement it either. See for instance SemihostFileRead(),
> FvSimpleFileSystemRead().
>
> To determine the file size you have to use GetInfo(). Please, fix the
> client code.
>
> Best regards
>
> Heinrich
Please, make it clear in the commit message, please, that this patch is
about reading a *directory entry* and not about reading a file.
Best regards
Heinrich
>
>>
>> Fixes: db12f518edb0("efi_loader: implement non-blocking file services")
>> Signed-off-by: Peng Fan
>> Cc: Heinrich Schuchardt
>> Cc: Stefan Sørensen
>> ---
>> lib/efi_loader/efi_file.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
>> index 204105e25a..6b3f5962be 100644
>> --- a/lib/efi_loader/efi_file.c
>> +++ b/lib/efi_loader/efi_file.c
>> @@ -554,7 +554,7 @@ static efi_status_t efi_file_read_int(struct
>> efi_file_handle *this,
>> efi_status_t ret = EFI_SUCCESS;
>> u64 bs;
>>
>> -if (!this || !buffer_size || !buffer)
>> +if (!this || !buffer_size)
>> return EFI_INVALID_PARAMETER;
>>
>> bs = *buffer_size;
>>
>
Re: [PATCH] efi_loader: loosen buffer parameter check in efi_file_read_int
On 28.04.21 10:15, Peng Fan (OSS) wrote:
> From: Peng Fan
>
> This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
> but that fix was wrongly partial reverted.
>
> To Fedora shim loader, when buffer is NULL, a use-case is to call
> efi_file_read with *buffer_size=0 and buffer=NULL to obtain the needed
> size before doing the actual read.
>
> Otherwise, we always met "Could not read \EFI\: Invalid Parameter"
The EFI specification does not require this behavior. EDK II does not
implement it either. See for instance SemihostFileRead(),
FvSimpleFileSystemRead().
To determine the file size you have to use GetInfo(). Please, fix the
client code.
Best regards
Heinrich
>
> Fixes: db12f518edb0("efi_loader: implement non-blocking file services")
> Signed-off-by: Peng Fan
> Cc: Heinrich Schuchardt
> Cc: Stefan Sørensen
> ---
> lib/efi_loader/efi_file.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
> index 204105e25a..6b3f5962be 100644
> --- a/lib/efi_loader/efi_file.c
> +++ b/lib/efi_loader/efi_file.c
> @@ -554,7 +554,7 @@ static efi_status_t efi_file_read_int(struct
> efi_file_handle *this,
> efi_status_t ret = EFI_SUCCESS;
> u64 bs;
>
> - if (!this || !buffer_size || !buffer)
> + if (!this || !buffer_size)
> return EFI_INVALID_PARAMETER;
>
> bs = *buffer_size;
>
Re: [PATCH] efi_loader: loosen buffer parameter check in efi_file_read_int
On Wed, Apr 28, 2021 at 8:43 AM Peng Fan (OSS) wrote:
>
> From: Peng Fan
>
> This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
> but that fix was wrongly partial reverted.
>
> To Fedora shim loader, when buffer is NULL, a use-case is to call
> efi_file_read with *buffer_size=0 and buffer=NULL to obtain the needed
> size before doing the actual read.
>
> Otherwise, we always met "Could not read \EFI\: Invalid Parameter"
>
> Fixes: db12f518edb0("efi_loader: implement non-blocking file services")
> Signed-off-by: Peng Fan
> Cc: Heinrich Schuchardt
> Cc: Stefan Sørensen
Tested-by: Peter Robinson
Tested on a patched 2021.04 with Fedora 34. Thanks!
> ---
> lib/efi_loader/efi_file.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
> index 204105e25a..6b3f5962be 100644
> --- a/lib/efi_loader/efi_file.c
> +++ b/lib/efi_loader/efi_file.c
> @@ -554,7 +554,7 @@ static efi_status_t efi_file_read_int(struct
> efi_file_handle *this,
> efi_status_t ret = EFI_SUCCESS;
> u64 bs;
>
> - if (!this || !buffer_size || !buffer)
> + if (!this || !buffer_size)
> return EFI_INVALID_PARAMETER;
>
> bs = *buffer_size;
> --
> 2.30.0
>
[PATCH v3 2/2] efi_loader: add PE/COFF image measurement
"TCG PC Client Platform Firmware Profile Specification"
requires to measure every attempt to load and execute
a OS Loader(a UEFI application) into PCR[4].
This commit adds the PE/COFF image measurement, extends PCR,
and appends measurement into Event Log.
Signed-off-by: Masahisa Kojima
---
(no changes since v2)
Changes in v2:
- Remove duplicate include
- Remove unnecessary __packed attribute
- Add all EV_EFI_* event definition
- Create common function to prepare 8-byte aligned image
- Add measurement for EV_EFI_BOOT_SERVICES_DRIVER and
EV_EFI_RUNTIME_SERVICES_DRIVER
- Use efi_search_protocol() to get device_path
- Add function comment
include/efi_loader.h | 6 +
include/efi_tcg2.h| 9 ++
include/tpm-v2.h | 18 +++
lib/efi_loader/efi_image_loader.c | 59 +++--
lib/efi_loader/efi_tcg2.c | 207 --
5 files changed, 275 insertions(+), 24 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index de1a496a97..9f2854a255 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -426,6 +426,10 @@ efi_status_t efi_disk_register(void);
efi_status_t efi_rng_register(void);
/* Called by efi_init_obj_list() to install EFI_TCG2_PROTOCOL */
efi_status_t efi_tcg2_register(void);
+/* measure the pe-coff image, extend PCR and add Event Log */
+efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size,
+ struct efi_loaded_image_obj *handle,
+ struct efi_loaded_image *loaded_image_info);
/* Create handles and protocols for the partitions of a block device */
int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc,
const char *if_typename, int diskid,
@@ -847,6 +851,8 @@ bool efi_secure_boot_enabled(void);
bool efi_capsule_auth_enabled(void);
+void *efi_prepare_aligned_image(void *efi, u64 *efi_size, void **new_efi);
+
bool efi_image_parse(void *efi, size_t len, struct efi_image_regions **regp,
WIN_CERTIFICATE **auth, size_t *auth_len);
diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h
index 40e241ce31..bcfb98168a 100644
--- a/include/efi_tcg2.h
+++ b/include/efi_tcg2.h
@@ -9,6 +9,7 @@
#if !defined _EFI_TCG2_PROTOCOL_H_
#define _EFI_TCG2_PROTOCOL_H_
+#include
#include
#define EFI_TCG2_PROTOCOL_GUID \
@@ -53,6 +54,14 @@ struct efi_tcg2_event {
u8 event[];
} __packed;
+struct uefi_image_load_event {
+ efi_physical_addr_t image_location_in_memory;
+ u64 image_length_in_memory;
+ u64 image_link_time_address;
+ u64 length_of_device_path;
+ struct efi_device_path device_path[];
+};
+
struct efi_tcg2_boot_service_capability {
u8 size;
struct efi_tcg2_version structure_version;
diff --git a/include/tpm-v2.h b/include/tpm-v2.h
index df67a196cf..6e812c017c 100644
--- a/include/tpm-v2.h
+++ b/include/tpm-v2.h
@@ -62,6 +62,24 @@ struct udevice;
#define EV_CPU_MICROCODE ((u32)0x0009)
#define EV_TABLE_OF_DEVICES((u32)0x000B)
+/*
+ * event types, cf.
+ * "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
+ * rev 1.04, June 3, 2019
+ */
+#define EV_EFI_EVENT_BASE ((u32)0x8000)
+#define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x8001)
+#define EV_EFI_VARIABLE_BOOT ((u32)0x8002)
+#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x8003)
+#define EV_EFI_BOOT_SERVICES_DRIVER((u32)0x8004)
+#define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x8005)
+#define EV_EFI_GPT_EVENT ((u32)0x8006)
+#define EV_EFI_ACTION ((u32)0x8007)
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x8008)
+#define EV_EFI_HANDOFF_TABLES ((u32)0x8009)
+#define EV_EFI_HCRTM_EVENT ((u32)0x8010)
+#define EV_EFI_VARIABLE_AUTHORITY ((u32)0x80E0)
+
/* TPMS_TAGGED_PROPERTY Structure */
struct tpms_tagged_property {
u32 property;
diff --git a/lib/efi_loader/efi_image_loader.c
b/lib/efi_loader/efi_image_loader.c
index b8a790bcb9..cc548e1b88 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -302,6 +302,40 @@ static int cmp_pe_section(const void *arg1, const void
*arg2)
return 1;
}
+/**
+ * efi_prepare_aligned_image() - prepare 8-byte aligned image
+ * @efi: pointer to the EFI binary
+ * @efi_size: size of @efi binary
+ * @new_efi: pointer to the newly allocated image
+ *
+ * If @efi is not 8-byte aligned, this function newly allocates
+ * the image buffer and updates @efi_size.
+ *
+ * Return: valid pointer to a image, return NULL if allocation fails.
+ */
+void *efi_prepare_aligned_image(void *efi, u64 *efi_size, void **new_efi)
+{
+ size_t new_efi_size;
+ void *p;
+
+ /*
+
[PATCH v3 0/2] PE/COFF measurement support
This patch series add the PE/COFF measurement support. Extending PCR and Event Log is tested with fTPM running as a OP-TEE TA. Unit test will be added in the separate series. Masahisa Kojima (2): efi_loader: expose efi_image_parse() even if UEFI Secure Boot is disabled efi_loader: add PE/COFF image measurement include/efi_loader.h | 6 + include/efi_tcg2.h| 9 ++ include/tpm-v2.h | 18 +++ lib/efi_loader/Kconfig| 6 + lib/efi_loader/Makefile | 2 +- lib/efi_loader/efi_image_loader.c | 132 +++ lib/efi_loader/efi_signature.c| 67 +- lib/efi_loader/efi_tcg2.c | 207 -- lib/efi_loader/efi_var_common.c | 3 + 9 files changed, 351 insertions(+), 99 deletions(-) -- 2.17.1
[PATCH v3 1/2] efi_loader: expose efi_image_parse() even if UEFI Secure Boot is disabled
This is preparation for PE/COFF measurement support.
PE/COFF image hash calculation is same in both
UEFI Secure Boot image verification and measurement in
measured boot. PE/COFF image parsing functions are
gathered into efi_image_loader.c, and exposed even if
UEFI Secure Boot is not enabled.
This commit also adds the EFI_SIGNATURE_SUPPORT option
to decide if efi_signature.c shall be compiled.
Signed-off-by: Masahisa Kojima
---
Changes in v3:
- hide EFI_SIGNATURE_SUPPORT option
Changes in v2:
- Remove all #ifdef from efi_image_loader.c and efi_signature.c
- Add EFI_SIGNATURE_SUPPORT option
- Explicitly include
- Gather PE/COFF parsing functions into efi_image_loader.c
- Move efi_guid_t efi_guid_image_security_database in efi_var_common.c
lib/efi_loader/Kconfig| 6 +++
lib/efi_loader/Makefile | 2 +-
lib/efi_loader/efi_image_loader.c | 73 +++
lib/efi_loader/efi_signature.c| 67 +---
lib/efi_loader/efi_var_common.c | 3 ++
5 files changed, 76 insertions(+), 75 deletions(-)
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 0b99d7c774..b76e77180e 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -174,6 +174,7 @@ config EFI_CAPSULE_AUTHENTICATE
select PKCS7_MESSAGE_PARSER
select PKCS7_VERIFY
select IMAGE_SIGN_INFO
+ select EFI_SIGNATURE_SUPPORT
default n
help
Select this option if you want to enable capsule
@@ -336,6 +337,7 @@ config EFI_SECURE_BOOT
select X509_CERTIFICATE_PARSER
select PKCS7_MESSAGE_PARSER
select PKCS7_VERIFY
+ select EFI_SIGNATURE_SUPPORT
default n
help
Select this option to enable EFI secure boot support.
@@ -343,6 +345,10 @@ config EFI_SECURE_BOOT
it is signed with a trusted key. To do that, you need to install,
at least, PK, KEK and db.
+config EFI_SIGNATURE_SUPPORT
+ bool
+ depends on EFI_SECURE_BOOT || EFI_CAPSULE_AUTHENTICATE
+
config EFI_ESRT
bool "Enable the UEFI ESRT generation"
depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 8bd343e258..fd344cea29 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -63,7 +63,7 @@ obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += efi_smbios.o
obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_rng.o
obj-$(CONFIG_EFI_TCG2_PROTOCOL) += efi_tcg2.o
obj-$(CONFIG_EFI_LOAD_FILE2_INITRD) += efi_load_initrd.o
-obj-y += efi_signature.o
+obj-$(CONFIG_EFI_SIGNATURE_SUPPORT) += efi_signature.o
EFI_VAR_SEED_FILE := $(subst $\",,$(CONFIG_EFI_VAR_SEED_FILE))
$(obj)/efi_var_seed.o: $(srctree)/$(EFI_VAR_SEED_FILE)
diff --git a/lib/efi_loader/efi_image_loader.c
b/lib/efi_loader/efi_image_loader.c
index f53ef367ec..b8a790bcb9 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -213,7 +213,68 @@ static void efi_set_code_and_data_type(
}
}
-#ifdef CONFIG_EFI_SECURE_BOOT
+/**
+ * efi_image_region_add() - add an entry of region
+ * @regs: Pointer to array of regions
+ * @start: Start address of region (included)
+ * @end: End address of region (excluded)
+ * @nocheck: flag against overlapped regions
+ *
+ * Take one entry of region [@start, @end[ and insert it into the list.
+ *
+ * * If @nocheck is false, the list will be sorted ascending by address.
+ * Overlapping entries will not be allowed.
+ *
+ * * If @nocheck is true, the list will be sorted ascending by sequence
+ * of adding the entries. Overlapping is allowed.
+ *
+ * Return: status code
+ */
+efi_status_t efi_image_region_add(struct efi_image_regions *regs,
+ const void *start, const void *end,
+ int nocheck)
+{
+ struct image_region *reg;
+ int i, j;
+
+ if (regs->num >= regs->max) {
+ EFI_PRINT("%s: no more room for regions\n", __func__);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ if (end < start)
+ return EFI_INVALID_PARAMETER;
+
+ for (i = 0; i < regs->num; i++) {
+ reg = ®s->reg[i];
+ if (nocheck)
+ continue;
+
+ /* new data after registered region */
+ if (start >= reg->data + reg->size)
+ continue;
+
+ /* new data preceding registered region */
+ if (end <= reg->data) {
+ for (j = regs->num - 1; j >= i; j--)
+ memcpy(®s->reg[j + 1], ®s->reg[j],
+ sizeof(*reg));
+ break;
+ }
+
+ /* new data overlapping registered region */
+ EFI_PRINT("%s: new region already part of another\n", __func__);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ reg = ®s->reg[i];
+
Re: Kirkwood: Fix tv sec/usec normalization in kwboot
>From a45340719110b8a8b5292f6353fda7509be81417 Mon Sep 17 00:00:00 2001
From: Property404
Date: Tue, 27 Apr 2021 15:48:31 -0400
Subject: [PATCH] Kirkwood: Fix tv sec/usec normalization in kwboot
`kwboot.c` had an issue where it failed to normalize the `tv` struct in
the case where the `tv_usec` field was 100, ie one second.
This caused issues on Fedora Linux 34, where `select` would return
`EINVAL`, preventing kwboot from communicating with the board.
Signed-off-by: Dagan Martinez
---
tools/kwboot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/kwboot.c b/tools/kwboot.c
index 4be094c9c8..5d5d501d36 100644
--- a/tools/kwboot.c
+++ b/tools/kwboot.c
@@ -167,7 +167,7 @@ kwboot_tty_recv(int fd, void *buf, size_t len, int timeo)
tv.tv_sec = 0;
tv.tv_usec = timeo * 1000;
-if (tv.tv_usec > 100) {
+if (tv.tv_usec >= 100) {
tv.tv_sec += tv.tv_usec / 100;
tv.tv_usec %= 100;
}
--
2.31.1
[PATCH] reset: stm32: Fix bank and offset computation
BITS_PER_LONG is used to represent register's size which is 32.
But when compiled on arch64, BITS_PER_LONG is then equal to 64.
Fix bank and offset computation to make it work on arch32 and
arch64 and ensure that register's size is always equal to 32.
Signed-off-by: Patrice Chotard
Signed-off-by: Pankaj Dev
---
drivers/reset/stm32-reset.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c
index daa2e47ebb..bbc6b135a9 100644
--- a/drivers/reset/stm32-reset.c
+++ b/drivers/reset/stm32-reset.c
@@ -40,8 +40,8 @@ static int stm32_reset_free(struct reset_ctl *reset_ctl)
static int stm32_reset_assert(struct reset_ctl *reset_ctl)
{
struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
- int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
- int offset = reset_ctl->id % BITS_PER_LONG;
+ int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
+ int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
reset_ctl->id, bank, offset);
@@ -61,8 +61,8 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl)
static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
{
struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
- int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
- int offset = reset_ctl->id % BITS_PER_LONG;
+ int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
+ int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
reset_ctl->id, bank, offset);
--
2.17.1
[PATCH v2] dm: core: Add address translation in fdt_get_resource
Today of_address_to_resource() is called only in
ofnode_read_resource() for livetree support and
fdt_get_resource() is called when livetree is not supported.
The fdt_get_resource() doesn't do the address translation
so when it is required, but the address translation is done
by ofnode_read_resource() caller, for example in
drivers/firmware/scmi/smt.c::scmi_dt_get_smt_buffer() {
...
ret = ofnode_read_resource(args.node, 0, &resource);
if (ret)
return ret;
faddr = cpu_to_fdt32(resource.start);
paddr = ofnode_translate_address(args.node, &faddr);
...
The both behavior should be aligned and the address translation
must be called in fdt_get_resource() and removed for each caller.
Fixes: a44810123f9e ("dm: core: Add dev_read_resource() to read device
resources")
Signed-off-by: Patrick Delaunay
---
This patch allows to remove the workaround in smci/smt.c
introduced by [1].
But it impact with all user of
- ofnode_read_resource
- ofnode_read_resource_byname
- dev_read_resource
- dev_read_resource_byname
After my first check, the only impacts are in drivers/net/mscc_eswitch
=> I remove the unnecessary translate after code review,
this patch need to be verify on real hardware
I proposed to merge the workaround [1] as soon as possible to avoid issue
on stm32mp1 platform and this patch can be merged when it will be acked
by mscc_eswitch maintainers and other API users.
[1] "scmi: translate the resource only when livetree is not activated"
http://patchwork.ozlabs.org/project/uboot/list/?series=236526&state=*
Changes in v2:
- remove translate in luton_switch.c:luton_probe()
drivers/firmware/scmi/smt.c | 12 +---
drivers/net/mscc_eswitch/jr2_switch.c | 4 +---
drivers/net/mscc_eswitch/luton_switch.c | 5 +
drivers/net/mscc_eswitch/ocelot_switch.c | 4 +---
drivers/net/mscc_eswitch/serval_switch.c | 4 +---
drivers/net/mscc_eswitch/servalt_switch.c | 4 +---
lib/fdtdec.c | 6 +-
7 files changed, 11 insertions(+), 28 deletions(-)
diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c
index f1915c0074..e60c2aebc8 100644
--- a/drivers/firmware/scmi/smt.c
+++ b/drivers/firmware/scmi/smt.c
@@ -30,8 +30,6 @@ int scmi_dt_get_smt_buffer(struct udevice *dev, struct
scmi_smt *smt)
int ret;
struct ofnode_phandle_args args;
struct resource resource;
- fdt32_t faddr;
- phys_addr_t paddr;
ret = dev_read_phandle_with_args(dev, "shmem", NULL, 0, 0, &args);
if (ret)
@@ -41,21 +39,13 @@ int scmi_dt_get_smt_buffer(struct udevice *dev, struct
scmi_smt *smt)
if (ret)
return ret;
- /* TEMP workaround for ofnode_read_resource translation issue */
- if (of_live_active()) {
- paddr = resource.start;
- } else {
- faddr = cpu_to_fdt32(resource.start);
- paddr = ofnode_translate_address(args.node, &faddr);
- }
-
smt->size = resource_size(&resource);
if (smt->size < sizeof(struct scmi_smt_header)) {
dev_err(dev, "Shared memory buffer too small\n");
return -EINVAL;
}
- smt->buf = devm_ioremap(dev, paddr, smt->size);
+ smt->buf = devm_ioremap(dev, resource.start, smt->size);
if (!smt->buf)
return -ENOMEM;
diff --git a/drivers/net/mscc_eswitch/jr2_switch.c
b/drivers/net/mscc_eswitch/jr2_switch.c
index 570d5a5109..d1e5b61ea5 100644
--- a/drivers/net/mscc_eswitch/jr2_switch.c
+++ b/drivers/net/mscc_eswitch/jr2_switch.c
@@ -863,7 +863,6 @@ static int jr2_probe(struct udevice *dev)
int i;
int ret;
struct resource res;
- fdt32_t faddr;
phys_addr_t addr_base;
unsigned long addr_size;
ofnode eth_node, node, mdio_node;
@@ -926,9 +925,8 @@ static int jr2_probe(struct udevice *dev)
if (ofnode_read_resource(mdio_node, 0, &res))
return -ENOMEM;
- faddr = cpu_to_fdt32(res.start);
- addr_base = ofnode_translate_address(mdio_node, &faddr);
+ addr_base = res.start;
addr_size = res.end - res.start;
/* If the bus is new then create a new bus */
diff --git a/drivers/net/mscc_eswitch/luton_switch.c
b/drivers/net/mscc_eswitch/luton_switch.c
index 54afa14c9d..73c950d118 100644
--- a/drivers/net/mscc_eswitch/luton_switch.c
+++ b/drivers/net/mscc_eswitch/luton_switch.c
@@ -588,7 +588,6 @@ static int luton_probe(struct udevice *dev)
struct luton_private *priv = dev_get_priv(dev);
int i, ret;
struct resource res;
- fdt32_t faddr;
phys_addr_t addr_base;
unsigned long addr_size;
ofnode eth_node, node, mdio_node;
@@ -658,9 +657,7 @@ static int luton_probe(struct udevice *dev)
if (ofnode_read_resource(mdio_node, 0, &res))
[PATCH v3 0/7] arm: cache: cp15: don't map reserved region with no-map property
Hi,
It it the v3 serie of [1].
This v3 serie is rebased on top of v2021.07-rc1 with integrated previous series:
- [2] for stm32mp parts and added dram_bank_mmu_setup
- [3] for LMB impacts
On STM32MP15x platform we can use OP-TEE, loaded in DDR in a region
protected by a firewall. This region is reserved in device with "no-map"
property.
Sometime the platform boot failed in U-Boot on a Cortex A7 access to
this region (depending of the binary and the issue can change with compiler
version or with code alignment), then the firewall raise an error,
for example:
E/TC:0 tzc_it_handler:19 TZC permission failure
E/TC:0 dump_fail_filter:420 Permission violation on filter 0
E/TC:0 dump_fail_filter:425 Violation @0xde5c6bf0, non-secure privileged read,
AXI ID 5c0
E/TC:0 Panic
After investigation, the forbidden access is a speculative request performed
by the Cortex A7 because all the DDR is mapped as MEMORY with CACHEABLE
property.
The issue is solved only when the region reserved by OP-TEE is no more
mapped in U-Boot as it is already done in Linux kernel.
Tested on DK2 board with OP-TEE 3.12 / TF-A 2.4:
With hard-coded address for OP-TEE reserved memory,
the error doesn't occur.
void dram_bank_mmu_setup(int bank)
{
for (i = start >> MMU_SECTION_SHIFT;
i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
i++) {
option = DCACHE_DEFAULT_OPTION;
if (i >= 0xde0)
option = INVALID_ENTRY;
set_section_dcache(i, option);
}
}
Just by modifying the test on 0xde0 to 0xdf0, the OP-TEE memory protected
by firewall is mapped cacheable and the error occurs.
I think that can be a general issue for ARM architecture: the no-map tag
in device should be respected by U-Boot.
But I don't propose a generic
solution in arm/lib/cache-cp15.c:dram_bank_mmu_setup()
because the device tree parsing done in lmb_init_and_reserve() take a
long time when it is executed without data cache.
=> the previous path 7/7 of v2 series is dropped to avoid
performance issue on other ARM target.
To avoid this issue on stm32mp32mp platform, this V3 series moves
the lmb initialization in enable_caches() and the lmb variable becomes a
static struct.
This v3 series is composed by 7 patches
- 1..3/7: preliminary steps to support flags in library in lmb
(as it is done in memblock.c in Linux)
- 4/7: unitary test on the added feature in lmb lib
- 5/7: save the no-map flags in lmb when the device tree is parsed
- 6/7: solve issue for the size of cacheable area in pre-reloc case
- 7/7: update the stm32mp mmu support
See also [4] which handle same speculative access on armv8 for area
with Executable attribute.
[1] http://patchwork.ozlabs.org/project/uboot/list/?series=228543&state=*
[2] http://patchwork.ozlabs.org/project/uboot/list/?series=228202&state=*
[3] http://patchwork.ozlabs.org/project/uboot/list/?series=227570&state=*
[4]
http://patchwork.ozlabs.org/project/uboot/patch/20200903000106.5016-1-marek.bykow...@gmail.com/
Regards
Patrick
Changes in v3:
- NEW: solve performance issue as relocated DT is not marked cacheable
- call lmb_init_and_reserve when data cache is activated in enable_caches()
- drop v2 patch "arm: cache: cp15: don't map the reserved region
with no-map property"
Changes in v2:
- remove unnecessary comments in lmb.h
- rebase on latest lmb patches
- NEW: update in stm32mp specific MMU setup functions
Patrick Delaunay (7):
lmb: Add support of flags for no-map properties
lmb: add lmb_is_reserved_flags
lmb: add lmb_dump_region() function
test: lmb: add test for lmb_reserve_flags
image-fdt: save no-map parameter of reserve-memory
stm32mp: Increase the reserved memory in board_get_usable_ram_top
stm32mp: don't map the reserved region with no-map property
arch/arm/mach-stm32mp/cpu.c | 17 +-
arch/arm/mach-stm32mp/dram_init.c | 3 +-
common/image-fdt.c| 23 +---
include/lmb.h | 21 +++
lib/lmb.c | 94 ++-
test/lib/lmb.c| 89 +
6 files changed, 209 insertions(+), 38 deletions(-)
--
2.17.1
[PATCH v3 7/7] stm32mp: don't map the reserved region with no-map property
No more map the reserved region with "no-map" property by marking
the corresponding TLB entries with invalid entry (=0) to avoid
speculative access.
The device tree parsing done in lmb_init_and_reserve() takes a
long time when it is executed without data cache, so it is called in
enable_caches() before to disable it.
This patch fixes an issue where predictive read access on secure DDR
OP-TEE reserved area are caught by firewall.
Signed-off-by: Patrick Delaunay
---
Changes in v3:
- call lmb_init_and_reserve when data cache is activated in enable_caches()
- drop v2 patch "arm: cache: cp15: don't map the reserved region
with no-map property"
Changes in v2:
- NEW: update in stm32mp specific MMU setup functions
arch/arm/mach-stm32mp/cpu.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 8115d58b19..592bfd413d 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -90,6 +91,8 @@
*/
u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
+struct lmb lmb;
+
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
#ifndef CONFIG_TFABOOT
static void security_init(void)
@@ -221,6 +224,8 @@ void dram_bank_mmu_setup(int bank)
int i;
phys_addr_t start;
phys_size_t size;
+ bool use_lmb = false;
+ enum dcache_option option;
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
@@ -229,6 +234,7 @@ void dram_bank_mmu_setup(int bank)
/* bd->bi_dram is available only after relocation */
start = bd->bi_dram[bank].start;
size = bd->bi_dram[bank].size;
+ use_lmb = true;
} else {
/* mark cacheable and executable the beggining of the DDR */
start = STM32_DDR_BASE;
@@ -237,8 +243,12 @@ void dram_bank_mmu_setup(int bank)
for (i = start >> MMU_SECTION_SHIFT;
i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
-i++)
- set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+i++) {
+ option = DCACHE_DEFAULT_OPTION;
+ if (use_lmb && lmb_is_reserved_flags(&lmb, i <<
MMU_SECTION_SHIFT, LMB_NOMAP))
+ option = 0; /* INVALID ENTRY in TLB */
+ set_section_dcache(i, option);
+ }
}
/*
* initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
@@ -302,6 +312,9 @@ int arch_cpu_init(void)
void enable_caches(void)
{
+ /* parse device tree when data cache is still activated */
+ lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
+
/* I-cache is already enabled in start.S: icache_enable() not needed */
/* deactivate the data cache, early enabled in arch_cpu_init() */
--
2.17.1
[PATCH v3 5/7] image-fdt: save no-map parameter of reserve-memory
Save the no-map information present in 'reserved-memory' node to allow
correct handling when the MMU is configured in board to avoid
speculative access.
Signed-off-by: Patrick Delaunay
---
(no changes since v1)
common/image-fdt.c | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/common/image-fdt.c b/common/image-fdt.c
index d50e1ba3fe..06dce92a28 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -75,18 +75,20 @@ static const image_header_t *image_get_fdt(ulong fdt_addr)
#endif
static void boot_fdt_reserve_region(struct lmb *lmb, uint64_t addr,
- uint64_t size)
+ uint64_t size, enum lmb_flags flags)
{
long ret;
- ret = lmb_reserve(lmb, addr, size);
+ ret = lmb_reserve_flags(lmb, addr, size, flags);
if (ret >= 0) {
- debug(" reserving fdt memory region: addr=%llx size=%llx\n",
- (unsigned long long)addr, (unsigned long long)size);
+ debug(" reserving fdt memory region: addr=%llx size=%llx
flags=%x\n",
+ (unsigned long long)addr,
+ (unsigned long long)size, flags);
} else {
puts("ERROR: reserving fdt memory region failed ");
- printf("(addr=%llx size=%llx)\n",
- (unsigned long long)addr, (unsigned long long)size);
+ printf("(addr=%llx size=%llx flags=%x)\n",
+ (unsigned long long)addr,
+ (unsigned long long)size, flags);
}
}
@@ -106,6 +108,7 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void
*fdt_blob)
int i, total, ret;
int nodeoffset, subnode;
struct fdt_resource res;
+ enum lmb_flags flags;
if (fdt_check_header(fdt_blob) != 0)
return;
@@ -115,7 +118,7 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void
*fdt_blob)
for (i = 0; i < total; i++) {
if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
continue;
- boot_fdt_reserve_region(lmb, addr, size);
+ boot_fdt_reserve_region(lmb, addr, size, LMB_NONE);
}
/* process reserved-memory */
@@ -127,9 +130,13 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void
*fdt_blob)
ret = fdt_get_resource(fdt_blob, subnode, "reg", 0,
&res);
if (!ret && fdtdec_get_is_enabled(fdt_blob, subnode)) {
+ flags = LMB_NONE;
+ if (fdtdec_get_bool(fdt_blob, subnode,
+ "no-map"))
+ flags = LMB_NOMAP;
addr = res.start;
size = res.end - res.start + 1;
- boot_fdt_reserve_region(lmb, addr, size);
+ boot_fdt_reserve_region(lmb, addr, size, flags);
}
subnode = fdt_next_subnode(fdt_blob, subnode);
--
2.17.1
[PATCH v3 3/7] lmb: add lmb_dump_region() function
Add lmb_dump_region() function, to simplify lmb_dump_all_force().
This patch is based on Linux memblock dump function.
An example of bdinfo output is:
.
fdt_size= 0x000146a0
FB base = 0xfdd0
lmb_dump_all:
memory.cnt = 0x1
memory[0] [0xc000-0x], 0x4000 bytes flags: 0
reserved.cnt = 0x6
reserved[0][0x1000-0x10045fff], 0x00046000 bytes flags: 4
reserved[1][0x3000-0x3003], 0x0004 bytes flags: 4
reserved[2][0x3800-0x3800], 0x0001 bytes flags: 4
reserved[3][0xe800-0xefff], 0x0800 bytes flags: 4
reserved[4][0xfbaea344-0xfdff], 0x02515cbc bytes flags: 0
reserved[5][0xfe00-0x], 0x0200 bytes flags: 4
arch_number = 0x
TLB addr= 0xfdff
Signed-off-by: Patrick Delaunay
---
(no changes since v1)
lib/lmb.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/lib/lmb.c b/lib/lmb.c
index e270e86186..3b1878fd58 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -14,32 +14,32 @@
#define LMB_ALLOC_ANYWHERE 0
-void lmb_dump_all_force(struct lmb *lmb)
+static void lmb_dump_region(struct lmb_region *rgn, char *name)
{
- unsigned long i;
+ unsigned long long base, size, end;
+ enum lmb_flags flags;
+ int i;
- printf("lmb_dump_all:\n");
- printf("memory.cnt = 0x%lx\n", lmb->memory.cnt);
- for (i = 0; i < lmb->memory.cnt; i++) {
- printf("memory.reg[0x%lx].base = 0x%llx\n", i,
- (unsigned long long)lmb->memory.region[i].base);
- printf(" .size = 0x%llx\n",
- (unsigned long long)lmb->memory.region[i].size);
- printf(" .flags = 0x%x\n",
- lmb->memory.region[i].flags);
- }
+ printf(" %s.cnt = 0x%lx\n", name, rgn->cnt);
- printf("\nreserved.cnt = 0x%lx\n", lmb->reserved.cnt);
- for (i = 0; i < lmb->reserved.cnt; i++) {
- printf("reserved.reg[0x%lx].base = 0x%llx\n", i,
- (unsigned long long)lmb->reserved.region[i].base);
- printf(" .size = 0x%llx\n",
- (unsigned long long)lmb->reserved.region[i].size);
- printf(" .flags = 0x%x\n",
- lmb->reserved.region[i].flags);
+ for (i = 0; i < rgn->cnt; i++) {
+ base = rgn->region[i].base;
+ size = rgn->region[i].size;
+ end = base + size - 1;
+ flags = rgn->region[i].flags;
+
+ printf(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: %x\n",
+ name, i, base, end, size, flags);
}
}
+void lmb_dump_all_force(struct lmb *lmb)
+{
+ printf("lmb_dump_all:\n");
+ lmb_dump_region(&lmb->memory, "memory");
+ lmb_dump_region(&lmb->reserved, "reserved");
+}
+
void lmb_dump_all(struct lmb *lmb)
{
#ifdef DEBUG
--
2.17.1
[PATCH v3 4/7] test: lmb: add test for lmb_reserve_flags
Add a test to check the management of reserved region with flags.
Signed-off-by: Patrick Delaunay
---
(no changes since v1)
test/lib/lmb.c | 89 ++
1 file changed, 89 insertions(+)
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index 0d8963fcbf..b2c2b99ef1 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -723,3 +723,92 @@ static int lib_test_lmb_max_regions(struct unit_test_state
*uts)
DM_TEST(lib_test_lmb_max_regions,
UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+static int lib_test_lmb_flags(struct unit_test_state *uts)
+{
+ const phys_addr_t ram = 0x4000;
+ const phys_size_t ram_size = 0x2000;
+ struct lmb lmb;
+ long ret;
+
+ lmb_init(&lmb);
+
+ ret = lmb_add(&lmb, ram, ram_size);
+ ut_asserteq(ret, 0);
+
+ /* reserve, same flag */
+ ret = lmb_reserve_flags(&lmb, 0x4001, 0x1, LMB_NOMAP);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x4001, 0x1,
+ 0, 0, 0, 0);
+
+ /* reserve again, same flag */
+ ret = lmb_reserve_flags(&lmb, 0x4001, 0x1, LMB_NOMAP);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x4001, 0x1,
+ 0, 0, 0, 0);
+
+ /* reserve again, new flag */
+ ret = lmb_reserve_flags(&lmb, 0x4001, 0x1, LMB_NONE);
+ ut_asserteq(ret, -1);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x4001, 0x1,
+ 0, 0, 0, 0);
+
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
+
+ /* merge after */
+ ret = lmb_reserve_flags(&lmb, 0x4002, 0x1, LMB_NOMAP);
+ ut_asserteq(ret, 1);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x4001, 0x2,
+ 0, 0, 0, 0);
+
+ /* merge before */
+ ret = lmb_reserve_flags(&lmb, 0x4000, 0x1, LMB_NOMAP);
+ ut_asserteq(ret, 1);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x4000, 0x3,
+ 0, 0, 0, 0);
+
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
+
+ ret = lmb_reserve_flags(&lmb, 0x4003, 0x1, LMB_NONE);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 2, 0x4000, 0x3,
+ 0x4003, 0x1, 0, 0);
+
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0);
+
+ /* test that old API use LMB_NONE */
+ ret = lmb_reserve(&lmb, 0x4004, 0x1);
+ ut_asserteq(ret, 1);
+ ASSERT_LMB(&lmb, ram, ram_size, 2, 0x4000, 0x3,
+ 0x4003, 0x2, 0, 0);
+
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0);
+
+ ret = lmb_reserve_flags(&lmb, 0x4007, 0x1, LMB_NOMAP);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 3, 0x4000, 0x3,
+ 0x4003, 0x2, 0x4007, 0x1);
+
+ ret = lmb_reserve_flags(&lmb, 0x4005, 0x1, LMB_NOMAP);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 4, 0x4000, 0x3,
+ 0x4003, 0x2, 0x4005, 0x1);
+
+ /* merge with 2 adjacent regions */
+ ret = lmb_reserve_flags(&lmb, 0x4006, 0x1, LMB_NOMAP);
+ ut_asserteq(ret, 2);
+ ASSERT_LMB(&lmb, ram, ram_size, 3, 0x4000, 0x3,
+ 0x4003, 0x2, 0x4005, 0x3);
+
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0);
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[2]), 1);
+
+ return 0;
+}
+
+DM_TEST(lib_test_lmb_flags,
+ UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
--
2.17.1
[PATCH v3 1/7] lmb: Add support of flags for no-map properties
Add "flags" in lmb_property to save the "no-map" property of
reserved region and a new function lmb_reserve_flags() to check
this flag.
The default allocation use flags = LMB_NONE.
The adjacent reserved memory region are merged only when they have
the same flags value.
This patch is partially based on flags support done in Linux kernel
mm/memblock .c (previously lmb.c); it is why LMB_NOMAP = 0x4, it is
aligned with MEMBLOCK_NOMAP value.
Signed-off-by: Patrick Delaunay
---
(no changes since v2)
Changes in v2:
- remove unnecessary comments in lmb.h
- rebase on latest lmb patches
include/lmb.h | 20
lib/lmb.c | 52 ++-
2 files changed, 63 insertions(+), 9 deletions(-)
diff --git a/include/lmb.h b/include/lmb.h
index 541e17093c..aa196c63bf 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -12,6 +12,16 @@
* Copyright (C) 2001 Peter Bergner, IBM Corp.
*/
+/**
+ * enum lmb_flags - definition of memory region attributes
+ * @LMB_NONE: no special request
+ * @LMB_NOMAP: don't add to mmu configuration
+ */
+enum lmb_flags {
+ LMB_NONE= 0x0,
+ LMB_NOMAP = 0x4,
+};
+
/**
* struct lmb_property - Description of one region.
*
@@ -21,6 +31,7 @@
struct lmb_property {
phys_addr_t base;
phys_size_t size;
+ enum lmb_flags flags;
};
/**
@@ -69,6 +80,8 @@ extern void lmb_init_and_reserve_range(struct lmb *lmb,
phys_addr_t base,
phys_size_t size, void *fdt_blob);
extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+extern long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base,
+ phys_size_t size, enum lmb_flags flags);
extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align);
extern phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong
align,
phys_addr_t max_addr);
@@ -92,6 +105,13 @@ lmb_size_bytes(struct lmb_region *type, unsigned long
region_nr)
void board_lmb_reserve(struct lmb *lmb);
void arch_lmb_reserve(struct lmb *lmb);
+/* Low level functions */
+
+static inline bool lmb_is_nomap(struct lmb_property *m)
+{
+ return !!(m->flags & LMB_NOMAP);
+}
+
#endif /* __KERNEL__ */
#endif /* _LINUX_LMB_H */
diff --git a/lib/lmb.c b/lib/lmb.c
index c08c4d942b..69700bf9ba 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -25,6 +25,8 @@ void lmb_dump_all_force(struct lmb *lmb)
(unsigned long long)lmb->memory.region[i].base);
printf(" .size = 0x%llx\n",
(unsigned long long)lmb->memory.region[i].size);
+ printf(" .flags = 0x%x\n",
+ lmb->memory.region[i].flags);
}
printf("\nreserved.cnt = 0x%lx\n", lmb->reserved.cnt);
@@ -33,6 +35,8 @@ void lmb_dump_all_force(struct lmb *lmb)
(unsigned long long)lmb->reserved.region[i].base);
printf(" .size = 0x%llx\n",
(unsigned long long)lmb->reserved.region[i].size);
+ printf(" .flags = 0x%x\n",
+ lmb->reserved.region[i].flags);
}
}
@@ -81,6 +85,7 @@ static void lmb_remove_region(struct lmb_region *rgn,
unsigned long r)
for (i = r; i < rgn->cnt - 1; i++) {
rgn->region[i].base = rgn->region[i + 1].base;
rgn->region[i].size = rgn->region[i + 1].size;
+ rgn->region[i].flags = rgn->region[i + 1].flags;
}
rgn->cnt--;
}
@@ -144,7 +149,8 @@ void lmb_init_and_reserve_range(struct lmb *lmb,
phys_addr_t base,
}
/* This routine called with relocation disabled. */
-static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base,
phys_size_t size)
+static long lmb_add_region_flags(struct lmb_region *rgn, phys_addr_t base,
+phys_size_t size, enum lmb_flags flags)
{
unsigned long coalesced = 0;
long adjacent, i;
@@ -152,6 +158,7 @@ static long lmb_add_region(struct lmb_region *rgn,
phys_addr_t base, phys_size_t
if (rgn->cnt == 0) {
rgn->region[0].base = base;
rgn->region[0].size = size;
+ rgn->region[0].flags = flags;
rgn->cnt = 1;
return 0;
}
@@ -160,18 +167,27 @@ static long lmb_add_region(struct lmb_region *rgn,
phys_addr_t base, phys_size_t
for (i = 0; i < rgn->cnt; i++) {
phys_addr_t rgnbase = rgn->region[i].base;
phys_size_t rgnsize = rgn->region[i].size;
+ phys_size_t rgnflags = rgn->region[i].flags;
- if ((rgnbase == base) && (rgnsize == size))
- /* Already have this region, so we're don
[PATCH v3 6/7] stm32mp: Increase the reserved memory in board_get_usable_ram_top
Add 8M for the U-Boot reserved memory (display, fdt, gd, ...). Without this patch the device tree, located before the MALLOC area is not tagged cacheable just after relocation, before mmu reconfiguration. This patch reduces the duration for device tree parsing in lmb_init_and_reserve. Signed-off-by: Patrick Delaunay --- Changes in v3: - NEW: solve performance issue as relocated DT is not marked cacheable arch/arm/mach-stm32mp/dram_init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 66e81bacca..9fb3ade82e 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -50,7 +50,8 @@ ulong board_get_usable_ram_top(ulong total_size) lmb_init(&lmb); lmb_add(&lmb, gd->ram_base, gd->ram_size); boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); - size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), + /* add 8M for reserved memory for display, fdt, gd,... */ + size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE); if (!reg) -- 2.17.1
[PATCH v3 2/7] lmb: add lmb_is_reserved_flags
Add a new function lmb_is_reserved_flags to check is a
address is reserved with a specific flags.
This function can be used to check if an address was
reserved with no-map flags with:
lmb_is_reserved_flags(lmb, addr, LMB_NOMAP);
Signed-off-by: Patrick Delaunay
---
(no changes since v1)
include/lmb.h | 1 +
lib/lmb.c | 10 --
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/include/lmb.h b/include/lmb.h
index aa196c63bf..6537d56e18 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -91,6 +91,7 @@ extern phys_addr_t lmb_alloc_addr(struct lmb *lmb,
phys_addr_t base,
phys_size_t size);
extern phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr);
extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
+extern int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags);
extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern void lmb_dump_all(struct lmb *lmb);
diff --git a/lib/lmb.c b/lib/lmb.c
index 69700bf9ba..e270e86186 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -443,7 +443,7 @@ phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t
addr)
return 0;
}
-int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr)
+int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags)
{
int i;
@@ -451,11 +451,17 @@ int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr)
phys_addr_t upper = lmb->reserved.region[i].base +
lmb->reserved.region[i].size - 1;
if ((addr >= lmb->reserved.region[i].base) && (addr <= upper))
- return 1;
+ return !!((lmb->reserved.region[i].flags & flags)
+ == flags);
}
return 0;
}
+int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr)
+{
+ return lmb_is_reserved_flags(lmb, addr, LMB_NONE);
+}
+
__weak void board_lmb_reserve(struct lmb *lmb)
{
/* please define platform specific board_lmb_reserve() */
--
2.17.1
[PATCH] sunxi: clock: H6/H616: Fix PLL6 clock calculation
The "n" factor of the PLL_PERIPH0 clock is using the usual +1 encoding, so we need to adjust the register value before doing the calculation. This fixes the MMC clock setup on those SoCs, which could be slightly off due to the wrong parent frequency: mmc 2 set mod-clk req 5200 parent 117600 n 2 m 12 rate 4900 Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/clock_sun50i_h6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 492fc4a3fca..a947463e0a5 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -94,7 +94,7 @@ unsigned int clock_get_pll6(void) int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2; uint32_t rval = readl(&ccm->pll6_cfg); - int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> CCM_PLL6_CTRL_DIV1_SHIFT) + 1; int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> -- 2.17.5
[PATCH] efi_loader: loosen buffer parameter check in efi_file_read_int
From: Peng Fan
This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
but that fix was wrongly partial reverted.
To Fedora shim loader, when buffer is NULL, a use-case is to call
efi_file_read with *buffer_size=0 and buffer=NULL to obtain the needed
size before doing the actual read.
Otherwise, we always met "Could not read \EFI\: Invalid Parameter"
Fixes: db12f518edb0("efi_loader: implement non-blocking file services")
Signed-off-by: Peng Fan
Cc: Heinrich Schuchardt
Cc: Stefan Sørensen
---
lib/efi_loader/efi_file.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
index 204105e25a..6b3f5962be 100644
--- a/lib/efi_loader/efi_file.c
+++ b/lib/efi_loader/efi_file.c
@@ -554,7 +554,7 @@ static efi_status_t efi_file_read_int(struct
efi_file_handle *this,
efi_status_t ret = EFI_SUCCESS;
u64 bs;
- if (!this || !buffer_size || !buffer)
+ if (!this || !buffer_size)
return EFI_INVALID_PARAMETER;
bs = *buffer_size;
--
2.30.0
