Re: [PATCH] fastboot: Fix overflow when calculating chunk size
Hi Sean,
> On 5/13/21 11:54 AM, Sean Anderson wrote:
> > Hi Lukasz,
> >
> > Can this make it into 2020.07? Thanks,
>
> ping? Should Tom pick this up instead?
>
Yes, Tom please pick it up - as I will not prepare PR sooner than June.
> --Sean
>
> >
> > --Sean
> >
> > On 4/16/21 5:58 PM, Sean Anderson wrote:
> >> If a chunk was larger than 4GiB, then chunk_data_sz would overflow
> >> and blkcnt would not be calculated correctly. Upgrade it to a u64
> >> and cast its multiplicands as well. Also fix bytes_written while
> >> we're at it.
> >>
> >> Signed-off-by: Sean Anderson
> >> ---
> >>
> >> lib/image-sparse.c | 12 ++--
> >> 1 file changed, 6 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/lib/image-sparse.c b/lib/image-sparse.c
> >> index 187ac28cd3..52c8dcc08c 100644
> >> --- a/lib/image-sparse.c
> >> +++ b/lib/image-sparse.c
> >> @@ -55,10 +55,10 @@ int write_sparse_image(struct sparse_storage
> >> *info, lbaint_t blk;
> >> lbaint_t blkcnt;
> >> lbaint_t blks;
> >> - uint32_t bytes_written = 0;
> >> + uint64_t bytes_written = 0;
> >> unsigned int chunk;
> >> unsigned int offset;
> >> - unsigned int chunk_data_sz;
> >> + uint64_t chunk_data_sz;
> >> uint32_t *fill_buf = NULL;
> >> uint32_t fill_val;
> >> sparse_header_t *sparse_header;
> >> @@ -132,7 +132,7 @@ int write_sparse_image(struct sparse_storage
> >> *info, sizeof(chunk_header_t));
> >> }
> >> - chunk_data_sz = sparse_header->blk_sz *
> >> chunk_header->chunk_sz;
> >> + chunk_data_sz = ((u64)sparse_header->blk_sz) *
> >> chunk_header->chunk_sz; blkcnt = chunk_data_sz / info->blksz;
> >> switch (chunk_header->chunk_type) {
> >> case CHUNK_TYPE_RAW:
> >> @@ -162,7 +162,7 @@ int write_sparse_image(struct sparse_storage
> >> *info, return -1;
> >> }
> >> blk += blks;
> >> - bytes_written += blkcnt * info->blksz;
> >> + bytes_written += ((u64)blkcnt) * info->blksz;
> >> total_blocks += chunk_header->chunk_sz;
> >> data += chunk_data_sz;
> >> break;
> >> @@ -222,7 +222,7 @@ int write_sparse_image(struct sparse_storage
> >> *info, blk += blks;
> >> i += j;
> >> }
> >> - bytes_written += blkcnt * info->blksz;
> >> + bytes_written += ((u64)blkcnt) * info->blksz;
> >> total_blocks += chunk_data_sz /
> >> sparse_header->blk_sz; free(fill_buf);
> >> break;
> >> @@ -253,7 +253,7 @@ int write_sparse_image(struct sparse_storage
> >> *info, debug("Wrote %d blocks, expected to write %d blocks\n",
> >> total_blocks, sparse_header->total_blks);
> >> - printf(" wrote %u bytes to '%s'\n", bytes_written,
> >> part_name);
> >> + printf(" wrote %llu bytes to '%s'\n", bytes_written,
> >> part_name); if (total_blocks != sparse_header->total_blks) {
> >> info->mssg("sparse image write failure", response);
> >>
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
pgpkGMD68qyFs.pgp
Description: OpenPGP digital signature
Re: [PATCH] net: ravb: Add additional refclk
On Tue, May 25, 2021 at 8:52 PM Adam Ford wrote:
>
> The ethernet requires an external reference clock, and the driver
> currently assumes the clock is always running. For devices using
> a programmable clock, this may not be true. Add an optional clock
> called 'refclk' to open and enable the refclk for hardware running
> with programmable clocks.
>
> Signed-off-by: Adam Ford
> ---
> This was also done in the Linux kernel, see:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/net/ethernet/renesas/ravb_main.c?id=8ef7adc6beb2ef0bce83513dc9e4505e7b21e8c2
>
> diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
> index 6953b7286a..ced80485de 100644
> --- a/drivers/net/ravb.c
> +++ b/drivers/net/ravb.c
> @@ -130,6 +130,7 @@ struct ravb_priv {
> struct mii_dev *bus;
> void __iomem*iobase;
> struct clk clk;
> + struct clk *refclk;
> struct gpio_descreset_gpio;
> };
>
> @@ -489,6 +490,8 @@ static int ravb_probe(struct udevice *dev)
> if (ret < 0)
> goto err_mdio_alloc;
>
> + eth->refclk = devm_clk_get_optional(dev, "refclk");
> +
> ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
> &phandle_args);
> if (!ret) {
> gpio_request_by_name_nodev(phandle_args.node, "reset-gpios",
> 0,
> @@ -522,6 +525,10 @@ static int ravb_probe(struct udevice *dev)
> if (ret)
> goto err_mdio_register;
>
> + ret = clk_enable(eth->refclk);
> + if (ret)
> + goto err_disable_clk;
> +
> ret = ravb_reset(dev);
> if (ret)
> goto err_mdio_reset;
> @@ -533,6 +540,8 @@ static int ravb_probe(struct udevice *dev)
> return 0;
>
> err_mdio_reset:
> + clk_disable(eth->refclk);
> +err_disable_clk:
> clk_disable(ð->clk);
> err_mdio_register:
> mdio_free(mdiodev);
> @@ -545,6 +554,7 @@ static int ravb_remove(struct udevice *dev)
> {
> struct ravb_priv *eth = dev_get_priv(dev);
>
> + clk_disable(eth->refclk);
> clk_disable(ð->clk);
>
> free(eth->phydev);
> --
> 2.25.1
>
Reviewed-by: Ramon Fried
Re: [PATCH] fs/squashfs: fix reading of fragmented files
Hi Joao, Joao Marcos Costa wrote on Mon, 17 May 2021 18:20:38 -0300: > The fragmented files were not correctly read because of two issues: > > - The squashfs_file_info struct has a field named 'comp', which tells if > the file's fragment is compressed or not. This field was always set to > 'true' in sqfs_get_regfile_info and sqfs_get_lregfile_info. It should > actually take sqfs_frag_lookup's return value. This patch addresses > these two assignments. > > - In sqfs_read, the fragments (compressed or not) were copied to the > output buffer through a for loop which was reading data at the wrong > offset. Replace these loops by equivalent calls to memcpy, with the > right parameters. Good idea to get rid of these memcpy of 1 byte :) > I tested this patch by comparing the MD5 checksum of a few fragmented > files with the respective md5sum output in sandbox, considering both > compressed and uncompressed fragments. > > Signed-off-by: Joao Marcos Costa Reviewed-by: Miquel Raynal But next time, when you fix two issues (even if they fix the same feature) please provide two patches ;) Thanks, Miquèl
[PULL] u-boot-riscv/master
Hi Tom,
The following changes since commit eb53b943be2949ca40a8e05532cd74cda058:
Merge https://source.denx.de/u-boot/custodians/u-boot-sh (2021-05-23 10:15:15
-0400)
are available in the Git repository at:
g...@source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 9358576a281ab5e3b7348685bbd5f713833a5048:
drivers: pci: pcie_dw_common: fix Werror compilation error (2021-05-24
23:54:54 +0800)
Gitlab CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7620
Green Wan (9):
riscv: cpu: fu740: Add support for cpu fu740
drivers: clk: add fu740 support
drivers: ram: sifive: rename fu540_ddr and add fu740 support
drivers: pci: add pcie support for fu740
riscv: dts: add fu740 support
riscv: dts: add SiFive Unmatched board support
board: sifive: add HiFive Unmatched board support
riscv: cpu: fu740: clear feature disable CSR
drivers: pci: pcie_dw_common: fix Werror compilation error
arch/riscv/Kconfig |5 +
arch/riscv/cpu/fu540/Kconfig |2 +-
arch/riscv/cpu/fu740/Kconfig | 37 +
arch/riscv/cpu/fu740/Makefile | 12 +
arch/riscv/cpu/fu740/cache.c | 55 +
arch/riscv/cpu/fu740/cpu.c | 22 +
arch/riscv/cpu/fu740/dram.c| 38 +
arch/riscv/cpu/fu740/spl.c | 38 +
arch/riscv/dts/Makefile|1 +
arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 ++
arch/riscv/dts/fu740-c000.dtsi | 329 +
arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489
arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi| 41 +
arch/riscv/dts/hifive-unmatched-a00.dts| 259
arch/riscv/include/asm/arch-fu740/cache.h | 14 +
arch/riscv/include/asm/arch-fu740/clk.h| 14 +
arch/riscv/include/asm/arch-fu740/gpio.h | 38 +
arch/riscv/include/asm/arch-fu740/reset.h | 13 +
arch/riscv/include/asm/arch-fu740/spl.h| 14 +
board/sifive/unleashed/Kconfig |1 +
board/sifive/unmatched/Kconfig | 51 +
board/sifive/unmatched/MAINTAINERS |9 +
board/sifive/unmatched/Makefile|9 +
board/sifive/unmatched/spl.c | 85 ++
board/sifive/unmatched/unmatched.c | 24 +
common/spl/Kconfig |4 +-
configs/sifive_unmatched_defconfig | 54 +
doc/board/sifive/index.rst |1 +
doc/board/sifive/unmatched.rst | 536 +++
drivers/clk/sifive/Kconfig |8 +-
drivers/clk/sifive/Makefile|4 +-
drivers/clk/sifive/fu540-prci.c| 769 +-
drivers/clk/sifive/fu540-prci.h| 22 +
drivers/clk/sifive/fu740-prci.c| 158 +++
drivers/clk/sifive/fu740-prci.h| 22 +
drivers/clk/sifive/sifive-prci.c | 733 ++
drivers/clk/sifive/sifive-prci.h | 323 +
drivers/pci/Kconfig| 10 +
drivers/pci/Makefile |1 +
drivers/pci/pcie_dw_common.c | 54 +-
drivers/pci/pcie_dw_sifive.c | 507 +++
drivers/ram/sifive/Kconfig |8 +-
drivers/ram/sifive/Makefile|2 +-
drivers/ram/sifive/{fu540_ddr.c => sifive_ddr.c} | 89 +-
drivers/reset/Kconfig |2 +-
include/configs/sifive-unmatched.h | 85 ++
include/dt-bindings/clock/sifive-fu740-prci.h | 25 +
include/dt-bindings/reset/sifive-fu740-prci.h | 19 +
48 files changed, 5310 insertions(+), 831 deletions(-)
create mode 100644 arch/riscv/cpu/fu740/Kconfig
create mode 100644 arch/riscv/cpu/fu740/Makefile
create mode 100644 arch/riscv/cpu/fu740/cache.c
create mode 100644 arch/riscv/cpu/fu740/cpu.c
create mode 100644 arch/riscv/cpu/fu740/dram.c
create mode 100644 arch/riscv/cpu/fu740/spl.c
create mode 100644 arch/riscv/dts/fu740-c000-u-boot.dtsi
create mode 100644 arch/riscv/dts/fu740-c000.dtsi
create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts
create mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
create mode 100644 arch/riscv/include/asm/arch-fu740/clk.h
create mode 100644 arch/riscv/include/asm/arch-fu740/gpio.h
create mode 100644 arch/riscv/include/asm/arch-fu740/reset.h
creat
[PATCH] rk3399: boot_devices fix spinor node name
Problem: board_spl_was_booted_from return wrong boot_devices[3] value
/spi@ff1d and same-as-spl dont work properly for SPINOR flash
because arch/arm/mach-rockchip/spl-boot-order.c spl_node_to_boot_device
need parse SPINOR flash node as UCLASS_SPI_FLASH
spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ...
/spi@ff1d > board_boot_order: could not map node @618 to a boot-device
/sdhci@fe33 > /mmc@fe32
Solution: just change it to /spi@ff1d/flash@0
spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ...
/spi@ff1d/flash@0 > /sdhci@fe33 > /mmc@fe32
Signed-off-by: Artem Lapkin
---
arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c
b/arch/arm/mach-rockchip/rk3399/rk3399.c
index 869d2159..69e0c8c2 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe33",
- [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d",
+ [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@fe32",
};
--
2.25.1
[PATCH] evb_rk3399: add usb ohci definations
Problem: not possible to use CONFIG_USB_OHCI_HCD=y and CONFIG_USB_OHCI_GENERIC=y options without CONFIG_USB_OHCI_NEW and CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS definations Add missed definations. Signed-off-by: Artem Lapkin --- include/configs/evb_rk3399.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index b7e85037..492b7b4d 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -15,4 +15,7 @@ #define SDRAM_BANK_SIZE(2UL << 30) +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + #endif -- 2.25.1
[PATCH] rk3399_common: setup fdtoverlay_addr_r value
fdtoverlay (pxe_utils) require define fdtoverlay_addr_r env variable for example sunxi-common.h meson64.h already have it. Signed-off-by: Artem Lapkin --- include/configs/rk3399_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index f0be3830..13d15b1f 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -51,6 +51,7 @@ "script_size_f=0x2000\0" \ "pxefile_addr_r=0x0060\0" \ "fdt_addr_r=0x01f0\0" \ + "fdtoverlay_addr_r=0x0200\0" \ "kernel_addr_r=0x0208\0" \ "ramdisk_addr_r=0x0600\0" \ "kernel_comp_addr_r=0x0800\0" \ -- 2.25.1
Uboot raspberry pi watchdog disabled by mistake
Hello uboot community, In 2019, commit [1] deleted commit [2]. Commit [2] implemented the watchdog feature for raspberry pi. The delete reason is, I quote, "The BCM2835/2836 watchdog is not used in mainline U-Boot at all". I am using commit [2] in conjunction with bootlimit: - uboot increments bootcount, enables watchdog and boots linux using bootcmd - if linux hangs, the watchdog resets the board - in uboot, if bootcount > bootlimit then boot using altbootcmd and boots another partition with linux So, there is use of commit [2] and I consider that commit [1] is a mistake. [1] https://lists.denx.de/pipermail/u-boot/2019-May/369007.html [2] https://lists.denx.de/pipermail/u-boot/2017-January/279573.html Thank you, L-C. Duca
Re: [PATCH] phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSB
Hi Andre,
Le Wed 26 May 21, 01:57, Andre Przywara a écrit :
> From: Paul Kocialkowski
>
> Recent Allwinner platforms (starting with the H3) only use the MUSB
> controller for peripheral mode and use HCI for host mode. As a result,
> extra steps need to be taken to properly route USB signals to one or
> the other. More precisely, the following is required:
> * Routing the pins to either HCI/MUSB (controlled by PHY);
> * Enabling USB PHY passby in HCI mode (controlled by PMU).
>
> The current code will enable passby for each PHY and reroute PHY0 to
> MUSB, which is inconsistent and results in broken USB host support
> for port 0.
>
> Passby on PHY0 must only be enabled when we want to use HCI. Since
> host/device mode detection is not available from the PHY code and
> because U-Boot does not support changing the mode dynamically anyway,
> we can just mux the controller to MUSB if it is enabled and mux it to
> HCI otherwise.
>
> This fixes USB host support for port 0 on platforms with PHY0 dual-route,
> especially on boards like Pine64 (with only USB-A host ports) and
> TV boxes without OTG ports.
>
> Signed-off-by: Paul Kocialkowski
> [Andre: tweak commit message, use IS_ENABLED()]
> Signed-off-by: Andre Przywara
> ---
> Hi,
>
> for H6 boards to work this requires a DT update (to get the <&usbphy 0>
> links between HCI and PHY), which I will send later.
> Tested on Pine H64, Pine64-LTS, OrangePi Zero, OrangePi PC 2, BananaPi M64,
> BananaPi M1.
Thanks for resending this, I've also had to revive this patch lately to get
USB working on the V3 so I definitely second that it's still relevant!
Paul
> Cheers,
> Andre
>
> drivers/phy/allwinner/phy-sun4i-usb.c | 16 ++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> b/drivers/phy/allwinner/phy-sun4i-usb.c
> index 5723c980323..e6ceafc7648 100644
> --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> @@ -313,9 +313,21 @@ static int sun4i_usb_phy_init(struct phy *phy)
> data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
> }
>
> - sun4i_usb_phy_passby(phy, true);
> + if (IS_ENABLED(CONFIG_USB_MUSB_SUNXI)) {
> + /* Needed for HCI and conflicts with MUSB, keep PHY0 on MUSB */
> + if (usb_phy->id != 0)
> + sun4i_usb_phy_passby(phy, true);
> +
> + /* Route PHY0 to MUSB to allow USB gadget */
> + if (data->cfg->phy0_dual_route)
> + sun4i_usb_phy0_reroute(data, true);
> + } else {
> + sun4i_usb_phy_passby(phy, true);
>
> - sun4i_usb_phy0_reroute(data, true);
> + /* Route PHY0 to HCI to allow USB host */
> + if (data->cfg->phy0_dual_route)
> + sun4i_usb_phy0_reroute(data, false);
> + }
>
> return 0;
> }
> --
> 2.17.5
>
--
Developer of free digital technology and hardware support.
Website: https://www.paulk.fr/
Coding blog: https://code.paulk.fr/
Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/
signature.asc
Description: PGP signature
Re: [PATCH] spi: zynqmp_gqspi: Fix write issue
On 5/25/21 2:36 PM, Ashok Reddy Soma wrote:
> Enable manual start in zynqmp_qspi_fill_gen_fifo().
> Also enable GQSPI_IXR_GFNFULL_MASK and check for it instead of
> GQSPI_IXR_GFEMTY_MASK.
>
> Add dummy write to genfifo register in chipselect.
>
> Signed-off-by: Ashok Reddy Soma
> ---
>
> drivers/spi/zynqmp_gqspi.c | 18 +-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
> index 17780066ae..fc81b07343 100644
> --- a/drivers/spi/zynqmp_gqspi.c
> +++ b/drivers/spi/zynqmp_gqspi.c
> @@ -39,6 +39,7 @@
> #define GQSPI_IXR_TXFULL_MASK0x0008 /* QSPI TX FIFO is
> full */
> #define GQSPI_IXR_RXNEMTY_MASK 0x0010 /* QSPI RX FIFO Not
> Empty */
> #define GQSPI_IXR_GFEMTY_MASK0x0080 /* QSPI Generic FIFO
> Empty */
> +#define GQSPI_IXR_GFNFULL_MASK 0x0200 /* QSPI GENFIFO not
> full */
> #define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \
>GQSPI_IXR_RXNEMTY_MASK)
>
> @@ -238,9 +239,21 @@ static void zynqmp_qspi_fill_gen_fifo(struct
> zynqmp_qspi_priv *priv,
> u32 gqspi_fifo_reg)
> {
> struct zynqmp_qspi_regs *regs = priv->regs;
> + u32 config_reg, ier;
> int ret = 0;
>
> - ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1,
> + config_reg = readl(®s->confr);
> + /* Manual start if needed */
> + config_reg |= GQSPI_STRT_GEN_FIFO;
> + writel(config_reg, ®s->confr);
> +
> + /* Enable interrupts */
> + ier = readl(®s->ier);
> + ier |= GQSPI_IXR_GFNFULL_MASK;
> + writel(ier, ®s->ier);
> +
> + /* Wait until the fifo is not full to write the new command */
> + ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFNFULL_MASK, 1,
> GQSPI_TIMEOUT, 1);
> if (ret)
> printf("%s Timeout\n", __func__);
> @@ -263,6 +276,9 @@ static void zynqmp_qspi_chipselect(struct
> zynqmp_qspi_priv *priv, int is_on)
>
> debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
>
> + /* Dummy generic FIFO entry */
> + zynqmp_qspi_fill_gen_fifo(priv, 0);
> +
> zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
> }
>
>
Tested-by: Michal Simek
I will queue it and should be good to get it to v2021.07.
Thanks,
Michal
[PATCH v2 1/2] rockchip: rk3568: add device tree file
From: Elaine Zhang Add dts binding header for rk3568, files origin from kernel. Signed-off-by: Elaine Zhang --- include/dt-bindings/clock/rk3568-cru.h | 925 + 1 file changed, 925 insertions(+) create mode 100644 include/dt-bindings/clock/rk3568-cru.h diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h new file mode 100644 index ..c1942422a438 --- /dev/null +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -0,0 +1,925 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H + +/* pmucru-clocks indices */ + +/* pmucru plls */ +#define PLL_PPLL 1 +#define PLL_HPLL 2 + +/* pmucru clocks */ +#define XIN_OSC0_DIV 4 +#define CLK_RTC_32K5 +#define CLK_PMU6 +#define CLK_I2C0 7 +#define CLK_RTC32K_FRAC8 +#define CLK_UART0_DIV 9 +#define CLK_UART0_FRAC 10 +#define SCLK_UART0 11 +#define DBCLK_GPIO012 +#define CLK_PWM0 13 +#define CLK_CAPTURE_PWM0_NDFT 14 +#define CLK_PMUPVTM15 +#define CLK_CORE_PMUPVTM 16 +#define CLK_REF24M 17 +#define XIN_OSC0_USBPHY0_G 18 +#define CLK_USBPHY0_REF19 +#define XIN_OSC0_USBPHY1_G 20 +#define CLK_USBPHY1_REF21 +#define XIN_OSC0_MIPIDSIPHY0_G 22 +#define CLK_MIPIDSIPHY0_REF23 +#define XIN_OSC0_MIPIDSIPHY1_G 24 +#define CLK_MIPIDSIPHY1_REF25 +#define CLK_WIFI_DIV 26 +#define CLK_WIFI_OSC0 27 +#define CLK_WIFI 28 +#define CLK_PCIEPHY0_DIV 29 +#define CLK_PCIEPHY0_OSC0 30 +#define CLK_PCIEPHY0_REF 31 +#define CLK_PCIEPHY1_DIV 32 +#define CLK_PCIEPHY1_OSC0 33 +#define CLK_PCIEPHY1_REF 34 +#define CLK_PCIEPHY2_DIV 35 +#define CLK_PCIEPHY2_OSC0 36 +#define CLK_PCIEPHY2_REF 37 +#define CLK_PCIE30PHY_REF_M38 +#define CLK_PCIE30PHY_REF_N39 +#define CLK_HDMI_REF 40 +#define XIN_OSC0_EDPPHY_G 41 +#define PCLK_PDPMU 42 +#define PCLK_PMU 43 +#define PCLK_UART0 44 +#define PCLK_I2C0 45 +#define PCLK_GPIO0 46 +#define PCLK_PMUPVTM 47 +#define PCLK_PWM0 48 +#define CLK_PDPMU 49 +#define SCLK_32K_IOE 50 + +#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_VPLL 5 +#define PLL_NPLL 6 + +/* cru clocks */ +#define CPLL_333M 9 +#define ARMCLK 10 +#define USB480M11 +#define ACLK_CORE_NIU2BUS 18 +#define CLK_CORE_PVTM 19 +#define CLK_CORE_PVTM_CORE 20 +#define CLK_CORE_PVTPLL21 +#define CLK_GPU_SRC22 +#define CLK_GPU_PRE_NDFT 23 +#define CLK_GPU_PRE_MUX24 +#define ACLK_GPU_PRE 25 +#define PCLK_GPU_PRE 26 +#define CLK_GPU27 +#define CLK_GPU_NP528 +#define PCLK_GPU_PVTM 29 +#define CLK_GPU_PVTM 30 +#define CLK_GPU_PVTM_CORE 31 +#define CLK_GPU_PVTPLL 32 +#define CLK_NPU_SRC33 +#define CLK_NPU_PRE_NDFT 34 +#define CLK_NPU35 +#define CLK_NPU_NP536 +#define HCLK_NPU_PRE 37 +#define PCLK_NPU_PRE 38 +#define ACLK_NPU_PRE 39 +#define ACLK_NPU 40 +#define HCLK_NPU 41 +#define PCLK_NPU_PVTM 42 +#define CLK_NPU_PVTM 43 +#define CLK_NPU_PVTM_CORE 44 +#define CLK_NPU_PVTPLL 45 +#define CLK_DDRPHY1X_SRC 46 +#define CLK_DDRPHY1X_HWFFC_SRC 47 +#define CLK_DDR1X 48 +#define CLK_MSCH 49 +#define CLK24_DDRMON 50 +#define ACLK_GIC_AUDIO 51 +#define HCLK_GIC_AUDIO 52 +#define HCLK_SDMMC_BUFFER 53 +#define DCLK_SDMMC_BUFFER 54 +#define ACLK_GIC60055 +#define ACLK_SPINLOCK 56 +#define HCLK_I2S0_8CH 57 +#define HCLK_I2S1_8CH 58 +#define HCLK_I2S2_2CH 59 +#define HCLK_I2S3_2CH 60 +#define CLK_I2S0_8CH_TX_SRC61 +#define CLK_I2S0_8CH_TX_FRAC 62 +#define MCLK_I2S0_8CH_TX 63 +#define I2S0_MCLKOUT_TX64 +#define CLK_I2S0_8CH_RX_SRC65 +#define CLK_I2S0_8CH_RX_FRAC 66 +#define MCLK_I2S0_8CH_RX 67 +#define I2S0_MCLKOUT_RX68 +#define CLK_I2S1_8CH_TX_SRC69 +#define CLK_I2S1_8CH_TX_FRAC 70 +#define MCLK_I2S1_8CH_TX 71 +#define I2S1_MCLKOUT_TX72 +#define CLK_I2S1_8CH_RX_SRC73 +#define
[PATCH v2 0/2] clk: rockchip: rk3568: add clock driver
From: Elaine Zhang Add basic clock for rk3568 which including cpu, bus, mmc, i2c, pwm, gmac ...clocks init. Change in V2: [PATCH v2 0/1]: No change. [PATCH v2 0/2]: update the copyright info and remove unused clock set/get. Elaine Zhang (2): rockchip: rk3568: add device tree file rockchip: rk3568: add clock driver .../include/asm/arch-rockchip/cru_rk3568.h| 504 +++ drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk_rk3568.c | 2959 + include/dt-bindings/clock/rk3568-cru.h| 925 ++ 4 files changed, 4389 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3568.h create mode 100644 drivers/clk/rockchip/clk_rk3568.c create mode 100644 include/dt-bindings/clock/rk3568-cru.h -- 2.17.1
[PATCH v5 0/6] power: pmic: support more PMIC
From: Elaine Zhang Support more PMIC and improve compatibility between pmics. Change in V5: [PATCH v5 1/6]: Fixed test case run error. [PATCH v5 2/6]: Resolve compile warning. [PATCH v5 3/6]: No change. [PATCH v5 4/6]: No change. [PATCH v5 5/6]: No change. [PATCH v5 6/6]: No change. Change in V4: [PATCH v4 1/6]: No change. [PATCH v4 2/6]: No change. [PATCH v4 3/6]: No change. [PATCH v4 4/6]: No change. [PATCH v4 5/6]: Resolve code conflicts after ptach v3 5/8 and 6/8 deletion.. [PATCH v4 6/6]: Resolve code conflicts after ptach v3 5/8 and 6/8 deletion. Remove [PATCH v3 5/8] and [PATCH v3 6/8], There is no application scenario. Change in V3: [PATCH v3 1/8]: Add document instructions, Correct error handling. [PATCH v3 2/8]: No change. [PATCH v3 3/8]: No change. [PATCH v3 4/8]: No change. [PATCH v3 5/8]: Update commit message. [PATCH v3 6/8]: Update commit message. [PATCH v3 7/8]: No change. [PATCH v3 8/8]: No change. Change in V2: [PATCH v2 1/8]: Add regulator suspend volatge and en/disable test. [PATCH v2 2/8]: Split the [PATCH v1 2/7], rk808 and rk818 updates. [PATCH v2 3/8]: Split the [PATCH v1 2/7], support rk816 pmic and update commit message. [PATCH v2 4/8]: Update commit message. [PATCH v2 5/8]: No change. [PATCH v2 6/8]: No change. [PATCH v2 7/8]: Remove rk809 keywords and update commit message. [PATCH v2 8/8]: Update commit message. Elaine Zhang (3): power: regulator: rk8xx: update the driver for rk808 and rk818 power: pmic: rk816: support rk816 pmic power: pmic: rk805: support rk805 pmic Joseph Chen (3): dm: regulator: support regulator more state power: pmic: rk817: support rk817 pmic power: pmic: rk809: support rk809 pmic doc/device-tree-bindings/regulator/regulator.txt | 27 + drivers/power/pmic/rk8xx.c | 89 ++- drivers/power/regulator/regulator-uclass.c | 70 ++ drivers/power/regulator/rk8xx.c | 939 +-- include/power/regulator.h| 64 ++ include/power/rk8xx_pmic.h | 42 + test/dm/regulator.c | 57 ++ 7 files changed, 1200 insertions(+), 88 deletions(-) -- 1.9.1
[PATCH v5 1/6] dm: regulator: support regulator more state
From: Joseph Chen
support parse regulator standard property:
regulator-off-in-suspend;
regulator-init-microvolt;
regulator-suspend-microvolt:
regulator_get_suspend_enable
regulator_set_suspend_enable
regulator_get_suspend_value
regulator_set_suspend_value
Signed-off-by: Joseph Chen
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
---
doc/device-tree-bindings/regulator/regulator.txt | 27 +
drivers/power/regulator/regulator-uclass.c | 70
include/power/regulator.h| 64 ++
test/dm/regulator.c | 57 +++
4 files changed, 218 insertions(+)
diff --git a/doc/device-tree-bindings/regulator/regulator.txt
b/doc/device-tree-bindings/regulator/regulator.txt
index 4ba642b7c77f..6c9a02120fde 100644
--- a/doc/device-tree-bindings/regulator/regulator.txt
+++ b/doc/device-tree-bindings/regulator/regulator.txt
@@ -36,6 +36,28 @@ Optional properties:
- regulator-always-on: regulator should never be disabled
- regulator-boot-on: enabled by bootloader/firmware
- regulator-ramp-delay: ramp delay for regulator (in uV/us)
+- regulator-init-microvolt: a init allowed Voltage value
+- regulator-state-(standby|mem|disk)
+ type: object
+ description:
+sub-nodes for regulator state in Standby, Suspend-to-RAM, and
+Suspend-to-DISK modes. Equivalent with standby, mem, and disk Linux
+sleep states.
+
+properties:
+ regulator-on-in-suspend:
+description: regulator should be on in suspend state.
+type: boolean
+
+ regulator-off-in-suspend:
+description: regulator should be off in suspend state.
+type: boolean
+
+ regulator-suspend-microvolt:
+description: the default voltage which regulator would be set in
+ suspend. This property is now deprecated, instead setting voltage
+ for suspend mode via the API which regulator driver provides is
+ recommended.
Note
The "regulator-name" constraint is used for setting the device's uclass
@@ -59,7 +81,12 @@ ldo0 {
regulator-max-microvolt = <180>;
regulator-min-microamp = <10>;
regulator-max-microamp = <10>;
+ regulator-init-microvolt = <180>;
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <12000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <180>;
+ };
};
diff --git a/drivers/power/regulator/regulator-uclass.c
b/drivers/power/regulator/regulator-uclass.c
index 76be95bcd159..4986c87e7ba6 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -77,6 +77,33 @@ int regulator_set_value(struct udevice *dev, int uV)
return ret;
}
+int regulator_set_suspend_value(struct udevice *dev, int uV)
+{
+ const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ if (uc_pdata->min_uV != -ENODATA && uV < uc_pdata->min_uV)
+ return -EINVAL;
+ if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV)
+ return -EINVAL;
+
+ if (!ops->set_suspend_value)
+ return -ENOSYS;
+
+ return ops->set_suspend_value(dev, uV);
+}
+
+int regulator_get_suspend_value(struct udevice *dev)
+{
+ const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
+
+ if (!ops->get_suspend_value)
+ return -ENOSYS;
+
+ return ops->get_suspend_value(dev);
+}
+
/*
* To be called with at most caution as there is no check
* before setting the actual voltage value.
@@ -170,6 +197,26 @@ int regulator_set_enable_if_allowed(struct udevice *dev,
bool enable)
return ret;
}
+int regulator_set_suspend_enable(struct udevice *dev, bool enable)
+{
+ const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
+
+ if (!ops->set_suspend_enable)
+ return -ENOSYS;
+
+ return ops->set_suspend_enable(dev, enable);
+}
+
+int regulator_get_suspend_enable(struct udevice *dev)
+{
+ const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
+
+ if (!ops->get_suspend_enable)
+ return -ENOSYS;
+
+ return ops->get_suspend_enable(dev);
+}
+
int regulator_get_mode(struct udevice *dev)
{
const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
@@ -235,6 +282,14 @@ int regulator_autoset(struct udevice *dev)
int ret = 0;
uc_pdata = dev_get_uclass_platdata(dev);
+
+ ret = regulator_set_suspend_enable(dev, uc_pdata->suspend_on);
+ if (!ret && uc_pdata->suspend_on) {
+ ret = regulator_set_suspend_value(dev, uc_pdata->suspend_uV);
+ if (!ret)
+ return ret;
+ }
+
if (!uc_pdata->always_on && !uc_pdata->boot_on)
[PATCH v2 2/2] rockchip: rk3568: add clock driver
From: Elaine Zhang
Add rk3568 clock driver and cru structure definition.
Signed-off-by: Elaine Zhang
---
.../include/asm/arch-rockchip/cru_rk3568.h| 504 +++
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk_rk3568.c | 2959 +
3 files changed, 3464 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3568.h
create mode 100644 drivers/clk/rockchip/clk_rk3568.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
new file mode 100644
index ..6c59033f03a6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
@@ -0,0 +1,504 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3568_H
+#define _ASM_ARCH_CRU_RK3568_H
+
+#define MHz100
+#define KHz1000
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ(816 * MHz)
+#define GPLL_HZ(1188 * MHz)
+#define CPLL_HZ(1000 * MHz)
+#define PPLL_HZ(100 * MHz)
+
+/* RK3568 pll id */
+enum rk3568_pll_id {
+ APLL,
+ DPLL,
+ CPLL,
+ GPLL,
+ NPLL,
+ VPLL,
+ PPLL,
+ HPLL,
+ PLL_COUNT,
+};
+
+struct rk3568_clk_info {
+ unsigned long id;
+ char *name;
+ bool is_cru;
+};
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3568_pmuclk_priv {
+ struct rk3568_pmucru *pmucru;
+ ulong ppll_hz;
+ ulong hpll_hz;
+};
+
+struct rk3568_clk_priv {
+ struct rk3568_cru *cru;
+ struct rk3568_grf *grf;
+ ulong ppll_hz;
+ ulong hpll_hz;
+ ulong gpll_hz;
+ ulong cpll_hz;
+ ulong npll_hz;
+ ulong vpll_hz;
+ ulong armclk_hz;
+ ulong armclk_enter_hz;
+ ulong armclk_init_hz;
+ bool sync_kernel;
+ bool set_armclk_rate;
+};
+
+struct rk3568_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ unsigned int con4;
+ unsigned int reserved0[3];
+};
+
+struct rk3568_pmucru {
+ struct rk3568_pll pll[2];/* Address Offset: 0x */
+ unsigned int reserved0[16];/* Address Offset: 0x0040 */
+ unsigned int mode_con00;/* Address Offset: 0x0080 */
+ unsigned int reserved1[31];/* Address Offset: 0x0084 */
+ unsigned int pmu_clksel_con[10];/* Address Offset: 0x0100 */
+ unsigned int reserved2[22];/* Address Offset: 0x0128 */
+ unsigned int pmu_clkgate_con[3];/* Address Offset: 0x0180 */
+ unsigned int reserved3[29];/* Address Offset: 0x018C */
+ unsigned int pmu_softrst_con[1];/* Address Offset: 0x0200 */
+};
+
+check_member(rk3568_pmucru, mode_con00, 0x80);
+check_member(rk3568_pmucru, pmu_softrst_con[0], 0x200);
+
+struct rk3568_cru {
+ struct rk3568_pll pll[6];
+ unsigned int mode_con00;/* Address Offset: 0x00C0 */
+ unsigned int misc_con[3];/* Address Offset: 0x00C4 */
+ unsigned int glb_cnt_th;/* Address Offset: 0x00D0 */
+ unsigned int glb_srst_fst;/* Address Offset: 0x00D4 */
+ unsigned int glb_srsr_snd; /* Address Offset: 0x00D8 */
+ unsigned int glb_rst_con;/* Address Offset: 0x00DC */
+ unsigned int glb_rst_st;/* Address Offset: 0x00E0 */
+ unsigned int reserved0[7];/* Address Offset: 0x00E4 */
+ unsigned int clksel_con[85]; /* Address Offset: 0x0100 */
+ unsigned int reserved1[43];/* Address Offset: 0x0254 */
+ unsigned int clkgate_con[36];/* Address Offset: 0x0300 */
+ unsigned int reserved2[28]; /* Address Offset: 0x0390 */
+ unsigned int softrst_con[30];/* Address Offset: 0x0400 */
+ unsigned int reserved3[2];/* Address Offset: 0x0478 */
+ unsigned int ssgtbl[32];/* Address Offset: 0x0480 */
+ unsigned int reserved4[32];/* Address Offset: 0x0500 */
+ unsigned int sdmmc0_con[2];/* Address Offset: 0x0580 */
+ unsigned int sdmmc1_con[2];/* Address Offset: 0x058C */
+ unsigned int sdmmc2_con[2];/* Address Offset: 0x0590 */
+ unsigned int emmc_con[2];/* Address Offset: 0x0598 */
+};
+
+check_member(rk3568_cru, mode_con00, 0xc0);
+check_member(rk3568_cru, softrst_con[0], 0x400);
+
+struct pll_rate_table {
+ unsigned long rate;
+ unsigned int fbdiv;
+ unsigned int postdiv1;
+ unsigned int refdiv;
+ unsigned int postdiv2;
+ unsigned int dsmpd;
+ unsigned int frac;
+};
+
+#define RK3568_PMU_MODE0x80
+#define RK3568_PMU_PLL_CON(x) ((x) * 0x4)
+#define RK3568_PLL_CON(x) ((x) * 0x4)
+#define RK3568_MODE_CON0xc0
+
+enum {
+ /* CRU_PMU_CLK_SEL0_CON */
+ RTC32K_SEL_SHIFT= 6,
+ RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT,
+ RTC32K_SEL_PMUPVTM
[RESEND PATCH v2 1/2] rockchip: rk3568: add device tree file
From: Elaine Zhang Add dts binding header for rk3568, files origin from kernel. Signed-off-by: Elaine Zhang --- include/dt-bindings/clock/rk3568-cru.h | 925 + 1 file changed, 925 insertions(+) create mode 100644 include/dt-bindings/clock/rk3568-cru.h diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h new file mode 100644 index ..c1942422a438 --- /dev/null +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -0,0 +1,925 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H + +/* pmucru-clocks indices */ + +/* pmucru plls */ +#define PLL_PPLL 1 +#define PLL_HPLL 2 + +/* pmucru clocks */ +#define XIN_OSC0_DIV 4 +#define CLK_RTC_32K5 +#define CLK_PMU6 +#define CLK_I2C0 7 +#define CLK_RTC32K_FRAC8 +#define CLK_UART0_DIV 9 +#define CLK_UART0_FRAC 10 +#define SCLK_UART0 11 +#define DBCLK_GPIO012 +#define CLK_PWM0 13 +#define CLK_CAPTURE_PWM0_NDFT 14 +#define CLK_PMUPVTM15 +#define CLK_CORE_PMUPVTM 16 +#define CLK_REF24M 17 +#define XIN_OSC0_USBPHY0_G 18 +#define CLK_USBPHY0_REF19 +#define XIN_OSC0_USBPHY1_G 20 +#define CLK_USBPHY1_REF21 +#define XIN_OSC0_MIPIDSIPHY0_G 22 +#define CLK_MIPIDSIPHY0_REF23 +#define XIN_OSC0_MIPIDSIPHY1_G 24 +#define CLK_MIPIDSIPHY1_REF25 +#define CLK_WIFI_DIV 26 +#define CLK_WIFI_OSC0 27 +#define CLK_WIFI 28 +#define CLK_PCIEPHY0_DIV 29 +#define CLK_PCIEPHY0_OSC0 30 +#define CLK_PCIEPHY0_REF 31 +#define CLK_PCIEPHY1_DIV 32 +#define CLK_PCIEPHY1_OSC0 33 +#define CLK_PCIEPHY1_REF 34 +#define CLK_PCIEPHY2_DIV 35 +#define CLK_PCIEPHY2_OSC0 36 +#define CLK_PCIEPHY2_REF 37 +#define CLK_PCIE30PHY_REF_M38 +#define CLK_PCIE30PHY_REF_N39 +#define CLK_HDMI_REF 40 +#define XIN_OSC0_EDPPHY_G 41 +#define PCLK_PDPMU 42 +#define PCLK_PMU 43 +#define PCLK_UART0 44 +#define PCLK_I2C0 45 +#define PCLK_GPIO0 46 +#define PCLK_PMUPVTM 47 +#define PCLK_PWM0 48 +#define CLK_PDPMU 49 +#define SCLK_32K_IOE 50 + +#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_VPLL 5 +#define PLL_NPLL 6 + +/* cru clocks */ +#define CPLL_333M 9 +#define ARMCLK 10 +#define USB480M11 +#define ACLK_CORE_NIU2BUS 18 +#define CLK_CORE_PVTM 19 +#define CLK_CORE_PVTM_CORE 20 +#define CLK_CORE_PVTPLL21 +#define CLK_GPU_SRC22 +#define CLK_GPU_PRE_NDFT 23 +#define CLK_GPU_PRE_MUX24 +#define ACLK_GPU_PRE 25 +#define PCLK_GPU_PRE 26 +#define CLK_GPU27 +#define CLK_GPU_NP528 +#define PCLK_GPU_PVTM 29 +#define CLK_GPU_PVTM 30 +#define CLK_GPU_PVTM_CORE 31 +#define CLK_GPU_PVTPLL 32 +#define CLK_NPU_SRC33 +#define CLK_NPU_PRE_NDFT 34 +#define CLK_NPU35 +#define CLK_NPU_NP536 +#define HCLK_NPU_PRE 37 +#define PCLK_NPU_PRE 38 +#define ACLK_NPU_PRE 39 +#define ACLK_NPU 40 +#define HCLK_NPU 41 +#define PCLK_NPU_PVTM 42 +#define CLK_NPU_PVTM 43 +#define CLK_NPU_PVTM_CORE 44 +#define CLK_NPU_PVTPLL 45 +#define CLK_DDRPHY1X_SRC 46 +#define CLK_DDRPHY1X_HWFFC_SRC 47 +#define CLK_DDR1X 48 +#define CLK_MSCH 49 +#define CLK24_DDRMON 50 +#define ACLK_GIC_AUDIO 51 +#define HCLK_GIC_AUDIO 52 +#define HCLK_SDMMC_BUFFER 53 +#define DCLK_SDMMC_BUFFER 54 +#define ACLK_GIC60055 +#define ACLK_SPINLOCK 56 +#define HCLK_I2S0_8CH 57 +#define HCLK_I2S1_8CH 58 +#define HCLK_I2S2_2CH 59 +#define HCLK_I2S3_2CH 60 +#define CLK_I2S0_8CH_TX_SRC61 +#define CLK_I2S0_8CH_TX_FRAC 62 +#define MCLK_I2S0_8CH_TX 63 +#define I2S0_MCLKOUT_TX64 +#define CLK_I2S0_8CH_RX_SRC65 +#define CLK_I2S0_8CH_RX_FRAC 66 +#define MCLK_I2S0_8CH_RX 67 +#define I2S0_MCLKOUT_RX68 +#define CLK_I2S1_8CH_TX_SRC69 +#define CLK_I2S1_8CH_TX_FRAC 70 +#define MCLK_I2S1_8CH_TX 71 +#define I2S1_MCLKOUT_TX72 +#define CLK_I2S1_8CH_RX_SRC73 +#define
[RESEND PATCH v2 0/2] clk: rockchip: rk3568: add clock driver
From: Elaine Zhang Add basic clock for rk3568 which including cpu, bus, mmc, i2c, pwm, gmac ...clocks init. Change in V2: [PATCH v2 0/1]: No change. [PATCH v2 0/2]: update the copyright info and remove unused clock set/get. Elaine Zhang (2): rockchip: rk3568: add device tree file rockchip: rk3568: add clock driver .../include/asm/arch-rockchip/cru_rk3568.h| 504 +++ drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk_rk3568.c | 2959 + include/dt-bindings/clock/rk3568-cru.h| 925 ++ 4 files changed, 4389 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3568.h create mode 100644 drivers/clk/rockchip/clk_rk3568.c create mode 100644 include/dt-bindings/clock/rk3568-cru.h -- 2.17.1
[RESEND PATCH v2 2/2] rockchip: rk3568: add clock driver
From: Elaine Zhang
Add rk3568 clock driver and cru structure definition.
Signed-off-by: Elaine Zhang
---
.../include/asm/arch-rockchip/cru_rk3568.h| 504 +++
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk_rk3568.c | 2959 +
3 files changed, 3464 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3568.h
create mode 100644 drivers/clk/rockchip/clk_rk3568.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
new file mode 100644
index ..6c59033f03a6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
@@ -0,0 +1,504 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3568_H
+#define _ASM_ARCH_CRU_RK3568_H
+
+#define MHz100
+#define KHz1000
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ(816 * MHz)
+#define GPLL_HZ(1188 * MHz)
+#define CPLL_HZ(1000 * MHz)
+#define PPLL_HZ(100 * MHz)
+
+/* RK3568 pll id */
+enum rk3568_pll_id {
+ APLL,
+ DPLL,
+ CPLL,
+ GPLL,
+ NPLL,
+ VPLL,
+ PPLL,
+ HPLL,
+ PLL_COUNT,
+};
+
+struct rk3568_clk_info {
+ unsigned long id;
+ char *name;
+ bool is_cru;
+};
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3568_pmuclk_priv {
+ struct rk3568_pmucru *pmucru;
+ ulong ppll_hz;
+ ulong hpll_hz;
+};
+
+struct rk3568_clk_priv {
+ struct rk3568_cru *cru;
+ struct rk3568_grf *grf;
+ ulong ppll_hz;
+ ulong hpll_hz;
+ ulong gpll_hz;
+ ulong cpll_hz;
+ ulong npll_hz;
+ ulong vpll_hz;
+ ulong armclk_hz;
+ ulong armclk_enter_hz;
+ ulong armclk_init_hz;
+ bool sync_kernel;
+ bool set_armclk_rate;
+};
+
+struct rk3568_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ unsigned int con4;
+ unsigned int reserved0[3];
+};
+
+struct rk3568_pmucru {
+ struct rk3568_pll pll[2];/* Address Offset: 0x */
+ unsigned int reserved0[16];/* Address Offset: 0x0040 */
+ unsigned int mode_con00;/* Address Offset: 0x0080 */
+ unsigned int reserved1[31];/* Address Offset: 0x0084 */
+ unsigned int pmu_clksel_con[10];/* Address Offset: 0x0100 */
+ unsigned int reserved2[22];/* Address Offset: 0x0128 */
+ unsigned int pmu_clkgate_con[3];/* Address Offset: 0x0180 */
+ unsigned int reserved3[29];/* Address Offset: 0x018C */
+ unsigned int pmu_softrst_con[1];/* Address Offset: 0x0200 */
+};
+
+check_member(rk3568_pmucru, mode_con00, 0x80);
+check_member(rk3568_pmucru, pmu_softrst_con[0], 0x200);
+
+struct rk3568_cru {
+ struct rk3568_pll pll[6];
+ unsigned int mode_con00;/* Address Offset: 0x00C0 */
+ unsigned int misc_con[3];/* Address Offset: 0x00C4 */
+ unsigned int glb_cnt_th;/* Address Offset: 0x00D0 */
+ unsigned int glb_srst_fst;/* Address Offset: 0x00D4 */
+ unsigned int glb_srsr_snd; /* Address Offset: 0x00D8 */
+ unsigned int glb_rst_con;/* Address Offset: 0x00DC */
+ unsigned int glb_rst_st;/* Address Offset: 0x00E0 */
+ unsigned int reserved0[7];/* Address Offset: 0x00E4 */
+ unsigned int clksel_con[85]; /* Address Offset: 0x0100 */
+ unsigned int reserved1[43];/* Address Offset: 0x0254 */
+ unsigned int clkgate_con[36];/* Address Offset: 0x0300 */
+ unsigned int reserved2[28]; /* Address Offset: 0x0390 */
+ unsigned int softrst_con[30];/* Address Offset: 0x0400 */
+ unsigned int reserved3[2];/* Address Offset: 0x0478 */
+ unsigned int ssgtbl[32];/* Address Offset: 0x0480 */
+ unsigned int reserved4[32];/* Address Offset: 0x0500 */
+ unsigned int sdmmc0_con[2];/* Address Offset: 0x0580 */
+ unsigned int sdmmc1_con[2];/* Address Offset: 0x058C */
+ unsigned int sdmmc2_con[2];/* Address Offset: 0x0590 */
+ unsigned int emmc_con[2];/* Address Offset: 0x0598 */
+};
+
+check_member(rk3568_cru, mode_con00, 0xc0);
+check_member(rk3568_cru, softrst_con[0], 0x400);
+
+struct pll_rate_table {
+ unsigned long rate;
+ unsigned int fbdiv;
+ unsigned int postdiv1;
+ unsigned int refdiv;
+ unsigned int postdiv2;
+ unsigned int dsmpd;
+ unsigned int frac;
+};
+
+#define RK3568_PMU_MODE0x80
+#define RK3568_PMU_PLL_CON(x) ((x) * 0x4)
+#define RK3568_PLL_CON(x) ((x) * 0x4)
+#define RK3568_MODE_CON0xc0
+
+enum {
+ /* CRU_PMU_CLK_SEL0_CON */
+ RTC32K_SEL_SHIFT= 6,
+ RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT,
+ RTC32K_SEL_PMUPVTM
Re: [PATCH] phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSB
On Wed, 26 May 2021 12:48:27 +0200
Paul Kocialkowski wrote:
Hi Paul,
> Le Wed 26 May 21, 01:57, Andre Przywara a écrit :
> > From: Paul Kocialkowski
> >
> > Recent Allwinner platforms (starting with the H3) only use the MUSB
> > controller for peripheral mode and use HCI for host mode. As a result,
> > extra steps need to be taken to properly route USB signals to one or
> > the other. More precisely, the following is required:
> > * Routing the pins to either HCI/MUSB (controlled by PHY);
> > * Enabling USB PHY passby in HCI mode (controlled by PMU).
> >
> > The current code will enable passby for each PHY and reroute PHY0 to
> > MUSB, which is inconsistent and results in broken USB host support
> > for port 0.
> >
> > Passby on PHY0 must only be enabled when we want to use HCI. Since
> > host/device mode detection is not available from the PHY code and
> > because U-Boot does not support changing the mode dynamically anyway,
> > we can just mux the controller to MUSB if it is enabled and mux it to
> > HCI otherwise.
> >
> > This fixes USB host support for port 0 on platforms with PHY0 dual-route,
> > especially on boards like Pine64 (with only USB-A host ports) and
> > TV boxes without OTG ports.
> >
> > Signed-off-by: Paul Kocialkowski
> > [Andre: tweak commit message, use IS_ENABLED()]
> > Signed-off-by: Andre Przywara
> > ---
> > Hi,
> >
> > for H6 boards to work this requires a DT update (to get the <&usbphy 0>
> > links between HCI and PHY), which I will send later.
> > Tested on Pine H64, Pine64-LTS, OrangePi Zero, OrangePi PC 2, BananaPi M64,
> > BananaPi M1.
>
> Thanks for resending this, I've also had to revive this patch lately to get
> USB working on the V3 so I definitely second that it's still relevant!
Great! I had this under observation for quite a while, but was somewhat
puzzled because your original commit message mentioned that OTG was
broken, which worked fine for me. Maybe this was fixed meanwhile?
But what was still broken for me is host port 0, which disables one of
the two USB-A ports on the Pine64 boards (Pine64+, Pine64-LTS,
Pine-H64), also on those TV boxes. This makes connecting a keyboard and
an USB stick at the same time complicated.
But even with this patch alone it doesn't work, because the DTs are
(were) missing the phys property for ehci0/ohci0 (which I meanwhile
fixed in Linux, for exactly that reason). We synced the A64 DTs already
back into U-Boot, and I will send the H3/H5/H6 parts today.
So can you confirm that this now works for you, ideally with both OTG
and host ports on the same device? I tried this with enforcing OTG
on the Pine64, but would love to see reports from others.
Please respond with a Tested-by: tag then!
Thanks!
Andre
P.S. I kept your bootlin address as the author (that's what we do at
work in those cases: keep attribution to the employer sponsoring the
work at the time), please let me know if I should change this. I can add
your current address in some other tag, to have a working contact.
>
> Paul
>
> > Cheers,
> > Andre
> >
> > drivers/phy/allwinner/phy-sun4i-usb.c | 16 ++--
> > 1 file changed, 14 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> > b/drivers/phy/allwinner/phy-sun4i-usb.c
> > index 5723c980323..e6ceafc7648 100644
> > --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> > @@ -313,9 +313,21 @@ static int sun4i_usb_phy_init(struct phy *phy)
> > data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
> > }
> >
> > - sun4i_usb_phy_passby(phy, true);
> > + if (IS_ENABLED(CONFIG_USB_MUSB_SUNXI)) {
> > + /* Needed for HCI and conflicts with MUSB, keep PHY0 on MUSB */
> > + if (usb_phy->id != 0)
> > + sun4i_usb_phy_passby(phy, true);
> > +
> > + /* Route PHY0 to MUSB to allow USB gadget */
> > + if (data->cfg->phy0_dual_route)
> > + sun4i_usb_phy0_reroute(data, true);
> > + } else {
> > + sun4i_usb_phy_passby(phy, true);
> >
> > - sun4i_usb_phy0_reroute(data, true);
> > + /* Route PHY0 to HCI to allow USB host */
> > + if (data->cfg->phy0_dual_route)
> > + sun4i_usb_phy0_reroute(data, false);
> > + }
> >
> > return 0;
> > }
> > --
> > 2.17.5
> >
>
[PATCH u-boot-dm + u-boot-spi v4 00/10] Support SPI NORs and OF partitions in `mtd list`
Hello, this is v4 of patchset that adds support for U-Boot to parse MTD partitions from device-tree, and also improves support for SPI NOR access via the `mtd` command. Small rebase was needed since last version. Finally passing CI since LTO is now merged and can optimize away the code increase. CI at https://github.com/u-boot/u-boot/pull/55 Changes since v3: - rebased against current master (removed first patch, not needed anymore) - check for CONFIG_OF_CONTROL in addition to CONFIG_DM, since we are also using ofnode_* functions - match mtd's name in a separate function to make code more readable. Also add non-DM version of this name matching function, since #if macro must be used (otherwise CI will fail for configurations with disabled DM) - addressed Simon's comments about using IS_ENABLED instead of #ifdefs - added Miquel's Reviewed-by and Patrice's Tested-by to the whole series Changes since v2: - addressed Pali's comments in patch that adds partition parsing (4/7 in this version): no check for whether the `compatible` property is present in a partition node and added comment explaining mask flags) - added 4 more patches: 1) adding ofnode_get_path() function 2) printing OF path in `mtd list` 3) in `mtd read ...`, can now also be DM's device name or OF path 4) the fact from 3) is added to `mtd help` Changes since v1: - added tests of ofnode_get_addr_size_index() and ofnode_get_addr_size_index_notrans() as requested by Simon - the last patch now probes SPI NORs in both versions of mtd_probe_devices(), that is when MTDPARTS is enabled or disabled Marek Cc: Jagan Teki Cc: Priyanka Jain Cc: Simon Glass Cc: Heiko Schocher Cc: Jagan Teki Cc: Patrick Delaunay Cc: Patrice CHOTARD Cc: Miquel Raynal Marek Behún (10): dm: core: add non-translating version of ofnode_get_addr_size_index() dm: core: add ofnode_get_path() mtd: add support for parsing partitions defined in OF mtd: spi-nor: allow registering multiple MTDs when DM is enabled mtd: spi-nor: fill-in mtd->dev member mtd: remove mtd_probe() function mtd: probe SPI NOR devices in mtd_probe_devices() cmd: mtd: print device OF path in listing mtd: compare also with OF path and device name in get_mtd_device_nm() cmd: mtd: expand argument definition in command help cmd/mtd.c | 9 ++- drivers/core/ofnode.c | 44 ++- drivers/mtd/mtd-uclass.c | 15 drivers/mtd/mtd_uboot.c| 129 - drivers/mtd/mtdcore.c | 35 + drivers/mtd/mtdpart.c | 63 drivers/mtd/spi/sf_internal.h | 4 +- drivers/mtd/spi/sf_mtd.c | 19 - drivers/mtd/spi/sf_probe.c | 6 +- drivers/mtd/spi/spi-nor-core.c | 1 + drivers/mtd/spi/spi-nor-tiny.c | 1 + include/dm/ofnode.h| 27 +++ include/linux/mtd/mtd.h| 10 +++ include/mtd.h | 1 - test/dm/ofnode.c | 26 +++ 15 files changed, 315 insertions(+), 75 deletions(-) -- 2.26.3
[PATCH u-boot-dm + u-boot-spi v4 04/10] mtd: spi-nor: allow registering multiple MTDs when DM is enabled
Currently when the SPI_FLASH_MTD config option is enabled, only one SPI
can be registered as MTD at any time - it is the last one probed (since
with old non-DM model only one SPI NOR could be probed at any time).
When DM is enabled, allow for registering multiple SPI NORs as MTDs by
utilizing the nor->mtd structure, which is filled in by spi_nor_scan
anyway, instead of filling a separate struct mtd_info.
Signed-off-by: Marek Behún
Reviewed-by: Pali Rohár
Reviewed-by: Miquel Raynal
Tested-by: Patrice Chotard
Cc: Jagan Teki
Cc: Priyanka Jain
Cc: Simon Glass
Cc: Heiko Schocher
Cc: Jagan Teki
Cc: Patrick Delaunay
---
drivers/mtd/spi/sf_internal.h | 4 ++--
drivers/mtd/spi/sf_mtd.c | 18 +-
drivers/mtd/spi/sf_probe.c| 6 --
3 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 786301ba4a..0b63e1bfc2 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -81,14 +81,14 @@ int spi_flash_cmd_get_sw_write_prot(struct spi_flash
*flash);
#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
int spi_flash_mtd_register(struct spi_flash *flash);
-void spi_flash_mtd_unregister(void);
+void spi_flash_mtd_unregister(struct spi_flash *flash);
#else
static inline int spi_flash_mtd_register(struct spi_flash *flash)
{
return 0;
}
-static inline void spi_flash_mtd_unregister(void)
+static inline void spi_flash_mtd_unregister(struct spi_flash *flash)
{
}
#endif
diff --git a/drivers/mtd/spi/sf_mtd.c b/drivers/mtd/spi/sf_mtd.c
index 987fac2501..94854fbfc4 100644
--- a/drivers/mtd/spi/sf_mtd.c
+++ b/drivers/mtd/spi/sf_mtd.c
@@ -10,6 +10,20 @@
#include
#include
+#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
+
+int spi_flash_mtd_register(struct spi_flash *flash)
+{
+ return add_mtd_device(&flash->mtd);
+}
+
+void spi_flash_mtd_unregister(struct spi_flash *flash)
+{
+ del_mtd_device(&flash->mtd);
+}
+
+#else /* !CONFIG_IS_ENABLED(DM_SPI_FLASH) */
+
static struct mtd_info sf_mtd_info;
static bool sf_mtd_registered;
static char sf_mtd_name[8];
@@ -123,7 +137,7 @@ int spi_flash_mtd_register(struct spi_flash *flash)
return ret;
}
-void spi_flash_mtd_unregister(void)
+void spi_flash_mtd_unregister(struct spi_flash *flash)
{
int ret;
@@ -146,3 +160,5 @@ void spi_flash_mtd_unregister(void)
printf("Failed to unregister MTD %s and the spi_flash object is going
away: you're in deep trouble!",
sf_mtd_info.name);
}
+
+#endif /* !CONFIG_IS_ENABLED(DM_SPI_FLASH) */
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 3befbe91ca..7edb8759fd 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -84,7 +84,7 @@ struct spi_flash *spi_flash_probe(unsigned int busnum,
unsigned int cs,
void spi_flash_free(struct spi_flash *flash)
{
if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
- spi_flash_mtd_unregister();
+ spi_flash_mtd_unregister(flash);
spi_free_slave(flash->spi);
free(flash);
@@ -150,8 +150,10 @@ int spi_flash_std_probe(struct udevice *dev)
static int spi_flash_std_remove(struct udevice *dev)
{
+ struct spi_flash *flash = dev_get_uclass_priv(dev);
+
if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
- spi_flash_mtd_unregister();
+ spi_flash_mtd_unregister(flash);
return 0;
}
--
2.26.3
[PATCH u-boot-dm + u-boot-spi v4 05/10] mtd: spi-nor: fill-in mtd->dev member
Fill in mtd->dev member with nor->dev. This can be used by MTD OF partition parser. Signed-off-by: Marek Behún Reviewed-by: Pali Rohár Reviewed-by: Miquel Raynal Tested-by: Patrice Chotard Cc: Jagan Teki Cc: Priyanka Jain Cc: Simon Glass Cc: Heiko Schocher Cc: Jagan Teki Cc: Patrick Delaunay --- drivers/mtd/spi/sf_mtd.c | 1 + drivers/mtd/spi/spi-nor-core.c | 1 + drivers/mtd/spi/spi-nor-tiny.c | 1 + 3 files changed, 3 insertions(+) diff --git a/drivers/mtd/spi/sf_mtd.c b/drivers/mtd/spi/sf_mtd.c index 94854fbfc4..04de868080 100644 --- a/drivers/mtd/spi/sf_mtd.c +++ b/drivers/mtd/spi/sf_mtd.c @@ -125,6 +125,7 @@ int spi_flash_mtd_register(struct spi_flash *flash) sf_mtd_info.size = flash->size; sf_mtd_info.priv = flash; + sf_mtd_info.dev = flash->dev; /* Only uniform flash devices for now */ sf_mtd_info.numeraseregions = 0; diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index a6625535a7..6af9c675a4 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2535,6 +2535,7 @@ int spi_nor_scan(struct spi_nor *nor) if (!mtd->name) mtd->name = info->name; + mtd->dev = nor->dev; mtd->priv = nor; mtd->type = MTD_NORFLASH; mtd->writesize = 1; diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c index 1d5861d55c..b0aa97d324 100644 --- a/drivers/mtd/spi/spi-nor-tiny.c +++ b/drivers/mtd/spi/spi-nor-tiny.c @@ -751,6 +751,7 @@ int spi_nor_scan(struct spi_nor *nor) return ret; mtd->name = "spi-flash"; + mtd->dev = nor->dev; mtd->priv = nor; mtd->type = MTD_NORFLASH; mtd->writesize = 1; -- 2.26.3
[PATCH u-boot-dm + u-boot-spi v4 03/10] mtd: add support for parsing partitions defined in OF
Add support for parsing partitions defined in device-trees via the
`partitions` node with `fixed-partitions` compatible.
The `mtdparts`/`mtdids` mechanism takes precedence. If some partitions
are defined for a MTD device via this mechanism, the code won't register
partitions for that MTD device from OF, even if they are defined.
Signed-off-by: Marek Behún
Reviewed-by: Miquel Raynal
Tested-by: Patrice Chotard
Cc: Simon Glass
Cc: Heiko Schocher
Cc: Jagan Teki
Cc: Patrick Delaunay
---
drivers/mtd/mtd_uboot.c | 106 +++-
drivers/mtd/mtdpart.c | 63
include/linux/mtd/mtd.h | 10
3 files changed, 135 insertions(+), 44 deletions(-)
diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c
index c53ec657a3..4843cf1b84 100644
--- a/drivers/mtd/mtd_uboot.c
+++ b/drivers/mtd/mtd_uboot.c
@@ -198,53 +198,11 @@ static void mtd_del_all_parts(void)
} while (ret > 0);
}
-int mtd_probe_devices(void)
+static int parse_mtdparts(const char *mtdparts, const char *mtdids)
{
- static char *old_mtdparts;
- static char *old_mtdids;
- const char *mtdparts = get_mtdparts();
- const char *mtdids = get_mtdids();
- const char *mtdparts_next = mtdparts;
+ const char *mtdparts_next;
struct mtd_info *mtd;
- mtd_probe_uclass_mtd_devs();
-
- /*
-* Check if mtdparts/mtdids changed, if the MTD dev list was updated
-* or if our previous attempt to delete existing partititions failed.
-* In any of these cases we want to update the partitions, otherwise,
-* everything is up-to-date and we can return 0 directly.
-*/
- if ((!mtdparts && !old_mtdparts && !mtdids && !old_mtdids) ||
- (mtdparts && old_mtdparts && mtdids && old_mtdids &&
-!mtd_dev_list_updated() && !mtd_del_all_parts_failed &&
-!strcmp(mtdparts, old_mtdparts) &&
-!strcmp(mtdids, old_mtdids)))
- return 0;
-
- /* Update the local copy of mtdparts */
- free(old_mtdparts);
- free(old_mtdids);
- old_mtdparts = strdup(mtdparts);
- old_mtdids = strdup(mtdids);
-
- /*
-* Remove all old parts. Note that partition removal can fail in case
-* one of the partition is still being used by an MTD user, so this
-* does not guarantee that all old partitions are gone.
-*/
- mtd_del_all_parts();
-
- /*
-* Call mtd_dev_list_updated() to clear updates generated by our own
-* parts removal loop.
-*/
- mtd_dev_list_updated();
-
- /* If either mtdparts or mtdids is empty, then exit */
- if (!mtdparts || !mtdids)
- return 0;
-
/* Start the parsing by ignoring the extra 'mtdparts=' prefix, if any */
if (!strncmp(mtdparts, "mtdparts=", sizeof("mtdparts=") - 1))
mtdparts += 9;
@@ -343,6 +301,66 @@ int mtd_probe_devices(void)
put_mtd_device(mtd);
}
+ return 0;
+}
+
+int mtd_probe_devices(void)
+{
+ static char *old_mtdparts;
+ static char *old_mtdids;
+ const char *mtdparts = get_mtdparts();
+ const char *mtdids = get_mtdids();
+ struct mtd_info *mtd;
+
+ mtd_probe_uclass_mtd_devs();
+
+ /*
+* Check if mtdparts/mtdids changed, if the MTD dev list was updated
+* or if our previous attempt to delete existing partititions failed.
+* In any of these cases we want to update the partitions, otherwise,
+* everything is up-to-date and we can return 0 directly.
+*/
+ if ((!mtdparts && !old_mtdparts && !mtdids && !old_mtdids) ||
+ (mtdparts && old_mtdparts && mtdids && old_mtdids &&
+!mtd_dev_list_updated() && !mtd_del_all_parts_failed &&
+!strcmp(mtdparts, old_mtdparts) &&
+!strcmp(mtdids, old_mtdids)))
+ return 0;
+
+ /* Update the local copy of mtdparts */
+ free(old_mtdparts);
+ free(old_mtdids);
+ old_mtdparts = strdup(mtdparts);
+ old_mtdids = strdup(mtdids);
+
+ /*
+* Remove all old parts. Note that partition removal can fail in case
+* one of the partition is still being used by an MTD user, so this
+* does not guarantee that all old partitions are gone.
+*/
+ mtd_del_all_parts();
+
+ /*
+* Call mtd_dev_list_updated() to clear updates generated by our own
+* parts removal loop.
+*/
+ mtd_dev_list_updated();
+
+ /* If both mtdparts and mtdids are non-empty, parse */
+ if (mtdparts && mtdids) {
+ if (parse_mtdparts(mtdparts, mtdids) < 0)
+ printf("Failed parsing MTD partitions from
mtdparts!\n");
+ }
+
+ /* Fallback to OF partitions */
+ mtd_for_each_device(mtd) {
+ if (list_empty(&mtd->partitions)) {
+ if (add
[PATCH u-boot-dm + u-boot-spi v4 01/10] dm: core: add non-translating version of ofnode_get_addr_size_index()
Add functions ofnode_get_addr_size_index_notrans(), which is a
non-translating version of ofnode_get_addr_size_index().
Some addresses are not meant to be translated, for example those of MTD
fixed-partitions.
Signed-off-by: Marek Behún
Reviewed-by: Simon Glass
Reviewed-by: Miquel Raynal
Tested-by: Patrice Chotard
---
drivers/core/ofnode.c | 19 ---
include/dm/ofnode.h | 17 +
test/dm/ofnode.c | 5 +
3 files changed, 38 insertions(+), 3 deletions(-)
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 6c771e364f..dd34cf8ca3 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -299,7 +299,8 @@ ofnode ofnode_get_by_phandle(uint phandle)
return node;
}
-fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size)
+static fdt_addr_t __ofnode_get_addr_size_index(ofnode node, int index,
+ fdt_size_t *size, bool translate)
{
int na, ns;
@@ -319,7 +320,7 @@ fdt_addr_t ofnode_get_addr_size_index(ofnode node, int
index, fdt_size_t *size)
ns = of_n_size_cells(ofnode_to_np(node));
- if (IS_ENABLED(CONFIG_OF_TRANSLATE) && ns > 0) {
+ if (translate && IS_ENABLED(CONFIG_OF_TRANSLATE) && ns > 0) {
return of_translate_address(ofnode_to_np(node),
prop_val);
} else {
na = of_n_addr_cells(ofnode_to_np(node));
@@ -330,12 +331,24 @@ fdt_addr_t ofnode_get_addr_size_index(ofnode node, int
index, fdt_size_t *size)
ns = ofnode_read_simple_size_cells(ofnode_get_parent(node));
return fdtdec_get_addr_size_fixed(gd->fdt_blob,
ofnode_to_offset(node), "reg",
- index, na, ns, size, true);
+ index, na, ns, size,
+ translate);
}
return FDT_ADDR_T_NONE;
}
+fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size)
+{
+ return __ofnode_get_addr_size_index(node, index, size, true);
+}
+
+fdt_addr_t ofnode_get_addr_size_index_notrans(ofnode node, int index,
+ fdt_size_t *size)
+{
+ return __ofnode_get_addr_size_index(node, index, size, false);
+}
+
fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
{
fdt_size_t size;
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 8a69fd87da..e3fccb506e 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -489,6 +489,23 @@ int ofnode_read_size(ofnode node, const char *propname);
phys_addr_t ofnode_get_addr_size_index(ofnode node, int index,
fdt_size_t *size);
+/**
+ * ofnode_get_addr_size_index_notrans() - get an address/size from a node
+ * based on index, without address
+ * translation
+ *
+ * This reads the register address/size from a node based on index.
+ * The resulting address is not translated. Useful for example for on-disk
+ * addresses.
+ *
+ * @node: node to read from
+ * @index: Index of address to read (0 for first)
+ * @size: Pointer to size of the address
+ * @return address, or FDT_ADDR_T_NONE if not present or invalid
+ */
+phys_addr_t ofnode_get_addr_size_index_notrans(ofnode node, int index,
+ fdt_size_t *size);
+
/**
* ofnode_get_addr_index() - get an address from a node
*
diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c
index e0b525eeb1..9a69cf70c1 100644
--- a/test/dm/ofnode.c
+++ b/test/dm/ofnode.c
@@ -289,6 +289,11 @@ static int dm_test_ofnode_get_reg(struct unit_test_state
*uts)
ut_asserteq(FDT_ADDR_T_NONE, addr);
ut_asserteq(FDT_SIZE_T_NONE, size);
+ node = ofnode_path("/translation-test@8000/noxlatebus@3,300/dev@42");
+ ut_assert(ofnode_valid(node));
+ addr = ofnode_get_addr_size_index_notrans(node, 0, &size);
+ ut_asserteq_64(0x42, addr);
+
return 0;
}
DM_TEST(dm_test_ofnode_get_reg, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
--
2.26.3
[PATCH u-boot-dm + u-boot-spi v4 02/10] dm: core: add ofnode_get_path()
Add function for retrieving full node path of a given ofnode.
This uses np->full_name if OF is live, otherwise a call to
fdt_get_path() is made.
Signed-off-by: Marek Behún
Reviewed-by: Simon Glass
Reviewed-by: Miquel Raynal
Tested-by: Patrice Chotard
---
drivers/core/ofnode.c | 25 +
include/dm/ofnode.h | 10 ++
test/dm/ofnode.c | 21 +
3 files changed, 56 insertions(+)
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index dd34cf8ca3..eeeccfb446 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -286,6 +286,31 @@ const char *ofnode_get_name(ofnode node)
return fdt_get_name(gd->fdt_blob, ofnode_to_offset(node), NULL);
}
+int ofnode_get_path(ofnode node, char *buf, int buflen)
+{
+ assert(ofnode_valid(node));
+
+ if (ofnode_is_np(node)) {
+ if (strlen(node.np->full_name) >= buflen)
+ return -ENOSPC;
+
+ strcpy(buf, node.np->full_name);
+
+ return 0;
+ } else {
+ int res;
+
+ res = fdt_get_path(gd->fdt_blob, ofnode_to_offset(node), buf,
+ buflen);
+ if (!res)
+ return res;
+ else if (res == -FDT_ERR_NOSPACE)
+ return -ENOSPC;
+ else
+ return -EINVAL;
+ }
+}
+
ofnode ofnode_get_by_phandle(uint phandle)
{
ofnode node;
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index e3fccb506e..3da05d8b21 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -458,6 +458,16 @@ ofnode ofnode_get_parent(ofnode node);
*/
const char *ofnode_get_name(ofnode node);
+/**
+ * ofnode_get_path() - get the full path of a node
+ *
+ * @node: valid node to look up
+ * @buf: buffer to write the node path into
+ * @buflen: buffer size
+ * @return 0 if OK, -ve on error
+ */
+int ofnode_get_path(ofnode node, char *buf, int buflen);
+
/**
* ofnode_get_by_phandle() - get ofnode from phandle
*
diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c
index 9a69cf70c1..94a4d2189e 100644
--- a/test/dm/ofnode.c
+++ b/test/dm/ofnode.c
@@ -297,3 +297,24 @@ static int dm_test_ofnode_get_reg(struct unit_test_state
*uts)
return 0;
}
DM_TEST(dm_test_ofnode_get_reg, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+static int dm_test_ofnode_get_path(struct unit_test_state *uts)
+{
+ const char *path = "/translation-test@8000/noxlatebus@3,300/dev@42";
+ char buf[64];
+ ofnode node;
+ int res;
+
+ node = ofnode_path(path);
+ ut_assert(ofnode_valid(node));
+
+ res = ofnode_get_path(node, buf, 64);
+ ut_asserteq(0, res);
+ ut_asserteq_str(path, buf);
+
+ res = ofnode_get_path(node, buf, 32);
+ ut_asserteq(-ENOSPC, res);
+
+ return 0;
+}
+DM_TEST(dm_test_ofnode_get_path, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
--
2.26.3
[PATCH u-boot-dm + u-boot-spi v4 06/10] mtd: remove mtd_probe() function
The device_probe() function does the same thing as mtd_probe() and
mtd_probe() is only used in mtd_probe_uclass_mtd_devs(), where the
probing can be made simpler by using uclass_foreach_dev_probe macro.
Signed-off-by: Marek Behún
Reviewed-by: Pali Rohár
Reviewed-by: Miquel Raynal
Tested-by: Patrice Chotard
Cc: Jagan Teki
Cc: Priyanka Jain
Cc: Simon Glass
Cc: Heiko Schocher
Cc: Jagan Teki
Cc: Patrick Delaunay
---
drivers/mtd/mtd-uclass.c | 15 ---
drivers/mtd/mtd_uboot.c | 9 +++--
include/mtd.h| 1 -
3 files changed, 3 insertions(+), 22 deletions(-)
diff --git a/drivers/mtd/mtd-uclass.c b/drivers/mtd/mtd-uclass.c
index 9f5f672ba3..4ab84de553 100644
--- a/drivers/mtd/mtd-uclass.c
+++ b/drivers/mtd/mtd-uclass.c
@@ -9,21 +9,6 @@
#include
#include
-/**
- * mtd_probe - Probe the device @dev if not already done
- *
- * @dev: U-Boot device to probe
- *
- * @return 0 on success, an error otherwise.
- */
-int mtd_probe(struct udevice *dev)
-{
- if (device_active(dev))
- return 0;
-
- return device_probe(dev);
-}
-
/*
* Implement a MTD uclass which should include most flash drivers.
* The uclass private is pointed to mtd_info.
diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c
index 4843cf1b84..a652d431ba 100644
--- a/drivers/mtd/mtd_uboot.c
+++ b/drivers/mtd/mtd_uboot.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -106,13 +107,9 @@ int mtd_search_alternate_name(const char *mtdname, char
*altname,
static void mtd_probe_uclass_mtd_devs(void)
{
struct udevice *dev;
- int idx = 0;
- /* Probe devices with DM compliant drivers */
- while (!uclass_find_device(UCLASS_MTD, idx, &dev) && dev) {
- mtd_probe(dev);
- idx++;
- }
+ uclass_foreach_dev_probe(UCLASS_MTD, dev)
+ ;
}
#else
static void mtd_probe_uclass_mtd_devs(void) { }
diff --git a/include/mtd.h b/include/mtd.h
index b0f8693386..b569331edb 100644
--- a/include/mtd.h
+++ b/include/mtd.h
@@ -8,7 +8,6 @@
#include
-int mtd_probe(struct udevice *dev);
int mtd_probe_devices(void);
void board_mtdparts_default(const char **mtdids, const char **mtdparts);
--
2.26.3
[PATCH u-boot-dm + u-boot-spi v4 07/10] mtd: probe SPI NOR devices in mtd_probe_devices()
In order for `mtd list` U-Boot command to list SPI NOR devices without
the need to run `sf probe` before, we have to probe SPI NOR devices in
mtd_probe_devices().
Signed-off-by: Marek Behún
Reviewed-by: Pali Rohár
Reviewed-by: Miquel Raynal
Tested-by: Patrice Chotard
Cc: Jagan Teki
Cc: Priyanka Jain
Cc: Simon Glass
Cc: Heiko Schocher
Cc: Jagan Teki
Cc: Patrick Delaunay
---
drivers/mtd/mtd_uboot.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c
index a652d431ba..90767ec417 100644
--- a/drivers/mtd/mtd_uboot.c
+++ b/drivers/mtd/mtd_uboot.c
@@ -115,6 +115,18 @@ static void mtd_probe_uclass_mtd_devs(void)
static void mtd_probe_uclass_mtd_devs(void) { }
#endif
+#if IS_ENABLED(CONFIG_DM_SPI_FLASH) && IS_ENABLED(CONFIG_SPI_FLASH_MTD)
+static void mtd_probe_uclass_spi_nor_devs(void)
+{
+ struct udevice *dev;
+
+ uclass_foreach_dev_probe(UCLASS_SPI_FLASH, dev)
+ ;
+}
+#else
+static void mtd_probe_uclass_spi_nor_devs(void) { }
+#endif
+
#if defined(CONFIG_MTD_PARTITIONS)
#define MTDPARTS_MAXLEN 512
@@ -310,6 +322,7 @@ int mtd_probe_devices(void)
struct mtd_info *mtd;
mtd_probe_uclass_mtd_devs();
+ mtd_probe_uclass_spi_nor_devs();
/*
* Check if mtdparts/mtdids changed, if the MTD dev list was updated
@@ -370,6 +383,7 @@ int mtd_probe_devices(void)
int mtd_probe_devices(void)
{
mtd_probe_uclass_mtd_devs();
+ mtd_probe_uclass_spi_nor_devs();
return 0;
}
--
2.26.3
[PATCH u-boot-dm + u-boot-spi v4 08/10] cmd: mtd: print device OF path in listing
Print MTD's device OF path in the output of `mtd list` command.
Signed-off-by: Marek Behún
Reviewed-by: Miquel Raynal
Tested-by: Patrice Chotard
Cc: Jagan Teki
Cc: Priyanka Jain
Cc: Simon Glass
Cc: Heiko Schocher
Cc: Jagan Teki
Cc: Patrick Delaunay
---
cmd/mtd.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/cmd/mtd.c b/cmd/mtd.c
index 485a963bdd..2aabfd4d29 100644
--- a/cmd/mtd.c
+++ b/cmd/mtd.c
@@ -126,6 +126,13 @@ static void mtd_show_device(struct mtd_info *mtd)
printf(" - driver: %s\n", mtd->dev->driver->name);
}
#endif
+ if (IS_ENABLED(CONFIG_OF_CONTROL) && mtd->dev) {
+ char buf[256];
+ int res;
+
+ res = ofnode_get_path(mtd_get_ofnode(mtd), buf, 256);
+ printf(" - path: %s\n", res == 0 ? buf : "unavailable");
+ }
/* MTD device information */
printf(" - type: ");
--
2.26.3
[PATCH u-boot-dm + u-boot-spi v4 10/10] cmd: mtd: expand argument definition in command help
The argument can now also be MTD's DM device name or OF path. Mention this is command help. Signed-off-by: Marek Behún Reviewed-by: Miquel Raynal Tested-by: Patrice Chotard Cc: Jagan Teki Cc: Priyanka Jain Cc: Simon Glass Cc: Heiko Schocher Cc: Jagan Teki Cc: Patrick Delaunay --- cmd/mtd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/mtd.c b/cmd/mtd.c index 2aabfd4d29..c22478c152 100644 --- a/cmd/mtd.c +++ b/cmd/mtd.c @@ -542,7 +542,7 @@ static char mtd_help_text[] = "mtd bad \n" "\n" "With:\n" - "\t: NAND partition/chip name\n" + "\t: NAND partition/chip name (or corresponding DM device name or OF path)\n" "\t: user address from/to which data will be retrieved/stored\n" "\t: offset in in bytes (default: start of the part)\n" "\t\t* must be block-aligned for erase\n" -- 2.26.3
[PATCH u-boot-dm + u-boot-spi v4 09/10] mtd: compare also with OF path and device name in get_mtd_device_nm()
The get_mtd_device_nm() function (code imported from Linux) simply
iterates all registered MTD devices and compares the given name with
all MTDs' names.
With SPI_FLASH_MTD enabled U-Boot registers a SPI-NOR as a MTD device
with name identical to the SPI flash chip name (from SPI ID table). Thus
for a board with multiple same SPI-NORs it registers multiple MTDs, but
all with the same name (such as "s25fl164k"). We do not want to change
this behaviour, since such a change could break existing boot scripts,
which can rely on a hardcoded name.
In order to allow somehow to uniqely select a MTD device, change
get_mtd_device_nm() function as such:
- if first character of name is '/', try interpreting it as OF path
- otherwise compare the name with MTDs name and MTDs device name.
In the following example a board has two "s25fl164k" SPI-NORs. They both
have name "s25fl164k", thus cannot be uniquely selected via this name.
With this change, the user can select the second SPI-NOR either with
"spi-nor@1" or "/soc/spi@10600/spi-nor@1".
Example:
=> mtd list
List of MTD devices:
* s25fl164k
- device: spi-nor@0
- parent: spi@10600
- driver: jedec_spi_nor
- path: /soc/spi@10600/spi-nor@0
- type: NOR flash
- block size: 0x1000 bytes
- min I/O: 0x1 bytes
- 0x-0x0080 : "s25fl164k"
* s25fl164k
- device: spi-nor@1
- parent: spi@10600
- driver: jedec_spi_nor
- path: /soc/spi@10600/spi-nor@1
- type: NOR flash
- block size: 0x1000 bytes
- min I/O: 0x1 bytes
- 0x-0x0080 : "s25fl164k"
Signed-off-by: Marek Behún
Reviewed-by: Miquel Raynal
Tested-by: Patrice Chotard
Cc: Jagan Teki
Cc: Priyanka Jain
Cc: Simon Glass
Cc: Heiko Schocher
Cc: Jagan Teki
Cc: Patrick Delaunay
---
drivers/mtd/mtdcore.c | 35 +++
1 file changed, 35 insertions(+)
---
Changes since v3:
- check for CONFIG_OF_CONTROL in addition to CONFIG_DM, since we are
also using ofnode_* functions
- match mtd's name in a separate function to make code more readable.
Also add non-DM version of this name matching function, since #if
macro must be used (otherwise CI will fail for configurations with
disabled DM)
- addressed Simon's comments about using IS_ENABLED instead of #ifdefs
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index 0d1f94c6cb..582129d0df 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -768,6 +768,32 @@ int __get_mtd_device(struct mtd_info *mtd)
}
EXPORT_SYMBOL_GPL(__get_mtd_device);
+#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(OF_CONTROL)
+static bool mtd_device_matches_name(struct mtd_info *mtd, const char *name)
+{
+ struct udevice *dev = NULL;
+ bool is_part;
+
+ /*
+* If the first character of mtd name is '/', try interpreting as OF
+* path. Otherwise try comparing by mtd->name and mtd->dev->name.
+*/
+ if (*name == '/')
+ device_get_global_by_ofnode(ofnode_path(name), &dev);
+
+ is_part = mtd_is_partition(mtd);
+
+ return (!is_part && dev && mtd->dev == dev) ||
+ !strcmp(name, mtd->name) ||
+ (is_part && mtd->dev && !strcmp(name, mtd->dev->name));
+}
+#else
+static bool mtd_device_matches_name(struct mtd_info *mtd, const char *name)
+{
+ return !strcmp(name, mtd->name);
+}
+#endif
+
/**
* get_mtd_device_nm - obtain a validated handle for an MTD device by
* device name
@@ -784,10 +810,19 @@ struct mtd_info *get_mtd_device_nm(const char *name)
mutex_lock(&mtd_table_mutex);
mtd_for_each_device(other) {
+#ifdef __UBOOT__
+ if (mtd_device_matches_name(other, name)) {
+ if (mtd)
+ printf("\nWarning: MTD name \"%s\" is not
unique!\n\n",
+ name);
+ mtd = other;
+ }
+#else /* !__UBOOT__ */
if (!strcmp(name, other->name)) {
mtd = other;
break;
}
+#endif /* !__UBOOT__ */
}
if (!mtd)
--
2.26.3
Re: [PATCH] fs/squashfs: fix reading of fragmented files
Hello, Miquèl Em qua., 26 de mai. de 2021 às 04:52, Miquel Raynal < miquel.ray...@bootlin.com> escreveu: > Hi Joao, > > Joao Marcos Costa wrote on Mon, 17 May 2021 > 18:20:38 -0300: > > > The fragmented files were not correctly read because of two issues: > > > > - The squashfs_file_info struct has a field named 'comp', which tells if > > the file's fragment is compressed or not. This field was always set to > > 'true' in sqfs_get_regfile_info and sqfs_get_lregfile_info. It should > > actually take sqfs_frag_lookup's return value. This patch addresses > > these two assignments. > > > > - In sqfs_read, the fragments (compressed or not) were copied to the > > output buffer through a for loop which was reading data at the wrong > > offset. Replace these loops by equivalent calls to memcpy, with the > > right parameters. > > Good idea to get rid of these memcpy of 1 byte :) > > > I tested this patch by comparing the MD5 checksum of a few fragmented > > files with the respective md5sum output in sandbox, considering both > > compressed and uncompressed fragments. > > > > Signed-off-by: Joao Marcos Costa > > Reviewed-by: Miquel Raynal > > But next time, when you fix two issues (even if they fix the same > feature) please provide two patches ;) > > Thanks, > Miquèl > Will do! Thanks for the review! Best regards, Joao -- Atenciosamente, João Marcos Costa www.linkedin.com/in/jmarcoscosta/ https://github.com/jmarcoscosta
Re: problems with boards with CONFIG_DM disabled
On Wed, May 26, 2021 at 02:25:54AM +0200, Marek Behun wrote: > On Wed, 26 May 2021 01:27:56 +0200 > Marek Behun wrote: > > > Tom, Simon, > > > > now that LTO is merged I am working on > > Support SPI NORs and OF partitions in `mtd list` > > > > but CI fails for some boards, see > > https://github.com/u-boot/u-boot/pull/55 > > > > The reason is that there are still several boards which do not use > > CONFIG_DM. > > > > On the previous version Simon commented that I should use > > if (IS_ENABLED(...)) > > instead of > > #if > > but this does not currently work for those boards with CONFIG_DM > > disabled (struct udevice's members are not visible at all, and > > functions from dm/device.h do not exist). > > > > There are multiple possible workarounds: > > - use #if (until all boards are at CONFIG_DM) > > - create static inline versions of functions from dm/device.h returning > > failures when CONFIG_DM is not set (this would be rather big :( ) > > - wait till all those boards with CONFIG_DM disabled are removed > > - ... > > Since there is rather a large number of defconfigs with CONFIG_DM > disabled, and since the relevant code was rather complex > > if (!is_part && dev && mtd->dev == dev) || > !strcmp(name, mtd->name) || > (is_part && mtd->dev && !strcmp(name, mtd->dev->name)) > > I moved the code into a separate name matching function and for now > created a non-DM version. > > Hopefully this will be acceptable and pass CI. There's two parts to it, I suppose. First, looking at the failed build: https://dev.azure.com/u-boot/u-boot/_build/results?buildId=2297&view=logs&j=9905d24b-10d5-587f-b981-9e43e4414ee0&t=4fbb7fc6-2c55-511b-8011-58267bbd0b81&l=510 that's not a no-CONFIG_DM migration (SPL_DM is not required). Second, I wonder what it would look like on top of my WIP/make-DM_USB-fatal branch as that has removed a number of non-migrated boards. The deadline for CONFIG_DM causing removal itself is still a bit away, but that branch does remove a number of boards. -- Tom signature.asc Description: PGP signature
Re: [PATCH] net: Remove ne2000 driver
On Tue, May 25, 2021 at 11:54:41AM -0400, Tom Rini wrote: > With the last user of this driver removed, remove the driver. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: Pull request for efi-2021-07-rc4
On Tue, May 25, 2021 at 05:46:08PM +0200, Heinrich Schuchardt wrote: > Dear Tom, > > The following changes since commit e1bf0336a58cfe873a34c36ff53e5e3806f2d263: > > Prepare v2021.07-rc3 (2021-05-24 20:53:13 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-efi.git > tags/efi-2021-07-rc4 > > for you to fetch changes up to 1f6871df40d6ad94a00a2dcd46f3cc91b232c4d6: > > efi_loader: Fix -Wextra warning for EFI TCG2 (2021-05-25 14:33:22 +0200) > > > Gitlab reported no problems: > > https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/7623 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-mips
On Tue, May 25, 2021 at 04:59:55PM +0200, Daniel Schwierzeck wrote: > Hi Tom, > > please pull a minor bugfix for MIPS64 Octeon and the removal of qemu_mips > boards. > > Gitlab: > https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/7625 > > Azure: > https://dev.azure.com/danielschwierzeck/u-boot/_build/results?buildId=24&view=results > > > The following changes since commit e1bf0336a58cfe873a34c36ff53e5e3806f2d263: > > Prepare v2021.07-rc3 (2021-05-24 20:53:13 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-mips.git/ > tags/mips-pull-2021-05-25 > > for you to fetch changes up to 835b4fdf3bf5ec778e1fb7610f00707754454974: > > doc: update and fix Qemu MIPS documentation (2021-05-25 15:35:06 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 0/3] test/py: Rewrite SquashFS commands test suite
Hi, Le 24/05/2021 à 04:31, Joao Marcos Costa a écrit : Hello, This patch series fixes the following issues: - poor strategy to check if files were properly loaded - wrong quoting style for strings - tests failing at the second run because of a wrong clean-up strategy Finally, it improves: - code overall documentation level, with more comments and better naming for functions and variables - code readability by adding more helper functions - completeness: more test cases were added for both sqfsls and sqfsload commands The sqfsload new test suite may fail when testing images with fragmented files if the patch I previously sent (fs/squashfs: fix reading of fragmented files) is not applied, so this patch series depends on it. Best regards, Joao Joao Marcos Costa (3): test/py: rewrite common tools for SquashFS tests test/py: rewrite sqfsload command test suite test/py: rewrite sqfsls command test suite .../test_fs/test_squashfs/sqfs_common.py | 198 -- .../test_fs/test_squashfs/test_sqfs_load.py | 99 ++--- .../test_fs/test_squashfs/test_sqfs_ls.py | 80 +-- 3 files changed, 264 insertions(+), 113 deletions(-) Tested-by: Richard Genoud Thanks !
Re: problems with boards with CONFIG_DM disabled
On Wed, 26 May 2021 08:52:58 -0400 Tom Rini wrote: > On Wed, May 26, 2021 at 02:25:54AM +0200, Marek Behun wrote: > > On Wed, 26 May 2021 01:27:56 +0200 > > Marek Behun wrote: > > > > > Tom, Simon, > > > > > > now that LTO is merged I am working on > > > Support SPI NORs and OF partitions in `mtd list` > > > > > > but CI fails for some boards, see > > > https://github.com/u-boot/u-boot/pull/55 > > > > > > The reason is that there are still several boards which do not use > > > CONFIG_DM. > > > > > > On the previous version Simon commented that I should use > > > if (IS_ENABLED(...)) > > > instead of > > > #if > > > but this does not currently work for those boards with CONFIG_DM > > > disabled (struct udevice's members are not visible at all, and > > > functions from dm/device.h do not exist). > > > > > > There are multiple possible workarounds: > > > - use #if (until all boards are at CONFIG_DM) > > > - create static inline versions of functions from dm/device.h > > > returning failures when CONFIG_DM is not set (this would be > > > rather big :( ) > > > - wait till all those boards with CONFIG_DM disabled are removed > > > - ... > > > > Since there is rather a large number of defconfigs with CONFIG_DM > > disabled, and since the relevant code was rather complex > > > > if (!is_part && dev && mtd->dev == dev) || > > !strcmp(name, mtd->name) || > > (is_part && mtd->dev && !strcmp(name, mtd->dev->name)) > > > > I moved the code into a separate name matching function and for now > > created a non-DM version. > > > > Hopefully this will be acceptable and pass CI. > > There's two parts to it, I suppose. First, looking at the failed > build: > https://dev.azure.com/u-boot/u-boot/_build/results?buildId=2297&view=logs&j=9905d24b-10d5-587f-b981-9e43e4414ee0&t=4fbb7fc6-2c55-511b-8011-58267bbd0b81&l=510 > that's not a no-CONFIG_DM migration (SPL_DM is not required). > Second, I wonder what it would look like on top of my > WIP/make-DM_USB-fatal branch as that has removed a number of > non-migrated boards. The deadline for CONFIG_DM causing removal > itself is still a bit away, but that branch does remove a number of > boards. > I've solved this for now, hopefully in an acceptable way, check it out: https://patchwork.ozlabs.org/project/uboot/patch/20210526120826.8045-10-marek.be...@nic.cz/ look for mtd_device_matches_name, there are 2 implementations guarded by macros.
Re: [PULL] u-boot-riscv/master
On Wed, May 26, 2021 at 04:12:50PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit eb53b943be2949ca40a8e05532cd74cda058: > > Merge https://source.denx.de/u-boot/custodians/u-boot-sh (2021-05-23 > 10:15:15 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 9358576a281ab5e3b7348685bbd5f713833a5048: > > drivers: pci: pcie_dw_common: fix Werror compilation error (2021-05-24 > 23:54:54 +0800) > > Gitlab CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7620 > NAK. ERROR: fdt or initrd relocation disabled at boot time #993: FILE: include/configs/sifive-unmatched.h:65: + "fdt_high=0x\0" \ ERROR: fdt or initrd relocation disabled at boot time #994: FILE: include/configs/sifive-unmatched.h:66: + "initrd_high=0x\0" \ You can, but shouldn't disable initrd relocation. You cannot disable device tree relocation as that leads to too many issues due to misalignment later. Make use of bootm_size or similar to make sure everything is within an appropriate area of memory. Thanks. -- Tom signature.asc Description: PGP signature
[PATCH v2 1/7] arm: a37xx: pci: Don't put link into LTSSM Recovery state during probe
During our debugging of the Aardvark driver in Linux we have discovered that the PCIE_CORE_LINK_CTRL_STAT_REG register in fact controls standard PCIe Link Control Register for PCIe Root Bridge. This led us to discover that the name of the PCIE_CORE_LINK_TRAINING macro and the corresponding comment by this macro's usage is misleading; this bit in fact controls Retrain Link, which, according to PCIe base spec is defined as: A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration, re-entering Recovery is permitted but not required. Entering Recovery state is normally done from LTSSM L0, L0s and L1 states. But since the pci-aardvark.c driver enables Link Training just a few lines above, the controller is not in L0 ready state yet. So setting aardvark bit PCIE_CORE_LINK_TRAINING does not actually enter Recovery state at this place. Moreover, trying to enter LTSSM Recovery state without other configuration is causing issues for some cards (e.g. Atheros AR9xxx and QCA9xxx). Since Recovery state is not entered, these issues are not triggered. Remove code which tries to enter LTSSM Recovery state completely. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- drivers/pci/pci-aardvark.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index c43d4f309b19..06c567e236f9 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -613,11 +613,6 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) reg |= PIO_CTRL_ADDR_WIN_DISABLE; advk_writel(pcie, reg, PIO_CTRL); - /* Start link training */ - reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); - reg |= PCIE_CORE_LINK_TRAINING; - advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); - /* Wait for PCIe link up */ if (pcie_advk_wait_for_link(pcie)) return -ENXIO; -- 2.20.1
[PATCH v2 6/7] arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiB
For some configurations with more PCIe cards and PCIe bridges, 16 MiB of PCIe MEM space may not be enough. Since TF-A already allocates a 128 MiB CPU window for PCIe, and since IO port space is only 64 KiB in total, use all the remaining space (64 + 32 + 16 + 8 + 4 + 2 + 1 = 127 MiB) for PCIe MEM. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- Changes in v2: * Fix size for PCIe MEM --- arch/arm/dts/armada-37xx.dtsi | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index b7d325b40577..2615b8c748c1 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -332,10 +332,17 @@ status = "disabled"; bus-range = <0 0xff>; + /* +* The 128 MiB address range [0xe800-0xf000] is +* dedicated for PCIe and can be assigned to 8 windows +* with size a power of two. Use one 64 KiB window for +* IO at the end and the remaining seven windows +* (totaling 127 MiB) for MEM. +*/ ranges = <0x8200 0 0xe800 -0 0xe800 0 0x100 /* Port 0 MEM */ -0x8100 0 0xe900 -0 0xe900 0 0x1>; /* Port 0 IO*/ +0 0xe800 0 0x7f0 /* Port 0 MEM */ +0x8100 0 0xefff +0 0xefff 0 0x1>; /* Port 0 IO*/ }; }; }; -- 2.20.1
[PATCH v2 4/7] arm: a37xx: pci: Find PCIe controller node by compatible instead of path
Find PCIe DT node by compatible string instead of retrieving it by using
hardcoded DT path.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
arch/arm/mach-mvebu/armada3700/cpu.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c
b/arch/arm/mach-mvebu/armada3700/cpu.c
index 0cf60d7cdd7d..1abac7c9a47a 100644
--- a/arch/arm/mach-mvebu/armada3700/cpu.c
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -53,8 +53,6 @@
#define A3700_PTE_BLOCK_DEVICE \
(PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE)
-#define PCIE_PATH "/soc/pcie@d007"
-
DECLARE_GLOBAL_DATA_PTR;
static struct mm_region mvebu_mem_map[MAX_MEM_MAP_REGIONS] = {
@@ -288,7 +286,7 @@ int a3700_fdt_fix_pcie_regions(void *blob)
const u32 *ranges;
int node, len;
- node = fdt_path_offset(blob, PCIE_PATH);
+ node = fdt_node_offset_by_compatible(blob, -1,
"marvell,armada-3700-pcie");
if (node < 0)
return node;
--
2.20.1
[PATCH v2 3/7] arm: a37xx: pci: Fix DT compatible string to Linux' DT compatible
Change DT compatible string for A3700 PCIe from 'marvell,armada-37xx-pcie'
to 'marvell,armada-3700-pcie' to make U-Boot A3700 PCIe DT node compatible
with Linux' DT node.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
arch/arm/dts/armada-37xx.dtsi | 2 +-
drivers/pci/pci-aardvark.c| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index a1052add0cca..b7d325b40577 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -323,7 +323,7 @@
};
pcie0: pcie@d007 {
- compatible = "marvell,armada-37xx-pcie";
+ compatible = "marvell,armada-3700-pcie";
reg = <0 0xd007 0 0x2>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index ee81b2ea46d3..ae1a20551fed 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -717,7 +717,7 @@ static const struct dm_pci_ops pcie_advk_ops = {
};
static const struct udevice_id pcie_advk_ids[] = {
- { .compatible = "marvell,armada-37xx-pcie" },
+ { .compatible = "marvell,armada-3700-pcie" },
{ }
};
--
2.20.1
[PATCH v2 5/7] arm: a37xx: pci: Fix a3700_fdt_fix_pcie_regions() function
Current version of this function uses a lot of incorrect assumptions about
the `ranges` DT property:
* parent(#address-cells) == 2
* #size-cells == 2
* number of entries == 2
* address size of first entry == 0x100
* second child address entry == base + 0x100
Trying to increase PCIe MEM space to more than 16 MiB leads to an overlap
with PCIe IO space, and trying to define additional MEM space (as a third
entry in the `ranges` DT property) causes U-Boot to crash when booting the
kernel.
## Flattened Device Tree blob at 04f0
Booting using the fdt blob at 0x4f0
Loading Device Tree to 1fb01000, end 1fb08f12 ... OK
ERROR: board-specific fdt fixup failed:
- must RESET the board to recover.
Fix a3700_fdt_fix_pcie_regions() to properly parse and update all addresses
in the `ranges` property according to
https://elinux.org/Device_Tree_Usage#PCI_Address_Translation
Now it is possible to increase PCIe MEM space from 16 MiB to maximal value
of 127 MiB.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
Fixes: cb2ddb291ee6 ("arm64: mvebu: a37xx: add device-tree fixer for PCIe
regions")
---
arch/arm/mach-mvebu/armada3700/cpu.c | 74 ++--
1 file changed, 60 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c
b/arch/arm/mach-mvebu/armada3700/cpu.c
index 1abac7c9a47a..9aec0ce9a430 100644
--- a/arch/arm/mach-mvebu/armada3700/cpu.c
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -280,36 +281,81 @@ static u32 find_pcie_window_base(void)
return -1;
}
+static int fdt_setprop_inplace_u32_partial(void *blob, int node,
+ const char *name,
+ u32 idx, u32 val)
+{
+ val = cpu_to_fdt32(val);
+
+ return fdt_setprop_inplace_namelen_partial(blob, node, name,
+ strlen(name),
+ idx * sizeof(u32),
+ &val, sizeof(u32));
+}
+
int a3700_fdt_fix_pcie_regions(void *blob)
{
- u32 new_ranges[14], base;
+ int acells, pacells, scells;
+ u32 base, fix_offset;
const u32 *ranges;
- int node, len;
+ int node, pnode;
+ int ret, i, len;
+
+ base = find_pcie_window_base();
+ if (base == -1)
+ return -ENOENT;
node = fdt_node_offset_by_compatible(blob, -1,
"marvell,armada-3700-pcie");
if (node < 0)
return node;
ranges = fdt_getprop(blob, node, "ranges", &len);
- if (!ranges)
+ if (!ranges || len % sizeof(u32))
return -ENOENT;
- if (len != sizeof(new_ranges))
- return -EINVAL;
-
- memcpy(new_ranges, ranges, len);
+ /*
+* The "ranges" property is an array of
+* {}
+*
+* All 3 elements can span a diffent number of cells. Fetch their sizes.
+*/
+ pnode = fdt_parent_offset(blob, node);
+ acells = fdt_address_cells(blob, node);
+ pacells = fdt_address_cells(blob, pnode);
+ scells = fdt_size_cells(blob, node);
- base = find_pcie_window_base();
- if (base == -1)
+ /* Child PCI addresses always use 3 cells */
+ if (acells != 3)
return -ENOENT;
- new_ranges[2] = cpu_to_fdt32(base);
- new_ranges[4] = new_ranges[2];
+ /* Calculate fixup offset from first child address (in last cell) */
+ fix_offset = base - fdt32_to_cpu(ranges[2]);
- new_ranges[9] = cpu_to_fdt32(base + 0x100);
- new_ranges[11] = new_ranges[9];
+ /*
+* Fix address (last cell) of each child address and each parent
+* address
+*/
+ for (i = 0; i < len / sizeof(u32); i += acells + pacells + scells) {
+ int idx;
+
+ /* fix child address */
+ idx = i + acells - 1;
+ ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
+ fdt32_to_cpu(ranges[idx])
+
+ fix_offset);
+ if (ret)
+ return ret;
+
+ /* fix parent address */
+ idx = i + acells + pacells - 1;
+ ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
+ fdt32_to_cpu(ranges[idx])
+
+ fix_offset);
+ if (ret)
+ return ret;
+ }
- return fdt_setprop_inplace(blob, node, "ranges", new_ranges, len);
+ return 0;
}
void reset_cpu(void)
--
2.20.1
[PATCH v2 7/7] arm: a37xx: pci: Fix configuring PCIe resources
The `ranges` DT property of the PCIe node is currently ignored by
Aardvark driver - all entries are used as transparent PCIe MEM, despite
some of them being defined for IO in DT.
This is because the driver does not setup PCIe outbound windows and thus
a default configuration is used.
This can cause an external abort on CPU when a device driver tries to
access non-MEM space.
Setup the PCIe windows according to the `ranges` property for all
non-MEM resources (currently only IO) and also non-transparent MEM
resources.
Because Linux expects that bootloader does not setup Aardvark PCIe
windows, disable them before booting Linux.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
drivers/pci/pci-aardvark.c | 158 -
1 file changed, 157 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index ae1a20551fed..96aa039bdc26 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -99,6 +99,46 @@
#define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLEBIT(5)
#define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
+/* PCIe window configuration */
+#define OB_WIN_BASE_ADDR 0x4c00
+#define OB_WIN_BLOCK_SIZE 0x20
+#define OB_WIN_COUNT 8
+#define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
+OB_WIN_BLOCK_SIZE * (win) + \
+(offset))
+#define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
+#define OB_WIN_ENABLE BIT(0)
+#define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
+#define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
+#define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
+#define OB_WIN_MASK_LS(win)OB_WIN_REG_ADDR(win, 0x10)
+#define OB_WIN_MASK_MS(win)OB_WIN_REG_ADDR(win, 0x14)
+#define OB_WIN_ACTIONS(win)OB_WIN_REG_ADDR(win, 0x18)
+#define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1)
+ 0x4)
+#define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
+#define OB_WIN_FUNC_NUM_SHIFT 24
+#define OB_WIN_FUNC_NUM_ENABLE BIT(23)
+#define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
+#define OB_WIN_BUS_NUM_BITS_SHIFT 20
+#define OB_WIN_MSG_CODE_ENABLE BIT(22)
+#define OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
+#define OB_WIN_MSG_CODE_SHIFT 14
+#define OB_WIN_MSG_PAYLOAD_LEN BIT(12)
+#define OB_WIN_ATTR_ENABLE BIT(11)
+#define OB_WIN_ATTR_TC_MASKGENMASK(10, 8)
+#define OB_WIN_ATTR_TC_SHIFT 8
+#define OB_WIN_ATTR_RELAXEDBIT(7)
+#define OB_WIN_ATTR_NOSNOOPBIT(6)
+#define OB_WIN_ATTR_POISON BIT(5)
+#define OB_WIN_ATTR_IDOBIT(4)
+#define OB_WIN_TYPE_MASK GENMASK(3, 0)
+#define OB_WIN_TYPE_SHIFT 0
+#define OB_WIN_TYPE_MEM0x0
+#define OB_WIN_TYPE_IO 0x4
+#define OB_WIN_TYPE_CONFIG_TYPE0 0x8
+#define OB_WIN_TYPE_CONFIG_TYPE1 0x9
+#define OB_WIN_TYPE_MSG0xc
+
/* LMI registers base address and register offsets */
#define LMI_BASE_ADDR 0x6000
#define CFG_REG(LMI_BASE_ADDR + 0x0)
@@ -522,6 +562,86 @@ static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
return -ETIMEDOUT;
}
+/*
+ * Set PCIe address window register which could be used for memory
+ * mapping.
+ */
+static void pcie_advk_set_ob_win(struct pcie_advk *pcie, u8 win_num,
+phys_addr_t match, phys_addr_t remap,
+phys_addr_t mask, u32 actions)
+{
+ advk_writel(pcie, OB_WIN_ENABLE |
+ lower_32_bits(match), OB_WIN_MATCH_LS(win_num));
+ advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
+ advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
+ advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
+ advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
+ advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
+ advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
+}
+
+static void pcie_advk_disable_ob_win(struct pcie_advk *pcie, u8 win_num)
+{
+ advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
+ advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
+ advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
+ advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));
+ advk_writel(pcie, 0, OB_WIN_MASK_LS(win_
[PATCH v2 2/7] arm: a37xx: pci: Disable bus mastering when unloading driver
Disable Root Bridge I/O space, memory space and bus mastering in Aardvark's remove method, which is called before booting Linux kernel. This ensures that PCIe device which was initialized and used by U-Boot cannot do new DMA transfers until Linux initializes PCI subsystem and loads appropriate drivers for the device. During initialization of PCI subsystem Linux in fact disables this bus mastering on Root Bridge (and later enables it when driver is loaded and configured), but there is a possibility of a small window after U-Boot boots Linux when bus mastering is enabled, which is not correct. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- drivers/pci/pci-aardvark.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 06c567e236f9..ee81b2ea46d3 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -675,6 +675,12 @@ static int pcie_advk_remove(struct udevice *dev) struct pcie_advk *pcie = dev_get_priv(dev); u32 reg; + reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); + reg &= ~(PCIE_CORE_CMD_MEM_ACCESS_EN | +PCIE_CORE_CMD_IO_ACCESS_EN | +PCIE_CORE_CMD_MEM_IO_REQ_EN); + advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); + reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg &= ~LINK_TRAINING_EN; advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); -- 2.20.1
Re: [PATCH RFC 1/2] Revert "lib: introduce HASH_CALCULATE option"
On 5/24/21 9:28 PM, Alexandru Gagniuc wrote: > When we think of Kconfig, we usually think of features that we like > to enable or not. Ideally, we wouldn't use Kconfig to fix a build > issue, although sometimes it might make sense. With Kconfig it's hard > to guarantee that the fix is universal. We can only say that it works > for the set of tested configurations. In the majority of cases, it's > preferable to let the linker figure things out for us. > > The reverted commit attempted to fix a build issue by adding an > invisible Kconfig option. This is wrong in several ways: > > It invents a new Kconfig variable when CONFIG_HASH already > exists for the same purpose. > Second, hash-checksum.c makes use of the hash_progressive_lookup_algo() > symbol, which is only provided with CONFIG_HASH, but this dependency > was not expressed in the reverted patch. > > It feels like Kconfig is turning into a listing of all available > source files, and a buffet to 'select' which ones to compile. The > purpose of this revert is to enable the next change to make use of > CONFIG_HASH instead of adding to Kconfig. See upcoming patch efi_loader: add PE/COFF image measurement https://patchwork.ozlabs.org/project/uboot/patch/20210526030958.15701-2-masahisa.koj...@linaro.org/ Here we need to compile hash-checksum.o, but don't need FIT image support. Best regards Heinrich > > This reverts commit 87316da05f2fd49d3709275e64ef0c5980366ade. > > Signed-off-by: Alexandru Gagniuc > --- > common/Kconfig.boot| 1 - > lib/Kconfig| 3 --- > lib/Makefile | 2 +- > lib/efi_loader/Kconfig | 2 -- > 4 files changed, 1 insertion(+), 7 deletions(-) > > diff --git a/common/Kconfig.boot b/common/Kconfig.boot > index 3c6e77d099..89a3161f1f 100644 > --- a/common/Kconfig.boot > +++ b/common/Kconfig.boot > @@ -80,7 +80,6 @@ config FIT_SIGNATURE > select RSA_VERIFY > select IMAGE_SIGN_INFO > select FIT_FULL_CHECK > - select HASH_CALCULATE > help > This option enables signature verification of FIT uImages, > using a hash signed and verified using RSA. If > diff --git a/lib/Kconfig b/lib/Kconfig > index d675ab1d82..15019d2c65 100644 > --- a/lib/Kconfig > +++ b/lib/Kconfig > @@ -439,9 +439,6 @@ config CRC32C > config XXHASH > bool > > -config HASH_CALCULATE > - bool > - > endmenu > > menu "Compression Support" > diff --git a/lib/Makefile b/lib/Makefile > index 0835ea292c..6825671955 100644 > --- a/lib/Makefile > +++ b/lib/Makefile > @@ -61,7 +61,7 @@ endif > obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi/ > obj-$(CONFIG_$(SPL_)MD5) += md5.o > obj-$(CONFIG_$(SPL_)RSA) += rsa/ > -obj-$(CONFIG_HASH_CALCULATE) += hash-checksum.o > +obj-$(CONFIG_FIT_SIGNATURE) += hash-checksum.o > obj-$(CONFIG_SHA1) += sha1.o > obj-$(CONFIG_SHA256) += sha256.o > obj-$(CONFIG_SHA512_ALGO) += sha512.o > diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig > index eb5c4d6f29..c259abe033 100644 > --- a/lib/efi_loader/Kconfig > +++ b/lib/efi_loader/Kconfig > @@ -174,7 +174,6 @@ config EFI_CAPSULE_AUTHENTICATE > select PKCS7_MESSAGE_PARSER > select PKCS7_VERIFY > select IMAGE_SIGN_INFO > - select HASH_CALCULATE > default n > help > Select this option if you want to enable capsule > @@ -343,7 +342,6 @@ config EFI_SECURE_BOOT > select X509_CERTIFICATE_PARSER > select PKCS7_MESSAGE_PARSER > select PKCS7_VERIFY > - select HASH_CALCULATE > default n > help > Select this option to enable EFI secure boot support. >
Re: [PATCH RFC 1/2] Revert "lib: introduce HASH_CALCULATE option"
On 5/26/21 11:06 AM, Heinrich Schuchardt wrote: On 5/24/21 9:28 PM, Alexandru Gagniuc wrote: When we think of Kconfig, we usually think of features that we like to enable or not. Ideally, we wouldn't use Kconfig to fix a build issue, although sometimes it might make sense. With Kconfig it's hard to guarantee that the fix is universal. We can only say that it works for the set of tested configurations. In the majority of cases, it's preferable to let the linker figure things out for us. The reverted commit attempted to fix a build issue by adding an invisible Kconfig option. This is wrong in several ways: It invents a new Kconfig variable when CONFIG_HASH already exists for the same purpose. Second, hash-checksum.c makes use of the hash_progressive_lookup_algo() symbol, which is only provided with CONFIG_HASH, but this dependency was not expressed in the reverted patch. It feels like Kconfig is turning into a listing of all available source files, and a buffet to 'select' which ones to compile. The purpose of this revert is to enable the next change to make use of CONFIG_HASH instead of adding to Kconfig. See upcoming patch efi_loader: add PE/COFF image measurement https://patchwork.ozlabs.org/project/uboot/patch/20210526030958.15701-2-masahisa.koj...@linaro.org/ Here we need to compile hash-checksum.o, but don't need FIT image support. You can take the nest patch in this series and "select HASH". Alex Best regards Heinrich This reverts commit 87316da05f2fd49d3709275e64ef0c5980366ade. Signed-off-by: Alexandru Gagniuc --- common/Kconfig.boot| 1 - lib/Kconfig| 3 --- lib/Makefile | 2 +- lib/efi_loader/Kconfig | 2 -- 4 files changed, 1 insertion(+), 7 deletions(-) diff --git a/common/Kconfig.boot b/common/Kconfig.boot index 3c6e77d099..89a3161f1f 100644 --- a/common/Kconfig.boot +++ b/common/Kconfig.boot @@ -80,7 +80,6 @@ config FIT_SIGNATURE select RSA_VERIFY select IMAGE_SIGN_INFO select FIT_FULL_CHECK - select HASH_CALCULATE help This option enables signature verification of FIT uImages, using a hash signed and verified using RSA. If diff --git a/lib/Kconfig b/lib/Kconfig index d675ab1d82..15019d2c65 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -439,9 +439,6 @@ config CRC32C config XXHASH bool -config HASH_CALCULATE - bool - endmenu menu "Compression Support" diff --git a/lib/Makefile b/lib/Makefile index 0835ea292c..6825671955 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -61,7 +61,7 @@ endif obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi/ obj-$(CONFIG_$(SPL_)MD5) += md5.o obj-$(CONFIG_$(SPL_)RSA) += rsa/ -obj-$(CONFIG_HASH_CALCULATE) += hash-checksum.o +obj-$(CONFIG_FIT_SIGNATURE) += hash-checksum.o obj-$(CONFIG_SHA1) += sha1.o obj-$(CONFIG_SHA256) += sha256.o obj-$(CONFIG_SHA512_ALGO) += sha512.o diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index eb5c4d6f29..c259abe033 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -174,7 +174,6 @@ config EFI_CAPSULE_AUTHENTICATE select PKCS7_MESSAGE_PARSER select PKCS7_VERIFY select IMAGE_SIGN_INFO - select HASH_CALCULATE default n help Select this option if you want to enable capsule @@ -343,7 +342,6 @@ config EFI_SECURE_BOOT select X509_CERTIFICATE_PARSER select PKCS7_MESSAGE_PARSER select PKCS7_VERIFY - select HASH_CALCULATE default n help Select this option to enable EFI secure boot support.
Re: [PATCH v9 1/1] efi_loader: add PE/COFF image measurement
On 5/25/21 10:09 PM, Masahisa Kojima wrote:
"TCG PC Client Platform Firmware Profile Specification"
requires to measure every attempt to load and execute
a OS Loader(a UEFI application) into PCR[4].
This commit adds the PE/COFF image measurement, extends PCR,
and appends measurement into Event Log.
Acked-by: Ilias Apalodimas
Tested-by: Ilias Apalodimas
Signed-off-by: Masahisa Kojima
---
Changes in v9:
- use original return code from __get_active_pcr_banks()
- return EFI_UNSUPPORTED instead of EFI_INVALID_PARAMETER
if efi_image_parse() fails, it complies with TCG spec
- remove **new_efi parameter from efi_prepare_aligned_image()
to improve the readability
(no changes since v7)
Changes in v7:
- include hash-checksum.h instead of rsa.h
- select HASH_CALCULATE in Kconfig, not to update lib/Makefile
I want to remove HASH_CALCULATE for Kconfig for reasons outlined in (1):
(1)
https://patchwork.ozlabs.org/project/uboot/patch/20210524192857.1486696-2-mr.nuke...@gmail.com/
The root of the problem is that selecting SHA_xxx should compile and
link the hash_calculate() symbol, and this would make the existing
kconfig correct. Unfortunately, the selection doesn't happen
automatically because the SHA code isn't too well organized.
To solve your problem, I would prefer that you take the series in (1) --
there's a second patch after it -- and use "select HASH" here. You're
asking "What's the difference ?". The difference is that "HASH" is an
existing Kconfig symbol, so we don't need to also add "HASH_CALULATE".
Alex
- rebased the base code
Changes in v6:
- update lib/Makefile to add hash-checksum.c as a compilation target
(no changes since v2)
Changes in v2:
- Remove duplicate include
- Remove unnecessary __packed attribute
- Add all EV_EFI_* event definition
- Create common function to prepare 8-byte aligned image
- Add measurement for EV_EFI_BOOT_SERVICES_DRIVER and
EV_EFI_RUNTIME_SERVICES_DRIVER
- Use efi_search_protocol() to get device_path
- Add function comment
include/efi_loader.h | 6 +
include/efi_tcg2.h| 9 ++
include/tpm-v2.h | 18 +++
lib/efi_loader/Kconfig| 1 +
lib/efi_loader/efi_image_loader.c | 62 ++---
lib/efi_loader/efi_tcg2.c | 207 --
6 files changed, 277 insertions(+), 26 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 522696d635..0a9c82a257 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -426,6 +426,10 @@ efi_status_t efi_disk_register(void);
efi_status_t efi_rng_register(void);
/* Called by efi_init_obj_list() to install EFI_TCG2_PROTOCOL */
efi_status_t efi_tcg2_register(void);
+/* measure the pe-coff image, extend PCR and add Event Log */
+efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size,
+ struct efi_loaded_image_obj *handle,
+ struct efi_loaded_image *loaded_image_info);
/* Create handles and protocols for the partitions of a block device */
int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc,
const char *if_typename, int diskid,
@@ -886,6 +890,8 @@ bool efi_secure_boot_enabled(void);
bool efi_capsule_auth_enabled(void);
+void *efi_prepare_aligned_image(void *efi, u64 *efi_size);
+
bool efi_image_parse(void *efi, size_t len, struct efi_image_regions **regp,
WIN_CERTIFICATE **auth, size_t *auth_len);
diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h
index 40e241ce31..bcfb98168a 100644
--- a/include/efi_tcg2.h
+++ b/include/efi_tcg2.h
@@ -9,6 +9,7 @@
#if !defined _EFI_TCG2_PROTOCOL_H_
#define _EFI_TCG2_PROTOCOL_H_
+#include
#include
#define EFI_TCG2_PROTOCOL_GUID \
@@ -53,6 +54,14 @@ struct efi_tcg2_event {
u8 event[];
} __packed;
+struct uefi_image_load_event {
+ efi_physical_addr_t image_location_in_memory;
+ u64 image_length_in_memory;
+ u64 image_link_time_address;
+ u64 length_of_device_path;
+ struct efi_device_path device_path[];
+};
+
struct efi_tcg2_boot_service_capability {
u8 size;
struct efi_tcg2_version structure_version;
diff --git a/include/tpm-v2.h b/include/tpm-v2.h
index 7de7d6a57d..247b386967 100644
--- a/include/tpm-v2.h
+++ b/include/tpm-v2.h
@@ -70,6 +70,24 @@ struct udevice;
#define EV_TABLE_OF_DEVICES ((u32)0x000B)
#define EV_COMPACT_HASH ((u32)0x000C)
+/*
+ * event types, cf.
+ * "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
+ * rev 1.04, June 3, 2019
+ */
+#define EV_EFI_EVENT_BASE ((u32)0x8000)
+#define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x8001)
+#define EV_EFI_VARIABLE_BOOT ((u32)0x8002)
+#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x8003)
+#define EV_EFI_BOOT_SERVICES_DRIVER
Re: [PATCH v4] Fix flashing of eMMC user area with Fastboot
Hello Tom,
coud you please cherry-pick this patch?
Lukasz doesn't respond :(
20.05.21 18:23, Oleh Kravchenko пише:
> Hello Lukasz,
> Could you please review this patch too?
>
> This patch fixes Fastboot behaviour,
> when flashing or erasing of eMMC user area was requested.
>
> 20.05.21 18:00, Sean Anderson пише:
>>
>> On 5/20/21 10:44 AM, Oleh Kravchenko wrote:
>>> Thank you, Sean!
>>>
>>> Could you please take a look at this patch too?
>>> https://patchwork.ozlabs.org/project/uboot/patch/20210514210620.24715-1-o...@kaa.org.ua/
>> You may want to CC Lukas Majewski. I believe he took fastboot patches last
>> time they got merged.
>>
>> --Sean
>>
>>> 20.05.21 17:32, Sean Anderson пише:
On 5/19/21 6:31 AM, Oleh Kravchenko wrote:
> 'gpt' and 'mmc0' fastboot partitions have been treated as the same device,
> but it is wrong.
>
> Fill disk_partition structure with eMMC user partition info
> to properly flash data.
>
> Signed-off-by: Oleh Kravchenko
> Cc: Pantelis Antoniou
> Cc: Marek Vasut
> Cc: Sean Anderson
> Cc: Tom Rini
> ---
>
>
> Changes for v2:
> - code cleanup;
> Changes for v3:
> - QA passed at https://github.com/u-boot/u-boot/pull/75;
> Changes for v4:
> - fixed ugly code;
> - QA passed at https://github.com/u-boot/u-boot/pull/75.
>
> drivers/fastboot/fb_mmc.c | 22 +++---
> 1 file changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c
> index 2f3837e559..a009863e89 100644
> --- a/drivers/fastboot/fb_mmc.c
> +++ b/drivers/fastboot/fb_mmc.c
> @@ -512,7 +512,7 @@ void fastboot_mmc_flash_write(const char *cmd, void
> *download_buffer,
> u32 download_bytes, char *response)
> {
> struct blk_desc *dev_desc;
> - struct disk_partition info;
> + struct disk_partition info = {0};
> #ifdef CONFIG_FASTBOOT_MMC_BOOT_SUPPORT
> if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT1_NAME) == 0) {
> @@ -532,12 +532,7 @@ void fastboot_mmc_flash_write(const char *cmd, void
> *download_buffer,
> #endif
> #if CONFIG_IS_ENABLED(EFI_PARTITION)
> -#ifndef CONFIG_FASTBOOT_MMC_USER_SUPPORT
> if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) {
> -#else
> - if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0 ||
> - strcmp(cmd, CONFIG_FASTBOOT_MMC_USER_NAME) == 0) {
> -#endif
> dev_desc = fastboot_mmc_get_dev(response);
> if (!dev_desc)
> return;
> @@ -599,7 +594,20 @@ void fastboot_mmc_flash_write(const char *cmd, void
> *download_buffer,
> }
> #endif
> - if (fastboot_mmc_get_part_info(cmd, &dev_desc, &info, response) <
> 0)
> +#if CONFIG_IS_ENABLED(FASTBOOT_MMC_USER_SUPPORT)
> + if (strcmp(cmd, CONFIG_FASTBOOT_MMC_USER_NAME) == 0) {
> + dev_desc = fastboot_mmc_get_dev(response);
> + if (!dev_desc)
> + return;
> +
> + strlcpy((char *)&info.name, cmd, sizeof(info.name));
> + info.size = dev_desc->lba;
> + info.blksz = dev_desc->blksz;
> + }
> +#endif
> +
> + if (!info.name[0] &&
> + fastboot_mmc_get_part_info(cmd, &dev_desc, &info, response) < 0)
> return;
> if (is_sparse_image(download_buffer)) {
>
Reviewed-by: Sean Anderson
[scan-ad...@coverity.com: New Defects reported by Coverity Scan for Das U-Boot]
- Forwarded message from scan-ad...@coverity.com -
Date: Tue, 25 May 2021 01:05:20 + (UTC)
From: scan-ad...@coverity.com
To: tom.r...@gmail.com
Subject: New Defects reported by Coverity Scan for Das U-Boot
Hi,
Please find the latest report on new defect(s) introduced to Das U-Boot found
with Coverity Scan.
3 new defect(s) introduced to Das U-Boot found with Coverity Scan.
2 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent
build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 3 of 3 defect(s)
** CID 331856: Uninitialized variables (UNINIT)
*** CID 331856: Uninitialized variables (UNINIT)
/lib/efi_loader/efi_tcg2.c: 921 in create_specid_event()
915 spec_event->spec_version_major =
916 TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2;
917 spec_event->spec_errata =
918 TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2;
919 spec_event->uintn_size = sizeof(efi_uintn_t) / sizeof(u32);
920
>>> CID 331856: Uninitialized variables (UNINIT)
>>> Using uninitialized value "supported" when calling "tpm2_get_pcr_info".
921 err = tpm2_get_pcr_info(dev, &supported, &active,
922 &spec_event->number_of_algorithms);
923 if (err)
924 goto out;
925 if (spec_event->number_of_algorithms > MAX_HASH_COUNT ||
926 spec_event->number_of_algorithms < 1)
** CID 331855: Uninitialized variables (UNINIT)
*** CID 331855: Uninitialized variables (UNINIT)
/lib/efi_loader/efi_tcg2.c: 921 in create_specid_event()
915 spec_event->spec_version_major =
916 TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2;
917 spec_event->spec_errata =
918 TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2;
919 spec_event->uintn_size = sizeof(efi_uintn_t) / sizeof(u32);
920
>>> CID 331855: Uninitialized variables (UNINIT)
>>> Using uninitialized value "active" when calling "tpm2_get_pcr_info".
921 err = tpm2_get_pcr_info(dev, &supported, &active,
922 &spec_event->number_of_algorithms);
923 if (err)
924 goto out;
925 if (spec_event->number_of_algorithms > MAX_HASH_COUNT ||
926 spec_event->number_of_algorithms < 1)
** CID 331854: Control flow issues (NO_EFFECT)
/lib/efi_loader/efi_tcg2.c: 752 in efi_tcg2_hash_log_extend_event()
*** CID 331854: Control flow issues (NO_EFFECT)
/lib/efi_loader/efi_tcg2.c: 752 in efi_tcg2_hash_log_extend_event()
746 if (efi_tcg_event->size < efi_tcg_event->header.header_size +
747 sizeof(u32)) {
748 ret = EFI_INVALID_PARAMETER;
749 goto out;
750 }
751
>>> CID 331854: Control flow issues (NO_EFFECT)
>>> This less-than-zero comparison of an unsigned value is never true.
>>> "efi_tcg_event->header.pcr_index < 0U".
752 if (efi_tcg_event->header.pcr_index < 0 ||
753 efi_tcg_event->header.pcr_index > TPM2_MAX_PCRS) {
754 ret = EFI_INVALID_PARAMETER;
755 goto out;
756 }
757
To view the defects in Coverity Scan visit,
https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P0qcxCbhZ31OYv50yoA22WlOQ-2By3ieUvdbKmOyw68TMVT4Kip-2BBzfOGWXJ5yIiYplmPF9KAnKIja4Zd7tU-3DH9_4_EEm8SbLgSDsaDZif-2Bv7ch8WqhKpLoKErHi4nXpwDNTuOTF5O38i4jL-2BD-2FsmrMh2lPzvREHBhqI8vCJ-2BIP-2FXhAJ3irlT-2FJk2sTfzSE0n6yvc5mZv-2F1TXb3F0Ev-2FdreWwRhxjJoa-2FPZBEnX6yBmc80HGnkfFCmBlGixi3NDktrXT0unG8R8-2B-2BMnfJ5ZEf2wap1no4QCXizq5T9klMZiXxyjw-3D-3D
To manage Coverity Scan email notifications for "tom.r...@gmail.com", click
https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P0qcxCbhZ31OYv50yped04pjJnmXOsUBtKYNIXxWeIHzDeopm-2BEWQ6S6K-2FtUHv9ZTk8qZbuzkkz9sa-2BJFw4elYDyedRVZOC-2ButxjBZdouVmTGuWB6Aj6G7lm7t25-2Biv1B-2B9082pHzCCex2kqMs-3DrJM5_EEm8SbLgSDsaDZif-2Bv7ch8WqhKpLoKErHi4nXpwDNTuOTF5O38i4jL-2BD-2FsmrMh2lCbMtreDazwi5HIVw-2FInsq1UjQPSekFOErjT207tnNVPyexr3egGBVAo2ZA7Ge-2Fl7I3INbrgnTuXLIb-2FaWaodarJVao56-2BJxiYKJP-2B-2F-2FDlnIXZgenQkkpFLZvmZ4cmX1xLH9fbJ713T6bqjKF-2Fjt7HQ-3D-3D
- End forwarded message -
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH u-boot-dm + u-boot-spi v4 00/10] Support SPI NORs and OF partitions in `mtd list`
On Wed, May 26, 2021 at 5:39 PM Marek Behún wrote: > > Hello, > > this is v4 of patchset that adds support for U-Boot to parse MTD > partitions from device-tree, and also improves support for SPI NOR > access via the `mtd` command. > > Small rebase was needed since last version. > > Finally passing CI since LTO is now merged and can optimize away the > code increase. CI at https://github.com/u-boot/u-boot/pull/55 > > Changes since v3: > - rebased against current master (removed first patch, not needed > anymore) > - check for CONFIG_OF_CONTROL in addition to CONFIG_DM, since we are > also using ofnode_* functions > - match mtd's name in a separate function to make code more readable. > Also add non-DM version of this name matching function, since #if > macro must be used (otherwise CI will fail for configurations with > disabled DM) > - addressed Simon's comments about using IS_ENABLED instead of #ifdefs > - added Miquel's Reviewed-by and Patrice's Tested-by to the whole series > > Changes since v2: > - addressed Pali's comments in patch that adds partition parsing (4/7 in > this version): no check for whether the `compatible` property is > present in a partition node and added comment explaining mask flags) > - added 4 more patches: > 1) adding ofnode_get_path() function > 2) printing OF path in `mtd list` > 3) in `mtd read ...`, can now also be DM's device name > or OF path > 4) the fact from 3) is added to `mtd help` > > Changes since v1: > - added tests of ofnode_get_addr_size_index() and > ofnode_get_addr_size_index_notrans() as requested by Simon > - the last patch now probes SPI NORs in both versions of > mtd_probe_devices(), that is when MTDPARTS is enabled or disabled > > Marek > > Cc: Jagan Teki > Cc: Priyanka Jain > Cc: Simon Glass > Cc: Heiko Schocher > Cc: Jagan Teki > Cc: Patrick Delaunay > Cc: Patrice CHOTARD > Cc: Miquel Raynal > > Marek Behún (10): > dm: core: add non-translating version of ofnode_get_addr_size_index() > dm: core: add ofnode_get_path() > mtd: add support for parsing partitions defined in OF > mtd: spi-nor: allow registering multiple MTDs when DM is enabled > mtd: spi-nor: fill-in mtd->dev member > mtd: remove mtd_probe() function > mtd: probe SPI NOR devices in mtd_probe_devices() > cmd: mtd: print device OF path in listing > mtd: compare also with OF path and device name in get_mtd_device_nm() > cmd: mtd: expand argument definition in command help > > cmd/mtd.c | 9 ++- > drivers/core/ofnode.c | 44 ++- > drivers/mtd/mtd-uclass.c | 15 > drivers/mtd/mtd_uboot.c| 129 - > drivers/mtd/mtdcore.c | 35 + > drivers/mtd/mtdpart.c | 63 > drivers/mtd/spi/sf_internal.h | 4 +- > drivers/mtd/spi/sf_mtd.c | 19 - > drivers/mtd/spi/sf_probe.c | 6 +- > drivers/mtd/spi/spi-nor-core.c | 1 + > drivers/mtd/spi/spi-nor-tiny.c | 1 + > include/dm/ofnode.h| 27 +++ > include/linux/mtd/mtd.h| 10 +++ > include/mtd.h | 1 - > test/dm/ofnode.c | 26 +++ > 15 files changed, 315 insertions(+), 75 deletions(-) This series have some conflicts wrt my series about MTD UCLASS migration. Does this bypass that series? Jagan.
Re: [PATCH v9 00/28] mtd: spi-nor-core: add xSPI Octal DTR support
On Mon, May 10, 2021 at 6:50 PM Pratyush Yadav wrote: > > Jagan, > > On 05/05/21 03:11PM, Pratyush Yadav wrote: > > Hi, > > > > This series adds support for octal DTR flashes in the SPI NOR framework, > > and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA > > flashes. > > > > The Cadence QSPI controller driver is also updated to run in Octal DTR > > mode. > > > > Tested on TI J721E for MT35XU512ABA and J7200 for S28HS512T. Also tested > > on M`T25QU512A for regressions. > > Can you please pick this series up as soon as possible? It makes lots of > changes to the SPI NOR core. Let's cook this in next for a while to > catch out any issues. This would avoid surprises close to the merge > window. I have a plan to apply this to the next since it crosses the last MW. can you send the footprint statistics? I can see and then apply next on my repo to merge early MW.
Re: [PATCH] phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSB
On Wed, May 26, 2021 at 6:27 AM Andre Przywara wrote:
>
> From: Paul Kocialkowski
>
> Recent Allwinner platforms (starting with the H3) only use the MUSB
> controller for peripheral mode and use HCI for host mode. As a result,
> extra steps need to be taken to properly route USB signals to one or
> the other. More precisely, the following is required:
> * Routing the pins to either HCI/MUSB (controlled by PHY);
> * Enabling USB PHY passby in HCI mode (controlled by PMU).
>
> The current code will enable passby for each PHY and reroute PHY0 to
> MUSB, which is inconsistent and results in broken USB host support
> for port 0.
>
> Passby on PHY0 must only be enabled when we want to use HCI. Since
> host/device mode detection is not available from the PHY code and
> because U-Boot does not support changing the mode dynamically anyway,
> we can just mux the controller to MUSB if it is enabled and mux it to
> HCI otherwise.
>
> This fixes USB host support for port 0 on platforms with PHY0 dual-route,
> especially on boards like Pine64 (with only USB-A host ports) and
> TV boxes without OTG ports.
>
> Signed-off-by: Paul Kocialkowski
> [Andre: tweak commit message, use IS_ENABLED()]
> Signed-off-by: Andre Przywara
> ---
> Hi,
>
> for H6 boards to work this requires a DT update (to get the <&usbphy 0>
> links between HCI and PHY), which I will send later.
> Tested on Pine H64, Pine64-LTS, OrangePi Zero, OrangePi PC 2, BananaPi M64,
> BananaPi M1.
>
> Cheers,
> Andre
>
> drivers/phy/allwinner/phy-sun4i-usb.c | 16 ++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> b/drivers/phy/allwinner/phy-sun4i-usb.c
> index 5723c980323..e6ceafc7648 100644
> --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> @@ -313,9 +313,21 @@ static int sun4i_usb_phy_init(struct phy *phy)
> data->cfg->disc_thresh,
> PHY_DISCON_TH_LEN);
> }
>
> - sun4i_usb_phy_passby(phy, true);
> + if (IS_ENABLED(CONFIG_USB_MUSB_SUNXI)) {
I believe i did comment this before to use driver_data flag as this is
full dm driver instead of macro style.
Jagan.
IRC server access
Hey all, As you might have seen elsewhere, the Freenode IRC network is undergoing some changes. As such, I've moved over to Libera.Chat (irc.libera.chat) and updated the wiki page to note this. Thanks all. -- Tom signature.asc Description: PGP signature
[PATCH] configs: sam boards: add hash command
Add hash and hash verify commands. These would be useful for verifying copied data. Signed-off-by: Eugen Hristev --- configs/sam9x60ek_mmc_defconfig| 2 ++ configs/sam9x60ek_nandflash_defconfig | 2 ++ configs/sam9x60ek_qspiflash_defconfig | 2 ++ configs/sama5d27_som1_ek_mmc1_defconfig| 2 ++ configs/sama5d27_som1_ek_mmc_defconfig | 2 ++ configs/sama5d27_som1_ek_qspiflash_defconfig | 2 ++ configs/sama5d27_wlsom1_ek_mmc_defconfig | 2 ++ configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 2 ++ configs/sama5d2_icp_mmc_defconfig | 2 ++ configs/sama5d2_ptc_ek_mmc_defconfig | 2 ++ configs/sama5d2_ptc_ek_nandflash_defconfig | 2 ++ configs/sama5d2_xplained_emmc_defconfig| 2 ++ configs/sama5d2_xplained_mmc_defconfig | 2 ++ configs/sama5d2_xplained_qspiflash_defconfig | 2 ++ configs/sama5d2_xplained_spiflash_defconfig| 2 ++ configs/sama5d3_xplained_mmc_defconfig | 2 ++ configs/sama5d3_xplained_nandflash_defconfig | 2 ++ configs/sama5d4_xplained_mmc_defconfig | 2 ++ configs/sama5d4_xplained_nandflash_defconfig | 2 ++ configs/sama5d4_xplained_spiflash_defconfig| 2 ++ configs/sama7g5ek_mmc1_defconfig | 2 ++ configs/sama7g5ek_mmc_defconfig| 2 ++ 22 files changed, 44 insertions(+) diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig index 81d2724580..e5b5226324 100644 --- a/configs/sam9x60ek_mmc_defconfig +++ b/configs/sam9x60ek_mmc_defconfig @@ -31,6 +31,8 @@ CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig index 779b59f483..0cf940f8d7 100644 --- a/configs/sam9x60ek_nandflash_defconfig +++ b/configs/sam9x60ek_nandflash_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig index 694c74bd63..57a87a67e9 100644 --- a/configs/sam9x60ek_qspiflash_defconfig +++ b/configs/sam9x60ek_qspiflash_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index 66b5f25703..fbc07360d8 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -39,6 +39,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index b7d3b64d15..6be9cc1896 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig index 4425fa610f..2467f4041f 100644 --- a/configs/sama5d27_som1_ek_qspiflash_defconfig +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index c60d4c6be5..83901980ff 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index 44124cdf49..3cb1ff62aa 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -46,6 +46,8 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index 88d6e1f5b0..c9e82d03b8 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -41,6 +41,8 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +
Re: [PATCH] phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSB
On Wed, 26 May 2021 22:37:14 +0530
Jagan Teki wrote:
Hi Jagan,
thanks for having a look!
> On Wed, May 26, 2021 at 6:27 AM Andre Przywara wrote:
> >
> > From: Paul Kocialkowski
> >
> > Recent Allwinner platforms (starting with the H3) only use the MUSB
> > controller for peripheral mode and use HCI for host mode. As a result,
> > extra steps need to be taken to properly route USB signals to one or
> > the other. More precisely, the following is required:
> > * Routing the pins to either HCI/MUSB (controlled by PHY);
> > * Enabling USB PHY passby in HCI mode (controlled by PMU).
> >
> > The current code will enable passby for each PHY and reroute PHY0 to
> > MUSB, which is inconsistent and results in broken USB host support
> > for port 0.
> >
> > Passby on PHY0 must only be enabled when we want to use HCI. Since
> > host/device mode detection is not available from the PHY code and
> > because U-Boot does not support changing the mode dynamically anyway,
> > we can just mux the controller to MUSB if it is enabled and mux it to
> > HCI otherwise.
> >
> > This fixes USB host support for port 0 on platforms with PHY0 dual-route,
> > especially on boards like Pine64 (with only USB-A host ports) and
> > TV boxes without OTG ports.
> >
> > Signed-off-by: Paul Kocialkowski
> > [Andre: tweak commit message, use IS_ENABLED()]
> > Signed-off-by: Andre Przywara
> > ---
> > Hi,
> >
> > for H6 boards to work this requires a DT update (to get the <&usbphy 0>
> > links between HCI and PHY), which I will send later.
> > Tested on Pine H64, Pine64-LTS, OrangePi Zero, OrangePi PC 2, BananaPi M64,
> > BananaPi M1.
> >
> > Cheers,
> > Andre
> >
> > drivers/phy/allwinner/phy-sun4i-usb.c | 16 ++--
> > 1 file changed, 14 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> > b/drivers/phy/allwinner/phy-sun4i-usb.c
> > index 5723c980323..e6ceafc7648 100644
> > --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> > @@ -313,9 +313,21 @@ static int sun4i_usb_phy_init(struct phy *phy)
> > data->cfg->disc_thresh,
> > PHY_DISCON_TH_LEN);
> > }
> >
> > - sun4i_usb_phy_passby(phy, true);
> > + if (IS_ENABLED(CONFIG_USB_MUSB_SUNXI)) {
>
> I believe i did comment this before to use driver_data flag as this is
> full dm driver instead of macro style.
Which driver_data field would that be? This is not about a particular
SoC's PHY, this is about whether we use peripheral or host mode for
controller 0. As Paul mentioned in the commit message above:
"... Since host/device mode detection is not available from the PHY
code and because U-Boot does not support changing the mode dynamically
anyway, "
So a possible alternative would be to look up the dr_mode property in
the DT node. BUT: this property lives in the musb DT node, not in this
node the PHY driver knows about. Happy to take a patch that makes the
connection and looks that up. But I am not sure that covers all cases.
Meanwhile a equivalent and MUCH simpler solution is to use the Kconfig
symbol for the MUSB driver: as Paul correctly mentioned, this is a
static decision: only one of them can be effectively active in a build,
and inclusion of the MUSB driver wins over the host controller. So
using this symbol as a switch seems to be the best solution to me.
Cheers,
Andre
Re: [PATCH u-boot-dm + u-boot-spi v4 00/10] Support SPI NORs and OF partitions in `mtd list`
On Wed, 26 May 2021 22:28:34 +0530 Jagan Teki wrote: > This series have some conflicts wrt my series about MTD UCLASS > migration. Does this bypass that series? > > Jagan. Jagan, I was working on top of Tom's master branch... Are the conflicts big? Marek
[PATCH] efi_loader: Fix coverity warnings for efi tcg2 protocol
Coverity reported 3 warnings on the current code.
CID 331856, 331855, 331854 on the latest scan.
Fix the rest of the warnings by initializing the variables before
passing them to tpm2_get_pcr_info().
In order to avoid future warnings and errors initialize them to 0 within
the function as well, since the values are always OR'ed after querying the
hardware.
Signed-off-by: Ilias Apalodimas
---
lib/efi_loader/efi_tcg2.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index 39074f754772..ee743f5951fb 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -403,6 +403,9 @@ static int tpm2_get_pcr_info(struct udevice *dev, u32
*supported_pcr,
size_t i;
int tpm_ret;
+ *supported_pcr = 0;
+ *active_pcr = 0;
+ *pcr_banks = 0;
memset(response, 0, sizeof(response));
ret = tpm2_get_capability(dev, TPM2_CAP_PCRS, 0, response, 1);
if (ret)
@@ -481,7 +484,7 @@ out:
static efi_status_t __get_active_pcr_banks(u32 *active_pcr_banks)
{
struct udevice *dev;
- u32 active, supported, pcr_banks;
+ u32 active = 0, supported = 0, pcr_banks = 0;
efi_status_t ret;
int err;
@@ -900,7 +903,7 @@ static efi_status_t create_specid_event(struct udevice
*dev, void *buffer,
struct tcg_efi_spec_id_event *spec_event;
size_t spec_event_size;
efi_status_t ret = EFI_DEVICE_ERROR;
- u32 active, supported;
+ u32 active = 0, supported = 0;
int err;
size_t i;
--
2.31.1
Re: [PATCH u-boot-dm + u-boot-spi v4 00/10] Support SPI NORs and OF partitions in `mtd list`
On Wed, May 26, 2021 at 11:25 PM Marek Behún wrote: > > On Wed, 26 May 2021 22:28:34 +0530 > Jagan Teki wrote: > > > This series have some conflicts wrt my series about MTD UCLASS > > migration. Does this bypass that series? > > > > Jagan. > > Jagan, I was working on top of Tom's master branch... Are the conflicts > big? Not on master, but master with my MTD UCLASS changes in mailing list. Let me figure it out. I will update it. Jagan.
[PATCH v2] siemens: rut: disable video after DM_VIDEO conversion deadline
The board was not converted to DM_VIDEO before deadline, so disable video support for now. Signed-off-by: Anatolij Gustschin --- Changes in v2: - fix build error: undefined reference to `arch_early_init_r' configs/rut_defconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 6fc06f1ed9..2ddf0e63dd 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -31,7 +31,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_EARLY_INIT_R=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y @@ -101,10 +100,10 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0908 CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_ETHER=y -CONFIG_VIDEO=y +# CONFIG_VIDEO is not set # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_SYS_CONSOLE_BG_COL=0xff CONFIG_SYS_CONSOLE_FG_COL=0x00 CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y +# CONFIG_VIDEO_BMP_RLE8 is not set -- 2.17.1
Re: [PATCH] phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSB
On Wed, May 26, 2021 at 11:02 PM Andre Przywara wrote:
>
> On Wed, 26 May 2021 22:37:14 +0530
> Jagan Teki wrote:
>
> Hi Jagan,
>
> thanks for having a look!
>
> > On Wed, May 26, 2021 at 6:27 AM Andre Przywara
> > wrote:
> > >
> > > From: Paul Kocialkowski
> > >
> > > Recent Allwinner platforms (starting with the H3) only use the MUSB
> > > controller for peripheral mode and use HCI for host mode. As a result,
> > > extra steps need to be taken to properly route USB signals to one or
> > > the other. More precisely, the following is required:
> > > * Routing the pins to either HCI/MUSB (controlled by PHY);
> > > * Enabling USB PHY passby in HCI mode (controlled by PMU).
> > >
> > > The current code will enable passby for each PHY and reroute PHY0 to
> > > MUSB, which is inconsistent and results in broken USB host support
> > > for port 0.
> > >
> > > Passby on PHY0 must only be enabled when we want to use HCI. Since
> > > host/device mode detection is not available from the PHY code and
> > > because U-Boot does not support changing the mode dynamically anyway,
> > > we can just mux the controller to MUSB if it is enabled and mux it to
> > > HCI otherwise.
> > >
> > > This fixes USB host support for port 0 on platforms with PHY0 dual-route,
> > > especially on boards like Pine64 (with only USB-A host ports) and
> > > TV boxes without OTG ports.
> > >
> > > Signed-off-by: Paul Kocialkowski
> > > [Andre: tweak commit message, use IS_ENABLED()]
> > > Signed-off-by: Andre Przywara
> > > ---
> > > Hi,
> > >
> > > for H6 boards to work this requires a DT update (to get the <&usbphy 0>
> > > links between HCI and PHY), which I will send later.
> > > Tested on Pine H64, Pine64-LTS, OrangePi Zero, OrangePi PC 2, BananaPi
> > > M64,
> > > BananaPi M1.
> > >
> > > Cheers,
> > > Andre
> > >
> > > drivers/phy/allwinner/phy-sun4i-usb.c | 16 ++--
> > > 1 file changed, 14 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> > > b/drivers/phy/allwinner/phy-sun4i-usb.c
> > > index 5723c980323..e6ceafc7648 100644
> > > --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> > > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> > > @@ -313,9 +313,21 @@ static int sun4i_usb_phy_init(struct phy *phy)
> > > data->cfg->disc_thresh,
> > > PHY_DISCON_TH_LEN);
> > > }
> > >
> > > - sun4i_usb_phy_passby(phy, true);
> > > + if (IS_ENABLED(CONFIG_USB_MUSB_SUNXI)) {
> >
> > I believe i did comment this before to use driver_data flag as this is
> > full dm driver instead of macro style.
>
> Which driver_data field would that be? This is not about a particular
> SoC's PHY, this is about whether we use peripheral or host mode for
> controller 0. As Paul mentioned in the commit message above:
>
> "... Since host/device mode detection is not available from the PHY
> code and because U-Boot does not support changing the mode dynamically
> anyway, "
Yeah., I missed it. Thanks for pointing it out.
>
> So a possible alternative would be to look up the dr_mode property in
> the DT node. BUT: this property lives in the musb DT node, not in this
> node the PHY driver knows about. Happy to take a patch that makes the
> connection and looks that up. But I am not sure that covers all cases.
>
> Meanwhile a equivalent and MUCH simpler solution is to use the Kconfig
> symbol for the MUSB driver: as Paul correctly mentioned, this is a
> static decision: only one of them can be effectively active in a build,
> and inclusion of the MUSB driver wins over the host controller. So
> using this symbol as a switch seems to be the best solution to me.
Handling dr_mode can be possible in U-Boot, I did tried but not
completed as patch.
drivers/usb/musb-new/ti-musb.c has base code for ti musb chips.
May be supporting that would handle this case.
Jagan.
Re: [PATCH] phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSB
On Wed, 26 May 2021 23:51:41 +0530
Jagan Teki wrote:
Hi,
> On Wed, May 26, 2021 at 11:02 PM Andre Przywara
> wrote:
> >
> > On Wed, 26 May 2021 22:37:14 +0530
> > Jagan Teki wrote:
> >
> > Hi Jagan,
> >
> > thanks for having a look!
> >
> > > On Wed, May 26, 2021 at 6:27 AM Andre Przywara
> > > wrote:
> > > >
> > > > From: Paul Kocialkowski
> > > >
> > > > Recent Allwinner platforms (starting with the H3) only use the MUSB
> > > > controller for peripheral mode and use HCI for host mode. As a result,
> > > > extra steps need to be taken to properly route USB signals to one or
> > > > the other. More precisely, the following is required:
> > > > * Routing the pins to either HCI/MUSB (controlled by PHY);
> > > > * Enabling USB PHY passby in HCI mode (controlled by PMU).
> > > >
> > > > The current code will enable passby for each PHY and reroute PHY0 to
> > > > MUSB, which is inconsistent and results in broken USB host support
> > > > for port 0.
> > > >
> > > > Passby on PHY0 must only be enabled when we want to use HCI. Since
> > > > host/device mode detection is not available from the PHY code and
> > > > because U-Boot does not support changing the mode dynamically anyway,
> > > > we can just mux the controller to MUSB if it is enabled and mux it to
> > > > HCI otherwise.
> > > >
> > > > This fixes USB host support for port 0 on platforms with PHY0
> > > > dual-route,
> > > > especially on boards like Pine64 (with only USB-A host ports) and
> > > > TV boxes without OTG ports.
> > > >
> > > > Signed-off-by: Paul Kocialkowski
> > > > [Andre: tweak commit message, use IS_ENABLED()]
> > > > Signed-off-by: Andre Przywara
> > > > ---
> > > > Hi,
> > > >
> > > > for H6 boards to work this requires a DT update (to get the <&usbphy 0>
> > > > links between HCI and PHY), which I will send later.
> > > > Tested on Pine H64, Pine64-LTS, OrangePi Zero, OrangePi PC 2, BananaPi
> > > > M64,
> > > > BananaPi M1.
> > > >
> > > > Cheers,
> > > > Andre
> > > >
> > > > drivers/phy/allwinner/phy-sun4i-usb.c | 16 ++--
> > > > 1 file changed, 14 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> > > > b/drivers/phy/allwinner/phy-sun4i-usb.c
> > > > index 5723c980323..e6ceafc7648 100644
> > > > --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> > > > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> > > > @@ -313,9 +313,21 @@ static int sun4i_usb_phy_init(struct phy *phy)
> > > > data->cfg->disc_thresh,
> > > > PHY_DISCON_TH_LEN);
> > > > }
> > > >
> > > > - sun4i_usb_phy_passby(phy, true);
> > > > + if (IS_ENABLED(CONFIG_USB_MUSB_SUNXI)) {
> > >
> > > I believe i did comment this before to use driver_data flag as this is
> > > full dm driver instead of macro style.
> >
> > Which driver_data field would that be? This is not about a particular
> > SoC's PHY, this is about whether we use peripheral or host mode for
> > controller 0. As Paul mentioned in the commit message above:
> >
> > "... Since host/device mode detection is not available from the PHY
> > code and because U-Boot does not support changing the mode dynamically
> > anyway, "
>
> Yeah., I missed it. Thanks for pointing it out.
>
>
> >
> > So a possible alternative would be to look up the dr_mode property in
> > the DT node. BUT: this property lives in the musb DT node, not in this
> > node the PHY driver knows about. Happy to take a patch that makes the
> > connection and looks that up. But I am not sure that covers all cases.
> >
> > Meanwhile a equivalent and MUCH simpler solution is to use the Kconfig
> > symbol for the MUSB driver: as Paul correctly mentioned, this is a
> > static decision: only one of them can be effectively active in a build,
> > and inclusion of the MUSB driver wins over the host controller. So
> > using this symbol as a switch seems to be the best solution to me.
>
> Handling dr_mode can be possible in U-Boot, I did tried but not
> completed as patch.
> drivers/usb/musb-new/ti-musb.c has base code for ti musb chips.
Sure, there are certainly ways to do that. As I said: patches welcome!
But given that this patch here is around for 2 years now and fixes a
real problem - without any downsides, as far as I can tell - I would
rather take this first.
And while it sounds indeed cleaner to look at dr_mode, there is more to
it for it to be really useful: we probably need some form of dynamic
switching between peripheral and host mode, either by code (user calls
fastboot vs. user calls "usb reset"), or by sampling the ID pin.
And even if not, how would we deal with the case when dr_mode says
peripheral, but the MUSB driver is not compiled in?
That's why looking at CONFIG_USB_MUSB_SUNXI is actually a quite clever
and easy solution, at least for now.
Cheers,
Andre
> May be supporting that would handle this case.
>
> Jagan.
RZ/G2 USB tree question
I have a board with multiple USB controllers, but they all seem to show in index of 1 with usb tree. USB device tree: 1 Hub (5 Gb/s, 0mA) U-Boot XHCI Host Controller 1 Hub (480 Mb/s, 0mA) u-boot EHCI Host Controller 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Hub (480 Mb/s, 2mA) | +-3 Mass Storage (480 Mb/s, 200mA) |Generic Mass Storage 20621F3F | +-4 Mass Storage (480 Mb/s, 224mA) SanDisk Ultra USB 3.0 4C530001010924108332 => Is this normal behavior? I thought the different hubs would have unique numbers similar to how the devices connected to a lower hub each have unique numbers adam
[PATCH] drivers: tpm2: update reset gpio semantics
Use the more generic reset-gpios propery name.
Signed-off-by: Jorge Ramirez-Ortiz
---
doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt | 2 +-
drivers/tpm/tpm2_tis_spi.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
index 3a2ee4bd17..bbcd12950f 100644
--- a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
+++ b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
@@ -6,7 +6,7 @@ Required properties:
- reg : SPI Chip select
Optional properties:
-- gpio-reset : Reset GPIO (if not connected to the SoC reset line)
+- reset-gpios : Reset GPIO (if not connected to the SoC reset line)
- spi-max-frequency: See spi-bus.txt
Example:
diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c
index 4b33ac8fd3..94ac52d9ce 100644
--- a/drivers/tpm/tpm2_tis_spi.c
+++ b/drivers/tpm/tpm2_tis_spi.c
@@ -589,7 +589,7 @@ static int tpm_tis_spi_probe(struct udevice *dev)
if (CONFIG_IS_ENABLED(DM_GPIO)) {
struct gpio_desc reset_gpio;
- ret = gpio_request_by_name(dev, "gpio-reset", 0,
+ ret = gpio_request_by_name(dev, "reset-gpios", 0,
&reset_gpio, GPIOD_IS_OUT);
if (ret) {
log(LOGC_NONE, LOGL_NOTICE, "%s: missing reset GPIO\n",
--
2.31.1
Re: [PATCH] fastboot: Fix overflow when calculating chunk size
On Fri, Apr 16, 2021 at 05:58:21PM -0400, Sean Anderson wrote:
> If a chunk was larger than 4GiB, then chunk_data_sz would overflow and
> blkcnt would not be calculated correctly. Upgrade it to a u64 and cast
> its multiplicands as well. Also fix bytes_written while we're at it.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Heiko Schocher
> ---
>
> lib/image-sparse.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/lib/image-sparse.c b/lib/image-sparse.c
> index 187ac28cd3..52c8dcc08c 100644
> --- a/lib/image-sparse.c
> +++ b/lib/image-sparse.c
> @@ -55,10 +55,10 @@ int write_sparse_image(struct sparse_storage *info,
> lbaint_t blk;
> lbaint_t blkcnt;
> lbaint_t blks;
> - uint32_t bytes_written = 0;
> + uint64_t bytes_written = 0;
> unsigned int chunk;
> unsigned int offset;
> - unsigned int chunk_data_sz;
> + uint64_t chunk_data_sz;
> uint32_t *fill_buf = NULL;
> uint32_t fill_val;
> sparse_header_t *sparse_header;
> @@ -132,7 +132,7 @@ int write_sparse_image(struct sparse_storage *info,
>sizeof(chunk_header_t));
> }
>
> - chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz;
> + chunk_data_sz = ((u64)sparse_header->blk_sz) *
> chunk_header->chunk_sz;
> blkcnt = chunk_data_sz / info->blksz;
> switch (chunk_header->chunk_type) {
> case CHUNK_TYPE_RAW:
> @@ -162,7 +162,7 @@ int write_sparse_image(struct sparse_storage *info,
> return -1;
> }
> blk += blks;
> - bytes_written += blkcnt * info->blksz;
> + bytes_written += ((u64)blkcnt) * info->blksz;
> total_blocks += chunk_header->chunk_sz;
> data += chunk_data_sz;
> break;
> @@ -222,7 +222,7 @@ int write_sparse_image(struct sparse_storage *info,
> blk += blks;
> i += j;
> }
> - bytes_written += blkcnt * info->blksz;
> + bytes_written += ((u64)blkcnt) * info->blksz;
> total_blocks += chunk_data_sz / sparse_header->blk_sz;
> free(fill_buf);
> break;
> @@ -253,7 +253,7 @@ int write_sparse_image(struct sparse_storage *info,
>
> debug("Wrote %d blocks, expected to write %d blocks\n",
> total_blocks, sparse_header->total_blks);
> - printf(" wrote %u bytes to '%s'\n", bytes_written, part_name);
> + printf(" wrote %llu bytes to '%s'\n", bytes_written, part_name);
>
> if (total_blocks != sparse_header->total_blks) {
> info->mssg("sparse image write failure", response);
This results in things like:
pico-dwarf-imx7d: all +506 bss +48 rodata +2 text +456
u-boot: add: 1/0, grow: 1/0 bytes: 452/0 (452)
function old new delta
__aeabi_uldivmod - 392+392
write_sparse_image 712 772 +60
Which I believe means that some of the division above needs to be
converted to use do_div(). Since I can't easily confirm the changes,
can you please check in to it? Thanks.
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH v5 0/6] power: pmic: support more PMIC
Hi, On 5/26/21 5:46 PM, ela...@denx.de wrote: > From: Elaine Zhang > > Support more PMIC and improve compatibility between pmics. I didn't see your full patchset, except [PATCH V5 1/6]. If i missed something, let me know, plz. Best Regards, Jaehoon Chung > > Change in V5: > [PATCH v5 1/6]: Fixed test case run error. > [PATCH v5 2/6]: Resolve compile warning. > [PATCH v5 3/6]: No change. > [PATCH v5 4/6]: No change. > [PATCH v5 5/6]: No change. > [PATCH v5 6/6]: No change. > > Change in V4: > [PATCH v4 1/6]: No change. > [PATCH v4 2/6]: No change. > [PATCH v4 3/6]: No change. > [PATCH v4 4/6]: No change. > [PATCH v4 5/6]: Resolve code conflicts after ptach v3 5/8 and 6/8 deletion.. > [PATCH v4 6/6]: Resolve code conflicts after ptach v3 5/8 and 6/8 deletion. > Remove [PATCH v3 5/8] and [PATCH v3 6/8], There is no application scenario. > > Change in V3: > [PATCH v3 1/8]: Add document instructions, Correct error handling. > [PATCH v3 2/8]: No change. > [PATCH v3 3/8]: No change. > [PATCH v3 4/8]: No change. > [PATCH v3 5/8]: Update commit message. > [PATCH v3 6/8]: Update commit message. > [PATCH v3 7/8]: No change. > [PATCH v3 8/8]: No change. > > Change in V2: > [PATCH v2 1/8]: Add regulator suspend volatge and en/disable test. > [PATCH v2 2/8]: Split the [PATCH v1 2/7], rk808 and rk818 updates. > [PATCH v2 3/8]: Split the [PATCH v1 2/7], support rk816 pmic and update > commit message. > [PATCH v2 4/8]: Update commit message. > [PATCH v2 5/8]: No change. > [PATCH v2 6/8]: No change. > [PATCH v2 7/8]: Remove rk809 keywords and update commit message. > [PATCH v2 8/8]: Update commit message. > > Elaine Zhang (3): > power: regulator: rk8xx: update the driver for rk808 and rk818 > power: pmic: rk816: support rk816 pmic > power: pmic: rk805: support rk805 pmic > > Joseph Chen (3): > dm: regulator: support regulator more state > power: pmic: rk817: support rk817 pmic > power: pmic: rk809: support rk809 pmic > > doc/device-tree-bindings/regulator/regulator.txt | 27 + > drivers/power/pmic/rk8xx.c | 89 ++- > drivers/power/regulator/regulator-uclass.c | 70 ++ > drivers/power/regulator/rk8xx.c | 939 > +-- > include/power/regulator.h| 64 ++ > include/power/rk8xx_pmic.h | 42 + > test/dm/regulator.c | 57 ++ > 7 files changed, 1200 insertions(+), 88 deletions(-) >
Re: [PATCH v5 1/6] dm: regulator: support regulator more state
Hi,
On 5/26/21 5:46 PM, ela...@denx.de wrote:
> From: Joseph Chen
Is it right patch? This patch had been already applied.
Best Regards,
Jaehoon Chung
>
> support parse regulator standard property:
> regulator-off-in-suspend;
> regulator-init-microvolt;
> regulator-suspend-microvolt:
> regulator_get_suspend_enable
> regulator_set_suspend_enable
> regulator_get_suspend_value
> regulator_set_suspend_value
>
> Signed-off-by: Joseph Chen
> Signed-off-by: Elaine Zhang
> Reviewed-by: Kever Yang
> ---
> doc/device-tree-bindings/regulator/regulator.txt | 27 +
> drivers/power/regulator/regulator-uclass.c | 70
>
> include/power/regulator.h| 64 ++
> test/dm/regulator.c | 57 +++
> 4 files changed, 218 insertions(+)
>
> diff --git a/doc/device-tree-bindings/regulator/regulator.txt
> b/doc/device-tree-bindings/regulator/regulator.txt
> index 4ba642b7c77f..6c9a02120fde 100644
> --- a/doc/device-tree-bindings/regulator/regulator.txt
> +++ b/doc/device-tree-bindings/regulator/regulator.txt
> @@ -36,6 +36,28 @@ Optional properties:
> - regulator-always-on: regulator should never be disabled
> - regulator-boot-on: enabled by bootloader/firmware
> - regulator-ramp-delay: ramp delay for regulator (in uV/us)
> +- regulator-init-microvolt: a init allowed Voltage value
> +- regulator-state-(standby|mem|disk)
> + type: object
> + description:
> +sub-nodes for regulator state in Standby, Suspend-to-RAM, and
> +Suspend-to-DISK modes. Equivalent with standby, mem, and disk Linux
> +sleep states.
> +
> +properties:
> + regulator-on-in-suspend:
> +description: regulator should be on in suspend state.
> +type: boolean
> +
> + regulator-off-in-suspend:
> +description: regulator should be off in suspend state.
> +type: boolean
> +
> + regulator-suspend-microvolt:
> +description: the default voltage which regulator would be set in
> + suspend. This property is now deprecated, instead setting voltage
> + for suspend mode via the API which regulator driver provides is
> + recommended.
>
> Note
> The "regulator-name" constraint is used for setting the device's uclass
> @@ -59,7 +81,12 @@ ldo0 {
> regulator-max-microvolt = <180>;
> regulator-min-microamp = <10>;
> regulator-max-microamp = <10>;
> + regulator-init-microvolt = <180>;
> regulator-always-on;
> regulator-boot-on;
> regulator-ramp-delay = <12000>;
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <180>;
> + };
> };
> diff --git a/drivers/power/regulator/regulator-uclass.c
> b/drivers/power/regulator/regulator-uclass.c
> index 76be95bcd159..4986c87e7ba6 100644
> --- a/drivers/power/regulator/regulator-uclass.c
> +++ b/drivers/power/regulator/regulator-uclass.c
> @@ -77,6 +77,33 @@ int regulator_set_value(struct udevice *dev, int uV)
> return ret;
> }
>
> +int regulator_set_suspend_value(struct udevice *dev, int uV)
> +{
> + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
> + struct dm_regulator_uclass_platdata *uc_pdata;
> +
> + uc_pdata = dev_get_uclass_platdata(dev);
> + if (uc_pdata->min_uV != -ENODATA && uV < uc_pdata->min_uV)
> + return -EINVAL;
> + if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV)
> + return -EINVAL;
> +
> + if (!ops->set_suspend_value)
> + return -ENOSYS;
> +
> + return ops->set_suspend_value(dev, uV);
> +}
> +
> +int regulator_get_suspend_value(struct udevice *dev)
> +{
> + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
> +
> + if (!ops->get_suspend_value)
> + return -ENOSYS;
> +
> + return ops->get_suspend_value(dev);
> +}
> +
> /*
> * To be called with at most caution as there is no check
> * before setting the actual voltage value.
> @@ -170,6 +197,26 @@ int regulator_set_enable_if_allowed(struct udevice *dev,
> bool enable)
> return ret;
> }
>
> +int regulator_set_suspend_enable(struct udevice *dev, bool enable)
> +{
> + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
> +
> + if (!ops->set_suspend_enable)
> + return -ENOSYS;
> +
> + return ops->set_suspend_enable(dev, enable);
> +}
> +
> +int regulator_get_suspend_enable(struct udevice *dev)
> +{
> + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
> +
> + if (!ops->get_suspend_enable)
> + return -ENOSYS;
> +
> + return ops->get_suspend_enable(dev);
> +}
> +
> int regulator_get_mode(struct udevice *dev)
> {
> const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
> @@ -235,6 +282,14 @@ int regulator_autoset(struct udevice *dev)
> int ret = 0;
>
> uc_pdata = dev_get_uclass_pla
Re: [PATCH v2 3/6] clk: sunxi: v3s: fix tabs / spaces
On Sun, 23 May 2021 01:17:29 +0200
Andreas Rehn wrote:
> align CLK_USB_PHY0 with tabs
>
> Signed-off-by: Andreas Rehn
Reviewed-by: Andre Przywara
Cheers,
Andre
P.S. Please send a whole v2 series next time, to make this easier to
sort out which patch still applies and which not.
> ---
> Changes in v2:
> - revert CLK_SPI0 extra tab
>
> drivers/clk/sunxi/clk_v3s.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
> index 55fc597043..bc6b7b4870 100644
> --- a/drivers/clk/sunxi/clk_v3s.c
> +++ b/drivers/clk/sunxi/clk_v3s.c
> @@ -29,7 +29,7 @@ static struct ccu_clk_gate v3s_gates[] = {
>
> [CLK_SPI0] = GATE(0x0a0, BIT(31)),
>
> - [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
> + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
> };
>
> static struct ccu_reset v3s_resets[] = {
Re: [PATCH v2 4/6] net: sun8i-emac: add v3s variant
On Sun, 23 May 2021 01:22:38 +0200
Andreas Rehn wrote:
Hi,
> Add variant V3S_EMAC.
> Handle pinmux compile time error by skipping goio setup, because
> V3s uses internal phy and don't expose pins.
>
> Signed-off-by: Andreas Rehn
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> Changes in v2:
> - skip pinmux and add proper description
> - Add V3S variant add it to compatible list
> - Skip (R)GMII flags and handle sun8i_handle_internal_phy
>
> drivers/net/sun8i_emac.c | 15 ---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> index 5a1b38bf80..ab9f61994c 100644
> --- a/drivers/net/sun8i_emac.c
> +++ b/drivers/net/sun8i_emac.c
> @@ -145,6 +145,7 @@ enum emac_variant {
> A64_EMAC,
> R40_GMAC,
> H6_EMAC,
> + V3S_EMAC,
> };
>
> struct emac_dma_desc {
> @@ -303,7 +304,7 @@ static void sun8i_adjust_link(struct emac_eth_dev *priv,
> static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
> {
> if (priv->use_internal_phy) {
> - /* H3 based SoC's that has an Internal 100MBit PHY
> + /* H3 and V3s based SoC's that has an Internal 100MBit PHY
>* needs to be configured and powered up before use
> */
> reg &= ~H3_EPHY_DEFAULT_MASK;
> @@ -354,7 +355,8 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata
> *pdata,
> case PHY_INTERFACE_MODE_RGMII_ID:
> case PHY_INTERFACE_MODE_RGMII_RXID:
> case PHY_INTERFACE_MODE_RGMII_TXID:
> - reg |= SC_EPIT | SC_ETCS_INT_GMII;
> + if (priv->variant != V3S_EMAC)
> + reg |= SC_EPIT | SC_ETCS_INT_GMII;
> break;
> case PHY_INTERFACE_MODE_RMII:
> if (priv->variant == H3_EMAC ||
> @@ -566,6 +568,10 @@ static int parse_phy_pins(struct udevice *dev)
> iomux = SUN8I_IOMUX;
> else if (IS_ENABLED(CONFIG_MACH_SUN50I))
> iomux = SUN8I_IOMUX;
> + else if (IS_ENABLED(CONFIG_MACH_SUN8I_V3S))
> + // V3s does not expose any MAC pins,
> + // but case is required to handle BUILD_BUG_ON_MSG.
> + return 0;
> else
> BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
>
> @@ -956,7 +962,8 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
> return -EINVAL;
> }
>
> - if (priv->variant == H3_EMAC) {
> + if (priv->variant == H3_EMAC ||
> + priv->variant == V3S_EMAC) {
> ret = sun8i_handle_internal_phy(dev, priv);
> if (ret)
> return ret;
> @@ -1009,6 +1016,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = {
> .data = (uintptr_t)R40_GMAC },
> {.compatible = "allwinner,sun50i-h6-emac",
> .data = (uintptr_t)H6_EMAC },
> + {.compatible = "allwinner,sun8i-v3s-emac",
> + .data = (uintptr_t)V3S_EMAC },
> { }
> };
>
Re: [PATCH v2] sunxi: clock: H6/H616: Fix PLL clock factor encodings
On Wed, 5 May 2021 13:53:05 +0100
Andre Przywara wrote:
Hi,
> Most clock factors and dividers in the H6 PLLs use a "+1 encoding",
> which we were missing on two occasions.
can someone please confirm that I didn't mess this up?
Cheers,
Andre
>
> This fixes the MMC clock setup on the H6, which could be slightly off due
> to the wrong parent frequency:
> mmc 2 set mod-clk req 5200 parent 117600 n 2 m 12 rate 4900
>
> Also the CPU frequency was a tad too high before.
>
> Signed-off-by: Andre Przywara
> ---
> Changelog v1 .. v2:
> - Also fix PLL5 factor calculation (video, currently unused)
> - Also fix PLL1 factor calculation (CPU clock)
>
> arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 4 ++--
> arch/arm/mach-sunxi/clock_sun50i_h6.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
> b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
> index 62abfc4ef6b..2e076cf594d 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
> @@ -233,14 +233,14 @@ struct sunxi_ccm_reg {
> #define CCM_PLL1_OUT_EN BIT(27)
> #define CCM_PLL1_CLOCK_TIME_2(2 << 24)
> #define CCM_PLL1_CTRL_P(p) ((p) << 16)
> -#define CCM_PLL1_CTRL_N(n) ((n) << 8)
> +#define CCM_PLL1_CTRL_N(n) (((n) - 1) << 8)
>
> /* pll5 bit field */
> #define CCM_PLL5_CTRL_EN BIT(31)
> #define CCM_PLL5_LOCK_EN BIT(29)
> #define CCM_PLL5_LOCKBIT(28)
> #define CCM_PLL5_OUT_EN BIT(27)
> -#define CCM_PLL5_CTRL_N(n) ((n) << 8)
> +#define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8)
> #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0)
> #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1)
>
> diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c
> b/arch/arm/mach-sunxi/clock_sun50i_h6.c
> index 492fc4a3fca..a947463e0a5 100644
> --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
> +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
> @@ -94,7 +94,7 @@ unsigned int clock_get_pll6(void)
> int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2;
>
> uint32_t rval = readl(&ccm->pll6_cfg);
> - int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
> + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
> int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
> CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
> int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
Re: [PATCH] MAINTAINERS: Add allwinner/sunxi driver directories
On Wed, 21 Apr 2021 11:58:47 +0100 Andre Przywara wrote: Simon, Tom, > On Sun, 18 Apr 2021 22:13:36 -0500 > Samuel Holland wrote: > > > These drivers are sunxi platform-specific, and so are of interest to the > > sunxi maintainers. > > Thanks, that seems to be in line with what other platforms do. > CC:ing Lukasz for the clock tree and Anatolij for video. > > > In fact, as there is no PHY driver maintainer, drivers/phy/allwinner had > > no maintainer at all. > > > > Signed-off-by: Samuel Holland > > Acked-by: Andre Przywara Shall I take this through the sunxi tree? Or are you going to take this? Cheers, Andre > > --- > > MAINTAINERS | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index c6dd9bf838..2d66831694 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -478,6 +478,9 @@ F: arch/arm/cpu/armv7/sunxi/ > > F: arch/arm/include/asm/arch-sunxi/ > > F: arch/arm/mach-sunxi/ > > F: board/sunxi/ > > +F: drivers/clk/sunxi/ > > +F: drivers/phy/allwinner/ > > +F: drivers/video/sunxi/ > > > > ARM TEGRA > > M: Tom Warren >
[PATCH 1/3] arm: dts: sunxi: h6: Update DT files
Update the H6 DT files from the Linux 5.12 release.
The changes are minimal (many LED node renames), but also help to enable
USB port 0 in U-Boot (later), enable the RSB device (not yet used in
U-Boot), and also introduce an MMC frequency limit.
Signed-off-by: Andre Przywara
---
arch/arm/dts/sun50i-h6-beelink-gs1.dts | 6 +-
arch/arm/dts/sun50i-h6-cpu-opp.dtsi| 20 ++--
arch/arm/dts/sun50i-h6-orangepi-3.dts | 4 ++--
arch/arm/dts/sun50i-h6-orangepi.dtsi | 4 ++--
arch/arm/dts/sun50i-h6-pine-h64.dts| 7 ---
arch/arm/dts/sun50i-h6.dtsi| 26 ++
6 files changed, 45 insertions(+), 22 deletions(-)
diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts
b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
index 7c9dbde645b..b5808047d6e 100644
--- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
@@ -43,7 +43,7 @@
leds {
compatible = "gpio-leds";
- power {
+ led {
label = "beelink:white:power";
gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
default-state = "on";
@@ -289,10 +289,6 @@
vcc-pm-supply = <®_aldo1>;
};
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
&spdif {
status = "okay";
};
diff --git a/arch/arm/dts/sun50i-h6-cpu-opp.dtsi
b/arch/arm/dts/sun50i-h6-cpu-opp.dtsi
index 1a5eddc5a40..8c6e8536b69 100644
--- a/arch/arm/dts/sun50i-h6-cpu-opp.dtsi
+++ b/arch/arm/dts/sun50i-h6-cpu-opp.dtsi
@@ -8,7 +8,7 @@
nvmem-cells = <&cpu_speed_grade>;
opp-shared;
- opp@48000 {
+ opp-48000 {
clock-latency-ns = <244144>; /* 8 32k periods */
opp-hz = /bits/ 64 <48000>;
@@ -17,7 +17,7 @@
opp-microvolt-speed2 = <82 82 120>;
};
- opp@72000 {
+ opp-72000 {
clock-latency-ns = <244144>; /* 8 32k periods */
opp-hz = /bits/ 64 <72000>;
@@ -26,7 +26,7 @@
opp-microvolt-speed2 = <82 82 120>;
};
- opp@81600 {
+ opp-81600 {
clock-latency-ns = <244144>; /* 8 32k periods */
opp-hz = /bits/ 64 <81600>;
@@ -35,7 +35,7 @@
opp-microvolt-speed2 = <82 82 120>;
};
- opp@88800 {
+ opp-88800 {
clock-latency-ns = <244144>; /* 8 32k periods */
opp-hz = /bits/ 64 <88800>;
@@ -44,7 +44,7 @@
opp-microvolt-speed2 = <82 82 120>;
};
- opp@108000 {
+ opp-108000 {
clock-latency-ns = <244144>; /* 8 32k periods */
opp-hz = /bits/ 64 <108000>;
@@ -53,7 +53,7 @@
opp-microvolt-speed2 = <88 88 120>;
};
- opp@132000 {
+ opp-132000 {
clock-latency-ns = <244144>; /* 8 32k periods */
opp-hz = /bits/ 64 <132000>;
@@ -62,7 +62,7 @@
opp-microvolt-speed2 = <94 94 120>;
};
- opp@148800 {
+ opp-148800 {
clock-latency-ns = <244144>; /* 8 32k periods */
opp-hz = /bits/ 64 <148800>;
@@ -71,7 +71,7 @@
opp-microvolt-speed2 = <100 100 120>;
};
- opp@160800 {
+ opp-160800 {
clock-latency-ns = <244144>; /* 8 32k periods */
opp-hz = /bits/ 64 <160800>;
@@ -80,7 +80,7 @@
opp-microvolt-speed2 = <103 103 120>;
};
- opp@170400 {
+ opp-170400 {
clock-latency-ns = <244144>; /* 8 32k periods */
opp-hz = /bits/ 64 <170400>;
@@ -89,7 +89,7 @@
opp-microvolt-speed2 = <106 106 120>;
};
- opp@18 {
+ opp-18 {
clock-latency-ns = <244144>; /* 8 32k periods */
opp-hz = /bits/ 64 <18>;
diff --git a/arch/arm/dts/sun50i-h6-orangepi-3.dts
b/arch/arm/dts/sun50i-h6-orangepi-3.dts
index 15c9dd8c447..7e83f6146f8 100644
--- a/arch/arm/dts/sun50i-h6-orangepi-3.dts
+++ b/arch/arm/dts/sun50i-h6-orangepi-3.dts
@@ -43,13 +43,13 @@
leds {
compatible = "gpio-leds";
- power {
+ led-0 {
label
[PATCH 0/3] sunxi: dts: Update H3/H5/H6 devicetree from Linux
This syncs the SoC .dtsi and board .dts files from the Linux 5.12 release. For the H3 and H5 this brings us the proper RGMII modes for the boards with Gigabit Ethernet PHYs. The rest are smaller updates, but bring us port 0 USB support on the H6 boards in U-Boot. I know it's a bit late in the game, but those changes look innocent enough to make it into the v2021.07 release still. This way we have all 64-bit boards using Linux 5.12 DTs. Cheers, Andre Andre Przywara (3): arm: dts: sunxi: h6: Update DT files arm: dts: sunxi: h5: Update DT files arm: dts: sunxi: h3: Update DT files .../dts/sun50i-h5-bananapi-m2-plus-v1.2.dts | 1 + arch/arm/dts/sun50i-h5-cpu-opp.dtsi | 79 +++ .../arm/dts/sun50i-h5-libretech-all-h3-cc.dts | 1 + .../arm/dts/sun50i-h5-libretech-all-h5-cc.dts | 2 +- arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts | 6 +- arch/arm/dts/sun50i-h5-nanopi-neo2.dts| 4 +- arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 27 +- arch/arm/dts/sun50i-h5-orangepi-prime.dts | 6 +- arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts | 4 +- .../arm/dts/sun50i-h5-orangepi-zero-plus2.dts | 38 arch/arm/dts/sun50i-h5.dtsi | 61 ++-- arch/arm/dts/sun50i-h6-beelink-gs1.dts| 6 +- arch/arm/dts/sun50i-h6-cpu-opp.dtsi | 20 ++-- arch/arm/dts/sun50i-h6-orangepi-3.dts | 4 +- arch/arm/dts/sun50i-h6-orangepi.dtsi | 4 +- arch/arm/dts/sun50i-h6-pine-h64.dts | 7 +- arch/arm/dts/sun50i-h6.dtsi | 26 + .../dts/sun8i-h2-plus-bananapi-m2-zero.dts| 96 ++- arch/arm/dts/sun8i-h3-beelink-x2.dts | 4 +- arch/arm/dts/sun8i-h3-nanopi-duo2.dts | 4 +- arch/arm/dts/sun8i-h3-nanopi-neo-air.dts | 4 +- arch/arm/dts/sun8i-h3-nanopi.dtsi | 4 +- arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts| 5 - arch/arm/dts/sun8i-h3-orangepi-plus2e.dts | 2 +- arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts | 38 arch/arm/dts/sun8i-h3.dtsi| 49 +- arch/arm/dts/sunxi-h3-h5.dtsi | 42 +++- 27 files changed, 483 insertions(+), 61 deletions(-) create mode 100644 arch/arm/dts/sun50i-h5-cpu-opp.dtsi -- 2.17.5
[PATCH 3/3] arm: dts: sunxi: h3: Update DT files
Update the H3 DT files from the Linux 5.12 release.
The changes update some boards, and don't affect U-Boot, but fix Gigabit
Ethernet when this DT is passed on to the Linux kernel.
Signed-off-by: Andre Przywara
---
.../dts/sun8i-h2-plus-bananapi-m2-zero.dts| 96 ++-
arch/arm/dts/sun8i-h3-beelink-x2.dts | 4 +-
arch/arm/dts/sun8i-h3-nanopi-duo2.dts | 4 +-
arch/arm/dts/sun8i-h3-nanopi-neo-air.dts | 4 +-
arch/arm/dts/sun8i-h3-nanopi.dtsi | 4 +-
arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts| 5 -
arch/arm/dts/sun8i-h3-orangepi-plus2e.dts | 2 +-
arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts | 38
8 files changed, 142 insertions(+), 15 deletions(-)
diff --git a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
index d277d043031..f3f7a2c912a 100644
--- a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
+++ b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
@@ -31,7 +31,7 @@
pwr_led {
label = "bananapi-m2-zero:red:pwr";
- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
default-state = "on";
};
};
@@ -62,6 +62,35 @@
states = <110 0>, <130 1>;
};
+ reg_vcc_dram: vcc-dram {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-dram";
+ regulator-min-microvolt = <150>;
+ regulator-max-microvolt = <150>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+ vin-supply = <®_vcc5v0>;
+ };
+
+ reg_vcc1v2: vcc1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v2";
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ vin-supply = <®_vcc5v0>;
+ };
+
+ poweroff {
+ compatible = "regulator-poweroff";
+ cpu-supply = <®_vcc1v2>;
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
@@ -125,6 +154,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
+ max-speed = <150>;
clocks = <&rtc 1>;
clock-names = "lpo";
vbat-supply = <®_vcc3v3>;
@@ -136,6 +166,70 @@
};
+&pio {
+ gpio-line-names =
+ /* PA */
+ "CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15",
+ "CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29",
+ "CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05",
+ "CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16",
+ "CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27",
+ "CON2-P40", "CON2-P38", "", "",
+ "", "", "", "", "", "", "", "",
+
+ /* PB */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+
+ /* PC */
+ "CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24",
+ "CON2-P18", "", "", "CON2-P26",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+
+ /* PD */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "CSI-PWR-EN", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+
+ /* PE */
+ "CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07",
+ "CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20",
+ "CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12",
+ "CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+
+ /* PF */
+ "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
+ "SDC0-D2", "SDC0-DET", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+
+ /* PG */
+ "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1",
+ "WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX",
+ "BT-UART-RTS", "BT-UAR
[PATCH 2/3] arm: dts: sunxi: h5: Update DT files
Update the H5 DT files from the Linux 5.12 release.
The changes don't affect U-Boot at all, but fix Gigabit Ethernet when
this DT is passed on to the Linux kernel. It also introduces DVFS.
This also updates the shared sunxi-h3-h5.dtsi, but that only adds nodes
that are of no concern to U-Boot.
Signed-off-by: Andre Przywara
---
.../dts/sun50i-h5-bananapi-m2-plus-v1.2.dts | 1 +
arch/arm/dts/sun50i-h5-cpu-opp.dtsi | 79 +++
.../arm/dts/sun50i-h5-libretech-all-h3-cc.dts | 1 +
.../arm/dts/sun50i-h5-libretech-all-h5-cc.dts | 2 +-
arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts | 6 +-
arch/arm/dts/sun50i-h5-nanopi-neo2.dts| 4 +-
arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 27 ++-
arch/arm/dts/sun50i-h5-orangepi-prime.dts | 6 +-
arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts | 4 +-
.../arm/dts/sun50i-h5-orangepi-zero-plus2.dts | 38 +
arch/arm/dts/sun50i-h5.dtsi | 61 --
arch/arm/dts/sun8i-h3.dtsi| 49 +++-
arch/arm/dts/sunxi-h3-h5.dtsi | 42 +-
13 files changed, 296 insertions(+), 24 deletions(-)
create mode 100644 arch/arm/dts/sun50i-h5-cpu-opp.dtsi
diff --git a/arch/arm/dts/sun50i-h5-bananapi-m2-plus-v1.2.dts
b/arch/arm/dts/sun50i-h5-bananapi-m2-plus-v1.2.dts
index 2e2b14c0ae7..8857a379159 100644
--- a/arch/arm/dts/sun50i-h5-bananapi-m2-plus-v1.2.dts
+++ b/arch/arm/dts/sun50i-h5-bananapi-m2-plus-v1.2.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
#include
/ {
diff --git a/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
b/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
new file mode 100644
index 000..b2657201957
--- /dev/null
+++ b/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Chen-Yu Tsai
+
+/ {
+ cpu_opp_table: cpu-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-40800 {
+ opp-hz = /bits/ 64 <40800>;
+ opp-microvolt = <100 100 131>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-64800 {
+ opp-hz = /bits/ 64 <64800>;
+ opp-microvolt = <104 104 131>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-81600 {
+ opp-hz = /bits/ 64 <81600>;
+ opp-microvolt = <108 108 131>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-91200 {
+ opp-hz = /bits/ 64 <91200>;
+ opp-microvolt = <112 112 131>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-96000 {
+ opp-hz = /bits/ 64 <96000>;
+ opp-microvolt = <116 116 131>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-100800 {
+ opp-hz = /bits/ 64 <100800>;
+ opp-microvolt = <120 120 131>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-105600 {
+ opp-hz = /bits/ 64 <105600>;
+ opp-microvolt = <124 124 131>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-110400 {
+ opp-hz = /bits/ 64 <110400>;
+ opp-microvolt = <126 126 131>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-115200 {
+ opp-hz = /bits/ 64 <115200>;
+ opp-microvolt = <130 130 131>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
diff --git a/arch/arm/dts/sun50i-h5-libretech-all-h3-cc.dts
b/arch/arm/dts/sun50i-h5-libretech-all-h3-cc.dts
index a91806618e6..016da3ec321 100644
--- a/arch/arm/dts/sun50i-h5-libretech-all-h3-cc.dts
+++ b/arch/arm/dts/sun50i-h5-libretech-all-h3-cc.dts
@@ -4,6 +4,7 @@
/dts-v1/;
#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
#include
/ {
diff --git a/arch/arm/dts/sun50i-h5-libretech-all-h5-cc.dts
b/arch/arm/dts/sun50i-h5-libretech-all-h5-cc.dts
Re: [PATCH] MAINTAINERS: Add allwinner/sunxi driver directories
On Thu, May 27, 2021 at 12:53:00AM +0100, Andre Przywara wrote: > On Wed, 21 Apr 2021 11:58:47 +0100 > Andre Przywara wrote: > > Simon, Tom, > > > On Sun, 18 Apr 2021 22:13:36 -0500 > > Samuel Holland wrote: > > > > > These drivers are sunxi platform-specific, and so are of interest to the > > > sunxi maintainers. > > > > Thanks, that seems to be in line with what other platforms do. > > CC:ing Lukasz for the clock tree and Anatolij for video. > > > > > In fact, as there is no PHY driver maintainer, drivers/phy/allwinner had > > > no maintainer at all. > > > > > > Signed-off-by: Samuel Holland > > > > Acked-by: Andre Przywara > > Shall I take this through the sunxi tree? Or are you going to take this? Yeah, the sunxi tree, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH RFC 0/2] lib: Remove the need for a HASH_CALCULATE config
Hi Alexandru,
I agree with this series.
Use CONFIG_HASH is more general than adding new CONFIG_HASH_CALCULATE.
Thanks,
Masahisa Kojima
On Tue, 25 May 2021 at 04:28, Alexandru Gagniuc wrote:
>
> I had accidentally noticed commit 87316da05f2f ("lib: introduce
> HASH_CALCULATE option"), when rebasing an unrelated series. It
> immediately caught my attention because It seemed to me to increase
> complexity, without any actual benefit.
>
> In this series, I present an alternative approach, which solves the
> problem by leveraging existing infrastructure instead of adding more
> Kconfig variables.
>
> Alexandru Gagniuc (2):
> Revert "lib: introduce HASH_CALCULATE option"
> efi_loader: Work-around build issue due to missing hash_calculate()
>
> common/Kconfig.boot| 1 -
> lib/Kconfig| 3 ---
> lib/Makefile | 2 +-
> lib/efi_loader/Kconfig | 4 ++--
> 4 files changed, 3 insertions(+), 7 deletions(-)
>
> --
> 2.31.1
>
Re: [PATCH v9 1/1] efi_loader: add PE/COFF image measurement
On Thu, 27 May 2021 at 01:28, Alex G. wrote:
>
> On 5/25/21 10:09 PM, Masahisa Kojima wrote:
> > "TCG PC Client Platform Firmware Profile Specification"
> > requires to measure every attempt to load and execute
> > a OS Loader(a UEFI application) into PCR[4].
> > This commit adds the PE/COFF image measurement, extends PCR,
> > and appends measurement into Event Log.
> >
> > Acked-by: Ilias Apalodimas
> > Tested-by: Ilias Apalodimas
> > Signed-off-by: Masahisa Kojima
> > ---
> >
> > Changes in v9:
> > - use original return code from __get_active_pcr_banks()
> > - return EFI_UNSUPPORTED instead of EFI_INVALID_PARAMETER
> >if efi_image_parse() fails, it complies with TCG spec
> > - remove **new_efi parameter from efi_prepare_aligned_image()
> >to improve the readability
> >
> > (no changes since v7)
> >
> > Changes in v7:
> > - include hash-checksum.h instead of rsa.h
> > - select HASH_CALCULATE in Kconfig, not to update lib/Makefile
>
> I want to remove HASH_CALCULATE for Kconfig for reasons outlined in (1):
>
> (1)
> https://patchwork.ozlabs.org/project/uboot/patch/20210524192857.1486696-2-mr.nuke...@gmail.com/
>
> The root of the problem is that selecting SHA_xxx should compile and
> link the hash_calculate() symbol, and this would make the existing
> kconfig correct. Unfortunately, the selection doesn't happen
> automatically because the SHA code isn't too well organized.
>
> To solve your problem, I would prefer that you take the series in (1) --
> there's a second patch after it -- and use "select HASH" here. You're
> asking "What's the difference ?". The difference is that "HASH" is an
> existing Kconfig symbol, so we don't need to also add "HASH_CALULATE".
As I replied to your series, I agree with your modification.
Thanks,
Masahisa Kojima
>
> Alex
>
> > - rebased the base code
> >
> > Changes in v6:
> > - update lib/Makefile to add hash-checksum.c as a compilation target
> >
> > (no changes since v2)
> >
> > Changes in v2:
> > - Remove duplicate include
> > - Remove unnecessary __packed attribute
> > - Add all EV_EFI_* event definition
> > - Create common function to prepare 8-byte aligned image
> > - Add measurement for EV_EFI_BOOT_SERVICES_DRIVER and
> >EV_EFI_RUNTIME_SERVICES_DRIVER
> > - Use efi_search_protocol() to get device_path
> > - Add function comment
> >
> > include/efi_loader.h | 6 +
> > include/efi_tcg2.h| 9 ++
> > include/tpm-v2.h | 18 +++
> > lib/efi_loader/Kconfig| 1 +
> > lib/efi_loader/efi_image_loader.c | 62 ++---
> > lib/efi_loader/efi_tcg2.c | 207 --
> > 6 files changed, 277 insertions(+), 26 deletions(-)
> >
> > diff --git a/include/efi_loader.h b/include/efi_loader.h
> > index 522696d635..0a9c82a257 100644
> > --- a/include/efi_loader.h
> > +++ b/include/efi_loader.h
> > @@ -426,6 +426,10 @@ efi_status_t efi_disk_register(void);
> > efi_status_t efi_rng_register(void);
> > /* Called by efi_init_obj_list() to install EFI_TCG2_PROTOCOL */
> > efi_status_t efi_tcg2_register(void);
> > +/* measure the pe-coff image, extend PCR and add Event Log */
> > +efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size,
> > +struct efi_loaded_image_obj *handle,
> > +struct efi_loaded_image
> > *loaded_image_info);
> > /* Create handles and protocols for the partitions of a block device */
> > int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc,
> > const char *if_typename, int diskid,
> > @@ -886,6 +890,8 @@ bool efi_secure_boot_enabled(void);
> >
> > bool efi_capsule_auth_enabled(void);
> >
> > +void *efi_prepare_aligned_image(void *efi, u64 *efi_size);
> > +
> > bool efi_image_parse(void *efi, size_t len, struct efi_image_regions
> > **regp,
> >WIN_CERTIFICATE **auth, size_t *auth_len);
> >
> > diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h
> > index 40e241ce31..bcfb98168a 100644
> > --- a/include/efi_tcg2.h
> > +++ b/include/efi_tcg2.h
> > @@ -9,6 +9,7 @@
> > #if !defined _EFI_TCG2_PROTOCOL_H_
> > #define _EFI_TCG2_PROTOCOL_H_
> >
> > +#include
> > #include
> >
> > #define EFI_TCG2_PROTOCOL_GUID \
> > @@ -53,6 +54,14 @@ struct efi_tcg2_event {
> > u8 event[];
> > } __packed;
> >
> > +struct uefi_image_load_event {
> > + efi_physical_addr_t image_location_in_memory;
> > + u64 image_length_in_memory;
> > + u64 image_link_time_address;
> > + u64 length_of_device_path;
> > + struct efi_device_path device_path[];
> > +};
> > +
> > struct efi_tcg2_boot_service_capability {
> > u8 size;
> > struct efi_tcg2_version structure_version;
> > diff --git a/include/tpm-v2.h b/include/tpm-v2.h
> > index 7de7d6a57d..247b386967 100644
> > --- a/include/tpm-v2.h
> > +++ b/include/tpm-v2.h
> > @@ -70,6 +70,24 @@ struct udevice;
> > #define EV_TABLE_OF_DEVICES
Re: Re: [PATCH v5 1/6] dm: regulator: support regulator more state
Hi,
Please ignore these two emails, they are sent in error.
[PATCH v5 0/6] power: pmic: support more PMIC
PATCH v5 1/6] dm: regulator: support regulator more state
张晴
瑞芯微电子股份有限公司
Rockchip Electronics Co.,Ltd
地址：福建省福州市铜盘路软件大道89号软件园A区21号楼
Add:No.21 Building, A District, No.89 Software Boulevard Fuzhou, Fujian 350003,
P.R.China
Tel:+86-0591-83991906-8601
邮编：350003
E-mail:elaine.zh...@rock-chips.com
From: Jaehoon Chung
Date: 2021-05-27 06:18
To: Elaine; Zhang; sjg; philipp.tomsich; kever.yang; lukma
CC: zhangqing; u-boot; chenjh
Subject: Re: [PATCH v5 1/6] dm: regulator: support regulator more state
Hi,
On 5/26/21 5:46 PM, ela...@denx.de wrote:
> From: Joseph Chen
Is it right patch? This patch had been already applied.
Best Regards,
Jaehoon Chung
>
> support parse regulator standard property:
> regulator-off-in-suspend;
> regulator-init-microvolt;
> regulator-suspend-microvolt:
> regulator_get_suspend_enable
> regulator_set_suspend_enable
> regulator_get_suspend_value
> regulator_set_suspend_value
>
> Signed-off-by: Joseph Chen
> Signed-off-by: Elaine Zhang
> Reviewed-by: Kever Yang
> ---
> doc/device-tree-bindings/regulator/regulator.txt | 27 +
> drivers/power/regulator/regulator-uclass.c | 70
>
> include/power/regulator.h| 64 ++
> test/dm/regulator.c | 57 +++
> 4 files changed, 218 insertions(+)
>
> diff --git a/doc/device-tree-bindings/regulator/regulator.txt
> b/doc/device-tree-bindings/regulator/regulator.txt
> index 4ba642b7c77f..6c9a02120fde 100644
> --- a/doc/device-tree-bindings/regulator/regulator.txt
> +++ b/doc/device-tree-bindings/regulator/regulator.txt
> @@ -36,6 +36,28 @@ Optional properties:
> - regulator-always-on: regulator should never be disabled
> - regulator-boot-on: enabled by bootloader/firmware
> - regulator-ramp-delay: ramp delay for regulator (in uV/us)
> +- regulator-init-microvolt: a init allowed Voltage value
> +- regulator-state-(standby|mem|disk)
> + type: object
> + description:
> +sub-nodes for regulator state in Standby, Suspend-to-RAM, and
> +Suspend-to-DISK modes. Equivalent with standby, mem, and disk Linux
> +sleep states.
> +
> +properties:
> + regulator-on-in-suspend:
> +description: regulator should be on in suspend state.
> +type: boolean
> +
> + regulator-off-in-suspend:
> +description: regulator should be off in suspend state.
> +type: boolean
> +
> + regulator-suspend-microvolt:
> +description: the default voltage which regulator would be set in
> + suspend. This property is now deprecated, instead setting voltage
> + for suspend mode via the API which regulator driver provides is
> + recommended.
>
> Note
> The "regulator-name" constraint is used for setting the device's uclass
> @@ -59,7 +81,12 @@ ldo0 {
> regulator-max-microvolt = <180>;
> regulator-min-microamp = <10>;
> regulator-max-microamp = <10>;
> + regulator-init-microvolt = <180>;
> regulator-always-on;
> regulator-boot-on;
> regulator-ramp-delay = <12000>;
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <180>;
> + };
> };
> diff --git a/drivers/power/regulator/regulator-uclass.c
> b/drivers/power/regulator/regulator-uclass.c
> index 76be95bcd159..4986c87e7ba6 100644
> --- a/drivers/power/regulator/regulator-uclass.c
> +++ b/drivers/power/regulator/regulator-uclass.c
> @@ -77,6 +77,33 @@ int regulator_set_value(struct udevice *dev, int uV)
> return ret;
> }
>
> +int regulator_set_suspend_value(struct udevice *dev, int uV)
> +{
> + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
> + struct dm_regulator_uclass_platdata *uc_pdata;
> +
> + uc_pdata = dev_get_uclass_platdata(dev);
> + if (uc_pdata->min_uV != -ENODATA && uV < uc_pdata->min_uV)
> + return -EINVAL;
> + if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV)
> + return -EINVAL;
> +
> + if (!ops->set_suspend_value)
> + return -ENOSYS;
> +
> + return ops->set_suspend_value(dev, uV);
> +}
> +
> +int regulator_get_suspend_value(struct udevice *dev)
> +{
> + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
> +
> + if (!ops->get_suspend_value)
> + return -ENOSYS;
> +
> + return ops->get_suspend_value(dev);
> +}
> +
> /*
> * To be called with at most caution as there is no check
> * before setting the actual voltage value.
> @@ -170,6 +197,26 @@ int regulator_set_enable_if_allowed(struct udevice *dev,
> bool enable)
> return ret;
> }
>
> +int regulator_set_suspend_enable(struct udevice *dev, bool enable)
> +{
> + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
> +
> + if (!ops->set_suspend_enable)
> + return -ENOSYS;
> +
> + return ops->set_suspend_enable(dev, enable);
> +}
> +
> +int regulator_get_suspend_enable(struct udevice *dev)
> +{
> + const struct dm_regul
Re: [PATCH u-boot-marvell 1/5] serial: a37xx: Fix parent clock rate value and divider calculation
On 25.05.21 19:42, Marek Behún wrote:
From: Pali Rohár
UART parent clock is by default the platform's xtal clock, which is
25 MHz.
The value defined in the driver, though, is 25.8048 MHz. This is a hack
for the suboptimal divisor calculation
Divisor = UART clock / (16 * baudrate)
which does not use rounding division, resulting in a suboptimal value
for divisor if the correct parent clock rate was used.
Change the code for divisor calculation to round to closest value, i.e.
Divisor = Round(UART clock / (16 * baudrate))
and change the parent clock rate value to that returned by
get_ref_clk().
This makes A3720 UART stable at standard UART baudrates between 1800 and
230400.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/serial/serial_mvebu_a3700.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/serial/serial_mvebu_a3700.c
b/drivers/serial/serial_mvebu_a3700.c
index 8f404879a5..9e7e479f80 100644
--- a/drivers/serial/serial_mvebu_a3700.c
+++ b/drivers/serial/serial_mvebu_a3700.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
struct mvebu_plat {
void __iomem *base;
@@ -29,8 +30,6 @@ struct mvebu_plat {
#define UART_CTRL_RXFIFO_RESET0x4000
#define UART_CTRL_TXFIFO_RESET0x8000
-#define CONFIG_UART_BASE_CLOCK 25804800
-
static int mvebu_serial_putc(struct udevice *dev, const char ch)
{
struct mvebu_plat *plat = dev_get_plat(dev);
@@ -75,12 +74,15 @@ static int mvebu_serial_setbrg(struct udevice *dev, int
baudrate)
{
struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
+ u32 parent_rate, divider;
/*
* Calculate divider
* baudrate = clock / 16 / divider
*/
- writel(CONFIG_UART_BASE_CLOCK / baudrate / 16, base + UART_BAUD_REG);
+ parent_rate = get_ref_clk() * 100;
+ divider = DIV_ROUND_CLOSEST(parent_rate, baudrate * 16);
+ writel(divider, base + UART_BAUD_REG);
/*
* Set Programmable Oversampling Stack to 0,
@@ -144,6 +146,7 @@ U_BOOT_DRIVER(serial_mvebu) = {
static inline void _debug_uart_init(void)
{
void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+ u32 baudrate, parent_rate, divider;
/* reset FIFOs */
writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET,
@@ -156,7 +159,10 @@ static inline void _debug_uart_init(void)
* Calculate divider
* baudrate = clock / 16 / divider
*/
- writel(CONFIG_UART_BASE_CLOCK / 115200 / 16, base + UART_BAUD_REG);
+ baudrate = 115200;
+ parent_rate = get_ref_clk() * 100;
+ divider = DIV_ROUND_CLOSEST(parent_rate, baudrate * 16);
+ writel(divider, base + UART_BAUD_REG);
/*
* Set Programmable Oversampling Stack to 0,
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH u-boot-marvell 2/5] clk: armada-37xx: Set DM_FLAG_PRE_RELOC
On 25.05.21 19:42, Marek Behún wrote:
Setting DM_FLAG_PRE_RELOC for Armada 3720 clock drivers (TBG and
peripheral clocks) makes it possible for serial driver to retrieve clock
rates via clk API.
Signed-off-by: Marek Behún
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/clk/mvebu/armada-37xx-periph.c | 1 +
drivers/clk/mvebu/armada-37xx-tbg.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c
b/drivers/clk/mvebu/armada-37xx-periph.c
index b0f47c33b3..3b767d7060 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -626,4 +626,5 @@ U_BOOT_DRIVER(armada_37xx_periph_clk) = {
.ops= &armada_37xx_periph_clk_ops,
.priv_auto = sizeof(struct a37xx_periphclk),
.probe = armada_37xx_periph_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c
b/drivers/clk/mvebu/armada-37xx-tbg.c
index b1c0852e89..054aff5e6a 100644
--- a/drivers/clk/mvebu/armada-37xx-tbg.c
+++ b/drivers/clk/mvebu/armada-37xx-tbg.c
@@ -152,4 +152,5 @@ U_BOOT_DRIVER(armada_37xx_tbg_clk) = {
.ops= &armada_37xx_tbg_clk_ops,
.priv_auto = sizeof(struct a37xx_tbgclk),
.probe = armada_37xx_tbg_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
};
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH u-boot-marvell 3/5] serial: a37xx: Use TBG as parent clock
On 25.05.21 19:42, Marek Behún wrote:
From: Pali Rohár
Using TBG clock as parent clock for UART allows us using higher
baudrates than 230400.
Turris MOX with external FT232RL USB-UART works fine up to 3 MBaud
(which is maximum for this USB-UART controller), while EspressoBIN with
integrated pl2303 USB-UART also works fine up to 6 MBaud.
Slower baudrates with TBG as a parent clock can be achieved by
increasing TBG dividers and oversampling divider. When using the slowest
TBG clock, minimal working baudrate is 300.
Signed-off-by: Pali Rohár
Signed-off-by: Marek Behún
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/serial/serial_mvebu_a3700.c | 106 ++--
1 file changed, 101 insertions(+), 5 deletions(-)
diff --git a/drivers/serial/serial_mvebu_a3700.c
b/drivers/serial/serial_mvebu_a3700.c
index 9e7e479f80..ba2ac5917f 100644
--- a/drivers/serial/serial_mvebu_a3700.c
+++ b/drivers/serial/serial_mvebu_a3700.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -11,6 +12,8 @@
struct mvebu_plat {
void __iomem *base;
+ ulong tbg_rate;
+ u8 tbg_idx;
};
/*
@@ -74,21 +77,70 @@ static int mvebu_serial_setbrg(struct udevice *dev, int
baudrate)
{
struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
- u32 parent_rate, divider;
+ u32 divider, d1, d2;
+ u32 oversampling;
/*
* Calculate divider
* baudrate = clock / 16 / divider
*/
- parent_rate = get_ref_clk() * 100;
- divider = DIV_ROUND_CLOSEST(parent_rate, baudrate * 16);
- writel(divider, base + UART_BAUD_REG);
+ d1 = d2 = 1;
+ divider = DIV_ROUND_CLOSEST(plat->tbg_rate, baudrate * 16 * d1 * d2);
/*
* Set Programmable Oversampling Stack to 0,
* UART defaults to 16x scheme
*/
- writel(0, base + UART_POSSR_REG);
+ oversampling = 0;
+
+ if (divider < 1)
+ divider = 1;
+ else if (divider > 1023) {
+ /*
+* If divider is too high for selected baudrate then set
+* divider d1 to the maximal value 6.
+*/
+ d1 = 6;
+ divider = DIV_ROUND_CLOSEST(plat->tbg_rate,
+ baudrate * 16 * d1 * d2);
+ if (divider < 1)
+ divider = 1;
+ else if (divider > 1023) {
+ /*
+* If divider is still too high then set also divider
+* d2 to the maximal value 6.
+*/
+ d2 = 6;
+ divider = DIV_ROUND_CLOSEST(plat->tbg_rate,
+ baudrate * 16 * d1 * d2);
+ if (divider < 1)
+ divider = 1;
+ else if (divider > 1023) {
+ /*
+* And if divider is still to high then
+* use oversampling with maximal factor 63.
+*/
+ oversampling = (63 << 0) | (63 << 8) |
+ (63 << 16) | (63 << 24);
+ divider = DIV_ROUND_CLOSEST(plat->tbg_rate,
+ baudrate * 63 * d1 * d2);
+ if (divider < 1)
+ divider = 1;
+ else if (divider > 1023)
+ divider = 1023;
+ }
+ }
+ }
+
+ divider |= BIT(19); /* Do not use XTAL as a base clock */
+ divider |= d1 << 15; /* Set d1 divider */
+ divider |= d2 << 12; /* Set d2 divider */
+ divider |= plat->tbg_idx << 10; /* Use selected TBG as a base clock */
+
+ while (!(readl(base + UART_STATUS_REG) & UART_STATUS_TX_EMPTY))
+ ;
+ writel(divider, base + UART_BAUD_REG);
+ writel(oversampling, base + UART_POSSR_REG);
return 0;
}
@@ -97,6 +149,50 @@ static int mvebu_serial_probe(struct udevice *dev)
{
struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
+ struct udevice *nb_clk;
+ ofnode nb_clk_node;
+ int i, res;
+
+ nb_clk_node = ofnode_by_compatible(ofnode_null(),
+
"marvell,armada-3700-periph-clock-nb");
+ if (!ofnode_valid(nb_clk_node)) {
+ printf("%s: NB periph clock node not available\n", __func__);
+ return -ENODEV;
+ }
+
+ res = device_get_global_by_ofnode(nb_clk_node, &nb_clk);
+ if (res) {
+ printf("%s: Cannot get NB periph clock\n", __func__);
+ return res;
+
Re: [PATCH u-boot-marvell 5/5] arm: mvebu: a37xx: Enable more baudrates
On 25.05.21 19:42, Marek Behún wrote:
From: Pali Rohár
Extend CONFIG_SYS_BAUDRATE_TABLE and include all standard baudrates and
also nonstandard up to the 6 MBaud. U-Boot's A3720 UART driver can use
baudrates from 300 Baud to 6 MBaud.
This changes all A3720 boards, since all of them include either
mvebu_armada-37xx.h or turris_mox.h config file.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
include/configs/mvebu_armada-37xx.h | 9 +++--
include/configs/turris_mox.h| 9 +++--
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/include/configs/mvebu_armada-37xx.h
b/include/configs/mvebu_armada-37xx.h
index 2ad4325eaf..a2bea2947d 100644
--- a/include/configs/mvebu_armada-37xx.h
+++ b/include/configs/mvebu_armada-37xx.h
@@ -17,8 +17,13 @@
#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200, 230400, 460800, 921600 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
+ 9600, 19200, 38400, 57600, 115200, \
+ 230400, 460800, 50, 576000, \
+ 921600, 100, 1152000, 150, \
+ 200, 250, 300, 350, \
+ 400, 450, 500, 550, \
+ 600 }
/*
* For booting Linux, the board info and command line data
diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h
index 51445ec60a..df312f2019 100644
--- a/include/configs/turris_mox.h
+++ b/include/configs/turris_mox.h
@@ -22,8 +22,13 @@
/* auto boot */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200, 230400, 460800, 921600 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
+ 9600, 19200, 38400, 57600, 115200, \
+ 230400, 460800, 50, 576000, \
+ 921600, 100, 1152000, 150, \
+ 200, 250, 300, 350, \
+ 400, 450, 500, 550, \
+ 600 }
/*
* For booting Linux, the board info and command line data
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH u-boot-marvell 4/5] serial: a37xx: Switch to XTAL clock when booting Linux kernel
On 25.05.21 19:42, Marek Behún wrote:
From: Pali Rohár
Unfortunately the UART driver in current Linux for Armada 3700 expects
UART's parent clock to be XTAL and calculats baudrate divisor according
to XTAL clock. Therefore we must switch back to XTAL clock before
booting kernel.
Do you plan to enhance the Linux driver as well to support TBG as
clock in input at some time?
Implement .remove method for this driver with DM_FLAG_OS_PREPARE flag
set.
If current baudrate is unsuitable for XTAL clock then we do not change
anything. This can only happen if the user either configured unsupported
settings or knows what they are doing and has kernel patches which allow
usage of non-XTAL parent clock.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/serial/serial_mvebu_a3700.c | 67 +
1 file changed, 67 insertions(+)
diff --git a/drivers/serial/serial_mvebu_a3700.c
b/drivers/serial/serial_mvebu_a3700.c
index ba2ac5917f..c7e66fef87 100644
--- a/drivers/serial/serial_mvebu_a3700.c
+++ b/drivers/serial/serial_mvebu_a3700.c
@@ -204,6 +204,71 @@ static int mvebu_serial_probe(struct udevice *dev)
return 0;
}
+static int mvebu_serial_remove(struct udevice *dev)
+{
+ struct mvebu_plat *plat = dev_get_plat(dev);
+ void __iomem *base = plat->base;
+ ulong new_parent_rate, parent_rate;
+ u32 new_divider, divider;
+ u32 new_oversampling;
+ u32 oversampling;
+ u32 d1, d2;
+
+ /*
+* Switch UART base clock back to XTAL because older Linux kernel
+* expects it. Otherwise it does not calculate UART divisor correctly
+* and therefore UART does not work in kernel.
+*/
+ divider = readl(base + UART_BAUD_REG);
+ if (!(divider & BIT(19))) /* UART already uses XTAL */
+ return 0;
+
+ /* Read current divisors settings */
+ d1 = (divider >> 15) & 7;
+ d2 = (divider >> 12) & 7;
+ parent_rate = plat->tbg_rate;
+ divider &= 1023;
+ oversampling = readl(base + UART_POSSR_REG) & 63;
+ if (!oversampling)
+ oversampling = 16;
+
+ /* Calculate new divisor against XTAL clock without changing baudrate */
+ new_oversampling = 0;
+ new_parent_rate = get_ref_clk() * 100;
+ new_divider = DIV_ROUND_CLOSEST(new_parent_rate * divider * d1 * d2 *
+ oversampling, parent_rate * 16);
+
+ /*
+* UART does not work reliably when XTAL divisor is smaller than 4.
+* In this case we do not switch UART parent to XTAL. User either
+* configured unsupported settings or has newer kernel with patches
+* which allow usage of non-XTAL clock as a parent clock.
+*/
+ if (new_divider < 4)
+ return 0;
+
+ /*
+* If new divisor is larger than maximal supported, try to switch
+* from default x16 scheme to oversampling with maximal factor 63.
+*/
+ if (new_divider > 1023) {
+ new_oversampling = 63;
+ new_divider = DIV_ROUND_CLOSEST(new_parent_rate * divider * d1 *
+ d2 * oversampling,
+ parent_rate * new_oversampling);
+ if (new_divider < 4 || new_divider > 1023)
+ return 0;
+ }
+
+ while (!(readl(base + UART_STATUS_REG) & UART_STATUS_TX_EMPTY))
+ ;
+
+ writel(new_divider, base + UART_BAUD_REG);
+ writel(new_oversampling, base + UART_POSSR_REG);
+
+ return 0;
+}
+
static int mvebu_serial_of_to_plat(struct udevice *dev)
{
struct mvebu_plat *plat = dev_get_plat(dev);
@@ -232,6 +297,8 @@ U_BOOT_DRIVER(serial_mvebu) = {
.of_to_plat = mvebu_serial_of_to_plat,
.plat_auto = sizeof(struct mvebu_plat),
.probe = mvebu_serial_probe,
+ .remove = mvebu_serial_remove,
+ .flags = DM_FLAG_OS_PREPARE,
.ops= &mvebu_serial_ops,
};
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v2 1/7] arm: a37xx: pci: Don't put link into LTSSM Recovery state during probe
On 26.05.21 17:59, Pali Rohár wrote: During our debugging of the Aardvark driver in Linux we have discovered that the PCIE_CORE_LINK_CTRL_STAT_REG register in fact controls standard PCIe Link Control Register for PCIe Root Bridge. This led us to discover that the name of the PCIE_CORE_LINK_TRAINING macro and the corresponding comment by this macro's usage is misleading; this bit in fact controls Retrain Link, which, according to PCIe base spec is defined as: A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration, re-entering Recovery is permitted but not required. Entering Recovery state is normally done from LTSSM L0, L0s and L1 states. But since the pci-aardvark.c driver enables Link Training just a few lines above, the controller is not in L0 ready state yet. So setting aardvark bit PCIE_CORE_LINK_TRAINING does not actually enter Recovery state at this place. Moreover, trying to enter LTSSM Recovery state without other configuration is causing issues for some cards (e.g. Atheros AR9xxx and QCA9xxx). Since Recovery state is not entered, these issues are not triggered. Remove code which tries to enter LTSSM Recovery state completely. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese Thanks, Stefan --- drivers/pci/pci-aardvark.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index c43d4f309b19..06c567e236f9 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -613,11 +613,6 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) reg |= PIO_CTRL_ADDR_WIN_DISABLE; advk_writel(pcie, reg, PIO_CTRL); - /* Start link training */ - reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); - reg |= PCIE_CORE_LINK_TRAINING; - advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); - /* Wait for PCIe link up */ if (pcie_advk_wait_for_link(pcie)) return -ENXIO; Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v2 2/7] arm: a37xx: pci: Disable bus mastering when unloading driver
On 26.05.21 17:59, Pali Rohár wrote: Disable Root Bridge I/O space, memory space and bus mastering in Aardvark's remove method, which is called before booting Linux kernel. This ensures that PCIe device which was initialized and used by U-Boot cannot do new DMA transfers until Linux initializes PCI subsystem and loads appropriate drivers for the device. During initialization of PCI subsystem Linux in fact disables this bus mastering on Root Bridge (and later enables it when driver is loaded and configured), but there is a possibility of a small window after U-Boot boots Linux when bus mastering is enabled, which is not correct. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese Thanks, Stefan --- drivers/pci/pci-aardvark.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 06c567e236f9..ee81b2ea46d3 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -675,6 +675,12 @@ static int pcie_advk_remove(struct udevice *dev) struct pcie_advk *pcie = dev_get_priv(dev); u32 reg; + reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); + reg &= ~(PCIE_CORE_CMD_MEM_ACCESS_EN | +PCIE_CORE_CMD_IO_ACCESS_EN | +PCIE_CORE_CMD_MEM_IO_REQ_EN); + advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); + reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg &= ~LINK_TRAINING_EN; advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v2 3/7] arm: a37xx: pci: Fix DT compatible string to Linux' DT compatible
On 26.05.21 17:59, Pali Rohár wrote:
Change DT compatible string for A3700 PCIe from 'marvell,armada-37xx-pcie'
to 'marvell,armada-3700-pcie' to make U-Boot A3700 PCIe DT node compatible
with Linux' DT node.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/dts/armada-37xx.dtsi | 2 +-
drivers/pci/pci-aardvark.c| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index a1052add0cca..b7d325b40577 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -323,7 +323,7 @@
};
pcie0: pcie@d007 {
- compatible = "marvell,armada-37xx-pcie";
+ compatible = "marvell,armada-3700-pcie";
reg = <0 0xd007 0 0x2>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index ee81b2ea46d3..ae1a20551fed 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -717,7 +717,7 @@ static const struct dm_pci_ops pcie_advk_ops = {
};
static const struct udevice_id pcie_advk_ids[] = {
- { .compatible = "marvell,armada-37xx-pcie" },
+ { .compatible = "marvell,armada-3700-pcie" },
{ }
};
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v2 4/7] arm: a37xx: pci: Find PCIe controller node by compatible instead of path
On 26.05.21 17:59, Pali Rohár wrote:
Find PCIe DT node by compatible string instead of retrieving it by using
hardcoded DT path.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/mach-mvebu/armada3700/cpu.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c
b/arch/arm/mach-mvebu/armada3700/cpu.c
index 0cf60d7cdd7d..1abac7c9a47a 100644
--- a/arch/arm/mach-mvebu/armada3700/cpu.c
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -53,8 +53,6 @@
#define A3700_PTE_BLOCK_DEVICE \
(PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE)
-#define PCIE_PATH "/soc/pcie@d007"
-
DECLARE_GLOBAL_DATA_PTR;
static struct mm_region mvebu_mem_map[MAX_MEM_MAP_REGIONS] = {
@@ -288,7 +286,7 @@ int a3700_fdt_fix_pcie_regions(void *blob)
const u32 *ranges;
int node, len;
- node = fdt_path_offset(blob, PCIE_PATH);
+ node = fdt_node_offset_by_compatible(blob, -1,
"marvell,armada-3700-pcie");
if (node < 0)
return node;
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v2 5/7] arm: a37xx: pci: Fix a3700_fdt_fix_pcie_regions() function
On 26.05.21 17:59, Pali Rohár wrote:
Current version of this function uses a lot of incorrect assumptions about
the `ranges` DT property:
* parent(#address-cells) == 2
* #size-cells == 2
* number of entries == 2
* address size of first entry == 0x100
* second child address entry == base + 0x100
Trying to increase PCIe MEM space to more than 16 MiB leads to an overlap
with PCIe IO space, and trying to define additional MEM space (as a third
entry in the `ranges` DT property) causes U-Boot to crash when booting the
kernel.
## Flattened Device Tree blob at 04f0
Booting using the fdt blob at 0x4f0
Loading Device Tree to 1fb01000, end 1fb08f12 ... OK
ERROR: board-specific fdt fixup failed:
- must RESET the board to recover.
Fix a3700_fdt_fix_pcie_regions() to properly parse and update all addresses
in the `ranges` property according to
https://elinux.org/Device_Tree_Usage#PCI_Address_Translation
Now it is possible to increase PCIe MEM space from 16 MiB to maximal value
of 127 MiB.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
Fixes: cb2ddb291ee6 ("arm64: mvebu: a37xx: add device-tree fixer for PCIe
regions")
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/mach-mvebu/armada3700/cpu.c | 74 ++--
1 file changed, 60 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c
b/arch/arm/mach-mvebu/armada3700/cpu.c
index 1abac7c9a47a..9aec0ce9a430 100644
--- a/arch/arm/mach-mvebu/armada3700/cpu.c
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -280,36 +281,81 @@ static u32 find_pcie_window_base(void)
return -1;
}
+static int fdt_setprop_inplace_u32_partial(void *blob, int node,
+ const char *name,
+ u32 idx, u32 val)
+{
+ val = cpu_to_fdt32(val);
+
+ return fdt_setprop_inplace_namelen_partial(blob, node, name,
+ strlen(name),
+ idx * sizeof(u32),
+ &val, sizeof(u32));
+}
+
int a3700_fdt_fix_pcie_regions(void *blob)
{
- u32 new_ranges[14], base;
+ int acells, pacells, scells;
+ u32 base, fix_offset;
const u32 *ranges;
- int node, len;
+ int node, pnode;
+ int ret, i, len;
+
+ base = find_pcie_window_base();
+ if (base == -1)
+ return -ENOENT;
node = fdt_node_offset_by_compatible(blob, -1, "marvell,armada-3700-pcie");
if (node < 0)
return node;
ranges = fdt_getprop(blob, node, "ranges", &len);
- if (!ranges)
+ if (!ranges || len % sizeof(u32))
return -ENOENT;
- if (len != sizeof(new_ranges))
- return -EINVAL;
-
- memcpy(new_ranges, ranges, len);
+ /*
+* The "ranges" property is an array of
+* {}
+*
+* All 3 elements can span a diffent number of cells. Fetch their sizes.
+*/
+ pnode = fdt_parent_offset(blob, node);
+ acells = fdt_address_cells(blob, node);
+ pacells = fdt_address_cells(blob, pnode);
+ scells = fdt_size_cells(blob, node);
- base = find_pcie_window_base();
- if (base == -1)
+ /* Child PCI addresses always use 3 cells */
+ if (acells != 3)
return -ENOENT;
- new_ranges[2] = cpu_to_fdt32(base);
- new_ranges[4] = new_ranges[2];
+ /* Calculate fixup offset from first child address (in last cell) */
+ fix_offset = base - fdt32_to_cpu(ranges[2]);
- new_ranges[9] = cpu_to_fdt32(base + 0x100);
- new_ranges[11] = new_ranges[9];
+ /*
+* Fix address (last cell) of each child address and each parent
+* address
+*/
+ for (i = 0; i < len / sizeof(u32); i += acells + pacells + scells) {
+ int idx;
+
+ /* fix child address */
+ idx = i + acells - 1;
+ ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
+ fdt32_to_cpu(ranges[idx])
+
+ fix_offset);
+ if (ret)
+ return ret;
+
+ /* fix parent address */
+ idx = i + acells + pacells - 1;
+ ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
+ fdt32_to_cpu(ranges[idx])
+
+ fix_offset);
+ if (ret)
+ return ret;
+ }
- return fdt_setprop_inplace(blob, node, "ranges", new_ranges, len);
+ return 0;
}
void reset_cpu(void)
Viele Grü
Re: [PATCH v2 6/7] arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiB
On 26.05.21 17:59, Pali Rohár wrote: For some configurations with more PCIe cards and PCIe bridges, 16 MiB of PCIe MEM space may not be enough. Since TF-A already allocates a 128 MiB CPU window for PCIe, and since IO port space is only 64 KiB in total, use all the remaining space (64 + 32 + 16 + 8 + 4 + 2 + 1 = 127 MiB) for PCIe MEM. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese Thanks, Stefan --- Changes in v2: * Fix size for PCIe MEM --- arch/arm/dts/armada-37xx.dtsi | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index b7d325b40577..2615b8c748c1 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -332,10 +332,17 @@ status = "disabled"; bus-range = <0 0xff>; + /* +* The 128 MiB address range [0xe800-0xf000] is +* dedicated for PCIe and can be assigned to 8 windows +* with size a power of two. Use one 64 KiB window for +* IO at the end and the remaining seven windows +* (totaling 127 MiB) for MEM. +*/ ranges = <0x8200 0 0xe800 -0 0xe800 0 0x100 /* Port 0 MEM */ -0x8100 0 0xe900 -0 0xe900 0 0x1>; /* Port 0 IO*/ +0 0xe800 0 0x7f0 /* Port 0 MEM */ +0x8100 0 0xefff +0 0xefff 0 0x1>; /* Port 0 IO*/ }; }; }; Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v2 7/7] arm: a37xx: pci: Fix configuring PCIe resources
On 26.05.21 17:59, Pali Rohár wrote:
The `ranges` DT property of the PCIe node is currently ignored by
Aardvark driver - all entries are used as transparent PCIe MEM, despite
some of them being defined for IO in DT.
This is because the driver does not setup PCIe outbound windows and thus
a default configuration is used.
This can cause an external abort on CPU when a device driver tries to
access non-MEM space.
Setup the PCIe windows according to the `ranges` property for all
non-MEM resources (currently only IO) and also non-transparent MEM
resources.
Because Linux expects that bootloader does not setup Aardvark PCIe
windows, disable them before booting Linux.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/pci/pci-aardvark.c | 158 -
1 file changed, 157 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index ae1a20551fed..96aa039bdc26 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -99,6 +99,46 @@
#define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
#define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLEBIT(6)
+/* PCIe window configuration */
+#define OB_WIN_BASE_ADDR 0x4c00
+#define OB_WIN_BLOCK_SIZE 0x20
+#define OB_WIN_COUNT 8
+#define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
+OB_WIN_BLOCK_SIZE * (win) + \
+(offset))
+#define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
+#define OB_WIN_ENABLE BIT(0)
+#define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
+#define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
+#define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
+#define OB_WIN_MASK_LS(win)OB_WIN_REG_ADDR(win, 0x10)
+#define OB_WIN_MASK_MS(win)OB_WIN_REG_ADDR(win, 0x14)
+#define OB_WIN_ACTIONS(win)OB_WIN_REG_ADDR(win, 0x18)
+#define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1)
+ 0x4)
+#define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
+#define OB_WIN_FUNC_NUM_SHIFT 24
+#define OB_WIN_FUNC_NUM_ENABLE BIT(23)
+#define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
+#define OB_WIN_BUS_NUM_BITS_SHIFT 20
+#define OB_WIN_MSG_CODE_ENABLE BIT(22)
+#define OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
+#define OB_WIN_MSG_CODE_SHIFT 14
+#define OB_WIN_MSG_PAYLOAD_LEN BIT(12)
+#define OB_WIN_ATTR_ENABLE BIT(11)
+#define OB_WIN_ATTR_TC_MASKGENMASK(10, 8)
+#define OB_WIN_ATTR_TC_SHIFT 8
+#define OB_WIN_ATTR_RELAXEDBIT(7)
+#define OB_WIN_ATTR_NOSNOOPBIT(6)
+#define OB_WIN_ATTR_POISON BIT(5)
+#define OB_WIN_ATTR_IDOBIT(4)
+#define OB_WIN_TYPE_MASK GENMASK(3, 0)
+#define OB_WIN_TYPE_SHIFT 0
+#define OB_WIN_TYPE_MEM0x0
+#define OB_WIN_TYPE_IO 0x4
+#define OB_WIN_TYPE_CONFIG_TYPE0 0x8
+#define OB_WIN_TYPE_CONFIG_TYPE1 0x9
+#define OB_WIN_TYPE_MSG0xc
+
/* LMI registers base address and register offsets */
#define LMI_BASE_ADDR 0x6000
#define CFG_REG (LMI_BASE_ADDR + 0x0)
@@ -522,6 +562,86 @@ static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
return -ETIMEDOUT;
}
+/*
+ * Set PCIe address window register which could be used for memory
+ * mapping.
+ */
+static void pcie_advk_set_ob_win(struct pcie_advk *pcie, u8 win_num,
+phys_addr_t match, phys_addr_t remap,
+phys_addr_t mask, u32 actions)
+{
+ advk_writel(pcie, OB_WIN_ENABLE |
+ lower_32_bits(match), OB_WIN_MATCH_LS(win_num));
+ advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
+ advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
+ advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
+ advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
+ advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
+ advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
+}
+
+static void pcie_advk_disable_ob_win(struct pcie_advk *pcie, u8 win_num)
+{
+ advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
+ advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
+ advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
+
[PATCH] meson64: add kernel compression vars
make possible to load simple compressed linux kernel for meson64 Signed-off-by: Artem Lapkin --- include/configs/meson64.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/meson64.h b/include/configs/meson64.h index e3d25493..552a08c2 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -113,6 +113,8 @@ "stdin=" STDIN_CFG "\0" \ "stdout=" STDOUT_CFG "\0" \ "stderr=" STDOUT_CFG "\0" \ + "kernel_comp_addr_r=0x0d08\0" \ + "kernel_comp_size=0x200\0" \ "fdt_addr_r=0x08008000\0" \ "loadaddr=0x0100\0" \ "scriptaddr=0x0800\0" \ -- 2.25.1
