[PATCH] configs: layerscape: Disable the EFI_LOADER feature
From: Hou Zhiqiang
The feature BOOTENV_SHARED_EFI is not supported on layerscape
boards, it didn't result kernel boot crash previously since
there isn't the efi/boot/"BOOTEFI_NAME" and it skip calling of
'boot_efi_binary'.
But since the commit f3866909e350 ("distro_bootcmd: call EFI
bootmgr even without having /EFI/boot"), it will cause kernel
boot crash as there isn't a valid fdt_addr and it finially uses
the device tree blob of U-Boot and further cause errors.
As this feature is enabled by default for armv7 and armv8, so
disable it explicitly to avoid calling the 'scan_dev_for_efi'.
Signed-off-by: Hou Zhiqiang
---
configs/ls1012a2g5rdb_qspi_defconfig | 1 +
configs/ls1012a2g5rdb_tfa_defconfig | 1 +
configs/ls1012afrdm_qspi_defconfig | 1 +
configs/ls1012afrdm_tfa_defconfig| 1 +
configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 +
configs/ls1012afrwy_qspi_defconfig | 1 +
configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig| 1 +
configs/ls1012afrwy_tfa_defconfig| 1 +
configs/ls1012aqds_qspi_defconfig| 1 +
configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1012aqds_tfa_defconfig | 1 +
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig| 1 +
configs/ls1012ardb_qspi_defconfig| 1 +
configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1012ardb_tfa_defconfig | 1 +
configs/ls1021aiot_qspi_defconfig| 1 +
configs/ls1021aiot_sdcard_defconfig | 1 +
configs/ls1021aqds_ddr4_nor_defconfig| 1 +
configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 +
configs/ls1021aqds_nand_defconfig| 1 +
configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 +
configs/ls1021aqds_nor_defconfig | 1 +
configs/ls1021aqds_nor_lpuart_defconfig | 1 +
configs/ls1021aqds_qspi_defconfig| 1 +
configs/ls1021aqds_sdcard_ifc_defconfig | 1 +
configs/ls1021aqds_sdcard_qspi_defconfig | 1 +
configs/ls1021atsn_qspi_defconfig| 1 +
configs/ls1021atsn_sdcard_defconfig | 1 +
configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 +
configs/ls1021atwr_nor_defconfig | 1 +
configs/ls1021atwr_nor_lpuart_defconfig | 1 +
configs/ls1021atwr_qspi_defconfig| 1 +
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
configs/ls1021atwr_sdcard_ifc_defconfig | 1 +
configs/ls1021atwr_sdcard_qspi_defconfig | 1 +
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1028aqds_tfa_defconfig | 1 +
configs/ls1028aqds_tfa_lpuart_defconfig | 1 +
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1028ardb_tfa_defconfig | 1 +
configs/ls1043aqds_defconfig | 1 +
configs/ls1043aqds_lpuart_defconfig | 1 +
configs/ls1043aqds_nand_defconfig| 1 +
configs/ls1043aqds_nor_ddr3_defconfig| 1 +
configs/ls1043aqds_qspi_defconfig| 1 +
configs/ls1043aqds_sdcard_ifc_defconfig | 1 +
configs/ls1043aqds_sdcard_qspi_defconfig | 1 +
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1043aqds_tfa_defconfig | 1 +
configs/ls1043ardb_SECURE_BOOT_defconfig | 1 +
configs/ls1043ardb_defconfig | 1 +
configs/ls1043ardb_nand_SECURE_BOOT_defconfig| 1 +
configs/ls1043ardb_nand_defconfig| 1 +
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 +
configs/ls1043ardb_sdcard_defconfig | 1 +
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1043ardb_tfa_defconfig | 1 +
configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig| 1 +
configs/ls1046afrwy_tfa_defconfig| 1 +
configs/ls1046aqds_SECURE_BOOT_defconfig | 1 +
configs/ls1046aqds_defconfig | 1 +
configs/ls1046aqds_lpuart_defconfig | 1 +
configs/ls1046aqds_nand_defconfig| 1 +
configs/ls1046aqds_qspi_defconfig| 1 +
configs/ls1046aqds_sdcard_ifc_defconfig | 1 +
configs/ls1046aqds_sdcard_qspi_defconfig | 1 +
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1046aqds_tfa_defconfig | 1 +
configs/ls1046ardb_emmc_defconfig| 1 +
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig| 1 +
configs/ls1046ardb_qspi_defconfig| 1 +
configs/ls1046ardb_qspi_spl_defconfig| 1 +
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
Re: [PATCH 08/22] sandbox: Add work-around for SDL2 display
On 7/6/21 12:32 AM, Simon Glass wrote:
At present the display does not show on some machines, e.g. Ubunutu
20.04 but the reason is unknown. Add a work-around until this can be
determined.
I am running Ubuntu 20.04 and
./u-boot -T -l
shows the graphical console for sandbox_defconfig.
Please, provide more detail on how to reproduce the issue on Ubuntu Hirsute.
Best regards
Heinrich
Also include more error checking just in case.
Signed-off-by: Simon Glass
---
arch/sandbox/cpu/sdl.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/sandbox/cpu/sdl.c b/arch/sandbox/cpu/sdl.c
index 8102649be3a..e2649494818 100644
--- a/arch/sandbox/cpu/sdl.c
+++ b/arch/sandbox/cpu/sdl.c
@@ -164,8 +164,29 @@ int sandbox_sdl_init_display(int width, int height, int
log2_bpp,
int sandbox_sdl_sync(void *lcd_base)
{
+ struct SDL_Rect rect;
+ int ret;
+
+ if (!sdl.texture)
+ return 0;
+ SDL_RenderClear(sdl.renderer);
SDL_UpdateTexture(sdl.texture, NULL, lcd_base, sdl.pitch);
- SDL_RenderCopy(sdl.renderer, sdl.texture, NULL, NULL);
+ ret = SDL_RenderCopy(sdl.renderer, sdl.texture, NULL, NULL);
+ if (ret) {
+ printf("SDL copy %d: %s\n", ret, SDL_GetError());
+ return -EIO;
+ }
+
+ /*
+* On some machines this does not appear. Draw an empty rectangle which
+* seems to fix that.
+*/
+ rect.x = 0;
+ rect.y = 0;
+ rect.w = 0;
+ rect.h = 0;
+ SDL_RenderDrawRect(sdl.renderer, &rect);
+
SDL_RenderPresent(sdl.renderer);
sandbox_sdl_poll_events();
Re: [PATCH 2/5] doc: Move coccinelle into its own section
On 7/22/21 5:35 AM, Simon Glass wrote: This tool has nothing to do with testing. It is for refactoring code automatically using a 'semantic patch' tool. Create a new section for 'refactoring' and move it into there. It is likely that other topics may fall under the same heading, such as using moveconfig and search/replace tools. Signed-off-by: Simon Glass --- This patch was submitted previously: http://patchwork.ozlabs.org/project/uboot/patch/20210304135118.643277-38-...@chromium.org/ It was rejected, but I think that was incorrect. doc/develop/index.rst | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 901d39f4564..2bd7c4a1a3a 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -41,7 +41,14 @@ Testing :maxdepth: 1 testing - coccinelle py_testing tests_writing tests_sandbox + +Refactoring +--- Coccinelle is used to detect common coding issues (e.g. using 0 instead of NULL for pointers). How does this relate to refactoring? Best regards Heinrich + +.. toctree:: + :maxdepth: 1 + + coccinelle
Re: [PATCH 1/5] doc: Create an intro section for testing
On 7/22/21 5:35 AM, Simon Glass wrote: At present this information is hidden away. Make it more visible by putting it first, in an intro section. Signed-off-by: Simon Glass --- doc/develop/index.rst | 2 +- doc/develop/testing.rst | 6 -- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 3edffbc6373..901d39f4564 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -40,8 +40,8 @@ Testing .. toctree:: :maxdepth: 1 - coccinelle testing + coccinelle This change seems to be unrelated. Otherwise Reviewed-by: Heinrich Schuchardt py_testing tests_writing tests_sandbox diff --git a/doc/develop/testing.rst b/doc/develop/testing.rst index ced13ac8bb4..1abe4d7f0f0 100644 --- a/doc/develop/testing.rst +++ b/doc/develop/testing.rst @@ -1,5 +1,7 @@ -Testing in U-Boot -= +.. SPDX-License-Identifier: GPL-2.0+ + +Introduction to testing +=== U-Boot has a large amount of code. This file describes how this code is tested and what tests you should write when adding a new feature.
[PATCH 5/5] moveconfig: Update to newer kconfiglib
Some of the more advanced features of this tool don't work anymore since
kconfiglib was update. Update the code accordingly.
Signed-off-by: Simon Glass
---
tools/moveconfig.py | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index f3fd75504f7..373b395fda4 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -1262,8 +1262,8 @@ def find_kconfig_rules(kconf, config, imply_config):
"""
sym = kconf.syms.get(imply_config)
if sym:
-for sel in sym.get_selected_symbols() | sym.get_implied_symbols():
-if sel.get_name() == config:
+for sel, cond in (sym.selects + sym.implies):
+if sel == config:
return sym
return None
@@ -1288,10 +1288,10 @@ def check_imply_rule(kconf, config, imply_config):
sym = kconf.syms.get(imply_config)
if not sym:
return 'cannot find sym'
-locs = sym.get_def_locations()
-if len(locs) != 1:
-return '%d locations' % len(locs)
-fname, linenum = locs[0]
+nodes = sym.nodes
+if len(nodes) != 1:
+return '%d locations' % len(nodes)
+fname, linenum = nodes[0].filename, nodes[0].linern
cwd = os.getcwd()
if cwd and fname.startswith(cwd):
fname = fname[len(cwd) + 1:]
@@ -1502,9 +1502,9 @@ def do_imply_config(config_list, add_imply, imply_flags,
skip_added,
iconfig[CONFIG_LEN:])
kconfig_info = ''
if sym:
-locs = sym.get_def_locations()
-if len(locs) == 1:
-fname, linenum = locs[0]
+nodes = sym.nodes
+if len(nodes) == 1:
+fname, linenum = nodes[0].filename, nodes[0].linenr
if cwd and fname.startswith(cwd):
fname = fname[len(cwd) + 1:]
kconfig_info = '%s:%d' % (fname, linenum)
@@ -1514,9 +1514,9 @@ def do_imply_config(config_list, add_imply, imply_flags,
skip_added,
sym = kconf.syms.get(iconfig[CONFIG_LEN:])
fname = ''
if sym:
-locs = sym.get_def_locations()
-if len(locs) == 1:
-fname, linenum = locs[0]
+nodes = sym.nodes
+if len(nodes) == 1:
+fname, linenum = nodes[0].filename, nodes[0].linenr
if cwd and fname.startswith(cwd):
fname = fname[len(cwd) + 1:]
in_arch_board = not sym or (fname.startswith('arch') or
--
2.32.0.402.g57bb445576-goog
[PATCH 3/5] doc: Add docs for the moveconfig tool
Move these docs into htmldocs so they can be read there. Signed-off-by: Simon Glass --- doc/develop/index.rst | 1 + doc/develop/moveconfig.rst | 296 + tools/moveconfig.py| 291 +--- 3 files changed, 298 insertions(+), 290 deletions(-) create mode 100644 doc/develop/moveconfig.rst diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 2bd7c4a1a3a..3b8a6144ff9 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -52,3 +52,4 @@ Refactoring :maxdepth: 1 coccinelle + moveconfig diff --git a/doc/develop/moveconfig.rst b/doc/develop/moveconfig.rst new file mode 100644 index 000..aaa155e8c70 --- /dev/null +++ b/doc/develop/moveconfig.rst @@ -0,0 +1,296 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +moveconfig +== + +Since Kconfig was introduced to U-Boot, we have worked on moving +config options from headers to Kconfig (defconfig). + +This tool intends to help this tremendous work. + +Installing +-- + +You may need to install 'python3-asteval' for the 'asteval' module. + +Usage +- + +First, you must edit the Kconfig to add the menu entries for the configs +you are moving. + +Then run this tool giving CONFIG names you want to move. +For example, if you want to move CONFIG_CMD_USB and CONFIG_SYS_TEXT_BASE, +simply type as follows:: + + $ tools/moveconfig.py CONFIG_CMD_USB CONFIG_SYS_TEXT_BASE + +The tool walks through all the defconfig files and move the given CONFIGs. + +The log is also displayed on the terminal. + +The log is printed for each defconfig as follows:: + + + + + + ... + +`` is the name of the defconfig. + +`` shows what the tool did for that defconfig. +It looks like one of the following: + + - Move 'CONFIG\_... ' + This config option was moved to the defconfig + + - CONFIG\_... is not defined in Kconfig. Do nothing. + The entry for this CONFIG was not found in Kconfig. The option is not + defined in the config header, either. So, this case can be just skipped. + + - CONFIG\_... is not defined in Kconfig (suspicious). Do nothing. + This option is defined in the config header, but its entry was not found + in Kconfig. + There are two common cases: + + - You forgot to create an entry for the CONFIG before running + this tool, or made a typo in a CONFIG passed to this tool. + - The entry was hidden due to unmet 'depends on'. + + The tool does not know if the result is reasonable, so please check it + manually. + + - 'CONFIG\_...' is the same as the define in Kconfig. Do nothing. + The define in the config header matched the one in Kconfig. + We do not need to touch it. + + - Compiler is missing. Do nothing. + The compiler specified for this architecture was not found + in your PATH environment. + (If -e option is passed, the tool exits immediately.) + + - Failed to process. + An error occurred during processing this defconfig. Skipped. + (If -e option is passed, the tool exits immediately on error.) + +Finally, you will be asked, Clean up headers? [y/n]: + +If you say 'y' here, the unnecessary config defines are removed +from the config headers (include/configs/\*.h). +It just uses the regex method, so you should not rely on it. +Just in case, please do 'git diff' to see what happened. + + +How does it work? +- + +This tool runs configuration and builds include/autoconf.mk for every +defconfig. The config options defined in Kconfig appear in the .config +file (unless they are hidden because of unmet dependency.) +On the other hand, the config options defined by board headers are seen +in include/autoconf.mk. The tool looks for the specified options in both +of them to decide the appropriate action for the options. If the given +config option is found in the .config, but its value does not match the +one from the board header, the config option in the .config is replaced +with the define in the board header. Then, the .config is synced by +"make savedefconfig" and the defconfig is updated with it. + +For faster processing, this tool handles multi-threading. It creates +separate build directories where the out-of-tree build is run. The +temporary build directories are automatically created and deleted as +needed. The number of threads are chosen based on the number of the CPU +cores of your system although you can change it via -j (--jobs) option. + + +Toolchains +-- + +Appropriate toolchain are necessary to generate include/autoconf.mk +for all the architectures supported by U-Boot. Most of them are available +at the kernel.org site, some are not provided by kernel.org. This tool uses +the same tools as buildman, so see that tool for setup (e.g. --fetch-arch). + + +Tips and trips +-- + +To sync only X86 defconfigs:: + + ./tools/moveconfig.py -s -d <(grep -l X86 configs/*) + +or:: + + grep -l X86 configs/* | ./tools/moveconfig.py -s -d - +
[PATCH 4/5] doc: Fix up outdated moveconfig docs
The examples here are a bit messed up since the command does not match the documentation. Use a different example instead. Signed-off-by: Simon Glass --- doc/develop/moveconfig.rst | 58 +++--- 1 file changed, 22 insertions(+), 36 deletions(-) diff --git a/doc/develop/moveconfig.rst b/doc/develop/moveconfig.rst index aaa155e8c70..dcd4d927e40 100644 --- a/doc/develop/moveconfig.rst +++ b/doc/develop/moveconfig.rst @@ -144,50 +144,36 @@ This tool can help find such configs. To use it, first build a database:: Then try to query it:: -./tools/moveconfig.py -i CONFIG_CMD_IRQ -CONFIG_CMD_IRQ found in 311/2384 defconfigs -44 : CONFIG_SYS_FSL_ERRATUM_IFC_A002769 -41 : CONFIG_SYS_FSL_ERRATUM_A007075 -31 : CONFIG_SYS_FSL_DDR_VER_44 -28 : CONFIG_ARCH_P1010 -28 : CONFIG_SYS_FSL_ERRATUM_P1010_A003549 -28 : CONFIG_SYS_FSL_ERRATUM_SEC_A003571 -28 : CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -25 : CONFIG_SYS_FSL_ERRATUM_A008044 -22 : CONFIG_ARCH_P1020 -21 : CONFIG_SYS_FSL_DDR_VER_46 -20 : CONFIG_MAX_PIRQ_LINKS -20 : CONFIG_HPET_ADDRESS -20 : CONFIG_X86 -20 : CONFIG_PCIE_ECAM_SIZE -20 : CONFIG_IRQ_SLOT_COUNT -20 : CONFIG_I8259_PIC -20 : CONFIG_CPU_ADDR_BITS -20 : CONFIG_RAMBASE -20 : CONFIG_SYS_FSL_ERRATUM_A005871 -20 : CONFIG_PCIE_ECAM_BASE -20 : CONFIG_X86_TSC_TIMER -20 : CONFIG_I8254_TIMER -20 : CONFIG_CMD_GETTIME -19 : CONFIG_SYS_FSL_ERRATUM_A005812 -18 : CONFIG_X86_RUN_32BIT -17 : CONFIG_CMD_CHIP_CONFIG -... - -This shows a list of config options which might imply CONFIG_CMD_EEPROM along + ./tools/moveconfig.py -i CONFIG_I8042_KEYB + CONFIG_I8042_KEYB found in 33/5155 defconfigs + 28 : CONFIG_X86 + 28 : CONFIG_SA_PCIEX_LENGTH + 28 : CONFIG_HPET_ADDRESS + 28 : CONFIG_MAX_PIRQ_LINKS + 28 : CONFIG_I8254_TIMER + 28 : CONFIG_I8259_PIC + 28 : CONFIG_RAMBASE + 28 : CONFIG_IRQ_SLOT_COUNT + 28 : CONFIG_PCIE_ECAM_SIZE + 28 : CONFIG_APIC + ... + +This shows a list of config options which might imply CONFIG_I8042_KEYB along with how many defconfigs they cover. From this you can see that CONFIG_X86 -implies CONFIG_CMD_EEPROM. Therefore, instead of adding CONFIG_CMD_EEPROM to +generally implies CONFIG_I8042_KEYB but not always (28 out of 35). Therefore, +instead of adding CONFIG_I8042_KEYB to the defconfig of every x86 board, you could add a single imply line to the -Kconfig file: +Kconfig file:: config X86 bool "x86 architecture" ... imply CMD_EEPROM -That will cover 20 defconfigs. Many of the options listed are not suitable as -they are not related. E.g. it would be odd for CONFIG_CMD_GETTIME to imply -CMD_EEPROM. +That will cover 28 defconfigs and you can perhaps find another condition that +indicates that CONFIG_I8042_KEYB is not needed for the remaining 5 boards. Many +of the options listed are not suitable as they are not related. E.g. it would be +odd for CONFIG_RAMBASE to imply CONFIG_I8042_KEYB. Using this search you can reduce the size of moveconfig patches. -- 2.32.0.402.g57bb445576-goog
[PATCH 2/5] doc: Move coccinelle into its own section
This tool has nothing to do with testing. It is for refactoring code automatically using a 'semantic patch' tool. Create a new section for 'refactoring' and move it into there. It is likely that other topics may fall under the same heading, such as using moveconfig and search/replace tools. Signed-off-by: Simon Glass --- This patch was submitted previously: http://patchwork.ozlabs.org/project/uboot/patch/20210304135118.643277-38-...@chromium.org/ It was rejected, but I think that was incorrect. doc/develop/index.rst | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 901d39f4564..2bd7c4a1a3a 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -41,7 +41,14 @@ Testing :maxdepth: 1 testing - coccinelle py_testing tests_writing tests_sandbox + +Refactoring +--- + +.. toctree:: + :maxdepth: 1 + + coccinelle -- 2.32.0.402.g57bb445576-goog
[PATCH 1/5] doc: Create an intro section for testing
At present this information is hidden away. Make it more visible by putting it first, in an intro section. Signed-off-by: Simon Glass --- doc/develop/index.rst | 2 +- doc/develop/testing.rst | 6 -- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 3edffbc6373..901d39f4564 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -40,8 +40,8 @@ Testing .. toctree:: :maxdepth: 1 - coccinelle testing + coccinelle py_testing tests_writing tests_sandbox diff --git a/doc/develop/testing.rst b/doc/develop/testing.rst index ced13ac8bb4..1abe4d7f0f0 100644 --- a/doc/develop/testing.rst +++ b/doc/develop/testing.rst @@ -1,5 +1,7 @@ -Testing in U-Boot -= +.. SPDX-License-Identifier: GPL-2.0+ + +Introduction to testing +=== U-Boot has a large amount of code. This file describes how this code is tested and what tests you should write when adding a new feature. -- 2.32.0.402.g57bb445576-goog
[PATCH 0/5] doc: Improve documentation for testing
This creates an introduction section for testing so that it is easier to figure out what is going on. It also moves the moveconfig docs to rST and brings in an old patch that was rejected at the time. Simon Glass (5): doc: Create an intro section for testing doc: Move coccinelle into its own section doc: Add docs for the moveconfig tool doc: Fix up outdated moveconfig docs moveconfig: Update to newer kconfiglib doc/develop/index.rst | 10 +- doc/develop/moveconfig.rst | 282 + doc/develop/testing.rst| 6 +- tools/moveconfig.py| 315 ++--- 4 files changed, 308 insertions(+), 305 deletions(-) create mode 100644 doc/develop/moveconfig.rst -- 2.32.0.402.g57bb445576-goog
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit c9204859bbdb924cda811813c545032971656480: Merge branch 'master' of git://source.denx.de/u-boot-sh (2021-07-20 19:31:40 -0400) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 219cb173114c9cfaf1dc7fed21281f2c43c88c9f: board: sifive: unmatched: reset USB hub, PCIe-USB bridge, and ULPI device in SPL (2021-07-21 22:25:15 +0800) CI result show no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8344 Vincent Chen (2): board: sifive: unmatched: refine GEMGXL initialized function in SPL board: sifive: unmatched: reset USB hub, PCIe-USB bridge, and ULPI device in SPL Vitaly Wool (1): riscv: booti: do not force relocation if force_reloc is not set Zong Li (2): board: sifive: remove the command for setting serial number board: sifive: drop stuff related to unmatched revision 1 arch/riscv/dts/Makefile|2 +- .../dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi | 1489 .../dts/hifive-unmatched-a00-rev1-u-boot.dtsi |7 - arch/riscv/dts/hifive-unmatched-a00-rev1.dts |4 - arch/riscv/lib/image.c |7 +- .../sifive/unmatched/hifive-platform-i2c-eeprom.c | 23 +- board/sifive/unmatched/spl.c | 114 +- configs/sifive_unmatched_defconfig |4 - 8 files changed, 81 insertions(+), 1569 deletions(-) delete mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1.dts Best regards, Leo
Re: [PATCH 06/22] Makefile: Avoid rebuilding .dtb files each time
Hi Masahiro, On Sun, 18 Jul 2021 at 07:36, Masahiro Yamada wrote: > > On Sun, Jul 18, 2021 at 5:41 AM Simon Glass wrote: > > > > Drop the FORCE from the rule that builds .dtb files and let the normal > > dependency checking do its work. This should work correctly, at least > > for .dts files that don't use /include/. > > > > Signed-off-by: Simon Glass > > --- > > > > scripts/Makefile.lib | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > Applied to u-boot-dm, thanks! > > > I am no longer working on U-Boot, > but this patch is obviously wrong. > > if_changed_dep must always have FORCE > as the prerequisite. Thanks for the email. OK I found the documentation about this in Linux so will add it to U-Boot. > > If it is not working, you may miss adding > the objects to the 'targets'. > > Somebody had broken the build system? I'm not sure, but let's drop this patch for now. Regards, Simon
Re: [PATCH 6/6] binman: Add basic support for debugging performance
One of binman's attributes is that it is extremely fast, at least for a Python program. Add some simple timing around operations that might take a while, such as reading an image and compressing it. This should help to maintain the performance as new features are added. This is for debugging purposes only. Signed-off-by: Simon Glass --- tools/binman/control.py| 3 ++ tools/binman/etype/blob.py | 5 +++ tools/binman/ftest.py | 8 + tools/binman/state.py | 72 ++ 4 files changed, 88 insertions(+) Applied to u-boot-dm, thanks!
Re: [PATCH 1/6] binman: Put compressed data into separate files
At present compression uses the same temporary file for all invocations. With multithreading this causes the data to become corrupted. Use a different filename each time. Signed-off-by: Simon Glass --- tools/patman/tools.py | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) Applied to u-boot-dm, thanks!
Re: [PATCH 1/1] sandbox: don't set SA_NODEFER in signal handler
Hi Heinrich, On Wed, 7 Jul 2021 at 11:37, Simon Glass wrote: > > Hi Heinrich, > > On Mon, 5 Jul 2021 at 11:43, Heinrich Schuchardt wrote: > > > > The sandbox can handle signals. Due to a damaged global data pointer > > additional exceptions in the signal handler may occur leading to an endless > > loop. In this case leave the handling of the secondary exception to the > > operating system. > > > > Signed-off-by: Heinrich Schuchardt > > --- > > arch/sandbox/cpu/os.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > I'm OK with this since it doesn't actually matter, now that the > signal-catching behaviour is optional. > > But as I understand it, it will mean that the second exception is > reported, but not the first? In other words, any core dump will be > 'incorrect' in that it is not suitable for postmortem debugging. I tested this by: - setting sandbox's 'state' pointer to NULL in the 'md' command - dropping state = &main_state from state_uninit - running it and typing 'md' This causes a recursive crash without your patch. With your patch it is not recursive. So I think it makes the -S option work better. Reviewed-by: Simon Glass Regards, Simon Applied to u-boot-dm, thanks!
Re: [PATCH 2/6] binman: Support multithreading for building images
Some images may take a while to build, e.g. if they are large and use slow compression. Support compiling sections in parallel to speed things up. Signed-off-by: Simon Glass --- tools/binman/binman.rst | 18 ++ tools/binman/cmdline.py | 4 tools/binman/control.py | 4 tools/binman/etype/section.py | 36 --- tools/binman/ftest.py | 33 tools/binman/image.py | 3 +++ tools/binman/state.py | 23 ++ 7 files changed, 114 insertions(+), 7 deletions(-) Applied to u-boot-dm, thanks!
Re: [PATCH 3/6] binman: Split node-reading out from constructor in files
The constructor should not read the node information. Move it to the ReadNode() method instead. This allows this etype to be subclassed. Signed-off-by: Simon Glass --- tools/binman/etype/files.py | 3 +++ 1 file changed, 3 insertions(+) Applied to u-boot-dm, thanks!
Re: [PATCH 4/6] binman: Use bytearray instead of string
This is faster if data is being concatenated. Update the section and collection etypes. Signed-off-by: Simon Glass --- tools/binman/etype/collection.py | 2 +- tools/binman/etype/section.py| 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) Applied to u-boot-dm, thanks!
Re: [PATCH 5/6] patman: Use bytearray instead of string
If the process outputs a lot of data on stdout this can be quite slow, since the bytestring is regenerated each time. Use a bytearray instead. Signed-off-by: Simon Glass --- tools/patman/cros_subprocess.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Applied to u-boot-dm, thanks!
Re: [PATCH v3] dm: core: fix no null pointer detection in ofnode_get_addr_size_index()
On Mon, 12 Jul 2021 at 01:40, chenguanqiao wrote: > > From: Chen Guanqiao > > Fixed a defect of a null pointer being discovered by Coverity Scan: >CID 331544: Null pointer dereferences (REVERSE_INULL) >Null-checking "size" suggests that it may be null, but it has already been >dereferenced on all paths leading to the check. > > Signed-off-by: Chen Guanqiao > --- > v3: > Add this changelog. > > v2: > 1. Remove redundant return. > 2. apply patch to u-boot/next. > > drivers/core/ofnode.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Simon Glass Applied to u-boot-dm, thanks!
[PATCH v2] doc: Bring in Makefile documentation
U-Boot uses the Linux Kbuild build system. Add the associated documentation so that people can understand the Makefiles better. This is taken from Linux v5.12 Signed-off-by: Simon Glass --- Changes in v2: - Put the new entry in sorted order - Update text so that it shows up sorted in the htmldocs also doc/develop/index.rst |1 + doc/develop/makefiles.rst | 1675 + 2 files changed, 1676 insertions(+) create mode 100644 doc/develop/makefiles.rst diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 3edffbc6373..54e14dd77b5 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -13,6 +13,7 @@ Implementation driver-model/index global_data logging + makefiles menus uefi/index version diff --git a/doc/develop/makefiles.rst b/doc/develop/makefiles.rst new file mode 100644 index 000..37a7deaca92 --- /dev/null +++ b/doc/develop/makefiles.rst @@ -0,0 +1,1675 @@ += +Makefiles += + +Note: This document mostly applies to U-Boot so is included here even +though it refers to Linux. + +This document describes the Linux kernel Makefiles. + +.. Table of Contents + + === 1 Overview + === 2 Who does what + === 3 The kbuild files + --- 3.1 Goal definitions + --- 3.2 Built-in object goals - obj-y + --- 3.3 Loadable module goals - obj-m + --- 3.4 + --- 3.5 Library file goals - lib-y + --- 3.6 Descending down in directories + --- 3.7 Non-builtin vmlinux targets - extra-y + --- 3.8 Always built goals - always-y + --- 3.9 Compilation flags + --- 3.10 Dependency tracking + --- 3.11 Custom Rules + --- 3.12 Command change detection + --- 3.13 $(CC) support functions + --- 3.14 $(LD) support functions + --- 3.15 Script Invocation + + === 4 Host Program support + --- 4.1 Simple Host Program + --- 4.2 Composite Host Programs + --- 4.3 Using C++ for host programs + --- 4.4 Controlling compiler options for host programs + --- 4.5 When host programs are actually built + + === 5 Userspace Program support + --- 5.1 Simple Userspace Program + --- 5.2 Composite Userspace Programs + --- 5.3 Controlling compiler options for userspace programs + --- 5.4 When userspace programs are actually built + + === 6 Kbuild clean infrastructure + + === 7 Architecture Makefiles + --- 7.1 Set variables to tweak the build to the architecture + --- 7.2 Add prerequisites to archheaders + --- 7.3 Add prerequisites to archprepare + --- 7.4 List directories to visit when descending + --- 7.5 Architecture-specific boot images + --- 7.6 Building non-kbuild targets + --- 7.7 Commands useful for building a boot image + --- 7.8 + --- 7.9 Preprocessing linker scripts + --- 7.10 Generic header files + --- 7.11 Post-link pass + + === 8 Kbuild syntax for exported headers + --- 8.1 no-export-headers + --- 8.2 generic-y + --- 8.3 generated-y + --- 8.4 mandatory-y + + === 9 Kbuild Variables + === 10 Makefile language + === 11 Credits + === 12 TODO + +1 Overview +== + +The Makefiles have five parts:: + + Makefilethe top Makefile. + .config the kernel configuration file. + arch/$(SRCARCH)/Makefilethe arch Makefile. + scripts/Makefile.* common rules etc. for all kbuild Makefiles. + kbuild Makefilesexist in every subdirectory + +The top Makefile reads the .config file, which comes from the kernel +configuration process. + +The top Makefile is responsible for building two major products: vmlinux +(the resident kernel image) and modules (any module files). +It builds these goals by recursively descending into the subdirectories of +the kernel source tree. +The list of subdirectories which are visited depends upon the kernel +configuration. The top Makefile textually includes an arch Makefile +with the name arch/$(SRCARCH)/Makefile. The arch Makefile supplies +architecture-specific information to the top Makefile. + +Each subdirectory has a kbuild Makefile which carries out the commands +passed down from above. The kbuild Makefile uses information from the +.config file to construct various file lists used by kbuild to build +any built-in or modular targets. + +scripts/Makefile.* contains all the definitions/rules etc. that +are used to build the kernel based on the kbuild makefiles. + + +2 Who does what +=== + +People have four different relationships with the kernel Makefiles. + +*Users* are people who build kernels. These people type commands such as +"make menuconfig" or "make". They usually do not read or ed
bug in SPI on rk3399 devices
I am not sure if it impacts non rk3399 devices or not, but on at least rk3399 devices after https://source.denx.de/u-boot/u-boot/-/commit/346df7d4fa62afc578d820b3a18815eec765074f was applied installing u-boot into SPI flash results in an unbootable system. SPL loads and runs, u-boot.itb is not found and the boot hangs. I am looking into it but would appreciate more eyes on it. Dennis
[PATCH][RFC] image: fdt: Fix DT relocation handling with multiple DRAM banks with gap
The current implementation of boot_relocate_fdt() places DT at the
highest usable DRAM address, which is calculated as:
env_get_bootm_low() + env_get_bootm_mapsize()
which by default becomes gd->ram_base + gd->ram_size.
Systems like i.MX53 can have multiple DRAM banks with gap between them,
e.g. have DRAM at 0x7000-0x8fff and 0xb000-0xcfff , so
for them the calculated highest DRAM address is 0xafff, which is
exactly in the gap and thus not usable.
Fix this by iterating over all DRAM banks and tracking the remaining
amount of the total mapping size obtained from env_get_bootm_mapsize().
Limit the maximum LMB area size to each bank, to avoid using nonexistent
DRAM.
Signed-off-by: Marek Vasut
Cc: Heinrich Schuchardt
Cc: Simon Glass
Cc: Tom Rini
---
common/image-fdt.c | 40
1 file changed, 36 insertions(+), 4 deletions(-)
diff --git a/common/image-fdt.c b/common/image-fdt.c
index 327a8c4c395..2b199ffc2b1 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -157,8 +157,11 @@ int boot_relocate_fdt(struct lmb *lmb, char
**of_flat_tree, ulong *of_size)
{
void*fdt_blob = *of_flat_tree;
void*of_start = NULL;
+ u64 start, size, usable;
char*fdt_high;
+ ulong mapsize, low;
ulong of_len = 0;
+ int bank;
int err;
int disable_relocation = 0;
@@ -198,10 +201,39 @@ int boot_relocate_fdt(struct lmb *lmb, char
**of_flat_tree, ulong *of_size)
(void *)(ulong) lmb_alloc(lmb, of_len, 0x1000);
}
} else {
- of_start =
- (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
- env_get_bootm_mapsize()
- + env_get_bootm_low());
+ mapsize = env_get_bootm_mapsize();
+ low = env_get_bootm_low();
+ of_start = NULL;
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start = gd->bd->bi_dram[bank].start;
+ size = gd->bd->bi_dram[bank].size;
+
+ /* DRAM bank addresses are too low, skip it. */
+ if (start + size < low)
+ continue;
+
+ usable = min(size, (u64)mapsize);
+
+ /*
+* At least part of this DRAM bank is usable, try
+* using it for LMB allocation.
+*/
+ of_start =
+ (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
+ start + usable);
+ /* Allocation succeeded, use this block. */
+ if (of_start != NULL)
+ break;
+
+ /*
+* Reduce the mapping size in the next bank
+* by the size of attempt in current bank.
+*/
+ mapsize -= usable - max(start, (u64)low);
+ if (!mapsize)
+ break;
+ }
}
if (of_start == NULL) {
--
2.30.2
[PATCH] rk3399: Add basic support for helios64
From: Dennis Gilmore
This is a stripped down version of the vendor U-Boot patch by Aditya
Prayoga found in the armbian repository. This patch is enough to have
the 1G ethernet port, the micro SD card, eMMC, PCIe and UART. It sets
uart2 as the default outiput device. the defconfig file has been cleaned
up a lot from the vendor version.
The device tree file is from the for-next branch of linux-rockchip and
targeted for 5.15 needed for SPI, stdout-path, and tsadc enablement
Signed-off-by: Dennis Gilmore
---
arch/arm/dts/Makefile | 1 +
.../arm/dts/rk3399-kobol-helios64-u-boot.dtsi | 23 +
arch/arm/dts/rk3399-kobol-helios64.dts| 534 ++
arch/arm/mach-rockchip/rk3399/Kconfig | 17 +
board/kobol/helios64-rk3399/Kconfig | 17 +
board/kobol/helios64-rk3399/MAINTAINERS | 7 +
board/kobol/helios64-rk3399/Makefile | 5 +
board/kobol/helios64-rk3399/helios64.c| 262 +
board/kobol/helios64-rk3399/sys_otp.c | 253 +
board/kobol/helios64-rk3399/sys_otp.h | 15 +
board/pine64/rockpro64_rk3399/Kconfig | 2 +
configs/helios64-rk3399_defconfig | 114
include/configs/helios64-rk3399.h | 56 ++
13 files changed, 1306 insertions(+)
create mode 100644 arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-kobol-helios64.dts
create mode 100644 board/kobol/helios64-rk3399/Kconfig
create mode 100644 board/kobol/helios64-rk3399/MAINTAINERS
create mode 100644 board/kobol/helios64-rk3399/Makefile
create mode 100644 board/kobol/helios64-rk3399/helios64.c
create mode 100644 board/kobol/helios64-rk3399/sys_otp.c
create mode 100644 board/kobol/helios64-rk3399/sys_otp.h
create mode 100644 configs/helios64-rk3399_defconfig
create mode 100644 include/configs/helios64-rk3399.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9fb38682e6..2788d7dd7b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -124,6 +124,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
+ rk3399-kobol-helios64.dtb \
rk3399-khadas-edge.dtb \
rk3399-khadas-edge-captain.dtb \
rk3399-khadas-edge-v.dtb \
diff --git a/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi
b/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi
new file mode 100644
index 00..f534c14b13
--- /dev/null
+++ b/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Aditya Prayoga (adi...@kobol.io)
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &spiflash, &sdmmc,
&sdhci;
+ };
+
+ config {
+ u-boot,spl-payload-offset = <0x6>; /* @ 384KB */
+ };
+};
+
+&spi1 {
+ spiflash: flash@0 {
+ u-boot,dm-pre-reloc;
+ };
+};
diff --git a/arch/arm/dts/rk3399-kobol-helios64.dts
b/arch/arm/dts/rk3399-kobol-helios64.dts
new file mode 100644
index 00..63c7681843
--- /dev/null
+++ b/arch/arm/dts/rk3399-kobol-helios64.dts
@@ -0,0 +1,534 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Aditya Prayoga
+ */
+
+/*
+ * The Kobol Helios64 is a board designed to operate as a NAS and optionally
+ * ships with an enclosing that can host five 2.5" hard disks.
+ *
+ * See https://wiki.kobol.io/helios64/intro/ for further details.
+ */
+
+/dts-v1/;
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Kobol Helios64";
+ compatible = "kobol,helios64", "rockchip,rk3399";
+
+ aliases {
+ mmc0 = &sdmmc;
+ mmc1 = &sdhci;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi5 = &spi5;
+ };
+
+ avdd_0v9_s0: avdd-0v9-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd_0v9_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <90>;
+ regulator-max-microvolt = <90>;
+ vin-supply = <&vcc1v8_sys_s3>;
+ };
+
+ avdd_1v8_s0: avdd-1v8-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ vin-supply = <&vcc3v3_sys_s3>;
+ };
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+
[PATCH 1/1] arm: Finish migration of HAS_FSL_XHCI_USB
This symbol was largely migrated, except for one case. Update it. Cc: Priyanka Jain Signed-off-by: Tom Rini --- Note that include/configs/lx2160a_common.h isn't under any MAINTAINERS entry but should be. --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 -- include/configs/lx2160a_common.h | 1 - 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 9c58f69dbd0d..9cef363fbaab 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -58,6 +58,7 @@ config ARCH_LS1043A select ARM_ERRATA_855873 if !TFABOOT select FSL_LAYERSCAPE select FSL_LSCH2 + select HAS_FSL_XHCI_USB if USB_HOST select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -89,6 +90,7 @@ config ARCH_LS1046A select ARMV8_SET_SMPEN select FSL_LAYERSCAPE select FSL_LSCH2 + select HAS_FSL_XHCI_USB if USB_HOST select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -245,6 +247,7 @@ config ARCH_LX2160A bool select ARMV8_SET_SMPEN select FSL_LSCH3 + select HAS_FSL_XHCI_USB if USB_HOST select NXP_LSCH3_2 select SYS_HAS_SERDES select SYS_FSL_SRDS_1 @@ -642,9 +645,8 @@ config SPL_LDSCRIPT config HAS_FSL_XHCI_USB bool - default y if ARCH_LS1043A || ARCH_LS1046A help - For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use + For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use pins, select it when the pins are assigned to USB. config SYS_FSL_BOOTROM_BASE diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 1338ee3cda3b..8977ee9de23a 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -143,7 +143,6 @@ /* USB */ #ifdef CONFIG_USB_HOST -#define CONFIG_HAS_FSL_XHCI_USB #ifndef CONFIG_TARGET_LX2162AQDS #define CONFIG_USB_MAX_CONTROLLER_COUNT2 #endif -- 2.17.1
Re: [PATCH] Nokia RX-51: Update documentation about ext2/3/4
On Friday 18 June 2021 13:07:08 Tom Rini wrote:
> On Fri, Jun 18, 2021 at 03:28:44PM +0200, Pali Rohár wrote:
>
> > Since commit 25c5b6517854 ("Nokia RX-51: Do not try calling both ext2load
> > and ext4load") command ext4load is used for all ext2/3/4 fs variants.
> >
> > Signed-off-by: Pali Rohár
> > ---
> > doc/README.nokia_rx51 | 5 ++---
> > 1 file changed, 2 insertions(+), 3 deletions(-)
>
> Can you please convert this to rST and move it under doc/board/ ?
> Thanks!
Done, here is link to patch:
http://patchwork.ozlabs.org/project/uboot/patch/20210721212507.27145-1-p...@kernel.org/
[PATCH] Nokia RX-51: Convert documentation to rst format
Signed-off-by: Pali Rohár
---
board/nokia/rx51/MAINTAINERS | 2 +-
doc/board/index.rst | 1 +
doc/board/nokia/index.rst | 7 +
.../nokia/rx51.rst} | 142 +-
4 files changed, 83 insertions(+), 69 deletions(-)
create mode 100644 doc/board/nokia/index.rst
rename doc/{README.nokia_rx51 => board/nokia/rx51.rst} (32%)
diff --git a/board/nokia/rx51/MAINTAINERS b/board/nokia/rx51/MAINTAINERS
index 58b16bf9a95c..25f8b3c5a9ad 100644
--- a/board/nokia/rx51/MAINTAINERS
+++ b/board/nokia/rx51/MAINTAINERS
@@ -4,5 +4,5 @@ S: Maintained
F: board/nokia/rx51/
F: include/configs/nokia_rx51.h
F: configs/nokia_rx51_defconfig
-F: doc/README.nokia_rx51
+F: doc/board/nokia/rx51.rst
F: test/nokia_rx51_test.sh
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 747511f7ddd2..4c470abbac02 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -19,6 +19,7 @@ Board-specific doc
intel/index
kontron/index
microchip/index
+ nokia/index
rockchip/index
sifive/index
sipeed/index
diff --git a/doc/board/nokia/index.rst b/doc/board/nokia/index.rst
new file mode 100644
index ..fb0db2f34244
--- /dev/null
+++ b/doc/board/nokia/index.rst
@@ -0,0 +1,7 @@
+Nokia
+=
+
+.. toctree::
+ :maxdepth: 2
+
+ rx51
diff --git a/doc/README.nokia_rx51 b/doc/board/nokia/rx51.rst
similarity index 32%
rename from doc/README.nokia_rx51
rename to doc/board/nokia/rx51.rst
index e739b02088ea..c84fdcddf166 100644
--- a/doc/README.nokia_rx51
+++ b/doc/board/nokia/rx51.rst
@@ -1,6 +1,7 @@
-Board: Nokia RX-51 aka N900
+Nokia RX-51 aka N900
+
-This board definition results in a u-boot.bin which can be chainloaded
+This board definition results in a ``u-boot.bin`` which can be chainloaded
from NOLO in qemu or on a real N900. It does very little hardware config
because NOLO has already configured the board. Only needed is enabling
internal eMMC memory via twl4030 regulator which is not enabled by NOLO.
@@ -8,64 +9,64 @@ internal eMMC memory via twl4030 regulator which is not
enabled by NOLO.
NOLO is expecting a kernel image and will treat any image it finds in
onenand as such. This u-boot is intended to be flashed to the N900 like
a kernel. In order to transparently boot the original kernel, it will be
-appended to u-boot.bin at 0x4. NOLO will load the entire image into
+appended to ``u-boot.bin`` at 0x4. NOLO will load the entire image into
(random) memory and execute u-boot, which saves hw revision, boot reason
and boot mode ATAGs set by NOLO. Then the bootscripts will attempt to load
-uImage, zImage or boot.scr from a fat or ext2/3/4 filesystem on external
-SD card or internal eMMC memory. If this fails or keyboard is closed then
-the appended kernel image will be booted using some generated and some
-stored ATAGs (see boot order).
+``uImage``, ``zImage`` or ``boot.scr`` file from a fat or ext2/3/4 filesystem
+on external SD card or internal eMMC memory. If this fails or keyboard is
+closed then the appended kernel image will be booted using some generated
+and some stored ATAGs (see boot order).
For generating combined image of u-boot and kernel (either in uImage or zImage
-format) there is a simple script called u-boot-gen-combined. It is available in
-following repository:
+format) there is a simple script called ``u-boot-gen-combined``. It is
available
+in following repository:
- https://github.com/pali/u-boot-maemo
+ https://github.com/pali/u-boot-maemo
-To generate combined.bin image from u-boot.bin and kernel.bin (either uImage
-or zImage) use:
+To generate ``combined.bin`` image from ``u-boot.bin`` and ``kernel.bin``
+(either uImage or zImage format) use::
- sh u-boot-gen-combined u-boot.bin kernel.bin combined.bin
+ $ sh u-boot-gen-combined u-boot.bin kernel.bin combined.bin
Original Maemo Fremantle PR1.3 zImage kernel binary is available at:
-
http://repository.maemo.org/pool/maemo5.0/free/k/kernel/kernel_2.6.28-20103103+0m5_armel.deb
+
http://repository.maemo.org/pool/maemo5.0/free/k/kernel/kernel_2.6.28-20103103+0m5_armel.deb
-To unpack it (from DEB/AR, TAR and FIASCO) call commands:
+To unpack it (from DEB/AR, TAR and FIASCO) call commands::
- ar x kernel_2.6.28-20103103+0m5_armel.deb data.tar.gz
- tar -O -xf data.tar.gz ./boot/zImage-2.6.28-20103103+0m5.fiasco >
kernel_2.6.28-20103103+0m5.fiasco
- 0x -M kernel_2.6.28-20103103+0m5.fiasco -u
+ $ ar x kernel_2.6.28-20103103+0m5_armel.deb data.tar.gz
+ $ tar -O -xf data.tar.gz ./boot/zImage-2.6.28-20103103+0m5.fiasco >
kernel_2.6.28-20103103+0m5.fiasco
+ $ 0x -M kernel_2.6.28-20103103+0m5.fiasco -u
-Flashed image must start with 2 kB "NOLO!img" header which contains size of
-the image. Header consist of bytes "NOLO!img\x02\x00\x00\x00\x00\x00\x00\x00"
+Flashed image must start with 2 kB ``NOLO!img`` header which contains size of
Re: [PATCH] doc: Bring in Makefile documentation
Am 21. Juli 2021 22:56:58 MESZ schrieb Simon Glass : >U-Boot uses the Linux Kbuild build system. Add the associated >documentation so that people can understand the Makefiles better. > >This is taken from Linux v5.12 > >Signed-off-by: Simon Glass >--- > > doc/develop/index.rst |1 + > doc/develop/makefiles.rst | 1674 + > 2 files changed, 1675 insertions(+) > create mode 100644 doc/develop/makefiles.rst > >diff --git a/doc/develop/index.rst b/doc/develop/index.rst >index 3edffbc6373..c1bbca617c9 100644 >--- a/doc/develop/index.rst >+++ b/doc/develop/index.rst >@@ -16,6 +16,7 @@ Implementation >menus >uefi/index >version >+ makefiles I would prefer to keep the alphabetic order. Best regards Heinrich > > Debugging > - >diff --git a/doc/develop/makefiles.rst b/doc/develop/makefiles.rst >new file mode 100644 >index 000..c3b5b66992b >--- /dev/null >+++ b/doc/develop/makefiles.rst >@@ -0,0 +1,1674 @@ >+== >+Linux Kernel Makefiles >+== >+ >+Note: This document mostly applies to U-Boot so is included here. >+ >+This document describes the Linux kernel Makefiles. >+ >+.. Table of Contents >+ >+ === 1 Overview >+ === 2 Who does what >+ === 3 The kbuild files >+ --- 3.1 Goal definitions >+ --- 3.2 Built-in object goals - obj-y >+ --- 3.3 Loadable module goals - obj-m >+ --- 3.4 >+ --- 3.5 Library file goals - lib-y >+ --- 3.6 Descending down in directories >+ --- 3.7 Non-builtin vmlinux targets - extra-y >+ --- 3.8 Always built goals - always-y >+ --- 3.9 Compilation flags >+ --- 3.10 Dependency tracking >+ --- 3.11 Custom Rules >+ --- 3.12 Command change detection >+ --- 3.13 $(CC) support functions >+ --- 3.14 $(LD) support functions >+ --- 3.15 Script Invocation >+ >+ === 4 Host Program support >+ --- 4.1 Simple Host Program >+ --- 4.2 Composite Host Programs >+ --- 4.3 Using C++ for host programs >+ --- 4.4 Controlling compiler options for host programs >+ --- 4.5 When host programs are actually built >+ >+ === 5 Userspace Program support >+ --- 5.1 Simple Userspace Program >+ --- 5.2 Composite Userspace Programs >+ --- 5.3 Controlling compiler options for userspace programs >+ --- 5.4 When userspace programs are actually built >+ >+ === 6 Kbuild clean infrastructure >+ >+ === 7 Architecture Makefiles >+ --- 7.1 Set variables to tweak the build to the architecture >+ --- 7.2 Add prerequisites to archheaders >+ --- 7.3 Add prerequisites to archprepare >+ --- 7.4 List directories to visit when descending >+ --- 7.5 Architecture-specific boot images >+ --- 7.6 Building non-kbuild targets >+ --- 7.7 Commands useful for building a boot image >+ --- 7.8 >+ --- 7.9 Preprocessing linker scripts >+ --- 7.10 Generic header files >+ --- 7.11 Post-link pass >+ >+ === 8 Kbuild syntax for exported headers >+ --- 8.1 no-export-headers >+ --- 8.2 generic-y >+ --- 8.3 generated-y >+ --- 8.4 mandatory-y >+ >+ === 9 Kbuild Variables >+ === 10 Makefile language >+ === 11 Credits >+ === 12 TODO >+ >+1 Overview >+== >+ >+The Makefiles have five parts:: >+ >+ Makefilethe top Makefile. >+ .config the kernel configuration file. >+ arch/$(SRCARCH)/Makefilethe arch Makefile. >+ scripts/Makefile.* common rules etc. for all kbuild >Makefiles. >+ kbuild Makefilesexist in every subdirectory >+ >+The top Makefile reads the .config file, which comes from the kernel >+configuration process. >+ >+The top Makefile is responsible for building two major products: >vmlinux >+(the resident kernel image) and modules (any module files). >+It builds these goals by recursively descending into the >subdirectories of >+the kernel source tree. >+The list of subdirectories which are visited depends upon the kernel >+configuration. The top Makefile textually includes an arch Makefile >+with the name arch/$(SRCARCH)/Makefile. The arch Makefile supplies >+architecture-specific information to the top Makefile. >+ >+Each subdirectory has a kbuild Makefile which carries out the commands >+passed down from above. The kbuild Makefile uses information from the >+.config file to construct various file lists used by kbuild to build >+any built-in or modular targets. >+ >+scripts/Makefile.* contains all the definitions/rules etc. that >+are used to build the kernel based on the kbuild makefiles. >+ >+ >+2 Who does what >+=== >+ >+People have four different relationships with the kernel Makefiles. >+ >+*Users* are people who build kernels. These people type comm
[PATCH] doc: Bring in Makefile documentation
U-Boot uses the Linux Kbuild build system. Add the associated documentation so that people can understand the Makefiles better. This is taken from Linux v5.12 Signed-off-by: Simon Glass --- doc/develop/index.rst |1 + doc/develop/makefiles.rst | 1674 + 2 files changed, 1675 insertions(+) create mode 100644 doc/develop/makefiles.rst diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 3edffbc6373..c1bbca617c9 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -16,6 +16,7 @@ Implementation menus uefi/index version + makefiles Debugging - diff --git a/doc/develop/makefiles.rst b/doc/develop/makefiles.rst new file mode 100644 index 000..c3b5b66992b --- /dev/null +++ b/doc/develop/makefiles.rst @@ -0,0 +1,1674 @@ +== +Linux Kernel Makefiles +== + +Note: This document mostly applies to U-Boot so is included here. + +This document describes the Linux kernel Makefiles. + +.. Table of Contents + + === 1 Overview + === 2 Who does what + === 3 The kbuild files + --- 3.1 Goal definitions + --- 3.2 Built-in object goals - obj-y + --- 3.3 Loadable module goals - obj-m + --- 3.4 + --- 3.5 Library file goals - lib-y + --- 3.6 Descending down in directories + --- 3.7 Non-builtin vmlinux targets - extra-y + --- 3.8 Always built goals - always-y + --- 3.9 Compilation flags + --- 3.10 Dependency tracking + --- 3.11 Custom Rules + --- 3.12 Command change detection + --- 3.13 $(CC) support functions + --- 3.14 $(LD) support functions + --- 3.15 Script Invocation + + === 4 Host Program support + --- 4.1 Simple Host Program + --- 4.2 Composite Host Programs + --- 4.3 Using C++ for host programs + --- 4.4 Controlling compiler options for host programs + --- 4.5 When host programs are actually built + + === 5 Userspace Program support + --- 5.1 Simple Userspace Program + --- 5.2 Composite Userspace Programs + --- 5.3 Controlling compiler options for userspace programs + --- 5.4 When userspace programs are actually built + + === 6 Kbuild clean infrastructure + + === 7 Architecture Makefiles + --- 7.1 Set variables to tweak the build to the architecture + --- 7.2 Add prerequisites to archheaders + --- 7.3 Add prerequisites to archprepare + --- 7.4 List directories to visit when descending + --- 7.5 Architecture-specific boot images + --- 7.6 Building non-kbuild targets + --- 7.7 Commands useful for building a boot image + --- 7.8 + --- 7.9 Preprocessing linker scripts + --- 7.10 Generic header files + --- 7.11 Post-link pass + + === 8 Kbuild syntax for exported headers + --- 8.1 no-export-headers + --- 8.2 generic-y + --- 8.3 generated-y + --- 8.4 mandatory-y + + === 9 Kbuild Variables + === 10 Makefile language + === 11 Credits + === 12 TODO + +1 Overview +== + +The Makefiles have five parts:: + + Makefilethe top Makefile. + .config the kernel configuration file. + arch/$(SRCARCH)/Makefilethe arch Makefile. + scripts/Makefile.* common rules etc. for all kbuild Makefiles. + kbuild Makefilesexist in every subdirectory + +The top Makefile reads the .config file, which comes from the kernel +configuration process. + +The top Makefile is responsible for building two major products: vmlinux +(the resident kernel image) and modules (any module files). +It builds these goals by recursively descending into the subdirectories of +the kernel source tree. +The list of subdirectories which are visited depends upon the kernel +configuration. The top Makefile textually includes an arch Makefile +with the name arch/$(SRCARCH)/Makefile. The arch Makefile supplies +architecture-specific information to the top Makefile. + +Each subdirectory has a kbuild Makefile which carries out the commands +passed down from above. The kbuild Makefile uses information from the +.config file to construct various file lists used by kbuild to build +any built-in or modular targets. + +scripts/Makefile.* contains all the definitions/rules etc. that +are used to build the kernel based on the kbuild makefiles. + + +2 Who does what +=== + +People have four different relationships with the kernel Makefiles. + +*Users* are people who build kernels. These people type commands such as +"make menuconfig" or "make". They usually do not read or edit +any kernel Makefiles (or any other source files). + +*Normal developers* are people who work on features such as device +drivers,
[PATCH 1/2] fdt: Tidy up the code a bit with fdt addr
Clean up the code a little before changing it.
Signed-off-by: Simon Glass
---
cmd/fdt.c | 37 +
1 file changed, 13 insertions(+), 24 deletions(-)
diff --git a/cmd/fdt.c b/cmd/fdt.c
index f1e2fc2fd8b..5acc3ebaf33 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -115,26 +115,20 @@ static int do_fdt(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
if (argc < 2)
return CMD_RET_USAGE;
- /*
-* Set the address of the fdt
-*/
+ /* fdt addr: Set the address of the fdt */
if (strncmp(argv[1], "ad", 2) == 0) {
unsigned long addr;
int control = 0;
struct fdt_header *blob;
- /*
-* Set the address [and length] of the fdt.
-*/
+
+ /* Set the address [and length] of the fdt */
argc -= 2;
argv += 2;
-/* Temporary #ifdef - some archs don't have fdt_blob yet */
-#ifdef CONFIG_OF_CONTROL
if (argc && !strcmp(*argv, "-c")) {
control = 1;
argc--;
argv++;
}
-#endif
if (argc == 0) {
if (control)
blob = (struct fdt_header *)gd->fdt_blob;
@@ -160,22 +154,18 @@ static int do_fdt(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
if (argc >= 2) {
int len;
int err;
- /*
-* Optional new length
-*/
+
+ /* Optional new length */
len = simple_strtoul(argv[1], NULL, 16);
if (len < fdt_totalsize(blob)) {
- printf ("New length %d < existing length %d, "
- "ignoring.\n",
- len, fdt_totalsize(blob));
+ printf("New length %d < existing length %d,
ignoring\n",
+ len, fdt_totalsize(blob));
} else {
- /*
-* Open in place with a new length.
-*/
+ /* Open in place with a new length */
err = fdt_open_into(blob, blob, len);
if (err != 0) {
- printf ("libfdt fdt_open_into(): %s\n",
- fdt_strerror(err));
+ printf("libfdt fdt_open_into(): %s\n",
+ fdt_strerror(err));
}
}
}
@@ -184,10 +174,9 @@ static int do_fdt(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
}
if (!working_fdt) {
- puts(
- "No FDT memory address configured. Please configure\n"
- "the FDT address via \"fdt addr \" command.\n"
- "Aborting!\n");
+ puts("No FDT memory address configured. Please configure\n"
+"the FDT address via \"fdt addr \" command.\n"
+"Aborting!\n");
return CMD_RET_FAILURE;
}
--
2.32.0.402.g57bb445576-goog
[PATCH 2/2] fdt: Show the type of devicetree with fdt addr
It seems useful to show whether the address of the Control or Working
devicetree is being shown. Add support for this. Drop the confusing 0x
prefix since the command itself only accepts hex.
Signed-off-by: Simon Glass
---
cmd/fdt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/cmd/fdt.c b/cmd/fdt.c
index 5acc3ebaf33..baec05529ad 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -136,9 +136,10 @@ static int do_fdt(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
blob = working_fdt;
if (!blob || !fdt_valid(&blob))
return 1;
- printf("The address of the fdt is %#08lx\n",
+ printf("%s fdt: %08lx\n",
+ control ? "Control" : "Working",
control ? (ulong)map_to_sysmem(blob) :
- env_get_hex("fdtaddr", 0));
+ env_get_hex("fdtaddr", 0));
return 0;
}
--
2.32.0.402.g57bb445576-goog
Bootcount device-model I2C EEPROM partition
Hi,
I'm implementing device-model backed bootcount which uses I2C EEPROM chip. I've
found following device tree, which I'm replicating:
https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/imx53-ppd.dts
https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/imx53-ppd-uboot.dtsi
Here is the important code snippet from `imx53-ppd-uboot.dtsi`. As you can see,
the `bootcount` partition from eeprom is referenced as the `i2c-eeprom` device
in `bootcount` device.
/ {
bootcount {
compatible = "u-boot,bootcount-i2c-eeprom";
i2c-eeprom = <&bootcount>;
};
};
&eeprom {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
vpd@0 {
reg = <0 800>;
};
bootcount: bootcount@1022 {
reg = <1022 2>;
};
};
};
Here you can see my snippet from `imx7-colibri-u-boot.dtsi`, where that I have
to reference not the partition but the whole eeprom device, because otherwise
I'll get following error: "bootcount: could not get backing device".
/ {
bootcount {
compatible = "u-boot,bootcount-i2c-eeprom";
i2c-eeprom = <&eeprom>;
};
};
&eeprom {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootcount: bootcount@0 {
reg = <0 2>;
};
};
};
The question is what I'm missing? Why referencing the whole eeprom works, but
referencing a single partition not. Do you have any idea?
Thank you very much
Richard Forro
P.S. there is no problem with the definition of eeprom inside the
`imx7-colibri.dtsi` file. It is exactly the same as in `imx53-ppd.dts`.
&i2c4 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>;
scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
status = "okay";
eeprom: eeprom@50 {
compatible = "atmel,24c02"; /* our at34c02d is semi-compatible
*/
reg = <0x50>;
pagesize = <16>;
};
};
[PATCH] net: fsl-mc: fix logically dead code
The result of dpio_close() is actually taken into account.
Signed-off-by: Cosmin-Florin Aluchenesei
---
drivers/net/fsl-mc/mc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 972db4cf3a..914ec001ec 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2017-2018, 2020 NXP
+ * Copyright 2017-2018, 2020-2021 NXP
*/
#include
#include
@@ -1126,7 +1126,7 @@ static int dpio_exit(void)
goto err;
}
- dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+ err = dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
if (err < 0) {
printf("dpio_close() failed: %d\n", err);
goto err;
--
2.21.0
[PATCH] drivers: net: aquantia: fix unsigned compared against 0
Change the reg variable to not be unsigned so that we not get into an
unsigned compared against 0.
Signed-off-by: Cosmin-Florin Aluchenesei
---
drivers/net/phy/aquantia.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index 9061afa620..d3d35a75d0 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -3,7 +3,7 @@
* Aquantia PHY drivers
*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include
#include
@@ -554,8 +554,9 @@ int aquantia_config(struct phy_device *phydev)
int aquantia_startup(struct phy_device *phydev)
{
- u32 reg, speed;
+ u32 speed;
int i = 0;
+ int reg;
phydev->duplex = DUPLEX_FULL;
--
2.21.0
Re: [PATCH v2 3/3] sysreset: provide SBI based sysreset driver
On 7/21/21 12:33 PM, Heinrich Schuchardt wrote:
Provide sysreset driver using the SBI system reset extension.
Signed-off-by: Heinrich Schuchardt
---
v2:
remove a superfluous check in sbi_sysreset_request()
---
MAINTAINERS | 1 +
arch/riscv/cpu/cpu.c| 13 -
arch/riscv/include/asm/sbi.h| 1 +
arch/riscv/lib/sbi.c| 21 ++--
drivers/sysreset/Kconfig| 11
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_sbi.c | 96 +
lib/efi_loader/Kconfig | 2 +-
8 files changed, 140 insertions(+), 6 deletions(-)
create mode 100644 drivers/sysreset/sysreset_sbi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index a6b49b54b9..29ac9450f5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1012,6 +1012,7 @@ T:git
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
F:arch/riscv/
F:cmd/riscv/
F:doc/usage/sbi.rst
+F: drivers/sysreset/sysreset_sbi.c
F:drivers/timer/andes_plmt_timer.c
F:drivers/timer/sifive_clint_timer.c
F:tools/prelink-riscv.c
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c894ac10b5..8e49b6d736 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -138,7 +139,17 @@ int arch_cpu_init_dm(void)
int arch_early_init_r(void)
{
- return riscv_cpu_probe();
+ int ret;
+
+ ret = riscv_cpu_probe();
+ if (ret)
+ return ret;
+
+ if (IS_ENABLED(CONFIG_SYSRESET_SBI))
+ device_bind_driver(gd->dm_root, "sbi-sysreset",
+ "sbi-sysreset", NULL);
+
+ return 0;
}
/**
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 39d5a022e0..b702fca176 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -150,5 +150,6 @@ void sbi_set_timer(uint64_t stime_value);
long sbi_get_spec_version(void);
int sbi_get_impl_id(void);
int sbi_probe_extension(int ext);
+void sbi_srst_reset(unsigned long type, unsigned long reason);
#endif
diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
index 77845a73ca..8508041f2a 100644
--- a/arch/riscv/lib/sbi.c
+++ b/arch/riscv/lib/sbi.c
@@ -8,13 +8,14 @@
*/
#include
+#include
#include
#include
-struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
- unsigned long arg1, unsigned long arg2,
- unsigned long arg3, unsigned long arg4,
- unsigned long arg5)
+struct sbiret __efi_runtime sbi_ecall(int ext, int fid, unsigned long arg0,
+ unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5)
{
struct sbiret ret;
@@ -108,6 +109,18 @@ int sbi_probe_extension(int extid)
return -ENOTSUPP;
}
+/**
+ * sbi_srst_reset() - invoke system reset extension
+ *
+ * @type: type of reset
+ * @reason:reason for reset
+ */
+void __efi_runtime sbi_srst_reset(unsigned long type, unsigned long reason)
+{
+ sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
+ 0, 0, 0, 0);
+}
+
#ifdef CONFIG_SBI_V01
/**
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index ac77ffbc8b..e095951166 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -85,6 +85,17 @@ config SYSRESET_PSCI
Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware
must be running on your system.
+config SYSRESET_SBI
+ bool "Enable support for SBI System Reset"
+ depends on RISCV_SMODE && SBI_V02
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+ help
+ Enable system reset and poweroff via the SBI system reset extension.
+ If the SBI implementation provides the extension, is board specific.
+ The extension was introduced in version 0.3 of the SBI specification.
+ The SBI system reset driver supports the UEFI ResetSystem() service
+ at runtime.
+
config SYSRESET_SOCFPGA
bool "Enable support for Intel SOCFPGA family"
depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 ||
TARGET_SOCFPGA_ARRIA10)
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index de81c399d7..8e00be0779 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
+obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o
obj-$(C
Re: [PATCH v2 1/3] risv: add missing SBI extension definitions
On 7/21/21 12:33 PM, Heinrich Schuchardt wrote:
Add the System Reset Extension and the Hart State Management Extension
definitions.
Add missing RFENCE Extension enum values.
The SBI 0.1 extension constants are needed for for the sbi command. Remove
an #ifdef.
Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Signed-off-by: Heinrich Schuchardt
---
v2:
correct constants that were blindly copied from Linux
---
arch/riscv/include/asm/sbi.h | 36 ++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 53ca316180..39d5a022e0 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -12,7 +12,6 @@
#include
enum sbi_ext_id {
-#ifdef CONFIG_SBI_V01
SBI_EXT_0_1_SET_TIMER = 0x0,
SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
@@ -22,11 +21,12 @@ enum sbi_ext_id {
SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
SBI_EXT_0_1_SHUTDOWN = 0x8,
-#endif
SBI_EXT_BASE = 0x10,
SBI_EXT_TIME = 0x54494D45,
SBI_EXT_IPI = 0x735049,
SBI_EXT_RFENCE = 0x52464E43,
+ SBI_EXT_HSM = 0x48534D,
+ SBI_EXT_SRST = 0x53525354,
};
enum sbi_ext_base_fid {
@@ -51,6 +51,38 @@ enum sbi_ext_rfence_fid {
SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+};
+
+enum sbi_ext_hsm_fid {
+ SBI_EXT_HSM_HART_START = 0,
+ SBI_EXT_HSM_HART_STOP,
+ SBI_EXT_HSM_HART_STATUS,
+};
+
+enum sbi_hsm_hart_status {
+ SBI_HSM_HART_STATUS_STARTED = 0,
+ SBI_HSM_HART_STATUS_STOPPED,
+ SBI_HSM_HART_STATUS_START_PENDING,
+ SBI_HSM_HART_STATUS_STOP_PENDING,
Perhaps add the suspend states from
https://github.com/riscv/riscv-sbi-doc/pull/66
+};
+
+enum sbi_ext_srst_fid {
+ SBI_EXT_SRST_RESET = 0,
+};
+
+enum sbi_srst_reset_type {
+ SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
+ SBI_SRST_RESET_TYPE_COLD_REBOOT,
+ SBI_SRST_RESET_TYPE_WARM_REBOOT,
+};
+
+enum sbi_srst_reset_reason {
+ SBI_SRST_RESET_REASON_NONE = 0,
+ SBI_SRST_RESET_REASON_SYS_FAILURE,
};
#ifdef CONFIG_SBI_V01
--
2.30.2
Reviewed-by: Sean Anderson
[PATCH v2 3/3] sysreset: provide SBI based sysreset driver
Provide sysreset driver using the SBI system reset extension.
Signed-off-by: Heinrich Schuchardt
---
v2:
remove a superfluous check in sbi_sysreset_request()
---
MAINTAINERS | 1 +
arch/riscv/cpu/cpu.c| 13 -
arch/riscv/include/asm/sbi.h| 1 +
arch/riscv/lib/sbi.c| 21 ++--
drivers/sysreset/Kconfig| 11
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_sbi.c | 96 +
lib/efi_loader/Kconfig | 2 +-
8 files changed, 140 insertions(+), 6 deletions(-)
create mode 100644 drivers/sysreset/sysreset_sbi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index a6b49b54b9..29ac9450f5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1012,6 +1012,7 @@ T:git
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
F: arch/riscv/
F: cmd/riscv/
F: doc/usage/sbi.rst
+F: drivers/sysreset/sysreset_sbi.c
F: drivers/timer/andes_plmt_timer.c
F: drivers/timer/sifive_clint_timer.c
F: tools/prelink-riscv.c
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c894ac10b5..8e49b6d736 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -138,7 +139,17 @@ int arch_cpu_init_dm(void)
int arch_early_init_r(void)
{
- return riscv_cpu_probe();
+ int ret;
+
+ ret = riscv_cpu_probe();
+ if (ret)
+ return ret;
+
+ if (IS_ENABLED(CONFIG_SYSRESET_SBI))
+ device_bind_driver(gd->dm_root, "sbi-sysreset",
+ "sbi-sysreset", NULL);
+
+ return 0;
}
/**
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 39d5a022e0..b702fca176 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -150,5 +150,6 @@ void sbi_set_timer(uint64_t stime_value);
long sbi_get_spec_version(void);
int sbi_get_impl_id(void);
int sbi_probe_extension(int ext);
+void sbi_srst_reset(unsigned long type, unsigned long reason);
#endif
diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
index 77845a73ca..8508041f2a 100644
--- a/arch/riscv/lib/sbi.c
+++ b/arch/riscv/lib/sbi.c
@@ -8,13 +8,14 @@
*/
#include
+#include
#include
#include
-struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
- unsigned long arg1, unsigned long arg2,
- unsigned long arg3, unsigned long arg4,
- unsigned long arg5)
+struct sbiret __efi_runtime sbi_ecall(int ext, int fid, unsigned long arg0,
+ unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5)
{
struct sbiret ret;
@@ -108,6 +109,18 @@ int sbi_probe_extension(int extid)
return -ENOTSUPP;
}
+/**
+ * sbi_srst_reset() - invoke system reset extension
+ *
+ * @type: type of reset
+ * @reason:reason for reset
+ */
+void __efi_runtime sbi_srst_reset(unsigned long type, unsigned long reason)
+{
+ sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
+ 0, 0, 0, 0);
+}
+
#ifdef CONFIG_SBI_V01
/**
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index ac77ffbc8b..e095951166 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -85,6 +85,17 @@ config SYSRESET_PSCI
Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware
must be running on your system.
+config SYSRESET_SBI
+ bool "Enable support for SBI System Reset"
+ depends on RISCV_SMODE && SBI_V02
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+ help
+ Enable system reset and poweroff via the SBI system reset extension.
+ If the SBI implementation provides the extension, is board specific.
+ The extension was introduced in version 0.3 of the SBI specification.
+ The SBI system reset driver supports the UEFI ResetSystem() service
+ at runtime.
+
config SYSRESET_SOCFPGA
bool "Enable support for Intel SOCFPGA family"
depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 ||
TARGET_SOCFPGA_ARRIA10)
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index de81c399d7..8e00be0779 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
+obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o
obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
diff --git a/drivers/sysreset/sysreset_sbi.c
[PATCH v2 0/3] riscv: enable SBI system reset
The purpose of this series is to provide the UEFI ResetSystem() service at runtime on RISC-V systems. With SBI v0.3 a system reset extension is available. This allows to implement reboot and poweroff in U-Boot in a system independent way. * Provide a system reset driver using the system reset extension. v2: correct constants in patch 1 which were copied from incorrect Linux avoid a superfluous check in the sysreset driver drop K210 specific patches which need further work Heinrich Schuchardt (3): risv: add missing SBI extension definitions cmd/sbi: use constants instead of numerical values sysreset: provide SBI based sysreset driver MAINTAINERS | 1 + arch/riscv/cpu/cpu.c| 13 - arch/riscv/include/asm/sbi.h| 37 - arch/riscv/lib/sbi.c| 21 ++-- cmd/riscv/sbi.c | 30 +-- drivers/sysreset/Kconfig| 11 drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_sbi.c | 96 + lib/efi_loader/Kconfig | 2 +- 9 files changed, 189 insertions(+), 23 deletions(-) create mode 100644 drivers/sysreset/sysreset_sbi.c -- 2.30.2
[PATCH v2 1/3] risv: add missing SBI extension definitions
Add the System Reset Extension and the Hart State Management Extension
definitions.
Add missing RFENCE Extension enum values.
The SBI 0.1 extension constants are needed for for the sbi command. Remove
an #ifdef.
Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Signed-off-by: Heinrich Schuchardt
---
v2:
correct constants that were blindly copied from Linux
---
arch/riscv/include/asm/sbi.h | 36 ++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 53ca316180..39d5a022e0 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -12,7 +12,6 @@
#include
enum sbi_ext_id {
-#ifdef CONFIG_SBI_V01
SBI_EXT_0_1_SET_TIMER = 0x0,
SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
@@ -22,11 +21,12 @@ enum sbi_ext_id {
SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
SBI_EXT_0_1_SHUTDOWN = 0x8,
-#endif
SBI_EXT_BASE = 0x10,
SBI_EXT_TIME = 0x54494D45,
SBI_EXT_IPI = 0x735049,
SBI_EXT_RFENCE = 0x52464E43,
+ SBI_EXT_HSM = 0x48534D,
+ SBI_EXT_SRST = 0x53525354,
};
enum sbi_ext_base_fid {
@@ -51,6 +51,38 @@ enum sbi_ext_rfence_fid {
SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+};
+
+enum sbi_ext_hsm_fid {
+ SBI_EXT_HSM_HART_START = 0,
+ SBI_EXT_HSM_HART_STOP,
+ SBI_EXT_HSM_HART_STATUS,
+};
+
+enum sbi_hsm_hart_status {
+ SBI_HSM_HART_STATUS_STARTED = 0,
+ SBI_HSM_HART_STATUS_STOPPED,
+ SBI_HSM_HART_STATUS_START_PENDING,
+ SBI_HSM_HART_STATUS_STOP_PENDING,
+};
+
+enum sbi_ext_srst_fid {
+ SBI_EXT_SRST_RESET = 0,
+};
+
+enum sbi_srst_reset_type {
+ SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
+ SBI_SRST_RESET_TYPE_COLD_REBOOT,
+ SBI_SRST_RESET_TYPE_WARM_REBOOT,
+};
+
+enum sbi_srst_reset_reason {
+ SBI_SRST_RESET_REASON_NONE = 0,
+ SBI_SRST_RESET_REASON_SYS_FAILURE,
};
#ifdef CONFIG_SBI_V01
--
2.30.2
[PATCH v2 2/3] cmd/sbi: use constants instead of numerical values
Use constants for extension IDs.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Sean Anderson
Reviewed-by: Leo Yu-Chi Liang
---
v2:
no change
---
cmd/riscv/sbi.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index 90c0811e14..65a2c93290 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -29,21 +29,21 @@ static struct sbi_imp implementations[] = {
};
static struct sbi_ext extensions[] = {
- { 0x, "sbi_set_timer" },
- { 0x0001, "sbi_console_putchar" },
- { 0x0002, "sbi_console_getchar" },
- { 0x0003, "sbi_clear_ipi" },
- { 0x0004, "sbi_send_ipi" },
- { 0x0005, "sbi_remote_fence_i" },
- { 0x0006, "sbi_remote_sfence_vma" },
- { 0x0007, "sbi_remote_sfence_vma_asid" },
- { 0x0008, "sbi_shutdown" },
- { 0x0010, "SBI Base Functionality" },
- { 0x54494D45, "Timer Extension" },
- { 0x00735049, "IPI Extension" },
- { 0x52464E43, "RFENCE Extension" },
- { 0x0048534D, "Hart State Management Extension" },
- { 0x53525354, "System Reset Extension" },
+ { SBI_EXT_0_1_SET_TIMER, "sbi_set_timer" },
+ { SBI_EXT_0_1_CONSOLE_PUTCHAR,"sbi_console_putchar" },
+ { SBI_EXT_0_1_CONSOLE_GETCHAR,"sbi_console_getchar" },
+ { SBI_EXT_0_1_CLEAR_IPI, "sbi_clear_ipi" },
+ { SBI_EXT_0_1_SEND_IPI, "sbi_send_ipi" },
+ { SBI_EXT_0_1_REMOTE_FENCE_I, "sbi_remote_fence_i" },
+ { SBI_EXT_0_1_REMOTE_SFENCE_VMA, "sbi_remote_sfence_vma" },
+ { SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, "sbi_remote_sfence_vma_asid" },
+ { SBI_EXT_0_1_SHUTDOWN, "sbi_shutdown" },
+ { SBI_EXT_BASE, "SBI Base Functionality" },
+ { SBI_EXT_TIME, "Timer Extension" },
+ { SBI_EXT_IPI,"IPI Extension" },
+ { SBI_EXT_RFENCE, "RFENCE Extension" },
+ { SBI_EXT_HSM,"Hart State Management Extension"
},
+ { SBI_EXT_SRST, "System Reset Extension" },
};
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
--
2.30.2
Re: [PATCH RESEND u-boot-spi 0/8] Fix `mtd erase` when used with mtdpart
Hi Marek, On Thu, Jul 15, 2021 at 5:21 AM Marek Behún wrote: > > Hello, > > I accidentally forgot to send this series to U-Boot's mailing list last > time, meaning it did not end up in patchwork, so now I am resending it. > Sorry for this mess. > > The original cover letter said: > > this patch series fixes the `mtd erase` command when used with mtdpart > with a partition of non-zero offset. > > Currently when the `mtd erase` command is used for such a partition, > it does not erase all blocks. Instead after a block is erased, the next > block address not current block address + block size, but current block > address + block size + partition offset, due to spi_nor_erase() not > calling mtd_erase_callback(): > => mtd erase "Rescue system" > Erasing 0x ... 0x006f (1792 eraseblock(s)) > jedec_spi_nor spi-nor@0: at 0x10, len 4096 > jedec_spi_nor spi-nor@0: at 0x201000, len 4096 > jedec_spi_nor spi-nor@0: at 0x302000, len 4096 > jedec_spi_nor spi-nor@0: at 0x403000, len 4096 > jedec_spi_nor spi-nor@0: at 0x504000, len 4096 > jedec_spi_nor spi-nor@0: at 0x605000, len 4096 > jedec_spi_nor spi-nor@0: at 0x706000, len 4096 > > This series adds some fixes to spi_nor_erase() function, then adds > calling of mtd_erase_callback() to fix this bug. > > The series also contains an improvement - adding the posibility to > interrupt spi_nor_erase() with Ctrl+C; and another one - making mtdpart's > _erase() method more sane so that the above mentioned bug will not occur > even if underlying driver does not call mtd_erase_callback(). > > Moreover I would also like to start a discussion regarding the MTD > subsystem: > - U-Boot's MTD subsystem is based on Linux's, with many #ifdef __U_BOOT__ > macros > - this was done to make it easier to port Linux's patches to U-Boot > - the problem is that it seems nobody did port Linux's MTD patches to > U-Boot for a long time, the code is many times different from Linux', > and it would be very hard to align it > - therefore I propose to get rid of all the #ifdefs, remove the Linux > specific code, and continue developing the code independently from > Linux. This would make it impossible to apply Linux patches in some > kind of automatic way, but this is currently already impossible > anyway > What do you guys think? > > Marek > > Marek Behún (8): > mtd: spi-nor-core: Try cleaning up in case writing BAR failed > mtd: spi-nor-core: Check return value of write_enable() in > spi_nor_erase() > mtd: spi-nor-core: Don't overwrite return value if it is non-zero > mtd: spi-nor-core: Check return value of write_disable() in > spi_nor_erase() > mtd: spi-nor-core: Don't check for zero length in spi_nor_erase() > mtd: spi-nor-core: Call mtd_erase_callback() from spi_nor_erase() > mtd: spi-nor-core: Check for ctrlc() in spi_nor_erase() > mtd: mtdpart: Make mtdpart's _erase method sane Found the build error with CI [1], would you please check? [1] https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/8345 Jagan.
[PATCH v5 19/20] doc: board: Move j721e document to doc/board/ti/ directory
Move j721e document from board/ti/j721e/README to doc/board/ti/j721e_evm.rst after converting it to RST format. Signed-off-by: Kishon Vijay Abraham I --- board/ti/j721e/README | 277 doc/board/index.rst| 1 + doc/board/ti/j721e_evm.rst | 316 + 3 files changed, 317 insertions(+), 277 deletions(-) delete mode 100644 board/ti/j721e/README create mode 100644 doc/board/ti/j721e_evm.rst diff --git a/board/ti/j721e/README b/board/ti/j721e/README deleted file mode 100644 index b1c9145c92..00 --- a/board/ti/j721e/README +++ /dev/null @@ -1,277 +0,0 @@ -Introduction: -- -The J721e family of SoCs are part of K3 Multicore SoC architecture platform -targeting automotive applications. They are designed as a low power, high -performance and highly integrated device architecture, adding significant -enhancement on processing power, graphics capability, video and imaging -processing, virtualization and coherent memory support. - -The device is partitioned into three functional domains, each containing -specific processing cores and peripherals: -1. Wake-up (WKUP) domain: - - Device Management and Security Controller (DMSC) -2. Microcontroller (MCU) domain: - - Dual Core ARM Cortex-R5F processor -3. MAIN domain: - - Dual core 64-bit ARM Cortex-A72 - - 2 x Dual cortex ARM Cortex-R5 subsystem - - 2 x C66x Digital signal processor sub system - - C71x Digital signal processor sub-system with MMA. - -More info can be found in TRM: http://www.ti.com/lit/pdf/spruil1 - -Boot Flow: --- -Boot flow is similar to that of AM65x SoC and extending it with remoteproc -support. Below is the pictorial representation of boot flow: - -++---+ -|DMSC| MCU R5 |A72| MAIN R5/C66x/C7x | -++---+ -|++ | | | | -|| Reset | | | | | -|++ | | | | -| : | | | | -|++ | +---+ | | | -|| *ROM* |--|-->| Reset rls | | | | -|++ | +---+ | | | -||| | : | | | -|| ROM | | : | | | -||services| | : | | | -||| | +-+ | | | -||| | | *R5 ROM* | | | | -||| | +-+ | | | -|||<-|---|Load and auth| | | | -||| | | tiboot3.bin | | | | -||| | +-+ | | | -||| | : | | | -||| | : | | | -||| | : | | | -||| | +-+ | | | -||| | | *R5 SPL* | | | | -||| | +-+ | | | -||| | |Load | | | | -||| | | sysfw.itb | | | | -|| Start | | +-+ | | | -|| System |<-|---|Start| | | | -||Firmware| | |SYSFW| | | | -|++ | +-+ | | | -|: | | | | |
[PATCH v5 20/20] doc: board: j721e_evm: Add documentation for firmware loading
Add documentation for loading firmwares to be used by remote cores in the system including the environment variables that has to be set to load the firmwares. Signed-off-by: Kishon Vijay Abraham I --- doc/board/ti/j721e_evm.rst | 15 +++ 1 file changed, 15 insertions(+) diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst index 8b460709d1..44dc316afd 100644 --- a/doc/board/ti/j721e_evm.rst +++ b/doc/board/ti/j721e_evm.rst @@ -314,3 +314,18 @@ Flash layout for OSPI: | ospi.rootfs(UBIFS) | || ++ + +Firmwares: +-- + +The J721e u-boot allows firmware to be loaded for the Cortex-R5 subsystem. +The CPSW5G in J7200 and CPSW9G in J721E present in MAIN domain is configured +and controlled by the ethernet firmware that executes in the MAIN Cortex R5. +The default supported environment variables support loading these firmwares +from only MMC. "dorprocboot" env variable has to be set for the U-BOOT to load +and start the remote cores in the system. + +J721E common processor board can be attached to a Ethernet QSGMII card and the +PHY in the card has to be reset before it can be used for data transfer. +"do_main_cpsw0_qsgmii_phyinit" env variable has to be set for the U-BOOT to +configure this PHY. -- 2.17.1
[PATCH v5 16/20] configs: j7200_evm_a72_defconfig: Add config for torrent serdes and common clock framework
From: Aswath Govindraju Add config for torrent serdes and common clock framework. Signed-off-by: Aswath Govindraju Signed-off-by: Kishon Vijay Abraham I --- configs/j7200_evm_a72_defconfig | 7 +++ 1 file changed, 7 insertions(+) diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index b0cde842dd..4132d8e2b5 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -96,6 +96,7 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_CLK_CCF=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y @@ -137,9 +138,15 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_MULTIPLEXER=y +CONFIG_MUX_MMIO=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_PHY_CADENCE_TORRENT=y +CONFIG_PHY_J721E_WIZ=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y -- 2.17.1
[PATCH v5 18/20] configs: j7200_evm_a72: Add CONFIG_PREBOOT to configure ethernet PHY
Add CONFIG_PREBOOT to provide an automatic and easier way
to configure ethernet PHY before loading the firmware.
Signed-off-by: Kishon Vijay Abraham I
---
configs/j7200_evm_a72_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 4132d8e2b5..a68cbb0a97 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -30,6 +30,7 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
+CONFIG_PREBOOT="run main_cpsw0_qsgmii_phyinit;"
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
--
2.17.1
[PATCH v5 17/20] env: ti: j721e-evm: Add env variable to power on & reset QSGMII PHY in J7200 EVM
MAIN CPSW0 requires the PHY to be powered on and reset for QSGMII
operation. Add a env variable to configure driving "0" on ENET_EXP_PWRDN
controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 17 and driving "1"
on ENET_EXP_RESETZ controlled by GPIO EXPANDER2 (I2C Addr: 0x22),
PIN: 18.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Suman Anna
---
include/configs/j721e_evm.h | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index b707fc4e89..00d0a18a68 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -139,11 +139,24 @@
#endif /* CONFIG_TARGET_J721E_A72_EVM */
#ifdef CONFIG_TARGET_J7200_A72_EVM
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
+ "do_main_cpsw0_qsgmii_phyinit=1\0" \
+ "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
+"gpio clear gpio@22_16\0" \
+ "main_cpsw0_qsgmii_phyinit="\
+ "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot}
-eq 1 && " \
+ "test ${boot} = mmc; then " \
+ "run init_main_cpsw0_qsgmii_phy;" \
+ "fi;\0"
#define DEFAULT_RPROCS "" \
"2 /lib/firmware/j7200-main-r5f0_0-fw " \
"3 /lib/firmware/j7200-main-r5f0_1-fw "
#endif /* CONFIG_TARGET_J7200_A72_EVM */
+#ifndef EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
+#endif
+
/* set default dfu_bufsiz to 128KB (sector size of OSPI) */
#define EXTRA_ENV_DFUARGS \
"dfu_bufsiz=0x2\0" \
@@ -170,7 +183,8 @@
EXTRA_ENV_RPROC_SETTINGS\
EXTRA_ENV_DFUARGS \
DEFAULT_UFS_TI_ARGS \
- EXTRA_ENV_J721E_BOARD_SETTINGS_MTD
+ EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \
+ EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
/* Now for the remaining common defines */
#include
--
2.17.1
[PATCH v5 15/20] configs: j721e_evm_a72_defconfig: Enable the drivers required for the USB3 support
From: Jean-Jacques Hiblot Enable the mmio mux driver, the J721E-wiz PHy driver and the cadence sierra phy driver. All of them are required for USB3 support Signed-off-by: Jean-Jacques Hiblot Signed-off-by: Vignesh Raghavendra Signed-off-by: Kishon Vijay Abraham I --- configs/j721e_evm_a72_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 365d662690..e2b0270ef9 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -135,9 +135,15 @@ CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_TI_DP83867=y +CONFIG_MULTIPLEXER=y +CONFIG_MUX_MMIO=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_PHY_CADENCE_SIERRA=y +CONFIG_PHY_J721E_WIZ=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y -- 2.17.1
[PATCH v5 08/20] phy: cadence: Add driver for Torrent SERDES
From: Aswath Govindraju Add driver for Torrent SERDES. Signed-off-by: Aswath Govindraju Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/Kconfig |6 + drivers/phy/cadence/Makefile |1 + drivers/phy/cadence/phy-cadence-torrent.c | 2463 + 3 files changed, 2470 insertions(+) create mode 100644 drivers/phy/cadence/phy-cadence-torrent.c diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index 18a04819f5..549ddbf504 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -3,3 +3,9 @@ config PHY_CADENCE_SIERRA depends on DM_RESET help Enable this to support the Cadence Sierra PHY driver + +config PHY_CADENCE_TORRENT + tristate "Cadence Torrent PHY Driver" + depends on DM_RESET + help + Enable this to support the Cadence Torrent PHY driver diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile index d57856152a..af63b32d9f 100644 --- a/drivers/phy/cadence/Makefile +++ b/drivers/phy/cadence/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_$(SPL_)PHY_CADENCE_SIERRA)+= phy-cadence-sierra.o +obj-$(CONFIG_$(SPL_)PHY_CADENCE_TORRENT) += phy-cadence-torrent.o diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c new file mode 100644 index 00..141ece479f --- /dev/null +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -0,0 +1,2463 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cadence Torrent SD0801 PHY driver. + * + * Based on the linux driver provided by Cadence + * + * Copyright (c) 2018 Cadence Design Systems + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define REF_CLK_19_2MHz1920 +#define REF_CLK_25MHz 2500 + +#define MAX_NUM_LANES 4 +#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps*/ + +#define NUM_SSC_MODE 3 +#define NUM_PHY_TYPE 6 + +#define POLL_TIMEOUT_US5000 +#define PLL_LOCK_TIMEOUT 10 + +#define TORRENT_COMMON_CDB_OFFSET 0x0 + +#define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ + ((0x4000 << (block_offset)) + \ + (((ln) << 9) << (reg_offset))) +#define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ + ((0x8000 << (block_offset)) + \ + (((ln) << 9) << (reg_offset))) + +#define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset)\ + (0xC000 << (block_offset)) + +#define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset)\ + (0xE000 << (block_offset)) + +/* + * register offsets from SD0801 PHY register block base (i.e MHDP + * register base + 0x50) + */ +#define CMN_SSM_BANDGAP_TMR0x0021U +#define CMN_SSM_BIAS_TMR 0x0022U +#define CMN_PLLSM0_PLLPRE_TMR 0x002AU +#define CMN_PLLSM0_PLLLOCK_TMR 0x002CU +#define CMN_PLLSM1_PLLPRE_TMR 0x0032U +#define CMN_PLLSM1_PLLLOCK_TMR 0x0034U +#define CMN_CDIAG_CDB_PWRI_OVRD0x0041U +#define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U +#define CMN_BGCAL_INIT_TMR 0x0064U +#define CMN_BGCAL_ITER_TMR 0x0065U +#define CMN_IBCAL_INIT_TMR 0x0074U +#define CMN_PLL0_VCOCAL_TCTRL 0x0082U +#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U +#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U +#define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U +#define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U +#define CMN_PLL0_INTDIV_M0 0x0090U +#define CMN_PLL0_FRACDIVL_M0 0x0091U +#define CMN_PLL0_FRACDIVH_M0 0x0092U +#define CMN_PLL0_HIGH_THR_M0 0x0093U +#define CMN_PLL0_DSM_DIAG_M0 0x0094U +#define CMN_PLL0_SS_CTRL1_M0 0x0098U +#define CMN_PLL0_SS_CTRL2_M0 0x0099U +#define CMN_PLL0_SS_CTRL3_M0 0x009AU +#define CMN_PLL0_SS_CTRL4_M0 0x009BU +#define CMN_PLL0_LOCK_REFCNT_START 0x009CU +#define CMN_PLL0_LOCK_PLLCNT_START 0x009EU +#define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU +#define CMN_PLL0_INTDIV_M1 0x00A0U +#define CMN_PLL0_FRACDIVH_M1 0x00A2U +#define CMN_PLL0_HIGH_THR_M1 0x00A3U +#define CMN_PLL0_DSM_DIAG_M1 0x00A4U +#define CMN_PLL0_SS_CTRL1_M1 0x00A8U +#define CMN_PLL0_SS_CTRL2_M1 0x00A9U +#define CMN_PLL0_SS_CTRL3_M1 0x00AAU +#define CMN_PLL0_SS_CTRL4_M1 0x00ABU +#define CMN_PLL1_VCOCAL_TCTRL 0x00C2U +#define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U +#define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U +#define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U +#def
[PATCH v5 14/20] arm: dts: k3-j7200-common-proc-board-u-boot: Add u-boot tags for torrent serdes
From: Aswath Govindraju
Add u-boot tags for torrent serdes. This has properties specific to
u-boot on top of DT in v5.13 Linux Kernel.
Signed-off-by: Aswath Govindraju
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index 786cc48050..8a3f1891e2 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -188,3 +188,15 @@
&hbmc_mux {
u-boot,dm-spl;
};
+
+&serdes_ln_ctrl {
+ u-boot,mux-autoprobe;
+};
+
+&usb_serdes_mux {
+ u-boot,mux-autoprobe;
+};
+
+&serdes0 {
+ u-boot,dm-spl;
+};
--
2.17.1
[PATCH v5 13/20] arm: dts: k3-j7200-common-proc-board: Enable SERDES DT
From: Aswath Govindraju
Add default lane function for torrent serdes. This is in sync
with v5.13 Linux Kernel.
Signed-off-by: Aswath Govindraju
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/dts/k3-j7200-common-proc-board.dts | 23 +
1 file changed, 23 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts
b/arch/arm/dts/k3-j7200-common-proc-board.dts
index 5120711d4f..f0440cda1a 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
/ {
chosen {
@@ -281,3 +282,25 @@
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
+
+&serdes_refclk {
+ clock-frequency = <1>;
+};
+
+&serdes0 {
+ serdes0_pcie_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = ;
+ resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+ };
+
+ serdes0_qsgmii_link: link@1 {
+ reg = <2>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = ;
+ resets = <&serdes_wiz0 3>;
+ };
+};
--
2.17.1
[PATCH v5 12/20] arm: dts: k3-j7200-main: Add DT node for torrent serdes
From: Aswath Govindraju
Add DT node for torrent serdes. This is in sync with v5.13 Linux Kernel.
Signed-off-by: Aswath Govindraju
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/dts/k3-j7200-main.dtsi | 63 +
1 file changed, 63 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index 1131464075..138702cf9d 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -5,6 +5,13 @@
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
+/ {
+ serdes_refclk: serdes-refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+};
+
&cbass_main {
msmc_ram: sram@7000 {
compatible = "mmio-sram";
@@ -554,6 +561,62 @@
clock-names = "gpio";
};
+ serdes_wiz0: wiz@506 {
+ compatible = "ti,j721e-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ ranges = <0x506 0x0 0x506 0x1>;
+
+ assigned-clocks = <&k3_clks 292 85>;
+ assigned-clock-parents = <&k3_clks 292 89>;
+
+ wiz0_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll0_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 292 85>;
+ };
+
+ wiz0_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll1_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 292 85>;
+ };
+
+ wiz0_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-output-names = "wiz0_refclk_dig";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 292 85>;
+ };
+
+ wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz0_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ serdes0: serdes@506 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0506 0x0001>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&wiz0_pll0_refclk>;
+ clock-names = "refclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
--
2.17.1
[PATCH v5 11/20] ARM: dts: k3-j721e: Add support for USB3 in USB0 instance
Configure the parent clock of wiz3_pll0_refclk to the internal clock
required for USB3 to be functional and also remove "ti,usb2-only"
property as it now supports USB3 mode. This has properties specific to
u-boot on top of DT present in v5.13 of Linux Kernel.
Signed-off-by: Jean-Jacques Hiblot
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Kishon Vijay Abraham I
---
.../k3-j721e-common-proc-board-u-boot.dtsi| 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 974dae8416..85dbf8d2ac 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -129,13 +129,17 @@
u-boot,dm-spl;
};
+&wiz3_pll1_refclk {
+ assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
+};
+
&main_usbss0_pins_default {
u-boot,dm-spl;
};
&usbss0 {
u-boot,dm-spl;
- ti,usb2-only;
};
&usb0 {
@@ -215,3 +219,16 @@
&main_r5fss1 {
ti,cluster-mode = <0>;
};
+
+&wiz3_pll1_refclk {
+ assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
+};
+
+&serdes_ln_ctrl {
+ u-boot,mux-autoprobe;
+};
+
+&usb_serdes_mux {
+ u-boot,mux-autoprobe;
+};
--
2.17.1
[PATCH v5 09/20] phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC
From: Jean-Jacques Hiblot
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to the SERDES. It is
used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures
three clock selects (pll0, pll1, dig) and supports resets for each of the
lanes.
This is an adaptation of the linux driver.
Signed-off-by: Jean-Jacques Hiblot
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/Kconfig|1 +
drivers/phy/Makefile |1 +
drivers/phy/ti/Kconfig |9 +
drivers/phy/ti/Makefile|1 +
drivers/phy/ti/phy-j721e-wiz.c | 1156
5 files changed, 1168 insertions(+)
create mode 100644 drivers/phy/ti/Kconfig
create mode 100644 drivers/phy/ti/Makefile
create mode 100644 drivers/phy/ti/phy-j721e-wiz.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 9208e430a6..7821161e3c 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -270,5 +270,6 @@ config PHY_MTK_TPHY
source "drivers/phy/rockchip/Kconfig"
source "drivers/phy/cadence/Kconfig"
+source "drivers/phy/ti/Kconfig"
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 4736c5eadb..2efaa8827b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-y += cadence/
+obj-y += ti/
diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig
new file mode 100644
index 00..111085f235
--- /dev/null
+++ b/drivers/phy/ti/Kconfig
@@ -0,0 +1,9 @@
+config PHY_J721E_WIZ
+ tristate "TI J721E WIZ (SERDES Wrapper) support"
+ depends on ARCH_K3
+ help
+ This option enables support for WIZ module present in TI's J721E
+ SoC. WIZ is a serdes wrapper used to configure some of the input
+ signals to the SERDES (Sierra/Torrent). This driver configures
+ three clock selects (pll0, pll1, dig) and resets for each of the
+ lanes.
diff --git a/drivers/phy/ti/Makefile b/drivers/phy/ti/Makefile
new file mode 100644
index 00..873ddbf036
--- /dev/null
+++ b/drivers/phy/ti/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_$(SPL_)PHY_J721E_WIZ) += phy-j721e-wiz.o
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
new file mode 100644
index 00..d74efcd212
--- /dev/null
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -0,0 +1,1156 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Jean-Jacques Hiblot
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define WIZ_MAX_INPUT_CLOCKS 4
+/* To include mux clocks, divider clocks and gate clocks */
+#define WIZ_MAX_OUTPUT_CLOCKS 32
+
+#define WIZ_MAX_LANES 4
+#define WIZ_MUX_NUM_CLOCKS 3
+#define WIZ_DIV_NUM_CLOCKS_16G 2
+#define WIZ_DIV_NUM_CLOCKS_10G 1
+
+#define WIZ_SERDES_CTRL0x404
+#define WIZ_SERDES_TOP_CTRL0x408
+#define WIZ_SERDES_RST 0x40c
+#define WIZ_SERDES_TYPEC 0x410
+#define WIZ_LANECTL(n) (0x480 + (0x40 * (n)))
+#define WIZ_LANEDIV(n) (0x484 + (0x40 * (n)))
+
+#define WIZ_MAX_LANES 4
+#define WIZ_MUX_NUM_CLOCKS 3
+#define WIZ_DIV_NUM_CLOCKS_16G 2
+#define WIZ_DIV_NUM_CLOCKS_10G 1
+
+#define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30)
+
+enum wiz_lane_standard_mode {
+ LANE_MODE_GEN1,
+ LANE_MODE_GEN2,
+ LANE_MODE_GEN3,
+ LANE_MODE_GEN4,
+};
+
+enum wiz_refclk_mux_sel {
+ PLL0_REFCLK,
+ PLL1_REFCLK,
+ REFCLK_DIG,
+};
+
+enum wiz_refclk_div_sel {
+ CMN_REFCLK,
+ CMN_REFCLK1,
+};
+
+enum wiz_clock_input {
+ WIZ_CORE_REFCLK,
+ WIZ_EXT_REFCLK,
+ WIZ_CORE_REFCLK1,
+ WIZ_EXT_REFCLK1,
+};
+
+static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
+static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
+static const struct reg_field pll1_refclk_mux_sel =
+ REG_FIELD(WIZ_SERDES_RST, 29, 29);
+static const struct reg_field pll0_refclk_mux_sel =
+ REG_FIELD(WIZ_SERDES_RST, 28, 28);
+static const struct reg_field refclk_dig_sel_16g =
+ REG_FIELD(WIZ_SERDES_RST, 24, 25);
+static const struct reg_field refclk_dig_sel_10g =
+ REG_FIELD(WIZ_SERDES_RST, 24, 24);
+static const struct reg_field pma_cmn_refclk_int_mode =
+ REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
+static const struct reg_field pma_cmn_refclk_mode =
+ REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
+static const struct reg_field pma_cmn_refclk
[PATCH v5 10/20] board: ti: j721e: Add support for probing and configuring Torrent serdes on J7200
From: Aswath Govindraju
Add support for probing and configuring Torrent serdes on J7200.
Signed-off-by: Aswath Govindraju
Signed-off-by: Kishon Vijay Abraham I
---
board/ti/j721e/evm.c | 34 +-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index b9a9f19552..580f13c3ab 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -29,7 +30,8 @@
#define board_is_j721e_som() (board_ti_k3_is("J721EX-PM1-SOM") || \
board_ti_k3_is("J721EX-PM2-SOM"))
-#define board_is_j7200_som() board_ti_k3_is("J7200X-PM1-SOM")
+#define board_is_j7200_som() (board_ti_k3_is("J7200X-PM1-SOM") || \
+board_ti_k3_is("J7200X-PM2-SOM"))
/* Max number of MAC addresses that are parsed/processed per daughter card */
#define DAUGHTER_CARD_NO_OF_MAC_ADDR 8
@@ -384,6 +386,33 @@ static int probe_daughtercards(void)
}
#endif
+void configure_serdes_torrent(void)
+{
+ struct udevice *dev;
+ struct phy serdes;
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_PHY_CADENCE_TORRENT))
+ return;
+
+ ret = uclass_get_device_by_driver(UCLASS_PHY,
+ DM_DRIVER_GET(torrent_phy_provider),
+ &dev);
+ if (ret)
+ printf("Torrent init failed:%d\n", ret);
+
+ serdes.dev = dev;
+ serdes.id = 0;
+
+ ret = generic_phy_init(&serdes);
+ if (ret)
+ printf("phy_init failed!!\n");
+
+ ret = generic_phy_power_on(&serdes);
+ if (ret)
+ printf("phy_power_on failed !!\n");
+}
+
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
@@ -394,6 +423,9 @@ int board_late_init(void)
probe_daughtercards();
}
+ if (board_is_j7200_som())
+ configure_serdes_torrent();
+
return 0;
}
--
2.17.1
[PATCH v5 07/20] phy: cadence: Add driver for Sierra PHY
From: Alan Douglas Add a Sierra PHY driver with PCIe and USB support. This driver is a port from the mainline linux driver. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY One difference with the linux driver is that the PHY is always reset after it is powered-on. This is because role switching is not supported in u-boot and the cable orientation is handled by the PHY reset. Signed-off-by: Jean-Jacques Hiblot Signed-off-by: Alan Douglas Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Vignesh Raghavendra --- drivers/phy/Kconfig | 2 + drivers/phy/Makefile | 1 + drivers/phy/cadence/Kconfig | 5 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-sierra.c | 751 +++ 5 files changed, 760 insertions(+) create mode 100644 drivers/phy/cadence/Kconfig create mode 100644 drivers/phy/cadence/Makefile create mode 100644 drivers/phy/cadence/phy-cadence-sierra.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 008186a10d..9208e430a6 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -269,4 +269,6 @@ config PHY_MTK_TPHY so you can easily distinguish them by banks layout. source "drivers/phy/rockchip/Kconfig" +source "drivers/phy/cadence/Kconfig" + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 3c4a673a83..4736c5eadb 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o +obj-y += cadence/ diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig new file mode 100644 index 00..18a04819f5 --- /dev/null +++ b/drivers/phy/cadence/Kconfig @@ -0,0 +1,5 @@ +config PHY_CADENCE_SIERRA + tristate "Cadence Sierra PHY Driver" + depends on DM_RESET + help + Enable this to support the Cadence Sierra PHY driver diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile new file mode 100644 index 00..d57856152a --- /dev/null +++ b/drivers/phy/cadence/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_$(SPL_)PHY_CADENCE_SIERRA)+= phy-cadence-sierra.o diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c new file mode 100644 index 00..715def6f17 --- /dev/null +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -0,0 +1,751 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cadence Sierra PHY Driver + * + * Based on the linux driver provided by Cadence + * + * Copyright (c) 2018 Cadence Design Systems + * Author: Alan Douglas + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Jean-Jacques Hiblot + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PHY register offsets */ +#define SIERRA_COMMON_CDB_OFFSET 0x0 +#define SIERRA_MACRO_ID_REG0x0 +#define SIERRA_CMN_PLLLC_MODE_PREG 0x48 +#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 +#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A +#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG0x4B +#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F +#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 +#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG0x62 + +#define SIERRA_LANE_CDB_OFFSET(ln, offset) \ + (0x4000 + ((ln) * (0x800 >> (2 - (offset) + +#define SIERRA_DET_STANDEC_A_PREG 0x000 +#define SIERRA_DET_STANDEC_B_PREG 0x001 +#define SIERRA_DET_STANDEC_C_PREG 0x002 +#define SIERRA_DET_STANDEC_D_PREG 0x003 +#define SIERRA_DET_STANDEC_E_PREG 0x004 +#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 +#define SIERRA_PSM_A0IN_TMR_PREG 0x009 +#define SIERRA_PSM_DIAG_PREG 0x015 +#define SIERRA_PSC_TX_A0_PREG 0x028 +#define SIERRA_PSC_TX_A1_PREG
[PATCH v5 06/20] dt-bindings: ti-serdes-mux: Add defines for AM64 SoC
AM64 has a single lane SERDES which can be configured to be used with either PCIe or USB. Define the possilbe values for the SERDES function in AM64 SoC here. Signed-off-by: Kishon Vijay Abraham I --- include/dt-bindings/mux/ti-serdes.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index 9047ec6bd3..d417b9268b 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h @@ -90,4 +90,9 @@ #define J7200_SERDES0_LANE3_USB0x2 #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 +/* AM64 */ + +#define AM64_SERDES0_LANE0_PCIE0 0x0 +#define AM64_SERDES0_LANE0_USB 0x1 + #endif /* _DT_BINDINGS_MUX_TI_SERDES */ -- 2.17.1
[PATCH v5 04/20] dt-bindings: phy: Add defines for AM64 SERDES Wrapper
Add defines for AM64 SERDES Wrapper. Signed-off-by: Kishon Vijay Abraham I --- include/dt-bindings/phy/phy-ti.h | 21 + 1 file changed, 21 insertions(+) create mode 100644 include/dt-bindings/phy/phy-ti.h diff --git a/include/dt-bindings/phy/phy-ti.h b/include/dt-bindings/phy/phy-ti.h new file mode 100644 index 00..ad955d3a56 --- /dev/null +++ b/include/dt-bindings/phy/phy-ti.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for TI SERDES. + */ + +#ifndef _DT_BINDINGS_TI_SERDES +#define _DT_BINDINGS_TI_SERDES + +/* Clock index for output clocks from WIZ */ + +/* MUX Clocks */ +#define TI_WIZ_PLL0_REFCLK 0 +#define TI_WIZ_PLL1_REFCLK 1 +#define TI_WIZ_REFCLK_DIG 2 + +/* Reserve index here for future additions */ + +/* MISC Clocks */ +#define TI_WIZ_PHY_EN_REFCLK 16 + +#endif /* _DT_BINDINGS_TI_SERDES */ -- 2.17.1
[PATCH v5 05/20] dt-bindings: phy: cadence-torrent: Add defines for refclk driver
Add defines for refclk driver used to route the refclk out of torrent SERDES. Signed-off-by: Kishon Vijay Abraham I --- include/dt-bindings/phy/phy-cadence.h | 20 1 file changed, 20 insertions(+) create mode 100644 include/dt-bindings/phy/phy-cadence.h diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h new file mode 100644 index 00..4652bcb862 --- /dev/null +++ b/include/dt-bindings/phy/phy-cadence.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for Cadence SERDES. + */ + +#ifndef _DT_BINDINGS_CADENCE_SERDES_H +#define _DT_BINDINGS_CADENCE_SERDES_H + +/* Torrent */ +#define TORRENT_SERDES_NO_SSC 0 +#define TORRENT_SERDES_EXTERNAL_SSC1 +#define TORRENT_SERDES_INTERNAL_SSC2 + +#define CDNS_TORRENT_REFCLK_DRIVER 0 + +/* Sierra */ +#define CDNS_SIERRA_PLL_CMNLC 0 +#define CDNS_SIERRA_PLL_CMNLC1 1 + +#endif /* _DT_BINDINGS_CADENCE_SERDES_H */ -- 2.17.1
[PATCH v5 03/20] dt-bindings: phy: Add definitions for additional phy types
From: Aswath Govindraju Add definitions for additional phy types that's used specifically for Torrent SERDES. Signed-off-by: Aswath Govindraju Signed-off-by: Kishon Vijay Abraham I --- include/dt-bindings/phy/phy.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h index 7e657da454..d3714edd4b 100644 --- a/include/dt-bindings/phy/phy.h +++ b/include/dt-bindings/phy/phy.h @@ -19,5 +19,6 @@ #define PHY_TYPE_DP6 #define PHY_TYPE_XPCS 7 #define PHY_TYPE_SGMII 8 +#define PHY_TYPE_QSGMII9 #endif /* _DT_BINDINGS_PHY */ -- 2.17.1
[PATCH v5 01/20] dm: core: Add helper to compare node names
Add helper to compare node names.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/core/ofnode.c | 13 +
include/dm/ofnode.h | 10 ++
2 files changed, 23 insertions(+)
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index eeeccfb446..e83d3141b2 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -18,6 +18,19 @@
#include
#include
+bool ofnode_name_eq(ofnode node, const char *name)
+{
+ const char *node_name;
+ size_t len;
+
+ assert(ofnode_valid(node));
+
+ node_name = ofnode_get_name(node);
+ len = strchrnul(node_name, '@') - node_name;
+
+ return (strlen(name) == len) && !strncmp(node_name, name, len);
+}
+
int ofnode_read_u32(ofnode node, const char *propname, u32 *outp)
{
return ofnode_read_u32_index(node, propname, 0, outp);
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 3da05d8b21..4e1a8447e6 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -231,6 +231,16 @@ static inline ofnode ofnode_root(void)
return node;
}
+/**
+ * ofnode_name_eq() - Check if the node name is equivalent to a given name
+ *ignoring the unit address
+ *
+ * @node: valid node reference that has to be compared
+ * @name: name that has to be compared with the node name
+ * @return true if matches, false if it doesn't match
+ */
+bool ofnode_name_eq(ofnode node, const char *name);
+
/**
* ofnode_read_u32() - Read a 32-bit integer from a property
*
--
2.17.1
[PATCH v5 02/20] dm: test: Add test case to check node name ignoring unit address
Add test to check node name ignoring unit address.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Simon Glass
---
test/dm/core.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/test/dm/core.c b/test/dm/core.c
index 2210345dd1..e83f71f767 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -177,6 +177,20 @@ static int dm_test_autobind_uclass_pdata_alloc(struct
unit_test_state *uts)
}
DM_TEST(dm_test_autobind_uclass_pdata_alloc, UT_TESTF_SCAN_PDATA);
+/* compare node names ignoring the unit address */
+static int dm_test_compare_node_name(struct unit_test_state *uts)
+{
+ ofnode node;
+
+ node = ofnode_path("/mmio-bus@0");
+ ut_assert(ofnode_valid(node));
+ ut_assert(ofnode_name_eq(node, "mmio-bus"));
+
+ return 0;
+}
+
+DM_TEST(dm_test_compare_node_name, UT_TESTF_SCAN_PDATA);
+
/* Test that binding with uclass plat setting occurs correctly */
static int dm_test_autobind_uclass_pdata_valid(struct unit_test_state *uts)
{
--
2.17.1
[PATCH v5 00/20] TI/Cadence: Add Sierra/Torrent SERDES driver
Patch series adds Sierra and Torrent SERDES driver for the SERDES used in TI's K3 platforms. This SERDES is used by USB3, PCIe and Ethernet. This series is mostly an adaptation of drivers added in upstream Linux kernel. Changes from v4: 1) Dropped `[PATCH v4 01/21] drivers: reset: Add devm_to_reset() to return dummy "struct reset_ctl"` and will be worked independently of this series. This was mainly introduced for handling optional reset which is not mandatory for both Sierra and Torrent. 2) Fixed sectionauthor name for j721e_evm.rst Changes from v3: 1) Dropped "drivers: reset: Handle gracefully NULL pointers" and added "drivers: reset: Add devm_to_reset() to return dummy "struct reset_ctl" 2) Moved documentation from board/ti/j721e/README to doc/board/ti/j721e_evm.rst 3) Adapted Sierra and Torrent driver to 1). Changes from v2: 1) Re-worked "Handle gracefully NULL pointers" to fix Simons comments 2) Ported the part that allows creating clocks without explicit sub-nodes in DT from the upstream linux kernel. Changes from v1: 1) Fixed string comparison strncmp() to remove "==" 2) Added a test for node name comparison to ignore unit address in test/dm 3) Added better commit message in "drivers: reset: Handle gracefully NULL pointers" Alan Douglas (1): phy: cadence: Add driver for Sierra PHY Aswath Govindraju (7): dt-bindings: phy: Add definitions for additional phy types phy: cadence: Add driver for Torrent SERDES board: ti: j721e: Add support for probing and configuring Torrent serdes on J7200 arm: dts: k3-j7200-main: Add DT node for torrent serdes arm: dts: k3-j7200-common-proc-board: Enable SERDES DT arm: dts: k3-j7200-common-proc-board-u-boot: Add u-boot tags for torrent serdes configs: j7200_evm_a72_defconfig: Add config for torrent serdes and common clock framework Jean-Jacques Hiblot (2): phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC configs: j721e_evm_a72_defconfig: Enable the drivers required for the USB3 support Kishon Vijay Abraham I (10): dm: core: Add helper to compare node names dm: test: Add test case to check node name ignoring unit address dt-bindings: phy: Add defines for AM64 SERDES Wrapper dt-bindings: phy: cadence-torrent: Add defines for refclk driver dt-bindings: ti-serdes-mux: Add defines for AM64 SoC ARM: dts: k3-j721e: Add support for USB3 in USB0 instance env: ti: j721e-evm: Add env variable to power on & reset QSGMII PHY in J7200 EVM configs: j7200_evm_a72: Add CONFIG_PREBOOT to configure ethernet PHY doc: board: Move j721e document to doc/board/ti/ directory doc: board: j721e_evm: Add documentation for firmware loading .../k3-j7200-common-proc-board-u-boot.dtsi| 12 + arch/arm/dts/k3-j7200-common-proc-board.dts | 23 + arch/arm/dts/k3-j7200-main.dtsi | 63 + .../k3-j721e-common-proc-board-u-boot.dtsi| 19 +- board/ti/j721e/README | 277 -- board/ti/j721e/evm.c | 34 +- configs/j7200_evm_a72_defconfig |8 + configs/j721e_evm_a72_defconfig |6 + doc/board/index.rst |1 + doc/board/ti/j721e_evm.rst| 331 +++ drivers/core/ofnode.c | 13 + drivers/phy/Kconfig |3 + drivers/phy/Makefile |2 + drivers/phy/cadence/Kconfig | 11 + drivers/phy/cadence/Makefile |2 + drivers/phy/cadence/phy-cadence-sierra.c | 751 + drivers/phy/cadence/phy-cadence-torrent.c | 2463 + drivers/phy/ti/Kconfig|9 + drivers/phy/ti/Makefile |1 + drivers/phy/ti/phy-j721e-wiz.c| 1156 include/configs/j721e_evm.h | 16 +- include/dm/ofnode.h | 10 + include/dt-bindings/mux/ti-serdes.h |5 + include/dt-bindings/phy/phy-cadence.h | 20 + include/dt-bindings/phy/phy-ti.h | 21 + include/dt-bindings/phy/phy.h |1 + test/dm/core.c| 14 + 27 files changed, 4992 insertions(+), 280 deletions(-) delete mode 100644 board/ti/j721e/README create mode 100644 doc/board/ti/j721e_evm.rst create mode 100644 drivers/phy/cadence/Kconfig create mode 100644 drivers/phy/cadence/Makefile create mode 100644 drivers/phy/cadence/phy-cadence-sierra.c create mode 100644 drivers/phy/cadence/phy-cadence-torrent.c create mode 100644 drivers/phy/ti/Kconfig create mode 100644 drivers/phy/ti/Makefile create mode 100644 drivers/phy/ti/phy-j721e-wiz.c create mode 100644 include/dt-bindings/phy/phy-cadence.h create mode 100644 include/dt-bindings/phy/phy-ti.h -- 2.17.1
Re: [PATCH RESEND u-boot-spi 2/8] mtd: spi-nor-core: Check return value of write_enable() in spi_nor_erase()
On Thu, Jul 15, 2021 at 5:21 AM Marek Behún wrote: > > The spi_nor_erase() function does not check return value of the > write_enable() call. Fix this. > > Signed-off-by: Marek Behún > Tested-by: Masami Hiramatsu > --- Reviewed-by: Jagan Teki
Re: [PATCH RESEND u-boot-spi 1/8] mtd: spi-nor-core: Try cleaning up in case writing BAR failed
On Thu, Jul 15, 2021 at 5:21 AM Marek Behún wrote: > > Use the cleanup codepath of spi_nor_erase() also in the event of failure > of writing the BAR register. > > Signed-off-by: Marek Behún > Tested-by: Masami Hiramatsu > --- Reviewed-by: Jagan Teki
Re: [PATCH 00/15] lib: Add support for a decimal 0m prefix for numbers
Hi Wolfgang, On Wed, 21 Jul 2021 at 01:53, Wolfgang Denk wrote: > > Hi, > > In message <20210720160547.GM9379@bill-the-cat> you wrote: > > > > > So for example (10)123 would mean decimal 123? I don't know how we > > > would parse brackets separately from expressions though. > > > > (123)10 would be "123" in decimal. Which is indeed a mouthful. But it > > would also be generic and (123)16 would be 0x123. So the parsing > > shouldn't be too hard, for most commands. But then yes, expressions > > become quite hard. > > Come on, guys, be serious! This is a boot loader. Size matters. > > Do we _really_ need all this, and is it worth the code size? > > Simon's patches include some cleanup, which probably even reduces > the size, so good. It reduces U-Boot proper by about 400-700 bytes but not much effect on SPL: 16: RFC: Change simple_strtoul() et al to default to hex arm: evb-ast2500 brppt1_spi brsmarc1 aarch64: (for 300/301 boards) all -754.8 bss +0.0 spl/u-boot-spl:all -9.9 spl/u-boot-spl:text -9.9 text -754.8 arc: (for 10/11 boards) all -242.0 text -242.0 arm: (for 625/627 boards) all -468.7 bss +0.8 data +0.0 rodata +0.0 spl/u-boot-spl:all -1.5 spl/u-boot-spl:bss -0.1 spl/u-boot-spl:text -1.4 text -469.5 m68k: (for 18/18 boards) all -499.1 data +11.8 text -510.9 microblaze: (for 1/1 boards) all -392.0 bss +44.0 data +4.0 rodata -4.0 text -436.0 mips: (for 43/43 boards) all -457.5 bss +1.1 text -458.6 nds32: (for 2/2 boards) all -206.0 text -206.0 nios2: (for 2/2 boards) all -480.0 text -480.0 powerpc: (for 40/98 boards) all -708.4 text -708.4 > > But whether it's 0m123 or 0t123 or 0!123 or ... is pretty much > irrelevant - chose one symbol, use it, and be done with that. Regards, Simon
Re: [PATCH 2/2] board: sifive: unmatched: reset USB hub, PCIe-USB bridge, and ULPI device in SPL
On Thu, Jul 08, 2021 at 09:08:21AM +0800, Vincent Chen wrote: > Ensure USB hub, PCIe-USB bridge, and ULPI device to be reset > even if the rebooting is without power-cycling. > > Signed-off-by: Vincent Chen > --- > board/sifive/unmatched/spl.c | 36 > 1 file changed, 36 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 1/2] board: sifive: unmatched: refine GEMGXL initialized function in SPL
On Thu, Jul 08, 2021 at 09:08:20AM +0800, Vincent Chen wrote: > Create a new function spl_reset_device_by_gpio to reset the device > whose reset pin is connected to the GPIO. Then, using this function > to initialize GEMGXL. > > Signed-off-by: Vincent Chen > --- > board/sifive/unmatched/spl.c | 58 > +--- > 1 file changed, 39 insertions(+), 19 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 13/15] RFC: lib: Support a binary prefix 0y
Hi Wolfgang, On Wed, 21 Jul 2021 at 02:27, Wolfgang Denk wrote: > > Dear Simon, > > In message <20210720132940.1171011-14-...@chromium.org> you wrote: > > In some cases it is useful to be able to supply a binary value to a > > command. Use the '0y' prefix for this (binarY). > > We also don't handle octal input yet, and also miss a number of > other interesting numberbases, like 42. > > But ... do we really *need* all this stuff? No... I added binary as an RFC because I have found a few cases where it is nice to be able to specify the bits (e.g. programming GPIOs). We could update 'md' to support it too. I added octal as an RFC since the current impl is almost never available (only when 0 is parted to simple_strtoul()) which seems odd. > > %% (signatures) > Perfection is reached, not when there is no longer anything to add, > but when there is no longer anything to take away. >- Antoine de Saint-Exupery Well, yes. Perhaps we should just drop octal? Regards, Simon
Re: [PATCH] patman: add warning for invalid tag
Hi Patrick,
On Wed, 21 Jul 2021 at 03:45, Patrick Delaunay
wrote:
>
> Add a error in patman tool when the commit message contents an invalid
> tag "Serie-.*" instead of "Series-.*".
>
> Signed-off-by: Patrick Delaunay
> ---
> I create this patch to avoid my frequent mistake:
> using "Serie-" tag instead of "Series-" as it is done in [1].
>
> RE_INV_TAG can be extended to other frequent errors.
>
> Any "Serie-" tag is refused with the patch, for example:
>
> ValueError: Line 28: Invalid tag =
>'Serie-cc: Marek Behún '
>
> [1]
> http://patchwork.ozlabs.org/project/uboot/patch/20210720203353.1.I550b95f6d12d59aeef5b744d837dbb360037d39e@changeid/
>
>
> tools/patman/patchstream.py | 9 +
> 1 file changed, 9 insertions(+)
This is a great idea! But please do add a test.
>
> diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
> index a44cd861af..b960292427 100644
> --- a/tools/patman/patchstream.py
> +++ b/tools/patman/patchstream.py
> @@ -59,6 +59,9 @@ RE_DIFF = re.compile(r'^>.*diff --git a/(.*) b/(.*)$')
> # Detect a context line, like '> @@ -153,8 +153,13 @@ CheckPatch
> RE_LINE = re.compile(r'>.*@@ \-(\d+),\d+ \+(\d+),\d+ @@ *(.*)')
>
> +# Detect line with invalid TAG
> +RE_INV_TAG = re.compile('^Serie-([a-z-]*): *(.*)')
> +
> # States we can be in - can we use range() and still have comments?
> STATE_MSG_HEADER = 0# Still in the message header
> STATE_PATCH_SUBJECT = 1 # In patch subject (first line of log for a
> commit)
> @@ -318,6 +321,7 @@ class PatchStream:
> leading_whitespace_match = RE_LEADING_WHITESPACE.match(line)
> diff_match = RE_DIFF.match(line)
> line_match = RE_LINE.match(line)
> +invalid_match = RE_INV_TAG.match(line)
> tag_match = None
> if self.state == STATE_PATCH_HEADER:
> tag_match = RE_TAG.match(line)
> @@ -471,6 +475,11 @@ class PatchStream:
> self._add_warn('Line %d: Ignoring Commit-%s' %
> (self.linenum, name))
>
> +# Detect invalid tags
> +elif invalid_match:
> +raise ValueError("Line %d: Invalid tag = '%s'" %
> +(self.linenum, line))
> +
> # Detect the start of a new commit
> elif commit_match:
> self._close_commit()
> --
> 2.25.1
>
Regards,
Simon
Re: [PATCH] arm: vexpress64: juno: Enable distro_bootcmd functionality
On Mon, Jul 12, 2021 at 1:25 AM Andre Przywara wrote: > The ARM Juno boards can be used as somewhat decent machines to run > off-the-shelf distributions, with USB, SATA, GBit Ethernet and 8GB of > DRAM. > > With stable DTs in the board's NOR flash this would work really nicely, > however the default boot command is to fetch a kernel and an initrd from > the on-board NOR flash, which sounds somewhat embedded. > > Include the config_distro_bootcmd.h header and define the available > devices (starting with USB, to catch USB installer sticks) to make > distributions and UEFI work out of the box. > The NOR flash kernel functionality is still preserved as the last > resort, should all other methods fail. > > Signed-off-by: Andre Przywara Looks helpful! Reviewed-by: Linus Walleij Yours, Linus Walleij
Re: [PATCH 00/15] lib: Add support for a decimal 0m prefix for numbers
Hi Tom, On Tue, 20 Jul 2021 at 13:28, Tom Rini wrote: > > On Tue, Jul 20, 2021 at 12:33:14PM -0600, Simon Glass wrote: > > Hi Tom. > > > > On Tue, 20 Jul 2021 at 10:05, Tom Rini wrote: > > > > > > On Tue, Jul 20, 2021 at 09:57:55AM -0600, Simon Glass wrote: > > > > Hi Tom, > > > > > > > > On Tue, 20 Jul 2021 at 08:22, Tom Rini wrote: > > > > > > > > > > On Tue, Jul 20, 2021 at 07:29:24AM -0600, Simon Glass wrote: > > > > > > > > > > > U-Boot mostly uses hex for value input, largely because addresses are much > > > > > > easier to understand in hex. > > > > > > > > > > > > But in some cases a hex value is requested, but it is more convenient to > > > > > > provide a decimal value. This may be because the value comes from another > > > > > > source, where its base cannot be controlled. > > > > > > > > > > > > This series adds support for a 0m prefix to indicate a decimal number. The > > > > > > > > > > I _really_ don't want to invent something here. When the setexpr thread > > > > > came up before I went and did a little digging. Per > > > > > https://en.wikipedia.org/wiki/Radix the general way to express a number > > > > > is (x)y where x is the number and y is the base (and y is in base10, and > > > > > also a subscript). I thought it was a bit cumbersome for general use > > > > > and didn't bring it up at the time. > > > > > > > > Well I don't want to invent something either...but what to do? > > > > > > > > So for example (10)123 would mean decimal 123? I don't know how we > > > > would parse brackets separately from expressions though. > > > > > > (123)10 would be "123" in decimal. Which is indeed a mouthful. But it > > > would also be generic and (123)16 would be 0x123. So the parsing > > > shouldn't be too hard, for most commands. But then yes, expressions > > > become quite hard. > > > > > > > > If we're going to add some global way to always say a number is decimal, > > > > > and I'm not sure I think that's a good idea even (I kind of think it > > > > > might be better on a case by case basis to maybe tweak some prints so > > > > > that for example "ls mmc 0:10" tells the user it's accessing partition > > > > > 16 would lead to a quick "oh that's hex, #$%@!"), I think it should > > > > > follow the radix notation, or if not, some other well known example. > > > > > > > > Can you give examples for what you are thinking for radix notation? > > > > > > Well, since we don't have subscript in shell, '(number)base' would how > > > it would be. Which I'm not convinced is better than making it clear to > > > users that almost everything is hex input, including a few places that > > > might surprise you such as partition numbers. > > > > After a bit of thought and digging, I think that is a mathematical > > thing and confusing/unworkable on the command line. > > I agree. > > > Should we consider 0t for decimal? > > My biggest concern is that when I search for "0t prefix" the first > relevant answers are the MS links where 0t is for ocTal, and not the > other examples where it's decimal (base Ten, I assume). Hmm, so make 0n would make more sense? I know it is a new thing but I think it would be very useful... Regards, Simon
[PATCH V4 43/44] arm: dts: add i.MX8ULP dtsi
From: Peng Fan Add i.MX8ULP dtsi Signed-off-by: Peng Fan --- arch/arm/dts/imx8ulp-pinfunc.h| 978 ++ arch/arm/dts/imx8ulp.dtsi | 728 include/dt-bindings/clock/imx8ulp-clock.h | 247 ++ 3 files changed, 1953 insertions(+) create mode 100644 arch/arm/dts/imx8ulp-pinfunc.h create mode 100644 arch/arm/dts/imx8ulp.dtsi create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h diff --git a/arch/arm/dts/imx8ulp-pinfunc.h b/arch/arm/dts/imx8ulp-pinfunc.h new file mode 100644 index 00..c21c3b644e --- /dev/null +++ b/arch/arm/dts/imx8ulp-pinfunc.h @@ -0,0 +1,978 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __DTS_IMX8ULP_PINFUNC_H +#define __DTS_IMX8ULP_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX8ULP_PAD_PTD0__PTD00x 0x 0x1 0x0 +#define MX8ULP_PAD_PTD0__I2S6_RX_BCLK0x 0x0B44 0x7 0x1 +#define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x 0x 0x8 0x0 +#define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x 0x0974 0x9 0x1 +#define MX8ULP_PAD_PTD0__CLKOUT2 0x 0x 0xa 0x0 +#define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x 0x 0xb 0x0 +#define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_00x 0x 0xc 0x0 +#define MX8ULP_PAD_PTD0__CLKOUT1 0x 0x 0xd 0x0 +#define MX8ULP_PAD_PTD0__DEBUG_MUX0_00x 0x 0xe 0x0 +#define MX8ULP_PAD_PTD0__DEBUG_MUX1_00x 0x 0xf 0x0 +#define MX8ULP_PAD_PTD1__PTD10x0004 0x 0x1 0x0 +#define MX8ULP_PAD_PTD1__I2S6_RX_FS 0x0004 0x0B48 0x7 0x1 +#define MX8ULP_PAD_PTD1__SDHC0_CMD 0x0004 0x 0x8 0x0 +#define MX8ULP_PAD_PTD1__FLEXSPI2_B_DATA70x0004 0x0970 0x9 0x1 +#define MX8ULP_PAD_PTD1__EPDC0_SDCLK 0x0004 0x 0xb 0x0 +#define MX8ULP_PAD_PTD1__DPI0_PCLK 0x0004 0x 0xc 0x0 +#define MX8ULP_PAD_PTD1__LP_APD_DBG_MUX_10x0004 0x 0xd 0x0 +#define MX8ULP_PAD_PTD1__DEBUG_MUX0_10x0004 0x 0xe 0x0 +#define MX8ULP_PAD_PTD1__DEBUG_MUX1_10x0004 0x 0xf 0x0 +#define MX8ULP_PAD_PTD2__PTD20x0008 0x 0x1 0x0 +#define MX8ULP_PAD_PTD2__I2S6_RXD0 0x0008 0x0B34 0x7 0x1 +#define MX8ULP_PAD_PTD2__SDHC0_CLK 0x0008 0x 0x8 0x0 +#define MX8ULP_PAD_PTD2__FLEXSPI2_B_DATA60x0008 0x096C 0x9 0x1 +#define MX8ULP_PAD_PTD2__EPDC0_SDLE 0x0008 0x 0xb 0x0 +#define MX8ULP_PAD_PTD2__DPI0_HSYNC 0x0008 0x 0xc 0x0 +#define MX8ULP_PAD_PTD2__LP_APD_DBG_MUX_20x0008 0x 0xd 0x0 +#define MX8ULP_PAD_PTD2__DEBUG_MUX0_20x0008 0x 0xe 0x0 +#define MX8ULP_PAD_PTD2__DEBUG_MUX1_20x0008 0x 0xf 0x0 +#define MX8ULP_PAD_PTD3__PTD30x000C 0x 0x1 0x0 +#define MX8ULP_PAD_PTD3__I2S6_RXD1 0x000C 0x0B38 0x7 0x1 +#define MX8ULP_PAD_PTD3__SDHC0_D70x000C 0x 0x8 0x0 +#define MX8ULP_PAD_PTD3__FLEXSPI2_B_DATA50x000C 0x0968 0x9 0x1 +#define MX8ULP_PAD_PTD3__EPDC0_GDSP 0x000C 0x 0xb 0x0 +#define MX8ULP_PAD_PTD3__DPI0_VSYNC 0x000C 0x 0xc 0x0 +#define MX8ULP_PAD_PTD3__LP_APD_DBG_MUX_30x000C 0x 0xd 0x0 +#define MX8ULP_PAD_PTD3__DEBUG_MUX0_30x000C 0x 0xe 0x0 +#define MX8ULP_PAD_PTD3__DEBUG_MUX1_30x000C 0x 0xf 0x0 +#define MX8ULP_PAD_PTD4__PTD40x0010 0x 0x1 0x0 +#define MX8ULP_PAD_PTD4__EXT_AUD_MCLK3 0x0010 0x0B14 0x4 0x1 +#define MX8ULP_PAD_PTD4__SDHC0_VS0x0010 0x 0x5 0x0 +#define MX8ULP_PAD_PTD4__TPM8_CH50x0010 0x0B2C 0x6 0x1 +#define MX8ULP_PAD_PTD4__I2S6_MCLK 0x0010 0x 0x7 0x0 +#define MX8ULP_PAD_PTD4__SDHC0_D60x0010 0x 0x8 0x0 +#define MX8ULP_PAD_PTD4__FLEXSPI2_B_DATA40x0010 0x0964 0x9 0x1 +#define MX8ULP_PAD_PTD4__EPDC0_SDCE0
[PATCH V4 34/44] arm: imx8ulp: add dummy imx_get_mac_from_fuse
From: Peng Fan
Add imx_get_mac_from_fuse for enet build pass
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index e5985c4cf1..0728cb9847 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -532,3 +532,8 @@ __weak void __noreturn jump_to_image_no_args(struct
spl_image_info *spl_image)
;
}
#endif
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ memset(mac, 0, 6);
+}
--
2.30.0
[PATCH V4 36/44] driver: misc: imx8ulp: Add fuse driver for imx8ulp
From: Ye Li
This driver uses FSB to read some fuses, but not support program fuse.
It only works in SPL (secure mode), u-boot needs traps to ATF to
read them.
Some fuses can read from S400 API and others are from FSB.
Also support program some fuses via S400 API
Signed-off-by: Ye Li
---
drivers/misc/imx8ulp/Makefile | 1 +
drivers/misc/imx8ulp/fuse.c | 198 ++
2 files changed, 199 insertions(+)
create mode 100644 drivers/misc/imx8ulp/fuse.c
diff --git a/drivers/misc/imx8ulp/Makefile b/drivers/misc/imx8ulp/Makefile
index 1d792415d2..927cc55216 100644
--- a/drivers/misc/imx8ulp/Makefile
+++ b/drivers/misc/imx8ulp/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += s400_api.o imx8ulp_mu.o
+obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/imx8ulp/fuse.c b/drivers/misc/imx8ulp/fuse.c
new file mode 100644
index 00..d1feb62ab5
--- /dev/null
+++ b/drivers/misc/imx8ulp/fuse.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FUSE_BANKS 64
+#define WORDS_PER_BANKS 8
+
+struct fsb_map_entry {
+ s32 fuse_bank;
+ u32 fuse_words;
+ bool redundancy;
+};
+
+struct s400_map_entry {
+ s32 fuse_bank;
+ u32 fuse_words;
+ u32 fuse_offset;
+ u32 s400_index;
+};
+
+struct fsb_map_entry fsb_mapping_table[] = {
+ { 3, 8 },
+ { 4, 8 },
+ { 5, 8 },
+ { 6, 8 },
+ { -1, 48 }, /* Reserve 48 words */
+ { 8, 4, true },
+ { 24, 4, true },
+ { 26, 4, true },
+ { 27, 4, true },
+ { 28, 8 },
+ { 29, 8 },
+ { 30, 8 },
+ { 31, 8 },
+ { 37, 8 },
+ { 38, 8 },
+ { 39, 8 },
+ { 40, 8 },
+ { 41, 8 },
+ { 42, 8 },
+ { 43, 8 },
+ { 44, 8 },
+ { 45, 8 },
+ { 46, 8 },
+};
+
+struct s400_map_entry s400_api_mapping_table[] = {
+ { 1, 8 }, /* LOCK */
+ { 2, 8 }, /* ECID */
+ { 7, 4, 0, 1 }, /* OTP_UNIQ_ID */
+ { 23, 1, 4, 2 }, /* OTFAD */
+};
+
+static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
+{
+ s32 size = ARRAY_SIZE(fsb_mapping_table);
+ s32 i, word_pos = 0;
+
+ /* map the fuse from ocotp fuse map to FSB*/
+ for (i = 0; i < size; i++) {
+ if (fsb_mapping_table[i].fuse_bank != -1 &&
+ fsb_mapping_table[i].fuse_bank == bank) {
+ break;
+ }
+
+ word_pos += fsb_mapping_table[i].fuse_words;
+ }
+
+ if (i == size)
+ return -1; /* Failed to find */
+
+ if (fsb_mapping_table[i].redundancy) {
+ *redundancy = true;
+ return (word >> 1) + word_pos;
+ }
+
+ *redundancy = false;
+ return word + word_pos;
+}
+
+static s32 map_s400_fuse_index(u32 bank, u32 word)
+{
+ s32 size = ARRAY_SIZE(s400_api_mapping_table);
+ s32 i;
+
+ /* map the fuse from ocotp fuse map to FSB*/
+ for (i = 0; i < size; i++) {
+ if (s400_api_mapping_table[i].fuse_bank != -1 &&
+ s400_api_mapping_table[i].fuse_bank == bank) {
+ if (word >= s400_api_mapping_table[i].fuse_offset &&
+ word < (s400_api_mapping_table[i].fuse_offset +
+ s400_api_mapping_table[i].fuse_words))
+ break;
+ }
+ }
+
+ if (i == size)
+ return -1; /* Failed to find */
+
+ if (s400_api_mapping_table[i].s400_index != 0)
+ return s400_api_mapping_table[i].s400_index;
+
+ return s400_api_mapping_table[i].fuse_bank * 8 + word;
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ s32 word_index;
+ bool redundancy;
+
+ if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ return -EINVAL;
+
+ word_index = map_fsb_fuse_index(bank, word, &redundancy);
+ if (word_index >= 0) {
+ *val = readl((ulong)FSB_BASE_ADDR + 0x800 + (word_index << 2));
+ if (redundancy)
+ *val = (*val >> ((word % 2) * 16)) & 0x;
+
+ return 0;
+ }
+
+ word_index = map_s400_fuse_index(bank, word);
+ if (word_index >= 0) {
+ u32 data[4];
+ u32 res, size = 4;
+ int ret;
+
+ /* Only UID return 4 words */
+ if (word_index != 1)
+ size = 1;
+
+ ret = ahab_read_common_fuse(word_index, data, size, &res);
+ if (ret) {
+ printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+ return ret;
+ }
+
+ if (word_index == 1) {
+ *val = data[
[PATCH V4 44/44] arm: imx: add i.MX8ULP EVK support
From: Peng Fan
Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART
Log as below: I would keep some debug info for now, and after we move
to be stable and production launch, we could drop that.
U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800)
Normal Boot
upower_init: soc_id=48
upower_init: version:11.11.6
upower_init: start uPower RAM service
user_upwr_rdy_callb: soc=b
user_upwr_rdy_callb: RAM version:12.6
Turn on switches ok
Turn on memories ok
Clear DDR retention ok
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F0 frequency.
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F2 frequency.
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F2 frequency.
complete
De-Skew PLL is locked and ready
WDT: Not found!
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0
Load image from 0x3a800 by ROM_API
NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94
NOTICE: BL31: Built : 01:56:58, Jun 29 2021
NOTICE: upower_init: start uPower RAM service
NOTICE: user_upwr_rdy_callb: soc=b
NOTICE: user_upwr_rdy_callb: RAM version:12.6
U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800)
CPU: Freescale i.MX8ULP rev1.0 at 744 MHz
Reset cause: POR
Boot mode: Single boot
Model: FSL i.MX8ULP EVK
DRAM: 2 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 2
Loading Environment from MMC... ***
Warning - bad CRC, using default environment
In:serial@293a
Out: serial@293a
Err: serial@293a
Net:
Warning: ethernet@2995 (eth0) using random MAC address -
96:35:88:62:e0:44
eth0: ethernet@2995
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan
---
arch/arm/dts/Makefile |3 +
arch/arm/dts/imx8ulp-evk-u-boot.dtsi| 40 +
arch/arm/dts/imx8ulp-evk.dts| 223
arch/arm/mach-imx/imx8ulp/Kconfig |7 +
board/freescale/imx8ulp_evk/Kconfig | 14 +
board/freescale/imx8ulp_evk/MAINTAINERS |6 +
board/freescale/imx8ulp_evk/Makefile|7 +
board/freescale/imx8ulp_evk/ddr_init.c | 207
board/freescale/imx8ulp_evk/imx8ulp_evk.c | 67 ++
board/freescale/imx8ulp_evk/lpddr4_timing.c | 1159 +++
board/freescale/imx8ulp_evk/spl.c | 105 ++
configs/imx8ulp_evk_defconfig | 103 ++
include/configs/imx8ulp_evk.h | 107 ++
13 files changed, 2048 insertions(+)
create mode 100644 arch/arm/dts/imx8ulp-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8ulp-evk.dts
create mode 100644 board/freescale/imx8ulp_evk/Kconfig
create mode 100644 board/freescale/imx8ulp_evk/MAINTAINERS
create mode 100644 board/freescale/imx8ulp_evk/Makefile
create mode 100644 board/freescale/imx8ulp_evk/ddr_init.c
create mode 100644 board/freescale/imx8ulp_evk/imx8ulp_evk.c
create mode 100644 board/freescale/imx8ulp_evk/lpddr4_timing.c
create mode 100644 board/freescale/imx8ulp_evk/spl.c
create mode 100644 configs/imx8ulp_evk_defconfig
create mode 100644 include/configs/imx8ulp_evk.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 90e3004dbe..91228b7032 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -859,6 +859,9 @@ dtb-$(CONFIG_ARCH_IMX8) += \
imx8-deneb.dtb \
imx8-giedi.dtb
+dtb-$(CONFIG_ARCH_IMX8ULP) += \
+ imx8ulp-evk.dtb
+
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
new file mode 100644
index 00..7c1dab2acf
--- /dev/null
+++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+&{/soc@0} {
+ u-boot,dm-spl;
+};
+
+&per_bridge3 {
+ u-boot,dm-spl;
+};
+
+&per_bridge4 {
+ u-boot,dm-spl;
+};
+
+&iomuxc1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_lpuart5 {
+ u-boot,dm-spl;
+};
+
+&s400_mu {
+ u-boot,dm-spl;
+};
+
+&lpuart5 {
+ u-boot,dm-spl;
+};
+
+&usdhc0 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc0 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8ulp-evk.dts b/arch/arm/dts/imx8ulp-evk.dts
new file mode 100644
index 00..da09ff48ff
--- /dev/null
+++ b/arch/arm/dts/imx8ulp-evk.dts
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8ulp.dtsi"
+
+/ {
+ model = "FSL i.MX8ULP EVK";
+ compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
+
+ chosen {
+ stdout-path = &lpuart5;
+ bootargs = "console=ttyLP1,115200 earlycon";
+ };
+
+ usdhc2_pwrseq: usdhc2_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpio
[PATCH V4 41/44] imx8ulp: add upower api support
From: Peng Fan
Add upower api support, this is modified from upower firmware exported
package.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/upower.h| 15 +
arch/arm/mach-imx/imx8ulp/Makefile| 4 +
arch/arm/mach-imx/imx8ulp/upower/Makefile | 6 +
arch/arm/mach-imx/imx8ulp/upower/upower_api.c | 486 ++
arch/arm/mach-imx/imx8ulp/upower/upower_api.h | 258 ++
arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 180 +++
6 files changed, 949 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8ulp/upower.h
create mode 100644 arch/arm/mach-imx/imx8ulp/upower/Makefile
create mode 100644 arch/arm/mach-imx/imx8ulp/upower/upower_api.c
create mode 100644 arch/arm/mach-imx/imx8ulp/upower/upower_api.h
create mode 100644 arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
diff --git a/arch/arm/include/asm/arch-imx8ulp/upower.h
b/arch/arm/include/asm/arch-imx8ulp/upower.h
new file mode 100644
index 00..0f1875bbd6
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/upower.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8ULP_UPOWER_H
+#define __ASM_ARCH_IMX8ULP_UPOWER_H
+
+#include
+
+int upower_init(void);
+int upower_pmic_i2c_write(u32 reg_addr, u32 reg_val);
+int upower_pmic_i2c_read(u32 reg_addr, u32 *reg_val);
+
+#endif
diff --git a/arch/arm/mach-imx/imx8ulp/Makefile
b/arch/arm/mach-imx/imx8ulp/Makefile
index 1ef6cd5c91..2c9938fcdf 100644
--- a/arch/arm/mach-imx/imx8ulp/Makefile
+++ b/arch/arm/mach-imx/imx8ulp/Makefile
@@ -5,3 +5,7 @@
obj-y += lowlevel_init.o
obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += upower/
+endif
diff --git a/arch/arm/mach-imx/imx8ulp/upower/Makefile
b/arch/arm/mach-imx/imx8ulp/upower/Makefile
new file mode 100644
index 00..f8b5da2ad3
--- /dev/null
+++ b/arch/arm/mach-imx/imx8ulp/upower/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 NXP
+#
+
+obj-y += upower_api.o upower_hal.o
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_api.c
b/arch/arm/mach-imx/imx8ulp/upower/upower_api.c
new file mode 100644
index 00..7e94ed9c77
--- /dev/null
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_api.c
@@ -0,0 +1,486 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2021 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include "upower_api.h"
+
+enum upwr_api_state api_state;
+enum soc_domain pwr_domain;
+void *sh_buffer[UPWR_SG_COUNT];
+struct upwr_code_vers fw_rom_version;
+struct upwr_code_vers fw_ram_version;
+u32 fw_launch_option;
+u32 sg_busy;
+struct mu_type *mu;
+upwr_up_max_msg sg_rsp_msg[UPWR_SG_COUNT];
+upwr_callb user_callback[UPWR_SG_COUNT];
+UPWR_RX_CALLB_FUNC_T sgrp_callback[UPWR_SG_COUNT];
+u32 sg_rsp_siz[UPWR_SG_COUNT];
+
+#define UPWR_MU_MSG_SIZE(2)
+#define UPWR_SG_BUSY(sg) (sg_busy & (1 << (sg)))
+#define UPWR_USR_CALLB(sg, cb) \
+ do {\
+ user_callback[sg] = cb; \
+ } while (0)
+#define UPWR_MSG_HDR(hdr, sg, fn) \
+ (hdr).domain = (u32)pwr_domain; \
+ (hdr).srvgrp = sg;\
+ (hdr).function = fn
+
+static u32 upwr_ptr2offset(u64 ptr, enum upwr_sg sg, size_t siz, size_t
offset, const void *vptr)
+{
+ if (ptr >= UPWR_DRAM_SHARED_BASE_ADDR &&
+ ((ptr - UPWR_DRAM_SHARED_BASE_ADDR) < UPWR_DRAM_SHARED_SIZE)) {
+ return (u32)(ptr - UPWR_DRAM_SHARED_BASE_ADDR);
+ }
+
+ /* pointer is outside the shared memory, copy the struct to buffer */
+ memcpy(offset + (char *)sh_buffer[sg], (void *)vptr, siz);
+
+ return (u32)((u64)sh_buffer[sg] + offset - UPWR_DRAM_SHARED_BASE_ADDR);
+}
+
+enum upwr_req_status upwr_req_status(enum upwr_sg sg, u32 *sgfptr, enum
upwr_resp *errptr,
+int *retptr)
+{
+ enum upwr_req_status status;
+
+ status = (sg_rsp_msg[sg].hdr.errcode == UPWR_RESP_OK) ? UPWR_REQ_OK :
UPWR_REQ_ERR;
+
+ return status;
+}
+
+void upwr_copy2tr(struct mu_type *mu, const u32 *msg, u32 size)
+{
+ int i;
+
+ for (i = size - 1; i > -1; i--)
+ writel(msg[i], &mu->tr[i]);
+}
+
+int upwr_tx(const u32 *msg, u32 size)
+{
+ if (size > UPWR_MU_MSG_SIZE)
+ return -2;
+ if (!size)
+ return -2;
+
+ if (readl(&mu->tsr) != UPWR_MU_TSR_EMPTY)
+ return -1; /* not all TE bits in 1: some data to send still */
+
+ upwr_copy2tr(mu, msg, size);
+ writel(1 << (size - 1), &mu->tcr);
+
+ return 0;
+}
+
+void upwr_srv_req(enum upwr_sg sg, u32 *msg, u32 size)
+{
+ sg_busy |= 1 << sg;
+
+ upwr_tx(msg, size);
+}
+
+int upwr_pwm_power_on(const u32 swton[], const u32 memon[], upwr_callb callb)
+{
+ upwr_pwm_pwron_msg txmsg;
+ u64 ptrval; /* needed for X86, ARM64 */
+ size_t stsiz
[PATCH V4 42/44] ddr: Add DDR driver for iMX8ULP
From: Ye Li
Add iMX8ULP DDR initialization driver which loads the DDR timing
parameters and executes the training procedure.
When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode
to do DDR init
Signed-off-by: Ye Li
---
drivers/Makefile | 1 +
drivers/ddr/imx/Kconfig| 1 +
drivers/ddr/imx/imx8ulp/Kconfig| 11 ++
drivers/ddr/imx/imx8ulp/Makefile | 9 ++
drivers/ddr/imx/imx8ulp/ddr_init.c | 217 +
5 files changed, 239 insertions(+)
create mode 100644 drivers/ddr/imx/imx8ulp/Kconfig
create mode 100644 drivers/ddr/imx/imx8ulp/Makefile
create mode 100644 drivers/ddr/imx/imx8ulp/ddr_init.c
diff --git a/drivers/Makefile b/drivers/Makefile
index 4081289104..54815a2d80 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
+obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/
diff --git a/drivers/ddr/imx/Kconfig b/drivers/ddr/imx/Kconfig
index 7e06fb2f7d..179f34530d 100644
--- a/drivers/ddr/imx/Kconfig
+++ b/drivers/ddr/imx/Kconfig
@@ -1 +1,2 @@
source "drivers/ddr/imx/imx8m/Kconfig"
+source "drivers/ddr/imx/imx8ulp/Kconfig"
diff --git a/drivers/ddr/imx/imx8ulp/Kconfig b/drivers/ddr/imx/imx8ulp/Kconfig
new file mode 100644
index 00..e56062a1d0
--- /dev/null
+++ b/drivers/ddr/imx/imx8ulp/Kconfig
@@ -0,0 +1,11 @@
+menu "i.MX8ULP DDR controllers"
+ depends on ARCH_IMX8ULP
+
+config IMX8ULP_DRAM
+ bool "imx8m dram"
+
+config IMX8ULP_DRAM_PHY_PLL_BYPASS
+ bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "
+ depends on IMX8ULP_DRAM
+
+endmenu
diff --git a/drivers/ddr/imx/imx8ulp/Makefile b/drivers/ddr/imx/imx8ulp/Makefile
new file mode 100644
index 00..7f44a92180
--- /dev/null
+++ b/drivers/ddr/imx/imx8ulp/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_IMX8ULP_DRAM) += ddr_init.o
+endif
diff --git a/drivers/ddr/imx/imx8ulp/ddr_init.c
b/drivers/ddr/imx/imx8ulp/ddr_init.c
new file mode 100644
index 00..16aaf56103
--- /dev/null
+++ b/drivers/ddr/imx/imx8ulp/ddr_init.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2021 NXP
+ */
+#include
+#include
+#include
+#include
+#include
+
+#define DENALI_CTL_00 (DDR_CTL_BASE_ADDR + 4 * 0)
+#define CTL_START 0x1
+
+#define DENALI_CTL_03 (DDR_CTL_BASE_ADDR + 4 * 3)
+#define DENALI_CTL_197 (DDR_CTL_BASE_ADDR + 4 * 197)
+#define DENALI_CTL_250 (DDR_CTL_BASE_ADDR + 4 * 250)
+#define DENALI_CTL_251 (DDR_CTL_BASE_ADDR + 4 * 251)
+#define DENALI_CTL_266 (DDR_CTL_BASE_ADDR + 4 * 266)
+#define DFI_INIT_COMPLETE 0x2
+
+#define DENALI_CTL_614 (DDR_CTL_BASE_ADDR + 4 * 614)
+#define DENALI_CTL_615 (DDR_CTL_BASE_ADDR + 4 * 615)
+
+#define DENALI_PI_00 (DDR_PI_BASE_ADDR + 4 * 0)
+#define PI_START 0x1
+
+#define DENALI_PI_04 (DDR_PI_BASE_ADDR + 4 * 4)
+#define DENALI_PI_11 (DDR_PI_BASE_ADDR + 4 * 11)
+#define DENALI_PI_12 (DDR_PI_BASE_ADDR + 4 * 12)
+#define DENALI_CTL_23 (DDR_CTL_BASE_ADDR + 4 * 23)
+#define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25)
+
+#define DENALI_PHY_1624(DDR_PHY_BASE_ADDR + 4 * 1624)
+#define DENALI_PHY_1537(DDR_PHY_BASE_ADDR + 4 * 1537)
+#define PHY_FREQ_SEL_MULTICAST_EN(X) ((X) << 8)
+#define PHY_FREQ_SEL_INDEX(X) ((X) << 16)
+
+#define DENALI_PHY_1547(DDR_PHY_BASE_ADDR + 4 * 1547)
+#define DENALI_PHY_1555(DDR_PHY_BASE_ADDR + 4 * 1555)
+#define DENALI_PHY_1564(DDR_PHY_BASE_ADDR + 4 * 1564)
+#define DENALI_PHY_1565(DDR_PHY_BASE_ADDR + 4 * 1565)
+
+static void ddr_enable_pll_bypass(void)
+{
+ u32 reg_val;
+
+ /* PI_INIT_LVL_EN=0x0 (DENALI_PI_04) */
+ reg_val = readl(DENALI_PI_04) & ~0x1;
+ writel(reg_val, DENALI_PI_04);
+
+ /* PI_FREQ_MAP=0x1 (DENALI_PI_12) */
+ writel(0x1, DENALI_PI_12);
+
+ /* PI_INIT_WORK_FREQ=0x0 (DENALI_PI_11) */
+ reg_val = readl(DENALI_PI_11) & ~(0x1f << 8);
+ writel(reg_val, DENALI_PI_11);
+
+ /* DFIBUS_FREQ_INIT=0x0 (DENALI_CTL_23) */
+ reg_val = readl(DENALI_CTL_23) & ~(0x3 << 24);
+ writel(reg_val, DENALI_CTL_23);
+
+ /* PHY_LP4_BOOT_DISABLE=0x0 (DENALI_PHY_1547) */
+ reg_val = readl(DENALI_PHY_1547) & ~(0x1 << 8);
+ writel(reg_val, DENALI_PHY_1547);
+
+ /* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */
+ reg_val = readl(DENALI_PHY_1624) | 0x1;
+ writel
[PATCH V4 40/44] imx8ulp: move struct mu_type to common header
From: Peng Fan
Move struct mu_type to common header to make it reusable by upower and
S400
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 25
drivers/misc/imx8ulp/imx8ulp_mu.c| 19 +--
2 files changed, 26 insertions(+), 18 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
index 5231155089..af6845cbff 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
@@ -63,6 +63,31 @@
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
+struct mu_type {
+ u32 ver;
+ u32 par;
+ u32 cr;
+ u32 sr;
+ u32 reserved0[60];
+ u32 fcr;
+ u32 fsr;
+ u32 reserved1[2];
+ u32 gier;
+ u32 gcr;
+ u32 gsr;
+ u32 reserved2;
+ u32 tcr;
+ u32 tsr;
+ u32 rcr;
+ u32 rsr;
+ u32 reserved3[52];
+ u32 tr[16];
+ u32 reserved4[16];
+ u32 rr[16];
+ u32 reserved5[14];
+ u32 mu_attr;
+};
+
struct usbphy_regs {
u32 usbphy_pwd; /* 0x000 */
u32 usbphy_pwd_set; /* 0x004 */
diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c
b/drivers/misc/imx8ulp/imx8ulp_mu.c
index 913ebe7ad3..333ebdf576 100644
--- a/drivers/misc/imx8ulp/imx8ulp_mu.c
+++ b/drivers/misc/imx8ulp/imx8ulp_mu.c
@@ -10,29 +10,12 @@
#include
#include
#include
+#include
#include
#include
DECLARE_GLOBAL_DATA_PTR;
-struct mu_type {
- u32 ver;
- u32 par;
- u32 cr;
- u32 sr;
- u32 reserved0[68];
- u32 tcr;
- u32 tsr;
- u32 rcr;
- u32 rsr;
- u32 reserved1[52];
- u32 tr[16];
- u32 reserved2[16];
- u32 rr[16];
- u32 reserved4[14];
- u32 mu_attr;
-};
-
struct imx8ulp_mu {
struct mu_type *base;
};
--
2.30.0
[PATCH V4 38/44] imx8ulp: Use DGO_GP5 to get boot config
From: Ye Li
Since CMC1 MR0 only reflects high 16 bits boot cfg used for AP domian,
it does not connect to low 16 bits for RTD. So we can't get the correct
boot mode.
Change to use DGO_GP5 of SEC_SIM which is set by ROM.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx8ulp/soc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 9bdbe3c846..96d65690c4 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -120,7 +120,7 @@ enum bt_mode get_boot_mode(void)
{
u32 bt0_cfg = 0;
- bt0_cfg = readl(CMC1_BASE_ADDR + 0xa0);
+ bt0_cfg = readl(SIM_SEC_BASE_ADDR + 0x24);
bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
--
2.30.0
[PATCH V4 39/44] imx8ulp: Add workaround for eMMC boot
From: Ye Li
When booting from boot part1/2, the image offset should be 0, but
ROM has a bug to return 0x8000. Has to workaround the issue before
ROM fix it.
Use a ROM function to know boot from emmc boot part or user part
So we can set the image offset accordingly.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/image-container.c | 7 +++
arch/arm/mach-imx/imx8ulp/soc.c | 10 ++
2 files changed, 17 insertions(+)
diff --git a/arch/arm/mach-imx/image-container.c
b/arch/arm/mach-imx/image-container.c
index c3f62872c6..68b30bcfc5 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -265,10 +265,17 @@ unsigned long spl_nor_get_uboot_base(void)
#endif
#ifdef CONFIG_SPL_BOOTROM_SUPPORT
+u32 __weak spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev)
+{
+ return image_offset;
+}
+
ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev)
{
ulong end;
+ image_offset = spl_arch_boot_image_offset(image_offset, rom_bt_dev);
+
end = get_imageset_end((void *)(ulong)image_offset, ROM_API_DEV);
end = ROUND(end, SZ_1K);
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 96d65690c4..1c33acc7dd 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -533,3 +533,13 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
memset(mac, 0, 6);
}
+
+int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc;
+u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev)
+{
+ /* Hard code for eMMC image_offset on 8ULP ROM, need fix by ROM, temp
workaround */
+ if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC &&
card_emmc_is_boot_part_en())
+ image_offset = 0;
+
+ return image_offset;
+}
--
2.30.0
[PATCH V4 33/44] arm: imx8ulp: Allocate DCNANO and MIPI_DSI to AD domain
From: Ye Li Configure DCNANO and MIPI_DSI to be controlled by AD for single boot Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index add4618440..e5985c4cf1 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -482,6 +482,8 @@ int arch_cpu_init(void) setbits_le32(0x2802B044, BIT(7)); /* GPU 2D/3D to APD */ setbits_le32(0x2802B04C, BIT(1) | BIT(2)); + /* DCNANO and MIPI_DSI to APD */ + setbits_le32(0x2802B04C, BIT(1) | BIT(2) | BIT(3) | BIT(4)); } /* release xrdc, then allow A35 to write SRAM2 */ -- 2.30.0
[PATCH V4 35/44] arm: imx8ulp: add iomuxc support
From: Peng Fan
Add i.MX8ULP iomuxc support
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/iomux.h | 82 +++
arch/arm/mach-imx/imx8ulp/iomux.c | 56 +++-
2 files changed, 137 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-imx8ulp/iomux.h
diff --git a/arch/arm/include/asm/arch-imx8ulp/iomux.h
b/arch/arm/include/asm/arch-imx8ulp/iomux.h
new file mode 100644
index 00..0210489b1a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/iomux.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __MACH_IMX8ULP_IOMUX_H__
+#define __MACH_IMX8ULP_IOMUX_H__
+
+typedef u64 iomux_cfg_t;
+
+#define MUX_CTRL_OFS_SHIFT 0
+#define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0x << MUX_CTRL_OFS_SHIFT)
+#define MUX_SEL_INPUT_OFS_SHIFT16
+#define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0x << MUX_SEL_INPUT_OFS_SHIFT)
+
+#define MUX_MODE_SHIFT 32
+#define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT)
+#define MUX_SEL_INPUT_SHIFT38
+#define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
+#define MUX_PAD_CTRL_SHIFT 42
+#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7 << MUX_PAD_CTRL_SHIFT)
+
+#define MUX_PAD_CTRL(x)((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+
+#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,
sel_input, pad_ctrl) \
+ (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
+ ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
+ ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
+ ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
+ ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
+
+#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) |
MUX_PAD_CTRL(pad))
+
+#define IOMUX_CONFIG_MPORTS 0x20
+#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \
MUX_MODE_SHIFT)
+
+/* Bit definition below needs to be fixed acccording to ulp rm */
+
+#define NO_PAD_CTRLBIT(18)
+#define PAD_CTL_OBE_ENABLE BIT(17)
+#define PAD_CTL_IBE_ENABLE BIT(16)
+#define PAD_CTL_DSEBIT(6)
+#define PAD_CTL_ODEBIT(5)
+#define PAD_CTL_SRE_FAST (0 << 2)
+#define PAD_CTL_SRE_SLOW BIT(2)
+#define PAD_CTL_PUEBIT(1)
+#define PAD_CTL_PUS_UP (BIT(0) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE)
+
+#define IOMUXC_PCR_MUX_ALT0(0 << 8)
+#define IOMUXC_PCR_MUX_ALT1(1 << 8)
+#define IOMUXC_PCR_MUX_ALT2(2 << 8)
+#define IOMUXC_PCR_MUX_ALT3(3 << 8)
+#define IOMUXC_PCR_MUX_ALT4(4 << 8)
+#define IOMUXC_PCR_MUX_ALT5(5 << 8)
+#define IOMUXC_PCR_MUX_ALT6(6 << 8)
+#define IOMUXC_PCR_MUX_ALT7(7 << 8)
+#define IOMUXC_PCR_MUX_ALT8(8 << 8)
+#define IOMUXC_PCR_MUX_ALT9(9 << 8)
+#define IOMUXC_PCR_MUX_ALT10 (10 << 8)
+#define IOMUXC_PCR_MUX_ALT11 (11 << 8)
+#define IOMUXC_PCR_MUX_ALT12 (12 << 8)
+#define IOMUXC_PCR_MUX_ALT13 (13 << 8)
+#define IOMUXC_PCR_MUX_ALT14 (14 << 8)
+#define IOMUXC_PCR_MUX_ALT15 (15 << 8)
+
+#define IOMUXC_PSMI_IMUX_ALT0 (0x0)
+#define IOMUXC_PSMI_IMUX_ALT1 (0x1)
+#define IOMUXC_PSMI_IMUX_ALT2 (0x2)
+#define IOMUXC_PSMI_IMUX_ALT3 (0x3)
+#define IOMUXC_PSMI_IMUX_ALT4 (0x4)
+#define IOMUXC_PSMI_IMUX_ALT5 (0x5)
+#define IOMUXC_PSMI_IMUX_ALT6 (0x6)
+#define IOMUXC_PSMI_IMUX_ALT7 (0x7)
+
+#define IOMUXC_PCR_MUX_ALT_SHIFT (8)
+#define IOMUXC_PCR_MUX_ALT_MASK(0xF00)
+#define IOMUXC_PSMI_IMUX_ALT_SHIFT (0)
+
+void imx8ulp_iomux_setup_pad(iomux_cfg_t pad);
+void imx8ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, unsigned
int count);
+#endif
diff --git a/arch/arm/mach-imx/imx8ulp/iomux.c
b/arch/arm/mach-imx/imx8ulp/iomux.c
index c52ccdeaea..c6d20f5468 100644
--- a/arch/arm/mach-imx/imx8ulp/iomux.c
+++ b/arch/arm/mach-imx/imx8ulp/iomux.c
@@ -1,4 +1,58 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
+
+#include
+#include
+#include
+#include
+
+static void *base = (void *)IOMUXC_BASE_ADDR;
+static void *base_mports = (void *)(0x280A1000);
+
+/*
+ * configures a single pad in the iomuxer
+ */
+void imx8ulp_iomux_setup_pad(iomux_cfg_t pad)
+{
+ u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+ u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+ u32 sel_input_ofs =
+ (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+ u32 sel_input =
+ (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
+ u32 pad_ctrl_ofs = mux_ctrl_ofs;
+ u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PA
[PATCH V4 37/44] imx8ulp: soc: correct reset cause
From: Peng Fan
The CMC1 SRS reflects the current reset cause, not SSRS.
Then you could get "Reset cause: WARM-WDG" when issue reset in U-Boot.
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 0728cb9847..9bdbe3c846 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -149,8 +149,6 @@ enum bt_mode get_boot_mode(void)
#define CMC_SRS_POR BIT(1)
#define CMC_SRS_WUP BIT(0)
-static u32 reset_cause = -1;
-
static char *get_reset_cause(char *ret)
{
u32 cause1, cause = 0, srs = 0;
@@ -163,9 +161,7 @@ static char *get_reset_cause(char *ret)
srs = readl(reg_srs);
cause1 = readl(reg_ssrs);
- reset_cause = cause1;
-
- cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
+ cause = srs & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
switch (cause) {
case CMC_SRS_POR:
@@ -175,7 +171,7 @@ static char *get_reset_cause(char *ret)
sprintf(ret, "%s", "WUP");
break;
case CMC_SRS_WARM:
- cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
+ cause = srs & (CMC_SRS_WDG | CMC_SRS_SW |
CMC_SRS_JTAG_RST);
switch (cause) {
case CMC_SRS_WDG:
@@ -193,7 +189,7 @@ static char *get_reset_cause(char *ret)
}
break;
default:
- sprintf(ret, "%s-%X", "UNKN", cause1);
+ sprintf(ret, "%s-%X", "UNKN", srs);
break;
}
--
2.30.0
[PATCH V4 32/44] arm: iMX8ULP: Add boot device relevant functions
From: Ye Li
Read from ROM API to get current boot device.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 +
arch/arm/mach-imx/imx8ulp/soc.c | 84 +++
2 files changed, 85 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 47ee46bdf4..1a142dce72 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -15,4 +15,5 @@ ulong spl_romapi_get_uboot_base(u32 image_offset, u32
rom_bt_dev);
enum bt_mode get_boot_mode(void);
int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
+enum boot_device get_boot_device(void);
#endif
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 8828a94318..add4618440 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -27,6 +28,89 @@ DECLARE_GLOBAL_DATA_PTR;
struct rom_api *g_rom_api = (struct rom_api *)0x1980;
+enum boot_device get_boot_device(void)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 boot;
+ u16 boot_type;
+ u8 boot_instance;
+ enum boot_device boot_dev = SD1_BOOT;
+
+ ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
+ ((uintptr_t)&boot) ^ QUERY_BT_DEV);
+ set_gd(pgd);
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: failure at query_boot_info\n");
+ return -1;
+ }
+
+ boot_type = boot >> 16;
+ boot_instance = (boot >> 8) & 0xff;
+
+ switch (boot_type) {
+ case BT_DEV_TYPE_SD:
+ boot_dev = boot_instance + SD1_BOOT;
+ break;
+ case BT_DEV_TYPE_MMC:
+ boot_dev = boot_instance + MMC1_BOOT;
+ break;
+ case BT_DEV_TYPE_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case BT_DEV_TYPE_FLEXSPINOR:
+ boot_dev = QSPI_BOOT;
+ break;
+ case BT_DEV_TYPE_USB:
+ boot_dev = USB_BOOT;
+ break;
+ default:
+ break;
+ }
+
+ return boot_dev;
+}
+
+bool is_usb_boot(void)
+{
+ return get_boot_device() == USB_BOOT;
+}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int mmc_get_env_dev(void)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 boot;
+ u16 boot_type;
+ u8 boot_instance;
+
+ ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
+ ((uintptr_t)&boot) ^ QUERY_BT_DEV);
+ set_gd(pgd);
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: failure at query_boot_info\n");
+ return CONFIG_SYS_MMC_ENV_DEV;
+ }
+
+ boot_type = boot >> 16;
+ boot_instance = (boot >> 8) & 0xff;
+
+ /* If not boot from sd/mmc, use default value */
+ if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC)
+ return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
+
+ return board_mmc_get_env_dev(boot_instance);
+}
+#endif
+
u32 get_cpu_rev(void)
{
return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0;
--
2.30.0
[PATCH V4 30/44] imx8ulp: unify rdc functions
From: Peng Fan
Unify rdc function to rdc.c
Update soc.c to use new rdc function
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/rdc.h | 27 +++
arch/arm/mach-imx/imx8ulp/rdc.c | 283 +++-
arch/arm/mach-imx/imx8ulp/soc.c | 180 ++-
3 files changed, 317 insertions(+), 173 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx8ulp/rdc.h
diff --git a/arch/arm/include/asm/arch-imx8ulp/rdc.h
b/arch/arm/include/asm/arch-imx8ulp/rdc.h
new file mode 100644
index 00..97463756b0
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/rdc.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8ULP_RDC_H
+#define __ASM_ARCH_IMX8ULP_RDC_H
+
+enum rdc_type {
+ RDC_TRDC,
+ RDC_XRDC,
+};
+
+int release_rdc(enum rdc_type type);
+void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access);
+int xrdc_config_mrc_dx_perm(u32 mrc_con, u32 region, u32 dom, u32 dxsel);
+int xrdc_config_mrc_w0_w1(u32 mrc_con, u32 region, u32 w0, u32 size);
+int xrdc_config_mrc_w3_w4(u32 mrc_con, u32 region, u32 w3, u32 w4);
+int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
+int xrdc_config_pdac_openacc(u32 bridge, u32 index);
+int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool
sec_access);
+int trdc_mrc_region_set_access(u32 mrc_x, u32 dom_x, u32 addr_start, u32
addr_end, bool sec_access);
+
+void xrdc_init_mda(void);
+void xrdc_init_mrc(void);
+
+#endif
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index 7a098718da..e2eca0633e 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -1,18 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 NXP
+ * Copyright 2021 NXP
*/
#include
-#include
-#include
#include
-#include
-#include
+#include
+#include
#include
-#include
-
-DECLARE_GLOBAL_DATA_PTR;
+#include
+#include
+#include
+#include
#define XRDC_ADDR 0x292f
#define MRC_OFFSET 0x2000
@@ -41,6 +40,45 @@ DECLARE_GLOBAL_DATA_PTR;
#define D4SEL_DAT (SP(RW) | SU(RW))
#define D3SEL_DAT SP(RW)
+struct mbc_mem_dom {
+ u32 mem_glbcfg[4];
+ u32 nse_blk_index;
+ u32 nse_blk_set;
+ u32 nse_blk_clr;
+ u32 nsr_blk_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MBC */
+ u32 mem0_blk_cfg_w[64];
+ u32 mem0_blk_nse_w[16];
+ u32 mem1_blk_cfg_w[8];
+ u32 mem1_blk_nse_w[2];
+ u32 mem2_blk_cfg_w[8];
+ u32 mem2_blk_nse_w[2];
+ u32 mem3_blk_cfg_w[8];
+ u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */
+ u32 reserved[2];
+};
+
+struct mrc_rgn_dom {
+ u32 mrc_glbcfg[4];
+ u32 nse_rgn_indirect;
+ u32 nse_rgn_set;
+ u32 nse_rgn_clr;
+ u32 nse_rgn_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MRC */
+ u32 rgn_desc_words[8][2]; /* 8 regions, 2 words per region */
+ u32 reserved[16];
+ u32 rgn_nse;
+ u32 reserved2[15];
+};
+
+struct trdc {
+ u8 res0[0x1000];
+ struct mbc_mem_dom mem_dom[4][8];
+ struct mrc_rgn_dom mrc_dom[2][8];
+};
+
union dxsel_perm {
struct {
u8 dx;
@@ -142,3 +180,232 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32
perm)
return 0;
}
+
+int release_rdc(enum rdc_type type)
+{
+ ulong s_mu_base = 0x2702UL;
+ struct imx8ulp_s400_msg msg;
+ int ret;
+ u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_RELEASE_RDC_REQ_CID;
+ msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */
+
+ mu_hal_init(s_mu_base);
+ mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg));
+ mu_hal_sendmsg(s_mu_base, 1, msg.data[0]);
+
+ ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg);
+ if (!ret) {
+ ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]);
+ if (!ret) {
+ if ((msg.data[0] & 0xff) == 0xd6)
+ return 0;
+ }
+
+ return -EIO;
+ }
+
+ return ret;
+}
+
+void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access)
+{
+ ulong xrdc_base = 0x292f, off;
+ u32 mrgd[5];
+ u8 mrcfg, j, region_num;
+ u8 dsel;
+
+ mrcfg = readb(xrdc_base + 0x140 + mrc_index);
+ region_num = mrcfg & 0x1f;
+
+ for (j = 0; j < region_num; j++) {
+ off = 0x2000 + mrc_index * 0x200 + j * 0x20;
+
+ mrgd[0] = readl(xrdc_base + off);
+ mrgd[1] = readl(xrdc_base + off + 4);
+ mrgd[2] = readl(xrdc_base + off + 8);
+ mrgd[3] = readl(xrdc_base + off + 0xc);
+ mrgd[4] = readl(xrdc_base +
[PATCH V4 31/44] arm: imx8ulp: Probe the S400 MU device in arch init
From: Ye Li
Need probe the S400 MU device in arch_cpu_init_dm, so we can use
S400 API in u-boot
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 35 -
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index c5e20408c6..8828a94318 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -16,6 +16,12 @@
#include
#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -322,7 +328,18 @@ int dram_init(void)
#ifdef CONFIG_SERIAL_TAG
void get_board_serial(struct tag_serialnr *serialnr)
{
- /* TODO */
+ u32 uid[4];
+ u32 res;
+ int ret;
+
+ ret = ahab_read_common_fuse(1, uid, 4, &res);
+ if (ret)
+ printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+ else
+ printf("UID 0x%x,0x%x,0x%x,0x%x\n", uid[0], uid[1], uid[2],
uid[3]);
+
+ serialnr->low = uid[0];
+ serialnr->high = uid[3];
}
#endif
@@ -396,6 +413,22 @@ int arch_cpu_init(void)
return 0;
}
+int arch_cpu_init_dm(void)
+{
+ struct udevice *devp;
+ int node, ret;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"fsl,imx8ulp-mu");
+
+ ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
+ if (ret) {
+ printf("could not get S400 mu %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
#if defined(CONFIG_SPL_BUILD)
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
--
2.30.0
[PATCH V4 29/44] arm: imx8ulp: release trdc and assign lpav from RTD to APD
From: Peng Fan
Rlease LPAV from RTD to APD
Release gpu2D/3D to APD
Set TRDC MBC2 MEM1 for iomuxc0 access
Since upower depends AP/M33 SW to configure IOMUX for its PMIC i2c
and MODE pins. we have to open iomuxc0 access for A35 core (domain 7)
in single boot.
Signed-off-by: Peng Fan
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx8ulp/soc.c | 104 +++-
1 file changed, 103 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 43fe62c2fd..29f7d5be02 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -380,6 +380,102 @@ static int release_rdc(enum rdc_type type)
return ret;
}
+struct mbc_mem_dom {
+ u32 mem_glbcfg[4];
+ u32 nse_blk_index;
+ u32 nse_blk_set;
+ u32 nse_blk_clr;
+ u32 nsr_blk_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MBC */
+ u32 mem0_blk_cfg_w[64];
+ u32 mem0_blk_nse_w[16];
+ u32 mem1_blk_cfg_w[8];
+ u32 mem1_blk_nse_w[2];
+ u32 mem2_blk_cfg_w[8];
+ u32 mem2_blk_nse_w[2];
+ u32 mem3_blk_cfg_w[8];
+ u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */
+ u32 reserved[2];
+};
+
+struct trdc {
+ u8 res0[0x1000];
+ struct mbc_mem_dom mem_dom[4][8];
+};
+
+/* MBC[m]_[d]_MEM[s]_BLK_CFG_W[w] */
+int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, u32 perm)
+{
+ struct trdc *trdc_base = (struct trdc *)0x28031000U;
+ struct mbc_mem_dom *mbc_dom;
+ u32 *cfg_w, *nse_w;
+ u32 index, offset, val;
+
+ mbc_dom = &trdc_base->mem_dom[mbc_x][dom_x];
+
+ switch (mem_x) {
+ case 0:
+ cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8];
+ nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32];
+ break;
+ case 1:
+ cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8];
+ nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32];
+ break;
+ case 2:
+ cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8];
+ nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32];
+ break;
+ case 3:
+ cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8];
+ nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32];
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ index = blk_x % 8;
+ offset = index * 4;
+
+ val = readl((void __iomem *)cfg_w);
+
+ val &= ~(0xFU << offset);
+
+ if (perm == 0x7700) {
+ val |= (0x0 << offset);
+ writel(perm, (void __iomem *)cfg_w);
+ } else if (perm == 0x0077) {
+ val |= (0x8 << offset); /* nse bit set */
+ writel(val, (void __iomem *)cfg_w);
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int trdc_set_access(void)
+{
+ /*
+* CGC0: PBridge0 slot 47
+* trdc_mbc_set_access(2, 7, 0, 47, 0x7700);
+* For secure access, default single boot already support,
+* For non-secure access, need add in future per usecase.
+*/
+trdc_mbc_set_access(2, 7, 0, 49, 0x7700);
+trdc_mbc_set_access(2, 7, 0, 50, 0x7700);
+trdc_mbc_set_access(2, 7, 0, 51, 0x7700);
+trdc_mbc_set_access(2, 7, 0, 52, 0x7700);
+
+trdc_mbc_set_access(2, 7, 0, 47, 0x0077);
+
+/* iomuxc 0 */
+trdc_mbc_set_access(2, 7, 1, 33, 0x7700);
+
+ return 0;
+}
+
static void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access)
{
ulong xrdc_base = 0x292f, off;
@@ -428,8 +524,14 @@ int arch_cpu_init(void)
/* Disable wdog */
init_wdog();
- if (get_boot_mode() == SINGLE_BOOT)
+ if (get_boot_mode() == SINGLE_BOOT) {
release_rdc(RDC_TRDC);
+ trdc_set_access();
+ /* LPAV to APD */
+ setbits_le32(0x2802B044, BIT(7));
+ /* GPU 2D/3D to APD */
+ setbits_le32(0x2802B04C, BIT(1) | BIT(2));
+ }
/* release xrdc, then allow A35 to write SRAM2 */
release_rdc(RDC_XRDC);
--
2.30.0
[PATCH V4 28/44] arm: imx8ulp: add trdc release request
From: Peng Fan
Add TRDC release request, then we could configure resources to be
accessible by A35 Domain.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 62c02a6223..43fe62c2fd 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -344,17 +344,23 @@ static void set_core0_reset_vector(u32 entry)
setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
}
-static int release_xrdc(void)
+enum rdc_type {
+ RDC_TRDC,
+ RDC_XRDC,
+};
+
+static int release_rdc(enum rdc_type type)
{
ulong s_mu_base = 0x2702UL;
struct imx8ulp_s400_msg msg;
int ret;
+ u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_RELEASE_RDC_REQ_CID;
- msg.data[0] = (0x78 << 8) | 0x2; /* A35 XRDC */
+ msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */
mu_hal_init(s_mu_base);
mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg));
@@ -363,13 +369,12 @@ static int release_xrdc(void)
ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg);
if (!ret) {
ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]);
- if (!ret)
- return ret;
+ if (!ret) {
+ if ((msg.data[0] & 0xff) == 0xd6)
+ return 0;
+ }
- if ((msg.data[0] & 0xff) == 0)
- return 0;
- else
- return -EIO;
+ return -EIO;
}
return ret;
@@ -423,8 +428,11 @@ int arch_cpu_init(void)
/* Disable wdog */
init_wdog();
+ if (get_boot_mode() == SINGLE_BOOT)
+ release_rdc(RDC_TRDC);
+
/* release xrdc, then allow A35 to write SRAM2 */
- release_xrdc();
+ release_rdc(RDC_XRDC);
xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);
clock_init();
--
2.30.0
[PATCH V4 27/44] arm: imx8ulp: add rdc support
From: Peng Fan
There is xrdc inside i.MX8ULP, we need to configure permission to make
sure AP non-secure world could access the resources.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 2 +
arch/arm/mach-imx/imx8ulp/Makefile| 2 +-
arch/arm/mach-imx/imx8ulp/rdc.c | 144 ++
3 files changed, 147 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-imx/imx8ulp/rdc.c
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index a8f632f45e..47ee46bdf4 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -13,4 +13,6 @@ extern unsigned long rom_pointer[];
ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
enum bt_mode get_boot_mode(void);
+int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
+int xrdc_config_pdac_openacc(u32 bridge, u32 index);
#endif
diff --git a/arch/arm/mach-imx/imx8ulp/Makefile
b/arch/arm/mach-imx/imx8ulp/Makefile
index 78c81d78bb..1ef6cd5c91 100644
--- a/arch/arm/mach-imx/imx8ulp/Makefile
+++ b/arch/arm/mach-imx/imx8ulp/Makefile
@@ -4,4 +4,4 @@
#
obj-y += lowlevel_init.o
-obj-y += soc.o clock.o iomux.o pcc.o cgc.o
+obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
new file mode 100644
index 00..7a098718da
--- /dev/null
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define XRDC_ADDR 0x292f
+#define MRC_OFFSET 0x2000
+#define MRC_STEP 0x200
+
+#define SP(X) ((X) << 9)
+#define SU(X) ((X) << 6)
+#define NP(X) ((X) << 3)
+#define NU(X) ((X) << 0)
+
+#define RWX7
+#define RW 6
+#define R 4
+#define X 1
+
+#define D7SEL_CODE (SP(RW) | SU(RW) | NP(RWX) | NU(RWX))
+#define D6SEL_CODE (SP(RW) | SU(RW) | NP(RWX))
+#define D5SEL_CODE (SP(RW) | SU(RWX))
+#define D4SEL_CODE SP(RWX)
+#define D3SEL_CODE (SP(X) | SU(X) | NP(X) | NU(X))
+#define D0SEL_CODE 0
+
+#define D7SEL_DAT (SP(RW) | SU(RW) | NP(RW) | NU(RW))
+#define D6SEL_DAT (SP(RW) | SU(RW) | NP(RW))
+#define D5SEL_DAT (SP(RW) | SU(RW) | NP(R) | NU(R))
+#define D4SEL_DAT (SP(RW) | SU(RW))
+#define D3SEL_DAT SP(RW)
+
+union dxsel_perm {
+ struct {
+ u8 dx;
+ u8 perm;
+ };
+
+ u32 dom_perm;
+};
+
+int xrdc_config_mrc_dx_perm(u32 mrc_con, u32 region, u32 dom, u32 dxsel)
+{
+ ulong w2_addr;
+ u32 val = 0;
+
+ w2_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 +
0x8;
+
+ val = (readl(w2_addr) & (~(7 << (3 * dom | (dxsel << (3 * dom));
+ writel(val, w2_addr);
+
+ return 0;
+}
+
+int xrdc_config_mrc_w0_w1(u32 mrc_con, u32 region, u32 w0, u32 size)
+{
+ ulong w0_addr, w1_addr;
+
+ w0_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20;
+ w1_addr = w0_addr + 4;
+
+ if ((size % 32) != 0)
+ return -EINVAL;
+
+ writel(w0 & ~0x1f, w0_addr);
+ writel(w0 + size - 1, w1_addr);
+
+ return 0;
+}
+
+int xrdc_config_mrc_w3_w4(u32 mrc_con, u32 region, u32 w3, u32 w4)
+{
+ ulong w3_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region *
0x20 + 0xC;
+ ulong w4_addr = w3_addr + 4;
+
+ writel(w3, w3_addr);
+ writel(w4, w4_addr);
+
+ return 0;
+}
+
+int xrdc_config_pdac_openacc(u32 bridge, u32 index)
+{
+ ulong w0_addr;
+ u32 val;
+
+ switch (bridge) {
+ case 3:
+ w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index;
+ break;
+ case 4:
+ w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index;
+ break;
+ case 5:
+ w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index;
+ break;
+ default:
+ return -EINVAL;
+ }
+ writel(0xff, w0_addr);
+
+ val = readl(w0_addr + 4);
+ writel(val | BIT(31), w0_addr + 4);
+
+ return 0;
+}
+
+int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm)
+{
+ ulong w0_addr;
+ u32 val;
+
+ switch (bridge) {
+ case 3:
+ w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index;
+ break;
+ case 4:
+ w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index;
+ break;
+ case 5:
+ w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index;
+ break;
+ default:
+ return -EINVAL;
+ }
+ val = readl(w0_addr);
+ writel((val & ~(0x7 << (dom * 3))) | (perm << (dom * 3)), w0_ad
[PATCH V4 25/44] drivers: misc: s400_api: Update API for fuse read and write
From: Ye Li
Add API to support fuse read and write
Signed-off-by: Ye Li
---
arch/arm/include/asm/arch-imx8ulp/s400_api.h | 7 +-
drivers/misc/imx8ulp/s400_api.c | 81
2 files changed, 87 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
index 41ad4002b1..c848f0dfb8 100644
--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
@@ -14,8 +14,11 @@
#define AHAB_AUTH_OEM_CTNR_CID 0x87
#define AHAB_VERIFY_IMG_CID 0x88
#define AHAB_RELEASE_CTNR_CID 0x89
-#define AHAB_RELEASE_RDC_REQ_CID 0xC4
+#define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91
#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95
+#define AHAB_READ_FUSE_REQ_CID 0x97
+#define AHAB_RELEASE_RDC_REQ_CID 0xC4
+#define AHAB_WRITE_FUSE_REQ_CID0xD6
#define S400_MAX_MSG 8U
@@ -32,5 +35,7 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ahab_release_container(u32 *response);
int ahab_verify_image(u32 img_id, u32 *response);
int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
+int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
+int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32
*response);
#endif
diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c
index 315221a463..d76a95febe 100644
--- a/drivers/misc/imx8ulp/s400_api.c
+++ b/drivers/misc/imx8ulp/s400_api.c
@@ -161,3 +161,84 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
return ret;
}
+
+int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32
*response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ if (!fuse_words) {
+ printf("Invalid parameters for fuse read\n");
+ return -EINVAL;
+ }
+
+ if ((fuse_id != 1 && fuse_num != 1) ||
+ (fuse_id == 1 && fuse_num != 4)) {
+ printf("Invalid fuse number parameter\n");
+ return -EINVAL;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_READ_FUSE_REQ_CID;
+ msg.data[0] = fuse_id;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+ __func__, ret, fuse_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ fuse_words[0] = msg.data[1];
+ if (fuse_id == 1) {
+ /* OTP_UNIQ_ID */
+ fuse_words[1] = msg.data[2];
+ fuse_words[2] = msg.data[3];
+ fuse_words[3] = msg.data[4];
+ }
+
+ return ret;
+}
+
+int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 3;
+ msg.command = AHAB_WRITE_FUSE_REQ_CID;
+ msg.data[0] = (32 << 16) | (fuse_id << 5);
+ if (lock)
+ msg.data[0] |= (1 << 31);
+
+ msg.data[1] = fuse_val;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+ __func__, ret, fuse_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
--
2.30.0
[PATCH V4 26/44] arm: imx8ulp: release and configure XRDC at early phase
From: Ye Li
Since S400 will set the memory of SPL image to R/X. We can't write
to any data in SPL image.
1. Set the parameters save/restore only for u-boot, not for SPL. to
avoid write data.
2. Not use MU DM driver but directly call MU API to send release XRDC
to S400 at early phase.
3. Configure the SPL image memory of SRAM2 to writable (R/W/X)
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/mu_hal.h | 12
arch/arm/mach-imx/imx8ulp/lowlevel_init.S | 10 +--
arch/arm/mach-imx/imx8ulp/soc.c| 84 ++
drivers/misc/imx8ulp/imx8ulp_mu.c | 36 +-
4 files changed, 118 insertions(+), 24 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx8ulp/mu_hal.h
diff --git a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
b/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
new file mode 100644
index 00..10d966d5d4
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __IMX8ULP_MU_HAL_H__
+#define __IMX8ULP_MU_HAL_H__
+
+void mu_hal_init(ulong base);
+int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg);
+int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg);
+#endif
diff --git a/arch/arm/mach-imx/imx8ulp/lowlevel_init.S
b/arch/arm/mach-imx/imx8ulp/lowlevel_init.S
index 7d81a75639..791c26407c 100644
--- a/arch/arm/mach-imx/imx8ulp/lowlevel_init.S
+++ b/arch/arm/mach-imx/imx8ulp/lowlevel_init.S
@@ -16,17 +16,11 @@ rom_pointer:
.global save_boot_params
save_boot_params:
+#ifndef CONFIG_SPL_BUILD
/* The firmware provided ATAG/FDT address can be found in r2/x0 */
adr x0, rom_pointer
stp x1, x2, [x0], #16
stp x3, x4, [x0], #16
-
+#endif
/* Returns */
b save_boot_params_ret
-
-.global restore_boot_params
-restore_boot_params:
- adr x0, rom_pointer
- ldp x1, x2, [x0], #16
- ldp x3, x4, [x0], #16
- ret
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 5e7bf57a62..62c02a6223 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -11,6 +11,10 @@
#include
#include
#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -340,9 +344,89 @@ static void set_core0_reset_vector(u32 entry)
setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
}
+static int release_xrdc(void)
+{
+ ulong s_mu_base = 0x2702UL;
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_RELEASE_RDC_REQ_CID;
+ msg.data[0] = (0x78 << 8) | 0x2; /* A35 XRDC */
+
+ mu_hal_init(s_mu_base);
+ mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg));
+ mu_hal_sendmsg(s_mu_base, 1, msg.data[0]);
+
+ ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg);
+ if (!ret) {
+ ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]);
+ if (!ret)
+ return ret;
+
+ if ((msg.data[0] & 0xff) == 0)
+ return 0;
+ else
+ return -EIO;
+ }
+
+ return ret;
+}
+
+static void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access)
+{
+ ulong xrdc_base = 0x292f, off;
+ u32 mrgd[5];
+ u8 mrcfg, j, region_num;
+ u8 dsel;
+
+ mrcfg = readb(xrdc_base + 0x140 + mrc_index);
+ region_num = mrcfg & 0x1f;
+
+ for (j = 0; j < region_num; j++) {
+ off = 0x2000 + mrc_index * 0x200 + j * 0x20;
+
+ mrgd[0] = readl(xrdc_base + off);
+ mrgd[1] = readl(xrdc_base + off + 4);
+ mrgd[2] = readl(xrdc_base + off + 8);
+ mrgd[3] = readl(xrdc_base + off + 0xc);
+ mrgd[4] = readl(xrdc_base + off + 0x10);
+
+ debug("MRC [%u][%u]\n", mrc_index, j);
+ debug("0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
+ mrgd[0], mrgd[1], mrgd[2], mrgd[3], mrgd[4]);
+
+ /* hit */
+ if (addr >= mrgd[0] && addr <= mrgd[1]) {
+ /* find domain 7 DSEL */
+ dsel = (mrgd[2] >> 21) & 0x7;
+ if (dsel == 1) {
+ mrgd[4] &= ~0xFFF;
+ mrgd[4] |= (access & 0xFFF);
+ } else if (dsel == 2) {
+ mrgd[4] &= ~0xFFF;
+ mrgd[4] |= ((access & 0xFFF) << 16);
+ }
+
+ /* not handle other cases, since S400 only set ACCESS1
and 2 */
+ writel(mrgd[4], xrdc_base + off + 0x10);
+ return;
+ }
+ }
+}
+
int arch_cpu_init(void)
{
if (IS_ENABLED(CONF
[PATCH V4 24/44] drivers: misc: imx8ulp: Update S400 API for release RDC
From: Ye Li
The RDC API is updated to add a field for XRDC or TRDC
Signed-off-by: Ye Li
---
arch/arm/include/asm/arch-imx8ulp/s400_api.h | 2 +-
drivers/misc/imx8ulp/s400_api.c | 7 +--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
index 30dab8be24..41ad4002b1 100644
--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
@@ -27,7 +27,7 @@ struct imx8ulp_s400_msg {
u32 data[(S400_MAX_MSG - 1U)];
};
-int ahab_release_rdc(u8 core_id, u32 *response);
+int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response);
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ahab_release_container(u32 *response);
int ahab_verify_image(u32 img_id, u32 *response);
diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c
index 4047d6efee..315221a463 100644
--- a/drivers/misc/imx8ulp/s400_api.c
+++ b/drivers/misc/imx8ulp/s400_api.c
@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int ahab_release_rdc(u8 core_id, u32 *response)
+int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
int size = sizeof(struct imx8ulp_s400_msg);
@@ -30,7 +30,10 @@ int ahab_release_rdc(u8 core_id, u32 *response)
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_RELEASE_RDC_REQ_CID;
- msg.data[0] = core_id;
+ if (xrdc)
+ msg.data[0] = (0x78 << 8) | core_id;
+ else
+ msg.data[0] = (0x74 << 8) | core_id;
ret = misc_call(dev, false, &msg, size, &msg, size);
if (ret)
--
2.30.0
[PATCH V4 23/44] drivers: misc: imx8ulp: Add S400 API for image authentication
From: Ye Li
Add S400 API for image authentication
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/s400_api.h | 8 +-
drivers/misc/imx8ulp/s400_api.c | 121 ++-
2 files changed, 127 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
index 3ba6b525c5..30dab8be24 100644
--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
@@ -15,6 +15,7 @@
#define AHAB_VERIFY_IMG_CID 0x88
#define AHAB_RELEASE_CTNR_CID 0x89
#define AHAB_RELEASE_RDC_REQ_CID 0xC4
+#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95
#define S400_MAX_MSG 8U
@@ -26,5 +27,10 @@ struct imx8ulp_s400_msg {
u32 data[(S400_MAX_MSG - 1U)];
};
-int ahab_release_rdc(u8 core_id);
+int ahab_release_rdc(u8 core_id, u32 *response);
+int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
+int ahab_release_container(u32 *response);
+int ahab_verify_image(u32 img_id, u32 *response);
+int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
+
#endif
diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c
index 82fd3117a4..4047d6efee 100644
--- a/drivers/misc/imx8ulp/s400_api.c
+++ b/drivers/misc/imx8ulp/s400_api.c
@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int ahab_release_rdc(u8 core_id)
+int ahab_release_rdc(u8 core_id, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
int size = sizeof(struct imx8ulp_s400_msg);
@@ -37,5 +37,124 @@ int ahab_release_rdc(u8 core_id)
printf("Error: %s: ret %d, core id %u, response 0x%x\n",
__func__, ret, core_id, msg.data[0]);
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 3;
+ msg.command = AHAB_AUTH_OEM_CTNR_CID;
+ msg.data[0] = upper_32_bits(ctnr_addr);
+ msg.data[1] = lower_32_bits(ctnr_addr);
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, cntr_addr 0x%lx, response 0x%x\n",
+ __func__, ret, ctnr_addr, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_release_container(u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = AHAB_RELEASE_CTNR_CID;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_verify_image(u32 img_id, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_VERIFY_IMG_CID;
+ msg.data[0] = 1 << img_id;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, img_id %u, response 0x%x\n",
+ __func__, ret, img_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_FWD_LIFECYCLE_UP_REQ_CID;
+ msg.data[0] = life_cycle;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, life_cycle 0x%x, response 0x%x\n",
+ __func__, ret, life_cyc
[PATCH V4 21/44] arm: imx8ulp: Update the reset vector in u-boot
From: Ye Li
Because we have set reset vector to ATF in SPL, have to set it back
to ROM for any reset in u-boot
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 35 +
1 file changed, 22 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 051dec1a5a..5e7bf57a62 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -321,21 +321,10 @@ void get_board_serial(struct tag_serialnr *serialnr)
}
#endif
-int arch_cpu_init(void)
+static void set_core0_reset_vector(u32 entry)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD))
- clock_init();
-
- return 0;
-}
-
-#if defined(CONFIG_SPL_BUILD)
-__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
-{
- debug("image entry point: 0x%lx\n", spl_image->entry_point);
-
/* Update SIM1 DGO8 for reset vector base */
- writel((u32)spl_image->entry_point, SIM1_BASE_ADDR + 0x5c);
+ writel(entry, SIM1_BASE_ADDR + 0x5c);
/* set update bit */
setbits_le32(SIM1_BASE_ADDR + 0x8, 0x1 << 24);
@@ -349,6 +338,26 @@ __weak void __noreturn jump_to_image_no_args(struct
spl_image_info *spl_image)
/* clear the ack by set 1 */
setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
+}
+
+int arch_cpu_init(void)
+{
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ clock_init();
+ } else {
+ /* reconfigure core0 reset vector to ROM */
+ set_core0_reset_vector(0x1000);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ debug("image entry point: 0x%lx\n", spl_image->entry_point);
+
+ set_core0_reset_vector((u32)spl_image->entry_point);
/* Enable the 512KB cache */
setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 4));
--
2.30.0
[PATCH V4 22/44] drivers: misc: s400_api: Update S400_SUCCESS_IND to 0xd6
From: Ye Li According to latest S400 API doc, the the success indicate value is changed to 0xd6. So update the driver codes. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/misc/imx8ulp/imx8ulp_mu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c b/drivers/misc/imx8ulp/imx8ulp_mu.c index 3f6dd558e6..f3ca5473e3 100644 --- a/drivers/misc/imx8ulp/imx8ulp_mu.c +++ b/drivers/misc/imx8ulp/imx8ulp_mu.c @@ -185,7 +185,7 @@ static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg, } result = ((struct imx8ulp_s400_msg *)rx_msg)->data[0]; - if ((result & 0xff) == 0) + if ((result & 0xff) == 0xd6) return 0; return -EIO; -- 2.30.0
[PATCH V4 20/44] arm: imx8ulp: disable wdog3
From: Peng Fan
Disable wdog3 which is configured by ROM
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 36 -
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 33aec228e3..051dec1a5a 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -144,9 +144,43 @@ int print_cpuinfo(void)
}
#endif
+#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
+#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
+#define REFRESH_WORD0 0xA602 /* 1st refresh word */
+#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
+
+static void disable_wdog(void __iomem *wdog_base)
+{
+ u32 val_cs = readl(wdog_base + 0x00);
+
+ if (!(val_cs & 0x80))
+ return;
+
+ dmb();
+ __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
+ __raw_writel(REFRESH_WORD1, (wdog_base + 0x04));
+ dmb();
+
+ if (!(val_cs & 800)) {
+ dmb();
+ __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04));
+ __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04));
+ dmb();
+
+ while (!(readl(wdog_base + 0x00) & 0x800))
+ ;
+ }
+ writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
+ writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
+ writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
+
+ while (!(readl(wdog_base + 0x00) & 0x400))
+ ;
+}
+
void init_wdog(void)
{
- /* TODO */
+ disable_wdog((void __iomem *)WDG3_RBASE);
}
static struct mm_region imx8ulp_arm64_mem_map[] = {
--
2.30.0
[PATCH V4 19/44] arm: imx8ulp: Enable full L2 cache in SPL
From: Ye Li
SRAM2 is half L2 cache and default to SRAM after system boot.
To enable the full l2 cache (512KB), it needs to reset A35 to make
the change happen.
So re-implement the jump entry function in SPL:
1. configure the core0 reset vector to entry (ATF)
2. enable the L2 full cache
3. reset A35
So when core0 up, it runs into ATF. And we have 512KB L2 cache working.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 34 +
1 file changed, 34 insertions(+)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index cddcdc2d20..33aec228e3 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -9,6 +9,8 @@
#include
#include
#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -292,3 +294,35 @@ int arch_cpu_init(void)
return 0;
}
+
+#if defined(CONFIG_SPL_BUILD)
+__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ debug("image entry point: 0x%lx\n", spl_image->entry_point);
+
+ /* Update SIM1 DGO8 for reset vector base */
+ writel((u32)spl_image->entry_point, SIM1_BASE_ADDR + 0x5c);
+
+ /* set update bit */
+ setbits_le32(SIM1_BASE_ADDR + 0x8, 0x1 << 24);
+
+ /* polling the ack */
+ while ((readl(SIM1_BASE_ADDR + 0x8) & (0x1 << 26)) == 0)
+ ;
+
+ /* clear the update */
+ clrbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 24));
+
+ /* clear the ack by set 1 */
+ setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
+
+ /* Enable the 512KB cache */
+ setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 4));
+
+ /* reset core */
+ setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 16));
+
+ while (1)
+ ;
+}
+#endif
--
2.30.0
[PATCH V4 16/44] arm: imx8ulp: add clock support
From: Peng Fan
Add i.MX8ULP clock support
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/cgc.h | 130 ++
arch/arm/include/asm/arch-imx8ulp/clock.h| 9 +-
arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 1 +
arch/arm/include/asm/arch-imx8ulp/pcc.h | 139 ++
arch/arm/mach-imx/imx8ulp/Makefile | 2 +-
arch/arm/mach-imx/imx8ulp/cgc.c | 455 +++
arch/arm/mach-imx/imx8ulp/clock.c| 374 ++-
arch/arm/mach-imx/imx8ulp/pcc.c | 449 ++
arch/arm/mach-imx/imx8ulp/soc.c | 3 +
9 files changed, 1558 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx8ulp/cgc.h
create mode 100644 arch/arm/include/asm/arch-imx8ulp/pcc.h
create mode 100644 arch/arm/mach-imx/imx8ulp/cgc.c
create mode 100644 arch/arm/mach-imx/imx8ulp/pcc.c
diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h
b/arch/arm/include/asm/arch-imx8ulp/cgc.h
new file mode 100644
index 00..34a15fb59c
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef _ASM_ARCH_CGC_H
+#define _ASM_ARCH_CGC_H
+
+enum cgc1_clk {
+ DUMMY0_CLK,
+ DUMMY1_CLK,
+ LPOSC,
+ XBAR_BUSCLK,
+ SOSC,
+ SOSC_DIV1,
+ SOSC_DIV2,
+ SOSC_DIV3,
+ FRO,
+ FRO_DIV1,
+ FRO_DIV2,
+ FRO_DIV3,
+ PLL2,
+ PLL3,
+ PLL3_VCODIV,
+ PLL3_PFD0,
+ PLL3_PFD1,
+ PLL3_PFD2,
+ PLL3_PFD3,
+ PLL3_PFD0_DIV1,
+ PLL3_PFD0_DIV2,
+ PLL3_PFD1_DIV1,
+ PLL3_PFD1_DIV2,
+ PLL3_PFD2_DIV1,
+ PLL3_PFD2_DIV2,
+ PLL3_PFD3_DIV1,
+ PLL3_PFD3_DIV2,
+};
+
+struct cgc1_regs {
+ u32 verid;
+ u32 rsvd1[4];
+ u32 ca35clk;
+ u32 rsvd2[2];
+ u32 clkoutcfg;
+ u32 rsvd3[4];
+ u32 nicclk;
+ u32 xbarclk;
+ u32 rsvd4[21];
+ u32 clkdivrst;
+ u32 rsvd5[29];
+ u32 soscdiv;
+ u32 rsvd6[63];
+ u32 frodiv;
+ u32 rsvd7[189];
+ u32 pll2csr;
+ u32 rsvd8[3];
+ u32 pll2cfg;
+ u32 rsvd9;
+ u32 pll2denom;
+ u32 pll2num;
+ u32 pll2ss;
+ u32 rsvd10[55];
+ u32 pll3csr;
+ u32 pll3div_vco;
+ u32 pll3div_pfd0;
+ u32 pll3div_pfd1;
+ u32 pll3cfg;
+ u32 pll3pfdcfg;
+ u32 pll3denom;
+ u32 pll3num;
+ u32 pll3ss;
+ u32 pll3lock;
+ u32 rsvd11[54];
+ u32 enetstamp;
+ u32 rsvd12[67];
+ u32 pllusbcfg;
+ u32 rsvd13[59];
+ u32 aud_clk1;
+ u32 sai5_4_clk;
+ u32 tpm6_7clk;
+ u32 mqs1clk;
+ u32 rsvd14[60];
+ u32 lvdscfg;
+};
+
+struct cgc2_regs {
+ u32 verid;
+ u32 rsvd1[4];
+ u32 hificlk;
+ u32 rsvd2[2];
+ u32 clkoutcfg;
+ u32 rsvd3[6];
+ u32 niclpavclk;
+ u32 ddrclk;
+ u32 rsvd4[19];
+ u32 clkdivrst;
+ u32 rsvd5[29];
+ u32 soscdiv;
+ u32 rsvd6[63];
+ u32 frodiv;
+ u32 rsvd7[253];
+ u32 pll4csr;
+ u32 pll4div_vco;
+ u32 pll4div_pfd0;
+ u32 pll4div_pfd1;
+ u32 pll4cfg;
+ u32 pll4pfdcfg;
+ u32 pll4denom;
+ u32 pll4num;
+ u32 pll4ss;
+ u32 pll4lock;
+ u32 rsvd8[128];
+ u32 aud_clk2;
+ u32 sai7_6_clk;
+ u32 tpm8clk;
+ u32 rsvd9[1];
+ u32 spdifclk;
+ u32 rsvd10[59];
+ u32 lvdscfg;
+};
+
+u32 cgc1_clk_get_rate(enum cgc1_clk clk);
+void cgc1_pll3_init(void);
+void cgc1_pll2_init(void);
+void cgc1_soscdiv_init(void);
+void cgc1_init_core_clk(void);
+void cgc2_pll4_init(void);
+void cgc2_ddrclk_config(u32 src, u32 div);
+u32 cgc1_sosc_div(enum cgc1_clk clk);
+#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h
b/arch/arm/include/asm/arch-imx8ulp/clock.h
index e145c33f01..58e3356e32 100644
--- a/arch/arm/include/asm/arch-imx8ulp/clock.h
+++ b/arch/arm/include/asm/arch-imx8ulp/clock.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2020 NXP
+ * Copyright 2021 NXP
*/
#ifndef _ASM_ARCH_IMX8ULP_CLOCK_H
@@ -17,6 +17,7 @@ enum mxc_clock {
MXC_DDR_CLK,
MXC_ESDHC_CLK,
MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
MXC_I2C_CLK,
};
@@ -26,9 +27,15 @@ u32 get_lpuart_clk(void);
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
u32 imx_get_i2cclk(unsigned int i2c_num);
#endif
+void enable_usboh3_clk(unsigned char enable);
+int enable_usb_pll(ulong usb_phy_base);
#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable);
#endif
void init_clk_usdhc(u32 index);
+void init_clk_fspi(int index);
+void init_clk_ddr(void);
+int set_ddr_clk(u32 phy_freq_mhz);
void clock_init(void);
+void cgc1_enet_stamp_sel(u32 clk_src);
#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
b/arch/arm/include/asm
[PATCH V4 17/44] drivers: mmc: fsl_esdhc_imx: support i.MX8ULP
From: Peng Fan
i.MX8ULP reuse same SDHC IP as i.MX8M, so follow i.MX8M code logic.
Signed-off-by: Peng Fan
---
drivers/mmc/Kconfig | 2 +-
drivers/mmc/fsl_esdhc_imx.c | 12
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 717ce5a62f..1569e8c44a 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -832,7 +832,7 @@ config FSL_ESDHC_IMX
config FSL_USDHC
bool "Freescale/NXP i.MX uSDHC controller support"
- depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT
+ depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMXRT
select FSL_ESDHC_IMX
help
This enables the Ultra Secured Digital Host Controller enhancements
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 465d935daf..aabf39535f 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -291,7 +291,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
{
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
|| \
+ defined(CONFIG_IMX8ULP)
dma_addr_t addr;
#endif
uint wml_value;
@@ -304,7 +305,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
|| \
+ defined(CONFIG_IMX8ULP)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -341,7 +343,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
|| \
+ defined(CONFIG_IMX8ULP)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -406,7 +409,8 @@ static void check_and_invalidate_dcache_range
unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
-#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
|| \
+ defined(CONFIG_IMX8ULP)
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));
--
2.30.0
[PATCH V4 18/44] arm: imx8ulp: soc: Change to use CMC1 to get bootcfg
From: Ye Li
CMC1 also has a MR register for bootcfg
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx8ulp/soc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 6f4b506386..cddcdc2d20 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -23,7 +23,7 @@ enum bt_mode get_boot_mode(void)
{
u32 bt0_cfg = 0;
- bt0_cfg = readl(CMC0_RBASE + 0x80);
+ bt0_cfg = readl(CMC1_BASE_ADDR + 0xa0);
bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
--
2.30.0
