Re: [PATCH v4 11/11] doc:bootmenu: add UEFI boot variable and distro boot support
On 3/24/22 14:54, Masahisa Kojima wrote:
The bootmenu enumerates the UEFI boot variable and distro boot
(boot_targets) for boot device selection.
Signed-off-by: Masahisa Kojima
---
Newly created in v4
doc/usage/bootmenu.rst | 65 ++
In origin/master the file is called doc/usage/cmd/bootmenu.rst.
1 file changed, 65 insertions(+)
diff --git a/doc/usage/bootmenu.rst b/doc/usage/bootmenu.rst
index 1f094ad6ed..dc1d22062b 100644
--- a/doc/usage/bootmenu.rst
+++ b/doc/usage/bootmenu.rst
@@ -93,3 +93,68 @@ When you intend to use the bootmenu on a color frame buffer
console,
make sure to additionally define::
CONFIG_CFB_CONSOLE_ANSI=y
+
+UEFI boot variable enumeration
+==
+
+The bootmenu automatically generates the UEFI boot variable("BOOT")
How do you ensure that those variables that are autogenerated are not saved?
+in order of "BootOrder". When the user selects the UEFI boot
+variable entry, bootmenu sets the selected boot variable index
+to "BootNext", then call the uefi boot manager with the command
+"bootefi bootmgr".
+
+The bootmenu automatically enumerates the possible bootable
+media devices supporting EFI_SIMPLE_FILE_SYSTEM_PROTOCOL.
+
+The bootmenu prints the EFI_LOAD_OPTION.Description[] as title
+of the entry together with "UEFI" prefix and BOOT variable name.
+
+Example bootmenu is as below::
+
+*** U-Boot Boot Menu ***
+
+ UEFI BOOT : mmc0:1
+ UEFI BOOT0001 : mmc0:2
+ UEFI BOOT0002 : debian
+ UEFI BOOT0003 : nvme0:1
+ UEFI BOOT0004 : ubuntu
+ UEFI BOOT0005 : nvme0:2
+ UEFI BOOT0006 : usb0:2
+
+To scan the discoverable devices connected to the buses such as
+USB and PCIe prior to bootmenu showing up, CONFIG_PREBOOT can be
+used to run the command before showing the bootmenu, i.e.::
+
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum; usb start; scsi scan; nvme scan; virtio scan"
+
+distro boot command enumeration
+===
+
+The bootmenu also automatically generates the entries for
+distro boot command. The bootmenu shows the devices in boot_targets
+environment variable.
+When the user selects the distro boot command entry, the bootmenu
+runs the command defined in "bootcmd_xxx" environment variable.
+As an example, if user selects "usb0" entry, bootmenu runs the
+command defined in "bootcmd_usb0".
+
+Example boot_targets::
+
+usb0, scsi0, nvme0, dhcp
+
+Example bootmenu is as below::
+
+*** U-Boot Boot Menu ***
+
+ distro_boot : usb0
+ distro_boot : scsi0
+ distro_boot : nvme0
+ distro_boot : dhcp
+
+Disable to enter the U-Boot console
+===
+
+To improve the product security, U-Boot console can be disabled by::
+
+CONFIG_CMD_BOOTMENU_ENTER_UBOOT_CONSOLE=n
The man page should have a section 'Configuration' which lists all
relevant configuration options for the bootmenu command.
Re: [PATCH v4 00/11] enable menu-driven boot device selection
On 3/24/22 14:54, Masahisa Kojima wrote: This patch series adds the menu-driven boot device selection, by extending the existing "bootmenu" to include UEFI and distro_boot related entries, and supports menu-driven UEFI boot variable maintenance. This patch series also includes the removable media support that UEFI specification requires to support. The menu example is as follows. *** U-Boot Boot Menu *** bootmenu_00 : Boot 1. kernel bootmenu_01 : Boot 2. kernel bootmenu_02 : Reset board UEFI BOOT : debian UEFI BOOT0001 : ubuntu UEFI BOOT0002 : mmc0:1 UEFI BOOT0003 : mmc0:2 UEFI BOOT0004 : nvme0:1 UEFI BOOT0005 : nvme0:2 UEFI BOOT0006 : usb0:2 UEFI BOOT0007 : usb1:1 UEFI BOOT0008 : usb1:2 distro_boot : usb0 distro_boot : scsi0 distro_boot : virtio0 distro_boot : dhcp Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit [Major changes from RFC v3] - add Kconfig option to disable U-Boot console - add UEFI boot variable maintenance feature - support removable media support and user selection - app bootmenu enhancement documentation [How to run on QEMU(arm64)] 1) clone source code $ git clone https://git.linaro.org/people/masahisa.kojima/u-boot.git \ -b kojima/bootmenu_v4_upstream_0324 --depth 1 2) prepare U-Boot .config $ make qemu_arm64_menuconfig then, enable CONFIG_CMD_BOOTMENU and CONFIG_AUTOBOOT_MENU_SHOW 3) run on QEMU(arm64) example $ qemu-system-aarch64 -machine virt,gic-version=3 -cpu cortex-a57 -m 4G -nographic \ -no-acpi -bios ./u-boot.bin -hda xxx.img I applied the series to origin/master. make sandbox_defconfig CONFIG_CMD_BOOTMENU=y CONFIG_AUTOBOOT_MENU_SHOW=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="host bind 0 ../sandbox.img" sandbox.img contains file ubootefi.var defining two boot options 1: Boot0003: test3 2: Boot00A0: hello ./u-boot -T just shows the U-Boot prompt and no menu. What do I miss? Best regards Heinrich AKASHI Takahiro (2): efi_loader: export efi_locate_device_handle() efi_loader: bootmgr: add booting from removable media Masahisa Kojima (9): bootmenu: fix menu API error handling lib/charset: add u16_strlcat() function test: unit test for u16_strlcat() menu: always show the menu regardless of the number or entry bootmenu: add UEFI and disto_boot entries bootmenu: factor out the user input handling efi_loader: add menu-driven UEFI Boot Variable maintenance bootmenu: add removable media entries doc:bootmenu: add UEFI boot variable and distro boot support cmd/Kconfig | 10 + cmd/bootmenu.c| 678 +++ common/menu.c | 139 ++- doc/usage/bootmenu.rst| 65 ++ include/charset.h | 15 + include/config_distro_bootcmd.h | 14 +- include/efi_default_filename.h| 26 + include/efi_loader.h | 63 ++ include/menu.h| 20 + lib/charset.c | 21 + lib/efi_loader/Makefile |1 + lib/efi_loader/efi_bootmenu_maintenance.c | 1244 + lib/efi_loader/efi_bootmgr.c | 50 +- lib/efi_loader/efi_boottime.c | 59 +- lib/efi_loader/efi_console.c | 81 ++ lib/efi_loader/efi_disk.c | 11 + lib/efi_loader/efi_file.c | 75 +- test/unicode_ut.c | 45 + 18 files changed, 2357 insertions(+), 260 deletions(-) create mode 100644 include/efi_default_filename.h create mode 100644 lib/efi_loader/efi_bootmenu_maintenance.c
[PATCH 1/1] doc: correct bootefi.rst
* add link to booti man-page * correct link description for efidebug command * correct punctuation Signed-off-by: Heinrich Schuchardt --- doc/usage/cmd/bootefi.rst | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/doc/usage/cmd/bootefi.rst b/doc/usage/cmd/bootefi.rst index 282f22aac9..31279fc0cb 100644 --- a/doc/usage/cmd/bootefi.rst +++ b/doc/usage/cmd/bootefi.rst @@ -24,7 +24,7 @@ The *bootefi* command is used to launch a UEFI binary which can be either of * UEFI run-time services driver An operating system requires a hardware description which can either be -presented as ACPI table (CONFIG\_GENERATE\_ACPI\_TABLE=y) or as device-tree +presented as ACPI table (CONFIG\_GENERATE\_ACPI\_TABLE=y) or as device-tree. The load address of the device-tree may be provided as parameter *fdt\_addr*. If this address is not specified, the bootefi command will try to fall back in sequence to: @@ -123,6 +123,7 @@ Configuration - To use the *bootefi* command you must specify CONFIG\_CMD\_BOOTEFI=y. +The *bootefi bootmgr* sub-command requries CMD\_BOOTEFI\_BOOTMGR=y. The *bootefi hello* sub-command requries CMD\_BOOTEFI\_HELLO=y. The *bootefi selftest* sub-command depends on CMD\_BOOTEFI\_SELFTEST=y. @@ -130,6 +131,6 @@ See also * *bootm* for launching UEFI binaries packed in FIT images -* *booti*, *bootm*, *bootz* for launching a Linux kernel without using the - UEFI sub-system -* *efidebug* for setting UEFI boot variables +* :doc:`booti`, *bootm*, *bootz* for launching a Linux kernel without + using the UEFI sub-system +* *efidebug* for setting UEFI boot variables and boot options -- 2.34.1
[PATCH v2 1/2] net: eth-uclass: Fix eth_halt
From: qianfan Zhao
eth_device_priv maybe unaccessable after @stop handler due to eth device
is removed in @stop, touch it will trigger data abort.
Fix data abort bug when run dhcp or tftp command via usbnet.
Signed-off-by: qianfan Zhao
---
net/eth-uclass.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 0da0e85be0..2b88b6c145 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -339,8 +339,15 @@ void eth_halt(void)
return;
eth_get_ops(current)->stop(current);
- priv->state = ETH_STATE_PASSIVE;
- priv->running = false;
+
+ /* ethernet device maybe removed when @stop handler, that will cause
+* @priv is freed. get private data again to avoid it
+*/
+ priv = dev_get_uclass_priv(current);
+ if (priv) {
+ priv->state = ETH_STATE_PASSIVE;
+ priv->running = false;
+ }
}
int eth_is_active(struct udevice *dev)
--
2.17.1
[PATCH v2 2/2] net: eth-uclass: Fix data abort when tftp get nonexistent file via usb
From: qianfan Zhao
tftp_handler do eth_halt when TFTP_ERROR, but eth_halt will remove eth
device if it is an usb network. usbeth's private data will be unaccessable
when usb_eth_free_pkt, touch it will trigger data abort.
Next is the console messages:
=> tftp xxx
...
Loading: *
TFTP error: 'open failed: No such file or directory' (1)
Not retrying...
data abort
pc : [<9feb6ba2>] lr : [<9feb6b9f>]
Fix it.
Signed-off-by: qianfan Zhao
---
net/eth-uclass.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 2b88b6c145..c9bba4f8de 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -407,6 +407,13 @@ int eth_rx(void)
flags = 0;
if (ret > 0)
net_process_received_packet(packet, ret);
+
+ /* ethernet maybe halted when packet_handler, check again */
+ if (!eth_is_active(current)) {
+ ret = 0;
+ break;
+ }
+
if (ret >= 0 && eth_get_ops(current)->free_pkt)
eth_get_ops(current)->free_pkt(current, packet, ret);
if (ret <= 0)
--
2.17.1
Re: [PATCH v1] net: eth-uclass: Fix eth_halt
在 2022/4/2 3:26, Ramon Fried 写道: On Mon, Mar 28, 2022 at 9:14 AM wrote: From: qianfan Zhao eth_device_priv maybe unaccessable after @stop handler due to eth device is removed in @stop. Setting private data before @stop handler. This also fix data abort bug when run dhcp or tftp command via usbnet. Signed-off-by: qianfan Zhao --- net/eth-uclass.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 58c308f332..c6eb1bc8f8 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -338,9 +338,14 @@ void eth_halt(void) if (!priv || !priv->running) return; - eth_get_ops(current)->stop(current); - priv->state = ETH_STATE_PASSIVE; Why did you delete this line ? As we all konw priv->state can't set after @stop handler. But some eth driver such as drivers/net/ldpaa_eth/ldpaa_eth.c check @priv->state in @stop handler, do noting if state is ETH_STATE_PASSIVE. So I delete this. But I think it's a mistake when I check source code again. Should get private again after @stop handler and set state to ETH_STATE_PASSIVE if private data available. I will send new patch later. + /* Make sure setting private data before @stop handler, it may remove +* ethernet device and will cause @priv unaccessable. +* eg: +* usb_eth_stop -> usb_gadget_release -> device_remove +*/ priv->running = false; + + eth_get_ops(current)->stop(current); } int eth_is_active(struct udevice *dev) -- 2.17.1
[PATCH] power: domain: ti: Extend use of PTCMD and PTSTAT registers for high PDs
It is possible for power domain IDs to be great than 31. If this
happens, the PTCMD and PTSTAT registers must overflow into adjacent
corresponding PTCMD_H and PTSTAT_H registers for each. Update the driver
to account for this.
Signed-off-by: Dave Gerlach
---
drivers/power/domain/ti-power-domain.c | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/power/domain/ti-power-domain.c
b/drivers/power/domain/ti-power-domain.c
index b45e9b824539..cf20acd1a322 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -16,7 +16,9 @@
#include
#define PSC_PTCMD 0x120
+#define PSC_PTCMD_H0x124
#define PSC_PTSTAT 0x128
+#define PSC_PTSTAT_H 0x12C
#define PSC_PDSTAT 0x200
#define PSC_PDCTL 0x300
#define PSC_MDSTAT 0x800
@@ -115,10 +117,17 @@ static int ti_power_domain_probe(struct udevice *dev)
static int ti_pd_wait(struct ti_pd *pd)
{
u32 ptstat;
+ u32 pdoffset = 0;
+ u32 ptstatreg = PSC_PTSTAT;
int ret;
- ret = readl_poll_timeout(pd->psc->base + PSC_PTSTAT, ptstat,
-!(ptstat & BIT(pd->id)), PD_TIMEOUT);
+ if (pd->id > 31) {
+ pdoffset = 32;
+ ptstatreg = PSC_PTSTAT_H;
+ }
+
+ ret = readl_poll_timeout(pd->psc->base + ptstatreg, ptstat,
+!(ptstat & BIT(pd->id - pdoffset)),
PD_TIMEOUT);
if (ret)
printf("%s: psc%d, pd%d failed to transition.\n", __func__,
@@ -129,7 +138,15 @@ static int ti_pd_wait(struct ti_pd *pd)
static void ti_pd_transition(struct ti_pd *pd)
{
- psc_write(BIT(pd->id), pd->psc, PSC_PTCMD);
+ u32 pdoffset = 0;
+ u32 ptcmdreg = PSC_PTCMD;
+
+ if (pd->id > 31) {
+ pdoffset = 32;
+ ptcmdreg = PSC_PTCMD_H;
+ }
+
+ psc_write(BIT(pd->id - pdoffset), pd->psc, ptcmdreg);
}
u8 ti_pd_state(struct ti_pd *pd)
--
2.35.0
Re: [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP
On 4/1/22 23:28, Tim Harvey wrote:
On Fri, Apr 1, 2022 at 7:32 AM Marek Vasut wrote:
The i.MX8MP glue needs to be configured based on a couple of DT
properties, implement .glue_configure callback to parse those DT
properties and configure the glue accordingly.
Signed-off-by: Marek Vasut
Cc: Angus Ainslie
Cc: Bin Meng
Cc: Fabio Estevam
Cc: Kunihiko Hayashi
Cc: Michal Simek
Cc: Peng Fan
Cc: Stefano Babic
---
drivers/usb/dwc3/dwc3-generic.c | 52 +
1 file changed, 52 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 7e3814207e4..6cf844cb483 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -223,6 +223,57 @@ struct dwc3_glue_ops {
enum usb_dr_mode mode);
};
+void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
+ enum usb_dr_mode mode)
+{
+/* USB glue registers */
+#define USB_CTRL0 0x00
+#define USB_CTRL1 0x04
+
+#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
+#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
+#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
+
+#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
+#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
+ fdt_addr_t regs = dev_read_addr_index(dev, 1);
+ void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
+ u32 value;
+
+ value = readl(base + USB_CTRL0);
+
+ if (dev_read_bool(dev, "fsl,permanently-attached"))
+ value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
+ else
+ value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
+
+ if (dev_read_bool(dev, "fsl,disable-port-power-control"))
+ value &= ~(USB_CTRL0_PORTPWR_EN);
+ else
+ value |= USB_CTRL0_PORTPWR_EN;
+
+ writel(value, base + USB_CTRL0);
+
+ value = readl(base + USB_CTRL1);
+ if (dev_read_bool(dev, "fsl,over-current-active-low"))
+ value |= USB_CTRL1_OC_POLARITY;
+ else
+ value &= ~USB_CTRL1_OC_POLARITY;
+
+ if (dev_read_bool(dev, "fsl,power-active-low"))
+ value |= USB_CTRL1_PWR_POLARITY;
+ else
+ value &= ~USB_CTRL1_PWR_POLARITY;
+
+ writel(value, base + USB_CTRL1);
+
+ unmap_physmem(base, MAP_NOCACHE);
+}
+
+struct dwc3_glue_ops imx8mp_ops = {
+ .glue_configure = dwc3_imx8mp_glue_configure,
+};
+
void dwc3_ti_glue_configure(struct udevice *dev, int index,
enum usb_dr_mode mode)
{
@@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "rockchip,rk3328-dwc3" },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "qcom,dwc3" },
+ { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)_ops },
{ .compatible = "fsl,imx8mq-dwc3" },
{ .compatible = "intel,tangier-dwc3" },
{ }
--
2.35.1
Marek,
Looks like your working on IMX8MP USB support - thanks for that!
I'm working on bring-up of an IMX8MP board and can test your
power-domain and USB patches but I'm having trouble getting some of
your patches to apply - do you have a repo I can pull from?
https://source.denx.de/u-boot/custodians/u-boot-usb/-/commits/imx-8mp
Re: [PATCH v3 27/29] serial: sandbox: Implement puts
On Tue, Mar 22, 2022 at 04:59:35PM -0400, Sean Anderson wrote: > This implements puts for sandbox. It is fairly straightforward, except > that we break out the shared color printing functionality into its own > function. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass This breaks the "handoff" test at least, and perhaps others, on sandbox*. -- Tom signature.asc Description: PGP signature
Re: The contradictory nature of spl_nand_fit_read
Hi Sean
On Fri, Apr 1, 2022 at 8:53 PM Sean Anderson wrote:
>
>
>
> On 4/1/22 2:46 PM, Sean Anderson wrote:
> > Hi all,
> >
> > I don't understand how spl_nand_fit_read is supposed to work. This
> > function has been seemingly hacked together by multiple people over the
> > years, and it (presumably) (somehow) works despite mass confusion of
> > units. I tried to do some refactoring, but the contradictions make it
> > very difficult to determine what is a bug and what is intentional.
> >
> > Lets start with the basics. spl_nand_fit_read is used to implement
> > spl_load_info.load. I've reproduced the documentation for this function
> > below:
> >
> >> read() - Read from device
> >>
> >> @load: Information about the load state
> >> @sector: Sector number to read from (each @load->bl_len bytes)
> >> @count: Number of sectors to read
> >> @buf: Buffer to read into
> >> @return number of sectors read, 0 on error
> >
> > In particular, both @sector and @count are in units of load.bl_len. In
> > addition, the return value should be @count on success.
> >
> >> static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
> >> ulong size, void *dst)
> >> {
> >> int err;
> >> #ifdef CONFIG_SYS_NAND_BLOCK_SIZE
> >
> > The following logic was introduced in commit 9f6a14c47f ("spl: fit:
> > nand: fix fit loading in case of bad blocks"). However, at the time it
> > was not guarded by the above ifdef. nand_spl_adjust_offset is not
> > defined for all nand drivers. It is defined for at least mxs, am335x,
> > atmel, and simple. Additionally, some drivers (such as rockchip)
> > implement bad block skipping in nand_spl_load_image.
> >
> > It's not at all clear to me that there is common config which determines
> > whether nand_spl_adjust_offset is implemented. Nevertheless, in commit
> > aa0032f672 ("spl: fit: nand: allow for non-page-aligned elements"), the
> > above directive selects different code if CONFIG_SYS_NAND_BLOCK_SIZE is
> > defined.
> >
> >> ulong sector;
> >>
> >> sector = *(int *)load->priv;
> >
> > This is the offset passed to nand_spl_load_image. This
> > offset is in units of bytes, and is aligned to the block size. However,
> > it is *not* set if CONFIG_SPL_LOAD_IMX_CONTAINER is enabled. Oops.
> >
> >> offs = sector + nand_spl_adjust_offset(sector, offs - sector);
>
> I forgot to mention this, but this also adds sector to offs, but offs already
> includes the sector:
>
> > return spl_load_simple_fit(spl_image, , offset / bl_len, header);
The spl_nand_fit_read was called from info->read that was in units of sectors
count = info->read(info, sector, sectors, fit);
debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu, size=0x%lx\n",
sector, sectors, fit, count, size);
load.dev = NULL;
load.priv =
load.filename = NULL;
load.bl_len = 1;
load.read = spl_nand_fit_read;
static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
ulong size, void *dst)
{
ulong sector;
int ret;
sector = *(int *)load->priv;
offs = sector + nand_spl_adjust_offset(sector, offs - sector);
ret = nand_spl_load_image(offs, size, dst);
if (!ret)
return size;
else
return 0;
}
Sorry it's a bit of time and I think that we are discussing about this
commit at the time was introduced
Michael
>
> Which means that we add in sector twice (but with different units!)
>
> > The documentation for this this function is as follows
> >
> >> nand_spl_adjust_offset - Adjust offset from a starting sector
> >> @sector: Address of the sector
> >> @offs: Offset starting from @sector
> >>
> >> If one or more bad blocks are in the address space between @sector
> >> and @sector + @offs, @offs is increased by the NAND block size for
> >> each bad block found.
> >
> > In particular, note that offs is in units of bytes. However, we know
> > from above that at this point in the function, offs is in units of
> > bl_len. Oops.
> >
> >> #else
> >> offs *= load->bl_len;
> >> size *= load->bl_len;
> >
> > This code path adjusts both offs and size to be in units of
>
> *units of bytes
>
> >> #endif
> >> err = nand_spl_load_image(offs, size, dst);
> >
> > So by the time we get here, one code path is in units of bytes, and the
> > other is in units of bl_len. nand_spl_load_image seems to expect bytes
> > (though there is no documentation, so I can't be sure). Which of course
> > begs the question: how did the code introduced in 9f6a14c47f ever work?
> >
> >> if (err)
> >> return 0;
> >>
> >> return size / load->bl_len;
> >
> > And of course, this should only be done if size is in units of bytes.
> >
> >> }
> >
> > I have some patches for what I think are bugs, but the logic of this
> > function is so confused that I am unable to determine if they actually
> > are bugs. I would greatly appreciate if some of
Re: [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP
On Fri, Apr 1, 2022 at 7:32 AM Marek Vasut wrote:
>
> The i.MX8MP glue needs to be configured based on a couple of DT
> properties, implement .glue_configure callback to parse those DT
> properties and configure the glue accordingly.
>
> Signed-off-by: Marek Vasut
> Cc: Angus Ainslie
> Cc: Bin Meng
> Cc: Fabio Estevam
> Cc: Kunihiko Hayashi
> Cc: Michal Simek
> Cc: Peng Fan
> Cc: Stefano Babic
> ---
> drivers/usb/dwc3/dwc3-generic.c | 52 +
> 1 file changed, 52 insertions(+)
>
> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
> index 7e3814207e4..6cf844cb483 100644
> --- a/drivers/usb/dwc3/dwc3-generic.c
> +++ b/drivers/usb/dwc3/dwc3-generic.c
> @@ -223,6 +223,57 @@ struct dwc3_glue_ops {
>enum usb_dr_mode mode);
> };
>
> +void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
> + enum usb_dr_mode mode)
> +{
> +/* USB glue registers */
> +#define USB_CTRL0 0x00
> +#define USB_CTRL1 0x04
> +
> +#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
> +#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
> +#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
> +
> +#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
> +#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
> + fdt_addr_t regs = dev_read_addr_index(dev, 1);
> + void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
> + u32 value;
> +
> + value = readl(base + USB_CTRL0);
> +
> + if (dev_read_bool(dev, "fsl,permanently-attached"))
> + value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> + else
> + value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> +
> + if (dev_read_bool(dev, "fsl,disable-port-power-control"))
> + value &= ~(USB_CTRL0_PORTPWR_EN);
> + else
> + value |= USB_CTRL0_PORTPWR_EN;
> +
> + writel(value, base + USB_CTRL0);
> +
> + value = readl(base + USB_CTRL1);
> + if (dev_read_bool(dev, "fsl,over-current-active-low"))
> + value |= USB_CTRL1_OC_POLARITY;
> + else
> + value &= ~USB_CTRL1_OC_POLARITY;
> +
> + if (dev_read_bool(dev, "fsl,power-active-low"))
> + value |= USB_CTRL1_PWR_POLARITY;
> + else
> + value &= ~USB_CTRL1_PWR_POLARITY;
> +
> + writel(value, base + USB_CTRL1);
> +
> + unmap_physmem(base, MAP_NOCACHE);
> +}
> +
> +struct dwc3_glue_ops imx8mp_ops = {
> + .glue_configure = dwc3_imx8mp_glue_configure,
> +};
> +
> void dwc3_ti_glue_configure(struct udevice *dev, int index,
> enum usb_dr_mode mode)
> {
> @@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
> { .compatible = "rockchip,rk3328-dwc3" },
> { .compatible = "rockchip,rk3399-dwc3" },
> { .compatible = "qcom,dwc3" },
> + { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)_ops },
> { .compatible = "fsl,imx8mq-dwc3" },
> { .compatible = "intel,tangier-dwc3" },
> { }
> --
> 2.35.1
>
Marek,
Looks like your working on IMX8MP USB support - thanks for that!
I'm working on bring-up of an IMX8MP board and can test your
power-domain and USB patches but I'm having trouble getting some of
your patches to apply - do you have a repo I can pull from?
Best Regards,
Tim
Re: [PATCH 5/6] net: add MV88E61xx DSA driver
On Thu, Mar 31, 2022 at 3:30 AM Marek Behún wrote: > > On Wed, 30 Mar 2022 08:46:06 -0700 > Tim Harvey wrote: > > > On Tue, Mar 29, 2022 at 4:22 PM Marek Behún wrote: > > > > > > On Tue, 29 Mar 2022 15:52:39 -0700 > > > Tim Harvey wrote: > > > > > > > Add a DSA driver for the MV88E61xx compatible GbE Ethernet switches. > > > > > > > > Signed-off-by: Tim Harvey > > > > > > > Marek, > > > > Thanks for looking at this. > > > > > Is this final version that should be accepted? > > > > This is the first submission of the new driver. > > > > > > > > The drivers seems to support not only 61xx, but 6xxx (6096, 6250, 6352, > > > ...). > > > > It should also support all the same devices that the non dsa driver it > > was derived from (drivers/net/phy/mv88e61xx.c) but I only have a board > > with 88E6176 to test with. > > > > It is not completely clear to me what devices are supported in the > > original driver per Kconfig but from looking over the code I would say > > the following appear to be supported: > > mv88e6096 > > mv88e6097 > > mv88e6020 > > mv88e6070 > > mv88e6071 > > mv88e6172 > > mv88e6176 > > mv88e6220 > > mv88e6240 > > mv88e6250 > > mv88e6352 > > > > > > > > Also there are some commented lines, for example > > > > > > > +// u16 port_stat_link_mask;/* Bitmask for port link status bits */ > > > > +// u16 port_stat_dup_mask; /* Bitmask for port duplex status bits */ > > > > +// u8 port_stat_speed_width;/* Width of speed status bitfield */ > > > > > > What is their purpose? > > > > > > > oops... that was a mistake. I'm surprised checkpatch didn't catch > > those. Those were in the non-dsa driver and not used here so will be > > removed. > > > > > Why is mv88e61xx_dsa_xmit() no-op? > > > > For DSA dsa-uclass calls the switch master eth device send function > > after calling the dsa_ops->xmit function so that a dsa driver can add > > any header/footer if needed. The function is required but in my case I > > don't care about header/footer tagging or vlan as only 1 port is > > active at a time in U-Boot so I just return success. > > So if I make one port active, the other are completely disabled? They > won't even switch? Is that how DSA uclass is supposed to work in U-Boot? > > I would think that it should be somehow configurable instead. > Marek, I'll let Vladimir correct me if I'm wrong but my understanding is DSA in U-Boot is not intended to allow switches to forward packets on their own from port to port but instead just for forwarding packets between the active port and the MAC connected to the CPU (at least that's what I intended when I wrote the ksz9477 dsa driver previously). In my opinion what a DSA driver provides is avoidance of putting switches in forwarding mode having the potential of easily creating bridge loops. With the existing mv88e61xx driver I've had users create bridge loops often. Best regards, Tim
Re: [PATCH] net: tftp: fix tftp server initialization
On Thu, Mar 31, 2022 at 2:50 PM Arjan Minzinga Zijlstra wrote: > > Some globals where not properly initialized causing timeouts > as data packets where not immediately acknowledged. I don't see a scenario where these two variables will not be initialized. Can you please elaborate ? > > Signed-off-by: Arjan Minzinga Zijlstra > --- > net/tftp.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/net/tftp.c b/net/tftp.c > index 62a9648474..9d5fe2f2d9 100644 > --- a/net/tftp.c > +++ b/net/tftp.c > @@ -912,6 +912,8 @@ void tftp_start_server(void) > tftp_block_size = TFTP_BLOCK_SIZE; > tftp_cur_block = 0; > tftp_our_port = WELL_KNOWN_PORT; > + tftp_windowsize = 1; > + tftp_next_ack = tftp_windowsize; > > #ifdef CONFIG_TFTP_TSIZE > tftp_tsize = 0; > -- > 2.25.1
Re: [PATCH 2/6] net: dsa: move cpu port probe to dsa_post_probe
On Wed, Mar 30, 2022 at 1:52 AM Tim Harvey wrote:
>
> In order to ensure that a DSA driver probe gets called before
> dsa_ops->port_probe move the port_probe of the cpu_port to
> a post-probe function.
>
> Signed-off-by: Tim Harvey
> ---
> net/dsa-uclass.c | 14 +++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c
> index 9ff55a02fb23..07edc584daf3 100644
> --- a/net/dsa-uclass.c
> +++ b/net/dsa-uclass.c
> @@ -466,8 +466,6 @@ static int dsa_pre_probe(struct udevice *dev)
> {
> struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
> struct dsa_priv *priv = dev_get_uclass_priv(dev);
> - struct dsa_ops *ops = dsa_get_ops(dev);
> - int err;
>
> priv->num_ports = pdata->num_ports;
> priv->cpu_port = pdata->cpu_port;
> @@ -480,6 +478,15 @@ static int dsa_pre_probe(struct udevice *dev)
> uclass_find_device_by_ofnode(UCLASS_ETH, pdata->master_node,
> >master_dev);
>
> + return 0;
> +}
> +
> +static int dsa_post_probe(struct udevice *dev)
> +{
> + struct dsa_priv *priv = dev_get_uclass_priv(dev);
> + struct dsa_ops *ops = dsa_get_ops(dev);
> + int err;
> +
> /* Simulate a probing event for the CPU port */
> if (ops->port_probe) {
> err = ops->port_probe(dev, priv->cpu_port,
> @@ -489,13 +496,14 @@ static int dsa_pre_probe(struct udevice *dev)
> }
>
> return 0;
> -}
> +};
>
> UCLASS_DRIVER(dsa) = {
> .id = UCLASS_DSA,
> .name = "dsa",
> .post_bind = dsa_post_bind,
> .pre_probe = dsa_pre_probe,
> + .post_probe = dsa_post_probe,
> .per_device_auto = sizeof(struct dsa_priv),
> .per_device_plat_auto = sizeof(struct dsa_pdata),
> .per_child_plat_auto = sizeof(struct dsa_port_pdata),
> --
> 2.17.1
>
Reviewed-by: Ramon Fried
Re: [PATCH 1/6] net: mdio-uclass: scan for dm mdio children on post-bind
On Wed, Mar 30, 2022 at 1:52 AM Tim Harvey wrote: > > If a DM_MDIO driver is used we need to scan the subnodes as well. > > Signed-off-by: Tim Harvey > Signed-off-by: Vladimir Oltean > --- > net/mdio-uclass.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c > index e74e34f78f9c..190cb08b31d8 100644 > --- a/net/mdio-uclass.c > +++ b/net/mdio-uclass.c > @@ -59,7 +59,11 @@ static int dm_mdio_post_bind(struct udevice *dev) > return -EINVAL; > } > > +#if CONFIG_IS_ENABLED(OF_REAL) > + return dm_scan_fdt_dev(dev); > +#else > return 0; > +#endif > } > > /* > -- > 2.17.1 > Reviewed-by: Ramon Fried
Re: [PATCH u-boot-net v3 00/14] u-boot-net refactors, fixes, cleanups
On Tue, Mar 29, 2022 at 11:08 PM Marek Behún wrote: > > From: Marek Behún > > Hello, > > this is v3 of https://patchwork.ozlabs.org/project/uboot/list/?series=290889. > > Changes since v2: > - added UT tests for ofnode_get_phy_node() and ofnode_get_phy_mode(), as > requested by Simon > > Marek Behún (14): > net: mdio-uclass: fix type for phy_mode_str and phy_handle_str > net: mdio-uclass: use ARRAY_SIZE() > net: introduce helpers to get PHY ofnode from MAC > net: mdio-uclass: add wrappers for read/write/reset operations > treewide: use dm_mdio_read/write/reset() wrappers > net: phy: fix parsing wrong property > net: introduce helpers to get PHY interface mode from a device/ofnode > treewide: Rename PHY_INTERFACE_MODE_COUNT to PHY_INTERFACE_MODE_MAX > treewide: Rename PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA > phy: Move PHY_INTERFACE_MODE_NA to the beginning of the enum > definition > net: phy: xilinx: Check interface type in ->config(), not ->probe() > net: phy: use ->is_c45 instead of is_10g_interface() > bcmgenet, sun8i_emac: Don't connect PHY two times > net: phy: don't require PHY interface mode during PHY creation > > arch/sandbox/dts/test.dts | 12 ++ > board/CZ.NIC/turris_mox/turris_mox.c| 2 +- > board/boundary/nitrogen6x/nitrogen6x.c | 2 +- > board/freescale/corenet_ds/eth_hydra.c | 2 +- > board/freescale/corenet_ds/eth_superhydra.c | 4 +- > board/freescale/t104xrdb/eth.c | 4 +- > board/gdsys/a38x/controlcenterdc.c | 7 +- > board/gdsys/a38x/ihs_phys.c | 6 +- > board/st/stm32f746-disco/stm32f746-disco.c | 13 +-- > drivers/core/ofnode.c | 44 > drivers/core/read.c | 10 ++ > drivers/net/ag7xxx.c| 9 +- > drivers/net/altera_tse.c| 17 +-- > drivers/net/bcm6348-eth.c | 8 +- > drivers/net/bcmgenet.c | 12 +- > drivers/net/designware.c| 10 +- > drivers/net/dwc_eth_qos.c | 40 +-- > drivers/net/ethoc.c | 4 +- > drivers/net/fec_mxc.c | 15 +-- > drivers/net/fm/b4860.c | 8 +- > drivers/net/fm/eth.c| 13 +-- > drivers/net/fm/init.c | 8 +- > drivers/net/fm/ls1043.c | 6 +- > drivers/net/fm/ls1046.c | 8 +- > drivers/net/fm/p1023.c | 4 +- > drivers/net/fm/p4080.c | 6 +- > drivers/net/fm/p5020.c | 6 +- > drivers/net/fm/p5040.c | 6 +- > drivers/net/fm/t1024.c | 4 +- > drivers/net/fm/t1040.c | 4 +- > drivers/net/fm/t2080.c | 6 +- > drivers/net/fm/t4240.c | 6 +- > drivers/net/fsl_enetc.c | 13 +-- > drivers/net/ftgmac100.c | 11 +- > drivers/net/higmacv300.c| 9 +- > drivers/net/ldpaa_eth/ldpaa_eth.c | 28 + > drivers/net/ldpaa_eth/ldpaa_wriop.c | 10 +- > drivers/net/ldpaa_eth/ls1088a.c | 4 +- > drivers/net/ldpaa_eth/ls2080a.c | 4 +- > drivers/net/ldpaa_eth/lx2160a.c | 4 +- > drivers/net/macb.c | 10 +- > drivers/net/mdio_mux_sandbox.c | 6 +- > drivers/net/mscc_eswitch/jr2_switch.c | 2 +- > drivers/net/mscc_eswitch/luton_switch.c | 2 +- > drivers/net/mscc_eswitch/ocelot_switch.c| 2 +- > drivers/net/mscc_eswitch/serval_switch.c| 2 +- > drivers/net/mscc_eswitch/servalt_switch.c | 2 +- > drivers/net/mt7620-eth.c| 45 +++- > drivers/net/mtk_eth.c | 8 +- > drivers/net/mvgbe.c | 7 +- > drivers/net/mvneta.c| 11 +- > drivers/net/mvpp2.c | 9 +- > drivers/net/pch_gbe.c | 4 +- > drivers/net/phy/aquantia.c | 2 +- > drivers/net/phy/phy.c | 115 +++- > drivers/net/phy/xilinx_gmii2rgmii.c | 14 +-- > drivers/net/pic32_eth.c | 11 +- > drivers/net/qe/dm_qe_uec.c | 11 +- > drivers/net/ravb.c | 19 +--- > drivers/net/sh_eth.c| 19 +--- > drivers/net/sni_ave.c | 16 +-- > drivers/net/sni_netsec.c| 10 +- > drivers/net/sun8i_emac.c| 13 +-- > drivers/net/sunxi_emac.c| 5 +- > drivers/net/ti/am65-cpsw-nuss.c | 15 +-- > drivers/net/ti/cpsw.c | 10 +- > drivers/net/ti/keystone_net.c | 24 ++-- >
Re: [PATCH v1] net: eth-uclass: Fix eth_halt
On Mon, Mar 28, 2022 at 9:14 AM wrote: > > From: qianfan Zhao > > eth_device_priv maybe unaccessable after @stop handler due to eth device > is removed in @stop. Setting private data before @stop handler. > > This also fix data abort bug when run dhcp or tftp command via usbnet. > > Signed-off-by: qianfan Zhao > --- > net/eth-uclass.c | 9 +++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/net/eth-uclass.c b/net/eth-uclass.c > index 58c308f332..c6eb1bc8f8 100644 > --- a/net/eth-uclass.c > +++ b/net/eth-uclass.c > @@ -338,9 +338,14 @@ void eth_halt(void) > if (!priv || !priv->running) > return; > > - eth_get_ops(current)->stop(current); > - priv->state = ETH_STATE_PASSIVE; Why did you delete this line ? > + /* Make sure setting private data before @stop handler, it may remove > +* ethernet device and will cause @priv unaccessable. > +* eg: > +* usb_eth_stop -> usb_gadget_release -> device_remove > +*/ > priv->running = false; > + > + eth_get_ops(current)->stop(current); > } > > int eth_is_active(struct udevice *dev) > -- > 2.17.1 >
Re: [PATCH v2 2/2] net: eth-uclass: Fix data abort when tftp get nonexistent file via usb
On Mon, Mar 28, 2022 at 12:58 PM wrote:
>
> From: qianfan Zhao
>
> tftp_handler do eth_halt when TFTP_ERROR, but eth_halt will remove eth
> device if it is an usb network. usbeth's private data will be unaccessable
> when usb_eth_free_pkt, touch it will trigger data abort.
>
> Next is the console messages:
>
> => tftp xxx
> ...
> Loading: *
> TFTP error: 'open failed: No such file or directory' (1)
> Not retrying...
> data abort
> pc : [<9feb6ba2>] lr : [<9feb6b9f>]
>
> Fix it.
>
> Signed-off-by: qianfan Zhao
> ---
> net/eth-uclass.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/net/eth-uclass.c b/net/eth-uclass.c
> index c6eb1bc8f8..27baf52c26 100644
> --- a/net/eth-uclass.c
> +++ b/net/eth-uclass.c
> @@ -405,6 +405,13 @@ int eth_rx(void)
> flags = 0;
> if (ret > 0)
> net_process_received_packet(packet, ret);
> +
> + /* ethernet maybe halted when packet_handler, check again */
> + if (!eth_is_active(current)) {
> + ret = 0;
> + break;
> + }
> +
> if (ret >= 0 && eth_get_ops(current)->free_pkt)
> eth_get_ops(current)->free_pkt(current, packet, ret);
> if (ret <= 0)
> --
> 2.17.1
>
Reviewed-by: Ramon Fried
Re: [PATCH] net: phy: dp83867: Fix a never true comparison
On Fri, Apr 1, 2022 at 6:32 PM Ramon Fried wrote:
>
> On Sat, Mar 19, 2022 at 4:02 PM wrote:
> >
> > From: Haolin Li
> >
> > The type of the return value of phy_read() and phy_read_mmd() is int.
> > Change the variable to not be unsigned so that we not get into an
> > unsigned compared against 0.
> >
> > Signed-off-by: Haolin Li
> > ---
> > drivers/net/phy/dp83867.c | 7 +--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
> > index eada4541c9..c5d44f4629 100644
> > --- a/drivers/net/phy/dp83867.c
> > +++ b/drivers/net/phy/dp83867.c
> > @@ -266,7 +266,7 @@ static int dp83867_of_init(struct phy_device *phydev)
> > static int dp83867_config(struct phy_device *phydev)
> > {
> > struct dp83867_private *dp83867;
> > - unsigned int val, delay, cfg2;
> > + int val, delay, cfg2;
> > int ret, bs;
> >
> > dp83867 = (struct dp83867_private *)phydev->priv;
> > @@ -291,8 +291,11 @@ static int dp83867_config(struct phy_device *phydev)
> >
> > if (phy_interface_is_rgmii(phydev)) {
> > val = phy_read(phydev, MDIO_DEVAD_NONE,
> > MII_DP83867_PHYCTRL);
> > - if (val < 0)
> > + if (val < 0) {
> > + ret = val;
> > goto err_out;
> > + }
> > +
> > val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
> > val |= (dp83867->fifo_depth <<
> > DP83867_PHYCR_FIFO_DEPTH_SHIFT);
> >
> > --
> > 2.25.1
> >
> Reviewed-by: Ramon Fried
Applied to u-boot-net/next
Thanks,
Ramon
[PATCH v5 6/8] FMP: Remove GUIDs for FIT and raw images
The capsule update code has been modified for getting the image GUID
values from the platform code. With this, each image now has a unique
GUID value. With this change, there is no longer a need for defining
GUIDs for FIT and raw images. Remove these GUID values.
Signed-off-by: Sughosh Ganu
Reviewed-by: Ilias Apalodimas
---
Changes since V4: None
include/efi_api.h | 8
lib/efi_loader/efi_firmware.c | 4
2 files changed, 12 deletions(-)
diff --git a/include/efi_api.h b/include/efi_api.h
index 982c200172..c7f7873b5d 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -1967,14 +1967,6 @@ struct efi_signature_list {
EFI_GUID(0x86c77a67, 0x0b97, 0x4633, 0xa1, 0x87, \
0x49, 0x10, 0x4d, 0x06, 0x85, 0xc7)
-#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID \
- EFI_GUID(0xae13ff2d, 0x9ad4, 0x4e25, 0x9a, 0xc8, \
-0x6d, 0x80, 0xb3, 0xb2, 0x21, 0x47)
-
-#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID \
- EFI_GUID(0xe2bb9c06, 0x70e9, 0x4b14, 0x97, 0xa3, \
-0x5a, 0x79, 0x13, 0x17, 0x6e, 0x3f)
-
#define IMAGE_ATTRIBUTE_IMAGE_UPDATABLE0x0001
#define IMAGE_ATTRIBUTE_RESET_REQUIRED 0x0002
#define IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED0x0004
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index cbfa57f64f..38a0e43b6a 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -206,8 +206,6 @@ static efi_status_t efi_fill_image_desc_array(
* - versioning of firmware image
* - package information
*/
-const efi_guid_t efi_firmware_image_type_uboot_fit =
- EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID;
/**
* efi_firmware_fit_get_image_info - return information about the current
@@ -314,8 +312,6 @@ const struct efi_firmware_management_protocol efi_fmp_fit =
{
* This FIRMWARE_MANAGEMENT_PROTOCOL driver provides a firmware update
* method with raw data.
*/
-const efi_guid_t efi_firmware_image_type_uboot_raw =
- EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID;
/**
* efi_firmware_raw_get_image_info - return information about the current
--
2.25.1
[PATCH v5 8/8] doc: uefi: Update the capsule update related documentation
Update the capsule update functionality related documentation to
refect the additional definitions that need to be made per platform
for supporting the capsule update feature.
Signed-off-by: Sughosh Ganu
---
Changes since V4:
* Change the description of the platform data based on the changes
made in earlier patches
doc/develop/uefi/uefi.rst | 51 +--
1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index fe337c88bd..b766aecf67 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -312,8 +312,8 @@ Run the following command
.. code-block:: console
$ mkeficapsule \
- --index 1 --instance 0 \
- [--fit | --raw ] \
+ --index --instance 0 \
+ --guid \
Performing the update
@@ -333,6 +333,53 @@ won't be taken over across the reboot. If this is the
case, you can skip
this feature check with the Kconfig option (CONFIG_EFI_IGNORE_OSINDICATIONS)
set.
+A few values need to be defined in the board file for performing the
+capsule update. These values are defined in the board file by
+initialisation of a structure which provides information needed for
+capsule updates. The following structures have been defined for
+containing the image related information
+
+.. code-block:: c
+
+ struct efi_fw_images {
+ efi_guid_t image_type_id;
+ u16 *fw_name;
+ u8 image_index;
+ };
+
+ struct efi_capsule_update_info {
+ const char *dfu_string;
+ struct efi_fw_images *images;
+ };
+
+
+A string is defined which is to be used for populating the
+dfu_alt_info variable. This string is used by the function
+set_dfu_alt_info. Instead of taking the variable from the environment,
+the capsule update feature requires that the variable be set through
+the function, since that is more robust. Allowing the user to change
+the location of the firmware updates is not a very secure
+practice. Getting this information from the firmware itself is more
+secure, assuming the firmware has been verified by a previous stage
+boot loader.
+
+The firmware images structure defines the GUID values, image index
+values and the name of the images that are to be updated through
+the capsule update feature. These values are to be defined as part of
+an array. These GUID values would be used by the Firmware Management
+Protocol(FMP) to populate the image descriptor array and also
+displayed as part of the ESRT table. The image index values defined in
+the array should be one greater than the dfu alt number that
+corresponds to the firmware image. So, if the dfu alt number for an
+image is 2, the value of image index in the fw_images array for that
+image should be 3. The dfu alt number can be obtained by running the
+following command::
+
+dfu list
+
+When using the FMP for FIT images, the image index value needs to be
+set to 1.
+
Finally, the capsule update can be initiated by rebooting the board.
Enabling Capsule Authentication
--
2.25.1
[PATCH v5 7/8] mkeficapsule: Remove raw and FIT GUID types
While building a capsule, the GUID value of that specific image is to
be passed through the --guid command option to the mkeficapsule
tool. This renders the EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID and
EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID values superfluous. Remove the
--raw and --fit command line options as well.
Signed-off-by: Sughosh Ganu
Acked-by: Ilias Apalodimas
---
Changes since V4: None
tools/eficapsule.h | 8
tools/mkeficapsule.c | 26 +-
2 files changed, 1 insertion(+), 33 deletions(-)
diff --git a/tools/eficapsule.h b/tools/eficapsule.h
index 69c9c58c2f..d63b831443 100644
--- a/tools/eficapsule.h
+++ b/tools/eficapsule.h
@@ -37,14 +37,6 @@ typedef struct {
EFI_GUID(0x6dcbd5ed, 0xe82d, 0x4c44, 0xbd, 0xa1, \
0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a)
-#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID \
- EFI_GUID(0xae13ff2d, 0x9ad4, 0x4e25, 0x9a, 0xc8, \
-0x6d, 0x80, 0xb3, 0xb2, 0x21, 0x47)
-
-#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID \
- EFI_GUID(0xe2bb9c06, 0x70e9, 0x4b14, 0x97, 0xa3, \
-0x5a, 0x79, 0x13, 0x17, 0x6e, 0x3f)
-
#define EFI_CERT_TYPE_PKCS7_GUID \
EFI_GUID(0x4aafd29d, 0x68df, 0x49ee, 0x8a, 0xa9, \
0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7)
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index c118335b93..5f74d23b9e 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -27,17 +27,11 @@
static const char *tool_name = "mkeficapsule";
efi_guid_t efi_guid_fm_capsule = EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
-efi_guid_t efi_guid_image_type_uboot_fit =
- EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID;
-efi_guid_t efi_guid_image_type_uboot_raw =
- EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID;
efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID;
-static const char *opts_short = "frg:i:I:v:p:c:m:dh";
+static const char *opts_short = "g:i:I:v:p:c:m:dh";
static struct option options[] = {
- {"fit", no_argument, NULL, 'f'},
- {"raw", no_argument, NULL, 'r'},
{"guid", required_argument, NULL, 'g'},
{"index", required_argument, NULL, 'i'},
{"instance", required_argument, NULL, 'I'},
@@ -54,8 +48,6 @@ static void print_usage(void)
fprintf(stderr, "Usage: %s [options] \n"
"Options:\n"
- "\t-f, --fit FIT image type\n"
- "\t-r, --raw raw image type\n"
"\t-g, --guid guid for image blob type\n"
"\t-i, --index update image index\n"
"\t-I, --instanceupdate hardware instance\n"
@@ -606,22 +598,6 @@ int main(int argc, char **argv)
break;
switch (c) {
- case 'f':
- if (guid) {
- fprintf(stderr,
- "Image type already specified\n");
- exit(EXIT_FAILURE);
- }
- guid = _guid_image_type_uboot_fit;
- break;
- case 'r':
- if (guid) {
- fprintf(stderr,
- "Image type already specified\n");
- exit(EXIT_FAILURE);
- }
- guid = _guid_image_type_uboot_raw;
- break;
case 'g':
if (guid) {
fprintf(stderr,
--
2.25.1
[PATCH v5 5/8] test: capsule: Modify the capsule tests to use GUID values for sandbox
The current UEFI capsule updation code uses two GUID values, one for
FIT images, and one for raw images across platforms. This logic is
being changed to have GUID values per image, per platform. Change the
tests for the capsule update code to reflect this change. The GUID
values now used are the ones specific to the sandbox platform -- one
for the u-boot image, and another for the u-boot environment image.
The UEFI specification does not allow installation of multiple
Firmware Management Protocols(FMP) at the same time. Install the
FMP instance for raw images on the sandbox variant for testing the
capsule update code. Install the FMP instance for the FIT images on
the sandbox64 and sandbox_flattree variant for testing capsule update
for FIT images. This is being done by splitting the capsule update
script for FIT and raw images.
Signed-off-by: Sughosh Ganu
---
Changes since V4: None
configs/sandbox64_defconfig | 1 -
configs/sandbox_defconfig | 1 -
configs/sandbox_flattree_defconfig| 5 +
test/py/tests/test_efi_capsule/conftest.py| 21 +-
.../test_capsule_firmware_fit.py | 186 ++
...rmware.py => test_capsule_firmware_raw.py} | 159 +--
6 files changed, 258 insertions(+), 115 deletions(-)
create mode 100644 test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
rename test/py/tests/test_efi_capsule/{test_capsule_firmware.py =>
test_capsule_firmware_raw.py} (75%)
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 7c157a23d0..1a0142795a 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -247,7 +247,6 @@ CONFIG_ERRNO_STR=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
-CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_EFI_SECURE_BOOT=y
CONFIG_TEST_FDTDEC=y
CONFIG_UNIT_TEST=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index ab0e2defee..de2526df09 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -318,7 +318,6 @@ CONFIG_LZ4=y
CONFIG_ERRNO_STR=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
-CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_EFI_SECURE_BOOT=y
CONFIG_TEST_FDTDEC=y
diff --git a/configs/sandbox_flattree_defconfig
b/configs/sandbox_flattree_defconfig
index 217b0647bb..bbcf435ac6 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -29,6 +29,7 @@ CONFIG_CMD_BOOTEFI_HELLO=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_NVEDIT_INFO=y
CONFIG_CMD_NVEDIT_LOAD=y
CONFIG_CMD_NVEDIT_SELECT=y
@@ -210,3 +211,7 @@ CONFIG_HEXDUMP=y
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_DFU_SF=y
diff --git a/test/py/tests/test_efi_capsule/conftest.py
b/test/py/tests/test_efi_capsule/conftest.py
index 9076087a12..d757415c88 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -72,7 +72,7 @@ def efi_capsule_data(request, u_boot_config):
# Create capsule files
# two regions: one for u-boot.bin and the other for u-boot.env
-check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n
u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old -> u-boot.env.old; echo -n
u-boot-env:New > u-boot.env.new' % data_dir,
+check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n
u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old > u-boot.env.old; echo -n
u-boot-env:New > u-boot.env.new' % data_dir,
shell=True)
check_call('sed -e \"s?BINFILE1?u-boot.bin.new?\" -e
\"s?BINFILE2?u-boot.env.new?\"
%s/test/py/tests/test_efi_capsule/uboot_bin_env.its > %s/uboot_bin_env.its' %
(u_boot_config.source_dir, data_dir),
@@ -80,21 +80,29 @@ def efi_capsule_data(request, u_boot_config):
check_call('cd %s; %s/tools/mkimage -f uboot_bin_env.its
uboot_bin_env.itb' %
(data_dir, u_boot_config.build_dir),
shell=True)
-check_call('cd %s; %s/tools/mkeficapsule --index 1 --fit
uboot_bin_env.itb Test01' %
+check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid
09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test01' %
(data_dir, u_boot_config.build_dir),
shell=True)
-check_call('cd %s; %s/tools/mkeficapsule --index 1 --raw
u-boot.bin.new Test02' %
+check_call('cd %s; %s/tools/mkeficapsule --index 2 --guid
5A7021F5-FEF2-48B4-AABA-832E777418C0 u-boot.env.new Test02' %
(data_dir, u_boot_config.build_dir),
shell=True)
-check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid
E2BB9C06-70E9-4B14-97A3-5A7913176E3F
[PATCH v5 3/8] capsule: Put a check for image index before the update
The current capsule update code compares the image GUID value in the
capsule header with the image GUID value obtained from the
GetImageInfo function of the Firmware Management Protocol(FMP). This
comparison is done to ascertain if the FMP's SetImage function can be
called for the update. Make this checking more robust by comparing the
image_index value passed through the capsule with that returned by the
FMP's GetImageInfo function. This protects against the scenario of the
firmware being updated in a wrong partition/location on the storage
device if an incorrect value has been passed through the capsule,
since the image_index is used to determine the location of the update
on the storage device.
Signed-off-by: Sughosh Ganu
Reviewed-by: Masami Hiramatsu
Reviewed-by: Ilias Apalodimas
---
Changes since V4: None
lib/efi_loader/efi_capsule.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index f00440163d..f03f4c9044 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -128,6 +128,7 @@ void set_capsule_result(int index, struct
efi_capsule_header *capsule,
/**
* efi_fmp_find - search for Firmware Management Protocol drivers
* @image_type:Image type guid
+ * @image_index: Image Index
* @instance: Instance number
* @handles: Handles of FMP drivers
* @no_handles:Number of handles
@@ -141,8 +142,8 @@ void set_capsule_result(int index, struct
efi_capsule_header *capsule,
* * NULL - on failure
*/
static struct efi_firmware_management_protocol *
-efi_fmp_find(efi_guid_t *image_type, u64 instance, efi_handle_t *handles,
-efi_uintn_t no_handles)
+efi_fmp_find(efi_guid_t *image_type, u8 image_index, u64 instance,
+efi_handle_t *handles, efi_uintn_t no_handles)
{
efi_handle_t *handle;
struct efi_firmware_management_protocol *fmp;
@@ -203,6 +204,7 @@ efi_fmp_find(efi_guid_t *image_type, u64 instance,
efi_handle_t *handles,
log_debug("+++ desc[%d] index: %d, name: %ls\n",
j, desc->image_index, desc->image_id_name);
if (!guidcmp(>image_type_id, image_type) &&
+ (desc->image_index == image_index) &&
(!instance ||
!desc->hardware_instance ||
desc->hardware_instance == instance))
@@ -449,8 +451,8 @@ static efi_status_t efi_capsule_update_firmware(
}
/* find a device for update firmware */
- /* TODO: should we pass index as well, or nothing but type? */
fmp = efi_fmp_find(>update_image_type_id,
+ image->update_image_index,
image->update_hardware_instance,
handles, no_handles);
if (!fmp) {
--
2.25.1
[PATCH v5 4/8] efi: Define set_dfu_alt_info() for boards with UEFI capsule update enabled
Currently, there are a bunch of boards which enable the UEFI capsule
update feature. The actual update of the firmware images is done
through the dfu framework which uses the dfu_alt_info environment
variable for getting information on the update, like device, partition
number/address etc. The dfu framework allows the variable to be set
through the set_dfu_alt_info function defined by the platform, or if
the function is not defined, it gets the variable from the
environment. Using the value set in the environment is not very
robust, since the variable can be modified from the u-boot command
line and this can cause an incorrect update.
To prevent this from happening, define the set_dfu_alt_info function
when the capsule update feature is enabled. A weak function is defined
which sets the dfu_alt_info environment variable by getting the string
for the variable from the platform.
Signed-off-by: Sughosh Ganu
---
Changes since V4:
* Define a weak function set_dfu_alt_info for setting the variable in
a non board specific file as suggested by Ilias
* Drop the definitions of set_dfu_alt_info that were being added in
the board files
lib/efi_loader/Kconfig| 2 ++
lib/efi_loader/efi_firmware.c | 23 +++
2 files changed, 25 insertions(+)
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index e5e35fe51f..09fb8cbe75 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -174,6 +174,7 @@ config EFI_CAPSULE_FIRMWARE_FIT
depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT
select UPDATE_FIT
select DFU
+ select SET_DFU_ALT_INFO
select EFI_CAPSULE_FIRMWARE
help
Select this option if you want to enable firmware management protocol
@@ -185,6 +186,7 @@ config EFI_CAPSULE_FIRMWARE_RAW
depends on SANDBOX || (!SANDBOX && !EFI_CAPSULE_FIRMWARE_FIT)
select DFU_WRITE_ALT
select DFU
+ select SET_DFU_ALT_INFO
select EFI_CAPSULE_FIRMWARE
help
Select this option if you want to enable firmware management protocol
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index e9fc4b9c1e..cbfa57f64f 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -11,9 +11,11 @@
#include
#include
#include
+#include
#include
#include
+#include
#define FMP_PAYLOAD_HDR_SIGNATURE SIGNATURE_32('M', 'S', 'S', '1')
@@ -35,6 +37,27 @@ struct fmp_payload_header {
u32 lowest_supported_version;
};
+#define DFU_ALT_BUF_LENSZ_1K
+
+__weak void set_dfu_alt_info(char *interface, char *devstr)
+{
+ int n;
+ const char *dfu_alt_info;
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+
+ if (!CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) &&
+ env_get("dfu_alt_info"))
+ return;
+
+ dfu_alt_info = update_info.dfu_string;
+ n = strlen(dfu_alt_info);
+ memset(buf, 0, n + 1);
+
+ strncpy(buf, dfu_alt_info, n);
+
+ env_set("dfu_alt_info", buf);
+}
+
/* Place holder; not supported */
static
efi_status_t EFIAPI efi_firmware_get_image_unsupported(
--
2.25.1
[PATCH v5 2/8] capsule: FMP: Populate the image descriptor array from platform data
Currently, the image descriptor array that has been passed to the
GetImageInfo function of the Firmware Management Protocol(FMP) gets
populated through the data stored with the dfu framework. The
dfu data is not restricted to contain information only of the images
updatable through the capsule update mechanism, but it also contains
information on other images. The image descriptor array is also parsed
by the ESRT generation code, and thus the ESRT table contains entries
for other images that are not being handled by the FMP for the capsule
updates. Fix this by populating the image descriptor array from the
structure initialised in the board file.
The other issue fixed is assignment of a separate GUID for all images
in the image descriptor array. The UEFI specification mandates that
all entries in the ESRT table should have a unique GUID value as part
of the FwClass member of the EFI_SYSTEM_RESOURCE_ENTRY. Currently, all
images are assigned a single GUID value, either an FIT GUID or a raw
image GUID. This is fixed by obtaining the GUID values from the
efi_fw_images array defined per platform.
Signed-off-by: Sughosh Ganu
---
Changes since V4:
* Drop the image_count variable as was suggested by Ilias
* Drop another unused variable names_len
lib/efi_loader/efi_firmware.c | 95 +++
1 file changed, 28 insertions(+), 67 deletions(-)
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index a5ff32f121..e9fc4b9c1e 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -97,91 +97,58 @@ efi_status_t EFIAPI
efi_firmware_set_package_info_unsupported(
}
/**
- * efi_get_dfu_info - return information about the current firmware image
+ * efi_fill_image_desc_array - populate image descriptor array
* @this: Protocol instance
* @image_info_size: Size of @image_info
* @image_info:Image information
* @descriptor_version:Pointer to version number
- * @descriptor_count: Pointer to number of descriptors
+ * @descriptor_count: Image count
* @descriptor_size: Pointer to descriptor size
- * package_version:Package version
- * package_version_name: Package version's name
- * image_type: Image type GUID
+ * @package_version: Package version
+ * @package_version_name: Package version's name
*
* Return information bout the current firmware image in @image_info.
* @image_info will consist of a number of descriptors.
- * Each descriptor will be created based on "dfu_alt_info" variable.
+ * Each descriptor will be created based on "efi_fw_images" variable.
*
* Return status code
*/
-static efi_status_t efi_get_dfu_info(
+static efi_status_t efi_fill_image_desc_array(
efi_uintn_t *image_info_size,
struct efi_firmware_image_descriptor *image_info,
u32 *descriptor_version,
u8 *descriptor_count,
efi_uintn_t *descriptor_size,
u32 *package_version,
- u16 **package_version_name,
- const efi_guid_t *image_type)
+ u16 **package_version_name)
{
- struct dfu_entity *dfu;
- size_t names_len, total_size;
- int dfu_num, i;
- u16 *name, *next;
- int ret;
-
- ret = dfu_init_env_entities(NULL, NULL);
- if (ret)
- return EFI_SUCCESS;
-
- names_len = 0;
- dfu_num = 0;
- list_for_each_entry(dfu, _list, list) {
- names_len += (utf8_utf16_strlen(dfu->name) + 1) * 2;
- dfu_num++;
- }
- if (!dfu_num) {
- log_warning("No entities in dfu_alt_info\n");
- *image_info_size = 0;
- dfu_free_entities();
+ size_t total_size;
+ struct efi_fw_images *fw_array;
+ int i;
- return EFI_SUCCESS;
- }
+ fw_array = update_info.images;
+ *descriptor_count = num_image_type_guids;
+
+ total_size = sizeof(*image_info) * num_image_type_guids;
- total_size = sizeof(*image_info) * dfu_num + names_len;
- /*
-* we will assume that sizeof(*image_info) * dfu_name
-* is, at least, a multiple of 2. So the start address for
-* image_id_name would be aligned with 2 bytes.
-*/
if (*image_info_size < total_size) {
*image_info_size = total_size;
- dfu_free_entities();
return EFI_BUFFER_TOO_SMALL;
}
*image_info_size = total_size;
*descriptor_version = EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION;
- *descriptor_count = dfu_num;
*descriptor_size = sizeof(*image_info);
*package_version = 0x; /* not supported */
*package_version_name = NULL; /* not supported */
- /* DFU alt number should correspond to image_index */
- i = 0;
- /* Name area starts just after descriptors */
-
[PATCH v5 1/8] capsule: board: Add information needed for capsule updates
Add a structure which defines the information that is needed for
executing capsule updates on a platform. Some information in the
structure is used for making the update process more robust while some
information is used for fixing some issues. Initialise this structure
in the board file, and use the information for the capsule updates.
Signed-off-by: Sughosh Ganu
---
Changes since V1:
* Define a structure efi_capsule_update_info which includes the string
for populating dfu_alt_info
* Initialise the string for dfu_alt_info in the board file
.../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 25 +
.../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 24 +
board/emulation/qemu-arm/qemu-arm.c | 24 +
board/kontron/pitx_imx8m/pitx_imx8m.c | 21 ++-
board/kontron/sl-mx8mm/sl-mx8mm.c | 20 +++
board/kontron/sl28/sl28.c | 21 +++
board/sandbox/sandbox.c | 34 ++
board/socionext/developerbox/developerbox.c | 33 +
board/xilinx/common/board.c | 28 +++
include/configs/imx8mm-cl-iot-gate.h | 10 ++
include/configs/imx8mp_rsb3720.h | 10 ++
include/configs/kontron-sl-mx8mm.h| 6
include/configs/kontron_pitx_imx8m.h | 6
include/configs/kontron_sl28.h| 6
include/configs/qemu-arm.h| 10 ++
include/configs/sandbox.h | 14
include/configs/synquacer.h | 14
include/configs/xilinx_versal.h | 6
include/configs/xilinx_zynqmp.h | 10 ++
include/configs/zynq-common.h | 10 ++
include/efi_loader.h | 36 +++
21 files changed, 367 insertions(+), 1 deletion(-)
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index 16566092bd..aa9cfa8339 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -6,6 +6,8 @@
#include
#include
+#include
+#include
#include
#include
#include
@@ -21,6 +23,7 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -44,6 +47,28 @@ static void setup_gpmi_nand(void)
}
#endif
+#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
+struct efi_fw_images fw_images[] = {
+ {
+#if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)
+ .image_type_id = IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID,
+#elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
+ .image_type_id = IMX8MP_RSB3720A1_6G_FIT_IMAGE_GUID,
+#endif
+ .fw_name = u"IMX8MP-RSB3720-FIT",
+ .image_index = 1,
+ },
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "mmc 2=flash-bin raw 0 0x1B00 mmcpart 1",
+ .images = fw_images,
+};
+
+u8 num_image_type_guids = ARRAY_SIZE(fw_images);
+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
+
+
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
index 7e2d88f449..f2f5eb10f1 100644
--- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
+++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
@@ -5,6 +5,8 @@
*/
#include
+#include
+#include
#include
#include
#include
@@ -21,11 +23,33 @@
#include
#include
#include
+#include
#include "ddr/ddr.h"
DECLARE_GLOBAL_DATA_PTR;
+#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
+struct efi_fw_images fw_images[] = {
+ {
+#if defined(CONFIG_TARGET_IMX8MM_CL_IOT_GATE)
+ .image_type_id = IMX8MM_CL_IOT_GATE_FIT_IMAGE_GUID,
+#elif defined(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE)
+ .image_type_id = IMX8MM_CL_IOT_GATE_OPTEE_FIT_IMAGE_GUID,
+#endif
+ .fw_name = u"IMX8MM-CL-IOT-GATE-FIT",
+ .image_index = 1,
+ },
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "mmc 2=flash-bin raw 0x42 0x1D00 mmcpart 1",
+ .images = fw_images,
+};
+
+u8 num_image_type_guids = ARRAY_SIZE(fw_images);
+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
+
int board_phys_sdram_size(phys_size_t *size)
{
struct lpddr4_tcm_desc *lpddr4_tcm_desc =
diff --git a/board/emulation/qemu-arm/qemu-arm.c
b/board/emulation/qemu-arm/qemu-arm.c
index 16d5a97167..f36709ea27 100644
--- a/board/emulation/qemu-arm/qemu-arm.c
+++ b/board/emulation/qemu-arm/qemu-arm.c
@@ -6,15 +6,39 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
#include
#include
+#include
+
#ifdef CONFIG_ARM64
#include
+#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
+struct efi_fw_images fw_images[] =
[PATCH v5 0/8] efi: capsule: Capsule Update fixes and enhancements
This series is cleaning up the usage of the image GUIDs that are used in capsule update and the EFI System Resource Table(ESRT). There are some other enhancements being made to the capsule update code to make it more robust. Firstly, an overview of the fixes being made. Currently, there are two instances of the Firmware Management Protocol(FMP), one defined for updating the FIT images, and the other for updating raw images. The FMP code defines two GUID values, one for all FIT images, and one for raw images. Depending on the FMP instance used on a platform, the platform needs to use the corresponding image GUID value for all images on the platform, and also across platforms. A few issues are being fixed through the patch series. One, that an image for a different platform can be flashed on another platform if both the platforms are using the same FMP instance. So, for e.g. a capsule generated for the Socionext DeveloperBox platform can be flashed on the ZynqMP platform, since both the platforms use the CONFIG_EFI_CAPSULE_FIRMWARE_RAW instance of the FMP. This can be corrected if each firmware image that can be updated through the capsule update mechanism has it's own unique image GUID. The second issue that this patch series fixes is the value of FwClass in the ESRT. With the current logic, all firmware image entries in the ESRT display the same GUID value -- either the FIT GUID or the raw GUID. This is not in compliance with the UEFI specification, as the specification requires all entries to have unique GUID values. The third issue being fixed is the population of the EFI_FIRMWARE_IMAGE_DESCRIPTOR array. The current code uses the dfu framework for populating the image descriptor array. However, there might be other images that are not to be updated through the capsule update mechanism also registered with the dfu framework. As a result of this, the ESRT will show up entries of images that are not to be targeted by the capsule update mechanism. These issues are being fixed by defining a structure, efi_fw_images. A platform can then define image related information like the image GUID and image name. Every platform that uses capsule update mechanism needs to define fw_images array. This array will then be used to populate the image descriptor array, and also in determining if a particular capsule's payload can be used for updating an image on the platform. The other part of the patches are some enhancements being made to the capsule update code to make it more robust. The first enhancement being made is to have a check for the image index being passed through the capsule header. The capsule update code uses the image index value as the dfu alt number, which points to the partition to which the update must be made. The platform is supposed to define the image index value for the updatable firmare images as part of the fw_images array. This value must correspond to the dfu alt num for the corresponding image, and can be obtained by checking the output of the 'dfu list' u-boot command. At the time of update, the image index being passed through the capsule is checked against the image index value obtained from the platform. The second enhancement made is the retrieval of the dfu_alt_info variable from the set_dfu_alt_info function instead of using the value defined in the environment. The dfu framework checks for the existence of this function, and if the function is not defined, gets the value from the environment. This can cause in an incorrect update if the environment variable value is incorrect. A weak function is defined for populating dfu_alt_info from the information obtained from the platform. This function gets invoked on all platforms which enabled capsule update feature. The first patch adds the structure efi_capsule_update_info and initialises the structure on all platforms which enable capsule update feature The second patch populates the image descriptor array in the GetImageInfo function with the values from the fw_images array defined in the board file The third patch adds a check for the image index value from the capsule header against the value obtained from the fw_images array for the corresponding image The fourth patch defines a weak function set_dfu_alt_info which is used to populate dfu_alt_info to be used for capsule updates. The fifth patch splits the capsule update test script into two, one for FMP for raw images, and one for FMP for FIT images. The test for FIT images is being enabled on the sandbox_flattree variant. The sixth patch removes the now unused FIT and raw image GUID values from the FMP module. The seventh patch removes the --raw and --fit command line parameters in the mkeficapsule utility. The eighth patch makes corresponding changes in the capsule update related documentation. Changes since V4: - * Define a structure efi_capsule_update_info which includes the string for populating dfu_alt_info * Initialise the string for
Re: [PATCH 4/6] net: fec: add support for DM_MDIO
On Fri, Apr 01, 2022 at 10:53:14AM -0700, Tim Harvey wrote: > Can you review 'net: add MV88E61xx DSA driver' for me? I will. I've been thinking all day today about what to say that isn't stupid. Give me some time and I'll provide feedback.
Re: [PATCH 1/2] net: phy: dp83867: avoid error in dp83867_of_init() when PHY has no OF node
On Thu, Mar 3, 2022 at 9:52 AM Ramon Fried wrote:
>
> On Wed, Feb 23, 2022 at 3:21 PM Vladimir Oltean
> wrote:
> >
> > A DM_ETH driver may use phy_connect() towards a PHY address on an MDIO
> > bus which is not specified in the device tree, as evidenced by:
> >
> > pfe_eth_probe
> > -> pfe_phy_configure
> >-> phy_connect
> >
> > When this happens, the PHY will have an invalid OF node.
> >
> > The dp83867_config() method has extra initialization steps which are
> > bypassed when the PHY lacks an OF node, which is undesirable because it
> > will lead to broken networking. Allow the rest of the code to run.
> >
> > Fixes: 085445ca4104 ("net: phy: ti: Allow the driver to be more
> > configurable")
> > Signed-off-by: Vladimir Oltean
> > ---
> > drivers/net/phy/dp83867.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
> > index eada4541c9c3..49978d0f25f3 100644
> > --- a/drivers/net/phy/dp83867.c
> > +++ b/drivers/net/phy/dp83867.c
> > @@ -158,7 +158,7 @@ static int dp83867_of_init(struct phy_device *phydev)
> >
> > node = phy_get_ofnode(phydev);
> > if (!ofnode_valid(node))
> > - return -EINVAL;
> > + return 0;
> >
> > /* Optional configuration */
> > ret = ofnode_read_u32(node, "ti,clk-output-sel",
> > --
> > 2.25.1
> >
> Reviewed-by: Ramon Fried
Applied to u-boot-net/next
Thanks,
Ramon
Re: [PATCH 2/2] net: phy: atheros: avoid error in ar803x_of_init() when PHY has no OF node
On Thu, Mar 3, 2022 at 9:53 AM Ramon Fried wrote:
>
> On Wed, Feb 23, 2022 at 3:21 PM Vladimir Oltean
> wrote:
> >
> > A DM_ETH driver may use phy_connect() towards a PHY address on an MDIO
> > bus which is not specified in the device tree, as evidenced by:
> >
> > pfe_eth_probe
> > -> pfe_phy_configure
> >-> phy_connect
> >
> > When this happens, the PHY will have an invalid OF node.
> >
> > When ar803x_config() runs, it silently fails at ar803x_of_init(), and
> > therefore, fails to run the rest of the initialization.
> >
> > This makes MII_BMCR contain what it had after BMCR_RESET (0x8000) has
> > been written into it by phy_reset(). Since BMCR_RESET is volatile and
> > self-clearing, the MII_BMCR ends up having a value of 0x0. The further
> > configuration of this register, which is supposed to be handled by
> > genphy_config_aneg() lower in ar803x_config(), never gets a chance to
> > run due to this early error from ar803x_of_init().
> >
> > As a result of having MII_BMCR as 0, the following symptom appears:
> >
> > => setenv ethact pfe_eth0
> > => setenv ipaddr 10.0.0.1
> > => ping 10.0.0.2
> > pfe_eth0 Waiting for PHY auto negotiation to complete. TIMEOUT !
> > Could not initialize PHY pfe_eth0
> >
> > Manually writing 0x1140 into register 0 of the PHY makes the connection
> > work, but it is rather desirable that the port works without any manual
> > intervention.
> >
> > Fixes: fe6293a80959 ("phy: atheros: add device tree bindings and config")
> > Signed-off-by: Vladimir Oltean
> > ---
> > drivers/net/phy/atheros.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
> > index f922fecd6b5d..fa1fe08518f4 100644
> > --- a/drivers/net/phy/atheros.c
> > +++ b/drivers/net/phy/atheros.c
> > @@ -199,7 +199,7 @@ static int ar803x_of_init(struct phy_device *phydev)
> >
> > node = phy_get_ofnode(phydev);
> > if (!ofnode_valid(node))
> > - return -EINVAL;
> > + return 0;
> >
> > priv = malloc(sizeof(*priv));
> > if (!priv)
> > --
> > 2.25.1
> >
> Reviewed-by: Ramon Fried
Applied to u-boot-net/next
Thanks,
Ramon
[RFC PATCH 7/7] spl: Convert spi to spl_load
This converts the spi load method to use spl_load. As a consequence, it
also adds support for LOAD_FIT_FULL.
Signed-off-by: Sean Anderson
---
common/spl/spl_spi.c | 48 +++-
1 file changed, 7 insertions(+), 41 deletions(-)
diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index cf3f7ef4c0..037db1a19f 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c
@@ -83,6 +83,10 @@ static int spl_spi_load_image(struct spl_image_info
*spl_image,
unsigned int payload_offs;
struct spi_flash *flash;
struct image_header *header;
+ struct spl_load_info load = {
+ .bl_len = 1,
+ .read = spl_spi_fit_read,
+ };
/*
* Load U-Boot image from SPI flash into RAM
@@ -99,6 +103,7 @@ static int spl_spi_load_image(struct spl_image_info
*spl_image,
return -ENODEV;
}
+ load.dev = flash;
payload_offs = spl_spi_get_uboot_offs(flash);
header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
@@ -121,47 +126,8 @@ static int spl_spi_load_image(struct spl_image_info
*spl_image,
return err;
}
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) &&
- image_get_magic(header) == FDT_MAGIC) {
- err = spi_flash_read(flash, payload_offs,
-roundup(fdt_totalsize(header), 4),
-(void *)CONFIG_SYS_LOAD_ADDR);
- if (err)
- return err;
- err = spl_parse_image_header(spl_image, bootdev,
- (struct image_header
*)CONFIG_SYS_LOAD_ADDR);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.dev = flash;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = 1;
- load.read = spl_spi_fit_read;
- err = spl_load_simple_fit(spl_image, ,
- payload_offs,
- header);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
- struct spl_load_info load;
-
- load.dev = flash;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = 1;
- load.read = spl_spi_fit_read;
-
- err = spl_load_imx_container(spl_image, ,
-payload_offs);
- } else {
- err = spl_parse_image_header(spl_image, bootdev,
header);
- if (err)
- return err;
- err = spi_flash_read(flash, payload_offs +
spl_image->offset,
-spl_image->size,
-(void *)spl_image->load_addr);
- }
+ err = spl_load(spl_image, bootdev, , header, 0,
+ payload_offs);
}
return err;
--
2.35.1.1320.gc452695387.dirty
[RFC PATCH 5/7] spl: Convert net to spl_load
This converts the net load method to use spl_load. As a result, it also
adds support for LOAD_FIT_FULL and IMX images.
Signed-off-by: Sean Anderson
---
common/spl/spl_net.c | 24 +---
1 file changed, 5 insertions(+), 19 deletions(-)
diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c
index a853e6aead..3b4374add6 100644
--- a/common/spl/spl_net.c
+++ b/common/spl/spl_net.c
@@ -29,6 +29,10 @@ static int spl_net_load_image(struct spl_image_info
*spl_image,
struct spl_boot_device *bootdev)
{
struct image_header *header = (struct image_header *)image_load_addr;
+ struct spl_load_info load = {
+ .bl_len = 1,
+ .read = spl_net_load_read,
+ };
int rv;
env_init();
@@ -47,25 +51,7 @@ static int spl_net_load_image(struct spl_image_info
*spl_image,
return rv;
}
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.bl_len = 1;
- load.read = spl_net_load_read;
- rv = spl_load_simple_fit(spl_image, , 0, header);
- } else {
- debug("Legacy image\n");
-
- rv = spl_parse_image_header(spl_image, bootdev, header);
- if (rv)
- return rv;
-
- memcpy((void *)spl_image->load_addr, header, spl_image->size);
- }
-
- return rv;
+ return spl_load(spl_image, bootdev, , header, 0, 0);
}
#endif
--
2.35.1.1320.gc452695387.dirty
[RFC PATCH 6/7] spl: Convert nor to spl_load
This converts the nor load method to use spl_load. As a result it also
adds support LOAD_FIT_FULL.
Signed-off-by: Sean Anderson
---
common/spl/spl_nor.c | 35 ++-
1 file changed, 6 insertions(+), 29 deletions(-)
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index 0f4fff8493..90ece77af1 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -26,8 +26,11 @@ unsigned long __weak spl_nor_get_uboot_base(void)
static int spl_nor_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
- __maybe_unused const struct image_header *header;
- __maybe_unused struct spl_load_info load;
+ struct image_header *header = (void *)spl_nor_get_uboot_base();
+ struct spl_load_info load = {
+ .bl_len = 1,
+ .read = spl_nor_load_read,
+ };
/*
* Loading of the payload to SDRAM is done with skipping of
@@ -91,32 +94,6 @@ static int spl_nor_load_image(struct spl_image_info
*spl_image,
* Load real U-Boot from its location in NOR flash to its
* defined location in SDRAM
*/
-#ifdef CONFIG_SPL_LOAD_FIT
- header = (const struct image_header *)spl_nor_get_uboot_base();
- if (image_get_magic(header) == FDT_MAGIC) {
- debug("Found FIT format U-Boot\n");
- load.bl_len = 1;
- load.read = spl_nor_load_read;
- return spl_load_simple_fit(spl_image, ,
- spl_nor_get_uboot_base(),
- (void *)header);
- }
-#endif
- if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
- load.bl_len = 1;
- load.read = spl_nor_load_read;
- return spl_load_imx_container(spl_image, ,
- spl_nor_get_uboot_base());
- }
-
- /* Legacy image handling */
- if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_SUPPORT)) {
- load.bl_len = 1;
- load.read = spl_nor_load_read;
- return spl_load_legacy_img(spl_image, bootdev, ,
- spl_nor_get_uboot_base());
- }
-
- return 0;
+ return spl_load(spl_image, bootdev, , header, 0, 0);
}
SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image);
--
2.35.1.1320.gc452695387.dirty
[RFC PATCH 4/7] spl: Convert mmc to spl_load
This converts the mmc loader to spl_load. Legacy images are handled by
spl_load (via spl_parse_image_header), so mmc_load_legacy can be
omitted.
Signed-off-by: Sean Anderson
---
common/spl/spl_mmc.c | 73
1 file changed, 6 insertions(+), 67 deletions(-)
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 1c41d24ff4..113566166f 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -17,48 +17,6 @@
#include
#include
-static int mmc_load_legacy(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev,
- struct mmc *mmc,
- ulong sector, struct image_header *header)
-{
- u32 image_offset_sectors;
- u32 image_size_sectors;
- unsigned long count;
- u32 image_offset;
- int ret;
-
- ret = spl_parse_image_header(spl_image, bootdev, header);
- if (ret)
- return ret;
-
- /* convert offset to sectors - round down */
- image_offset_sectors = spl_image->offset / mmc->read_bl_len;
- /* calculate remaining offset */
- image_offset = spl_image->offset % mmc->read_bl_len;
-
- /* convert size to sectors - round up */
- image_size_sectors = (spl_image->size + mmc->read_bl_len - 1) /
-mmc->read_bl_len;
-
- /* Read the header too to avoid extra memcpy */
- count = blk_dread(mmc_get_blk_desc(mmc),
- sector + image_offset_sectors,
- image_size_sectors,
- (void *)(ulong)spl_image->load_addr);
- debug("read %x sectors to %lx\n", image_size_sectors,
- spl_image->load_addr);
- if (count != image_size_sectors)
- return -EIO;
-
- if (image_offset)
- memmove((void *)(ulong)spl_image->load_addr,
- (void *)(ulong)spl_image->load_addr + image_offset,
- spl_image->size);
-
- return 0;
-}
-
static ulong h_spl_load_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
{
@@ -86,6 +44,11 @@ int mmc_load_image_raw_sector(struct spl_image_info
*spl_image,
struct image_header *header;
struct blk_desc *bd = mmc_get_blk_desc(mmc);
int ret = 0;
+ struct spl_load_info load = {
+ .dev = mmc,
+ .bl_len = mmc->read_bl_len,
+ .read = h_spl_load_read,
+ };
header = spl_get_load_buffer(-sizeof(*header), bd->blksz);
@@ -97,31 +60,7 @@ int mmc_load_image_raw_sector(struct spl_image_info
*spl_image,
goto end;
}
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.dev = mmc;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = mmc->read_bl_len;
- load.read = h_spl_load_read;
- ret = spl_load_simple_fit(spl_image, , sector, header);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
- struct spl_load_info load;
-
- load.dev = mmc;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = mmc->read_bl_len;
- load.read = h_spl_load_read;
-
- ret = spl_load_imx_container(spl_image, , sector);
- } else {
- ret = mmc_load_legacy(spl_image, bootdev, mmc, sector, header);
- }
-
+ ret = spl_load(spl_image, bootdev, , header, 0, sector);
end:
if (ret) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
--
2.35.1.1320.gc452695387.dirty
[RFC PATCH 2/7] spl: Convert ext to use spl_load
This converts the ext load method to use spl_load. As a consequence, it
also adds support for FIT and IMX images.
Signed-off-by: Sean Anderson
---
common/spl/spl_ext.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index ebd914c492..1384842776 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -9,6 +9,18 @@
#include
#include
+static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
+ ulong size, void *buf)
+{
+ int ret;
+ loff_t actlen;
+
+ ret = ext4fs_read(buf, file_offset, size, );
+ if (ret)
+ return ret;
+ return actlen;
+}
+
int spl_load_image_ext(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev,
struct blk_desc *block_dev, int partition,
@@ -18,6 +30,10 @@ int spl_load_image_ext(struct spl_image_info *spl_image,
struct image_header *header;
loff_t filelen, actlen;
struct disk_partition part_info = {};
+ struct spl_load_info load = {
+ .read = spl_fit_read,
+ .bl_len = 1,
+ };
header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
@@ -47,13 +63,7 @@ int spl_load_image_ext(struct spl_image_info *spl_image,
goto end;
}
- err = spl_parse_image_header(spl_image, bootdev, header);
- if (err < 0) {
- puts("spl: ext: failed to parse image header\n");
- goto end;
- }
-
- err = ext4fs_read((char *)spl_image->load_addr, 0, filelen, );
+ err = spl_load(spl_image, bootdev, , header, filelen, 0);
end:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
--
2.35.1.1320.gc452695387.dirty
[RFC PATCH 3/7] spl: Convert fat to spl_load
This converts the fat loader to use spl_load.
Signed-off-by: Sean Anderson
---
common/spl/spl_fat.c | 36 ++--
1 file changed, 6 insertions(+), 30 deletions(-)
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 5b270541fc..c092eb3481 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -61,6 +61,11 @@ int spl_load_image_fat(struct spl_image_info *spl_image,
{
int err;
struct image_header *header;
+ struct spl_load_info load = {
+ .read = spl_fit_read,
+ .bl_len = 1,
+ .filename = filename,
+ };
err = spl_register_fat_device(block_dev, partition);
if (err)
@@ -72,36 +77,7 @@ int spl_load_image_fat(struct spl_image_info *spl_image,
if (err <= 0)
goto end;
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) &&
- image_get_magic(header) == FDT_MAGIC) {
- err = file_fat_read(filename, (void *)CONFIG_SYS_LOAD_ADDR, 0);
- if (err <= 0)
- goto end;
- err = spl_parse_image_header(spl_image, bootdev,
- (struct image_header *)CONFIG_SYS_LOAD_ADDR);
- if (err == -EAGAIN)
- return err;
- if (err == 0)
- err = 1;
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.read = spl_fit_read;
- load.bl_len = 1;
- load.filename = (void *)filename;
- load.priv = NULL;
-
- return spl_load_simple_fit(spl_image, , 0, header);
- } else {
- err = spl_parse_image_header(spl_image, bootdev, header);
- if (err)
- goto end;
-
- err = file_fat_read(filename,
- (u8 *)(uintptr_t)spl_image->load_addr, 0);
- }
+ err = spl_load(spl_image, bootdev, , header, err, 0);
end:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
--
2.35.1.1320.gc452695387.dirty
[RFC PATCH 0/7] spl: Use common function for loading/parsing images
This series adds support for loading all image types (Legacy, FIT (with and without LOAD_FIT_FULL), and i.MX) to the MMC, SPI, NOR, NET, FAT, and EXT load methods. It does this by introducing a helper function which handles the minutiae of invoking the proper parsing function, and reading the rest of the image. Hopefully, this will make it easier for load methods to support all image types that U-Boot supports, without having undocumented unsupported image types. I applied this to several loaders which were invoking spl_load_simple_fit and/or spl_parse_image_header, but I did not use it with others (e.g. DFU/RAM) which had complications in the mix. Here's some bloat-o-meter for j7200_evm_a72_defconfig with ext4 support enabled: add/remove: 1/0 grow/shrink: 2/4 up/down: 224/-232 (-8) Function old new delta spl_load - 176+176 spl_fit_read 60 104 +44 spl_load_image_ext 364 368 +4 spl_nor_load_image 120 108 -12 spl_spi_load_image 280 232 -48 spl_load_image_fat 320 264 -56 spl_mmc_load 712 596-116 Total: Before=264476, After=264468, chg -0.00% ext4 support is +48 bytes, because the original image support was so bare-bones (just legacy/raw images). For most boards with a few load methods (where one of them isn't ext4), this series should be no bloat or a net negative. However, in the worst case this series will add 150-180 bytes. I haven't tested most of this, so this series is marked RFC. I had a nand conversion in here as well, but dropped due to difficulties outlines in [1]. [1] https://lore.kernel.org/u-boot/c2ea7097-9e85-b9ec-e404-bd46eb83d...@seco.com/ Sean Anderson (7): spl: Add generic spl_load function spl: Convert ext to use spl_load spl: Convert fat to spl_load spl: Convert mmc to spl_load spl: Convert net to spl_load spl: Convert nor to spl_load spl: Convert spi to spl_load common/spl/spl.c | 61 common/spl/spl_ext.c | 24 ++- common/spl/spl_fat.c | 36 -- common/spl/spl_mmc.c | 73 common/spl/spl_net.c | 24 +++ common/spl/spl_nor.c | 35 - common/spl/spl_spi.c | 48 + include/spl.h| 30 +- 8 files changed, 137 insertions(+), 194 deletions(-) -- 2.35.1.1320.gc452695387.dirty
[RFC PATCH 1/7] spl: Add generic spl_load function
Implementers of SPL_LOAD_IMAGE_METHOD have to correctly determine what
type of image is being loaded and then call the appropriate image load
function correctly. This is tricky, because some image load functions
expect the whole image to already be loaded (CONFIG_SPL_LOAD_FIT_FULL),
some will load the image automatically using spl_load_info.read()
(CONFIG_SPL_LOAD_FIT/CONFIG_SPL_LOAD_IMX_CONTAINER), and some just parse
the header and expect the caller to do the actual loading afterwards
(legacy/raw images). Load methods often only support a subset of the
above methods, meaning that not all image types can be used with all
load methods. Further, the code to invoke these functions is
duplicated between different load functions.
To address this problem, this commit introduces a "spl_load" function.
It aims to handle image detection and correct invocation of each of the
parse/load functions. spl_simple_read is a wrapper around
spl_load_info.read with get_aligned_image* functions inlined for size
purposes. Additionally, we assume that bl_len is a power of 2 so we can
do bitshifts instead of divisions (which is smaller and faster).
Signed-off-by: Sean Anderson
---
common/spl/spl.c | 61
include/spl.h| 30 +++-
2 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index b452d4feeb..f26df7ac3f 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -398,6 +398,67 @@ int spl_parse_image_header(struct spl_image_info
*spl_image,
return 0;
}
+static int spl_simple_read(struct spl_load_info *info, void *buf, size_t size,
+ size_t offset)
+{
+ int ret;
+ size_t bl_len = info->filename ? ARCH_DMA_MINALIGN : bl_len;
+ size_t bl_mask = bl_len - 1;
+ size_t bl_shift = ffs(bl_mask);
+ size_t overhead = offset & bl_mask;
+
+ buf -= overhead;
+ size = (size + overhead + bl_mask) >> bl_shift;
+ offset = offset >> bl_shift;
+
+ ret = info->read(info, offset, size, buf);
+ return ret == size ? 0 : -EIO;
+}
+
+int spl_load(struct spl_image_info *spl_image,
+const struct spl_boot_device *bootdev, struct spl_load_info *info,
+struct image_header *header, size_t size, size_t sector)
+{
+ int ret;
+ size_t offset = sector * info->bl_len;
+
+ if (image_get_magic(header) == FDT_MAGIC) {
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) {
+ void *buf;
+
+ /*
+* In order to support verifying images in the FIT, we
+* need to load the whole FIT into memory. Try and
+* guess how much we need to load by using the total
+* size. This will fail for FITs with external data,
+* but there's not much we can do about that.
+*/
+ if (!size)
+ size = roundup(fdt_totalsize(header), 4);
+ buf = spl_get_load_buffer(0, size);
+ ret = spl_simple_read(info, buf, size, offset);
+ if (ret)
+ return ret;
+
+ return spl_parse_image_header(spl_image, bootdev, buf);
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT))
+ return spl_load_simple_fit(spl_image, info, sector,
+ header);
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER))
+ return spl_load_imx_container(spl_image, info, sector);
+
+ ret = spl_parse_image_header(spl_image, bootdev, header);
+ if (ret)
+ return ret;
+
+ return spl_simple_read(info, (void *)spl_image->load_addr,
+ spl_image->size, offset + spl_image->offset);
+}
+
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_noargs_t)(void);
diff --git a/include/spl.h b/include/spl.h
index 8ceb3c0f09..6606f4e5f6 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -236,7 +236,7 @@ struct spl_image_info {
*
* @dev: Pointer to the device, e.g. struct mmc *
* @priv: Private data for the device
- * @bl_len: Block length for reading in bytes
+ * @bl_len: Block length for reading in bytes; must be a power of 2
* @filename: Name of the fit image file.
* @read: Function to call to read from the device
*/
@@ -608,6 +608,34 @@ int spl_load_image_ext_os(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev,
struct blk_desc *block_dev, int partition);
+/**
+ * spl_load() - Parse a header and load the image
+ * @spl_image: Image data which will be filled in by this function
+ * @bootdev: The device to load from
+ *
Re: The contradictory nature of spl_nand_fit_read
On 4/1/22 2:46 PM, Sean Anderson wrote:
> Hi all,
>
> I don't understand how spl_nand_fit_read is supposed to work. This
> function has been seemingly hacked together by multiple people over the
> years, and it (presumably) (somehow) works despite mass confusion of
> units. I tried to do some refactoring, but the contradictions make it
> very difficult to determine what is a bug and what is intentional.
>
> Lets start with the basics. spl_nand_fit_read is used to implement
> spl_load_info.load. I've reproduced the documentation for this function
> below:
>
>> read() - Read from device
>>
>> @load: Information about the load state
>> @sector: Sector number to read from (each @load->bl_len bytes)
>> @count: Number of sectors to read
>> @buf: Buffer to read into
>> @return number of sectors read, 0 on error
>
> In particular, both @sector and @count are in units of load.bl_len. In
> addition, the return value should be @count on success.
>
>> static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
>> ulong size, void *dst)
>> {
>> int err;
>> #ifdef CONFIG_SYS_NAND_BLOCK_SIZE
>
> The following logic was introduced in commit 9f6a14c47f ("spl: fit:
> nand: fix fit loading in case of bad blocks"). However, at the time it
> was not guarded by the above ifdef. nand_spl_adjust_offset is not
> defined for all nand drivers. It is defined for at least mxs, am335x,
> atmel, and simple. Additionally, some drivers (such as rockchip)
> implement bad block skipping in nand_spl_load_image.
>
> It's not at all clear to me that there is common config which determines
> whether nand_spl_adjust_offset is implemented. Nevertheless, in commit
> aa0032f672 ("spl: fit: nand: allow for non-page-aligned elements"), the
> above directive selects different code if CONFIG_SYS_NAND_BLOCK_SIZE is
> defined.
>
>> ulong sector;
>>
>> sector = *(int *)load->priv;
>
> This is the offset passed to nand_spl_load_image. This
> offset is in units of bytes, and is aligned to the block size. However,
> it is *not* set if CONFIG_SPL_LOAD_IMX_CONTAINER is enabled. Oops.
>
>> offs = sector + nand_spl_adjust_offset(sector, offs - sector);
I forgot to mention this, but this also adds sector to offs, but offs already
includes the sector:
> return spl_load_simple_fit(spl_image, , offset / bl_len, header);
Which means that we add in sector twice (but with different units!)
> The documentation for this this function is as follows
>
>> nand_spl_adjust_offset - Adjust offset from a starting sector
>> @sector: Address of the sector
>> @offs: Offset starting from @sector
>>
>> If one or more bad blocks are in the address space between @sector
>> and @sector + @offs, @offs is increased by the NAND block size for
>> each bad block found.
>
> In particular, note that offs is in units of bytes. However, we know
> from above that at this point in the function, offs is in units of
> bl_len. Oops.
>
>> #else
>> offs *= load->bl_len;
>> size *= load->bl_len;
>
> This code path adjusts both offs and size to be in units of
*units of bytes
>> #endif
>> err = nand_spl_load_image(offs, size, dst);
>
> So by the time we get here, one code path is in units of bytes, and the
> other is in units of bl_len. nand_spl_load_image seems to expect bytes
> (though there is no documentation, so I can't be sure). Which of course
> begs the question: how did the code introduced in 9f6a14c47f ever work?
>
>> if (err)
>> return 0;
>>
>> return size / load->bl_len;
>
> And of course, this should only be done if size is in units of bytes.
>
>> }
>
> I have some patches for what I think are bugs, but the logic of this
> function is so confused that I am unable to determine if they actually
> are bugs. I would greatly appreciate if some of the authors of the
> mentioned commits could comment on their intent, and what they thought
> the units of offs and size were.
>
> --Sean
>
The contradictory nature of spl_nand_fit_read
Hi all,
I don't understand how spl_nand_fit_read is supposed to work. This
function has been seemingly hacked together by multiple people over the
years, and it (presumably) (somehow) works despite mass confusion of
units. I tried to do some refactoring, but the contradictions make it
very difficult to determine what is a bug and what is intentional.
Lets start with the basics. spl_nand_fit_read is used to implement
spl_load_info.load. I've reproduced the documentation for this function
below:
> read() - Read from device
>
> @load: Information about the load state
> @sector: Sector number to read from (each @load->bl_len bytes)
> @count: Number of sectors to read
> @buf: Buffer to read into
> @return number of sectors read, 0 on error
In particular, both @sector and @count are in units of load.bl_len. In
addition, the return value should be @count on success.
> static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
> ulong size, void *dst)
> {
> int err;
> #ifdef CONFIG_SYS_NAND_BLOCK_SIZE
The following logic was introduced in commit 9f6a14c47f ("spl: fit:
nand: fix fit loading in case of bad blocks"). However, at the time it
was not guarded by the above ifdef. nand_spl_adjust_offset is not
defined for all nand drivers. It is defined for at least mxs, am335x,
atmel, and simple. Additionally, some drivers (such as rockchip)
implement bad block skipping in nand_spl_load_image.
It's not at all clear to me that there is common config which determines
whether nand_spl_adjust_offset is implemented. Nevertheless, in commit
aa0032f672 ("spl: fit: nand: allow for non-page-aligned elements"), the
above directive selects different code if CONFIG_SYS_NAND_BLOCK_SIZE is
defined.
> ulong sector;
>
> sector = *(int *)load->priv;
This is the offset passed to nand_spl_load_image. This
offset is in units of bytes, and is aligned to the block size. However,
it is *not* set if CONFIG_SPL_LOAD_IMX_CONTAINER is enabled. Oops.
> offs = sector + nand_spl_adjust_offset(sector, offs - sector);
The documentation for this this function is as follows
> nand_spl_adjust_offset - Adjust offset from a starting sector
> @sector: Address of the sector
> @offs:Offset starting from @sector
>
> If one or more bad blocks are in the address space between @sector
> and @sector + @offs, @offs is increased by the NAND block size for
> each bad block found.
In particular, note that offs is in units of bytes. However, we know
from above that at this point in the function, offs is in units of
bl_len. Oops.
> #else
> offs *= load->bl_len;
> size *= load->bl_len;
This code path adjusts both offs and size to be in units of
> #endif
> err = nand_spl_load_image(offs, size, dst);
So by the time we get here, one code path is in units of bytes, and the
other is in units of bl_len. nand_spl_load_image seems to expect bytes
(though there is no documentation, so I can't be sure). Which of course
begs the question: how did the code introduced in 9f6a14c47f ever work?
> if (err)
> return 0;
>
> return size / load->bl_len;
And of course, this should only be done if size is in units of bytes.
> }
I have some patches for what I think are bugs, but the logic of this
function is so confused that I am unable to determine if they actually
are bugs. I would greatly appreciate if some of the authors of the
mentioned commits could comment on their intent, and what they thought
the units of offs and size were.
--Sean
Re: [PATCH 01/11] db-mv784mp-gp: Rename CONFIG_DB_784MP_GP to CONFIG_TARGET_DB_MV784MP_GP
On Thu, Mar 24, 2022 at 05:17:56PM -0400, Tom Rini wrote: > The value CONFIG_DB_784MP_GP is only used in the DDR code to refer to > CONFIG_TARGET_DB_MV784MP_GP so just use that second value directly. > > Cc: Stefan Roese > Signed-off-by: Tom Rini > Reviewed-by: Stefan Roese For the whole of the series, applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 01/22] Convert CONFIG_CF_DSPI to Kconfig
On Wed, Mar 23, 2022 at 05:19:48PM -0400, Tom Rini wrote: > This converts the following to Kconfig: >CONFIG_CF_DSPI > > Signed-off-by: Tom Rini For the whole of the series, applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/7] am33xx: musb: Remove unused configuration logic
On Mon, Mar 21, 2022 at 09:33:27PM -0400, Tom Rini wrote: > At this point DM and OF_CONTROL are used to configure how the USB ports > are enabled, with the exception of in SPL and no SPL_OF_CONTROL. Remove > a bunch of now unused logic to simplify the code. > > Signed-off-by: Tom Rini For the whole of the series, applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 4/6] net: fec: add support for DM_MDIO
On Thu, Mar 31, 2022 at 12:36 PM Vladimir Oltean
wrote:
>
> On Thu, Mar 31, 2022 at 10:48:55AM -0700, Tim Harvey wrote:
> > > On which branch does this apply? The context above
> > > fecmxc_read_rom_hwaddr()
> > > is different in the branches I've checked:
> > > https://source.denx.de/u-boot/u-boot/-/blob/master/drivers/net/fec_mxc.c#L1276
> > > https://source.denx.de/u-boot/custodians/u-boot-net/-/blob/next/drivers/net/fec_mxc.c#L1276
> > >
> >
> > Sorry, I should have specified in my cover letter that this is on top
> > of next which removes the non dm-eth support from the driver which is
> > quite the cleanup.
>
> Ok, but now the next patch fails to apply to the 'next' branch:
I based on top of origin/next, specifically:
34d2b7f20369 (origin/next) Merge tag 'v2022.04-rc5' into next
>
> Applying: net: dsa: move cpu port probe to dsa_post_probe
> Applying: net: mdio-uclass: add wrappers for read/write/reset operations
> Applying: net: fec: add support for DM_MDIO
> Applying: net: add MV88E61xx DSA driver
> error: patch failed: drivers/net/Kconfig:428
> error: drivers/net/Kconfig: patch does not apply
> error: patch failed: drivers/net/Makefile:66
> error: drivers/net/Makefile: patch does not apply
> Patch failed at 0005 net: add MV88E61xx DSA driver
>
> > Also, after more testing I believe the dm-mdio driver code 'above' is
> > correct but the business of trying to use it and fallback 'below' is
> > wrong and needs work. It doesn't break current users of fec_mxc from
> > what I can tell but it also doesn't properly connect the dm_mdio
> > driver.
>
> Can you spell out what is wrong about the fallback logic?
>
Let me revisit later today and see if I can better explain the issue
here and/or come up with a proper fix.
Can you review 'net: add MV88E61xx DSA driver' for me?
> The whole thing with eth_phy_get_mdio_bus()/eth_phy_set_mdio_bus() has
> me so confused that I am not really following along anymore.
>
I'm pretty confused at CONFIG_DM_ETH_PHY as well. I think that got
added where dm_mdio should have been added instead. see commit
5fe419ef2a61 ("net: Add eth phy generic driver for shared MDIO").
I've added Ye and Peng to the list... maybe they could comment on why
dm_mdio wasn't a viable solution for sharing an mdio bus? Its only
used in for fec_mxc dwc_eth_qos which are only on IMX boards and
believe it was added for IMX8M boards. It's enabled in a whole slew of
imx defconfigs where most of them are likely not needed.
Tim
What I'm trying to accomplish here vs just simply using
dm_fec_bind_mdio(dev) and dm_eth_phy_connect(dev) is to provide a
fallback for the many users of fec_mxc that do not have a dt that
works with dm-mdio yet still have defconfig's that enable DM_MDIO.
Most of the users would not currently have an mdio subnode in the fec
node, nor have the required phy-mode 'and' phy-handle prop or
fixed-link subnode which would cause the dm_eth_phy_connect to fail.
Best Regards,
Tim
Re: [PATCH] dm: Use explicit numbers for all enum values
Hi Michal,
On 4/1/22 6:13 AM, Michal Simek wrote:
> Based on discussion at
> https://lore.kernel.org/r/20200318125003.ga2727...@kroah.com we got
> recommendation to use explicit values for all enum values.
> The patch is following this recommendation.
To comment on Greg's comment
> Yes, but is that guaranteed by the compiler? I keep getting
> conflicting advice with that.
It's guaranteed by the spec as far back as C89:
> Each subsequent enumerator with no = defines its enumeration constant
> as the value of the constant expression obtained by adding 1 to the
> value of the previous enumeration constant.
from http://port70.net/~nsz/c/c89/c89-draft.html#3.5.2.2
I prefer explicit enumerations when dealing with hardware (to
make it very clear what the value of the constant is). However, when
these enumerations are used only by software, they act as arbitrary
identifiers. They can be changed or rearranged at will without regard to
breaking hardware compatibility. This is especially the case if, like
uclass identifiers, they are entirely internal to U-Boot.
For example, the uclass list is sorted alphabetically. This helps reduce
merge conflicts, since multiple uclasses can be added without trampling
on each other's diff context. This patch would make it such that new
uclass identifiers could only be added to the end of the list, or each
identifier would need to be redefined. This would drastically increase
the incident of merge conflicts in this enum. For this reason, I don't
think this patch should be applied.
> The same change was also done by commit 31431dd466e7 ("firmware: xilinx:
> Use explicit values for all enum values").
>
> Signed-off-by: Michal Simek
> ---
>
> I was doing some debug and got uclass ID but without values it is hard to
> find out which uclass it is.
You can get a list of all compiled-in uclasses along with their ids with
the "dm uclass" command.
--Sean
Re: [PATCH 03/25] tegra: Migrate CI_UDC_HAS_HOSTPC to Kconfig
On Wed, Mar 30, 2022 at 11:08 PM Tom Rini wrote: > > This option is only enabled for CI_UDC and !TEGRA20, so implement it as > such in Kconfig directly. > > Signed-off-by: Tom Rini Reviewed-by: Peter Robinson Tested-by: Peter Robinson > --- > arch/arm/mach-tegra/Kconfig | 4 > include/configs/apalis-tk1.h | 1 - > include/configs/apalis_t30.h | 1 - > include/configs/beaver.h | 1 - > include/configs/cei-tk1-som.h | 1 - > include/configs/colibri_t20.h | 1 - > include/configs/colibri_t30.h | 1 - > include/configs/dalmore.h | 1 - > include/configs/jetson-tk1.h | 1 - > include/configs/nyan-big.h| 1 - > include/configs/p2371-.h | 1 - > include/configs/p2371-2180.h | 1 - > include/configs/p2571.h | 1 - > include/configs/p3450-.h | 1 - > include/configs/tegra-common-usb-gadget.h | 18 -- > include/configs/venice2.h | 1 - > 16 files changed, 4 insertions(+), 32 deletions(-) > delete mode 100644 include/configs/tegra-common-usb-gadget.h > > diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig > index 957e3ce64a5e..5309be9cc210 100644 > --- a/arch/arm/mach-tegra/Kconfig > +++ b/arch/arm/mach-tegra/Kconfig > @@ -164,6 +164,10 @@ config TEGRA_DISCONNECT_UDC_ON_BOOT > USB controller when U-Boot boots to avoid leaving a stale USB device > present. > > +config CI_UDC_HAS_HOSTPC > + def_bool y > + depends on CI_UDC && !TEGRA20 > + > config SYS_MALLOC_F_LEN > default 0x1800 > > diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h > index da935f77b9a6..59c901994fd3 100644 > --- a/include/configs/apalis-tk1.h > +++ b/include/configs/apalis-tk1.h > @@ -111,7 +111,6 @@ > #undef CONFIG_SYS_MAXARGS > #define CONFIG_SYS_MAXARGS 32 > > -#include "tegra-common-usb-gadget.h" > #include "tegra-common-post.h" > > #endif /* __CONFIG_H */ > diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h > index eab4f22be34e..b7a2fb695e2f 100644 > --- a/include/configs/apalis_t30.h > +++ b/include/configs/apalis_t30.h > @@ -49,7 +49,6 @@ > #define BOARD_EXTRA_ENV_SETTINGS \ > UBOOT_UPDATE > > -#include "tegra-common-usb-gadget.h" > #include "tegra-common-post.h" > > #endif /* __CONFIG_H */ > diff --git a/include/configs/beaver.h b/include/configs/beaver.h > index 8be491e60103..1d51bb4e4c48 100644 > --- a/include/configs/beaver.h > +++ b/include/configs/beaver.h > @@ -24,7 +24,6 @@ > #define CONFIG_TEGRA_SLINK_CTRLS 6 > #define CONFIG_SPI_FLASH_SIZE (4 << 20) > > -#include "tegra-common-usb-gadget.h" > #include "tegra-common-post.h" > > #endif /* __CONFIG_H */ > diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h > index 1cc86091022b..0672b7dbbe93 100644 > --- a/include/configs/cei-tk1-som.h > +++ b/include/configs/cei-tk1-som.h > @@ -25,7 +25,6 @@ > /* SPI */ > #define CONFIG_SPI_FLASH_SIZE (4 << 20) > > -#include "tegra-common-usb-gadget.h" > #include "tegra-common-post.h" > > #endif /* __CONFIG_H */ > diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h > index c45016a83583..fdf6bb284191 100644 > --- a/include/configs/colibri_t20.h > +++ b/include/configs/colibri_t20.h > @@ -39,7 +39,6 @@ > #undef CONFIG_SYS_MAXARGS > #define CONFIG_SYS_MAXARGS 32 > > -#include "tegra-common-usb-gadget.h" > #include "tegra-common-post.h" > > #endif /* __CONFIG_H */ > diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h > index 324e607839a9..cbe73bf86bad 100644 > --- a/include/configs/colibri_t30.h > +++ b/include/configs/colibri_t30.h > @@ -47,7 +47,6 @@ > #define BOARD_EXTRA_ENV_SETTINGS \ > UBOOT_UPDATE > > -#include "tegra-common-usb-gadget.h" > #include "tegra-common-post.h" > > #endif /* __CONFIG_H */ > diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h > index 2a020e96c405..e03a24adca4a 100644 > --- a/include/configs/dalmore.h > +++ b/include/configs/dalmore.h > @@ -22,7 +22,6 @@ > /* SPI */ > #define CONFIG_SPI_FLASH_SIZE (4 << 20) > > -#include "tegra-common-usb-gadget.h" > #include "tegra-common-post.h" > > #endif /* __CONFIG_H */ > diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h > index b4c42fd37229..69aa55f86c5f 100644 > --- a/include/configs/jetson-tk1.h > +++ b/include/configs/jetson-tk1.h > @@ -23,7 +23,6 @@ > /* SPI */ > #define CONFIG_SPI_FLASH_SIZE (4 << 20) > > -#include "tegra-common-usb-gadget.h" > #include "tegra-common-post.h" > > #endif /* __CONFIG_H */ > diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h > index 3584d9ad90e1..bc5754566bdd 100644 > --- a/include/configs/nyan-big.h > +++ b/include/configs/nyan-big.h > @@ -26,7 +26,6 @@ >
Re: [PATCH v3 2/4] net: mvneta: add SFP TX disable handling
On Thu, Mar 24, 2022 at 11:58 AM Robert Marko wrote:
>
> Add support for handling SFP TX disable for MVNETA in the same fashion as
> to what MVPP2 is doing in order to enable using SFP-s.
>
> This allows using ethernet on SFP only boards.
>
> Signed-off-by: Robert Marko
> ---
> Changes in v3:
> * Check whether the SFP node is enabled
>
> Changes in v2:
> * Parse the standard SFP node for TX disable GPIO instead of using a
> custom property
>
> drivers/net/mvneta.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
> index 4a4268c2b2..edd818338c 100644
> --- a/drivers/net/mvneta.c
> +++ b/drivers/net/mvneta.c
> @@ -286,6 +286,7 @@ struct mvneta_port {
> struct phy_device *phydev;
> #if CONFIG_IS_ENABLED(DM_GPIO)
> struct gpio_desc phy_reset_gpio;
> + struct gpio_desc sfp_tx_disable_gpio;
> #endif
> struct mii_dev *bus;
> };
> @@ -1693,6 +1694,9 @@ static int mvneta_probe(struct udevice *dev)
> {
> struct eth_pdata *pdata = dev_get_plat(dev);
> struct mvneta_port *pp = dev_get_priv(dev);
> +#if CONFIG_IS_ENABLED(DM_GPIO)
> + struct ofnode_phandle_args sfp_args;
> +#endif
> void *blob = (void *)gd->fdt_blob;
> int node = dev_of_offset(dev);
> struct mii_dev *bus;
> @@ -1767,6 +1771,11 @@ static int mvneta_probe(struct udevice *dev)
> return ret;
>
> #if CONFIG_IS_ENABLED(DM_GPIO)
> + ret = dev_read_phandle_with_args(dev, "sfp", NULL, 0, 0, _args);
> + if (!ret && ofnode_is_enabled(sfp_args.node))
> + gpio_request_by_name_nodev(sfp_args.node, "tx-disable-gpio",
> 0,
> + >sfp_tx_disable_gpio,
> GPIOD_IS_OUT);
> +
> gpio_request_by_name(dev, "phy-reset-gpios", 0,
> >phy_reset_gpio, GPIOD_IS_OUT);
>
> @@ -1775,6 +1784,9 @@ static int mvneta_probe(struct udevice *dev)
> mdelay(10);
> dm_gpio_set_value(>phy_reset_gpio, 0);
> }
> +
> + if (dm_gpio_is_valid(>sfp_tx_disable_gpio))
> + dm_gpio_set_value(>sfp_tx_disable_gpio, 0);
> #endif
>
> return board_network_enable(bus);
> --
> 2.35.1
>
Reviewed-by: Ramon Fried
Re: [PATCH] net: phy: dp83867: Fix a never true comparison
On Sat, Mar 19, 2022 at 4:02 PM wrote:
>
> From: Haolin Li
>
> The type of the return value of phy_read() and phy_read_mmd() is int.
> Change the variable to not be unsigned so that we not get into an
> unsigned compared against 0.
>
> Signed-off-by: Haolin Li
> ---
> drivers/net/phy/dp83867.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
> index eada4541c9..c5d44f4629 100644
> --- a/drivers/net/phy/dp83867.c
> +++ b/drivers/net/phy/dp83867.c
> @@ -266,7 +266,7 @@ static int dp83867_of_init(struct phy_device *phydev)
> static int dp83867_config(struct phy_device *phydev)
> {
> struct dp83867_private *dp83867;
> - unsigned int val, delay, cfg2;
> + int val, delay, cfg2;
> int ret, bs;
>
> dp83867 = (struct dp83867_private *)phydev->priv;
> @@ -291,8 +291,11 @@ static int dp83867_config(struct phy_device *phydev)
>
> if (phy_interface_is_rgmii(phydev)) {
> val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
> - if (val < 0)
> + if (val < 0) {
> + ret = val;
> goto err_out;
> + }
> +
> val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
> val |= (dp83867->fifo_depth <<
> DP83867_PHYCR_FIFO_DEPTH_SHIFT);
>
> --
> 2.25.1
>
Reviewed-by: Ramon Fried
[PATCH] arm: dts: imx8mp: Import GPCv2 subset, HSIOMIX and USB PD
Add DT bindings for a subset of GPCv2 which handles USB and PCIe PDs,
HSIOMIX PD controller and missing USB PD properties. This is required
to bring up the DWC3 USB controller up.
This is based on linux next and patches which are still pending
review, but which are likely going to be part of Linux 5.19:
b2d67d7bdf74 ("arm64: dts: imx8mp: disable usb3_phy1")
290918c72a29 ("arm64: dts: imx8mp: Add memory for USB3 glue layer to usb3
nodes")
https://www.spinics.net/lists/arm-kernel/msg958501.html
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
---
arch/arm/dts/imx8mp.dtsi | 72 ++--
1 file changed, 70 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index f9d64253c8a..79b65750da9 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -434,6 +435,44 @@
interrupts = ;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a {
+ compatible = "fsl,imx8mp-gpc";
+ reg = <0x303a 0x1000>;
+ interrupt-parent = <>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_pcie_phy: power-domain@1 {
+ #power-domain-cells = <0>;
+ reg =
;
+ };
+
+ pgc_usb1_phy: power-domain@2 {
+ #power-domain-cells = <0>;
+ reg =
;
+ };
+
+ pgc_usb2_phy: power-domain@3 {
+ #power-domain-cells = <0>;
+ reg =
;
+ };
+
+ pgc_hsiomix: power-domains@17 {
+ #power-domain-cells = <0>;
+ reg =
;
+ clocks = <
IMX8MP_CLK_HSIO_AXI>,
+<
IMX8MP_CLK_HSIO_ROOT>;
+ assigned-clocks = <
IMX8MP_CLK_HSIO_AXI>;
+ assigned-clock-parents = <
IMX8MP_SYS_PLL2_500M>;
+ assigned-clock-rates =
<5>;
+ };
+ };
+ };
};
aips2: bus@3040 {
@@ -842,6 +881,28 @@
};
};
+ aips4: bus@32c0 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x32c0 0x40>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ hsio_blk_ctrl: blk-ctrl@32f1 {
+ compatible = "fsl,imx8mp-hsio-blk-ctrl",
"syscon";
+ reg = <0x32f1 0x24>;
+ clocks = < IMX8MP_CLK_USB_ROOT>,
+< IMX8MP_CLK_PCIE_ROOT>;
+ clock-names = "usb", "pcie";
+ power-domains = <_hsiomix>, <_hsiomix>,
+ <_usb1_phy>,
<_usb2_phy>,
+ <_hsiomix>, <_pcie_phy>;
+ power-domain-names = "bus", "usb", "usb-phy1",
+"usb-phy2", "pcie",
"pcie-phy";
+ #power-domain-cells = <1>;
+ };
+ };
+
gic: interrupt-controller@3880 {
compatible = "arm,gic-v3";
reg = <0x3880 0x1>,
@@ -865,17 +926,20 @@
clock-names = "phy";
assigned-clocks = < IMX8MP_CLK_USB_PHY_REF>;
assigned-clock-parents = < IMX8MP_CLK_24M>;
+ power-domains = <_blk_ctrl
IMX8MP_HSIOBLK_PD_USB_PHY1>;
#phy-cells = <0>;
status = "disabled";
};
usb3_0: usb@32f10100 {
[PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP
The i.MX8MP glue needs to be configured based on a couple of DT
properties, implement .glue_configure callback to parse those DT
properties and configure the glue accordingly.
Signed-off-by: Marek Vasut
Cc: Angus Ainslie
Cc: Bin Meng
Cc: Fabio Estevam
Cc: Kunihiko Hayashi
Cc: Michal Simek
Cc: Peng Fan
Cc: Stefano Babic
---
drivers/usb/dwc3/dwc3-generic.c | 52 +
1 file changed, 52 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 7e3814207e4..6cf844cb483 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -223,6 +223,57 @@ struct dwc3_glue_ops {
enum usb_dr_mode mode);
};
+void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
+ enum usb_dr_mode mode)
+{
+/* USB glue registers */
+#define USB_CTRL0 0x00
+#define USB_CTRL1 0x04
+
+#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
+#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
+#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
+
+#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
+#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
+ fdt_addr_t regs = dev_read_addr_index(dev, 1);
+ void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
+ u32 value;
+
+ value = readl(base + USB_CTRL0);
+
+ if (dev_read_bool(dev, "fsl,permanently-attached"))
+ value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
+ else
+ value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
+
+ if (dev_read_bool(dev, "fsl,disable-port-power-control"))
+ value &= ~(USB_CTRL0_PORTPWR_EN);
+ else
+ value |= USB_CTRL0_PORTPWR_EN;
+
+ writel(value, base + USB_CTRL0);
+
+ value = readl(base + USB_CTRL1);
+ if (dev_read_bool(dev, "fsl,over-current-active-low"))
+ value |= USB_CTRL1_OC_POLARITY;
+ else
+ value &= ~USB_CTRL1_OC_POLARITY;
+
+ if (dev_read_bool(dev, "fsl,power-active-low"))
+ value |= USB_CTRL1_PWR_POLARITY;
+ else
+ value &= ~USB_CTRL1_PWR_POLARITY;
+
+ writel(value, base + USB_CTRL1);
+
+ unmap_physmem(base, MAP_NOCACHE);
+}
+
+struct dwc3_glue_ops imx8mp_ops = {
+ .glue_configure = dwc3_imx8mp_glue_configure,
+};
+
void dwc3_ti_glue_configure(struct udevice *dev, int index,
enum usb_dr_mode mode)
{
@@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "rockchip,rk3328-dwc3" },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "qcom,dwc3" },
+ { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)_ops },
{ .compatible = "fsl,imx8mq-dwc3" },
{ .compatible = "intel,tangier-dwc3" },
{ }
--
2.35.1
[PATCH 1/2] usb: dwc3: Rename .select_dr_mode to .glue_configure
Rename the select_dr_mode callback to glue_configure, the callback is
used for more than enforcing controller mode even on the TI chips, so
change the name to a more generic one. No functional change.
Signed-off-by: Marek Vasut
Cc: Angus Ainslie
Cc: Bin Meng
Cc: Fabio Estevam
Cc: Kunihiko Hayashi
Cc: Michal Simek
Cc: Peng Fan
Cc: Stefano Babic
---
drivers/usb/dwc3/dwc3-generic.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 01bd0ca190e..7e3814207e4 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -219,11 +219,11 @@ U_BOOT_DRIVER(dwc3_generic_host) = {
#endif
struct dwc3_glue_ops {
- void (*select_dr_mode)(struct udevice *dev, int index,
+ void (*glue_configure)(struct udevice *dev, int index,
enum usb_dr_mode mode);
};
-void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
+void dwc3_ti_glue_configure(struct udevice *dev, int index,
enum usb_dr_mode mode)
{
#define USBOTGSS_UTMI_OTG_STATUS 0x0084
@@ -304,7 +304,7 @@ enum dwc3_omap_utmi_mode {
}
struct dwc3_glue_ops ti_ops = {
- .select_dr_mode = dwc3_ti_select_dr_mode,
+ .glue_configure = dwc3_ti_glue_configure,
};
static int dwc3_glue_bind(struct udevice *parent)
@@ -435,8 +435,8 @@ static int dwc3_glue_probe(struct udevice *dev)
dr_mode = usb_get_dr_mode(dev_ofnode(child));
device_find_next_child();
- if (ops && ops->select_dr_mode)
- ops->select_dr_mode(dev, index, dr_mode);
+ if (ops && ops->glue_configure)
+ ops->glue_configure(dev, index, dr_mode);
index++;
}
--
2.35.1
[PATCH v2] clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock
Add clock tables required to bring up DWC3 USB, USB PHY and HSIOMIX domain.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
---
V2: - Get and probe 24m clock without registering it again (suggested by Ye)
- Add 32k clock the same way for usb_root_clk
---
drivers/clk/imx/clk-imx8mp.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index c77500bcce0..041ba5321a3 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -76,6 +76,10 @@ static const char *imx8mp_a53_sels[] = {"clock-osc-24m",
"arm_pll_out", "sys_pll
"sys_pll2_1000m", "sys_pll1_800m",
"sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
+static const char *imx8mp_hsio_axi_sels[] = {"clock-osc-24m", "sys_pll2_500m",
"sys_pll1_800m",
+"sys_pll2_100m", "sys_pll2_200m",
"clk_ext2",
+"clk_ext4", "audio_pll2_out", };
+
static const char *imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m",
"sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_1000m",
"audio_pll1_out",
"video_pll1_out",
"sys_pll1_100m",};
@@ -156,6 +160,14 @@ static const char *imx8mp_uart4_sels[] = {"clock-osc-24m",
"sys_pll1_80m", "sys_
"sys_pll2_100m", "sys_pll3_out",
"clk_ext2",
"clk_ext3", "audio_pll2_out", };
+static const char *imx8mp_usb_core_ref_sels[] = {"clock-osc-24m",
"sys_pll1_100m", "sys_pll1_40m",
+"sys_pll2_100m",
"sys_pll2_200m", "clk_ext2",
+"clk_ext3", "audio_pll2_out",
};
+
+static const char *imx8mp_usb_phy_ref_sels[] = {"clock-osc-24m",
"sys_pll1_100m", "sys_pll1_40m",
+ "sys_pll2_100m",
"sys_pll2_200m", "clk_ext2",
+ "clk_ext3", "audio_pll2_out", };
+
static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m",
"sys_pll1_40m",
"sys_pll2_100m", "sys_pll1_800m",
"sys_pll2_500m", "clk_ext4",
"audio_pll2_out" };
@@ -276,7 +288,9 @@ static struct clk_ops imx8mp_clk_ops = {
static int imx8mp_clk_probe(struct udevice *dev)
{
+ struct clk osc_24m_clk, osc_32k_clk;
void __iomem *base;
+ int ret;
base = (void *)ANATOP_BASE_ADDR;
@@ -324,6 +338,16 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m",
"sys_pll2_out", 1, 2));
clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m",
"sys_pll2_out", 1, 1));
+ ret = clk_get_by_name(dev, "osc_24m", _24m_clk);
+ if (ret)
+ return ret;
+ clk_dm(IMX8MP_CLK_24M, dev_get_clk_ptr(osc_24m_clk.dev));
+
+ ret = clk_get_by_name(dev, "osc_32k", _32k_clk);
+ if (ret)
+ return ret;
+ clk_dm(IMX8MP_CLK_32K, dev_get_clk_ptr(osc_32k_clk.dev));
+
base = dev_read_addr_ptr(dev);
if (!base)
return -EINVAL;
@@ -332,6 +356,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src",
base + 0x8000, 28));
clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div",
"arm_a53_cg", base + 0x8000, 0, 3));
+ clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi",
imx8mp_hsio_axi_sels, base + 0x8380));
clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi",
imx8mp_main_axi_sels, base + 0x8800));
clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi",
imx8mp_enet_axi_sels, base + 0x8880));
clk_dm(IMX8MP_CLK_NAND_USDHC_BUS,
imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base +
0x8900));
@@ -361,6 +386,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2",
imx8mp_uart2_sels, base + 0xaf80));
clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3",
imx8mp_uart3_sels, base + 0xb000));
clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4",
imx8mp_uart4_sels, base + 0xb080));
+ clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite("usb_core_ref",
imx8mp_usb_core_ref_sels, base + 0xb100));
+ clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite("usb_phy_ref",
imx8mp_usb_phy_ref_sels, base + 0xb180));
clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic",
imx8mp_gic_sels, base + 0xb200));
clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels,
base + 0xb900));
Re: [PATCH] ARM: dts: colibri-imx6ull: fix mac address passing
On Thu, Sep 23, 2021 at 09:55:21AM +0200, Francesco Dolcini wrote: > colibri-imx6ull ethernet device is fec2, while the optional secondary > ethernet is fec1, update the ethernet aliases in the .dts file so that > ethaddr is set to fec2 and eth1addr to fec1. > > Without this change the ethernet interfaces have a different > mac address between Linux and U-Boot. > > Signed-off-by: Francesco Dolcini > Reviewed-by: Fabio Estevam Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[uU PATCH 8/8] binman: dtsi: tispl: j721e: Use binman to package tispl.bin
Explicit make commands were earlier used to generate tispl.bin image,
now it is replaced using binman.
Binman picks up and packages entries according to the description of
entries given in the binman node in the device tree. The make commands
that were earlier responsible for generating tispl.bin has been removed.
j721e-a72-binman.dtsi has been introduced for A72 specific binman node.
It can be included in files that require it like
k3-j721e-common-proc-board-u-boot.dtsi.
Note that make commands for secure devices has also been removed as
focus is on general purpose devices at present time.
Signed-off-by: Tarun Sahu
[n-fran...@ti.com: prepared patch for upstreaming]
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/j721e-a72-binman.dtsi| 92 +++
.../k3-j721e-common-proc-board-u-boot.dtsi| 1 +
arch/arm/mach-k3/config.mk| 33 ---
board/ti/j721e/Kconfig| 1 +
scripts/Makefile.spl | 4 -
5 files changed, 94 insertions(+), 37 deletions(-)
create mode 100644 arch/arm/dts/j721e-a72-binman.dtsi
diff --git a/arch/arm/dts/j721e-a72-binman.dtsi
b/arch/arm/dts/j721e-a72-binman.dtsi
new file mode 100644
index 00..a01b1fcc6d
--- /dev/null
+++ b/arch/arm/dts/j721e-a72-binman.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+
+#include
+
+#ifdef CONFIG_ARM64
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+ {
+ tispl {
+ filename = "tispl.bin";
+ fit {
+ description = "FIT IMAGE";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+ images {
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = ;
+ entry = ;
+ atf-bl31 {
+ filename = "bl31.bin";
+ };
+ };
+ tee {
+ description = "OPTEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <0x9e80>;
+ entry = <0x9e80>;
+ tee-os {
+ filename = "tee-pager.bin";
+ missing-msg = "tee-os";
+ };
+ };
+ dm {
+ description = "DM binary";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0x8900>;
+ entry = <0x8900>;
+ ti-dm {
+ filename = "dm.bin";
+ };
+ };
+ spl {
+ description = "SPL (64-bit)";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x8008>;
+ entry = <0x8008>;
+ blob-ext {
+ filename =
"spl/u-boot-spl-nodtb.bin";
+ };
+ };
+ k3-j721e-common-proc-board.dtb {
+ description =
"k3-j721e-common-proc-board";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename =
[uU PATCH 7/8] binman: etype: dm: Add entry type for TI DM
K3 devices introduces the concept of centralized power, resource and
security management to System Firmware. This is to overcome challenges
by the traditional approach that implements system control functions on
each of the processing units.
The software interface for System Firmware is split into TIFS and DM. DM
(Device Manager) is responsible for resource and power management from
secure and non-secure hosts. This additional binary is necessary for
specific platforms' ROM boot images and is to be packaged into tispl.bin
Add an entry for DM. The entry can be used for the packaging of
tispl.bin by binman along with ATF and TEE.
Signed-off-by: Neha Malcom Francis
---
Makefile| 1 +
tools/binman/entries.rst| 10 ++
tools/binman/etype/ti_dm.py | 22 ++
tools/binman/ftest.py | 7 +++
tools/binman/test/225_ti_dm.dts | 13 +
5 files changed, 53 insertions(+)
create mode 100644 tools/binman/etype/ti_dm.py
create mode 100644 tools/binman/test/225_ti_dm.dts
diff --git a/Makefile b/Makefile
index 4672147318..dd3403f912 100644
--- a/Makefile
+++ b/Makefile
@@ -1328,6 +1328,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if
$(BINMAN_DEBUG),-D) \
$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
-a atf-bl31-path=${BL31} \
-a tee-os-path=${TEE} \
+ -a ti-dm-path=${DM} \
-a opensbi-path=${OPENSBI} \
-a default-dt=$(default_dt) \
-a scp-path=$(SCP) \
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index 7c95bbfbec..cf392b6e32 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -1030,6 +1030,16 @@ devices.
+Entry: ti-dm: Texas Instruments Device Manager (DM) blob
+-
+
+Properties / Entry arguments:
+- ti-dm-path: Filename of file to read into the entry, typically dm.bin
+
+This entry holds the device manager responsible for resource and power
management in K3 devices.
+
+
+
Entry: section: Entry that contains other entries
-
diff --git a/tools/binman/etype/ti_dm.py b/tools/binman/etype/ti_dm.py
new file mode 100644
index 00..f44ee21777
--- /dev/null
+++ b/tools/binman/etype/ti_dm.py
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Entry type for TI Device Manager
+
+from binman.etype.blob_named_by_arg import Entry_blob_named_by_arg
+import os
+
+
+class Entry_ti_dm(Entry_blob_named_by_arg):
+"""Entry containing a Device Manager (DM)
+
+Properties / Entry arguments:
+- ti-dm-path: Filename of file to read into the entry, typically dm.bin
+
+This entry holds the device manager responsible for resource and power
management
+in K3 devices.
+"""
+
+def __init__(self, section, etype, node):
+super().__init__(section, etype, node, 'ti-dm')
+self.external = True
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 7c12058fe4..52bfbe792c 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -85,6 +85,7 @@ FSP_S_DATA= b'fsp_s'
FSP_T_DATA= b'fsp_t'
ATF_BL31_DATA = b'bl31'
TEE_OS_DATA = b'this is some tee OS data'
+TI_DM_DATA= b'tidmtidm'
ATF_BL2U_DATA = b'bl2u'
OPENSBI_DATA = b'opensbi'
SYSFW_DATA= b'sysfw'
@@ -191,6 +192,7 @@ class TestFunctional(unittest.TestCase):
TestFunctional._MakeInputFile('compress_big', COMPRESS_DATA_BIG)
TestFunctional._MakeInputFile('bl31.bin', ATF_BL31_DATA)
TestFunctional._MakeInputFile('tee-pager.bin', TEE_OS_DATA)
+TestFunctional._MakeInputFile('dm.bin', TI_DM_DATA)
TestFunctional._MakeInputFile('bl2u.bin', ATF_BL2U_DATA)
TestFunctional._MakeInputFile('fw_dynamic.bin', OPENSBI_DATA)
TestFunctional._MakeInputFile('sysfw.bin', SYSFW_DATA)
@@ -5305,6 +5307,11 @@ fdt fdtmapExtract the devicetree
blob from the fdtmap
data = self._DoReadFile('222_tee_os.dts')
self.assertEqual(TEE_OS_DATA, data[:len(TEE_OS_DATA)])
+def testPackTiDm(self):
+"""Test that an image with a TI DM binary can be created"""
+data = self._DoReadFile('225_ti_dm.dts')
+self.assertEqual(TI_DM_DATA, data[:len(TI_DM_DATA)])
+
def testFitFdtOper(self):
"""Check handling of a specified FIT operation"""
entry_args = {
diff --git a/tools/binman/test/225_ti_dm.dts b/tools/binman/test/225_ti_dm.dts
new file mode 100644
index 00..3ab754131e
--- /dev/null
+++ b/tools/binman/test/225_ti_dm.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ binman {
+ ti-dm {
+
[uU PATCH 6/8] binman: dtsi: sysfw: j721e: Use binman to package sysfw.itb
By providing entries in the binman node of the device tree, binman will
be able to find and package board config binary artifacts generated by
TIBoardConfig with sysfw.bin and generate the final image sysfw.itb.
j721e-r5-binman.dtsi has been introduced for R5 specific binman node. It
can be then be include by files that require it like
k3-j721e-r5-common-proc-board-u-boot.dtsi.
Signed-off-by: Tarun Sahu
[n-fran...@ti.com: prepared patch for upstreaming]
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/j721e-r5-binman.dtsi | 75 +++
.../k3-j721e-r5-common-proc-board-u-boot.dtsi | 1 +
board/ti/j721e/Kconfig| 1 +
3 files changed, 77 insertions(+)
create mode 100644 arch/arm/dts/j721e-r5-binman.dtsi
diff --git a/arch/arm/dts/j721e-r5-binman.dtsi
b/arch/arm/dts/j721e-r5-binman.dtsi
new file mode 100644
index 00..6e69084eaa
--- /dev/null
+++ b/arch/arm/dts/j721e-r5-binman.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+
+#include
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+ {
+ binary {
+ filename = "sysfw.bin";
+ sysfw {
+ filename = "ti-fs-firmware-j721e-gp.bin";
+ device = "j721e";
+ load = <0x004>;
+ };
+ };
+ itb {
+ filename = "sysfw.itb";
+ fit {
+ description = "SYSFW and Config Fragments";
+ #address-cells = <1>;
+ images {
+ sysfw.bin {
+ description = "sysfw";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sysfw.bin";
+ };
+ };
+ board-cfg.bin {
+ description = "board-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "board-cfg.bin";
+ };
+ };
+ pm-cfg.bin {
+ description = "pm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "pm-cfg.bin";
+ };
+ };
+ rm-cfg.bin {
+ description = "rm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "rm-cfg.bin";
+ };
+ };
+ sec-cfg.bin {
+ description = "sec-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sec-cfg.bin";
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
index 48c6ddf672..75fae60a97 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
@@ -4,6 +4,7 @@
*/
#include "k3-j721e-common-proc-board-u-boot.dtsi"
+#include "j721e-r5-binman.dtsi"
/ {
chosen {
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
index c28752a658..a3a9d504ae 100644
--- a/board/ti/j721e/Kconfig
+++ b/board/ti/j721e/Kconfig
@@ -24,6 +24,7 @@ config TARGET_J721E_R5_EVM
select RAM
select SPL_RAM
select K3_DDRSS
+ select BINMAN
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
--
2.17.1
[uU PATCH 5/8] binman: sysfw: Add support for packaging tiboot3.bin and sysfw.itb
For devices that require sysfw.itb, board config binary artifacts must be populated in the R5 output directory. These can be used by binman to package sysfw.itb. config.mk for mach-k3 updated to generate the required binaries using tibcfg_gen.py. K3_CERT_GEN has been introduced in config.mk to remove hardcoding of the certificate signing script. Signed-off-by: Neha Malcom Francis --- arch/arm/mach-k3/config.mk | 21 - 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk index da458bcfb2..5491fc4dc8 100644 --- a/arch/arm/mach-k3/config.mk +++ b/arch/arm/mach-k3/config.mk @@ -13,6 +13,7 @@ endif IMAGE_SIZE= $(shell cat $(obj)/u-boot-spl.bin | wc -c) MAX_SIZE= $(shell printf "%d" $(CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE)) +K3_CERT_GEN= $(srctree)/tools/k3_gen_x509_cert.sh ifeq ($(CONFIG_SYS_K3_KEY), "") KEY="" @@ -28,6 +29,24 @@ else KEY=$(patsubst "%",$(srctree)/%,$(CONFIG_SYS_K3_KEY)) endif +# Board config binary artifacts necessary for packaging of tiboot3.bin +# and sysfw.itb by binman, currently for general purpose devices and +# devices that require sysfw.itb in ROM boot image. Currently set up +# for J721E +ifneq ($(CONFIG_SOC_K3_J721E), ) +ifneq ($(CONFIG_TI_SECURE_DEVICE), y) + +CONFIG_YAML = $(srctree)/board/ti/$(BOARD)/config.yaml +SCHEMA_YAML = $(srctree)/board/ti/common/schema.yaml +board-cfg.bin pm-cfg.bin rm-cfg.bin sec-cfg.bin: + $(PYTHON3) $(srctree)/tools/tibcfg_gen.py $(CONFIG_YAML) $(SCHEMA_YAML) +INPUTS-y += board-cfg.bin +INPUTS-y += pm-cfg.bin +INPUTS-y += rm-cfg.bin +INPUTS-y += sec-cfg.bin +endif +endif + # tiboot3.bin is mandated by ROM and ROM only supports R5 boot. # So restrict tiboot3.bin creation for CPU_V7R. ifdef CONFIG_CPU_V7R @@ -41,7 +60,7 @@ image_check: $(obj)/u-boot-spl.bin FORCE fi tiboot3.bin: image_check FORCE - $(srctree)/tools/k3_gen_x509_cert.sh -c 16 -b $(obj)/u-boot-spl.bin \ + $(K3_CERT_GEN) -c 16 -b $(obj)/u-boot-spl.bin \ -o $@ -l $(CONFIG_SPL_TEXT_BASE) -k $(KEY) INPUTS-y += tiboot3.bin -- 2.17.1
[uU PATCH 4/8] config: yaml: j721e_evm: Add board config for J721E EVM
Board config file must be provided in board/ti/ in YAML. These can then be consumed for generation of binaries to package system firmware. Added YAML config for J721E EVM in particular. It is to be noted that the bootflow followed by J721E requires tiboot3.bin, TIFS and board config binaries to be packaged into sysfw.itb along with u-boot.img. It also requires DM, ATF, OPTEE packaged into tispl.bin. Signed-off-by: Tarun Sahu [n-fran...@ti.com: prepared patch for upstreaming] Signed-off-by: Neha Malcom Francis --- board/ti/j721e/config.yaml | 3162 1 file changed, 3162 insertions(+) create mode 100644 board/ti/j721e/config.yaml diff --git a/board/ti/j721e/config.yaml b/board/ti/j721e/config.yaml new file mode 100644 index 00..710517404f --- /dev/null +++ b/board/ti/j721e/config.yaml @@ -0,0 +1,3162 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for J721E EVM +# + +--- + +pm-cfg: +rev: +boardcfg_abi_maj: 0x0 +boardcfg_abi_min: 0x1 + +board-cfg: +rev: +boardcfg_abi_maj: 0x0 +boardcfg_abi_min: 0x1 +control: +subhdr: +magic: 0xC1D3 +size: 7 +main_isolation_enable: 0x5A +main_isolation_hostid: 0x2 +secproxy: +subhdr: +magic: 0x1207 +size: 7 +scaling_factor: 0x1 +scaling_profile: 0x1 +disable_main_nav_secure_proxy: 0 +msmc: +subhdr: +magic: 0xA5C3 +size: 5 +msmc_cache_size: 0x0 +debug_cfg: +subhdr: +magic: 0x020C +size: 8 +trace_dst_enables: 0x00 +trace_src_enables: 0x00 + +sec-cfg: +rev: +boardcfg_abi_maj: 0x0 +boardcfg_abi_min: 0x1 +processor_acl_list: +subhdr: +magic: 0xF1EA +size: 164 +proc_acl_entries: +- #1 +processor_id: 0 +proc_access_master: 0 +proc_access_secondary: [0, 0, 0] +- #2 +processor_id: 0 +proc_access_master: 0 +proc_access_secondary: [0, 0, 0] +- #3 +processor_id: 0 +proc_access_master: 0 +proc_access_secondary: [0, 0, 0] +- #4 +processor_id: 0 +proc_access_master: 0 +proc_access_secondary: [0, 0, 0] +- #5 +processor_id: 0 +proc_access_master: 0 +proc_access_secondary: [0, 0, 0] +- #6 +processor_id: 0 +proc_access_master: 0 +proc_access_secondary: [0, 0, 0] +- #7 +processor_id: 0 +proc_access_master: 0 +proc_access_secondary: [0, 0, 0] +- #8 +processor_id: 0 +proc_access_master: 0 +proc_access_secondary: [0, 0, 0] +- #9 +processor_id: 0 +proc_access_master: 0 +proc_access_secondary: [0, 0, 0] +- #10 +processor_id: 0 +proc_access_master: 0 +proc_access_secondary: [0, 0, 0] +- #11 +processor_id: 0 +proc_access_master: 0 +proc_access_secondary: [0, 0, 0] +- #12 +processor_id: 0 +proc_access_master: 0 +proc_access_secondary: [0, 0, 0] +- #13 +processor_id: 0 +proc_access_master: 0 +proc_access_secondary: [0, 0, 0] +- #14 +processor_id: 0 +
[uU PATCH 3/8] schema: yaml: Add board config schema
Schema file in YAML must be provided in board/ti/common for validating input config files and packaging system firmware. The schema includes entries for rm-cfg, board-cfg, pm-cfg and sec-cfg. Signed-off-by: Tarun Sahu [n-fran...@ti.com: cleaned up config and schema files] Signed-off-by: Neha Malcom Francis --- board/ti/common/schema.yaml | 355 1 file changed, 355 insertions(+) create mode 100644 board/ti/common/schema.yaml diff --git a/board/ti/common/schema.yaml b/board/ti/common/schema.yaml new file mode 100644 index 00..070ff797e0 --- /dev/null +++ b/board/ti/common/schema.yaml @@ -0,0 +1,355 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ +# +# Config schema for TI K3 devices +# + +--- + +definitions: +u8: +type: integer +minimum: 0 +maximum: 0xff +u16: +type: integer +minimum: 0 +maximum: 0x +u32: +type: integer +minimum: 0 +maximum: 0x + + + +type: object +properties: +pm-cfg: +type: object +properties: +rev: +type: object +properties: +boardcfg_abi_maj: +$ref: "#/definitions/u8" +boardcfg_abi_min: +$ref: "#/definitions/u8" +board-cfg: +type: object +properties: +rev: +type: object +properties: +boardcfg_abi_maj: +$ref: "#/definitions/u8" +boardcfg_abi_min: +$ref: "#/definitions/u8" +control: +type: object +properties: +subhdr: +type: object +properties: +magic: +$ref: "#/definitions/u16" +size: +$ref: "#/definitions/u16" +main_isolation_enable: +$ref: "#/definitions/u8" +main_isolation_hostid: +$ref: "#/definitions/u16" + + +secproxy: +type: object +properties: +subhdr: +type: object +properties: +magic: +$ref: "#/definitions/u16" +size: +$ref: "#/definitions/u16" +scaling_factor: +$ref: "#/definitions/u8" +scaling_profile: +$ref: "#/definitions/u8" +disable_main_nav_secure_proxy: +$ref: "#/definitions/u8" + +msmc: +type: object +properties: +subhdr: +type: object +properties: +magic: +$ref: "#/definitions/u16" +size: +$ref: "#/definitions/u16" +msmc_cache_size: +$ref: "#/definitions/u8" +debug_cfg: +type: object +properties: +subhdr: +type: object +properties: +magic: +$ref: "#/definitions/u16" +size: +$ref: "#/definitions/u16" +trace_dst_enables: +$ref: "#/definitions/u16" +trace_src_enables: +$ref: "#/definitions/u16" + +sec-cfg: +type: object +properties: +rev: +type: object +properties: +boardcfg_abi_maj: +$ref: "#/definitions/u8" +boardcfg_abi_min: +$ref: "#/definitions/u8" + +processor_acl_list: +type: object +properties: +subhdr: +type: object +properties: +magic: +$ref: "#/definitions/u16" +size: +$ref: "#/definitions/u16" +proc_acl_entries: +type: array +minItems: 32 +maxItems: 32 +items: +type: object +properties: +processor_id: +
[uU PATCH 2/8] binman: etype: sysfw: Add entry type for sysfw
For K3 devices that require a sysfw image, add entry for SYSFW. It can
contain system firmware image that can be packaged into sysfw.itb by
binman. The method ReadBlobContents in sysfw.py runs the TI K3
certificate generation script to create the signed sysfw image that can
be used for packaging by binman into sysfw.bin.
Signed-off-by: Tarun Sahu
[n-fran...@ti.com: added tests for addition of etype]
Signed-off-by: Neha Malcom Francis
---
tools/binman/entries.rst| 11 ++
tools/binman/etype/sysfw.py | 60 +
tools/binman/ftest.py | 7
tools/binman/test/226_sysfw.dts | 13 +++
4 files changed, 91 insertions(+)
create mode 100644 tools/binman/etype/sysfw.py
create mode 100644 tools/binman/test/226_sysfw.dts
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index 484cde5c80..7c95bbfbec 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -1019,6 +1019,17 @@ This entry holds firmware for an external
platform-specific coprocessor.
+Entry: sysfw: Texas Instruments System Firmware (SYSFW) blob
+
+
+Properties / Entry arguments:
+- sysfw-path: Filename of file to read into the entry, typically sysfw.bin
+
+This entry contains system firmware necessary for booting of K3 architecture
+devices.
+
+
+
Entry: section: Entry that contains other entries
-
diff --git a/tools/binman/etype/sysfw.py b/tools/binman/etype/sysfw.py
new file mode 100644
index 00..c73300400b
--- /dev/null
+++ b/tools/binman/etype/sysfw.py
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Entry type module for TI SYSFW binary blob
+#
+
+import struct
+import zlib
+import os
+import sys
+
+from binman.etype.blob_named_by_arg import Entry_blob_named_by_arg
+from dtoc import fdt_util
+from patman import tools
+
+
+class Entry_sysfw(Entry_blob_named_by_arg):
+"""Entry containing System Firmware (SYSFW) blob
+
+Properties / Entry arguments:
+- sysfw-path: Filename of file to read into the entry, typically
sysfw.bin
+
+This entry contains system firmware necessary for booting of K3 architecture
devices.
+"""
+
+def __init__(self, section, etype, node):
+super().__init__(section, etype, node, 'scp')
+self.core = "0"
+self.missing_msg = "sysfw"
+
+def ReadNode(self):
+self._load_addr = fdt_util.GetInt(self._node, 'load', 0)
+self._args = []
+
+def _SignSysfw(self, out):
+"""Sign the sysfw image and write it to the output directory"""
+# Try running the K3 x509 certificate signing script
+try:
+args = [
+'-c', "0",
+'-b', self._filename,
+'-l', str(self._load_addr),
+'-o', out
+]
+k3_cert_gen_path = os.environ['srctree'] + \
+"/tools/k3_gen_x509_cert.sh"
+tools.run(k3_cert_gen_path, *args)
+self.SetContents(tools.read_file(out))
+return True
+# If not available (example, in the case of binman tests, set entry
contents as dummy binary)
+except KeyError:
+self.missing = True
+self.SetContents(b'sysfw')
+return True
+
+def ObtainContents(self):
+self.missing = False
+out = tools.get_output_filename("sysfwint")
+self._SignSysfw(out)
+return True
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 8f00db6945..7c12058fe4 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -87,6 +87,7 @@ ATF_BL31_DATA = b'bl31'
TEE_OS_DATA = b'this is some tee OS data'
ATF_BL2U_DATA = b'bl2u'
OPENSBI_DATA = b'opensbi'
+SYSFW_DATA= b'sysfw'
SCP_DATA = b'scp'
TEST_FDT1_DATA= b'fdt1'
TEST_FDT2_DATA= b'test-fdt2'
@@ -192,6 +193,7 @@ class TestFunctional(unittest.TestCase):
TestFunctional._MakeInputFile('tee-pager.bin', TEE_OS_DATA)
TestFunctional._MakeInputFile('bl2u.bin', ATF_BL2U_DATA)
TestFunctional._MakeInputFile('fw_dynamic.bin', OPENSBI_DATA)
+TestFunctional._MakeInputFile('sysfw.bin', SYSFW_DATA)
TestFunctional._MakeInputFile('scp.bin', SCP_DATA)
# Add a few .dtb files for testing
@@ -5321,6 +5323,11 @@ fdt fdtmapExtract the devicetree
blob from the fdtmap
self.assertIn("Node '/binman/fit': Unknown operation 'unknown'",
str(exc.exception))
+def testPackSysfw(self):
+"""Test that an image with a SYSFW binary can be created"""
+data = self._DoReadFile('226_sysfw.dts')
+self.assertEqual(SYSFW_DATA, data[:len(SYSFW_DATA)])
+
if __name__ == "__main__":
unittest.main()
diff --git
[uU PATCH 1/8] tools: config: yaml: Add board config class to generate config binaries
For validating config files and generating binary config artifacts, here
board specific config class is added.
Add function cfgBinaryGen() in tibcfg_gen.py. It uses TIBoardConfig
class to load given schema and config files in YAML, validate them and
generate binaries.
Signed-off-by: Tarun Sahu
[n-fran...@ti.com: prepared patch for upstreaming]
Signed-off-by: Neha Malcom Francis
---
test/py/requirements.txt | 1 +
tools/tibcfg_gen.py | 116 +++
2 files changed, 117 insertions(+)
create mode 100644 tools/tibcfg_gen.py
diff --git a/test/py/requirements.txt b/test/py/requirements.txt
index 33c5c0bbc4..a91ba64563 100644
--- a/test/py/requirements.txt
+++ b/test/py/requirements.txt
@@ -4,6 +4,7 @@ coverage==4.5.4
extras==1.0.0
fixtures==3.0.0
importlib-metadata==0.23
+jsonschema==4.0.0
linecache2==1.0.0
more-itertools==7.2.0
packaging==19.2
diff --git a/tools/tibcfg_gen.py b/tools/tibcfg_gen.py
new file mode 100644
index 00..7635596906
--- /dev/null
+++ b/tools/tibcfg_gen.py
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# TI Board Configuration Class for Schema Validation and Binary Generation
+#
+
+from jsonschema import validate
+
+import yaml
+import os
+import sys
+
+
+class TIBoardConfig:
+file_yaml = {}
+schema_yaml = {}
+data_rules = {}
+
+def __init__(self):
+pass
+
+def Load(self, file, schema, data_rules=""):
+with open(file, 'r') as f:
+self.file_yaml = yaml.safe_load(f)
+with open(schema, 'r') as sch:
+self.schema_yaml = yaml.safe_load(sch)
+self.data_rules = data_rules
+
+def CheckValidity(self):
+try:
+validate(self.file_yaml, self.schema_yaml)
+return True
+except Exception as e:
+print(e)
+return False
+
+def __ConvertToByteChunk(self, val, data_type):
+br = []
+size = 0
+if(data_type == "#/definitions/u8"):
+size = 1
+elif(data_type == "#/definitions/u16"):
+size = 2
+elif(data_type == "#/definitions/u32"):
+size = 4
+else:
+return -1
+if(type(val) == int):
+while(val != 0):
+br = br + [(val & 0xFF)]
+val = val >> 8
+while(len(br) < size):
+br = br + [0]
+return br
+
+def __CompileYaml(self, schema_yaml, file_yaml):
+br = []
+for key in file_yaml.keys():
+if not 'type' in schema_yaml['properties'][key]:
+br = br + \
+self.__ConvertToByteChunk(
+file_yaml[key], schema_yaml['properties'][key]["$ref"])
+elif schema_yaml['properties'][key]['type'] == 'object':
+br = br + \
+self.__CompileYaml(
+schema_yaml['properties'][key], file_yaml[key])
+elif schema_yaml['properties'][key]['type'] == 'array':
+for item in file_yaml[key]:
+if not isinstance(item, dict):
+br = br + \
+self.__ConvertToByteChunk(
+item,
schema_yaml['properties'][key]['items']["$ref"])
+else:
+br = br + \
+self.__CompileYaml(
+schema_yaml['properties'][key]['items'], item)
+return br
+
+def GenerateBinaries(self, out_path=""):
+if not os.path.isdir(out_path):
+os.mkdir(out_path)
+if(self.CheckValidity()):
+for key in self.file_yaml.keys():
+br = []
+br = self.__CompileYaml(
+self.schema_yaml['properties'][key], self.file_yaml[key])
+with open(out_path + "/" + key + ".bin", 'wb') as cfg:
+cfg.write(bytearray(br))
+else:
+raise ValueError("Config YAML Validation failed!")
+
+def DeleteBinaries(self, out_path=""):
+if os.path.isdir(out_path):
+for key in self.file_yaml.keys():
+if os.path.isfile(out_path + "/" + key + ".bin"):
+os.remove(out_path + "/" + key + ".bin")
+
+
+def cfgBinaryGen():
+"""Generate config binaries from YAML config file and YAML schema
+Arguments:
+- config_yaml: board config file in YAML
+- schema_yaml: schema file in YAML to validate config_yaml against
+Pass the arguments along with the filename in the Makefile.
+"""
+tibcfg = TIBoardConfig()
+config_yaml = sys.argv[1]
+schema_yaml = sys.argv[2]
+try:
+tibcfg.Load(config_yaml, schema_yaml)
+except:
+raise ValueError("Could not find config files!")
+tibcfg.GenerateBinaries(os.environ['O'])
+
+
[uU PATCH 0/8] Integration of sysfw and tispl with U-Boot build
Devices that belong to the K3 architecture require SYSFW which is a FIT image consisting of a signed system firmware image and board config binaries. Board config binaries are needed to bring up SYSFW during U-Boot SPL startup. The board config data is given in YAML as input. These board configs contain board-specific information such as resource management, power management and security. The following series intends to plumb the system firmware generation into U-Boot using binman for packaging. Thus it will eliminate the need for additional custom repositories for SYSFW generation and also moves t owards the community standard build flow. The series also plumbs the generation of tispl.bin into the build flow. This image is required for loading u-boot in K3 devices. The image is packaged using ATF, OPTEE and DM (Device Manager). Please note that the following series has implemented the above for J721E general purpose board. The board configs and device trees added are specific to J721E GP devices. Also note the introduction of two new etypes for sysfw and ti-dm. The binman tests for sysfw has coverage of 90%, this is believed to be because of the requirement of sysfw to access a signing script located outside the binman directory. Logs of the binman test is located here: https://pastebin.ubuntu.com/p/n5CdT7TFJg/ On running CI tests on Github, errors were produced during world builds of keystone2_keystone3 and siemens (I0T2050 which is based on AM65x). This patch series is intended for only J721E and future work is to expand to the remaining K3 devices as well. The errors that come are mainly due to the boards other than J721E trying to generate tispl.bin. Error logs of the CI test is located here: https://pastebin.ubuntu.com/p/rpMrWzH7tv/ Neha Malcom Francis (8): tools: config: yaml: Add board config class to generate config binaries binman: etype: sysfw: Add entry type for sysfw schema: yaml: Add board config schema config: yaml: j721e_evm: Add board config for J721E EVM binman: sysfw: Add support for packaging tiboot3.bin and sysfw.itb binman: dtsi: sysfw: j721e: Use binman to package sysfw.itb binman: etype: dm: Add entry type for TI DM binman: dtsi: tispl: j721e: Use binman to package tispl.bin Makefile |1 + arch/arm/dts/j721e-a72-binman.dtsi| 92 + arch/arm/dts/j721e-r5-binman.dtsi | 75 + .../k3-j721e-common-proc-board-u-boot.dtsi|1 + .../k3-j721e-r5-common-proc-board-u-boot.dtsi |1 + arch/arm/mach-k3/config.mk| 54 +- board/ti/common/schema.yaml | 355 ++ board/ti/j721e/Kconfig|2 + board/ti/j721e/config.yaml| 3162 + scripts/Makefile.spl |4 - test/py/requirements.txt |1 + tools/binman/entries.rst | 21 + tools/binman/etype/sysfw.py | 60 + tools/binman/etype/ti_dm.py | 22 + tools/binman/ftest.py | 14 + tools/binman/test/225_ti_dm.dts | 13 + tools/binman/test/226_sysfw.dts | 13 + tools/tibcfg_gen.py | 116 + 18 files changed, 3969 insertions(+), 38 deletions(-) create mode 100644 arch/arm/dts/j721e-a72-binman.dtsi create mode 100644 arch/arm/dts/j721e-r5-binman.dtsi create mode 100644 board/ti/common/schema.yaml create mode 100644 board/ti/j721e/config.yaml create mode 100644 tools/binman/etype/sysfw.py create mode 100644 tools/binman/etype/ti_dm.py create mode 100644 tools/binman/test/225_ti_dm.dts create mode 100644 tools/binman/test/226_sysfw.dts create mode 100644 tools/tibcfg_gen.py -- 2.17.1 Thanking You Neha Malcom Francis
[PATCH v2] imx: power-domain: Add i.MX8MP HSIOMIX driver
Add trivial driver for i.MX8MP HSIOMIX handling. This is responsible
for enabling the GPCv2 power domains and clock for USB 3.0 and PCIe
in the correct order. Currently supported is the USB 3.0 part which
can be tested, PCIe support should be easy to add.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
---
V2: Drop two left over unused variables which triggered build warning
---
drivers/power/domain/Kconfig | 7 ++
drivers/power/domain/Makefile | 1 +
drivers/power/domain/imx8mp-hsiomix.c | 159 ++
3 files changed, 167 insertions(+)
create mode 100644 drivers/power/domain/imx8mp-hsiomix.c
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 04fc0054323..7e1b8c072fa 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -40,6 +40,13 @@ config IMX8M_POWER_DOMAIN
Enable support for manipulating NXP i.MX8M on-SoC power domains via
requests to the ATF.
+config IMX8MP_HSIOMIX_BLKCTRL
+ bool "Enable i.MX8MP HSIOMIX domain driver"
+ depends on POWER_DOMAIN && IMX8MP
+ select CLK
+ help
+ Enable support for manipulating NXP i.MX8MP on-SoC HSIOMIX block
controller.
+
config MTK_POWER_DOMAIN
bool "Enable the MediaTek power domain driver"
depends on POWER_DOMAIN && ARCH_MEDIATEK
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 7c8af67dbd6..e6244776216 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_APPLE_PMGR_POWER_DOMAIN) += apple-pmgr.o
obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain-legacy.o
imx8-power-domain.o
obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o
+obj-$(CONFIG_IMX8MP_HSIOMIX_BLKCTRL) += imx8mp-hsiomix.o
obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o
diff --git a/drivers/power/domain/imx8mp-hsiomix.c
b/drivers/power/domain/imx8mp-hsiomix.c
new file mode 100644
index 000..6a721a934a7
--- /dev/null
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Marek Vasut
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define GPR_REG0 0x0
+#define PCIE_CLOCK_MODULE_EN BIT(0)
+#define USB_CLOCK_MODULE_EN BIT(1)
+
+struct imx8mp_hsiomix_priv {
+ void __iomem *base;
+ struct clk clk_usb;
+ struct power_domain pd_bus;
+ struct power_domain pd_usb;
+ struct power_domain pd_usb_phy1;
+ struct power_domain pd_usb_phy2;
+};
+
+static int imx8mp_hsiomix_on(struct power_domain *power_domain)
+{
+ struct udevice *dev = power_domain->dev;
+ struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
+ struct power_domain *domain;
+ int ret;
+
+ ret = power_domain_on(>pd_bus);
+ if (ret)
+ return ret;
+
+ if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) {
+ domain = >pd_usb;
+ } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1) {
+ domain = >pd_usb_phy1;
+ } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) {
+ domain = >pd_usb_phy2;
+ } else {
+ ret = -EINVAL;
+ goto err_pd;
+ }
+
+ ret = power_domain_on(domain);
+ if (ret)
+ goto err_pd;
+
+ ret = clk_enable(>clk_usb);
+ if (ret)
+ goto err_clk;
+
+ if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
+ setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
+
+ return 0;
+
+err_clk:
+ power_domain_off(domain);
+err_pd:
+ power_domain_off(>pd_bus);
+ return ret;
+}
+
+static int imx8mp_hsiomix_off(struct power_domain *power_domain)
+{
+ struct udevice *dev = power_domain->dev;
+ struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
+
+ if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
+ clrbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
+
+ clk_disable(>clk_usb);
+
+ if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
+ power_domain_off(>pd_usb);
+ else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1)
+ power_domain_off(>pd_usb_phy1);
+ else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2)
+ power_domain_off(>pd_usb_phy2);
+
+ power_domain_off(>pd_bus);
+
+ return 0;
+}
+
+static int imx8mp_hsiomix_of_xlate(struct power_domain *power_domain,
+ struct ofnode_phandle_args *args)
+{
+ power_domain->id = args->args[0];
+
+ return 0;
+}
+
+static int imx8mp_hsiomix_probe(struct udevice *dev)
+{
+
Re: [PATCH] ARM: dts: colibri-imx6ull: fix mac address passing
On Fri, Apr 01, 2022 at 10:04:04AM -0400, Tom Rini wrote: > On Fri, Apr 01, 2022 at 02:01:25PM +, Marcel Ziswiler wrote: > > On Fri, 2022-04-01 at 09:43 -0400, Tom Rini wrote: > > > On Fri, Apr 01, 2022 at 12:57:40PM +, Marcel Ziswiler wrote: > > > > > > > May I inquire about the status of this one? Thanks! > > > > > > Should I take it for this release? > > > > Yes, please. Thanks! > > And, re-reading the whole thread in patchwork, I'm going to assume / > hope for a full dts resync for the next merge window. We are in process to update the Linux kernel DTS files now, as soon as this is done we will do the sync. Doing it now would not make sense. Francesco
Re: [PATCH] ARM: dts: colibri-imx6ull: fix mac address passing
On Fri, Apr 01, 2022 at 02:01:25PM +, Marcel Ziswiler wrote: > On Fri, 2022-04-01 at 09:43 -0400, Tom Rini wrote: > > On Fri, Apr 01, 2022 at 12:57:40PM +, Marcel Ziswiler wrote: > > > > > May I inquire about the status of this one? Thanks! > > > > Should I take it for this release? > > Yes, please. Thanks! And, re-reading the whole thread in patchwork, I'm going to assume / hope for a full dts resync for the next merge window. -- Tom signature.asc Description: PGP signature
Re: [PATCH] ARM: dts: colibri-imx6ull: fix mac address passing
On Fri, Apr 01, 2022 at 02:01:25PM +, Marcel Ziswiler wrote: > On Fri, 2022-04-01 at 09:43 -0400, Tom Rini wrote: > > On Fri, Apr 01, 2022 at 12:57:40PM +, Marcel Ziswiler wrote: > > > > > May I inquire about the status of this one? Thanks! > > > > Should I take it for this release? > > Yes, please. Thanks! Will do. Any other toradex platform fixes? > > > > On Fri, 2022-02-04 at 14:55 -0300, Fabio Estevam wrote: > > > > On Thu, Sep 23, 2021 at 4:55 AM Francesco Dolcini > > > > wrote: > > > > > > > > > > colibri-imx6ull ethernet device is fec2, while the optional secondary > > > > > ethernet is fec1, update the ethernet aliases in the .dts file so that > > > > > ethaddr is set to fec2 and eth1addr to fec1. > > > > > > > > > > Without this change the ethernet interfaces have a different > > > > > mac address between Linux and U-Boot. > > > > > > > > > > Signed-off-by: Francesco Dolcini > > > > > > > > Reviewed-by: Fabio Estevam -- Tom signature.asc Description: PGP signature
Re: [PATCH] ARM: dts: colibri-imx6ull: fix mac address passing
On Fri, 2022-04-01 at 09:43 -0400, Tom Rini wrote: > On Fri, Apr 01, 2022 at 12:57:40PM +, Marcel Ziswiler wrote: > > > May I inquire about the status of this one? Thanks! > > Should I take it for this release? Yes, please. Thanks! > > On Fri, 2022-02-04 at 14:55 -0300, Fabio Estevam wrote: > > > On Thu, Sep 23, 2021 at 4:55 AM Francesco Dolcini > > > wrote: > > > > > > > > colibri-imx6ull ethernet device is fec2, while the optional secondary > > > > ethernet is fec1, update the ethernet aliases in the .dts file so that > > > > ethaddr is set to fec2 and eth1addr to fec1. > > > > > > > > Without this change the ethernet interfaces have a different > > > > mac address between Linux and U-Boot. > > > > > > > > Signed-off-by: Francesco Dolcini > > > > > > Reviewed-by: Fabio Estevam
Re: Pull request for efi-2022-04-rc6
On Fri, Apr 01, 2022 at 03:21:14AM +0200, Heinrich Schuchardt wrote: > Dear Tom, > > The following changes since commit 64b78f5721e65e96ea5a3d100d46b2e6fda722df: > > Merge branch '2022-03-31-critical-fixes' (2022-03-31 08:28:43 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-efi.git > tags/efi-2022-04-rc6 > > for you to fetch changes up to b6370aca3709ef23a9e8fe556beaa2e4b4e089c3: > > efi_loader: initrddump: Actually use the custom CFLAGS (2022-03-31 > 19:06:17 +0200) > > No problems were reported by Gitlab CI: > > https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/11531 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] ARM: dts: colibri-imx6ull: fix mac address passing
On Fri, Apr 01, 2022 at 12:57:40PM +, Marcel Ziswiler wrote: > May I inquire about the status of this one? Thanks! Should I take it for this release? > > On Fri, 2022-02-04 at 14:55 -0300, Fabio Estevam wrote: > > On Thu, Sep 23, 2021 at 4:55 AM Francesco Dolcini > > wrote: > > > > > > colibri-imx6ull ethernet device is fec2, while the optional secondary > > > ethernet is fec1, update the ethernet aliases in the .dts file so that > > > ethaddr is set to fec2 and eth1addr to fec1. > > > > > > Without this change the ethernet interfaces have a different > > > mac address between Linux and U-Boot. > > > > > > Signed-off-by: Francesco Dolcini > > > > Reviewed-by: Fabio Estevam -- Tom signature.asc Description: PGP signature
[PATCH 11/11] socfpga: arria10: Allow dcache_enable before relocation
Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).
Since commit 503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.
Signed-off-by: Paweł Anikiel
---
arch/arm/mach-socfpga/misc_arria10.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc_arria10.c
b/arch/arm/mach-socfpga/misc_arria10.c
index 0ed2adfd84..7ce888d197 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -246,3 +246,29 @@ int qspi_flash_software_reset(void)
return 0;
}
#endif
+
+void dram_bank_mmu_setup(int bank)
+{
+ struct bd_info *bd = gd->bd;
+ u32 start, size;
+ int i;
+
+ /* If we're still in OCRAM, don't set the XN bit on it */
+ if (!(gd->flags & GD_FLG_RELOC)) {
+ set_section_dcache(
+ CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
+ DCACHE_WRITETHROUGH);
+ }
+
+ /*
+* The default implementation of this function allows the DRAM dcache
+* to be enabled only after relocation. However, to speed up ECC
+* initialization, we want to be able to enable DRAM dcache before
+* relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram
+* is set first).
+*/
+ start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+ size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+ for (i = start; i < start + size; i++)
+ set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+}
--
2.35.1.1094.g7c7d902a7c-goog
[PATCH 04/11] board: Add Chameleonv3 board dir
Add board directory for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel
---
board/google/chameleonv3/Makefile | 5 +++
board/google/chameleonv3/board.c | 27 ++
board/google/chameleonv3/fpga.its | 28 ++
board/google/chameleonv3/fpga_early_io.its | 35 ++
board/google/chameleonv3/mercury_aa1.c | 43 ++
board/google/chameleonv3/mercury_aa1.h | 12 ++
6 files changed, 150 insertions(+)
create mode 100644 board/google/chameleonv3/Makefile
create mode 100644 board/google/chameleonv3/board.c
create mode 100644 board/google/chameleonv3/fpga.its
create mode 100644 board/google/chameleonv3/fpga_early_io.its
create mode 100644 board/google/chameleonv3/mercury_aa1.c
create mode 100644 board/google/chameleonv3/mercury_aa1.h
diff --git a/board/google/chameleonv3/Makefile
b/board/google/chameleonv3/Makefile
new file mode 100644
index 00..bb413fde83
--- /dev/null
+++ b/board/google/chameleonv3/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright 2022 Google LLC
+
+obj-y := board.o mercury_aa1.o
diff --git a/board/google/chameleonv3/board.c b/board/google/chameleonv3/board.c
new file mode 100644
index 00..4d3049689d
--- /dev/null
+++ b/board/google/chameleonv3/board.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include
+#include
+#include "mercury_aa1.h"
+
+int misc_init_r(void)
+{
+ u8 mac[ARP_HLEN];
+ int res;
+
+ if (env_get("ethaddr"))
+ return 0;
+
+ res = mercury_aa1_read_mac(mac);
+ if (res) {
+ printf("couldn't read mac address: %s\n", errno_str(res));
+ return 0;
+ }
+
+ if (is_valid_ethaddr(mac))
+ eth_env_set_enetaddr("ethaddr", mac);
+
+ return 0;
+}
diff --git a/board/google/chameleonv3/fpga.its
b/board/google/chameleonv3/fpga.its
new file mode 100644
index 00..85a830002f
--- /dev/null
+++ b/board/google/chameleonv3/fpga.its
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+ description = "FIT image with FPGA bistream";
+ #address-cells = <1>;
+
+ images {
+ fpga-periph-1 {
+ description = "FPGA full bitstream";
+ data = /incbin/("../../../fpga.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "config-1";
+ config-1 {
+ description = "Boot with FPGA config";
+ fpga = "fpga-periph-1";
+ };
+ };
+};
diff --git a/board/google/chameleonv3/fpga_early_io.its
b/board/google/chameleonv3/fpga_early_io.its
new file mode 100644
index 00..ebc7bcbaae
--- /dev/null
+++ b/board/google/chameleonv3/fpga_early_io.its
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+ description = "FIT image with FPGA bistream";
+ #address-cells = <1>;
+
+ images {
+ fpga-periph-1 {
+ description = "FPGA peripheral bitstream";
+ data = /incbin/("../../../periph.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+ fpga-core-1 {
+ description = "FPGA core bitstream";
+ data = /incbin/("../../../core.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "config-1";
+ config-1 {
+ description = "Boot with FPGA config";
+ fpga = "fpga-periph-1", "fpga-core-1";
+ };
+ };
+};
diff --git a/board/google/chameleonv3/mercury_aa1.c
b/board/google/chameleonv3/mercury_aa1.c
new file mode 100644
index 00..ed447ec37c
--- /dev/null
+++ b/board/google/chameleonv3/mercury_aa1.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include
+#include
+#include
+#include
+#include "mercury_aa1.h"
+
+#define MERCURY_AA1_ATSHA204A_OTP_MAC0 4
+#define MERCURY_AA1_ATSHA204A_OTP_MAC1 5
+
+int mercury_aa1_read_mac(u8 *mac)
+{
+ struct udevice *dev;
+ u8 buf[8];
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", );
+ if (ret)
+ return ret;
+
+ ret = atsha204a_wakeup(dev);
+ if (ret)
+ return ret;
+
+ ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+
[PATCH 10/11] socfpga: arria10: Wait for fifo empty after writing bitstream
For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.
Signed-off-by: Paweł Anikiel
---
drivers/fpga/socfpga_arria10.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 07bfe3060e..d8089122af 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -80,6 +80,13 @@ static int wait_for_user_mode(void)
1, FPGA_TIMEOUT_MSEC, false);
}
+static int wait_for_fifo_empty(void)
+{
+ return wait_for_bit_le32(_manager_base->imgcfg_stat,
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK,
+ 1, FPGA_TIMEOUT_MSEC, false);
+}
+
int is_fpgamgr_early_user_mode(void)
{
return (readl(_manager_base->imgcfg_stat) &
@@ -874,6 +881,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void
*buf, size_t bsize,
WATCHDOG_RESET();
}
+ wait_for_fifo_empty();
if (fpga_loadfs.rbfinfo.section == periph_section) {
if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
--
2.35.1.1094.g7c7d902a7c-goog
[PATCH 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
Using udelay while the clocks aren't fully configured causes the timer
system to save the wrong clock rate. Use sdelay and wait_on_value
instead (the values used in these functions were found experimentally).
Signed-off-by: Paweł Anikiel
---
arch/arm/mach-socfpga/clock_manager.c | 7 ---
arch/arm/mach-socfpga/clock_manager_arria10.c | 12 ++--
arch/arm/mach-socfpga/include/mach/clock_manager.h | 4
3 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c
b/arch/arm/mach-socfpga/clock_manager.c
index 9e645a4253..c9bd4859f7 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -39,9 +39,10 @@ void cm_wait_for_lock(u32 mask)
/* function to poll in the fsm busy bit */
int cm_wait_for_fsm(void)
{
- return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
-CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 2,
-false);
+ void *reg = (void *)(socfpga_get_clkmgr_addr() + CLKMGR_STAT);
+
+ /* 20s timeout */
+ return wait_on_value(CLKMGR_STAT_BUSY, 0, reg, 1);
}
int set_cpu_clk_info(void)
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 58d5d3fd8a..daa06b9d03 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -551,13 +551,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
- mdelay(1);
+ sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
main_cfg->vco1_numer,
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
- mdelay(1);
+ sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
@@ -585,13 +585,13 @@ static void cm_pll_ramp_periph(struct mainpll_cfg
*main_cfg,
clk_hz),
socfpga_get_clkmgr_addr() +
CLKMGR_A10_PERPLL_VCO1);
- mdelay(1);
+ sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
per_cfg->vco1_numer,
socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
- mdelay(1);
+ sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
@@ -727,7 +727,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct
perpll_cfg *per_cfg)
socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
/* Wait for at least 5 us */
- udelay(5);
+ sdelay(5000);
/* Now deassert BGPWRDN and PWRDN */
clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
@@ -738,7 +738,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct
perpll_cfg *per_cfg)
CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
/* Wait for at least 7 us */
- udelay(7);
+ sdelay(7000);
/* enable the VCO and disable the external regulator to PLL */
writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index a8cb07a1c4..78013f0527 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -20,6 +20,10 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
#endif
#endif
+void sdelay(unsigned long loops);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+ u32 bound);
+
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#include
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
--
2.35.1.1094.g7c7d902a7c-goog
[PATCH 09/11] socfpga: arria10: Improve bitstream loading speed
Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):
* Change the size of the first fs read, so that all the subsequent
reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
This value was chosen so that in subsequent reads the fat fs driver
doesn't have to allocate a temporary buffer in get_contents
(assuming 8KiB clusters).
* Change the buffer size to a larger value when reading to ddr
(but not too large, because large transfers cause a stack overflow
in the dwmmc driver).
Signed-off-by: Paweł Anikiel
---
drivers/fpga/socfpga_arria10.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 798e3a3f90..07bfe3060e 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -30,6 +30,14 @@
#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
#define FPGA_TIMEOUT_CNT 0x100
#define DEFAULT_DDR_LOAD_ADDRESS 0x400
+#define DDR_BUFFER_SIZE0x10
+
+/* When reading bitstream from a filesystem, the size of the first read is
+ * changed so that the subsequent reads are aligned to this value. This value
+ * was chosen so that in subsequent reads the fat fs driver doesn't have to
+ * allocate a temporary buffer in get_contents (assuming 8KiB clusters).
+ */
+#define MAX_FIRST_LOAD_SIZE0x2000
DECLARE_GLOBAL_DATA_PTR;
@@ -526,7 +534,8 @@ static void get_rbf_image_info(struct rbf_info *rbf, u16
*buffer)
#ifdef CONFIG_FS_LOADER
static int first_loading_rbf_to_buffer(struct udevice *dev,
struct fpga_loadfs_info *fpga_loadfs,
- u32 *buffer, size_t *buffer_bsize)
+ u32 *buffer, size_t *buffer_bsize,
+ size_t *buffer_bsize_ori)
{
u32 *buffer_p = (u32 *)*buffer;
u32 *loadable = buffer_p;
@@ -674,6 +683,7 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
}
buffer_size = rbf_size;
+ *buffer_bsize_ori = DDR_BUFFER_SIZE;
}
debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
@@ -686,11 +696,16 @@ static int first_loading_rbf_to_buffer(struct udevice
*dev,
* chunk by chunk transfer is required due to smaller buffer size
* compare to bitstream
*/
+
+ if (buffer_size > MAX_FIRST_LOAD_SIZE)
+ buffer_size = MAX_FIRST_LOAD_SIZE;
+
if (rbf_size <= buffer_size) {
/* Loading whole bitstream into buffer */
buffer_size = rbf_size;
fpga_loadfs->remaining = 0;
} else {
+ buffer_size -= rbf_offset % buffer_size;
fpga_loadfs->remaining -= buffer_size;
}
@@ -806,7 +821,8 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void
*buf, size_t bsize,
* function below.
*/
ret = first_loading_rbf_to_buffer(dev, _loadfs, ,
- _sizebytes);
+ _sizebytes,
+ _sizebytes_ori);
if (ret == 1) {
printf("FPGA: Skipping configuration ...\n");
return 0;
--
2.35.1.1094.g7c7d902a7c-goog
[PATCH 05/11] config: Add Chameleonv3 config
Add defconfig and Kconfig files for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel
---
arch/arm/mach-socfpga/Kconfig | 15
configs/socfpga_chameleonv3_defconfig | 29
include/configs/socfpga_chameleonv3.h | 49 +++
3 files changed, 93 insertions(+)
create mode 100644 configs/socfpga_chameleonv3_defconfig
create mode 100644 include/configs/socfpga_chameleonv3.h
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index bddfd44427..926d535e54 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -118,6 +118,10 @@ config TARGET_SOCFPGA_STRATIX10
select FPGA_INTEL_SDM_MAILBOX
select TARGET_SOCFPGA_SOC64
+config TARGET_SOCFPGA_CHAMELEONV3
+ bool
+ select TARGET_SOCFPGA_ARRIA10
+
choice
prompt "Altera SOCFPGA board select"
optional
@@ -143,6 +147,14 @@ config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
+config TARGET_SOCFPGA_CHAMELEONV3_480_2
+ bool "Google Chameleon V3 480-2 (Arria 10)"
+ select TARGET_SOCFPGA_CHAMELEONV3
+
+config TARGET_SOCFPGA_CHAMELEONV3_270_3
+ bool "Google Chameleon V3 270-3 (Arria 10)"
+ select TARGET_SOCFPGA_CHAMELEONV3
+
config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -194,6 +206,7 @@ config SYS_BOARD
default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+ default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -219,6 +232,7 @@ config SYS_VENDOR
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+ default "google" if TARGET_SOCFPGA_CHAMELEONV3
default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -234,6 +248,7 @@ config SYS_CONFIG_NAME
default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+ default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
diff --git a/configs/socfpga_chameleonv3_defconfig
b/configs/socfpga_chameleonv3_defconfig
new file mode 100644
index 00..815250e589
--- /dev/null
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_CHAMELEONV3_480_2=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_chameleonv3_480_2"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_SIZE=0x1
+CONFIG_ENV_OFFSET=0x4400
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_MMC_DW=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_MISC_INIT_R=y
+CONFIG_ATSHA204A=y
diff --git a/include/configs/socfpga_chameleonv3.h
b/include/configs/socfpga_chameleonv3.h
new file mode 100644
index 00..2f224dfa4c
--- /dev/null
+++ b/include/configs/socfpga_chameleonv3.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 Google LLC
+ */
+#ifndef __SOCFGPA_CHAMELEONV3_H__
+#define __SOCFGPA_CHAMELEONV3_H__
+
+#include
+
+#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
+
+/*
+ * U-Boot general configurations
+ */
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x4000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x0100\0" \
+ "fdt_addr_r=0x0200\0" \
+ "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw
rootwait\0" \
+ "distro_bootcmd=bridge enable; run bootcmd_fit\0" \
+ "autoload=no\0" \
+ "bootcmd_tftp=dhcp; " \
+ "tftpboot ${kernel_addr_r} ${target}/zImage; " \
+ "tftpboot ${fdt_addr_r}
[PATCH 07/11] sysreset: socfpga: Use parent device for reading base address
This driver is a child of the rstmgr driver, both of which share the
same devicetree node. As a result, passing the child's udevice pointer
to dev_read_addr_ptr results in a failure of reading the #address-cells
property. Use the parent udevice pointer instead.
Signed-off-by: Paweł Anikiel
---
drivers/sysreset/sysreset_socfpga.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/sysreset/sysreset_socfpga.c
b/drivers/sysreset/sysreset_socfpga.c
index e38296ac3f..9b62dd5eab 100644
--- a/drivers/sysreset/sysreset_socfpga.c
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -40,7 +40,7 @@ static int socfpga_sysreset_probe(struct udevice *dev)
{
struct socfpga_sysreset_data *data = dev_get_priv(dev);
- data->rstmgr_base = dev_read_addr_ptr(dev);
+ data->rstmgr_base = dev_read_addr_ptr(dev_get_parent(dev));
return 0;
}
--
2.35.1.1094.g7c7d902a7c-goog
[PATCH 06/11] misc: atsha204a: Increase wake delay by tWHI
>From the ATSHA204A datasheet (document DS40002025A):
Wake: If SDA is held low for a period greater than tWLO, the device
exits low-power mode and, after a delay of tWHI, is ready to receive
I2C commands.
tWHI value can be found in table 7-2.
Signed-off-by: Paweł Anikiel
---
drivers/misc/atsha204a-i2c.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c
index b89463babb..ba2ae3d85a 100644
--- a/drivers/misc/atsha204a-i2c.c
+++ b/drivers/misc/atsha204a-i2c.c
@@ -20,7 +20,8 @@
#include
#include
-#define ATSHA204A_TWLO 60
+#define ATSHA204A_TWLO_US 60
+#define ATSHA204A_TWHI_US 2500
#define ATSHA204A_TRANSACTION_TIMEOUT 10
#define ATSHA204A_TRANSACTION_RETRY5
#define ATSHA204A_EXECTIME 5000
@@ -225,7 +226,7 @@ int atsha204a_wakeup(struct udevice *dev)
continue;
}
- udelay(ATSHA204A_TWLO);
+ udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US);
res = atsha204a_recv_resp(dev, );
if (res) {
--
2.35.1.1094.g7c7d902a7c-goog
[PATCH 03/11] arm: dts: Add Chameleonv3 devicetree
Add devicetree for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel
---
arch/arm/dts/Makefile | 2 ++
arch/arm/dts/socfpga_chameleonv3.dtsi | 21 +
arch/arm/dts/socfpga_chameleonv3_270_3.dts | 9 +
arch/arm/dts/socfpga_chameleonv3_480_2.dts | 9 +
4 files changed, 41 insertions(+)
create mode 100644 arch/arm/dts/socfpga_chameleonv3.dtsi
create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3.dts
create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index beaaf15131..0ec4a4cab6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -411,6 +411,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_arria5_secu1.dtb\
socfpga_arria5_socdk.dtb\
socfpga_arria10_socdk_sdmmc.dtb \
+ socfpga_chameleonv3_270_3.dtb \
+ socfpga_chameleonv3_480_2.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_is1.dtb\
socfpga_cyclone5_socdk.dtb \
diff --git a/arch/arm/dts/socfpga_chameleonv3.dtsi
b/arch/arm/dts/socfpga_chameleonv3.dtsi
new file mode 100644
index 00..8b6a6cd8e4
--- /dev/null
+++ b/arch/arm/dts/socfpga_chameleonv3.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_mercury_aa1.dtsi"
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_chameleonv3_270_3.dts
b/arch/arm/dts/socfpga_chameleonv3_270_3.dts
new file mode 100644
index 00..2e29d052e3
--- /dev/null
+++ b/arch/arm/dts/socfpga_chameleonv3_270_3.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+#include "socfpga_chameleonv3_270_3_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_chameleonv3.dtsi"
diff --git a/arch/arm/dts/socfpga_chameleonv3_480_2.dts
b/arch/arm/dts/socfpga_chameleonv3_480_2.dts
new file mode 100644
index 00..3273f216f2
--- /dev/null
+++ b/arch/arm/dts/socfpga_chameleonv3_480_2.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+#include "socfpga_chameleonv3_480_2_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_chameleonv3.dtsi"
--
2.35.1.1094.g7c7d902a7c-goog
[PATCH 02/11] arm: dts: Add Chameleonv3 handoff headers
Add handoff headers for the Google Chameleonv3 variants: 480-2 and 270-3. Both files were generated using qts-filter-a10.sh. Signed-off-by: Paweł Anikiel --- .../dts/socfpga_chameleonv3_270_3_handoff.h | 305 ++ .../dts/socfpga_chameleonv3_480_2_handoff.h | 305 ++ 2 files changed, 610 insertions(+) create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2_handoff.h diff --git a/arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h b/arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h new file mode 100644 index 00..9d8f4a0dd3 --- /dev/null +++ b/arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Intel Arria 10 SoCFPGA configuration + */ + +#ifndef __SOCFPGA_ARRIA10_CONFIG_H__ +#define __SOCFPGA_ARRIA10_CONFIG_H__ + +/* Clocks */ +#define CB_INTOSC_LS_CLK_HZ 6000 +#define EMAC0_CLK_HZ 25000 +#define EMAC1_CLK_HZ 25000 +#define EMAC2_CLK_HZ 25000 +#define EOSC1_CLK_HZ +#define F2H_FREE_CLK_HZ 2 +#define H2F_USER0_CLK_HZ 2 +#define H2F_USER1_CLK_HZ 1 +#define L3_MAIN_FREE_CLK_HZ 2 +#define SDMMC_CLK_HZ 2 +#define TPIU_CLK_HZ 1 +#define MAINPLLGRP_CNTR15CLK_CNT 900 +#define MAINPLLGRP_CNTR2CLK_CNT 900 +#define MAINPLLGRP_CNTR3CLK_CNT 900 +#define MAINPLLGRP_CNTR4CLK_CNT 900 +#define MAINPLLGRP_CNTR5CLK_CNT 900 +#define MAINPLLGRP_CNTR6CLK_CNT 7 +#define MAINPLLGRP_CNTR7CLK_CNT 7 +#define MAINPLLGRP_CNTR7CLK_SRC 0 +#define MAINPLLGRP_CNTR8CLK_CNT 15 +#define MAINPLLGRP_CNTR9CLK_CNT 900 +#define MAINPLLGRP_CNTR9CLK_SRC 0 +#define MAINPLLGRP_MPUCLK_CNT 0 +#define MAINPLLGRP_MPUCLK_SRC 0 +#define MAINPLLGRP_NOCCLK_CNT 0 +#define MAINPLLGRP_NOCCLK_SRC 0 +#define MAINPLLGRP_NOCDIV_CSATCLK 0 +#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1 +#define MAINPLLGRP_NOCDIV_CSTRACECLK 0 +#define MAINPLLGRP_NOCDIV_L4MAINCLK 0 +#define MAINPLLGRP_NOCDIV_L4MPCLK 1 +#define MAINPLLGRP_NOCDIV_L4SPCLK 2 +#define MAINPLLGRP_VCO0_PSRC 0 +#define MAINPLLGRP_VCO1_DENOM 32 +#define MAINPLLGRP_VCO1_NUMER 1584 +#define PERPLLGRP_CNTR2CLK_CNT 5 +#define PERPLLGRP_CNTR2CLK_SRC 1 +#define PERPLLGRP_CNTR3CLK_CNT 900 +#define PERPLLGRP_CNTR3CLK_SRC 1 +#define PERPLLGRP_CNTR4CLK_CNT 14 +#define PERPLLGRP_CNTR4CLK_SRC 1 +#define PERPLLGRP_CNTR5CLK_CNT 374 +#define PERPLLGRP_CNTR5CLK_SRC 1 +#define PERPLLGRP_CNTR6CLK_CNT 900 +#define PERPLLGRP_CNTR6CLK_SRC 0 +#define PERPLLGRP_CNTR7CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_SRC 0 +#define PERPLLGRP_CNTR9CLK_CNT 900 +#define PERPLLGRP_EMACCTL_EMAC0SEL 0 +#define PERPLLGRP_EMACCTL_EMAC1SEL 0 +#define PERPLLGRP_EMACCTL_EMAC2SEL 0 +#define PERPLLGRP_GPIODIV_GPIODBCLK 32000 +#define PERPLLGRP_VCO0_PSRC 0 +#define PERPLLGRP_VCO1_DENOM 32 +#define PERPLLGRP_VCO1_NUMER 1485 +#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16 +#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8 +#define CLKMGR_TESTIOCTRL_PERICLKSEL 8 +#define ALTERAGRP_MPUCLK_MAINCNT 1 +#define ALTERAGRP_MPUCLK_PERICNT 900 +#define ALTERAGRP_NOCCLK_MAINCNT 7 +#define ALTERAGRP_NOCCLK_PERICNT 900 +#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \ + (ALTERAGRP_MPUCLK_MAINCNT)) +#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \ + (ALTERAGRP_NOCCLK_MAINCNT)) + +/* Pin Mux Configuration */ +#define CONFIG_IO_10_INPUT_BUF_EN 1 +#define CONFIG_IO_10_PD_DRV_STRG 10 +#define CONFIG_IO_10_PD_SLW_RT 1 +#define CONFIG_IO_10_PU_DRV_STRG 8 +#define CONFIG_IO_10_PU_SLW_RT 1 +#define CONFIG_IO_10_RTRIM 1 +#define CONFIG_IO_10_WK_PU_EN 0 +#define CONFIG_IO_11_INPUT_BUF_EN 1 +#define CONFIG_IO_11_PD_DRV_STRG 10 +#define CONFIG_IO_11_PD_SLW_RT 1 +#define CONFIG_IO_11_PU_DRV_STRG 8 +#define CONFIG_IO_11_PU_SLW_RT 1 +#define CONFIG_IO_11_RTRIM 1 +#define CONFIG_IO_11_WK_PU_EN 0 +#define CONFIG_IO_12_INPUT_BUF_EN 0 +#define CONFIG_IO_12_PD_DRV_STRG 0 +#define CONFIG_IO_12_PD_SLW_RT 0 +#define CONFIG_IO_12_PU_DRV_STRG 0 +#define CONFIG_IO_12_PU_SLW_RT 0 +#define CONFIG_IO_12_RTRIM 1 +#define CONFIG_IO_12_WK_PU_EN 1 +#define CONFIG_IO_13_INPUT_BUF_EN 0 +#define CONFIG_IO_13_PD_DRV_STRG 0 +#define CONFIG_IO_13_PD_SLW_RT 0 +#define CONFIG_IO_13_PU_DRV_STRG 0 +#define CONFIG_IO_13_PU_SLW_RT 0 +#define CONFIG_IO_13_RTRIM 1 +#define CONFIG_IO_13_WK_PU_EN 1 +#define CONFIG_IO_14_INPUT_BUF_EN 0 +#define CONFIG_IO_14_PD_DRV_STRG 0 +#define CONFIG_IO_14_PD_SLW_RT 0 +#define CONFIG_IO_14_PU_DRV_STRG 0 +#define CONFIG_IO_14_PU_SLW_RT 0 +#define CONFIG_IO_14_RTRIM 1 +#define CONFIG_IO_14_WK_PU_EN 1 +#define CONFIG_IO_15_INPUT_BUF_EN 0 +#define CONFIG_IO_15_PD_DRV_STRG 0 +#define CONFIG_IO_15_PD_SLW_RT 0 +#define CONFIG_IO_15_PU_DRV_STRG 0 +#define CONFIG_IO_15_PU_SLW_RT 0 +#define CONFIG_IO_15_RTRIM 1 +#define CONFIG_IO_15_WK_PU_EN 1 +#define CONFIG_IO_16_INPUT_BUF_EN 0 +#define CONFIG_IO_16_PD_DRV_STRG 10 +#define CONFIG_IO_16_PD_SLW_RT 1 +#define CONFIG_IO_16_PU_DRV_STRG 8 +#define
[PATCH 01/11] arm: dts: Add Mercury+ AA1 devicetree
Device tree header for Mercury+ AA1 module
Signed-off-by: Paweł Anikiel
---
arch/arm/dts/socfpga_mercury_aa1.dtsi | 95 +++
1 file changed, 95 insertions(+)
create mode 100644 arch/arm/dts/socfpga_mercury_aa1.dtsi
diff --git a/arch/arm/dts/socfpga_mercury_aa1.dtsi
b/arch/arm/dts/socfpga_mercury_aa1.dtsi
new file mode 100644
index 00..7d0bf884a3
--- /dev/null
+++ b/arch/arm/dts/socfpga_mercury_aa1.dtsi
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10.dtsi"
+#include "socfpga_arria10-u-boot.dtsi"
+
+/ {
+ model = "Altera SOCFPGA Arria 10";
+ compatible = "altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ ethernet0 =
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ firmware-loader = <_loader0>;
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x8000>; /* 2GB */
+ };
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = < 1>;
+ };
+};
+
+_mgr {
+ u-boot,dm-pre-reloc;
+ altr,bitstream = "fpga.itb";
+};
+
+ {
+ phy-mode = "rgmii";
+ phy-addr = <0x>; /* probe for phy addr */
+
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ max-frame-size = <3800>;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+
+ atsha204a@64 {
+ u-boot,dm-pre-reloc;
+ compatible = "atmel,atsha204a";
+ reg = <0x64>;
+ };
+};
+
+_sdmmc_clk {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ broken-cd;
+ bus-width = <4>;
+ u-boot,dm-pre-reloc;
+};
+
+_sdmmc_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_free_clk {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
--
2.35.1.1094.g7c7d902a7c-goog
[PATCH 00/11] Add Chameleon V3 support
The Google Chameleon V3 is a board made for testing both video and audio interfaces of external devices. It has a connector compatible with the Mercury+ AA1 module, which itself contains an Arria 10 SoCFPGA. The AA1 module comes in a few different configurations, the Chameleon V3 supports ME-AA1-270-3E4-D11 and ME-AA1-480-2I3-D12E. This patchset adds support for the Chameleon V3 (both versions), as well as some bugfixes and optimizations, mostly in Arria 10 code. Paweł Anikiel (11): arm: dts: Add Mercury+ AA1 devicetree arm: dts: Add Chameleonv3 handoff headers arm: dts: Add Chameleonv3 devicetree board: Add Chameleonv3 board dir config: Add Chameleonv3 config misc: atsha204a: Increase wake delay by tWHI sysreset: socfpga: Use parent device for reading base address socfpga: arria10: Replace delays with busy waiting in cm_full_cfg socfpga: arria10: Improve bitstream loading speed socfpga: arria10: Wait for fifo empty after writing bitstream socfpga: arria10: Allow dcache_enable before relocation arch/arm/dts/Makefile | 2 + arch/arm/dts/socfpga_chameleonv3.dtsi | 21 ++ arch/arm/dts/socfpga_chameleonv3_270_3.dts| 9 + .../dts/socfpga_chameleonv3_270_3_handoff.h | 305 ++ arch/arm/dts/socfpga_chameleonv3_480_2.dts| 9 + .../dts/socfpga_chameleonv3_480_2_handoff.h | 305 ++ arch/arm/dts/socfpga_mercury_aa1.dtsi | 103 ++ arch/arm/mach-socfpga/Kconfig | 15 + arch/arm/mach-socfpga/clock_manager.c | 7 +- arch/arm/mach-socfpga/clock_manager_arria10.c | 12 +- .../mach-socfpga/include/mach/clock_manager.h | 4 + arch/arm/mach-socfpga/misc_arria10.c | 26 ++ board/google/chameleonv3/Makefile | 5 + board/google/chameleonv3/board.c | 27 ++ board/google/chameleonv3/fpga.its | 28 ++ board/google/chameleonv3/fpga_early_io.its| 35 ++ board/google/chameleonv3/mercury_aa1.c| 43 +++ board/google/chameleonv3/mercury_aa1.h| 12 + configs/socfpga_chameleonv3_defconfig | 29 ++ drivers/fpga/socfpga_arria10.c| 28 +- drivers/misc/atsha204a-i2c.c | 5 +- drivers/sysreset/sysreset_socfpga.c | 2 +- include/configs/socfpga_chameleonv3.h | 49 +++ 23 files changed, 1067 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/socfpga_chameleonv3.dtsi create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3.dts create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2.dts create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2_handoff.h create mode 100644 arch/arm/dts/socfpga_mercury_aa1.dtsi create mode 100644 board/google/chameleonv3/Makefile create mode 100644 board/google/chameleonv3/board.c create mode 100644 board/google/chameleonv3/fpga.its create mode 100644 board/google/chameleonv3/fpga_early_io.its create mode 100644 board/google/chameleonv3/mercury_aa1.c create mode 100644 board/google/chameleonv3/mercury_aa1.h create mode 100644 configs/socfpga_chameleonv3_defconfig create mode 100644 include/configs/socfpga_chameleonv3.h -- 2.35.1.1094.g7c7d902a7c-goog
Re: [PATCH] ARM: dts: colibri-imx6ull: fix mac address passing
May I inquire about the status of this one? Thanks! On Fri, 2022-02-04 at 14:55 -0300, Fabio Estevam wrote: > On Thu, Sep 23, 2021 at 4:55 AM Francesco Dolcini > wrote: > > > > colibri-imx6ull ethernet device is fec2, while the optional secondary > > ethernet is fec1, update the ethernet aliases in the .dts file so that > > ethaddr is set to fec2 and eth1addr to fec1. > > > > Without this change the ethernet interfaces have a different > > mac address between Linux and U-Boot. > > > > Signed-off-by: Francesco Dolcini > > Reviewed-by: Fabio Estevam
Fwd: Re: U-Boot and DM9000 eth driver support
Just noticed this having been only a private discussion. CCing mailing list as well. Forwarded Message From: Tom Rini To: Marcel Ziswiler Cc: ma...@denx.de , tsi-chung.l...@nxp.com , stel...@popies.net , ezequ...@collabora.com , we...@corscience.de Subject: Re: U-Boot and DM9000 eth driver support Date: Thu, 31 Mar 2022 08:15:16 -0400 On Thu, Mar 31, 2022 at 09:23:11AM +, Marcel Ziswiler wrote: > Hi Marek > > On Wed, 2022-03-30 at 22:12 +0200, Marek Vasut wrote: > > On 3/30/22 20:36, Tom Rini wrote: > > > Hey all, > > > > > > As I was doing some Kconfig migrations I noticed that there's symbols > > > for the DM9000 ethernet driver that haven't been migrated. In turn > > > however, that driver hasn't been migrated to DM yet, and the deadline > > > for that was v2020.07. Since that means I'll be posting patches to drop > > > the driver later this year, I wanted to give everyone a heads-up now to > > > see if anyone is able to convert the driver since you're listed as > > > maintainers of a platform that uses it. Thanks! > > > > +CC Marcel, since this is used on Colibri PXA270 . > > Yeah, I guess we could also just drop Colibri PXA270 support as we stopped > selling those quite a while ago. > Unless, of course, somebody would be interested to keep it further > maintained... > > I can send a removal commit as an RFC and we will see. Okay? Yes, board removals (JFYI, everyone on the list) is also a valid path forward. -- Tom
Re: [PATCH v8] wdt: nuvoton: Add support for Nuvoton
On 4/1/22 11:59, Jim Liu wrote:
Add watchdog controller driver for NPCM7xx/npcm8xx
the wdt design of npcm750 and npcm845 is the same.
so the driver can work on npcm750 and npcm845.
about npcm845 wdt dtsi i will followed kernel dts name
to use nuvoton,npcm750-wdt.
Signed-off-by: Jim Liu
Reviewed-by: Stefan Roese
Reviewed-by: Simon Glass
Changes for v2:
- coding style cleanup
- change register type from struct
Changes for v3:
- remove common.h
Changes for v4:
- add a bit of detail about the device in Kconfig
- lower-case hex change
- remove the reset function delay.
Actually when setting writel(NPCM_WTR )the watchdog is resetting
the BMC
changes for v5:
- modify compatible name to support all NPCM SOC
changes for v6:
- followed linux kernel to modify compatible name
change for v7:
- add second compatible name to driver
change for v8
- remove second compatible name
---
Just a quick note: Thanks for the patch revision history. This makes
reviewing easier in general. But: The history should be placed below
the "---" line instead. Otherwise the patch revision history will also
be added to the git commit message, which should not be the case.
No need to resend. Just make sure to change the order in your next
submissions.
Thanks,
Stefan
drivers/watchdog/Kconfig| 8 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/npcm_wdt.c | 116
3 files changed, 125 insertions(+)
create mode 100644 drivers/watchdog/npcm_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index f90f0ca02b..d33882fb6a 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -196,6 +196,14 @@ config WDT_MTK
The watchdog timer is stopped when initialized.
It performs full SoC reset.
+config WDT_NPCM
+ bool "Nuvoton watchdog timer support"
+ depends on WDT && ARCH_NPCM
+ help
+ This enables Nuvoton npcm7xx/npcm8xx watchdog timer driver,
+ The watchdog timer is stopped when initialized.
+ It performs full SoC reset.
+
config WDT_OCTEONTX
bool "OcteonTX core watchdog support"
depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2)
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index a35bd559f5..1089cd21f5 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o
obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
+obj-$(CONFIG_WDT_NPCM) += npcm_wdt.o
obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o
obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c
new file mode 100644
index 00..256020f5d3
--- /dev/null
+++ b/drivers/watchdog/npcm_wdt.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology, Inc
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */
+#define NPCM_WTE BIT(7) /* Enable */
+#define NPCM_WTIE BIT(6) /* Enable irq */
+#define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */
+#define NPCM_WTIF BIT(3) /* Interrupt flag*/
+#define NPCM_WTRF BIT(2) /* Reset flag */
+#define NPCM_WTRE BIT(1) /* Reset enable */
+#define NPCM_WTR BIT(0) /* Reset counter */
+
+struct npcm_wdt_priv {
+ void __iomem *regs;
+};
+
+static int npcm_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ struct npcm_wdt_priv *priv = dev_get_priv(dev);
+ u32 time_out, val;
+
+ time_out = (u32)(timeout_ms) / 1000;
+ if (time_out < 2)
+ val = 0x800;
+ else if (time_out < 3)
+ val = 0x420;
+ else if (time_out < 6)
+ val = 0x810;
+ else if (time_out < 11)
+ val = 0x430;
+ else if (time_out < 22)
+ val = 0x820;
+ else if (time_out < 44)
+ val = 0xc00;
+ else if (time_out < 87)
+ val = 0x830;
+ else if (time_out < 173)
+ val = 0xc10;
+ else if (time_out < 688)
+ val = 0xc20;
+ else
+ val = 0xc30;
+
+ val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE;
+ writel(val, priv->regs);
+
+ return 0;
+}
+
+static int npcm_wdt_stop(struct udevice *dev)
+{
+ struct npcm_wdt_priv *priv = dev_get_priv(dev);
+
+ writel(0, priv->regs);
+
+ return 0;
+}
+
+static int npcm_wdt_reset(struct udevice *dev)
+{
+ struct npcm_wdt_priv *priv = dev_get_priv(dev);
+
+ writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs);
+
+
[PATCH] dm: Use explicit numbers for all enum values
Based on discussion at
https://lore.kernel.org/r/20200318125003.ga2727...@kroah.com we got
recommendation to use explicit values for all enum values.
The patch is following this recommendation.
The same change was also done by commit 31431dd466e7 ("firmware: xilinx:
Use explicit values for all enum values").
Signed-off-by: Michal Simek
---
I was doing some debug and got uclass ID but without values it is hard to
find out which uclass it is.
---
include/dm/uclass-id.h | 240 -
1 file changed, 120 insertions(+), 120 deletions(-)
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 0e26e1d13824..30d120879a4e 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -13,129 +13,129 @@
enum uclass_id {
/* These are used internally by driver model */
UCLASS_ROOT = 0,
- UCLASS_DEMO,
- UCLASS_TEST,
- UCLASS_TEST_FDT,
- UCLASS_TEST_FDT_MANUAL,
- UCLASS_TEST_BUS,
- UCLASS_TEST_PROBE,
- UCLASS_TEST_DUMMY,
- UCLASS_TEST_DEVRES,
- UCLASS_TEST_ACPI,
- UCLASS_SPI_EMUL,/* sandbox SPI device emulator */
- UCLASS_I2C_EMUL,/* sandbox I2C device emulator */
- UCLASS_I2C_EMUL_PARENT, /* parent for I2C device emulators */
- UCLASS_PCI_EMUL,/* sandbox PCI device emulator */
- UCLASS_PCI_EMUL_PARENT, /* parent for PCI device emulators */
- UCLASS_USB_EMUL,/* sandbox USB bus device emulator */
- UCLASS_AXI_EMUL,/* sandbox AXI bus device emulator */
+ UCLASS_DEMO = 1,
+ UCLASS_TEST = 2,
+ UCLASS_TEST_FDT = 3,
+ UCLASS_TEST_FDT_MANUAL = 4,
+ UCLASS_TEST_BUS = 5,
+ UCLASS_TEST_PROBE = 6,
+ UCLASS_TEST_DUMMY = 7,
+ UCLASS_TEST_DEVRES = 8,
+ UCLASS_TEST_ACPI = 10,
+ UCLASS_SPI_EMUL = 11, /* sandbox SPI device emulator */
+ UCLASS_I2C_EMUL = 12, /* sandbox I2C device emulator */
+ UCLASS_I2C_EMUL_PARENT = 12, /* parent for I2C device emulators */
+ UCLASS_PCI_EMUL = 13, /* sandbox PCI device emulator */
+ UCLASS_PCI_EMUL_PARENT = 14, /* parent for PCI device emulators */
+ UCLASS_USB_EMUL = 15, /* sandbox USB bus device emulator */
+ UCLASS_AXI_EMUL = 16, /* sandbox AXI bus device emulator */
/* U-Boot uclasses start here - in alphabetical order */
- UCLASS_ACPI_PMC,/* (x86) Power-management controller (PMC) */
- UCLASS_ADC, /* Analog-to-digital converter */
- UCLASS_AHCI,/* SATA disk controller */
- UCLASS_AUDIO_CODEC, /* Audio codec with control and data path */
- UCLASS_AXI, /* AXI bus */
- UCLASS_BLK, /* Block device */
- UCLASS_BOOTCOUNT, /* Bootcount backing store */
- UCLASS_BUTTON, /* Button */
- UCLASS_CACHE, /* Cache controller */
- UCLASS_CLK, /* Clock source, e.g. used by peripherals */
- UCLASS_CPU, /* CPU, typically part of an SoC */
- UCLASS_CROS_EC, /* Chrome OS EC */
- UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
- UCLASS_DSI_HOST,/* Display Serial Interface host */
- UCLASS_DMA, /* Direct Memory Access */
- UCLASS_DSA, /* Distributed (Ethernet) Switch Architecture */
- UCLASS_ECDSA, /* Elliptic curve cryptographic device */
- UCLASS_EFI_LOADER, /* Devices created by UEFI applications */
- UCLASS_EFI_MEDIA, /* Devices provided by UEFI firmware */
- UCLASS_ETH, /* Ethernet device */
- UCLASS_ETH_PHY, /* Ethernet PHY device */
- UCLASS_FIRMWARE,/* Firmware */
- UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */
- UCLASS_GPIO,/* Bank of general-purpose I/O pins */
- UCLASS_HASH,/* Hash device */
- UCLASS_HWSPINLOCK, /* Hardware semaphores */
- UCLASS_I2C, /* I2C bus */
- UCLASS_I2C_EEPROM, /* I2C EEPROM device */
- UCLASS_I2C_GENERIC, /* Generic I2C device */
- UCLASS_I2C_MUX, /* I2C multiplexer */
- UCLASS_I2S, /* I2S bus */
- UCLASS_IDE, /* IDE device */
- UCLASS_IOMMU, /* IOMMU */
- UCLASS_IRQ, /* Interrupt controller */
- UCLASS_KEYBOARD,/* Keyboard input device */
- UCLASS_LED, /* Light-emitting diode (LED) */
- UCLASS_LPC, /* x86 'low pin count' interface */
- UCLASS_MAILBOX, /* Mailbox controller */
- UCLASS_MASS_STORAGE,/* Mass storage device */
- UCLASS_MDIO,/* MDIO bus */
- UCLASS_MDIO_MUX,/* MDIO MUX/switch */
- UCLASS_MISC,/* Miscellaneous device */
- UCLASS_MMC, /* SD / MMC card or chip */
- UCLASS_MOD_EXP,
[PATCH v8] wdt: nuvoton: Add support for Nuvoton
Add watchdog controller driver for NPCM7xx/npcm8xx
the wdt design of npcm750 and npcm845 is the same.
so the driver can work on npcm750 and npcm845.
about npcm845 wdt dtsi i will followed kernel dts name
to use nuvoton,npcm750-wdt.
Signed-off-by: Jim Liu
Reviewed-by: Stefan Roese
Reviewed-by: Simon Glass
Changes for v2:
- coding style cleanup
- change register type from struct
Changes for v3:
- remove common.h
Changes for v4:
- add a bit of detail about the device in Kconfig
- lower-case hex change
- remove the reset function delay.
Actually when setting writel(NPCM_WTR )the watchdog is resetting
the BMC
changes for v5:
- modify compatible name to support all NPCM SOC
changes for v6:
- followed linux kernel to modify compatible name
change for v7:
- add second compatible name to driver
change for v8
- remove second compatible name
---
drivers/watchdog/Kconfig| 8 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/npcm_wdt.c | 116
3 files changed, 125 insertions(+)
create mode 100644 drivers/watchdog/npcm_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index f90f0ca02b..d33882fb6a 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -196,6 +196,14 @@ config WDT_MTK
The watchdog timer is stopped when initialized.
It performs full SoC reset.
+config WDT_NPCM
+ bool "Nuvoton watchdog timer support"
+ depends on WDT && ARCH_NPCM
+ help
+ This enables Nuvoton npcm7xx/npcm8xx watchdog timer driver,
+ The watchdog timer is stopped when initialized.
+ It performs full SoC reset.
+
config WDT_OCTEONTX
bool "OcteonTX core watchdog support"
depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2)
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index a35bd559f5..1089cd21f5 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o
obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
+obj-$(CONFIG_WDT_NPCM) += npcm_wdt.o
obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o
obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c
new file mode 100644
index 00..256020f5d3
--- /dev/null
+++ b/drivers/watchdog/npcm_wdt.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology, Inc
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */
+#define NPCM_WTE BIT(7) /* Enable */
+#define NPCM_WTIE BIT(6) /* Enable irq */
+#define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */
+#define NPCM_WTIF BIT(3) /* Interrupt flag*/
+#define NPCM_WTRF BIT(2) /* Reset flag */
+#define NPCM_WTRE BIT(1) /* Reset enable */
+#define NPCM_WTR BIT(0) /* Reset counter */
+
+struct npcm_wdt_priv {
+ void __iomem *regs;
+};
+
+static int npcm_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ struct npcm_wdt_priv *priv = dev_get_priv(dev);
+ u32 time_out, val;
+
+ time_out = (u32)(timeout_ms) / 1000;
+ if (time_out < 2)
+ val = 0x800;
+ else if (time_out < 3)
+ val = 0x420;
+ else if (time_out < 6)
+ val = 0x810;
+ else if (time_out < 11)
+ val = 0x430;
+ else if (time_out < 22)
+ val = 0x820;
+ else if (time_out < 44)
+ val = 0xc00;
+ else if (time_out < 87)
+ val = 0x830;
+ else if (time_out < 173)
+ val = 0xc10;
+ else if (time_out < 688)
+ val = 0xc20;
+ else
+ val = 0xc30;
+
+ val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE;
+ writel(val, priv->regs);
+
+ return 0;
+}
+
+static int npcm_wdt_stop(struct udevice *dev)
+{
+ struct npcm_wdt_priv *priv = dev_get_priv(dev);
+
+ writel(0, priv->regs);
+
+ return 0;
+}
+
+static int npcm_wdt_reset(struct udevice *dev)
+{
+ struct npcm_wdt_priv *priv = dev_get_priv(dev);
+
+ writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs);
+
+ return 0;
+}
+
+static int npcm_wdt_of_to_plat(struct udevice *dev)
+{
+ struct npcm_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->regs = dev_read_addr_ptr(dev);
+ if (!priv->regs)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct wdt_ops npcm_wdt_ops = {
+ .start = npcm_wdt_start,
+ .reset = npcm_wdt_reset,
+ .stop = npcm_wdt_stop,
+};
+
+static const struct udevice_id
Re: [PATCH v4 4/8] board: Define set_dfu_alt_info() for boards with UEFI capsule update enabled
Hi Sughosh
On Fri, 1 Apr 2022 at 09:58, Sughosh Ganu wrote:
>
> hi Ilias,
>
> On Fri, 1 Apr 2022 at 01:05, Ilias Apalodimas
> wrote:
> >
> > Hi Sughosh,
> >
> > Some nots below
> >
> > On Thu, Mar 31, 2022 at 06:57:46PM +0530, Sughosh Ganu wrote:
> > > Currently, there are a bunch of boards which enable the UEFI capsule
> > > update feature. The actual update of the firmware images is done
> > > through the dfu framework which uses the dfu_alt_info environment
> > > variable for getting information on the update, like device, partition
> > > number/address etc. Currently, these boards define the dfu_alt_info
> > > variable in the board config header, as an environment variable. With
> > > this, the variable can be modified from the u-boot command line and
> > > this can cause an incorrect update.
> > >
> > > To prevent this from happening, define the set_dfu_alt_info function
> > > in the board file, and select SET_DFU_ALT_INFO for all platforms which
> > > enable the capsule update feature. With the function defined, the dfu
> > > framework populates the dfu_alt_info variable through the board file,
> > > instead of fetching the variable from the environment, thus making the
> > > update more robust.
> > >
> > > Signed-off-by: Sughosh Ganu
> > > ---
> > >
> > > Changes since V3:
> > > * Do not remove the existing dfu_alt_info definitions made by
> > > platforms in the config files, as discussed with Masami.
> > > * Squash the selection of the SET_DFU_ALT_INFO config symbol for
> > > capsule update feature as part of this patch.
> > >
> > >
> > > .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 24 +
> > > .../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 24 +
> > > board/emulation/common/qemu_dfu.c | 6 ++---
> > > board/kontron/pitx_imx8m/pitx_imx8m.c | 24 +
> > > board/kontron/sl-mx8mm/sl-mx8mm.c | 24 +
> > > board/kontron/sl28/sl28.c | 25 ++
> > > board/sandbox/sandbox.c | 26 +++
> > > board/socionext/developerbox/developerbox.c | 26 +++
> > > board/xilinx/zynq/board.c | 5 ++--
> > > board/xilinx/zynqmp/zynqmp.c | 5 ++--
> > > lib/efi_loader/Kconfig| 2 ++
> > > 11 files changed, 184 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
> > > b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
> > > index 1c953ba195..41154ca9f3 100644
> > > --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
> > > +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
> > > @@ -5,10 +5,12 @@
> > > */
> > >
> > > #include
> > > +#include
> > > #include
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > > #include
> > > @@ -24,6 +26,7 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #include
> > >
> > > DECLARE_GLOBAL_DATA_PTR;
> > > @@ -231,3 +234,24 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct
> > > mmc *mmc)
> > > }
> > > }
> > > #endif /* CONFIG_SPL_MMC_SUPPORT */
> > > +
> > > +#if defined(CONFIG_SET_DFU_ALT_INFO)
> > > +
> > > +#define DFU_ALT_BUF_LEN SZ_1K
> > > +
> > > +void set_dfu_alt_info(char *interface, char *devstr)
> > > +{
> > > + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
> > > +
> > > + if (!CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) &&
> > > + env_get("dfu_alt_info"))
> > > + return;
> >
> > Just add a helper function with this since we need to repeat it for every
> > board. Something like 'bool needs_runtime_dfu_alt_info() '
>
> Okay
>
> > > +
> > > + memset(buf, 0, DFU_ALT_BUF_LEN);
> >
> > I'd prefer sizeof(buf) instead of explicitly calling the length.
>
> So the current boards are using this wrong. The
> ALLOC_CACHE_ALIGN_BUFFER actually defines an array named __buf, and a
> char *buf which points to the array. So the existing code in some
> boards was zeroing out only the sizeof(char *) number of bytes. The
> sandbox clang build throws up this warning, which is how I found it.
>
> -sughosh
Ah right, then that's fine.
Thinking about the common function a bit more can we slightly change
what you have?
On the fw_images struct add a const char* with the dfu_alt_str.
Instead of defining a string literal and snprintf it, use the per
board struct definition and get the string you need. So the common
case can be abstracted in a __weak function for all the boards to use
and if some platform needs something more it can replace it with it's
own function at link time.
Cheers
/Ilias
>
> >
> > Otherwise LGTM, but I'd prefer if board maintainer had a look as well
> >
> > Thanks
> > /Ilias
> >
> > > +
> > > + snprintf(buf, DFU_ALT_BUF_LEN,
> > > + "mmc 2=flash-bin raw 0 0x1B00 mmcpart 1");
> > > +
>
[PATCH] usb: dwc3: Add missing dependency on DWC3 for DWC3 gadget
There is not covered dependency on DWC3. Signed-off-by: Michal Simek --- drivers/usb/host/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 8f77412cc71b..48cbed15e104 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -19,6 +19,7 @@ if USB_XHCI_HCD config USB_XHCI_DWC3 bool "DesignWare USB3 DRD Core Support" + depends on DWC3 help Say Y or if your system has a Dual Role SuperSpeed USB controller based on the DesignWare USB3 IP Core. -- 2.35.1
Re: [PATCH 1/2] sf: dataflash: add support for "extended ID"
On Tue, Mar 22, 2022 at 4:26 PM Luca Ellero wrote: > > From: Luca Ellero > > Take as reference Linux kernel code: > drivers/mtd/devices/mtd_dataflash.c Linux commit id?
Re: [PATCH] mtd: spi: Add ISSI QSPI to lightweight SPI flash stack for spl
On Tue, Mar 15, 2022 at 3:03 PM wrote: > > From: "Lokanathan, Raaj" > > Add support for reading data/images from this ISSI QSPI flash. Look like the patch is doing quad enable for ISSI but the commit head and body seem misleading or confusing. Can you elaborate on the same? Jagan.
Re: [PATCH v4 4/8] board: Define set_dfu_alt_info() for boards with UEFI capsule update enabled
hi Ilias,
On Fri, 1 Apr 2022 at 01:05, Ilias Apalodimas
wrote:
>
> Hi Sughosh,
>
> Some nots below
>
> On Thu, Mar 31, 2022 at 06:57:46PM +0530, Sughosh Ganu wrote:
> > Currently, there are a bunch of boards which enable the UEFI capsule
> > update feature. The actual update of the firmware images is done
> > through the dfu framework which uses the dfu_alt_info environment
> > variable for getting information on the update, like device, partition
> > number/address etc. Currently, these boards define the dfu_alt_info
> > variable in the board config header, as an environment variable. With
> > this, the variable can be modified from the u-boot command line and
> > this can cause an incorrect update.
> >
> > To prevent this from happening, define the set_dfu_alt_info function
> > in the board file, and select SET_DFU_ALT_INFO for all platforms which
> > enable the capsule update feature. With the function defined, the dfu
> > framework populates the dfu_alt_info variable through the board file,
> > instead of fetching the variable from the environment, thus making the
> > update more robust.
> >
> > Signed-off-by: Sughosh Ganu
> > ---
> >
> > Changes since V3:
> > * Do not remove the existing dfu_alt_info definitions made by
> > platforms in the config files, as discussed with Masami.
> > * Squash the selection of the SET_DFU_ALT_INFO config symbol for
> > capsule update feature as part of this patch.
> >
> >
> > .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 24 +
> > .../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 24 +
> > board/emulation/common/qemu_dfu.c | 6 ++---
> > board/kontron/pitx_imx8m/pitx_imx8m.c | 24 +
> > board/kontron/sl-mx8mm/sl-mx8mm.c | 24 +
> > board/kontron/sl28/sl28.c | 25 ++
> > board/sandbox/sandbox.c | 26 +++
> > board/socionext/developerbox/developerbox.c | 26 +++
> > board/xilinx/zynq/board.c | 5 ++--
> > board/xilinx/zynqmp/zynqmp.c | 5 ++--
> > lib/efi_loader/Kconfig| 2 ++
> > 11 files changed, 184 insertions(+), 7 deletions(-)
> >
> > diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
> > b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
> > index 1c953ba195..41154ca9f3 100644
> > --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
> > +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
> > @@ -5,10 +5,12 @@
> > */
> >
> > #include
> > +#include
> > #include
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -24,6 +26,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> > @@ -231,3 +234,24 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc
> > *mmc)
> > }
> > }
> > #endif /* CONFIG_SPL_MMC_SUPPORT */
> > +
> > +#if defined(CONFIG_SET_DFU_ALT_INFO)
> > +
> > +#define DFU_ALT_BUF_LEN SZ_1K
> > +
> > +void set_dfu_alt_info(char *interface, char *devstr)
> > +{
> > + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
> > +
> > + if (!CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) &&
> > + env_get("dfu_alt_info"))
> > + return;
>
> Just add a helper function with this since we need to repeat it for every
> board. Something like 'bool needs_runtime_dfu_alt_info() '
Okay
> > +
> > + memset(buf, 0, DFU_ALT_BUF_LEN);
>
> I'd prefer sizeof(buf) instead of explicitly calling the length.
So the current boards are using this wrong. The
ALLOC_CACHE_ALIGN_BUFFER actually defines an array named __buf, and a
char *buf which points to the array. So the existing code in some
boards was zeroing out only the sizeof(char *) number of bytes. The
sandbox clang build throws up this warning, which is how I found it.
-sughosh
>
> Otherwise LGTM, but I'd prefer if board maintainer had a look as well
>
> Thanks
> /Ilias
>
> > +
> > + snprintf(buf, DFU_ALT_BUF_LEN,
> > + "mmc 2=flash-bin raw 0 0x1B00 mmcpart 1");
> > +
> > + env_set("dfu_alt_info", buf);
> > +}
> > +#endif /* CONFIG_SET_DFU_ALT_INFO */
>
> [...]
Re: [PATCH v4 07/11] bootmenu: add UEFI and disto_boot entries
Hi Kojima-san,
[...]
> + entry->title = u16_strdup(lo.label);
> + if (!entry->title) {
> + free(load_option);
> + free(entry);
We need to free bootorder as well
> + return -ENOMEM;
> + }
> + entry->command = strdup("bootefi bootmgr");
> + sprintf(entry->key, "%d", i);
> + entry->num = i;
> + entry->menu = menu;
> + entry->type = BOOTMENU_TYPE_UEFI_BOOT_OPTION;
> + entry->bootorder = bootorder[j];
> + entry->next = NULL;
> +
> + if (!iter)
> + menu->first = entry;
> + else
> + iter->next = entry;
> +
> + iter = entry;
> + i++;
> + }
> +
> + free(load_option);
> +
> + if (i == MAX_COUNT - 1)
> + break;
> + }
> +
> + free(bootorder);
> + *index = i;
> + *current = iter;
> +
> + return 1;
> +}
> +
> +static int prepare_distro_boot_entry(struct bootmenu_data *menu,
> + struct bootmenu_entry **current,
> + unsigned short int *index)
> +{
> + char *p;
> + int len;
> + char *token;
> + char *boot_targets;
> + unsigned short int i = *index;
> + struct bootmenu_entry *entry = NULL;
> + struct bootmenu_entry *iter = *current;
> +
> + /* list the distro boot "boot_targets" */
> + boot_targets = env_get("boot_targets");
> + if (!boot_targets)
> + return -ENOENT;
> +
> + len = strlen(boot_targets);
> + p = calloc(1, len + 1);
> + strlcpy(p, boot_targets, len);
> +
> + token = strtok(p, " ");
> +
> + do {
> + u16 *buf;
> + char *command;
> + int command_size;
> +
> + entry = malloc(sizeof(struct bootmenu_entry));
> + if (!entry)
> + return -ENOMEM;
> +
> + len = strlen(token);
> + buf = calloc(1, (len + 1) * sizeof(u16));
> + entry->title = buf;
> + if (!entry->title) {
> + free(entry);
> + return -ENOMEM;
> + }
> + utf8_utf16_strncpy(, token, len);
> + sprintf(entry->key, "%d", i);
> + entry->num = i;
> + entry->menu = menu;
> +
> + command_size = sizeof("run bootcmd_") + len;
> + command = calloc(1, command_size);
> + if (!command) {
> + free(entry->title);
> + free(entry);
> + return -ENOMEM;
We need to free p as well
> + }
> + snprintf(command, command_size, "run bootcmd_%s", token);
> + entry->command = command;
> + entry->type = BOOTMENU_TYPE_DISTRO_BOOT;
> entry->next = NULL;
>
> if (!iter)
> @@ -341,10 +512,59 @@ static struct bootmenu_data *bootmenu_create(int delay)
> iter->next = entry;
>
> iter = entry;
> - ++i;
> + i++;
>
> if (i == MAX_COUNT - 1)
> break;
> +
> + token = strtok(NULL, " ");
> + } while (token);
> +
> + free(p);
> + *index = i;
> + *current = iter;
> +
> + return 1;
> +}
> +
> +static struct bootmenu_data *bootmenu_create(int delay)
> +{
> + int ret;
> + unsigned short int i = 0;
> + struct bootmenu_data *menu;
> + struct bootmenu_entry *iter = NULL;
> + struct bootmenu_entry *entry;
> +
> + char *default_str;
> +
> + menu = malloc(sizeof(struct bootmenu_data));
> + if (!menu)
> + return NULL;
> +
> + menu->delay = delay;
> + menu->active = 0;
> + menu->first = NULL;
> +
> + default_str = env_get("bootmenu_default");
> + if (default_str)
> + menu->active = (int)simple_strtol(default_str, NULL, 10);
> +
> + ret = prepare_bootmenu_entry(menu, , );
> + if (ret < 0)
> + goto cleanup;
> +
> + if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) {
> + if (i < MAX_COUNT - 1) {
> + ret = prepare_uefi_bootorder_entry(menu, , );
> + if (ret < 0 && ret != -ENOENT)
> + goto cleanup;
> + }
> + }
> +
> + if (i < MAX_COUNT - 1) {
> + ret = prepare_distro_boot_entry(menu, , );
> + if (ret < 0 && ret != -ENOENT)
> + goto cleanup;
> }
>
> /* Add U-Boot console entry at the end */
> @@ -353,7 +573,12 @@ static struct bootmenu_data *bootmenu_create(int delay)
> if (!entry)
> goto
