Re: [PATCH V2 3/4] arm: mach-imx: cmd_nandbcb fix bad block handling
Hi Tim
Do you have an alternative board to test?
Michael
On Fri, May 6, 2022 at 4:41 PM Han Xu wrote:
>
> On 22/04/27 07:50AM, Michael Trimarchi wrote:
> > The badblock should be skipped properly in reading and writing.
> > Fix the logic. The bcb struct is written, skipping the bad block,
> > so we need to read using the same logic. This was tested create
> > bad block in the area and then flash it and read it back.
> >
> > Cc: Han Xu
> > Cc: Fabio Estevam
> > Signed-off-by: Michael Trimarchi
>
> Acked-by: Han Xu
>
> > ---
> > V1->V2:
> > - Adjust the commit message
> > - Add Cc Han Xu and Fabio
> > - move out from RFC
> > ---
> > arch/arm/mach-imx/cmd_nandbcb.c | 21 +++--
> > 1 file changed, 7 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/cmd_nandbcb.c
> > b/arch/arm/mach-imx/cmd_nandbcb.c
> > index f119e9f88d..c54f52b343 100644
> > --- a/arch/arm/mach-imx/cmd_nandbcb.c
> > +++ b/arch/arm/mach-imx/cmd_nandbcb.c
> > @@ -506,10 +506,6 @@ static int read_fcb(struct boot_config *boot_cfg,
> > struct fcb_block *fcb,
> > int ret = 0;
> >
> > mtd = boot_cfg->mtd;
> > - if (mtd_block_isbad(mtd, off)) {
> > - printf("Block %d is bad, skipped\n",
> > (int)CONV_TO_BLOCKS(off));
> > - return 1;
> > - }
> >
> > fcb_raw_page = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
> > if (!fcb_raw_page) {
> > @@ -530,7 +526,7 @@ static int read_fcb(struct boot_config *boot_cfg,
> > struct fcb_block *fcb,
> > else if (plat_config.misc_flags & FCB_ENCODE_BCH_40b)
> > mxs_nand_mode_fcb_40bit(mtd);
> >
> > - ret = nand_read(mtd, off, &size, (u_char *)fcb);
> > + ret = nand_read_skip_bad(mtd, off, &size, NULL, mtd->size,
> > (u_char *)fcb);
> >
> > /* switch BCH back */
> > mxs_nand_mode_normal(mtd);
> > @@ -617,6 +613,7 @@ static int write_fcb(struct boot_config *boot_cfg,
> > struct fcb_block *fcb)
> > for (i = 0; i < g_boot_search_count; i++) {
> > if (mtd_block_isbad(mtd, off)) {
> > printf("Block %d is bad, skipped\n", i);
> > + off += mtd->erasesize;
> > continue;
> > }
> >
> > @@ -676,20 +673,15 @@ static int read_dbbt(struct boot_config *boot_cfg,
> > struct dbbt_block *dbbt,
> > void *dbbt_data_page, loff_t off)
> > {
> > size_t size;
> > + size_t actual_size;
> > struct mtd_info *mtd;
> > loff_t to;
> > int ret;
> >
> > mtd = boot_cfg->mtd;
> >
> > - if (mtd_block_isbad(mtd, off)) {
> > - printf("Block %d is bad, skipped\n",
> > -(int)CONV_TO_BLOCKS(off));
> > - return 1;
> > - }
> > -
> > size = sizeof(struct dbbt_block);
> > - ret = nand_read(mtd, off, &size, (u_char *)dbbt);
> > + ret = nand_read_skip_bad(mtd, off, &size, &actual_size, mtd->size,
> > (u_char *)dbbt);
> > printf("NAND DBBT read from 0x%llx offset 0x%zx read: %s\n",
> > off, size, ret ? "ERROR" : "OK");
> > if (ret)
> > @@ -697,9 +689,9 @@ static int read_dbbt(struct boot_config *boot_cfg,
> > struct dbbt_block *dbbt,
> >
> > /* dbbtpages == 0 if no bad blocks */
> > if (dbbt->dbbtpages > 0) {
> > - to = off + 4 * mtd->writesize;
> > + to = off + 4 * mtd->writesize + actual_size - size;
> > size = mtd->writesize;
> > - ret = nand_read(mtd, to, &size, dbbt_data_page);
> > + ret = nand_read_skip_bad(mtd, to, &size, NULL, mtd->size,
> > dbbt_data_page);
> > printf("DBBT data read from 0x%llx offset 0x%zx read: %s\n",
> > to, size, ret ? "ERROR" : "OK");
> >
> > @@ -729,6 +721,7 @@ static int write_dbbt(struct boot_config *boot_cfg,
> > struct dbbt_block *dbbt,
> > if (mtd_block_isbad(mtd, off)) {
> > printf("Block %d is bad, skipped\n",
> > (int)(i + CONV_TO_BLOCKS(off)));
> > + off += mtd->erasesize;
> > continue;
> > }
> >
> > --
> > 2.25.1
> >
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH] kontron-sl-mx8mm: Select the CONFIG_CMD_UNZIP option
Am 11.05.22 um 01:06 schrieb Fabio Estevam: > From: Fabio Estevam > > Select the CMD_UNZIP option so that the 'gzwrite' command > can be used to flash wic.gz image into the eMMC. > > Signed-off-by: Fabio Estevam Reviewed-by: Frieder Schrempf > --- > configs/kontron-sl-mx8mm_defconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/configs/kontron-sl-mx8mm_defconfig > b/configs/kontron-sl-mx8mm_defconfig > index 1375c78a8c44..f07b7890a0ce 100644 > --- a/configs/kontron-sl-mx8mm_defconfig > +++ b/configs/kontron-sl-mx8mm_defconfig > @@ -37,7 +37,7 @@ CONFIG_SPL_WATCHDOG=y > CONFIG_SPL_ATF=y > CONFIG_CMD_NVEDIT_EFI=y > # CONFIG_CMD_LZMADEC is not set > -# CONFIG_CMD_UNZIP is not set > +CONFIG_CMD_UNZIP=y > CONFIG_CMD_CLK=y > CONFIG_CMD_DFU=y > CONFIG_CMD_FUSE=y
[PATCH v2 1/2] common: spl: spl_spi: add support for dynamic override of sf bus
Currently the SPI flash to load from is defined through the compile
time config CONFIG_SF_DEFAULT_BUS and CONFIG_SF_DEFAULT_CS, this
prevents the loading of binaries from different SPI flash using the
same build.E.g. supporting QSPI flash boot and OSPI flash boot
on J721E platform is not possible due to this limitation.
This commit adds lookup functions spl_spi_boot_bus()
and spl_spi_boot_cs for identifying the flash device based on the
selected boot device, when not overridden the lookup functions are
weakly defined in common/spl/spl_spi.c.
Signed-off-by: Vaishnav Achath
---
common/spl/spl_spi.c | 16 +---
include/spl.h| 16
2 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index cf3f7ef4c0..3eef2f8d68 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c
@@ -71,6 +71,16 @@ unsigned int __weak spl_spi_get_uboot_offs(struct spi_flash
*flash)
return CONFIG_SYS_SPI_U_BOOT_OFFS;
}
+u32 __weak spl_spi_boot_bus(void)
+{
+ return CONFIG_SF_DEFAULT_BUS;
+}
+
+u32 __weak spl_spi_boot_cs(void)
+{
+ return CONFIG_SF_DEFAULT_CS;
+}
+
/*
* The main entry for SPI booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
@@ -83,15 +93,15 @@ static int spl_spi_load_image(struct spl_image_info
*spl_image,
unsigned int payload_offs;
struct spi_flash *flash;
struct image_header *header;
+ unsigned int sf_bus = spl_spi_boot_bus();
+ unsigned int sf_cs = spl_spi_boot_cs();
/*
* Load U-Boot image from SPI flash into RAM
* In DM mode: defaults speed and mode will be
* taken from DT when available
*/
-
- flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
- CONFIG_SF_DEFAULT_CS,
+ flash = spi_flash_probe(sf_bus, sf_cs,
CONFIG_SF_DEFAULT_SPEED,
CONFIG_SF_DEFAULT_MODE);
if (!flash) {
diff --git a/include/spl.h b/include/spl.h
index 6134aba857..438f2fdf7c 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -361,6 +361,22 @@ int spl_load_imx_container(struct spl_image_info
*spl_image,
void preloader_console_init(void);
u32 spl_boot_device(void);
+/**
+ * spl_spi_boot_bus() - Lookup function for the SPI boot bus source.
+ *
+ * This function returns the SF bus to load from.
+ * If not overridden, it is weakly defined in common/spl/spl_spi.c.
+ */
+u32 spl_spi_boot_bus(void);
+
+/**
+ * spl_spi_boot_cs() - Lookup function for the SPI boot CS source.
+ *
+ * This function returns the SF CS to load from.
+ * If not overridden, it is weakly defined in common/spl/spl_spi.c.
+ */
+u32 spl_spi_boot_cs(void);
+
/**
* spl_mmc_boot_mode() - Lookup function for the mode of an MMC boot source.
* @boot_device: ID of the device which the MMC driver wants to read
--
2.17.1
[PATCH v2 2/2] arm: k3: j721e: add dynamic sf bus override support for j721e
implement overrides for spl_spi_boot_bus() and spl_spi_boot_cs()
lookup functions according to bootmode selection, so as to support
both QSPI and OSPI boot using the same build.
Signed-off-by: Vaishnav Achath
---
arch/arm/mach-k3/j721e_init.c | 17 +
arch/arm/mach-k3/sysfw-loader.c | 4 ++--
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index f503f15f19..82391b5cf8 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -355,6 +355,23 @@ static u32 __get_primary_bootmedia(u32 main_devstat, u32
wkup_devstat)
return bootmode;
}
+u32 spl_spi_boot_bus(void)
+{
+ u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
+ u32 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+ u32 bootmode = ((wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+ WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT) |
+ ((main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
BOOT_MODE_B_SHIFT);
+
+ return (bootmode == BOOT_DEVICE_QSPI) ? 1 : 0;
+}
+
+/* both OSPI and QSPI flash are in CS0 */
+u32 spl_spi_boot_cs(void)
+{
+ return 0;
+}
+
u32 spl_boot_device(void)
{
u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 5e48c36ccd..8ff36759c1 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -324,9 +324,9 @@ static void *k3_sysfw_get_spi_addr(void)
struct udevice *dev;
fdt_addr_t addr;
int ret;
+ unsigned int sf_bus = spl_spi_boot_bus();
- ret = uclass_find_device_by_seq(UCLASS_SPI, CONFIG_SF_DEFAULT_BUS,
- &dev);
+ ret = uclass_find_device_by_seq(UCLASS_SPI, sf_bus, &dev);
if (ret)
return NULL;
--
2.17.1
[PATCH v2 0/2] Add support for dynamic overriding of default SF bus
Currently the SPI flash to load from is defined through the compile time config CONFIG_SF_DEFAULT_BUS and CONFIG_SF_DEFAULT_CS, this prevents the loading of binaries from different SPI flash using the same build. This series adds support for choosing the flash device based on the selected boot device thus allowing platforms to override the SF_BUS and SF_CS to load from the desired flash. Changes tested on J721E for OSPI and QSPI boot. V1->V2: * drop unnecessary Kconfig option for SF bus override, suggested by Heiko Schocher. Vaishnav Achath (2): common: spl: spl_spi: add support for dynamic override of sf bus arm: k3: j721e: add dynamic sf bus override support for j721e arch/arm/mach-k3/j721e_init.c | 17 + arch/arm/mach-k3/sysfw-loader.c | 4 ++-- common/spl/spl_spi.c| 16 +--- include/spl.h | 16 4 files changed, 48 insertions(+), 5 deletions(-) -- 2.17.1
Re: [EXTERNAL] Re: [PATCH 1/2] common: spl: spl_spi: add support for dynamic detection of sf bus
Hi Heiko, On 09/05/22 12:49, Heiko Schocher wrote: Hello Achat, On 09.05.22 08:43, Vaishnav Achath wrote: Currently the SPI flash to load from is defined through the compile time config CONFIG_SF_DEFAULT_BUS and CONFIG_SF_DEFAULT_CS, this prevents the loading of binaries from different SPI flash using the same build.E.g. supporting QSPI flash boot and OSPI flash boot on J721E platform is not possible due to this limitation. This commit adds lookup functions spl_spi_boot_bus() and spl_spi_boot_cs for identifying the flash device based on the selected boot devic, when not overridden the lookup functions are weakly defined in common/spl/spl_spi.c. Signed-off-by: Vaishnav Achath --- common/spl/Kconfig | 4 common/spl/spl_spi.c | 19 +-- include/spl.h| 18 ++ 3 files changed, 39 insertions(+), 2 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index ac61b25a06..b13492b6a2 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1103,6 +1103,10 @@ config SPL_SPI_FLASH_SUPPORT lines). This enables the drivers in drivers/mtd/spi as part of an SPL build. This normally requires SPL_SPI. +config SPL_DYNAMIC_SF_BUS_DETECT + bool "Detect which SPI flash to load from" + depends on SPL_SPI_FLASH_SUPPORT Do you really need here a new Kconfig option? I think you can drop it... adding the Kconfig option is not necessary, will drop it in V2. Thank you for the feedback. bye, Heiko -- Thanks and Regards, Vaishnav
Re: [PATCH] net: fix phy_string_for_interface
On 11.05.22 00:49, Tim Harvey wrote:
commit ffb0f6f488b9 ("treewide: Rename PHY_INTERFACE_MODE_NONE to
PHY_INTERFACE_MODE_NA") broke the phy_string_for_interface function.
Fix it.
Fixes ffb0f6f488b9 ("treewide: Rename PHY_INTERFACE_MODE_NONE to
PHY_INTERFACE_MODE_NA")
Signed-off-by: Tim Harvey
Cc: Marek Behún
Cc: Stefan Roese
Cc: Ramon Fried
Cc: Vladimir Oltean
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
include/phy_interface.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/phy_interface.h b/include/phy_interface.h
index ce3b5004ec22..fed3357b9a26 100644
--- a/include/phy_interface.h
+++ b/include/phy_interface.h
@@ -85,7 +85,7 @@ static const char * const backplane_mode_strings[] = {
static inline const char *phy_string_for_interface(phy_interface_t i)
{
/* Default to unknown */
- if (i > PHY_INTERFACE_MODE_NA)
+ if (i >= PHY_INTERFACE_MODE_MAX)
i = PHY_INTERFACE_MODE_NA;
return phy_interface_strings[i];
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 1/1] btrfs: simplify lookup_data_extent()
On 5/11/22 01:13, Heinrich Schuchardt wrote:
After returning if ret <= 0 we know that ret > 0. No need to check it.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Anand Jain
---
fs/btrfs/inode.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index d00b515333..0173d30cd8 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -546,15 +546,12 @@ static int lookup_data_extent(struct btrfs_root *root,
struct btrfs_path *path,
/* Error or we're already at the file extent */
if (ret <= 0)
return ret;
- if (ret > 0) {
- /* Check previous file extent */
- ret = btrfs_previous_item(root, path, ino,
- BTRFS_EXTENT_DATA_KEY);
- if (ret < 0)
- return ret;
- if (ret > 0)
- goto check_next;
- }
+ /* Check previous file extent */
+ ret = btrfs_previous_item(root, path, ino, BTRFS_EXTENT_DATA_KEY);
+ if (ret < 0)
+ return ret;
+ if (ret > 0)
+ goto check_next;
/* Now the key.offset must be smaller than @file_offset */
btrfs_item_key_to_cpu(path->nodes[0], &key, path->slots[0]);
if (key.objectid != ino ||
runtime configuration of env_addr
Hi All, I was wondering if there is a way to override the gd->env_addr that is initialized in env_flash_init() for flash based environment. As I see, env_addr depends on the env_ptr which is set to compile time value of CONFIG_ENV_ADDR. I was thinking of doing it in board_early_init_f(). But, as I understand, the env_init() will override it. Thanks, -h
Re: [PULL] u-boot-stm32/master v2022.07 = u-boot-stm32-20220510
On Tue, May 10, 2022 at 04:47:25PM +0200, Patrice CHOTARD wrote: > Hi Tom > > Please pull the STM32 related patches for u-boot/master, v2022.07: > u-boot-stm32-20220510 > > CI status: > https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/11978 > > Thanks > Patrice > > The following changes since commit f08ed34371c54244421eac8ffb4c77559c5ea013: > > Prepare v2022.07-rc2 (2022-05-09 12:49:31 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-stm.git > tags/u-boot-stm32-20220510 > > for you to fetch changes up to e198d4fe7c34cbb97d7d3cbf31d3a78a5ecc43f7: > > doc: Add documentation for STM32 MCUs (2022-05-10 13:56:12 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH] gpio: sunxi: Fix build with CONFIG_SPL_SERIAL=n
This driver uses simple_strtol(), so it needs SPL_STRTO. Before commit
88ca8e26958b6 ("disk: Add an option for partitions in SPL"), SPL_STRTO
was always selected indirectly. Now it is not, so select it here.
Signed-off-by: Samuel Holland
---
drivers/gpio/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 89068c7800..b955543e97 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -347,6 +347,7 @@ config SANDBOX_GPIO_COUNT
config SUNXI_GPIO
bool "Allwinner GPIO driver"
depends on ARCH_SUNXI
+ select SPL_STRTO if SPL
help
Support the GPIO device in Allwinner SoCs.
--
2.35.1
Re: [PATCH 0/7] clk: sunxi: Out-of-bounds access fix and driver cleanup
On Mon, 9 May 2022 00:29:30 -0500 Samuel Holland wrote: Hi Samuel, > This series fixes an issue with out-of-bounds access to the gate array > (patches 1-2), uses the rearranged array size information to remove a > bunch of duplicate code (patches 3-4), and then simplifies how the reset > driver is bound (patches 5-7). > > The original motivation for these changes was adding a driver for the > legacy A31/A23/A33 PRCM binding (which I will send separately), and > trying to use OF_PLATDATA in SPL (which did not work out). But I think > at least some of the cleanup is worth applying on its own. > > Patch 4 is generally the same change I made between v1 and v2 of the > pinctrl series, using some #ifdefs to share a U_BOOT_DRIVER. It's not > quite as clean as the pinctrl case, because here the SoC-specific parts > are in different files, so all of the CCU descriptors have to be global. so I skimmed over the series and quite like it: the negative diffstat speaks for itself ;-) I need to go over each individual patch with more scrutiny (unless someone beats me to it), but assuming no issues, I am planning on taking this for the next merge window. You mention out-of-bounds accesses: did you actually encounter one with the old or new DTs, that would need fixing now? Cheers, Andre > Samuel Holland (7): > clk: sunxi: Store the array sizes in the CCU descriptor > clk: sunxi: Prevent out-of-bounds gate array access > reset: sunxi: Get the reset count from the CCU descriptor > clk: sunxi: Use a single driver for all variants > clk: sunxi: Convert driver private data to platform data > reset: sunxi: Convert driver private data to platform data > reset: sunxi: Reuse the platform data from the clock driver > > drivers/clk/sunxi/clk_a10.c | 27 +- > drivers/clk/sunxi/clk_a10s.c | 27 +- > drivers/clk/sunxi/clk_a23.c | 27 +- > drivers/clk/sunxi/clk_a31.c | 25 + > drivers/clk/sunxi/clk_a31_r.c | 29 +- > drivers/clk/sunxi/clk_a64.c | 25 + > drivers/clk/sunxi/clk_a80.c | 36 ++-- > drivers/clk/sunxi/clk_a83t.c | 25 + > drivers/clk/sunxi/clk_h3.c| 27 +- > drivers/clk/sunxi/clk_h6.c| 25 + > drivers/clk/sunxi/clk_h616.c | 25 + > drivers/clk/sunxi/clk_h6_r.c | 27 +- > drivers/clk/sunxi/clk_r40.c | 25 + > drivers/clk/sunxi/clk_sunxi.c | 168 ++ > drivers/clk/sunxi/clk_v3s.c | 27 +- > drivers/reset/reset-sunxi.c | 55 ++- > include/clk/sunxi.h | 21 + > 17 files changed, 208 insertions(+), 413 deletions(-) >
[PATCH] kontron-sl-mx8mm: Select the CONFIG_CMD_UNZIP option
From: Fabio Estevam Select the CMD_UNZIP option so that the 'gzwrite' command can be used to flash wic.gz image into the eMMC. Signed-off-by: Fabio Estevam --- configs/kontron-sl-mx8mm_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 1375c78a8c44..f07b7890a0ce 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -37,7 +37,7 @@ CONFIG_SPL_WATCHDOG=y CONFIG_SPL_ATF=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_LZMADEC is not set -# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_UNZIP=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FUSE=y -- 2.25.1
[PATCH] net: fix phy_string_for_interface
commit ffb0f6f488b9 ("treewide: Rename PHY_INTERFACE_MODE_NONE to
PHY_INTERFACE_MODE_NA") broke the phy_string_for_interface function.
Fix it.
Fixes ffb0f6f488b9 ("treewide: Rename PHY_INTERFACE_MODE_NONE to
PHY_INTERFACE_MODE_NA")
Signed-off-by: Tim Harvey
Cc: Marek Behún
Cc: Stefan Roese
Cc: Ramon Fried
Cc: Vladimir Oltean
---
include/phy_interface.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/phy_interface.h b/include/phy_interface.h
index ce3b5004ec22..fed3357b9a26 100644
--- a/include/phy_interface.h
+++ b/include/phy_interface.h
@@ -85,7 +85,7 @@ static const char * const backplane_mode_strings[] = {
static inline const char *phy_string_for_interface(phy_interface_t i)
{
/* Default to unknown */
- if (i > PHY_INTERFACE_MODE_NA)
+ if (i >= PHY_INTERFACE_MODE_MAX)
i = PHY_INTERFACE_MODE_NA;
return phy_interface_strings[i];
--
2.17.1
Re: [PATCH 1/1] btrfs: simplify lookup_data_extent()
On 2022/5/11 03:43, Heinrich Schuchardt wrote:
After returning if ret <= 0 we know that ret > 0. No need to check it.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Qu Wenruo
Thanks,
Qu
---
fs/btrfs/inode.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index d00b515333..0173d30cd8 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -546,15 +546,12 @@ static int lookup_data_extent(struct btrfs_root *root,
struct btrfs_path *path,
/* Error or we're already at the file extent */
if (ret <= 0)
return ret;
- if (ret > 0) {
- /* Check previous file extent */
- ret = btrfs_previous_item(root, path, ino,
- BTRFS_EXTENT_DATA_KEY);
- if (ret < 0)
- return ret;
- if (ret > 0)
- goto check_next;
- }
+ /* Check previous file extent */
+ ret = btrfs_previous_item(root, path, ino, BTRFS_EXTENT_DATA_KEY);
+ if (ret < 0)
+ return ret;
+ if (ret > 0)
+ goto check_next;
/* Now the key.offset must be smaller than @file_offset */
btrfs_item_key_to_cpu(path->nodes[0], &key, path->slots[0]);
if (key.objectid != ino ||
Re: [PATCH] ls1028a: hdp: Add config support for HDP firmware loading
Am 2022-05-10 19:47, schrieb Vladimir Oltean: On Tue, May 10, 2022 at 04:18:32PM +0200, Michael Walle wrote: > From: Alison Wang > > This patch adds config support for HDP firmware loading on LS1028A. FWIW, I really don't like this as this is just for a downstream kernel. This => what? I only see a config option. I searched the list and the source code for CONFIG_VIDEO_LS_HDP_LOAD and I don't see any user... You are right, I didn't actually notice that. The whole loading thing [1] is missing. For the upstream kernel the firmware should be loaded by the kernel itself. In principle I agree. But unfortunately, there is no development there. (I have some half baked patches though and can confirm, that firmware loading is working from linux). Instead of this I'd like to see some work to support the DP PHY in upstream linux as this is really the last missing piece to get graphics working. It is? What did I miss? I don't know? etnaviv is working [2 and more], mesa will be working soon [3]. mali-dp500 should have been working all the time. So only the output path is missing. If you are interested, this [4] is my take on the support, which is actually working. But I haven't found any time to look at it again. And I'm missing any documentation, so most information was found out by educated guesses and comparing to the downstream driver. I'd greatly appreciate any help ;) [1] https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot/tree/drivers/video/nxp/layerscape?h=integration [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/etnaviv?id=12495f4eb298963565e0bdd37d8096ab1136d89f [3] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255 [4] https://github.com/mwalle/linux/tree/feature-cdns-phy -michael
Re: [PATCH RFC v2 00/11] Integration of sysfw, tispl and tiboot3
On Fri, May 06, 2022 at 10:07:48AM +0530, Neha Malcom Francis wrote: > Devices that belong to the K3 architecture require SYSFW which is a FIT > image consisting of a signed system firmware image and board config > binaries. > > Board config binaries are needed to bring up SYSFW during U-Boot SPL > startup. The board config data is given in YAML as input. These board > configs contain board-specific information such as resource management, > power management and security. > > The following series intends to plumb the system firmware generation > into U-Boot using binman for packaging. Thus it will eliminate the need > for additional custom repositories for SYSFW generation and also moves t > owards the community standard build flow. We use binman to package > tiboot3.bin and sysfw.itb images. > > These images also require x509 certificates which are created using the > etype x509-cert. > > The series also plumbs the generation of tispl.bin into the build flow. > This image is required for loading u-boot in K3 devices. The image is > packaged using ATF, OPTEE and DM (Device Manager). > > Please note that the following series has implemented the above for > J721E general purpose board. The board configs and device trees added > are specific to J721E GP devices. > > Also note the introduction of three new etypes: ti-sysfw, ti-dm and > x509-cert. > > On running CI tests on Github, errors were produced during world builds > of keystone2_keystone3 and siemens (I0T2050 which is based on AM65x). > This patch series is intended for only J721E and future work is to expand > to the remaining K3 devices as well. The errors that come are mainly due > to the boards other than J721E trying to generate tispl.bin. > > v2: > - Added etype x509-cert for creating x509 Texas Instruments certificate > binary > - Added packaging of tiboot3.bin > - Packaging of tiboot3.bin and sysfw.itb using new etype x509 > - sysfw --> ti-sysfw > - Reformatted and re-arranged patches > - Removed k3_fit_atf.sh and k3_gen_x509_cert.sh as their functionality > is provided by binman now > > Neha Malcom Francis (11): > j721e_evm: schema: yaml: Add general schema and J721E board config > files > ti: tools: config: Add board config class to generate config binaries > ti: etype: sysfw: Add entry type for sysfw > ti: etype: dm: Add entry type for TI DM > ti: etype: x509: Add etype for x509 certificate for K3 devices > ti: sysfw: Add support for packaging sysfw.itb > ti: tiboot3.bin: Remove tiboot3.bin target from makefile > ti: tispl.bin: Removed script that packages tispl.bin > ti: x509: Remove shell script used for signing > ti: dtsi: j721e: Use binman to package sysfw.itb and tiboot3.bin > ti: dtsi: j721e: Use binman to package tispl.bin > > Makefile |2 + > arch/arm/dts/k3-j721e-a72-binman.dtsi | 86 + > .../k3-j721e-common-proc-board-u-boot.dtsi|1 + > arch/arm/dts/k3-j721e-r5-binman.dtsi | 88 + > .../k3-j721e-r5-common-proc-board-u-boot.dtsi |1 + > arch/arm/mach-k3/config.mk| 64 +- > board/ti/common/schema.yaml | 355 ++ > board/ti/j721e/Kconfig|2 + > board/ti/j721e/config.yaml| 3162 + > scripts/Makefile.spl |4 - > test/py/requirements.txt |1 + > tools/binman/entries.rst | 36 + > tools/binman/etype/ti_dm.py | 23 + > tools/binman/etype/ti_sysfw.py| 28 + > tools/binman/etype/x509_cert.py | 248 ++ > tools/binman/ftest.py | 21 + > tools/binman/test/225_ti_dm.dts | 13 + > tools/binman/test/232_ti_sysfw.dts| 13 + > tools/binman/test/232_x509_cert.dts | 18 + > tools/k3_fit_atf.sh | 123 - > tools/k3_gen_x509_cert.sh | 252 -- > tools/tibcfg_gen.py | 114 + > 22 files changed, 4227 insertions(+), 428 deletions(-) > create mode 100644 arch/arm/dts/k3-j721e-a72-binman.dtsi > create mode 100644 arch/arm/dts/k3-j721e-r5-binman.dtsi > create mode 100644 board/ti/common/schema.yaml > create mode 100644 board/ti/j721e/config.yaml > create mode 100644 tools/binman/etype/ti_dm.py > create mode 100644 tools/binman/etype/ti_sysfw.py > create mode 100644 tools/binman/etype/x509_cert.py > create mode 100644 tools/binman/test/225_ti_dm.dts > create mode 100644 tools/binman/test/232_ti_sysfw.dts > create mode 100644 tools/binman/test/232_x509_cert.dts > delete mode 100755 tools/k3_fit_atf.sh > delete mode 100755 tools/k3_gen_x509_cert.sh > create mode 100644 tools/tibcfg_gen.py Adding the other binman maintainer.. -- Tom signature.asc Description: PGP signature
[PATCH 1/1] fs/squashfs: fix sqfs_read_sblk()
Setting sblk = NULL has no effect on the caller.
We want to set *sblk = NULL if an error occurrs to avoid usage after free.
Signed-off-by: Heinrich Schuchardt
---
fs/squashfs/sqfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
index b07c41e911..18cd386abb 100644
--- a/fs/squashfs/sqfs.c
+++ b/fs/squashfs/sqfs.c
@@ -49,7 +49,7 @@ static int sqfs_read_sblk(struct squashfs_super_block **sblk)
if (sqfs_disk_read(0, 1, *sblk) != 1) {
free(*sblk);
- sblk = NULL;
+ *sblk = NULL;
return -EINVAL;
}
--
2.34.1
[PATCH 1/1] btrfs: simplify lookup_data_extent()
After returning if ret <= 0 we know that ret > 0. No need to check it.
Signed-off-by: Heinrich Schuchardt
---
fs/btrfs/inode.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index d00b515333..0173d30cd8 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -546,15 +546,12 @@ static int lookup_data_extent(struct btrfs_root *root,
struct btrfs_path *path,
/* Error or we're already at the file extent */
if (ret <= 0)
return ret;
- if (ret > 0) {
- /* Check previous file extent */
- ret = btrfs_previous_item(root, path, ino,
- BTRFS_EXTENT_DATA_KEY);
- if (ret < 0)
- return ret;
- if (ret > 0)
- goto check_next;
- }
+ /* Check previous file extent */
+ ret = btrfs_previous_item(root, path, ino, BTRFS_EXTENT_DATA_KEY);
+ if (ret < 0)
+ return ret;
+ if (ret > 0)
+ goto check_next;
/* Now the key.offset must be smaller than @file_offset */
btrfs_item_key_to_cpu(path->nodes[0], &key, path->slots[0]);
if (key.objectid != ino ||
--
2.34.1
[PATCH] zlib: Port fix for CVE-2018-25032 to U-Boot
While our copy of zlib is missing upstream commit 263b1a05b04e ("Allow
deflatePrime() to insert bits in the middle of a stream.") we do have
Z_FIXED support, and so the majority of the code changes in 5c44459c3b28
("Fix a bug that can crash deflate on some input when using Z_FIXED.")
apply here directly and cleanly. As this has been assigned a CVE, lets
go and apply these changes.
Link:
https://github.com/madler/zlib/commit/5c44459c3b28a9bd3283aaceab7c615f8020c531
Reported-by: "Gan, Yau Wai"
Signed-off-by: Tom Rini
---
lib/zlib/deflate.c | 64 +++---
lib/zlib/deflate.h | 25 --
lib/zlib/trees.c | 50 ++--
3 files changed, 74 insertions(+), 65 deletions(-)
diff --git a/lib/zlib/deflate.c b/lib/zlib/deflate.c
index 63473359e456..4549f4dc12a0 100644
--- a/lib/zlib/deflate.c
+++ b/lib/zlib/deflate.c
@@ -223,11 +223,6 @@ int ZEXPORT deflateInit2_(strm, level, method, windowBits,
memLevel, strategy,
int wrap = 1;
static const char my_version[] = ZLIB_VERSION;
-ushf *overlay;
-/* We overlay pending_buf and d_buf+l_buf. This works since the average
- * output size for (length,distance) codes is <= 24 bits.
- */
-
if (version == Z_NULL || version[0] != my_version[0] ||
stream_size != sizeof(z_stream)) {
return Z_VERSION_ERROR;
@@ -287,9 +282,47 @@ int ZEXPORT deflateInit2_(strm, level, method, windowBits,
memLevel, strategy,
s->lit_bufsize = 1 << (memLevel + 6); /* 16K elements by default */
-overlay = (ushf *) ZALLOC(strm, s->lit_bufsize, sizeof(ush)+2);
-s->pending_buf = (uchf *) overlay;
-s->pending_buf_size = (ulg)s->lit_bufsize * (sizeof(ush)+2L);
+/* We overlay pending_buf and sym_buf. This works since the average size
+ * for length/distance pairs over any compressed block is assured to be 31
+ * bits or less.
+ *
+ * Analysis: The longest fixed codes are a length code of 8 bits plus 5
+ * extra bits, for lengths 131 to 257. The longest fixed distance codes are
+ * 5 bits plus 13 extra bits, for distances 16385 to 32768. The longest
+ * possible fixed-codes length/distance pair is then 31 bits total.
+ *
+ * sym_buf starts one-fourth of the way into pending_buf. So there are
+ * three bytes in sym_buf for every four bytes in pending_buf. Each symbol
+ * in sym_buf is three bytes -- two for the distance and one for the
+ * literal/length. As each symbol is consumed, the pointer to the next
+ * sym_buf value to read moves forward three bytes. From that symbol, up to
+ * 31 bits are written to pending_buf. The closest the written pending_buf
+ * bits gets to the next sym_buf symbol to read is just before the last
+ * code is written. At that time, 31*(n-2) bits have been written, just
+ * after 24*(n-2) bits have been consumed from sym_buf. sym_buf starts at
+ * 8*n bits into pending_buf. (Note that the symbol buffer fills when n-1
+ * symbols are written.) The closest the writing gets to what is unread is
+ * then n+14 bits. Here n is lit_bufsize, which is 16384 by default, and
+ * can range from 128 to 32768.
+ *
+ * Therefore, at a minimum, there are 142 bits of space between what is
+ * written and what is read in the overlain buffers, so the symbols cannot
+ * be overwritten by the compressed data. That space is actually 139 bits,
+ * due to the three-bit fixed-code block header.
+ *
+ * That covers the case where either Z_FIXED is specified, forcing fixed
+ * codes, or when the use of fixed codes is chosen, because that choice
+ * results in a smaller compressed block than dynamic codes. That latter
+ * condition then assures that the above analysis also covers all dynamic
+ * blocks. A dynamic-code block will only be chosen to be emitted if it has
+ * fewer bits than a fixed-code block would for the same set of symbols.
+ * Therefore its average symbol length is assured to be less than 31. So
+ * the compressed data for a dynamic block also cannot overwrite the
+ * symbols from which it is being constructed.
+ */
+
+s->pending_buf = (uchf *) ZALLOC(strm, s->lit_bufsize, 4);
+s->pending_buf_size = (ulg)s->lit_bufsize * 4;
if (s->window == Z_NULL || s->prev == Z_NULL || s->head == Z_NULL ||
s->pending_buf == Z_NULL) {
@@ -298,8 +331,12 @@ int ZEXPORT deflateInit2_(strm, level, method, windowBits,
memLevel, strategy,
deflateEnd (strm);
return Z_MEM_ERROR;
}
-s->d_buf = overlay + s->lit_bufsize/sizeof(ush);
-s->l_buf = s->pending_buf + (1+sizeof(ush))*s->lit_bufsize;
+s->sym_buf = s->pending_buf + s->lit_bufsize;
+s->sym_end = (s->lit_bufsize - 1) * 3;
+/* We avoid equality with lit_bufsize*3 because of wraparound at 64K
+ * on 16 bit machines and because stored blocks are restricted to
+ * 64K-1 bytes.
+ */
Re: [PATCH] ls1028a: hdp: Add config support for HDP firmware loading
On Tue, May 10, 2022 at 04:18:32PM +0200, Michael Walle wrote: > > From: Alison Wang > > > > This patch adds config support for HDP firmware loading on LS1028A. > > FWIW, I really don't like this as this is just for a downstream kernel. This => what? I only see a config option. I searched the list and the source code for CONFIG_VIDEO_LS_HDP_LOAD and I don't see any user... > For the upstream kernel the firmware should be loaded by the kernel itself. In principle I agree. > But unfortunately, there is no development there. (I have some half > baked patches though and can confirm, that firmware loading is working > from linux). Instead of this I'd like to see some work to support the > DP PHY in upstream linux as this is really the last missing piece to > get graphics working. It is? What did I miss? > Now this is purely board related code, so it is probably fine. But in the > past the handling of purly downstream stuff was removed from upstream > u-boot anyway in favor of the upstream method. i.e. fixup of the > ls1028a-gpu node. > > -michael
Re: [PATCH] dm: core: Provide fallbacks for ofnode_conf_read_...
On 3/28/22 6:14 PM, Sean Anderson wrote:
> Because fdt_get_config_str et al. were moved/renamed to
> ofnode_conf_read_str, they now depend on CONFIG_DM as well as
> CONFIG_OF_CONTROL. Add some fallback implementations, preventing a
> linker error when CONFIG_SPL_OF_CONTROL and CONFIG_SPL_ENV_IS_IN_MMC are
> enabled and CONFIG_SPL_DM is disabled.
>
> Fixes: 7de8bd03c3 ("treewide: fdt: Move fdt_get_config_... to
> ofnode_conf_read...")
> Signed-off-by: Sean Anderson
> ---
>
> include/dm/ofnode.h | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
> index 744dffe0a2..434696b2b6 100644
> --- a/include/dm/ofnode.h
> +++ b/include/dm/ofnode.h
> @@ -1180,6 +1180,7 @@ int ofnode_write_string(ofnode node, const char
> *propname, const char *value);
> */
> int ofnode_set_enabled(ofnode node, bool value);
>
> +#if CONFIG_IS_ENABLED(DM)
> /**
> * ofnode_conf_read_bool() - Read a boolean value from the U-Boot config
> *
> @@ -1216,5 +1217,21 @@ int ofnode_conf_read_int(const char *prop_name, int
> default_val);
> * Return: string value, if found, or NULL if not
> */
> const char *ofnode_conf_read_str(const char *prop_name);
> +#else /* CONFIG_DM */
> +static inline bool ofnode_conf_read_bool(const char *prop_name)
> +{
> + return false;
> +}
> +
> +static inline int ofnode_conf_read_int(const char *prop_name, int
> default_val)
> +{
> + return default_val;
> +}
> +
> +static inline const char *ofnode_conf_read_str(const char *prop_name)
> +{
> + return NULL;
> +}
> +#endif /* CONFIG_DM */
>
> #endif
>
ping?
--Sean
Re: [v2] misc: Correct Kconfig dependencies for a number of options
On 5/10/22 12:51 PM, Tom Rini wrote: > We have many cases of SPL (or TPL or VPL) drivers that don't depend on > SPL_MISC (and so on) but rather just MISC. > > Cc: Sean Anderson > Signed-off-by: Tom Rini > --- > Changes in v2: > - [STV]PL_CROS_EC should depend on the correct _MISC only, per Sean > --- > drivers/misc/Kconfig | 23 --- > 1 file changed, 12 insertions(+), 11 deletions(-) > > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig > index 85ae7f62e911..419ddd31c0b9 100644 > --- a/drivers/misc/Kconfig > +++ b/drivers/misc/Kconfig > @@ -125,7 +125,7 @@ config CROS_EC > > config SPL_CROS_EC > bool "Enable Chrome OS EC in SPL" > - depends on SPL > + depends on SPL_MISC > help > Enable access to the Chrome OS EC in SPL. This is a separate > microcontroller typically available on a SPI bus on Chromebooks. It > @@ -135,7 +135,7 @@ config SPL_CROS_EC > > config TPL_CROS_EC > bool "Enable Chrome OS EC in TPL" > - depends on TPL > + depends on TPL_MISC > help > Enable access to the Chrome OS EC in TPL. This is a separate > microcontroller typically available on a SPI bus on Chromebooks. It > @@ -145,7 +145,7 @@ config TPL_CROS_EC > > config VPL_CROS_EC > bool "Enable Chrome OS EC in VPL" > - depends on VPL > + depends on VPL_MISC > help > Enable access to the Chrome OS EC in VPL. This is a separate > microcontroller typically available on a SPI bus on Chromebooks. It > @@ -173,7 +173,7 @@ config CROS_EC_LPC > > config SPL_CROS_EC_LPC > bool "Enable Chrome OS EC LPC driver in SPL" > - depends on CROS_EC > + depends on CROS_EC && SPL_MISC > help > Enable I2C access to the Chrome OS EC. This is used on x86 > Chromebooks such as link and falco. The keyboard is provided > @@ -182,7 +182,7 @@ config SPL_CROS_EC_LPC > > config TPL_CROS_EC_LPC > bool "Enable Chrome OS EC LPC driver in TPL" > - depends on CROS_EC > + depends on CROS_EC && TPL_MISC > help > Enable I2C access to the Chrome OS EC. This is used on x86 > Chromebooks such as link and falco. The keyboard is provided > @@ -191,7 +191,7 @@ config TPL_CROS_EC_LPC > > config VPL_CROS_EC_LPC > bool "Enable Chrome OS EC LPC driver in VPL" > - depends on CROS_EC > + depends on CROS_EC && VPL_MISC > help > Enable I2C access to the Chrome OS EC. This is used on x86 > Chromebooks such as link and falco. The keyboard is provided > @@ -284,7 +284,7 @@ config MXC_OCOTP > > config SPL_MXC_OCOTP > bool "Enable MXC OCOTP driver in SPL" > - depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || > ARCH_VF610) > + depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || > ARCH_MX7ULP || ARCH_VF610) > default y > help > If you say Y here, you will get support for the One Time > @@ -314,7 +314,7 @@ config P2SB > > config SPL_P2SB > bool "Intel Primary to Sideband Bridge in SPL" > - depends on SPL && (X86 || SANDBOX) > + depends on SPL_MISC && (X86 || SANDBOX) > help > The Primary to Sideband Bridge is used to access various peripherals > through memory-mapped I/O in a large chunk of PCI space. The space is > @@ -324,7 +324,7 @@ config SPL_P2SB > > config TPL_P2SB > bool "Intel Primary to Sideband Bridge in TPL" > - depends on TPL && (X86 || SANDBOX) > + depends on TPL_MISC && (X86 || SANDBOX) > help > The Primary to Sideband Bridge is used to access various peripherals > through memory-mapped I/O in a large chunk of PCI space. The space is > @@ -343,7 +343,7 @@ config PWRSEQ > > config SPL_PWRSEQ > bool "Enable power-sequencing drivers for SPL" > - depends on PWRSEQ > + depends on SPL_MISC && PWRSEQ > help > Power-sequencing drivers provide support for controlling power for > devices. They are typically referenced by a phandle from another > @@ -451,7 +451,7 @@ config I2C_EEPROM > > config SPL_I2C_EEPROM > bool "Enable driver for generic I2C-attached EEPROMs for SPL" > - depends on MISC && SPL && SPL_DM > + depends on SPL_MISC > help > This option is an SPL-variant of the I2C_EEPROM option. > See the help of I2C_EEPROM for details. > @@ -504,6 +504,7 @@ config FS_LOADER > > config SPL_FS_LOADER > bool "Enable loader driver for file system" > + depends on SPL > help > This is file system generic loader which can be used to load > the file image from the storage into target such as memory. > Reviewed-by: Sean Anderson Any reason not to remove the defaults in this patch? --Sean
[v2] misc: Correct Kconfig dependencies for a number of options
We have many cases of SPL (or TPL or VPL) drivers that don't depend on SPL_MISC (and so on) but rather just MISC. Cc: Sean Anderson Signed-off-by: Tom Rini --- Changes in v2: - [STV]PL_CROS_EC should depend on the correct _MISC only, per Sean --- drivers/misc/Kconfig | 23 --- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 85ae7f62e911..419ddd31c0b9 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -125,7 +125,7 @@ config CROS_EC config SPL_CROS_EC bool "Enable Chrome OS EC in SPL" - depends on SPL + depends on SPL_MISC help Enable access to the Chrome OS EC in SPL. This is a separate microcontroller typically available on a SPI bus on Chromebooks. It @@ -135,7 +135,7 @@ config SPL_CROS_EC config TPL_CROS_EC bool "Enable Chrome OS EC in TPL" - depends on TPL + depends on TPL_MISC help Enable access to the Chrome OS EC in TPL. This is a separate microcontroller typically available on a SPI bus on Chromebooks. It @@ -145,7 +145,7 @@ config TPL_CROS_EC config VPL_CROS_EC bool "Enable Chrome OS EC in VPL" - depends on VPL + depends on VPL_MISC help Enable access to the Chrome OS EC in VPL. This is a separate microcontroller typically available on a SPI bus on Chromebooks. It @@ -173,7 +173,7 @@ config CROS_EC_LPC config SPL_CROS_EC_LPC bool "Enable Chrome OS EC LPC driver in SPL" - depends on CROS_EC + depends on CROS_EC && SPL_MISC help Enable I2C access to the Chrome OS EC. This is used on x86 Chromebooks such as link and falco. The keyboard is provided @@ -182,7 +182,7 @@ config SPL_CROS_EC_LPC config TPL_CROS_EC_LPC bool "Enable Chrome OS EC LPC driver in TPL" - depends on CROS_EC + depends on CROS_EC && TPL_MISC help Enable I2C access to the Chrome OS EC. This is used on x86 Chromebooks such as link and falco. The keyboard is provided @@ -191,7 +191,7 @@ config TPL_CROS_EC_LPC config VPL_CROS_EC_LPC bool "Enable Chrome OS EC LPC driver in VPL" - depends on CROS_EC + depends on CROS_EC && VPL_MISC help Enable I2C access to the Chrome OS EC. This is used on x86 Chromebooks such as link and falco. The keyboard is provided @@ -284,7 +284,7 @@ config MXC_OCOTP config SPL_MXC_OCOTP bool "Enable MXC OCOTP driver in SPL" - depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) + depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) default y help If you say Y here, you will get support for the One Time @@ -314,7 +314,7 @@ config P2SB config SPL_P2SB bool "Intel Primary to Sideband Bridge in SPL" - depends on SPL && (X86 || SANDBOX) + depends on SPL_MISC && (X86 || SANDBOX) help The Primary to Sideband Bridge is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is @@ -324,7 +324,7 @@ config SPL_P2SB config TPL_P2SB bool "Intel Primary to Sideband Bridge in TPL" - depends on TPL && (X86 || SANDBOX) + depends on TPL_MISC && (X86 || SANDBOX) help The Primary to Sideband Bridge is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is @@ -343,7 +343,7 @@ config PWRSEQ config SPL_PWRSEQ bool "Enable power-sequencing drivers for SPL" - depends on PWRSEQ + depends on SPL_MISC && PWRSEQ help Power-sequencing drivers provide support for controlling power for devices. They are typically referenced by a phandle from another @@ -451,7 +451,7 @@ config I2C_EEPROM config SPL_I2C_EEPROM bool "Enable driver for generic I2C-attached EEPROMs for SPL" - depends on MISC && SPL && SPL_DM + depends on SPL_MISC help This option is an SPL-variant of the I2C_EEPROM option. See the help of I2C_EEPROM for details. @@ -504,6 +504,7 @@ config FS_LOADER config SPL_FS_LOADER bool "Enable loader driver for file system" + depends on SPL help This is file system generic loader which can be used to load the file image from the storage into target such as memory. -- 2.25.1
Re: [PATCH] misc: Correct Kconfig dependencies for a number of options
On Tue, May 10, 2022 at 12:43:40PM -0400, Sean Anderson wrote: > Hi Tom, > > On 5/10/22 11:08 AM, Tom Rini wrote: > > We have many cases of SPL (or TPL or VPL) drivers that don't depend on > > SPL_MISC (and so on) but rather just MISC. > > > > Signed-off-by: Tom Rini > > --- > > drivers/misc/Kconfig | 34 +++--- > > 1 file changed, 23 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig > > index c829939622b0..ebe84b15a49a 100644 > > --- a/drivers/misc/Kconfig > > +++ b/drivers/misc/Kconfig > > @@ -115,7 +115,7 @@ config CROS_EC > > > > config SPL_CROS_EC > > bool "Enable Chrome OS EC in SPL" > > - depends on SPL > > + depends on SPL && SPL_MISC > > Can't we just depend on SPL_MISC? Yes and.. > > --Sean > > > help > > Enable access to the Chrome OS EC in SPL. This is a separate > > microcontroller typically available on a SPI bus on Chromebooks. It > > @@ -125,7 +125,7 @@ config SPL_CROS_EC > > > > config TPL_CROS_EC > > bool "Enable Chrome OS EC in TPL" > > - depends on TPL > > + depends on TPL && TPL_MISC TPL_MISC alone too. I caught this in some places but not all, I'll respin and check for others. Thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] misc: Correct Kconfig dependencies for a number of options
Hi Tom, On 5/10/22 11:08 AM, Tom Rini wrote: > We have many cases of SPL (or TPL or VPL) drivers that don't depend on > SPL_MISC (and so on) but rather just MISC. > > Signed-off-by: Tom Rini > --- > drivers/misc/Kconfig | 34 +++--- > 1 file changed, 23 insertions(+), 11 deletions(-) > > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig > index c829939622b0..ebe84b15a49a 100644 > --- a/drivers/misc/Kconfig > +++ b/drivers/misc/Kconfig > @@ -115,7 +115,7 @@ config CROS_EC > > config SPL_CROS_EC > bool "Enable Chrome OS EC in SPL" > - depends on SPL > + depends on SPL && SPL_MISC Can't we just depend on SPL_MISC? --Sean > help > Enable access to the Chrome OS EC in SPL. This is a separate > microcontroller typically available on a SPI bus on Chromebooks. It > @@ -125,7 +125,7 @@ config SPL_CROS_EC > > config TPL_CROS_EC > bool "Enable Chrome OS EC in TPL" > - depends on TPL > + depends on TPL && TPL_MISC > help > Enable access to the Chrome OS EC in TPL. This is a separate > microcontroller typically available on a SPI bus on Chromebooks. It > @@ -135,7 +135,7 @@ config TPL_CROS_EC > > config VPL_CROS_EC > bool "Enable Chrome OS EC in VPL" > - depends on VPL > + depends on VPL && VPL_MISC > help > Enable access to the Chrome OS EC in VPL. This is a separate > microcontroller typically available on a SPI bus on Chromebooks. It > @@ -163,7 +163,7 @@ config CROS_EC_LPC > > config SPL_CROS_EC_LPC > bool "Enable Chrome OS EC LPC driver in SPL" > - depends on CROS_EC > + depends on CROS_EC && SPL_MISC > help > Enable I2C access to the Chrome OS EC. This is used on x86 > Chromebooks such as link and falco. The keyboard is provided > @@ -172,7 +172,7 @@ config SPL_CROS_EC_LPC > > config TPL_CROS_EC_LPC > bool "Enable Chrome OS EC LPC driver in TPL" > - depends on CROS_EC > + depends on CROS_EC && TPL_MISC > help > Enable I2C access to the Chrome OS EC. This is used on x86 > Chromebooks such as link and falco. The keyboard is provided > @@ -181,7 +181,7 @@ config TPL_CROS_EC_LPC > > config VPL_CROS_EC_LPC > bool "Enable Chrome OS EC LPC driver in VPL" > - depends on CROS_EC > + depends on CROS_EC && VPL_MISC > help > Enable I2C access to the Chrome OS EC. This is used on x86 > Chromebooks such as link and falco. The keyboard is provided > @@ -274,7 +274,7 @@ config MXC_OCOTP > > config SPL_MXC_OCOTP > bool "Enable MXC OCOTP driver in SPL" > - depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || > ARCH_VF610) > + depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || > ARCH_MX7ULP || ARCH_VF610) > default y > help > If you say Y here, you will get support for the One Time > @@ -304,7 +304,7 @@ config P2SB > > config SPL_P2SB > bool "Intel Primary to Sideband Bridge in SPL" > - depends on SPL && (X86 || SANDBOX) > + depends on SPL_MISC && (X86 || SANDBOX) > help > The Primary to Sideband Bridge is used to access various peripherals > through memory-mapped I/O in a large chunk of PCI space. The space is > @@ -314,7 +314,7 @@ config SPL_P2SB > > config TPL_P2SB > bool "Intel Primary to Sideband Bridge in TPL" > - depends on TPL && (X86 || SANDBOX) > + depends on TPL_MISC && (X86 || SANDBOX) > help > The Primary to Sideband Bridge is used to access various peripherals > through memory-mapped I/O in a large chunk of PCI space. The space is > @@ -333,7 +333,7 @@ config PWRSEQ > > config SPL_PWRSEQ > bool "Enable power-sequencing drivers for SPL" > - depends on PWRSEQ > + depends on SPL_MISC && PWRSEQ > help > Power-sequencing drivers provide support for controlling power for > devices. They are typically referenced by a phandle from another > @@ -441,7 +441,7 @@ config I2C_EEPROM > > config SPL_I2C_EEPROM > bool "Enable driver for generic I2C-attached EEPROMs for SPL" > - depends on MISC && SPL && SPL_DM > + depends on SPL_MISC > help > This option is an SPL-variant of the I2C_EEPROM option. > See the help of I2C_EEPROM for details. > @@ -494,7 +494,7 @@ config FS_LOADER > > config SPL_FS_LOADER > bool "Enable loader driver for file system" > + depends on SPL > help > This is file system generic loader which can be used to load > the file image from the storage into target such as memory. >
Re: [PATCH v2] misc: Fix always compiling MISC even for SPL/TPL
On Fri, Apr 22, 2022 at 04:11:37PM -0400, Sean Anderson wrote:
> We should only build support for misc if the appropriate SPL/TPL symbol
> is defined. To ease the transition, make SPL/TPL_MISC default to MISC.
> This is necessary because many drivers don't specify their dependencies
> properly. These defaults can be removed once all drivers depend on the
> appropriate config.
>
> Fixes: aaba703fd0 ("spl: misc: Allow misc drivers in SPL and TPL")
> Signed-off-by: Sean Anderson
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
[PATCH] misc: Correct Kconfig dependencies for a number of options
We have many cases of SPL (or TPL or VPL) drivers that don't depend on SPL_MISC (and so on) but rather just MISC. Signed-off-by: Tom Rini --- drivers/misc/Kconfig | 34 +++--- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index c829939622b0..ebe84b15a49a 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -115,7 +115,7 @@ config CROS_EC config SPL_CROS_EC bool "Enable Chrome OS EC in SPL" - depends on SPL + depends on SPL && SPL_MISC help Enable access to the Chrome OS EC in SPL. This is a separate microcontroller typically available on a SPI bus on Chromebooks. It @@ -125,7 +125,7 @@ config SPL_CROS_EC config TPL_CROS_EC bool "Enable Chrome OS EC in TPL" - depends on TPL + depends on TPL && TPL_MISC help Enable access to the Chrome OS EC in TPL. This is a separate microcontroller typically available on a SPI bus on Chromebooks. It @@ -135,7 +135,7 @@ config TPL_CROS_EC config VPL_CROS_EC bool "Enable Chrome OS EC in VPL" - depends on VPL + depends on VPL && VPL_MISC help Enable access to the Chrome OS EC in VPL. This is a separate microcontroller typically available on a SPI bus on Chromebooks. It @@ -163,7 +163,7 @@ config CROS_EC_LPC config SPL_CROS_EC_LPC bool "Enable Chrome OS EC LPC driver in SPL" - depends on CROS_EC + depends on CROS_EC && SPL_MISC help Enable I2C access to the Chrome OS EC. This is used on x86 Chromebooks such as link and falco. The keyboard is provided @@ -172,7 +172,7 @@ config SPL_CROS_EC_LPC config TPL_CROS_EC_LPC bool "Enable Chrome OS EC LPC driver in TPL" - depends on CROS_EC + depends on CROS_EC && TPL_MISC help Enable I2C access to the Chrome OS EC. This is used on x86 Chromebooks such as link and falco. The keyboard is provided @@ -181,7 +181,7 @@ config TPL_CROS_EC_LPC config VPL_CROS_EC_LPC bool "Enable Chrome OS EC LPC driver in VPL" - depends on CROS_EC + depends on CROS_EC && VPL_MISC help Enable I2C access to the Chrome OS EC. This is used on x86 Chromebooks such as link and falco. The keyboard is provided @@ -274,7 +274,7 @@ config MXC_OCOTP config SPL_MXC_OCOTP bool "Enable MXC OCOTP driver in SPL" - depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) + depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) default y help If you say Y here, you will get support for the One Time @@ -304,7 +304,7 @@ config P2SB config SPL_P2SB bool "Intel Primary to Sideband Bridge in SPL" - depends on SPL && (X86 || SANDBOX) + depends on SPL_MISC && (X86 || SANDBOX) help The Primary to Sideband Bridge is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is @@ -314,7 +314,7 @@ config SPL_P2SB config TPL_P2SB bool "Intel Primary to Sideband Bridge in TPL" - depends on TPL && (X86 || SANDBOX) + depends on TPL_MISC && (X86 || SANDBOX) help The Primary to Sideband Bridge is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is @@ -333,7 +333,7 @@ config PWRSEQ config SPL_PWRSEQ bool "Enable power-sequencing drivers for SPL" - depends on PWRSEQ + depends on SPL_MISC && PWRSEQ help Power-sequencing drivers provide support for controlling power for devices. They are typically referenced by a phandle from another @@ -441,7 +441,7 @@ config I2C_EEPROM config SPL_I2C_EEPROM bool "Enable driver for generic I2C-attached EEPROMs for SPL" - depends on MISC && SPL && SPL_DM + depends on SPL_MISC help This option is an SPL-variant of the I2C_EEPROM option. See the help of I2C_EEPROM for details. @@ -494,7 +494,7 @@ config FS_LOADER config SPL_FS_LOADER bool "Enable loader driver for file system" + depends on SPL help This is file system generic loader which can be used to load the file image from the storage into target such as memory. -- 2.25.1
Re: How not to have uboot env partition on SPI flash?
Thanks Sean. This works. Regards, Gangadhar On Tue, May 10, 2022 at 6:57 PM Sean Anderson wrote: > On 5/10/22 9:20 AM, Gangadhar N wrote: > > Hi All, > > Is there a way to remove the uboot env partition on SPI flash? > > I always want uboot to use the “default env” that is part of uboot.bin. > > I want only uboot.bin on SPI flash and no separate uboot env partition on > > flash. > > > > Thanks & Regards, > > Gangadhar > > > > CONFIG_ENV_IS_NOWHERE > >
[PULL] u-boot-stm32/master v2022.07 = u-boot-stm32-20220510
Hi Tom Please pull the STM32 related patches for u-boot/master, v2022.07: u-boot-stm32-20220510 CI status: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/11978 Thanks Patrice The following changes since commit f08ed34371c54244421eac8ffb4c77559c5ea013: Prepare v2022.07-rc2 (2022-05-09 12:49:31 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-stm.git tags/u-boot-stm32-20220510 for you to fetch changes up to e198d4fe7c34cbb97d7d3cbf31d3a78a5ecc43f7: doc: Add documentation for STM32 MCUs (2022-05-10 13:56:12 +0200) Add new STM32 MCU boards and Documentation STM32 programmer improvements video: support several LTDC HW versions and fix data enable polarity board: fix stboard error message, consider USB cable connected when boot device is USB configs: stm32mp1: set console variable for extlinux.conf configs: stm32mp1: add support for baudrate higher than 115200 for ST-Link ARM: stm32mp: Fix Silicon version handling and ft_system_setup() phy: stm32-usbphyc: Add DT phy tuning support arm: dts: stm32mp15: alignment with v5.18 ram: Conditionally enable ASR mach-stm32mp: psci: retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend configs: Use TFTP_TSIZE on DHSOM and STMicroelectronics boards ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM pinctrl: stm32: rework GPIO holes management Marek Vasut (6): ram: stm32mp1: Conditionally enable ASR stm32mp: psci: Retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM ARM: stm32: Use CONFIG_TFTP_TSIZE on DHSOM ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI clk: stm32mp1: Add missing newline Patrice Chotard (17): pinctrl: pinctrl_stm32: Update pinmux_mode definition pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins gpio: stm32_gpio: Rework GPIO hole management phy: stm32-usbphyc: stm32-usbphyc: Add DT phy tuning support board: st: stm32mp1: Consider USB cable connected when boot device is USB configs: stm32f746-disco: Concatenate spl and u-boot binaries configs: stm32f746-disco: Rename stm32f746-disco_defconfig to stm32f746-disco_spl_defconfig configs: stm32f746-disco: Add stm32f746-disco_defconfig configs: stm32f769-disco: Rename stm32f769-disco_defconfig to stm32f769-disco_spl_defconfig configs: stm32f769-disco: Add stm32f769-disco_defconfig configs: stm32f769-disco: Migrate SPL flags to defconfig configs: stm32f746-disco: Migrate SPL flags to defconfig board: stm32f746-disco: Fix dram_init() in none SPL config configs: stm32f746-disco: use CONFIG_DEFAULT_DEVICE_TREE as fdtfile configs: stm32746g-eval: Add stm32746g-eval_defconfig configs: stm32746g-eval: Add stm32746g-eval_spl_defconfig doc: Add documentation for STM32 MCUs Patrick Delaunay (15): stm32mp: stm32prog: fix comment stm32mp: stm32prog: add CONFIG_CMD_STM32PROG_OTP stm32mp: stm32prog: add TEE support in stm32prog command stm32mp: stm32prog: add support of STM32IMAGE version 2 stm32mp: stm32prog: add support of UUID for FIP partition stm32mp: stm32prog: handle interruption during the first enumeration stm32mp: stm32prog: handle U-Boot script in flashlayout alternate stm32mp: stm32prog: handle flashlayout without STM32 image header board: st: common: fix the error messages in stboard command configs: stm32mp1: set the console variable for extlinux.conf configs: stm32mp1: Add support for baudrates higher than 115200 for st-link ARM: stm32mp: skip ft_system_setup when the soc node is absent ARM: stm32mp: correctly handle Silicon revision arm: dts: stm32mp15: alignment with v5.18 ARM: stm32: Use CONFIG_TFTP_TSIZE on STMicroelectronics boards Yannick FERTRE (1): video: stm32: stm32_ltdc: fix data enable polarity Yannick Fertre (1): video: stm32: stm32_ltdc: support several hardware versions arch/arm/dts/stm32mp15-pinctrl.dtsi| 92 +++ arch/arm/dts/stm32mp15-u-boot.dtsi | 12 -- arch/arm/dts/stm32mp151.dtsi | 37 + arch/arm/dts/stm32mp153.dtsi | 7 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts| 2 + arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 2 + arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 4 ++ arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts | 4 ++ arch/arm/dts/stm32mp157c-ed1.dts | 2 + arch/arm/dts/stm32mp157c-odyssey.dts | 2
Re: [PATCH] squashfs: Fix compilation on big endian systems
On Wednesday 06 April 2022 23:31:53 Pali Rohár wrote: > Signed-off-by: Pali Rohár > --- > fs/squashfs/sqfs.c | 3 +-- > fs/squashfs/sqfs_dir.c | 3 +-- > 2 files changed, 2 insertions(+), 4 deletions(-) > > diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c > index 5d9c52af80ba..41cb811c1b32 100644 > --- a/fs/squashfs/sqfs.c > +++ b/fs/squashfs/sqfs.c > @@ -11,8 +11,7 @@ > #include > #include > #include > -#include > -#include > +#include > #include > #include > #include > diff --git a/fs/squashfs/sqfs_dir.c b/fs/squashfs/sqfs_dir.c > index a265b98fe685..ed83c90682ff 100644 > --- a/fs/squashfs/sqfs_dir.c > +++ b/fs/squashfs/sqfs_dir.c > @@ -7,8 +7,7 @@ > > #include > #include > -#include > -#include > +#include > #include > #include > #include > -- > 2.20.1 > PING?
[PATCH] arm64: zynqmp: Set qspi tx-buswidth to 4
From: Amit Kumar Mahapatra
In all the ZynqMP boards dts files tx-buswidth is by default set to 1. Due
to this the framework only issues 1-1-1 write commands to the GQSPI driver.
But the GQSPI controller is capable of handling 1-4-4 write commands, so
updated the tx-buswidth to 4 in ZynqMP boards dts files. This would enable
the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This
will increase the tx data transfer rate, as now the tx data will be
transferred on four lines instead on single line.
Signed-off-by: Amit Kumar Mahapatra
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +-
arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +-
arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +-
arch/arm/dts/zynqmp-mini-qspi.dts | 2 +-
arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +-
arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts | 2 +-
arch/arm/dts/zynqmp-zc1232-revA.dts | 2 +-
arch/arm/dts/zynqmp-zc1254-revA.dts | 2 +-
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +-
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 +-
arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +-
arch/arm/dts/zynqmp-zcu104-revA.dts | 2 +-
arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +-
arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +-
arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +-
arch/arm/dts/zynqmp-zcu1275-revA.dts | 2 +-
arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +-
arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +-
18 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index 86f2ccf4d951..7b3722f0808b 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -77,7 +77,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <10800>;
};
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index e980fb07fc30..11b2a58a0f06 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -73,7 +73,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <10800>;
};
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index c8c5100672fe..db199c467b0d 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -73,7 +73,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <10800>;
};
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts
b/arch/arm/dts/zynqmp-mini-qspi.dts
index 9b4320fe6e20..20c21deb6673 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -68,7 +68,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <4000>;
};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts
b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 14ab31685dfe..e904cd8ea093 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -117,7 +117,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <4000>; /* 40MHz */
partition@0 {
diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
index 300e2ebe96e8..3750bb38b585 100644
--- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
+++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
@@ -61,7 +61,7 @@
compatible = "st,m25p80", "n25q256a", "jedec,spi-nor";
m25p,fast-read;
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-
Re: [PATCH] soc: xilinx: zynqmp: fix out of bounds array access
st 20. 4. 2022 v 9:39 odesílatel Michal Simek napsal:
>
> The call to xilinx_pm_request requires an array of a larger size.
>
> Signed-off-by: Michal Simek
> ---
>
> The same change was done for versal by
> https://lore.kernel.org/r/20220416181530.2311155-1-jo...@foundries.io
> ---
> drivers/soc/soc_xilinx_zynqmp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
> index 7d33ce2163d8..a71115b17ccd 100644
> --- a/drivers/soc/soc_xilinx_zynqmp.c
> +++ b/drivers/soc/soc_xilinx_zynqmp.c
> @@ -49,7 +49,7 @@ static const struct soc_ops soc_xilinx_zynqmp_ops = {
> static int soc_xilinx_zynqmp_probe(struct udevice *dev)
> {
> struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
> - u32 ret_payload[4];
> + u32 ret_payload[PAYLOAD_ARG_CNT];
> int ret;
>
> priv->family = zynqmp_family;
> --
> 2.35.1
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
[PATCH] xilinx: zynqmp: Do not guard SPL_FS_LOAD_PAYLOAD_NAME by SDHCI driver
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME is used by set_dfu_alt_info() for string generation. It doesn't depend on SDHCI because the same file can be stored to other non volatile memories like qspi. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 8eb44b18d20c..f25d796a1e72 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -226,7 +226,6 @@ #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf-uboot.ub" /* MMC support */ -#ifdef CONFIG_MMC_SDHCI_ZYNQ # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */ # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS0 /* unused */ # if defined(CONFIG_SPL_LOAD_FIT) @@ -234,7 +233,6 @@ # else # define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" # endif -#endif #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) # define CONFIG_SPL_HASH -- 2.36.0
[PATCH] arm64: zynqmp: zynqmp-zcu106-rev1.0: Fix DP PLL configuration
From: Neal Frager This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-rev1.0 evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Signed-off-by: Neal Frager Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c index 2ac4e035d887..3dc9bf8f3a83 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c @@ -81,8 +81,8 @@ static unsigned long psu_clock_init_data(void) psu_mask_write(0xFF5E0104, 0x0007U, 0xU); psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U); - psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U); psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U); psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); -- 2.36.0
Re: [PATCH] ls1028a: hdp: Add config support for HDP firmware loading
> From: Alison Wang > > This patch adds config support for HDP firmware loading on LS1028A. FWIW, I really don't like this as this is just for a downstream kernel. For the upstream kernel the firmware should be loaded by the kernel itself. But unfortunately, there is no development there. (I have some half baked patches though and can confirm, that firmware loading is working from linux). Instead of this I'd like to see some work to support the DP PHY in upstream linux as this is really the last missing piece to get graphics working. Now this is purely board related code, so it is probably fine. But in the past the handling of purly downstream stuff was removed from upstream u-boot anyway in favor of the upstream method. i.e. fixup of the ls1028a-gpu node. -michael
Re: How not to have uboot env partition on SPI flash?
On 5/10/22 9:20 AM, Gangadhar N wrote: Hi All, Is there a way to remove the uboot env partition on SPI flash? I always want uboot to use the “default env” that is part of uboot.bin. I want only uboot.bin on SPI flash and no separate uboot env partition on flash. Thanks & Regards, Gangadhar CONFIG_ENV_IS_NOWHERE
Re: [PATCH v4 06/25] mips: mtmips: add two reference boards for mt7621
On 10.05.22 14:18, Weijie Gao wrote:
The mt7621_rfb board supports integrated giga PHYs plus one external
giga PHYs. It also has up to 512MiB DDR3, 16MB SPI-NOR, 3 mini PCI-e x1
slots, SDXC and USB.
The mt7621_nand_rfb board is almost the same as mt7621_rfb board, but it
uses NAND flash and SDXC is not available.
Reviewed-by: Daniel Schwierzeck
Signed-off-by: Weijie Gao
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
v4 changes:
Modify defconfig files for booting from flash
v3 changes: none
v2 changes:
Add config file for mt7621-rfb boards
---
arch/mips/dts/Makefile | 2 +
arch/mips/dts/mediatek,mt7621-nand-rfb.dts | 52 ++
arch/mips/dts/mediatek,mt7621-rfb.dts | 68 ++
arch/mips/mach-mtmips/mt7621/Kconfig | 20 ++
board/mediatek/mt7621/MAINTAINERS | 8 +++
board/mediatek/mt7621/Makefile | 3 +
board/mediatek/mt7621/board.c | 6 ++
configs/mt7621_nand_rfb_defconfig | 81 ++
configs/mt7621_rfb_defconfig | 80 +
9 files changed, 320 insertions(+)
create mode 100644 arch/mips/dts/mediatek,mt7621-nand-rfb.dts
create mode 100644 arch/mips/dts/mediatek,mt7621-rfb.dts
create mode 100644 board/mediatek/mt7621/MAINTAINERS
create mode 100644 board/mediatek/mt7621/Makefile
create mode 100644 board/mediatek/mt7621/board.c
create mode 100644 configs/mt7621_nand_rfb_defconfig
create mode 100644 configs/mt7621_rfb_defconfig
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 95144b24dc..1b179116c9 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -16,6 +16,8 @@ dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) +=
comtrend,wap-5813n.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb
dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb
+dtb-$(CONFIG_BOARD_MT7621_RFB) += mediatek,mt7621-rfb.dtb
+dtb-$(CONFIG_BOARD_MT7621_NAND_RFB) += mediatek,mt7621-nand-rfb.dtb
dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) +=
gardena-smart-gateway-mt7688.dtb
dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb
diff --git a/arch/mips/dts/mediatek,mt7621-nand-rfb.dts
b/arch/mips/dts/mediatek,mt7621-nand-rfb.dts
new file mode 100644
index 00..d159531a56
--- /dev/null
+++ b/arch/mips/dts/mediatek,mt7621-nand-rfb.dts
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao
+ */
+
+/dts-v1/;
+
+#include "mt7621.dtsi"
+
+/ {
+ compatible = "mediatek,mt7621-nand-rfb", "mediatek,mt7621-soc";
+ model = "MediaTek MT7621 RFB (NAND)";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&pinctrl {
+ state_default: pin_state {
+ nand {
+ groups = "spi", "sdxc";
+ function = "nand";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
+
+ð {
+ status = "okay";
+};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/mips/dts/mediatek,mt7621-rfb.dts
b/arch/mips/dts/mediatek,mt7621-rfb.dts
new file mode 100644
index 00..4a3b850ddd
--- /dev/null
+++ b/arch/mips/dts/mediatek,mt7621-rfb.dts
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao
+ */
+
+/dts-v1/;
+
+#include "mt7621.dtsi"
+
+/ {
+ compatible = "mediatek,mt7621-rfb", "mediatek,mt7621-soc";
+ model = "MediaTek MT7621 RFB (SPI-NOR)";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&pinctrl {
+ state_default: pin_state {
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
+
+&spi {
+ status = "okay";
+ num-cs = <2>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <2500>;
+ reg = <0>;
+ };
+};
+
+ð {
+ status = "okay";
+};
+
+&mmc {
+ cap-sd-highspeed;
+
+ status = "okay";
+};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/mips/mach-mtmips/mt7621/Kconfig
b/arch/mips/mach-mtmips/mt7621/Kconfig
index 37d512c68f..008a28f991 100644
--- a/arch/mips/mach-mtmips/mt7621/Kconfig
+++ b/arch/mips/mach-mtmips/mt7621/Kconfig
@@ -79,6 +79,26 @@ config MT7621_BOOT_FROM_NAND
choice
prompt "Board select"
+config BOARD_MT7621_RFB
+
How not to have uboot env partition on SPI flash?
Hi All, Is there a way to remove the uboot env partition on SPI flash? I always want uboot to use the “default env” that is part of uboot.bin. I want only uboot.bin on SPI flash and no separate uboot env partition on flash. Thanks & Regards, Gangadhar
[PATCH] phy: zynqmp: Increase timeout value to 10ms
Observing psgtr pll timeouts with some usb hubs and devices behind it.
Increase timeout to 10ms to take care of it.
Signed-off-by: Ashok Reddy Soma
---
drivers/phy/phy-zynqmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c
index 08c1b6efcf..d1288bb17f 100644
--- a/drivers/phy/phy-zynqmp.c
+++ b/drivers/phy/phy-zynqmp.c
@@ -168,7 +168,7 @@ enum {
};
/* Timeout values */
-#define TIMEOUT_US 1000
+#define TIMEOUT_US 1
#define IOU_SLCR_GEM_CLK_CTRL 0x308
#define GEM_CTRL_GEM_SGMII_MODEBIT(2)
--
2.17.1
[PATCH V3 7/7] binman_sym: guard with CONFIG_SPL_BINMAN_SYMBOLS
From: Peng Fan There is case that CONFIG_BINMAN is defined, but CONFIG_SPL_BINMAN_SYMBOLS is not defined. In that case, there will be build failure. So use CONFIG_SPL_BINMAN_SYMBOLS to guard the macros, and define CONFIG_SPL_BINMAN_SYMBOLS in binman syms test. Tested-by: Tim Harvey #imx8m[m,n,p]-venice Tested-by: Tim Harvey #imx8m[m,n,p]-venice Signed-off-by: Peng Fan --- include/binman_sym.h| 2 +- tools/binman/test/u_boot_binman_syms.c | 1 + tools/binman/test/u_boot_binman_syms_size.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/binman_sym.h b/include/binman_sym.h index 72e6765fe52..548d8f5654c 100644 --- a/include/binman_sym.h +++ b/include/binman_sym.h @@ -13,7 +13,7 @@ #define BINMAN_SYM_MISSING (-1UL) -#ifdef CONFIG_BINMAN +#ifdef CONFIG_SPL_BINMAN_SYMBOLS /** * binman_symname() - Internal function to get a binman symbol name diff --git a/tools/binman/test/u_boot_binman_syms.c b/tools/binman/test/u_boot_binman_syms.c index 37fc339ce84..f4a4d1f6846 100644 --- a/tools/binman/test/u_boot_binman_syms.c +++ b/tools/binman/test/u_boot_binman_syms.c @@ -6,6 +6,7 @@ */ #define CONFIG_BINMAN +#define CONFIG_SPL_BINMAN_SYMBOLS #include binman_sym_declare(unsigned long, u_boot_spl_any, offset); diff --git a/tools/binman/test/u_boot_binman_syms_size.c b/tools/binman/test/u_boot_binman_syms_size.c index 7224bc1863c..3a01d8ca4be 100644 --- a/tools/binman/test/u_boot_binman_syms_size.c +++ b/tools/binman/test/u_boot_binman_syms_size.c @@ -6,6 +6,7 @@ */ #define CONFIG_BINMAN +#define CONFIG_SPL_BINMAN_SYMBOLS #include binman_sym_declare(char, u_boot_spl, pos); -- 2.36.0
[PATCH V3 6/7] arm: dts: imx8m: shrink ddr firmware size to actual file size
From: Peng Fan
After we switch to use BINMAN_SYMBOLS, there is no need to pad
the file size to 0x8000 and 0x4000. After we use BINMAN_SYMBOLS,
the u-boot-spl-ddr.bin shrink about 36KB with i.MX8MP-EVK.
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-u-boot.dtsi | 8
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 8
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 8
arch/arm/dts/imx8mn-evk-u-boot.dtsi | 8
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 8
arch/arm/dts/imx8mn-venice-u-boot.dtsi | 8
arch/arm/dts/imx8mp-u-boot.dtsi | 8
arch/arm/dts/imx8mq-cm-u-boot.dtsi | 8
arch/arm/dts/imx8mq-u-boot.dtsi | 8
9 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 5de55a2d80b..19a2da30f51 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -41,25 +41,25 @@
imem_1d: blob-ext@1 {
filename = "lpddr4_pmu_train_1d_imem.bin";
- size = <0x8000>;
+ align-end = <4>;
type = "blob-ext";
};
dmem_1d: blob-ext@2 {
filename = "lpddr4_pmu_train_1d_dmem.bin";
- size = <0x4000>;
+ align-end = <4>;
type = "blob-ext";
};
imem_2d: blob-ext@3 {
filename = "lpddr4_pmu_train_2d_imem.bin";
- size = <0x8000>;
+ align-end = <4>;
type = "blob-ext";
};
dmem_2d: blob-ext@4 {
filename = "lpddr4_pmu_train_2d_dmem.bin";
- size = <0x4000>;
+ align-end = <4>;
type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index eb1dd8debba..e1740fa31a6 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -149,22 +149,22 @@
blob_1: blob-ext@1 {
filename = "lpddr4_pmu_train_1d_imem.bin";
- size = <0x8000>;
+ align-end = <4>;
};
blob_2: blob-ext@2 {
filename = "lpddr4_pmu_train_1d_dmem.bin";
- size = <0x4000>;
+ align-end = <4>;
};
blob_3: blob-ext@3 {
filename = "lpddr4_pmu_train_2d_imem.bin";
- size = <0x8000>;
+ align-end = <4>;
};
blob_4: blob-ext@4 {
filename = "lpddr4_pmu_train_2d_dmem.bin";
- size = <0x4000>;
+ align-end = <4>;
};
};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 4d0ecb07d4f..1fe2d0fd507 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -157,22 +157,22 @@
blob_1: blob-ext@1 {
filename = "ddr4_imem_1d_201810.bin";
- size = <0x8000>;
+ align-end = <4>;
};
blob_2: blob-ext@2 {
filename = "ddr4_dmem_1d_201810.bin";
- size = <0x4000>;
+ align-end = <4>;
};
blob_3: blob-ext@3 {
filename = "ddr4_imem_2d_201810.bin";
- size = <0x8000>;
+ align-end = <4>;
};
blob_4: blob-ext@4 {
filename = "ddr4_dmem_2d_201810.bin";
- size = <0x4000>;
+ align-end = <4>;
};
};
diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
index 3db46d4cbcb..4f6dcf307b2 100644
--- a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
@@ -38,22 +38,22 @@
blob_1: blob-ext@1 {
filename = "lpddr4_pmu_train_1d_imem.bin";
- size = <0x8000>;
+ align-end = <4>;
};
blob_2: blob-ext@2 {
filename = "lpddr4_pmu_train_1d_dmem.bin";
- size = <0x4000>;
+ align-end = <4>;
};
blob_3: blob-ext@3 {
[PATCH V3 5/7] ddr: imx8m: helper: load ddr firmware according to binman symbols
From: Peng Fan
By reading binman symbols, we no need hard coded IMEM_LEN/DMEM_LEN after
we update the binman dtsi to drop 0x8000/0x4000 length for the firmware.
And that could save binary size for many KBs.
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
---
drivers/ddr/imx/imx8m/helper.c | 51 --
1 file changed, 43 insertions(+), 8 deletions(-)
diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c
index f23904bf712..b3bd57531b7 100644
--- a/drivers/ddr/imx/imx8m/helper.c
+++ b/drivers/ddr/imx/imx8m/helper.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -25,15 +26,30 @@ DECLARE_GLOBAL_DATA_PTR;
#define DMEM_OFFSET_ADDR 0x00054000
#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+binman_sym_declare(ulong, blob_ext_1, image_pos);
+binman_sym_declare(ulong, blob_ext_1, size);
+
+binman_sym_declare(ulong, blob_ext_2, image_pos);
+binman_sym_declare(ulong, blob_ext_2, size);
+
+#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
+binman_sym_declare(ulong, blob_ext_3, image_pos);
+binman_sym_declare(ulong, blob_ext_3, size);
+
+binman_sym_declare(ulong, blob_ext_4, image_pos);
+binman_sym_declare(ulong, blob_ext_4, size);
+#endif
+
/* We need PHY iMEM PHY is 32KB padded */
void ddr_load_train_firmware(enum fw_type type)
{
u32 tmp32, i;
u32 error = 0;
unsigned long pr_to32, pr_from32;
- unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
- unsigned long imem_start = (unsigned long)&_end + fw_offset;
- unsigned long dmem_start;
+ uint32_t fw_offset = type ? IMEM_2D_OFFSET : 0;
+ uint32_t imem_start = (unsigned long)&_end + fw_offset;
+ uint32_t dmem_start;
+ uint32_t imem_len = IMEM_LEN, dmem_len = DMEM_LEN;
#ifdef CONFIG_SPL_OF_CONTROL
if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
@@ -43,11 +59,30 @@ void ddr_load_train_firmware(enum fw_type type)
}
#endif
- dmem_start = imem_start + IMEM_LEN;
+ if (CONFIG_IS_ENABLED(BINMAN_SYMBOLS)) {
+ switch (type) {
+ case FW_1D_IMAGE:
+ imem_start = binman_sym(ulong, blob_ext_1, image_pos);
+ imem_len = binman_sym(ulong, blob_ext_1, size);
+ dmem_start = binman_sym(ulong, blob_ext_2, image_pos);
+ dmem_len = binman_sym(ulong, blob_ext_2, size);
+ break;
+ case FW_2D_IMAGE:
+#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
+ imem_start = binman_sym(ulong, blob_ext_3, image_pos);
+ imem_len = binman_sym(ulong, blob_ext_3, size);
+ dmem_start = binman_sym(ulong, blob_ext_4, image_pos);
+ dmem_len = binman_sym(ulong, blob_ext_4, size);
+#endif
+ break;
+ }
+ }
+
+ dmem_start = imem_start + imem_len;
pr_from32 = imem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
- for (i = 0x0; i < IMEM_LEN; ) {
+ for (i = 0x0; i < imem_len; ) {
tmp32 = readl(pr_from32);
writew(tmp32 & 0x, pr_to32);
pr_to32 += 4;
@@ -59,7 +94,7 @@ void ddr_load_train_firmware(enum fw_type type)
pr_from32 = dmem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
- for (i = 0x0; i < DMEM_LEN; ) {
+ for (i = 0x0; i < dmem_len; ) {
tmp32 = readl(pr_from32);
writew(tmp32 & 0x, pr_to32);
pr_to32 += 4;
@@ -72,7 +107,7 @@ void ddr_load_train_firmware(enum fw_type type)
debug("check ddr_pmu_train_imem code\n");
pr_from32 = imem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
- for (i = 0x0; i < IMEM_LEN; ) {
+ for (i = 0x0; i < imem_len; ) {
tmp32 = (readw(pr_to32) & 0x);
pr_to32 += 4;
tmp32 += ((readw(pr_to32) & 0x) << 16);
@@ -93,7 +128,7 @@ void ddr_load_train_firmware(enum fw_type type)
debug("check ddr4_pmu_train_dmem code\n");
pr_from32 = dmem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
- for (i = 0x0; i < DMEM_LEN;) {
+ for (i = 0x0; i < dmem_len;) {
tmp32 = (readw(pr_to32) & 0x);
pr_to32 += 4;
tmp32 += ((readw(pr_to32) & 0x) << 16);
--
2.36.0
[PATCH V3 4/7] tools: binman: section: replace @ with -
From: Peng Fan
In arch/arm/dts/imx8mp-u-boot.dtsi, there are blob-ext@1, blob-ext@2 and
etc which is for packing ddr phy firmware. However we could not declare
symbol name such as 'binman_sym_declare(ulong, blob_ext@1, image_pos)',
because '@' is not allowed, so we choose to declare the symbol
'binman_sym_declare(ulong, blob_ext_1, image_pos);' with '@' replaced with
'_'. It does not impact if there is no '@' in section name.
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Reviewed-by: Tom Rini
Signed-off-by: Peng Fan
---
tools/binman/etype/section.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py
index bd67238b919..e3f362b442b 100644
--- a/tools/binman/etype/section.py
+++ b/tools/binman/etype/section.py
@@ -875,7 +875,7 @@ class Entry_section(Entry):
entries[entry.GetPath()] = entry
for entry in to_add.values():
self._CollectEntries(entries, entries_by_name, entry)
-entries_by_name[add_entry.name] = add_entry
+entries_by_name[add_entry.name.replace('@', '-')] = add_entry
def MissingArgs(self, entry, missing):
"""Report a missing argument, if enabled
--
2.36.0
[PATCH V3 3/7] armv8: u-boot-spl.lds: mark __image_copy_start as symbol
From: Peng Fan
In arch/arm/lib/sections.c there is below code:
char __image_copy_start[0] __section(".__image_copy_start");
But actually 'objdump -t spl/u-boot-spl' not able to find out
symbol '__image_copy_start' for binman update image-pos/size.
So update link file
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
---
arch/arm/cpu/armv8/u-boot-spl.lds | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds
b/arch/arm/cpu/armv8/u-boot-spl.lds
index 730eb93dbc3..9b1e7d46287 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -23,7 +23,7 @@ SECTIONS
{
.text : {
. = ALIGN(8);
- *(.__image_copy_start)
+ __image_copy_start = .;
CPUDIR/start.o (.text*)
*(.text*)
} >.sram
--
2.36.0
[PATCH V3 2/7] arm: dts: imx8m: update binman ddr firmware node name
From: Peng Fan
We are migrating to use BINMAN SYMBOLS, the current name is not
a valid binman type, so update to use blob-ext@[1,2,3,4].
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-u-boot.dtsi | 8
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 4 ++--
arch/arm/dts/imx8mn-venice-u-boot.dtsi| 8
arch/arm/dts/imx8mq-u-boot.dtsi | 8
4 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 9f66cdb65a9..5de55a2d80b 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -39,25 +39,25 @@
filename = "u-boot-spl.bin";
};
- 1d-imem {
+ imem_1d: blob-ext@1 {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
- 1d-dmem {
+ dmem_1d: blob-ext@2 {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
};
- 2d-imem {
+ imem_2d: blob-ext@3 {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
- 2d-dmem {
+ dmem_2d: blob-ext@4 {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
index 46a9d7fd78b..5a52b73d7e9 100644
--- a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
@@ -111,13 +111,13 @@
filename = "u-boot-spl.bin";
};
- 1d-imem {
+ imem_1d: blob-ext@1 {
filename = "ddr3_imem_1d.bin";
size = <0x8000>;
type = "blob-ext";
};
- 1d_dmem {
+ dmem_1d: blob-ext@2 {
filename = "ddr3_dmem_1d.bin";
size = <0x4000>;
type = "blob-ext";
diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
index 35819553879..67922146963 100644
--- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
@@ -126,25 +126,25 @@
filename = "u-boot-spl.bin";
};
- 1d-imem {
+ imem_1d: blob-ext@1 {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
- 1d_dmem {
+ dmem_1d: blob-ext@2 {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
};
- 2d_imem {
+ imem_2d: blob-ext@3 {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
- 2d_dmem {
+ dmem_2d: blob-ext@4 {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi
index 912a3d4a356..389414ad26f 100644
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -46,25 +46,25 @@
filename = "u-boot-spl.bin";
};
- 1d-imem {
+ imem_1d: blob-ext@1 {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
- 1d-dmem {
+ dmem_1d: blob-ext@2 {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
};
- 2d-imem {
+ imem_2d: blob-ext@3 {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
- 2d-dmem {
+ dmem_2d: blob-ext@4 {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
--
2.36.0
[PATCH V3 1/7] spl: guard u_boot_any with X86
From: Peng Fan
set the symbol as weak not work if LTO is enabled. Since u_boot_any is
only used on X86 for now, so guard it with X86, otherwise build break
if we use BINMAN_SYMBOLS on i.MX.
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
---
common/spl/spl.c | 8 ++--
common/spl/spl_ram.c | 4
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index c8c463f80bd..4b28180467a 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -50,7 +50,7 @@ DECLARE_GLOBAL_DATA_PTR;
u32 *boot_params_ptr = NULL;
-#if CONFIG_IS_ENABLED(BINMAN_SYMBOLS)
+#if CONFIG_IS_ENABLED(BINMAN_SYMBOLS) && CONFIG_IS_ENABLED(X86)
/* See spl.h for information about this */
binman_sym_declare(ulong, u_boot_any, image_pos);
binman_sym_declare(ulong, u_boot_any, size);
@@ -148,7 +148,7 @@ void spl_fixup_fdt(void *fdt_blob)
#endif
}
-#if CONFIG_IS_ENABLED(BINMAN_SYMBOLS)
+#if CONFIG_IS_ENABLED(BINMAN_SYMBOLS) && CONFIG_IS_ENABLED(X86)
ulong spl_get_image_pos(void)
{
#ifdef CONFIG_VPL
@@ -221,7 +221,11 @@ __weak struct image_header *spl_get_load_buffer(ssize_t
offset, size_t size)
void spl_set_header_raw_uboot(struct spl_image_info *spl_image)
{
+#if CONFIG_IS_ENABLED(X86)
ulong u_boot_pos = binman_sym(ulong, u_boot_any, image_pos);
+#else
+ ulong u_boot_pos = BINMAN_SYM_MISSING;
+#endif
spl_image->size = CONFIG_SYS_MONITOR_LEN;
diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c
index 82964592571..083b14102ee 100644
--- a/common/spl/spl_ram.c
+++ b/common/spl/spl_ram.c
@@ -70,7 +70,11 @@ static int spl_ram_load_image(struct spl_image_info
*spl_image,
load.read = spl_ram_load_read;
spl_load_simple_fit(spl_image, &load, 0, header);
} else {
+#if CONFIG_IS_ENABLED(X86)
ulong u_boot_pos = binman_sym(ulong, u_boot_any, image_pos);
+#else
+ ulong u_boot_pos = BINMAN_SYM_MISSING;
+#endif
debug("Legacy image\n");
/*
--
2.36.0
[PATCH V3 0/7] arm64: binman: use binman symbols for imx
From: Peng Fan V3: Add R-b/T-b Fix build warning V2: resolve some CI failure include patch 7 binman symbol is a good feature, but only used on X86 for now. This patchset is to use it for i.MX8M platform. The current imx8m ddr phy firmware consumes lots of space, because we pad them to the largest 32KB and 16KB for IMEM and DMEM. With this patchset we use binman symbols to get firmware location and size, we could save near 36KB with i.MX8MP-EVK. Please help check and test Peng Fan (7): spl: guard u_boot_any with X86 arm: dts: imx8m: update binman ddr firmware node name armv8: u-boot-spl.lds: mark __image_copy_start as symbol tools: binman: section: replace @ with - ddr: imx8m: helper: load ddr firmware according to binman symbols arm: dts: imx8m: shrink ddr firmware size to actual file size binman_sym: guard with CONFIG_SPL_BINMAN_SYMBOLS arch/arm/cpu/armv8/u-boot-spl.lds | 2 +- arch/arm/dts/imx8mm-u-boot.dtsi | 16 +++--- arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 8 +-- .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 4 +- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 8 +-- arch/arm/dts/imx8mn-evk-u-boot.dtsi | 8 +-- .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 8 +-- arch/arm/dts/imx8mn-venice-u-boot.dtsi| 16 +++--- arch/arm/dts/imx8mp-u-boot.dtsi | 8 +-- arch/arm/dts/imx8mq-cm-u-boot.dtsi| 8 +-- arch/arm/dts/imx8mq-u-boot.dtsi | 16 +++--- common/spl/spl.c | 8 ++- common/spl/spl_ram.c | 4 ++ drivers/ddr/imx/imx8m/helper.c| 51 --- include/binman_sym.h | 2 +- tools/binman/etype/section.py | 2 +- tools/binman/test/u_boot_binman_syms.c| 1 + tools/binman/test/u_boot_binman_syms_size.c | 1 + 18 files changed, 108 insertions(+), 63 deletions(-) -- 2.36.0
Re: [PATCH] usb: xhci-dwc3: Support role switch default role
> From: Mark Kettenis
> Date: Tue, 19 Apr 2022 21:06:33 +0200
>
> When the device tree indicates support for role switching through
> the "usb-role-switch" property, take the "role-switch-default-mode"
> property into account when deciding which role to put the
> controller into.
>
> This makes USB devices work on Apple M1 systems where the device
> tree may include a "dr_mode" property that is set to "otg", but
> where we need to put the controller into "host" mode to see
> devices connected to the type-C ports.
>
> Signed-off-by: Mark Kettenis
> ---
> drivers/usb/common/common.c | 16
> drivers/usb/host/xhci-dwc3.c | 6 ++
> include/linux/usb/otg.h | 10 ++
> 3 files changed, 32 insertions(+)
Ping?
> diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
> index ee0c064f1f..cff86a51ae 100644
> --- a/drivers/usb/common/common.c
> +++ b/drivers/usb/common/common.c
> @@ -40,6 +40,22 @@ enum usb_dr_mode usb_get_dr_mode(ofnode node)
> return USB_DR_MODE_UNKNOWN;
> }
>
> +enum usb_dr_mode usb_get_role_switch_default_mode(ofnode node)
> +{
> + const char *dr_mode;
> + int i;
> +
> + dr_mode = ofnode_read_string(node, "role-switch-default-mode");
> + if (!dr_mode)
> + return USB_DR_MODE_UNKNOWN;
> +
> + for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
> + if (!strcmp(dr_mode, usb_dr_modes[i]))
> + return i;
> +
> + return USB_DR_MODE_UNKNOWN;
> +}
> +
> static const char *const speed_names[] = {
> [USB_SPEED_UNKNOWN] = "UNKNOWN",
> [USB_SPEED_LOW] = "low-speed",
> diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
> index bec0d98081..1dbd65dfaa 100644
> --- a/drivers/usb/host/xhci-dwc3.c
> +++ b/drivers/usb/host/xhci-dwc3.c
> @@ -209,6 +209,12 @@ static int xhci_dwc3_probe(struct udevice *dev)
> writel(reg, &dwc3_reg->g_usb2phycfg[0]);
>
> dr_mode = usb_get_dr_mode(dev_ofnode(dev));
> + if (dr_mode == USB_DR_MODE_OTG &&
> + dev_read_bool(dev, "usb-role-switch")) {
> + dr_mode = usb_get_role_switch_default_mode(dev_ofnode(dev));
> + if (dr_mode == USB_DR_MODE_UNKNOWN)
> + dr_mode = USB_DR_MODE_OTG;
> + }
> if (dr_mode == USB_DR_MODE_UNKNOWN)
> /* by default set dual role mode to HOST */
> dr_mode = USB_DR_MODE_HOST;
> diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
> index c19b916be9..5d0dac950e 100644
> --- a/include/linux/usb/otg.h
> +++ b/include/linux/usb/otg.h
> @@ -27,6 +27,16 @@ enum usb_dr_mode {
> */
> enum usb_dr_mode usb_get_dr_mode(ofnode node);
>
> +/**
> + * usb_get_dr_mode() - Get dual role mode for given device
> + * @node: ofnode of the given device
> + *
> + * The function gets phy interface string from property
> + * 'role-switch-defaulr-mode', and returns the correspondig enum
> + * usb_dr_mode
> + */
> +enum usb_dr_mode usb_get_role_switch_default_mode(ofnode node);
> +
> /**
> * usb_get_maximum_speed() - Get maximum speed for given device
> * @node: ofnode of the given device
> --
> 2.35.1
>
>
Re: [ANN] U-Boot v2022.07-rc2 released
On Tue, May 10, 2022 at 01:37:53PM +0200, Pali Rohár wrote: > On Monday 09 May 2022 12:50:42 Tom Rini wrote: > > Hey all, > > > > It's release day and so here's v2022.07-rc2. I believe things are > > largely caught up in terms of big outstanding changes but if you know of > > something you were expecting to be in by now, and is not, please speak > > up. > > There are still more powerpc fixes which are not in v2022.07-rc2. > I created "bundle" on patchwork for easier tracking: > https://patchwork.ozlabs.org/bundle/pali/powerpc/ Thanks. For: https://patchwork.ozlabs.org/project/uboot/patch/20220406213153.30437-1-p...@kernel.org/ please follow-up and ask the maintainers to comment. > Important is patch which fixes regression introduced in v2022.07-rc2 > which broke NOR booting. Are anything other than the first two patches there regression fixes? -- Tom signature.asc Description: PGP signature
Re: [PATCH] SPL: Do not allow enabling SPL symbols for non-SPL builds
On Tue, May 10, 2022 at 01:29:30PM +0200, Pali Rohár wrote: > On Monday 09 May 2022 16:22:50 Tom Rini wrote: > > On Mon, May 09, 2022 at 08:53:50PM +0200, Pali Rohár wrote: > > > > > It does not make sense to enable SPL options when not building SPL binary. > > > > > > So disallow selecting SPL options for non-SPL builds. > > > > > > Signed-off-by: Pali Rohár > > > > Some of this makes sense, where you add SPL as an explicit dependency. > > But others: > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > index 0afec5155b1b..e4b2b76650fe 100644 > > > --- a/arch/arm/Kconfig > > > +++ b/arch/arm/Kconfig > > > @@ -985,7 +985,7 @@ config ARCH_MX6 > > > imply SYS_THUMB_BUILD > > > imply SPL_SEPARATE_BSS > > > > > > -if ARCH_MX6 > > > +if ARCH_MX6 && SPL > > > config SPL_LDSCRIPT > > > default "arch/arm/mach-omap2/u-boot-spl.lds" > > > endif > > > @@ -2343,7 +2343,11 @@ source "arch/arm/Kconfig.debug" > > > > > > endmenu > > > > > > +if SPL > > > + > > > config SPL_LDSCRIPT > > > default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || > > > ARCH_MX28) && !SPL_FRAMEWORK > > > default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 > > > default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 > > > + > > > +endif > > > > Where it's like this and we're providing default values and the option > > itself is prompt'd elsewhere don't as it's not cluttering the resulting > > .config file. > > Apparently it clutters the resulting .config file. Espressobin with > mvebu_espressobin-88f3720_defconfig has CONFIG_SPL_LDSCRIPT in .config > even there is no SPL for Espressobin. Ah, OK, that is odd. I think we need to move these to where the question is asked then, instead. -- Tom signature.asc Description: PGP signature
Re: [Uboot-stm32] [PATCH 2/4] clk: stm32mp13: add a STM32MP13 RCC clock driver
Hi, On Tue, May 10, 2022 at 09:51:11AM +0200, Patrick Delaunay wrote: > Introduce a minimal STM32MP13 RCC driver only to allow bind of RCC MISC > driver. Consider s/only/just/ and s/bind of/binding of the/. > diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile > -%<- > obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o > +obj-$(CONFIG_CLK_STM32MP13) += clk-stm32mp13.o > \ No newline at end of file Could you add a newline here? I think it was there in the previous patch. Also, note that the new file name seems to break the convention of using underscores. All the best -- Grzegorz signature.asc Description: PGP signature
Re: [Uboot-stm32] [PATCH] phy: stm32-usbphyc: stm32-usbphyc: Add DT phy tuning support
My Bad, this patch is not concerned, i keep it merged in STM32 custodian master. On 5/10/22 13:50, Patrice CHOTARD wrote: > After discussion with Patrick, the whole series will not be merged in stm32 > git custodian master branch > > Patrice > > On 5/10/22 10:10, Patrice CHOTARD wrote: >> >> >> On 5/6/22 10:50, Patrick DELAUNAY wrote: >>> Hi >>> >>> On 4/22/22 09:39, Patrice Chotard wrote: Add support of phy-tuning properties for sm32-usbphyc's phy tuning aligned with v5.15 kernel bindings. Signed-off-by: Patrice Chotard --- drivers/phy/phy-stm32-usbphyc.c | 167 1 file changed, 167 insertions(+) >>> >>> Reviewed-by: Patrick Delaunay >>> >>> Thanks >>> Patrick >>> >>> >> Applied to u-boot-stm32 >> >> Thanks >> Patrice > ___ > Uboot-stm32 mailing list > uboot-st...@st-md-mailman.stormreply.com > https://st-md-mailman.stormreply.com/mailman/listinfo/uboot-stm32
Re: [Uboot-stm32] [PATCH 1/3] phy: stm32-usbphyc: add counter of PLL consumer
On 5/10/22 09:45, Patrice CHOTARD wrote:
>
>
> On 5/6/22 16:18, Patrice CHOTARD wrote:
>> Hi Patrick
>>
>> On 4/26/22 14:37, Patrick Delaunay wrote:
>>> Add the counter of the PLL user n_pll_cons managed by the 2 functions
>>> stm32_usbphyc_pll_enable / stm32_usbphyc_pll_disable.
>>>
>>> This counter allow to remove the function stm32_usbphyc_is_init
>>> and it is a preliminary step for ck_usbo_48m introduction.
>>>
>>> Signed-off-by: Patrick Delaunay
>>> ---
>>>
>>> drivers/phy/phy-stm32-usbphyc.c | 76 +
>>> 1 file changed, 48 insertions(+), 28 deletions(-)
>>>
>>> diff --git a/drivers/phy/phy-stm32-usbphyc.c
>>> b/drivers/phy/phy-stm32-usbphyc.c
>>> index 9c1dcfae52..16c8799eca 100644
>>> --- a/drivers/phy/phy-stm32-usbphyc.c
>>> +++ b/drivers/phy/phy-stm32-usbphyc.c
>>> @@ -65,6 +65,7 @@ struct stm32_usbphyc {
>>> bool init;
>>> bool powered;
>>> } phys[MAX_PHYS];
>>> + int n_pll_cons;
>>> };
>>>
>>> static void stm32_usbphyc_get_pll_params(u32 clk_rate,
>>> @@ -124,18 +125,6 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc
>>> *usbphyc)
>>> return 0;
>>> }
>>>
>>> -static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
>>> -{
>>> - int i;
>>> -
>>> - for (i = 0; i < MAX_PHYS; i++) {
>>> - if (usbphyc->phys[i].init)
>>> - return true;
>>> - }
>>> -
>>> - return false;
>>> -}
>>> -
>>> static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
>>> {
>>> int i;
>>> @@ -148,18 +137,17 @@ static bool stm32_usbphyc_is_powered(struct
>>> stm32_usbphyc *usbphyc)
>>> return false;
>>> }
>>>
>>> -static int stm32_usbphyc_phy_init(struct phy *phy)
>>> +static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
>>> {
>>> - struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
>>> - struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
>>> bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
>>> true : false;
>>> int ret;
>>>
>>> - dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
>>> - /* Check if one phy port has already configured the pll */
>>> - if (pllen && stm32_usbphyc_is_init(usbphyc))
>>> - goto initialized;
>>> + /* Check if one consumer has already configured the pll */
>>> + if (pllen && usbphyc->n_pll_cons) {
>>> + usbphyc->n_pll_cons++;
>>> + return 0;
>>> + }
>>>
>>> if (usbphyc->vdda1v1) {
>>> ret = regulator_set_enable(usbphyc->vdda1v1, true);
>>> @@ -190,23 +178,19 @@ static int stm32_usbphyc_phy_init(struct phy *phy)
>>> if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
>>> return -EIO;
>>>
>>> -initialized:
>>> - usbphyc_phy->init = true;
>>> + usbphyc->n_pll_cons++;
>>>
>>> return 0;
>>> }
>>>
>>> -static int stm32_usbphyc_phy_exit(struct phy *phy)
>>> +static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
>>> {
>>> - struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
>>> - struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
>>> int ret;
>>>
>>> - dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
>>> - usbphyc_phy->init = false;
>>> + usbphyc->n_pll_cons--;
>>>
>>> - /* Check if other phy port requires pllen */
>>> - if (stm32_usbphyc_is_init(usbphyc))
>>> + /* Check if other consumer requires pllen */
>>> + if (usbphyc->n_pll_cons)
>>> return 0;
>>>
>>> clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
>>> @@ -235,6 +219,42 @@ static int stm32_usbphyc_phy_exit(struct phy *phy)
>>> return 0;
>>> }
>>>
>>> +static int stm32_usbphyc_phy_init(struct phy *phy)
>>> +{
>>> + struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
>>> + struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
>>> + int ret;
>>> +
>>> + dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
>>> + if (usbphyc_phy->init)
>>> + return 0;
>>> +
>>> + ret = stm32_usbphyc_pll_enable(usbphyc);
>>> + if (ret)
>>> + return log_ret(ret);
>>> +
>>> + usbphyc_phy->init = true;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int stm32_usbphyc_phy_exit(struct phy *phy)
>>> +{
>>> + struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
>>> + struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
>>> + int ret;
>>> +
>>> + dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
>>> + if (!usbphyc_phy->init)
>>> + return 0;
>>> +
>>> + ret = stm32_usbphyc_pll_disable(usbphyc);
>>> +
>>> + usbphyc_phy->init = false;
>>> +
>>> + return log_ret(ret);
>>> +}
>>> +
>>> static int stm32_usbphyc_phy_power_on(struct phy *phy)
>>> {
>>> struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
>> Reviewed-by: Patrice Chotard
>>
>> Thanks
>> Patrice
After discussion with Patrick, the whole series will not be merged in stm32 git
custodian master branch
Patrice
>> _
Re: [PATCH] phy: stm32-usbphyc: stm32-usbphyc: Add DT phy tuning support
After discussion with Patrick, the whole series will not be merged in stm32 git custodian master branch Patrice On 5/10/22 10:10, Patrice CHOTARD wrote: > > > On 5/6/22 10:50, Patrick DELAUNAY wrote: >> Hi >> >> On 4/22/22 09:39, Patrice Chotard wrote: >>> Add support of phy-tuning properties for sm32-usbphyc's phy tuning >>> aligned with v5.15 kernel bindings. >>> >>> Signed-off-by: Patrice Chotard >>> --- >>> >>> drivers/phy/phy-stm32-usbphyc.c | 167 >>> 1 file changed, 167 insertions(+) >>> >> >> Reviewed-by: Patrick Delaunay >> >> Thanks >> Patrick >> >> > Applied to u-boot-stm32 > > Thanks > Patrice
Re: [ANN] U-Boot v2022.07-rc2 released
On Monday 09 May 2022 12:50:42 Tom Rini wrote: > Hey all, > > It's release day and so here's v2022.07-rc2. I believe things are > largely caught up in terms of big outstanding changes but if you know of > something you were expecting to be in by now, and is not, please speak > up. There are still more powerpc fixes which are not in v2022.07-rc2. I created "bundle" on patchwork for easier tracking: https://patchwork.ozlabs.org/bundle/pali/powerpc/ Important is patch which fixes regression introduced in v2022.07-rc2 which broke NOR booting.
RE: [PATCH 0/3] xilinx: Swith platforms to DM_ETH_PHY
Acked-for-series: Ashok Reddy Soma Thanks, Ashok > -Original Message- > From: U-Boot On Behalf Of Michal Simek > Sent: Tuesday, May 10, 2022 4:56 PM > To: u-boot@lists.denx.de; git > Cc: Joe Hershberger ; Ramon Fried > > Subject: [PATCH 0/3] xilinx: Swith platforms to DM_ETH_PHY > > > This patch series adds support for shared MDIO by using generic phy > framework. Also enable DM_ETH_PHY config for all xilinx platforms. > > Thanks, > Michal > > > T Karthik Reddy (3): > net: xilinx: axi_emac: Use shared MDIO bus support for axi emac driver > net: xilinx: axi_emaclite: Use shared MDIO bus support for axi > emaclite driver > xilinx: Add CONFIG_DM_ETH_PHY config > > configs/microblaze-generic_defconfig | 1 + > configs/xilinx_versal_virt_defconfig | 1 + > configs/xilinx_zynq_virt_defconfig | 1 + > configs/xilinx_zynqmp_virt_defconfig | 1 + > drivers/net/xilinx_axi_emac.c| 38 > drivers/net/xilinx_emaclite.c| 43 ++-- > 6 files changed, 58 insertions(+), 27 deletions(-) > > -- > 2.36.0
Re: [PATCH 1/3] phy: stm32-usbphyc: add counter of PLL consumer
Hi Patrick,
Hi Sean,
On 5/9/22 16:37, Patrick DELAUNAY wrote:
Hi Sean,
On 5/8/22 20:21, Sean Anderson wrote:
On 4/26/22 8:37 AM, Patrick Delaunay wrote:
Add the counter of the PLL user n_pll_cons managed by the 2 functions
stm32_usbphyc_pll_enable / stm32_usbphyc_pll_disable.
This counter allow to remove the function stm32_usbphyc_is_init
and it is a preliminary step for ck_usbo_48m introduction.
Is it necessary to disable this clock before booting to Linux? If it
isn't,
then perhaps it is simpler to just not disable the clock.
--Sean
No, it is not necessary, we only need to enable the clock for the first
user.
I copy the clock behavior from kernel,
but I agree that can be simpler.
Amelie any notice about this point ?
Do you prefer that I kept the behavior - same as kernel driver - or I
simplify the U-Boot driver ?
In case the PLL has not been disabled before Kernel boot, usbphyc Kernel
driver will wait for the PLL pwerdown.
USB could also not being used in Kernel, so PLL would remain enabled,
and would waste power.
I am rather in favor of disabling the PLL.
Regards,
Amelie
Patrick
Signed-off-by: Patrick Delaunay
---
drivers/phy/phy-stm32-usbphyc.c | 76 +
1 file changed, 48 insertions(+), 28 deletions(-)
diff --git a/drivers/phy/phy-stm32-usbphyc.c
b/drivers/phy/phy-stm32-usbphyc.c
index 9c1dcfae52..16c8799eca 100644
--- a/drivers/phy/phy-stm32-usbphyc.c
+++ b/drivers/phy/phy-stm32-usbphyc.c
@@ -65,6 +65,7 @@ struct stm32_usbphyc {
bool init;
bool powered;
} phys[MAX_PHYS];
+ int n_pll_cons;
};
static void stm32_usbphyc_get_pll_params(u32 clk_rate,
@@ -124,18 +125,6 @@ static int stm32_usbphyc_pll_init(struct
stm32_usbphyc *usbphyc)
return 0;
}
-static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
-{
- int i;
-
- for (i = 0; i < MAX_PHYS; i++) {
- if (usbphyc->phys[i].init)
- return true;
- }
-
- return false;
-}
-
static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
{
int i;
@@ -148,18 +137,17 @@ static bool stm32_usbphyc_is_powered(struct
stm32_usbphyc *usbphyc)
return false;
}
-static int stm32_usbphyc_phy_init(struct phy *phy)
+static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
{
- struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
- struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
true : false;
int ret;
- dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
- /* Check if one phy port has already configured the pll */
- if (pllen && stm32_usbphyc_is_init(usbphyc))
- goto initialized;
+ /* Check if one consumer has already configured the pll */
+ if (pllen && usbphyc->n_pll_cons) {
+ usbphyc->n_pll_cons++;
+ return 0;
+ }
if (usbphyc->vdda1v1) {
ret = regulator_set_enable(usbphyc->vdda1v1, true);
@@ -190,23 +178,19 @@ static int stm32_usbphyc_phy_init(struct phy *phy)
if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
return -EIO;
-initialized:
- usbphyc_phy->init = true;
+ usbphyc->n_pll_cons++;
return 0;
}
-static int stm32_usbphyc_phy_exit(struct phy *phy)
+static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
{
- struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
- struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
- dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
- usbphyc_phy->init = false;
+ usbphyc->n_pll_cons--;
- /* Check if other phy port requires pllen */
- if (stm32_usbphyc_is_init(usbphyc))
+ /* Check if other consumer requires pllen */
+ if (usbphyc->n_pll_cons)
return 0;
clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
@@ -235,6 +219,42 @@ static int stm32_usbphyc_phy_exit(struct phy *phy)
return 0;
}
+static int stm32_usbphyc_phy_init(struct phy *phy)
+{
+ struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
+ struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
+ int ret;
+
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
+ if (usbphyc_phy->init)
+ return 0;
+
+ ret = stm32_usbphyc_pll_enable(usbphyc);
+ if (ret)
+ return log_ret(ret);
+
+ usbphyc_phy->init = true;
+
+ return 0;
+}
+
+static int stm32_usbphyc_phy_exit(struct phy *phy)
+{
+ struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
+ struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
+ int ret;
+
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
+ if (!usbphyc_phy->init)
+ return 0;
+
+ ret = stm32_usbphyc_pll_disable(usbphyc);
+
+ usbphyc_phy->init = false;
+
+ return log_ret(ret);
+}
+
static int stm32_usbphyc_phy_power_on(struct phy *phy)
{
struct stm32_usbphyc *usbphyc = dev
[PATCH] arm:socfpga:soc64: To notify SDM when U-Boot pass control to Linux
From: Dinesh Maniyam
Prior U-Boot pass control to Linux, U-Boot will send a mailbox command
"HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on HPS SW
transition.
Signed-off-by: Chin Liang See
Signed-off-by: Dinesh Maniyam
---
arch/arm/mach-socfpga/misc_soc64.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc_soc64.c
b/arch/arm/mach-socfpga/misc_soc64.c
index 2acdfad07b..3148eb46a5 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -89,3 +89,8 @@ void do_bridge_reset(int enable, unsigned int mask)
socfpga_bridges_reset(enable);
}
+
+void arch_preboot_os(void)
+{
+ mbox_hps_stage_notify(HPS_EXECUTION_STATE_OS);
+}
\ No newline at end of file
--
2.26.2
[PATCH] ddr:altera:soc64: Integer fix overflow that caused DDR size mismatched
From: Dinesh Maniyam
Convert the constant integer to 'phys_size_t' to avoid overflow
when calculating the SDRAM size.
Signed-off-by: Chee Hong Ang
Signed-off-by: Dinesh Maniyam
---
drivers/ddr/altera/sdram_soc64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index d6baac2410..1f479c514d 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -239,7 +239,8 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat
*plat)
{
u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
- phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+ phys_size_t size = (phys_size_t)1 <<
+ (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
--
2.26.2
Re: [PATCH] SPL: Do not allow enabling SPL symbols for non-SPL builds
On Monday 09 May 2022 16:22:50 Tom Rini wrote: > On Mon, May 09, 2022 at 08:53:50PM +0200, Pali Rohár wrote: > > > It does not make sense to enable SPL options when not building SPL binary. > > > > So disallow selecting SPL options for non-SPL builds. > > > > Signed-off-by: Pali Rohár > > Some of this makes sense, where you add SPL as an explicit dependency. > But others: > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index 0afec5155b1b..e4b2b76650fe 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -985,7 +985,7 @@ config ARCH_MX6 > > imply SYS_THUMB_BUILD > > imply SPL_SEPARATE_BSS > > > > -if ARCH_MX6 > > +if ARCH_MX6 && SPL > > config SPL_LDSCRIPT > > default "arch/arm/mach-omap2/u-boot-spl.lds" > > endif > > @@ -2343,7 +2343,11 @@ source "arch/arm/Kconfig.debug" > > > > endmenu > > > > +if SPL > > + > > config SPL_LDSCRIPT > > default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || > > ARCH_MX28) && !SPL_FRAMEWORK > > default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 > > default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 > > + > > +endif > > Where it's like this and we're providing default values and the option > itself is prompt'd elsewhere don't as it's not cluttering the resulting > .config file. Apparently it clutters the resulting .config file. Espressobin with mvebu_espressobin-88f3720_defconfig has CONFIG_SPL_LDSCRIPT in .config even there is no SPL for Espressobin. > > diff --git a/lib/Kconfig b/lib/Kconfig > > index acc0ac081a44..299381ac80d5 100644 > > --- a/lib/Kconfig > > +++ b/lib/Kconfig > > @@ -239,6 +239,7 @@ config GENERATE_ACPI_TABLE > > > > config SPL_TINY_MEMSET > > bool "Use a very small memset() in SPL" > > + depends on SPL > > help > > The faster memset() is the arch-specific one (if available) enabled > > by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get > > @@ -556,6 +557,7 @@ config MD5 > > > > config SPL_MD5 > > bool "Support MD5 algorithm in SPL" > > + depends on SPL > > help > > This option enables MD5 support in SPL. MD5 is an algorithm designed > > in 1991 that produces a 16-byte digest (or checksum) from its input > > @@ -642,6 +644,7 @@ config ZSTD > > > > config SPL_LZ4 > > bool "Enable LZ4 decompression support in SPL" > > + depends on SPL > > help > > This enables support for the LZ4 decompression algorithm in SPL. LZ4 > > is a lossless data compression algorithm that is focused on > > @@ -650,6 +653,7 @@ config SPL_LZ4 > > > > config SPL_LZMA > > bool "Enable LZMA decompression support for SPL build" > > + depends on SPL > > help > > This enables support for LZMA compression algorithm for SPL boot. > > > > @@ -661,22 +665,26 @@ config VPL_LZMA > > > > config SPL_LZO > > bool "Enable LZO decompression support in SPL" > > + depends on SPL > > help > > This enables support for LZO compression algorithm in the SPL. > > > > config SPL_GZIP > > bool "Enable gzip decompression support for SPL build" > > + depends on SPL > > select SPL_ZLIB > > help > > This enables support for the GZIP compression algorithm for SPL boot. > > > > config SPL_ZLIB > > bool > > + depends on SPL > > help > > This enables compression lib for SPL boot. > > > > config SPL_ZSTD > > bool "Enable Zstandard decompression support in SPL" > > + depends on SPL > > select XXHASH > > help > > This enables Zstandard decompression library in the SPL. > > Most of these should all be under one big if SPL ... endif > > -- > Tom Ok, I can change it.
Re: [PATCH 0/2] powerpc: mpc85xx: Fix NOR booting
On Monday 02 May 2022 18:36:37 Pali Rohár wrote:
> NOR version of U-Boot for mpc85xx is currently broken.
>
> NOR booting with CONFIG_OF_SEPARATE is broken since my commit
> e8c0e0064c8a ("powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support") which
> was merged into master few days ago and was fixing SD card booting.
PING. v2022.07-rc2 was already released with with above commit!
> NOR booting with CONFIG_OF_EMBED seems to be broken for a longer time.
>
> This patch series fix it. Tested on P2020 board, both SD and NOR booting
> with CONFIG_OF_SEPARATE and also with CONFIG_OF_EMBED.
>
> Pali Rohár (2):
> powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support for NOR booting
> powerpc: mpc85xx: Fix CONFIG_OF_EMBED support for NOR booting
>
> Makefile | 2 +-
> arch/powerpc/dts/u-boot.dtsi | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> --
> 2.20.1
>
[PATCH 2/3] net: xilinx: axi_emaclite: Use shared MDIO bus support for axi emaclite driver
From: T Karthik Reddy
CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy
framework. Though if ethernet PHY node is in other ethernet node, it
will use shared MDIO to access the PHY of other ethernet. Move ethernet
print info statement from plat function to probe function, as phyaddr is
not enumerated when CONFIG_DM_ETH_PHY is enabled.
Signed-off-by: T Karthik Reddy
Signed-off-by: Michal Simek
---
drivers/net/xilinx_emaclite.c | 43 +++
1 file changed, 28 insertions(+), 15 deletions(-)
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 43fc36dc6a82..6c9f1f7c2728 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -564,14 +565,27 @@ static int emaclite_probe(struct udevice *dev)
struct xemaclite *emaclite = dev_get_priv(dev);
int ret;
- emaclite->bus = mdio_alloc();
- emaclite->bus->read = emaclite_miiphy_read;
- emaclite->bus->write = emaclite_miiphy_write;
- emaclite->bus->priv = emaclite;
+ if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+ emaclite->bus = eth_phy_get_mdio_bus(dev);
- ret = mdio_register_seq(emaclite->bus, dev_seq(dev));
- if (ret)
- return ret;
+ if (!emaclite->bus) {
+ emaclite->bus = mdio_alloc();
+ emaclite->bus->read = emaclite_miiphy_read;
+ emaclite->bus->write = emaclite_miiphy_write;
+ emaclite->bus->priv = emaclite;
+
+ ret = mdio_register_seq(emaclite->bus, dev_seq(dev));
+ if (ret)
+ return ret;
+ }
+
+ if (IS_ENABLED(CONFIG_DM_ETH_PHY)) {
+ eth_phy_set_mdio_bus(dev, emaclite->bus);
+ emaclite->phyaddr = eth_phy_get_addr(dev);
+ }
+
+ printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
+ emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
return 0;
}
@@ -606,20 +620,19 @@ static int emaclite_of_to_plat(struct udevice *dev)
emaclite->phyaddr = -1;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
- "phy-handle");
- if (offset > 0)
- emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
- "reg", -1);
+ if (!(IS_ENABLED(CONFIG_DM_ETH_PHY))) {
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
+ "phy-handle");
+ if (offset > 0)
+ emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob,
+ offset, "reg", -1);
+ }
emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,tx-ping-pong", 0);
emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,rx-ping-pong", 0);
- printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
- emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
-
return 0;
}
--
2.36.0
[PATCH 3/3] xilinx: Add CONFIG_DM_ETH_PHY config
From: T Karthik Reddy Enable CONFIG_DM_ETH_PHY to utilize shared MDIO bus support on all xilinx platforms. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- configs/microblaze-generic_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 3142b469c26b..7994110b28a7 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -76,6 +76,7 @@ CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y CONFIG_XILINX_AXIEMAC=y CONFIG_XILINX_EMACLITE=y CONFIG_SYS_NS16550=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 38747ffd02cb..c9ae0185f8ad 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -92,6 +92,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI_DP83867=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y +CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y CONFIG_XILINX_AXIEMAC=y CONFIG_XILINX_AXIMRMAC=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 1f3e6a42a146..120bc29393d8 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -111,6 +111,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_REALTEK=y CONFIG_PHY_XILINX=y +CONFIG_DM_ETH_PHY=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_ARM_DCC=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 35894076c52f..abaebb8edaf2 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -160,6 +160,7 @@ CONFIG_PHY_TI_DP83867=y CONFIG_PHY_VITESSE=y CONFIG_PHY_XILINX_GMII2RGMII=y CONFIG_PHY_FIXED=y +CONFIG_DM_ETH_PHY=y CONFIG_XILINX_AXIEMAC=y CONFIG_ZYNQ_GEM=y CONFIG_DM_REGULATOR=y -- 2.36.0
[PATCH 1/3] net: xilinx: axi_emac: Use shared MDIO bus support for axi emac driver
From: T Karthik Reddy
CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy
framework. Though if ethernet PHY node is in other ethernet node, it
will use shared MDIO to access the PHY of other ethernet. Move ethernet
print info statement from plat function to probe function, as phyaddr is
not enumerated when CONFIG_DM_ETH_PHY is enabled.
Signed-off-by: T Karthik Reddy
Signed-off-by: Michal Simek
---
drivers/net/xilinx_axi_emac.c | 38 ---
1 file changed, 26 insertions(+), 12 deletions(-)
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index a4715735c3c4..04277b1269f3 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -295,6 +296,9 @@ static int axiemac_phy_init(struct udevice *dev)
/* Set default MDIO divisor */
writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
+ if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+ priv->phyaddr = eth_phy_get_addr(dev);
+
if (priv->phyaddr == -1) {
/* Detect the PHY address */
for (i = 31; i >= 0; i--) {
@@ -778,18 +782,29 @@ static int axi_emac_probe(struct udevice *dev)
priv->phy_of_handle = plat->phy_of_handle;
priv->interface = pdata->phy_interface;
- priv->bus = mdio_alloc();
- priv->bus->read = axiemac_miiphy_read;
- priv->bus->write = axiemac_miiphy_write;
- priv->bus->priv = priv;
+ if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+ priv->bus = eth_phy_get_mdio_bus(dev);
- ret = mdio_register_seq(priv->bus, dev_seq(dev));
- if (ret)
- return ret;
+ if (!priv->bus) {
+ priv->bus = mdio_alloc();
+ priv->bus->read = axiemac_miiphy_read;
+ priv->bus->write = axiemac_miiphy_write;
+ priv->bus->priv = priv;
+
+ ret = mdio_register_seq(priv->bus, dev_seq(dev));
+ if (ret)
+ return ret;
+ }
+
+ if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+ eth_phy_set_mdio_bus(dev, priv->bus);
axiemac_phy_init(dev);
}
+ printf("AXI EMAC: %lx, phyaddr %d, interface %s\n",
(ulong)pdata->iobase,
+ priv->phyaddr, phy_string_for_interface(pdata->phy_interface));
+
return 0;
}
@@ -844,8 +859,10 @@ static int axi_emac_of_to_plat(struct udevice *dev)
offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
"phy-handle");
if (offset > 0) {
- plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
- "reg", -1);
+ if (!(IS_ENABLED(CONFIG_DM_ETH_PHY)))
+ plat->phyaddr = fdtdec_get_int(gd->fdt_blob,
+ offset,
+ "reg", -1);
plat->phy_of_handle = offset;
}
@@ -857,9 +874,6 @@ static int axi_emac_of_to_plat(struct udevice *dev)
"xlnx,eth-hasnobuf");
}
- printf("AXI EMAC: %lx, phyaddr %d, interface %s\n",
(ulong)pdata->iobase,
- plat->phyaddr, phy_string_for_interface(pdata->phy_interface));
-
return 0;
}
--
2.36.0
[PATCH 0/3] xilinx: Swith platforms to DM_ETH_PHY
This patch series adds support for shared MDIO by using generic phy framework. Also enable DM_ETH_PHY config for all xilinx platforms. Thanks, Michal T Karthik Reddy (3): net: xilinx: axi_emac: Use shared MDIO bus support for axi emac driver net: xilinx: axi_emaclite: Use shared MDIO bus support for axi emaclite driver xilinx: Add CONFIG_DM_ETH_PHY config configs/microblaze-generic_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + drivers/net/xilinx_axi_emac.c| 38 drivers/net/xilinx_emaclite.c| 43 ++-- 6 files changed, 58 insertions(+), 27 deletions(-) -- 2.36.0
[PATCH] ls1028a: hdp: Add config support for HDP firmware loading
From: Alison Wang
This patch adds config support for HDP firmware loading on LS1028A.
Signed-off-by: Oliver Brown
Signed-off-by: Alison Wang
Signed-off-by: Ye Li
Signed-off-by: Yangbo Lu
---
board/freescale/ls1028a/ls1028a.c| 7 ++-
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 ++
configs/ls1028aqds_tfa_defconfig | 2 ++
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 ++
configs/ls1028ardb_tfa_defconfig | 2 ++
5 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/board/freescale/ls1028a/ls1028a.c
b/board/freescale/ls1028a/ls1028a.c
index 71a086ef67..1a7806fad7 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019, 2021 NXP
+ * Copyright 2019-2022 NXP
*/
#include
@@ -328,3 +328,8 @@ int checkboard(void)
return 0;
}
#endif
+
+void *video_hw_init(void)
+{
+ return NULL;
+}
diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index 2e4db036a4..26613168f1 100644
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -98,3 +98,5 @@ CONFIG_WDT_SP805=y
CONFIG_RSA=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_LS_HDP_LOAD=y
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index 556f77e222..7e66e681fe 100644
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -103,3 +103,5 @@ CONFIG_WDT=y
CONFIG_WDT_SP805=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_LS_HDP_LOAD=y
diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
index 20cb844b01..024f9394b1 100644
--- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
@@ -92,3 +92,5 @@ CONFIG_WDT_SP805=y
CONFIG_RSA=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_LS_HDP_LOAD=y
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index fdfdf39c61..97e979ca97 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -101,3 +101,5 @@ CONFIG_WDT=y
CONFIG_WDT_SP805=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_LS_HDP_LOAD=y
--
2.25.1
Re: [PATCH] efi_loader: fix a problem in loading an image from a short-path
On Fri, Apr 29, 2022 at 12:57:15PM +0200, Heinrich Schuchardt wrote:
> On 4/28/22 06:50, AKASHI Takahiro wrote:
> > Booting from a short-form device path which starts with the first element
> > being a File Path Media Device Path failed because it doesn't contain
> > any valid device with simple file system protocol and efi_dp_find_obj()
> > in efi_load_image_from_path() will return NULL.
> > For instance,
> > /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/Scsi(0,0)/\helloworld.efi
> >-> shortened version: /\helloworld.efi
>
> Thanks for enabling this.
>
> Please, enhance test/py/tests/test_efi_bootmgr to test booting from a
> filename only device path.
Okay, but you should have added tests in your patch.
> >
> > With this patch applied, all the media devices with simple file system
> > protocol are enumerated and the boot manager attempts to boot temporarily
> > generated device paths one-by-one.
> >
> > This new implementation is still a bit incompatible with the UEFI
> > specification in terms of:
> > * not creating real boot options
>
> The UEFI specification has:
>
> "These new boot options must not be saved to non volatile storage,
> and may not be added to BootOrder."
>
> Is there really something missing?
When the boot manager attempts to boot a short-form File Path
Media Device Path, it will enumerate all removable media devices,
followed
by all fixed media devices, creating boot options for each device.
^
> > * not distinguishing removable media and fix media
>
> struct blk_desc has field 'removable' which is mirrored in struct
> efi_disk_obj.
Instead of relying on such an internal structure, we can and should
use a public interface, efi_block_io(->media.removable_media).
> mmc_bind() always sets removable to 1 irrespective of the device being
> eMMC or SD-card. I guess this would need to be fixed.
>
> > (See section 3.1.3 "Boot Options".)
> >
> > But it still gives us a closer and better solution than the current.
> >
> > Fixes: commit 9cdf470274ff ("efi_loader: support booting via short-form
> > device-path")
> > Signed-off-by: AKASHI Takahiro
> > ---
> > include/efi_loader.h | 3 ++
> > lib/efi_loader/efi_boottime.c | 87 +++
> > lib/efi_loader/efi_file.c | 35 ++
> > 3 files changed, 107 insertions(+), 18 deletions(-)
> >
> > diff --git a/include/efi_loader.h b/include/efi_loader.h
> > index ba79a9afb404..9730c1375a55 100644
> > --- a/include/efi_loader.h
> > +++ b/include/efi_loader.h
> > @@ -661,6 +661,9 @@ void efi_signal_event(struct efi_event *event);
> > struct efi_simple_file_system_protocol *efi_simple_file_system(
> > struct blk_desc *desc, int part, struct efi_device_path *dp);
> >
> > +/* open file from simple file system */
> > +struct efi_file_handle *efi_file_from_fs(struct
> > efi_simple_file_system_protocol *v,
> > +struct efi_device_path *fp);
> > /* open file from device-path: */
> > struct efi_file_handle *efi_file_from_path(struct efi_device_path *fp);
> >
> > diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
> > index 5bcb8253edba..39b0e8f7ade0 100644
> > --- a/lib/efi_loader/efi_boottime.c
> > +++ b/lib/efi_loader/efi_boottime.c
> > @@ -1868,19 +1868,21 @@ out:
> > }
> >
> > /**
> > - * efi_load_image_from_file() - load an image from file system
> > + * __efi_load_image_from_file() - load an image from file system
> >*
> >* Read a file into a buffer allocated as EFI_BOOT_SERVICES_DATA. It is
> > the
> >* callers obligation to update the memory type as needed.
> >*
> > + * @v: simple file system
>
> Please, use a meaningful variable name.
I will fully re-write this patch.
While efi boot manager should be responsible for handling a short-form device
path
starting with a file path, my current implementation is made in
efi_load_image_from_path() hence LoadImage API.
Instead, the logic of enumerating file_system_protocol devices will be added
to try_load_entry()/efi_bootmgr_load().
-Takahiro Akashi
> >* @file_path:the path of the image to load
> >* @buffer: buffer containing the loaded image
> >* @size: size of the loaded image
> >* Return:status code
> >*/
> > static
> > -efi_status_t efi_load_image_from_file(struct efi_device_path *file_path,
> > - void **buffer, efi_uintn_t *size)
> > +efi_status_t __efi_load_image_from_file(struct
> > efi_simple_file_system_protocol *v,
> > + struct efi_device_path *file_path,
> > + void **buffer, efi_uintn_t *size)
> > {
> > struct efi_file_handle *f;
> > efi_status_t ret;
> > @@ -1888,7 +1890,11 @@ efi_status_t efi_load_image_from_file(struct
> > efi_device_path *f
RE: [PATCH V2 5/7] ddr: imx8m: helper: load ddr firmware according to binman symbols
Tim,
> Subject: Re: [PATCH V2 5/7] ddr: imx8m: helper: load ddr firmware according to
> binman symbols
>
> On Sat, May 7, 2022 at 3:22 AM Peng Fan (OSS) wrote:
> >
> > From: Peng Fan
> >
> > By reading binman symbols, we no need hard coded IMEM_LEN/DMEM_LEN
> > after we update the binman dtsi to drop 0x8000/0x4000 length for the
> firmware.
> >
> > And that could save binary size for many KBs.
> >
> > Signed-off-by: Peng Fan
> > ---
> > drivers/ddr/imx/imx8m/helper.c | 53
> > --
> > 1 file changed, 44 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/ddr/imx/imx8m/helper.c
> > b/drivers/ddr/imx/imx8m/helper.c index f23904bf712..b10ba602665 100644
> > --- a/drivers/ddr/imx/imx8m/helper.c
> > +++ b/drivers/ddr/imx/imx8m/helper.c
> > @@ -4,6 +4,7 @@
> > */
> >
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -25,15 +26,30 @@ DECLARE_GLOBAL_DATA_PTR; #define
> DMEM_OFFSET_ADDR
> > 0x00054000 #define DDR_TRAIN_CODE_BASE_ADDR
> > IP2APB_DDRPHY_IPS_BASE_ADDR(0)
> >
> > +binman_sym_declare(ulong, blob_ext_1, image_pos);
> > +binman_sym_declare(ulong, blob_ext_1, size);
> > +
> > +binman_sym_declare(ulong, blob_ext_2, image_pos);
> > +binman_sym_declare(ulong, blob_ext_2, size);
> > +
> > +#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
> > +binman_sym_declare(ulong, blob_ext_3, image_pos);
> > +binman_sym_declare(ulong, blob_ext_3, size);
> > +
> > +binman_sym_declare(ulong, blob_ext_4, image_pos);
> > +binman_sym_declare(ulong, blob_ext_4, size); #endif
> > +
> > /* We need PHY iMEM PHY is 32KB padded */ void
> > ddr_load_train_firmware(enum fw_type type) {
> > u32 tmp32, i;
> > u32 error = 0;
> > - unsigned long pr_to32, pr_from32;
> > - unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
> > - unsigned long imem_start = (unsigned long)&_end + fw_offset;
> > - unsigned long dmem_start;
> > + uint32_t pr_to32, pr_from32;
> > + uint32_t fw_offset = type ? IMEM_2D_OFFSET : 0;
> > + uint32_t imem_start = (uint32_t)&_end + fw_offset;
> > + uint32_t dmem_start;
> > + uint32_t imem_len = IMEM_LEN, dmem_len = DMEM_LEN;
> >
> > #ifdef CONFIG_SPL_OF_CONTROL
> > if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) { @@
> > -43,11 +59,30 @@ void ddr_load_train_firmware(enum fw_type type)
> > }
> > #endif
> >
> > - dmem_start = imem_start + IMEM_LEN;
> > + if (CONFIG_IS_ENABLED(BINMAN_SYMBOLS)) {
> > + switch (type) {
> > + case FW_1D_IMAGE:
> > + imem_start = binman_sym(ulong, blob_ext_1,
> > image_pos);
> > + imem_len = binman_sym(ulong, blob_ext_1, size);
> > + dmem_start = binman_sym(ulong, blob_ext_2,
> > image_pos);
> > + dmem_len = binman_sym(ulong, blob_ext_2, size);
> > + break;
> > + case FW_2D_IMAGE:
> > +#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
> > + imem_start = binman_sym(ulong, blob_ext_3,
> > image_pos);
> > + imem_len = binman_sym(ulong, blob_ext_3, size);
> > + dmem_start = binman_sym(ulong, blob_ext_4,
> > image_pos);
> > + dmem_len = binman_sym(ulong, blob_ext_4,
> > +size); #endif
> > + break;
> > + }
> > + }
> > +
> > + dmem_start = imem_start + imem_len;
> >
> > pr_from32 = imem_start;
> > pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
> > - for (i = 0x0; i < IMEM_LEN; ) {
> > + for (i = 0x0; i < imem_len; ) {
> > tmp32 = readl(pr_from32);
> > writew(tmp32 & 0x, pr_to32);
> > pr_to32 += 4;
> > @@ -59,7 +94,7 @@ void ddr_load_train_firmware(enum fw_type type)
> >
> > pr_from32 = dmem_start;
> > pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
> > - for (i = 0x0; i < DMEM_LEN; ) {
> > + for (i = 0x0; i < dmem_len; ) {
> > tmp32 = readl(pr_from32);
> > writew(tmp32 & 0x, pr_to32);
> > pr_to32 += 4;
> > @@ -72,7 +107,7 @@ void ddr_load_train_firmware(enum fw_type type)
> > debug("check ddr_pmu_train_imem code\n");
> > pr_from32 = imem_start;
> > pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
> > - for (i = 0x0; i < IMEM_LEN; ) {
> > + for (i = 0x0; i < imem_len; ) {
> > tmp32 = (readw(pr_to32) & 0x);
> > pr_to32 += 4;
> > tmp32 += ((readw(pr_to32) & 0x) << 16); @@
> > -93,7 +128,7 @@ void ddr_load_train_firmware(enum fw_type type)
> > debug("check ddr4_pmu_train_dmem code\n");
> > pr_from32 = dmem_start;
> > pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
> > - for (i = 0x0; i < DMEM_LEN;) {
> > + for (i = 0x
Re: [PATCH] i2c: ihs: intel: Fix typo in comments (actual)
Hello Michal, On 19.04.22 15:01, Michal Simek wrote: > s/actucal/actual/g > > Signed-off-by: Michal Simek > --- > > drivers/i2c/ihs_i2c.c | 2 +- > drivers/i2c/intel_i2c.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) Applied to u-boot-i2c master Thanks! bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH] doc: Add device-tree-bindings for atsha204 and atsha204a
Hello Pali, On 10.05.22 06:42, Heiko Schocher wrote: > Hello Pali, > > On 28.04.22 20:58, Pali Rohár wrote: >> Document trivial bindings for atsha204 and atsha204a. >> >> Signed-off-by: Pali Rohár >> --- >> doc/device-tree-bindings/misc/atsha204.txt | 4 >> 1 file changed, 4 insertions(+) >> create mode 100644 doc/device-tree-bindings/misc/atsha204.txt > > Thanks! > > Reviewed-by: Heiko Schocher Applied to u-boot-i2c master Thanks! bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH] misc: atsha204a: Add support for atsha204 chip
Hello Pali.
On 10.05.22 06:45, Heiko Schocher wrote:
> Hello Pali,
>
> On 22.04.22 05:59, Heiko Schocher wrote:
>> Hello Pali,
>>
>> On 21.04.22 11:40, Pali Rohár wrote:
>>> On Thursday 21 April 2022 06:11:11 Heiko Schocher wrote:
Hello Pali,
On 05.04.22 16:10, Pali Rohár wrote:
> On Tuesday 05 April 2022 15:52:17 Stefan Roese wrote:
>> On 4/5/22 15:28, Pali Rohár wrote:
>>> On Tuesday 05 April 2022 15:14:52 Stefan Roese wrote:
On 4/5/22 14:49, Pali Rohár wrote:
> atsha204 chip is predecessor of atsha204a chip. Current U-Boot driver
> atsha204a-i2c.c can use both atsha204 and atsha204a chips because it
> does
> not call specific functions to just one of these chips.
>
> So just add compatible string for atsha204.
>
> Signed-off-by: Pali Rohár
> ---
>drivers/misc/atsha204a-i2c.c | 1 +
>1 file changed, 1 insertion(+)
>
> diff --git a/drivers/misc/atsha204a-i2c.c
> b/drivers/misc/atsha204a-i2c.c
> index 63fe541dade3..8b0055f99893 100644
> --- a/drivers/misc/atsha204a-i2c.c
> +++ b/drivers/misc/atsha204a-i2c.c
> @@ -399,6 +399,7 @@ static int atsha204a_of_to_plat(struct udevice
> *dev)
>}
>static const struct udevice_id atsha204a_ids[] = {
> + { .compatible = "atmel,atsha204" },
> { .compatible = "atmel,atsha204a" },
> { }
>};
Why do we need this new compatible here in the driver?
>>>
>>> They are different chips,
>>
>> Sure...
>>
>>> so should have different compatible strings.
>>
>> ... but is this really necessary and "best practice"? If the driver
>> can handle both chips without any changes, why do you need the new
>> compatible here?
>
> Well, currently it can handle both of them.
>
> But if driver is going to be extended to support e.g. SHA command
> (Calculate a SHA256 digest) then this command should be issued only for
> atsha204a. atsha204 does not support it.
>
> Similarly, if other DTS-based system is going to implement that SHA
> command, it would mean that U-Boot DTS file would not be compatible with
> that other system.
>
> Also it is a good idea to have DTS files and its compatible strings
> universal and not u-boot specific. So it could be used also by other
> projects (e.g. linux kernel).
>
> And if we mix now two chips which are similar (and supports lot of
> common operations) we would not be able in future to extend drivers in
> backward compatible manner.
>
> Just to note, I'm not going to implement atsha204a specific commands
> (which are not available in atsha204; like SHA command) because I do not
> need them (right now).
>
>> Don't get me wrong. I'm not blocking this change, just want to be sure
>> that it's really necessary.
>
> In case U-Boot driver has compatible string something like
> "atsha204-common" which could say that driver is using only functions
> which are available in all chip family then there would not be need for
> it. But if driver has chip specific name, I think the best is not to
> mask one chip by another which does not have 1:1 SW API compatibility.
From my side this is full okay to add here a new compatibility string
to differ between the two chips, and to see in DTS immediately which
chip is on the board. Also later if the driver really supports features
the other chip does not have, you do not need to change DTS anymore.
I would love to see this patch first in linux. Do you plan to sent
similiar change to linux?
>>>
>>> Hello! We are not using Linux kernel driver for atsha cryptochips (I was
>>> told that it decrease lifetime) but I can send also similar change to
>>> Linux.
>>
>> See it, thanks!
>
> Reviewed-by: Heiko Schocher
>
> Will apply soon, as it is accepted in linux.
applied to u-boot-i2c master
Thanks!
bye,
Heiko
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v2 12/12] doc: Add documentation for STM32 MCUs
On 4/27/22 13:54, Patrice Chotard wrote: > Add documentation for STM32 MCUs (F4, F7 and H7 series). > > Signed-off-by: Patrice Chotard > > --- > > Changes in v2: >- fix documentation file stm32_MCU.rst > > board/st/stm32f429-discovery/MAINTAINERS | 1 + > board/st/stm32f429-evaluation/MAINTAINERS | 1 + > board/st/stm32f469-discovery/MAINTAINERS | 1 + > board/st/stm32f746-disco/MAINTAINERS | 1 + > board/st/stm32h743-disco/MAINTAINERS | 1 + > board/st/stm32h743-eval/MAINTAINERS | 1 + > board/st/stm32h750-art-pi/MAINTAINERS | 1 + > doc/board/st/index.rst| 1 + > doc/board/st/stm32_MCU.rst| 186 ++ > 9 files changed, 194 insertions(+) > create mode 100644 doc/board/st/stm32_MCU.rst > > diff --git a/board/st/stm32f429-discovery/MAINTAINERS > b/board/st/stm32f429-discovery/MAINTAINERS > index fdb62e98e8..7661a15fdd 100644 > --- a/board/st/stm32f429-discovery/MAINTAINERS > +++ b/board/st/stm32f429-discovery/MAINTAINERS > @@ -1,6 +1,7 @@ > STM32F429-DISCOVERY BOARD > M: Kamil Lulko > S: Maintained > +F: doc/board/st/ > F: board/st/stm32f429-discovery/ > F: include/configs/stm32f429-discovery.h > F: configs/stm32f429-discovery_defconfig > diff --git a/board/st/stm32f429-evaluation/MAINTAINERS > b/board/st/stm32f429-evaluation/MAINTAINERS > index 29d00ef27e..b272893ef7 100644 > --- a/board/st/stm32f429-evaluation/MAINTAINERS > +++ b/board/st/stm32f429-evaluation/MAINTAINERS > @@ -1,6 +1,7 @@ > STM32F429-EVALUATION BOARD > M: Patrice Chotard > S: Maintained > +F: doc/board/st/ > F: board/st/stm32f429-evaluation/ > F: include/configs/stm32f429-evaluation.h > F: configs/stm32f429-evaluation_defconfig > diff --git a/board/st/stm32f469-discovery/MAINTAINERS > b/board/st/stm32f469-discovery/MAINTAINERS > index 5a6a78b39e..a95f93f6f6 100644 > --- a/board/st/stm32f469-discovery/MAINTAINERS > +++ b/board/st/stm32f469-discovery/MAINTAINERS > @@ -1,6 +1,7 @@ > STM32F469-DISCOVERY BOARD > M: Patrice Chotard > S: Maintained > +F: doc/board/st/ > F: board/st/stm32f469-discovery/ > F: include/configs/stm32f469-discovery.h > F: configs/stm32f469-discovery_defconfig > diff --git a/board/st/stm32f746-disco/MAINTAINERS > b/board/st/stm32f746-disco/MAINTAINERS > index bc0952c563..18e4c99c4f 100644 > --- a/board/st/stm32f746-disco/MAINTAINERS > +++ b/board/st/stm32f746-disco/MAINTAINERS > @@ -1,6 +1,7 @@ > STM32F746 DISCOVERY BOARD > M: Vikas Manocha > S: Maintained > +F: doc/board/st/ > F: board/st/stm32f746-disco > F: include/configs/stm32f746-disco.h > F: configs/stm32f746-disco_defconfig > diff --git a/board/st/stm32h743-disco/MAINTAINERS > b/board/st/stm32h743-disco/MAINTAINERS > index 60fbe344f8..f4ecef3aa5 100644 > --- a/board/st/stm32h743-disco/MAINTAINERS > +++ b/board/st/stm32h743-disco/MAINTAINERS > @@ -1,6 +1,7 @@ > STM32H743 DISCOVERY BOARD > M: Patrice Chotard > S: Maintained > +F: doc/board/st/ > F: board/st/stm32h743-disco > F: include/configs/stm32h743-disco.h > F: configs/stm32h743-disco_defconfig > diff --git a/board/st/stm32h743-eval/MAINTAINERS > b/board/st/stm32h743-eval/MAINTAINERS > index fda93db777..b69e0d4abb 100644 > --- a/board/st/stm32h743-eval/MAINTAINERS > +++ b/board/st/stm32h743-eval/MAINTAINERS > @@ -1,6 +1,7 @@ > STM32H743 EVALUATION BOARD > M: Patrice Chotard > S: Maintained > +F: doc/board/st/ > F: board/st/stm32h743-eval > F: include/configs/stm32h743-eval.h > F: configs/stm32h743-eval_defconfig > diff --git a/board/st/stm32h750-art-pi/MAINTAINERS > b/board/st/stm32h750-art-pi/MAINTAINERS > index 9578833068..2fd69e6d1c 100644 > --- a/board/st/stm32h750-art-pi/MAINTAINERS > +++ b/board/st/stm32h750-art-pi/MAINTAINERS > @@ -1,6 +1,7 @@ > STM32H750 ART PI BOARD > M: Dillon Min > S: Maintained > +F: doc/board/st/ > F: board/st/stm32h750-art-pi > F: include/configs/stm32h750-art-pi.h > F: configs/stm32h750-art-pi_defconfig > diff --git a/doc/board/st/index.rst b/doc/board/st/index.rst > index 9bba42f1da..2a8a4ef3b8 100644 > --- a/doc/board/st/index.rst > +++ b/doc/board/st/index.rst > @@ -8,3 +8,4 @@ STMicroelectronics > > st-dt > stm32mp1 > + stm32_MCU > diff --git a/doc/board/st/stm32_MCU.rst b/doc/board/st/stm32_MCU.rst > new file mode 100644 > index 00..7ff7c730fa > --- /dev/null > +++ b/doc/board/st/stm32_MCU.rst > @@ -0,0 +1,186 @@ > +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause > +.. sectionauthor:: Patrice Chotard > + > +STM32 MCU boards > += > + > +This is a quick instruction for setup STM32 MCU boards. > + > +Supported devices > +- > + > +U-Boot supports the following STMP32 MCU SoCs: > + > + - STM32F429 > + - STM32F469 > + - STM32F746 > + - STM32F769 > + - STM32H743 > + - STM32H750 > + > +SoCs information: > +- > +STM32F4 series are Cortex-M4 MCU. > +STM32F7 and STM32
Re: [PATCH v2 11/12] configs: stm32746g-eval: Add stm32746g-eval_spl_defconfig
On 4/27/22 13:54, Patrice Chotard wrote: > Add stm32746g-eval_spl_defconfig for stm32746g evaluation board to > build SPL. > > Signed-off-by: Patrice Chotard > Reviewed-by: Patrick Delaunay > --- > > (no changes since v1) > > board/st/stm32f746-disco/MAINTAINERS | 1 + > configs/stm32746g-eval_spl_defconfig | 86 > 2 files changed, 87 insertions(+) > create mode 100644 configs/stm32746g-eval_spl_defconfig > > diff --git a/board/st/stm32f746-disco/MAINTAINERS > b/board/st/stm32f746-disco/MAINTAINERS > index 7f128a8b69..bc0952c563 100644 > --- a/board/st/stm32f746-disco/MAINTAINERS > +++ b/board/st/stm32f746-disco/MAINTAINERS > @@ -6,5 +6,6 @@ F:include/configs/stm32f746-disco.h > F: configs/stm32f746-disco_defconfig > F: configs/stm32f746-disco_spl_defconfig > F: configs/stm32746g-eval_defconfig > +F: configs/stm32746g-eval_spl_defconfig > F: configs/stm32f769-disco_defconfig > F: configs/stm32f769-disco_spl_defconfig > diff --git a/configs/stm32746g-eval_spl_defconfig > b/configs/stm32746g-eval_spl_defconfig > new file mode 100644 > index 00..169a9c5b23 > --- /dev/null > +++ b/configs/stm32746g-eval_spl_defconfig > @@ -0,0 +1,86 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_STM32=y > +CONFIG_SYS_TEXT_BASE=0x08008000 > +CONFIG_SYS_MALLOC_LEN=0x10 > +CONFIG_SYS_MALLOC_F_LEN=0xE00 > +CONFIG_SPL_GPIO=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_NR_DRAM_BANKS=1 > +CONFIG_ENV_SIZE=0x2000 > +CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval" > +CONFIG_SPL_TEXT_BASE=0x800 > +CONFIG_SPL_SERIAL=y > +CONFIG_SPL_DRIVERS_MISC=y > +CONFIG_STM32F7=y > +CONFIG_TARGET_STM32F746_DISCO=y > +CONFIG_SPL=y > +CONFIG_BUILD_TARGET="u-boot-with-spl.bin" > +CONFIG_DISTRO_DEFAULTS=y > +CONFIG_SYS_LOAD_ADDR=0x8008000 > +CONFIG_BOOTDELAY=3 > +CONFIG_AUTOBOOT_KEYED=y > +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" > +CONFIG_AUTOBOOT_STOP_STR=" " > +CONFIG_USE_BOOTARGS=y > +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 > ignore_loglevel" > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_BOARD_LATE_INIT=y > +CONFIG_SPL_BOARD_INIT=y > +CONFIG_SPL_SYS_MALLOC_SIMPLE=y > +CONFIG_SPL_MTD_SUPPORT=y > +CONFIG_SPL_XIP_SUPPORT=y > +CONFIG_SPL_DM_RESET=y > +CONFIG_SYS_PROMPT="U-Boot > " > +CONFIG_CMD_GPT=y > +# CONFIG_RANDOM_UUID is not set > +CONFIG_CMD_MMC=y > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_SNTP=y > +CONFIG_CMD_DNS=y > +CONFIG_CMD_LINK_LOCAL=y > +CONFIG_CMD_BMP=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_TIMER=y > +# CONFIG_ISO_PARTITION is not set > +CONFIG_OF_CONTROL=y > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_NETCONSOLE=y > +CONFIG_SPL_DM=y > +CONFIG_SPL_DM_SEQ_ALIAS=y > +CONFIG_SPL_OF_TRANSLATE=y > +CONFIG_SPL_CLK=y > +CONFIG_ARM_PL180_MMCI=y > +CONFIG_MTD=y > +CONFIG_DM_MTD=y > +CONFIG_MTD_NOR_FLASH=y > +CONFIG_STM32_FLASH=y > +CONFIG_DM_SPI_FLASH=y > +CONFIG_SPI_FLASH_MACRONIX=y > +CONFIG_SPI_FLASH_STMICRO=y > +CONFIG_PHY_SMSC=y > +CONFIG_DM_ETH=y > +CONFIG_ETH_DESIGNWARE=y > +CONFIG_MII=y > +# CONFIG_PINCTRL_FULL is not set > +CONFIG_SPL_PINCTRL=y > +CONFIG_SPL_RAM=y > +CONFIG_SPECIFY_CONSOLE_INDEX=y > +CONFIG_SPI=y > +CONFIG_DM_SPI=y > +CONFIG_STM32_QSPI=y > +CONFIG_SPL_TIMER=y > +CONFIG_DM_VIDEO=y > +CONFIG_BACKLIGHT_GPIO=y > +CONFIG_VIDEO_STM32=y > +CONFIG_VIDEO_STM32_MAX_XRES=480 > +CONFIG_VIDEO_STM32_MAX_YRES=640 > +CONFIG_SPLASH_SCREEN=y > +CONFIG_SPLASH_SCREEN_ALIGN=y > +CONFIG_VIDEO_BMP_RLE8=y > +CONFIG_BMP_16BPP=y > +CONFIG_BMP_24BPP=y > +CONFIG_BMP_32BPP=y > +CONFIG_OF_LIBFDT_OVERLAY=y Applied to u-boot-stm32 Thanks Patrice
Re: [PATCH v2 10/12] configs: stm32746g-eval: Add stm32746g-eval_defconfig
On 4/27/22 13:53, Patrice Chotard wrote: > Add stm32746g-eval_defconfig for stm32746g evaluation board to > build U-Boot proper. > > Full board description can be found here : > https://www.st.com/en/evaluation-tools/stm32746g-eval.html > > Signed-off-by: Patrice Chotard > Reviewed-by: Patrick Delaunay > --- > > (no changes since v1) > > board/st/stm32f746-disco/MAINTAINERS | 1 + > configs/stm32746g-eval_defconfig | 64 > 2 files changed, 65 insertions(+) > create mode 100644 configs/stm32746g-eval_defconfig > > diff --git a/board/st/stm32f746-disco/MAINTAINERS > b/board/st/stm32f746-disco/MAINTAINERS > index 68f61fd5ff..7f128a8b69 100644 > --- a/board/st/stm32f746-disco/MAINTAINERS > +++ b/board/st/stm32f746-disco/MAINTAINERS > @@ -5,5 +5,6 @@ F:board/st/stm32f746-disco > F: include/configs/stm32f746-disco.h > F: configs/stm32f746-disco_defconfig > F: configs/stm32f746-disco_spl_defconfig > +F: configs/stm32746g-eval_defconfig > F: configs/stm32f769-disco_defconfig > F: configs/stm32f769-disco_spl_defconfig > diff --git a/configs/stm32746g-eval_defconfig > b/configs/stm32746g-eval_defconfig > new file mode 100644 > index 00..9f79b5a2b4 > --- /dev/null > +++ b/configs/stm32746g-eval_defconfig > @@ -0,0 +1,64 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_STM32=y > +CONFIG_SYS_TEXT_BASE=0x0800 > +CONFIG_SYS_MALLOC_LEN=0x10 > +CONFIG_SYS_MALLOC_F_LEN=0xE00 > +CONFIG_NR_DRAM_BANKS=1 > +CONFIG_ENV_SIZE=0x2000 > +CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval" > +CONFIG_STM32F7=y > +CONFIG_TARGET_STM32F746_DISCO=y > +CONFIG_DISTRO_DEFAULTS=y > +CONFIG_SYS_LOAD_ADDR=0x8008000 > +CONFIG_BOOTDELAY=3 > +CONFIG_AUTOBOOT_KEYED=y > +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" > +CONFIG_AUTOBOOT_STOP_STR=" " > +CONFIG_USE_BOOTARGS=y > +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 > ignore_loglevel" > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_BOARD_LATE_INIT=y > +CONFIG_SYS_PROMPT="U-Boot > " > +CONFIG_CMD_GPT=y > +# CONFIG_RANDOM_UUID is not set > +CONFIG_CMD_MMC=y > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_SNTP=y > +CONFIG_CMD_DNS=y > +CONFIG_CMD_LINK_LOCAL=y > +CONFIG_CMD_BMP=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_TIMER=y > +# CONFIG_ISO_PARTITION is not set > +CONFIG_OF_CONTROL=y > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_NETCONSOLE=y > +CONFIG_ARM_PL180_MMCI=y > +CONFIG_MTD=y > +CONFIG_DM_MTD=y > +CONFIG_MTD_NOR_FLASH=y > +CONFIG_STM32_FLASH=y > +CONFIG_DM_SPI_FLASH=y > +CONFIG_SPI_FLASH_MACRONIX=y > +CONFIG_SPI_FLASH_STMICRO=y > +CONFIG_PHY_SMSC=y > +CONFIG_DM_ETH=y > +CONFIG_ETH_DESIGNWARE=y > +CONFIG_MII=y > +# CONFIG_PINCTRL_FULL is not set > +CONFIG_SPI=y > +CONFIG_DM_SPI=y > +CONFIG_STM32_QSPI=y > +CONFIG_DM_VIDEO=y > +CONFIG_BACKLIGHT_GPIO=y > +CONFIG_VIDEO_STM32=y > +CONFIG_VIDEO_STM32_MAX_XRES=480 > +CONFIG_VIDEO_STM32_MAX_YRES=640 > +CONFIG_SPLASH_SCREEN=y > +CONFIG_SPLASH_SCREEN_ALIGN=y > +CONFIG_VIDEO_BMP_RLE8=y > +CONFIG_BMP_16BPP=y > +CONFIG_BMP_24BPP=y > +CONFIG_BMP_32BPP=y > +CONFIG_OF_LIBFDT_OVERLAY=y Applied to u-boot-stm32 Thanks Patrice
Re: [PATCH v2 09/12] configs: stm32f746-disco: use CONFIG_DEFAULT_DEVICE_TREE as fdtfile
On 4/27/22 13:53, Patrice Chotard wrote: > As stm32f46-disco, stm32f769-disco and stm32746g-eval are very similar > except their respective device tree file. These 3 boards uses the same > TARGET_STM32F746_DISCO flag (so same include/configs/stm32f746-disco.h > and same board file board/st/stm32f746-disco/stm32f746-disco.c) > > To be able to compile these 3 boards, replace the hard-coded device-tree > name in include/configs/stm32f746-disco.h by CONFIG_DEFAULT_DEVICE_TREE > which is set in each board defconfig file with the correct value. > > Signed-off-by: Patrice Chotard > Reviewed-by: Patrick Delaunay > --- > > (no changes since v1) > > include/configs/stm32f746-disco.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/configs/stm32f746-disco.h > b/include/configs/stm32f746-disco.h > index b93acdcc1f..cc3d4b4449 100644 > --- a/include/configs/stm32f746-disco.h > +++ b/include/configs/stm32f746-disco.h > @@ -34,7 +34,7 @@ > #include > #define CONFIG_EXTRA_ENV_SETTINGS\ > "kernel_addr_r=0xC0008000\0"\ > - "fdtfile=stm32f746-disco.dtb\0" \ > + "fdtfile="CONFIG_DEFAULT_DEVICE_TREE".dtb\0"\ > "fdt_addr_r=0xC0408000\0" \ > "scriptaddr=0xC0418000\0" \ > "pxefile_addr_r=0xC0428000\0" \ Applied to u-boot-stm32 Thanks Patrice
Re: [PATCH v2 08/12] board: stm32f746-disco: Fix dram_init() in none SPL config
On 4/27/22 13:53, Patrice Chotard wrote:
> Replace CONFIG_SUPPORT_SPL by CONFIG_SPL_BUILD to allow
> dram_init() execution when using none SPL defconfig
> (stm32f746-disco_defconfig).
>
> Signed-off-by: Patrice Chotard
> Reviewed-by: Patrick Delaunay
> ---
>
> (no changes since v1)
>
> board/st/stm32f746-disco/stm32f746-disco.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/st/stm32f746-disco/stm32f746-disco.c
> b/board/st/stm32f746-disco/stm32f746-disco.c
> index 69f657c54b..2ab23f2f4f 100644
> --- a/board/st/stm32f746-disco/stm32f746-disco.c
> +++ b/board/st/stm32f746-disco/stm32f746-disco.c
> @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
>
> int dram_init(void)
> {
> -#ifndef CONFIG_SUPPORT_SPL
> +#ifndef CONFIG_SPL_BUILD
> int rv;
> struct udevice *dev;
> rv = uclass_get_device(UCLASS_RAM, 0, &dev);
Applied to u-boot-stm32
Thanks
Patrice
Re: [PATCH v2 06/12] configs: stm32f769-disco: Migrate SPL flags to defconfig
On 4/27/22 13:53, Patrice Chotard wrote: > Migrate SPL flags to stm32f769-disco_spl_defconfig > > Signed-off-by: Patrice Chotard > Reviewed-by: Patrick Delaunay > --- > > (no changes since v1) > > configs/stm32f769-disco_spl_defconfig | 25 + > 1 file changed, 21 insertions(+), 4 deletions(-) > > diff --git a/configs/stm32f769-disco_spl_defconfig > b/configs/stm32f769-disco_spl_defconfig > index f151dab04f..672c1ec065 100644 > --- a/configs/stm32f769-disco_spl_defconfig > +++ b/configs/stm32f769-disco_spl_defconfig > @@ -3,12 +3,19 @@ CONFIG_ARCH_STM32=y > CONFIG_SYS_TEXT_BASE=0x08008000 > CONFIG_SYS_MALLOC_LEN=0x10 > CONFIG_SYS_MALLOC_F_LEN=0xE00 > +CONFIG_SPL_GPIO=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > CONFIG_NR_DRAM_BANKS=1 > CONFIG_ENV_SIZE=0x2000 > CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco" > CONFIG_SPL_TEXT_BASE=0x800 > +CONFIG_SPL_SERIAL=y > +CONFIG_SPL_DRIVERS_MISC=y > CONFIG_STM32F7=y > CONFIG_TARGET_STM32F746_DISCO=y > +CONFIG_SPL=y > +CONFIG_BUILD_TARGET="u-boot-with-spl.bin" > CONFIG_SYS_LOAD_ADDR=0x8008000 > CONFIG_DISTRO_DEFAULTS=y > CONFIG_BOOTDELAY=3 > @@ -18,6 +25,11 @@ CONFIG_AUTOBOOT_STOP_STR=" " > CONFIG_USE_BOOTARGS=y > CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 > ignore_loglevel" > # CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_SPL_BOARD_INIT=y > +CONFIG_SPL_SYS_MALLOC_SIMPLE=y > +CONFIG_SPL_MTD_SUPPORT=y > +CONFIG_SPL_XIP_SUPPORT=y > +CONFIG_SPL_DM_RESET=y > CONFIG_SYS_PROMPT="U-Boot > " > CONFIG_CMD_GPT=y > # CONFIG_RANDOM_UUID is not set > @@ -29,15 +41,16 @@ CONFIG_CMD_LINK_LOCAL=y > CONFIG_CMD_BMP=y > CONFIG_CMD_CACHE=y > CONFIG_CMD_TIMER=y > -# CONFIG_SPL_DOS_PARTITION is not set > # CONFIG_ISO_PARTITION is not set > -# CONFIG_SPL_EFI_PARTITION is not set > CONFIG_OF_CONTROL=y > +CONFIG_SPL_OF_CONTROL=y > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > CONFIG_NET_RANDOM_ETHADDR=y > CONFIG_NETCONSOLE=y > -# CONFIG_SPL_BLK is not set > -# CONFIG_SPL_DM_MMC is not set > +CONFIG_SPL_DM=y > +CONFIG_SPL_DM_SEQ_ALIAS=y > +CONFIG_SPL_OF_TRANSLATE=y > +CONFIG_SPL_CLK=y > CONFIG_ARM_PL180_MMCI=y > CONFIG_MTD=y > CONFIG_DM_MTD=y > @@ -51,9 +64,13 @@ CONFIG_DM_ETH=y > CONFIG_ETH_DESIGNWARE=y > CONFIG_MII=y > # CONFIG_PINCTRL_FULL is not set > +CONFIG_SPL_PINCTRL=y > +CONFIG_SPL_RAM=y > +CONFIG_SPECIFY_CONSOLE_INDEX=y > CONFIG_SPI=y > CONFIG_DM_SPI=y > CONFIG_STM32_QSPI=y > +CONFIG_SPL_TIMER=y > CONFIG_DM_VIDEO=y > CONFIG_BACKLIGHT_GPIO=y > CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y Applied to u-boot-stm32 Thanks Patrice
Re: [PATCH v2 07/12] configs: stm32f746-disco: Migrate SPL flags to defconfig
On 4/27/22 13:53, Patrice Chotard wrote: > Migrate SPL flags to stm32f746-disco_spl_defconfig > > Signed-off-by: Patrice Chotard > Reviewed-by: Patrick Delaunay > --- > > (no changes since v1) > > arch/arm/mach-stm32/Kconfig | 20 > configs/stm32f746-disco_spl_defconfig | 24 > 2 files changed, 20 insertions(+), 24 deletions(-) > > diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig > index a439dbd10f..a44ebf2597 100644 > --- a/arch/arm/mach-stm32/Kconfig > +++ b/arch/arm/mach-stm32/Kconfig > @@ -25,26 +25,6 @@ config STM32F7 > select PINCTRL > select PINCTRL_STM32 > select RAM > - select SPL > - select SPL_BOARD_INIT > - select SPL_CLK > - select SPL_DM > - select SPL_DM_RESET > - select SPL_DM_SEQ_ALIAS > - select SPL_DRIVERS_MISC > - select SPL_GPIO > - select SPL_LIBCOMMON_SUPPORT > - select SPL_LIBGENERIC_SUPPORT > - select SPL_MTD_SUPPORT > - select SPL_OF_CONTROL > - select SPL_OF_LIBFDT > - select SPL_OF_TRANSLATE > - select SPL_PINCTRL > - select SPL_RAM > - select SPL_SERIAL > - select SPL_SYS_MALLOC_SIMPLE > - select SPL_TIMER > - select SPL_XIP_SUPPORT > select STM32_RCC > select STM32_RESET > select STM32_SDRAM > diff --git a/configs/stm32f746-disco_spl_defconfig > b/configs/stm32f746-disco_spl_defconfig > index 0133867942..9fef65fa7b 100644 > --- a/configs/stm32f746-disco_spl_defconfig > +++ b/configs/stm32f746-disco_spl_defconfig > @@ -3,12 +3,18 @@ CONFIG_ARCH_STM32=y > CONFIG_SYS_TEXT_BASE=0x08008000 > CONFIG_SYS_MALLOC_LEN=0x10 > CONFIG_SYS_MALLOC_F_LEN=0xE00 > +CONFIG_SPL_GPIO=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > CONFIG_NR_DRAM_BANKS=1 > CONFIG_ENV_SIZE=0x2000 > CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco" > CONFIG_SPL_TEXT_BASE=0x800 > +CONFIG_SPL_SERIAL=y > +CONFIG_SPL_DRIVERS_MISC=y > CONFIG_STM32F7=y > CONFIG_TARGET_STM32F746_DISCO=y > +CONFIG_SPL=y > CONFIG_BUILD_TARGET="u-boot-with-spl.bin" > CONFIG_SYS_LOAD_ADDR=0x8008000 > CONFIG_DISTRO_DEFAULTS=y > @@ -20,6 +26,11 @@ CONFIG_USE_BOOTARGS=y > CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 > ignore_loglevel" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_BOARD_LATE_INIT=y > +CONFIG_SPL_BOARD_INIT=y > +CONFIG_SPL_SYS_MALLOC_SIMPLE=y > +CONFIG_SPL_MTD_SUPPORT=y > +CONFIG_SPL_XIP_SUPPORT=y > +CONFIG_SPL_DM_RESET=y > CONFIG_SYS_PROMPT="U-Boot > " > CONFIG_CMD_GPT=y > # CONFIG_RANDOM_UUID is not set > @@ -31,15 +42,16 @@ CONFIG_CMD_LINK_LOCAL=y > CONFIG_CMD_BMP=y > CONFIG_CMD_CACHE=y > CONFIG_CMD_TIMER=y > -# CONFIG_SPL_DOS_PARTITION is not set > # CONFIG_ISO_PARTITION is not set > -# CONFIG_SPL_EFI_PARTITION is not set > CONFIG_OF_CONTROL=y > +CONFIG_SPL_OF_CONTROL=y > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > CONFIG_NET_RANDOM_ETHADDR=y > CONFIG_NETCONSOLE=y > -# CONFIG_SPL_BLK is not set > -# CONFIG_SPL_DM_MMC is not set > +CONFIG_SPL_DM=y > +CONFIG_SPL_DM_SEQ_ALIAS=y > +CONFIG_SPL_OF_TRANSLATE=y > +CONFIG_SPL_CLK=y > CONFIG_ARM_PL180_MMCI=y > CONFIG_MTD=y > CONFIG_DM_MTD=y > @@ -53,9 +65,13 @@ CONFIG_DM_ETH=y > CONFIG_ETH_DESIGNWARE=y > CONFIG_MII=y > # CONFIG_PINCTRL_FULL is not set > +CONFIG_SPL_PINCTRL=y > +CONFIG_SPL_RAM=y > +CONFIG_SPECIFY_CONSOLE_INDEX=y > CONFIG_SPI=y > CONFIG_DM_SPI=y > CONFIG_STM32_QSPI=y > +CONFIG_SPL_TIMER=y > CONFIG_DM_VIDEO=y > CONFIG_BACKLIGHT_GPIO=y > CONFIG_VIDEO_STM32=y Applied to u-boot-stm32 Thanks Patrice
Re: [PATCH v2 05/12] configs: stm32f769-disco: Add stm32f769-disco_defconfig
On 4/27/22 13:53, Patrice Chotard wrote: > Add stm32f769-disco_defconfig for stm32f769 discovery board to > build U-Boot proper. > > Signed-off-by: Patrice Chotard > Reviewed-by: Patrick Delaunay > --- > > (no changes since v1) > > configs/stm32f769-disco_defconfig | 65 +++ > 1 file changed, 65 insertions(+) > create mode 100644 configs/stm32f769-disco_defconfig > > diff --git a/configs/stm32f769-disco_defconfig > b/configs/stm32f769-disco_defconfig > new file mode 100644 > index 00..3c112882cc > --- /dev/null > +++ b/configs/stm32f769-disco_defconfig > @@ -0,0 +1,65 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_STM32=y > +CONFIG_SYS_TEXT_BASE=0x0800 > +CONFIG_SYS_MALLOC_LEN=0x10 > +CONFIG_SYS_MALLOC_F_LEN=0xE00 > +CONFIG_NR_DRAM_BANKS=1 > +CONFIG_ENV_SIZE=0x2000 > +CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco" > +CONFIG_STM32F7=y > +CONFIG_TARGET_STM32F746_DISCO=y > +CONFIG_DISTRO_DEFAULTS=y > +CONFIG_SYS_LOAD_ADDR=0x8008000 > +CONFIG_BOOTDELAY=3 > +CONFIG_AUTOBOOT_KEYED=y > +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" > +CONFIG_AUTOBOOT_STOP_STR=" " > +CONFIG_USE_BOOTARGS=y > +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 > ignore_loglevel" > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_SYS_PROMPT="U-Boot > " > +CONFIG_CMD_GPT=y > +# CONFIG_RANDOM_UUID is not set > +CONFIG_CMD_MMC=y > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_SNTP=y > +CONFIG_CMD_DNS=y > +CONFIG_CMD_LINK_LOCAL=y > +CONFIG_CMD_BMP=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_TIMER=y > +# CONFIG_ISO_PARTITION is not set > +CONFIG_OF_CONTROL=y > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_NETCONSOLE=y > +CONFIG_ARM_PL180_MMCI=y > +CONFIG_MTD=y > +CONFIG_DM_MTD=y > +CONFIG_MTD_NOR_FLASH=y > +CONFIG_STM32_FLASH=y > +CONFIG_DM_SPI_FLASH=y > +CONFIG_SPI_FLASH_MACRONIX=y > +CONFIG_SPI_FLASH_STMICRO=y > +CONFIG_PHY_SMSC=y > +CONFIG_DM_ETH=y > +CONFIG_ETH_DESIGNWARE=y > +CONFIG_MII=y > +# CONFIG_PINCTRL_FULL is not set > +CONFIG_SPI=y > +CONFIG_DM_SPI=y > +CONFIG_STM32_QSPI=y > +CONFIG_DM_VIDEO=y > +CONFIG_BACKLIGHT_GPIO=y > +CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y > +CONFIG_VIDEO_STM32=y > +CONFIG_VIDEO_STM32_DSI=y > +CONFIG_VIDEO_STM32_MAX_XRES=480 > +CONFIG_VIDEO_STM32_MAX_YRES=800 > +CONFIG_SPLASH_SCREEN=y > +CONFIG_SPLASH_SCREEN_ALIGN=y > +CONFIG_VIDEO_BMP_RLE8=y > +CONFIG_BMP_16BPP=y > +CONFIG_BMP_24BPP=y > +CONFIG_BMP_32BPP=y > +CONFIG_OF_LIBFDT_OVERLAY=y Applied to u-boot-stm32 Thanks Patrice
Re: [PATCH 1/2] misc: i2c_eeprom: add support for microchip 24aa025e48
Hello Eugen,
On 10.05.22 09:44, eugen.hris...@microchip.com wrote:
> On 5/2/22 12:24 PM, Michael Walle wrote:
>>> 24aa025e48 is a variant of 24aa02e48 that has a page size of 16 bytes.
>>>
>>> Signed-off-by: Eugen Hristev
>>> ---
>>> drivers/misc/i2c_eeprom.c | 8
>>> 1 file changed, 8 insertions(+)
>>>
>>> diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c
>>> index 89a450d0f8..265c1d0591 100644
>>> --- a/drivers/misc/i2c_eeprom.c
>>> +++ b/drivers/misc/i2c_eeprom.c
>>> @@ -176,6 +176,13 @@ static const struct i2c_eeprom_drv_data
>>> mc24aa02e48_data = {
>>>.offset_len = 1,
>>> };
>>>
>>> +static const struct i2c_eeprom_drv_data mc24aa025e48_data = {
>>> + .size = 256,
>>> + .pagesize = 16,
>>> + .addr_offset_mask = 0,
>>> + .offset_len = 1,
>>> +};
>>> +
>>> static const struct i2c_eeprom_drv_data atmel24c01a_data = {
>>>.size = 128,
>>>.pagesize = 8,
>>> @@ -264,6 +271,7 @@ static const struct i2c_eeprom_drv_data
>>> atmel24c512_data = {
>>> static const struct udevice_id i2c_eeprom_std_ids[] = {
>>>{ .compatible = "i2c-eeprom", (ulong)&eeprom_data },
>>>{ .compatible = "microchip,24aa02e48", (ulong)&mc24aa02e48_data },
>>> + { .compatible = "microchip,24aa025e48", (ulong)&mc24aa025e48_data },
>>
>> As far as I can see, this is not a documented compatible string in the
>> device tree bindings, which means u-boot is diverting again from its linux
>> counterpart. (The same goes for the 24aa02e48).
>
> Hello Michael,
>
> I know. But I thought it was the best way rather than reusing one
> existing compatible and forcing the page size. I can do that if you feel
> it's better.
>
> I have to check how Linux is handling this eeprom as it's using the
> at24c32 compatible which is incorrect. It may be that the at24c32
> compatible with additional properties makes the driver behaving as if
> it's a mc23aa025e48 . Which is not really right... (as the idea above)
>
> Heiko, your thoughts ?
Best would be to find out, what linux do.
I think, you should have the same problem with linux?
So I think, best would be to introduce this 2 compatible strings also
in linux and add of course the correct settings for "24aa025e48".
bye,
Heiko
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v2 04/12] configs: stm32f769-disco: Rename stm32f769-disco_defconfig to stm32f769-disco_spl_defconfig
On 4/27/22 13:53, Patrice Chotard wrote:
> The current stm32f769-disco_defconfig file supports SPL, rename it to
> stm32f769-disco_spl_defconfig to reflect the supported configuration.
>
> Signed-off-by: Patrice Chotard
> Reviewed-by: Patrick Delaunay
> ---
>
> (no changes since v1)
>
> board/st/stm32f746-disco/MAINTAINERS | 1 +
> .../{stm32f769-disco_defconfig => stm32f769-disco_spl_defconfig} | 0
> 2 files changed, 1 insertion(+)
> rename configs/{stm32f769-disco_defconfig => stm32f769-disco_spl_defconfig}
> (100%)
>
> diff --git a/board/st/stm32f746-disco/MAINTAINERS
> b/board/st/stm32f746-disco/MAINTAINERS
> index 06d366e8a2..68f61fd5ff 100644
> --- a/board/st/stm32f746-disco/MAINTAINERS
> +++ b/board/st/stm32f746-disco/MAINTAINERS
> @@ -6,3 +6,4 @@ F:include/configs/stm32f746-disco.h
> F: configs/stm32f746-disco_defconfig
> F: configs/stm32f746-disco_spl_defconfig
> F: configs/stm32f769-disco_defconfig
> +F: configs/stm32f769-disco_spl_defconfig
> diff --git a/configs/stm32f769-disco_defconfig
> b/configs/stm32f769-disco_spl_defconfig
> similarity index 100%
> rename from configs/stm32f769-disco_defconfig
> rename to configs/stm32f769-disco_spl_defconfig
Applied to u-boot-stm32
Thanks
Patrice
Re: [PATCH v2 03/12] configs: stm32f746-disco: Add stm32f746-disco_defconfig
On 4/27/22 13:53, Patrice Chotard wrote: > Add stm32f746-disco_defconfig for stm32f746 discovery board to > build U-Boot proper. > > Signed-off-by: Patrice Chotard > Reviewed-by: Patrick Delaunay > --- > > (no changes since v1) > > configs/stm32f746-disco_defconfig | 64 +++ > 1 file changed, 64 insertions(+) > create mode 100644 configs/stm32f746-disco_defconfig > > diff --git a/configs/stm32f746-disco_defconfig > b/configs/stm32f746-disco_defconfig > new file mode 100644 > index 00..2c70bac9cd > --- /dev/null > +++ b/configs/stm32f746-disco_defconfig > @@ -0,0 +1,64 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_STM32=y > +CONFIG_SYS_TEXT_BASE=0x0800 > +CONFIG_SYS_MALLOC_LEN=0x10 > +CONFIG_SYS_MALLOC_F_LEN=0xE00 > +CONFIG_NR_DRAM_BANKS=1 > +CONFIG_ENV_SIZE=0x2000 > +CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco" > +CONFIG_STM32F7=y > +CONFIG_TARGET_STM32F746_DISCO=y > +CONFIG_DISTRO_DEFAULTS=y > +CONFIG_SYS_LOAD_ADDR=0x8008000 > +CONFIG_BOOTDELAY=3 > +CONFIG_AUTOBOOT_KEYED=y > +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" > +CONFIG_AUTOBOOT_STOP_STR=" " > +CONFIG_USE_BOOTARGS=y > +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 > ignore_loglevel" > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_BOARD_LATE_INIT=y > +CONFIG_SYS_PROMPT="U-Boot > " > +CONFIG_CMD_GPT=y > +# CONFIG_RANDOM_UUID is not set > +CONFIG_CMD_MMC=y > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_SNTP=y > +CONFIG_CMD_DNS=y > +CONFIG_CMD_LINK_LOCAL=y > +CONFIG_CMD_BMP=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_TIMER=y > +# CONFIG_ISO_PARTITION is not set > +CONFIG_OF_CONTROL=y > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_NETCONSOLE=y > +CONFIG_ARM_PL180_MMCI=y > +CONFIG_MTD=y > +CONFIG_DM_MTD=y > +CONFIG_MTD_NOR_FLASH=y > +CONFIG_STM32_FLASH=y > +CONFIG_DM_SPI_FLASH=y > +CONFIG_SPI_FLASH_MACRONIX=y > +CONFIG_SPI_FLASH_STMICRO=y > +CONFIG_PHY_SMSC=y > +CONFIG_DM_ETH=y > +CONFIG_ETH_DESIGNWARE=y > +CONFIG_MII=y > +# CONFIG_PINCTRL_FULL is not set > +CONFIG_SPI=y > +CONFIG_DM_SPI=y > +CONFIG_STM32_QSPI=y > +CONFIG_DM_VIDEO=y > +CONFIG_BACKLIGHT_GPIO=y > +CONFIG_VIDEO_STM32=y > +CONFIG_VIDEO_STM32_MAX_XRES=480 > +CONFIG_VIDEO_STM32_MAX_YRES=640 > +CONFIG_SPLASH_SCREEN=y > +CONFIG_SPLASH_SCREEN_ALIGN=y > +CONFIG_VIDEO_BMP_RLE8=y > +CONFIG_BMP_16BPP=y > +CONFIG_BMP_24BPP=y > +CONFIG_BMP_32BPP=y > +CONFIG_OF_LIBFDT_OVERLAY=y Applied to u-boot-stm32 Thanks Patrice
Re: [PATCH v2 02/12] configs: stm32f746-disco: Rename stm32f746-disco_defconfig to stm32f746-disco_spl_defconfig
On 4/27/22 13:53, Patrice Chotard wrote:
> The current stm32f746-disco_defconfig file supports SPL, rename it to
> stm32f746-disco_spl_defconfig to reflect the supported configuration.
>
> Signed-off-by: Patrice Chotard
> Reviewed-by: Patrick Delaunay
> ---
>
> (no changes since v1)
>
> board/st/stm32f746-disco/MAINTAINERS | 1 +
> .../{stm32f746-disco_defconfig => stm32f746-disco_spl_defconfig} | 0
> 2 files changed, 1 insertion(+)
> rename configs/{stm32f746-disco_defconfig => stm32f746-disco_spl_defconfig}
> (100%)
>
> diff --git a/board/st/stm32f746-disco/MAINTAINERS
> b/board/st/stm32f746-disco/MAINTAINERS
> index 3bbb513ad7..06d366e8a2 100644
> --- a/board/st/stm32f746-disco/MAINTAINERS
> +++ b/board/st/stm32f746-disco/MAINTAINERS
> @@ -4,4 +4,5 @@ S:Maintained
> F: board/st/stm32f746-disco
> F: include/configs/stm32f746-disco.h
> F: configs/stm32f746-disco_defconfig
> +F: configs/stm32f746-disco_spl_defconfig
> F: configs/stm32f769-disco_defconfig
> diff --git a/configs/stm32f746-disco_defconfig
> b/configs/stm32f746-disco_spl_defconfig
> similarity index 100%
> rename from configs/stm32f746-disco_defconfig
> rename to configs/stm32f746-disco_spl_defconfig
Applied to u-boot-stm32
Thanks
Patrice
Re: [PATCH v2 01/12] configs: stm32f746-disco: Concatenate spl and u-boot binaries
On 4/27/22 13:53, Patrice Chotard wrote: > This allows to concatenate spl and u-boot binaries together. > Previously, both binaries has to be flashed separately at the correct > offset (spl at offset 0 and u-boot at offset 0x8000). > With this patch, only one binary is generated (u-boot-with-spl.bin) > and has to be copied in flash at offset 0 using openocd for example > or simply copied in exported mass storage. > > Signed-off-by: Patrice Chotard > Reviewed-by: Patrick Delaunay > --- > > (no changes since v1) > > configs/stm32f746-disco_defconfig | 1 + > include/configs/stm32f746-disco.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/configs/stm32f746-disco_defconfig > b/configs/stm32f746-disco_defconfig > index 130b90fae3..0133867942 100644 > --- a/configs/stm32f746-disco_defconfig > +++ b/configs/stm32f746-disco_defconfig > @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco" > CONFIG_SPL_TEXT_BASE=0x800 > CONFIG_STM32F7=y > CONFIG_TARGET_STM32F746_DISCO=y > +CONFIG_BUILD_TARGET="u-boot-with-spl.bin" > CONFIG_SYS_LOAD_ADDR=0x8008000 > CONFIG_DISTRO_DEFAULTS=y > CONFIG_BOOTDELAY=3 > diff --git a/include/configs/stm32f746-disco.h > b/include/configs/stm32f746-disco.h > index 8ad4bb99c8..b93acdcc1f 100644 > --- a/include/configs/stm32f746-disco.h > +++ b/include/configs/stm32f746-disco.h > @@ -49,6 +49,7 @@ > #define CONFIG_SYS_UBOOT_START 0x080083FD > #define CONFIG_SYS_UBOOT_BASE(CONFIG_SYS_FLASH_BASE + \ >CONFIG_SYS_SPL_LEN) > +#define CONFIG_SPL_PAD_TO0x8000 > > /* DT blob (fdt) address */ > #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ Applied to u-boot-stm32 Thanks Patrice
Re: [PATCH] board: st: stm32mp1: Consider USB cable connected when boot device is USB
On 5/6/22 10:51, Patrick DELAUNAY wrote: > Hi, > > On 4/22/22 09:39, Patrice Chotard wrote: >> Always consider USB cable is connected when USB boot device is detected. >> >> Signed-off-by: Patrice Chotard >> --- >> >> board/st/stm32mp1/stm32mp1.c | 7 +++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c >> index fff1880e5b..62a5fc23e6 100644 >> --- a/board/st/stm32mp1/stm32mp1.c >> +++ b/board/st/stm32mp1/stm32mp1.c >> @@ -199,6 +199,13 @@ int g_dnl_board_usb_cable_connected(void) >> if (!IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG)) >> return -ENODEV; >> + /* >> + * In case of USB boot device is detected, consider USB cable is >> + * connected >> + */ >> + if ((get_bootmode() & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_USB) >> + return true; >> + >> /* if typec stusb160x is present, means DK1 or DK2 board */ >> ret = stusb160x_cable_connected(); >> if (ret >= 0) > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > > Applied to u-boot-stm32 Thanks Patrice
Re: [PATCH] phy: stm32-usbphyc: stm32-usbphyc: Add DT phy tuning support
On 5/6/22 10:50, Patrick DELAUNAY wrote: > Hi > > On 4/22/22 09:39, Patrice Chotard wrote: >> Add support of phy-tuning properties for sm32-usbphyc's phy tuning >> aligned with v5.15 kernel bindings. >> >> Signed-off-by: Patrice Chotard >> --- >> >> drivers/phy/phy-stm32-usbphyc.c | 167 >> 1 file changed, 167 insertions(+) >> > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > > Applied to u-boot-stm32 Thanks Patrice
Re: [PATCH 3/3] gpio: stm32_gpio: Rework GPIO hole management
On 5/6/22 10:39, Patrick DELAUNAY wrote:
> Hi,
>
> On 4/22/22 09:38, Patrice Chotard wrote:
>> On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank
>> Example:
>> If GPIO bank have 16 GPIO pins [0-15].
>> In particular SoC's package case, some GPIO bank can have less GPIO pins:
>> - [0-10] => 11 pins;
>> - [2-7] => 6 pins.
>>
>> Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management")
>> proposed a first implementation by not counting GPIO "inside" hole. GPIO
>> are not displaying correctly using gpio or pinmux command when GPIO holes
>> are located at the beginning of GPIO bank.
>>
>> To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges
>> struct to indicate if a GPIO is mapped or not. GPIO uclass offers several
>> GPIO functions ("input", "output", "unused", "unknown" and "func"), use
>> "unknown" GPIO function to indicate that a GPIO is not mapped.
>>
>> stm32_offset_to_index() is no more needed and removed.
>>
>> This must be reflected using the "gpio" command to indicate to user
>> that a particular GPIO is not mapped (marked as "unknown") as shown below:
>>
>> Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins
>> mapped):
>> GPIOI0 : unknown
>> GPIOI1 : unknown
>> GPIOI2 : analog
>> GPIOI3 : analog
>> GPIOI4 : alt function 0 push-pull pull-down
>> GPIOI5 : alt function 0 push-pull pull-down
>> GPIOI6 : alt function 0 push-pull pull-down
>> GPIOI7 : analog
>> GPIOI8 : unknown
>> GPIOI9 : unknown
>> GPIOI10 : unknown
>> GPIOI11 : unknown
>> GPIOI12 : unknown
>> GPIOI13 : unknown
>> GPIOI14 : unknown
>> GPIOI15 : unknown
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> drivers/gpio/stm32_gpio.c | 103 +++-
>> drivers/gpio/stm32_gpio_priv.h | 2 -
>> drivers/pinctrl/pinctrl_stm32.c | 5 +-
>> 3 files changed, 37 insertions(+), 73 deletions(-)
>>
>> diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
>> index 8667ed3835..7a2ca91c76 100644
>> --- a/drivers/gpio/stm32_gpio.c
>> +++ b/drivers/gpio/stm32_gpio.c
>> @@ -83,38 +83,22 @@ static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct
>> stm32_gpio_regs *regs,
>> return (readl(®s->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
>> }
>> -/*
>> - * convert gpio offset to gpio index taking into account gpio holes
>> - * into gpio bank
>> - */
>> -int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
>> +static bool stm32_gpio_is_mapped(struct udevice *dev, int offset)
>> {
>> struct stm32_gpio_priv *priv = dev_get_priv(dev);
>> - unsigned int idx = 0;
>> - int i;
>> -
>> - for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
>> - if (priv->gpio_range & BIT(i)) {
>> - if (idx == offset)
>> - return idx;
>> - idx++;
>> - }
>> - }
>> - /* shouldn't happen */
>> - return -EINVAL;
>> +
>> + return !!(priv->gpio_range & BIT(offset));
>> }
>> static int stm32_gpio_direction_input(struct udevice *dev, unsigned
>> offset)
>> {
>> struct stm32_gpio_priv *priv = dev_get_priv(dev);
>> struct stm32_gpio_regs *regs = priv->regs;
>> - int idx;
>> - idx = stm32_offset_to_index(dev, offset);
>> - if (idx < 0)
>> - return idx;
>> + if (!stm32_gpio_is_mapped(dev, offset))
>> + return -ENXIO;
>> - stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
>> + stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_IN);
>> return 0;
>> }
>> @@ -124,15 +108,13 @@ static int stm32_gpio_direction_output(struct udevice
>> *dev, unsigned offset,
>> {
>> struct stm32_gpio_priv *priv = dev_get_priv(dev);
>> struct stm32_gpio_regs *regs = priv->regs;
>> - int idx;
>> - idx = stm32_offset_to_index(dev, offset);
>> - if (idx < 0)
>> - return idx;
>> + if (!stm32_gpio_is_mapped(dev, offset))
>> + return -ENXIO;
>> - stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
>> + stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_OUT);
>> - writel(BSRR_BIT(idx, value), ®s->bsrr);
>> + writel(BSRR_BIT(offset, value), ®s->bsrr);
>> return 0;
>> }
>> @@ -141,26 +123,22 @@ static int stm32_gpio_get_value(struct udevice *dev,
>> unsigned offset)
>> {
>> struct stm32_gpio_priv *priv = dev_get_priv(dev);
>> struct stm32_gpio_regs *regs = priv->regs;
>> - int idx;
>> - idx = stm32_offset_to_index(dev, offset);
>> - if (idx < 0)
>> - return idx;
>> + if (!stm32_gpio_is_mapped(dev, offset))
>> + return -ENXIO;
>> - return readl(®s->idr) & BIT(idx) ? 1 : 0;
>> + return readl(®s->idr) & BIT(offset) ? 1 : 0;
>> }
>> static int stm32_gpio_set_value(struct udevice *dev, unsigned offset,
>> int value)
>> {
>> struct stm32_gpio_priv *priv = dev_get_priv(de
Re: [PATCH 2/3] pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins
On 5/6/22 10:37, Patrick DELAUNAY wrote:
> Hi,
>
> On 4/22/22 09:38, Patrice Chotard wrote:
>> GPIOF_UNKNOWN becomes a valid pin muxing information to indicate
>> that a pin is not mapped.
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> drivers/pinctrl/pinctrl_stm32.c | 2 --
>> 1 file changed, 2 deletions(-)
>>
>> diff --git a/drivers/pinctrl/pinctrl_stm32.c
>> b/drivers/pinctrl/pinctrl_stm32.c
>> index 5d8e156d62..373f51f046 100644
>> --- a/drivers/pinctrl/pinctrl_stm32.c
>> +++ b/drivers/pinctrl/pinctrl_stm32.c
>> @@ -220,8 +220,6 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice
>> *dev,
>> switch (mode) {
>> case GPIOF_UNKNOWN:
>> - /* should never happen */
>> - return -EINVAL;
>> case GPIOF_UNUSED:
>> snprintf(buf, size, "%s", pinmux_mode[mode]);
>> break;
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
>
Applied to u-boot-stm32
Thanks
Patrice
Re: [PATCH 1/3] pinctrl: pinctrl_stm32: Update pinmux_mode definition
On 5/6/22 10:37, Patrick DELAUNAY wrote:
> Hi,
>
> On 4/22/22 09:38, Patrice Chotard wrote:
>> pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c
>> So reuse the same gpio_func_t enum value
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> drivers/pinctrl/pinctrl_stm32.c | 13 ++---
>> 1 file changed, 6 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/pinctrl/pinctrl_stm32.c
>> b/drivers/pinctrl/pinctrl_stm32.c
>> index 5729799b12..5d8e156d62 100644
>> --- a/drivers/pinctrl/pinctrl_stm32.c
>> +++ b/drivers/pinctrl/pinctrl_stm32.c
>> @@ -42,13 +42,12 @@ struct stm32_gpio_bank {
>> #ifndef CONFIG_SPL_BUILD
>> static char pin_name[PINNAME_SIZE];
>> -#define PINMUX_MODE_COUNT 5
>> -static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
>> - "gpio input",
>> - "gpio output",
>> - "analog",
>> - "unknown",
>> - "alt function",
>> +static const char * const pinmux_mode[GPIOF_COUNT] = {
>> + [GPIOF_INPUT] = "gpio input",
>> + [GPIOF_OUTPUT] = "gpio output",
>> + [GPIOF_UNUSED] = "analog",
>> + [GPIOF_UNKNOWN] = "unknown",
>> + [GPIOF_FUNC] = "alt function",
>> };
>> static const char * const pinmux_bias[] = {
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
>
Applied to u-boot-stm32
Thanks
Patrice
RE: [PATCH] armv8: Fix TCR 64-bit writes
> Subject: [PATCH] armv8: Fix TCR 64-bit writes > > The AArch64 TCR_ELx register is a 64-bit register, and many newer architecture > features use bits in the upper half. So far U-Boot was igorant of those bits, > trying to leave them alone. > However, in an effort to set bit 31 to 1, it failed doing so, because the > compiler > sign-extended "1 << 31", so that all bits[63:31] got set. > > Older ARMv8.0 cores don't define anything dangerous up there, but newer > architecture revisions do, and setting all those bits will end badly: > = > $ qemu-system-aarch64 -cpu max > U-Boot 2022.07-rc1 (May 09 2022 - 15:21:00 +0100) > > DRAM: 1.5 GiB > = (hangs here) > > Defining TCR_ELx_RSVD to "1U << 31" avoids the sign-extension, so all upper > bits stay at a safe 0 value. This means no more surprises when U-Boot runs on > a > more capable CPU core. > > Reported-by: Balaji Anandapadmanaban > Signed-off-by: Andre Przywara Reviewed-by: Peng Fan > --- > arch/arm/include/asm/armv8/mmu.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/include/asm/armv8/mmu.h > b/arch/arm/include/asm/armv8/mmu.h > index fc97c55114..c36b2cf5a5 100644 > --- a/arch/arm/include/asm/armv8/mmu.h > +++ b/arch/arm/include/asm/armv8/mmu.h > @@ -99,9 +99,9 @@ > #define TCR_TG0_16K (2 << 14) > #define TCR_EPD1_DISABLE (1 << 23) > > -#define TCR_EL1_RSVD (1 << 31) > -#define TCR_EL2_RSVD (1 << 31 | 1 << 23) > -#define TCR_EL3_RSVD (1 << 31 | 1 << 23) > +#define TCR_EL1_RSVD (1U << 31) > +#define TCR_EL2_RSVD (1U << 31 | 1 << 23) > +#define TCR_EL3_RSVD (1U << 31 | 1 << 23) > > #ifndef __ASSEMBLY__ > static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) > -- > 2.25.1
Re: [PATCH] ARM: stm32: Use CONFIG_TFTP_TSIZE on STMicroelectronics boards
On 5/5/22 14:21, Patrick Delaunay wrote: > Long TFTP transfers lead to a wall of # characters on UART, which in > the end may slow down the transfer itself. Use CONFIG_TFTP_TSIZE to > print progress in fewer # characters. > > Signed-off-by: Patrick Delaunay > --- > > configs/stm32mp15_basic_defconfig | 1 + > configs/stm32mp15_defconfig | 1 + > configs/stm32mp15_trusted_defconfig | 1 + > 3 files changed, 3 insertions(+) > > diff --git a/configs/stm32mp15_basic_defconfig > b/configs/stm32mp15_basic_defconfig > index 5d1b2e0fd7..1b1c255b98 100644 > --- a/configs/stm32mp15_basic_defconfig > +++ b/configs/stm32mp15_basic_defconfig > @@ -80,6 +80,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y > CONFIG_SYS_MMC_ENV_DEV=-1 > # CONFIG_SPL_ENV_IS_NOWHERE is not set > # CONFIG_SPL_ENV_IS_IN_SPI_FLASH is not set > +CONFIG_TFTP_TSIZE=y > CONFIG_STM32_ADC=y > CONFIG_SET_DFU_ALT_INFO=y > CONFIG_USB_FUNCTION_FASTBOOT=y > diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig > index f6e7fc81b0..02b37e14ea 100644 > --- a/configs/stm32mp15_defconfig > +++ b/configs/stm32mp15_defconfig > @@ -61,6 +61,7 @@ CONFIG_ENV_UBI_VOLUME="uboot_config" > CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > CONFIG_SYS_MMC_ENV_DEV=-1 > +CONFIG_TFTP_TSIZE=y > CONFIG_STM32_ADC=y > CONFIG_CLK_SCMI=y > CONFIG_SET_DFU_ALT_INFO=y > diff --git a/configs/stm32mp15_trusted_defconfig > b/configs/stm32mp15_trusted_defconfig > index 855a394893..df31c0fbb1 100644 > --- a/configs/stm32mp15_trusted_defconfig > +++ b/configs/stm32mp15_trusted_defconfig > @@ -62,6 +62,7 @@ CONFIG_ENV_UBI_VOLUME="uboot_config" > CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > CONFIG_SYS_MMC_ENV_DEV=-1 > +CONFIG_TFTP_TSIZE=y > CONFIG_STM32_ADC=y > CONFIG_CLK_SCMI=y > CONFIG_SET_DFU_ALT_INFO=y Applied to u-boot-stm32 Thanks Patrice
Re: [PATCH] ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI
On 5/6/22 10:42, Patrick DELAUNAY wrote: > Hi, > > On 5/4/22 14:50, Marek Vasut wrote: >> The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3 >> in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant >> which has extra Empirion DCDC converter in front of the 1V8 IO supply, or >> outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter. >> >> The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily >> high input voltage to the Empirion DCDC converter, so move it into matching >> DTSI to stop confusing users. >> >> Signed-off-by: Marek Vasut >> Cc: Patrice Chotard >> Cc: Patrick Delaunay >> --- >> arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi | 5 + >> arch/arm/dts/stm32mp15xx-dhcor-som.dtsi | 4 ++-- >> 2 files changed, 7 insertions(+), 2 deletions(-) >> > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > > > Applied to u-boot-stm32 Thanks Patrice
Re: [PATCH 2/2] ARM: stm32: Use CONFIG_TFTP_TSIZE on DHSOM
On 5/1/22 18:43, Marek Vasut wrote: > Long TFTP transfers lead to a wall of # characters on UART, which in > the end may slow down the transfer itself. Use CONFIG_TFTP_TSIZE to > print progress in fewer # characters. > > Signed-off-by: Marek Vasut > Cc: Patrick Delaunay > Cc: Patrice Chotard > Cc: Ramon Fried > --- > configs/stm32mp15_dhcom_basic_defconfig | 1 + > configs/stm32mp15_dhcor_basic_defconfig | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/configs/stm32mp15_dhcom_basic_defconfig > b/configs/stm32mp15_dhcom_basic_defconfig > index 0ff015cae49..7f7aecf2510 100644 > --- a/configs/stm32mp15_dhcom_basic_defconfig > +++ b/configs/stm32mp15_dhcom_basic_defconfig > @@ -80,6 +80,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y > CONFIG_SPL_ENV_IS_NOWHERE=y > CONFIG_NET_RANDOM_ETHADDR=y > CONFIG_IP_DEFRAG=y > +CONFIG_TFTP_TSIZE=y > CONFIG_STM32_ADC=y > CONFIG_SPL_BLOCK_CACHE=y > CONFIG_DFU_MMC=y > diff --git a/configs/stm32mp15_dhcor_basic_defconfig > b/configs/stm32mp15_dhcor_basic_defconfig > index 83614b9fc8e..35e43a9a2fc 100644 > --- a/configs/stm32mp15_dhcor_basic_defconfig > +++ b/configs/stm32mp15_dhcor_basic_defconfig > @@ -77,6 +77,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y > CONFIG_SPL_ENV_IS_NOWHERE=y > CONFIG_NET_RANDOM_ETHADDR=y > CONFIG_IP_DEFRAG=y > +CONFIG_TFTP_TSIZE=y > CONFIG_STM32_ADC=y > CONFIG_SPL_BLOCK_CACHE=y > CONFIG_DFU_MMC=y Applied to u-boot-stm32 Thanks Patrice
Re: [PATCH 1/2] ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM
On 5/2/22 10:25, Patrick DELAUNAY wrote: > Hi Marek, > > On 5/1/22 18:43, Marek Vasut wrote: >> The DHCOM does ship with KS8851 with 1.5 kiB packet buffer. The DHSOM >> may be extended with other MAC options connected to FMC2 bus, like the >> DM9000, wih similar limitations. Use default CONFIG_TFTP_BLOCKSIZE of >> 1468 Bytes instead of 1536 Bytes, which always avoids overflowing the >> packet buffers of such limited MACs, which leads to e.g. TFTP timeouts. >> This also avoids receiving a short packet fragment at the end of each >> TFTP block, which led to reduced performance. >> >> Signed-off-by: Marek Vasut >> Cc: Patrick Delaunay >> Cc: Patrice Chotard >> Cc: Ramon Fried >> --- >> configs/stm32mp15_dhcom_basic_defconfig | 1 - >> configs/stm32mp15_dhcor_basic_defconfig | 1 - >> 2 files changed, 2 deletions(-) >> >> diff --git a/configs/stm32mp15_dhcom_basic_defconfig >> b/configs/stm32mp15_dhcom_basic_defconfig >> index ec955eae200..0ff015cae49 100644 >> --- a/configs/stm32mp15_dhcom_basic_defconfig >> +++ b/configs/stm32mp15_dhcom_basic_defconfig >> @@ -80,7 +80,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y >> CONFIG_SPL_ENV_IS_NOWHERE=y >> CONFIG_NET_RANDOM_ETHADDR=y >> CONFIG_IP_DEFRAG=y >> -CONFIG_TFTP_BLOCKSIZE=1536 >> CONFIG_STM32_ADC=y >> CONFIG_SPL_BLOCK_CACHE=y >> CONFIG_DFU_MMC=y >> diff --git a/configs/stm32mp15_dhcor_basic_defconfig >> b/configs/stm32mp15_dhcor_basic_defconfig >> index 387e068155e..83614b9fc8e 100644 >> --- a/configs/stm32mp15_dhcor_basic_defconfig >> +++ b/configs/stm32mp15_dhcor_basic_defconfig >> @@ -77,7 +77,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y >> CONFIG_SPL_ENV_IS_NOWHERE=y >> CONFIG_NET_RANDOM_ETHADDR=y >> CONFIG_IP_DEFRAG=y >> -CONFIG_TFTP_BLOCKSIZE=1536 >> CONFIG_STM32_ADC=y >> CONFIG_SPL_BLOCK_CACHE=y >> CONFIG_DFU_MMC=y > > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied to u-boot-stm32 Thanks Patrice
[PATCH 4/4] ARM: dts: stm32: add rcc node for STM32MP13
Add the RCC node, not yet in Linux kernel device tree
to handle the U-Boot RCC drivers.
Signed-off-by: Patrick Delaunay
---
arch/arm/dts/stm32mp13-u-boot.dtsi | 4
arch/arm/dts/stm32mp131.dtsi | 7 +++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi
b/arch/arm/dts/stm32mp13-u-boot.dtsi
index 1b5b358690..126f282816 100644
--- a/arch/arm/dts/stm32mp13-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp13-u-boot.dtsi
@@ -86,6 +86,10 @@
u-boot,dm-pre-reloc;
};
+&rcc {
+ u-boot,dm-pre-reloc;
+};
+
&syscfg {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
index 950e172e45..fcb0af09b5 100644
--- a/arch/arm/dts/stm32mp131.dtsi
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -159,6 +159,13 @@
dma-channels = <16>;
};
+ rcc: rcc@5000 {
+ compatible = "st,stm32mp13-rcc", "syscon";
+ reg = <0x5000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp13-exti", "syscon";
interrupt-controller;
--
2.25.1
[PATCH 1/4] clk: Add directory for STM32 clock drivers
Add a directory in drivers/clk to regroup the clock drivers for all
STM32 Soc with CONFIG_ARCH_STM32 (MCUs with cortex M) or
CONFIG_ARCH_STM32MP (MPUs with cortex A).
Signed-off-by: Patrick Delaunay
---
MAINTAINERS| 2 +-
drivers/clk/Kconfig| 17 +
drivers/clk/Makefile | 5 ++---
drivers/clk/stm32/Kconfig | 23 +++
drivers/clk/stm32/Makefile | 7 +++
drivers/clk/{ => stm32}/clk_stm32f.c | 0
drivers/clk/{ => stm32}/clk_stm32h7.c | 0
drivers/clk/{ => stm32}/clk_stm32mp1.c | 0
8 files changed, 34 insertions(+), 20 deletions(-)
create mode 100644 drivers/clk/stm32/Kconfig
create mode 100644 drivers/clk/stm32/Makefile
rename drivers/clk/{ => stm32}/clk_stm32f.c (100%)
rename drivers/clk/{ => stm32}/clk_stm32h7.c (100%)
rename drivers/clk/{ => stm32}/clk_stm32mp1.c (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 56be0bfad0..3f37edd716 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -469,7 +469,7 @@ S: Maintained
F: arch/arm/mach-stm32mp/
F: doc/board/st/
F: drivers/adc/stm32-adc*
-F: drivers/clk/clk_stm32mp1.c
+F: drivers/clk/stm32/
F: drivers/gpio/stm32_gpio.c
F: drivers/hwspinlock/stm32_hwspinlock.c
F: drivers/i2c/stm32f7_i2c.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 6dc271f71b..98ad481d9e 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -140,22 +140,6 @@ config CLK_SCMI
by a SCMI agent based on SCMI clock protocol communication
with a SCMI server.
-config CLK_STM32F
- bool "Enable clock driver support for STM32F family"
- depends on CLK && (STM32F7 || STM32F4)
- default y
- help
- This clock driver adds support for RCC clock management
- for STM32F4 and STM32F7 SoCs.
-
-config CLK_STM32MP1
- bool "Enable RCC clock driver for STM32MP1"
- depends on ARCH_STM32MP && CLK
- default y
- help
- Enable the STM32 clock (RCC) driver. Enable support for
- manipulating STM32MP1's on-SoC clocks.
-
config CLK_HSDK
bool "Enable cgu clock driver for HSDK boards"
depends on CLK && TARGET_HSDK
@@ -225,6 +209,7 @@ source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sifive/Kconfig"
+source "drivers/clk/stm32/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/ti/Kconfig"
source "drivers/clk/uniphier/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index bb4eee5d99..09fbaf6233 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -22,6 +22,8 @@ obj-$(CONFIG_ARCH_MESON) += meson/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
+obj-$(CONFIG_ARCH_STM32) += stm32/
+obj-$(CONFIG_ARCH_STM32MP) += stm32/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
@@ -38,8 +40,6 @@ obj-$(CONFIG_CLK_OWL) += owl/
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
obj-$(CONFIG_CLK_SIFIVE) += sifive/
-obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
-obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
@@ -52,4 +52,3 @@ obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
-obj-$(CONFIG_STM32H7) += clk_stm32h7.o
diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig
new file mode 100644
index 00..eac3fc1e9d
--- /dev/null
+++ b/drivers/clk/stm32/Kconfig
@@ -0,0 +1,23 @@
+config CLK_STM32F
+ bool "Enable clock driver support for STM32F family"
+ depends on CLK && (STM32F7 || STM32F4)
+ default y
+ help
+ This clock driver adds support for RCC clock management
+ for STM32F4 and STM32F7 SoCs.
+
+config CLK_STM32H7
+ bool "Enable clock driver support for STM32H7 family"
+ depends on CLK && STM32H7
+ default y
+ help
+ This clock driver adds support for RCC clock management
+ for STM32H7 SoCs.
+
+config CLK_STM32MP1
+ bool "Enable RCC clock driver for STM32MP15"
+ depends on ARCH_STM32MP && CLK
+ default y if STM32MP15x
+ help
+ Enable the STM32 clock (RCC) driver. Enable support for
+ manipulating STM32MP15's on-SoC clocks.
diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile
new file mode 100644
index 00..b420eeaa4e
--- /dev/null
+++ b/drivers/clk/stm32/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+
+obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
+obj-$(CONFIG
[PATCH 3/4] misc: stm32mp13: introduce STM32MP13 RCC driver
Add the MISC RCC driver for STM32MP13, and bind it to the RCC reset
driver, required for initial support.
Signed-off-by: Patrick Delaunay
---
drivers/misc/stm32_rcc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c
index f14d6e26d9..b816503bfa 100644
--- a/drivers/misc/stm32_rcc.c
+++ b/drivers/misc/stm32_rcc.c
@@ -39,6 +39,11 @@ struct stm32_rcc_clk stm32_rcc_clk_mp1 = {
.soc = STM32MP1,
};
+struct stm32_rcc_clk stm32_rcc_clk_mp13 = {
+ .drv_name = "stm32mp13_clk",
+ .soc = STM32MP1,
+};
+
static int stm32_rcc_bind(struct udevice *dev)
{
struct udevice *child;
@@ -79,6 +84,7 @@ static const struct udevice_id stm32_rcc_ids[] = {
{.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
{.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
{.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_clk_mp1 },
+ {.compatible = "st,stm32mp13-rcc", .data = (ulong)&stm32_rcc_clk_mp13 },
{ }
};
--
2.25.1
[PATCH 0/4] stm32mp: add minimal RCC support for STM32MP13
Add a minimal support for STM32MP13 RCC, the reset and clock controller
- update of the RCC MISC driver to bind the correct clock and reset driver
- reset driver, same than STM32MP15x = drivers/reset/stm32-reset.c
- clock driver, add a empty driver for STM32MP13x =
drivers/clk/stm32/clk-stm32mp13.c
- Add RCC node in SOC device tree with u-boot,dm-pre-reloc property
This serie is only a preliminary step for STM32MP13 clock and reset support
in U-Boot, based on Linux kernel binding introduced by [1] and it prepares
the next device tree alignment with Linux kernel.
The functional STMP13 clock driver based on CCF and on SCMI clocks
provided by OP-TEE and the clock and reset references in SOC device tree
will be pushed when the associated patches in [1] will be accepted.
[1] Introduction of STM32MP13 RCC driver (Reset Clock Controller)
https://lore.kernel.org/linux-arm-kernel/20220316131000.9874-1-gabriel.fernan...@foss.st.com/
Patrick Delaunay (4):
clk: Add directory for STM32 clock drivers
clk: stm32mp13: add a STM32MP13 RCC clock driver
misc: stm32mp13: introduce STM32MP13 RCC driver
ARM: dts: stm32: add rcc node for STM32MP13
MAINTAINERS| 2 +-
arch/arm/dts/stm32mp13-u-boot.dtsi | 4
arch/arm/dts/stm32mp131.dtsi | 7 ++
drivers/clk/Kconfig| 17 +-
drivers/clk/Makefile | 5 ++---
drivers/clk/stm32/Kconfig | 31 ++
drivers/clk/stm32/Makefile | 8 +++
drivers/clk/stm32/clk-stm32mp13.c | 21 +
drivers/clk/{ => stm32}/clk_stm32f.c | 0
drivers/clk/{ => stm32}/clk_stm32h7.c | 0
drivers/clk/{ => stm32}/clk_stm32mp1.c | 0
drivers/misc/stm32_rcc.c | 6 +
12 files changed, 81 insertions(+), 20 deletions(-)
create mode 100644 drivers/clk/stm32/Kconfig
create mode 100644 drivers/clk/stm32/Makefile
create mode 100644 drivers/clk/stm32/clk-stm32mp13.c
rename drivers/clk/{ => stm32}/clk_stm32f.c (100%)
rename drivers/clk/{ => stm32}/clk_stm32h7.c (100%)
rename drivers/clk/{ => stm32}/clk_stm32mp1.c (100%)
--
2.25.1
[PATCH 2/4] clk: stm32mp13: add a STM32MP13 RCC clock driver
Introduce a minimal STM32MP13 RCC driver only to allow bind of RCC MISC
driver.
Signed-off-by: Patrick Delaunay
---
drivers/clk/stm32/Kconfig | 8
drivers/clk/stm32/Makefile| 1 +
drivers/clk/stm32/clk-stm32mp13.c | 21 +
3 files changed, 30 insertions(+)
create mode 100644 drivers/clk/stm32/clk-stm32mp13.c
diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig
index eac3fc1e9d..7444164b81 100644
--- a/drivers/clk/stm32/Kconfig
+++ b/drivers/clk/stm32/Kconfig
@@ -21,3 +21,11 @@ config CLK_STM32MP1
help
Enable the STM32 clock (RCC) driver. Enable support for
manipulating STM32MP15's on-SoC clocks.
+
+config CLK_STM32MP13
+ bool "Enable RCC clock driver for STM32MP13"
+ depends on ARCH_STM32MP && CLK
+ default y if STM32MP13x
+ help
+ Enable the STM32 clock (RCC) driver. Enable support for
+ manipulating STM32MP13's on-SoC clocks.
diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile
index b420eeaa4e..feeb796f76 100644
--- a/drivers/clk/stm32/Makefile
+++ b/drivers/clk/stm32/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
obj-$(CONFIG_CLK_STM32H7) += clk_stm32h7.o
obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
+obj-$(CONFIG_CLK_STM32MP13) += clk-stm32mp13.o
\ No newline at end of file
diff --git a/drivers/clk/stm32/clk-stm32mp13.c
b/drivers/clk/stm32/clk-stm32mp13.c
new file mode 100644
index 00..afd116361b
--- /dev/null
+++ b/drivers/clk/stm32/clk-stm32mp13.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * Author: Gabriel Fernandez for STMicroelectronics.
+ */
+
+#define LOG_CATEGORY UCLASS_CLK
+
+#include
+#include
+
+static int stm32mp1_clk_probe(struct udevice *dev)
+{
+ return -EINVAL;
+}
+
+U_BOOT_DRIVER(stm32mp1_clock) = {
+ .name = "stm32mp13_clk",
+ .id = UCLASS_CLK,
+ .probe = stm32mp1_clk_probe,
+};
--
2.25.1
