[PATCH 5/5] CI: Add Aspeed AST2600

[Joel Stanley]

The AST2600 has a Qemu model that allows testing. Create a SPI NOR image
containing the combined SPL and u-boot FIT image.

Signed-off-by: Joel Stanley 
---
 .azure-pipelines.yml | 3 +++
 .gitlab-ci.yml   | 6 ++
 2 files changed, 9 insertions(+)

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index ad540ea63536..bdc515ebcdc1 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -261,6 +261,9 @@ stages:
 evb_ast2500:
   TEST_PY_BD: "evb-ast2500"
   TEST_PY_ID: "--id qemu"
+evb_ast2600:
+  TEST_PY_BD: "evb-ast2600"
+  TEST_PY_ID: "--id qemu"
 vexpress_ca9x4:
   TEST_PY_BD: "vexpress_ca9x4"
   TEST_PY_ID: "--id qemu"
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index c6a608f7e2a7..f9cd41750791 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -272,6 +272,12 @@ evb-ast2500 test.py:
 TEST_PY_ID: "--id qemu"
   <<: *buildman_and_testpy_dfn
 
+evb-ast2600 test.py:
+  variables:
+TEST_PY_BD: "evb-ast2600"
+TEST_PY_ID: "--id qemu"
+  <<: *buildman_and_testpy_dfn
+
 sandbox_flattree test.py:
   variables:
 TEST_PY_BD: "sandbox_flattree"
-- 
2.35.1

[PATCH 4/5] ast2600: Configure u-boot-with-spl.bin target

[Joel Stanley]

For the u-boot-with-spl.bin target to be useful for the AST2600, set the
maximum SPL size which also sets the padding length.

The normal way of loading u-boot is as a FIT, so configure u-boot.img as
the SPL playload.

With this the following simple steps can be used to build and boot a
system:

  make u-boot-with-spl.bin
  truncate -s 64M u-boot-with-spl.bin
  qemu-system-arm -nographic -M ast2600-evb \
-drive file=u-boot-with-spl.bin,if=mtd,format=raw

Signed-off-by: Joel Stanley 
---
 include/configs/evb_ast2600.h | 3 +++
 configs/evb-ast2600_defconfig | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h
index 3c2155da46df..f5ac88447b52 100644
--- a/include/configs/evb_ast2600.h
+++ b/include/configs/evb_ast2600.h
@@ -10,6 +10,9 @@
 
 #define CONFIG_SYS_UBOOT_BASE  CONFIG_SYS_TEXT_BASE
 
+/* The maximum size the AST2600 bootrom can load is 64KB */
+#define CONFIG_SPL_MAX_SIZE65536
+
 /* Misc */
 #define STR_HELPER(s)  #s
 #define STR(s) STR_HELPER(s)
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 160bccff48e2..5230515f7ab6 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -20,6 +20,8 @@ CONFIG_SPL_SIZE_LIMIT=0x1
 CONFIG_SPL=y
 # CONFIG_ARMV7_NONSEC is not set
 CONFIG_SYS_LOAD_ADDR=0x8300
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_SPL_FIT_SIGNATURE=y
-- 
2.35.1

[PATCH 3/5] config/ast2600: Disable hash hardware accel

[Joel Stanley]

The Qemu model or the u-boot driver is unable to correctly compute the
SHA256 hash used in a FIT. Disable it by default while that issue is
worked out to enable boot testing in Qemu.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index f3a6cb222020..160bccff48e2 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -59,9 +59,6 @@ CONFIG_REGMAP=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_DM_HASH=y
-CONFIG_HASH_ASPEED=y
-CONFIG_ASPEED_ACRY=y
 CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_MISC=y
-- 
2.35.1

[PATCH 2/5] config/ast2600: Make position independent

[Joel Stanley]

Allows loading one u-boot from another. Useful for testing on hardware.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 53ba36a28374..f3a6cb222020 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SYS_DCACHE_OFF=y
+CONFIG_POSITION_INDEPENDENT=y
 CONFIG_SPL_SYS_THUMB_BUILD=y
 CONFIG_ARCH_ASPEED=y
 CONFIG_SYS_TEXT_BASE=0x8000
-- 
2.35.1

[PATCH 1/5] config/ast2600: Enable CRC32

[Joel Stanley]

Useful for testing images with the default hash type.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index f84b723bbba3..53ba36a28374 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -35,6 +35,7 @@ CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
+CONFIG_SPL_CRC32=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_RAM_SUPPORT=y
-- 
2.35.1

[PATCH 0/5] aspeed: Add to CI

[Joel Stanley]

The Aspeed AST2600 is modelled in Qemu. This makes some configuration
changes so it can be added to CI.

It has a depednency on the u-boot-test-hooks patches I sent here:

 https://lore.kernel.org/u-boot/20220624023420.3925916-1-j...@jms.id.au

I've given it a run on Azure and the tests passed.

Joel Stanley (5):
  config/ast2600: Enable CRC32
  config/ast2600: Make position independent
  config/ast2600: Disable hash hardware accel
  ast2600: Configure u-boot-with-spl.bin target
  CI: Add Aspeed AST2600

 include/configs/evb_ast2600.h | 3 +++
 .azure-pipelines.yml  | 3 +++
 .gitlab-ci.yml| 6 ++
 configs/evb-ast2600_defconfig | 7 ---
 4 files changed, 16 insertions(+), 3 deletions(-)

-- 
2.35.1

[u-boot-test-hooks PATCH 2/2] travis-ci: Add Aspeed AST2600 Qemu configuration

[Joel Stanley]

Similar to the AST2500 this machine is emulated by Qemu. It boots from
a 64MB SPI NOR flash device by default.

Signed-off-by: Joel Stanley 
---
 bin/travis-ci/conf.evb-ast2600_qemu  | 13 +
 py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py |  4 
 2 files changed, 17 insertions(+)
 create mode 100644 bin/travis-ci/conf.evb-ast2600_qemu
 create mode 100644 py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py

diff --git a/bin/travis-ci/conf.evb-ast2600_qemu 
b/bin/travis-ci/conf.evb-ast2600_qemu
new file mode 100644
index ..386ff7d25774
--- /dev/null
+++ b/bin/travis-ci/conf.evb-ast2600_qemu
@@ -0,0 +1,13 @@
+# Copyright 2022 IBM Corp.
+# Joel Stanley 
+# SPDX-License-Identifier: GPL-2.0+
+
+console_impl=qemu
+qemu_machine="ast2600-evb"
+qemu_binary="qemu-system-arm"
+qemu_extra_args="-nographic -nic user,tftp=${UBOOT_TRAVIS_BUILD_DIR}"
+qemu_kernel_args="-drive file=${U_BOOT_BUILD_DIR}/flash.img,format=raw,if=mtd"
+flash_u_boot_bin="u-boot-with-spl.bin"
+reset_impl=none
+flash_impl=qemu_gen_padded_image
+flash_size=64
diff --git a/py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py 
b/py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py
new file mode 100644
index ..396261efa3a3
--- /dev/null
+++ b/py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py
@@ -0,0 +1,4 @@
+import travis_tftp
+
+env__net_dhcp_server = True
+env__net_tftp_readable_file = travis_tftp.file2env('u-boot')
-- 
2.35.1

[u-boot-test-hooks PATCH 1/2] ast2500: Simplify Qemu command line

[Joel Stanley]

The Aspeed machine in Qemu has appropriate defaults so we don't need to
specify these options.

Signed-off-by: Joel Stanley 
---
 bin/travis-ci/conf.evb-ast2500_qemu | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bin/travis-ci/conf.evb-ast2500_qemu 
b/bin/travis-ci/conf.evb-ast2500_qemu
index 7f0f3c56e006..2e9adc6af9b0 100644
--- a/bin/travis-ci/conf.evb-ast2500_qemu
+++ b/bin/travis-ci/conf.evb-ast2500_qemu
@@ -5,7 +5,7 @@
 console_impl=qemu
 qemu_machine="ast2500-evb"
 qemu_binary="qemu-system-arm"
-qemu_extra_args="-nographic -m 512M -serial mon:stdio -net nic,model=ftgmac100 
-net user,id=net0,tftp=${UBOOT_TRAVIS_BUILD_DIR}"
+qemu_extra_args="-nographic -nic user,tftp=${UBOOT_TRAVIS_BUILD_DIR}"
 qemu_kernel_args="-drive file=${U_BOOT_BUILD_DIR}/flash.img,format=raw,if=mtd"
 reset_impl=none
 flash_impl=qemu_gen_padded_image
-- 
2.35.1

[u-boot-test-hooks PATCH 0/2] Aspeed updates

[Joel Stanley]

Hi Tom,

This updates the configuration for the aspeed machines, adding support
for the ast2600.

Joel Stanley (2):
  ast2500: Simplify Qemu command line
  travis-ci: Add Aspeed AST2600 Qemu configuration

 bin/travis-ci/conf.evb-ast2500_qemu  |  2 +-
 bin/travis-ci/conf.evb-ast2600_qemu  | 13 +
 py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py |  4 
 3 files changed, 18 insertions(+), 1 deletion(-)
 create mode 100644 bin/travis-ci/conf.evb-ast2600_qemu
 create mode 100644 py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py

-- 
2.35.1

Re: [PATCH] sunxi: fix initial environment loading without MMC

[Samuel Holland]

Hi Andre,

>>> On 4/20/22 7:34 PM, Andre Przywara wrote:  
 Commit e42dad4168fe ("sunxi: use boot source for determining environment
 location") changed our implementation of env_get_location() and enabled
 it for every board, even those without MMC support (like the C.H.I.P.
 boards). However the default fallback location of ENVL_FAT does not cope
 very well without MMC support compiled in, so the board hangs when trying
 to initially load the environment.

 Change the default fallback location to be ENVL_FAT only when the FAT
 environment support is enabled, and use ENVL_NOWHERE and ENVL_UBI as
 alternative fallbacks, when those sources are enabled.

 This fixes U-Boot loading on the C.H.I.P. boards.

 Fixes: e42dad4168fe ("sunxi: use boot source for determining environment 
 location")
 Reported-by: Chris Morgan 
 Signed-off-by: Andre Przywara 
 ---
  board/sunxi/board.c | 9 -
  1 file changed, 8 insertions(+), 1 deletion(-)

 diff --git a/board/sunxi/board.c b/board/sunxi/board.c
 index 89324159d55..befb6076ca6 100644
 --- a/board/sunxi/board.c
 +++ b/board/sunxi/board.c
 @@ -132,7 +132,14 @@ void i2c_init_board(void)
   */
  enum env_location env_get_location(enum env_operation op, int prio)
  {
 -  enum env_location boot_loc = ENVL_FAT;
 +  enum env_location boot_loc;
 +
 +  if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
 +  boot_loc = ENVL_NOWHERE;
 +  else if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
 +  boot_loc = ENVL_FAT;
 +  else if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
 +  boot_loc = ENVL_UBI;  
>>>
>>> This could leave boot_loc uninitialized. And there is still an 
>>> unconditional use
>>> of ENVL_FAT in the BOOT_DEVICE_MMCx case.  
>>
>> Yeah, it's a mess, and there doesn't seem to be a one-fits-all fallback
>> value. Returning ENVL_UNKNOWN when prio is 0 definitely hangs, as does
>> returning some source without having the corresponding driver compiled in,
>> so getting this right *and* nice-looking is a bit tricky.
>>
gd->env_load_prio = prio;  
>>>
>>> I don't think the hook is supposed to change this variable.  
>>
>> Yeah, don't remember why I initially put that in, I must have copied that
>> from somewhere. All I remember is that this code is touchy (as the bug
>> report leading to that patch shows), and there are quite some corner cases
>> to test.
>>
>>> I'm still a bit confused on the fallback logic you have in place. Splitting 
>>> it
>>> up into three blocks doesn't help. If the goal is to load the environment 
>>> from
>>> the boot device, while preferring filesystems over raw block devices, I 
>>> propose
>>> the following:  
>>
>> Admittedly this gets messier, I mainly wanted to fix the regression
>> quickly, since it already broke the release for the CHIP boards.
>> I will have a closer look at your suggestion and check for those corner
>> cases, but will probably go with that instead of piling up more cruft on
>> my previous code ;-)
> 
> So I was about to submit your solution, but this is suffering from the
> same old problem: we must not return ENVL_UNKNOWN on the first call.
> FEL booting triggers this: it will lead to env_init() returning a
> negative error value, which is fatal, as it's part of init_sequence_f[].
> I think the proper fix is to treat this case the same as the -ENOENT
> case at the end of env_init(), but I don't dare to do this generic
> change this late in the cycle.
> My plan is to hack-fix this for sunxi, for now (see below), then
> propose the generic change for the next cycle. Does this sound OK?
> Another solution is to always select ENV_IS_NOWHERE, then return this,
> but I don't know if this has more side effects, so is also risky at
> this point.

Yes, this sounds reasonable to me.

Regards,
Samuel

>>>
>>> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
>>> index 427113534b..27508bd306 100644
>>> --- a/board/sunxi/board.c
>>> +++ b/board/sunxi/board.c
>>> @@ -129,26 +129,38 @@
>>>   * Try to use the environment from the boot source first.
>>>   * For MMC, this means a FAT partition on the boot device (SD or eMMC).
>>>   * If the raw MMC environment is also enabled, this is tried next.
>>> - * SPI flash falls back to FAT (on SD card).
>>>   */
>>>  enum env_location env_get_location(enum env_operation op, int prio)
>>>  {
>>> -   enum env_location boot_loc = ENVL_FAT;
>>> +   if (prio > 1)
>>> +   return ENVL_UNKNOWN;
>>>
>>> -   gd->env_load_prio = prio;
>>> +   if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
>>> +   return ENVL_NOWHERE;
>>>
>>> switch (sunxi_get_boot_device()) {
>>> case BOOT_DEVICE_MMC1:
>>> case BOOT_DEVICE_MMC2:
>>> -   boot_loc = ENVL_FAT;
>>> +   if (prio == 0) {
>>> +   if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
>>> +   return ENVL_EXT4;
>>> +   if (IS_ENABLE

Re: [PATCH] sunxi: fix initial environment loading without MMC

[Andre Przywara]

On Tue, 26 Apr 2022 15:25:56 +0100
Andre Przywara  wrote:

Hi Samuel,

> On Sat, 23 Apr 2022 16:01:00 -0500
> Samuel Holland  wrote:
> 
> Hi Samuel,
> 
> thanks for having a look and the comments.
> 
> > On 4/20/22 7:34 PM, Andre Przywara wrote:  
> > > Commit e42dad4168fe ("sunxi: use boot source for determining environment
> > > location") changed our implementation of env_get_location() and enabled
> > > it for every board, even those without MMC support (like the C.H.I.P.
> > > boards). However the default fallback location of ENVL_FAT does not cope
> > > very well without MMC support compiled in, so the board hangs when trying
> > > to initially load the environment.
> > > 
> > > Change the default fallback location to be ENVL_FAT only when the FAT
> > > environment support is enabled, and use ENVL_NOWHERE and ENVL_UBI as
> > > alternative fallbacks, when those sources are enabled.
> > > 
> > > This fixes U-Boot loading on the C.H.I.P. boards.
> > > 
> > > Fixes: e42dad4168fe ("sunxi: use boot source for determining environment 
> > > location")
> > > Reported-by: Chris Morgan 
> > > Signed-off-by: Andre Przywara 
> > > ---
> > >  board/sunxi/board.c | 9 -
> > >  1 file changed, 8 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> > > index 89324159d55..befb6076ca6 100644
> > > --- a/board/sunxi/board.c
> > > +++ b/board/sunxi/board.c
> > > @@ -132,7 +132,14 @@ void i2c_init_board(void)
> > >   */
> > >  enum env_location env_get_location(enum env_operation op, int prio)
> > >  {
> > > - enum env_location boot_loc = ENVL_FAT;
> > > + enum env_location boot_loc;
> > > +
> > > + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
> > > + boot_loc = ENVL_NOWHERE;
> > > + else if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
> > > + boot_loc = ENVL_FAT;
> > > + else if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
> > > + boot_loc = ENVL_UBI;  
> > 
> > This could leave boot_loc uninitialized. And there is still an 
> > unconditional use
> > of ENVL_FAT in the BOOT_DEVICE_MMCx case.  
> 
> Yeah, it's a mess, and there doesn't seem to be a one-fits-all fallback
> value. Returning ENVL_UNKNOWN when prio is 0 definitely hangs, as does
> returning some source without having the corresponding driver compiled in,
> so getting this right *and* nice-looking is a bit tricky.
> 
> > >   gd->env_load_prio = prio;  
> > 
> > I don't think the hook is supposed to change this variable.  
> 
> Yeah, don't remember why I initially put that in, I must have copied that
> from somewhere. All I remember is that this code is touchy (as the bug
> report leading to that patch shows), and there are quite some corner cases
> to test.
> 
> > I'm still a bit confused on the fallback logic you have in place. Splitting 
> > it
> > up into three blocks doesn't help. If the goal is to load the environment 
> > from
> > the boot device, while preferring filesystems over raw block devices, I 
> > propose
> > the following:  
> 
> Admittedly this gets messier, I mainly wanted to fix the regression
> quickly, since it already broke the release for the CHIP boards.
> I will have a closer look at your suggestion and check for those corner
> cases, but will probably go with that instead of piling up more cruft on
> my previous code ;-)

So I was about to submit your solution, but this is suffering from the
same old problem: we must not return ENVL_UNKNOWN on the first call.
FEL booting triggers this: it will lead to env_init() returning a
negative error value, which is fatal, as it's part of init_sequence_f[].
I think the proper fix is to treat this case the same as the -ENOENT
case at the end of env_init(), but I don't dare to do this generic
change this late in the cycle.
My plan is to hack-fix this for sunxi, for now (see below), then
propose the generic change for the next cycle. Does this sound OK?
Another solution is to always select ENV_IS_NOWHERE, then return this,
but I don't know if this has more side effects, so is also risky at
this point.

> > 
> > diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> > index 427113534b..27508bd306 100644
> > --- a/board/sunxi/board.c
> > +++ b/board/sunxi/board.c
> > @@ -129,26 +129,38 @@
> >   * Try to use the environment from the boot source first.
> >   * For MMC, this means a FAT partition on the boot device (SD or eMMC).
> >   * If the raw MMC environment is also enabled, this is tried next.
> > - * SPI flash falls back to FAT (on SD card).
> >   */
> >  enum env_location env_get_location(enum env_operation op, int prio)
> >  {
> > -   enum env_location boot_loc = ENVL_FAT;
> > +   if (prio > 1)
> > +   return ENVL_UNKNOWN;
> > 
> > -   gd->env_load_prio = prio;
> > +   if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
> > +   return ENVL_NOWHERE;
> > 
> > switch (sunxi_get_boot_device()) {
> > case BOOT_DEVICE_MMC1:
> > case BOOT_DEVICE_MMC2:
> > -   boot_loc = ENVL_FAT;
> > +   if (prio == 0) {
> > + 

[PATCH] qemu_arm64: Enable CONFIG_ARMV8_CRYPTO support

[Tom Rini]

Now that we can make use of CPU features for sha1/sha256, enable in QEMU
so that we get some test coverage.

Cc: Loic Poulain 
Cc: Tuomas Tynkkynen 
Signed-off-by: Tom Rini 
---
 configs/qemu_arm64_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig
index 87acf00f30e3..f7c93ba2af54 100644
--- a/configs/qemu_arm64_defconfig
+++ b/configs/qemu_arm64_defconfig
@@ -8,6 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x4
 CONFIG_DEFAULT_DEVICE_TREE="qemu-arm64"
 CONFIG_DEBUG_UART_BASE=0x900
 CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_ARMV8_CRYPTO=y
 CONFIG_SYS_LOAD_ADDR=0x4020
 CONFIG_ENV_ADDR=0x400
 CONFIG_DEBUG_UART=y
-- 
2.25.1

Re: [PATCH 1/3] mmc: stm32_sdmmc2: cosmetic: rename stm32_sdmmc_bind

[Marek Vasut]

On 6/20/22 18:13, Patrick Delaunay wrote:

Rename stm32_sdmmc_bind to stm32_sdmmc2_bind as all oter function


s@oter@other@ typo

Re: [PATCH 4/4] drivers: rng: add smccc trng driver

[Tom Rini]

On Wed, Jun 01, 2022 at 10:27:34AM +0200, Etienne Carriere wrote:

> Adds random number generator driver using Arm SMCCC TRNG interface to
> get entropy bytes from secure monitor. The driver registers as an
> Arm SMCCC feature driver to allow PSCI driver to bind a device for
> when secure monitor exposes RNG support from Arm SMCCC TRNG interface.
> 
> Cc: Sughosh Ganu 
> Cc: Heinrich Schuchardt 
> Signed-off-by: Etienne Carriere 

Applied to u-boot/next, thanks!

-- 
Tom


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Description: PGP signature

Re: [PATCH 3/4] firmware: psci: bind arm smccc features when discovered

[Tom Rini]

On Wed, Jun 01, 2022 at 10:27:33AM +0200, Etienne Carriere wrote:

> Use PSCI device to query Arm SMCCC v1.1 support from secure monitor
> and if so, bind drivers for the SMCCC features that monitor supports.
> 
> Drivers willing to be bound from Arm SMCCC features discovery can use
> macro ARM_SMCCC_FEATURE_DRIVER() to register to smccc feature discovery,
> providing target driver name and a callback function that returns
> whether or not the SMCCC feature is supported by the system.
> 
> Signed-off-by: Etienne Carriere 

Applied to u-boot/next, thanks!

-- 
Tom


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Description: PGP signature

Re: [PATCH 2/4] firmware: psci: reorder header files inclusion

[Tom Rini]

On Wed, Jun 01, 2022 at 10:27:32AM +0200, Etienne Carriere wrote:

> Fixes ordering of header files inclusion in PSCI firmware driver.
> 
> Signed-off-by: Etienne Carriere 

Applied to u-boot/next, thanks!

-- 
Tom


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Description: PGP signature

Re: [PATCH 1/4] smccc: define generic IDs for feature discovery

[Tom Rini]

On Wed, Jun 01, 2022 at 10:27:31AM +0200, Etienne Carriere wrote:

> Defines function IDs ARM_SMCCC_ARCH_FEATURES used to query SMCCC feature
> support, applicable from Arm SMCCC v1.1 specification.
> 
> Defines macro ARM_SMCCC_RET_NOT_SUPPORTED as generic return identifier
> for when a SMCCC feature is not supported.
> 
> Signed-off-by: Etienne Carriere 

Applied to u-boot/next, thanks!

-- 
Tom


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Description: PGP signature

Re: [PATCH v2 01/14] firmware: scmi: optee: use TEE shared memory for SCMI messages

[Tom Rini]

On Tue, May 31, 2022 at 06:09:16PM +0200, Etienne Carriere wrote:

> Changes implementation when using TEE dynamically allocated shared
> memory to synchronize with the Linux implementation where the legacy
> SMT protocol cannot be used with such memory since it is expected from
> device mapped memory whereas OP-TEE shared memory is cached and
> hence should not be accessed using memcpy_toio()/memcpy_fromio().
> 
> This change implements the MSG shared memory protocol introduced
> in Linux [1]. The protocol uses a simplified SMT header of 32bit
> named MSG_SMT to carry SCMI protocol information and uses side channel
> means to carry exchanged buffer size information, as TEE invocation API
> parameters when used in the SCMI OP-TEE transport.
> 
> Link: [1] 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f301bba0ca7392d16a6ea4f1d264a91f1fadea1a
> Signed-off-by: Etienne Carriere 

For the series, applied to u-boot/next, thanks!

-- 
Tom


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Description: PGP signature

Re: [PATCH v3 01/13] serial: sandbox: Fix buffer underflow in puts

[Tom Rini]

On Mon, May 30, 2022 at 10:00:01AM +, Andrew Scull wrote:

> Fix the buffer underflow that would occur if puts is called with length
> of zero.
> 
> Fixes: efa51f2bd64 ("serial: sandbox: Implement puts")
> Cc: Sean Anderson 
> Cc: Simon Glass 
> Reviewed-by: Sean Anderson 

For the series, applied to u-boot/next, thanks!

-- 
Tom


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Description: PGP signature

Re: [PATCH 2/2] imx: kontron-sl-mx8mm: Enable PCA9450 regulator driver and fix SD card access

[Fabio Estevam]

On 23/06/2022 14:42, Frieder Schrempf wrote:

From: Frieder Schrempf 

Currently accessing the SD card on USDHC2 fails with:

=> mmc dev 1
Card did not respond to voltage select! : -110

This is due to the fact that UHS modes are enabled in the defconfig
and the devicetree, but the referenced LDO5 regulator (reg_nvcc_sd)
is not available to switch the data lines from 3.3V to 1.8V mode.

By enabling the regulator driver the vqmmc-supply is now available
and the SD card works also in high speed modes:

=> mmc dev 1
switch to partitions #0, OK
mmc1 is current device

Please note that the board has a GPIO connected to the SD_VSEL signal
of the PMIC. As the driver uses the LDO5CTRL_H register to set the
voltage, we need to make sure that this GPIO (GPIO01_IO4) is set to
a high level.

Signed-off-by: Frieder Schrempf 


Reviewed-by: Fabio Estevam 

Re: [PATCH 1/2] pmic: pca9450: Add optional SD_VSEL GPIO for LDO5

[Fabio Estevam]

On 23/06/2022 14:42, Frieder Schrempf wrote:

From: Frieder Schrempf 

LDO5 has two separate control registers. LDO5CTRL_L is used if the
input signal SD_VSEL is low and LDO5CTRL_H if it is high.
The current driver implementation only uses LDO5CTRL_H. To make this
work on boards that have SD_VSEL connected to a GPIO, we add support
for specifying an optional GPIO and setting it to high at probe time.

In the future we might also want to add support for boards that have
SD_VSEL set to a fixed low level. In this case we need to change the
driver to be able to use the LDO5CTRL_L register.

This is a port of the same change in the Linux kernel:
8c67a11bae88 ("regulator: pca9450: Add SD_VSEL GPIO for LDO5")

Signed-off-by: Frieder Schrempf 


Reviewed-by: Fabio Estevam 

[PATCH 2/2] imx: kontron-sl-mx8mm: Enable PCA9450 regulator driver and fix SD card access

[Frieder Schrempf]

From: Frieder Schrempf 

Currently accessing the SD card on USDHC2 fails with:

=> mmc dev 1
Card did not respond to voltage select! : -110

This is due to the fact that UHS modes are enabled in the defconfig
and the devicetree, but the referenced LDO5 regulator (reg_nvcc_sd)
is not available to switch the data lines from 3.3V to 1.8V mode.

By enabling the regulator driver the vqmmc-supply is now available
and the SD card works also in high speed modes:

=> mmc dev 1
switch to partitions #0, OK
mmc1 is current device

Please note that the board has a GPIO connected to the SD_VSEL signal
of the PMIC. As the driver uses the LDO5CTRL_H register to set the
voltage, we need to make sure that this GPIO (GPIO01_IO4) is set to
a high level.

Signed-off-by: Frieder Schrempf 
---
Hi Tom, sorry for another late fix. I just keep discovering things
that are broken.

Please note that this depends on a driver change in patch 1 of this
series.
---
 configs/kontron-sl-mx8mm_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/kontron-sl-mx8mm_defconfig 
b/configs/kontron-sl-mx8mm_defconfig
index 2e9d52522b2..727f99f0063 100644
--- a/configs/kontron-sl-mx8mm_defconfig
+++ b/configs/kontron-sl-mx8mm_defconfig
@@ -99,6 +99,7 @@ CONFIG_DM_PMIC=y
 CONFIG_DM_PMIC_PCA9450=y
 CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_RV8803=y
 CONFIG_CONS_INDEX=2
-- 
2.36.1

[PATCH 1/2] pmic: pca9450: Add optional SD_VSEL GPIO for LDO5

[Frieder Schrempf]

From: Frieder Schrempf 

LDO5 has two separate control registers. LDO5CTRL_L is used if the
input signal SD_VSEL is low and LDO5CTRL_H if it is high.
The current driver implementation only uses LDO5CTRL_H. To make this
work on boards that have SD_VSEL connected to a GPIO, we add support
for specifying an optional GPIO and setting it to high at probe time.

In the future we might also want to add support for boards that have
SD_VSEL set to a fixed low level. In this case we need to change the
driver to be able to use the LDO5CTRL_L register.

This is a port of the same change in the Linux kernel:
8c67a11bae88 ("regulator: pca9450: Add SD_VSEL GPIO for LDO5")

Signed-off-by: Frieder Schrempf 
---
 drivers/power/pmic/pca9450.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c
index 116ac49a8db..6b9befba18c 100644
--- a/drivers/power/pmic/pca9450.c
+++ b/drivers/power/pmic/pca9450.c
@@ -7,9 +7,12 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -26,6 +29,10 @@ static const struct pmic_child_info pmic_children_info[] = {
{ },
 };
 
+struct pca9450_priv {
+   struct gpio_desc *sd_vsel_gpio;
+};
+
 static int pca9450_reg_count(struct udevice *dev)
 {
return PCA9450_REG_NUM;
@@ -76,6 +83,24 @@ static int pca9450_bind(struct udevice *dev)
return 0;
 }
 
+static int pca9450_probe(struct udevice *dev)
+{
+   struct pca9450_priv *priv = dev_get_priv(dev);
+   int ret = 0;
+
+   if (IS_ENABLED(CONFIG_DM_GPIO) && 
IS_ENABLED(CONFIG_DM_REGULATOR_PCA9450)) {
+   priv->sd_vsel_gpio = devm_gpiod_get_optional(dev, "sd-vsel",
+GPIOD_IS_OUT |
+
GPIOD_IS_OUT_ACTIVE);
+   if (IS_ERR(priv->sd_vsel_gpio)) {
+   ret = PTR_ERR(priv->sd_vsel_gpio);
+   dev_err(dev, "Failed to request SD_VSEL GPIO: %d\n", 
ret);
+   }
+   }
+
+   return ret;
+}
+
 static struct dm_pmic_ops pca9450_ops = {
.reg_count = pca9450_reg_count,
.read = pca9450_read,
@@ -94,5 +119,7 @@ U_BOOT_DRIVER(pmic_pca9450) = {
.id = UCLASS_PMIC,
.of_match = pca9450_ids,
.bind = pca9450_bind,
+   .probe = pca9450_probe,
.ops = &pca9450_ops,
+   .priv_auto = sizeof(struct pca9450_priv),
 };
-- 
2.36.1

Re: [PATCH 1/2] powerpc: mpc85xx: Add support for generating QorIQ pre-PBL eSDHC boot sector

[Pali Rohár]

On Saturday 04 June 2022 15:02:38 Pali Rohár wrote:
> On Wednesday 18 May 2022 12:53:20 Pali Rohár wrote:
> > On Wednesday 11 May 2022 22:59:28 Pali Rohár wrote:
> > > On Monday 25 April 2022 14:36:14 Pali Rohár wrote:
> > > > On Monday 25 April 2022 05:25:34 Priyanka Jain (OSS) wrote:
> > > > > >-Original Message-
> > > > > >From: U-Boot  On Behalf Of Pali Rohár
> > > > > >Sent: Tuesday, April 5, 2022 7:11 PM
> > > > > >To: Priyanka Jain ; Qiang Zhao 
> > > > > >;
> > > > > >Shengzhou Liu ; Alexander Graf 
> > > > > >;
> > > > > >Bin Meng ; Wolfgang Denk ; Sinan
> > > > > >Akman 
> > > > > >Cc: u-boot@lists.denx.de
> > > > > >Subject: [PATCH 1/2] powerpc: mpc85xx: Add support for generating 
> > > > > >QorIQ pre-
> > > > > >PBL eSDHC boot sector
> > > > > >
> > > > > >QorIQ U-Boot binary for SD card booting compiled during build 
> > > > > >process (either u-
> > > > > >boot.bin or u-boot-with-spl.bin) cannot be directly loaded by QorIQ 
> > > > > >pre-PBL
> > > > > >BootROM. Compiled U-Boot binary first needs to be processed by 
> > > > > >Freescale
> > > > > >boot_format tool as described in doc/README.mpc85xx-sd-spi-boot
> > > > > >
> > > > > >BootROM requires that image on SD card must contain special boot 
> > > > > >sector.
> > > > > >Implement support for generating this special boot sector directly 
> > > > > >in U-Boot start
> > > > > >code. Boot sector needs to be at the beginning of the image, so when 
> > > > > >compiling
> > > > > >only proper U-Boot without SPL then it needs to be in proper U-Boot. 
> > > > > >When
> > > > > >compiling SPL with proper U-Boot then it needs to be only in SPL.
> > > > > >
> > > > > >Support can be enabled by a new config option
> > > > > >FSL_PREPBL_ESDHC_BOOT_SECTOR.
> > > > > >Via other two additional options FSL_PREPBL_ESDHC_BOOT_SECTOR_START 
> > > > > >and
> > > > > >FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA it is possible to tune how final 
> > > > > >U-Boot
> > > > > >image could be stored on the SD card.
> > > > > >
> > > > > >Signed-off-by: Pali Rohár 
> > > > > >---
> > > > > 
> > > > > Kindly rebase the series to master.
> > > > > 
> > > > > Regards
> > > > > Priyanka
> > > > 
> > > > Hello! Both patches still applies cleanly on master, just they depend
> > > > on another patch series (powerpc: mpc85xx: Fix and cleanup mpc85xx code)
> > > > which I mentioned in cover letter and therefore needs V2 patch of
> > > > "powerpc: mpc85xx: Set TEXT_BASE addresses to real base values" which I
> > > > sent recently.
> > > 
> > > I sent a new version v2 of this patch, see email:
> > > [PATCH v2] powerpc: mpc85xx: Add support for generating QorIQ pre-PBL 
> > > eSDHC boot sector
> > 
> > Priyanka: PING
> 
> PING?

PING?

[PATCH v2] board: freescale: p1_p2_rdb_pc: Remove mapping for TDM-PMC card

[Pali Rohár]

>From whole P1/P2 family of RDB boards is TDM-PMC card (PCI Mezzanine Card,
Freescale PQ-MDS-T1) available only on P1021RDB and P1025RDB boards.

So address mapping for TDM-PMC card on LBC should not be enabled on any
other P1/P2 RDB board as there is no device at that TDM-PMC address.

Support for P1021RDB and P1025RDB boards was already removed from mainline
U-Boot in commits 6d1dd76afe85 ("board/freescale: Remove P1021RDB board
support") and d521cece5adb ("board/freescale: Remove P1025RDB board
support").

So do not enable TDM-PMC address mapping on remaining P1/P2 RDB boards and
remove all macros related to TDM-PMC address mappings.

Signed-off-by: Pali Rohár 
---
Changes in v2:
* Rebase on top of next branch, commit 9121478ee6f2aee381f8fe49d8997d43527d351a
---
 board/freescale/p1_p2_rdb_pc/law.c | 1 -
 board/freescale/p1_p2_rdb_pc/tlb.c | 3 ---
 include/configs/p1_p2_rdb_pc.h | 9 -
 scripts/config_whitelist.txt   | 4 
 4 files changed, 17 deletions(-)

diff --git a/board/freescale/p1_p2_rdb_pc/law.c 
b/board/freescale/p1_p2_rdb_pc/law.c
index 5f4d713ca569..6bdfb356eede 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -9,7 +9,6 @@
 
 struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-   SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
 #ifdef CONFIG_VSC7385_ENET
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c 
b/board/freescale/p1_p2_rdb_pc/tlb.c
index 6ded38ac683e..38843a96cbfb 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -65,9 +65,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
-   SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
-   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-   0, 10, BOOKE_PAGESZ_64K, 1),
 #endif /* not SPL */
 
 #ifdef CONFIG_SYS_NAND_BASE
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 56a16502dcc7..f95a77b7ed32 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -182,7 +182,6 @@
  * 0xf8f8_ 0xf8ff_ L2 SRAM Up to 512K cacheable
  *   (early boot only)
  * 0xff80_ 0xff80_7fff NAND flash  32K non-cacheable   CS1/0
- * 0xff98_ 0xff98_ PMC 64K non-cacheable   CS2
  * 0xffa0_ 0xffaf_ CPLD1M non-cacheableCS3
  * 0xffb0_ 0xffbf_ VSC7385 switch  1M non-cacheableCS2
  * 0xffc0_ 0xffc3_ PCI IO range256k non-cacheable
@@ -289,14 +288,6 @@
 #endif
 /* CPLD config size: 1Mb */
 
-#define CONFIG_SYS_PMC_BASE0xff98
-#define CONFIG_SYS_PMC_BASE_PHYS   CONFIG_SYS_PMC_BASE
-#define CONFIG_PMC_BR_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
-   BR_PS_8 | BR_V)
-#define CONFIG_PMC_OR_PRELIM   (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
-OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
-OR_GPCM_EAD)
-
 /* Vsc7385 switch */
 #ifdef CONFIG_VSC7385_ENET
 #define __VSCFW_ADDR   "vscfw_addr=ef00\0"
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 726973b26e21..7fed8b612bd7 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -456,8 +456,6 @@ CONFIG_PHY_IRAM_BASE
 CONFIG_PL011_CLOCK
 CONFIG_PL01x_PORTS
 CONFIG_PM
-CONFIG_PMC_BR_PRELIM
-CONFIG_PMC_OR_PRELIM
 CONFIG_PME_PLAT_CLK_DIV
 CONFIG_POST
 CONFIG_POSTBOOTMENU
@@ -1465,8 +1463,6 @@ CONFIG_SYS_PLL_FDR
 CONFIG_SYS_PLL_ODR
 CONFIG_SYS_PLL_SETTLING_TIME
 CONFIG_SYS_PMAN
-CONFIG_SYS_PMC_BASE
-CONFIG_SYS_PMC_BASE_PHYS
 CONFIG_SYS_PME_CLK
 CONFIG_SYS_POST_MEMORY
 CONFIG_SYS_POST_MEM_REGIONS
-- 
2.20.1

Re: [PATCH] mmc: fsl_esdhc: Fix 'Internal clock never stabilised.' error

[Pali Rohár]

On Tuesday 14 June 2022 11:25:18 Jaehoon Chung wrote:
> Hi,
> 
> On 6/12/22 18:12, Pali Rohár wrote:
> > PING?
> 
> Sorry for too late. 

When will be this fix patch processed and merged?

> > 
> > On Friday 29 April 2022 20:27:34 Pali Rohár wrote:
> >> Only newer eSDHC controllers set PRSSTAT_SDSTB flag. So do not wait until
> >> flag PRSSTAT_SDSTB is set on old pre-2.2 controllers. Instead sleep for
> >> fixed amount of time like it was before commit 6f883e501b65 ("mmc:
> >> fsl_esdhc: Add emmc hs200 support").
> >>
> >> This change fixes error 'Internal clock never stabilised.' which is printed
> >> on P2020 board at every access to SD card.
> >>
> >> Fixes: 6f883e501b65 ("mmc: fsl_esdhc: Add emmc hs200 support")
> >> Signed-off-by: Pali Rohár 
> 
> Reviewed-by: Jaehoon Chung 
> 
> Best Regards,
> Jaehoon Chung
> 
> >> ---
> >>  drivers/mmc/fsl_esdhc.c | 17 +
> >>  1 file changed, 17 insertions(+)
> >>
> >> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> >> index fdf2cc290e06..3b3587bd8d72 100644
> >> --- a/drivers/mmc/fsl_esdhc.c
> >> +++ b/drivers/mmc/fsl_esdhc.c
> >> @@ -503,6 +503,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, 
> >> struct mmc *mmc, uint clock)
> >>u32 time_out;
> >>u32 value;
> >>uint clk;
> >> +  u32 hostver;
> >>  
> >>if (clock < mmc->cfg->f_min)
> >>clock = mmc->cfg->f_min;
> >> @@ -543,6 +544,14 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, 
> >> struct mmc *mmc, uint clock)
> >>  
> >>esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
> >>  
> >> +  /* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */
> >> +  hostver = esdhc_read32(&priv->esdhc_regs->hostver);
> >> +  if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) {
> >> +  udelay(1);
> >> +  esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
> >> +  return;
> >> +  }
> >> +
> >>time_out = 20;
> >>value = PRSSTAT_SDSTB;
> >>while (!(esdhc_read32(®s->prsstat) & value)) {
> >> @@ -562,6 +571,7 @@ static void esdhc_clock_control(struct fsl_esdhc_priv 
> >> *priv, bool enable)
> >>struct fsl_esdhc *regs = priv->esdhc_regs;
> >>u32 value;
> >>u32 time_out;
> >> +  u32 hostver;
> >>  
> >>value = esdhc_read32(®s->sysctl);
> >>  
> >> @@ -572,6 +582,13 @@ static void esdhc_clock_control(struct fsl_esdhc_priv 
> >> *priv, bool enable)
> >>  
> >>esdhc_write32(®s->sysctl, value);
> >>  
> >> +  /* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */
> >> +  hostver = esdhc_read32(&priv->esdhc_regs->hostver);
> >> +  if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) {
> >> +  udelay(1);
> >> +  return;
> >> +  }
> >> +
> >>time_out = 20;
> >>value = PRSSTAT_SDSTB;
> >>while (!(esdhc_read32(®s->prsstat) & value)) {
> >> -- 
> >> 2.20.1
> >>
> > 
> 

Re: [PATCH] distroboot: Fix ubifs

[Pali Rohár]

On Tuesday 31 May 2022 10:32:36 Pali Rohár wrote:
> Fix multiple issues in ubifs distroboot code:
> 
> U-Boot supports attaching only one MTD device as UBI at the time. So
> always call 'ubifsmount ubi0:${bootubivol}' for mounting UBI volume
> ${bootubivol}. Usage of 'ubi${devnum}' is incorrect as 'ubi part'
> command attach MTD device always as UBI device ubi0.
> 
> Set distroboot ${bootfstype} variable to ubifs in ubifs_boot command.
> Distroboot scripts require ${bootfstype} variable to be properly set and it
> is already set for all other boot types.
> 
> Set distroboot ${distro_bootpart} variable to ${bootubivol} value. UBI
> device does not have partitions, but has volumes. Distroboot scripts
> require something to be set in ${distro_bootpart} variable, so set it to
> the UBI volume which is currently mounted by ubifs.
> 
> Set distroboot ${devnum} variable to fixed string "ubi0". ubifs code
> differs from the other partition code that it requires "ubi" prefix before
> number.
> 
> Explicitly unmount ubifs volume after loading all data from it. This allows
> to detach UBI device from MTD device.
> 
> Move definition of MTD device with UBI and UBI volume with ubifs filesystem
> from global env variables ${bootubipart} and ${bootubivol} into the
> distroboot "func" macro, defined in board include config files. UBIFS
> distroboot macros then set ${bootubipart} and ${bootubivol} local variables
> for compatibility with existing distroboot scripts.
> 
> This last change allows to define more UBIFS target devices and make it
> clear what is boot MTD/UBI device.
> 
> All board include config files are adjusted to use this new scheme of
> specifying boot MTD/UBI device.
> 
> Signed-off-by: Pali Rohár 
> ---
> CI test passed on https://github.com/u-boot/u-boot/pull/179
> ---

PING?

>  include/config_distro_bootcmd.h| 27 ---
>  include/configs/am335x_guardian.h  |  3 +--
>  include/configs/colibri-imx6ull.h  |  1 -
>  include/configs/colibri_imx7.h |  1 -
>  include/configs/kontron-sl-mx6ul.h |  2 +-
>  include/configs/mys_6ulx.h |  2 +-
>  include/configs/npi_imx6ull.h  |  2 +-
>  include/configs/omap3_beagle.h |  4 +---
>  include/configs/omap3_evm.h|  4 +---
>  include/configs/pcl063.h   |  2 +-
>  include/configs/stm32mp15_common.h |  2 +-
>  include/configs/uniphier.h |  2 +-
>  12 files changed, 25 insertions(+), 27 deletions(-)
> 
> diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
> index c55023889cab..c6e9c497413d 100644
> --- a/include/config_distro_bootcmd.h
> +++ b/include/config_distro_bootcmd.h
> @@ -70,18 +70,23 @@
>  #ifdef CONFIG_CMD_UBIFS
>  #define BOOTENV_SHARED_UBIFS \
>   "ubifs_boot=" \
> - "env exists bootubipart || " \
> - "env set bootubipart UBI; " \
> - "env exists bootubivol || " \
> - "env set bootubivol boot; " \
>   "if ubi part ${bootubipart} && " \
> - "ubifsmount ubi${devnum}:${bootubivol}; " \
> + "ubifsmount ubi0:${bootubivol}; " \
>   "then " \
>   "devtype=ubi; " \
> + "devnum=ubi0; " \
> + "bootfstype=ubifs; " \
> + "distro_bootpart=${bootubivol}; " \
>   "run scan_dev_for_boot; " \
> + "ubifsumount; " \
>   "fi\0"
> -#define BOOTENV_DEV_UBIFSBOOTENV_DEV_BLKDEV
> -#define BOOTENV_DEV_NAME_UBIFS   BOOTENV_DEV_NAME_BLKDEV
> +#define BOOTENV_DEV_UBIFS(devtypeu, devtypel, instance, bootubipart, 
> bootubivol) \
> + "bootcmd_ubifs" #instance "=" \
> + "bootubipart=" #bootubipart "; " \
> + "bootubivol=" #bootubivol "; " \
> + "run ubifs_boot\0"
> +#define BOOTENV_DEV_NAME_UBIFS(devtypeu, devtypel, instance, bootubipart, 
> bootubivol) \
> + #devtypel #instance " "
>  #else
>  #define BOOTENV_SHARED_UBIFS
>  #define BOOTENV_DEV_UBIFS \
> @@ -411,13 +416,13 @@
>   BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE
>  #endif
>  
> -#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance) \
> - BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance)
> +#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance, ...) \
> + BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance, ## 
> __VA_ARGS__)
>  #define BOOTENV_BOOT_TARGETS \
>   "boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0"
>  
> -#define BOOTENV_DEV(devtypeu, devtypel, instance) \
> - BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance)
> +#define BOOTENV_DEV(devtypeu, devtypel, instance, ...) \
> + BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance, ## __VA_ARGS__)
>  #define BOOTENV \
>   BOOTENV_SHARED_HOST \
>   BOOTENV_SHARED_MMC \
> diff --git a/include/configs/am335x_guardian.h 
> b/include/configs/am335x_guardian.h
> index b92703205cde..340715dad5c6 

Re: [PATCH v3 8/8] board: gw_ventana: enable MV88E61XX DSA support

[Tim Harvey]

On Thu, Jun 23, 2022 at 5:42 AM Vladimir Oltean  wrote:
>
> On Tue, Jun 21, 2022 at 09:57:35AM -0700, Tim Harvey wrote:
> > > > diff --git a/board/gateworks/gw_ventana/gw_ventana.c 
> > > > b/board/gateworks/gw_ventana/gw_ventana.c
> > > > index c06630a66b66..bef3f7ef0d2b 100644
> > > > --- a/board/gateworks/gw_ventana/gw_ventana.c
> > > > +++ b/board/gateworks/gw_ventana/gw_ventana.c
> > > > @@ -68,44 +68,30 @@ int board_phy_config(struct phy_device *phydev)
> > > >   phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
> > > >   }
> > > >
> > > > + /* Fixed PHY: for GW5904/GW5909 this is Marvell 88E6176 GbE 
> > > > Switch */
> > > > + else if (phydev->phy_id == 0xa5a55a5a &&
> > > > +  ((board_type == GW5904) || (board_type == GW5909))) {
> > > > + struct mii_dev *bus = miiphy_get_dev_by_name("mdio");
> > > > +
> > > > + puts("MV88E61XX ");
> > > > + /* GPIO[0] output CLK125 for RGMII_REFCLK */
> > > > + bus->write(bus, 0x1c, 0, 0x1a, (1 << 15) | (0x62 << 8) | 
> > > > 0xfe);
> > > > + bus->write(bus, 0x1c, 0, 0x1a, (1 << 15) | (0x68 << 8) | 
> > > > 7);
> > > > +
> > > > + /* Port 0-3 LED configuration: Table 80/82 */
> > > > + /* LED configuration: 7:4-green (8=Activity)  3:0 amber 
> > > > (8=Link) */
> > > > + bus->write(bus, 0x10, 0, 0x16, 0x8088);
> > > > + bus->write(bus, 0x11, 0, 0x16, 0x8088);
> > > > + bus->write(bus, 0x12, 0, 0x16, 0x8088);
> > > > + bus->write(bus, 0x13, 0, 0x16, 0x8088);
> > > > + }
> > > > +
> > >
> > > There's nothing too board specific about this configuration, why do you
> > > feel it does not belong to the DSA driver?
> > >
> > > Some macros hiding away magic register addresses and values would be
> > > good either way.
> > >
> >
> > I don't much care for MAC/PHY drivers configuring GPIO's and LED's due
> > to the lack of consistent dt bindings for such a thing and I wasn't
> > planning on trying to enhance the capabilities of the mv88e6xxx
> > driver.
> >
> > There are 7 functions each of the 15 GPIO's can be set to:
> > 0 - GPIO
> > 1 - PTP_TRIG - Precise Timing Protocol Trigger Generate Output
> > 2 - PTP_EVREQ - Precise Timing Protocol Event Request Input
> > 3 - PTP_EXTCLK - Precise Timing Protocol ExternalClock Input
> > 4 - SE_RCLK0 - SyncE Receive Clock 0 Output
> > 5 - SE_RCLK1 - SyncE Receive Clock 1 Output
> > 6 - Reserved
> > 7 - CLK125 - Free running 125 MHz Clock Output
> >
> > There are two LED's per port each of which can be set to 16 different
> > functions also and these functions take a lot of words to describe
> > thus probably wouldn't lend well to #define names.
> >
> > Are there dt bindings that you would suggest I look at for per-port
> > LED config on a switch, or GPIO config on a switch? If I add
> > dt-bindings I'll have to update the kernel driver as well which again,
> > was not my goal here. Maybe moving these into the mv88e6xxx driver per
> > dt bindings could be a 'todo'.
> >
> > This patch isn't making what is already in the board file more
> > obscure, it is just updating it to work with the new dsa driver. The
> > following was what this patch replaced:
> > -#ifdef CONFIG_MV88E61XX_SWITCH
> > -int mv88e61xx_hw_reset(struct phy_device *phydev)
> > -{
> > -   struct mii_dev *bus = phydev->bus;
> > -
> > -   /* GPIO[0] output, CLK125 */
> > -   debug("enabling RGMII_REFCLK\n");
> > -   bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
> > -  0x1a /*MV_SCRATCH_MISC*/,
> > -  (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
> > -   bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
> > -  0x1a /*MV_SCRATCH_MISC*/,
> > -  (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
> > -
> > -   /* RGMII delay - Physical Control register bit[15:14] */
> > -   debug("setting port%d RGMII rx/tx delay\n", 
> > CONFIG_MV88E61XX_CPU_PORT);
> > -   /* forced 1000mbps full-duplex link */
> > -   bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
> > -   phydev->autoneg = AUTONEG_DISABLE;
> > -   phydev->speed = SPEED_1000;
> > -   phydev->duplex = DUPLEX_FULL;
> > -
> > -   /* LED configuration: 7:4-green (8=Activity)  3:0 amber (8=Link) */
> > -   bus->write(bus, 0x10, 0, 0x16, 0x8088);
> > -   bus->write(bus, 0x11, 0, 0x16, 0x8088);
> > -   bus->write(bus, 0x12, 0, 0x16, 0x8088);
> > -   bus->write(bus, 0x13, 0, 0x16, 0x8088);
> > -
> > -   return 0;
> > -}
> > -#endif // CONFIG_MV88E61XX_SWITCH
> >
> > Best Regards,
> >
> > Tim
>
> Ok, I was thinking PHY LED configuration could be hardcoded in the
> driver itself (no DT bindings) and nobody would probably even notice.

No, it is always a bad idea to hard code a specific configuration in a
driver. Most modern PHY's have 4 LEDs with 16 configurations and board
vendors vary on what 2 LED's they use and how. I have seen th

Re: [PATCH 2/2] imx: kontron-sl-mx8mm: Remove deprecated phy-mode property

[Tom Rini]

On Tue, Jun 14, 2022 at 03:03:19PM +0200, Frieder Schrempf wrote:

> From: Frieder Schrempf 
> 
> This was previously needed, but U-Boot is now capable of parsing
> the new "phy-connection-type" property that is already used in
> the main devicetree.
> 
> Signed-off-by: Frieder Schrempf 
> Reviewed-by: Fabio Estevam 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH 1/2] imx: kontron-sl-mx8mm: Sync dts files and fix ethernet

[Tom Rini]

On Tue, Jun 14, 2022 at 03:03:18PM +0200, Frieder Schrempf wrote:

> From: Frieder Schrempf 
> 
> This syncs the devicetree files with the latest Linux kernel (5.19-rc2).
> This also fixes the currently broken ethernet support:
> 
> Before:
> 
>   Net:   Could not get PHY for FEC0: addr 0
> 
> After:
> 
>   Net:   eth0: ethernet@30be
> 
> Signed-off-by: Frieder Schrempf 
> Reviewed-by: Fabio Estevam 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v2 3/3] arm: apple: Increase RTKit timeouts

[Tom Rini]

On Tue, Jun 14, 2022 at 09:09:09AM +0200, Janne Grunau wrote:

> Timeouts are not expected to happen and are handled as fatal errors.
> Increase all timeouts to 1 second as defensive measure to avoid relying
> on the timing behaviour of certain firmware versions or configurations.
> 
> Signed-off-by: Janne Grunau 
> Reviewed-by: Mark Kettenis 
> Tested-by: Mark Kettenis 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v2 2/3] MAINTAINERS: Add nvme_apple to Apple SoC section

[Tom Rini]

On Tue, Jun 14, 2022 at 09:09:08AM +0200, Janne Grunau wrote:

> Signed-off-by: Janne Grunau 
> Reviewed-by: Mark Kettenis 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v2 1/3] arm: apple: nvme: Add SART support and RTKit buffer management

[Tom Rini]

On Tue, Jun 14, 2022 at 09:09:07AM +0200, Janne Grunau wrote:

> The NVMe firmware in the macOS 13 beta blocks or crashes with u-boot's
> current minimal RTKit implementation. It does not provide buffers for
> the firmware's buffer requests. The ANS2 firmware included in macOS 11
> and 12 tolerates this. The firmware included in the first macOS 13 beta
> requires buffers for the crashlog and ioreport endpoints to function.
> 
> In the case of the NVMe the buffers are physical memory. Access to
> physical memory is guarded by what Apple calls SART.
> Import m1n1's SART driver (exclusively used for the NVMe controller).
> Implement buffer management helpers for RTKit. These are generic since
> other devices (none in u-boot so far) require different handling.
> 
> Signed-off-by: Janne Grunau 
> Reviewed-by: Mark Kettenis 
> Tested-by: Mark Kettenis 

Applied to u-boot/master, thanks!

-- 
Tom


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[RFC] Proposed location to host the firmware handoff specification.

[Jose Marinho]

Hi,

Arm worked to draft a firmware handoff [1] specification, evolving it based on 
community feedback.
This activity followed the request of some members of the Arm ecosystem [2].
The spec (still at ALP – feedback/comments welcome!) standardizes how 
information is propagated between different firmware components during boot.

The spec hopes to remove the reliance on bespoke/platform-specific information 
handoff mechanisms, thus reducing the code maintenance burden.

The concept of entry types is present in the spec – these are data structure 
layouts that carry a specific type of data.
New types are meant to be added, following the needs and use-cases of the 
different communities.
Thus, these communities should be empowered to request new types!

To enable community contributions, the specification must be hosted in a 
location that is friendly to change requests.

We propose to host the spec in trustedfirmware.org (tf.org).

Tf.org hosts several open-source projects and already has an open governance 
model.
TF-A, and the associated community, rely on tf.org, and thus are already well 
equipped to maintain this specification and keep it up to date.
Tf.org is agnostic of any downstream projects that would adopt this 
specification (e.g. U-boot, EDK2, etc.).

We welcome the views of the communities and want to understand if there are any 
strong objections to what’s being proposed!
If anyone has objections, we are happy to consider alternatives and associated 
trade-offs.

Regards

[1] https://developer.arm.com/documentation/den0135/latest
[2] Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information 
passing between boot stages - TF-A - 
lists.trustedfirmware.org

Re: [PATCH v2] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot

[Pali Rohár]

On Thursday 16 June 2022 17:01:50 Peng Fan (OSS) wrote:
> 在 2022/4/25 22:50, Pali Rohár 写道:
> > All *boot env commands overrides default boot source location via i2c.
> > After board reset without power off, BootROM then starts booting U-Boot
> > from this specified location instead of the default one.
> > 
> > Add new env command defboot which reverts boot location to the default
> > value, which in most cases is configurable by HW DIP switches.
> > 
> > And add new env commands norlowerboot, norupperboot, sd2boot to boot from
> > other locations. norlowerboot would instruct BootROM to boot from lower NOR
> > bank, norupperboot from upper NOR bank and sd2boot from SD card with
> > alternative configuration.
> > 
> > Signed-off-by: Pali Rohár 
> 
> Not able to apply this patch.

And what is the reason? It applies cleanly on top of next branch, which
is today at commit 9121478ee6f2aee381f8fe49d8997d43527d351a.

See my steps and output:

$ git clone https://source.denx.de/u-boot/u-boot.git -b next
Cloning into 'u-boot'...
remote: Enumerating objects: 861911, done.
remote: Counting objects: 100% (15749/15749), done.
remote: Compressing objects: 100% (3457/3457), done.
remote: Total 861911 (delta 12303), reused 15650 (delta 12234), pack-reused 
846162
Receiving objects: 100% (861911/861911), 171.30 MiB | 38.97 MiB/s, done.
Resolving deltas: 100% (72/72), done.

$ cd u-boot

$ wget 
https://patchwork.ozlabs.org/project/uboot/patch/20220425145043.9945-1-p...@kernel.org/mbox/
 -O patch
--2022-06-23 15:39:52--  
https://patchwork.ozlabs.org/project/uboot/patch/20220425145043.9945-1-p...@kernel.org/mbox/
Resolving patchwork.ozlabs.org (patchwork.ozlabs.org)... 2401:3900:2:1::2, 
203.11.71.1
Connecting to patchwork.ozlabs.org 
(patchwork.ozlabs.org)|2401:3900:2:1::2|:443... connected.
HTTP request sent, awaiting response... 200 OK
Length: 8916 (8.7K) [text/plain]
Saving to: 'patch'

patch   100%[===>]   8.71K  --.-KB/sin 0s

2022-06-23 15:39:53 (57.2 MB/s) - 'patch' saved [8916/8916]

$ git am patch
Applying: board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, 
norupperboot, sd2boot and defboot

$ git log --oneline | head -4
b94d5df9eb49 board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, 
norupperboot, sd2boot and defboot
9121478ee6f2 Merge branch '2022-06-22-platform-updates-and-additions' into 
next
929e581a620f corstone1000: Convert to text file environment
781a144a7a7e gxp: Convert to text file environment

> Please new version.
> 
> Thanks,
> Peng.
> > ---
> > Changes in v2:
> > * Fix commit message
> > * Adapt code to use p1_p2_bootsrc.h
> > ---
> >   include/configs/p1_p2_bootsrc.h | 20 
> >   include/configs/p1_p2_rdb_pc.h  | 13 +
> >   2 files changed, 33 insertions(+)
> > 
> > diff --git a/include/configs/p1_p2_bootsrc.h 
> > b/include/configs/p1_p2_bootsrc.h
> > index a274c57786f5..60741ef544c0 100644
> > --- a/include/configs/p1_p2_bootsrc.h
> > +++ b/include/configs/p1_p2_bootsrc.h
> > @@ -30,6 +30,18 @@
> >   #define RST_NOR_CMD(var, ...) ""
> >   #endif
> > +#ifdef __SW_BOOT_NOR_BANK_LO
> > +#define RST_NOR_LO_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ 
> > __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_LO, __SW_BOOT_MASK))
> > +#else
> > +#define RST_NOR_LO_CMD(var, ...) ""
> > +#endif
> > +
> > +#ifdef __SW_BOOT_NOR_BANK_UP
> > +#define RST_NOR_UP_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ 
> > __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_UP, __SW_BOOT_MASK))
> > +#else
> > +#define RST_NOR_UP_CMD(var, ...) ""
> > +#endif
> > +
> >   #ifdef __SW_BOOT_SPI
> >   #define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ 
> > __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK))
> >   #else
> > @@ -42,6 +54,12 @@
> >   #define RST_SD_CMD(var, ...) ""
> >   #endif
> > +#ifdef __SW_BOOT_SD2
> > +#define RST_SD2_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ 
> > __BOOTSRC_CMD(__SW_BOOT_SD2, __SW_BOOT_MASK))
> > +#else
> > +#define RST_SD2_CMD(var, ...) ""
> > +#endif
> > +
> >   #ifdef __SW_BOOT_NAND
> >   #define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ 
> > __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK))
> >   #else
> > @@ -53,3 +71,5 @@
> >   #else
> >   #define RST_PCIE_CMD(var, ...) ""
> >   #endif
> > +
> > +#define RST_DEF_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ 
> > __BOOTSRC_CMD(0x00, 0xff))
> > diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
> > index 47bd20eeeafb..50ce2d9aaed4 100644
> > --- a/include/configs/p1_p2_rdb_pc.h
> > +++ b/include/configs/p1_p2_rdb_pc.h
> > @@ -25,6 +25,9 @@
> >   #define __SW_NOR_BANK_MASK0xfd
> >   #define __SW_NOR_BANK_UP  0x00
> >   #define __SW_NOR_BANK_LO  0x02
> > +#define __SW_BOOT_NOR_BANK_UP  0x5c /* (__SW_BOOT_NOR | 
> > __SW_NOR_BANK_UP) */
> > +#define __SW_BOOT_NOR_BANK_LO  0x5e /* (__SW_BOOT_NOR | 
> > __SW_NOR_BANK_LO) 

Re: [PATCH] riscv: fix compitible with binutils 2.38

[Heiko Stübner]

Hi,

Am Montag, 23. Mai 2022, 14:05:27 CEST schrieb Coelacanthus:
> commit 6df2a016c0c8a3d0933ef33dd192ea6606b115e3 from linux kernel
> 
> Since binutils 2.38, default ISA spec version switch to 20191213,
> in this version, original I extension be split into I, Zicsr and Zifencei.
> Zicsr is csr read/write (csrr*/csrw*) instructions, and Zifencei
> is fence.i instruction.
> This will cause compile error like this:
> Error: unrecognized opcode `csrr a5,0xc01'
> Error: unrecognized opcode `fence.i'
> 
> This commit add code to detect new Zicsr and Zifencei extensions,
> and enable it when needed.
> 
> Signed-off-by: Coelacanthus 
> Cc: Rick Chen 
> Cc: Leo 

while this fixes the build issue I'm seeing after a recent binutils,
there has been already a patch proposed for this fix [0]
and in that thread some pending issue was discussed as well.

So please coordinate with the other people over there :-)


Thanks
Heiko

[0] 
https://lore.kernel.org/all/20220128134713.2322800-1-alexandre.gh...@canonical.com/

> ---
>  arch/riscv/Makefile | 9 -
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index 0b80eb8d86..62712f8d38 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -24,7 +24,14 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
>   CMODEL = medany
>  endif
>  
> -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
> +RISCV_MARCH_y = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
> +
> +# Newer binutils versions default to ISA spec version 20191213 which moves 
> some
> +# instructions from the I extension to the Zicsr and Zifencei extensions.
> +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) 
> -march=$(RISCV_MARCH_y)_zicsr_zifencei)
> +RISCV_MARCH_$(toolchain-need-zicsr-zifencei) := 
> $(RISCV_MARCH_y)_zicsr_zifencei
> +
> +ARCH_FLAGS = -march=$(RISCV_MARCH_y) -mabi=$(ABI) \
>-mcmodel=$(CMODEL)
>  
>  PLATFORM_CPPFLAGS+= $(ARCH_FLAGS)
> 

Re: [PATCH] riscv: Fix build against binutils 2.38

[Heiko Stübner]

Am Freitag, 28. Januar 2022, 14:47:13 CEST schrieb Alexandre Ghiti:
> The following description is copied from the equivalent patch for the
> Linux Kernel proposed by Aurelien Jarno:
> 
> From version 2.38, binutils default to ISA spec version 20191213. This
> means that the csr read/write (csrr*/csrw*) instructions and fence.i
> instruction has separated from the `I` extension, become two standalone
> extensions: Zicsr and Zifencei. As the kernel uses those instruction,
> this causes the following build failure:
> 
> arch/riscv/cpu/mtrap.S: Assembler messages:
> arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
> arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
> arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
> arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
> 
> Signed-off-by: Alexandre Ghiti 

After upgrading my binutils to the recent snapshot package
in Debian-unstable (2.38.50.20220622-1), I've also run into that issue:

/home/devel/hstuebner/04_riscv/sun20i_d1_u-boot/drivers/timer/riscv_timer.c: 
Assembler messages:
/home/devel/hstuebner/04_riscv/sun20i_d1_u-boot/drivers/timer/riscv_timer.c:24: 
Error: unrecognized opcode `csrr a0,0xc01', extension `zicsr' required
make[3]: *** 
[/home/devel/hstuebner/04_riscv/sun20i_d1_u-boot/scripts/Makefile.build:254: 
drivers/timer/riscv_timer.o] Fehler 1


Is there progress in getting this patch applied to u-boot in some way?
Also it looks like there was another patch with similar content submitted
recently [0].


In any case:

On a D1-Nezha it fixes the build (and boot)
Tested-by: Heiko Stuebner 


Thanks
Heiko


[0] 
https://lore.kernel.org/all/ph7pr14mb5594fd11d1be74284f554bebce...@ph7pr14mb5594.namprd14.prod.outlook.com/

> ---
>  arch/riscv/Makefile | 11 ++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index 0b80eb8d86..53d1194ffb 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
>   CMODEL = medany
>  endif
>  
> -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
> +RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
> +
> +# Newer binutils versions default to ISA spec version 20191213 which moves 
> some
> +# instructions from the I extension to the Zicsr and Zifencei extensions.
> +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) 
> -march=$(RISCV_MARCH)_zicsr_zifencei)
> +ifeq ($(toolchain-need-zicsr-zifencei),y)
> + RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
> +endif
> +
> +ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
>-mcmodel=$(CMODEL)
>  
>  PLATFORM_CPPFLAGS+= $(ARCH_FLAGS)
> 

Re: [PATCH v2] mmc: fsl_esdhc_spl: Add support for loading proper U-Boot from unaligned location

[Pali Rohár]

On Monday 20 June 2022 12:54:26 Pali Rohár wrote:
> This allows to concatenate SPL and proper U-Boot without extra alignment.
> 
> Signed-off-by: Pali Rohár 
> ---
> Changes in v2:
> * Rebased on top of the U-Boot next branch, commit 
> 98c4828740f4944462b7d9608b95d5b73850c7b0

PING?

> ---
>  drivers/mmc/fsl_esdhc_spl.c | 27 +++
>  1 file changed, 23 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
> index 760f13d24018..54bf8152ca7a 100644
> --- a/drivers/mmc/fsl_esdhc_spl.c
> +++ b/drivers/mmc/fsl_esdhc_spl.c
> @@ -58,10 +58,10 @@ void __noreturn mmc_boot(void)
>  {
>   __attribute__((noreturn)) void (*uboot)(void);
>   uint blk_start, blk_cnt, err;
> + u32 blk_off;
>  #ifndef CONFIG_FSL_CORENET
>   uchar *tmp_buf;
>   u32 blklen;
> - u32 blk_off;
>   uchar val;
>  #ifndef CONFIG_SPL_FSL_PBL
>   u32 val32;
> @@ -155,10 +155,21 @@ again:
>   * Load U-Boot image from mmc into RAM
>   */
>   code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
> - blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
> - blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
> + blk_start = offset / mmc->read_bl_len;
> + blk_off = offset % mmc->read_bl_len;
> + blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len + 1;
> + if (blk_off) {
> + err = mmc->block_dev.block_read(&mmc->block_dev,
> + blk_start, 1, tmp_buf);
> + if (err != 1) {
> + puts("spl: mmc read failed!!\n");
> + hang();
> + }
> + blk_start++;
> + }
>   err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
> - (uchar *)CONFIG_SYS_MMC_U_BOOT_DST);
> + (uchar *)CONFIG_SYS_MMC_U_BOOT_DST +
> + (blk_off ? (mmc->read_bl_len - blk_off) 
> : 0));
>   if (err != blk_cnt) {
>   puts("spl: mmc read failed!!\n");
>  #ifndef CONFIG_FSL_CORENET
> @@ -166,6 +177,14 @@ again:
>  #endif
>   hang();
>   }
> + /*
> +  * SDHC DMA may erase bytes at dst + bl_len - blk_off - 8
> +  * due to unaligned access. So copy leading bytes from tmp_buf
> +  * after SDHC DMA transfer.
> +  */
> + if (blk_off)
> + memcpy((uchar *)CONFIG_SYS_MMC_U_BOOT_DST,
> +tmp_buf + blk_off, mmc->read_bl_len - blk_off);
>  
>   /*
>   * Clean d-cache and invalidate i-cache, to
> -- 
> 2.20.1
> 

[PATCH v2] board: freescale: p1_p2_rdb_pc: Allow to compile without __SW_BOOT_SD macro

[Pali Rohár]

Add #ifdef guard for __SW_BOOT_SD macro like there are guards for all other
__SW_BOOT_* macros.

Signed-off-by: Pali Rohár 
---
Changes in v2:
* Rebase on top of next branch, commit 9121478ee6f2aee381f8fe49d8997d43527d351a
---
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c 
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 947bbc9a5ab7..ffa9aebad1c0 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -224,8 +224,11 @@ int checkboard(void)
val = (in & io_config) | (out & (~io_config));
 
puts("rom_loc: ");
-   if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
+   if (0) {
+#ifdef __SW_BOOT_SD
+   } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
puts("sd");
+#endif
 #ifdef __SW_BOOT_SD2
} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) {
puts("sd");
-- 
2.20.1

[PATCH v2] board: freescale: p1_p2_rdb_pc: Allow to compile without BOARD_NAME

[Pali Rohár]

Signed-off-by: Pali Rohár 
---
Changes in v2:
* Rebase on top of next branch, commit 9121478ee6f2aee381f8fe49d8997d43527d351a
---
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c 
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 947bbc9a5ab7..949fe170ffd2 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -186,7 +186,11 @@ int checkboard(void)
int bus_num = CONFIG_SYS_SPD_BUS_NUM;
 
/* FIXME: This should just use the model from the device tree or 
similar */
-   printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", BOARD_NAME,
+#ifdef BOARD_NAME
+   printf("Board: %s ", BOARD_NAME);
+#endif
+
+   printf("CPLD: V%d.%d PCBA: V%d.0\n",
in_8(&cpld_data->cpld_rev_major) & 0x0F,
in_8(&cpld_data->cpld_rev_minor) & 0x0F,
in_8(&cpld_data->pcba_rev) & 0x0F);
-- 
2.20.1

Re: [PATCH v3] board: freescale: p1_p2_rdb_pc: Fix parsing inverted bits from boot input data

[Pali Rohár]

On Thursday 16 June 2022 14:37:07 Pali Rohár wrote:
> On some boards upper 4 bits of i2c boot input data (register 0) are
> inverted. Information which bits are inverted is stored in register 2.
> 
> So invert read input data back according to register 2 prior processing
> them. This fixes printing "rom_loc: value" line during booting.
> 
> Signed-off-by: Pali Rohár 
> ---
> Changes in v3:
> * Rebased on top of the U-Boot next branch, commit 
> a87a6fcd20c0e29fe55bfbb6917c4aa1f1bbce74

PING?

> Changes in v2:
> * Use register 2 for detecting which bits needs to be inverted
> ---
>  board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c 
> b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> index 6665aa4ba94e..d36306f35427 100644
> --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> @@ -174,7 +174,7 @@ int checkboard(void)
>  {
>   struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
>   ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> - u8 in, out, io_config, val;
> + u8 in, out, invert, io_config, val;
>   int bus_num = CONFIG_SYS_SPD_BUS_NUM;
>  
>   /* FIXME: This should just use the model from the device tree or 
> similar */
> @@ -198,6 +198,7 @@ int checkboard(void)
>  
>   if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
>   dm_i2c_read(dev, 1, &out, 1) < 0 ||
> + dm_i2c_read(dev, 2, &invert, 1) < 0 ||
>   dm_i2c_read(dev, 3, &io_config, 1) < 0) {
>   printf("Error reading i2c boot information!\n");
>   return 0; /* Don't want to hang() on this error */
> @@ -207,13 +208,14 @@ int checkboard(void)
>  
>   if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
>   i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
> + i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
>   i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
>   printf("Error reading i2c boot information!\n");
>   return 0; /* Don't want to hang() on this error */
>   }
>   #endif
>  
> - val = (in & io_config) | (out & (~io_config));
> + val = ((in ^ invert) & io_config) | (out & (~io_config));
>  
>   puts("rom_loc: ");
>   if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
> -- 
> 2.20.1
> 

Re: [PATCH v3 7/8] net: add MV88E61xx DSA driver

[Vladimir Oltean]

On Tue, Jun 21, 2022 at 08:11:06AM -0700, Tim Harvey wrote:
> On Tue, Jun 21, 2022 at 12:21 AM Vladimir Oltean
>  wrote:
> >
> > On Mon, Jun 20, 2022 at 04:37:45PM -0700, Tim Harvey wrote:
> > > On Mon, Jun 20, 2022 at 4:58 AM Vladimir Oltean
> > >  wrote:
> > > >
> > > > On Mon, May 23, 2022 at 11:25:48AM -0700, Tim Harvey wrote:
> > > > > +/* bind and probe the switch mdios */
> > > > > +static int mv88e61xx_dsa_probe_mdio(struct udevice *dev)
> > > > > +{
> > > > > + struct udevice *pdev;
> > > > > + ofnode node, mdios;
> > > > > + const char *name;
> > > > > + int ret;
> > > > > +
> > > > > + /* bind phy ports of mdios child node to mv88e61xx_mdio device 
> > > > > */
> > > > > + mdios = dev_read_subnode(dev, "mdios");
> > > > > + if (ofnode_valid(mdios)) {
> > > > > + ofnode_for_each_subnode(node, mdios) {
> > > > > + name = ofnode_get_name(node);
> > > > > + ret = device_bind_driver_to_node(dev,
> > > > > +  
> > > > > "mv88e61xx_mdio",
> > > > > +  name, node, 
> > > > > &pdev);
> > > > > + if (ret) {
> > > > > + dev_err(dev, "failed to bind %s: %d\n", 
> > > > > name, ret);
> > > > > + continue;
> > > > > + }
> > > > > +
> > > > > + /* need to probe it as there is no compatible 
> > > > > to do so */
> > > > > + ret = uclass_get_device_by_ofnode(UCLASS_MDIO, 
> > > > > node, &pdev);
> > > > > + if (ret) {
> > > > > + dev_err(dev, "failed to probe %s: 
> > > > > %d\n", name, ret);
> > > > > + continue;
> > > > > + }
> > > >
> > > > What do you do with this pdev once you get it? Are you missing a 
> > > > device_probe() call?
> > > > Also, why "pdev" and not "dev"? What does the "p" stand for?
> > >
> > > struct udevice *dev is passed into the function so I use pdev to
> > > iterate over the ports in the mdios node so 'pdev' means 'port' here.
> >
> > Yes, but those under the mdios node aren't ports, they're MDIO
> > controllers, hence my comment.
> 
> how about devp (dev pointer) or subdev or mdio?

The terminology problem I have with "mdio" is that it would be a
struct udevice *, whereas the plural variable, "mdios", is an ofnode.
How about mdev, for mdio device?

Re: [PATCH v3 8/8] board: gw_ventana: enable MV88E61XX DSA support

[Vladimir Oltean]

On Tue, Jun 21, 2022 at 09:57:35AM -0700, Tim Harvey wrote:
> > > diff --git a/board/gateworks/gw_ventana/gw_ventana.c 
> > > b/board/gateworks/gw_ventana/gw_ventana.c
> > > index c06630a66b66..bef3f7ef0d2b 100644
> > > --- a/board/gateworks/gw_ventana/gw_ventana.c
> > > +++ b/board/gateworks/gw_ventana/gw_ventana.c
> > > @@ -68,44 +68,30 @@ int board_phy_config(struct phy_device *phydev)
> > >   phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
> > >   }
> > >
> > > + /* Fixed PHY: for GW5904/GW5909 this is Marvell 88E6176 GbE Switch 
> > > */
> > > + else if (phydev->phy_id == 0xa5a55a5a &&
> > > +  ((board_type == GW5904) || (board_type == GW5909))) {
> > > + struct mii_dev *bus = miiphy_get_dev_by_name("mdio");
> > > +
> > > + puts("MV88E61XX ");
> > > + /* GPIO[0] output CLK125 for RGMII_REFCLK */
> > > + bus->write(bus, 0x1c, 0, 0x1a, (1 << 15) | (0x62 << 8) | 
> > > 0xfe);
> > > + bus->write(bus, 0x1c, 0, 0x1a, (1 << 15) | (0x68 << 8) | 7);
> > > +
> > > + /* Port 0-3 LED configuration: Table 80/82 */
> > > + /* LED configuration: 7:4-green (8=Activity)  3:0 amber 
> > > (8=Link) */
> > > + bus->write(bus, 0x10, 0, 0x16, 0x8088);
> > > + bus->write(bus, 0x11, 0, 0x16, 0x8088);
> > > + bus->write(bus, 0x12, 0, 0x16, 0x8088);
> > > + bus->write(bus, 0x13, 0, 0x16, 0x8088);
> > > + }
> > > +
> >
> > There's nothing too board specific about this configuration, why do you
> > feel it does not belong to the DSA driver?
> >
> > Some macros hiding away magic register addresses and values would be
> > good either way.
> >
> 
> I don't much care for MAC/PHY drivers configuring GPIO's and LED's due
> to the lack of consistent dt bindings for such a thing and I wasn't
> planning on trying to enhance the capabilities of the mv88e6xxx
> driver.
> 
> There are 7 functions each of the 15 GPIO's can be set to:
> 0 - GPIO
> 1 - PTP_TRIG - Precise Timing Protocol Trigger Generate Output
> 2 - PTP_EVREQ - Precise Timing Protocol Event Request Input
> 3 - PTP_EXTCLK - Precise Timing Protocol ExternalClock Input
> 4 - SE_RCLK0 - SyncE Receive Clock 0 Output
> 5 - SE_RCLK1 - SyncE Receive Clock 1 Output
> 6 - Reserved
> 7 - CLK125 - Free running 125 MHz Clock Output
> 
> There are two LED's per port each of which can be set to 16 different
> functions also and these functions take a lot of words to describe
> thus probably wouldn't lend well to #define names.
> 
> Are there dt bindings that you would suggest I look at for per-port
> LED config on a switch, or GPIO config on a switch? If I add
> dt-bindings I'll have to update the kernel driver as well which again,
> was not my goal here. Maybe moving these into the mv88e6xxx driver per
> dt bindings could be a 'todo'.
> 
> This patch isn't making what is already in the board file more
> obscure, it is just updating it to work with the new dsa driver. The
> following was what this patch replaced:
> -#ifdef CONFIG_MV88E61XX_SWITCH
> -int mv88e61xx_hw_reset(struct phy_device *phydev)
> -{
> -   struct mii_dev *bus = phydev->bus;
> -
> -   /* GPIO[0] output, CLK125 */
> -   debug("enabling RGMII_REFCLK\n");
> -   bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
> -  0x1a /*MV_SCRATCH_MISC*/,
> -  (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
> -   bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
> -  0x1a /*MV_SCRATCH_MISC*/,
> -  (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
> -
> -   /* RGMII delay - Physical Control register bit[15:14] */
> -   debug("setting port%d RGMII rx/tx delay\n", 
> CONFIG_MV88E61XX_CPU_PORT);
> -   /* forced 1000mbps full-duplex link */
> -   bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
> -   phydev->autoneg = AUTONEG_DISABLE;
> -   phydev->speed = SPEED_1000;
> -   phydev->duplex = DUPLEX_FULL;
> -
> -   /* LED configuration: 7:4-green (8=Activity)  3:0 amber (8=Link) */
> -   bus->write(bus, 0x10, 0, 0x16, 0x8088);
> -   bus->write(bus, 0x11, 0, 0x16, 0x8088);
> -   bus->write(bus, 0x12, 0, 0x16, 0x8088);
> -   bus->write(bus, 0x13, 0, 0x16, 0x8088);
> -
> -   return 0;
> -}
> -#endif // CONFIG_MV88E61XX_SWITCH
> 
> Best Regards,
> 
> Tim

Ok, I was thinking PHY LED configuration could be hardcoded in the
driver itself (no DT bindings) and nobody would probably even notice.
For pin configuration as RGMII 125 MHz clock or GPIO or otherwise,
there would probably need to be a "pinctrl" DT subnode with a specific
pinctrl driver attached. It's best if the development for that would be
done in concert with the Linux community, perhaps even in Linux first.

In any case, from my side it's ok if you leave a pinctrl sub-driver as TODO.

[PATCH 2/2] powerpc: dts: p2020: Remove duplicate pic@40000 node

[Pali Rohár]

DT node pic@4 is defined explicitly in p2020-post.dtsi file and also
transitionally via include file pq3-mpic.dtsi. Remove duplicate definition
from p2020-post.dtsi.

No change in final DTB file.

Signed-off-by: Pali Rohár 
---
 arch/powerpc/dts/p2020-post.dtsi | 12 
 1 file changed, 12 deletions(-)

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 3351874b5389..ea215ab075fe 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -88,18 +88,6 @@
 /include/ "pq3-mpic.dtsi"
 /include/ "pq3-mpic-timer-B.dtsi"
 
-   mpic: pic@4 {
-   interrupt-controller;
-   #address-cells = <0>;
-   #interrupt-cells = <4>;
-   reg = <0x4 0x4>;
-   compatible = "fsl,mpic";
-   device_type = "open-pic";
-   big-endian;
-   single-cpu-affinity;
-   last-interrupt-source = <255>;
-   };
-
global-utilities@e {
compatible = "fsl,p2020-guts";
reg = <0xe 0x1000>;
-- 
2.20.1

[PATCH 1/2] powerpc: dts: p2020: Sort DT nodes by their addresses

[Pali Rohár]

No functional change.

Signed-off-by: Pali Rohár 
---
 arch/powerpc/dts/p2020-post.dtsi | 89 
 1 file changed, 45 insertions(+), 44 deletions(-)

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 0d0cd2273cd4..3351874b5389 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -13,49 +13,6 @@
compatible = "fsl,p2020-immr", "simple-bus";
bus-frequency = <0x0>;
 
-   usb@22000 {
-   compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
-   reg = <0x22000 0x1000>;
-   #address-cells = <1>;
-   #size-cells = <0>;
-   interrupts = <28 0x2 0 0>;
-   phy_type = "ulpi";
-   };
-
-   mpic: pic@4 {
-   interrupt-controller;
-   #address-cells = <0>;
-   #interrupt-cells = <4>;
-   reg = <0x4 0x4>;
-   compatible = "fsl,mpic";
-   device_type = "open-pic";
-   big-endian;
-   single-cpu-affinity;
-   last-interrupt-source = <255>;
-   };
-
-   esdhc: sdhc@2e000 {
-   compatible = "fsl,p2020-esdhc", "fsl,esdhc";
-   reg = <0x2e000 0x1000>;
-   interrupts = <72 0x2 0 0>;
-   /* Filled in by U-Boot */
-   clock-frequency = <0>;
-   };
-
-   espi0: spi@7000 {
-   compatible = "fsl,mpc8536-espi";
-   #address-cells = <1>;
-   #size-cells = <0>;
-   reg = <0x7000 0x1000>;
-   interrupts = < 0x3b 0x02 0x00 0x00 >;
-   fsl,espi-num-chipselects = <4>;
-   };
-
-/include/ "pq3-i2c-0.dtsi"
-/include/ "pq3-i2c-1.dtsi"
-/include/ "pq3-duart-0.dtsi"
-/include/ "pq3-gpio-0.dtsi"
-
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
@@ -74,6 +31,22 @@
interrupts = <18 2 0 0>;
};
 
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+
+   espi0: spi@7000 {
+   compatible = "fsl,mpc8536-espi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x7000 0x1000>;
+   interrupts = < 0x3b 0x02 0x00 0x00 >;
+   fsl,espi-num-chipselects = <4>;
+   };
+
+/include/ "pq3-dma-1.dtsi"
+/include/ "pq3-gpio-0.dtsi"
+
L2: l2-cache-controller@2 {
compatible = "fsl,p2020-l2-cache-controller";
reg = <0x2 0x1000>;
@@ -83,7 +56,15 @@
};
 
 /include/ "pq3-dma-0.dtsi"
-/include/ "pq3-dma-1.dtsi"
+
+   usb@22000 {
+   compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
+   reg = <0x22000 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   interrupts = <28 0x2 0 0>;
+   phy_type = "ulpi";
+   };
 
 /include/ "pq3-etsec1-0.dtsi"
 /include/ "pq3-etsec1-timer-0.dtsi"
@@ -95,10 +76,30 @@
 /include/ "pq3-etsec1-1.dtsi"
 /include/ "pq3-etsec1-2.dtsi"
 
+   esdhc: sdhc@2e000 {
+   compatible = "fsl,p2020-esdhc", "fsl,esdhc";
+   reg = <0x2e000 0x1000>;
+   interrupts = <72 0x2 0 0>;
+   /* Filled in by U-Boot */
+   clock-frequency = <0>;
+   };
+
 /include/ "pq3-sec3.1-0.dtsi"
 /include/ "pq3-mpic.dtsi"
 /include/ "pq3-mpic-timer-B.dtsi"
 
+   mpic: pic@4 {
+   interrupt-controller;
+   #address-cells = <0>;
+   #interrupt-cells = <4>;
+   reg = <0x4 0x4>;
+   compatible = "fsl,mpic";
+   device_type = "open-pic";
+   big-endian;
+   single-cpu-affinity;
+   last-interrupt-source = <255>;
+   };
+
global-utilities@e {
compatible = "fsl,p2020-guts";
reg = <0xe 0x1000>;
-- 
2.20.1

Re: [PATCH v3] powerpc: mpc85xx: Set TEXT_BASE addresses to real base values

[Tom Rini]

On Thu, Jun 23, 2022 at 01:29:10PM +0200, Pali Rohár wrote:
> On Thursday 16 June 2022 14:19:44 Pali Rohár wrote:
> > Currently CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE addresses are
> > manually increased by 0x1000 due to .bootpg section. This section has size
> > of 0x1000 bytes and is manually put by linker script before .text section
> > (and therefore before base address) when CONFIG_SYS_MPC85XX_NO_RESETVEC is
> > set. Due to this fact lot of other config options are manually increased by
> > 0x1000 value to make correct layout. Note that entry point is not on
> > CONFIG_SPL_TEXT_BASE (image+0x1000) but it is really on address
> > CONFIG_SPL_TEXT_BASE-0x1000 (means at the start of the image).
> > 
> > Cleanup handling of .bootpg section when CONFIG_SYS_MPC85XX_NO_RESETVEC is
> > set. Put .bootpg code directly into .text section and move text base
> > address to the start of .bootpg code. And finally remove +0x1000 value from
> > lot of config options. With this removal custom PHDRS is not used anymore,
> > so remove it too.
> > 
> > After this change entry point would be at CONFIG_SPL_TEXT_BASE and not at
> > address -0x1000 anymore.
> > 
> > Tested on P2020 board with SPL and proper U-Boot.
> > 
> > Signed-off-by: Pali Rohár 
> > ---
> 
> PING???
> 

Yes, I thought this was part of fsl-qoriq-2022-6-20-v2 but I see it is
not.  I really don't want to see this have problems to apply, again.
But it probably will if it's not picked up pretty much now.  Peng,
should I grab this for next?  Otherwise someone is going to need to grab
this, edit and recountdiff it for it to apply as it's really not fair to
ask Pali to rebase it yet again if it doesn't and git also doesn't
handle it on a rebase.

-- 
Tom


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Re: [PATCH v5 08/23] FWU: Add boot time checks as highlighted by the FWU specification

[Etienne Carriere]

Hi Sughosh,

On Thu, 23 Jun 2022 at 11:46, Sughosh Ganu  wrote:
>
> hi Etienne,
>
> On Tue, 21 Jun 2022 at 16:26, Etienne Carriere
>  wrote:
> >
> > Hi Sughosh,
> >
> > On Thu, 9 Jun 2022 at 14:31, Sughosh Ganu  wrote:
> > >
> > > The FWU Multi Bank Update specification requires the Update Agent to
> > > carry out certain checks at the time of platform boot. The Update
> > > Agent is the component which is responsible for updating the firmware
> > > components and maintaining and keeping the metadata in sync.
> > >
> > > The spec requires that the Update Agent perform the following checks
> > > at the time of boot
> > > * Sanity check of both the metadata copies maintained by the platform.
> > > * Get the boot index passed to U-Boot by the prior stage bootloader
> > >   and use this value for metadata bookkeeping.
> > > * Check if the system is booting in Trial State. If the system boots
> > >   in the Trial State for more than a specified number of boot counts,
> > >   change the Active Bank to be booting the platform from.
> > >
> > > Add these checks in the board initialisation sequence, invoked after
> > > relocation.
> > >
> > > Signed-off-by: Sughosh Ganu 
> > > ---
> > >  common/board_r.c  |   5 ++
> > >  include/fwu.h |   3 +
> > >  lib/fwu_updates/fwu.c | 170 ++
> > >  3 files changed, 178 insertions(+)
> > >  create mode 100644 lib/fwu_updates/fwu.c
>
> 
>
> > > --- /dev/null
> > > +++ b/lib/fwu_updates/fwu.c
> > > @@ -0,0 +1,170 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (c) 2022, Linaro Limited
> > > + */
> > > +
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +
> > > +#include 
> > > +#include 
> > > +
> > > +static u8 trial_state;
> > > +static u8 boottime_check;
> > > +
> > > +static int fwu_trial_state_check(void)
> > > +{
> > > +   int ret, i;
> > > +   efi_status_t status;
> > > +   efi_uintn_t var_size;
> > > +   u16 trial_state_ctr;
> > > +   u32 nimages, active_bank, var_attributes, active_idx;
> > > +   struct fwu_mdata *mdata = NULL;
> > > +   struct fwu_image_entry *img_entry;
> > > +   struct fwu_image_bank_info *img_bank_info;
> > > +
> > > +   ret = fwu_get_mdata(&mdata);
> > > +   if (ret)
> > > +   return ret;
> > > +
> > > +   ret = 0;
> > > +   nimages = CONFIG_FWU_NUM_IMAGES_PER_BANK;
> > > +   active_bank = mdata->active_index;
> > > +   img_entry = &mdata->img_entry[0];
> > > +   for (i = 0; i < nimages; i++) {
> > > +   img_bank_info = &img_entry[i].img_bank_info[active_bank];
> > > +   if (!img_bank_info->accepted) {
> > > +   trial_state = 1;
> > > +   break;
> > > +   }
> > > +   }
> > > +
> > > +   if (trial_state) {
> > > +   var_size = (efi_uintn_t)sizeof(trial_state_ctr);
> > > +   log_info("System booting in Trial State\n");
> > > +   var_attributes = EFI_VARIABLE_NON_VOLATILE |
> > > +   EFI_VARIABLE_BOOTSERVICE_ACCESS;
> > > +   status = efi_get_variable_int(L"TrialStateCtr",
> > > + &efi_global_variable_guid,
> > > + &var_attributes,
> > > + &var_size, &trial_state_ctr,
> > > + NULL);
> > > +   if (status != EFI_SUCCESS) {
> > > +   log_err("Unable to read TrialStateCtr 
> > > variable\n");
> > > +   ret = -1;
> > > +   goto out;
> > > +   }
> > > +
> > > +   ++trial_state_ctr;
> > > +   if (trial_state_ctr > CONFIG_FWU_TRIAL_STATE_CNT) {
> > > +   log_info("Trial State count exceeded. Revert back 
> > > to previous_active_index\n");
> > > +   active_idx = mdata->active_index;
> > > +   ret = fwu_revert_boot_index();
> > > +   if (ret) {
> > > +   log_err("Unable to revert 
> > > active_index\n");
> > > +   goto out;
> > > +   }
> > > +
> > > +   trial_state_ctr = 0;
> > > +   status = efi_set_variable_int(L"TrialStateCtr",
> > > + 
> > > &efi_global_variable_guid,
> > > + var_attributes,
> > > + 0,
> >
> > s/0/var_size/ ?
> > Ditto 24 lines below.
>
> The variable size is 0 since the variable is being deleted here and
> the other instance that you mention. Maybe I can put a comment in the
> two places.

The goal is to delete the variable or to reset it to 0

Re: [PATCH v2 9/9] MAINTAINERS: Introduce HPE GXP Architecture

[Tom Rini]

On Wed, Jun 08, 2022 at 04:21:42PM -0500, nick.hawk...@hpe.com wrote:

> From: Nick Hawkins 
> 
> Create a section in MAINTAINERS for the GXP HPE architecture
> 
> Signed-off-by: Nick Hawkins 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 8/9] configs: gxp: add gxp_defconfig

[Tom Rini]

On Wed, Jun 08, 2022 at 04:21:41PM -0500, nick.hawk...@hpe.com wrote:

> From: Nick Hawkins 
> 
> This is the initial very basic config that enables the U-Boot console on
> the hpe gxp soc.
> 
> Signed-off-by: Nick Hawkins 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 7/9] configs: gxp: add core support

[Tom Rini]

On Wed, Jun 08, 2022 at 04:21:40PM -0500, nick.hawk...@hpe.com wrote:

> From: Nick Hawkins 
> 
> Add the include file for the gxp soc.
> 
> Signed-off-by: Nick Hawkins 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 6/9] ARM: dts: Add device tree files for hpe gxp soc

[Tom Rini]

On Wed, Jun 08, 2022 at 04:21:39PM -0500, nick.hawk...@hpe.com wrote:

> From: Nick Hawkins 
> 
> The HPE SoC is new to linux. A basic device tree layout with minimum
> required for linux to boot including a timer and watchdog support has
> been created.
> 
> The dts file is empty at this point but will be updated in subsequent
> updates as board specific features are enabled.
> 
> Signed-off-by: Nick Hawkins 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 5/9] dt-bindings: spi: Add hpe gxp spi

[Tom Rini]

On Wed, Jun 08, 2022 at 04:21:38PM -0500, nick.hawk...@hpe.com wrote:

> From: Nick Hawkins 
> 
> Add support for the HPE GXP SPI Controller.
> 
> Signed-off-by: Nick Hawkins 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 4/9] board: hpe: gxp: add HPE GXP soc support

[Tom Rini]

On Wed, Jun 08, 2022 at 04:21:37PM -0500, nick.hawk...@hpe.com wrote:

> From: Nick Hawkins 
> 
> Add basic support for the HPE GXP SoC. Reset the EHCI controller at
> boot.
> 
> Signed-off-by: Nick Hawkins 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 3/9] spi: gxp_spi: Add GXP SPI controller driver

[Tom Rini]

On Wed, Jun 08, 2022 at 04:21:36PM -0500, nick.hawk...@hpe.com wrote:

> From: Nick Hawkins 
> 
> The GXP supports 3 separate SPI interfaces to accommodate the system
> flash, core flash, and other functions. The SPI engine supports variable
> clock frequency, selectable 3-byte or 4-byte addressing and a
> configurable x1, x2, and x4 command/address/data modes. The memory
> buffer for reading and writing ranges between 256 bytes and 8KB. This
> driver supports access to the core flash.
> 
> Signed-off-by: Nick Hawkins 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 2/9] timer: gxp: Add HPE GXP timer support

[Tom Rini]

On Wed, Jun 08, 2022 at 04:21:35PM -0500, nick.hawk...@hpe.com wrote:

> From: Nick Hawkins 
> 
> Add support for the HPE GXP SOC timer. The GXP supports several different
> kinds of timers but for the purpose of this driver there is only support
> for the General Timer. The timer has a 1us resolution and is 56 bits.
> 
> Signed-off-by: Nick Hawkins 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 1/9] ARM: hpe: gxp: add core support

[Tom Rini]

On Wed, Jun 08, 2022 at 04:21:34PM -0500, nick.hawk...@hpe.com wrote:

> From: Nick Hawkins 
> 
> The GXP is the HPE BMC SoC that is used in the majority
> of current generation HPE servers. Traditionally the asic will
> last multiple generations of server before being replaced.
> 
> Info about SoC:
> 
> HPE GXP is the name of the HPE Soc. This SoC is used to implement many BMC
> features at HPE. It supports ARMv7 architecture based on the Cortex A9
> core. It is capable of using an AXI bus to whicha memory controller is
> attached. It has multiple SPI interfaces to connect boot flash and BIOS
> flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple
> i2c engines to drive connectivity with a host infrastructure. There
> currently are no public specifications but this process is being worked.
> 
> Signed-off-by: Nick Hawkins 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v1] misc: nuvoton: Add NPCM7xx otp controller driver

[Tom Rini]

On Tue, Jun 07, 2022 at 04:33:54PM +0800, Jim Liu wrote:

> Add Nuvoton BMC npcm750 otp driver
> 
> Signed-off-by: Jim Liu 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v1 2/2] crypto: nuvoton: Add NPCM7xx SHA driver

[Tom Rini]

On Tue, Jun 07, 2022 at 04:32:09PM +0800, Jim Liu wrote:

> add nuvoton BMC npcm750 SHA driver
> 
> Signed-off-by: Jim Liu 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v1 1/2] crypto: nuvoton: Add NPCM7xx AES driver

[Tom Rini]

On Tue, Jun 07, 2022 at 04:32:08PM +0800, Jim Liu wrote:

> add nuvoton BMC npcm750 AES driver
> 
> Signed-off-by: Jim Liu 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v3 3/3] ARM: dts: omap3-devkit8000: Fix CONFIG_DM_ETH warning

[Tom Rini]

On Thu, Jun 02, 2022 at 10:27:08PM +0200, Anthoine Bourgeois wrote:

> Add the missing ethernet node in u-boot dts.
> 
> Signed-off-by: Anthoine Bourgeois 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v3 2/3] ARM: dts: omap3-devkit8000: Fix CONFIG_DM_I2C warning

[Tom Rini]

On Thu, Jun 02, 2022 at 10:27:07PM +0200, Anthoine Bourgeois wrote:

> Seems that u-boot can't probe i2c bus at 2.6Mhz speed, so lower
> the speed to the default value 100Khz.
> 
> v2: fix i2c1 frequency in the root omap3-u-boot.dtsi include.
> 
> Signed-off-by: Anthoine Bourgeois 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v3 1/3] ARM: dts: omap3-devkit8000: Add support for Devkit8000

[Tom Rini]

On Thu, Jun 02, 2022 at 10:27:06PM +0200, Anthoine Bourgeois wrote:

> This commit adds OMAP3 BeagleBoard devicetree files from Linux
> v5.16.0.
> This commit fixes CONFIG_DM_MMC warning.
> 
> v3: patch clean-up
> 
> Signed-off-by: Anthoine Bourgeois 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH] ast2600: spl: Add boot mode detection

[Tom Rini]

On Wed, Jun 01, 2022 at 04:43:52PM +0800, Chia-Wei Wang wrote:

> AST2600 supports boot from SPI(mmap), eMMC, and UART.
> This patch adds the boot mode detection and return the
> corresponding boot device type.
> 
> Signed-off-by: Chia-Wei Wang 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH] configs: ast2600: Move SPL bss section to DRAM space

[Tom Rini]

On Wed, Jun 01, 2022 at 04:21:15PM +0800, Chia-Wei Wang wrote:

> The commit b583348ca8c8 ("image: fit: Align hash output buffers") places
> the hash output buffer at the .bss section. However, AST2600 by default
> executes SPL in the NOR flash XIP way. This results in the hash output
> cannot be written to the buffer as it is located at the R/X only region.
> 
> We need to move the .bss section out of the SPL body to the DRAM space,
> where hash output can be written to. This patch includes:
>  - Define the .bss section base and size
>  - A new SPL linker script is added with a separate .bss region specified
>  - Enable CONFIG_SPL_SEPARATE_BSS kconfig option
> 
> Signed-off-by: Chia-Wei Wang 
> Reviewed-by: Neal Liu 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 2/2] arm: add support to corstone1000 platform

[Tom Rini]

On Wed, May 11, 2022 at 10:55:41AM +0100, Rui Miguel Silva wrote:

> Corstone1000 is a platform from arm, which includes pre
> verified Corstone SSE710 sub-system that combines Cortex-A and
> Cortex-M processors [0].
> 
> This code adds the support for the Cortex-A35 implementation
> at host side, it contains also the necessary bits to support
> the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the
> FPGA MPS3 board implementation of this platform. [2]
> 
> 0: https://developer.arm.com/documentation/102360/
> 1: 
> https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
> 2: https://developer.arm.com/documentation/dai0550/c/
> 
> Signed-off-by: Rui Miguel Silva 
> Reviewed-by: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 1/2] cmd: load: add load command for memory mapped

[Tom Rini]

On Wed, May 11, 2022 at 10:55:40AM +0100, Rui Miguel Silva wrote:

> cp.b is used a lot as a way to load binaries to memory and execute
> them, however we may need to integrate this with the efi subsystem to
> set it up as a bootdev.
> 
> So, introduce a loadm command that will be consistent with the other
> loadX commands and will call the efi API's.
> 
> ex: loadm $kernel_addr $kernel_addr_r $kernel_size
> 
> with this a kernel with CONFIG_EFI_STUB enabled will be loaded and
> then subsequently booted with bootefi command.
> 
> Signed-off-by: Rui Miguel Silva 
> Reviewed-by: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 2/2] corstone1000: Convert to text file environment

[Tom Rini]

On Wed, Jun 22, 2022 at 03:21:45PM -0400, Tom Rini wrote:

> Convert this platform to using the text file environment rather than
> defining CONFIG_EXTRA_ENV_SETTINGS.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 1/2] gxp: Convert to text file environment

[Tom Rini]

On Wed, Jun 22, 2022 at 03:21:44PM -0400, Tom Rini wrote:

> Convert this platform to using the text file environment rather than
> defining CONFIG_EXTRA_ENV_SETTINGS.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH] cmd/misc: Stop using a function pointer

[Tom Rini]

On Wed, Jun 22, 2022 at 04:10:18PM -0400, Tom Rini wrote:

> Currently, enabling CMD_MISC gives:
> cmd/misc.c:67:25: warning: assignment to 'int (*)(struct udevice *, int,  
> void *, int)' from incompatible pointer type 'int (*)(struct udevice *, int,  
> const void *, int)' [-Wincompatible-pointer-types]
> 
> Because 'misc_read' takes a void * and 'misc_write' takes a const void
> *, both of which make sense for their operation.  Given there's one
> place we make use of the function pointer, just call read or write
> directly for the operation we're called with.
> 
> Reviewed-by: Bin Meng 
> Reviewed-by: Sean Anderson 
> Signed-off-by: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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[PATCH] serial: ns16550: Wait in debug_uart_init until tx buffer is empty

[Pali Rohár]

Commit d293759d55cc ("serial: ns16550: Add support for
SPL_DEBUG_UART_BASE") fixed support for setting correct early debug UART
base address in SPL.

But after this commit, output from Marvell A385 BootROM is truncated or
lost and not fully present on serial console.

Debugging this issue showed that BootROM just put bytes into UART HW output
buffer and does not wait until UART HW transmit all characters. U-Boot
ns16550 early debug is initialized very early and during its initialization
is resetting UART HW and flushing remaining transmit buffer (which still
contains BootROM output).

Fix this issue by waiting in init function prior resetting UART HW until
TxEmpty bit in UART Line Status Register is set. TxEmpty is set when all
remaining bytes from HW buffer are transmitted.

Signed-off-by: Pali Rohár 
---
 drivers/serial/ns16550.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 78bfe6281ce3..13418004e2b0 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -328,6 +328,8 @@ static inline void _debug_uart_init(void)
struct ns16550 *com_port = (struct ns16550 
*)CONFIG_VAL(DEBUG_UART_BASE);
int baud_divisor;
 
+   while (!(serial_din(&com_port->lsr) & UART_LSR_TEMT));
+
/*
 * We copy the code from above because it is already horribly messy.
 * Trying to refactor to nicely remove the duplication doesn't seem
-- 
2.20.1

Re: [PATCH v5 02/23] FWU: Add FWU metadata structure and driver for accessing metadata

[Etienne Carriere]

Hi Sughosh,

On Thu, 23 Jun 2022 at 08:24, Sughosh Ganu  wrote:
>
> hi Etienne,
>
> On Tue, 21 Jun 2022 at 16:24, Etienne Carriere
>  wrote:
> >
> > Hello Sughosh,
> >
> >
> >
> > On Thu, 9 Jun 2022 at 14:30, Sughosh Ganu  wrote:
> > >
> > > In the FWU Multi Bank Update feature, the information about the
> > > updatable images is stored as part of the metadata, which is stored on
> > > a dedicated partition. Add the metadata structure, and a driver model
> > > uclass which provides functions to access the metadata. These are
> > > generic API's, and implementations can be added based on parameters
> > > like how the metadata partition is accessed and what type of storage
> > > device houses the metadata.
> > >
> > > Signed-off-by: Sughosh Ganu 
> > > ---
> > >  drivers/Kconfig  |   2 +
> > >  drivers/Makefile |   1 +
> > >  drivers/fwu-mdata/Kconfig|   7 +
> > >  drivers/fwu-mdata/Makefile   |   6 +
> > >  drivers/fwu-mdata/fwu-mdata-uclass.c | 459 +++
> > >  include/dm/uclass-id.h   |   1 +
> > >  include/fwu.h|  49 +++
> > >  include/fwu_mdata.h  |  67 
> > >  8 files changed, 592 insertions(+)
> > >  create mode 100644 drivers/fwu-mdata/Kconfig
> > >  create mode 100644 drivers/fwu-mdata/Makefile
> > >  create mode 100644 drivers/fwu-mdata/fwu-mdata-uclass.c
> > >  create mode 100644 include/fwu.h
> > >  create mode 100644 include/fwu_mdata.h
> > >
>
> 
>
> > > diff --git a/drivers/fwu-mdata/fwu-mdata-uclass.c 
> > > b/drivers/fwu-mdata/fwu-mdata-uclass.c
> > > new file mode 100644
> > > index 00..1530ceb01d
> > > --- /dev/null
> > > +++ b/drivers/fwu-mdata/fwu-mdata-uclass.c



> > > +/**
> > > + * fwu_get_mdata() - Get a FWU metadata copy
> > > + * @mdata: Copy of the FWU metadata
> > > + *
> > > + * Get a valid copy of the FWU metadata.
> > > + *
> > > + * Return: 0 if OK, -ve on error
> > > + *
> > > + */
> > > +int fwu_get_mdata(struct fwu_mdata **mdata)
> >
> > Is there a real need for this function to allocate an instance of struct 
> > mdata.
> > I think it would be clearer if it was the caller's responsibility to
> > allocate/free the structure.
> >
> > Or maybe rename this function fwu_alloc_and_copy_mdata() to highlight
> > that the function gives an allocated copy of the data.
>
> I guess I can put a comment in the function description saying that
> the function is responsible for the allocation of the metadata
> structure.

I think it would be better.

>
> > One should be careful when calling these API functions as some act on
> > a local copy (retrieved from fw_get_mdata()) while other functions
> > modify straight fwu-mdata in the storage media.
>
> Did you find any function which is modifying the metadata on the
> storage device directly. The API fwu_update_mdata() is supposed to be
> doing that. If you have come across any function which is directly
> modifying the metadata on the storage media, please let me know and I
> will fix it.

Many functions do so: fwu_clear_accept_image(),
fwu_clear_accept_image(), fwu_resert_boot_index(), etc... Actually all
generic functions do so while only fwu_get_mdata() and
fwu_update_mdata() act on a RAM copy.

Maybe fwu-mdata ops should have a status field for when a RAM copy was
exported and used to prevent direct updates to mdata in storage until
caller releases (fw_put_mdata()?) the exposed copy. Would this scheme
be overkilling...

Or maybe fwu_clear_accept_image() and other helper functions could
also require a mdata RAM reference to act on, letting the caller also
go through fwu_get_mdata()/fwu_update_mdata().

etienne

RE: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg

[Chee, Tien Fong]

> -Original Message-
> From: Paweł Anikiel 
> Sent: Tuesday, 21 June, 2022 12:00 AM
> To: Chee, Tien Fong 
> Cc: Vasut, Marek ; simon.k.r.goldschm...@gmail.com;
> michal.si...@xilinx.com; u-boot@lists.denx.de; s...@chromium.org;
> feste...@denx.de; ja...@amarulasolutions.com;
> andre.przyw...@arm.com; Armstrong, Neil ;
> pbrobin...@gmail.com; thar...@gateworks.com; paul@linaro.org;
> christianshew...@gmail.com; adrian.fiergol...@fastree3d.com;
> marek.be...@nic.cz; Denk, Wolfgang ; Lim, Elly Siew Chin
> ; upstr...@semihalf.com;
> ams...@chromium.org
> Subject: Re: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy
> waiting in cm_full_cfg
> 
> On Mon, Jun 20, 2022 at 2:29 PM Chee, Tien Fong 
> wrote:
> >
> >
> >
> > > -Original Message-
> > > From: Paweł Anikiel 
> > > Sent: Monday, 20 June, 2022 8:14 PM
> > > To: Chee, Tien Fong 
> > > Cc: Vasut, Marek ; simon.k.r.goldschm...@gmail.com;
> > > michal.si...@xilinx.com; u-boot@lists.denx.de; s...@chromium.org;
> > > feste...@denx.de; ja...@amarulasolutions.com;
> > > andre.przyw...@arm.com; Armstrong, Neil ;
> > > pbrobin...@gmail.com; thar...@gateworks.com; paul@linaro.org;
> > > christianshew...@gmail.com; adrian.fiergol...@fastree3d.com;
> > > marek.be...@nic.cz; Denk, Wolfgang ; Lim, Elly Siew
> Chin
> > > ; upstr...@semihalf.com;
> > > ams...@chromium.org
> > > Subject: Re: [PATCH v3 08/11] socfpga: arria10: Replace delays with
> > > busy waiting in cm_full_cfg
> > >
> > > On Mon, Jun 20, 2022 at 10:40 AM Chee, Tien Fong
> > >  wrote:
> > > >
> > > > Hi,
> > > >
> > > > > -Original Message-
> > > > > From: Paweł Anikiel 
> > > > > Sent: Friday, 17 June, 2022 6:47 PM
> > > > > To: Vasut, Marek ;
> > > > > simon.k.r.goldschm...@gmail.com; Chee, Tien Fong
> > > > > ; michal.si...@xilinx.com
> > > > > Cc: u-boot@lists.denx.de; s...@chromium.org; feste...@denx.de;
> > > > > ja...@amarulasolutions.com; andre.przyw...@arm.com; Armstrong,
> > > Neil
> > > > > ; pbrobin...@gmail.com;
> > > > > thar...@gateworks.com; paul@linaro.org;
> > > > > christianshew...@gmail.com; adrian.fiergol...@fastree3d.com;
> > > > > marek.be...@nic.cz; Denk, Wolfgang ; Lim, Elly Siew
> > > Chin
> > > > > ; upstr...@semihalf.com;
> > > > > ams...@chromium.org; Paweł Anikiel 
> > > > > Subject: [PATCH v3 08/11] socfpga: arria10: Replace delays with
> > > > > busy waiting in cm_full_cfg
> > > > >
> > > > > Using udelay while the clocks aren't fully configured causes the
> > > > > timer system to save the wrong clock rate. Use sdelay and
> > > > > wait_on_value instead (the values used in these functions were
> > > > > found
> > > experimentally).
> > > > >
> > > > > Signed-off-by: Paweł Anikiel 
> > > > > ---
> > > > >  arch/arm/mach-socfpga/clock_manager_arria10.c | 31
> > > > > +-
> > > > > -
> > > > >  1 file changed, 22 insertions(+), 9 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > index 58d5d3fd8a..b48a2b47bc 100644
> > > > > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > >
> > > > Did you try to call timer_init() after cm_basic_init() in
> > > > board_init_f? If that's
> > > working, then no change is required to fix this clock issue.
> > >
> > > Seems like timer_init() isn't implemented on Arria 10 (it defaults
> > > to the return 0 stub). I also tried dm_timer_init(), no luck.
> > >
> > > I did some code digging, the clock rate is read by clk_get_rate(),
> > > and the timer rate is set by dw_apb_timer_probe()
> > > (drivers/timer/dw-apb- timer.c:77), and there doesn't seem to be a
> > > good way of updating that value later.
> > >
> > > The only other function I could find that sets the timer rate is
> > > timer_pre_probe() from drivers/timer/timer-uclass.c, which very much
> > > looks like what we need, but it's static and the name suggests it
> > > shouldn't be called manually anyway.
> > >
> >
> > Thanks for the details finding.
> >
> > I found that both Cyclone 5 and S10 (including all AARCH64 devices) having
> own timer_init() as solution for this issue.
> > Cyclone 5 :
> > https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-
> socfp
> > ga/timer.c
> > S10:
> > https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-
> socfp
> > ga/timer_s10.c
> >
> > Do you think this is good idea having the same for A10 device?
> 
> I don't think overriding timer_init() alone is going to help.
> (Re)initializing the timer after cm_basic_init() won't help the fact that 
> xdelay()
> divides the clock ticks (which are correct) by
> gd->timer->uclass_priv_->clock_rate
> (https://source.denx.de/u-boot/u-boot/-/blob/master/lib/time.c#L81)
> (which was incorrectly set by a call to udelay() from cm_full_cfg()).
> 
> I honestly don't see how Cyclone/Arria 5 solve this problem, as they don't
> implement a __udelay(), and their cm

[3/4] net: phy: marvell: Remove PHY_INTERFACE_MODE_SGMII_2500

[hardeep sharma]

Hello U-boot Team ,
can anyone please help me out
regarding this patch just want to know why this patch still not merged with
the mainline code ? I am knew to this u-boot community Please add right POC
if you know .
[3/4] net: phy: marvell: Remove PHY_INTERFACE_MODE_SGMII_2500

Thanks & Regards ,
Hardeep Sharma

Re: [PATCH v3] powerpc: mpc85xx: Set TEXT_BASE addresses to real base values

[Pali Rohár]

On Thursday 16 June 2022 14:19:44 Pali Rohár wrote:
> Currently CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE addresses are
> manually increased by 0x1000 due to .bootpg section. This section has size
> of 0x1000 bytes and is manually put by linker script before .text section
> (and therefore before base address) when CONFIG_SYS_MPC85XX_NO_RESETVEC is
> set. Due to this fact lot of other config options are manually increased by
> 0x1000 value to make correct layout. Note that entry point is not on
> CONFIG_SPL_TEXT_BASE (image+0x1000) but it is really on address
> CONFIG_SPL_TEXT_BASE-0x1000 (means at the start of the image).
> 
> Cleanup handling of .bootpg section when CONFIG_SYS_MPC85XX_NO_RESETVEC is
> set. Put .bootpg code directly into .text section and move text base
> address to the start of .bootpg code. And finally remove +0x1000 value from
> lot of config options. With this removal custom PHDRS is not used anymore,
> so remove it too.
> 
> After this change entry point would be at CONFIG_SPL_TEXT_BASE and not at
> address -0x1000 anymore.
> 
> Tested on P2020 board with SPL and proper U-Boot.
> 
> Signed-off-by: Pali Rohár 
> ---

PING???

> Changes in v3:
> * Rebased on top of the U-Boot next branch, commit 
> a87a6fcd20c0e29fe55bfbb6917c4aa1f1bbce74
> 
> Changes in v2:
> * Rebased on top of the U-Boot master branch, commit 
> 9bb99fa95826d1a608737ca821977b4136a1a278
> ---
>  arch/powerpc/cpu/mpc85xx/start.S |  4 ++--
>  arch/powerpc/cpu/mpc85xx/u-boot-spl.lds  | 15 +++-
>  arch/powerpc/cpu/mpc85xx/u-boot.lds  | 24 ++--
>  configs/P1010RDB-PA_36BIT_NAND_defconfig |  8 +++
>  configs/P1010RDB-PA_36BIT_SDCARD_defconfig   |  6 ++---
>  configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig |  6 ++---
>  configs/P1010RDB-PA_NAND_defconfig   |  8 +++
>  configs/P1010RDB-PA_SDCARD_defconfig |  6 ++---
>  configs/P1010RDB-PA_SPIFLASH_defconfig   |  6 ++---
>  configs/P1010RDB-PB_36BIT_NAND_defconfig |  8 +++
>  configs/P1010RDB-PB_36BIT_SDCARD_defconfig   |  6 ++---
>  configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig |  6 ++---
>  configs/P1010RDB-PB_NAND_defconfig   |  8 +++
>  configs/P1010RDB-PB_SDCARD_defconfig |  6 ++---
>  configs/P1010RDB-PB_SPIFLASH_defconfig   |  6 ++---
>  configs/P1020RDB-PC_36BIT_NAND_defconfig |  8 +++
>  configs/P1020RDB-PC_36BIT_SDCARD_defconfig   |  6 ++---
>  configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig |  6 ++---
>  configs/P1020RDB-PC_NAND_defconfig   |  8 +++
>  configs/P1020RDB-PC_SDCARD_defconfig |  6 ++---
>  configs/P1020RDB-PC_SPIFLASH_defconfig   |  6 ++---
>  configs/P1020RDB-PD_NAND_defconfig   |  8 +++
>  configs/P1020RDB-PD_SDCARD_defconfig |  6 ++---
>  configs/P1020RDB-PD_SPIFLASH_defconfig   |  6 ++---
>  configs/P2020RDB-PC_36BIT_NAND_defconfig |  8 +++
>  configs/P2020RDB-PC_36BIT_SDCARD_defconfig   |  6 ++---
>  configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig |  6 ++---
>  configs/P2020RDB-PC_NAND_defconfig   |  8 +++
>  configs/P2020RDB-PC_SDCARD_defconfig |  6 ++---
>  configs/P2020RDB-PC_SPIFLASH_defconfig   |  6 ++---
>  configs/T1024RDB_NAND_defconfig  |  2 +-
>  configs/T1024RDB_SDCARD_defconfig|  2 +-
>  configs/T1024RDB_SPIFLASH_defconfig  |  2 +-
>  configs/T1042D4RDB_NAND_defconfig|  2 +-
>  configs/T1042D4RDB_SDCARD_defconfig  |  2 +-
>  configs/T1042D4RDB_SPIFLASH_defconfig|  2 +-
>  configs/T2080QDS_NAND_defconfig  |  2 +-
>  configs/T2080QDS_SDCARD_defconfig|  2 +-
>  configs/T2080QDS_SPIFLASH_defconfig  |  2 +-
>  configs/T2080RDB_NAND_defconfig  |  2 +-
>  configs/T2080RDB_SDCARD_defconfig|  2 +-
>  configs/T2080RDB_SPIFLASH_defconfig  |  2 +-
>  configs/T2080RDB_revD_NAND_defconfig |  2 +-
>  configs/T2080RDB_revD_SDCARD_defconfig   |  2 +-
>  configs/T2080RDB_revD_SPIFLASH_defconfig |  2 +-
>  configs/T4240RDB_SDCARD_defconfig|  2 +-
>  configs/qemu-ppce500_defconfig   |  4 ++--
>  47 files changed, 120 insertions(+), 139 deletions(-)
> 
> diff --git a/arch/powerpc/cpu/mpc85xx/start.S 
> b/arch/powerpc/cpu/mpc85xx/start.S
> index 9a28269020dc..5009cbef54a0 100644
> --- a/arch/powerpc/cpu/mpc85xx/start.S
> +++ b/arch/powerpc/cpu/mpc85xx/start.S
> @@ -1128,7 +1128,7 @@ switch_as:
>   /*--*/
>   lis r3,CONFIG_VAL(SYS_MONITOR_BASE)@h
>   ori r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l
> - addir3,r3,_start_cont - _start_cont
> + addir3,r3,_start_cont - CONFIG_VAL(SYS_MONITOR_BASE)
>   mtlrr3
>   blr
>  #endif
> @@ -1600,7 +1600,7 @@ relocate_code:
>   * initialization, now running from RAM.
>   */
>  
> - addir0,r10,in_ram - _start_cont
> + addir0,r10,in_ram - CONFIG_VAL(SYS_MONITO

Re: [PATCH 1/2] imx: kontron-sl-mx8mm: Sync dts files and fix ethernet

[Fabio Estevam]

Hi Frieder,

On Thu, Jun 23, 2022 at 4:22 AM Frieder Schrempf
 wrote:
>
> Hi Tom,
>
> Am 14.06.22 um 15:03 schrieb Frieder Schrempf:
> > From: Frieder Schrempf 
> >
> > This syncs the devicetree files with the latest Linux kernel (5.19-rc2).
> > This also fixes the currently broken ethernet support:
> >
> > Before:
> >
> >   Net:   Could not get PHY for FEC0: addr 0
> >
> > After:
> >
> >   Net:   eth0: ethernet@30be
> >
> > Signed-off-by: Frieder Schrempf 
>
> I only posted this last week and there haven't been any responses yet.
> But as the 2022.07 release is approaching and you were asking for
> pending fixes, this is one you might consider.

Yes, this one is a bug fix, so it should go to 2022.07 final.

Reviewed-by: Fabio Estevam 

Re: [PATCH 1/2] microblaze: Convert axi timer to DM driver

[Michal Simek]

On 6/23/22 10:37, Ovidiu Panait wrote:
CAUTION: This message has originated from an External Source. Please use proper 
judgment and caution when opening attachments, clicking links, or responding to 
this email.



Hi Michal,

On 6/8/22 13:38, Michal Simek wrote:
[...]

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 7b8ab56ed323..44d1a81bad3d 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -272,4 +272,12 @@ config IMX_GPT_TIMER
   Select this to enable support for the timer found on
   NXP i.MX devices.

+config XILINX_TIMER
+   bool "Xilinx timer support"
+   depends on TIMER
+   select REGMAP


Tested-by: Ovidiu Panait 


I think the SPL select should also be added:

    select SPL_REGMAP if SPL



No problem with it. Patch sent.

Thanks,
Michal

[PATCH] timer: Add SPL_REGMAP dependency for Xilinx timer

[Michal Simek]

Add SPL_REGMAP dependency when SPL is enabled. This can avoid compilation
issues if timer is selected but SPL_REGMAP not.

Reported-by: Ovidiu Panait 
Signed-off-by: Michal Simek 
---

 drivers/timer/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 44d1a81bad3d..61156371a666 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -276,6 +276,7 @@ config XILINX_TIMER
bool "Xilinx timer support"
depends on TIMER
select REGMAP
+   select SPL_REGMAP if SPL
help
  Select this to enable support for the timer found on
  any Xilinx boards (axi timer).
-- 
2.36.1

[PATCH] xilinx: Enable support for SquashFS

[Michal Simek]

Enable SquashFS for all xilinx platforms.

Signed-off-by: Michal Simek 
---

 configs/xilinx_versal_virt_defconfig | 1 +
 configs/xilinx_zynq_virt_defconfig   | 1 +
 configs/xilinx_zynqmp_virt_defconfig | 1 +
 3 files changed, 3 insertions(+)

diff --git a/configs/xilinx_versal_virt_defconfig 
b/configs/xilinx_versal_virt_defconfig
index c9ae0185f8ad..1ab9ae2ac3cb 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -44,6 +44,7 @@ CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SQUASHFS=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_UBI=y
 CONFIG_PARTITION_TYPE_GUID=y
diff --git a/configs/xilinx_zynq_virt_defconfig 
b/configs/xilinx_zynq_virt_defconfig
index 120bc29393d8..489e86adb344 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -58,6 +58,7 @@ CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SQUASHFS=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_MTDPARTS_SPREAD=y
 CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig 
b/configs/xilinx_zynqmp_virt_defconfig
index de945c5c65b5..59b4cf6eaa2b 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -81,6 +81,7 @@ CONFIG_CMD_TIMER=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SQUASHFS=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_MTDPARTS_SPREAD=y
 CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
-- 
2.36.1

[PATCH] ls1021atwr: caam: Enable Uboot validaion in SPL.

[Gaurav Jain]

caam driver model enabled in spl for secure boot.
fsl_rsa_mod_exp driver enabled in spl for validating uboot image.

Signed-off-by: Gaurav Jain 
---
 MAINTAINERS |  1 +
 arch/arm/dts/ls1021a-twr-u-boot.dtsi| 29 +
 arch/arm/dts/ls1021a-twr.dtsi   |  1 +
 board/freescale/common/fsl_chain_of_trust.c |  6 +
 board/freescale/common/fsl_validate.c   | 10 ++-
 board/freescale/ls1021atwr/ls1021atwr.c | 13 +++--
 6 files changed, 52 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/dts/ls1021a-twr-u-boot.dtsi

diff --git a/MAINTAINERS b/MAINTAINERS
index 28e4d38238..d9bfb307ef 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1450,5 +1450,6 @@ F:*/
 CAAM
 M: Gaurav Jain 
 S: Maintained
+F: arch/arm/dts/ls1021a-twr-u-boot.dtsi
 F: drivers/crypto/fsl/
 F: include/fsl_sec.h
diff --git a/arch/arm/dts/ls1021a-twr-u-boot.dtsi 
b/arch/arm/dts/ls1021a-twr-u-boot.dtsi
new file mode 100644
index 00..3711e42419
--- /dev/null
+++ b/arch/arm/dts/ls1021a-twr-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2022 NXP
+ */
+
+&{/soc} {
+   u-boot,dm-spl;
+   u-boot,dm-pre-reloc;
+};
+
+&crypto {
+   u-boot,dm-spl;
+};
+
+&sec_jr0 {
+   u-boot,dm-spl;
+};
+
+&sec_jr1 {
+   u-boot,dm-spl;
+};
+
+&sec_jr2 {
+   u-boot,dm-spl;
+};
+
+&sec_jr3 {
+   u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi
index bf96af7e36..82df2f11bb 100644
--- a/arch/arm/dts/ls1021a-twr.dtsi
+++ b/arch/arm/dts/ls1021a-twr.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include "ls1021a.dtsi"
+#include "ls1021a-twr-u-boot.dtsi"
 
 / {
model = "LS1021A TWR Board";
diff --git a/board/freescale/common/fsl_chain_of_trust.c 
b/board/freescale/common/fsl_chain_of_trust.c
index 7ffb315bc9..1b9733cf83 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2022 NXP
  */
 
 #include 
@@ -113,11 +114,6 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t 
img_addr)
fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-   if (sec_init() < 0)
-   fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT);
-#endif
-
 /*
  * dm_init_and_scan() is called as part of common SPL framework, so no
  * need to call it again but in case of powerpc platforms which currently
diff --git a/board/freescale/common/fsl_validate.c 
b/board/freescale/common/fsl_validate.c
index 34875d0b8f..569a8c4655 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
- * Copyright 2021 NXP
+ * Copyright 2021-2022 NXP
  */
 
 #include 
@@ -20,6 +20,7 @@
 #ifdef CONFIG_ARCH_LS1021A
 #include 
 #endif
+#include 
 
 #define SHA256_BITS256
 #define SHA256_BYTES   (256/8)
@@ -806,6 +807,13 @@ static int calculate_cmp_img_sig(struct 
fsl_secboot_img_priv *img)
prop.num_bits = key_len * 8;
prop.exp_len = key_len;
 
+#if defined(CONFIG_SPL_BUILD)
+   ret = device_bind_driver(NULL, "fsl_rsa_mod_exp", "fsl_rsa_mod_exp", 
NULL);
+   if (ret) {
+   printf("Couldn't bind fsl_rsa_mod_exp driver (%d)\n", ret);
+   return -EINVAL;
+   }
+#endif
ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev);
if (ret) {
printf("RSA: Can't find Modular Exp implementation\n");
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c 
b/board/freescale/ls1021atwr/ls1021atwr.c
index a3aa84deb2..746b35a678 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019, 2021 NXP
+ * Copyright 2019, 2021-2022 NXP
  */
 
 #include 
@@ -34,7 +34,7 @@
 #include 
 #endif
 #include 
-
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -530,6 +530,15 @@ int board_init(void)
 #if defined(CONFIG_SPL_BUILD)
 void spl_board_init(void)
 {
+   if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+   struct udevice *dev;
+   int ret;
+
+   ret = uclass_get_device_by_driver(UCLASS_MISC, 
DM_DRIVER_GET(caam_jr), &dev);
+   if (ret)
+   printf("Failed to initialize caam_jr: %d\n", ret);
+   }
+
ls102xa_smmu_stream_id_init();
 }
 #endif
-- 
2.25.1

Re: [PATCH v5 08/23] FWU: Add boot time checks as highlighted by the FWU specification

[Sughosh Ganu]

hi Patrick,

On Tue, 21 Jun 2022 at 17:16, Patrick DELAUNAY
 wrote:
>
> Hi,
>
>
> On 6/9/22 14:29, Sughosh Ganu wrote:
> > The FWU Multi Bank Update specification requires the Update Agent to
> > carry out certain checks at the time of platform boot. The Update
> > Agent is the component which is responsible for updating the firmware
> > components and maintaining and keeping the metadata in sync.
> >
> > The spec requires that the Update Agent perform the following checks
> > at the time of boot
> > * Sanity check of both the metadata copies maintained by the platform.
> > * Get the boot index passed to U-Boot by the prior stage bootloader
> >and use this value for metadata bookkeeping.
> > * Check if the system is booting in Trial State. If the system boots
> >in the Trial State for more than a specified number of boot counts,
> >change the Active Bank to be booting the platform from.
> >
> > Add these checks in the board initialisation sequence, invoked after
> > relocation.
> >
> > Signed-off-by: Sughosh Ganu 
> > ---
> >   common/board_r.c  |   5 ++
> >   include/fwu.h |   3 +
> >   lib/fwu_updates/fwu.c | 170 ++
> >   3 files changed, 178 insertions(+)
> >   create mode 100644 lib/fwu_updates/fwu.c
> >
> > diff --git a/common/board_r.c b/common/board_r.c
> > index 6f4aca2077..33a600715d 100644
> > --- a/common/board_r.c
> > +++ b/common/board_r.c
> > @@ -15,6 +15,7 @@
> >   #include 
> >   #include 
> >   #include 
> > +#include 
> >   #include 
> >   #include 
> >   #include 
> > @@ -797,6 +798,10 @@ static init_fnc_t init_sequence_r[] = {
> >   #if defined(CONFIG_PRAM)
> >   initr_mem,
> >   #endif
> > +
> > +#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
> > + fwu_boottime_checks,
> > +#endif
> >   run_main_loop,
> >   };
> >
> > diff --git a/include/fwu.h b/include/fwu.h
> > index 41774ff9e2..8fbd91b463 100644
> > --- a/include/fwu.h
> > +++ b/include/fwu.h
> > @@ -33,6 +33,9 @@ struct fwu_mdata_ops {
> >   EFI_GUID(0x8a7a84a0, 0x8387, 0x40f6, 0xab, 0x41, \
> >0xa8, 0xb9, 0xa5, 0xa6, 0x0d, 0x23)
> >
> > +int fwu_boottime_checks(void);
> > +u8 fwu_update_checks_pass(void);
> > +
> >   int fwu_get_mdata(struct fwu_mdata **mdata);
> >   int fwu_update_mdata(struct fwu_mdata *mdata);
> >   int fwu_get_active_index(u32 *active_idx);
> > diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c
> > new file mode 100644
> > index 00..af884439fb
> > --- /dev/null
> > +++ b/lib/fwu_updates/fwu.c
> > @@ -0,0 +1,170 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2022, Linaro Limited
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include 
> > +#include 
> > +
> > +static u8 trial_state;
> > +static u8 boottime_check;
> > +
> > +static int fwu_trial_state_check(void)
> > +{
> > + int ret, i;
> > + efi_status_t status;
> > + efi_uintn_t var_size;
> > + u16 trial_state_ctr;
> > + u32 nimages, active_bank, var_attributes, active_idx;
> > + struct fwu_mdata *mdata = NULL;
> > + struct fwu_image_entry *img_entry;
> > + struct fwu_image_bank_info *img_bank_info;
> > +
> > + ret = fwu_get_mdata(&mdata);
> > + if (ret)
> > + return ret;
> > +
> > + ret = 0;
> > + nimages = CONFIG_FWU_NUM_IMAGES_PER_BANK;
> > + active_bank = mdata->active_index;
> > + img_entry = &mdata->img_entry[0];
> > + for (i = 0; i < nimages; i++) {
> > + img_bank_info = &img_entry[i].img_bank_info[active_bank];
> > + if (!img_bank_info->accepted) {
> > + trial_state = 1;
> > + break;
> > + }
> > + }
> > +
> > + if (trial_state) {
> > + var_size = (efi_uintn_t)sizeof(trial_state_ctr);
> > + log_info("System booting in Trial State\n");
> > + var_attributes = EFI_VARIABLE_NON_VOLATILE |
> > + EFI_VARIABLE_BOOTSERVICE_ACCESS;
> > + status = efi_get_variable_int(L"TrialStateCtr",
> > +   &efi_global_variable_guid,
> > +   &var_attributes,
> > +   &var_size, &trial_state_ctr,
> > +   NULL);
>
> for 'L"TrialStateCtr"' => wide characters for unicode
>
> L string is really needed here ?
>
> cf=
> http://patchwork.ozlabs.org/project/uboot/patch/20220123195514.3152022-5-...@chromium.org/
>
> same for all the other string L"TrialStateCtr" in the file...

Will change.

>
>
> > + if (status != EFI_SUCCESS) {
> > + log_err("Unable to read TrialStateCtr variable\n");
> > + ret = -1;
> > + goto out;
> > + }
> > +
> > + ++trial_state_ctr;
> > + if (trial_state_ctr > CONFIG_FWU

Re: [PATCH v5 08/23] FWU: Add boot time checks as highlighted by the FWU specification

[Sughosh Ganu]

hi Etienne,

On Tue, 21 Jun 2022 at 16:26, Etienne Carriere
 wrote:
>
> Hi Sughosh,
>
> On Thu, 9 Jun 2022 at 14:31, Sughosh Ganu  wrote:
> >
> > The FWU Multi Bank Update specification requires the Update Agent to
> > carry out certain checks at the time of platform boot. The Update
> > Agent is the component which is responsible for updating the firmware
> > components and maintaining and keeping the metadata in sync.
> >
> > The spec requires that the Update Agent perform the following checks
> > at the time of boot
> > * Sanity check of both the metadata copies maintained by the platform.
> > * Get the boot index passed to U-Boot by the prior stage bootloader
> >   and use this value for metadata bookkeeping.
> > * Check if the system is booting in Trial State. If the system boots
> >   in the Trial State for more than a specified number of boot counts,
> >   change the Active Bank to be booting the platform from.
> >
> > Add these checks in the board initialisation sequence, invoked after
> > relocation.
> >
> > Signed-off-by: Sughosh Ganu 
> > ---
> >  common/board_r.c  |   5 ++
> >  include/fwu.h |   3 +
> >  lib/fwu_updates/fwu.c | 170 ++
> >  3 files changed, 178 insertions(+)
> >  create mode 100644 lib/fwu_updates/fwu.c



> > --- /dev/null
> > +++ b/lib/fwu_updates/fwu.c
> > @@ -0,0 +1,170 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2022, Linaro Limited
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include 
> > +#include 
> > +
> > +static u8 trial_state;
> > +static u8 boottime_check;
> > +
> > +static int fwu_trial_state_check(void)
> > +{
> > +   int ret, i;
> > +   efi_status_t status;
> > +   efi_uintn_t var_size;
> > +   u16 trial_state_ctr;
> > +   u32 nimages, active_bank, var_attributes, active_idx;
> > +   struct fwu_mdata *mdata = NULL;
> > +   struct fwu_image_entry *img_entry;
> > +   struct fwu_image_bank_info *img_bank_info;
> > +
> > +   ret = fwu_get_mdata(&mdata);
> > +   if (ret)
> > +   return ret;
> > +
> > +   ret = 0;
> > +   nimages = CONFIG_FWU_NUM_IMAGES_PER_BANK;
> > +   active_bank = mdata->active_index;
> > +   img_entry = &mdata->img_entry[0];
> > +   for (i = 0; i < nimages; i++) {
> > +   img_bank_info = &img_entry[i].img_bank_info[active_bank];
> > +   if (!img_bank_info->accepted) {
> > +   trial_state = 1;
> > +   break;
> > +   }
> > +   }
> > +
> > +   if (trial_state) {
> > +   var_size = (efi_uintn_t)sizeof(trial_state_ctr);
> > +   log_info("System booting in Trial State\n");
> > +   var_attributes = EFI_VARIABLE_NON_VOLATILE |
> > +   EFI_VARIABLE_BOOTSERVICE_ACCESS;
> > +   status = efi_get_variable_int(L"TrialStateCtr",
> > + &efi_global_variable_guid,
> > + &var_attributes,
> > + &var_size, &trial_state_ctr,
> > + NULL);
> > +   if (status != EFI_SUCCESS) {
> > +   log_err("Unable to read TrialStateCtr variable\n");
> > +   ret = -1;
> > +   goto out;
> > +   }
> > +
> > +   ++trial_state_ctr;
> > +   if (trial_state_ctr > CONFIG_FWU_TRIAL_STATE_CNT) {
> > +   log_info("Trial State count exceeded. Revert back 
> > to previous_active_index\n");
> > +   active_idx = mdata->active_index;
> > +   ret = fwu_revert_boot_index();
> > +   if (ret) {
> > +   log_err("Unable to revert active_index\n");
> > +   goto out;
> > +   }
> > +
> > +   trial_state_ctr = 0;
> > +   status = efi_set_variable_int(L"TrialStateCtr",
> > + 
> > &efi_global_variable_guid,
> > + var_attributes,
> > + 0,
>
> s/0/var_size/ ?
> Ditto 24 lines below.

The variable size is 0 since the variable is being deleted here and
the other instance that you mention. Maybe I can put a comment in the
two places.

>
> > + &trial_state_ctr, 
> > false);
> > +   if (status != EFI_SUCCESS) {
> > +   log_err("Unable to clear TrialStateCtr 
> > variable\n");
> > +   ret = -1;
> > +   goto out;
> > +   }
> > +   

[PATCH v2] led: pwm: Use NOP uclass driver for top-level node

[Stefan Herbrechtsmeier]

From: Stefan Herbrechtsmeier 

The top level DT node of pwm-leds is not a LED itself, bind NOP uclass
driver to it, and bind different LED uclass driver to its subnodes which
represent the actual LEDs. This change removes the top-level node from
the 'led list' command output and is based on the commit 01074697801b
("led: gpio: Use NOP uclass driver for top-level node").

Signed-off-by: Stefan Herbrechtsmeier 

---

Changes in v2:
- Remove unused uc_plat variable

 drivers/led/led_pwm.c | 19 +++
 1 file changed, 7 insertions(+), 12 deletions(-)

diff --git a/drivers/led/led_pwm.c b/drivers/led/led_pwm.c
index 10bd1636c3..0ebae358eb 100644
--- a/drivers/led/led_pwm.c
+++ b/drivers/led/led_pwm.c
@@ -95,27 +95,17 @@ static enum led_state_t led_pwm_get_state(struct udevice 
*dev)
 static int led_pwm_probe(struct udevice *dev)
 {
struct led_pwm_priv *priv = dev_get_priv(dev);
-   struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
-
-   /* Ignore the top-level LED node */
-   if (!uc_plat->label)
-   return 0;
 
return led_pwm_set_state(dev, (priv->enabled) ? LEDST_ON : LEDST_OFF);
 }
 
 static int led_pwm_of_to_plat(struct udevice *dev)
 {
-   struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct led_pwm_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
uint def_brightness, max_brightness;
int ret;
 
-   /* Ignore the top-level LED node */
-   if (!uc_plat->label)
-   return 0;
-
ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0, 
&args);
if (ret)
return ret;
@@ -173,10 +163,15 @@ static const struct udevice_id led_pwm_ids[] = {
 U_BOOT_DRIVER(led_pwm) = {
.name = LEDS_PWM_DRIVER_NAME,
.id = UCLASS_LED,
-   .of_match = led_pwm_ids,
.ops = &led_pwm_ops,
.priv_auto = sizeof(struct led_pwm_priv),
-   .bind = led_pwm_bind,
.probe = led_pwm_probe,
.of_to_plat = led_pwm_of_to_plat,
 };
+
+U_BOOT_DRIVER(led_pwm_wrap) = {
+   .name = LEDS_PWM_DRIVER_NAME "_wrap",
+   .id = UCLASS_NOP,
+   .of_match = led_pwm_ids,
+   .bind = led_pwm_bind,
+};
-- 
2.30.2

[PATCH RESEND 9/9] config/ast2600: Enable eMMC related boot options

[Joel Stanley]

Allow booting zImage from ext4 devices with DOS or UEFI partition
layouts.

Signed-off-by: Joel Stanley 
---
 configs/evb-ast2600_defconfig | 13 +
 1 file changed, 13 insertions(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 160bccff48e2..69f6f30c6543 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -42,6 +42,14 @@ CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_EEPROM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -49,6 +57,11 @@ CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_DOS_PARTITION=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-- 
2.35.1

[PATCH RESEND 8/9] mmc/aspeed: Enable controller clocks

[Joel Stanley]

Request and enable the controller level clocks.

Signed-off-by: Joel Stanley 
---
 drivers/mmc/aspeed_sdhci.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c
index 5591fa2b0891..9d79bf58cc70 100644
--- a/drivers/mmc/aspeed_sdhci.c
+++ b/drivers/mmc/aspeed_sdhci.c
@@ -99,6 +99,21 @@ U_BOOT_DRIVER(aspeed_sdhci_drv) = {
 
 static int aspeed_sdc_probe(struct udevice *parent)
 {
+   struct clk clk;
+   int ret;
+
+   ret = clk_get_by_index(parent, 0, &clk);
+   if (ret) {
+   debug("%s: clock get failed %d\n", __func__, ret);
+   return ret;
+   }
+
+   ret = clk_enable(&clk);
+   if (ret) {
+   debug("%s: clock enable failed %d\n", __func__, ret);
+   return ret;
+   }
+
return 0;
 }
 
-- 
2.35.1

[PATCH RESEND 7/9] mmc/aspeed: Probe from controller

[Joel Stanley]

The Aspeed SDHCI controller is arranged with some shared control
registers, followed by one or two sets of actual SDHCI registers.

Adjust the driver to probe this controller device first. The driver then
wants to iterate over the child nodes to probe the SDHCI proper:

ofnode node;

dev_for_each_subnode(node, parent) {
struct udevice *dev;
int ret;

ret = device_bind_driver_to_node(parent, "aspeed_sdhci",
 ofnode_get_name(node),
 node, &dev);
if (ret)
return ret;
}

However if we did this the sdhci driver would probe twice; once
"naturally" from the device tree and a second time due to this code.

Instead of doing this we can rely on the probe order, where the
controller will be set up before the sdhci devices. A better solution is
preferred.

Select MISC as the controller driver is implemented as a misc device.

Signed-off-by: Joel Stanley 
---
 drivers/mmc/aspeed_sdhci.c | 21 +
 drivers/mmc/Kconfig|  1 +
 2 files changed, 22 insertions(+)

diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c
index c71daae97584..5591fa2b0891 100644
--- a/drivers/mmc/aspeed_sdhci.c
+++ b/drivers/mmc/aspeed_sdhci.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 struct aspeed_sdhci_plat {
struct mmc_config cfg;
@@ -94,3 +95,23 @@ U_BOOT_DRIVER(aspeed_sdhci_drv) = {
.priv_auto  = sizeof(struct sdhci_host),
.plat_auto  = sizeof(struct aspeed_sdhci_plat),
 };
+
+
+static int aspeed_sdc_probe(struct udevice *parent)
+{
+   return 0;
+}
+
+static const struct udevice_id aspeed_sdc_ids[] = {
+   { .compatible = "aspeed,ast2400-sd-controller" },
+   { .compatible = "aspeed,ast2500-sd-controller" },
+   { .compatible = "aspeed,ast2600-sd-controller" },
+   { }
+};
+
+U_BOOT_DRIVER(aspeed_sdc_drv) = {
+   .name   = "aspeed_sdc",
+   .id = UCLASS_MISC,
+   .of_match   = aspeed_sdc_ids,
+   .probe  = aspeed_sdc_probe,
+};
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 5e2921ce41a7..07ff69afea69 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -489,6 +489,7 @@ config MMC_SDHCI_ASPEED
depends on ARCH_ASPEED
depends on DM_MMC
depends on MMC_SDHCI
+   select MISC
help
  Enables support for the Aspeed SDHCI 2.0 controller present on Aspeed
  SoCs. This device is compatible with SD 3.0 and/or MMC 4.3
-- 
2.35.1

[PATCH RESEND 6/9] mmc/aspeed: Add debuging for clock probe failures

[Joel Stanley]

Signed-off-by: Joel Stanley 
---
 drivers/mmc/aspeed_sdhci.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c
index 453731571987..c71daae97584 100644
--- a/drivers/mmc/aspeed_sdhci.c
+++ b/drivers/mmc/aspeed_sdhci.c
@@ -26,12 +26,16 @@ static int aspeed_sdhci_probe(struct udevice *dev)
int ret;
 
ret = clk_get_by_index(dev, 0, &clk);
-   if (ret)
+   if (ret) {
+   debug("%s: clock get failed %d\n", __func__, ret);
return ret;
+   }
 
ret = clk_enable(&clk);
-   if (ret)
+   if (ret) {
+   debug("%s: clock enable failed %d\n", __func__, ret);
goto free;
+   }
 
host->name = dev->name;
host->ioaddr = dev_read_addr_ptr(dev);
@@ -39,6 +43,7 @@ static int aspeed_sdhci_probe(struct udevice *dev)
max_clk = clk_get_rate(&clk);
if (IS_ERR_VALUE(max_clk)) {
ret = max_clk;
+   debug("%s: clock rate get failed %d\n", __func__, ret);
goto err;
}
 
-- 
2.35.1

[PATCH RESEND 5/9] clk/ast2500: Add SD clock

[Joel Stanley]

In order to use the clock from the sdhci driver, add the SD clock.

Signed-off-by: Joel Stanley 
---
 drivers/clk/aspeed/clk_ast2500.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index dcf299548de1..623c6915b81f 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -426,6 +427,25 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu 
*scu, ulong rate)
return new_rate;
 }
 
+#define SCU_CLKSTOP_SDIO 27
+static ulong ast2500_enable_sdclk(struct ast2500_scu *scu)
+{
+   u32 reset_bit;
+   u32 clkstop_bit;
+
+   reset_bit = BIT(ASPEED_RESET_SDIO);
+   clkstop_bit = BIT(SCU_CLKSTOP_SDIO);
+
+   setbits_le32(&scu->sysreset_ctrl1, reset_bit);
+   udelay(100);
+   //enable clk
+   clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
+   mdelay(10);
+   clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
+
+   return 0;
+}
+
 static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
 {
struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
@@ -481,6 +501,9 @@ static int ast2500_clk_enable(struct clk *clk)
case ASPEED_CLK_D2PLL:
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
break;
+   case ASPEED_CLK_GATE_SDCLK:
+   ast2500_enable_sdclk(priv->scu);
+   break;
default:
debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT;
-- 
2.35.1

[PATCH RESEND 4/9] clk/ast2600: Adjust eMMC clock names

[Joel Stanley]

Adjust clock to stay compatible with those used by the Linux kernel
device tree.

Signed-off-by: Joel Stanley 
---
 drivers/clk/aspeed/clk_ast2600.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index 7d85c7f09823..0df1dc3718d3 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -1073,13 +1073,13 @@ static int ast2600_clk_enable(struct clk *clk)
case ASPEED_CLK_GATE_SDCLK:
ast2600_enable_sdclk(priv->scu);
break;
-   case ASPEED_CLK_GATE_SDEXTCLK:
+   case ASPEED_CLK_SDIO:
ast2600_enable_extsdclk(priv->scu);
break;
case ASPEED_CLK_GATE_EMMCCLK:
ast2600_enable_emmcclk(priv->scu);
break;
-   case ASPEED_CLK_GATE_EMMCEXTCLK:
+   case ASPEED_CLK_EMMC:
ast2600_enable_extemmcclk(priv->scu);
break;
case ASPEED_CLK_GATE_FSICLK:
-- 
2.35.1

[PATCH RESEND 3/9] clk/aspeed: Add debug message when clock fails

[Joel Stanley]

A common message across platforms that prints the clock number.

Signed-off-by: Joel Stanley 
---
 drivers/clk/aspeed/clk_ast2500.c | 3 +++
 drivers/clk/aspeed/clk_ast2600.c | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index a1b4496ca2c6..dcf299548de1 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -173,6 +173,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = ast2500_get_uart_clk_rate(priv->scu, 5);
break;
default:
+   debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT;
}
 
@@ -438,6 +439,7 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong 
rate)
new_rate = ast2500_configure_d2pll(priv->scu, rate);
break;
default:
+   debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT;
}
 
@@ -480,6 +482,7 @@ static int ast2500_clk_enable(struct clk *clk)
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
break;
default:
+   debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT;
}
 
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index f191b0f31707..7d85c7f09823 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -471,7 +471,7 @@ static ulong ast2600_clk_get_rate(struct clk *clk)
rate = ast2600_get_uart_huxclk_rate(priv->scu);
break;
default:
-   debug("can't get clk rate\n");
+   debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT;
}
 
@@ -1098,7 +1098,7 @@ static int ast2600_clk_enable(struct clk *clk)
ast2600_enable_rsaclk(priv->scu);
break;
default:
-   pr_err("can't enable clk\n");
+   debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT;
}
 
-- 
2.35.1

[PATCH RESEND 2/9] ARM: dts: ast2500: Update SDHCI nodes

[Joel Stanley]

Match the description used by the Linux kernel, except use scu instead
of syscon as the phandle.

Signed-off-by: Joel Stanley 
---
 arch/arm/dts/ast2500-evb.dts |  4 
 arch/arm/dts/ast2500-u-boot.dtsi | 25 -
 arch/arm/dts/ast2500.dtsi| 28 
 3 files changed, 32 insertions(+), 25 deletions(-)

diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 4796ed445f57..2f1f246dc460 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -60,6 +60,10 @@
pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>;
 };
 
+&sdmmc {
+   status = "okay";
+};
+
 &sdhci0 {
status = "okay";
 
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index ea60e4c8db92..057390fe707e 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -28,31 +28,6 @@
clocks = <&scu ASPEED_CLK_MPLL>;
resets = <&rst ASPEED_RESET_SDRAM>;
};
-
-   ahb {
-   u-boot,dm-pre-reloc;
-
-   apb {
-   u-boot,dm-pre-reloc;
-
-   sdhci0: sdhci@1e740100 {
-   compatible = "aspeed,ast2500-sdhci";
-   reg = <0x1e740100>;
-   #reset-cells = <1>;
-   clocks = <&scu ASPEED_CLK_SDIO>;
-   resets = <&rst ASPEED_RESET_SDIO>;
-   };
-
-   sdhci1: sdhci@1e740200 {
-   compatible = "aspeed,ast2500-sdhci";
-   reg = <0x1e740200>;
-   #reset-cells = <1>;
-   clocks = <&scu ASPEED_CLK_SDIO>;
-   resets = <&rst ASPEED_RESET_SDIO>;
-   };
-   };
-
-   };
 };
 
 &uart1 {
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index ee66ef67042b..cea08e6f08df 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -207,6 +207,34 @@
reg = <0x1e72 0x9000>;  // 36K
};
 
+   sdmmc: sd-controller@1e74 {
+   compatible = "aspeed,ast2500-sd-controller";
+   reg = <0x1e74 0x100>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0x1e74 0x1>;
+   clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
+   status = "disabled";
+
+   sdhci0: sdhci@100 {
+   compatible = "aspeed,ast2500-sdhci";
+   reg = <0x100 0x100>;
+   interrupts = <26>;
+   sdhci,auto-cmd12;
+   clocks = <&scu ASPEED_CLK_SDIO>;
+   status = "disabled";
+   };
+
+   sdhci1: sdhci@200 {
+   compatible = "aspeed,ast2500-sdhci";
+   reg = <0x200 0x100>;
+   interrupts = <26>;
+   sdhci,auto-cmd12;
+   clocks = <&scu ASPEED_CLK_SDIO>;
+   status = "disabled";
+   };
+   };
+
gpio: gpio@1e78 {
#gpio-cells = <2>;
gpio-controller;
-- 
2.35.1

[PATCH RESEND 1/9] ARM: dts: ast2600: Update SDHCI nodes

[Joel Stanley]

Match the description used by the Linux kernel, except use scu instead
of syscon as the phandle.

Signed-off-by: Joel Stanley 
---
 arch/arm/dts/ast2600-evb.dts | 24 +++
 arch/arm/dts/ast2600.dtsi| 57 +++-
 2 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index 0d650543134a..47a0daa6dfbf 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -15,9 +15,9 @@
};
 
aliases {
-   mmc0 = &emmc_slot0;
-   mmc1 = &sdhci_slot0;
-   mmc2 = &sdhci_slot1;
+   mmc0 = &emmc;
+   mmc1 = &sdhci0;
+   mmc2 = &sdhci1;
spi0 = &fmc;
spi1 = &spi1;
spi2 = &spi2;
@@ -134,18 +134,16 @@
};
 };
 
-&emmc {
-   u-boot,dm-pre-reloc;
-   timing-phase = <0x700ff>;
+
+&emmc_controller {
+status = "okay";
 };
 
-&emmc_slot0 {
-   u-boot,dm-pre-reloc;
-   status = "okay";
-   bus-width = <4>;
-   pinctrl-names = "default";
-   pinctrl-0 = <&pinctrl_emmc_default>;
-   sdhci-drive-type = <1>;
+&emmc {
+non-removable;
+bus-width = <4>;
+max-frequency = <1>;
+clk-phase-mmc-hs200 = <9>, <225>;
 };
 
 &i2c4 {
diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 64074309b7b2..3161e76941fd 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -416,60 +416,51 @@
status = "disabled";
};
 
-   sdhci: sdhci@1e74 {
-   #interrupt-cells = <1>;
-   compatible = "aspeed,aspeed-sdhci-irq", 
"simple-mfd";
-   reg = <0x1e74 0x1000>;
-   interrupts = ;
-   interrupt-controller;
-   clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
-<&scu ASPEED_CLK_GATE_SDEXTCLK>;
-   clock-names = "ctrlclk", "extclk";
+   sdc: sdc@1e74 {
+   compatible = "aspeed,ast2600-sd-controller";
+   reg = <0x1e74 0x100>;
#address-cells = <1>;
#size-cells = <1>;
-   ranges = <0x0 0x1e74 0x1000>;
+   ranges = <0 0x1e74 0x1>;
+   clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
+   status = "disabled";
 
-   sdhci_slot0: sdhci_slot0@100 {
-   compatible = "aspeed,sdhci-ast2600";
+   sdhci0: sdhci@1e740100 {
+   compatible = "aspeed,ast2600-sdhci", 
"sdhci";
reg = <0x100 0x100>;
-   interrupts = <0>;
-   interrupt-parent = <&sdhci>;
+   interrupts = ;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
 
-   sdhci_slot1: sdhci_slot1@200 {
-   compatible = "aspeed,sdhci-ast2600";
+   sdhci1: sdhci@1e740200 {
+   compatible = "aspeed,ast2600-sdhci", 
"sdhci";
reg = <0x200 0x100>;
-   interrupts = <1>;
-   interrupt-parent = <&sdhci>;
+   interrupts = ;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
};
 
-   emmc: emmc@1e75 {
-   #interrupt-cells = <1>;
-   compatible = "aspeed,aspeed-emmc-irq", 
"simple-mfd";
-   reg = <0x1e75 0x1000>;
-   interrupts = ;
-   interrupt-controller;
-   clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>,
-<&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
-   clock-names = "ctrlclk", "extclk";
+   emmc_controller: sdc@1e75 {
+   compatible = "aspeed,ast2600-sd-controller";
+ 

[PATCH RESEND 0/9] mmc: Fixes for Aspeed boards

[Joel Stanley]

These changes get the SDHCI hardware on the AST2600 and AST2500 working
using the same device tree layout as upstream Linux.

The series has been tested on the Qemu models of the ast2500-evb and
ast2600-evb, and tested on the ast2600a3-evb hardware.

(this is a resend as I had a stray comma in the To list that broke
sending the first attempt)

Joel Stanley (9):
  ARM: dts: ast2600: Update SDHCI nodes
  ARM: dts: ast2500: Update SDHCI nodes
  clk/aspeed: Add debug message when clock fails
  clk/ast2600: Adjust eMMC clock names
  clk/ast2500: Add SD clock
  mmc/aspeed: Add debuging for clock probe failures
  mmc/aspeed: Probe from controller
  mmc/aspeed: Enable controller clocks
  config/ast2600: Enable eMMC related boot options

 drivers/clk/aspeed/clk_ast2500.c | 26 +++
 drivers/clk/aspeed/clk_ast2600.c |  8 ++---
 drivers/mmc/aspeed_sdhci.c   | 45 +++--
 arch/arm/dts/ast2500-evb.dts |  4 +++
 arch/arm/dts/ast2500-u-boot.dtsi | 25 --
 arch/arm/dts/ast2500.dtsi| 28 
 arch/arm/dts/ast2600-evb.dts | 24 ++
 arch/arm/dts/ast2600.dtsi| 57 ++--
 configs/evb-ast2600_defconfig| 13 
 drivers/mmc/Kconfig  |  1 +
 10 files changed, 154 insertions(+), 77 deletions(-)

-- 
2.35.1

[PATCH 1/9] ARM: dts: ast2600: Update SDHCI nodes

[Joel Stanley]

Match the description used by the Linux kernel, except use scu instead
of syscon as the phandle.

Signed-off-by: Joel Stanley 
---
 arch/arm/dts/ast2600-evb.dts | 24 +++
 arch/arm/dts/ast2600.dtsi| 57 +++-
 2 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index 0d650543134a..47a0daa6dfbf 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -15,9 +15,9 @@
};
 
aliases {
-   mmc0 = &emmc_slot0;
-   mmc1 = &sdhci_slot0;
-   mmc2 = &sdhci_slot1;
+   mmc0 = &emmc;
+   mmc1 = &sdhci0;
+   mmc2 = &sdhci1;
spi0 = &fmc;
spi1 = &spi1;
spi2 = &spi2;
@@ -134,18 +134,16 @@
};
 };
 
-&emmc {
-   u-boot,dm-pre-reloc;
-   timing-phase = <0x700ff>;
+
+&emmc_controller {
+status = "okay";
 };
 
-&emmc_slot0 {
-   u-boot,dm-pre-reloc;
-   status = "okay";
-   bus-width = <4>;
-   pinctrl-names = "default";
-   pinctrl-0 = <&pinctrl_emmc_default>;
-   sdhci-drive-type = <1>;
+&emmc {
+non-removable;
+bus-width = <4>;
+max-frequency = <1>;
+clk-phase-mmc-hs200 = <9>, <225>;
 };
 
 &i2c4 {
diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 64074309b7b2..3161e76941fd 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -416,60 +416,51 @@
status = "disabled";
};
 
-   sdhci: sdhci@1e74 {
-   #interrupt-cells = <1>;
-   compatible = "aspeed,aspeed-sdhci-irq", 
"simple-mfd";
-   reg = <0x1e74 0x1000>;
-   interrupts = ;
-   interrupt-controller;
-   clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
-<&scu ASPEED_CLK_GATE_SDEXTCLK>;
-   clock-names = "ctrlclk", "extclk";
+   sdc: sdc@1e74 {
+   compatible = "aspeed,ast2600-sd-controller";
+   reg = <0x1e74 0x100>;
#address-cells = <1>;
#size-cells = <1>;
-   ranges = <0x0 0x1e74 0x1000>;
+   ranges = <0 0x1e74 0x1>;
+   clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
+   status = "disabled";
 
-   sdhci_slot0: sdhci_slot0@100 {
-   compatible = "aspeed,sdhci-ast2600";
+   sdhci0: sdhci@1e740100 {
+   compatible = "aspeed,ast2600-sdhci", 
"sdhci";
reg = <0x100 0x100>;
-   interrupts = <0>;
-   interrupt-parent = <&sdhci>;
+   interrupts = ;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
 
-   sdhci_slot1: sdhci_slot1@200 {
-   compatible = "aspeed,sdhci-ast2600";
+   sdhci1: sdhci@1e740200 {
+   compatible = "aspeed,ast2600-sdhci", 
"sdhci";
reg = <0x200 0x100>;
-   interrupts = <1>;
-   interrupt-parent = <&sdhci>;
+   interrupts = ;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
};
 
-   emmc: emmc@1e75 {
-   #interrupt-cells = <1>;
-   compatible = "aspeed,aspeed-emmc-irq", 
"simple-mfd";
-   reg = <0x1e75 0x1000>;
-   interrupts = ;
-   interrupt-controller;
-   clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>,
-<&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
-   clock-names = "ctrlclk", "extclk";
+   emmc_controller: sdc@1e75 {
+   compatible = "aspeed,ast2600-sd-controller";
+ 

[PATCH 0/9] mmc: Aspeed fixes

[Joel Stanley]

These changes get the SDHCI hardware on the AST2600 and AST2500 working
using the same device tree layout as upstream Linux.

The series has been tested on the Qemu models of the ast2500-evb and
ast2600-evb, and tested on the ast2600a3-evb hardware.

Joel Stanley (9):
  ARM: dts: ast2600: Update SDHCI nodes
  ARM: dts: ast2500: Update SDHCI nodes
  clk/aspeed: Add debug message when clock fails
  clk/ast2600: Adjust eMMC clock names
  clk/ast2500: Add SD clock
  mmc/aspeed: Add debuging for clock probe failures
  mmc/aspeed: Probe from controller
  mmc/aspeed: Enable controller clocks
  config/ast2600: Enable eMMC related boot options

 drivers/clk/aspeed/clk_ast2500.c | 26 +++
 drivers/clk/aspeed/clk_ast2600.c |  8 ++---
 drivers/mmc/aspeed_sdhci.c   | 45 +++--
 arch/arm/dts/ast2500-evb.dts |  4 +++
 arch/arm/dts/ast2500-u-boot.dtsi | 25 --
 arch/arm/dts/ast2500.dtsi| 28 
 arch/arm/dts/ast2600-evb.dts | 24 ++
 arch/arm/dts/ast2600.dtsi| 57 ++--
 configs/evb-ast2600_defconfig| 13 
 drivers/mmc/Kconfig  |  1 +
 10 files changed, 154 insertions(+), 77 deletions(-)

-- 
2.35.1

Re: [PATCH 1/2] microblaze: Convert axi timer to DM driver

[Ovidiu Panait]

Hi Michal,

On 6/8/22 13:38, Michal Simek wrote:
[...]

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 7b8ab56ed323..44d1a81bad3d 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -272,4 +272,12 @@ config IMX_GPT_TIMER
   Select this to enable support for the timer found on
   NXP i.MX devices.

+config XILINX_TIMER
+   bool "Xilinx timer support"
+   depends on TIMER
+   select REGMAP


Tested-by: Ovidiu Panait 


I think the SPL select should also be added:

   select SPL_REGMAP if SPL


This will fix the spl link errors with the following config:

CONFIG_TIMER=y

CONFIG_SPL_TIMER=y

CONFIG_XILINX_TIMER=y

...

microblazeel-linux-ld.bfd: drivers/timer/xilinx-timer.o: in function 
`xilinx_timer_get_count':

drivers/timer/xilinx-timer.c:41: undefined reference to `regmap_read'
microblazeel-linux-ld.bfd: drivers/timer/xilinx-timer.o: in function 
`xilinx_timer_probe':

drivers/timer/xilinx-timer.c:52: undefined reference to `regmap_init_mem'
microblazeel-linux-ld.bfd: drivers/timer/xilinx-timer.c:58: undefined 
reference to `regmap_write'
microblazeel-linux-ld.bfd: drivers/timer/xilinx-timer.c:59: undefined 
reference to `regmap_write'
microblazeel-linux-ld.bfd: drivers/timer/xilinx-timer.c:60: undefined 
reference to `regmap_write'

make[1]: *** [scripts/Makefile.spl:525: spl/u-boot-spl] Error 1


Thanks,

Ovidiu


+   help
+ Select this to enable support for the timer found on
+ any Xilinx boards (axi timer).
+
  endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index b2f002d59789..4d06375317e1 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -27,3 +27,4 @@ obj-$(CONFIG_X86_TSC_TIMER)   += tsc_timer.o
  obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
  obj-$(CONFIG_MCHP_PIT64B_TIMER)+= mchp-pit64b-timer.o
  obj-$(CONFIG_IMX_GPT_TIMER)+= imx-gpt-timer.o
+obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o
diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c
new file mode 100644
index ..75b4473b6397
--- /dev/null
+++ b/drivers/timer/xilinx-timer.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 Advanced Micro Devices, Inc
+ * Michal Simek 
+ *
+ * (C) Copyright 2007 Michal Simek
+ * Michal SIMEK 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define TIMER_ENABLE_ALL0x400 /* ENALL */
+#define TIMER_PWM   0x200 /* PWMA0 */
+#define TIMER_INTERRUPT 0x100 /* T0INT */
+#define TIMER_ENABLE0x080 /* ENT0 */
+#define TIMER_ENABLE_INTR   0x040 /* ENIT0 */
+#define TIMER_RESET 0x020 /* LOAD0 */
+#define TIMER_RELOAD0x010 /* ARHT0 */
+#define TIMER_EXT_CAPTURE   0x008 /* CAPT0 */
+#define TIMER_EXT_COMPARE   0x004 /* GENT0 */
+#define TIMER_DOWN_COUNT0x002 /* UDT0 */
+#define TIMER_CAPTURE_MODE  0x001 /* MDT0 */
+
+#define TIMER_CONTROL_OFFSET   0
+#define TIMER_LOADREG_OFFSET   4
+#define TIMER_COUNTER_OFFSET   8
+
+struct xilinx_timer_priv {
+   struct regmap *regs;
+};
+
+static u64 xilinx_timer_get_count(struct udevice *dev)
+{
+   struct xilinx_timer_priv *priv = dev_get_priv(dev);
+   u32 value;
+
+   regmap_read(priv->regs, TIMER_COUNTER_OFFSET, &value);
+
+   return value;
+}
+
+static int xilinx_timer_probe(struct udevice *dev)
+{
+   struct xilinx_timer_priv *priv = dev_get_priv(dev);
+   int ret;
+
+   /* uc_priv->clock_rate has already clock rate */
+   ret = regmap_init_mem(dev_ofnode(dev), &priv->regs);
+   if (ret) {
+   dev_dbg(dev, "failed to get regbase of timer\n");
+   return ret;
+   }
+
+   regmap_write(priv->regs, TIMER_LOADREG_OFFSET, 0);
+   regmap_write(priv->regs, TIMER_CONTROL_OFFSET, TIMER_RESET);
+   regmap_write(priv->regs, TIMER_CONTROL_OFFSET,
+TIMER_ENABLE | TIMER_RELOAD);
+
+   return 0;
+}
+
+static const struct timer_ops xilinx_timer_ops = {
+   .get_count = xilinx_timer_get_count,
+};
+
+static const struct udevice_id xilinx_timer_ids[] = {
+   { .compatible = "xlnx,xps-timer-1.00.a" },
+   {}
+};
+
+U_BOOT_DRIVER(xilinx_timer) = {
+   .name = "xilinx_timer",
+   .id = UCLASS_TIMER,
+   .of_match = xilinx_timer_ids,
+   .priv_auto = sizeof(struct xilinx_timer_priv),
+   .probe = xilinx_timer_probe,
+   .ops = &xilinx_timer_ops,
+};
--
2.36.1

Re: [PATCH 1/2] imx: kontron-sl-mx8mm: Sync dts files and fix ethernet

[Frieder Schrempf]

Hi Tom,

Am 14.06.22 um 15:03 schrieb Frieder Schrempf:
> From: Frieder Schrempf 
> 
> This syncs the devicetree files with the latest Linux kernel (5.19-rc2).
> This also fixes the currently broken ethernet support:
> 
> Before:
> 
>   Net:   Could not get PHY for FEC0: addr 0
> 
> After:
> 
>   Net:   eth0: ethernet@30be
> 
> Signed-off-by: Frieder Schrempf 

I only posted this last week and there haven't been any responses yet.
But as the 2022.07 release is approaching and you were asking for
pending fixes, this is one you might consider.

Thanks
Frieder

> ---
>  arch/arm/dts/imx8mm-kontron-n801x-s.dts| 48 +++---
>  arch/arm/dts/imx8mm-kontron-n801x-som.dtsi |  6 +--
>  2 files changed, 8 insertions(+), 46 deletions(-)
> 
> diff --git a/arch/arm/dts/imx8mm-kontron-n801x-s.dts 
> b/arch/arm/dts/imx8mm-kontron-n801x-s.dts
> index c796d144e22..23be1ec538b 100644
> --- a/arch/arm/dts/imx8mm-kontron-n801x-s.dts
> +++ b/arch/arm/dts/imx8mm-kontron-n801x-s.dts
> @@ -6,7 +6,6 @@
>  /dts-v1/;
>  
>  #include "imx8mm-kontron-n801x-som.dtsi"
> -#include 
>  
>  / {
>   model = "Kontron i.MX8MM N801X S";
> @@ -81,7 +80,6 @@
>   regulator-name = "vdd-5v";
>   regulator-min-microvolt = <500>;
>   regulator-max-microvolt = <500>;
> - regulator-always-on;
>   };
>  };
>  
> @@ -124,38 +122,14 @@
>   #size-cells = <0>;
>  
>   ethphy: ethernet-phy@0 {
> - compatible = "ethernet-phy-id0007.0570";
>   reg = <0>;
> - reset-assert-us = <100>;
> - reset-deassert-us = <100>;
> + reset-assert-us = <1>;
> + reset-deassert-us = <15000>;
>   reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
> - vsc8531,led-0-mode = ;
> - vsc8531,led-1-mode = ;
> - vsc8531,led-0-combine-disable;
>   };
>   };
>  };
>  
> -&gpio4 {
> - dsi_mux_sel: dsi_mux_sel {
> - gpio-hog;
> - gpios = <14 GPIO_ACTIVE_HIGH>;
> - output-high;
> - line-name = "dsi-mux-sel";
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_dsi_sel>;
> - };
> -
> - dsi_mux_oe {
> - gpio-hog;
> - gpios = <15 GPIO_ACTIVE_LOW>;
> - output-high;
> - line-name = "dsi-mux-oe";
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_dsi_oe>;
> - };
> -};
> -
>  &i2c4 {
>   clock-frequency = <10>;
>   pinctrl-names = "default";
> @@ -208,7 +182,7 @@
>   #address-cells = <1>;
>   #size-cells = <0>;
>  
> - usbnet: usbether@1 {
> + usbnet: ethernet@1 {
>   compatible = "usb424,ec00";
>   reg = <1>;
>   local-mac-address = [ 00 00 00 00 00 00 ];
> @@ -237,18 +211,6 @@
>   >;
>   };
>  
> - pinctrl_dsi_sel: dsiselgrp {
> - fsl,pins = <
> - MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14   0x19
> - >;
> - };
> -
> - pinctrl_dsi_oe: dsioegrp {
> - fsl,pins = <
> - MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15   0x19
> - >;
> - };
> -
>   pinctrl_ecspi2: ecspi2grp {
>   fsl,pins = <
>   MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO0x82
> @@ -362,7 +324,7 @@
>   >;
>   };
>  
> - pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
>   fsl,pins = <
>   MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
>   MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
> @@ -374,7 +336,7 @@
>   >;
>   };
>  
> - pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
>   fsl,pins = <
>   MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
>   MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
> diff --git a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi 
> b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi
> index c3418d263eb..8f90eb02550 100644
> --- a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi
> +++ b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi
> @@ -63,10 +63,10 @@
>  &ecspi1 {
>   pinctrl-names = "default";
>   pinctrl-0 = <&pinctrl_ecspi1>;
> - cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
> + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
>   status = "okay";
>  
> - spi-flash@0 {
> + flash@0 {
>   compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
>   spi-max-frequency = <8000>;
>   reg = <0>;
> @@ -154,7 +154,7 @@
>   reg_vdd_snvs: LDO2 {
>