[PATCH 5/5] test/py: efi_secboot: add a test for a forged signed image
In this test case, a image binary, helloworld.efi.signed, is willfully
modified to print a corrupted message while the signature itself is
unchanged.
This binary must be rejected under secure boot mode.
Signed-off-by: AKASHI Takahiro
---
test/py/tests/test_efi_secboot/conftest.py| 3 ++
test/py/tests/test_efi_secboot/forge_image.sh | 5 +++
test/py/tests/test_efi_secboot/test_signed.py | 35 +++
3 files changed, 43 insertions(+)
create mode 100644 test/py/tests/test_efi_secboot/forge_image.sh
diff --git a/test/py/tests/test_efi_secboot/conftest.py
b/test/py/tests/test_efi_secboot/conftest.py
index 8a53dabe5414..db6b8d301f85 100644
--- a/test/py/tests/test_efi_secboot/conftest.py
+++ b/test/py/tests/test_efi_secboot/conftest.py
@@ -105,6 +105,9 @@ def efi_boot_env(request, u_boot_config):
# Sign already-signed image with another key
check_call('cd %s; sbsign --key db1.key --cert db1.crt --output
helloworld.efi.signed_2sigs helloworld.efi.signed'
% mnt_point, shell=True)
+# Create a corrupted signed image
+check_call('cd %s; sh %s/test/py/tests/test_efi_secboot/forge_image.sh
helloworld.efi.signed helloworld_forged.efi.signed'
+ % (mnt_point, u_boot_config.source_dir), shell=True)
# Digest image
check_call('cd %s; %shash-to-efi-sig-list helloworld.efi
db_hello.hash; %ssign-efi-sig-list -t "2020-04-07" -c KEK.crt -k KEK.key db
db_hello.hash db_hello.auth'
% (mnt_point, EFITOOLS_PATH, EFITOOLS_PATH),
diff --git a/test/py/tests/test_efi_secboot/forge_image.sh
b/test/py/tests/test_efi_secboot/forge_image.sh
new file mode 100644
index ..2465d10fa7b8
--- /dev/null
+++ b/test/py/tests/test_efi_secboot/forge_image.sh
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#!/bin/sh
+
+replace_exp="s/H\0e\0l\0l\0o\0/h\0E\0L\0L\0O\0/g"
+perl -p -e ${replace_exp} < $1 > $2
diff --git a/test/py/tests/test_efi_secboot/test_signed.py
b/test/py/tests/test_efi_secboot/test_signed.py
index 30b3fa4e701e..ca52e853d8f8 100644
--- a/test/py/tests/test_efi_secboot/test_signed.py
+++ b/test/py/tests/test_efi_secboot/test_signed.py
@@ -334,3 +334,38 @@ class TestEfiSignedImage(object):
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
+
+def test_efi_signed_image_auth8(self, u_boot_console, efi_boot_env):
+"""
+Test Case 8 - Secure boot is in force,
+ Same as Test Case 2 but the image binary to be loaded
+ was willfully modified (forged)
+ Must be rejected.
+"""
+u_boot_console.restart_uboot()
+disk_img = efi_boot_env
+with u_boot_console.log.section('Test Case 8a'):
+# Test Case 8a, Secure boot is not yet forced
+output = u_boot_console.run_command_list([
+'host bind 0 %s' % disk_img,
+'efidebug boot add -b 1 HELLO1 host 0:1
/helloworld_forged.efi.signed -s ""',
+'efidebug boot next 1',
+'efidebug test bootmgr'])
+assert('hELLO, world!' in ''.join(output))
+
+with u_boot_console.log.section('Test Case 8b'):
+# Test Case 8b, Install signature database and verify the image
+output = u_boot_console.run_command_list([
+'fatload host 0:1 400 db.auth',
+'setenv -e -nv -bs -rt -at -i 400:$filesize db',
+'fatload host 0:1 400 KEK.auth',
+'setenv -e -nv -bs -rt -at -i 400:$filesize KEK',
+'fatload host 0:1 400 PK.auth',
+'setenv -e -nv -bs -rt -at -i 400:$filesize PK'])
+assert 'Failed to set EFI variable' not in ''.join(output)
+output = u_boot_console.run_command_list([
+'efidebug boot next 1',
+'efidebug test bootmgr'])
+assert(not 'hELLO, world!' in ''.join(output))
+assert('\'HELLO1\' failed' in ''.join(output))
+assert('efi_start_image() returned: 26' in ''.join(output))
--
2.36.1
[PATCH 4/5] efi_loader: image_loader: add a missing digest verification for signed PE image
At the last step of PE image authentication, an image's hash value must be
compared with a message digest stored as the content (of SpcPeImageData type)
of pkcs7's contentInfo.
Fixes: commit 4540dabdcaca ("efi_loader: image_loader: support image
authentication")
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/Kconfig| 1 +
lib/efi_loader/efi_image_loader.c | 62 ++-
2 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index e2a1a5a69a24..e3f2402d0e8e 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -366,6 +366,7 @@ config EFI_SECURE_BOOT
select X509_CERTIFICATE_PARSER
select PKCS7_MESSAGE_PARSER
select PKCS7_VERIFY
+ select MSCODE_PARSER
select EFI_SIGNATURE_SUPPORT
help
Select this option to enable EFI secure boot support.
diff --git a/lib/efi_loader/efi_image_loader.c
b/lib/efi_loader/efi_image_loader.c
index fe8e4a89082c..eaf75a5803d4 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#include
@@ -516,6 +517,51 @@ err:
}
#ifdef CONFIG_EFI_SECURE_BOOT
+/**
+ * efi_image_verify_digest - verify image's message digest
+ * @regs: Array of memory regions to digest
+ * @msg: Signature in pkcs7 structure
+ *
+ * @regs contains all the data in a PE image to digest. Calculate
+ * a hash value based on @regs and compare it with a messaged digest
+ * in the content (SpcPeImageData) of @msg's contentInfo.
+ *
+ * Return: true if verified, false if not
+ */
+static bool efi_image_verify_digest(struct efi_image_regions *regs,
+ struct pkcs7_message *msg)
+{
+ struct pefile_context ctx;
+ void *hash;
+ int hash_len, ret;
+
+ const void *data;
+ size_t data_len;
+ size_t asn1hdrlen;
+
+ /* get pkcs7's contentInfo */
+ ret = pkcs7_get_content_data(msg, , _len, );
+ if (ret < 0 || !data)
+ return false;
+
+ /* parse data and retrieve a message digest into ctx */
+ ret = mscode_parse(, data, data_len, asn1hdrlen);
+ if (ret < 0)
+ return false;
+
+ /* calculate a hash value of PE image */
+ hash = NULL;
+ if (!efi_hash_regions(regs->reg, regs->num, , ctx.digest_algo,
+ _len))
+ return false;
+
+ /* match the digest */
+ if (ctx.digest_len != hash_len || memcmp(ctx.digest, hash, hash_len))
+ return false;
+
+ return true;
+}
+
/**
* efi_image_authenticate() - verify a signature of signed image
* @efi: Pointer to image
@@ -645,6 +691,9 @@ static bool efi_image_authenticate(void *efi, size_t
efi_size)
}
/*
+* verify signatures in pkcs7's signedInfos which are
+* to authenticate the integrity of pkcs7's contentInfo.
+*
* NOTE:
* UEFI specification defines two signature types possible
* in signature database:
@@ -677,12 +726,21 @@ static bool efi_image_authenticate(void *efi, size_t
efi_size)
}
/* try white-list */
- if (efi_signature_verify(regs, msg, db, dbx)) {
+ if (!efi_signature_verify(regs, msg, db, dbx)) {
+ log_debug("Signature was not verified by \"db\"\n");
+ continue;
+ }
+
+ /*
+* now calculate an image's hash value and compare it with
+* a messaged digest embedded in pkcs7's contentInfo
+*/
+ if (efi_image_verify_digest(regs, msg)) {
ret = true;
continue;
}
- log_debug("Signature was not verified by \"db\"\n");
+ log_debug("Message digest doesn't match\n");
}
--
2.36.1
[PATCH 3/5] efi_loader: image_loader: replace EFI_PRINT with log macros
Now We are migrating from EFI_PRINT() to log macro's.
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_image_loader.c | 54 +++
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/lib/efi_loader/efi_image_loader.c
b/lib/efi_loader/efi_image_loader.c
index 961139888504..fe8e4a89082c 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -238,7 +238,7 @@ efi_status_t efi_image_region_add(struct efi_image_regions
*regs,
int i, j;
if (regs->num >= regs->max) {
- EFI_PRINT("%s: no more room for regions\n", __func__);
+ log_err("%s: no more room for regions\n", __func__);
return EFI_OUT_OF_RESOURCES;
}
@@ -263,7 +263,7 @@ efi_status_t efi_image_region_add(struct efi_image_regions
*regs,
}
/* new data overlapping registered region */
- EFI_PRINT("%s: new region already part of another\n", __func__);
+ log_err("%s: new region already part of another\n", __func__);
return EFI_INVALID_PARAMETER;
}
@@ -434,8 +434,8 @@ bool efi_image_parse(void *efi, size_t len, struct
efi_image_regions **regp,
bytes_hashed = opt->SizeOfHeaders;
align = opt->FileAlignment;
} else {
- EFI_PRINT("%s: Invalid optional header magic %x\n", __func__,
- nt->OptionalHeader.Magic);
+ log_err("%s: Invalid optional header magic %x\n", __func__,
+ nt->OptionalHeader.Magic);
goto err;
}
@@ -445,7 +445,7 @@ bool efi_image_parse(void *efi, size_t len, struct
efi_image_regions **regp,
nt->FileHeader.SizeOfOptionalHeader);
sorted = calloc(sizeof(IMAGE_SECTION_HEADER *), num_sections);
if (!sorted) {
- EFI_PRINT("%s: Out of memory\n", __func__);
+ log_err("%s: Out of memory\n", __func__);
goto err;
}
@@ -464,7 +464,7 @@ bool efi_image_parse(void *efi, size_t len, struct
efi_image_regions **regp,
efi_image_region_add(regs, efi + sorted[i]->PointerToRawData,
efi + sorted[i]->PointerToRawData + size,
0);
- EFI_PRINT("section[%d](%s): raw: 0x%x-0x%x, virt: %x-%x\n",
+ log_debug("section[%d](%s): raw: 0x%x-0x%x, virt: %x-%x\n",
i, sorted[i]->Name,
sorted[i]->PointerToRawData,
sorted[i]->PointerToRawData + size,
@@ -478,7 +478,7 @@ bool efi_image_parse(void *efi, size_t len, struct
efi_image_regions **regp,
/* 3. Extra data excluding Certificates Table */
if (bytes_hashed + authsz < len) {
- EFI_PRINT("extra data for hash: %zu\n",
+ log_debug("extra data for hash: %zu\n",
len - (bytes_hashed + authsz));
efi_image_region_add(regs, efi + bytes_hashed,
efi + len - authsz, 0);
@@ -487,18 +487,18 @@ bool efi_image_parse(void *efi, size_t len, struct
efi_image_regions **regp,
/* Return Certificates Table */
if (authsz) {
if (len < authoff + authsz) {
- EFI_PRINT("%s: Size for auth too large: %u >= %zu\n",
- __func__, authsz, len - authoff);
+ log_err("%s: Size for auth too large: %u >= %zu\n",
+ __func__, authsz, len - authoff);
goto err;
}
if (authsz < sizeof(*auth)) {
- EFI_PRINT("%s: Size for auth too small: %u < %zu\n",
- __func__, authsz, sizeof(*auth));
+ log_err("%s: Size for auth too small: %u < %zu\n",
+ __func__, authsz, sizeof(*auth));
goto err;
}
*auth = efi + authoff;
*auth_len = authsz;
- EFI_PRINT("WIN_CERTIFICATE: 0x%x, size: 0x%x\n", authoff,
+ log_debug("WIN_CERTIFICATE: 0x%x, size: 0x%x\n", authoff,
authsz);
} else {
*auth = NULL;
@@ -549,7 +549,7 @@ static bool efi_image_authenticate(void *efi, size_t
efi_size)
size_t auth_size;
bool ret = false;
- EFI_PRINT("%s: Enter, %d\n", __func__, ret);
+ log_debug("%s: Enter, %d\n", __func__, ret);
if (!efi_secure_boot_enabled())
return true;
@@ -560,7 +560,7 @@ static bool efi_image_authenticate(void *efi, size_t
efi_size)
if (!efi_image_parse(new_efi, efi_size, , ,
_len)) {
- EFI_PRINT("Parsing PE executable image failed\n");
+
[PATCH 2/5] efi_loader: signature: export efi_hash_regions()
This function is used to calculate a message digest as part of
authentication process in a later patch.
Signed-off-by: AKASHI Takahiro
---
include/efi_loader.h | 2 ++
lib/efi_loader/efi_signature.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index c1e00ebac398..11930fbea838 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -931,6 +931,8 @@ struct efi_signature_store {
struct x509_certificate;
struct pkcs7_message;
+bool efi_hash_regions(struct image_region *regs, int count,
+ void **hash, const char *hash_algo, int *len);
bool efi_signature_lookup_digest(struct efi_image_regions *regs,
struct efi_signature_store *db,
bool dbx);
diff --git a/lib/efi_loader/efi_signature.c b/lib/efi_loader/efi_signature.c
index ddac751d128e..742d8919402c 100644
--- a/lib/efi_loader/efi_signature.c
+++ b/lib/efi_loader/efi_signature.c
@@ -125,8 +125,8 @@ struct pkcs7_message *efi_parse_pkcs7_header(const void
*buf,
*
* Return: true on success, false on error
*/
-static bool efi_hash_regions(struct image_region *regs, int count,
-void **hash, const char *hash_algo, int *len)
+bool efi_hash_regions(struct image_region *regs, int count,
+ void **hash, const char *hash_algo, int *len)
{
int ret, hash_len;
--
2.36.1
[PATCH 1/5] lib: crypto: add mscode_parser
In MS authenticode, pkcs7 should have data in its contentInfo field.
This data is tagged with SpcIndirectData type and, for a signed PE image,
provides a image's message digest as SpcPeImageData.
This parser is used in image authentication to parse the field and
retrieve a message digest.
Imported from linux v5.19-rc, crypto/asymmetric_keys/mscode*.
Checkpatch.pl generates tones of warnings, but those are not fixed
for the sake of maintainability (importing from another source).
Signed-off-by: AKASHI Takahiro
---
include/crypto/mscode.h| 43
lib/crypto/Kconfig | 9 +++
lib/crypto/Makefile| 12
lib/crypto/mscode.asn1 | 28
lib/crypto/mscode_parser.c | 135 +
5 files changed, 227 insertions(+)
create mode 100644 include/crypto/mscode.h
create mode 100644 lib/crypto/mscode.asn1
create mode 100644 lib/crypto/mscode_parser.c
diff --git a/include/crypto/mscode.h b/include/crypto/mscode.h
new file mode 100644
index ..551058b96e60
--- /dev/null
+++ b/include/crypto/mscode.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* PE Binary parser bits
+ *
+ * Copyright (C) 2014 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowe...@redhat.com)
+ */
+
+#include
+#ifndef __UBOOT__
+#include
+#endif
+
+struct pefile_context {
+#ifndef __UBOOT__
+ unsignedheader_size;
+ unsignedimage_checksum_offset;
+ unsignedcert_dirent_offset;
+ unsignedn_data_dirents;
+ unsignedn_sections;
+ unsignedcerts_size;
+ unsignedsig_offset;
+ unsignedsig_len;
+ const struct section_header *secs;
+#endif
+
+ /* PKCS#7 MS Individual Code Signing content */
+ const void *digest;/* Digest */
+ unsigneddigest_len; /* Digest length */
+ const char *digest_algo; /* Digest algorithm */
+};
+
+#ifndef __UBOOT__
+#define kenter(FMT, ...) \
+ pr_devel("==> %s("FMT")\n", __func__, ##__VA_ARGS__)
+#define kleave(FMT, ...) \
+ pr_devel("<== %s()"FMT"\n", __func__, ##__VA_ARGS__)
+#endif
+
+/*
+ * mscode_parser.c
+ */
+extern int mscode_parse(void *_ctx, const void *content_data, size_t data_len,
+ size_t asn1hdrlen);
diff --git a/lib/crypto/Kconfig b/lib/crypto/Kconfig
index 1c04a7ec5f48..c3f563b2e174 100644
--- a/lib/crypto/Kconfig
+++ b/lib/crypto/Kconfig
@@ -82,4 +82,13 @@ config PKCS7_MESSAGE_PARSER
config PKCS7_VERIFY
bool
+config MSCODE_PARSER
+ bool "MS authenticode parser"
+ select ASN1_DECODER
+ select ASN1_COMPILER
+ select OID_REGISTRY
+ help
+ This option provides support for parsing MicroSoft's Authenticode
+ in pkcs7 message.
+
endif # ASYMMETRIC_KEY_TYPE
diff --git a/lib/crypto/Makefile b/lib/crypto/Makefile
index 6792b1d4f007..bec1bc95a658 100644
--- a/lib/crypto/Makefile
+++ b/lib/crypto/Makefile
@@ -55,3 +55,15 @@ obj-$(CONFIG_$(SPL_)PKCS7_VERIFY) += pkcs7_verify.o
$(obj)/pkcs7_parser.o: $(obj)/pkcs7.asn1.h
$(obj)/pkcs7.asn1.o: $(obj)/pkcs7.asn1.c $(obj)/pkcs7.asn1.h
+
+#
+# Signed PE binary-wrapped key handling
+#
+obj-$(CONFIG_$(SPL_)MSCODE_PARSER) += mscode.o
+
+mscode-y := \
+ mscode_parser.o \
+ mscode.asn1.o
+
+$(obj)/mscode_parser.o: $(obj)/mscode.asn1.h $(obj)/mscode.asn1.h
+$(obj)/mscode.asn1.o: $(obj)/mscode.asn1.c $(obj)/mscode.asn1.h
diff --git a/lib/crypto/mscode.asn1 b/lib/crypto/mscode.asn1
new file mode 100644
index ..6d09ba48c41c
--- /dev/null
+++ b/lib/crypto/mscode.asn1
@@ -0,0 +1,28 @@
+--- Microsoft individual code signing data blob parser
+---
+--- Copyright (C) 2012 Red Hat, Inc. All Rights Reserved.
+--- Written by David Howells (dhowe...@redhat.com)
+---
+--- This program is free software; you can redistribute it and/or
+--- modify it under the terms of the GNU General Public Licence
+--- as published by the Free Software Foundation; either version
+--- 2 of the Licence, or (at your option) any later version.
+---
+
+MSCode ::= SEQUENCE {
+ typeSEQUENCE {
+ contentType ContentType,
+ parameters ANY
+ },
+ content SEQUENCE {
+ digestAlgorithm DigestAlgorithmIdentifier,
+ digest OCTET STRING ({ mscode_note_digest })
+ }
+}
+
+ContentType ::= OBJECT IDENTIFIER ({ mscode_note_content_type })
+
+DigestAlgorithmIdentifier ::= SEQUENCE {
+ algorithm OBJECT IDENTIFIER ({ mscode_note_digest_algo }),
+ parameters ANY OPTIONAL
+}
diff --git a/lib/crypto/mscode_parser.c b/lib/crypto/mscode_parser.c
new file mode 100644
index ..90d5b37a6cf2
--- /dev/null
+++ b/lib/crypto/mscode_parser.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* Parse a Microsoft
[PATCH 0/5] efi_loader: fix a verification process issue in secure boot
In the commit 4540dabdcaca ("efi_loader: image_loader: support image
authentication"), U-Boot implementation of UEFI secure boot was
introduced.
It was reported by a Siemens engineer, however, that the verification
process is not fully compliant with MicroSoft's authenticode specification
and it is possible to exploit the code in a signed PE image without deep
knowledge.
This patch series fixes this security issue and, in addition, adds a test
case.
patch#1-3: preparatory patches
patch#4: add a missing step in signature verification process
patch#5: a new test case under pytest
AKASHI Takahiro (5):
lib: crypto: add mscode_parser
efi_loader: signature: export efi_hash_regions()
efi_loader: image_loader: replace EFI_PRINT with log macros
efi_loader: image_loader: add a missing digest verification for signed
PE image
test/py: efi_secboot: add a test for a forged signed image
include/crypto/mscode.h | 43 ++
include/efi_loader.h | 2 +
lib/crypto/Kconfig| 9 ++
lib/crypto/Makefile | 12 ++
lib/crypto/mscode.asn1| 28
lib/crypto/mscode_parser.c| 135 ++
lib/efi_loader/Kconfig| 1 +
lib/efi_loader/efi_image_loader.c | 114 +++
lib/efi_loader/efi_signature.c| 4 +-
test/py/tests/test_efi_secboot/conftest.py| 3 +
test/py/tests/test_efi_secboot/forge_image.sh | 5 +
test/py/tests/test_efi_secboot/test_signed.py | 35 +
12 files changed, 361 insertions(+), 30 deletions(-)
create mode 100644 include/crypto/mscode.h
create mode 100644 lib/crypto/mscode.asn1
create mode 100644 lib/crypto/mscode_parser.c
create mode 100644 test/py/tests/test_efi_secboot/forge_image.sh
--
2.36.1
Re: [PATCH 4/8] board: qualcomm: Add support for dragonboard845c
Hi Daniel,
On Mon, 4 Jul 2022 at 21:36, Daniel Thompson wrote:
>
> On Mon, Jul 04, 2022 at 06:28:41PM +0530, Sumit Garg wrote:
> > diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi
> > b/arch/arm/dts/dragonboard845c-uboot.dtsi
> > new file mode 100644
> > index 00..8b5a7ee573
> > --- /dev/null
> > +++ b/arch/arm/dts/dragonboard845c-uboot.dtsi
> > @@ -0,0 +1,37 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * U-Boot addition to handle Qualcomm Robotics RB3 Development Platform
> > + * (dragonboard845c) pins
> > + *
> > + * (C) Copyright 2022 Sumit Garg
> > + */
> > +
> > +/
> > +{
> > + soc {
> > + u-boot,dm-pre-reloc;
> > +
> > + serial@a84000 {
> > + u-boot,dm-pre-reloc;
> > + };
> > +
> > + clock-controller@10 {
> > + u-boot,dm-pre-reloc;
> > + };
> > +
> > + pinctrl_north@390 {
> > + u-boot,dm-pre-reloc;
> > + };
> > + };
> > +};
>
> These additional u-boot,dm-pre-reloc changes are different to the ones
> that appear in starqltechn-uboot.dtsi .
As I mentioned in the patch #1 review, u-boot properties are specified
incorrectly in starqltechn-uboot.dtsi. I will correct that.
> That suggests that either patch 1
> is not actually removing redundant properties or that the DB845C port is
> wrong.
The other node I left for DB845C without "u-boot,dm-pre-reloc" is
"gpio_north@390" as currently I am not using GPIO driver prior to
relocation.
>-Sumit
>
> > +config TARGET_DRAGONBOARD845C
> > + bool "96Boards Dragonboard 845C"
> > + help
> > + Support for 96Boards Dragonboard 845C aka Robotics RB3 Development
> > + Platform. This board complies with 96Board Open Platform
>
> Nitpicking but... s/96Board/96Boards/
>
Okay, I will correct it.
-Sumit
>
> Daniel.
Re: uuu using u-boot-with-spl.imx
Hi Peng
On Tue, Jul 5, 2022 at 6:44 AM Michael Nazzareno Trimarchi
wrote:
>
> Hi
>
>
> On Tue, Jul 5, 2022 at 3:20 AM Peng Fan wrote:
> >
> >
> >
> > On 7/4/2022 7:00 PM, Michael Nazzareno Trimarchi wrote:
> > > Hi Fabio and Marek
> > >
> > > Trying to understand the reason why I can boot using imx_usb loader
> > > and not the uuu tool
> >
> > How do you use uuu? uuu -b sd flash.bin?
>
> sudo uuu -b nand u-boot-with-spl.imx
>
> U-Boot SPL 2022.07-rc5-00075-gf7d0e40577-dirty (Jul 05 2022 - 06:29)
> >>SPL: board_init_r()
> spl_init
> Trying to boot from USB SDP
> SDP: initialize...
> SDP: handle requests...
> Downloading file of size 624512 to 0x877fffc0... done
> Jumping to header at 0x877fffc0
> Header Tag is not an IMX image
> Found header at 0x877fffc0
> mkimage signature not found - ih_magic = 0
> image entry point: 0x8780
>
> Does not depend on SDP_ADDRESS even because default has no sense now
> is 0. I have chosen
> TEXT_BASE - HEADERSIZE
>
I have made some change on lst and now I can flash much better
from nand standard I must
change this one
These commands will be run when use SPL and will be skipped if no spl
# if (SPL support SDPV)
# {
SDPV: delay 1000
SDPV: write -f _flash.bin -skipspl
SDPV: jump
# }
To
These commands will be run when use SPL and will be skipped if no spl
# if (SPL support SDPV)
# {
SDPV: delay 1000
SDPV: write -f _flash.bin -offset 0x11000
SDPV: jump
# }
then I need to use SDP_ADDRESS
CONFIG_SDP_LOADADDR=0x877fffc0
0x11 is the padding on mkimage
After that I can boot using
sudo uuu -v -b nand_test.lst u-boot-with-spl.imx
Michael
Michael
> Michael
>
>
> >
> > Regards,
> > Peng.
> >
> > >
> > > If I do:
> > >
> > > ./imx_usb SPL
> > > ./imx_usb u-boot-dtb.img
> > >
> > > It works
> > >
> > > U-Boot SPL 2022.07-rc5-00075-g01d253835a-dirty (Jul 04 2022 - 12:39:
> > > 11 +0200)
> > >>> SPL: board_init_r()
> > > spl_init
> > > Trying to boot from USB SDP
> > > SDP: initialize...
> > > SDP: handle requests...
> > > Downloading file of size 594824 to 0x877fffc0... done
> > > Jumping to header at 0x877fffc0
> > > Header Tag is not an IMX image
> > > Found header at 0x877fffc0
> > > image entry point: 0x8780
> > >
> > >
> > > U-Boot 2022.07-rc5-00075-g01d253835a-dirty (Jul 04 2022 - 12:39:11 +
> > > 0200)
> > >
> > > CPU: Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz)
> > > CPU: Commercial temperature grade (0C to 95C) at 37C
> > > Reset cause: POR
> > > Model: BSH SMM M2
> > > DRAM: 128 MiB
> > > Core: 29 devices, 14 uclasses, devicetree: separate
> > > NAND: 256 MiB
> > > MMC: FSL_SDHC: 1
> > > Loading Environment from NAND... *** Warning - bad CRC, using defaul
> > > t environment
> > >
> > > In:serial@21f
> > > Out: serial@21f
> > > Err: serial@21f
> > > Net: CPU Net Initialization Failed
> > > No ethernet found.
> > > Hit any key to stop autoboot
> > >
> > > If I tried with the combined image using uuu it does not work like that.
> > >
> > > U-Boot SPL 2022.07-rc5-00075-g01d253835a-dirty (Jul 04 2022 - 12:39:
> > > 11 +0200)
> > >>> SPL: board_init_r()
> > > spl_init
> > > Trying to boot from USB SDP
> > > SDP: initialize...
> > > SDP: handle requests...
> > > Downloading file of size 594824 to 0x877fffc0... done
> > > Jumping to header at 0x877fffc0
> > > Header Tag is not an IMX image
> > > Found header at 0x877fffc0
> > > image entry point: 0x8780
> > >
> > >
> > > Any idea?
> > >
> > > Michael
>
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amarulasolutions.com
> www.amarulasolutions.com
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH 1/8] arm64: dts: sdm845: Remove redundant u-boot DT properties
Hi Daniel,
Thanks for your review.
On Mon, 4 Jul 2022 at 21:28, Daniel Thompson wrote:
>
> On Mon, Jul 04, 2022 at 06:28:38PM +0530, Sumit Garg wrote:
> > U-boot specific DT properties belong to *-uboot.dtsi
>
> ... and are already included in starqltechn-uboot.dtsi (which is the
> only current consumer of sdm845.dtsi).
>
>
> Adding fuller comments, such as the above, makes things much easier to
> review: it makes clear why you consider the properties redundant rather
> then misfiled.
>
I would rather say that this change is to follow the u-boot DT
recommendation [1]. I will update the commit message accordingly. BTW,
it looks like u-boot DT properties are incorrectly specified in
starqltechn-uboot.dtsi here [2] as there aren't any subnodes for the
"gcc" node. I will correct that too.
[1]
https://u-boot.readthedocs.io/en/latest/develop/devicetree/control.html#adding-tweaks-for-u-boot
[2]
https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/starqltechn-uboot.dtsi#L19
-Sumit
>
> Daniel.
>
>
> > , so remove
> > corresponding redundant properties.
> >
> > Signed-off-by: Sumit Garg
> > ---
> > arch/arm/dts/sdm845.dtsi | 3 ---
> > 1 file changed, 3 deletions(-)
> >
> > diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
> > index 6f2fb20d68..88030156d9 100644
> > --- a/arch/arm/dts/sdm845.dtsi
> > +++ b/arch/arm/dts/sdm845.dtsi
> > @@ -18,7 +18,6 @@
> > compatible = "simple-bus";
> >
> > gcc: clock-controller@10 {
> > - u-boot,dm-pre-reloc;
> > compatible = "qcom,gcc-sdm845";
> > reg = <0x10 0x1f>;
> > #clock-cells = <1>;
> > @@ -27,7 +26,6 @@
> > };
> >
> > gpio_north: gpio_north@390 {
> > - u-boot,dm-pre-reloc;
> > #gpio-cells = <2>;
> > compatible = "qcom,sdm845-pinctrl";
> > reg = <0x390 0x40>;
> > @@ -38,7 +36,6 @@
> > };
> >
> > tlmm_north: pinctrl_north@390 {
> > - u-boot,dm-pre-reloc;
> > compatible = "qcom,tlmm-sdm845";
> > reg = <0x390 0x40>;
> > gpio-count = <150>;
> > --
> > 2.25.1
> >
[PATCH V4 49/49] tools: image: support i.MX93
From: Peng Fan
Support build i.MX93 container image with mkimage
Signed-off-by: Peng Fan
---
include/imx8image.h | 15 +++--
tools/imx8image.c | 79 +
2 files changed, 78 insertions(+), 16 deletions(-)
diff --git a/include/imx8image.h b/include/imx8image.h
index 00c614ab6cc..32064bfeeb8 100644
--- a/include/imx8image.h
+++ b/include/imx8image.h
@@ -165,6 +165,7 @@ enum imx8image_core_type {
CFG_M40,
CFG_M41,
CFG_A35,
+ CFG_A55,
CFG_A53,
CFG_A72
};
@@ -180,7 +181,9 @@ enum imx8image_fld_types {
typedef enum SOC_TYPE {
NONE = 0,
QX,
- QM
+ QM,
+ ULP,
+ IMX9
} soc_type_t;
typedef enum option_type {
@@ -201,7 +204,9 @@ typedef enum option_type {
DATA,
PARTITION,
FILEOFF,
- MSG_BLOCK
+ MSG_BLOCK,
+ SENTINEL,
+ UPOWER
} option_type_t;
typedef struct {
@@ -221,6 +226,11 @@ typedef struct {
#define CORE_CA72 5
#define CORE_SECO 6
+#define CORE_ULP_CM33 0x1
+#define CORE_ULP_CA35 0x2
+#define CORE_ULP_UPOWER0x4
+#define CORE_ULP_SENTINEL 0x6
+
#define SC_R_OTP 357U
#define SC_R_DEBUG 354U
#define SC_R_ROM_0 236U
@@ -235,6 +245,7 @@ typedef struct {
#define IMG_TYPE_DATA0x04 /* Data image type */
#define IMG_TYPE_DCD_DDR 0x05 /* DCD/DDR image type */
#define IMG_TYPE_SECO0x06 /* SECO image type */
+#define IMG_TYPE_SENTINEL 0x06 /* SENTINEL image type */
#define IMG_TYPE_PROV0x07 /* Provisioning image type */
#define IMG_TYPE_DEK 0x08 /* DEK validation type */
diff --git a/tools/imx8image.c b/tools/imx8image.c
index fa8f2274876..01e14869114 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -60,6 +60,7 @@ static table_entry_t imx8image_core_entries[] = {
{CFG_M40, "M40", "M4 core 0",},
{CFG_M41, "M41", "M4 core 1",},
{CFG_A35, "A35", "A35 core", },
+ {CFG_A55, "A55", "A55 core", },
{CFG_A53, "A53", "A53 core", },
{CFG_A72, "A72", "A72 core", },
{-1,"", "", },
@@ -117,6 +118,10 @@ static void parse_cfg_cmd(image_t *param_stack, int32_t
cmd, char *token,
soc = QX;
} else if (!strncmp(token, "IMX8QM", 6)) {
soc = QM;
+ } else if (!strncmp(token, "ULP", 3)) {
+ soc = IMX9;
+ } else if (!strncmp(token, "IMX9", 4)) {
+ soc = IMX9;
} else {
fprintf(stderr, "Unknown CMD_SOC_TYPE");
exit(EXIT_FAILURE);
@@ -187,6 +192,7 @@ static void parse_cfg_fld(image_t *param_stack, int32_t
*cmd, char *token,
param_stack[p_idx].filename = token;
break;
case CFG_A35:
+ case CFG_A55:
param_stack[p_idx].ext = CORE_CA35;
param_stack[p_idx].option =
(*cmd == CMD_DATA) ? DATA : AP;
@@ -219,6 +225,7 @@ static void parse_cfg_fld(image_t *param_stack, int32_t
*cmd, char *token,
case CFG_M41:
case CFG_A35:
case CFG_A53:
+ case CFG_A55:
case CFG_A72:
param_stack[p_idx++].entry =
(uint32_t)strtoll(token, NULL, 0);
@@ -548,6 +555,18 @@ static void set_image_array_entry(flash_header_v3_t
*container,
img->dst = 0x20C0;
img->entry = 0x2000;
break;
+ case SENTINEL:
+ if (container->num_images > 0) {
+ fprintf(stderr, "Error: SENTINEL container only allows
1 image\n");
+ return;
+ }
+
+ img->hab_flags |= IMG_TYPE_SENTINEL;
+ img->hab_flags |= CORE_ULP_SENTINEL <<
BOOT_IMG_FLAGS_CORE_SHIFT;
+ tmp_name = "SENTINEL";
+ img->dst = 0xe400; /* S400 IRAM base */
+ img->entry = 0xe400;
+ break;
case AP:
if (soc == QX && core == CORE_CA35) {
meta = IMAGE_A35_DEFAULT_META(custom_partition);
@@ -555,6 +574,8 @@ static void set_image_array_entry(flash_header_v3_t
*container,
meta = IMAGE_A53_DEFAULT_META(custom_partition);
} else if (soc == QM && core == CORE_CA72) {
meta = IMAGE_A72_DEFAULT_META(custom_partition);
+ } else if (((soc == ULP) || (soc == IMX9)) && core ==
CORE_CA35) {
+ meta = 0;
} else {
[PATCH V4 48/49] board: freescale: imx93_evk: support ethernet
From: Peng Fan
Add ethernet support
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 7 +
board/freescale/imx93_evk/imx93_evk.c | 32 +++
configs/imx93_11x11_evk_defconfig | 9 +++
3 files changed, 48 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 049eca4f3a7..f575805c7da 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -7,6 +7,7 @@
#define __ASM_ARCH_IMX9_REGS_H__
#define ARCH_MXC
+#define FEC_QUIRK_ENET_MAC
#define IOMUXC_BASE_ADDR 0x443CUL
#define CCM_BASE_ADDR 0x4445UL
@@ -39,6 +40,12 @@
#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
+#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASKGENMASK(3, 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII(0x1 << 1)
+#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN(0x1 << 0)
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
#include
diff --git a/board/freescale/imx93_evk/imx93_evk.c
b/board/freescale/imx93_evk/imx93_evk.c
index 77b92b35db4..f111b99fc2e 100644
--- a/board/freescale/imx93_evk/imx93_evk.c
+++ b/board/freescale/imx93_evk/imx93_evk.c
@@ -38,8 +38,40 @@ int board_early_init_f(void)
return 0;
}
+static int setup_fec(void)
+{
+ return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+static int setup_eqos(void)
+{
+ struct blk_ctrl_wakeupmix_regs *bctrl =
+ (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
+
+ /* set INTF as RGMII, enable RGMII TXC clock */
+ clrsetbits_le32(>eqos_gpr,
+ BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
+ BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII |
BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
+
+ return set_clk_eqos(ENET_125MHZ);
+}
+
int board_init(void)
{
+ if (CONFIG_IS_ENABLED(FEC_MXC))
+ setup_fec();
+
+ if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
+ setup_eqos();
+
return 0;
}
diff --git a/configs/imx93_11x11_evk_defconfig
b/configs/imx93_11x11_evk_defconfig
index 8a396ed1c13..1f59f7e365d 100644
--- a/configs/imx93_11x11_evk_defconfig
+++ b/configs/imx93_11x11_evk_defconfig
@@ -75,6 +75,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
@@ -89,6 +90,14 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX93=y
--
2.36.0
[PATCH V4 47/49] net: dwc_eth_qos: introduce eqos hook eqos_get_enetaddr
From: Peng Fan
i.MX has specific hook to get MAC address, so introduce a hook and move
i.MX code to its own driver
Signed-off-by: Peng Fan
---
drivers/net/dwc_eth_qos.c | 9 ++---
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_imx.c | 12 +++-
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index a4380d17d9c..c1f2391d635 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -712,10 +712,13 @@ static int eqos_write_hwaddr(struct udevice *dev)
static int eqos_read_rom_hwaddr(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ int ret;
+
+ ret = eqos->config->ops->eqos_get_enetaddr(dev);
+ if (ret < 0)
+ return ret;
-#ifdef CONFIG_ARCH_IMX8M
- imx_get_mac_from_fuse(dev_seq(dev), pdata->enetaddr);
-#endif
return !is_valid_ethaddr(pdata->enetaddr);
}
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index f470189e8d4..b35e7742634 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -240,6 +240,7 @@ struct eqos_ops {
int (*eqos_calibrate_pads)(struct udevice *dev);
int (*eqos_disable_calibration)(struct udevice *dev);
int (*eqos_set_tx_clk_speed)(struct udevice *dev);
+ int (*eqos_get_enetaddr)(struct udevice *dev);
ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
};
diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index 2d1b5104af2..42cb164ad14 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -92,6 +92,15 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
return 0;
}
+static int eqos_get_enetaddr_imx(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+
+ imx_get_mac_from_fuse(dev_seq(dev), pdata->enetaddr);
+
+ return 0;
+}
+
static struct eqos_ops eqos_imx_ops = {
.eqos_inval_desc = eqos_inval_desc_generic,
.eqos_flush_desc = eqos_flush_desc_generic,
@@ -106,7 +115,8 @@ static struct eqos_ops eqos_imx_ops = {
.eqos_calibrate_pads = eqos_null_ops,
.eqos_disable_calibration = eqos_null_ops,
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
+ .eqos_get_enetaddr = eqos_get_enetaddr_imx,
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx,
};
struct eqos_config __maybe_unused eqos_imx_config = {
--
2.36.0
[PATCH V4 46/49] net: eqos: add function to get phy node and address
From: Ye Li
Since new atheros PHY driver needs to access its PHY node through
phy device, we have to assign the phy node in ethernet controller
driver. Otherwise the PHY driver will fail to get some nodes
and properties.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
drivers/net/dwc_eth_qos.c | 23 ---
drivers/net/dwc_eth_qos.h | 1 +
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 1f24f5cb0cf..a4380d17d9c 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -719,6 +719,24 @@ static int eqos_read_rom_hwaddr(struct udevice *dev)
return !is_valid_ethaddr(pdata->enetaddr);
}
+static int eqos_get_phy_addr(struct eqos_priv *priv, struct udevice *dev)
+{
+ struct ofnode_phandle_args phandle_args;
+ int reg;
+
+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ _args)) {
+ debug("Failed to find phy-handle");
+ return -ENODEV;
+ }
+
+ priv->phy_of_node = phandle_args.node;
+
+ reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
+
+ return reg;
+}
+
static int eqos_start(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -767,9 +785,7 @@ static int eqos_start(struct udevice *dev)
*/
if (!eqos->phy) {
int addr = -1;
-#ifdef CONFIG_DM_ETH_PHY
- addr = eth_phy_get_addr(dev);
-#endif
+ addr = eqos_get_phy_addr(eqos, dev);
#ifdef DWC_NET_PHYADDR
addr = DWC_NET_PHYADDR;
#endif
@@ -788,6 +804,7 @@ static int eqos_start(struct udevice *dev)
}
}
+ eqos->phy->node = eqos->phy_of_node;
ret = phy_config(eqos->phy);
if (ret < 0) {
pr_err("phy_config() failed: %d", ret);
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index ce90e1f1ce1..f470189e8d4 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -261,6 +261,7 @@ struct eqos_priv {
struct clk clk_slave_bus;
struct mii_dev *mii;
struct phy_device *phy;
+ ofnode phy_of_node;
u32 max_speed;
void *descs;
int tx_desc_idx, rx_desc_idx;
--
2.36.0
[PATCH V4 45/49] net: dwc_eth_qos: move i.MX code out
From: Peng Fan
Move i.MX code to a standalone file to make it easy for adding new
platform support
Reviewed-by: Ramon Fried
Signed-off-by: Peng Fan
---
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 92 --
drivers/net/dwc_eth_qos.h | 2 +
drivers/net/dwc_eth_qos_imx.c | 121 ++
4 files changed, 124 insertions(+), 92 deletions(-)
create mode 100644 drivers/net/dwc_eth_qos_imx.c
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 69fb3bbbf7c..9536af11946 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index b69a9feb824..1f24f5cb0cf 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -506,20 +506,6 @@ static ulong eqos_get_tick_clk_rate_stm32(struct udevice
*dev)
#endif
}
-__weak u32 imx_get_eqos_csr_clk(void)
-{
- return 100 * 100;
-}
-__weak int imx_eqos_txclk_set_rate(unsigned long rate)
-{
- return 0;
-}
-
-static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
-{
- return imx_get_eqos_csr_clk();
-}
-
static int eqos_set_full_duplex(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -616,38 +602,6 @@ static int eqos_set_tx_clk_speed_tegra186(struct udevice
*dev)
return 0;
}
-static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
-{
- struct eqos_priv *eqos = dev_get_priv(dev);
- ulong rate;
- int ret;
-
- debug("%s(dev=%p):\n", __func__, dev);
-
- switch (eqos->phy->speed) {
- case SPEED_1000:
- rate = 125 * 1000 * 1000;
- break;
- case SPEED_100:
- rate = 25 * 1000 * 1000;
- break;
- case SPEED_10:
- rate = 2.5 * 1000 * 1000;
- break;
- default:
- pr_err("invalid speed %d", eqos->phy->speed);
- return -EINVAL;
- }
-
- ret = imx_eqos_txclk_set_rate(rate);
- if (ret < 0) {
- pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
- return ret;
- }
-
- return 0;
-}
-
static int eqos_adjust_link(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1468,24 +1422,6 @@ static phy_interface_t eqos_get_interface_tegra186(const
struct udevice *dev)
return PHY_INTERFACE_MODE_MII;
}
-static int eqos_probe_resources_imx(struct udevice *dev)
-{
- struct eqos_priv *eqos = dev_get_priv(dev);
- phy_interface_t interface;
-
- debug("%s(dev=%p):\n", __func__, dev);
-
- interface = eqos->config->interface(dev);
-
- if (interface == PHY_INTERFACE_MODE_NA) {
- pr_err("Invalid PHY interface\n");
- return -EINVAL;
- }
-
- debug("%s: OK\n", __func__);
- return 0;
-}
-
static int eqos_remove_resources_tegra186(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1695,34 +1631,6 @@ static const struct eqos_config __maybe_unused
eqos_stm32_config = {
.ops = _stm32_ops
};
-static struct eqos_ops eqos_imx_ops = {
- .eqos_inval_desc = eqos_inval_desc_generic,
- .eqos_flush_desc = eqos_flush_desc_generic,
- .eqos_inval_buffer = eqos_inval_buffer_generic,
- .eqos_flush_buffer = eqos_flush_buffer_generic,
- .eqos_probe_resources = eqos_probe_resources_imx,
- .eqos_remove_resources = eqos_null_ops,
- .eqos_stop_resets = eqos_null_ops,
- .eqos_start_resets = eqos_null_ops,
- .eqos_stop_clks = eqos_null_ops,
- .eqos_start_clks = eqos_null_ops,
- .eqos_calibrate_pads = eqos_null_ops,
- .eqos_disable_calibration = eqos_null_ops,
- .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
-};
-
-struct eqos_config __maybe_unused eqos_imx_config = {
- .reg_access_always_ok = false,
- .mdio_wait = 10,
- .swr_wait = 50,
- .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
- .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
- .axi_bus_width = EQOS_AXI_WIDTH_64,
- .interface = dev_read_phy_mode,
- .ops = _imx_ops
-};
-
static const struct udevice_id eqos_ids[] = {
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186)
{
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index 68b367b068a..ce90e1f1ce1 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -278,3 +278,5 @@ void eqos_flush_desc_generic(void *desc);
void
[PATCH V4 44/49] net: dwc_eth_qos: public some functions
From: Peng Fan
Move macros and structures to header file and make some functions
public, so that could used by other files, this is to
prepare split platform specific config to one file.
Signed-off-by: Peng Fan
---
drivers/net/dwc_eth_qos.c | 280 +-
drivers/net/dwc_eth_qos.h | 280 ++
2 files changed, 287 insertions(+), 273 deletions(-)
create mode 100644 drivers/net/dwc_eth_qos.h
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 6048d56ff8c..b69a9feb824 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -51,275 +51,9 @@
#include
#include
#endif
-#include
#include
-/* Core registers */
-
-#define EQOS_MAC_REGS_BASE 0x000
-struct eqos_mac_regs {
- uint32_t configuration; /* 0x000 */
- uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
- uint32_t q0_tx_flow_ctrl; /* 0x070 */
- uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
- uint32_t rx_flow_ctrl; /* 0x090 */
- uint32_t unused_094;/* 0x094 */
- uint32_t txq_prty_map0; /* 0x098 */
- uint32_t unused_09c;/* 0x09c */
- uint32_t rxq_ctrl0; /* 0x0a0 */
- uint32_t unused_0a4;/* 0x0a4 */
- uint32_t rxq_ctrl2; /* 0x0a8 */
- uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
- uint32_t us_tic_counter;/* 0x0dc */
- uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
- uint32_t hw_feature0; /* 0x11c */
- uint32_t hw_feature1; /* 0x120 */
- uint32_t hw_feature2; /* 0x124 */
- uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
- uint32_t mdio_address; /* 0x200 */
- uint32_t mdio_data; /* 0x204 */
- uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
- uint32_t address0_high; /* 0x300 */
- uint32_t address0_low; /* 0x304 */
-};
-
-#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
-#define EQOS_MAC_CONFIGURATION_CST BIT(21)
-#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
-#define EQOS_MAC_CONFIGURATION_WD BIT(19)
-#define EQOS_MAC_CONFIGURATION_JD BIT(17)
-#define EQOS_MAC_CONFIGURATION_JE BIT(16)
-#define EQOS_MAC_CONFIGURATION_PS BIT(15)
-#define EQOS_MAC_CONFIGURATION_FES BIT(14)
-#define EQOS_MAC_CONFIGURATION_DM BIT(13)
-#define EQOS_MAC_CONFIGURATION_LM BIT(12)
-#define EQOS_MAC_CONFIGURATION_TE BIT(1)
-#define EQOS_MAC_CONFIGURATION_RE BIT(0)
-
-#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
-#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0x
-#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
-
-#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
-
-#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
-#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
-
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT0
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
-
-#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
-#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
-
-#define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
-#define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
-#define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
-#define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
-
-#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
-#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
-#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
-#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
-
-#define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
-#define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
-
-#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
-#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT16
-#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
-#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
-#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
-#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
-#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT2
-#define EQOS_MAC_MDIO_ADDRESS_GOC_READ
[PATCH V4 43/49] net: dwc_eth_qos: fix build break when CLK not enabled
From: Peng Fan
When CONFIG_CLK is not enabled, there will be buil break:
"error: ‘eqos’ undeclared (first use in this function)"
Take eqos definition out the CONFIG_CLK ifdef.
Signed-off-by: Peng Fan
---
drivers/net/dwc_eth_qos.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9d255cf95ff..6048d56ff8c 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1774,11 +1774,11 @@ static int eqos_remove_resources_tegra186(struct
udevice *dev)
static int eqos_remove_resources_stm32(struct udevice *dev)
{
-#ifdef CONFIG_CLK
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
+#ifdef CONFIG_CLK
clk_free(>clk_tx);
clk_free(>clk_rx);
clk_free(>clk_master_bus);
--
2.36.0
[PATCH V4 40/49] imx: imx93_evk: Add basic board support
From: Peng Fan
Add basic board codes and defconfig for i.MX93 11x11 EVK board.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/dts/Makefile |3 +
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 157 +++
arch/arm/dts/imx93-11x11-evk.dts | 527 +++
arch/arm/mach-imx/imx9/Kconfig | 12 +
board/freescale/common/Makefile|2 +-
board/freescale/imx93_evk/Kconfig | 21 +
board/freescale/imx93_evk/MAINTAINERS |6 +
board/freescale/imx93_evk/Makefile | 12 +
board/freescale/imx93_evk/imx93_evk.c | 58 +
board/freescale/imx93_evk/lpddr4x_timing.c | 1486
board/freescale/imx93_evk/spl.c| 126 ++
configs/imx93_11x11_evk_defconfig | 108 ++
include/configs/imx93_evk.h| 146 ++
13 files changed, 2663 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx93-11x11-evk.dts
create mode 100644 board/freescale/imx93_evk/Kconfig
create mode 100644 board/freescale/imx93_evk/MAINTAINERS
create mode 100644 board/freescale/imx93_evk/Makefile
create mode 100644 board/freescale/imx93_evk/imx93_evk.c
create mode 100644 board/freescale/imx93_evk/lpddr4x_timing.c
create mode 100644 board/freescale/imx93_evk/spl.c
create mode 100644 configs/imx93_11x11_evk_defconfig
create mode 100644 include/configs/imx93_evk.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 87b210dbb01..f379ee9dd22 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -968,6 +968,9 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb
+dtb-$(CONFIG_ARCH_IMX9) += \
+ imx93-11x11-evk.dtb
+
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
new file mode 100644
index 000..6f02b389893
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <>;
+ u-boot,dm-spl;
+ };
+
+ aliases {
+ usbgadget0 =
+ usbgadget1 =
+ };
+
+ usbg1: usbg1 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <>;
+ status = "okay";
+ };
+
+ usbg2: usbg2 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <>;
+ status = "okay";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <2>;
+ u-boot,dm-spl;
+};
+
+_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+_uart1 {
+ u-boot,dm-spl;
+};
+
+_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+_usdhc2 {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@4400/i2c@4435/pmic@25} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@4400/i2c@4435/pmic@25/regulators} {
+ u-boot,dm-spl;
+};
+
+_lpi2c2 {
+ u-boot,dm-spl;
+};
+
+ {
+ phy-reset-gpios = < 16 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
+};
+
+ {
+ compatible = "fsl,imx-eqos";
+};
+
+ {
+ reset-gpios = < 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <10>;
+};
+
+ {
+ status = "okay";
+ extcon = <>;
+};
+
+ {
+ status = "okay";
+ extcon = <_2>;
+};
+
+ {
+ u-boot,dm-spl;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts
new file mode 100644
index 000..b3a5a3d71e2
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk.dts
@@ -0,0 +1,527 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx93.dtsi"
+
+/{
+ chosen {
+ stdout-path =
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+
[PATCH V4 42/49] net: fec_mxc: support i.MX93
From: Peng Fan
Support i.MX93 in fec_mxc driver
Reviewed-by: Ramon Fried
Signed-off-by: Peng Fan
---
drivers/net/Kconfig | 2 +-
drivers/net/fec_mxc.c | 4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 56f9416a48d..b5315b18cca 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -344,7 +344,7 @@ config FEC_MXC_MDIO_BASE
config FEC_MXC
bool "FEC Ethernet controller"
- depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP ||
VF610
+ depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP ||
IMX93 || VF610
help
This driver supports the 10/100 Fast Ethernet controller for
NXP i.MX processors.
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index a623a5c45e4..8bc2b46d403 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -598,7 +598,8 @@ static int fecmxc_init(struct udevice *dev)
writel(0x, >eth->gaddr2);
/* Do not access reserved register */
- if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() &&
!is_imx8ulp()) {
+ if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() &&
!is_imx8ulp() &&
+ !is_imx93()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
@@ -1357,6 +1358,7 @@ static const struct udevice_id fecmxc_ids[] = {
{ .compatible = "fsl,imx53-fec" },
{ .compatible = "fsl,imx7d-fec" },
{ .compatible = "fsl,mvf600-fec" },
+ { .compatible = "fsl,imx93-fec" },
{ }
};
--
2.36.0
[PATCH V4 41/49] imx: imx93_evk: Set ARM clock to 1.7Ghz
From: Peng Fan
Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC
to Overdrive voltage 0.9V
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/clock.h | 4 +++-
arch/arm/mach-imx/imx9/clock.c | 9 +
board/freescale/imx93_evk/spl.c| 3 +++
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/clock.h
b/arch/arm/include/asm/arch-imx9/clock.h
index d96f126a1d1..336d8613181 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -217,6 +217,8 @@ void dram_pll_init(ulong pll_val);
void dram_enable_bypass(ulong clk_val);
void dram_disable_bypass(void);
+int configure_intpll(enum ccm_clk_src pll, u32 freq);
+
int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable);
@@ -238,5 +240,5 @@ int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool
user_mode, bool lock
void enable_usboh3_clk(unsigned char enable);
int set_clk_enet(enum enet_freq type);
int set_clk_eqos(enum enet_freq type);
-
+void set_arm_clk(ulong freq);
#endif
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 5d2bc0d2f8f..8240afc6172 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -665,6 +665,15 @@ void dram_disable_bypass(void)
/* Switch from DRAM clock root from CCM to PLL */
ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL);
}
+
+void set_arm_clk(ulong freq)
+{
+ /* Increase ARM clock to 1.7Ghz */
+ ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM);
+ configure_intpll(ARM_PLL_CLK, 17);
+ ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL);
+}
+
#endif
int clock_init(void)
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index ca33f943424..38cfbac6ea6 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -108,6 +108,9 @@ void board_init_f(ulong dummy)
}
power_init_board();
+ /* 1.7GHz */
+ set_arm_clk(17);
+
/* Init power of mix */
soc_power_init();
--
2.36.0
[PATCH V4 39/49] arm: dts: Add i.MX93 SoC DTSi file
From: Peng Fan
Add the DTSi file and DT header files for i.MX93 SoC
Signed-off-by: Ye Li
Signed-off-by: Alice Guo
Signed-off-by: Peng Fan
---
arch/arm/dts/imx93.dtsi | 688
include/dt-bindings/clock/imx93-clock.h | 203 +++
include/dt-bindings/power/imx93-power.h | 12 +
3 files changed, 903 insertions(+)
create mode 100644 arch/arm/dts/imx93.dtsi
create mode 100644 include/dt-bindings/clock/imx93-clock.h
create mode 100644 include/dt-bindings/power/imx93-power.h
diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi
new file mode 100644
index 000..28026ccecc8
--- /dev/null
+++ b/arch/arm/dts/imx93.dtsi
@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "imx93-pinfunc.h"
+
+/ {
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ gpio0 =
+ gpio1 =
+ gpio2 =
+ gpio3 =
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ ethernet0 =
+ ethernet1 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ serial4 =
+ serial5 =
+ serial6 =
+ serial7 =
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ i2c4 =
+ i2c5 =
+ usb0 =
+ usb1 =
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A55_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ };
+
+ A55_1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ };
+
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "osc_24m";
+ };
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13300>;
+ clock-output-names = "clk_ext1";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <2400>;
+ arm,no-tick-in-suspend;
+ interrupt-parent = <>;
+ };
+
+ gic: interrupt-controller@4800 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x4800 0 0x1>,
+ <0 0x4804 0 0xc>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = ;
+ interrupt-parent = <>;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x8000>,
+<0x2800 0x0 0x2800 0x1000>;
+
+ aips1: bus@4400 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x4400 0x80>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mu1: mailbox@4423 {
+ compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
+ reg = <0x4423 0x1>;
+ interrupts = ;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ anomix_ns_gpr: blk-ctrl-anomix@4242 {
+ compatible = "syscon";
+ reg = <0x4421 0x1000>;
+ };
+
+ system_counter: timer@4429 {
+ compatible = "nxp,sysctr-timer";
+
[PATCH V4 38/49] ddr: imx9: enable Performance monitor counter
From: Ye Li
Add Kconfig for enabling reference events counter in DDRC performance
monitor by default
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
drivers/ddr/imx/imx9/Kconfig| 6 ++
drivers/ddr/imx/imx9/ddr_init.c | 4
2 files changed, 10 insertions(+)
diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig
index a16ddc65e01..123ad173cfc 100644
--- a/drivers/ddr/imx/imx9/Kconfig
+++ b/drivers/ddr/imx/imx9/Kconfig
@@ -11,6 +11,12 @@ config IMX9_LPDDR4X
help
Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC.
+config IMX9_DRAM_PM_COUNTER
+ bool "imx9 DDRC performance monitor counter"
+ default y
+ help
+ Enable DDR controller performance monitor counter for reference
events.
+
config SAVED_DRAM_TIMING_BASE
hex "Define the base address for saved dram timing"
help
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index 16eac65105f..8b8ec7f8de3 100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -112,6 +112,10 @@ int ddr_init(struct dram_timing_info *dram_timing)
ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
debug("DDRINFO: ddrc config done\n");
+#ifdef CONFIG_IMX9_DRAM_PM_COUNTER
+ writel(0x20, REG_DDR_DEBUG_19);
+#endif
+
check_dfi_init_complete();
regval = readl(REG_DDR_SDRAM_CFG);
--
2.36.0
[PATCH V4 37/49] ddr: imx: Add i.MX9 DDR controller driver
From: Ye Li
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common
directory under imx, then use dedicated ddr controller driver for each
iMX9 and iMX8M.
The DDRPHY registers are space compressed, so it needs conversion to
access the DDRPHY address. Introduce a common PHY address remap function
for both iMX8M and iMX9 for all PHY registers accessing.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/ddr.h | 6 +-
arch/arm/include/asm/arch-imx9/ddr.h | 126 +
drivers/Makefile | 1 +
drivers/ddr/imx/Kconfig | 2 +
drivers/ddr/imx/imx8m/Kconfig | 1 +
drivers/ddr/imx/imx8m/Makefile| 3 +-
drivers/ddr/imx/imx8m/ddr_init.c | 219
drivers/ddr/imx/imx9/Kconfig | 21 +
drivers/ddr/imx/imx9/Makefile | 10 +
drivers/ddr/imx/imx9/ddr_init.c | 485 ++
drivers/ddr/imx/phy/Kconfig | 4 +
drivers/ddr/imx/phy/Makefile | 9 +
drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c | 0
drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c | 1 -
drivers/ddr/imx/phy/ddrphy_utils.c| 169 ++
drivers/ddr/imx/{imx8m => phy}/helper.c | 45 +-
16 files changed, 1077 insertions(+), 25 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx9/ddr.h
create mode 100644 drivers/ddr/imx/imx9/Kconfig
create mode 100644 drivers/ddr/imx/imx9/Makefile
create mode 100644 drivers/ddr/imx/imx9/ddr_init.c
create mode 100644 drivers/ddr/imx/phy/Kconfig
create mode 100644 drivers/ddr/imx/phy/Makefile
rename drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c (100%)
rename drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c (98%)
create mode 100644 drivers/ddr/imx/phy/ddrphy_utils.c
rename drivers/ddr/imx/{imx8m => phy}/helper.c (79%)
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h
b/arch/arm/include/asm/arch-imx8m/ddr.h
index 2ce8a8f2d41..2f76e7d69b9 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -725,6 +725,8 @@ void update_umctl2_rank_space_setting(unsigned int
pstat_num);
void get_trained_CDD(unsigned int fsp);
unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr);
+ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr);
+
static inline void reg32_write(unsigned long addr, u32 val)
{
writel(val, addr);
@@ -741,9 +743,9 @@ static inline void reg32setbit(unsigned long addr, u32 bit)
}
#define dwc_ddrphy_apb_wr(addr, data) \
- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr),
data)
#define dwc_ddrphy_apb_rd(addr) \
- reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))
+ reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
extern struct dram_cfg_param ddrphy_trained_csr[];
extern uint32_t ddrphy_trained_csr_num;
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h
b/arch/arm/include/asm/arch-imx9/ddr.h
new file mode 100644
index 000..62e6f7dda53
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8M_DDR_H
+#define __ASM_ARCH_IMX8M_DDR_H
+
+#include
+#include
+
+#define DDR_CTL_BASE 0x4E30
+#define DDR_PHY_BASE 0x4E10
+#define DDRMIX_BLK_CTRL_BASE 0x4E01
+
+#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24)
+#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110)
+#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)
+
+#define SRC_BASE_ADDR (0x4446)
+#define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400)
+#define REG_SRC_DPHY_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x20)
+#define REG_SRC_DPHY_SINGLE_RESET_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x24)
+
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (DDR_PHY_BASE + ((X) * 0x200))
+#define DDRPHY_MEM(X) (DDR_PHY_BASE + ((X) * 0x200) +
0x5)
+
+/* PHY State */
+enum pstate {
+ PS0,
+ PS1,
+ PS2,
+ PS3,
+};
+
+enum msg_response {
+ TRAIN_SUCCESS = 0x7,
+ TRAIN_STREAM_START = 0x8,
+ TRAIN_FAIL = 0xff,
+};
+
+/* user data type */
+enum fw_type {
+ FW_1D_IMAGE,
+ FW_2D_IMAGE,
+};
+
+struct dram_cfg_param {
+ unsigned int reg;
+ unsigned int val;
+};
+
+struct dram_fsp_msg {
+ unsigned int drate;
+ enum fw_type fw_type;
+ struct dram_cfg_param *fsp_cfg;
+ unsigned int fsp_cfg_num;
+};
+
+struct dram_timing_info {
+ /* umctl2 config */
+ struct dram_cfg_param *ddrc_cfg;
+ unsigned int ddrc_cfg_num;
+ /* ddrphy config */
+ struct dram_cfg_param *ddrphy_cfg;
+ unsigned int ddrphy_cfg_num;
+ /* ddr fsp
[PATCH V4 36/49] imx: imx9: clock: Add DDR clock support
From: Ye Li
Implement the DDR driver clock interfaces for set DDR rate and
bypass DDR PLL
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/clock.h | 3 ++
arch/arm/mach-imx/imx9/clock.c | 41 ++
2 files changed, 44 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/clock.h
b/arch/arm/include/asm/arch-imx9/clock.h
index fcf04d66f05..d96f126a1d1 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -213,6 +213,9 @@ void init_clk_usdhc(u32 index);
int enable_i2c_clk(unsigned char enable, u32 i2c_num);
u32 imx_get_i2cclk(u32 i2c_num);
u32 mxc_get_clock(enum mxc_clock clk);
+void dram_pll_init(ulong pll_val);
+void dram_enable_bypass(ulong clk_val);
+void dram_disable_bypass(void);
int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 55cbb40f328..5d2bc0d2f8f 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -626,6 +626,47 @@ void enable_usboh3_clk(unsigned char enable)
}
}
+#ifdef CONFIG_SPL_BUILD
+void dram_pll_init(ulong pll_val)
+{
+ configure_fracpll(DRAM_PLL_CLK, pll_val);
+}
+
+void dram_enable_bypass(ulong clk_val)
+{
+ switch (clk_val) {
+ case MHZ(400):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2);
+ break;
+ case MHZ(333):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD0, 3);
+ break;
+ case MHZ(200):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 4);
+ break;
+ case MHZ(100):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 8);
+ break;
+ default:
+ printf("No matched freq table %lu\n", clk_val);
+ return;
+ }
+
+ /* Set DRAM APB to 133Mhz */
+ ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* Switch from DRAM clock root from PLL to CCM */
+ ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_CCM);
+}
+
+void dram_disable_bypass(void)
+{
+ /* Set DRAM APB to 133Mhz */
+ ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* Switch from DRAM clock root from CCM to PLL */
+ ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL);
+}
+#endif
+
int clock_init(void)
{
int i;
--
2.36.0
[PATCH V4 35/49] imx: imx9: Support multiple env storages at runtime
From: Ye Li
Select env storages according to boot device at runtime
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index ca88271564c..797d7a802ba 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -288,6 +288,40 @@ int timer_init(void)
return 0;
}
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_device dev = get_boot_device();
+ enum env_location env_loc = ENVL_UNKNOWN;
+
+ if (prio)
+ return env_loc;
+
+ switch (dev) {
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+ case QSPI_BOOT:
+ env_loc = ENVL_SPI_FLASH;
+ break;
+#endif
+#if defined(CONFIG_ENV_IS_IN_MMC)
+ case SD1_BOOT:
+ case SD2_BOOT:
+ case SD3_BOOT:
+ case MMC1_BOOT:
+ case MMC2_BOOT:
+ case MMC3_BOOT:
+ env_loc = ENVL_MMC;
+ break;
+#endif
+ default:
+#if defined(CONFIG_ENV_IS_NOWHERE)
+ env_loc = ENVL_NOWHERE;
+#endif
+ break;
+ }
+
+ return env_loc;
+}
+
static int mix_power_init(enum mix_power_domain pd)
{
enum src_mix_slice_id mix_id;
--
2.36.0
[PATCH V4 34/49] imx: imx9: Support booting m33 from Acore
From: Peng Fan
Add bootaux command to support on-demand booting M33 from u-boot.
It kicks M33 via ATF by "bootaux 0x201e 0"
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/Makefile | 4 +
arch/arm/mach-imx/imx9/imx_bootaux.c | 133 +++
arch/arm/mach-imx/imx9/soc.c | 10 +-
include/imx_sip.h| 1 +
4 files changed, 147 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-imx/imx9/imx_bootaux.c
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 41a22500c95..6d038a60c67 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -5,3 +5,7 @@
obj-y += lowlevel_init.o
obj-y += soc.o clock.o clock_root.o trdc.o
obj-$(CONFIG_AHAB_BOOT) += ahab.o
+
+#ifndef CONFIG_SPL_BUILD
+obj-y += imx_bootaux.o
+#endif
diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c
b/arch/arm/mach-imx/imx9/imx_bootaux.c
new file mode 100644
index 000..3b6662aeb81
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/imx_bootaux.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
+ 0, 0, 0, 0, );
+
+ return res.a0;
+}
+
+int arch_auxiliary_core_down(u32 core_id)
+{
+ struct arm_smccc_res res;
+
+ printf("## Stopping auxiliary core\n");
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STOP, 0, 0,
+ 0, 0, 0, 0, );
+
+ return 0;
+}
+
+int arch_auxiliary_core_up(u32 core_id, ulong addr)
+{
+ struct arm_smccc_res res;
+ u32 stack, pc;
+
+ if (!addr)
+ return -EINVAL;
+
+ stack = *(u32 *)addr;
+ pc = *(u32 *)(addr + 4);
+
+ printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n",
stack, pc);
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0,
+ 0, 0, 0, 0, );
+
+ return 0;
+}
+
+/*
+ * To i.MX6SX and i.MX7D, the image supported by bootaux needs
+ * the reset vector at the head for the image, with SP and PC
+ * as the first two words.
+ *
+ * Per the cortex-M reference manual, the reset vector of M4/M7 needs
+ * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses
+ * of that vector. So to boot M4/M7, the A core must build the M4/M7's reset
+ * vector with getting the PC and SP from image and filling them to
+ * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself.
+ * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for
+ * accessing the M4/M7 TCMUL/IDTCM.
+ */
+static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong addr;
+ int ret, up;
+ u32 core = 0;
+ u32 stop = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (argc > 2)
+ core = simple_strtoul(argv[2], NULL, 10);
+
+ if (argc > 3)
+ stop = simple_strtoul(argv[3], NULL, 10);
+
+ up = arch_auxiliary_core_check_up(core);
+ if (up) {
+ printf("## Auxiliary core is already up\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ if (!addr)
+ return CMD_RET_FAILURE;
+
+ ret = arch_auxiliary_core_up(core, addr);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_stopaux(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret, up;
+
+ up = arch_auxiliary_core_check_up(0);
+ if (!up) {
+ printf("## Auxiliary core is already down\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ ret = arch_auxiliary_core_down(0);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ stopaux, CONFIG_SYS_MAXARGS, 1, do_stopaux,
+ "Stop auxiliary core",
+ " []\n"
+ " - start auxiliary core [] (default 0),\n"
+ " at address \n"
+);
+
+U_BOOT_CMD(
+ bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
+ "Start auxiliary core",
+ " []\n"
+ " - start auxiliary core [] (default 0),\n"
+ " at address \n"
+);
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 2a29454d1eb..ca88271564c 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -131,6 +131,14 @@ static struct mm_region imx93_mem_map[] = {
.size = 0x10UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* TCM */
+ .virt = 0x201cUL,
+ .phys = 0x201cUL,
+
[PATCH V4 33/49] imx: imx9: Add M33 release prepare function
From: Peng Fan
To support on-demand booting M33 image from A core. SPL needs
to follow M33 kick up sequence to release M33 firstly,
then set M33 CPUWAIT signal. ATF will clear CPUWAIT to kick
M33 to run.
The prepare function also works around the M33 TCM ECC issue by
clean the TCM. Also enable sentinel handshake and WDOG1 clock
for M33 stop and reset.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/sys_proto.h | 2 +
arch/arm/mach-imx/imx9/soc.c | 51 ++
2 files changed, 53 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h
b/arch/arm/include/asm/arch-imx9/sys_proto.h
index 5ae7a043398..ba97f92f5ae 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -9,4 +9,6 @@
#include
void soc_power_init(void);
+bool m33_is_rom_kicked(void);
+int m33_prepare(void);
#endif
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 68f3ddd4287..2a29454d1eb 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -378,3 +379,53 @@ void soc_power_init(void)
disable_isolation();
}
+
+static bool m33_is_rom_kicked(void)
+{
+ struct blk_ctrl_s_aonmix_regs *s_regs =
+ (struct blk_ctrl_s_aonmix_regs
*)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+
+ if (!(readl(_regs->m33_cfg) & BIT(2)))
+ return true;
+
+ return false;
+}
+
+int m33_prepare(void)
+{
+ struct src_mix_slice_regs *mix_regs =
+ (struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400
* (SRC_MIX_CM33 + 1));
+ struct src_general_regs *global_regs =
+ (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
+ struct blk_ctrl_s_aonmix_regs *s_regs =
+ (struct blk_ctrl_s_aonmix_regs
*)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+ u32 val;
+
+ if (m33_is_rom_kicked())
+ return -EPERM;
+
+ /* Release reset of M33 */
+ setbits_le32(_regs->scr, BIT(0));
+
+ /* Check the reset released in M33 MIX func stat */
+ val = readl(_regs->func_stat);
+ while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT))
+ val = readl(_regs->func_stat);
+
+ /* Release Sentinel TROUT */
+ ahab_release_m33_trout();
+
+ /* Mask WDOG1 IRQ from A55, we use it for M33 reset */
+ setbits_le32(_regs->ca55_irq_mask[1], BIT(6));
+
+ /* Turn on WDOG1 clock */
+ ccm_lpcg_on(CCGR_WDG1, 1);
+
+ /* Set sentinel LP handshake for M33 reset */
+ setbits_le32(_regs->lp_handshake[0], BIT(6));
+
+ /* Clear M33 TCM for ECC */
+ memset((void *)(ulong)0x201e, 0, 0x4);
+
+ return 0;
+}
--
2.36.0
[PATCH V4 32/49] imx: imx9: Add MIX power init
From: Peng Fan
Add power init of MEDIAMIX, MLMIX and DDRMIX. And clear isolation
of MIPI DSI/CSI, USBPHY after the power up.
SPL should call the power init in its boot sequence before accessing
above three MIX and USB.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 173 +
arch/arm/include/asm/arch-imx9/sys_proto.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 101
3 files changed, 275 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index fa6951ebbe8..049eca4f3a7 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -21,6 +21,24 @@
#define FSB_BASE_ADDR 0x4751UL
+#define ANATOP_BASE_ADDR0x4448UL
+
+#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x4242
+#define BLK_CTRL_S_ANOMIX_BASE_ADDR 0x444f
+
+#define SRC_IPS_BASE_ADDR (0x4446)
+#define SRC_GLOBAL_RBASE (SRC_IPS_BASE_ADDR + 0x)
+
+#define SRC_DDR_RBASE (SRC_IPS_BASE_ADDR + 0x1000)
+#define SRC_ML_RBASE (SRC_IPS_BASE_ADDR + 0x1800)
+#define SRC_MEDIA_RBASE(SRC_IPS_BASE_ADDR + 0x2400)
+#define SRC_M33P_RBASE (SRC_IPS_BASE_ADDR + 0x2800)
+
+#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0)
+#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2)
+#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
+#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
#include
@@ -49,6 +67,161 @@ struct mu_type {
u32 reserved5[14];
u32 mu_attr;
};
+
+enum mix_power_domain {
+ MIX_PD_MEDIAMIX,
+ MIX_PD_MLMIX,
+ MIX_PD_DDRMIX,
+};
+
+enum src_mix_slice_id {
+ SRC_MIX_EDGELOCK = 0,
+ SRC_MIX_AONMIX = 1,
+ SRC_MIX_WAKEUPMIX = 2,
+ SRC_MIX_DDRMIX = 3,
+ SRC_MIX_DDRPHY = 4,
+ SRC_MIX_ML = 5,
+ SRC_MIX_NIC = 6,
+ SRC_MIX_HSIO = 7,
+ SRC_MIX_MEDIA = 8,
+ SRC_MIX_CM33 = 9,
+ SRC_MIX_CA55C0 = 10,
+ SRC_MIX_CA55C1 = 11,
+ SRC_MIX_CA55CLUSTER = 12,
+};
+
+enum src_mem_slice_id {
+ SRC_MEM_AONMIX = 0,
+ SRC_MEM_WAKEUPMIX = 1,
+ SRC_MEM_DDRMIX = 2,
+ SRC_MEM_DDRPHY = 3,
+ SRC_MEM_ML = 4,
+ SRC_MEM_NIC = 5,
+ SRC_MEM_OCRAM = 6,
+ SRC_MEM_HSIO = 7,
+ SRC_MEM_MEDIA = 8,
+ SRC_MEM_CA55C0 = 9,
+ SRC_MEM_CA55C1 = 10,
+ SRC_MEM_CA55CLUSTER = 11,
+ SRC_MEM_L3 = 12,
+};
+
+struct blk_ctrl_s_aonmix_regs {
+ u32 cm33_irq_mask[7];
+ u32 initnsvtor;
+ u32 reserved1[8];
+ u32 ca55_irq_mask[7];
+ u32 initsvtor;
+ u32 m33_cfg;
+ u32 reserved2[11];
+ u32 axbs_aon_ctrl;
+ u32 reserved3[27];
+ u32 dap_access_stkybit;
+ u32 reserved4[3];
+ u32 lp_handshake[2];
+ u32 ca55_cpuwait;
+ u32 ca55_rvbaraddr0_l;
+ u32 ca55_rvbaraddr0_h;
+ u32 ca55_rvbaraddr1_l;
+ u32 ca55_rvbaraddr1_h;
+ u32 s401_irq_mask;
+ u32 s401_reset_req_mask;
+ u32 s401_halt_st;
+ u32 ca55_mode;
+ u32 nmi_mask;
+ u32 nmi_clr;
+ u32 wdog_any_mask;
+ u32 s4v1_ipi_noclk_ref1;
+};
+
+struct blk_ctrl_wakeupmix_regs {
+ u32 upper_addr;
+ u32 ipg_debug_cm33;
+ u32 reserved[2];
+ u32 qch_dis;
+ u32 ssi;
+ u32 reserved1[1];
+ u32 dexsc_err;
+ u32 mqs_setting;
+ u32 sai_clk_sel;
+ u32 eqos_gpr;
+ u32 enet_clk_sel;
+ u32 reserved2[1];
+ u32 volt_detect;
+ u32 i3c2_wakeup;
+ u32 ipg_debug_ca55c0;
+ u32 ipg_debug_ca55c1;
+ u32 axi_attr_cfg;
+ u32 i3c2_sda_irq;
+};
+
+struct src_general_regs {
+ u32 reserved[1];
+ u32 authen_ctrl;
+ u32 reserved1[2];
+ u32 scr;
+ u32 srtmr;
+ u32 srmask;
+ u32 reserved2[1];
+ u32 srmr[6];
+ u32 reserved3[2];
+ u32 sbmr[2];
+ u32 reserved4[2];
+ u32 srsr;
+ u32 gpr[19];
+ u32 reserved5[24];
+ u32 gpr20;
+ u32 cm_quiesce;
+ u32 cold_reset_ssar_ack_ctrl;
+ u32 sp_iso_ctrl;
+ u32 rom_lp_ctrl;
+ u32 a55_deny_stat;
+};
+
+struct src_mem_slice_regs {
+ u32 reserved[1];
+ u32 mem_ctrl;
+ u32 memlp_ctrl_0;
+ u32 reserved1[1];
+ u32 memlp_ctrl_1;
+ u32 memlp_ctrl_2;
+ u32 mem_stat;
+};
+
+struct src_mix_slice_regs {
+ u32 reserved[1];
+ u32 authen_ctrl;
+ u32 reserved1[2];
+ u32 lpm_setting[3];
+ u32 reserved2[1];
+ u32 slice_sw_ctrl;
+ u32 single_reset_sw_ctrl;
+ u32 reserved3[6];
+ u32 a55_hdsk_ack_ctrl;
+ u32 a55_hdsk_ack_stat;
+ u32 reserved4[2];
+ u32 ssar_ack_ctrl;
+ u32 ssar_ack_stat;
+ u32 reserved5[1];
+ u32 iso_off_dly_por;
+ u32 iso_on_dly;
+ u32 iso_off_dly;
+ u32 psw_off_lf_dly;
+
[PATCH V4 31/49] imx: imx9: Add gpio registers structure
From: Ye Li
Add GPIO registers structure for iMX93, so that we can enable lpgpio
driver
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/Kconfig | 1 +
arch/arm/include/asm/arch-imx9/gpio.h | 20
2 files changed, 21 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 84350445923..ce9b985db49 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -936,6 +936,7 @@ config ARCH_IMX9
select DM
select MACH_IMX
select SUPPORT_SPL
+ select GPIO_EXTRA_HEADER
select MISC
select IMX_SENTINEL
imply CMD_DM
diff --git a/arch/arm/include/asm/arch-imx9/gpio.h
b/arch/arm/include/asm/arch-imx9/gpio.h
index e69de29bb2d..40732022e7e 100644
--- a/arch/arm/include/asm/arch-imx9/gpio.h
+++ b/arch/arm/include/asm/arch-imx9/gpio.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_GPIO_H
+#define __ASM_ARCH_IMX9_GPIO_H
+
+struct gpio_regs {
+ u32 gpio_pdor;
+ u32 gpio_psor;
+ u32 gpio_pcor;
+ u32 gpio_ptor;
+ u32 gpio_pdir;
+ u32 gpio_pddr;
+ u32 gpio_pidr;
+ u8 gpio_pxdr[32];
+};
+
+#endif
--
2.36.0
[PATCH V4 30/49] misc: fuse: update the code for accessing fuse of i.MX93
From: Alice Guo
Sentinel have read access of OTP shadow register 0-511, and fsb have
read access of shadow 0-51/312-511.
Reviewed-by: Ye Li
Signed-off-by: Alice Guo
Signed-off-by: Peng Fan
---
drivers/misc/sentinel/fuse.c | 86 +++-
1 file changed, 74 insertions(+), 12 deletions(-)
diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c
index abb4c072f9b..e2b68757664 100644
--- a/drivers/misc/sentinel/fuse.c
+++ b/drivers/misc/sentinel/fuse.c
@@ -75,22 +75,44 @@ struct fsb_map_entry fsb_mapping_table[] = {
{ 0, 8 },
{ 1, 8 },
{ 2, 8 },
- { -1, 8 },
+ { 3, 8 },
{ 4, 8 },
{ 5, 8 },
- { 6, 8 }, /* UID */
- { -1, 8 },
- { 8, 8 },
- { 9, 8 },
- { 10, 8 },
+ { 6, 4 },
+ { -1, 260 },
+ { 39, 8 },
+ { 40, 8 },
+ { 41, 8 },
+ { 42, 8 },
+ { 43, 8 },
+ { 44, 8 },
+ { 45, 8 },
+ { 46, 8 },
+ { 47, 8 },
+ { 48, 8 },
+ { 49, 8 },
+ { 50, 8 },
+ { 51, 8 },
+ { 52, 8 },
+ { 53, 8 },
+ { 54, 8 },
+ { 55, 8 },
+ { 56, 8 },
+ { 57, 8 },
+ { 58, 8 },
+ { 59, 8 },
+ { 60, 8 },
+ { 61, 8 },
+ { 62, 8 },
+ { 63, 8 },
};
struct s400_map_entry s400_api_mapping_table[] = {
- { 3, 11 }, /* 24 .. 34 */
- { 7, 8 },
- { 16, 11 }, /* 128 .. 143 */
- { 22, 8 },
- { 23, 8 },
+ { 7, 1, 7, 63 },
+ { 16, 8, },
+ { 17, 8, },
+ { 22, 1, 6 },
+ { 23, 1, 4 },
};
#endif
@@ -102,7 +124,8 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool
*redundancy)
/* map the fuse from ocotp fuse map to FSB*/
for (i = 0; i < size; i++) {
if (fsb_mapping_table[i].fuse_bank != -1 &&
- fsb_mapping_table[i].fuse_bank == bank) {
+ fsb_mapping_table[i].fuse_bank == bank &&
+ fsb_mapping_table[i].fuse_words > word) {
break;
}
@@ -146,6 +169,7 @@ static s32 map_s400_fuse_index(u32 bank, u32 word)
return s400_api_mapping_table[i].fuse_bank * 8 + word;
}
+#if defined(CONFIG_IMX8ULP)
int fuse_sense(u32 bank, u32 word, u32 *val)
{
s32 word_index;
@@ -198,6 +222,44 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
return -ENOENT;
}
+#elif defined(CONFIG_ARCH_IMX9)
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ s32 word_index;
+ bool redundancy;
+
+ if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ return -EINVAL;
+
+ word_index = map_fsb_fuse_index(bank, word, );
+ if (word_index >= 0) {
+ *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW +
(word_index << 2));
+ if (redundancy)
+ *val = (*val >> ((word % 2) * 16)) & 0x;
+
+ return 0;
+ }
+
+ word_index = map_s400_fuse_index(bank, word);
+ if (word_index >= 0) {
+ u32 data;
+ u32 res, size = 1;
+ int ret;
+
+ ret = ahab_read_common_fuse(word_index, , size, );
+ if (ret) {
+ printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+ return ret;
+ }
+
+ *val = data;
+
+ return 0;
+ }
+
+ return -ENOENT;
+}
+#endif
int fuse_read(u32 bank, u32 word, u32 *val)
{
--
2.36.0
[PATCH V4 29/49] misc: fuse: support to access fuse on i.MX93
From: Alice Guo
i.MX93 fuse can be accessed through FSB and s400-api. Add mapping tables
for i.MX93. The offset address of FSB accessing OTP shadow registers is
different between i.MX8ULP and i.MX93, so use macro to define the offset
address instead of hardcode.
Signed-off-by: Alice Guo
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 2 ++
drivers/misc/sentinel/fuse.c | 30 ++-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 7b84b970b75..fa6951ebbe8 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -19,6 +19,8 @@
#define WDG4_BASE_ADDR 0x424aUL
#define WDG5_BASE_ADDR 0x424bUL
+#define FSB_BASE_ADDR 0x4751UL
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
#include
diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c
index 83d2c25731f..abb4c072f9b 100644
--- a/drivers/misc/sentinel/fuse.c
+++ b/drivers/misc/sentinel/fuse.c
@@ -31,6 +31,9 @@ struct s400_map_entry {
u32 s400_index;
};
+#if defined(CONFIG_IMX8ULP)
+#define FSB_OTP_SHADOW 0x800
+
struct fsb_map_entry fsb_mapping_table[] = {
{ 3, 8 },
{ 4, 8 },
@@ -65,6 +68,31 @@ struct s400_map_entry s400_api_mapping_table[] = {
{ 23, 1, 4, 2 }, /* OTFAD */
{ 25, 8 }, /* Test config2 */
};
+#elif defined(CONFIG_ARCH_IMX9)
+#define FSB_OTP_SHADOW 0x8000
+
+struct fsb_map_entry fsb_mapping_table[] = {
+ { 0, 8 },
+ { 1, 8 },
+ { 2, 8 },
+ { -1, 8 },
+ { 4, 8 },
+ { 5, 8 },
+ { 6, 8 }, /* UID */
+ { -1, 8 },
+ { 8, 8 },
+ { 9, 8 },
+ { 10, 8 },
+};
+
+struct s400_map_entry s400_api_mapping_table[] = {
+ { 3, 11 }, /* 24 .. 34 */
+ { 7, 8 },
+ { 16, 11 }, /* 128 .. 143 */
+ { 22, 8 },
+ { 23, 8 },
+};
+#endif
static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
{
@@ -128,7 +156,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
word_index = map_fsb_fuse_index(bank, word, );
if (word_index >= 0) {
- *val = readl((ulong)FSB_BASE_ADDR + 0x800 + (word_index << 2));
+ *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW +
(word_index << 2));
if (redundancy)
*val = (*val >> ((word % 2) * 16)) & 0x;
--
2.36.0
[PATCH V4 28/49] misc: imx8ulp: move fuse.c from imx8ulp to sentinel
From: Alice Guo
The i.MX93 platform wants to reuse drivers/misc/imx8ulp/fuse.c. Moving
fuse.c from the folder imx8ulp to sentinel makes it can be used by other
platforms.
Signed-off-by: Alice Guo
Signed-off-by: Peng Fan
---
drivers/misc/Makefile | 2 --
drivers/misc/imx8ulp/Makefile | 3 ---
drivers/misc/sentinel/Makefile| 1 +
drivers/misc/{imx8ulp => sentinel}/fuse.c | 0
4 files changed, 1 insertion(+), 5 deletions(-)
delete mode 100644 drivers/misc/imx8ulp/Makefile
rename drivers/misc/{imx8ulp => sentinel}/fuse.c (100%)
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index dcba39a15fc..33ccaf04f6a 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -49,8 +49,6 @@ obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o
obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
obj-$(CONFIG_IMX8) += imx8/
-obj-$(CONFIG_IMX8ULP) += imx8ulp/
-obj-$(CONFIG_IMX8ULP) += imx8ulp/
obj-$(CONFIG_IMX_SENTINEL) += sentinel/
obj-$(CONFIG_LED_STATUS) += status_led.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
diff --git a/drivers/misc/imx8ulp/Makefile b/drivers/misc/imx8ulp/Makefile
deleted file mode 100644
index 450e615e645..000
--- a/drivers/misc/imx8ulp/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/sentinel/Makefile b/drivers/misc/sentinel/Makefile
index 3e2f623b278..446154cb201 100644
--- a/drivers/misc/sentinel/Makefile
+++ b/drivers/misc/sentinel/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += s400_api.o s4mu.o
+obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/imx8ulp/fuse.c b/drivers/misc/sentinel/fuse.c
similarity index 100%
rename from drivers/misc/imx8ulp/fuse.c
rename to drivers/misc/sentinel/fuse.c
--
2.36.0
[PATCH V4 27/49] misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg
From: Ye Li
Use more generic name for S40x msg structure
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 2 +-
arch/arm/mach-imx/imx8ulp/rdc.c | 2 +-
arch/arm/mach-imx/imx9/trdc.c| 2 +-
drivers/misc/sentinel/s400_api.c | 44
drivers/misc/sentinel/s4mu.c | 6 ++--
5 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index dc176e1f619..89fa373d06f 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -26,7 +26,7 @@
#define S400_MAX_MSG 255U
-struct imx8ulp_s400_msg {
+struct sentinel_msg {
u8 version;
u8 size;
u8 command;
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index cc47079d8f5..e24eeff8a20 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -184,7 +184,7 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32
perm)
int release_rdc(enum rdc_type type)
{
ulong s_mu_base = 0x2702UL;
- struct imx8ulp_s400_msg msg;
+ struct sentinel_msg msg;
int ret;
u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index b0881697a10..3f37ce712c0 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -315,7 +315,7 @@ bool trdc_mbc_enabled(ulong trdc_base)
int release_rdc(u8 xrdc)
{
ulong s_mu_base = 0x4752UL;
- struct imx8ulp_s400_msg msg;
+ struct sentinel_msg msg;
int ret;
u32 rdc_id;
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index 01a673e5e13..65032f77362 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -17,8 +17,8 @@ DECLARE_GLOBAL_DATA_PTR;
int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -62,8 +62,8 @@ int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -92,8 +92,8 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
int ahab_release_container(u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -120,8 +120,8 @@ int ahab_release_container(u32 *response)
int ahab_verify_image(u32 img_id, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -149,8 +149,8 @@ int ahab_verify_image(u32 img_id, u32 *response)
int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -178,8 +178,8 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32
*response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -226,8 +226,8 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32
fuse_num, u32 *respo
int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -259,8 +259,8 @@ int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock,
u32 *response)
int ahab_release_caam(u32 core_did, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+
[PATCH V4 26/49] imx: imx9: Get the chip revision through S400 API
From: Peng Fan
Update the get chip revision methond to use S400 API, also record
other information like lifecycle and UID to global data.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/global_data.h | 3 ++
arch/arm/mach-imx/imx9/soc.c | 49 +-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index 09f352269e5..6ee2a767615 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -92,6 +92,9 @@ struct arch_global_data {
#ifdef CONFIG_IMX_SENTINEL
struct udevice *s400_dev;
+ u32 soc_rev;
+ u32 lifecycle;
+ u32 uid[4];
#endif
};
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 7c71cbdd55a..c71a5a92504 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -67,9 +68,18 @@ int mmc_get_env_dev(void)
}
#endif
+static void set_cpu_info(struct sentinel_get_info_data *info)
+{
+ gd->arch.soc_rev = info->soc;
+ gd->arch.lifecycle = info->lc;
+ memcpy((void *)>arch.uid, >uid, 4 * sizeof(u32));
+}
+
u32 get_cpu_rev(void)
{
- return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
+ u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+
+ return (MXC_CPU_IMX93 << 12) | (CHIP_REV_1_0 + rev);
}
#define UNLOCK_WORD 0xD928C520 /* unlock word */
@@ -198,6 +208,17 @@ int ft_system_setup(void *blob, struct bd_info *bd)
return 0;
}
+#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ printf("UID: 0x%x 0x%x 0x%x 0x%x\n",
+ gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2],
gd->arch.uid[3]);
+
+ serialnr->low = gd->arch.uid[0];
+ serialnr->high = gd->arch.uid[3];
+}
+#endif
+
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
@@ -212,6 +233,32 @@ int arch_cpu_init(void)
return 0;
}
+int imx9_probe_mu(void *ctx, struct event *event)
+{
+ struct udevice *devp;
+ int node, ret;
+ u32 res;
+ struct sentinel_get_info_data info;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"fsl,imx93-mu-s4");
+
+ ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, );
+ if (ret)
+ return ret;
+
+ if (gd->flags & GD_FLG_RELOC)
+ return 0;
+
+ ret = ahab_get_info(, );
+ if (ret)
+ return ret;
+
+ set_cpu_info();
+
+ return 0;
+}
+EVENT_SPY(EVT_DM_POST_INIT, imx9_probe_mu);
+
int timer_init(void)
{
#ifdef CONFIG_SPL_BUILD
--
2.36.0
[PATCH V4 25/49] imx: imx9: Add AHAB boot support
From: Ye Li
Add AHAB driver for iMX9 to do authentication by calling sentinel API
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/Kconfig | 5 +
arch/arm/mach-imx/imx9/Makefile | 1 +
arch/arm/mach-imx/imx9/ahab.c | 346
3 files changed, 352 insertions(+)
create mode 100644 arch/arm/mach-imx/imx9/ahab.c
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index ce58e41428f..dae9f658e65 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -1,5 +1,10 @@
if ARCH_IMX9
+config AHAB_BOOT
+bool "Support i.MX9 AHAB features"
+help
+This option enables the support for AHAB secure boot.
+
config IMX9
bool
select HAS_CAAM
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 0124212f266..41a22500c95 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -4,3 +4,4 @@
obj-y += lowlevel_init.o
obj-y += soc.o clock.o clock_root.o trdc.o
+obj-$(CONFIG_AHAB_BOOT) += ahab.o
diff --git a/arch/arm/mach-imx/imx9/ahab.c b/arch/arm/mach-imx/imx9/ahab.c
new file mode 100644
index 000..6aa949619b5
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/ahab.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMG_CONTAINER_BASE (0x8000UL)
+#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xUL)
+
+#define AHAB_NO_AUTHENTICATION_IND 0xee
+#define AHAB_BAD_KEY_HASH_IND 0xfa
+#define AHAB_INVALID_KEY_IND 0xf9
+#define AHAB_BAD_SIGNATURE_IND 0xf0
+#define AHAB_BAD_HASH_IND 0xf1
+
+static void display_ahab_auth_ind(u32 event)
+{
+ u8 resp_ind = (event >> 8) & 0xff;
+
+ switch (resp_ind) {
+ case AHAB_NO_AUTHENTICATION_IND:
+ printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_KEY_HASH_IND:
+ printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_INVALID_KEY_IND:
+ printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_SIGNATURE_IND:
+ printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_HASH_IND:
+ printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ default:
+ printf("Unknown Indicator (0x%02X)\n\n", resp_ind);
+ break;
+ }
+}
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
+{
+ int err;
+ u32 resp;
+
+ memcpy((void *)IMG_CONTAINER_BASE, (const void *)container,
+ ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
+
+ flush_dcache_range(IMG_CONTAINER_BASE,
+ IMG_CONTAINER_BASE + ALIGN(length,
CONFIG_SYS_CACHELINE_SIZE) - 1);
+
+ err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, );
+ if (err) {
+ printf("Authenticate container hdr failed, return %d, resp
0x%x\n",
+ err, resp);
+ display_ahab_auth_ind(resp);
+ }
+
+ return err;
+}
+
+int ahab_auth_release(void)
+{
+ int err;
+ u32 resp;
+
+ err = ahab_release_container();
+ if (err) {
+ printf("Error: release container failed, resp 0x%x!\n", resp);
+ display_ahab_auth_ind(resp);
+ }
+
+ return err;
+}
+
+int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
+{
+ int err;
+ u32 resp;
+
+ err = ahab_verify_image(image_index, );
+ if (err) {
+ printf("Authenticate img %d failed, return %d, resp 0x%x\n",
+ image_index, err, resp);
+ display_ahab_auth_ind(resp);
+
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static inline bool check_in_dram(ulong addr)
+{
+ int i;
+ struct bd_info *bd = gd->bd;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+ if (bd->bi_dram[i].size) {
+ if (addr >= bd->bi_dram[i].start &&
+ addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
+ return true;
+ }
+ }
+
+ return false;
+}
+
+int authenticate_os_container(ulong addr)
+{
+ struct container_hdr *phdr;
+ int i, ret = 0;
+ int err;
+ u16 length;
+ struct boot_img_t *img;
+ unsigned long s, e;
+
+ if (addr % 4) {
+ puts("Error: Image's address is not 4 byte aligned\n");
+ return -EINVAL;
+ }
+
+ if (!check_in_dram(addr)) {
+ puts("Error: Image's address is invalid\n");
+
[PATCH V4 24/49] imx: imx9: Add TRDC driver for TRDC init
From: Ye Li
Add TRDC driver to iMX9. The TRDC init splits to two phases:
1. Early init phase will release TRDC from Sentinel and open write
permission to the memory where SPL image runs. Sentinel will set
the memory to RX only after ROM authentication for the OEM
closed part.
2. Init phase will configure TRDC to allow non-secure master to
access DDR. So the peripherals can work in u-boot.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/trdc.h | 19 +
arch/arm/mach-imx/imx9/Makefile | 2 +-
arch/arm/mach-imx/imx9/soc.c | 3 +
arch/arm/mach-imx/imx9/trdc.c | 581 ++
4 files changed, 604 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-imx9/trdc.h
create mode 100644 arch/arm/mach-imx/imx9/trdc.c
diff --git a/arch/arm/include/asm/arch-imx9/trdc.h
b/arch/arm/include/asm/arch-imx9/trdc.h
new file mode 100644
index 000..1481ee375b7
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/trdc.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_TRDC_H
+#define __ASM_ARCH_IMX9_TRDC_H
+
+int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32
glbac_val);
+int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32
blk_x,
+ bool sec_access, u32 glbac_id);
+int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, u32 glbac_id, u32
glbac_val);
+int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32
addr_start,
+ u32 addr_end, bool sec_access, u32 glbac_id);
+
+void trdc_early_init(void);
+void trdc_init(void);
+
+#endif
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 7be0343d52e..0124212f266 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -3,4 +3,4 @@
# Copyright 2022 NXP
obj-y += lowlevel_init.o
-obj-y += soc.o clock.o clock_root.o
+obj-y += soc.o clock.o clock_root.o trdc.o
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 9ea2d51495b..7c71cbdd55a 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -204,6 +205,8 @@ int arch_cpu_init(void)
init_wdog();
clock_init();
+
+ trdc_early_init();
}
return 0;
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
new file mode 100644
index 000..b0881697a10
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -0,0 +1,581 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DID_NUM 16
+#define MBC_MAX_NUM 4
+#define MRC_MAX_NUM 2
+#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
+#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
+
+struct mbc_mem_dom {
+ u32 mem_glbcfg[4];
+ u32 nse_blk_index;
+ u32 nse_blk_set;
+ u32 nse_blk_clr;
+ u32 nsr_blk_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MBC */
+ u32 mem0_blk_cfg_w[64];
+ u32 mem0_blk_nse_w[16];
+ u32 mem1_blk_cfg_w[8];
+ u32 mem1_blk_nse_w[2];
+ u32 mem2_blk_cfg_w[8];
+ u32 mem2_blk_nse_w[2];
+ u32 mem3_blk_cfg_w[8];
+ u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */
+ u32 reserved[2];
+};
+
+struct mrc_rgn_dom {
+ u32 mrc_glbcfg[4];
+ u32 nse_rgn_indirect;
+ u32 nse_rgn_set;
+ u32 nse_rgn_clr;
+ u32 nse_rgn_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MRC */
+ u32 rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */
+ u32 rgn_nse;
+ u32 reserved2[15];
+};
+
+struct mda_inst {
+ u32 mda_w[8];
+};
+
+struct trdc_mgr {
+ u32 trdc_cr;
+ u32 res0[59];
+ u32 trdc_hwcfg0;
+ u32 trdc_hwcfg1;
+ u32 res1[450];
+ struct mda_inst mda[8];
+ u32 res2[15808];
+};
+
+struct trdc_mbc {
+ struct mbc_mem_dom mem_dom[DID_NUM];
+};
+
+struct trdc_mrc {
+ struct mrc_rgn_dom mrc_dom[DID_NUM];
+};
+
+int trdc_mda_set_cpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, u8 sa, u8 dids,
+u8 did, u8 pe, u8 pidm, u8 pid)
+{
+ struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+ u32 *mda_w = _base->mda[mda_inst].mda_w[mda_reg];
+ u32 val = readl(mda_w);
+
+ if (val & BIT(29)) /* non-cpu */
+ return -EINVAL;
+
+ val = BIT(31) | ((pid & 0x3f) << 16) | ((pidm & 0x3f) << 8) |
+ ((pe & 0x3) << 6) | ((sa & 0x3) << 14) | ((dids & 0x3) << 4) |
+ (did & 0xf);
+
+ writel(val, mda_w);
+
+ return 0;
+}
+
+int trdc_mda_set_noncpu(ulong
[PATCH V4 23/49] misc: s400_api: introduce ahab_release_m33_trout
From: Peng Fan
Introduce Sentinel API ahab_release_m33_trout to make sure sentinel
release M33 trout and make sure M33 could boot.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 1 +
drivers/misc/sentinel/s400_api.c | 25
2 files changed, 26 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index d95f8227b29..dc176e1f619 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -55,5 +55,6 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32
*response);
int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
int ahab_get_fw_status(u32 *status, u32 *response);
+int ahab_release_m33_trout(void);
#endif
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index ca7903670ed..01a673e5e13 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -420,3 +420,28 @@ int ahab_get_fw_status(u32 *status, u32 *response)
return ret;
}
+
+int ahab_release_m33_trout(void)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = 0xd3;
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ return ret;
+}
--
2.36.0
[PATCH V4 22/49] misc: S400_API: New API for FW status and chip info
From: Peng Fan
Add new API to get sentinel FW status and SoC chip info
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 13 +
drivers/misc/sentinel/s400_api.c | 61
2 files changed, 74 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index d09c078df01..d95f8227b29 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -19,8 +19,10 @@
#define AHAB_READ_FUSE_REQ_CID 0x97
#define AHAB_GET_FW_VERSION_CID0x9D
#define AHAB_RELEASE_RDC_REQ_CID 0xC4
+#define AHAB_GET_FW_STATUS_CID 0xC5
#define AHAB_WRITE_FUSE_REQ_CID0xD6
#define AHAB_CAAM_RELEASE_CID 0xD7
+#define AHAB_GET_INFO_CID 0xDA
#define S400_MAX_MSG 255U
@@ -32,6 +34,15 @@ struct imx8ulp_s400_msg {
u32 data[(S400_MAX_MSG - 1U)];
};
+struct sentinel_get_info_data {
+ u32 hdr;
+ u32 soc;
+ u32 lc;
+ u32 uid[4];
+ u32 sha256_rom_patch[8];
+ u32 sha_fw[8];
+};
+
int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ahab_release_container(u32 *response);
@@ -42,5 +53,7 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32
fuse_num, u32 *respo
int ahab_release_caam(u32 core_did, u32 *response);
int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
+int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
+int ahab_get_fw_status(u32 *status, u32 *response);
#endif
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index 4e90171420f..ca7903670ed 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -359,3 +359,64 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
return i;
}
+
+int ahab_get_info(struct sentinel_get_info_data *info, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 4;
+ msg.command = AHAB_GET_INFO_CID;
+ msg.data[0] = upper_32_bits((ulong)info);
+ msg.data[1] = lower_32_bits((ulong)info);
+ msg.data[2] = sizeof(struct sentinel_get_info_data);
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_get_fw_status(u32 *status, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = AHAB_GET_FW_STATUS_CID;
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ *status = msg.data[1] & 0xF;
+
+ return ret;
+}
--
2.36.0
[PATCH V4 21/49] misc: S400_API: Update release RDC API
From: Ye Li
To support more RDC instances on i.MX93, update API to latest
definition.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 2 +-
drivers/misc/sentinel/s400_api.c | 21 +
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index b3e6b3fa45d..d09c078df01 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -32,7 +32,7 @@ struct imx8ulp_s400_msg {
u32 data[(S400_MAX_MSG - 1U)];
};
-int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response);
+int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ahab_release_container(u32 *response);
int ahab_verify_image(u32 img_id, u32 *response);
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index 3d791bc868e..4e90171420f 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response)
+int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
int size = sizeof(struct imx8ulp_s400_msg);
@@ -30,10 +30,23 @@ int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response)
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_RELEASE_RDC_REQ_CID;
- if (xrdc)
- msg.data[0] = (0x78 << 8) | core_id;
- else
+ switch (xrdc) {
+ case 0:
msg.data[0] = (0x74 << 8) | core_id;
+ break;
+ case 1:
+ msg.data[0] = (0x78 << 8) | core_id;
+ break;
+ case 2:
+ msg.data[0] = (0x82 << 8) | core_id;
+ break;
+ case 3:
+ msg.data[0] = (0x86 << 8) | core_id;
+ break;
+ default:
+ printf("Error: wrong xrdc index %u\n", xrdc);
+ return -EINVAL;
+ }
ret = misc_call(dev, false, , size, , size);
if (ret)
--
2.36.0
[PATCH V4 20/49] misc: s4mu: Support iMX93 with Sentinel MU
From: Peng Fan
Support iMX93 communicate with Sentinel
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 30 +++
drivers/misc/sentinel/s4mu.c | 1 +
2 files changed, 31 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index e4babed40fc..7b84b970b75 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -19,4 +19,34 @@
#define WDG4_BASE_ADDR 0x424aUL
#define WDG5_BASE_ADDR 0x424bUL
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include
+#include
+
+struct mu_type {
+ u32 ver;
+ u32 par;
+ u32 cr;
+ u32 sr;
+ u32 reserved0[60];
+ u32 fcr;
+ u32 fsr;
+ u32 reserved1[2];
+ u32 gier;
+ u32 gcr;
+ u32 gsr;
+ u32 reserved2;
+ u32 tcr;
+ u32 tsr;
+ u32 rcr;
+ u32 rsr;
+ u32 reserved3[52];
+ u32 tr[16];
+ u32 reserved4[16];
+ u32 rr[16];
+ u32 reserved5[14];
+ u32 mu_attr;
+};
+#endif
+
#endif
diff --git a/drivers/misc/sentinel/s4mu.c b/drivers/misc/sentinel/s4mu.c
index 121a81060a6..18aea27105e 100644
--- a/drivers/misc/sentinel/s4mu.c
+++ b/drivers/misc/sentinel/s4mu.c
@@ -219,6 +219,7 @@ static struct misc_ops imx8ulp_mu_ops = {
static const struct udevice_id imx8ulp_mu_ids[] = {
{ .compatible = "fsl,imx8ulp-mu" },
+ { .compatible = "fsl,imx93-mu-s4" },
{ }
};
--
2.36.0
[PATCH V4 19/49] misc: imx: S400_API: Move S400 MU and API to a common place
From: Ye Li
Since iMX9 uses S401 which shares the API with iMX8ULP. So move S400
MU driver and API to a common place and selected by CONFIG_IMX_SENTINEL
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/Kconfig | 4 +
arch/arm/include/asm/global_data.h| 2 +-
.../asm/{arch-imx8ulp => mach-imx}/mu_hal.h | 4 +-
.../asm/{arch-imx8ulp => mach-imx}/s400_api.h | 0
arch/arm/mach-imx/imx8ulp/ahab.c | 345 ++
arch/arm/mach-imx/imx8ulp/rdc.c | 4 +-
arch/arm/mach-imx/imx8ulp/soc.c | 4 +-
board/freescale/imx8ulp_evk/spl.c | 2 +-
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 2 +
drivers/misc/imx8ulp/Makefile | 1 -
drivers/misc/imx8ulp/fuse.c | 2 +-
drivers/misc/sentinel/Makefile| 3 +
drivers/misc/{imx8ulp => sentinel}/s400_api.c | 6 +-
.../{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} | 4 +-
15 files changed, 375 insertions(+), 15 deletions(-)
rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/mu_hal.h (79%)
rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/s400_api.h (100%)
create mode 100644 arch/arm/mach-imx/imx8ulp/ahab.c
create mode 100644 drivers/misc/sentinel/Makefile
rename drivers/misc/{imx8ulp => sentinel}/s400_api.c (98%)
rename drivers/misc/{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} (98%)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ce171e36a01..84350445923 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -925,6 +925,8 @@ config ARCH_IMX8ULP
select OF_CONTROL
select SUPPORT_SPL
select GPIO_EXTRA_HEADER
+ select MISC
+ select IMX_SENTINEL
imply CMD_DM
imply DM_EVENT
@@ -934,6 +936,8 @@ config ARCH_IMX9
select DM
select MACH_IMX
select SUPPORT_SPL
+ select MISC
+ select IMX_SENTINEL
imply CMD_DM
imply DM_EVENT
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index 085e12b5d4d..09f352269e5 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -90,7 +90,7 @@ struct arch_global_data {
struct udevice *scu_dev;
#endif
-#ifdef CONFIG_ARCH_IMX8ULP
+#ifdef CONFIG_IMX_SENTINEL
struct udevice *s400_dev;
#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
b/arch/arm/include/asm/mach-imx/mu_hal.h
similarity index 79%
rename from arch/arm/include/asm/arch-imx8ulp/mu_hal.h
rename to arch/arm/include/asm/mach-imx/mu_hal.h
index 10d966d5d43..5db559c1ac5 100644
--- a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
+++ b/arch/arm/include/asm/mach-imx/mu_hal.h
@@ -3,8 +3,8 @@
* Copyright 2021 NXP
*/
-#ifndef __IMX8ULP_MU_HAL_H__
-#define __IMX8ULP_MU_HAL_H__
+#ifndef __SNT_MU_HAL_H__
+#define __SNT_MU_HAL_H__
void mu_hal_init(ulong base);
int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg);
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
similarity index 100%
rename from arch/arm/include/asm/arch-imx8ulp/s400_api.h
rename to arch/arm/include/asm/mach-imx/s400_api.h
diff --git a/arch/arm/mach-imx/imx8ulp/ahab.c b/arch/arm/mach-imx/imx8ulp/ahab.c
new file mode 100644
index 000..87c4c66a087
--- /dev/null
+++ b/arch/arm/mach-imx/imx8ulp/ahab.c
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMG_CONTAINER_BASE (0x2201UL)
+#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xUL)
+
+#define AHAB_NO_AUTHENTICATION_IND 0xee
+#define AHAB_BAD_KEY_HASH_IND 0xfa
+#define AHAB_INVALID_KEY_IND 0xf9
+#define AHAB_BAD_SIGNATURE_IND 0xf0
+#define AHAB_BAD_HASH_IND 0xf1
+
+static void display_ahab_auth_ind(u32 event)
+{
+ u8 resp_ind = (event >> 8) & 0xff;
+
+ switch (resp_ind) {
+ case AHAB_NO_AUTHENTICATION_IND:
+ printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_KEY_HASH_IND:
+ printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_INVALID_KEY_IND:
+ printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_SIGNATURE_IND:
+ printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_HASH_IND:
+ printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ default:
+ printf("Unknown Indicator (0x%02X)\n\n", resp_ind);
+ break;
+ }
+}
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16
[PATCH V4 18/49] imx: imx9: support romapi
From: Peng Fan
i.MX9 shares same ROM API with i.MX8ULP, so make the i.MX8ULP the function
prototype common and usable by i.MX9.
Also include mmc env functions that use ROM API.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 4 --
arch/arm/include/asm/mach-imx/sys_proto.h | 4 ++
arch/arm/mach-imx/imx9/soc.c | 37 +++
3 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 05859dfc2aa..a7869fbb573 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -8,10 +8,6 @@
#include
-extern unsigned long rom_pointer[];
-
-ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
-ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
enum bt_mode get_boot_mode(void);
int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 05532ebea89..17c5f44b208 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -180,6 +180,10 @@ enum boot_dev_type_e {
#define ROM_API_OKAY 0xF0
extern struct rom_api *g_rom_api;
+extern unsigned long rom_pointer[];
+
+ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
+ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
/* For i.MX ULP */
#define BT0CFG_LPBOOT_MASK 0x1
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 8b620832b5d..9ea2d51495b 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -29,6 +29,43 @@
DECLARE_GLOBAL_DATA_PTR;
+struct rom_api *g_rom_api = (struct rom_api *)0x1980;
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return devno; }
+
+int mmc_get_env_dev(void)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 boot;
+ u16 boot_type;
+ u8 boot_instance;
+
+ ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, ,
+ ((uintptr_t)) ^ QUERY_BT_DEV);
+ set_gd(pgd);
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: failure at query_boot_info\n");
+ return CONFIG_SYS_MMC_ENV_DEV;
+ }
+
+ boot_type = boot >> 16;
+ boot_instance = (boot >> 8) & 0xff;
+
+ debug("boot_type %d, instance %d\n", boot_type, boot_instance);
+
+ /* If not boot from sd/mmc, use default value */
+ if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC)
+ return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
+
+ return board_mmc_get_env_dev(boot_instance);
+}
+#endif
+
u32 get_cpu_rev(void)
{
return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
--
2.36.0
[PATCH V4 17/49] imx: imx9: disable watchdog
From: Ye Li
Disable all 3 wdogs on AIPS2 and unmask SRC reset trigger for WDOG3-5
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 4 ++
arch/arm/mach-imx/imx9/soc.c | 45 ++-
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 32c76ce9c3b..e4babed40fc 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -15,4 +15,8 @@
#define ANATOP_BASE_ADDR0x4448UL
+#define WDG3_BASE_ADDR 0x4249UL
+#define WDG4_BASE_ADDR 0x424aUL
+#define WDG5_BASE_ADDR 0x424bUL
+
#endif
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 4b8f1ca30d5..8b620832b5d 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -34,6 +34,45 @@ u32 get_cpu_rev(void)
return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
}
+#define UNLOCK_WORD 0xD928C520 /* unlock word */
+#define REFRESH_WORD 0xB480A602 /* refresh word */
+
+static void disable_wdog(void __iomem *wdog_base)
+{
+ u32 val_cs = readl(wdog_base + 0x00);
+
+ if (!(val_cs & 0x80))
+ return;
+
+ /* default is 32bits cmd */
+ writel(REFRESH_WORD, (wdog_base + 0x04)); /* Refresh the CNT */
+
+ if (!(val_cs & 0x800)) {
+ writel(UNLOCK_WORD, (wdog_base + 0x04));
+ while (!(readl(wdog_base + 0x00) & 0x800))
+ ;
+ }
+ writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
+ writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
+ writel(0x2120, (wdog_base + 0x00)); /* Disable it and set update */
+
+ while (!(readl(wdog_base + 0x00) & 0x400))
+ ;
+}
+
+void init_wdog(void)
+{
+ u32 src_val;
+
+ disable_wdog((void __iomem *)WDG3_BASE_ADDR);
+ disable_wdog((void __iomem *)WDG4_BASE_ADDR);
+ disable_wdog((void __iomem *)WDG5_BASE_ADDR);
+
+ src_val = readl(0x54460018); /* reset mask */
+ src_val &= ~0x1c;
+ writel(src_val, 0x54460018);
+}
+
static struct mm_region imx93_mem_map[] = {
{
/* ROM */
@@ -123,8 +162,12 @@ int ft_system_setup(void *blob, struct bd_info *bd)
int arch_cpu_init(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ /* Disable wdog */
+ init_wdog();
+
clock_init();
+ }
return 0;
}
--
2.36.0
[PATCH V4 16/49] imx: imx9: Add function to initialize timer
From: Jian Li
Add timer_init to update ARM arch timer with correct frequency
from system counter and enable system counter.
Signed-off-by: Jian Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 19 +++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 50ec902987d..32c76ce9c3b 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -11,6 +11,7 @@
#define IOMUXC_BASE_ADDR 0x443CUL
#define CCM_BASE_ADDR 0x4445UL
#define CCM_CCGR_BASE_ADDR 0x44458000UL
+#define SYSCNT_CTRL_BASE_ADDR 0x4429
#define ANATOP_BASE_ADDR0x4448UL
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index d4a97729c67..4b8f1ca30d5 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -128,3 +128,22 @@ int arch_cpu_init(void)
return 0;
}
+
+int timer_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
+ unsigned long freq = readl(>cntfid0);
+
+ /* Update with accurate clock frequency */
+ asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
+
+ clrsetbits_le32(>cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
+ SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
+#endif
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
--
2.36.0
[PATCH V4 15/49] spl: Use SPL_FIT_IMAGE_TINY for iMX9
From: Peng Fan Select SPL_FIT_IMAGE_TINY for i.MX9 Signed-off-by: Peng Fan --- common/spl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 27b3abea87b..d632f568fcc 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -549,7 +549,7 @@ config SPL_FIT_IMAGE_TINY bool "Remove functionality from SPL FIT loading to reduce size" depends on SPL_FIT default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6 - default y if ARCH_IMX8M + default y if ARCH_IMX8M || ARCH_IMX9 help Enable this to reduce the size of the FIT image loading code in SPL, if space for the SPL binary is very tight. -- 2.36.0
[PATCH V4 14/49] mmc: fsl_esdhc_imx: Support i.MX9
From: Peng Fan Support i.MX9 for fsl_esdhc_imx driver Signed-off-by: Peng Fan --- drivers/mmc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 5a87db6be08..4d31fbcd527 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -852,7 +852,7 @@ config FSL_ESDHC_IMX config FSL_USDHC bool "Freescale/NXP i.MX uSDHC controller support" - depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMXRT + depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMX9 || IMXRT select FSL_ESDHC_IMX help This enables the Ultra Secured Digital Host Controller enhancements -- 2.36.0
[PATCH V4 13/49] imx: imx9: Add CCM and clock API support
From: Peng Fan Add clock API to support CCM root clock and LPCG setting Set the CCM AUTHEN register to allow non-secure world to set root clock and lpcg. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx9/ccm_regs.h | 266 arch/arm/include/asm/arch-imx9/clock.h| 239 +++ arch/arm/include/asm/arch-imx9/imx-regs.h | 6 +- arch/arm/mach-imx/imx9/Makefile | 2 +- arch/arm/mach-imx/imx9/clock.c| 769 +- arch/arm/mach-imx/imx9/clock_root.c | 438 arch/arm/mach-imx/imx9/soc.c | 3 + 7 files changed, 1720 insertions(+), 3 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx9/ccm_regs.h create mode 100644 arch/arm/mach-imx/imx9/clock_root.c diff --git a/arch/arm/include/asm/arch-imx9/ccm_regs.h b/arch/arm/include/asm/arch-imx9/ccm_regs.h new file mode 100644 index 000..d326a6ea516 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/ccm_regs.h @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_CCM_REGS_H__ +#define __ASM_ARCH_IMX9_CCM_REGS_H__ +#define IMX93_CLK_ROOT_MAX 95 +#define IMX93_CLK_CCGR_MAX 127 + +#define ARM_A55_PERIPH_CLK_ROOT0 +#define ARM_A55_MTR_BUS_CLK_ROOT 1 +#define ARM_A55_CLK_ROOT 2 +#define M33_CLK_ROOT 3 +#define SENTINEL_CLK_ROOT 4 +#define BUS_WAKEUP_CLK_ROOT5 +#define BUS_AON_CLK_ROOT 6 +#define WAKEUP_AXI_CLK_ROOT7 +#define SWO_TRACE_CLK_ROOT 8 +#define M33_SYSTICK_CLK_ROOT 9 +#define FLEXIO1_CLK_ROOT 10 +#define FLEXIO2_CLK_ROOT 11 +#define LPIT1_CLK_ROOT 12 +#define LPIT2_CLK_ROOT 13 +#define LPTMR1_CLK_ROOT14 +#define LPTMR2_CLK_ROOT15 +#define TPM1_CLK_ROOT 16 +#define TPM2_CLK_ROOT 17 +#define TPM3_CLK_ROOT 18 +#define TPM4_CLK_ROOT 19 +#define TPM5_CLK_ROOT 20 +#define TPM6_CLK_ROOT 21 +#define FLEXSPI1_CLK_ROOT 22 +#define CAN1_CLK_ROOT 23 +#define CAN2_CLK_ROOT 24 +#define LPUART1_CLK_ROOT 25 +#define LPUART2_CLK_ROOT 26 +#define LPUART3_CLK_ROOT 27 +#define LPUART4_CLK_ROOT 28 +#define LPUART5_CLK_ROOT 29 +#define LPUART6_CLK_ROOT 30 +#define LPUART7_CLK_ROOT 31 +#define LPUART8_CLK_ROOT 32 +#define LPI2C1_CLK_ROOT33 +#define LPI2C2_CLK_ROOT34 +#define LPI2C3_CLK_ROOT35 +#define LPI2C4_CLK_ROOT36 +#define LPI2C5_CLK_ROOT37 +#define LPI2C6_CLK_ROOT38 +#define LPI2C7_CLK_ROOT39 +#define LPI2C8_CLK_ROOT40 +#define LPSPI1_CLK_ROOT41 +#define LPSPI2_CLK_ROOT42 +#define LPSPI3_CLK_ROOT43 +#define LPSPI4_CLK_ROOT44 +#define LPSPI5_CLK_ROOT45 +#define LPSPI6_CLK_ROOT46 +#define LPSPI7_CLK_ROOT47 +#define LPSPI8_CLK_ROOT48 +#define I3C1_CLK_ROOT 49 +#define I3C2_CLK_ROOT 50 +#define USDHC1_CLK_ROOT51 +#define USDHC2_CLK_ROOT52 +#define USDHC3_CLK_ROOT53 +#define SAI1_CLK_ROOT 54 +#define SAI2_CLK_ROOT 55 +#define SAI3_CLK_ROOT 56 +#define CCM_CKO1_CLK_ROOT 57 +#define CCM_CKO2_CLK_ROOT 58 +#define CCM_CKO3_CLK_ROOT 59 +#define CCM_CKO4_CLK_ROOT 60 +#define HSIO_CLK_ROOT 61 +#define HSIO_USB_TEST_60M_CLK_ROOT 62 +#define HSIO_ACSCAN_80M_CLK_ROOT 63 +#define HSIO_ACSCAN_480M_CLK_ROOT 64 +#define NIC_CLK_ROOT 65 +#define NIC_APB_CLK_ROOT 66 +#define ML_APB_CLK_ROOT67 +#define ML_CLK_ROOT68 +#define MEDIA_AXI_CLK_ROOT 69 +#define MEDIA_APB_CLK_ROOT 70 +#define MEDIA_LDB_CLK_ROOT 71 +#define MEDIA_DISP_PIX_CLK_ROOT72 +#define CAM_PIX_CLK_ROOT 73 +#define MIPI_TEST_BYTE_CLK_ROOT74 +#define MIPI_PHY_CFG_CLK_ROOT 75 +#define DRAM_ALT_CLK_ROOT 76 +#define DRAM_APB_CLK_ROOT 77 +#define ADC_CLK_ROOT 78 +#define PDM_CLK_ROOT 79 +#define TSTMR1_CLK_ROOT80 +#define TSTMR2_CLK_ROOT81 +#define MQS1_CLK_ROOT
[PATCH V4 12/49] imx: pinctrl: add pinctrl and pinfunc file for i.MX93
From: Peng Fan Add the pinctrl driver and pinfunc header file to support iMX93 Signed-off-by: Peng Fan --- arch/arm/dts/imx93-pinfunc.h| 625 drivers/pinctrl/nxp/Kconfig | 13 + drivers/pinctrl/nxp/Makefile| 1 + drivers/pinctrl/nxp/pinctrl-imx93.c | 37 ++ 4 files changed, 676 insertions(+) create mode 100644 arch/arm/dts/imx93-pinfunc.h create mode 100644 drivers/pinctrl/nxp/pinctrl-imx93.c diff --git a/arch/arm/dts/imx93-pinfunc.h b/arch/arm/dts/imx93-pinfunc.h new file mode 100644 index 000..7f0136c70b6 --- /dev/null +++ b/arch/arm/dts/imx93-pinfunc.h @@ -0,0 +1,625 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DTS_IMX93_PINFUNC_H +#define __DTS_IMX93_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI0x 0x01B0 0x03E0 0x0 0x0 +#define MX93_PAD_DAP_TDI__MQS2_LEFT 0x 0x01B0 0x 0x1 0x0 +#define MX93_PAD_DAP_TDI__CAN2_TX 0x 0x01B0 0x 0x3 0x0 +#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO300x 0x01B0 0x 0x4 0x0 +#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x 0x01B0 0x03CC 0x5 0x0 +#define MX93_PAD_DAP_TDI__LPUART5_RX 0x 0x01B0 0x0438 0x6 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03E4 0x0 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x 0x4 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO290x0004 0x01B4 0x03D0 0x5 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x 0x6 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03DC 0x0 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x 0x4 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x 0x5 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B0x0008 0x01B8 0x0434 0x6 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x 0x0 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x 0x1 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX0x000C 0x01BC 0x0364 0x3 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x 0x4 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x 0x5 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x043C 0x6 0x0 +#define MX93_PAD_GPIO_IO00__GPIO2_IO000x0010 0x01C0 0x 0x0 0x0 +#define MX93_PAD_GPIO_IO00__LPI2C3_SDA0x0010 0x01C0 0x03EC 0x1 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x 0x2 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x 0x3 0x0 +#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x 0x4 0x0 +#define MX93_PAD_GPIO_IO00__LPUART5_TX0x0010 0x01C0 0x043C 0x5 0x1 +#define MX93_PAD_GPIO_IO00__LPI2C5_SDA0x0010 0x01C0 0x03F4 0x6 0x0 +#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 +#define MX93_PAD_GPIO_IO01__GPIO2_IO010x0014 0x01C4 0x 0x0 0x0 +#define MX93_PAD_GPIO_IO01__LPI2C3_SCL0x0014 0x01C4 0x03E8 0x1 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x 0x2 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x 0x3 0x0 +#define MX93_PAD_GPIO_IO01__LPSPI6_SIN0x0014 0x01C4 0x 0x4 0x0 +#define MX93_PAD_GPIO_IO01__LPUART5_RX0x0014 0x01C4 0x0438 0x5 0x1 +#define MX93_PAD_GPIO_IO01__LPI2C5_SCL0x0014 0x01C4 0x03F0 0x6 0x0 +#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 +#define MX93_PAD_GPIO_IO02__GPIO2_IO020x0018 0x01C8 0x 0x0 0x0 +#define MX93_PAD_GPIO_IO02__LPI2C4_SDA0x0018 0x01C8 0x 0x1 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC0x0018 0x01C8 0x 0x2 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x 0x3 0x0 +#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x 0x4 0x0 +#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x0434 0x5 0x1 +#define MX93_PAD_GPIO_IO02__LPI2C6_SDA0x0018
[PATCH V4 09/49] imx: add basic i.MX9 support
From: Peng Fan
Add i.MX9 Kconfig and basic files for the new SoC
Signed-off-by: Peng Fan
---
arch/arm/Kconfig| 11 +
arch/arm/include/asm/arch-imx/cpu.h | 2 +
arch/arm/include/asm/arch-imx9/clock.h | 0
arch/arm/include/asm/arch-imx9/gpio.h | 0
arch/arm/include/asm/arch-imx9/imx-regs.h | 13 +
arch/arm/include/asm/arch-imx9/imx93_pins.h | 729
arch/arm/include/asm/arch-imx9/sys_proto.h | 11 +
arch/arm/include/asm/mach-imx/iomux-v3.h| 11 +-
arch/arm/include/asm/mach-imx/sys_proto.h | 3 +
arch/arm/mach-imx/Makefile | 11 +-
arch/arm/mach-imx/imx9/Kconfig | 17 +
arch/arm/mach-imx/imx9/Makefile | 6 +
arch/arm/mach-imx/imx9/clock.c | 27 +
arch/arm/mach-imx/imx9/lowlevel_init.S | 26 +
arch/arm/mach-imx/imx9/soc.c| 127
arch/arm/mach-imx/spl.c | 2 +-
16 files changed, 991 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx9/clock.h
create mode 100644 arch/arm/include/asm/arch-imx9/gpio.h
create mode 100644 arch/arm/include/asm/arch-imx9/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-imx9/imx93_pins.h
create mode 100644 arch/arm/include/asm/arch-imx9/sys_proto.h
create mode 100644 arch/arm/mach-imx/imx9/Kconfig
create mode 100644 arch/arm/mach-imx/imx9/Makefile
create mode 100644 arch/arm/mach-imx/imx9/clock.c
create mode 100644 arch/arm/mach-imx/imx9/lowlevel_init.S
create mode 100644 arch/arm/mach-imx/imx9/soc.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ef79fc3a0a7..ce171e36a01 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -928,6 +928,15 @@ config ARCH_IMX8ULP
imply CMD_DM
imply DM_EVENT
+config ARCH_IMX9
+ bool "NXP i.MX9 platform"
+ select ARM64
+ select DM
+ select MACH_IMX
+ select SUPPORT_SPL
+ imply CMD_DM
+ imply DM_EVENT
+
config ARCH_IMXRT
bool "NXP i.MXRT platform"
select CPU_V7M
@@ -2249,6 +2258,8 @@ source "arch/arm/mach-imx/imx8m/Kconfig"
source "arch/arm/mach-imx/imx8ulp/Kconfig"
+source "arch/arm/mach-imx/imx9/Kconfig"
+
source "arch/arm/mach-imx/imxrt/Kconfig"
source "arch/arm/mach-imx/mxs/Kconfig"
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm/arch-imx/cpu.h
index 4f63803765e..d54e6e63352 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -59,6 +59,7 @@
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
+#define MXC_CPU_IMX93 0xC1 /* dummy ID */
#define MXC_SOC_MX60x60
#define MXC_SOC_MX70x70
@@ -66,6 +67,7 @@
#define MXC_SOC_IMX8 0x90 /* dummy */
#define MXC_SOC_IMXRT 0xB0 /* dummy */
#define MXC_SOC_MX7ULP 0xE0 /* dummy */
+#define MXC_SOC_IMX9 0xC0 /* dummy */
#define CHIP_REV_1_00x10
#define CHIP_REV_1_10x11
diff --git a/arch/arm/include/asm/arch-imx9/clock.h
b/arch/arm/include/asm/arch-imx9/clock.h
new file mode 100644
index 000..e69de29bb2d
diff --git a/arch/arm/include/asm/arch-imx9/gpio.h
b/arch/arm/include/asm/arch-imx9/gpio.h
new file mode 100644
index 000..e69de29bb2d
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
new file mode 100644
index 000..2adbdadf03c
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_REGS_H__
+#define __ASM_ARCH_IMX9_REGS_H__
+
+#define ARCH_MXC
+
+#define IOMUXC_BASE_ADDR 0x443CUL
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/imx93_pins.h
b/arch/arm/include/asm/arch-imx9/imx93_pins.h
new file mode 100644
index 000..f13aef5619c
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx93_pins.h
@@ -0,0 +1,729 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX93_PINS_H__
+#define __ASM_ARCH_IMX93_PINS_H__
+
+#include
+
+enum {
+ MX93_PAD_DAP_TDI__JTAG_MUX_TDI = IOMUX_PAD(0x1B0,
0x, 0, 0x3D8, 0, 0),
+ MX93_PAD_DAP_TDI__MQS2_LEFT = IOMUX_PAD(0x1B0,
0x, 1, 0x, 0, 0),
+ MX93_PAD_DAP_TDI__CAN2_TX = IOMUX_PAD(0x1B0,
0x, 3, 0x, 0, 0),
+ MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 = IOMUX_PAD(0x1B0,
0x, 4, 0x, 0, 0),
+ MX93_PAD_DAP_TDI__GPIO3_IO28= IOMUX_PAD(0x1B0,
0x, 5, 0x, 0, 0),
+ MX93_PAD_DAP_TDI__LPUART5_RX= IOMUX_PAD(0x1B0,
0x, 6, 0x430, 0, 0),
+
+ MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS= IOMUX_PAD(0x1B4,
0x0004, 0, 0x3DC, 0, 0),
+ MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31=
[PATCH V4 11/49] gpio: pca953x: support pcal6524
From: Peng Fan
Support pcal6524 IO expander driver
Signed-off-by: Peng Fan
---
drivers/gpio/pca953x_gpio.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index e98e1e56dbc..4654f9e0989 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -43,6 +43,8 @@
#define PCA_GPIO_MASK 0x00FF
#define PCA_INT 0x0100
+#define PCA_PCAL BIT(9)
+#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
#define PCA953X_TYPE0x1000
#define PCA957X_TYPE0x2000
#define PCA_TYPE_MASK 0xF000
@@ -393,6 +395,8 @@ static const struct udevice_id pca953x_ids[] = {
{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
+ { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
+
{ .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
{ .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
--
2.36.0
[PATCH V4 10/49] fsl_lpuart: add i.MX9 support
From: Peng Fan
i.MX9 shares same register layout as i.MX7ULP, so
add the i.MX9 define here.
Signed-off-by: Peng Fan
---
include/fsl_lpuart.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h
index 18e5cc15d61..93c996b764b 100644
--- a/include/fsl_lpuart.h
+++ b/include/fsl_lpuart.h
@@ -5,7 +5,7 @@
*/
#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \
- defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP)
+ defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP) ||
defined(CONFIG_ARCH_IMX9)
struct lpuart_fsl_reg32 {
u32 verid;
u32 param;
--
2.36.0
[PATCH V4 08/49] imx: add USB2_BOOT type
From: Peng Fan
Add USB2_BOOT type for i.MX8ULP and i.MX9
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
arch/arm/mach-imx/imx_romapi.c| 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h
b/arch/arm/include/asm/mach-imx/boot_mode.h
index 6dc58559680..a568c443722 100644
--- a/arch/arm/include/asm/mach-imx/boot_mode.h
+++ b/arch/arm/include/asm/mach-imx/boot_mode.h
@@ -29,6 +29,7 @@ enum boot_device {
QSPI_BOOT,
FLEXSPI_BOOT,
USB_BOOT,
+ USB2_BOOT,
UNKNOWN_BOOT,
BOOT_DEV_NUM = UNKNOWN_BOOT,
};
diff --git a/arch/arm/mach-imx/imx_romapi.c b/arch/arm/mach-imx/imx_romapi.c
index 3b2cc6935dc..0f94091fc53 100644
--- a/arch/arm/mach-imx/imx_romapi.c
+++ b/arch/arm/mach-imx/imx_romapi.c
@@ -50,7 +50,7 @@ enum boot_device get_boot_device(void)
boot_dev = QSPI_BOOT;
break;
case BT_DEV_TYPE_USB:
- boot_dev = USB_BOOT;
+ boot_dev = boot_instance + USB_BOOT;
break;
default:
break;
--
2.36.0
[PATCH V4 07/49] imx: move get_boot_device to common file
From: Peng Fan
i.MX8MN/P/ULP supports ROM API, they have almost same get_boot_device
implementation, so move to a common file. And when support i.MX9,
no need to include the other function copy.
Since sys_proto.h is included in imx_romapi.c, there will be build
warning for i.MX8M because wdog_regs not defined, so include imx-regs.h
in i.MX8M sys_proro.h
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/sys_proto.h | 1 +
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/imx8m/soc.c | 47
arch/arm/mach-imx/imx8ulp/soc.c | 44 ---
arch/arm/mach-imx/imx_romapi.c | 60 +
5 files changed, 62 insertions(+), 91 deletions(-)
create mode 100644 arch/arm/mach-imx/imx_romapi.c
diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h
b/arch/arm/include/asm/arch-imx8m/sys_proto.h
index f8854e77128..55b46afaf78 100644
--- a/arch/arm/include/asm/arch-imx8m/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h
@@ -7,6 +7,7 @@
#define __ARCH_NMX8M_SYS_PROTO_H
#include
+#include
void set_wdog_reset(struct wdog_regs *wdog);
void enable_tzc380(void);
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index aa0b6447f14..c5be63dfe4f 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -242,4 +242,5 @@ obj-$(CONFIG_IMX8M) += imx8m/
obj-$(CONFIG_ARCH_IMX8) += imx8/
obj-$(CONFIG_ARCH_IMXRT) += imxrt/
+obj-$(CONFIG_IMX8MN)$(CONFIG_IMX8MP)$(CONFIG_IMX8ULP) += imx_romapi.o
obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 59335356b57..d2a856f5410 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -599,53 +599,6 @@ int arch_cpu_init(void)
#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
struct rom_api *g_rom_api = (struct rom_api *)0x980;
-
-enum boot_device get_boot_device(void)
-{
- volatile gd_t *pgd = gd;
- int ret;
- u32 boot;
- u16 boot_type;
- u8 boot_instance;
- enum boot_device boot_dev = SD1_BOOT;
-
- ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, ,
- ((uintptr_t)) ^ QUERY_BT_DEV);
- set_gd(pgd);
-
- if (ret != ROM_API_OKAY) {
- puts("ROMAPI: failure at query_boot_info\n");
- return -1;
- }
-
- boot_type = boot >> 16;
- boot_instance = (boot >> 8) & 0xff;
-
- switch (boot_type) {
- case BT_DEV_TYPE_SD:
- boot_dev = boot_instance + SD1_BOOT;
- break;
- case BT_DEV_TYPE_MMC:
- boot_dev = boot_instance + MMC1_BOOT;
- break;
- case BT_DEV_TYPE_NAND:
- boot_dev = NAND_BOOT;
- break;
- case BT_DEV_TYPE_FLEXSPINOR:
- boot_dev = QSPI_BOOT;
- break;
- case BT_DEV_TYPE_SPI_NOR:
- boot_dev = SPI_NOR_BOOT;
- break;
- case BT_DEV_TYPE_USB:
- boot_dev = USB_BOOT;
- break;
- default:
- break;
- }
-
- return boot_dev;
-}
#endif
#if defined(CONFIG_IMX8M)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 35020c9714d..529fda4594e 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -34,50 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
struct rom_api *g_rom_api = (struct rom_api *)0x1980;
-enum boot_device get_boot_device(void)
-{
- volatile gd_t *pgd = gd;
- int ret;
- u32 boot;
- u16 boot_type;
- u8 boot_instance;
- enum boot_device boot_dev = SD1_BOOT;
-
- ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, ,
- ((uintptr_t)) ^ QUERY_BT_DEV);
- set_gd(pgd);
-
- if (ret != ROM_API_OKAY) {
- puts("ROMAPI: failure at query_boot_info\n");
- return -1;
- }
-
- boot_type = boot >> 16;
- boot_instance = (boot >> 8) & 0xff;
-
- switch (boot_type) {
- case BT_DEV_TYPE_SD:
- boot_dev = boot_instance + SD1_BOOT;
- break;
- case BT_DEV_TYPE_MMC:
- boot_dev = boot_instance + MMC1_BOOT;
- break;
- case BT_DEV_TYPE_NAND:
- boot_dev = NAND_BOOT;
- break;
- case BT_DEV_TYPE_FLEXSPINOR:
- boot_dev = QSPI_BOOT;
- break;
- case BT_DEV_TYPE_USB:
- boot_dev = USB_BOOT;
- break;
- default:
- break;
- }
-
- return boot_dev;
-}
-
bool is_usb_boot(void)
{
return get_boot_device() == USB_BOOT;
diff --git a/arch/arm/mach-imx/imx_romapi.c b/arch/arm/mach-imx/imx_romapi.c
new file mode 100644
index 000..3b2cc6935dc
--- /dev/null
+++ b/arch/arm/mach-imx/imx_romapi.c
@@
[PATCH V4 06/49] imx: move get_boot_device to common header
From: Peng Fan
Most i.MX implements get_boot_device, move it to common header to
simplify code
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8/sys_proto.h| 1 -
arch/arm/include/asm/arch-imx8m/sys_proto.h | 1 -
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 -
arch/arm/include/asm/arch-mx7/sys_proto.h | 1 -
arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 1 -
arch/arm/include/asm/mach-imx/sys_proto.h | 2 ++
6 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h
b/arch/arm/include/asm/arch-imx8/sys_proto.h
index 6f1fc8f999d..d38f606e07e 100644
--- a/arch/arm/include/asm/arch-imx8/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -23,7 +23,6 @@ struct pass_over_info_t {
extern unsigned long boot_pointer[];
void build_info(void);
-enum boot_device get_boot_device(void);
int print_bootinfo(void);
int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate);
int imx8_power_domain_lookup_name(const char *name,
diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h
b/arch/arm/include/asm/arch-imx8m/sys_proto.h
index d328542ece2..f8854e77128 100644
--- a/arch/arm/include/asm/arch-imx8m/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h
@@ -12,6 +12,5 @@ void set_wdog_reset(struct wdog_regs *wdog);
void enable_tzc380(void);
void restore_boot_params(void);
extern unsigned long rom_pointer[];
-enum boot_device get_boot_device(void);
bool is_usb_boot(void);
#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 5f030eaa0ad..05859dfc2aa 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -15,7 +15,6 @@ ulong spl_romapi_get_uboot_base(u32 image_offset, u32
rom_bt_dev);
enum bt_mode get_boot_mode(void);
int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
-enum boot_device get_boot_device(void);
void set_lpav_qos(void);
void load_lposc_fuse(void);
bool m33_image_booted(void);
diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h
b/arch/arm/include/asm/arch-mx7/sys_proto.h
index e46a02198d6..634736cc09c 100644
--- a/arch/arm/include/asm/arch-mx7/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx7/sys_proto.h
@@ -8,6 +8,5 @@
#include
void set_wdog_reset(struct wdog_regs *wdog);
-enum boot_device get_boot_device(void);
#endif /* __SYS_PROTO_IMX7_ */
diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
index 0daa922fad9..7adf4720fec 100644
--- a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
@@ -8,5 +8,4 @@
#include
-enum boot_device get_boot_device(void);
#endif
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index fc5e5c66aad..cd69384d8ef 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -243,4 +243,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
void enable_ca7_smp(void);
#endif
+enum boot_device get_boot_device(void);
+
#endif
--
2.36.0
[PATCH V4 05/49] imx: simplify dependency with SPL_BOOTROM_SUPPORT
From: Peng Fan
For SoCs support ROM API, CONFIG_SPL_BOOTROM_SUPPORT is needed,
so use this macro to guard the code to avoid extend the list.
And drop the guard with structure definition, there is no need.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/sys_proto.h | 2 --
arch/arm/mach-imx/Kconfig | 3 ++-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index fdbbfb169cb..fc5e5c66aad 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -146,7 +146,6 @@ struct rproc_att {
u32 size; /* size of reg range */
};
-#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP)
struct rom_api {
u16 ver;
u16 tag;
@@ -178,7 +177,6 @@ enum boot_dev_type_e {
#define ROM_API_OKAY 0xF0
extern struct rom_api *g_rom_api;
-#endif
/* For i.MX ULP */
#define BT0CFG_LPBOOT_MASK 0x1
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ad0fb365023..5e9c4d9b355 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -166,7 +166,8 @@ config DDRMC_VF610_CALIBRATION
config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
- depends on IMX8MN || IMX8MP || IMX8ULP
+ depends on SPL_BOOTROM_SUPPORT
+ default 0
config IMX_DCD_ADDR
hex "DCD Blocks location on the image"
--
2.36.0
[PATCH V4 04/49] imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device
From: Ye Li
Move the default mapping of spl_boot_device to weak function of
spl_board_boot_device. So that every board of iMX7/8/8M can overwrite
this function to implement specific mapping.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/spl.c | 80 -
1 file changed, 38 insertions(+), 42 deletions(-)
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index e89e2277ef7..e5ad993b8d9 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -25,7 +25,43 @@ DECLARE_GLOBAL_DATA_PTR;
__weak int spl_board_boot_device(enum boot_device boot_dev_spl)
{
- return 0;
+ switch (boot_dev_spl) {
+#if defined(CONFIG_MX7)
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ return BOOT_DEVICE_MMC1;
+#elif defined(CONFIG_IMX8)
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ return BOOT_DEVICE_MMC2_2;
+ case SD3_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case FLEXSPI_BOOT:
+ return BOOT_DEVICE_SPI;
+#elif defined(CONFIG_IMX8M)
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC2;
+#endif
+ case NAND_BOOT:
+ return BOOT_DEVICE_NAND;
+ case SPI_NOR_BOOT:
+ return BOOT_DEVICE_SPI;
+ case QSPI_BOOT:
+ return BOOT_DEVICE_NOR;
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
}
#if defined(CONFIG_MX6)
@@ -140,47 +176,7 @@ u32 spl_boot_device(void)
enum boot_device boot_device_spl = get_boot_device();
- if (IS_ENABLED(CONFIG_IMX8MM) || IS_ENABLED(CONFIG_IMX8MN) ||
- IS_ENABLED(CONFIG_IMX8MP))
- return spl_board_boot_device(boot_device_spl);
-
- switch (boot_device_spl) {
-#if defined(CONFIG_MX7)
- case SD1_BOOT:
- case MMC1_BOOT:
- case SD2_BOOT:
- case MMC2_BOOT:
- case SD3_BOOT:
- case MMC3_BOOT:
- return BOOT_DEVICE_MMC1;
-#elif defined(CONFIG_IMX8)
- case MMC1_BOOT:
- return BOOT_DEVICE_MMC1;
- case SD2_BOOT:
- return BOOT_DEVICE_MMC2_2;
- case SD3_BOOT:
- return BOOT_DEVICE_MMC1;
- case FLEXSPI_BOOT:
- return BOOT_DEVICE_SPI;
-#elif defined(CONFIG_IMX8M)
- case SD1_BOOT:
- case MMC1_BOOT:
- return BOOT_DEVICE_MMC1;
- case SD2_BOOT:
- case MMC2_BOOT:
- return BOOT_DEVICE_MMC2;
-#endif
- case NAND_BOOT:
- return BOOT_DEVICE_NAND;
- case SPI_NOR_BOOT:
- return BOOT_DEVICE_SPI;
- case QSPI_BOOT:
- return BOOT_DEVICE_NOR;
- case USB_BOOT:
- return BOOT_DEVICE_BOARD;
- default:
- return BOOT_DEVICE_NONE;
- }
+ return spl_board_boot_device(boot_device_spl);
}
#endif /* CONFIG_MX7 || CONFIG_IMX8M || CONFIG_IMX8 */
--
2.36.0
[PATCH V4 03/49] imx: Change USB boot device type
From: Ye Li The SPL SDP is configured as BOOT_DEVICE_BOARD, so when booting from USB, change its type to BOOT_DEVICE_BOARD, so we can use SDP. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 64ca2967721..e89e2277ef7 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -177,7 +177,7 @@ u32 spl_boot_device(void) case QSPI_BOOT: return BOOT_DEVICE_NOR; case USB_BOOT: - return BOOT_DEVICE_USB; + return BOOT_DEVICE_BOARD; default: return BOOT_DEVICE_NONE; } -- 2.36.0
[PATCH V4 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE
From: Peng Fan
The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE
set to 0x7E1000.
Signed-off-by: Peng Fan
---
common/spl/Kconfig| 1 +
configs/imx8mm-cl-iot-gate-optee_defconfig| 1 -
configs/imx8mm-cl-iot-gate_defconfig | 1 -
configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 -
configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 -
configs/imx8mm-mx8menlo_defconfig | 1 -
configs/imx8mm_beacon_defconfig | 1 -
configs/imx8mm_data_modul_edm_sbc_defconfig | 1 -
configs/imx8mm_evk_defconfig | 1 -
configs/imx8mm_venice_defconfig | 1 -
configs/kontron-sl-mx8mm_defconfig| 1 -
configs/phycore-imx8mm_defconfig | 1 -
configs/verdin-imx8mm_defconfig | 1 -
13 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 3fd56448006..27b3abea87b 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -82,6 +82,7 @@ config SPL_MAX_SIZE
default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x2 && !MACH_SUN50I_H616
default 0x7000 if RCAR_GEN3
default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
+ default 0x27000 if IMX8MM && SPL_TEXT_BASE = 0x7E1000
default 0x0
help
Maximum size of the SPL image (text, data, rodata, and linker lists
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig
b/configs/imx8mm-cl-iot-gate-optee_defconfig
index 80055912096..a02010621ea 100644
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-cl-iot-gate_defconfig
b/configs/imx8mm-cl-iot-gate_defconfig
index dae7ddc20e0..f05ac98326c 100644
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -25,7 +25,6 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
index 69ebc6fa325..7d08b244f2c 100644
--- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb"
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
index a3c142feb28..acc5d34659b 100644
--- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb"
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-mx8menlo_defconfig
b/configs/imx8mm-mx8menlo_defconfig
index ec672f8764e..2a6f3b7c412 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -34,7 +34,6 @@ CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index bf2b6486347..fd21f9f6db8 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -25,7 +25,6 @@ CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run
loadbootscript; then run bootscript; else if run loadimage; then run mmcboot;
else run netboot; fi; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig
b/configs/imx8mm_data_modul_edm_sbc_defconfig
index 399b388460f..1fae936bda5 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -41,7 +41,6 @@ CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
[PATCH V4 02/49] arm: makefile: cleanup mach-imx usage
From: Peng Fan All the SoCs use mach-imx has CONFIG_MACH_IMX selected, so the macro could be the gate to build arch/arm/mach-imx to simplify the rules. Signed-off-by: Peng Fan --- arch/arm/Makefile | 12 ++-- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 64c58f4c4a3..a69cb1f610f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -96,6 +96,8 @@ machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5 +machine-$(CONFIG_MACH_IMX) += imx + machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) @@ -114,16 +116,6 @@ libs-y += arch/arm/cpu/$(CPU)/ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ -ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt)) -libs-y += arch/arm/mach-imx/ -endif -else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imxrt vf610)) -libs-y += arch/arm/mach-imx/ -endif -endif - ifneq (,$(filter $(SOC), kirkwood)) libs-y += arch/arm/mach-mvebu/ endif -- 2.36.0
[PATCH V4 00/49] imx: support i.MX93
From: Peng Fan
V4:
Rebased on Tom's next branch
Include kontron-sl-mx8mm_defconfig in patch 1
Address comments from net maintainers and add R-b
CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/12617
V3:
Fix issue reported by CI build
- Enlarge SPL_MAX_SIZE for i.MX8MM
- Fix i.MX8ULP break
This patchset is to support i.MX93, during the development, there are some
code cleanup and restructure to make i.MX93 code porting cleaner.
i.MX9 is a new i.MX family and i.MX93 is the first one that we would support
in upstream. It features two Cortex-A55 core, one NPU, one M33 and others.
There are some driver changes that also included to make i.MX93 function well,
lpuart/mmc/network.
mkimage also included, but I have not enable BINMAN which is under development,
will post a follow patchset to switch to binman.
Alice Guo (3):
misc: imx8ulp: move fuse.c from imx8ulp to sentinel
misc: fuse: support to access fuse on i.MX93
misc: fuse: update the code for accessing fuse of i.MX93
Jian Li (1):
imx: imx9: Add function to initialize timer
Peng Fan (31):
spl: imx8mm: enlarge SPL_MAX_SIZE
arm: makefile: cleanup mach-imx usage
imx: simplify dependency with SPL_BOOTROM_SUPPORT
imx: move get_boot_device to common header
imx: move get_boot_device to common file
imx: add USB2_BOOT type
imx: add basic i.MX9 support
fsl_lpuart: add i.MX9 support
gpio: pca953x: support pcal6524
imx: pinctrl: add pinctrl and pinfunc file for i.MX93
imx: imx9: Add CCM and clock API support
mmc: fsl_esdhc_imx: Support i.MX9
spl: Use SPL_FIT_IMAGE_TINY for iMX9
imx: imx9: support romapi
misc: s4mu: Support iMX93 with Sentinel MU
misc: S400_API: New API for FW status and chip info
misc: s400_api: introduce ahab_release_m33_trout
imx: imx9: Get the chip revision through S400 API
imx: imx9: Add MIX power init
imx: imx9: Add M33 release prepare function
imx: imx9: Support booting m33 from Acore
arm: dts: Add i.MX93 SoC DTSi file
imx: imx93_evk: Add basic board support
imx: imx93_evk: Set ARM clock to 1.7Ghz
net: fec_mxc: support i.MX93
net: dwc_eth_qos: fix build break when CLK not enabled
net: dwc_eth_qos: public some functions
net: dwc_eth_qos: move i.MX code out
net: dwc_eth_qos: introduce eqos hook eqos_get_enetaddr
board: freescale: imx93_evk: support ethernet
tools: image: support i.MX93
Ye Li (14):
imx: Change USB boot device type
imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device
imx: imx9: disable watchdog
misc: imx: S400_API: Move S400 MU and API to a common place
misc: S400_API: Update release RDC API
imx: imx9: Add TRDC driver for TRDC init
imx: imx9: Add AHAB boot support
misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg
imx: imx9: Add gpio registers structure
imx: imx9: Support multiple env storages at runtime
imx: imx9: clock: Add DDR clock support
ddr: imx: Add i.MX9 DDR controller driver
ddr: imx9: enable Performance monitor counter
net: eqos: add function to get phy node and address
arch/arm/Kconfig | 16 +
arch/arm/Makefile | 12 +-
arch/arm/dts/Makefile |3 +
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 157 ++
arch/arm/dts/imx93-11x11-evk.dts | 527 ++
arch/arm/dts/imx93-pinfunc.h | 625 +++
arch/arm/dts/imx93.dtsi | 688
arch/arm/include/asm/arch-imx/cpu.h |2 +
arch/arm/include/asm/arch-imx8/sys_proto.h|1 -
arch/arm/include/asm/arch-imx8m/ddr.h |6 +-
arch/arm/include/asm/arch-imx8m/sys_proto.h |2 +-
arch/arm/include/asm/arch-imx8ulp/sys_proto.h |5 -
arch/arm/include/asm/arch-imx9/ccm_regs.h | 266 +++
arch/arm/include/asm/arch-imx9/clock.h| 244 +++
arch/arm/include/asm/arch-imx9/ddr.h | 126 ++
arch/arm/include/asm/arch-imx9/gpio.h | 20 +
arch/arm/include/asm/arch-imx9/imx-regs.h | 234 +++
arch/arm/include/asm/arch-imx9/imx93_pins.h | 729
arch/arm/include/asm/arch-imx9/sys_proto.h| 14 +
arch/arm/include/asm/arch-imx9/trdc.h | 19 +
arch/arm/include/asm/arch-mx7/sys_proto.h |1 -
arch/arm/include/asm/arch-mx7ulp/sys_proto.h |1 -
arch/arm/include/asm/global_data.h|5 +-
arch/arm/include/asm/mach-imx/boot_mode.h |1 +
arch/arm/include/asm/mach-imx/iomux-v3.h | 11 +-
.../asm/{arch-imx8ulp => mach-imx}/mu_hal.h |4 +-
.../asm/{arch-imx8ulp => mach-imx}/s400_api.h | 18 +-
arch/arm/include/asm/mach-imx/sys_proto.h | 11 +-
arch/arm/mach-imx/Kconfig |3 +-
arch/arm/mach-imx/Makefile| 10 +-
arch/arm/mach-imx/imx8m/soc.c | 47 -
arch/arm/mach-imx/imx8ulp/ahab.c | 345
arch/arm/mach-imx/imx8ulp/rdc.c |6 +-
arch/arm/mach-imx/imx8ulp/soc.c
Re: uuu using u-boot-with-spl.imx
Hi On Tue, Jul 5, 2022 at 3:20 AM Peng Fan wrote: > > > > On 7/4/2022 7:00 PM, Michael Nazzareno Trimarchi wrote: > > Hi Fabio and Marek > > > > Trying to understand the reason why I can boot using imx_usb loader > > and not the uuu tool > > How do you use uuu? uuu -b sd flash.bin? sudo uuu -b nand u-boot-with-spl.imx U-Boot SPL 2022.07-rc5-00075-gf7d0e40577-dirty (Jul 05 2022 - 06:29) >>SPL: board_init_r() spl_init Trying to boot from USB SDP SDP: initialize... SDP: handle requests... Downloading file of size 624512 to 0x877fffc0... done Jumping to header at 0x877fffc0 Header Tag is not an IMX image Found header at 0x877fffc0 mkimage signature not found - ih_magic = 0 image entry point: 0x8780 Does not depend on SDP_ADDRESS even because default has no sense now is 0. I have chosen TEXT_BASE - HEADERSIZE Michael > > Regards, > Peng. > > > > > If I do: > > > > ./imx_usb SPL > > ./imx_usb u-boot-dtb.img > > > > It works > > > > U-Boot SPL 2022.07-rc5-00075-g01d253835a-dirty (Jul 04 2022 - 12:39: > > 11 +0200) > >>> SPL: board_init_r() > > spl_init > > Trying to boot from USB SDP > > SDP: initialize... > > SDP: handle requests... > > Downloading file of size 594824 to 0x877fffc0... done > > Jumping to header at 0x877fffc0 > > Header Tag is not an IMX image > > Found header at 0x877fffc0 > > image entry point: 0x8780 > > > > > > U-Boot 2022.07-rc5-00075-g01d253835a-dirty (Jul 04 2022 - 12:39:11 + > > 0200) > > > > CPU: Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz) > > CPU: Commercial temperature grade (0C to 95C) at 37C > > Reset cause: POR > > Model: BSH SMM M2 > > DRAM: 128 MiB > > Core: 29 devices, 14 uclasses, devicetree: separate > > NAND: 256 MiB > > MMC: FSL_SDHC: 1 > > Loading Environment from NAND... *** Warning - bad CRC, using defaul > > t environment > > > > In:serial@21f > > Out: serial@21f > > Err: serial@21f > > Net: CPU Net Initialization Failed > > No ethernet found. > > Hit any key to stop autoboot > > > > If I tried with the combined image using uuu it does not work like that. > > > > U-Boot SPL 2022.07-rc5-00075-g01d253835a-dirty (Jul 04 2022 - 12:39: > > 11 +0200) > >>> SPL: board_init_r() > > spl_init > > Trying to boot from USB SDP > > SDP: initialize... > > SDP: handle requests... > > Downloading file of size 594824 to 0x877fffc0... done > > Jumping to header at 0x877fffc0 > > Header Tag is not an IMX image > > Found header at 0x877fffc0 > > image entry point: 0x8780 > > > > > > Any idea? > > > > Michael -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 mich...@amarulasolutions.com __ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH v6 00/13] FWU: Add FWU Multi Bank Update feature support
On Mon, Jul 04, 2022 at 10:46:45AM +0530, Sughosh Ganu wrote: > > The patchset adds support for the FWU Multi Bank Update[1] > feature. Certain aspects of the Dependable Boot[2] specification have > also been implemented. > > The FWU multi bank update feature is used for supporting multiple > sets(also called banks) of firmware image(s), allowing the platform to > boot from a different bank, in case it fails to boot from the active > bank. This functionality is supported by keeping the relevant > information in a structure called metadata, which provides information > on the images. Among other parameters, the metadata structure contains > information on the currect active bank that is being used to boot > image(s). > > Functionality is being added to work with the UEFI capsule driver in > u-boot. The metadata is read to gather information on the update bank, > which is the bank to which the firmware images would be flashed to. On > a successful completion of the update of all components, the active > bank field in the metadata is updated, to reflect the bank from which > the platform will boot on the subsequent boots. > > Currently, the feature is being enabled on the STM32MP157C-DK2 and > Synquacer boards. The DK2 board boots a FIP image from a uSD card > partitioned with the GPT partioning scheme, while the Synquacer board > boots a FIP image from a MTD partitioned SPI NOR flash device. > > This feature also requires changes in a previous stage of > bootloader, which parses the metadata and selects the bank to boot the > image(s) from. Support has being added in tf-a(BL2 stage) for the > STM32MP157C-DK2 board to boot the active bank images. These changes > have been merged to the upstream tf-a repository. > > The earlier patchset contained patches for both the DK2 and the > Synquacer platforms. The handling of review comments for the Synquacer > platform is to be taken up by a different engineer, and has not been > done yet. After discussion with Tom Rini and Heinrich, it was decided > to send the patches for the DK2 platform separately for review. The > patch for adding a python test for the feature has been developed, and > was sent in the version 5 of the patches[3]. However, the test script > depends on adding support for the feature on MTD SPI NOR devices, and > that is being done as part of the Synquacer patches. Hence these set > of patches do not have the test script for the feature. That will be > added through the patches for adding support for the feauture on > Synquacer platform. > > [1] - https://developer.arm.com/documentation/den0118/a > [2] - > https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24e18d4319e108a758d02e/mbfw.pdf > [3] - https://lists.denx.de/pipermail/u-boot/2022-June/485992.html > > Changes since V5: > * Changed to yaml file from txt as per review comment > * Change the parameter to the function fwu_plat_get_alt_num to pass > the FWU udevice pointer instead of passing the metadata device > directly. > * Changed the logic to store the GPT partitioned block device through > a priv structure as suggested by Patrick > * Used dev_read_prop() to get the phandle_p instead of > ofnode_get_property() used earlier as suggested by Patrick > * Made relevant functions static as suggested by Etienne > * Change the mechanism to get the block device descriptor in > fwu_plat_get_alt_num() due to introduction of struct > fwu_mdata_gpt_blk_priv in the earlier patch. > * Shuffled the location of the TAMP_FWU_* macros as suggested by > Patrick > * Use u"TrialStateCtr" for the EFI variable name as suggested by > Patrick > * Dropped the call to uclass_get_device() in fwu_boottime_checks() as > suggested by Patrick > * Pass NULL instead of a pointer to trial_state_ctr variable when > deleting the variable as suggested by Etienne > * Use u"TrialStateCtr" as suggested by Patrick > * Do a metadata validity check by calling fwu_mdata_check() before > printing the FWU metadata as suggested by Michal > * Use ret and res variables in do_fwu_mdata_read() as suggested by > Patrick > * Change 'default y if FWU_MULTI_BANK_UPDATE' to default y as > suggested by Patrick > * Use capsule_type instead of capsule variable that was created > earlier to check for the type of capsule > * Remove use of payload variable in create_empty_capsule() as > suggested by Etienne > * Initialise the struct efi_capsule_header as suggested by Etienne > * Add some description about the reasoning for accept capsule needing > image GUID as suggested by Takahiro Thanks, but I don't still understand why we need GUID here as I said in https://lists.denx.de/pipermail/u-boot/2022-June/486733.html We need discussions. -Takahiro Akashi > > Sughosh Ganu (13): > dt/bindings: Add bindings for FWU Metadata storage device > FWU: Add FWU metadata structure and driver for accessing metadata > FWU: Add FWU metadata access driver for GPT partitioned block devices >
Re: [PATCH V2 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE
On 7/5/2022 9:35 AM, Peng Fan (OSS) wrote: On 6/29/2022 6:09 PM, Frieder Schrempf wrote: Am 27.06.22 um 05:24 schrieb Peng Fan (OSS): From: Peng Fan The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE set to 0x7E1000. Signed-off-by: Peng Fan --- common/spl/Kconfig| 1 + configs/imx8mm-cl-iot-gate-optee_defconfig| 1 - configs/imx8mm-cl-iot-gate_defconfig | 1 - configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 - configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 - configs/imx8mm-mx8menlo_defconfig | 1 - configs/imx8mm_beacon_defconfig | 1 - configs/imx8mm_data_modul_edm_sbc_defconfig | 1 - configs/imx8mm_evk_defconfig | 1 - configs/imx8mm_venice_defconfig | 1 - configs/phycore-imx8mm_defconfig | 1 - configs/verdin-imx8mm_defconfig | 1 - 12 files changed, 1 insertion(+), 11 deletions(-) Is there any reason, why you didn't include kontron-sl-mx8mm_defconfig in this patch? No specific reason. I may overlook kontron-sl-mx8mm_defconfig, but it not matter. The reason I did this patch, is a few boards reached its size limitation, so I enlarge to avoid build break. keep kontron-sl-mx8mm_defconfig as 0x25000 or move to 0x27000, both are ok. If you wanna enlarge, please do a new patch, I not wanna respin this large patchset, unless there are some major comments. Just rebase the patchset based on origin/next, and also see a few comments from Net maintainer. Will respin this patchset, so I will include kontron-sl-mx8mm_defconfig. Thanks, Peng. Thanks, Peng.
Re: [PATCH V2 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE
On 6/29/2022 6:09 PM, Frieder Schrempf wrote: Am 27.06.22 um 05:24 schrieb Peng Fan (OSS): From: Peng Fan The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE set to 0x7E1000. Signed-off-by: Peng Fan --- common/spl/Kconfig| 1 + configs/imx8mm-cl-iot-gate-optee_defconfig| 1 - configs/imx8mm-cl-iot-gate_defconfig | 1 - configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 - configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 - configs/imx8mm-mx8menlo_defconfig | 1 - configs/imx8mm_beacon_defconfig | 1 - configs/imx8mm_data_modul_edm_sbc_defconfig | 1 - configs/imx8mm_evk_defconfig | 1 - configs/imx8mm_venice_defconfig | 1 - configs/phycore-imx8mm_defconfig | 1 - configs/verdin-imx8mm_defconfig | 1 - 12 files changed, 1 insertion(+), 11 deletions(-) Is there any reason, why you didn't include kontron-sl-mx8mm_defconfig in this patch? No specific reason. I may overlook kontron-sl-mx8mm_defconfig, but it not matter. The reason I did this patch, is a few boards reached its size limitation, so I enlarge to avoid build break. keep kontron-sl-mx8mm_defconfig as 0x25000 or move to 0x27000, both are ok. If you wanna enlarge, please do a new patch, I not wanna respin this large patchset, unless there are some major comments. Thanks, Peng.
[GIT PULL] please pull fsl-qoriq-2022-7-3
Hi Tom, Please pull fsl-qoriq-2022-7-3 based on your next branch for 2022.10 CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/12603 -- Several patches from Pali - fsl_elbc detection fix - sort p2020 dts node, drop duplicated node - p1_p2_rdb_pc board cleanup - simplify mpc85xx _start_cont jumping code -- The following changes since commit 284c1a9b4b91120385c346a1924628a695314905: Merge tag 'u-boot-at91-2022.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next (2022-06-30 15:21:52 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git tags/fsl-qoriq-2022-7-3 for you to fetch changes up to 9167a1c28c2751b97ac48da5384e540e714a752a: powerpc: mpc85xx: Simplify jump to _start_cont in flash code (2022-07-03 15:13:51 +0800) Pali Rohár (7): mtd: rawnand: fsl_elbc: Fix detection when nand_scan_ident() has not selected ecc.mode powerpc: dts: p2020: Sort DT nodes by their addresses powerpc: dts: p2020: Remove duplicate pic@4 node board: freescale: p1_p2_rdb_pc: Allow to compile without BOARD_NAME board: freescale: p1_p2_rdb_pc: Allow to compile without __SW_BOOT_SD macro board: freescale: p1_p2_rdb_pc: Remove mapping for TDM-PMC card powerpc: mpc85xx: Simplify jump to _start_cont in flash code arch/powerpc/cpu/mpc85xx/start.S| 5 ++--- arch/powerpc/dts/p2020-post.dtsi| 77 + board/freescale/p1_p2_rdb_pc/law.c | 1 - board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 11 +-- board/freescale/p1_p2_rdb_pc/tlb.c | 3 --- drivers/mtd/nand/raw/fsl_elbc_nand.c| 6 +- include/configs/p1_p2_rdb_pc.h | 9 - scripts/config_whitelist.txt| 4 8 files changed, 49 insertions(+), 67 deletions(-)
Re: uuu using u-boot-with-spl.imx
On 7/4/2022 7:00 PM, Michael Nazzareno Trimarchi wrote: Hi Fabio and Marek Trying to understand the reason why I can boot using imx_usb loader and not the uuu tool How do you use uuu? uuu -b sd flash.bin? Regards, Peng. If I do: ./imx_usb SPL ./imx_usb u-boot-dtb.img It works U-Boot SPL 2022.07-rc5-00075-g01d253835a-dirty (Jul 04 2022 - 12:39: 11 +0200) SPL: board_init_r() spl_init Trying to boot from USB SDP SDP: initialize... SDP: handle requests... Downloading file of size 594824 to 0x877fffc0... done Jumping to header at 0x877fffc0 Header Tag is not an IMX image Found header at 0x877fffc0 image entry point: 0x8780 U-Boot 2022.07-rc5-00075-g01d253835a-dirty (Jul 04 2022 - 12:39:11 + 0200) CPU: Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 37C Reset cause: POR Model: BSH SMM M2 DRAM: 128 MiB Core: 29 devices, 14 uclasses, devicetree: separate NAND: 256 MiB MMC: FSL_SDHC: 1 Loading Environment from NAND... *** Warning - bad CRC, using defaul t environment In:serial@21f Out: serial@21f Err: serial@21f Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot If I tried with the combined image using uuu it does not work like that. U-Boot SPL 2022.07-rc5-00075-g01d253835a-dirty (Jul 04 2022 - 12:39: 11 +0200) SPL: board_init_r() spl_init Trying to boot from USB SDP SDP: initialize... SDP: handle requests... Downloading file of size 594824 to 0x877fffc0... done Jumping to header at 0x877fffc0 Header Tag is not an IMX image Found header at 0x877fffc0 image entry point: 0x8780 Any idea? Michael
Re: [PATCH 1/1] avb: honor CONFIG_SYS_64BIT_LBA
On Mon, Jul 04, 2022 at 08:37:48PM +0200, Heinrich Schuchardt wrote:
>
>
> On 7/4/22 14:19, Tom Rini wrote:
> > On Sat, Jul 02, 2022 at 03:28:32PM +0200, Heinrich Schuchardt wrote:
> >
> > > The size of lbaint_t depends on CONFIG_SYS_64BIT_LBA defined in common.h.
> > > common.h should always be included as first include.
> > >
> > > Signed-off-by: Heinrich Schuchardt
> > > ---
> > > common/avb_verify.c | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/common/avb_verify.c b/common/avb_verify.c
> > > index 0520a71455..6d11e31687 100644
> > > --- a/common/avb_verify.c
> > > +++ b/common/avb_verify.c
> > > @@ -4,6 +4,7 @@
> > >* SPDX-License-Identifier: GPL-2.0+
> > >*/
> > > +#include
> > > #include
> > > #include
> > > #include
> >
> > Did you find a problem here, by inspection? If so, OK, I'll take this
> > for master. Otherwise, please drop common.h from the file and see what
> > includes it needs directly, given that -next has the CONFIG symbol in
> > question migrated to Kconfig and so solves the overall problem.
> >
>
> You already merged
> 054de212cef6 ("disk: honor CONFIG_SYS_64BIT_LBA").
> I looked for other uses of blk.h without prior inclusion of common.h.
>
> Migration to Kconfig does not move the definition of CONFIG_SYS_64BIT_LBA
> into blk.h but keeps it in common.h. So the correct size of lbaint_t will
> still depend on including common.h.
Wait, I don't follow, sorry. Can you please reproduce the problem you
have, on next? CONFIG_SYS_64BIT_LBA is defined in Kconfig in next, so
it will always be defined (or not) before any header is used because of
-include.
And as a follow-up, nothing should be using as it's only
including other headers, so files and headers should include what they
need directly.
--
Tom
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Re: [PATCH 1/1] xen: pvblock: honor CONFIG_SYS_64BIT_LBA
On 7/4/22 14:19, Tom Rini wrote:
On Sat, Jul 02, 2022 at 03:23:42PM +0200, Heinrich Schuchardt wrote:
CONFIG_SYS_64BIT_LBA is defined in common.h and used to define the size of
lbaint_t in blk.h. On 32-bit system not including common.h first will lead
to differences in the size of lbaint_t between modules.
common.h should always be the first include.
Signed-off-by: Heinrich Schuchardt
---
cmd/pvblock.c | 2 +-
drivers/xen/pvblock.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/cmd/pvblock.c b/cmd/pvblock.c
index 56ce8b18d5..ccdd6304af 100644
--- a/cmd/pvblock.c
+++ b/cmd/pvblock.c
@@ -5,8 +5,8 @@
* XEN para-virtualized block device support
*/
-#include
#include
+#include
#include
/* Current I/O Device */
diff --git a/drivers/xen/pvblock.c b/drivers/xen/pvblock.c
index c25c3ea4ff..c0a156fbf7 100644
--- a/drivers/xen/pvblock.c
+++ b/drivers/xen/pvblock.c
@@ -6,8 +6,8 @@
#define LOG_CATEGORY UCLASS_PVBLOCK
-#include
#include
+#include
#include
#include
#include
Did you find a problem here, by inspection? If so, OK, I'll take this
for master. Otherwise, please drop common.h from the file and see what
includes it needs directly, given that -next has the CONFIG symbol in
question migrated to Kconfig and so solves the overall problem.
You already merged
054de212cef6 ("disk: honor CONFIG_SYS_64BIT_LBA").
I looked for other uses of blk.h without prior inclusion of common.h.
Migration to Kconfig does not move the definition of
CONFIG_SYS_64BIT_LBA into blk.h but keeps it in common.h. So the correct
size of lbaint_t will still depend on including common.h.
Best regards
Heinrich
Re: [PATCH 1/1] avb: honor CONFIG_SYS_64BIT_LBA
On 7/4/22 14:19, Tom Rini wrote:
On Sat, Jul 02, 2022 at 03:28:32PM +0200, Heinrich Schuchardt wrote:
The size of lbaint_t depends on CONFIG_SYS_64BIT_LBA defined in common.h.
common.h should always be included as first include.
Signed-off-by: Heinrich Schuchardt
---
common/avb_verify.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 0520a71455..6d11e31687 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include
#include
#include
#include
Did you find a problem here, by inspection? If so, OK, I'll take this
for master. Otherwise, please drop common.h from the file and see what
includes it needs directly, given that -next has the CONFIG symbol in
question migrated to Kconfig and so solves the overall problem.
You already merged
054de212cef6 ("disk: honor CONFIG_SYS_64BIT_LBA").
I looked for other uses of blk.h without prior inclusion of common.h.
Migration to Kconfig does not move the definition of
CONFIG_SYS_64BIT_LBA into blk.h but keeps it in common.h. So the correct
size of lbaint_t will still depend on including common.h.
Best regards
Heinrich
Re: uuu using u-boot-with-spl.imx
Hi Fabio
I have managed to boot with this lts
uuu_version 1.2.39
# @_flash.bin| bootloader
# @_uboot.bin| uboot.dtb
# @_image [_flash.bin] | image burn to nand, default is the same as bootloader
# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ
SDP: boot -f _flash.bin
# These commands will be run when use SPL and will be skipped if no spl
# if (SPL support SDPV)
# {
SDPV: delay 1000
SDPV: write -f _uboot.bin
SDPV: jump
# }
FB: ucmd setenv fastboot_buffer ${loadaddr}
FB: download -f _image
FB: ucmd if test -z "$fastboot_bytes"; then setenv fastboot_bytes $filesize; fi
# Burn image to nandfit partition if needed
FB: ucmd if env exists nandfit_part; then nand erase.part nandfit;
nand write ${fastboot_buffer} nandfit ${fastboot_bytes}; else true;
fi;
FB: ucmd nandbcb init ${fastboot_buffer} nandboot ${fastboot_bytes}
FB: Done
and using
sudo uuu -b nand_spl.lst SPL u-boot-dtb.img u-boot-with-spl.imx
I need to arrange the UBOOT_OFFS and OFFS_REDUNT position to take into
account the padding of 0x11000 and the two copies of nandbcb tools.
Do you know how others are flashing nand on the imx6 family?
Michael
On Mon, Jul 4, 2022 at 1:00 PM Michael Nazzareno Trimarchi
wrote:
>
> Hi Fabio and Marek
>
> Trying to understand the reason why I can boot using imx_usb loader
> and not the uuu tool
>
> If I do:
>
> ./imx_usb SPL
> ./imx_usb u-boot-dtb.img
>
> It works
>
> U-Boot SPL 2022.07-rc5-00075-g01d253835a-dirty (Jul 04 2022 - 12:39:
> 11 +0200)
> >>SPL: board_init_r()
> spl_init
> Trying to boot from USB SDP
> SDP: initialize...
> SDP: handle requests...
> Downloading file of size 594824 to 0x877fffc0... done
> Jumping to header at 0x877fffc0
> Header Tag is not an IMX image
> Found header at 0x877fffc0
> image entry point: 0x8780
>
>
> U-Boot 2022.07-rc5-00075-g01d253835a-dirty (Jul 04 2022 - 12:39:11 +
> 0200)
>
> CPU: Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz)
> CPU: Commercial temperature grade (0C to 95C) at 37C
> Reset cause: POR
> Model: BSH SMM M2
> DRAM: 128 MiB
> Core: 29 devices, 14 uclasses, devicetree: separate
> NAND: 256 MiB
> MMC: FSL_SDHC: 1
> Loading Environment from NAND... *** Warning - bad CRC, using defaul
> t environment
>
> In:serial@21f
> Out: serial@21f
> Err: serial@21f
> Net: CPU Net Initialization Failed
> No ethernet found.
> Hit any key to stop autoboot
>
> If I tried with the combined image using uuu it does not work like that.
>
> U-Boot SPL 2022.07-rc5-00075-g01d253835a-dirty (Jul 04 2022 - 12:39:
> 11 +0200)
> >>SPL: board_init_r()
> spl_init
> Trying to boot from USB SDP
> SDP: initialize...
> SDP: handle requests...
> Downloading file of size 594824 to 0x877fffc0... done
> Jumping to header at 0x877fffc0
> Header Tag is not an IMX image
> Found header at 0x877fffc0
> image entry point: 0x8780
>
>
> Any idea?
>
> Michael
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
Re: Building host tools on Windows
On Mon, Jul 4, 2022 at 9:50 PM Martin Bonner wrote: > > I am trying to build the host tools on Windows, and I have hit a road > block. Specifically, I get the output: > HOSTCC tools/mkeficapsule > tools/mkeficapsule.c:18:10: fatal error: uuid/uuid.h: No such file or > directory >18 | #include > > Steps so far: > Download latest msys > Double upgrade with "pacman -Syu" > pacman -S gcc make bison diffutils openssl-devel > pacman -S git > git clone from denx.de > pacman -S flex (because make complained "flex was missing" > > Now I have the above error. I am not familiar with MSYS packages - I have > tried "e2fsprogs" and "uuid-dev" but neither are found. Which package do I > need to include? Please do: pacman -S libgnutls-devel libuuid-devel as what is done in the CI. Regards, Bin
Re: [PATCH 4/8] board: qualcomm: Add support for dragonboard845c
On Mon, Jul 04, 2022 at 06:28:41PM +0530, Sumit Garg wrote:
> diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi
> b/arch/arm/dts/dragonboard845c-uboot.dtsi
> new file mode 100644
> index 00..8b5a7ee573
> --- /dev/null
> +++ b/arch/arm/dts/dragonboard845c-uboot.dtsi
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * U-Boot addition to handle Qualcomm Robotics RB3 Development Platform
> + * (dragonboard845c) pins
> + *
> + * (C) Copyright 2022 Sumit Garg
> + */
> +
> +/
> +{
> + soc {
> + u-boot,dm-pre-reloc;
> +
> + serial@a84000 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + clock-controller@10 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + pinctrl_north@390 {
> + u-boot,dm-pre-reloc;
> + };
> + };
> +};
These additional u-boot,dm-pre-reloc changes are different to the ones
that appear in starqltechn-uboot.dtsi . That suggests that either patch 1
is not actually removing redundant properties or that the DB845C port is
wrong.
> +config TARGET_DRAGONBOARD845C
> + bool "96Boards Dragonboard 845C"
> + help
> + Support for 96Boards Dragonboard 845C aka Robotics RB3 Development
> + Platform. This board complies with 96Board Open Platform
Nitpicking but... s/96Board/96Boards/
Daniel.
Re: [PATCH 1/8] arm64: dts: sdm845: Remove redundant u-boot DT properties
On Mon, Jul 04, 2022 at 06:28:38PM +0530, Sumit Garg wrote:
> U-boot specific DT properties belong to *-uboot.dtsi
... and are already included in starqltechn-uboot.dtsi (which is the
only current consumer of sdm845.dtsi).
Adding fuller comments, such as the above, makes things much easier to
review: it makes clear why you consider the properties redundant rather
then misfiled.
Daniel.
> , so remove
> corresponding redundant properties.
>
> Signed-off-by: Sumit Garg
> ---
> arch/arm/dts/sdm845.dtsi | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
> index 6f2fb20d68..88030156d9 100644
> --- a/arch/arm/dts/sdm845.dtsi
> +++ b/arch/arm/dts/sdm845.dtsi
> @@ -18,7 +18,6 @@
> compatible = "simple-bus";
>
> gcc: clock-controller@10 {
> - u-boot,dm-pre-reloc;
> compatible = "qcom,gcc-sdm845";
> reg = <0x10 0x1f>;
> #clock-cells = <1>;
> @@ -27,7 +26,6 @@
> };
>
> gpio_north: gpio_north@390 {
> - u-boot,dm-pre-reloc;
> #gpio-cells = <2>;
> compatible = "qcom,sdm845-pinctrl";
> reg = <0x390 0x40>;
> @@ -38,7 +36,6 @@
> };
>
> tlmm_north: pinctrl_north@390 {
> - u-boot,dm-pre-reloc;
> compatible = "qcom,tlmm-sdm845";
> reg = <0x390 0x40>;
> gpio-count = <150>;
> --
> 2.25.1
>
Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver
Hello Chin-Ting, On 7/3/22 10:47, Chin-Ting Kuo wrote: Hi Cédric, Thanks for the review. -Original Message- From: Cédric Le Goater Sent: Friday, July 1, 2022 5:28 PM To: Chin-Ting Kuo ; ChiaWei Wang ; lu...@denx.de; sean...@gmail.com; Ryan Chen ; BMC-SW ; ja...@amarulasolutions.com; vigne...@ti.com; u-boot@lists.denx.de; p.ya...@ti.com Subject: Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver Hello Chin-Ting, On 5/24/22 07:56, Chin-Ting Kuo wrote: Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. Signed-off-by: Chin-Ting Kuo I would split the patch furthermore to ease reading. Okay, this will be update in the next version. 1 - Add basic support with default decoding ranges set for all possible CS, even without a device. WE only have USER mode for now. So it's not important to correctly set the ranges since we won't use them before direct mapping is introduced. They should not overlap, that's all. 2 - decoding range adjustments On that topic, we might want to take the simple DT approach with a "ranges" property defining the mapping windows of each CE. I think it is safer than trying to compute perfect ranges like on Linux. 3 - clock settings That should simply be the property defined in the DT --- v2: Remove defconfig files from this patch. drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-aspeed.c | 822 +++ 3 files changed, 831 insertions(+) create mode 100644 drivers/spi/spi-aspeed.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1e515cb2b..a616294910 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -387,6 +387,14 @@ config SANDBOX_SPI }; }; +config SPI_ASPEED + bool "ASPEED SPI controller driver" + depends on DM_SPI && SPI_MEM + default n + help + Enable ASPEED SPI controller driver for AST2500 + and AST2600 SoCs. + config SPI_SIFIVE bool "SiFive SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06e81b465b..36a4bd5dce 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -9,6 +9,7 @@ obj-y += spi-uclass.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o obj-$(CONFIG_SOFT_SPI) += soft_spi.o +obj-$(CONFIG_SPI_ASPEED) += spi-aspeed.o obj-$(CONFIG_SPI_MEM) += spi-mem.o obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o diff --git a/drivers/spi/spi-aspeed.c
[PATCH] doc: board: amlogic: add documentation on boot flow
This is a preliminary documentation introducing different boot sequences, and notably the recovery mode. Signed-off-by: Neil Armstrong --- doc/board/amlogic/boot-flow.rst | 147 doc/board/amlogic/index.rst | 1 + 2 files changed, 148 insertions(+) create mode 100644 doc/board/amlogic/boot-flow.rst diff --git a/doc/board/amlogic/boot-flow.rst b/doc/board/amlogic/boot-flow.rst new file mode 100644 index 00..32943f42db --- /dev/null +++ b/doc/board/amlogic/boot-flow.rst @@ -0,0 +1,147 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Amlogic SoC Boot Flow += + +The Amlogic SoCs has a pre-defined boot sequence in the SoC ROM code. + +Here is the possible boot sources of different SoC families supported by U-Boot: + +GX* & AXG family + + ++--++---+---+---+---+ +| | 1| 2 | 3 |4 | 5 | ++==++===+===+===+===+ +| S905 | POC=0: SPI NOR | eMMC | NAND | SD Card | USB Device | +| S905X|| | | | | +| S905L|| | | | | +| S905W|| | | | | +| S912 || | | | | ++--++---+---+---+---+ +| S805X| POC=0: SPI NOR | eMMC | NAND | USB Device| - | +| A113D|| | | | | +| A113X|| | | | | ++--++---+---+---+---+ + +POC pin: `NAND_CLE` + +Usually boards provides a button to force USB BOOT which disables eMMC clock signal to +bypass eMMC. + +Most of the GX SBCs have removable eMMC modules, in this case removing the eMMC and SDCard +will boot over USB. + +An exception is the lafrite board (aml-s805x-xx) which doesn't have an SDCard and boots +over SPI. The only ways to boot over USB are: + + - erase first sectors of SPI NOR flash + - insert an HDMI boot plug forcing boot over USB + +The VIM1 and initial VIM2 boards provides a test point on the eMMC signals to block the +storage from answering and continue to the next boot step. + +The USB Device boot uses the first USB interface, on some boards this port is only +available on an USB-A type connector, and needs an special Type-A to Type-A cable +to communicate with the BootROM. + +G12* & SM1 family +- + ++---+---+---+---+---+---+---+ +| POC0 | POC1 | POC2 | 1 | 2 | 3 | 4 | ++===+===+===+===+===+===+===+ +| 0 | 0 | 0 | USB Device| SPI NOR | NAND/eMMC | SDCard| ++---+---+---+---+---+---+---+ +| 0 | 0 | 1 | USB Device| NAND/eMMC | SDCard| - | ++---+---+---+---+---+---+---+ +| 0 | 1 | 0 | SPI NOR | NAND/eMMC | SDCard| USB Device| ++---+---+---+---+---+---+---+ +| 0 | 1 | 1 | SPI NAND | NAND/eMMC | USB Device| - | ++---+---+---+---+---+---+---+ +| 1 | 0 | 0 | USB Device| SPI NOR | NAND/eMMC | SDCard| ++---+---+---+---+---+---+---+ +| 1 | 0 | 1 | USB Device| NAND/eMMC | SDCard| - | ++---+---+---+---+---+---+---+ +| 1 | 1 | 0 | SPI NOR | NAND/eMMC | SDCard| USB Device| ++---+---+---+---+---+---+---+ +| 1 | 1 | 1 | NAND/eMMC | SDCard| USB Device| - | ++---+---+---+---+---+---+---+ + +The last is the normal default boot on production devices. + + * POC0 pin: `BOOT_4` (0 and all other 1 means SPI NAND boot first) + * POC1 pin: `BOOT_5` (0 and all other 1 means USB Device boot first + * POC2 pin: `BOOT_6` (0 and all other 1 means SPI NOR boot first) + +Usually boards provides a button to force USB BOOT which lowers `BOOT_5` to 0. + +Some boards provides a test point on the eMMC or SPI NOR clock signals to block the +storage from answering and
[PATCH] arm64: zynqmp: Enable SLG gpo driver by default
This device is used on SOM CCs that's why enable it by default. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 855a1c97731a..2763346f785f 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -138,6 +138,7 @@ CONFIG_FPGA_ZYNQMPPL=y CONFIG_GPIO_HOG=y CONFIG_XILINX_GPIO=y CONFIG_DM_PCA953X=y +CONFIG_SLG7XL45106_I2C_GPO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_I2C_MUX=y -- 2.36.1
Re: dtboverlay to U-Boot runtime dtb
On 7/4/22 15:39, Tom Rini wrote: On Mon, Jul 04, 2022 at 03:27:26PM +0200, Heinrich Schuchardt wrote: On 7/4/22 14:51, Peter Robinson wrote: Hi Peng, I did a test to do overlay for U-Boot runtime dtb, but after overlay finish, U-Boot DM driver not work properly because the of_node pointer is changed in a device. So I am thinking whether this is valid to overlay to runtime U-Boot dtb or not. The reason I try this is that I wanna overlay the EFI capsule signature to U-Boot dtb, then capsule update with authentication could work, otherwise I need integrate the signature in dts and rebuild the image. I understand current U-Boot not support overlay U-Boot runtime dtb, just thinking whether this is valid or should we support it. Applying overlays to the control device-tree is not supported. Allowing console access on a system where you plan to apply authenticated capsules seems unwise from a security viewpoint. So we should not support your scenario. Note that Peng didn't say "apply an overlay from the console". I had assumed the desire was to see about doing all of this automatically as part of processing the update/etc. I thought we had something similar already, so that we could start with a "generic" device tree, figure out we're on board X, grab that device tree (as we're a FIT image and had N dtbs), and then switch to that. But right now I only spot the logic for selecting that dtb in SPL and telling full U-Boot to use that tree. His question was about avoiding rebuilding the image. So he wants to apply an overlay at run-time not at build time to change the key used to check capsule signatures. This should not be allowed. Best regards Heinrich
Building host tools on Windows
I am trying to build the host tools on Windows, and I have hit a road block. Specifically, I get the output: HOSTCC tools/mkeficapsule tools/mkeficapsule.c:18:10: fatal error: uuid/uuid.h: No such file or directory 18 | #include Steps so far: Download latest msys Double upgrade with "pacman -Syu" pacman -S gcc make bison diffutils openssl-devel pacman -S git git clone from denx.de pacman -S flex (because make complained "flex was missing" Now I have the above error. I am not familiar with MSYS packages - I have tried "e2fsprogs" and "uuid-dev" but neither are found. Which package do I need to include? Martin
[PATCH] drivers: xen: events: fix build issues with disabled Xen HVC
Some setups do not use Xen hypervisor console for logging, e.g. they
use emulated PL011 hardware or shared peripherals (real UART). In such
cases Xen HVC will be disabled on a build time and will cause issues in
current driver implementation.
This commit fixes build issues in Xen event channel driver, caused
by absense of console event channel, that is not available when console
config is disabled. Now console related code will be removed when
Xen HVC is turned off.
Signed-off-by: Dmytro Firsov
---
drivers/xen/events.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/xen/events.c b/drivers/xen/events.c
index 5e90a65846..532216fece 100644
--- a/drivers/xen/events.c
+++ b/drivers/xen/events.c
@@ -23,7 +23,9 @@
#include
#include
+#if CONFIG_IS_ENABLED(XEN_SERIAL)
extern u32 console_evtchn;
+#endif /* CONFIG_IS_ENABLED(XEN_SERIAL) */
#define NR_EVS 1024
@@ -51,8 +53,11 @@ void unbind_all_ports(void)
struct vcpu_info *vcpu_info = >vcpu_info[cpu];
for (i = 0; i < NR_EVS; i++) {
+#if CONFIG_IS_ENABLED(XEN_SERIAL)
if (i == console_evtchn)
continue;
+#endif /* CONFIG_IS_ENABLED(XEN_SERIAL) */
+
if (test_and_clear_bit(i, bound_ports)) {
printf("port %d still bound!\n", i);
unbind_evtchn(i);
--
2.25.1
[PATCH] watchdog: add pulse support to gpio watchdog driver
A common external watchdog circuit is kept alive by triggering a short
pulse on the reset pin. This patch adds support for this use case, while
making the algorithm configurable in the devicetree.
The "linux,wdt-gpio" driver being modified is based off the equivalent
driver in the Linux kernel, which provides support for this algorithm.
This patch brings parity to this driver, and is kept aligned with
the functionality and devicetree configuration in the kernel.
It should be noted that this adds a required property named 'hw_algo'
to the devicetree binding, following suit with the kernel. I'm happy to
make this backward-compatible if preferred.
Signed-off-by: Paul Doelle
---
arch/sandbox/dts/test.dts | 11 -
.../watchdog/gpio-wdt.txt | 8 +++-
drivers/watchdog/gpio_wdt.c | 40 +---
test/dm/wdt.c | 46 ---
4 files changed, 90 insertions(+), 15 deletions(-)
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 8f93775ff4..4dc591d995 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -830,10 +830,19 @@
};
};
- gpio-wdt {
+ wdt-gpio-toggle {
gpios = <_a 7 0>;
compatible = "linux,wdt-gpio";
hw_margin_ms = <100>;
+ hw_algo = "toggle";
+ always-running;
+ };
+
+ wdt-gpio-level {
+ gpios = <_a 7 0>;
+ compatible = "linux,wdt-gpio";
+ hw_margin_ms = <100>;
+ hw_algo = "level";
always-running;
};
diff --git a/doc/device-tree-bindings/watchdog/gpio-wdt.txt
b/doc/device-tree-bindings/watchdog/gpio-wdt.txt
index c9a8559a3e..746c2c081e 100644
--- a/doc/device-tree-bindings/watchdog/gpio-wdt.txt
+++ b/doc/device-tree-bindings/watchdog/gpio-wdt.txt
@@ -5,7 +5,12 @@ Describes a simple watchdog timer which is reset by toggling a
gpio.
Required properties:
- compatible: Must be "linux,wdt-gpio".
-- gpios: gpio to toggle when wdt driver reset method is called.
+- gpios: From common gpio binding; gpio connection to WDT reset pin.
+- hw_algo: The algorithm used by the driver. Should be one of the
+ following values:
+ - toggle: Toggle from high-to-low or low-to-high when resetting the watchdog.
+ - level: Maintain a constant high/low level, and trigger a short pulse when
+resetting the watchdog. Active level is determined by the GPIO flags.
- always-running: Boolean property indicating that the watchdog cannot
be disabled. At present, U-Boot only supports this kind of GPIO
watchdog.
@@ -15,5 +20,6 @@ Example:
gpio-wdt {
gpios = < 1 0>;
compatible = "linux,wdt-gpio";
+ hw_algo = "toggle";
always-running;
};
diff --git a/drivers/watchdog/gpio_wdt.c b/drivers/watchdog/gpio_wdt.c
index 982a66b3f9..fe06ec8cc9 100644
--- a/drivers/watchdog/gpio_wdt.c
+++ b/drivers/watchdog/gpio_wdt.c
@@ -4,20 +4,38 @@
#include
#include
#include
+#include
+
+enum {
+ HW_ALGO_TOGGLE,
+ HW_ALGO_LEVEL,
+};
struct gpio_wdt_priv {
- struct gpio_desc gpio;
- bool always_running;
- int state;
+ struct gpio_desc gpio;
+ unsigned inthw_algo;
+ boolalways_running;
+ int state;
};
static int gpio_wdt_reset(struct udevice *dev)
{
struct gpio_wdt_priv *priv = dev_get_priv(dev);
- priv->state = !priv->state;
-
- return dm_gpio_set_value(>gpio, priv->state);
+ switch (priv->hw_algo) {
+ case HW_ALGO_TOGGLE:
+ /* Toggle output pin */
+ priv->state = !priv->state;
+ dm_gpio_set_value(>gpio, priv->state);
+ break;
+ case HW_ALGO_LEVEL:
+ /* Pulse */
+ dm_gpio_set_value(>gpio, 1);
+ udelay(1);
+ dm_gpio_set_value(>gpio, 0);
+ break;
+ }
+ return 0;
}
static int gpio_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
@@ -34,6 +52,16 @@ static int dm_probe(struct udevice *dev)
{
struct gpio_wdt_priv *priv = dev_get_priv(dev);
int ret;
+ const char *algo = dev_read_string(dev, "hw_algo");
+
+ if (!algo)
+ return -EINVAL;
+ if (!strcmp(algo, "toggle"))
+ priv->hw_algo = HW_ALGO_TOGGLE;
+ else if (!strcmp(algo, "level"))
+ priv->hw_algo = HW_ALGO_LEVEL;
+ else
+ return -EINVAL;
priv->always_running = dev_read_bool(dev, "always-running");
ret = gpio_request_by_name(dev, "gpios", 0, >gpio, GPIOD_IS_OUT);
diff --git a/test/dm/wdt.c b/test/dm/wdt.c
index ee615f0e14..535f00a874 100644
--- a/test/dm/wdt.c
+++ b/test/dm/wdt.c
@@ -44,20 +44,20 @@ static int dm_test_wdt_base(struct unit_test_state *uts)
}
Re: [PATCH 0/5] Add support for versal specific cadence ospi driver
On 5/12/22 12:05, Ashok Reddy Soma wrote: This patch series does the following: * Move macros from cadence driver to cadence header file * Add new versal specific cadence ospi driver * Reset qspi flash in when driver probed * Enable/Disable apb linear mode based on dma usage * Fix cadence qspi flash speed programming T Karthik Reddy (5): spi: cadence-qspi: move cadence qspi macros to header file arm64: versal: Add versal specific cadence ospi driver spi: cadence-qspi: reset qspi flash for versal platform spi: cadence_qspi: Enable apb linear mode for apb read & write operations spi: cadence-qspi: Fix programming ospi flash speed MAINTAINERS | 1 + arch/arm/mach-versal/include/mach/hardware.h | 15 ++ configs/xilinx_versal_virt_defconfig | 2 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/cadence_ospi_versal.c| 237 +++ drivers/spi/cadence_qspi.c | 40 +++- drivers/spi/cadence_qspi.h | 189 +++ drivers/spi/cadence_qspi_apb.c | 163 + include/zynqmp_firmware.h| 9 + 10 files changed, 510 insertions(+), 155 deletions(-) create mode 100644 drivers/spi/cadence_ospi_versal.c fyi: This has been merged to next by Tom. M
Re: [PATCH] mtd: spi-nor-ids: Add support for flashes tested by xilinx
On 5/25/22 07:17, Ashok Reddy Soma wrote:
Add support for various flashes from below manufacturers which are tested
by xilinx for years.
EON:
en25q128b
GIGA:
gd25lx256e
ISSI:
is25lp008
is25lp016
is25lp01g
is25wp008
is25wp016
is25wp01g
is25wx256
MACRONIX:
mx25u51245f
mx66u1g45g
mx66l2g45g
MICRON:
mt35xl512aba
mt35xu01g
SPANSION:
s70fs01gs_256k
SST:
sst26wf016b
WINBOND:
w25q16dw
w25q16jv
w25q512jv
w25q32bv
w25h02jv
Signed-off-by: Ashok Reddy Soma
---
drivers/mtd/spi/spi-nor-ids.c | 37 +++
1 file changed, 37 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 7050ddc397..5d8bf05ff8 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -82,6 +82,7 @@ const struct flash_info spi_nor_ids[] = {
/* EON -- en25xxx */
{ INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
{ INFO("en25q64",0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
+ { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
{ INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
{ INFO("en25s64",0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
#endif
@@ -127,11 +128,17 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
+SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
+ },
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
/* ISSI */
{ INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
+ { INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
{ INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) },
{ INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) },
{ INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256,
@@ -140,6 +147,10 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ) },
{ INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
+ { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
{ INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128,
@@ -151,6 +162,10 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_4B_OPCODES) },
{ INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256,
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
/* Macronix */
@@ -176,8 +191,11 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
{ INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES | SECT_4K) },
{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
@@ -208,8 +226,10 @@ const struct
Re: dtboverlay to U-Boot runtime dtb
On Mon, Jul 04, 2022 at 03:27:26PM +0200, Heinrich Schuchardt wrote: > On 7/4/22 14:51, Peter Robinson wrote: > > Hi Peng, > > > > > I did a test to do overlay for U-Boot runtime dtb, but after overlay > > > finish, U-Boot DM driver not work properly because the of_node > > > pointer is changed in a device. > > > > > > So I am thinking whether this is valid to overlay to runtime U-Boot > > > dtb or not. The reason I try this is that I wanna overlay the EFI capsule > > > signature to U-Boot dtb, then capsule update with authentication > > > could work, otherwise I need integrate the signature in dts and > > > rebuild the image. I understand current U-Boot not support > > > overlay U-Boot runtime dtb, just thinking whether this is valid or > > > should we support it. > > Applying overlays to the control device-tree is not supported. Allowing > console access on a system where you plan to apply authenticated > capsules seems unwise from a security viewpoint. So we should not > support your scenario. Note that Peng didn't say "apply an overlay from the console". I had assumed the desire was to see about doing all of this automatically as part of processing the update/etc. I thought we had something similar already, so that we could start with a "generic" device tree, figure out we're on board X, grab that device tree (as we're a FIT image and had N dtbs), and then switch to that. But right now I only spot the logic for selecting that dtb in SPL and telling full U-Boot to use that tree. -- Tom signature.asc Description: PGP signature
[PATCH v6 7/7] test: rng: Add a UT testcase for the rng command
The 'rng' command dumps a number of random bytes on the console. Add a
set of tests for the 'rng' command. The test function performs basic
sanity testing of the command.
Since a unit test is being added for the command, enable it by default
in the sandbox platforms.
Reviewed-by: Simon Glass
Signed-off-by: Sughosh Ganu
---
cmd/Kconfig | 1 +
test/dm/rng.c | 29 +
2 files changed, 30 insertions(+)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 09193b61b9..eee5d44348 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1916,6 +1916,7 @@ config CMD_GETTIME
config CMD_RNG
bool "rng command"
depends on DM_RNG
+ default y if SANDBOX
select HEXDUMP
help
Print bytes from the hardware random number generator.
diff --git a/test/dm/rng.c b/test/dm/rng.c
index 5b34c93ed6..6d1f68848d 100644
--- a/test/dm/rng.c
+++ b/test/dm/rng.c
@@ -25,3 +25,32 @@ static int dm_test_rng_read(struct unit_test_state *uts)
return 0;
}
DM_TEST(dm_test_rng_read, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/* Test the rng command */
+static int dm_test_rng_cmd(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_get_device(UCLASS_RNG, 0, ));
+ ut_assertnonnull(dev);
+
+ ut_assertok(console_record_reset_enable());
+
+ run_command("rng", 0);
+ ut_assert_nextlinen(":");
+ ut_assert_nextlinen("0010:");
+ ut_assert_nextlinen("0020:");
+ ut_assert_nextlinen("0030:");
+ ut_assert_console_end();
+
+ run_command("rng 0 10", 0);
+ ut_assert_nextlinen(":");
+ ut_assert_console_end();
+
+ run_command("rng 20", 0);
+ ut_assert_nextlinen("No RNG device");
+ ut_assert_console_end();
+
+ return 0;
+}
+DM_TEST(dm_test_rng_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT |
UT_TESTF_CONSOLE_REC);
--
2.25.1
[PATCH v6 6/7] doc: rng: Add documentation for the rng command
Add a usage document for the 'rng' u-boot command. Reviewed-by: Ilias Apalodimas Reviewed-by: Simon Glass Signed-off-by: Sughosh Ganu --- Changes since V5: None doc/usage/cmd/rng.rst | 26 ++ doc/usage/index.rst | 1 + 2 files changed, 27 insertions(+) create mode 100644 doc/usage/cmd/rng.rst diff --git a/doc/usage/cmd/rng.rst b/doc/usage/cmd/rng.rst new file mode 100644 index 00..1a352da41a --- /dev/null +++ b/doc/usage/cmd/rng.rst @@ -0,0 +1,26 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +rng command +=== + +Synopsis + + +:: + +rng [devnum [n]] + +Description +--- + +The *rng* command reads the random number generator(RNG) device and +prints the random bytes read on the console. A maximum of 64 bytes can +be read in one invocation of the command. + +devnum +The RNG device from which the random bytes are to be +read. Defaults to 0. + +n +Number of random bytes to be read and displayed on the +console. Default value is 0x40. Max value is 0x40. diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 770418434a..ed3a78aa14 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -53,6 +53,7 @@ Shell commands cmd/pstore cmd/qfw cmd/reset + cmd/rng cmd/sbi cmd/sf cmd/scp03 -- 2.25.1
[PATCH v6 5/7] cmd: rng: Use a statically allocated array for random bytes
Use a statically allocated buffer on stack instead of using malloc for
reading the random bytes. Using a local array is faster than
allocating heap memory on every initiation of the command.
Signed-off-by: Sughosh Ganu
---
Changes since V5: None
cmd/rng.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/cmd/rng.c b/cmd/rng.c
index 2ddf27545f..81a23964b8 100644
--- a/cmd/rng.c
+++ b/cmd/rng.c
@@ -14,9 +14,9 @@
static int do_rng(struct cmd_tbl *cmdtp, int flag, int argc, char *const
argv[])
{
size_t n;
- struct udevice *dev;
- void *buf;
+ u8 buf[64];
int devnum;
+ struct udevice *dev;
int ret = CMD_RET_SUCCESS;
switch (argc) {
@@ -41,11 +41,10 @@ static int do_rng(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
return CMD_RET_FAILURE;
}
- buf = malloc(n);
- if (!buf) {
- printf("Out of memory\n");
- return CMD_RET_FAILURE;
- }
+ if (!n)
+ return 0;
+
+ n = min(n, sizeof(buf));
if (dm_rng_read(dev, buf, n)) {
printf("Reading RNG failed\n");
@@ -54,15 +53,13 @@ static int do_rng(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, n);
}
- free(buf);
-
return ret;
}
#ifdef CONFIG_SYS_LONGHELP
static char rng_help_text[] =
"[dev [n]]\n"
- " - print n random bytes read from dev\n";
+ " - print n random bytes(max 64) read from dev\n";
#endif
U_BOOT_CMD(
--
2.25.1
[PATCH v6 4/7] cmd: rng: Add support for selecting RNG device
The 'rng' u-boot command is used for printing a select number of
random bytes on the console. Currently, the RNG device from which the
random bytes are read is fixed. However, a platform can have multiple
RNG devices, one example being qemu, which has a virtio RNG device and
the RNG pseudo device through the TPM chip.
Extend the 'rng' command so that the user can provide the RNG device
number from which the random bytes are to be read. This will be the
device index under the RNG uclass.
Tested-by: Heinrich Schuchardt
Reviewed-by: Ilias Apalodimas
Signed-off-by: Sughosh Ganu
---
Changes since V5: None
cmd/rng.c | 31 +++
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/cmd/rng.c b/cmd/rng.c
index 1ad5a096c0..2ddf27545f 100644
--- a/cmd/rng.c
+++ b/cmd/rng.c
@@ -13,19 +13,34 @@
static int do_rng(struct cmd_tbl *cmdtp, int flag, int argc, char *const
argv[])
{
- size_t n = 0x40;
+ size_t n;
struct udevice *dev;
void *buf;
+ int devnum;
int ret = CMD_RET_SUCCESS;
- if (uclass_get_device(UCLASS_RNG, 0, ) || !dev) {
+ switch (argc) {
+ case 1:
+ devnum = 0;
+ n = 0x40;
+ break;
+ case 2:
+ devnum = hextoul(argv[1], NULL);
+ n = 0x40;
+ break;
+ case 3:
+ devnum = hextoul(argv[1], NULL);
+ n = hextoul(argv[2], NULL);
+ break;
+ default:
+ return CMD_RET_USAGE;
+ }
+
+ if (uclass_get_device_by_seq(UCLASS_RNG, devnum, ) || !dev) {
printf("No RNG device\n");
return CMD_RET_FAILURE;
}
- if (argc >= 2)
- n = hextoul(argv[1], NULL);
-
buf = malloc(n);
if (!buf) {
printf("Out of memory\n");
@@ -46,12 +61,12 @@ static int do_rng(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
#ifdef CONFIG_SYS_LONGHELP
static char rng_help_text[] =
- "[n]\n"
- " - print n random bytes\n";
+ "[dev [n]]\n"
+ " - print n random bytes read from dev\n";
#endif
U_BOOT_CMD(
- rng, 2, 0, do_rng,
+ rng, 3, 0, do_rng,
"print bytes from the hardware random number generator",
rng_help_text
);
--
2.25.1
[PATCH v6 3/7] tpm: Add the RNG child device
The TPM device comes with the random number generator(RNG)
functionality which is built into the TPM device. Add logic to add the
RNG child device in the TPM uclass post probe callback.
The RNG device can then be used to pass a set of random bytes to the
linux kernel, need for address space randomisation through the
EFI_RNG_PROTOCOL interface.
Signed-off-by: Sughosh Ganu
---
Changes since V5:
* Check if the TPM RNG device has already been added, through a call
to device_find_first_child_by_uclass()
drivers/tpm/tpm-uclass.c | 37 +
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/drivers/tpm/tpm-uclass.c b/drivers/tpm/tpm-uclass.c
index f67fe1019b..e1f1ef01e1 100644
--- a/drivers/tpm/tpm-uclass.c
+++ b/drivers/tpm/tpm-uclass.c
@@ -11,10 +11,15 @@
#include
#include
#include
+#include
#include
#include
#include "tpm_internal.h"
+#include
+
+#define TPM_RNG_DRV_NAME "tpm-rng"
+
int tpm_open(struct udevice *dev)
{
struct tpm_ops *ops = tpm_get_ops(dev);
@@ -136,12 +141,36 @@ int tpm_xfer(struct udevice *dev, const uint8_t *sendbuf,
size_t send_size,
return 0;
}
+static int tpm_uclass_post_probe(struct udevice *dev)
+{
+ int ret;
+ const char *drv = TPM_RNG_DRV_NAME;
+ struct udevice *child;
+
+ if (CONFIG_IS_ENABLED(TPM_RNG)) {
+ ret = device_find_first_child_by_uclass(dev, UCLASS_RNG,
+ );
+
+ if (ret != -ENODEV) {
+ log_debug("RNG child already added to the TPM
device\n");
+ return ret;
+ }
+
+ ret = device_bind_driver(dev, drv, "tpm-rng0", );
+ if (ret)
+ return log_msg_ret("bind", ret);
+ }
+
+ return 0;
+}
+
UCLASS_DRIVER(tpm) = {
- .id = UCLASS_TPM,
- .name = "tpm",
- .flags = DM_UC_FLAG_SEQ_ALIAS,
+ .id = UCLASS_TPM,
+ .name = "tpm",
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
#if CONFIG_IS_ENABLED(OF_REAL)
- .post_bind = dm_scan_fdt_dev,
+ .post_bind = dm_scan_fdt_dev,
#endif
+ .post_probe = tpm_uclass_post_probe,
.per_device_auto= sizeof(struct tpm_chip_priv),
};
--
2.25.1
[PATCH v6 2/7] tpm: rng: Add driver model interface for TPM RNG device
The TPM device has a builtin random number generator(RNG)
functionality. Expose the RNG functions of the TPM device to the
driver model so that they can be used by the EFI_RNG_PROTOCOL if the
protocol is installed.
Also change the function arguments and return type of the random
number functions to comply with the driver model api.
Signed-off-by: Sughosh Ganu
---
Changes since V5:
* Use the dev_get_parent() interface for getting the TPM device when
calling the tpm_get_random() function
drivers/rng/Kconfig | 11 +++
drivers/rng/Makefile | 1 +
drivers/rng/tpm_rng.c | 23 +++
lib/Kconfig | 1 +
lib/tpm-v1.c | 13 +++--
lib/tpm-v2.c | 6 +++---
lib/tpm_api.c | 6 +++---
7 files changed, 49 insertions(+), 12 deletions(-)
create mode 100644 drivers/rng/tpm_rng.c
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index c10f7d345b..67c65311c7 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -58,4 +58,15 @@ config RNG_IPROC200
depends on DM_RNG
help
Enable random number generator for RPI4.
+
+config TPM_RNG
+ bool "Enable random number generator on TPM device"
+ depends on TPM
+ default y
+ help
+ The TPM device has an inbuilt random number generator
+ functionality. Enable random number generator on TPM
+ devices.
+
+
endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 435b3b965a..e4ca9c4149 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_RNG_OPTEE) += optee_rng.o
obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
+obj-$(CONFIG_TPM_RNG) += tpm_rng.o
diff --git a/drivers/rng/tpm_rng.c b/drivers/rng/tpm_rng.c
new file mode 100644
index 00..1a5e9e2e4b
--- /dev/null
+++ b/drivers/rng/tpm_rng.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+#include
+#include
+#include
+
+static int rng_tpm_random_read(struct udevice *dev, void *data, size_t count)
+{
+ return tpm_get_random(dev_get_parent(dev), data, count);
+}
+
+static const struct dm_rng_ops tpm_rng_ops = {
+ .read = rng_tpm_random_read,
+};
+
+U_BOOT_DRIVER(tpm_rng) = {
+ .name = "tpm-rng",
+ .id = UCLASS_RNG,
+ .ops= _rng_ops,
+};
diff --git a/lib/Kconfig b/lib/Kconfig
index acc0ac081a..17efaa4c80 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -358,6 +358,7 @@ source lib/crypt/Kconfig
config TPM
bool "Trusted Platform Module (TPM) Support"
depends on DM
+ imply DM_RNG
help
This enables support for TPMs which can be used to provide security
features for your board. The TPM can be connected via LPC or I2C
diff --git a/lib/tpm-v1.c b/lib/tpm-v1.c
index 22a769c587..f7091e5bc7 100644
--- a/lib/tpm-v1.c
+++ b/lib/tpm-v1.c
@@ -9,12 +9,13 @@
#include
#include
#include
-#include
-#include
#include
#include
#include "tpm-utils.h"
+#include
+#include
+
#ifdef CONFIG_TPM_AUTH_SESSIONS
#ifndef CONFIG_SHA1
@@ -892,19 +893,19 @@ u32 tpm1_get_random(struct udevice *dev, void *data, u32
count)
if (pack_byte_string(buf, sizeof(buf), "sd",
0, command, sizeof(command),
length_offset, this_bytes))
- return TPM_LIB_ERROR;
+ return -EIO;
err = tpm_sendrecv_command(dev, buf, response,
_length);
if (err)
return err;
if (unpack_byte_string(response, response_length, "d",
data_size_offset, _size))
- return TPM_LIB_ERROR;
+ return -EIO;
if (data_size > count)
- return TPM_LIB_ERROR;
+ return -EIO;
if (unpack_byte_string(response, response_length, "s",
data_offset, out, data_size))
- return TPM_LIB_ERROR;
+ return -EIO;
count -= data_size;
out += data_size;
diff --git a/lib/tpm-v2.c b/lib/tpm-v2.c
index 1bf627853a..abca9a14b0 100644
--- a/lib/tpm-v2.c
+++ b/lib/tpm-v2.c
@@ -585,19 +585,19 @@ u32 tpm2_get_random(struct udevice *dev, void *data, u32
count)
if (pack_byte_string(buf, sizeof(buf), "sw",
0, command_v2, sizeof(command_v2),
sizeof(command_v2), this_bytes))
- return TPM_LIB_ERROR;
+ return -EIO;
err = tpm_sendrecv_command(dev, buf, response,
_length);
[PATCH v6 0/7] tpm: rng: Move TPM RNG functionality to driver model
The TPM device provides the random number generator(RNG) functionality, whereby sending a command to the TPM device results in the TPM device responding with random bytes. There was a discussion on the mailing list earlier[1], where it was explained that platforms with a TPM device can install the EFI_RNG_PROTOCOL for getting the random bytes instead of populating the dtb with the kaslr-seed property. That would make it possible to measure the dtb. The TPM uclass driver adds the RNG child device as part of it's post_probe function. Some additional changes have also been made to facilitate the use of the RNG devices, including extending the 'rng' command to take the RNG device as one of the command-line parameters. This series depends on a patch[2] from Simon Glass for moving the TPM device version detection functions to the tpm_api.h header as static inline functions. These patches were under discussion earlier, specifically the patch to add the RNG functionality under the TPM device as a child, either through manual binding or through the device tree. Ilias had commented on the discussion last[3]. The discussion can be resumed through this version. I have dropped certain patches which were changing some of the TPM API functions to return an int instead of the current u32. These patches have been dropped due to review comments from Simon[4]. This work can be taken up separately, if desired. [1] - https://lore.kernel.org/u-boot/20220103120738.47835-1-ilias.apalodi...@linaro.org/ [2] - https://lore.kernel.org/u-boot/20220301001125.1554442-2-...@chromium.org/T/#u [3] - https://lists.denx.de/pipermail/u-boot/2022-April/481708.html [4] - https://lists.denx.de/pipermail/u-boot/2022-March/477883.html Simon Glass (1): tpm: Export the TPM-version functions Sughosh Ganu (6): tpm: rng: Add driver model interface for TPM RNG device tpm: Add the RNG child device cmd: rng: Add support for selecting RNG device cmd: rng: Use a statically allocated array for random bytes doc: rng: Add documentation for the rng command test: rng: Add a UT testcase for the rng command cmd/Kconfig | 1 + cmd/rng.c| 42 +++-- doc/usage/cmd/rng.rst| 26 +++ doc/usage/index.rst | 1 + drivers/rng/Kconfig | 11 + drivers/rng/Makefile | 1 + drivers/rng/tpm_rng.c| 23 ++ drivers/tpm/tpm-uclass.c | 37 +-- include/tpm_api.h| 10 lib/Kconfig | 1 + lib/tpm-v1.c | 13 +++--- lib/tpm-v2.c | 6 +-- lib/tpm_api.c| 98 ++-- test/dm/rng.c| 29 14 files changed, 217 insertions(+), 82 deletions(-) create mode 100644 doc/usage/cmd/rng.rst create mode 100644 drivers/rng/tpm_rng.c -- 2.25.1
[PATCH v6 1/7] tpm: Export the TPM-version functions
From: Simon Glass
These functions should really be available outside the TPM code, so that
other callers can find out which version the TPM is. Rename them to have
a tpm_ prefix() and add them to the header file.
Signed-off-by: Simon Glass
---
Changes since V5: None
include/tpm_api.h | 10 ++
lib/tpm_api.c | 92 +--
2 files changed, 51 insertions(+), 51 deletions(-)
diff --git a/include/tpm_api.h b/include/tpm_api.h
index ef45b43a8f..11aa14eb79 100644
--- a/include/tpm_api.h
+++ b/include/tpm_api.h
@@ -319,4 +319,14 @@ u32 tpm_write_lock(struct udevice *dev, u32 index);
*/
u32 tpm_resume(struct udevice *dev);
+static inline bool tpm_is_v1(struct udevice *dev)
+{
+ return IS_ENABLED(CONFIG_TPM_V1) && tpm_get_version(dev) == TPM_V1;
+}
+
+static inline bool tpm_is_v2(struct udevice *dev)
+{
+ return IS_ENABLED(CONFIG_TPM_V2) && tpm_get_version(dev) == TPM_V2;
+}
+
#endif /* __TPM_API_H */
diff --git a/lib/tpm_api.c b/lib/tpm_api.c
index 4c662640a9..4ac4612c81 100644
--- a/lib/tpm_api.c
+++ b/lib/tpm_api.c
@@ -11,21 +11,11 @@
#include
#include
-static bool is_tpm1(struct udevice *dev)
-{
- return IS_ENABLED(CONFIG_TPM_V1) && tpm_get_version(dev) == TPM_V1;
-}
-
-static bool is_tpm2(struct udevice *dev)
-{
- return IS_ENABLED(CONFIG_TPM_V2) && tpm_get_version(dev) == TPM_V2;
-}
-
u32 tpm_startup(struct udevice *dev, enum tpm_startup_type mode)
{
- if (is_tpm1(dev)) {
+ if (tpm_is_v1(dev)) {
return tpm1_startup(dev, mode);
- } else if (is_tpm2(dev)) {
+ } else if (tpm_is_v2(dev)) {
enum tpm2_startup_types type;
switch (mode) {
@@ -47,9 +37,9 @@ u32 tpm_startup(struct udevice *dev, enum tpm_startup_type
mode)
u32 tpm_resume(struct udevice *dev)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return tpm1_startup(dev, TPM_ST_STATE);
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return tpm2_startup(dev, TPM2_SU_STATE);
else
return -ENOSYS;
@@ -57,9 +47,9 @@ u32 tpm_resume(struct udevice *dev)
u32 tpm_self_test_full(struct udevice *dev)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return tpm1_self_test_full(dev);
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return tpm2_self_test(dev, TPMI_YES);
else
return -ENOSYS;
@@ -67,9 +57,9 @@ u32 tpm_self_test_full(struct udevice *dev)
u32 tpm_continue_self_test(struct udevice *dev)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return tpm1_continue_self_test(dev);
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return tpm2_self_test(dev, TPMI_NO);
else
return -ENOSYS;
@@ -86,7 +76,7 @@ u32 tpm_clear_and_reenable(struct udevice *dev)
return ret;
}
- if (is_tpm1(dev)) {
+ if (tpm_is_v1(dev)) {
ret = tpm1_physical_enable(dev);
if (ret != TPM_SUCCESS) {
log_err("TPM: Can't set enabled state\n");
@@ -105,9 +95,9 @@ u32 tpm_clear_and_reenable(struct udevice *dev)
u32 tpm_nv_enable_locking(struct udevice *dev)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return tpm1_nv_define_space(dev, TPM_NV_INDEX_LOCK, 0, 0);
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return -ENOSYS;
else
return -ENOSYS;
@@ -115,9 +105,9 @@ u32 tpm_nv_enable_locking(struct udevice *dev)
u32 tpm_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return tpm1_nv_read_value(dev, index, data, count);
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return tpm2_nv_read_value(dev, index, data, count);
else
return -ENOSYS;
@@ -126,9 +116,9 @@ u32 tpm_nv_read_value(struct udevice *dev, u32 index, void
*data, u32 count)
u32 tpm_nv_write_value(struct udevice *dev, u32 index, const void *data,
u32 count)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return tpm1_nv_write_value(dev, index, data, count);
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return tpm2_nv_write_value(dev, index, data, count);
else
return -ENOSYS;
@@ -141,9 +131,9 @@ u32 tpm_set_global_lock(struct udevice *dev)
u32 tpm_write_lock(struct udevice *dev, u32 index)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return -ENOSYS;
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return tpm2_write_lock(dev, index);
else
return -ENOSYS;
@@ -152,9 +142,9 @@ u32 tpm_write_lock(struct udevice *dev, u32 index)
u32
Re: dtboverlay to U-Boot runtime dtb
On 7/4/22 14:51, Peter Robinson wrote: Hi Peng, I did a test to do overlay for U-Boot runtime dtb, but after overlay finish, U-Boot DM driver not work properly because the of_node pointer is changed in a device. So I am thinking whether this is valid to overlay to runtime U-Boot dtb or not. The reason I try this is that I wanna overlay the EFI capsule signature to U-Boot dtb, then capsule update with authentication could work, otherwise I need integrate the signature in dts and rebuild the image. I understand current U-Boot not support overlay U-Boot runtime dtb, just thinking whether this is valid or should we support it. Applying overlays to the control device-tree is not supported. Allowing console access on a system where you plan to apply authenticated capsules seems unwise from a security viewpoint. So we should not support your scenario. You can apply overlays to the device-tree passed to the Linux kernel. Best regards Heinrich Bootin did a pretty good blog post for DT overlays in U-Boot, not sure if that's useful for this usecase but for reference: https://bootlin.com/blog/using-the-u-boot-extension-board-manager-beaglebone-boards-example/
Re: [PATCH 0/8] New boards support: db845c and qcs404-evb
Hi Peter, On Mon, 4 Jul 2022 at 18:35, Peter Robinson wrote: > > > Add support for two new boards db845c and qcs404-evb: > > - db845c is a 96boards compliant platform aka RB3 based on Qualcomm > > SDM845 SoC. > > - qcs404-evb is an evaluation board from Qualcomm based on QCS404 SoC. > > > > Both these platforms have one thing in common that u-boot is chain-loaded > > in 64-bit mode via Android Boot Loader (ABL) which is an EFI application. > > Can we have some docs on how that works, how to build it, how to set > it up for chain loading etc. Please follow documentation added/updated by this patch-set [1] [2]. [1] doc/board/qualcomm/sdm845.rst [2] doc/board/qualcomm/qcs404.rst -Sumit > > Peter > > > Sumit Garg (8): > > arm64: dts: sdm845: Remove redundant u-boot DT properties > > clocks: sdm845: Import qcom,gcc-sdm845.h > > uart: sdm845: Fix debug UART pinmux > > board: qualcomm: Add support for dragonboard845c > > mmc: msm_sdhci: Add SDCC version 5.0.0 support > > pinctrl: qcom: Add pinctrl driver for QCS404 SoC > > clocks: qcom: Add clock driver for QCS404 SoC > > board: qualcomm: Add support for QCS404 EVB > > > > arch/arm/dts/Makefile | 1 + > > arch/arm/dts/dragonboard845c-uboot.dtsi | 37 +++ > > arch/arm/dts/dragonboard845c.dts | 44 > > arch/arm/dts/qcs404-evb-uboot.dtsi| 24 ++ > > arch/arm/dts/qcs404-evb.dts | 81 ++ > > arch/arm/dts/sdm845.dtsi | 8 +- > > arch/arm/mach-snapdragon/Kconfig | 25 ++ > > arch/arm/mach-snapdragon/Makefile | 3 + > > arch/arm/mach-snapdragon/clock-qcs404.c | 30 +++ > > arch/arm/mach-snapdragon/clock-sdm845.c | 3 +- > > arch/arm/mach-snapdragon/clock-snapdragon.c | 1 + > > .../include/mach/sysmap-qcs404.h | 13 + > > arch/arm/mach-snapdragon/pinctrl-qcs404.c | 55 > > arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 + > > arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 + > > arch/arm/mach-snapdragon/sysmap-qcs404.c | 31 +++ > > board/qualcomm/dragonboard845c/Kconfig| 12 + > > board/qualcomm/dragonboard845c/MAINTAINERS| 6 + > > board/qualcomm/dragonboard845c/Makefile | 9 + > > board/qualcomm/dragonboard845c/db845c.its | 63 + > > .../dragonboard845c/dragonboard845c.c | 9 + > > board/qualcomm/qcs404-evb/Kconfig | 15 ++ > > board/qualcomm/qcs404-evb/MAINTAINERS | 6 + > > board/qualcomm/qcs404-evb/Makefile| 6 + > > board/qualcomm/qcs404-evb/qcs404-evb.c| 33 +++ > > board/qualcomm/qcs404-evb/qcs404-evb.its | 64 + > > configs/dragonboard845c_defconfig | 28 ++ > > configs/qcs404evb_defconfig | 39 +++ > > doc/board/qualcomm/index.rst | 1 + > > doc/board/qualcomm/qcs404.rst | 79 ++ > > doc/board/qualcomm/sdm845.rst | 100 ++- > > drivers/mmc/msm_sdhci.c | 96 --- > > include/configs/dragonboard845c.h | 28 ++ > > include/configs/qcs404-evb.h | 27 ++ > > include/dt-bindings/clock/qcom,gcc-qcs404.h | 180 + > > include/dt-bindings/clock/qcom,gcc-sdm845.h | 246 ++ > > 36 files changed, 1354 insertions(+), 51 deletions(-) > > create mode 100644 arch/arm/dts/dragonboard845c-uboot.dtsi > > create mode 100644 arch/arm/dts/dragonboard845c.dts > > create mode 100644 arch/arm/dts/qcs404-evb-uboot.dtsi > > create mode 100644 arch/arm/dts/qcs404-evb.dts > > create mode 100644 arch/arm/mach-snapdragon/clock-qcs404.c > > create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h > > create mode 100644 arch/arm/mach-snapdragon/pinctrl-qcs404.c > > create mode 100644 arch/arm/mach-snapdragon/sysmap-qcs404.c > > create mode 100644 board/qualcomm/dragonboard845c/Kconfig > > create mode 100644 board/qualcomm/dragonboard845c/MAINTAINERS > > create mode 100644 board/qualcomm/dragonboard845c/Makefile > > create mode 100644 board/qualcomm/dragonboard845c/db845c.its > > create mode 100644 board/qualcomm/dragonboard845c/dragonboard845c.c > > create mode 100644 board/qualcomm/qcs404-evb/Kconfig > > create mode 100644 board/qualcomm/qcs404-evb/MAINTAINERS > > create mode 100644 board/qualcomm/qcs404-evb/Makefile > > create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.c > > create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.its > > create mode 100644 configs/dragonboard845c_defconfig > > create mode 100644 configs/qcs404evb_defconfig > > create mode 100644 doc/board/qualcomm/qcs404.rst > > create mode 100644 include/configs/dragonboard845c.h > > create mode 100644 include/configs/qcs404-evb.h > > create mode 100644 include/dt-bindings/clock/qcom,gcc-qcs404.h > > create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm845.h > > > > -- > > 2.25.1
Re: [PATCH 0/8] New boards support: db845c and qcs404-evb
> Add support for two new boards db845c and qcs404-evb: > - db845c is a 96boards compliant platform aka RB3 based on Qualcomm > SDM845 SoC. > - qcs404-evb is an evaluation board from Qualcomm based on QCS404 SoC. > > Both these platforms have one thing in common that u-boot is chain-loaded > in 64-bit mode via Android Boot Loader (ABL) which is an EFI application. Can we have some docs on how that works, how to build it, how to set it up for chain loading etc. Peter > Sumit Garg (8): > arm64: dts: sdm845: Remove redundant u-boot DT properties > clocks: sdm845: Import qcom,gcc-sdm845.h > uart: sdm845: Fix debug UART pinmux > board: qualcomm: Add support for dragonboard845c > mmc: msm_sdhci: Add SDCC version 5.0.0 support > pinctrl: qcom: Add pinctrl driver for QCS404 SoC > clocks: qcom: Add clock driver for QCS404 SoC > board: qualcomm: Add support for QCS404 EVB > > arch/arm/dts/Makefile | 1 + > arch/arm/dts/dragonboard845c-uboot.dtsi | 37 +++ > arch/arm/dts/dragonboard845c.dts | 44 > arch/arm/dts/qcs404-evb-uboot.dtsi| 24 ++ > arch/arm/dts/qcs404-evb.dts | 81 ++ > arch/arm/dts/sdm845.dtsi | 8 +- > arch/arm/mach-snapdragon/Kconfig | 25 ++ > arch/arm/mach-snapdragon/Makefile | 3 + > arch/arm/mach-snapdragon/clock-qcs404.c | 30 +++ > arch/arm/mach-snapdragon/clock-sdm845.c | 3 +- > arch/arm/mach-snapdragon/clock-snapdragon.c | 1 + > .../include/mach/sysmap-qcs404.h | 13 + > arch/arm/mach-snapdragon/pinctrl-qcs404.c | 55 > arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 + > arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 + > arch/arm/mach-snapdragon/sysmap-qcs404.c | 31 +++ > board/qualcomm/dragonboard845c/Kconfig| 12 + > board/qualcomm/dragonboard845c/MAINTAINERS| 6 + > board/qualcomm/dragonboard845c/Makefile | 9 + > board/qualcomm/dragonboard845c/db845c.its | 63 + > .../dragonboard845c/dragonboard845c.c | 9 + > board/qualcomm/qcs404-evb/Kconfig | 15 ++ > board/qualcomm/qcs404-evb/MAINTAINERS | 6 + > board/qualcomm/qcs404-evb/Makefile| 6 + > board/qualcomm/qcs404-evb/qcs404-evb.c| 33 +++ > board/qualcomm/qcs404-evb/qcs404-evb.its | 64 + > configs/dragonboard845c_defconfig | 28 ++ > configs/qcs404evb_defconfig | 39 +++ > doc/board/qualcomm/index.rst | 1 + > doc/board/qualcomm/qcs404.rst | 79 ++ > doc/board/qualcomm/sdm845.rst | 100 ++- > drivers/mmc/msm_sdhci.c | 96 --- > include/configs/dragonboard845c.h | 28 ++ > include/configs/qcs404-evb.h | 27 ++ > include/dt-bindings/clock/qcom,gcc-qcs404.h | 180 + > include/dt-bindings/clock/qcom,gcc-sdm845.h | 246 ++ > 36 files changed, 1354 insertions(+), 51 deletions(-) > create mode 100644 arch/arm/dts/dragonboard845c-uboot.dtsi > create mode 100644 arch/arm/dts/dragonboard845c.dts > create mode 100644 arch/arm/dts/qcs404-evb-uboot.dtsi > create mode 100644 arch/arm/dts/qcs404-evb.dts > create mode 100644 arch/arm/mach-snapdragon/clock-qcs404.c > create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h > create mode 100644 arch/arm/mach-snapdragon/pinctrl-qcs404.c > create mode 100644 arch/arm/mach-snapdragon/sysmap-qcs404.c > create mode 100644 board/qualcomm/dragonboard845c/Kconfig > create mode 100644 board/qualcomm/dragonboard845c/MAINTAINERS > create mode 100644 board/qualcomm/dragonboard845c/Makefile > create mode 100644 board/qualcomm/dragonboard845c/db845c.its > create mode 100644 board/qualcomm/dragonboard845c/dragonboard845c.c > create mode 100644 board/qualcomm/qcs404-evb/Kconfig > create mode 100644 board/qualcomm/qcs404-evb/MAINTAINERS > create mode 100644 board/qualcomm/qcs404-evb/Makefile > create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.c > create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.its > create mode 100644 configs/dragonboard845c_defconfig > create mode 100644 configs/qcs404evb_defconfig > create mode 100644 doc/board/qualcomm/qcs404.rst > create mode 100644 include/configs/dragonboard845c.h > create mode 100644 include/configs/qcs404-evb.h > create mode 100644 include/dt-bindings/clock/qcom,gcc-qcs404.h > create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm845.h > > -- > 2.25.1 >
[PATCH 8/8] board: qualcomm: Add support for QCS404 EVB
Add support for Qualcomm QCS404 SoC based evaluation board.
Features:
- Qualcomm Snapdragon QCS404 SoC
- 1GiB RAM
- 8GiB eMMC, uSD slot
U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.
For detailed build and boot instructions, refer to
doc/board/qualcomm/qcs404.rst.
Signed-off-by: Sumit Garg
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/qcs404-evb-uboot.dtsi| 24 ++
arch/arm/dts/qcs404-evb.dts | 81 +++
arch/arm/mach-snapdragon/Kconfig | 11 +++
arch/arm/mach-snapdragon/Makefile | 2 +
.../include/mach/sysmap-qcs404.h | 13 +++
arch/arm/mach-snapdragon/sysmap-qcs404.c | 31 +++
board/qualcomm/qcs404-evb/Kconfig | 15
board/qualcomm/qcs404-evb/MAINTAINERS | 6 ++
board/qualcomm/qcs404-evb/Makefile| 6 ++
board/qualcomm/qcs404-evb/qcs404-evb.c| 33
board/qualcomm/qcs404-evb/qcs404-evb.its | 64 +++
configs/qcs404evb_defconfig | 39 +
doc/board/qualcomm/index.rst | 1 +
doc/board/qualcomm/qcs404.rst | 79 ++
include/configs/qcs404-evb.h | 27 +++
16 files changed, 433 insertions(+)
create mode 100644 arch/arm/dts/qcs404-evb-uboot.dtsi
create mode 100644 arch/arm/dts/qcs404-evb.dts
create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
create mode 100644 arch/arm/mach-snapdragon/sysmap-qcs404.c
create mode 100644 board/qualcomm/qcs404-evb/Kconfig
create mode 100644 board/qualcomm/qcs404-evb/MAINTAINERS
create mode 100644 board/qualcomm/qcs404-evb/Makefile
create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.c
create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.its
create mode 100644 configs/qcs404evb_defconfig
create mode 100644 doc/board/qualcomm/qcs404.rst
create mode 100644 include/configs/qcs404-evb.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a7e0d9f6c0..a561b28cef 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -502,6 +502,7 @@ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
+dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
diff --git a/arch/arm/dts/qcs404-evb-uboot.dtsi
b/arch/arm/dts/qcs404-evb-uboot.dtsi
new file mode 100644
index 00..c18080a483
--- /dev/null
+++ b/arch/arm/dts/qcs404-evb-uboot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot addition to handle QCS404 EVB pre-relocation devices
+ *
+ * (C) Copyright 2022 Sumit Garg
+ */
+
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+
+ pinctrl_north@130 {
+ u-boot,dm-pre-reloc;
+ };
+
+ clock-controller@180 {
+ u-boot,dm-pre-reloc;
+ };
+
+ serial@78b1000 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts
new file mode 100644
index 00..4f0ae20bdb
--- /dev/null
+++ b/arch/arm/dts/qcs404-evb.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm QCS404 based evaluation board device tree source
+ *
+ * (C) Copyright 2022 Sumit Garg
+ */
+
+/dts-v1/;
+
+#include "skeleton64.dtsi"
+#include
+#include
+#include
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCS404 EVB";
+ compatible = "qcom,qcs404-evb", "qcom,qcs404";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = _uart;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x8000 0 0x4000>;
+ };
+
+ soc {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges = <0x0 0x0 0x0 0x>;
+ compatible = "simple-bus";
+
+ pinctrl_north@130 {
+ compatible = "qcom,tlmm-qcs404";
+ reg = <0x130 0x20>;
+
+ blsp1_uart2: uart {
+ pins = "GPIO_17", "GPIO_18";
+ function = "blsp_uart2";
+ };
+ };
+
+ gcc: clock-controller@180 {
+ compatible = "qcom,gcc-qcs404";
+ reg = <0x180 0x8>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ debug_uart: serial@78b1000 {
+ compatible =
[PATCH 7/8] clocks: qcom: Add clock driver for QCS404 SoC
Currently its a dummy clock driver as clocks for UART and eMMC have been
already enabled by ABL. Along with this import "qcom,gcc-qcs404.h" header
from Linux mainline to support DT bindings.
Signed-off-by: Sumit Garg
---
arch/arm/mach-snapdragon/clock-qcs404.c | 30
arch/arm/mach-snapdragon/clock-snapdragon.c | 1 +
include/dt-bindings/clock/qcom,gcc-qcs404.h | 180
3 files changed, 211 insertions(+)
create mode 100644 arch/arm/mach-snapdragon/clock-qcs404.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-qcs404.h
diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c
b/arch/arm/mach-snapdragon/clock-qcs404.c
new file mode 100644
index 00..0471adf0ba
--- /dev/null
+++ b/arch/arm/mach-snapdragon/clock-qcs404.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm QCS404
+ *
+ * (C) Copyright 2022 Sumit Garg
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "clock-snapdragon.h"
+
+#include
+
+ulong msm_set_rate(struct clk *clk, ulong rate)
+{
+ switch (clk->id) {
+ default:
+ /*
+* Clocks for UART and eMMC enabled in u-boot are already
+* initialized by ABL. In case any peripheral requires special
+* clock handling then that should be handled as a separate
+* case above.
+*/
+ return 0;
+ }
+}
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c
b/arch/arm/mach-snapdragon/clock-snapdragon.c
index 3deb08ac4a..5652d2fa36 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -136,6 +136,7 @@ static const struct udevice_id msm_clk_ids[] = {
{ .compatible = "qcom,gcc-msm8996" },
{ .compatible = "qcom,gcc-apq8096" },
{ .compatible = "qcom,gcc-sdm845" },
+ { .compatible = "qcom,gcc-qcs404" },
{ }
};
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h
b/include/dt-bindings/clock/qcom,gcc-qcs404.h
new file mode 100644
index 00..bc30515433
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
+
+#define GCC_APSS_AHB_CLK_SRC 0
+#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC1
+#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC2
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC3
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC4
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC5
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC6
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC7
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC8
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC9
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC10
+#define GCC_BLSP1_UART0_APPS_CLK_SRC 11
+#define GCC_BLSP1_UART1_APPS_CLK_SRC 12
+#define GCC_BLSP1_UART2_APPS_CLK_SRC 13
+#define GCC_BLSP1_UART3_APPS_CLK_SRC 14
+#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC15
+#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC16
+#define GCC_BLSP2_UART0_APPS_CLK_SRC 17
+#define GCC_BYTE0_CLK_SRC 18
+#define GCC_EMAC_CLK_SRC 19
+#define GCC_EMAC_PTP_CLK_SRC 20
+#define GCC_ESC0_CLK_SRC 21
+#define GCC_APSS_AHB_CLK 22
+#define GCC_APSS_AXI_CLK 23
+#define GCC_BIMC_APSS_AXI_CLK 24
+#define GCC_BIMC_GFX_CLK 25
+#define GCC_BIMC_MDSS_CLK 26
+#define GCC_BLSP1_AHB_CLK 27
+#define GCC_BLSP1_QUP0_I2C_APPS_CLK28
+#define GCC_BLSP1_QUP0_SPI_APPS_CLK29
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK30
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK31
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK32
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK33
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK34
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK35
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK36
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK37
+#define GCC_BLSP1_UART0_APPS_CLK 38
+#define GCC_BLSP1_UART1_APPS_CLK 39
+#define GCC_BLSP1_UART2_APPS_CLK 40
+#define GCC_BLSP1_UART3_APPS_CLK 41
+#define
[PATCH 6/8] pinctrl: qcom: Add pinctrl driver for QCS404 SoC
Currently this pinctrl driver only supports BLSP UART2 specific pin
configuration.
Signed-off-by: Sumit Garg
---
arch/arm/mach-snapdragon/Makefile | 1 +
arch/arm/mach-snapdragon/pinctrl-qcs404.c | 55 +++
arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 +
arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 +
4 files changed, 58 insertions(+)
create mode 100644 arch/arm/mach-snapdragon/pinctrl-qcs404.c
diff --git a/arch/arm/mach-snapdragon/Makefile
b/arch/arm/mach-snapdragon/Makefile
index 962855eb8c..cb8c1aa8d2 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -15,4 +15,5 @@ obj-y += dram.o
obj-y += pinctrl-snapdragon.o
obj-y += pinctrl-apq8016.o
obj-y += pinctrl-apq8096.o
+obj-y += pinctrl-qcs404.o
obj-$(CONFIG_SDM845) += pinctrl-sdm845.o
diff --git a/arch/arm/mach-snapdragon/pinctrl-qcs404.c
b/arch/arm/mach-snapdragon/pinctrl-qcs404.c
new file mode 100644
index 00..889ead0f57
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-qcs404.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm QCS404 pinctrl
+ *
+ * (C) Copyright 2022 Sumit Garg
+ */
+
+#include "pinctrl-snapdragon.h"
+#include
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const char * const msm_pinctrl_pins[] = {
+ "SDC1_RCLK",
+ "SDC1_CLK",
+ "SDC1_CMD",
+ "SDC1_DATA",
+ "SDC2_CLK",
+ "SDC2_CMD",
+ "SDC2_DATA",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"blsp_uart2", 1},
+};
+
+static const char *qcs404_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static const char *qcs404_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ if (selector < 120) {
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+ return pin_name;
+ } else {
+ return msm_pinctrl_pins[selector - 120];
+ }
+}
+
+static unsigned int qcs404_get_function_mux(unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].val;
+}
+
+struct msm_pinctrl_data qcs404_data = {
+ .pin_count = 126,
+ .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ .get_function_name = qcs404_get_function_name,
+ .get_function_mux = qcs404_get_function_mux,
+ .get_pin_name = qcs404_get_pin_name,
+};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
index d1c560dd40..c2148a5d0a 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -119,6 +119,7 @@ static const struct udevice_id msm_pinctrl_ids[] = {
#ifdef CONFIG_SDM845
{ .compatible = "qcom,tlmm-sdm845", .data = (ulong)_data },
#endif
+ { .compatible = "qcom,tlmm-qcs404", .data = (ulong)_data },
{ }
};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
index ea524312a0..178ee01a41 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
@@ -28,5 +28,6 @@ struct pinctrl_function {
extern struct msm_pinctrl_data apq8016_data;
extern struct msm_pinctrl_data apq8096_data;
extern struct msm_pinctrl_data sdm845_data;
+extern struct msm_pinctrl_data qcs404_data;
#endif
--
2.25.1
[PATCH 5/8] mmc: msm_sdhci: Add SDCC version 5.0.0 support
For SDCC version 5.0.0, MCI registers are removed from SDCC interface
and some registers are moved to HC. So add support to use the new
compatible string "qcom,sdhci-msm-v5". Based on this new msm variant,
pick the relevant variant data and use it to detect MCI presence thereby
configuring register read/write to msm specific registers.
Signed-off-by: Sumit Garg
---
drivers/mmc/msm_sdhci.c | 96 +++--
1 file changed, 64 insertions(+), 32 deletions(-)
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index d63d7b3a2c..604f9c3ff9 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -22,18 +22,17 @@
#define SDCC_MCI_POWER_SW_RST BIT(7)
/* This is undocumented register */
-#define SDCC_MCI_VERSION 0x50
-#define SDCC_MCI_VERSION_MAJOR_SHIFT 28
-#define SDCC_MCI_VERSION_MAJOR_MASK (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT)
-#define SDCC_MCI_VERSION_MINOR_MASK 0xff
+#define SDCC_MCI_VERSION 0x50
+#define SDCC_V5_VERSION0x318
+
+#define SDCC_VERSION_MAJOR_SHIFT 28
+#define SDCC_VERSION_MAJOR_MASK(0xf <<
SDCC_VERSION_MAJOR_SHIFT)
+#define SDCC_VERSION_MINOR_MASK0xff
#define SDCC_MCI_STATUS2 0x6C
#define SDCC_MCI_STATUS2_MCI_ACT 0x1
#define SDCC_MCI_HC_MODE 0x78
-/* Offset to SDHCI registers */
-#define SDCC_SDHCI_OFFSET 0x900
-
/* Non standard (?) SDHCI register */
#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c
@@ -47,6 +46,10 @@ struct msm_sdhc {
void *base;
};
+struct msm_sdhc_variant_info {
+ bool mci_removed;
+};
+
DECLARE_GLOBAL_DATA_PTR;
static int msm_sdc_clk_init(struct udevice *dev)
@@ -85,25 +88,8 @@ static int msm_sdc_clk_init(struct udevice *dev)
return 0;
}
-static int msm_sdc_probe(struct udevice *dev)
+static int msm_sdc_mci_init(struct msm_sdhc *prv)
{
- struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct msm_sdhc_plat *plat = dev_get_plat(dev);
- struct msm_sdhc *prv = dev_get_priv(dev);
- struct sdhci_host *host = >host;
- u32 core_version, core_minor, core_major;
- u32 caps;
- int ret;
-
- host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
-
- host->max_clk = 0;
-
- /* Init clocks */
- ret = msm_sdc_clk_init(dev);
- if (ret)
- return ret;
-
/* Reset the core and Enable SDHC mode */
writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
prv->base + SDCC_MCI_POWER);
@@ -126,12 +112,45 @@ static int msm_sdc_probe(struct udevice *dev)
/* Enable host-controller mode */
writel(1, prv->base + SDCC_MCI_HC_MODE);
- core_version = readl(prv->base + SDCC_MCI_VERSION);
+ return 0;
+}
- core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK);
- core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT;
+static int msm_sdc_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct msm_sdhc_plat *plat = dev_get_plat(dev);
+ struct msm_sdhc *prv = dev_get_priv(dev);
+ const struct msm_sdhc_variant_info *var_info;
+ struct sdhci_host *host = >host;
+ u32 core_version, core_minor, core_major;
+ u32 caps;
+ int ret;
- core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK;
+ host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
+
+ host->max_clk = 0;
+
+ /* Init clocks */
+ ret = msm_sdc_clk_init(dev);
+ if (ret)
+ return ret;
+
+ var_info = (void *)dev_get_driver_data(dev);
+ if (!var_info->mci_removed) {
+ ret = msm_sdc_mci_init(prv);
+ if (ret)
+ return ret;
+ }
+
+ if (!var_info->mci_removed)
+ core_version = readl(prv->base + SDCC_MCI_VERSION);
+ else
+ core_version = readl(host->ioaddr + SDCC_V5_VERSION);
+
+ core_major = (core_version & SDCC_VERSION_MAJOR_MASK);
+ core_major >>= SDCC_VERSION_MAJOR_SHIFT;
+
+ core_minor = core_version & SDCC_VERSION_MINOR_MASK;
/*
* Support for some capabilities is not advertised by newer
@@ -161,9 +180,13 @@ static int msm_sdc_probe(struct udevice *dev)
static int msm_sdc_remove(struct udevice *dev)
{
struct msm_sdhc *priv = dev_get_priv(dev);
+ const struct msm_sdhc_variant_info *var_info;
+
+ var_info = (void *)dev_get_driver_data(dev);
-/* Disable host-controller mode */
- writel(0, priv->base + SDCC_MCI_HC_MODE);
+ /* Disable host-controller mode */
+ if (!var_info->mci_removed)
+ writel(0, priv->base + SDCC_MCI_HC_MODE);
return 0;
}
@@ -195,8 +218,17 @@ static int msm_sdc_bind(struct udevice *dev)
return sdhci_bind(dev, >mmc, >cfg);
}
+static const struct msm_sdhc_variant_info msm_sdhc_mci_var = {
+
[PATCH 4/8] board: qualcomm: Add support for dragonboard845c
Add support for 96Boards Dragonboard 845C aka Robotics RB3 development
platform. This board complies with 96Boards Open Platform Specifications.
Features:
- Qualcomm Snapdragon SDA845 SoC
- 4GiB RAM
- 64GiB UFS drive
U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.
For detailed build and boot instructions, refer to
doc/board/qualcomm/sdm845.rst, board: dragonboard845c.
Signed-off-by: Sumit Garg
---
arch/arm/dts/dragonboard845c-uboot.dtsi | 37 +++
arch/arm/dts/dragonboard845c.dts | 44
arch/arm/mach-snapdragon/Kconfig | 14 +++
board/qualcomm/dragonboard845c/Kconfig| 12 +++
board/qualcomm/dragonboard845c/MAINTAINERS| 6 ++
board/qualcomm/dragonboard845c/Makefile | 9 ++
board/qualcomm/dragonboard845c/db845c.its | 63 +++
.../dragonboard845c/dragonboard845c.c | 9 ++
configs/dragonboard845c_defconfig | 28 +
doc/board/qualcomm/sdm845.rst | 100 +++---
include/configs/dragonboard845c.h | 28 +
11 files changed, 337 insertions(+), 13 deletions(-)
create mode 100644 arch/arm/dts/dragonboard845c-uboot.dtsi
create mode 100644 arch/arm/dts/dragonboard845c.dts
create mode 100644 board/qualcomm/dragonboard845c/Kconfig
create mode 100644 board/qualcomm/dragonboard845c/MAINTAINERS
create mode 100644 board/qualcomm/dragonboard845c/Makefile
create mode 100644 board/qualcomm/dragonboard845c/db845c.its
create mode 100644 board/qualcomm/dragonboard845c/dragonboard845c.c
create mode 100644 configs/dragonboard845c_defconfig
create mode 100644 include/configs/dragonboard845c.h
diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi
b/arch/arm/dts/dragonboard845c-uboot.dtsi
new file mode 100644
index 00..8b5a7ee573
--- /dev/null
+++ b/arch/arm/dts/dragonboard845c-uboot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot addition to handle Qualcomm Robotics RB3 Development Platform
+ * (dragonboard845c) pins
+ *
+ * (C) Copyright 2022 Sumit Garg
+ */
+
+/
+{
+ soc {
+ u-boot,dm-pre-reloc;
+
+ serial@a84000 {
+ u-boot,dm-pre-reloc;
+ };
+
+ clock-controller@10 {
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_north@390 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+_pon {
+ key_vol_down {
+ gpios = <_pon 1 0>;
+ label = "key_vol_down";
+ };
+ key_power {
+ gpios = <_pon 0 0>;
+ label = "key_power";
+ };
+};
diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts
new file mode 100644
index 00..1722dce33f
--- /dev/null
+++ b/arch/arm/dts/dragonboard845c.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm Robotics RB3 Development (dragonboard845c) board device
+ * tree source
+ *
+ * (C) Copyright 2022 Sumit Garg
+ */
+
+/dts-v1/;
+
+#include "sdm845.dtsi"
+
+/ {
+ model = "Thundercomm Dragonboard 845c";
+ compatible = "thundercomm,db845c", "qcom,sdm845";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = _uart;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x8000 0 0xfdfa>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc: soc {
+ serial@a84000 {
+ status = "okay";
+ };
+ };
+};
+
+#include "dragonboard845c-uboot.dtsi"
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index 12cf02a56a..34af40b915 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -44,6 +44,19 @@ config TARGET_DRAGONBOARD820C
- 3GiB RAM
- 32GiB UFS drive
+config TARGET_DRAGONBOARD845C
+ bool "96Boards Dragonboard 845C"
+ help
+ Support for 96Boards Dragonboard 845C aka Robotics RB3 Development
+ Platform. This board complies with 96Board Open Platform
+ Specifications. Features:
+ - Qualcomm Snapdragon SDA845 SoC
+ - 4GiB RAM
+ - 64GiB UFS drive
+ select MISC_INIT_R
+ select SDM845
+ select DM_ETH if NET
+
config TARGET_STARQLTECHN
bool "Samsung S9 SM-G9600(starqltechn)"
help
@@ -60,6 +73,7 @@ endchoice
source "board/qualcomm/dragonboard410c/Kconfig"
source "board/qualcomm/dragonboard820c/Kconfig"
+source "board/qualcomm/dragonboard845c/Kconfig"
source "board/samsung/starqltechn/Kconfig"
endif
diff --git a/board/qualcomm/dragonboard845c/Kconfig
b/board/qualcomm/dragonboard845c/Kconfig
new file mode 100644
index
[PATCH 3/8] uart: sdm845: Fix debug UART pinmux
Configure debug UART pins as function: "qup9" rather than being regular
gpios. It fixes a hang seen during pinmux setting.
Signed-off-by: Sumit Garg
---
arch/arm/dts/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index b9506f1297..df5b6dfcfc 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -47,7 +47,7 @@
/* DEBUG UART */
qup_uart9: qup-uart9-default {
pins = "GPIO_4", "GPIO_5";
- function = "gpio";
+ function = "qup9";
};
};
--
2.25.1
[PATCH 2/8] clocks: sdm845: Import qcom,gcc-sdm845.h
Rather than using magic numbers as clock ids for peripherals import
qcom,gcc-sdm845.h from Linux to be used standard macros for clock ids.
So start using corresponding clk-id macro for debug UART.
Signed-off-by: Sumit Garg
---
arch/arm/dts/sdm845.dtsi| 3 +-
arch/arm/mach-snapdragon/clock-sdm845.c | 3 +-
include/dt-bindings/clock/qcom,gcc-sdm845.h | 246
3 files changed, 250 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm845.h
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 88030156d9..b9506f1297 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -8,6 +8,7 @@
/dts-v1/;
+#include
#include "skeleton64.dtsi"
/ {
@@ -55,7 +56,7 @@
reg = <0xa84000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk";
- clocks = < 0x58>;
+ clocks = < GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <_uart9>;
qcom,wrapper-core = <0x8a>;
diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c
b/arch/arm/mach-snapdragon/clock-sdm845.c
index 9572639238..f69be80898 100644
--- a/arch/arm/mach-snapdragon/clock-sdm845.c
+++ b/arch/arm/mach-snapdragon/clock-sdm845.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include "clock-snapdragon.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
@@ -84,7 +85,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
- case 0x58: /*UART2*/
+ case GCC_QUPV3_WRAP1_S1_CLK: /*UART2*/
return clk_init_uart(priv, rate);
default:
return 0;
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h
b/include/dt-bindings/clock/qcom,gcc-sdm845.h
new file mode 100644
index 00..968fa65b9c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+
+/* GCC clock registers */
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
+#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK3
+#define GCC_AGGRE_USB3_SEC_AXI_CLK 4
+#define GCC_BOOT_ROM_AHB_CLK 5
+#define GCC_CAMERA_AHB_CLK 6
+#define GCC_CAMERA_AXI_CLK 7
+#define GCC_CAMERA_XO_CLK 8
+#define GCC_CE1_AHB_CLK9
+#define GCC_CE1_AXI_CLK10
+#define GCC_CE1_CLK11
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
+#define GCC_CPUSS_AHB_CLK 14
+#define GCC_CPUSS_AHB_CLK_SRC 15
+#define GCC_CPUSS_RBCPR_CLK16
+#define GCC_CPUSS_RBCPR_CLK_SRC17
+#define GCC_DDRSS_GPU_AXI_CLK 18
+#define GCC_DISP_AHB_CLK 19
+#define GCC_DISP_AXI_CLK 20
+#define GCC_DISP_GPLL0_CLK_SRC 21
+#define GCC_DISP_GPLL0_DIV_CLK_SRC 22
+#define GCC_DISP_XO_CLK23
+#define GCC_GP1_CLK24
+#define GCC_GP1_CLK_SRC25
+#define GCC_GP2_CLK26
+#define GCC_GP2_CLK_SRC27
+#define GCC_GP3_CLK28
+#define GCC_GP3_CLK_SRC29
+#define GCC_GPU_CFG_AHB_CLK30
+#define GCC_GPU_GPLL0_CLK_SRC 31
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 32
+#define GCC_GPU_MEMNOC_GFX_CLK 33
+#define GCC_GPU_SNOC_DVM_GFX_CLK 34
+#define GCC_MSS_AXIS2_CLK 35
+#define GCC_MSS_CFG_AHB_CLK36
+#define GCC_MSS_GPLL0_DIV_CLK_SRC 37
+#define GCC_MSS_MFAB_AXIS_CLK
