Re: [PATCH v3 0/2] fpga: Convert some options to Kconfig
On 7/21/22 15:31, Alexander Dahl wrote:
Hei hei,
tried to work on the feedback I got the best I could.
Greets
Alex
v2 -> v3:
- reworded commit messages
- added kconfig help text for SYS_FPGA_CHECK_CTRLC
- removed hardcoded def/undef from drivers
(implicit) v1 -> v2:
- dropped patch 3, same kconfig symbol addressed with commit
60d45642fe0673514aced37e6cc95d4f0fe02a19 ("fpga: Remove
CONFIG_FPGA_COUNT")
Cc: Wolfgang Wegner
Cc: Michal Simek
Cc: Tom Rini
Alexander Dahl (2):
fpga: Convert SYS_FPGA_CHECK_CTRLC to Kconfig
fpga: Convert SYS_FPGA_PROG_FEEDBACK to Kconfig
README | 7 ---
configs/astro_mcf5373l_defconfig | 1 +
drivers/fpga/Kconfig | 13 +
drivers/fpga/spartan2.c | 1 -
drivers/fpga/virtex2.c | 11 ---
include/configs/astro_mcf5373l.h | 1 -
scripts/config_whitelist.txt | 1 -
7 files changed, 14 insertions(+), 21 deletions(-)
base-commit: 88d931a71052fc8fb7b48126ae09aa875745d5ec
Applied.
M
Re: [PATCH v2 0/5] Enable power domain driver in ZynqMP and Versal
On 7/22/22 10:46, Ashok Reddy Soma wrote: This patch series enables power domain driver in ZynqMP and Versal platforms and its dependencies. - Add a preliminary check by loading overlay for APU0 and see if the pmufw accepts the config objects, based on that continue to load further objects or not. - This is needed to dynamically request for node of the IP's based on DT. - Load pmufw config object dynamically based on DT. Changes in v2: - Move static variable to inside zynqmp_pmufw_node and change name to skip_config from config_enabled - Use zynqmp_pmufw_node() in zynqmp_power_probe() to check for APU_0 config loading instead of calling zynqmp_pmufw_load_config_object() Ashok Reddy Soma (5): firmware: zynqmp: Change prototype of zynqmp_pmufw_load_config_object() firmware: zynqmp: Load config overlay for core0 to pmufw arm64: zynqmp: Enable power domain driver mailbox: zynqmp: Move struct zynqmp_ipi_msg from sys_proto.h arm64: versal: Enable power domain driver and its dependencies arch/arm/mach-zynqmp/include/mach/sys_proto.h | 5 configs/xilinx_versal_virt_defconfig | 4 configs/xilinx_zynqmp_virt_defconfig | 2 ++ drivers/firmware/firmware-zynqmp.c| 24 +++ drivers/mailbox/Kconfig | 2 +- drivers/mailbox/zynqmp-ipi.c | 2 +- include/zynqmp_firmware.h | 7 +- 7 files changed, 33 insertions(+), 13 deletions(-) applied. M
Re: [PATCH 0/3] Add reset driver support for ZynqMP and Versal
On 7/20/22 11:59, Ashok Reddy Soma wrote: This patch series does following things - Add reset driver support for Versal platform - Enable reset driver support for ZynqMP and Versal platforms Ashok Reddy Soma (1): arm64: zynqmp: Enable reset driver Michal Simek (1): arm64: versal: Enable reset driver for versal T Karthik Reddy (1): reset: zynqmp: Add reset driver support for versal configs/xilinx_versal_virt_defconfig | 2 ++ configs/xilinx_zynqmp_virt_defconfig | 2 ++ drivers/reset/Kconfig| 6 +++--- drivers/reset/reset-zynqmp.c | 10 +++--- 4 files changed, 14 insertions(+), 6 deletions(-) Applied. M
Re: [PATCH 1/2] xilinx: Wire uuid reading from FRU
On 7/21/22 16:19, Michal Simek wrote:
UUID is already recorded when FRU is parsed but it is not copied to local
structures and exported to variable that's why simply add it.
Data is saved in binary format but there must be conversion to string for
exporting it to variable and string should be in uuid format too.
One way how to use it directly is to setup pxeuuid based on it. For
example via preboot with "setenv pxeuuid ${board_uuid}"
Signed-off-by: Michal Simek
---
Happy to hear if there is more elagant way how to generate uuid string.
---
board/xilinx/common/board.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 5f2afb9def4e..b0c11aaa4256 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
#include "fru.h"
@@ -86,6 +87,7 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
#define EEPROM_HDR_SERIAL_LEN 20
#define EEPROM_HDR_NO_OF_MAC_ADDR 4
#define EEPROM_HDR_ETH_ALEN ETH_ALEN
+#define EEPROM_HDR_UUID_LEN16
struct xilinx_board_description {
u32 header;
@@ -94,6 +96,7 @@ struct xilinx_board_description {
char revision[EEPROM_HDR_REV_LEN + 1];
char serial[EEPROM_HDR_SERIAL_LEN + 1];
u8 mac_addr[EEPROM_HDR_NO_OF_MAC_ADDR][EEPROM_HDR_ETH_ALEN + 1];
+ char uuid[EEPROM_HDR_UUID_LEN + 1];
};
static int highest_id = -1;
@@ -237,6 +240,8 @@ static int xilinx_read_eeprom_fru(struct udevice *dev, char
*name,
/* It is clear that FRU was captured and structures were filled */
strncpy(desc->manufacturer, (char *)fru_data.brd.manufacturer_name,
sizeof(desc->manufacturer));
+ strncpy(desc->uuid, (char *)fru_data.brd.uuid,
+ sizeof(desc->uuid));
strncpy(desc->name, (char *)fru_data.brd.product_name,
sizeof(desc->name));
for (i = 0; i < sizeof(desc->name); i++) {
@@ -452,6 +457,19 @@ int board_late_init_xilinx(void)
ret |= env_set_by_index("serial", id,
desc->serial);
+ if (desc->uuid[0]) {
+ char uuid[UUID_STR_LEN + 1];
+ char *t = desc->uuid;
+
+ memset(uuid, 0, UUID_STR_LEN + 1);
+
+ sprintf(uuid,
"%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x",
+ t[0], t[1], t[2], t[3], t[4], t[5],
+ t[6], t[7], t[8], t[9], t[10], t[11],
+ t[12], t[13], t[14], t[15]);
+ ret |= env_set_by_index("uuid", id, uuid);
+ }
+
if (!CONFIG_IS_ENABLED(NET))
continue;
Applied.
M
[PATCH 1/1] efi_loader: fix efi_convert_device_path_to_text()
Ensure that the string we convert to UTF-16 is NUL terminated even
if the device path only contains end nodes.
Fixes: bd3d75bb0c58 ("efi_loader: multi part device paths to text")
Addresses-Coverity: 350434 ("Uninitialized scalar variable")
Signed-off-by: Heinrich Schuchardt
---
lib/efi_loader/efi_device_path_to_text.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/lib/efi_loader/efi_device_path_to_text.c
b/lib/efi_loader/efi_device_path_to_text.c
index 4d73954ef8..6c428ee061 100644
--- a/lib/efi_loader/efi_device_path_to_text.c
+++ b/lib/efi_loader/efi_device_path_to_text.c
@@ -432,6 +432,7 @@ static uint16_t EFIAPI *efi_convert_device_path_to_text(
*(u8 **)&device_path += device_path->length;
}
+ *str = 0;
text = efi_str_to_u16(buffer);
out:
--
2.36.1
[PATCH v3 7/8] ARM: dts: imx: add i.MXRT1170-EVK support
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 and Cortex-M4 core.
The EVK provides 64 MB SDRAM, Micro SD card socket,
USB 2.0 OTG.
This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
SD/MMC
SDRAM
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Remove unused constant clocks
V2 -> V3:
* Nothing done
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/imxrt1170-evk-u-boot.dtsi | 94 +
arch/arm/dts/imxrt1170-evk.dts | 250
arch/arm/dts/imxrt1170.dtsi| 257 +
4 files changed, 603 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imxrt1170-evk.dts
create mode 100644 arch/arm/dts/imxrt1170.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7fa275ea7c..ccdf643c86 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -974,7 +974,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-kontron-pitx-imx8m.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
- imxrt1020-evk.dtb
+ imxrt1020-evk.dtb \
+ imxrt1170-evk.dtb \
dtb-$(CONFIG_RCAR_GEN2) += \
r8a7790-lager-u-boot.dtb \
diff --git a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
new file mode 100644
index 00..88ff986ba0
--- /dev/null
+++ b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ * Giulio Benetti
+ */
+
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ clocks {
+ u-boot,dm-spl;
+ };
+
+ soc {
+ u-boot,dm-spl;
+ };
+};
+
+&osc {
+ u-boot,dm-spl;
+};
+
+&rcosc16M {
+ u-boot,dm-spl;
+};
+
+&osc32k {
+ u-boot,dm-spl;
+};
+
+&clks {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&gpt1 {
+ u-boot,dm-spl;
+};
+
+&lpuart1 { /* console */
+ u-boot,dm-spl;
+};
+
+&semc {
+ u-boot,dm-spl;
+
+ bank1: bank@0 {
+ u-boot,dm-spl;
+ };
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+
+ imxrt1170-evk {
+ u-boot,dm-spl;
+ pinctrl_lpuart1: lpuart1grp {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ u-boot,dm-spl;
+ };
+ pinctrl_semc: semcgrp {
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts
new file mode 100644
index 00..c2fd0c0392
--- /dev/null
+++ b/arch/arm/dts/imxrt1170-evk.dts
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ * Giulio Benetti
+ */
+
+/dts-v1/;
+#include "imxrt1170.dtsi"
+#include "imxrt1170-evk-u-boot.dtsi"
+#include "imxrt1170-pinfunc.h"
+
+/ {
+ model = "NXP imxrt1170-evk board";
+ compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ tick-timer = &gpt1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x2024 0xf 0x8000 0x400>;
+
+ ocram: ocram@2024 {
+ device_type = "memory";
+ reg = <0x2024 0xf>;
+ };
+
+ sdram: sdram@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x400>;
+ };
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&semc {
+ /*
+* Memory configuration from sdram datasheet IS42S16160J-6BLI
+*/
+ fsl,sdram-mux = /bits/ 8 ;
+ fsl,sdram-control = /bits/ 8 ;
+ fsl,sdram-timing = /bits/ 8 <0x2
+0x2
+0xd
+0x0
+0x8
+0x7
+
+0x0d
+0x0b
+0x00
+0x00
+
+0x00
+0x0A
+0x08
+0x09>;
+
+ bank1: bank@0 {
+ fsl,base-address = <0x8000>;
+
[PATCH v3 8/8] ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig
Add a base defconfig for the i.MXRT1170 Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done V2 -> V3: * Rebase --- configs/imxrt1170-evk_defconfig | 70 + include/configs/imxrt1170-evk.h | 29 ++ 2 files changed, 99 insertions(+) create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 include/configs/imxrt1170-evk.h diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig new file mode 100644 index 00..870ca115d5 --- /dev/null +++ b/configs/imxrt1170-evk_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_ARCH_IMXRT=y +CONFIG_SYS_TEXT_BASE=0x2024 +CONFIG_SYS_MALLOC_LEN=0x8000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_OFFSET=0x8 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imxrt1170-evk" +CONFIG_SPL_TEXT_BASE=0x202C +CONFIG_TARGET_IMXRT1170_EVK=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_SIZE_LIMIT=0x2 +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2034 +CONFIG_SYS_LOAD_ADDR=0x202C +CONFIG_SD_BOOT=y +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_NO_BSS_LIMIT=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 +# CONFIG_SPL_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_MII is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_OF_TRANSLATE is not set +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMXRT1170=y +CONFIG_CLK_IMXRT1170=y +# CONFIG_SPL_DM_GPIO is not set +CONFIG_MXC_GPIO=y +# CONFIG_INPUT is not set +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMXRT=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_IMXRT_SDRAM=y +CONFIG_FSL_LPUART=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h new file mode 100644 index 00..2459fe24e2 --- /dev/null +++ b/include/configs/imxrt1170-evk.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +#ifndef __IMXRT1170_EVK_H +#define __IMXRT1170_EVK_H + +#include + +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 + +/* + * Configuration of the external SDRAM memory + */ + +#define PHYS_SDRAM 0x8000 +#define PHYS_SDRAM_SIZE(64 * 1024 * 1024) + +#define DMAMEM_SZ_ALL (1 * 1024 * 1024) +#define DMAMEM_BASE(PHYS_SDRAM + PHYS_SDRAM_SIZE - \ +DMAMEM_SZ_ALL) +/* For SPL */ +#define CONFIG_SYS_UBOOT_START 0x202403FD +/* For SPL ends */ + +#endif /* __IMXRT1170_EVK_H */ -- 2.36.1
[PATCH v3 6/8] RAM: Add changes for i.MXRT11xx series
The i.MXRT11 series has different offsets for IOCR_MUX, it also can
address 64MiB of SDRAM so add a macro for that.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Nothing done
V2 -> V3:
* Nothing done
---
drivers/ram/imxrt_sdram.c| 9 +
include/dt-bindings/memory/imxrt-sdram.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c
index ca2eec767d..d0a88845cf 100644
--- a/drivers/ram/imxrt_sdram.c
+++ b/drivers/ram/imxrt_sdram.c
@@ -87,12 +87,21 @@ struct imxrt_semc_regs {
u32 sts[16];
};
+#if !defined(TARGET_IMXRT1170_EVK)
#define SEMC_IOCR_MUX_A8_SHIFT 0
#define SEMC_IOCR_MUX_CSX0_SHIFT 3
#define SEMC_IOCR_MUX_CSX1_SHIFT 6
#define SEMC_IOCR_MUX_CSX2_SHIFT 9
#define SEMC_IOCR_MUX_CSX3_SHIFT 12
#define SEMC_IOCR_MUX_RDY_SHIFT15
+#else
+#define SEMC_IOCR_MUX_A8_SHIFT 0
+#define SEMC_IOCR_MUX_CSX0_SHIFT 4
+#define SEMC_IOCR_MUX_CSX1_SHIFT 8
+#define SEMC_IOCR_MUX_CSX2_SHIFT 12
+#define SEMC_IOCR_MUX_CSX3_SHIFT 16
+#define SEMC_IOCR_MUX_RDY_SHIFT20
+#endif
struct imxrt_sdram_mux {
u8 a8;
diff --git a/include/dt-bindings/memory/imxrt-sdram.h
b/include/dt-bindings/memory/imxrt-sdram.h
index acb35bce27..4b3b0c2f50 100644
--- a/include/dt-bindings/memory/imxrt-sdram.h
+++ b/include/dt-bindings/memory/imxrt-sdram.h
@@ -82,6 +82,7 @@
#define MEM_WIDTH_8BITS0x0
#define MEM_WIDTH_16BITS 0x1
+#define MEM_WIDTH_32BITS 0x2
#define BL_1 0x0
#define BL_2 0x1
--
2.36.1
[PATCH v3 5/8] clk: imx: Add initial support for i.MXRT1170 clock driver
Add clock driver support for i.MXRT1170.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Use C file not dts for constant clock divider
V2 -> V3:
* Nothing done
---
drivers/clk/imx/Kconfig | 16 +++
drivers/clk/imx/Makefile| 1 +
drivers/clk/imx/clk-imxrt1170.c | 221
3 files changed, 238 insertions(+)
create mode 100644 drivers/clk/imx/clk-imxrt1170.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 04d252a1e0..abcb19ce6d 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -124,3 +124,19 @@ config CLK_IMXRT1050
select CLK_COMPOSITE_CCF
help
This enables support clock driver for i.MXRT1050 platforms.
+
+config SPL_CLK_IMXRT1170
+ bool "SPL clock support for i.MXRT1170"
+ depends on ARCH_IMXRT && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MXRT1170.
+
+config CLK_IMXRT1170
+ bool "Clock support for i.MXRT1170"
+ depends on ARCH_IMXRT
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MXRT1170 platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index c5766901f2..b9c197f952 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o
clk-pll14xx.o \
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1170) += clk-imxrt1170.o
diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
new file mode 100644
index 00..077dd1bf02
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1170.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static ulong imxrt1170_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imxrt1170_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int __imxrt1170_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imxrt1170_clk_disable(struct clk *clk)
+{
+ return __imxrt1170_clk_enable(clk, 0);
+}
+
+static int imxrt1170_clk_enable(struct clk *clk)
+{
+ return __imxrt1170_clk_enable(clk, 1);
+}
+
+static int imxrt1170_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, &cp);
+ if (ret)
+ return ret;
+
+ return clk_set_parent(c, cp);
+}
+
+static struct clk_ops imxrt1170_clk_ops = {
+ .set_rate = imxrt1170_clk_set_rate,
+ .get_rate = imxrt1170_clk_get_rate,
+ .enable = imxrt1170_clk_enable,
+ .disable = imxrt1170_clk_disable,
+ .set_parent = imxrt1170_clk_set_parent,
+};
+
+static const char * const lpuart1_sels[] = {"rcosc48M_div2", "osc",
"rcosc400M", "rcosc16M",
+"pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3"};
+static const char * const gpt1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3"};
+static const char * const usdhc1_sels[] = {"rcosc48M_div2", "osc",
"rcosc400M", "rcosc16M",
+"pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm"};
+static const char * const semc_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll1_div5", "pll2_sys", "pll2_pfd2", "pll3_pfd0"};
+
+static int imxrt1170_clk_probe(struct udevice *dev)
+{
+ void *base;
+
+ /* Anatop clocks */
+ base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(),
"fsl,imxrt-anatop"));
+
+
+
+ clk_dm(IMXRT1170_CLK_RCOSC_48M,
+ imx_clk_fixed_factor("rcosc48M", "rcosc16M", 3, 1));
+ clk_dm(IMXRT1170_CLK_RCOSC_400M,
+ imx_clk_fixed_factor("rcosc400M", "rcosc16M", 25, 1));
+ clk_dm(IMXRT1170_CLK_RCOSC_48M_DIV2,
+
[PATCH v3 4/8] clk: imx: Add i.MXRT11xx pllv3 variant
The i.MXRT11 series has two new pll types but are variants of existing.
This patch adds the ability to read one of the pll types' frequency
as it can't be changed unlike the generic pll it also has the
division factors swapped.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Change BM_PLL_POWER and BM_PLL_LOCK bit to variable
* Use different lock and power bit for new pll
V2 -> V3:
* Nothing done
---
drivers/clk/imx/clk-pllv3.c | 56 +++--
drivers/clk/imx/clk.h | 1 +
2 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 077757efcb..fad306aeed 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -21,19 +21,23 @@
#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
#define UBOOT_DM_CLK_IMX_PLLV3_ENET "imx_clk_pllv3_enet"
+#define UBOOT_DM_CLK_IMX_PLLV3_GENV2 "imx_clk_pllv3_genericv2"
#define PLL_NUM_OFFSET 0x10
#define PLL_DENOM_OFFSET 0x20
#define BM_PLL_POWER (0x1 << 12)
+#define BM_PLL_POWER_V2(0x1 << 21)
#define BM_PLL_ENABLE (0x1 << 13)
#define BM_PLL_LOCK(0x1 << 31)
+#define BM_PLL_LOCK_V2 (0x1 << 29)
struct clk_pllv3 {
struct clk clk;
void __iomem*base;
u32 power_bit;
boolpowerup_set;
+ u32 lock_bit;
u32 enable_bit;
u32 div_mask;
u32 div_shift;
@@ -42,6 +46,30 @@ struct clk_pllv3 {
#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
+static ulong clk_pllv3_genericv2_get_rate(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
+
+ return (div == 0) ? parent_rate * 22 : parent_rate * 20;
+}
+
+static ulong clk_pllv3_genericv2_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
+ u32 val = (div == 0) ? parent_rate * 22 : parent_rate * 20;
+
+ if (rate == val)
+ return 0;
+
+ return -EINVAL;
+}
+
static ulong clk_pllv3_generic_get_rate(struct clk *clk)
{
struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
@@ -71,7 +99,7 @@ static ulong clk_pllv3_generic_set_rate(struct clk *clk,
ulong rate)
writel(val, pll->base);
/* Wait for PLL to lock */
- while (!(readl(pll->base) & BM_PLL_LOCK))
+ while (!(readl(pll->base) & pll->lock_bit))
;
return 0;
@@ -120,6 +148,13 @@ static const struct clk_ops clk_pllv3_generic_ops = {
.set_rate = clk_pllv3_generic_set_rate,
};
+static const struct clk_ops clk_pllv3_genericv2_ops = {
+ .get_rate = clk_pllv3_genericv2_get_rate,
+ .enable = clk_pllv3_generic_enable,
+ .disable= clk_pllv3_generic_disable,
+ .set_rate = clk_pllv3_genericv2_set_rate,
+};
+
static ulong clk_pllv3_sys_get_rate(struct clk *clk)
{
struct clk_pllv3 *pll = to_clk_pllv3(clk);
@@ -153,7 +188,7 @@ static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong
rate)
writel(val, pll->base);
/* Wait for PLL to lock */
- while (!(readl(pll->base) & BM_PLL_LOCK))
+ while (!(readl(pll->base) & pll->lock_bit))
;
return 0;
@@ -221,7 +256,7 @@ static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong
rate)
writel(mfd, pll->base + PLL_DENOM_OFFSET);
/* Wait for PLL to lock */
- while (!(readl(pll->base) & BM_PLL_LOCK))
+ while (!(readl(pll->base) & pll->lock_bit))
;
return 0;
@@ -262,6 +297,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const
char *name,
pll->power_bit = BM_PLL_POWER;
pll->enable_bit = BM_PLL_ENABLE;
+ pll->lock_bit = BM_PLL_LOCK;
switch (type) {
case IMX_PLLV3_GENERIC:
@@ -269,6 +305,13 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const
char *name,
pll->div_shift = 0;
pll->powerup_set = false;
break;
+ case IMX_PLLV3_GENERICV2:
+ pll->power_bit = BM_PLL_POWER_V2;
+ pll->lock_bit = BM_PLL_LOCK_V2;
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENV2;
+ pll->div_shift = 0;
+ pll->powerup_set = false;
+ break;
case IMX_PLLV3_SYS:
drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
pll->div_shift = 0;
@@ -313,6 +356,13 @@ U_BOOT_DRIVER(clk_pllv3_generic) = {
.flags = DM_FLAG_PRE_RELOC,
[PATCH v3 3/8] dt-bindings: imx: Add clock binding for i.MXRT1170
Add the clock binding doc for i.MXRT1170. Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done V2 -> V3: * Nothing done --- include/dt-bindings/clock/imxrt1170-clock.h | 48 + 1 file changed, 48 insertions(+) create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h diff --git a/include/dt-bindings/clock/imxrt1170-clock.h b/include/dt-bindings/clock/imxrt1170-clock.h new file mode 100644 index 00..8ab8018a15 --- /dev/null +++ b/include/dt-bindings/clock/imxrt1170-clock.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + */ + +#ifndef __DT_BINDINGS_CLOCK_IMXRT1170_H +#define __DT_BINDINGS_CLOCK_IMXRT1170_H + +#define IMXRT1170_CLK_DUMMY0 +#define IMXRT1170_CLK_OSC 1 +#define IMXRT1170_CLK_OSC_32K 2 +#define IMXRT1170_CLK_RCOSC_16M3 +#define IMXRT1170_CLK_RCOSC_48M4 +#define IMXRT1170_CLK_RCOSC_48M_DIV2 5 +#define IMXRT1170_CLK_RCOSC_400M 6 +#define IMXRT1170_CLK_PLL_ARM 7 +#define IMXRT1170_CLK_PLL_AUDIO8 +#define IMXRT1170_CLK_PLL_VIDEO9 +#define IMXRT1170_CLK_PLL1 10 +#define IMXRT1170_CLK_PLL1_DIV211 +#define IMXRT1170_CLK_PLL1_DIV512 +#define IMXRT1170_CLK_PLL2 13 +#define IMXRT1170_CLK_PLL2_PFD014 +#define IMXRT1170_CLK_PLL2_PFD115 +#define IMXRT1170_CLK_PLL2_PFD216 +#define IMXRT1170_CLK_PLL2_PFD317 +#define IMXRT1170_CLK_PLL3 18 +#define IMXRT1170_CLK_PLL3_DIV219 +#define IMXRT1170_CLK_PLL3_PFD020 +#define IMXRT1170_CLK_PLL3_PFD121 +#define IMXRT1170_CLK_PLL3_PFD222 +#define IMXRT1170_CLK_PLL3_PFD323 +#define IMXRT1170_CLK_M7 24 +#define IMXRT1170_CLK_M4 25 +#define IMXRT1170_CLK_BUS 26 +#define IMXRT1170_CLK_BUS_LPSR 27 +#define IMXRT1170_CLK_LPUART1_SEL 28 +#define IMXRT1170_CLK_LPUART1 29 +#define IMXRT1170_CLK_USDHC1_SEL 30 +#define IMXRT1170_CLK_USDHC1 31 +#define IMXRT1170_CLK_GPT1_SEL 32 +#define IMXRT1170_CLK_GPT1 33 +#define IMXRT1170_CLK_SEMC_SEL 34 +#define IMXRT1170_CLK_SEMC 35 +#define IMXRT1170_CLK_END 36 + +#endif /* __DT_BINDINGS_CLOCK_IMXRT1170_H */ -- 2.36.1
[PATCH v3 2/8] ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header
Add binding header for i.MXRT1170 pinctrl device tree. Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done V2 -> V3: * Nothing done --- arch/arm/dts/imxrt1170-pinfunc.h | 1561 ++ 1 file changed, 1561 insertions(+) create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h diff --git a/arch/arm/dts/imxrt1170-pinfunc.h b/arch/arm/dts/imxrt1170-pinfunc.h new file mode 100644 index 00..fba5483a08 --- /dev/null +++ b/arch/arm/dts/imxrt1170-pinfunc.h @@ -0,0 +1,1561 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * Author(s): Jesse Taube + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H + +#define IMX_PAD_SION 0x4000 + +/* + * The pin function ID is a tuple of + * + */ + +#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX0x000 0x040 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_00_MIC_CLK0x000 0x040 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO12_IO000x000 0x040 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX0x004 0x044 0x080 0x0 0x0 +#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0 +#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO12_IO010x004 0x044 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_02_GPIO12_IO020x008 0x048 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE000x008 0x048 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0 +#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0 + +#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE010x00C 0x04C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS00x00C 0x04C 0x094 0x1 0x0 +#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0 +#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO12_IO030x00C 0x04C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0 +#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT0x010 0x050 0x0A0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO12_IO040x010 0x050 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_05_GPIO12_IO050x014 0x054 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0 +#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0 +#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1 +#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0 +#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0 + +#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0 +#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1 +#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3
[PATCH v3 1/8] imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK
This commit adds board support for i.MXRT1170-EVK from NXP. This board is an evaluation kit provided by NXP for i.MXRT117x processor family. Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done V2 -> V3: * Rebase --- arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/mach-imx/imxrt/Kconfig | 9 +++ arch/arm/mach-imx/imxrt/soc.c | 2 + board/freescale/imxrt1170-evk/Kconfig | 22 + board/freescale/imxrt1170-evk/MAINTAINERS | 7 ++ board/freescale/imxrt1170-evk/Makefile| 6 ++ board/freescale/imxrt1170-evk/imximage.cfg| 31 +++ board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 +++ 8 files changed, 158 insertions(+) create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 4f63803765..09767be1ca 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -56,6 +56,7 @@ #define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */ #define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */ +#define MXC_CPU_IMXRT1170 0xBA /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig index 8c89133965..c1d6b09e77 100644 --- a/arch/arm/mach-imx/imxrt/Kconfig +++ b/arch/arm/mach-imx/imxrt/Kconfig @@ -12,6 +12,10 @@ config IMXRT1050 bool select IMXRT +config IMXRT1170 + bool + select IMXRT + config SYS_SOC default "imxrt" @@ -27,9 +31,14 @@ config TARGET_IMXRT1050_EVK bool "Support imxrt1050 EVK board" select IMXRT1050 +config TARGET_IMXRT1170_EVK + bool "Support imxrt1170 EVK board" + select IMXRT1170 + endchoice source "board/freescale/imxrt1020-evk/Kconfig" source "board/freescale/imxrt1050-evk/Kconfig" +source "board/freescale/imxrt1170-evk/Kconfig" endif diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c index ba015992ee..34162a3976 100644 --- a/arch/arm/mach-imx/imxrt/soc.c +++ b/arch/arm/mach-imx/imxrt/soc.c @@ -43,6 +43,8 @@ u32 get_cpu_rev(void) return MXC_CPU_IMXRT1020 << 12; #elif defined(CONFIG_IMXRT1050) return MXC_CPU_IMXRT1050 << 12; +#elif defined(CONFIG_IMXRT1170) + return MXC_CPU_IMXRT1170 << 12; #else #error This IMXRT SoC is not supported #endif diff --git a/board/freescale/imxrt1170-evk/Kconfig b/board/freescale/imxrt1170-evk/Kconfig new file mode 100644 index 00..c61fc57971 --- /dev/null +++ b/board/freescale/imxrt1170-evk/Kconfig @@ -0,0 +1,22 @@ +if TARGET_IMXRT1170_EVK + +config SYS_BOARD + string + default "imxrt1170-evk" + +config SYS_VENDOR + string + default "freescale" + +config SYS_SOC + string + default "imxrt1170" + +config SYS_CONFIG_NAME + string + default "imxrt1170-evk" + +config IMX_CONFIG + default "board/freescale/imxrt1170-evk/imximage.cfg" + +endif diff --git a/board/freescale/imxrt1170-evk/MAINTAINERS b/board/freescale/imxrt1170-evk/MAINTAINERS new file mode 100644 index 00..1fc3179c00 --- /dev/null +++ b/board/freescale/imxrt1170-evk/MAINTAINERS @@ -0,0 +1,7 @@ +IMXRT1170 EVALUATION KIT +M: Giulio Benetti +M: Jesse Taube +S: Maintained +F: board/freescale/imxrt1170-evk +F: include/configs/imxrt1170-evk.h +F: configs/imxrt1170-evk_defconfig diff --git a/board/freescale/imxrt1170-evk/Makefile b/board/freescale/imxrt1170-evk/Makefile new file mode 100644 index 00..857a168b09 --- /dev/null +++ b/board/freescale/imxrt1170-evk/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 +# Author(s): Giulio Benetti + +obj-y := imxrt1170-evk.o diff --git a/board/freescale/imxrt1170-evk/imximage.cfg b/board/freescale/imxrt1170-evk/imximage.cfg new file mode 100644 index 00..57583d04ce --- /dev/null +++ b/board/freescale/imxrt1170-evk/imximage.cfg @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ diff --git a/board/freescale/imxrt1170-evk/imxrt1170-evk.c b/board/freescale/imxrt11
[PATCH v3 0/8] Add support for the i.MXRT1170
This patchset contains: - i.MXRT1170 clock driver adaption - i.MXRT1170-evk basic support Jesse Taube (8): imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header dt-bindings: imx: Add clock binding for i.MXRT1170 clk: imx: Add i.MXRT11xx pllv3 variant clk: imx: Add initial support for i.MXRT1170 clock driver RAM: Add changes for i.MXRT11xx series ARM: dts: imx: add i.MXRT1170-EVK support ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig arch/arm/dts/Makefile |3 +- arch/arm/dts/imxrt1170-evk-u-boot.dtsi| 94 + arch/arm/dts/imxrt1170-evk.dts| 250 +++ arch/arm/dts/imxrt1170-pinfunc.h | 1561 + arch/arm/dts/imxrt1170.dtsi | 257 +++ arch/arm/include/asm/arch-imx/cpu.h |1 + arch/arm/mach-imx/imxrt/Kconfig |9 + arch/arm/mach-imx/imxrt/soc.c |2 + board/freescale/imxrt1170-evk/Kconfig | 22 + board/freescale/imxrt1170-evk/MAINTAINERS |7 + board/freescale/imxrt1170-evk/Makefile|6 + board/freescale/imxrt1170-evk/imximage.cfg| 31 + board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 + configs/imxrt1170-evk_defconfig | 70 + drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile |1 + drivers/clk/imx/clk-imxrt1170.c | 221 +++ drivers/clk/imx/clk-pllv3.c | 56 +- drivers/clk/imx/clk.h |1 + drivers/ram/imxrt_sdram.c |9 + include/configs/imxrt1170-evk.h | 29 + include/dt-bindings/clock/imxrt1170-clock.h | 48 + include/dt-bindings/memory/imxrt-sdram.h |1 + 23 files changed, 2771 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imxrt1170-evk.dts create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h create mode 100644 arch/arm/dts/imxrt1170.dtsi create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 drivers/clk/imx/clk-imxrt1170.c create mode 100644 include/configs/imxrt1170-evk.h create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h -- 2.36.1
[PATCH v2 8/8] fs: erofs: add unaligned read range handling
I'm not an expert on erofs, but my quick glance didn't expose any
special handling on unaligned range, thus I think the U-boot erofs
driver doesn't really support unaligned read range.
This patch will add erofs_get_blocksize() so erofs can benefit from the
generic unaligned read support.
Cc: Huang Jianan
Cc: linux-er...@lists.ozlabs.org
Signed-off-by: Qu Wenruo
Reviewed-by: Huang Jianan
---
fs/erofs/internal.h | 1 +
fs/erofs/super.c| 6 ++
fs/fs.c | 2 +-
include/erofs.h | 1 +
4 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h
index 4af7c91560cc..d368a6481bf1 100644
--- a/fs/erofs/internal.h
+++ b/fs/erofs/internal.h
@@ -83,6 +83,7 @@ struct erofs_sb_info {
u16 available_compr_algs;
u16 lz4_max_distance;
u32 checksum;
+ u32 blocksize;
u16 extra_devices;
union {
u16 devt_slotoff; /* used for mkfs */
diff --git a/fs/erofs/super.c b/fs/erofs/super.c
index 4cca322b9ead..df01d2e719a7 100644
--- a/fs/erofs/super.c
+++ b/fs/erofs/super.c
@@ -99,7 +99,13 @@ int erofs_read_superblock(void)
sbi.build_time = le64_to_cpu(dsb->build_time);
sbi.build_time_nsec = le32_to_cpu(dsb->build_time_nsec);
+ sbi.blocksize = 1 << blkszbits;
memcpy(&sbi.uuid, dsb->uuid, sizeof(dsb->uuid));
return erofs_init_devices(&sbi, dsb);
}
+
+int erofs_get_blocksize(const char *filename)
+{
+ return sbi.blocksize;
+}
diff --git a/fs/fs.c b/fs/fs.c
index 2b847d83597b..23cfb1f5025b 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -375,7 +375,7 @@ static struct fstype_info fstypes[] = {
.readdir = erofs_readdir,
.ls = fs_ls_generic,
.read = erofs_read,
- .get_blocksize = fs_get_blocksize_unsupported,
+ .get_blocksize = erofs_get_blocksize,
.size = erofs_size,
.close = erofs_close,
.closedir = erofs_closedir,
diff --git a/include/erofs.h b/include/erofs.h
index 1fbe82bf72cb..18bd6807c538 100644
--- a/include/erofs.h
+++ b/include/erofs.h
@@ -10,6 +10,7 @@ int erofs_probe(struct blk_desc *fs_dev_desc,
struct disk_partition *fs_partition);
int erofs_read(const char *filename, void *buf, loff_t offset,
loff_t len, loff_t *actread);
+int erofs_get_blocksize(const char *filename);
int erofs_size(const char *filename, loff_t *size);
int erofs_exists(const char *filename);
void erofs_close(void);
--
2.37.0
[PATCH v2 7/8] fs: ubifs: rely on higher layer to do unaligned read
Currently ubifs doesn't support unaligned read offset, thanks to the
recent _fs_read() work to handle unaligned read, we only need to
implement ubifs_get_blocksize() to take advantage of it.
Now ubifs can do unaligned read without any problem.
Signed-off-by: Qu Wenruo
---
fs/fs.c | 2 +-
fs/ubifs/ubifs.c | 13 -
include/ubifs_uboot.h | 1 +
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/fs/fs.c b/fs/fs.c
index 3eb540c5fe30..2b847d83597b 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -311,7 +311,7 @@ static struct fstype_info fstypes[] = {
.exists = ubifs_exists,
.size = ubifs_size,
.read = ubifs_read,
- .get_blocksize = fs_get_blocksize_unsupported,
+ .get_blocksize = ubifs_get_blocksize,
.write = fs_write_unsupported,
.uuid = fs_uuid_unsupported,
.opendir = fs_opendir_unsupported,
diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c
index d3026e310168..a8ab556dd376 100644
--- a/fs/ubifs/ubifs.c
+++ b/fs/ubifs/ubifs.c
@@ -846,11 +846,9 @@ int ubifs_read(const char *filename, void *buf, loff_t
offset,
*actread = 0;
- if (offset & (PAGE_SIZE - 1)) {
- printf("ubifs: Error offset must be a multiple of %d\n",
- PAGE_SIZE);
- return -1;
- }
+ /* Higher layer should ensure it always pass page aligned range. */
+ assert(IS_ALIGNED(offset, PAGE_SIZE));
+ assert(IS_ALIGNED(size, PAGE_SIZE));
c->ubi = ubi_open_volume(c->vi.ubi_num, c->vi.vol_id, UBI_READONLY);
/* ubifs_findfile will resolve symlinks, so we know that we get
@@ -920,6 +918,11 @@ out:
return err;
}
+int ubifs_get_blocksize(const char *filename)
+{
+ return PAGE_SIZE;
+}
+
void ubifs_close(void)
{
}
diff --git a/include/ubifs_uboot.h b/include/ubifs_uboot.h
index b025779d59ff..bcd21715314a 100644
--- a/include/ubifs_uboot.h
+++ b/include/ubifs_uboot.h
@@ -29,6 +29,7 @@ int ubifs_exists(const char *filename);
int ubifs_size(const char *filename, loff_t *size);
int ubifs_read(const char *filename, void *buf, loff_t offset,
loff_t size, loff_t *actread);
+int ubifs_get_blocksize(const char *filename);
void ubifs_close(void);
#endif /* __UBIFS_UBOOT_H__ */
--
2.37.0
[PATCH v2 6/8] fs: fat: rely on higher layer to get block aligned read range
Just implement fat_get_blocksize() for fat, so that fat_read_file()
always get a block aligned read range.
Unfortunately I'm not experienced enough to cleanup the fat code, thus
further cleanup is appreciated.
Cc: Tom Rini
Signed-off-by: Qu Wenruo
---
fs/fat/fat.c | 13 +
fs/fs.c | 2 +-
include/fat.h | 1 +
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index dcceccbcee0a..e13035e8e6d1 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -1299,6 +1299,19 @@ int fat_read_file(const char *filename, void *buf,
loff_t offset, loff_t len,
return ret;
}
+int fat_get_blocksize(const char *filename)
+{
+ fsdata fsdata = {0};
+ int ret;
+
+ ret = get_fs_info(&fsdata);
+ if (ret)
+ return ret;
+
+ free(fsdata.fatbuf);
+ return fsdata.sect_size;
+}
+
typedef struct {
struct fs_dir_stream parent;
struct fs_dirent dirent;
diff --git a/fs/fs.c b/fs/fs.c
index 3d6cc6b38b26..3eb540c5fe30 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -207,7 +207,7 @@ static struct fstype_info fstypes[] = {
.exists = fat_exists,
.size = fat_size,
.read = fat_read_file,
- .get_blocksize = fs_get_blocksize_unsupported,
+ .get_blocksize = fat_get_blocksize,
#if CONFIG_IS_ENABLED(FAT_WRITE)
.write = file_fat_write,
.unlink = fat_unlink,
diff --git a/include/fat.h b/include/fat.h
index a9756fb4cd1b..c03a2bebecef 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -201,6 +201,7 @@ int file_fat_detectfs(void);
int fat_exists(const char *filename);
int fat_size(const char *filename, loff_t *size);
int file_fat_read(const char *filename, void *buffer, int maxsize);
+int fat_get_blocksize(const char *filename);
int fat_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info);
int fat_register_device(struct blk_desc *dev_desc, int part_no);
--
2.37.0
[PATCH v2 5/8] fs: ext4: rely on _fs_read() to handle leading unaligned block read
Just add ext4_get_blocksize() and a new assert() in ext4fs_read_file().
Signed-off-by: Qu Wenruo
---
fs/ext4/ext4fs.c | 22 ++
fs/fs.c | 2 +-
include/ext4fs.h | 1 +
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 4c89152ce4ad..b0568e77a895 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -69,6 +69,8 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos,
short status;
struct ext_block_cache cache;
+ assert(IS_ALIGNED(pos, blocksize));
+
ext_cache_init(&cache);
/* Adjust len so it we can't read past the end of the file. */
@@ -259,6 +261,26 @@ int ext4_read_file(const char *filename, void *buf, loff_t
offset, loff_t len,
return ext4fs_read(buf, offset, len, len_read);
}
+int ext4_get_blocksize(const char *filename)
+{
+ struct ext_filesystem *fs;
+ int log2blksz;
+ int log2_fs_blocksize;
+ loff_t file_len;
+ int ret;
+
+ ret = ext4fs_open(filename, &file_len);
+ if (ret < 0) {
+ printf("** File not found %s **\n", filename);
+ return -1;
+ }
+ fs = get_fs();
+ log2blksz = fs->dev_desc->log2blksz;
+ log2_fs_blocksize = LOG2_BLOCK_SIZE(ext4fs_file->data) - log2blksz;
+
+ return (1 << (log2_fs_blocksize + log2blksz));
+}
+
int ext4fs_uuid(char *uuid_str)
{
if (ext4fs_root == NULL)
diff --git a/fs/fs.c b/fs/fs.c
index 1e9f778e1f11..3d6cc6b38b26 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -236,7 +236,7 @@ static struct fstype_info fstypes[] = {
.exists = ext4fs_exists,
.size = ext4fs_size,
.read = ext4_read_file,
- .get_blocksize = fs_get_blocksize_unsupported,
+ .get_blocksize = ext4_get_blocksize,
#ifdef CONFIG_CMD_EXT4_WRITE
.write = ext4_write_file,
.ln = ext4fs_create_link,
diff --git a/include/ext4fs.h b/include/ext4fs.h
index cb5d9cc0a5c0..0f4cf32dcc2a 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -161,6 +161,7 @@ int ext4fs_probe(struct blk_desc *fs_dev_desc,
struct disk_partition *fs_partition);
int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
loff_t *actread);
+int ext4_get_blocksize(const char *filename);
int ext4_read_superblock(char *buffer);
int ext4fs_uuid(char *uuid_str);
void ext_cache_init(struct ext_block_cache *cache);
--
2.37.0
[PATCH v2 4/8] fs: btrfs: move the unaligned read code to _fs_read() for btrfs
Unlike FUSE or kernel, U-boot filesystem code makes the underly fs code
to handle the unaligned read (aka, read range is not aligned to fs block
size).
This makes underlying fs code harder to implement, as they have to handle
unaligned read all by themselves.
This patch will change the behavior, starting from btrfs, by moving the
unaligned read code into _fs_read().
The idea is pretty simple, if we have an unaligned read request, we
handle it in the following steps:
1. Grab the blocksize of the fs
2. Read the leading unaligned range
We will read the block that @offset is in, and copy the
requested part into buf.
The the block we read covers the whole range, we just call it a day.
3. Read the remaining part
The tailing part may be unaligned, but all fses handles the tailing
part much easier than the leading unaligned part.
As they just need to do a min(extent_size, start + len - cur) to
calculate the real read size.
In fact, for most file reading, the file size is not aligned and we
need to handle the tailing part anyway.
There is a btrfs specific cleanup involved:
- In btrfs_file_read(), merge the tailing unaligned read into the main
loop.
Just reuse the existing read length calculation is enough.
- Remove read_and_truncate_page() call
Since there is no explicit leading/tailing unaligned read anymore.
This has been tested with a proper randomly populated btrfs file, then
tried in sandbox mode with different aligned and unaligned range and
compare the output with md5sum.
Cc: Marek Behun
Cc: linux-bt...@vger.kernel.org
Signed-off-by: Qu Wenruo
---
fs/btrfs/btrfs.c | 10
fs/btrfs/inode.c | 89 +++-
fs/fs.c | 130 ---
include/btrfs.h | 1 +
4 files changed, 141 insertions(+), 89 deletions(-)
diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c
index bf9e1f2f17cf..7c8f4a3dfb87 100644
--- a/fs/btrfs/btrfs.c
+++ b/fs/btrfs/btrfs.c
@@ -234,6 +234,10 @@ int btrfs_read(const char *file, void *buf, loff_t offset,
loff_t len,
int ret;
ASSERT(fs_info);
+
+ /* Higher layer has ensures it never pass unaligned offset in. */
+ ASSERT(IS_ALIGNED(offset, fs_info->sectorsize));
+
ret = btrfs_lookup_path(fs_info->fs_root, BTRFS_FIRST_FREE_OBJECTID,
file, &root, &ino, &type, 40);
if (ret < 0) {
@@ -275,6 +279,12 @@ int btrfs_read(const char *file, void *buf, loff_t offset,
loff_t len,
return 0;
}
+int btrfs_get_blocksize(const char *filename)
+{
+ ASSERT(current_fs_info);
+ return current_fs_info->sectorsize;
+}
+
void btrfs_close(void)
{
if (current_fs_info) {
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 0173d30cd8ab..aa198c5aaf1f 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -617,44 +617,6 @@ check_next:
return 1;
}
-static int read_and_truncate_page(struct btrfs_path *path,
- struct btrfs_file_extent_item *fi,
- int start, int len, char *dest)
-{
- struct extent_buffer *leaf = path->nodes[0];
- struct btrfs_fs_info *fs_info = leaf->fs_info;
- u64 aligned_start = round_down(start, fs_info->sectorsize);
- u8 extent_type;
- char *buf;
- int page_off = start - aligned_start;
- int page_len = fs_info->sectorsize - page_off;
- int ret;
-
- ASSERT(start + len <= aligned_start + fs_info->sectorsize);
- buf = malloc_cache_aligned(fs_info->sectorsize);
- if (!buf)
- return -ENOMEM;
-
- extent_type = btrfs_file_extent_type(leaf, fi);
- if (extent_type == BTRFS_FILE_EXTENT_INLINE) {
- ret = btrfs_read_extent_inline(path, fi, buf);
- memcpy(dest, buf + page_off, min(page_len, ret));
- free(buf);
- return len;
- }
-
- ret = btrfs_read_extent_reg(path, fi,
- round_down(start, fs_info->sectorsize),
- fs_info->sectorsize, buf);
- if (ret < 0) {
- free(buf);
- return ret;
- }
- memcpy(dest, buf + page_off, page_len);
- free(buf);
- return len;
-}
-
int btrfs_file_read(struct btrfs_root *root, u64 ino, u64 file_offset, u64 len,
char *dest)
{
@@ -663,7 +625,6 @@ int btrfs_file_read(struct btrfs_root *root, u64 ino, u64
file_offset, u64 len,
struct btrfs_path path;
struct btrfs_key key;
u64 aligned_start = round_down(file_offset, fs_info->sectorsize);
- u64 aligned_end = round_down(file_offset + len, fs_info->sectorsize);
u64 next_offset;
u64 cur = aligned_start;
int ret = 0;
@@ -673,34 +634,14 @@ int btrfs_file_read(struct btrfs_root *root, u64 ino, u64
file_offset, u64 len,
/* Set the whole dest all zero, so we won't need to bother holes */
memset(dest,
[PATCH v2 3/8] fs: btrfs: fix a crash if specified range is beyond file size
[BUG]
When try to read a range beyond file size, btrfs driver will cause
crash/segfault:
=> load host 0 $kernel_addr_r 5k_file 0 0x2000
SEGFAULT
[CAUSE]
In btrfs_read(), if @len is 0, we will truncated it to file end, but if
file end is beyond our file size, this truncation will underflow @len,
making it -3K in this case.
And later that @len is used to memzero the output buffer, resulting
above crash.
[FIX]
Just error out if @offset is already beyond our file size.
Now it will fail properly with correct error message:
=> load host 0 $kernel_addr_r 5m_origin 0 0x2000
BTRFS: Read range beyond file size, offset 8192 file size 5120
Failed to load '5m_origin'
Signed-off-by: Qu Wenruo
---
fs/btrfs/btrfs.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c
index 9145727058d4..bf9e1f2f17cf 100644
--- a/fs/btrfs/btrfs.c
+++ b/fs/btrfs/btrfs.c
@@ -252,6 +252,12 @@ int btrfs_read(const char *file, void *buf, loff_t offset,
loff_t len,
return ret;
}
+ if (offset >= real_size) {
+ error("Read range beyond file size, offset %llu file size %llu",
+ offset, real_size);
+ return -EINVAL;
+ }
+
/*
* If the length is 0 (meaning read the whole file) or the range is
* beyond file size, truncate it to the end of the file.
--
2.37.0
[PATCH v2 2/8] fs: btrfs: fix a bug which no data get read if the length is not 0
[BUG]
When testing with unaligned read, if a specific length is passed in,
btrfs driver will read out nothing:
=> load host 0 $kernel_addr_r 5k_file 0x1000 0
0 bytes read in 0 ms
But if no length is passed in, it works fine, even if we pass a non-zero
length:
=> load host 0 $kernel_addr_r 5k_file 0 0x1000
1024 bytes read in 0 ms
[CAUSE]
In btrfs_read() if we have a larger size than our file, we will try to
truncate it using the file size.
However the real file size is not initialized if @len is not zero, thus
we always truncate our length to 0, and cause the problem.
[FIX]
Fix it by just always do the file size check.
In fact btrfs_size() always follow soft link, thus it will return the
real file size correctly.
Signed-off-by: Qu Wenruo
---
fs/btrfs/btrfs.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c
index 741c6e20f533..9145727058d4 100644
--- a/fs/btrfs/btrfs.c
+++ b/fs/btrfs/btrfs.c
@@ -246,16 +246,17 @@ int btrfs_read(const char *file, void *buf, loff_t
offset, loff_t len,
return -EINVAL;
}
- if (!len) {
- ret = btrfs_size(file, &real_size);
- if (ret < 0) {
- error("Failed to get inode size: %s", file);
- return ret;
- }
- len = real_size;
+ ret = btrfs_size(file, &real_size);
+ if (ret < 0) {
+ error("Failed to get inode size: %s", file);
+ return ret;
}
- if (len > real_size - offset)
+ /*
+* If the length is 0 (meaning read the whole file) or the range is
+* beyond file size, truncate it to the end of the file.
+*/
+ if (!len || len > real_size - offset)
len = real_size - offset;
ret = btrfs_file_read(root, ino, offset, len, buf);
--
2.37.0
[PATCH v2 1/8] fs: fat: unexport file_fat_read_at()
That function is only utilized inside fat driver, unexport it.
Signed-off-by: Qu Wenruo
---
fs/fat/fat.c | 4 ++--
include/fat.h | 2 --
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index df9ea2c028fc..dcceccbcee0a 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -1243,8 +1243,8 @@ out_free_itr:
return ret;
}
-int file_fat_read_at(const char *filename, loff_t pos, void *buffer,
-loff_t maxsize, loff_t *actread)
+static int file_fat_read_at(const char *filename, loff_t pos, void *buffer,
+ loff_t maxsize, loff_t *actread)
{
fsdata fsdata;
fat_itr *itr;
diff --git a/include/fat.h b/include/fat.h
index bd8e450b33a3..a9756fb4cd1b 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -200,8 +200,6 @@ static inline u32 sect_to_clust(fsdata *fsdata, int sect)
int file_fat_detectfs(void);
int fat_exists(const char *filename);
int fat_size(const char *filename, loff_t *size);
-int file_fat_read_at(const char *filename, loff_t pos, void *buffer,
-loff_t maxsize, loff_t *actread);
int file_fat_read(const char *filename, void *buffer, int maxsize);
int fat_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info);
int fat_register_device(struct blk_desc *dev_desc, int part_no);
--
2.37.0
[PATCH v2 0/8] U-boot: fs: add generic unaligned read offset handling
[CHANGELOG] v2->v1: - Fix a linkage error where (U64 % U32) is called without proper helper Fix it with U64 & (U32 - 1), as the U32 value (@blocksize) should always be power of 2, thus (@blocksize - 1) is the mask we want to calculate the offset inside the block. Above change only affects the 4th patch, everything else is not touched. RFC->v1: - More (manual) testing Unfortunately, in the latest master (75967970850a), the fs-tests.sh always seems to hang at preparing the fs image. Thus still has to do manual testing, tested btrfs, ext4 and fat, with aligned and unaligned read, also added soft link read, all looks fine here. Extra testing is still appreciated. - Two more btrfs specific bug fixes All exposed during manual tests - Remove the tailing unaligned block handling In fact, all fses can easily handle such case, just a min() call is enough. - Remove the support for sandboxfs Since it's using read() calls, really no need to do block alignment check. - Enhanced blocksize check Ensure the returned blocksize is not only non-error, but also non-zero. This patchset can be fetched from github: https://github.com/adam900710/u-boot/tree/fs_unaligned_read [BACKGROUND] Unlike FUSE/Kernel which always pass aligned read range, U-boot fs code just pass the request range to underlying fses. Under most case, this works fine, as U-boot only really needs to read the whole file (aka, 0 for both offset and len, len will be later determined using file size). But if some advanced user/script wants to extract kernel/initramfs from combined image, we may need to do unaligned read in that case. [ADVANTAGE] This patchset will handle unaligned read range in _fs_read(): - Get blocksize of the underlying fs - Read the leading block contianing the unaligned range The full block will be stored in a local buffer, then only copy the bytes in the unaligned range into the destination buffer. If the first block covers the whole range, we just call it aday. - Read the remaining range which starts at block aligned offset For most common case, which is 0 offset and 0 len, the code will not be changed at all. Just one extra get_blocksize() call, and for FAT/Btrfs/EROFS they all have cached blocksize, thus it takes almost no extra cost. Although for EXT4, it doesn't seem to cache the blocksize globally, thus has to do a path resolve and grab the blocksize. [DISADVANTAGE] The involved problem is: - Extra path resolving All those supported fs may have to do one extra path resolve if the read offset is not aligned. For EXT4, it will do one extra path resolve just to grab the blocksize. For data read which starts at offset 0 (the most common case), it should cause *NO* difference in performance. As the extra handling is only for unaligned offset. The common path is not really modified. [SUPPORTED FSES] - Btrfs (manually tested*) - Ext4 (manually tested) - FAT (manually tested) - Erofs - ubifs (unable to test, due to compile failure) *: Failed to get the test cases run, thus have to go sandbox mode, and attach an image with target fs, load the target file (with unaligned range) and compare the result using md5sum. For EXT4/FAT, they may need extra cleanup, as their existing unaligned range handling is no longer needed anymore, cleaning them up should free more code lines than the added one. Just not confident enough to modify them all by myself. [UNSUPPORTED FSES] - Squashfs They don't support non-zero offset, thus it can not handle the block aligned range. Need extra help to add block aligned offset support. - Semihostfs - Sandboxfs They all use read() directly, no need to do alignment check at all. Extra testing/feedback is always appreciated. Qu Wenruo (8): fs: fat: unexport file_fat_read_at() fs: btrfs: fix a bug which no data get read if the length is not 0 fs: btrfs: fix a crash if specified range is beyond file size fs: btrfs: move the unaligned read code to _fs_read() for btrfs fs: ext4: rely on _fs_read() to handle leading unaligned block read fs: fat: rely on higher layer to get block aligned read range fs: ubifs: rely on higher layer to do unaligned read fs: erofs: add unaligned read range handling fs/btrfs/btrfs.c | 33 --- fs/btrfs/inode.c | 89 +++-- fs/erofs/internal.h | 1 + fs/erofs/super.c | 6 ++ fs/ext4/ext4fs.c | 22 +++ fs/fat/fat.c | 17 +- fs/fs.c | 130 +++--- fs/ubifs/ubifs.c | 13 +++-- include/btrfs.h | 1 + include/erofs.h | 1 + include/ext4fs.h | 1 + include/fat.h | 3 +- include/ubifs_uboot.h | 1 + 13 files changed, 212 insertions(+), 106 deletions(-) -- 2.37.0
Fwd: New Defects reported by Coverity Scan for Das U-Boot
Hello Tom,
could you, please, have a look at the problems reported by Coverity
concerning code introduced by you into U-Boot.
For SHA256_Update_recycle() I guess you just have to change the
signature of the function to
SHA256_Update_recycled (SHA256_CTX *ctx,
unsigned char *block, size_t len)
Looking at
https://scan8.scan.coverity.com/reports.htm#v40863/p10710/fileInstanceId=59559157&defectInstanceId=12260012&mergedDefectId=355364
https://scan8.scan.coverity.com/reports.htm#v40863/p10710/fileInstanceId=59559157&defectInstanceId=12260012&mergedDefectId=355365
and
https://scan8.scan.coverity.com/reports.htm#v40863/p10710/fileInstanceId=59559157&defectInstanceId=12260012&mergedDefectId=355366
I think the issues are false positives:
Coverity ignores that if the sha256_update() is called will length < 64
sha256_process() will be called with blocks = 0 and will not access the
buffer.
Best regards
Heinrich
Forwarded Message
Subject: New Defects reported by Coverity Scan for Das U-Boot
Date: Tue, 26 Jul 2022 00:49:17 + (UTC)
From: scan-ad...@coverity.com
To: xypron.g...@gmx.de
Hi,
Please find the latest report on new defect(s) introduced to Das U-Boot
found with Coverity Scan.
3 new defect(s) introduced to Das U-Boot found with Coverity Scan.
2 defect(s), reported by Coverity Scan earlier, were marked fixed in the
recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 3 of 3 defect(s)
** CID 355366:(OVERRUN)
*** CID 355366:(OVERRUN)
/lib/crypt/crypt-sha256.c: 104 in SHA256_Update_recycled()
98 SHA256_Update_recycled (SHA256_CTX *ctx,
99 unsigned char block[32], size_t len)
100 {
101 size_t cnt;
102 for (cnt = len; cnt >= 32; cnt -= 32)
103 SHA256_Update (ctx, block, 32);
CID 355366:(OVERRUN)
Overrunning buffer pointed to by "(void const *)block" of 32 bytes by
passing it to a function which accesses it at byte offset 63.
104 SHA256_Update (ctx, block, cnt);
105 }
106 107 void
108 crypt_sha256crypt_rn (const char *phrase, size_t phr_size,
109 const char *setting, size_t ARG_UNUSED
(set_size),
/lib/crypt/crypt-sha256.c: 103 in SHA256_Update_recycled()
97 static void
98 SHA256_Update_recycled (SHA256_CTX *ctx,
99 unsigned char block[32], size_t len)
100 {
101 size_t cnt;
102 for (cnt = len; cnt >= 32; cnt -= 32)
CID 355366:(OVERRUN)
Overrunning buffer pointed to by "(void const *)block" of 32 bytes by
passing it to a function which accesses it at byte offset 63.
103 SHA256_Update (ctx, block, 32);
104 SHA256_Update (ctx, block, cnt);
105 }
106 107 void
108 crypt_sha256crypt_rn (const char *phrase, size_t phr_size,
** CID 355365: Memory - corruptions (OVERRUN)
*** CID 355365: Memory - corruptions (OVERRUN)
/lib/crypt/crypt-sha256.c: 212 in crypt_sha256crypt_rn()
206 characters and it ends at the first `$' character (for
207 compatibility with existing implementations). */
208 SHA256_Update (ctx, salt, salt_size);
209 210 /* Add for any character in the phrase one byte of the
alternate sum. */
211 for (cnt = phr_size; cnt > 32; cnt -= 32)
CID 355365: Memory - corruptions (OVERRUN)
Overrunning buffer pointed to by "(void const *)result" of 32 bytes by
passing it to a function which accesses it at byte offset 63.
212 SHA256_Update (ctx, result, 32);
213 SHA256_Update (ctx, result, cnt);
214 215 /* Take the binary representation of the length of the
phrase and for every
216 1 add the alternate sum, for every 0 the phrase. */
217 for (cnt = phr_size; cnt > 0; cnt >>= 1)
** CID 355364:(OVERRUN)
*** CID 355364:(OVERRUN)
/lib/sha256.c: 259 in sha256_finish()
253 PUT_UINT32_BE(low, msglen, 4);
254 255 last = ctx->total[0] & 0x3F;
256 padn = (last < 56) ? (56 - last) : (120 - last);
257 258 sha256_update(ctx, sha256_padding, padn);
CID 355364:(OVERRUN)
Overrunning array "msglen" of 8 bytes by passing it to a function which
accesses it at byte offset 63.
259 sha256_update(ctx, msglen, 8);
260 261 PUT_UINT32_BE(ctx->state[0], digest, 0);
262 PUT_UINT32_BE(ctx->state[1], digest, 4);
263 PUT_UINT32_BE(ctx->state[2], digest, 8);
264 PUT_UINT32_BE(ctx->state[3], digest, 12);
/lib/sha256.c: 259 in sha256_finish()
253 PUT_UINT32_BE(low, ms
Re: [PATCH v2 0/8] Add support for the i.MXRT1170
On 7/25/22 09:34, Stefano Babic wrote: Hi Jesse, I get errors as soon as I merge the series: https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/471284 In fact, you add new CONFIG_ but not via Kbuild: CONFIG_SPL_STACK CONFIG_SYS_FSL_ERRATUM_ESDHC13 I'm sorry I need to rebase. Thanks, Jesse Check this job, too: https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/471287 Best regards, Stefano On 17.06.22 18:42, Jesse Taube wrote: This patchset contains: - i.MXRT1170 clock driver adaption - i.MXRT1170-evk basic support Jesse Taube (8): imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header dt-bindings: imx: Add clock binding for i.MXRT1170 clk: imx: Add i.MXRT11xx pllv3 variant clk: imx: Add initial support for i.MXRT1170 clock driver RAM: Add changes for i.MXRT11xx series ARM: dts: imx: add i.MXRT1170-EVK support ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig arch/arm/dts/Makefile |3 +- arch/arm/dts/imxrt1170-evk-u-boot.dtsi| 94 + arch/arm/dts/imxrt1170-evk.dts| 250 +++ arch/arm/dts/imxrt1170-pinfunc.h | 1561 + arch/arm/dts/imxrt1170.dtsi | 257 +++ arch/arm/include/asm/arch-imx/cpu.h |1 + arch/arm/mach-imx/imxrt/Kconfig |9 + arch/arm/mach-imx/imxrt/soc.c |2 + board/freescale/imxrt1170-evk/Kconfig | 22 + board/freescale/imxrt1170-evk/MAINTAINERS |7 + board/freescale/imxrt1170-evk/Makefile|6 + board/freescale/imxrt1170-evk/imximage.cfg| 32 + board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 + configs/imxrt1170-evk_defconfig | 67 + drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile |1 + drivers/clk/imx/clk-imxrt1170.c | 221 +++ drivers/clk/imx/clk-pllv3.c | 56 +- drivers/clk/imx/clk.h |1 + drivers/ram/imxrt_sdram.c |9 + include/configs/imxrt1170-evk.h | 37 + include/dt-bindings/clock/imxrt1170-clock.h | 48 + include/dt-bindings/memory/imxrt-sdram.h |1 + 23 files changed, 2777 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imxrt1170-evk.dts create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h create mode 100644 arch/arm/dts/imxrt1170.dtsi create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 drivers/clk/imx/clk-imxrt1170.c create mode 100644 include/configs/imxrt1170-evk.h create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h
Re: [PATCH 1/8] fs: fat: unexport file_fat_read_at()
On Tue, Jul 26, 2022 at 09:35:51AM +0800, Qu Wenruo wrote: > > > On 2022/7/26 06:28, Tom Rini wrote: > > On Wed, Jun 29, 2022 at 07:38:22PM +0800, Qu Wenruo wrote: > > > > > That function is only utilized inside fat driver, unexport it. > > > > > > Signed-off-by: Qu Wenruo > > > > The series has a fails to build on nokia_rx51: > > https://source.denx.de/u-boot/u-boot/-/jobs/471877#L483 > > which to me says doing 64bit division (likely related to block size, > > etc) without using the appropriate helper macros to turn them in to bit > > shifts instead. > > > Should I update and resend the series or just send the incremental > update to fix the U64/U32 division? Please rebase and resend the whole series, thanks. -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/8] fs: fat: unexport file_fat_read_at()
On 2022/7/26 06:28, Tom Rini wrote: On Wed, Jun 29, 2022 at 07:38:22PM +0800, Qu Wenruo wrote: That function is only utilized inside fat driver, unexport it. Signed-off-by: Qu Wenruo The series has a fails to build on nokia_rx51: https://source.denx.de/u-boot/u-boot/-/jobs/471877#L483 which to me says doing 64bit division (likely related to block size, etc) without using the appropriate helper macros to turn them in to bit shifts instead. Should I update and resend the series or just send the incremental update to fix the U64/U32 division? Thanks, Qu
Re: [PATCH 1/4] arm: mach-k3: Add support for device type detection
On 7/25/22 11:57 AM, Tom Rini wrote: On Fri, Jul 15, 2022 at 11:34:32AM -0500, Andrew Davis wrote: K3 SoCs are available in a number of device types such as GP, HS-FS, EMU, etc. Like OMAP SoCs we can detect this at runtime and should print this out as part of the SoC information line. We add this as part of the common.c file as it will be used to also modify our security state early in the device boot. Signed-off-by: Andrew Davis Reviewed-by: Tom Rini --- arch/arm/mach-k3/common.c| 51 +++- arch/arm/mach-k3/common.h| 10 + arch/arm/mach-k3/include/mach/hardware.h | 10 + 3 files changed, 70 insertions(+), 1 deletion(-) When applying the whole series, am65x_hs_evm_r5 goes over size limitations at patch 2/4. I'm going to set this aside for the moment as I'm applying a number of your other patches and maybe I just missed something else that needs to come in too. Hmm, okay looks like AM65x SPL is right up against the SRAM limits. I've gone and made a quick attempt at giving us some more free space here[0]. Should be more than enough room after that to get this series in. [0] https://lore.kernel.org/u-boot/20220726012506.19368-1-...@ti.com/
[PATCH 2/4] firmware: ti_sci: Factor out message alloc failed message
We don't need to print the same message in every location, just
print it in the function that fails and remove all the extra
message printouts.
Signed-off-by: Andrew Davis
---
drivers/firmware/ti_sci.c | 40 ---
1 file changed, 4 insertions(+), 36 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 85db3f05fd..687acbf2b4 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -134,8 +134,11 @@ static struct ti_sci_xfer *ti_sci_setup_one_xfer(struct
ti_sci_info *info,
if (rx_message_size > info->desc->max_msg_size ||
tx_message_size > info->desc->max_msg_size ||
(rx_message_size > 0 && rx_message_size < sizeof(*hdr)) ||
- tx_message_size < sizeof(*hdr))
+ tx_message_size < sizeof(*hdr)) {
+ dev_err(info->dev, "TI-SCI message transfer size not sane\n");
return ERR_PTR(-ERANGE);
+ }
+
info->seq = ~info->seq;
xfer->tx_message.buf = buf;
@@ -282,7 +285,6 @@ static int ti_sci_cmd_get_revision(struct ti_sci_handle
*handle)
sizeof(*rev_info));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
- dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
@@ -346,7 +348,6 @@ static int cmd_set_board_config_using_msg(const struct
ti_sci_handle *handle,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
- dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.boardcfgp_high = (addr >> 32) & 0x;
@@ -505,7 +506,6 @@ static int ti_sci_set_device_state(const struct
ti_sci_handle *handle,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
- dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.id = id;
@@ -558,7 +558,6 @@ static int ti_sci_set_device_state_no_wait(const struct
ti_sci_handle *handle,
(u32 *)&req, sizeof(req), 0);
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
- dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.id = id;
@@ -607,7 +606,6 @@ static int ti_sci_get_device_state(const struct
ti_sci_handle *handle,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
- dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.id = id;
@@ -893,7 +891,6 @@ static int ti_sci_cmd_set_device_resets(const struct
ti_sci_handle *handle,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
- dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.id = id;
@@ -961,7 +958,6 @@ static int ti_sci_set_clock_state(const struct
ti_sci_handle *handle,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
- dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.dev_id = dev_id;
@@ -1017,7 +1013,6 @@ static int ti_sci_cmd_get_clock_state(const struct
ti_sci_handle *handle,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
- dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.dev_id = dev_id;
@@ -1231,7 +1226,6 @@ static int ti_sci_cmd_clk_set_parent(const struct
ti_sci_handle *handle,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
- dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.dev_id = dev_id;
@@ -1282,7 +1276,6 @@ static int ti_sci_cmd_clk_get_parent(const struct
ti_sci_handle *handle,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
- dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.dev_id = dev_id;
@@ -1335,7 +1328,6 @@ static int ti_sci_cmd_clk_get_num_parents(const struct
ti_sci_handle *handle,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
-
[PATCH 4/4] firmware: ti_sci: Move ACK checking to ti_sci_do_xfer() function
We can check if the message was acknowledged in the common
ti_sci_do_xfer() which lets us remove it from after each call to this
function. This simplifies the code and reduces binary size.
Signed-off-by: Andrew Davis
---
drivers/firmware/ti_sci.c | 165 ++
1 file changed, 24 insertions(+), 141 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index facc0709ae..727e090e8a 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -211,6 +211,19 @@ static int ti_sci_get_response(struct ti_sci_info *info,
return ret;
}
+/**
+ * ti_sci_is_response_ack() - Generic ACK/NACK message checkup
+ * @r: pointer to response buffer
+ *
+ * Return: true if the response was an ACK, else returns false.
+ */
+static bool ti_sci_is_response_ack(void *r)
+{
+ struct ti_sci_msg_hdr *hdr = r;
+
+ return hdr->flags & TI_SCI_FLAG_RESP_GENERIC_ACK ? true : false;
+}
+
/**
* ti_sci_do_xfer() - Do one transfer
* @info: Pointer to SCI entity information
@@ -249,8 +262,13 @@ static int ti_sci_do_xfer(struct ti_sci_info *info,
}
/* Get response if requested */
- if (xfer->rx_len)
+ if (xfer->rx_len) {
ret = ti_sci_get_response(info, xfer, &info->chan_rx);
+ if (!ti_sci_is_response_ack(xfer->tx_message.buf)) {
+ dev_err(info->dev, "Message not acknowledged");
+ ret = -ENODEV;
+ }
+ }
return ret;
}
@@ -304,19 +322,6 @@ static int ti_sci_cmd_get_revision(struct ti_sci_handle
*handle)
return 0;
}
-/**
- * ti_sci_is_response_ack() - Generic ACK/NACK message checkup
- * @r: pointer to response buffer
- *
- * Return: true if the response was an ACK, else returns false.
- */
-static bool ti_sci_is_response_ack(void *r)
-{
- struct ti_sci_msg_hdr *hdr = r;
-
- return hdr->flags & TI_SCI_FLAG_RESP_GENERIC_ACK ? true : false;
-}
-
/**
* cmd_set_board_config_using_msg() - Common command to send board
configuration
*message
@@ -358,11 +363,6 @@ static int cmd_set_board_config_using_msg(const struct
ti_sci_handle *handle,
if (ret)
return ret;
- resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
-
- if (!ti_sci_is_response_ack(resp))
- return -ENODEV;
-
return ret;
}
@@ -515,11 +515,6 @@ static int ti_sci_set_device_state(const struct
ti_sci_handle *handle,
if (ret)
return ret;
- resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
-
- if (!ti_sci_is_response_ack(resp))
- return -ENODEV;
-
if (state == MSG_DEVICE_SW_STATE_AUTO_OFF)
ti_sci_delete_exclusive_dev(info, id);
else if (flags & MSG_FLAG_DEVICE_EXCLUSIVE)
@@ -615,8 +610,6 @@ static int ti_sci_get_device_state(const struct
ti_sci_handle *handle,
return ret;
resp = (struct ti_sci_msg_resp_get_device_state *)xfer->tx_message.buf;
- if (!ti_sci_is_response_ack(resp))
- return -ENODEV;
if (clcnt)
*clcnt = resp->context_loss_count;
@@ -900,11 +893,6 @@ static int ti_sci_cmd_set_device_resets(const struct
ti_sci_handle *handle,
if (ret)
return ret;
- resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
-
- if (!ti_sci_is_response_ack(resp))
- return -ENODEV;
-
return ret;
}
@@ -968,11 +956,6 @@ static int ti_sci_set_clock_state(const struct
ti_sci_handle *handle,
if (ret)
return ret;
- resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
-
- if (!ti_sci_is_response_ack(resp))
- return -ENODEV;
-
return ret;
}
@@ -1024,9 +1007,6 @@ static int ti_sci_cmd_get_clock_state(const struct
ti_sci_handle *handle,
resp = (struct ti_sci_msg_resp_get_clock_state *)xfer->tx_message.buf;
- if (!ti_sci_is_response_ack(resp))
- return -ENODEV;
-
if (programmed_state)
*programmed_state = resp->programmed_state;
if (current_state)
@@ -1236,11 +1216,6 @@ static int ti_sci_cmd_clk_set_parent(const struct
ti_sci_handle *handle,
if (ret)
return ret;
- resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
-
- if (!ti_sci_is_response_ack(resp))
- return -ENODEV;
-
return ret;
}
@@ -1285,12 +1260,7 @@ static int ti_sci_cmd_clk_get_parent(const struct
ti_sci_handle *handle,
if (ret)
return ret;
- resp = (struct ti_sci_msg_resp_get_clock_parent *)xfer->tx_message.buf;
-
- if (!ti_sci_is_response_ack(resp))
- ret = -ENODEV;
- else
- *parent_id = resp->parent_id;
+ *parent_id = resp->parent_id;
return ret;
}
@@ -1340,10 +1310,7 @@ static int ti_sci_cmd
[PATCH 1/4] firmware: ti_sci: Reduce output on ti_sci_do_xfer error
This ti_sci_do_xfer() function already prints out the reason for the
failure, and the caller of each of these functions should also notify
the user of the failed task. Remove this extra level of error message.
Signed-off-by: Andrew Davis
---
drivers/firmware/ti_sci.c | 132 ++
1 file changed, 34 insertions(+), 98 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 0b6ba35b59..85db3f05fd 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -287,10 +287,8 @@ static int ti_sci_cmd_get_revision(struct ti_sci_handle
*handle)
}
ret = ti_sci_do_xfer(info, xfer);
- if (ret) {
- dev_err(info->dev, "Mbox communication fail %d\n", ret);
+ if (ret)
return ret;
- }
rev_info = (struct ti_sci_msg_resp_version *)xfer->tx_message.buf;
@@ -356,10 +354,8 @@ static int cmd_set_board_config_using_msg(const struct
ti_sci_handle *handle,
req.boardcfg_size = size;
ret = ti_sci_do_xfer(info, xfer);
- if (ret) {
- dev_err(info->dev, "Mbox send fail %d\n", ret);
+ if (ret)
return ret;
- }
resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
@@ -516,10 +512,8 @@ static int ti_sci_set_device_state(const struct
ti_sci_handle *handle,
req.state = state;
ret = ti_sci_do_xfer(info, xfer);
- if (ret) {
- dev_err(info->dev, "Mbox send fail %d\n", ret);
+ if (ret)
return ret;
- }
resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
@@ -572,7 +566,7 @@ static int ti_sci_set_device_state_no_wait(const struct
ti_sci_handle *handle,
ret = ti_sci_do_xfer(info, xfer);
if (ret)
- dev_err(info->dev, "Mbox send fail %d\n", ret);
+ return ret;
return ret;
}
@@ -619,10 +613,8 @@ static int ti_sci_get_device_state(const struct
ti_sci_handle *handle,
req.id = id;
ret = ti_sci_do_xfer(info, xfer);
- if (ret) {
- dev_err(info->dev, "Mbox send fail %d\n", ret);
+ if (ret)
return ret;
- }
resp = (struct ti_sci_msg_resp_get_device_state *)xfer->tx_message.buf;
if (!ti_sci_is_response_ack(resp))
@@ -908,10 +900,8 @@ static int ti_sci_cmd_set_device_resets(const struct
ti_sci_handle *handle,
req.resets = reset_state;
ret = ti_sci_do_xfer(info, xfer);
- if (ret) {
- dev_err(info->dev, "Mbox send fail %d\n", ret);
+ if (ret)
return ret;
- }
resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
@@ -979,10 +969,8 @@ static int ti_sci_set_clock_state(const struct
ti_sci_handle *handle,
req.request_state = state;
ret = ti_sci_do_xfer(info, xfer);
- if (ret) {
- dev_err(info->dev, "Mbox send fail %d\n", ret);
+ if (ret)
return ret;
- }
resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
@@ -1036,10 +1024,8 @@ static int ti_sci_cmd_get_clock_state(const struct
ti_sci_handle *handle,
req.clk_id = clk_id;
ret = ti_sci_do_xfer(info, xfer);
- if (ret) {
- dev_err(info->dev, "Mbox send fail %d\n", ret);
+ if (ret)
return ret;
- }
resp = (struct ti_sci_msg_resp_get_clock_state *)xfer->tx_message.buf;
@@ -1253,10 +1239,8 @@ static int ti_sci_cmd_clk_set_parent(const struct
ti_sci_handle *handle,
req.parent_id = parent_id;
ret = ti_sci_do_xfer(info, xfer);
- if (ret) {
- dev_err(info->dev, "Mbox send fail %d\n", ret);
+ if (ret)
return ret;
- }
resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
@@ -1305,10 +1289,8 @@ static int ti_sci_cmd_clk_get_parent(const struct
ti_sci_handle *handle,
req.clk_id = clk_id;
ret = ti_sci_do_xfer(info, xfer);
- if (ret) {
- dev_err(info->dev, "Mbox send fail %d\n", ret);
+ if (ret)
return ret;
- }
resp = (struct ti_sci_msg_resp_get_clock_parent *)xfer->tx_message.buf;
@@ -1360,10 +1342,8 @@ static int ti_sci_cmd_clk_get_num_parents(const struct
ti_sci_handle *handle,
req.clk_id = clk_id;
ret = ti_sci_do_xfer(info, xfer);
- if (ret) {
- dev_err(info->dev, "Mbox send fail %d\n", ret);
+ if (ret)
return ret;
- }
resp = (struct ti_sci_msg_resp_get_clock_num_parents *)
xfer->tx_message.buf;
@@ -1428,10 +1408,8 @@ static int ti_sci_cmd_clk_get_match_freq(const struct
ti_sci_handle *handle,
req.max_freq_hz = max_freq;
ret = ti_sci_do_xfer(info, xfer);
- if (ret) {
- dev_err(info->dev, "Mbox send fail %d\n", ret);
+
[PATCH 3/4] firmware: ti_sci: Remove inline keyword from functions
The inline hint is not needed here, the compiler will do the right thing
based on if we are compiling for speed or for code size. In this case the
inline causes this function to be placed inside each callsite which is
not the right thing to do for either speed nor size. There is no
performance benefit to this due to the larger function size reducing
cache locality, but there is a huge size penalty. Remove inline keyword.
Signed-off-by: Andrew Davis
---
drivers/firmware/ti_sci.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 687acbf2b4..facc0709ae 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -164,7 +164,7 @@ static struct ti_sci_xfer *ti_sci_setup_one_xfer(struct
ti_sci_info *info,
*return corresponding error, else if all goes well,
*return 0.
*/
-static inline int ti_sci_get_response(struct ti_sci_info *info,
+static int ti_sci_get_response(struct ti_sci_info *info,
struct ti_sci_xfer *xfer,
struct mbox_chan *chan)
{
@@ -218,7 +218,7 @@ static inline int ti_sci_get_response(struct ti_sci_info
*info,
*
* Return: 0 if all went fine, else return appropriate error.
*/
-static inline int ti_sci_do_xfer(struct ti_sci_info *info,
+static int ti_sci_do_xfer(struct ti_sci_info *info,
struct ti_sci_xfer *xfer)
{
struct k3_sec_proxy_msg *msg = &xfer->tx_message;
@@ -310,7 +310,7 @@ static int ti_sci_cmd_get_revision(struct ti_sci_handle
*handle)
*
* Return: true if the response was an ACK, else returns false.
*/
-static inline bool ti_sci_is_response_ack(void *r)
+static bool ti_sci_is_response_ack(void *r)
{
struct ti_sci_msg_hdr *hdr = r;
--
2.36.1
[PATCH 0/4] Reduce TI-SCI driver size to fix am65x_evm_r5 build
Hi All, The am65x_evm_r5_defconfig build was overflowing the SRAM area by 16 bytes on the latest master with the gcc-arm-9.2-2019.12 compiler. Lets do some simple cleanups in one of the largest drivers on these K3 systems and give us some more headroom for new features. $ ./tools/buildman/buildman -o ../buildman -b upstream/dev/ti-sci-size --step 0 -sS Summary of 2 commits for 1223 boards (32 threads, 1 job per thread) 01: configs: Resync with savedefconfig aarch64: w+ am62x_evm_a53 am64x_evm_a53 am65x_evm_a53 am65x_hs_evm_a53 j7200_evm_a72 j721e_evm_a72 j721e_hs_evm_a72 j721s2_evm_a72 arm: w+ am62x_evm_r5 am64x_evm_r5 am65x_evm_r5_usbdfu am65x_evm_r5_usbmsc am65x_hs_evm_r5 j7200_evm_r5 j721e_evm_r5 j721e_hs_evm_r5 j721s2_evm_r5 + am65x_evm_r5 05: firmware: ti_sci: Move ACK checking to ti_sci_do_xfer() function arm: w+ am65x_evm_r5 aarch64: (for 8/345 boards) all -20333.0 rodata -409.0 spl/u-boot-spl:all -20333.0 spl/u-boot-spl:rodata -409.0 spl/u-boot-spl:text -19924.0 text -19924.0 arm: (for 10/649 boards) all -16503.0 bss -3.6 rodata -409.0 spl/u-boot-spl:all -13894.6 spl/u-boot-spl:rodata -409.0 spl/u-boot-spl:text -13485.6 text -16090.4 Andrew Andrew Davis (4): firmware: ti_sci: Reduce output on ti_sci_do_xfer error firmware: ti_sci: Factor out message alloc failed message firmware: ti_sci: Remove inline keyword from functions firmware: ti_sci: Move ACK checking to ti_sci_do_xfer() function drivers/firmware/ti_sci.c | 341 +++--- 1 file changed, 64 insertions(+), 277 deletions(-) -- 2.36.1
Re: [PATCH] MAINTAINERS: Change POWERPC MPC85XX maintainer to Marek Behún
Hi Marek On 2022-07-25 11:06, Marek Behún wrote: After a discussion with Tom Rini, we've agreed that I am going to take over custodianship of the MPC85XX platform, since it seems other people do not have necessary interest or time and getting things done over there takes too long. Since I am only working on one MPC85XX board, Turris 1.x, and do not have time to do thorough reviews of patches for this entire platform (other than those concerning Turris 1.x board), for other boards I will only run patches through CI and checkpatch, and then send them via PR upwards to Tom. I have access to P2020-RDB and P2041-RDB boards. If you need me run tests with related patches I will do my best. -- sinan Signed-off-by: Marek Behún --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index cd54e6663d..3347bd4126 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1209,7 +1209,7 @@ F:arch/powerpc/cpu/mpc83xx/ F:arch/powerpc/include/asm/arch-mpc83xx/ POWERPC MPC85XX -M: Priyanka Jain +M: Marek Behún S:Maintained T:git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git F:arch/powerpc/cpu/mpc85xx/
[ANN] U-Boot v2022.10-rc1 released
Hey all, It's release day and so here's v2022.10-rc1. There's a lot in here, and there's a few more things yet to come, hopefully this week, in terms of pull requests, and also pulling things out of my own queue. One thing I want to call out specifically is the VBE series will be coming in soon, so general commentary is welcome and appreciated. Also, we've moved more of our process documentation from the wiki to rst and being in-tree. Patches to clean that up a bit more, or try and clarify points about how things work are much appreciated. In terms of a changelog, git log --merges v2022.04..v2022.07-rc1 contains what I've pulled but as always, better PR messages and tags will provide better results here. So we're now looking at regular releases every other Monday, and with final release on October 3rd, 2022. Thanks all! -- Tom signature.asc Description: PGP signature
Re: MVEBU A38x Regulator
Hi Pali, Great work! I applied the patch and removed the DM Regulator configs, rebuilt, and kwboot it. Using the improved GPIO command, I discovered my problem was the pins were misconfigured in the DTS include chain, or in the MPP configs somewhere. So the improved GPIO command did the trick :) ... I think we were flying blind with the old GPIO command, never realizing a pin was misconfigured. DS116> gpio clear mvebu0_15 Warning: Changing mpp15 function from ge0_rxd3 to gpio... gpio: pin mvebu0_15 (gpio 15) value is 0 DS116> gpio set mvebu0_15 gpio: pin mvebu0_15 (gpio 15) value is 1 DS116> scsi reset Reset SCSI scanning bus for devices... Target spinup took 0 ms. SATA link 1 timeout. AHCI 0001. 32 slots 2 ports 6 Gbps 0x3 impl SATA mode flags: 64bit ncq led only pmp fbss pio slum part sxs Device 0: (0:0) Vendor: ATA Prod.: HGST HTS721010A9 Rev: JB0O Type: Hard Disk Capacity: 953869.7 MB = 931.5 GB (1953525168 x 512) And verifying that ge0_rxd3 is not used by Ethernet. DS116> ping 192.168.0.220 ethernet@7 Waiting for PHY auto negotiation to complete done Using ethernet@7 device host 192.168.0.220 is alive The USB GPIO 26 and 27 were also similarly misconfigured . And now I can power up both USB ports with a clear/set GPIO. Thanks for an awesome patch in such a short time! Tony On Mon, Jul 25, 2022 at 1:22 PM Tony Dinh wrote: > > Hi Pali, > > I'll get the patch and give it a try. > > Thanks, > Tony > > On Mon, Jul 25, 2022 at 12:13 PM Pali Rohár wrote: > > > > On Sunday 24 July 2022 11:27:00 Pali Rohár wrote: > > > On Wednesday 20 July 2022 15:47:55 Tony Dinh wrote: > > > > Hi Pali/Marek, > > > > > > > > I'm writing u-boot for the Synology DS116 (Armada 385, dual core, 1.8 > > > > Ghz). I could not seem to get the DM Regulator to power up the SATA > > > > port on this board. I'm using Stefan ./board/Marvell/db-88f6820-gp as > > > > the starting point, and using the latest DTS > > > > > > > > https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/armada-385-synology-ds116.dts > > > > > > > > I noticed that the Linux kernel boot log (booted with stock Marvell > > > > u-boot) shows "supply ahci not found" error. But I can power up the > > > > SATA drive in stock u-boot by poking GPIO 15 (SATA power enable). And > > > > it works fine with this combination: stock u-boot, kernel 5.18.6. > > > > > > > > [2.861061] usb_phy_generic usb3_0_phy: dummy supplies not allowed > > > > for exclusive requests > > > > [2.870173] usb_phy_generic usb3_1_phy: dummy supplies not allowed > > > > for exclusive requests > > > > [2.879296] ahci-mvebu f10a8000.sata: supply ahci not found, using > > > > dummy regulator > > > > [2.887704] ahci-mvebu f10a8000.sata: supply phy not found, using > > > > dummy regulator > > > > [2.896101] ahci-mvebu f10a8000.sata: masking port_map 0x3 -> 0x1 > > > > [2.902951] ahci-mvebu f10a8000.sata: AHCI 0001. 32 slots 2 > > > > ports 6 Gbps 0x1 impl platform mode > > > > [2.912750] ahci-mvebu f10a8000.sata: flags: 64bit ncq sntf led > > > > only pmp fbs pio slum part sxs > > > > [2.923184] scsi host0: ahci-mvebu > > > > [2.927693] scsi host1: ahci-mvebu > > > > [2.931935] ata1: SATA max UDMA/133 mmio [mem > > > > 0xf10a8000-0xf10a9fff] port 0x100 irq 50 > > > > [2.940610] ata2: DUMMY > > > > > > > > My questions: does DM regulator + DM GPIO work for Armada 38x u-boot? > > > > and is the error "ahci-mvebu f10a8000.sata: supply ahci, using dummy > > > > regulator" a real error? I've googled this and came across some past > > > > related posts from you (Pali and Marek), but it is not apparent what > > > > was the solution. > > > > > > I'm really not sure if DM regulator and DM GPIO is working in U-Boot for > > > Armada 38x. Lot of Armada boards touch pinctrl/gpio registers directory > > > to configure GPIOs, instead of using DM GPIO API. > > > > DM GPIO for A38x is semi-broken. It requires DM pinctrl A38x driver, > > which is not in U-Boot yet. I implemented it and sent to ML: > > https://patchwork.ozlabs.org/project/uboot/list/?series=311133&state=* > > > > With this change U-Boot 'gpio' command is working fine on Turris Omnia > > (A385 board). > > > > It is possible that on other mvebu boards are gpios already working fine > > without new driver. It depends on initial MPP configuration. Above new > > pinctrl driver ensures that gpio subsystem set particular pin to GPIO > > mode (if it is not by default initialized to gpio) prior using it. > > > > > Stefan, any idea? > > > > > > > If you are interested in seeing more info while I'm at my new u-boot > > > > prompt (kwboot with the SPL kwb), I can post that followup. > > > > > > > > Thanks, > > > > Tony
Re: [PATCH 1/8] fs: fat: unexport file_fat_read_at()
On Wed, Jun 29, 2022 at 07:38:22PM +0800, Qu Wenruo wrote: > That function is only utilized inside fat driver, unexport it. > > Signed-off-by: Qu Wenruo The series has a fails to build on nokia_rx51: https://source.denx.de/u-boot/u-boot/-/jobs/471877#L483 which to me says doing 64bit division (likely related to block size, etc) without using the appropriate helper macros to turn them in to bit shifts instead. -- Tom signature.asc Description: PGP signature
Re: [PATCH 0/7] Add support for cyclic function execution infrastruture
On Mon, Jul 25, 2022 at 10:39:11AM +0200, Stefan Roese wrote: > Hi Tom, > > On 25.05.22 09:40, Stefan Roese wrote: > > This patchset adds the basic infrastructure to periodically execute > > code, e.g. all 100ms. Examples for such functions might be LED blinking > > etc. The functions that are hooked into this cyclic list should be > > small timewise as otherwise the execution of the other code that relies > > on a high frequent polling (e.g. UART rx char ready check) might be > > delayed too much. This patch also adds the Kconfig option > > CONFIG_CYCLIC_MAX_CPU_TIME_US, which configures the max allowed time > > for such a cyclic function. If it's execution time exceeds this time, > > this cyclic function will get removed from the cyclic list. > > > > How is this cyclic functionality executed? > > This patchset integrates the main function responsible for calling all > > registered cyclic functions cyclic_run() into the common WATCHDOG_RESET > > macro. This guarantees that cyclic_run() is executed very often, which > > is necessary for the cyclic functions to get scheduled and executed at > > their configured periods. > > > > This cyclic infrastructure will be used by a board specific function on > > the NIC23 MIPS Octeon board, which needs to check periodically, if a > > PCIe FLR has occurred. > > > > Ideas how to continue: > > One idea is to rename WATCHDOG_RESET to something like SCHEDULE and > > move the watchdog_reset call into this cyclic infrastructure as well. > > Or to perhaps move the shell UART RX ready polling to a cyclic > > function. > > > > It's also possible to extend the "cyclic" command, to support the > > creation of periodically executed shell commands (for testing etc). > > > > Thanks, > > Stefan > > Tom, did you find the time to take a look at this series? What are > you ideas / plans with it? I would very much like to get it merged > as one of it's pro's is, providing the base for bigger cleanups in > the current WATCHDOG_RESET mess in U-Boot at some time. Sorry, I had intended to chime in sooner. Conceptually, OK, lets see where this takes us. Implementation-wise, this fails to build on sandbox_spl and maybe others: https://source.denx.de/u-boot/u-boot/-/jobs/471828 -- Tom signature.asc Description: PGP signature
Re: [PATCH v1 03/26] tbs2910: prepare to synchronise device trees with linux
On 25.07.22 18:42, sba...@denx.de wrote: From: Marcel Ziswiler As a preparatory step make sure to refer to absolute node paths where labels were removed in Linux upstream. This avoids the following error once synchronised: +Error: arch/arm/dts/imx6q-tbs2910-u-boot.dtsi:3.1-7 Label or path aips1 not found +Error: arch/arm/dts/imx6q-tbs2910-u-boot.dtsi:11.1-5 Label or path soc not found Signed-off-by: Marcel Ziswiler Applied to u-boot-imx, master, thanks ! What a nonsense! We already discussed that it absolutely makes no sense to remove dt parts in u-boot that are accepted for linux and just not applied yet. Just to prepare a synchronization. Really stupid! Soeren Best regards, Stefano Babic
Re: [PATCH v2] drivers: xen: unmap Enlighten page before jumping to Linux
On Tue, Jul 19, 2022 at 02:55:28PM +, Dmytro Firsov wrote: > This commit fixes issue with usage of Xen hypervisor shared info page. > Previously U-boot did not unmap it at the end of OS boot process. Xen > did not prevent guest from this. So, it worked, but caused wierd > issues - one memory page, that was returned by memalign in U-boot > for Enlighten mapping was not unmaped by Xen (shared_info values was > not removed from there) and returned to allocator. During the Linux > boot, it uses shared_info page as regular RAM page, which leads to > hypervisor shared info corruption. > > So, to fix this issue, as discussed on the xen-devel mailing list, the > code should: >1) Unmap the page >2) Populate the area with memory using XENMEM_populate_physmap > > This patch adds page unmapping via XENMEM_remove_from_physmap, fills > hole in address space where page was mapped via XENMEM_populate_physmap > and return this address to memory allocator for freeing. > > Signed-off-by: Dmytro Firsov > Reviewed-by: Anastasiia Lukianenko Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] arm: Remove unused references to CONFIG_SOC_DM*
On Mon, Jul 18, 2022 at 11:33:39AM -0400, Tom Rini wrote: > There are no references to CONFIG_SOC_DM355 / CONFIG_SOC_DM365 / > CONFIG_SOC_DM644X / CONFIG_SOC_DM646X and the files these Makefile lines > reference have already been dropped. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] spl: Use SPL_TEXT_BASE instead of ISW_ENTRY_ADDR
On Fri, Jul 15, 2022 at 12:31:48PM -0500, Andrew Davis wrote: > The ISW_ENTRY_ADDR symbol was used for OMAP devices in place of > SPL_TEXT_BASE. Keystone2 HS devices were not using it right either. > Remove ISW_ENTRY_ADDR and use SPL_TEXT_BASE directly. > > Signed-off-by: Andrew Davis > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/2] arm: k3: config.mk: Read software revision information from file on HS
On Fri, Jul 15, 2022 at 11:38:54AM -0500, Andrew Davis wrote: > Read the swrv.txt file from the TI Security Development Tools when > TI_SECURE_DEVICE is enabled. This allows us to set our software > revision in one place and have it used by all the tools that create > TI x509 boot certificates. > > Signed-off-by: Andrew Davis Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/2] k3_gen_x509_cert: Make SWRV configurable for anti-rollback protection
On Fri, Jul 15, 2022 at 11:38:53AM -0500, Andrew Davis wrote: > From: Yogesh Siraswar > > The x509 certificate SWRV is currently hard-coded to 0. This need to be > updated to 1 for j721e 1.1, j7200 and am64x. It is don't care for other > k3 devices. > > Added new config K3_X509_SWRV to k3. Default is set to 1. > > Signed-off-by: Yogesh Siraswar > Reviewed-by: Dave Gerlach Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] arm: mach-k3: Remove ROM firewalls on GP devices
On Fri, Jul 15, 2022 at 11:21:27AM -0500, Andrew Davis wrote: > This isn't strictly needed as these firewalls should all be disabled on > GP, but it also doesn't hurt, so do this unconditionally to remove this > use of CONFIG_TI_SECURE_DEVICE. > > Signed-off-by: Andrew Davis > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 3/3] defconfigs: j721e_hs_evm: Sync HS and non-HS defconfigs
On Fri, Jul 15, 2022 at 11:19:41AM -0500, Andrew Davis wrote: > Additions have been made to the non-HS defconfig without the same > being made to the HS defconfig, sync them. > > Signed-off-by: Andrew Davis Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/3] defconfigs: am57xx_hs_evm: Sync HS and non-HS defconfigs
On Fri, Jul 15, 2022 at 11:19:39AM -0500, Andrew Davis wrote: > Sync new additions to non-HS defconfig with HS defconfig. > > Signed-off-by: Andrew Davis Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] defconfigs: Add a config for AM43xx HS EVM with QSPI Boot support
On Fri, Jul 15, 2022 at 10:58:49AM -0500, Andrew Davis wrote: > On AM43xx HS devices, QSPI boot is XIP and we use a single stage > bootloader. Add a defconfig for this. > > Signed-off-by: Andrew Davis Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/2] arm: mach-k3: Rename SOC_K3_AM6 to SOC_K3_AM654
On Fri, Jul 15, 2022 at 10:25:27AM -0500, Andrew Davis wrote: > The first AM6x device was the AM654x, but being the first we named it > just AM6, since more devices have come out with this same prefix we > should switch it to the normal convention of using the full name of the > first compatibility device the series. This makes what device we are > talking about more clear and matches all the K3 devices added since. > > Signed-off-by: Andrew Davis > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/2] arm: mach-k3: Only build init files for SPL
On Fri, Jul 15, 2022 at 10:25:26AM -0500, Andrew Davis wrote: > The content of these files are only used in SPL builds. The contents are > already ifdef for the same, remove that and only include the whole file > in the build when building for SPL. > > Signed-off-by: Andrew Davis > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] arm: dts: db410c/db820c: Fix SPMI addresses
On Wed, Jul 13, 2022 at 09:17:11PM +0200, Stephan Gerhold wrote:
> The Qualcomm device trees in U-Boot are currently not consistent with
> the upstream DTs used in the Linux kernel. While some bindings are
> similar to the official specification in the Linux kernel, several
> nodes have subtle differences, e.g. the "compatible"s or the exact
> specification of memory registers.
>
> This means that some of the Qualcomm-related U-Boot drivers are not
> compatible with the Linux DT (and vice versa).
>
> The SPMI node is one such example: the "core" region starts at
> 0x0200f000 in the upstream Linux MSM8916 DT, but in U-Boot it starts at
> 0x0200f800. The end result is normally the same, since the Linux SPMI
> driver simply adds the 0x800 internally.
>
> However, commit f5a2d6b4b03a ("spmi: msm: add arbiter version 5
> support") imported this behavior into the U-Boot driver, without
> adjusting the DB410c/DB820c device trees. This means that the 0x800
> offset is now added twice, breaking all SPMI read/write operations:
>
> Failed to find PMIC pon node. Check device tree
> Failed to find pm8916_gpios@c000 node.
> USB init failed: -6
> starting USB...
> Bus ehci@78d9000: Failed to find pm8916_gpios@c000 node.
> probe failed, error -6
> No working controllers found
>
> While the mistake is strictly speaking in the spmi-msm driver, fix the
> issue by making the SPMI nodes in the DB410c/DB820c consistent with the
> upstream Linux DT instead.
>
> Ideally we should even go a step further by fixing the remaining uses
> of custom bindings in the U-Boot drivers and moving to using the Linux
> DTs as-is. This would likely avoid such mistakes in the future and
> would also make the porting process much easier.
>
> Cc: Dzmitry Sankouski
> Fixes: f5a2d6b4b03a ("spmi: msm: add arbiter version 5 support")
> Signed-off-by: Stephan Gerhold
> Reviewed-by: Sumit Garg
Applied to u-boot/master, thanks!
--
Tom
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Re: [PATCH] board: ti: am65x: Do not disable SA2UL in DT
On Wed, Jul 13, 2022 at 11:12:48AM -0500, Andrew Davis wrote: > This is no longer needed as the SA2UL can now be shared with Linux. > Leave the SA2UL DT node enabled. > > Signed-off-by: Andrew Davis > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] armv8: mach-k3: correct define checking for AM625/AM642 memory maps
On Wed, Jul 13, 2022 at 04:49:36AM -0700, Matt Ranostay wrote: > Using CONFIG_IS_ENABLED breaks accessing memory map structure when > doing a A53 SPL build for AM625 and AM642 platforms. This is due to > 'abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y'' > in which there is no CONFIG_SPL_SOC_K3_AM625/CONFIG_SPL_SOC_K3_AM642 > defined in the configuration. > > For the A53 SPL builds on these platform to access the memory mapping > which it will need for enabling the mmu/cache it must use #if defined(X) > checks and not CONFIG_IS_ENABLED. > > Cc: Suman Anna > Cc: Neha Francis > Signed-off-by: Matt Ranostay > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] arm: dts: mt7622: remove default pinctrl of uart0
On Wed, Jul 13, 2022 at 11:16:39AM +0800, Weijie Gao wrote: > Currently u-boot running on mt7622 will print an warning log at beginning: > > serial_mtk serial@11002000: pinctrl_select_state_full: > > uclass_get_device_by_phandle_id: err=-19 > > It turns out that the pinctrl uclass can't work properly in board_f stage. > > Since the uart0 is the default UART device used by bootrom, and will be > initialized in both bootrom and tf-a bl2. It's ok not to setup pinctrl for > uart0 in u-boot. > > This patch removes the default pinctrl of uart0 to suppress the unwanted > warning. > > Signed-off-by: Weijie Gao Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] arm: dts: k3-am64-ddr fix typo causing DDR4 register corruption
On Tue, Jul 12, 2022 at 07:59:04PM -0500, Anand Gadiyar wrote: > The entry for DDRSS_PI_321_DATA was accidentally repeated leading to the > last few PI registers being incorrectly programmed. > > Fix this. > > Reported-by: Bin Liu > Signed-off-by: Vignesh Raghavendra > Signed-off-by: Anand Gadiyar > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 9/9] board: qualcomm: Add support for QCS404 EVB
On Tue, Jul 12, 2022 at 12:42:12PM +0530, Sumit Garg wrote: > Add support for Qualcomm QCS404 SoC based evaluation board. > > Features: > - Qualcomm Snapdragon QCS404 SoC > - 1GiB RAM > - 8GiB eMMC, uSD slot > > U-boot is chain loaded by ABL in 64-bit mode as part of boot.img. > For detailed build and boot instructions, refer to > doc/board/qualcomm/qcs404.rst. > > Signed-off-by: Sumit Garg Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 8/9] clocks: qcom: Add clock driver for QCS404 SoC
On Tue, Jul 12, 2022 at 12:42:11PM +0530, Sumit Garg wrote: > Currently this clock driver initializes clocks for UART and eMMC. Along > with this import "qcom,gcc-qcs404.h" header from Linux mainline to > support DT bindings. > > Signed-off-by: Sumit Garg Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 7/9] pinctrl: qcom: Add pinctrl driver for QCS404 SoC
On Tue, Jul 12, 2022 at 12:42:10PM +0530, Sumit Garg wrote: > Currently this pinctrl driver only supports BLSP UART2 specific pin > configuration. > > Signed-off-by: Sumit Garg > Reviewed-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 6/9] mmc: msm_sdhci: Add SDCC version 5.0.0 support
On Tue, Jul 12, 2022 at 12:42:09PM +0530, Sumit Garg wrote: > For SDCC version 5.0.0, MCI registers are removed from SDCC interface > and some registers are moved to HC. So add support to use the new > compatible string "qcom,sdhci-msm-v5". Based on this new msm variant, > pick the relevant variant data and use it to detect MCI presence thereby > configuring register read/write to msm specific registers. > > Signed-off-by: Sumit Garg > Reviewed-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 5/9] board: qualcomm: Add support for dragonboard845c
On Tue, Jul 12, 2022 at 12:42:08PM +0530, Sumit Garg wrote: > Add support for 96Boards Dragonboard 845C aka Robotics RB3 development > platform. This board complies with 96Boards Open Platform Specifications. > > Features: > - Qualcomm Snapdragon SDA845 SoC > - 4GiB RAM > - 64GiB UFS drive > > U-boot is chain loaded by ABL in 64-bit mode as part of boot.img. > For detailed build and boot instructions, refer to > doc/board/qualcomm/sdm845.rst, board: dragonboard845c. > > Signed-off-by: Sumit Garg > Reviewed-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 4/9] uart: sdm845: Fix debug UART pinmux
On Tue, Jul 12, 2022 at 12:42:07PM +0530, Sumit Garg wrote: > Configure debug UART pins as function: "qup9" rather than being regular > gpios. It fixes a hang seen during pinmux setting. > > Signed-off-by: Sumit Garg > Reviewed-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 3/9] clocks: sdm845: Import qcom,gcc-sdm845.h
On Tue, Jul 12, 2022 at 12:42:06PM +0530, Sumit Garg wrote: > Rather than using magic numbers as clock ids for peripherals import > qcom,gcc-sdm845.h from Linux to be used standard macros for clock ids. > So start using corresponding clk-id macro for debug UART. > > Signed-off-by: Sumit Garg > Reviewed-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 2/9] arm64: dts: sdm845: Remove redundant u-boot DT properties
On Tue, Jul 12, 2022 at 12:42:05PM +0530, Sumit Garg wrote: > According to u-boot DT recomendation, u-boot specific DT properties belong > to *-uboot.dtsi. Also for starqltechn board (which is the only current > consumer of sdm845.dtsi), the properties are already included in > starqltechn-uboot.dtsi, so remove corresponding redundant properties. > > Signed-off-by: Sumit Garg > Reviewed-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 1/9] board: starqltechn: Align DT node overrides with sdm845.dtsi
On Tue, Jul 12, 2022 at 12:42:04PM +0530, Sumit Garg wrote: > Currently there is a mismatch among DT node overrides in starqltechn > board DTS file and the actual DT nodes in the sdm845.dtsi. So fix that > to align with DT nodes in sdm845.dtsi. > > Signed-off-by: Sumit Garg > Reviewed-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/2] Nokia RX-51: Remove CONFIG_PREBOOT from defconfig
On Sun, Jul 10, 2022 at 01:42:56PM +0200, Pali Rohár wrote: > CONFIG_PREBOOT just cause putting "preboot=CONFIG_PREBOOT" into env list. > Value CONFIG_PREBOOT="run preboot" in defconfig is just nonsense and does > not do anything useful (it is infinite recursion). Config file for this > board already contains default preboot= env variable with correct value, > which has higher priority than CONFIG_PREBOOT and this is reason why > nonsense CONFIG_PREBOOT is ignored. > > Remove nonsense and unused CONFIG_PREBOOT from nokia_rx51_defconfig file. > > Signed-off-by: Pali Rohár Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/2] board: ti: am335x: Use correct dtbs for SanCloud boards
On Fri, Jul 08, 2022 at 10:25:46AM +0100, Paul Barker wrote: > We have different dtbs for the Lite and Extended WiFi variants of the > SanCloud BBE. > > Signed-off-by: Paul Barker > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/2] board: ti: am335x: Enable spi0 bus on SanCloud BBE Lite
On Fri, Jul 08, 2022 at 10:25:45AM +0100, Paul Barker wrote: > The SanCloud BBE Lite has a Micron Authenta flash device connected to > the spi0 bus. > > Signed-off-by: Paul Barker > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/2] board: ti: am335x: Enable spi0 bus on SanCloud BBE Lite
On Fri, Jul 08, 2022 at 10:25:45AM +0100, Paul Barker wrote: > The SanCloud BBE Lite has a Micron Authenta flash device connected to > the spi0 bus. > > Signed-off-by: Paul Barker > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] ti: keystone: Don't select GPIO_EXTRA_HEADER
On Fri, Jul 08, 2022 at 11:14:52AM +0200, Michal Simek wrote: > keystone doesn't have custom gpio.h that's why don't select > GPIO_EXTRA_HEADER which points to it. > > Logic in arch/arm/include/asm/gpio.h is very clear > > #ifdef CONFIG_GPIO_EXTRA_HEADER > #include > #endif > #include > > Where it is visible that there is no gpio.h in platform headers: > $ ls arch/arm/mach-keystone/include/mach/ > clock_defs.h clock-k2e.h clock-k2hk.h ddr3.h hardware-k2e.h > hardware-k2hk.h i2c_defs.h mon.h mux-k2g.h xhci-keystone.h > clock.h clock-k2g.h clock-k2l.h hardware.h hardware-k2g.h > hardware-k2l.h mmc_host_def.h msmc.h psc_defs.h > > Signed-off-by: Michal Simek > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] cmd: ti: ddr3: correct minor spelling mistake in Ti DDR3
On Fri, Jul 08, 2022 at 09:02:56AM +0100, Ramin Zaghi wrote: > Hi > > I've searched a little to find a document that explains how to > contribute to U-Boot. But couldn't find one. I hope this is the right > way and who do I CC !? > > From f6cdf2ac9fe6ade663aa7a4ff1b2d1ac38fc2704 Mon Sep 17 00:00:00 2001 > From: Ramin Zaghi > Date: Fri, 8 Jul 2022 09:00:58 +0100 > Subject: [PATCH] cmd: ti: ddr3: correct minor spelling mistake in Ti > DDR3 > command. > > Just a spelling mistake. > > Signed-off-by: Ramin Zaghi Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] phy: ti: j721e-wiz: use OF data for device specific data
On Thu, Jul 07, 2022 at 11:41:52PM -0700, Matt Ranostay wrote: > Move device specific data into OF data structure so it > is easier to maintain and we can get rid of if statements. > > Based on: > https://lore.kernel.org/linux-phy/20220526064121.27625-1-rog...@kernel.org/T/#u > > Cc: Roger Quadros > Signed-off-by: Matt Ranostay Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v1 3/3] configs: am62x_evm_r5: Add support for ESM
On Fri, Jul 01, 2022 at 02:30:12PM +0200, Julien Panis wrote: > Enable ESM driver for AM62x in R5 SPL/u-boot build. > > Signed-off-by: Julien Panis Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v1 2/3] arm64: mach-k3: am625_init: Probe ESM nodes
On Fri, Jul 01, 2022 at 02:30:11PM +0200, Julien Panis wrote: > On AM62x devices, main ESM error event outputs can be routed to > MCU ESM as inputs. So, two ESM device nodes are expected in the > device tree : one for main ESM and another one for MCU ESM. > MCU ESM error output can trigger the reset logic to reset > the device when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is > set to '0'. > > Signed-off-by: Julien Panis Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v1 1/3] arm64: dts: k3-am625-r5: Add support for ESM devices
On Fri, Jul 01, 2022 at 02:30:10PM +0200, Julien Panis wrote: > Add main ESM and MCU ESM nodes to AM625-R5 device tree. > > Signed-off-by: Julien Panis Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/2] arm: apple: Add initial Apple M2 support
On Fri, Jul 01, 2022 at 12:06:17AM +0200, Janne Grunau wrote: > Apple's M2 SoC very similar to the M1 and can use the same memory map. > The keyboard/trackpad on the MacBook Pro (13-inch, M2, 2022) uses > "dockchannel" as transport instead of SPI and needs a new driver. > USB, NVMe, uart, framebuffer and watchdog are working with the existing > drivers. > > Signed-off-by: Janne Grunau > Reviewed-by: Mark Kettenis Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/2] iommu: Add M2 support to Apple DART driver
On Fri, Jul 01, 2022 at 12:06:16AM +0200, Janne Grunau wrote: > "apple,t8112-dart" uses an incompatible register interface but still > offers the same functionality. This DART is found on the M2 and M1 > Pro/Max/Ultra SoCs. > > Signed-off-by: Janne Grunau > Reviewed-by: Mark Kettenis Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/3] defconfigs: am65x_hs_evm: Sync HS and non-HS defconfigs
On Fri, Jul 15, 2022 at 11:19:40AM -0500, Andrew Davis wrote: > Additions have been made to the non-HS defconfig without the same > being made to the HS defconfig, sync them. > > Signed-off-by: Andrew Davis > --- > configs/am65x_hs_evm_a53_defconfig | 23 ++- > configs/am65x_hs_evm_r5_defconfig | 8 > 2 files changed, 30 insertions(+), 1 deletion(-) This specifically fails on am65x_hs_evm_a53 with everything else I've applied, please rebase on top of master. -- Tom signature.asc Description: PGP signature
Re: MVEBU A38x Regulator
Hi Pali, I'll get the patch and give it a try. Thanks, Tony On Mon, Jul 25, 2022 at 12:13 PM Pali Rohár wrote: > > On Sunday 24 July 2022 11:27:00 Pali Rohár wrote: > > On Wednesday 20 July 2022 15:47:55 Tony Dinh wrote: > > > Hi Pali/Marek, > > > > > > I'm writing u-boot for the Synology DS116 (Armada 385, dual core, 1.8 > > > Ghz). I could not seem to get the DM Regulator to power up the SATA > > > port on this board. I'm using Stefan ./board/Marvell/db-88f6820-gp as > > > the starting point, and using the latest DTS > > > > > > https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/armada-385-synology-ds116.dts > > > > > > I noticed that the Linux kernel boot log (booted with stock Marvell > > > u-boot) shows "supply ahci not found" error. But I can power up the > > > SATA drive in stock u-boot by poking GPIO 15 (SATA power enable). And > > > it works fine with this combination: stock u-boot, kernel 5.18.6. > > > > > > [2.861061] usb_phy_generic usb3_0_phy: dummy supplies not allowed > > > for exclusive requests > > > [2.870173] usb_phy_generic usb3_1_phy: dummy supplies not allowed > > > for exclusive requests > > > [2.879296] ahci-mvebu f10a8000.sata: supply ahci not found, using > > > dummy regulator > > > [2.887704] ahci-mvebu f10a8000.sata: supply phy not found, using > > > dummy regulator > > > [2.896101] ahci-mvebu f10a8000.sata: masking port_map 0x3 -> 0x1 > > > [2.902951] ahci-mvebu f10a8000.sata: AHCI 0001. 32 slots 2 > > > ports 6 Gbps 0x1 impl platform mode > > > [2.912750] ahci-mvebu f10a8000.sata: flags: 64bit ncq sntf led > > > only pmp fbs pio slum part sxs > > > [2.923184] scsi host0: ahci-mvebu > > > [2.927693] scsi host1: ahci-mvebu > > > [2.931935] ata1: SATA max UDMA/133 mmio [mem > > > 0xf10a8000-0xf10a9fff] port 0x100 irq 50 > > > [2.940610] ata2: DUMMY > > > > > > My questions: does DM regulator + DM GPIO work for Armada 38x u-boot? > > > and is the error "ahci-mvebu f10a8000.sata: supply ahci, using dummy > > > regulator" a real error? I've googled this and came across some past > > > related posts from you (Pali and Marek), but it is not apparent what > > > was the solution. > > > > I'm really not sure if DM regulator and DM GPIO is working in U-Boot for > > Armada 38x. Lot of Armada boards touch pinctrl/gpio registers directory > > to configure GPIOs, instead of using DM GPIO API. > > DM GPIO for A38x is semi-broken. It requires DM pinctrl A38x driver, > which is not in U-Boot yet. I implemented it and sent to ML: > https://patchwork.ozlabs.org/project/uboot/list/?series=311133&state=* > > With this change U-Boot 'gpio' command is working fine on Turris Omnia > (A385 board). > > It is possible that on other mvebu boards are gpios already working fine > without new driver. It depends on initial MPP configuration. Above new > pinctrl driver ensures that gpio subsystem set particular pin to GPIO > mode (if it is not by default initialized to gpio) prior using it. > > > Stefan, any idea? > > > > > If you are interested in seeing more info while I'm at my new u-boot > > > prompt (kwboot with the SPL kwb), I can post that followup. > > > > > > Thanks, > > > Tony
Re: MVEBU A38x Regulator
On Sunday 24 July 2022 11:27:00 Pali Rohár wrote: > On Wednesday 20 July 2022 15:47:55 Tony Dinh wrote: > > Hi Pali/Marek, > > > > I'm writing u-boot for the Synology DS116 (Armada 385, dual core, 1.8 > > Ghz). I could not seem to get the DM Regulator to power up the SATA > > port on this board. I'm using Stefan ./board/Marvell/db-88f6820-gp as > > the starting point, and using the latest DTS > > > > https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/armada-385-synology-ds116.dts > > > > I noticed that the Linux kernel boot log (booted with stock Marvell > > u-boot) shows "supply ahci not found" error. But I can power up the > > SATA drive in stock u-boot by poking GPIO 15 (SATA power enable). And > > it works fine with this combination: stock u-boot, kernel 5.18.6. > > > > [2.861061] usb_phy_generic usb3_0_phy: dummy supplies not allowed > > for exclusive requests > > [2.870173] usb_phy_generic usb3_1_phy: dummy supplies not allowed > > for exclusive requests > > [2.879296] ahci-mvebu f10a8000.sata: supply ahci not found, using > > dummy regulator > > [2.887704] ahci-mvebu f10a8000.sata: supply phy not found, using > > dummy regulator > > [2.896101] ahci-mvebu f10a8000.sata: masking port_map 0x3 -> 0x1 > > [2.902951] ahci-mvebu f10a8000.sata: AHCI 0001. 32 slots 2 > > ports 6 Gbps 0x1 impl platform mode > > [2.912750] ahci-mvebu f10a8000.sata: flags: 64bit ncq sntf led > > only pmp fbs pio slum part sxs > > [2.923184] scsi host0: ahci-mvebu > > [2.927693] scsi host1: ahci-mvebu > > [2.931935] ata1: SATA max UDMA/133 mmio [mem > > 0xf10a8000-0xf10a9fff] port 0x100 irq 50 > > [2.940610] ata2: DUMMY > > > > My questions: does DM regulator + DM GPIO work for Armada 38x u-boot? > > and is the error "ahci-mvebu f10a8000.sata: supply ahci, using dummy > > regulator" a real error? I've googled this and came across some past > > related posts from you (Pali and Marek), but it is not apparent what > > was the solution. > > I'm really not sure if DM regulator and DM GPIO is working in U-Boot for > Armada 38x. Lot of Armada boards touch pinctrl/gpio registers directory > to configure GPIOs, instead of using DM GPIO API. DM GPIO for A38x is semi-broken. It requires DM pinctrl A38x driver, which is not in U-Boot yet. I implemented it and sent to ML: https://patchwork.ozlabs.org/project/uboot/list/?series=311133&state=* With this change U-Boot 'gpio' command is working fine on Turris Omnia (A385 board). It is possible that on other mvebu boards are gpios already working fine without new driver. It depends on initial MPP configuration. Above new pinctrl driver ensures that gpio subsystem set particular pin to GPIO mode (if it is not by default initialized to gpio) prior using it. > Stefan, any idea? > > > If you are interested in seeing more info while I'm at my new u-boot > > prompt (kwboot with the SPL kwb), I can post that followup. > > > > Thanks, > > Tony
Re: Replace make-fit-atf.py with binman. Was: migrate u-boot-rockchip.bin to binman and generate an image for SPI
El Mon, Jul 25, 2022 at 07:29:53PM +0200, Xavier Drudis Ferran deia:
>
> I copy here the rockchip-u-boot.dtsi file and then 2 patches on top of yours.
>
Sorry I copied a dirty version that din't work. The patches were correct, the
dtsi wasn't.
> #else
> collection {
> content = <&/binman/itb>;
It doesn't like this phandles nor just &itb.
These patches were the real thing. Sorry for the noise.
>
> >From 0f9cf7452a62268ec5978c80f46bf9323a269630 Mon Sep 17 00:00:00 2001
> From: Xavier Drudis Ferran
> Date: Mon, 25 Jul 2022 17:35:27 +0200
> Subject: [PATCH] Align the fit images that binman produces to 8 bytes.
>
> In commit 570c4636808 ("Makefile: Align fit-dtb.blob and u-boot.itb by
> 64bits") Michal Simek claims that according to the device tree spec,
> some things should be aligned to 4 bytes and some to 8, so passes -B 8
> to mkimage. Do the same when using binman so that we can try to
> replace make_fit_atf.py .
>
> Should this be optional? I haven't found any uses of split-elf that I
> might be breaking, and Marek said it's from dt spec, so it should be
> always required. So I'm hard coding it until the need for being
> optional arises.
> ---
> tools/binman/btool/mkimage.py | 4 +++-
> tools/binman/etype/fit.py | 1 +
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/tools/binman/btool/mkimage.py b/tools/binman/btool/mkimage.py
> index c85bfe053c..d614d72d62 100644
> --- a/tools/binman/btool/mkimage.py
> +++ b/tools/binman/btool/mkimage.py
> @@ -22,7 +22,7 @@ class Bintoolmkimage(bintool.Bintool):
>
> # pylint: disable=R0913
> def run(self, reset_timestamp=False, output_fname=None, external=False,
> -pad=None, version=False):
> +pad=None, version=False, align=None):
> """Run mkimage
>
> Args:
> @@ -36,6 +36,8 @@ class Bintoolmkimage(bintool.Bintool):
> version: True to get the mkimage version
> """
> args = []
> +if align:
> +args += ['-B', f'{align:x}']
> if external:
> args.append('-E')
> if pad:
> diff --git a/tools/binman/etype/fit.py b/tools/binman/etype/fit.py
> index 12306623af..7b99b83fa3 100644
> --- a/tools/binman/etype/fit.py
> +++ b/tools/binman/etype/fit.py
> @@ -420,6 +420,7 @@ class Entry_fit(Entry_section):
> ext_offset = self._fit_props.get('fit,external-offset')
> if ext_offset is not None:
> args = {
> +'align': 8,
> 'external': True,
> 'pad': fdt_util.fdt32_to_cpu(ext_offset.value)
> }
> --
> 2.20.1
>
> >From 9fc65a2eb55f742dd805ed96e3d2028b20078a03 Mon Sep 17 00:00:00 2001
> From: Xavier Drudis Ferran
> Date: Mon, 25 Jul 2022 18:01:24 +0200
> Subject: [PATCH] Replace make_fit_atf.py with binman.
>
> This boots my Rock Pi 4B, but likely needs more generalisation to
> cover more boards and configurations.
> ---
> Makefile | 3 --
> arch/arm/dts/rockchip-u-boot.dtsi | 70 ++
> configs/rock-pi-4-rk3399_defconfig | 1 +
> 3 files changed, 71 insertions(+), 3 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index 279aeacee3..ad739ef357 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -997,9 +997,6 @@ endif
>
> ifeq ($(CONFIG_ARCH_ROCKCHIP)$(CONFIG_SPL),yy)
> # Binman image dependencies
> -ifeq ($(CONFIG_ARM64),y)
> -INPUTS-y += u-boot.itb
> -endif
> else
> INPUTS-y += u-boot.img
> endif
> diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
> b/arch/arm/dts/rockchip-u-boot.dtsi
> index 4c26caa92a..5a613650f5 100644
> --- a/arch/arm/dts/rockchip-u-boot.dtsi
> +++ b/arch/arm/dts/rockchip-u-boot.dtsi
> @@ -13,6 +13,75 @@
>
> #ifdef CONFIG_SPL
> &binman {
> + itb {
> + filename = "u-boot.itb";
> + fit {
> + filename = "u-boot.itb";
> + description = "U-Boot FIT";
> + fit,fdt-list = "of-list";
> + fit,external-offset=<0>;
> +
> + images {
> + uboot {
> + description = "U-Boot (64-bit)";
> + type = "standalone";
> + os = "U-Boot";
> + arch = "arm64";
> + compression = "none";
> + load = ;
> + u-boot-nodtb {
> + };
> + };
> +#ifdef CONFIG_SPL_ATF
> + @atf_SEQ {
> + fit,operation = "split-elf";
> + description = "ARM Trusted Firmware";
> + type = "firmware";
> + arch = "arm64";
> +
Replace make-fit-atf.py with binman. Was: migrate u-boot-rockchip.bin to binman and generate an image for SPI
El Mon, Jul 25, 2022 at 06:39:31PM +0200, Quentin Schulz deia:
>
> Don't really want to hijack the thread with something slightly unrelated but
> posting this here for posterity:
>
> is what I have currently done and the outcome of this is:
>
>
> U-Boot TPL 2022.07-00811-gf6815f93eb-dirty (Jul 25 2022 - 18:24:06)
> Channel 0: DDR3, 666MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> Channel 1: DDR3, 666MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> 256B stride
> Trying to boot from BOOTROM
> Returning to boot ROM...
>
> U-Boot SPL 2022.07-00811-gf6815f93eb-dirty (Jul 25 2022 - 18:24:06 +0200)
> Trying to boot from MMC2
> alloc space exhausted
> FIT buffer of 1018880 bytes
> Could not get FIT buffer of 1018880 bytes
> check CONFIG_SYS_SPL_MALLOC_SIZE
Yeah, happened to me too before I did it external.
> No valid device tree binary found at 002c0e88
> initcall sequence 00286bd0 failed at call 00279604 (err=-1)
> ### ERROR ### Please RESET the board ###
>
> The new u-boot-rockchip.bin is only about 2KB bigger. The name and addresses
> are correctly returned by mkimage -l when comparing the current
> implementation and with the patch above applied.
Mmmm It looks very similar to what I got to boot.
I fixed alignment, just that, and my names are slightly different.
But I think it's either you have it external or syou increase space for buffers.
I copy here the rockchip-u-boot.dtsi file and then 2 patches on top of yours.
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki
*/
#include
/ {
binman: binman {
multiple-images;
};
};
#ifdef CONFIG_SPL
&binman {
#ifndef CONFIG_USE_SPL_FIT_GENERATOR
itb: itb {
filename = "u-boot.itb";
fit {
filename = "u-boot.itb";
description = "U-Boot FIT";
fit,fdt-list = "of-list";
fit,external-offset=<0>;
images {
uboot {
description = "U-Boot (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = ;
u-boot-nodtb {
};
};
#ifdef CONFIG_SPL_ATF
@atf_SEQ {
fit,operation = "split-elf";
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
os = "arm-trusted-firmware";
compression = "none";
fit,load;
fit,entry;
fit,data;
atf-bl31 {
};
};
#endif
#ifdef CONFIG_TEE
@tee_SEQ {
fit,operation = "split-elf";
description = "TEE";
type = "tee";
arch = "arm64";
os = "tee";
compression = "none";
fit,load;
fit,entry;
fit,data;
tee-os {
};
};
#endif
@fdt_SEQ {
description = "NAME.dtb";
type = "flat_dt";
compression = "none";
};
};
configurations {
default = "@config_DEFAULT-SEQ";
@config_SEQ {
description = "NAME.dtb";
fdt = "fdt_SEQ";
firmware = "atf_1";
loadables = "uboot","atf_2","atf_3";
};
};
};
};
#endif
simple-bin {
filename = "u-boot-rockchip.bin";
pad-byte = <0xff>;
mkimage {
Re: [PATCH v1 1/2] ARM: configs: npcm7xx: add full function for nuvoton npcm750
On Tue, Jul 12, 2022 at 05:24:06PM +0800, Jim Liu wrote: > Add add full function config for nuvoton npcm750 > > Signed-off-by: Jim Liu Does the i2c driver need to be reposted? This patch causes the platform to fail to build as the i2c driver file is missing. -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/4] arm: mach-k3: Add support for device type detection
On Fri, Jul 15, 2022 at 11:34:32AM -0500, Andrew Davis wrote: > K3 SoCs are available in a number of device types such as > GP, HS-FS, EMU, etc. Like OMAP SoCs we can detect this at runtime > and should print this out as part of the SoC information line. > We add this as part of the common.c file as it will be used > to also modify our security state early in the device boot. > > Signed-off-by: Andrew Davis > Reviewed-by: Tom Rini > --- > arch/arm/mach-k3/common.c| 51 +++- > arch/arm/mach-k3/common.h| 10 + > arch/arm/mach-k3/include/mach/hardware.h | 10 + > 3 files changed, 70 insertions(+), 1 deletion(-) When applying the whole series, am65x_hs_evm_r5 goes over size limitations at patch 2/4. I'm going to set this aside for the moment as I'm applying a number of your other patches and maybe I just missed something else that needs to come in too. -- Tom signature.asc Description: PGP signature
[PATCH v2 1/6] imx8: add hidden IMX8_ROMAPI Kconfig symbol
> In order not to repeat the IMX8MN || IMX8MP || IMX8ULP logic in > multiple places where we need to know if the SOC exposes the ROM API, > add a "def_bool y" Kconfig symbol. > Reviewed-by: Peng Fan > Signed-off-by: Rasmus Villemoes Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v1 23/26] imx8mp-rsb3720-a1: fix pwms property warnings
> From: Marcel Ziswiler > Fix the following build-time pwms property warnings: > w+arch/arm/dts/imx8mp-rsb3720-a1.dtb: Warning (pwms_property): > /lvds_backlight@0:pwms: property size (12) too small for cell size 3 > w+arch/arm/dts/imx8mp-rsb3720-a1.dtb: Warning (pwms_property): > /lvds_backlight@1:pwms: property size (12) too small for cell size 3 > Signed-off-by: Marcel Ziswiler Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v1 07/26] imx: mx6ul_14x14_evk: prepare to synchronise device trees with linux
> From: Marcel Ziswiler > As a preparatory step remove the qspi node with its flash0 label as this > is already in the Linux upstream device tree. > This avoids the following error once synchronised: > +arch/arm/dts/imx6ul-14x14-evk.dtb: ERROR (duplicate_label): > /soc/bus@210/spi@21e/n25q256a@0: Duplicate label 'flash0' on > /soc/bus@210/spi@21e/n25q256a@0 and > /soc/bus@210/spi@21e/flash@0 > Signed-off-by: Marcel Ziswiler Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v1 5/8] toradex: common: Remove stale function declaration
> Remove stale show_boot_logo() declaration, not used anywhere.
> Fixes: e6fd30dd9eef ("toradex: drop legacy show_boot_logo function and use
> splashscreen")
> Signed-off-by: Francesco Dolcini
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
[PATCH v1 17/26] imx8mm-venice-gw700x: prepare to synchronise device trees with linux
> From: Marcel Ziswiler > As a preparatory step remove the pinctrl_pmic reference which does not > exist in the Linux upistream device tree. > This avoids the following error once synchronised: > +Error: arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi:26.1-14 Label or > path pinctrl_pmic not found > Signed-off-by: Marcel Ziswiler Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v1 03/26] tbs2910: prepare to synchronise device trees with linux
> From: Marcel Ziswiler > As a preparatory step make sure to refer to absolute node paths where > labels were removed in Linux upstream. > This avoids the following error once synchronised: > +Error: arch/arm/dts/imx6q-tbs2910-u-boot.dtsi:3.1-7 Label or path aips1 > not found > +Error: arch/arm/dts/imx6q-tbs2910-u-boot.dtsi:11.1-5 Label or path soc > not found > Signed-off-by: Marcel Ziswiler Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v2 6/6] imx8ulp: soc.c: use rom_api_query_boot_infor() wrapper
> Signed-off-by: Rasmus Villemoes Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v1 04/26] imx6dl/imx6qdl: synchronise device trees with linux
> From: Marcel Ziswiler > Synchronise device trees with linux-next next-20220708. > Signed-off-by: Marcel Ziswiler Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH] usb: ehci-mx6: Remove MX6Q_ARM2 related ifdefery
> From: Fabio Estevam > The imx6q arm2 board support has been removed from U-Boot > as it did not get converted to DM. > Remove the MX6Q_ARM2 related ifdefery in the driver. > Signed-off-by: Fabio Estevam Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v1 2/8] toradex: common: Remove stale comments about modules availability
> Remove comment "not currently on sale" on specific SKUs, this > information does not belong to the code and will never be accurate. > Signed-off-by: Francesco Dolcini Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v1 21/26] imx8mn: synchronise device tree with linux
> From: Marcel Ziswiler > Synchronise device tree with linux v5.19-rc5. > Signed-off-by: Marcel Ziswiler Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v1 12/26] imx7s/d: synchronise device trees with linux
> From: Marcel Ziswiler > Synchronise device tree with linux-next next-20220708. > Signed-off-by: Marcel Ziswiler Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v1 7/8] toradex: tdx-cfg-block: Use official SKU names
> Up to now in the code we named Toradex SKUs in a slightly different way > compared to the official product name, start using the official names > from now on to avoid misunderstanding. > This has also the nice benefit of the string being shorter, allowing > to fit nicely in 80 columns even adding the product ID when printing > the hardware information. > Signed-off-by: Francesco Dolcini Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v1 15/26] vf500/vf610: synchronise device trees with linux
> From: Marcel Ziswiler > Synchronise device trees with linux v5.19-rc5. > Signed-off-by: Marcel Ziswiler Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v1 18/26] imx8mm: synchronise device tree with linux
> From: Marcel Ziswiler > Synchronise device tree with linux v5.19-rc5. > Signed-off-by: Marcel Ziswiler Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v6 4/7] board: freescale: Add QSPI Boot support in spl for i.MX8m
> Add QSPI Boot option in u-boot-spl for i.MX8m EVK. > Signed-off-by: Mamta Shukla > Signed-off-by: Thomas Haemmerle > Tested-by: Adam Ford > Reviewed-by: Fabio Estevam Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v1 09/26] colibri-imx6ull/-emmc: synchronise device tree with linux
> From: Marcel Ziswiler > Synchronise device tree with linux v5.19-rc5. > Please note that this also means that instead of the previous "generic" > U-Boot specific carrier board agnostic device trees we are now using the > regular ones for the Colibri Evaluation (carrier) board V3 (e.g. > imx6ull-colibri-eval-v3.dtb rather than the previous imx6ull-colibri.dtb > and imx6ull-colibri-emmc-eval-v3.dtb rather than the previous > imx6ull-colibri-emmc.dtb). > Signed-off-by: Marcel Ziswiler Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
