Re: [PATCH v1] mtd: parsers: ofpart: Fix parsing when size-cells is 0

[Marek Vasut]

On 12/15/22 08:16, Miquel Raynal wrote:

Hi Marek & Francesco,


Hi,


ma...@denx.de wrote on Mon, 5 Dec 2022 17:25:11 +0100:


On 12/5/22 14:49, Miquel Raynal wrote:

Hi Francesco,


Hi,


france...@dolcini.it wrote on Mon, 5 Dec 2022 12:26:44 +0100:
   

On Fri, Dec 02, 2022 at 06:08:22PM +0100, Marek Vasut wrote:

But here I would say this is a firmware bug and it might have to be handled
like a firmware bug, i.e. with fixup in the partition parser. I seem to be
changing my opinion here again.


I was thinking at this over the weekend, and I came to the following
ideas:

   - we need some improvement on the fixup we already have in the
 partition parser. We cannot ignore the fdt produced by U-Boot - as
 bad as it is.
   - the proposed fixup is fine for the immediate need, but it is
 not going to be enough to cover the general issue with the U-Boot
 generated partitions. U-Boot might keep generating partitions as direct
 child of the nand controller even when a partitions{} node is
 available. In this case the current parser just fails since it looks
 only into it and it will find it empty.
   - the current U-Boot only handle partitions{} as a direct child of the
 nand-controller, the nand-chip is ignored. This is not the way it is
 supposed to work. U-Boot code would need to be improved.


I've been thinking about it this weekend as well and the current fix
which "just set" s_cell to 1 seems risky for me, it is typically the
type of quick & dirty fix that might even break other board (nobody
knew that U-Boot current logic expected #size-cells to be set in the
DT, what if another "broken" DT expects the opposite...)


Then with the current configuration, such broken DT would not work, since current DT 
does set #size-cells=<1> (wrongly).


, not
mentioning potential issues with big storages (> 4GiB).

All in all, I really think we should revert the DT change now, reverting
as little to no drawbacks besides a dt_binding_check warning and gives
us time to deal with it properly (both in U-Boot and Linux).


I am really not happy with this, but if that's marked as intermediate fix, go 
for it.

How do we deal with this in the long run however? Parser-side fix like this 
one, maybe with better heuristics ?


Yesterday while talking about an ACPI mis-description which needed
fixing, I realized fixing up what the firmware provides to Linux should
preferably be handled as early as possible. So my first first idea was
to avoid using the broken "fixup mtdparts" function in U-Boot and I am
still convinced this is what we should do in priority. However, as
rightly pointed in this thread, we need to take care about the case
where someone would use a newer DT (let's say, with the reverted changed
reverted again) with an old U-Boot. I am still against piggy hacks in
the generic ofpart.c driver, but what we could do however is a DT
fixup in the init_machine (or the dt_fixup) hook for imx7 Colibri, very
much like this:
https://elixir.bootlin.com/linux/latest/source/arch/arm/mach-mvebu/board-v7.c#L111
Plus a warning there saying "your dt is broken, update your firmware".


This does not work, because the old U-Boot fixup_mtdparts() may be 
applied on any machine, it is not colibri mx7 specific. Also, new 
arch-side workaround are really not welcome by the architecture 
maintainers as far as I can tell.



So next time someone stumbles upon this issue, we can tell them "fix
your bootloader", and apply the same hack in their board family (there
are three or four IIRC which might be concerned some day).


There are also those machines we do not even know about which might be 
generating bogus DT using old U-Boot and fixup_mtdparts(), so, unless 
there is some all-arch fixup implementation, we wouldn't be able to fix 
them all on arch side. I think the all-arch fixup implementation would 
be the driver one, i.e. this patch as it is (or maybe with some 
improvement).



That would fix all cases and only have an impact on the affected boards.


Sadly, it does only fix the known cases, not the unknown cases like 
downstream forks which never get any bootloader updates ever, and which 
you can't find in upstream U-Boot, and which you therefore cannot easily 
catch in the arch side fixup.


[...]

Re: [PATCH v1] mtd: parsers: ofpart: Fix parsing when size-cells is 0

[Miquel Raynal]

Hi Marek & Francesco,

ma...@denx.de wrote on Mon, 5 Dec 2022 17:25:11 +0100:

> On 12/5/22 14:49, Miquel Raynal wrote:
> > Hi Francesco,  
> 
> Hi,
> 
> > france...@dolcini.it wrote on Mon, 5 Dec 2022 12:26:44 +0100:
> >   
> >> On Fri, Dec 02, 2022 at 06:08:22PM +0100, Marek Vasut wrote:  
> >>> But here I would say this is a firmware bug and it might have to be 
> >>> handled
> >>> like a firmware bug, i.e. with fixup in the partition parser. I seem to be
> >>> changing my opinion here again.  
> >>
> >> I was thinking at this over the weekend, and I came to the following
> >> ideas:
> >>
> >>   - we need some improvement on the fixup we already have in the
> >> partition parser. We cannot ignore the fdt produced by U-Boot - as
> >> bad as it is.
> >>   - the proposed fixup is fine for the immediate need, but it is
> >> not going to be enough to cover the general issue with the U-Boot
> >> generated partitions. U-Boot might keep generating partitions as direct
> >> child of the nand controller even when a partitions{} node is
> >> available. In this case the current parser just fails since it looks
> >> only into it and it will find it empty.
> >>   - the current U-Boot only handle partitions{} as a direct child of the
> >> nand-controller, the nand-chip is ignored. This is not the way it is
> >> supposed to work. U-Boot code would need to be improved.  
> > 
> > I've been thinking about it this weekend as well and the current fix
> > which "just set" s_cell to 1 seems risky for me, it is typically the
> > type of quick & dirty fix that might even break other board (nobody
> > knew that U-Boot current logic expected #size-cells to be set in the
> > DT, what if another "broken" DT expects the opposite...)  
> 
> Then with the current configuration, such broken DT would not work, since 
> current DT does set #size-cells=<1> (wrongly).
> 
> > , not
> > mentioning potential issues with big storages (> 4GiB).
> > 
> > All in all, I really think we should revert the DT change now, reverting
> > as little to no drawbacks besides a dt_binding_check warning and gives
> > us time to deal with it properly (both in U-Boot and Linux).  
> 
> I am really not happy with this, but if that's marked as intermediate fix, go 
> for it.
> 
> How do we deal with this in the long run however? Parser-side fix like this 
> one, maybe with better heuristics ?

Yesterday while talking about an ACPI mis-description which needed
fixing, I realized fixing up what the firmware provides to Linux should
preferably be handled as early as possible. So my first first idea was
to avoid using the broken "fixup mtdparts" function in U-Boot and I am
still convinced this is what we should do in priority. However, as
rightly pointed in this thread, we need to take care about the case
where someone would use a newer DT (let's say, with the reverted changed
reverted again) with an old U-Boot. I am still against piggy hacks in
the generic ofpart.c driver, but what we could do however is a DT
fixup in the init_machine (or the dt_fixup) hook for imx7 Colibri, very
much like this:
https://elixir.bootlin.com/linux/latest/source/arch/arm/mach-mvebu/board-v7.c#L111
Plus a warning there saying "your dt is broken, update your firmware".

So next time someone stumbles upon this issue, we can tell them "fix
your bootloader", and apply the same hack in their board family (there
are three or four IIRC which might be concerned some day).

That would fix all cases and only have an impact on the affected boards.

Thanks,
Miquèl

Re: [RFC PATCH 04/17] pinctrl: sunxi: add GPIO in/out wrappers

[Samuel Holland]

On 12/5/22 18:45, Andre Przywara wrote:
> So far we were open-coding the pincontroller's GPIO output/input access
> in each function using that.
> 
> Provide two functions that wrap that nicely, so users don't need to know
> about the internals, and we can abstract the new D1 pinctrl more easily.
> 
> Signed-off-by: Andre Przywara 
> ---
>  arch/arm/include/asm/arch-sunxi/gpio.h |  2 ++
>  arch/arm/mach-sunxi/pinmux.c   | 10 ++
>  drivers/gpio/sunxi_gpio.c  | 26 +-
>  3 files changed, 17 insertions(+), 21 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
> b/arch/arm/include/asm/arch-sunxi/gpio.h
> index 8333810a69f..42ca03d8c18 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -211,6 +211,8 @@ void sunxi_gpio_set_cfgbank(void *bank_base, int 
> pin_offset, u32 val);
>  void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
>  int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset);
>  int sunxi_gpio_get_cfgpin(u32 pin);
> +void sunxi_gpio_set_output_bank(void *bank_base, u32 clear_mask, u32 
> set_mask);
> +u32 sunxi_gpio_get_output_bank(void *bank_base);
>  void sunxi_gpio_set_drv(u32 pin, u32 val);
>  void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val);
>  void sunxi_gpio_set_pull(u32 pin, u32 val);
> diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c
> index b650f6b1aea..91acbf9269f 100644
> --- a/arch/arm/mach-sunxi/pinmux.c
> +++ b/arch/arm/mach-sunxi/pinmux.c
> @@ -46,6 +46,16 @@ int sunxi_gpio_get_cfgpin(u32 pin)
>   return sunxi_gpio_get_cfgbank(bank_base, pin % 32);
>  }
>  
> +void sunxi_gpio_set_output_bank(void *bank_base, u32 clear_mask, u32 
> set_mask)
> +{
> + clrsetbits_le32(bank_base + GPIO_DAT_REG_OFFSET, clear_mask, set_mask);
> +}
> +
> +u32 sunxi_gpio_get_output_bank(void *bank_base)
> +{
> + return readl(bank_base + GPIO_DAT_REG_OFFSET);
> +}
> +
>  void sunxi_gpio_set_drv(u32 pin, u32 val)
>  {
>   u32 bank = GPIO_BANK(pin);
> diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
> index 1bf691a204a..767996c10fc 100644
> --- a/drivers/gpio/sunxi_gpio.c
> +++ b/drivers/gpio/sunxi_gpio.c
> @@ -21,33 +21,22 @@
>  #if !CONFIG_IS_ENABLED(DM_GPIO)
>  static int sunxi_gpio_output(u32 pin, u32 val)
>  {
> - u32 dat;
>   u32 bank = GPIO_BANK(pin);
>   u32 num = GPIO_NUM(pin);
>   void *pio = BANK_TO_GPIO(bank);
>  
> - dat = readl(pio + 0x10);
> - if (val)
> - dat |= 0x1 << num;
> - else
> - dat &= ~(0x1 << num);
> -
> - writel(dat, pio + 0x10);
> -
> + sunxi_gpio_set_output_bank(pio, val ? 0 : 1U << num,
> + val ? 1U << num : 0);
>   return 0;
>  }
>  
>  static int sunxi_gpio_input(u32 pin)
>  {
> - u32 dat;
>   u32 bank = GPIO_BANK(pin);
>   u32 num = GPIO_NUM(pin);
>   void *pio = BANK_TO_GPIO(bank);
>  
> - dat = readl(pio + 0x10);
> - dat >>= num;
> -
> - return dat & 0x1;
> + return (sunxi_gpio_get_output_bank(pio) >> num) & 0x1;
>  }

I would suggest putting this change before patch 3. And I would suggest
following the existing pattern of functions, with an inner one taking
(bank pointer, pin offset, value), and a wrapper calling BANK_TO_GPIO.
This would consolidate the shifting/masking as well.

If you move these two functions to pinmux.c, then all of the
BANK_TO_GPIO callers are in that file, and you can move BANK_TO_GPIO to
pinmux.c as well when you remove the struct and touch all of the call
sites anyway.

Regards,
Samuel

>  
>  int gpio_request(unsigned gpio, const char *label)
> @@ -136,12 +125,8 @@ static int sunxi_gpio_get_value(struct udevice *dev, 
> unsigned offset)
>  {
>   struct sunxi_gpio_plat *plat = dev_get_plat(dev);
>   u32 num = GPIO_NUM(offset);
> - unsigned dat;
> -
> - dat = readl(plat->regs + GPIO_DAT_REG_OFFSET);
> - dat >>= num;
>  
> - return dat & 0x1;
> + return (sunxi_gpio_get_output_bank(plat->regs) >> num) & 0x1;
>  }
>  
>  static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
> @@ -181,8 +166,7 @@ static int sunxi_gpio_set_flags(struct udevice *dev, 
> unsigned int offset,
>   u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE);
>   u32 num = GPIO_NUM(offset);
>  
> - clrsetbits_le32(plat->regs + GPIO_DAT_REG_OFFSET,
> - 1 << num, value << num);
> + sunxi_gpio_set_output_bank(plat->regs, 1U << num, value << num);
>   sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
>   } else if (flags & GPIOD_IS_IN) {
>   u32 pull = 0;

Re: [PATCH] usb: gadget: ether: split start/stop from init/halt

[Marek Vasut]

On 12/13/22 12:01, Niel Fourie wrote:

Hi Marek,


Hi,


On 12/12/2022 17:46, Marek Vasut wrote:

On 12/12/22 16:29, Niel Fourie wrote:

Split out _usb_eth_start() from _usb_eth_init() and
usb_eth_stop() from _usb_eth_halt(). Now _usb_eth_init() only
initialises and registers the gadget device, which _usb_eth_halt()
reverses, and together are used for probing and removing the
device. The _usb_eth_start() and _usb_eth_stop() functions connect
and disconnect the gadget as expected by the start()/stop()
callbacks.

Previously the gadget device was probed on every start() and
removed on every stop(), which is inconsistent with other DM_ETH
drivers. For non-DM gadget drivers the old behaviour has been
retained.


Does this mean the udevice pointer and associated private date are 
retained during the entire operation of the USB gadget , i.e. even 
between stop/start cycles ?


In the DM_ETH case, yes. The drivers/devices remain registered the whole 
time between _usb_eth_init() and _usb_eth_halt(), and the need for 
revalidating the private data pointer falls away as was done in my 
previous patch.


Perfect.

I tested this on imx8mp with the dwc3 gadget driver, and the data 
structures, specifically the private data, remained intact from probe() 
until remove(). I also tested that probing again after removal works as 
expected.


Excellent.

[...]

Should "[PATCH v2] net: eth-uclass: revalidate priv after stop() in 
eth_halt()" be dropped ? It seems this patch fully replaces it.

Re: [PATCH v2] cmd: pxe_utils: Limit fdtcontroladdr usage to non-fitImage

[Simon Glass]

On Tue, 13 Dec 2022 at 22:45, Marek Vasut  wrote:
>
> Commit d5ba6188dfb ("cmd: pxe_utils: Check fdtcontroladdr in label_boot")
> forces '$fdtcontroladdr' DT address as a third parameter of bootm command
> even if the PXE transfer pulls in a fitImage which contains configuration
> node with its own DT that is preferrable to be passed to Linux. Limit the
> $fdtcontroladdr fallback utilization to non-fitImages, since it is highly
> likely a fitImage would come with its own DT, while single-file images do
> need a separate DT.
>
> Fixes: d5ba6188dfb ("cmd: pxe_utils: Check fdtcontroladdr in label_boot")
> Signed-off-by: Marek Vasut 
> ---
> Cc: Peter Hoyes 
> Cc: Ramon Fried 
> Cc: Simon Glass 
> ---
> V1: Map the kernel buffer before testing image type
> V2: Update code comment to reflect the change
> ---
>  boot/pxe_utils.c | 9 +
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c
> index 8133006875f..099aa2f4bc7 100644
> --- a/boot/pxe_utils.c
> +++ b/boot/pxe_utils.c
> @@ -617,7 +617,7 @@ static int label_boot(struct pxe_context *ctx, struct 
> pxe_label *label)
>  * bootm, and adjust argc appropriately.
>  *
>  * Scenario 3: If there is an fdtcontroladdr specified, pass it along 
> to
> -* bootm, and adjust argc appropriately.
> +* bootm, and adjust argc appropriately, unless the image type is 
> fitImage.
>  *
>  * Scenario 4: fdt blob is not available.
>  */
> @@ -724,7 +724,10 @@ static int label_boot(struct pxe_context *ctx, struct 
> pxe_label *label)
> if (!bootm_argv[3])
> bootm_argv[3] = env_get("fdt_addr");
>
> -   if (!bootm_argv[3])
> +   kernel_addr_r = genimg_get_kernel_addr(kernel_addr);
> +   buf = map_sysmem(kernel_addr_r, 0);
> +
> +   if (!bootm_argv[3] && genimg_get_format(buf) != IMAGE_FORMAT_FIT)
> bootm_argv[3] = env_get("fdtcontroladdr");
>
> if (bootm_argv[3]) {
> @@ -733,8 +736,6 @@ static int label_boot(struct pxe_context *ctx, struct 
> pxe_label *label)
> bootm_argc = 4;
> }
>
> -   kernel_addr_r = genimg_get_kernel_addr(kernel_addr);
> -   buf = map_sysmem(kernel_addr_r, 0);
> /* Try bootm for legacy and FIT format image */
> if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID &&
>  IS_ENABLED(CONFIG_CMD_BOOTM))
> --
> 2.35.1
>

Reviewed-by: Simon Glass 

Re: [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR

[Samuel Holland]

Andre,

On 12/14/22 08:25, Andre Przywara wrote:
> On Wed, 14 Dec 2022 02:37:12 -0600 Samuel Holland  wrote:
>> On 12/5/22 18:45, Andre Przywara wrote:
>>> diff --git a/configs/Sinovoip_BPI_M3_defconfig 
>>> b/configs/Sinovoip_BPI_M3_defconfig
>>> index ab70eff68eb..bcc8b1fba98 100644
>>> --- a/configs/Sinovoip_BPI_M3_defconfig
>>> +++ b/configs/Sinovoip_BPI_M3_defconfig
>>> @@ -13,7 +13,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
>>>  CONFIG_USB0_ID_DET="PH11"
>>>  CONFIG_USB1_VBUS_PIN="PD24"
>>>  CONFIG_AXP_GPIO=y
>>> -CONFIG_SATAPWR="PD25"
>>>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>>>  CONFIG_SYS_MONITOR_LEN=786432
>>>  CONFIG_CONSOLE_MUX=y
>>> diff --git a/configs/orangepi_plus_defconfig 
>>> b/configs/orangepi_plus_defconfig
>>> index 5c7f0731d90..f4ce4851d7c 100644
>>> --- a/configs/orangepi_plus_defconfig
>>> +++ b/configs/orangepi_plus_defconfig
>>> @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672
>>>  CONFIG_MACPWR="PD6"
>>>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>>>  CONFIG_USB1_VBUS_PIN="PG13"
>>> -CONFIG_SATAPWR="PG11"  
>>
>> BananaPi M3 and OrangePi Plus have USB-SATA adapters, not onboard AHCI,
>> so they would lose the ability to use SATA with this change.
> 
> Many thanks for having a thorough look, I much appreciate that.
> Of course you are right. I actually found this myself, and thought I
> mentioned it somewhere, but apparently this got lost in between cover
> letter versions and commit messages on different branches. Apologies for
> that.
> So yeah, my research figured that this isn't described properly in the DT,
> so SATA disks just work in Linux because U-Boot flipped the bit here.
> I heard about USB child DT nodes, which IIUC are possible to describe
> errata and such, but I don't think it's a good solution here. Would
> probably need driver changes, so wouldn't be backwards compatible.
> 
>> OrangePi Plus has the SATA controller regulator as usb3_vbus-supply in
>> its devicetree. So we could replace this with CONFIG_USB3_VBUS_PIN for
>> now, and it will continue to work once we switch the PHY driver to use
>> the regulator uclass.
>>
>> But the BananaPi M3 has its USB-SATA downstream from an external hub.
>> CONFIG_USB1_VBUS_PIN is used for the regulator powering the hub, so I do
>> not see an obvious solution here.
> 
> Yeah, I didn't find a neat automatic solution for that either.
> Can we add a regulator-fixed, and make this regulator-boot-on? Without
> actually referencing this regulator anywhere? I need to check this
> actually works in U-Boot, but what do you say with your Linux/DT maintainer
> hat on?

I can think of a few solutions, though none is perfect:

1) As you suggest, add a new fixed regulator with regulator-boot-on. It
also needs regulator-always-on to keep the OS from disabling it later,
since it would have no consumer. We would also need to call
regulators_enable_boot_on() from our board code to enable in in U-Boot.

2) Add a new fixed regulator, and point usb1_vbus-supply to it. Then
have the new regulator reference the hub regulator as its vin-supply.
This would require updating the U-Boot fixed regulator driver to control
its vin-supply. And it is also a misleading use of usb1_vbus-supply.

3) Add a gpio-hog to the devicetree, to unconditionally enable the
regulator. This would be the closest equivalent to what we are doing
now, and the quickest path to getting the legacy board code removed. We
could do this entirely within U-Boot, so I lean toward this solution.

Regards,
Samuel

[PATCH v4 25/25] board: rockchip: Add Edgeble Neu2 IO Board

[Jagan Teki]

Neural Compute Module 2(Neu2) IO board is an industrial form factor
IO board from Edgeble AI.

General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion

Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.

Add support for it.

Signed-off-by: Jagan Teki 
---
Changes for v4:
- add MONITOR_LEN config
Changes for v3:
- updated the board names
Changes for v2:
- none

 .../dts/rv1126-edgeble-neu2-io-u-boot.dtsi| 10 
 arch/arm/mach-rockchip/rv1126/Kconfig | 16 ++
 board/edgeble/neural-compute-module-2/Kconfig | 16 ++
 .../neural-compute-module-2/MAINTAINERS   |  6 ++
 .../edgeble/neural-compute-module-2/Makefile  |  7 +++
 board/edgeble/neural-compute-module-2/neu2.c  |  4 ++
 configs/neu2-io-rv1126_defconfig  | 57 +++
 doc/board/rockchip/rockchip.rst   |  3 +
 include/configs/neural-compute-module-2.h | 21 +++
 9 files changed, 140 insertions(+)
 create mode 100644 arch/arm/dts/rv1126-edgeble-neu2-io-u-boot.dtsi
 create mode 100644 board/edgeble/neural-compute-module-2/Kconfig
 create mode 100644 board/edgeble/neural-compute-module-2/MAINTAINERS
 create mode 100644 board/edgeble/neural-compute-module-2/Makefile
 create mode 100644 board/edgeble/neural-compute-module-2/neu2.c
 create mode 100644 configs/neu2-io-rv1126_defconfig
 create mode 100644 include/configs/neural-compute-module-2.h

diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io-u-boot.dtsi 
b/arch/arm/dts/rv1126-edgeble-neu2-io-u-boot.dtsi
new file mode 100644
index 00..51a1617708
--- /dev/null
+++ b/arch/arm/dts/rv1126-edgeble-neu2-io-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include "rv1126-u-boot.dtsi"
+
+ {
+   status = "disabled";
+};
diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig 
b/arch/arm/mach-rockchip/rv1126/Kconfig
index 4f5021b083..7382c55996 100644
--- a/arch/arm/mach-rockchip/rv1126/Kconfig
+++ b/arch/arm/mach-rockchip/rv1126/Kconfig
@@ -1,5 +1,19 @@
 if ROCKCHIP_RV1126
 
+config TARGET_RV1126_NEU2
+   bool "Edgeble Neural Compute Module 2(Neu2) SoM"
+   help
+ Neu2:
+ Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
+ based on Rockchip RV1126 from Edgeble AI.
+ Neu2 powered with Consumer grade (0 to +80 °C) RV1126 SoC.
+ Neu2k powered with Industrial grade (-40 °C to +85 °C) RV1126K SoC.
+
+ Neu2-IO:
+ Neural Compute Module 2(Neu2) IO board is an industrial form factor
+ IO board and Neu2 needs to mount on top of this IO board in order to
+ create complete Edgeble Neural Compute Module 2(Neu2) IO platform.
+
 config SOC_SPECIFIC_OPTIONS # dummy
def_bool y
select HAS_CUSTOM_SYS_INIT_SP_ADDR
@@ -40,4 +54,6 @@ config SYS_MALLOC_F_LEN
 config TEXT_BASE
default 0x60
 
+source board/edgeble/neural-compute-module-2/Kconfig
+
 endif
diff --git a/board/edgeble/neural-compute-module-2/Kconfig 
b/board/edgeble/neural-compute-module-2/Kconfig
new file mode 100644
index 00..21faf4ad26
--- /dev/null
+++ b/board/edgeble/neural-compute-module-2/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_RV1126_NEU2
+
+config SYS_BOARD
+   default "neural-compute-module-2"
+
+config SYS_VENDOR
+   default "edgeble"
+
+config SYS_CONFIG_NAME
+   default "neural-compute-module-2"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+   select RAM_ROCKCHIP_LPDDR4
+
+endif
diff --git a/board/edgeble/neural-compute-module-2/MAINTAINERS 
b/board/edgeble/neural-compute-module-2/MAINTAINERS
new file mode 100644
index 00..38edb3a360
--- /dev/null
+++ b/board/edgeble/neural-compute-module-2/MAINTAINERS
@@ -0,0 +1,6 @@
+RV1126-ECM0
+M: Jagan Teki 
+S: Maintained
+F: board/edgeble/neural-compute-module-2
+F: include/configs/neural-compute-module-2.h
+F: configs/neu2-io-rv1126_defconfig
diff --git a/board/edgeble/neural-compute-module-2/Makefile 
b/board/edgeble/neural-compute-module-2/Makefile
new file mode 100644
index 00..3bfc89fa15
--- /dev/null
+++ b/board/edgeble/neural-compute-module-2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += neu2.o
diff --git a/board/edgeble/neural-compute-module-2/neu2.c 
b/board/edgeble/neural-compute-module-2/neu2.c
new file mode 100644
index 00..3d2262ce97
--- /dev/null
+++ b/board/edgeble/neural-compute-module-2/neu2.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
diff --git a/configs/neu2-io-rv1126_defconfig b/configs/neu2-io-rv1126_defconfig
new file mode 100644
index 

[PATCH v4 24/25] ARM: dts: rockchip: Add rv1126-u-boot.dtsi

[Jagan Teki]

Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
for Rockchip RV1126 SoC.

Both eMMC and SD boot are tested in Edgeble Neu2 SoM.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 arch/arm/dts/rv1126-u-boot.dtsi | 62 +
 1 file changed, 62 insertions(+)
 create mode 100644 arch/arm/dts/rv1126-u-boot.dtsi

diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi
new file mode 100644
index 00..bc77037760
--- /dev/null
+++ b/arch/arm/dts/rv1126-u-boot.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include "rockchip-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = \
+   "same-as-spl", , 
+   };
+
+   dmc {
+   compatible = "rockchip,rv1126-dmc";
+   u-boot,dm-pre-reloc;
+   };
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
-- 
2.25.1

[PATCH v4 23/25] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IO

[Jagan Teki]

Neural Compute Module 2(Neu2) IO board is an industrial form factor
evaluation board from Edgeble AI.

General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion

Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.

Add support for it.

Signed-off-by: Jagan Teki 
---
Changes for v4:
- pick changes from linux
Changes for v3:
- rebase on linux
Changes for v2:
- none

 arch/arm/dts/Makefile   |  3 ++
 arch/arm/dts/rv1126-edgeble-neu2-io.dts | 42 +
 2 files changed, 45 insertions(+)
 create mode 100644 arch/arm/dts/rv1126-edgeble-neu2-io.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 43951a7731..a0ea23113c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -170,6 +170,9 @@ dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb
 
+dtb-$(CONFIG_ROCKCHIP_RV1126) += \
+   rv1126-edgeble-neu2-io.dtb
+
 dtb-$(CONFIG_ARCH_S5P4418) += \
s5p4418-nanopi2.dtb
 
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts 
b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
new file mode 100644
index 00..dded0a12f0
--- /dev/null
+++ b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/dts-v1/;
+#include "rv1126.dtsi"
+#include "rv1126-edgeble-neu2.dtsi"
+
+/ {
+   model = "Edgeble Neu2 IO Board";
+   compatible = "edgeble,neural-compute-module-2-io",
+"edgeble,neural-compute-module-2", "rockchip,rv1126";
+
+   aliases {
+   serial2 = 
+   };
+
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+};
+
+ {
+   bus-width = <4>;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
+   card-detect-delay = <200>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_clk _cmd _bus4 _det>;
+   rockchip,default-sample-phase = <90>;
+   sd-uhs-sdr12;
+   sd-uhs-sdr25;
+   sd-uhs-sdr104;
+   vqmmc-supply = <_sd>;
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
-- 
2.25.1

[PATCH v4 22/25] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2)

[Jagan Teki]

Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RV1126 from Edgeble AI.

General features:
- Rockchip RV1126
- 2/4GB LPDDR4
- 8/16/32GB eMMC
- 2x MIPI CSI2 FPC connector
- Fn-link 8223A-SR WiFi/BT

Industrial grade (-40 °C to +85 °C) version of the same class of module
called Neu2k powered with Rockchip RV1126K.

Neu2 needs to mount on top of Edgeble IO boards for creating complete
platform solutions.

Add support for it.

Signed-off-by: Jagan Teki 
---
Changes for v4:
- pick changes from linux
Changes for v3:
- rebase on linux
Changes for v2:
- none

 arch/arm/dts/rv1126-edgeble-neu2.dtsi | 338 ++
 1 file changed, 338 insertions(+)
 create mode 100644 arch/arm/dts/rv1126-edgeble-neu2.dtsi

diff --git a/arch/arm/dts/rv1126-edgeble-neu2.dtsi 
b/arch/arm/dts/rv1126-edgeble-neu2.dtsi
new file mode 100644
index 00..cc64ba4be3
--- /dev/null
+++ b/arch/arm/dts/rv1126-edgeble-neu2.dtsi
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/ {
+   compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
+
+   aliases {
+   mmc0 = 
+   };
+
+   vcc5v0_sys: vcc5v0-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vccio_flash: vccio-flash-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < RK_PB3 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_vol_sel>;
+   regulator-name = "vccio_flash";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   vin-supply = <_3v3>;
+   };
+
+   sdio_pwrseq: pwrseq-sdio {
+   compatible = "mmc-pwrseq-simple";
+   clocks = < 1>;
+   clock-names = "ext_clock";
+   pinctrl-names = "default";
+   pinctrl-0 = <_enable_h>;
+   reset-gpios = < RK_PD0 GPIO_ACTIVE_LOW>;
+   };
+};
+
+ {
+   cpu-supply = <_arm>;
+};
+
+ {
+   bus-width = <8>;
+   non-removable;
+   pinctrl-names = "default";
+   pinctrl-0 = <_bus8 _cmd _clk _rstnout>;
+   rockchip,default-sample-phase = <90>;
+   vmmc-supply = <_3v3>;
+   vqmmc-supply = <_flash>;
+   status = "okay";
+};
+
+ {
+   clock-frequency = <40>;
+   status = "okay";
+
+   rk809: pmic@20 {
+   compatible = "rockchip,rk809";
+   reg = <0x20>;
+   interrupt-parent = <>;
+   interrupts = ;
+   #clock-cells = <1>;
+   clock-output-names = "rk808-clkout1", "rk808-clkout2";
+   pinctrl-names = "default";
+   pinctrl-0 = <_int_l>;
+   rockchip,system-power-controller;
+   wakeup-source;
+
+   vcc1-supply = <_sys>;
+   vcc2-supply = <_sys>;
+   vcc3-supply = <_sys>;
+   vcc4-supply = <_sys>;
+   vcc5-supply = <_buck5>;
+   vcc6-supply = <_buck5>;
+   vcc7-supply = <_sys>;
+   vcc8-supply = <_sys>;
+   vcc9-supply = <_sys>;
+
+   regulators {
+   vdd_npu_vepu: DCDC_REG1 {
+   regulator-name = "vdd_npu_vepu";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-initial-mode = <0x2>;
+   regulator-min-microvolt = <65>;
+   regulator-max-microvolt = <95>;
+   regulator-ramp-delay = <6001>;
+   regulator-state-mem {
+   regulator-off-in-suspend;
+   };
+   };
+
+   vdd_arm: DCDC_REG2 {
+   regulator-name = "vdd_arm";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-initial-mode = <0x2>;
+   regulator-min-microvolt = <725000>;
+   regulator-max-microvolt = <135>;
+   regulator-ramp-delay = <6001>;
+   regulator-state-mem {
+   regulator-off-in-suspend;
+   };
+   };
+
+ 

[PATCH v4 19/25] arm: rockchip: Add RV1126 arch core support

[Jagan Teki]

Rockchip RV1126 is a high-performance vision processor SoC
for IPC/CVR, especially for AI related application.

Add arch core support for it.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- drop MONITOR_LEN config
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 arch/arm/include/asm/arch-rv1126/boot0.h  | 11 
 arch/arm/include/asm/arch-rv1126/gpio.h   | 11 
 arch/arm/mach-rockchip/Kconfig| 46 ++
 arch/arm/mach-rockchip/Makefile   |  1 +
 arch/arm/mach-rockchip/rv1126/Kconfig | 43 +
 arch/arm/mach-rockchip/rv1126/Makefile| 13 
 arch/arm/mach-rockchip/rv1126/clk_rv1126.c| 33 ++
 arch/arm/mach-rockchip/rv1126/rv1126.c| 63 +++
 arch/arm/mach-rockchip/rv1126/syscon_rv1126.c | 47 ++
 common/spl/Kconfig.tpl|  2 +-
 include/configs/rv1126_common.h   | 40 
 11 files changed, 309 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-rv1126/boot0.h
 create mode 100644 arch/arm/include/asm/arch-rv1126/gpio.h
 create mode 100644 arch/arm/mach-rockchip/rv1126/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rv1126/Makefile
 create mode 100644 arch/arm/mach-rockchip/rv1126/clk_rv1126.c
 create mode 100644 arch/arm/mach-rockchip/rv1126/rv1126.c
 create mode 100644 arch/arm/mach-rockchip/rv1126/syscon_rv1126.c
 create mode 100644 include/configs/rv1126_common.h

diff --git a/arch/arm/include/asm/arch-rv1126/boot0.h 
b/arch/arm/include/asm/arch-rv1126/boot0.h
new file mode 100644
index 00..2e78b074ad
--- /dev/null
+++ b/arch/arm/include/asm/arch-rv1126/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include 
+
+#endif
diff --git a/arch/arm/include/asm/arch-rv1126/gpio.h 
b/arch/arm/include/asm/arch-rv1126/gpio.h
new file mode 100644
index 00..eca79d5159
--- /dev/null
+++ b/arch/arm/include/asm/arch-rv1126/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include 
+
+#endif
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 69d51ff378..7c67084113 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -301,6 +301,51 @@ config ROCKCHIP_RV1108
  The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
  and a DSP.
 
+config ROCKCHIP_RV1126
+   bool "Support Rockchip RV1126"
+   select CPU_V7A
+   select SKIP_LOWLEVEL_INIT_ONLY
+   select TPL
+   select SUPPORT_TPL
+   select TPL_NEEDS_SEPARATE_STACK
+   select TPL_ROCKCHIP_BACK_TO_BROM
+   select SPL
+   select SUPPORT_SPL
+   select SPL_STACK_R
+   select CLK
+   select FIT
+   select PINCTRL
+   select RAM
+   select ROCKCHIP_SDRAM_COMMON
+   select REGMAP
+   select SYSCON
+   select DM_PMIC
+   select DM_REGULATOR_FIXED
+   select DM_RESET
+   select REGULATOR_RK8XX
+   select PMIC_RK8XX
+   select BOARD_LATE_INIT
+   imply ROCKCHIP_COMMON_BOARD
+   imply TPL_DM
+   imply TPL_LIBCOMMON_SUPPORT
+   imply TPL_LIBGENERIC_SUPPORT
+   imply TPL_OF_CONTROL
+   imply TPL_OF_PLATDATA
+   imply TPL_RAM
+   imply TPL_ROCKCHIP_COMMON_BOARD
+   imply TPL_SERIAL
+   imply SPL_CLK
+   imply SPL_DM
+   imply SPL_DRIVERS_MISC
+   imply SPL_LIBCOMMON_SUPPORT
+   imply SPL_LIBGENERIC_SUPPORT
+   imply SPL_OF_CONTROL
+   imply SPL_RAM
+   imply SPL_REGMAP
+   imply SPL_ROCKCHIP_COMMON_BOARD
+   imply SPL_SERIAL
+   imply SPL_SYSCON
+
 config ROCKCHIP_USB_UART
bool "Route uart output to usb pins"
help
@@ -446,4 +491,5 @@ source "arch/arm/mach-rockchip/rk3368/Kconfig"
 source "arch/arm/mach-rockchip/rk3399/Kconfig"
 source "arch/arm/mach-rockchip/rk3568/Kconfig"
 source "arch/arm/mach-rockchip/rv1108/Kconfig"
+source "arch/arm/mach-rockchip/rv1126/Kconfig"
 endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 6c1c7b8a10..32138fa723 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
 obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
 obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
+obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
 
 # Clear out SPL objects, in case this is a TPL build
 obj-spl-$(CONFIG_TPL_BUILD) =
diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig 
b/arch/arm/mach-rockchip/rv1126/Kconfig
new file mode 100644
index 00..4f5021b083
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1126/Kconfig
@@ -0,0 +1,43 @@
+if 

[PATCH v4 21/25] rockchip: mkimage: Add rv1126 support

[Jagan Teki]

Add support for rv1126 package header in mkimage tool.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 tools/rkcommon.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 0db45c2d41..9c5e1a29e5 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -133,6 +133,7 @@ static struct spl_info spl_infos[] = {
{ "rk3368", "RK33", 0x8000 - 0x1000, false, RK_HEADER_V1 },
{ "rk3399", "RK33", 0x3 - 0x2000, false, RK_HEADER_V1 },
{ "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
+   { "rv1126", "110B", 0x1 - 0x1000, false, RK_HEADER_V1 },
{ "rk3568", "RK35", 0x14000 - 0x1000, false, RK_HEADER_V2 },
 };
 
-- 
2.25.1

[PATCH v4 20/25] arm: rockchip: rv1126: Set dram area unsecure for SPL

[Jagan Teki]

Unsecure the dram area so that MMC, USB, and SFC controllers
can able to read data from dram.

Signed-off-by: Jason Zhu 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 arch/arm/mach-rockchip/rv1126/rv1126.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c 
b/arch/arm/mach-rockchip/rv1126/rv1126.c
index 91554c98b6..b9b898756f 100644
--- a/arch/arm/mach-rockchip/rv1126/rv1126.c
+++ b/arch/arm/mach-rockchip/rv1126/rv1126.c
@@ -10,6 +10,8 @@
 #include 
 #include 
 
+#define FIREWALL_APB_BASE  0xffa6
+#define FW_DDR_CON_REG 0x80
 #define GRF_BASE   0xFE00
 
 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
@@ -58,6 +60,16 @@ void board_debug_uart_init(void)
 #ifndef CONFIG_TPL_BUILD
 int arch_cpu_init(void)
 {
+   /**
+* Set dram area unsecure in spl
+*
+* usb & mmc & sfc controllers can read data to dram
+* since they are unsecure.
+* (Note: only secure-world can access this register)
+*/
+   if (IS_ENABLED(CONFIG_SPL_BUILD))
+   writel(0, FIREWALL_APB_BASE + FW_DDR_CON_REG);
+
return 0;
 }
 #endif
-- 
2.25.1

[PATCH v4 18/25] ARM: dts: rockchip: Add Rockchip RV1126 SoC

[Jagan Teki]

RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.

It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.

This patch add basic core dtsi support.

Signed-off-by: Jon Lin 
Signed-off-by: Sugar Zhang 
Signed-off-by: Jagan Teki 
---
Changes for v4:
- pick changes from linux
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 arch/arm/dts/rv1126.dtsi | 438 +++
 1 file changed, 438 insertions(+)
 create mode 100644 arch/arm/dts/rv1126.dtsi

diff --git a/arch/arm/dts/rv1126.dtsi b/arch/arm/dts/rv1126.dtsi
new file mode 100644
index 00..1cb43147e9
--- /dev/null
+++ b/arch/arm/dts/rv1126.dtsi
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   compatible = "rockchip,rv1126";
+
+   interrupt-parent = <>;
+
+   aliases {
+   i2c0 = 
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@f00 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0xf00>;
+   enable-method = "psci";
+   clocks = < ARMCLK>;
+   };
+
+   cpu1: cpu@f01 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0xf01>;
+   enable-method = "psci";
+   clocks = < ARMCLK>;
+   };
+
+   cpu2: cpu@f02 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0xf02>;
+   enable-method = "psci";
+   clocks = < ARMCLK>;
+   };
+
+   cpu3: cpu@f03 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0xf03>;
+   enable-method = "psci";
+   clocks = < ARMCLK>;
+   };
+   };
+
+   arm-pmu {
+   compatible = "arm,cortex-a7-pmu";
+   interrupts = ,
+,
+,
+;
+   interrupt-affinity = <>, <>, <>, <>;
+   };
+
+   psci {
+   compatible = "arm,psci-1.0";
+   method = "smc";
+   };
+
+   timer {
+   compatible = "arm,armv7-timer";
+   interrupts = ,
+,
+,
+;
+   clock-frequency = <2400>;
+   };
+
+   xin24m: oscillator {
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   clock-output-names = "xin24m";
+   #clock-cells = <0>;
+   };
+
+   grf: syscon@fe00 {
+   compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
+   reg = <0xfe00 0x2>;
+   };
+
+   pmugrf: syscon@fe02 {
+   compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
+   reg = <0xfe02 0x1000>;
+
+   pmu_io_domains: io-domains {
+   compatible = "rockchip,rv1126-pmu-io-voltage-domain";
+   status = "disabled";
+   };
+   };
+
+   qos_emmc: qos@fe86 {
+   compatible = "rockchip,rv1126-qos", "syscon";
+   reg = <0xfe86 0x20>;
+   };
+
+   qos_nandc: qos@fe860080 {
+   compatible = "rockchip,rv1126-qos", "syscon";
+   reg = <0xfe860080 0x20>;
+   };
+
+   qos_sfc: qos@fe860200 {
+   compatible = "rockchip,rv1126-qos", "syscon";
+   reg = <0xfe860200 0x20>;
+   };
+
+   qos_sdio: qos@fe86c000 {
+   compatible = "rockchip,rv1126-qos", "syscon";
+   reg = <0xfe86c000 0x20>;
+   };
+
+   gic: interrupt-controller@feff {
+   compatible = "arm,gic-400";
+   interrupt-controller;
+   #interrupt-cells = <3>;
+   #address-cells = <0>;
+
+   reg = <0xfeff1000 0x1000>,
+ <0xfeff2000 0x2000>,
+ <0xfeff4000 0x2000>,
+ <0xfeff6000 0x2000>;
+   interrupts = ;
+   };
+
+   pmu: power-management@ff3e {
+   compatible = 

[PATCH v4 14/25] clk: rockchip: Add rv1126 clk support

[Jagan Teki]

Add clock driver support for Rockchip RV1126 SoC.

Signed-off-by: Joseph Chen 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 drivers/clk/rockchip/Makefile |1 +
 drivers/clk/rockchip/clk_rv1126.c | 1889 +
 2 files changed, 1890 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk_rv1126.c

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index a72d8fe58a..f719f4e379 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
 obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
 obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
+obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o
diff --git a/drivers/clk/rockchip/clk_rv1126.c 
b/drivers/clk/rockchip/clk_rv1126.c
new file mode 100644
index 00..3ed29364de
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rv1126.c
@@ -0,0 +1,1889 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ * Author: Finley Xiao 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define RV1126_CPUCLK_RATE(_rate, _aclk_div, _pclk_div)\
+{  \
+   .rate   = _rate##U, \
+   .aclk_div = _aclk_div,  \
+   .pclk_div = _pclk_div,  \
+}
+
+#define DIV_TO_RATE(input_rate, div)((input_rate) / ((div) + 1))
+
+static struct rockchip_cpu_rate_table rv1126_cpu_rates[] = {
+   RV1126_CPUCLK_RATE(12, 1, 5),
+   RV1126_CPUCLK_RATE(100800, 1, 5),
+   RV1126_CPUCLK_RATE(81600, 1, 3),
+   RV1126_CPUCLK_RATE(6, 1, 3),
+   RV1126_CPUCLK_RATE(40800, 1, 1),
+};
+
+static struct rockchip_pll_rate_table rv1126_pll_rates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE(16, 3, 200, 1, 1, 1, 0),
+   RK3036_PLL_RATE(14, 3, 350, 2, 1, 1, 0),
+   RK3036_PLL_RATE(12, 1, 100, 2, 1, 1, 0),
+   RK3036_PLL_RATE(118800, 1, 99, 2, 1, 1, 0),
+   RK3036_PLL_RATE(11, 3, 275, 2, 1, 1, 0),
+   RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
+   RK3036_PLL_RATE(10, 3, 250, 2, 1, 1, 0),
+   RK3036_PLL_RATE(81600, 1, 68, 2, 1, 1, 0),
+   RK3036_PLL_RATE(8, 3, 200, 2, 1, 1, 0),
+   RK3036_PLL_RATE(6, 1, 100, 4, 1, 1, 0),
+   RK3036_PLL_RATE(59400, 1, 99, 4, 1, 1, 0),
+   RK3036_PLL_RATE(5, 1, 125, 6, 1, 1, 0),
+   RK3036_PLL_RATE(2, 1, 100, 6, 2, 1, 0),
+   RK3036_PLL_RATE(1, 1, 100, 6, 4, 1, 0),
+   { /* sentinel */ },
+};
+
+static struct rockchip_pll_clock rv1126_pll_clks[] = {
+   [APLL] = PLL(pll_rk3328, PLL_APLL, RV1126_PLL_CON(0),
+RV1126_MODE_CON, 0, 10, 0, rv1126_pll_rates),
+   [DPLL] = PLL(pll_rk3328, PLL_DPLL, RV1126_PLL_CON(8),
+RV1126_MODE_CON, 2, 10, 0, NULL),
+   [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126_PLL_CON(16),
+RV1126_MODE_CON, 4, 10, 0, rv1126_pll_rates),
+   [HPLL] = PLL(pll_rk3328, PLL_HPLL, RV1126_PLL_CON(24),
+RV1126_MODE_CON, 6, 10, 0, rv1126_pll_rates),
+   [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1126_PMU_PLL_CON(0),
+RV1126_PMU_MODE, 0, 10, 0, rv1126_pll_rates),
+};
+
+static ulong rv1126_gpll_set_rate(struct rv1126_clk_priv *priv,
+ struct rv1126_pmuclk_priv *pmu_priv,
+ ulong rate);
+/*
+ *
+ * rational_best_approximation(31415, 1,
+ * (1 << 8) - 1, (1 << 5) - 1, , );
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+static void rational_best_approximation(unsigned long given_numerator,
+   unsigned long given_denominator,
+   unsigned long max_numerator,
+   unsigned long max_denominator,
+   unsigned long *best_numerator,
+   unsigned long *best_denominator)
+{
+   unsigned long n, d, n0, d0, n1, d1;
+
+   n = given_numerator;
+   d = given_denominator;
+   n0 = 0;
+   d1 = 0;
+   n1 = 1;
+   d0 = 1;
+   for (;;) {
+   unsigned long t, a;
+
+   

[PATCH v4 16/25] arm: rockchip: Add grf header for rv1126

[Jagan Teki]

Add GRF header for Rockchip RV1126.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 .../include/asm/arch-rockchip/grf_rv1126.h| 251 ++
 1 file changed, 251 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rv1126.h

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1126.h 
b/arch/arm/include/asm/arch-rockchip/grf_rv1126.h
new file mode 100644
index 00..4e0488b91a
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1126.h
@@ -0,0 +1,251 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _ASM_ARCH_GRF_RV1126_H
+#define _ASM_ARCH_GRF_RV1126_H
+
+struct rv1126_grf {
+   unsigned int soc_con0;
+   unsigned int soc_con1;
+   unsigned int soc_con2;
+   unsigned int reserved0[1];
+   unsigned int soc_status0;
+   unsigned int soc_status1;
+   unsigned int reserved1[2];
+   unsigned int cpu_con0;
+   unsigned int cpu_con1;
+   unsigned int reserved2[2];
+   unsigned int cpu_status0;
+   unsigned int reserved3[3];
+   unsigned int noc_con0;
+   unsigned int noc_con1;
+   unsigned int noc_con2;
+   unsigned int noc_con3;
+   unsigned int usbhost_con0;
+   unsigned int usbhost_con1;
+   unsigned int usbhost_status0;
+   unsigned int usbotg_con0;
+   unsigned int usbotg_con1;
+   unsigned int usbotg_status0;
+   unsigned int usbotg_status1;
+   unsigned int usbotg_status2;
+   unsigned int mac_con0;
+   unsigned int mac_con1;
+   unsigned int mac_con2;
+   unsigned int reserved4[2];
+   unsigned int mac_status0;
+   unsigned int mac_status1;
+   unsigned int mac_status2;
+   unsigned int mem_con0;
+   unsigned int mem_con1;
+   unsigned int mem_con2;
+   unsigned int mem_con3;
+   unsigned int reserved5[(0x100 - 0x09c) / 4 - 1];
+   unsigned int tsadc_con0;
+   unsigned int reserved6[3];
+   unsigned int chip_id;
+   unsigned int reserved7[(0x1 - 0x110) / 4 - 1];
+   unsigned int gpio0c_iomux_h;
+   unsigned int gpio0d_iomux_l;
+   unsigned int gpio0d_iomux_h;
+   unsigned int reserved8[1];
+   unsigned int gpio1a_iomux_l;
+   unsigned int gpio1a_iomux_h;
+   unsigned int gpio1b_iomux_l;
+   unsigned int gpio1b_iomux_h;
+   unsigned int gpio1c_iomux_l;
+   unsigned int gpio1c_iomux_h;
+   unsigned int gpio1d_iomux_l;
+   unsigned int gpio1d_iomux_h;
+   unsigned int gpio2a_iomux_l;
+   unsigned int gpio2a_iomux_h;
+   unsigned int gpio2b_iomux_l;
+   unsigned int gpio2b_iomux_h;
+   unsigned int gpio2c_iomux_l;
+   unsigned int gpio2c_iomux_h;
+   unsigned int gpio2d_iomux_l;
+   unsigned int gpio2d_iomux_h;
+   unsigned int gpio3a_iomux_l;
+   unsigned int gpio3a_iomux_h;
+   unsigned int gpio3b_iomux_l;
+   unsigned int gpio3b_iomux_h;
+   unsigned int gpio3c_iomux_l;
+   unsigned int gpio3c_iomux_h;
+   unsigned int gpio3d_iomux_l;
+   unsigned int gpio3d_iomux_h;
+   unsigned int gpio4a_iomux_l;
+   unsigned int reserved9[3];
+   unsigned int gpio0c_ds_h;
+   unsigned int gpio0d_ds_l;
+   unsigned int gpio0d_ds_h;
+   unsigned int reserved10[1];
+   unsigned int gpio1a_ds_l;
+   unsigned int gpio1a_ds_h;
+   unsigned int gpio1b_ds_l;
+   unsigned int gpio1b_ds_h;
+   unsigned int gpio1c_ds_l;
+   unsigned int gpio1c_ds_h;
+   unsigned int gpio1d_ds_l;
+   unsigned int gpio1d_ds_h;
+   unsigned int gpio2a_ds_l;
+   unsigned int gpio2a_ds_h;
+   unsigned int gpio2b_ds_l;
+   unsigned int gpio2b_ds_h;
+   unsigned int gpio2c_ds_l;
+   unsigned int gpio2c_ds_h;
+   unsigned int gpio2d_ds_l;
+   unsigned int gpio2d_ds_h;
+   unsigned int gpio3a_ds_l;
+   unsigned int gpio3a_ds_h;
+   unsigned int gpio3b_ds_l;
+   unsigned int gpio3b_ds_h;
+   unsigned int gpio3c_ds_l;
+   unsigned int gpio3c_ds_h;
+   unsigned int gpio3d_ds_l;
+   unsigned int gpio3d_ds_h;
+   unsigned int gpio4a_ds_l;
+   unsigned int reserved12[3];
+   unsigned int gpio0c_p_h;
+   unsigned int gpio0d_p;
+   unsigned int gpio1a_p;
+   unsigned int gpio1b_p;
+   unsigned int gpio1c_p;
+   unsigned int gpio1d_p;
+   unsigned int gpio2a_p;
+   unsigned int gpio2b_p;
+   unsigned int gpio2c_p;
+   unsigned int gpio2d_p;
+   unsigned int gpio3a_p;
+   unsigned int gpio3b_p;
+   unsigned int gpio3c_p;
+   unsigned int gpio3d_p;
+   unsigned int gpio4a_p;
+   unsigned int reserved13[1];
+   unsigned int gpio0c_ie_h;
+   unsigned int gpio0d_ie;
+   unsigned int gpio1a_ie;
+   unsigned int gpio1b_ie;
+   unsigned int gpio1c_ie;
+   unsigned int gpio1d_ie;
+  

[PATCH v4 17/25] ARM: dts: rockchip: Add Rockchip RV1126 pinctrl

[Jagan Teki]

Add pinctrl definitions for Rockchip RV1126.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- pick changes from linux
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 arch/arm/dts/rv1126-pinctrl.dtsi | 211 +++
 1 file changed, 211 insertions(+)
 create mode 100644 arch/arm/dts/rv1126-pinctrl.dtsi

diff --git a/arch/arm/dts/rv1126-pinctrl.dtsi b/arch/arm/dts/rv1126-pinctrl.dtsi
new file mode 100644
index 00..28d8d29942
--- /dev/null
+++ b/arch/arm/dts/rv1126-pinctrl.dtsi
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+ {
+   emmc {
+   /omit-if-no-ref/
+   emmc_rstnout: emmc-rstnout {
+   rockchip,pins =
+   /* emmc_rstn */
+   <1 RK_PA3 2 _pull_none>;
+   };
+   /omit-if-no-ref/
+   emmc_bus8: emmc-bus8 {
+   rockchip,pins =
+   /* emmc_d0 */
+   <0 RK_PC4 2 _pull_up_drv_level_2>,
+   /* emmc_d1 */
+   <0 RK_PC5 2 _pull_up_drv_level_2>,
+   /* emmc_d2 */
+   <0 RK_PC6 2 _pull_up_drv_level_2>,
+   /* emmc_d3 */
+   <0 RK_PC7 2 _pull_up_drv_level_2>,
+   /* emmc_d4 */
+   <0 RK_PD0 2 _pull_up_drv_level_2>,
+   /* emmc_d5 */
+   <0 RK_PD1 2 _pull_up_drv_level_2>,
+   /* emmc_d6 */
+   <0 RK_PD2 2 _pull_up_drv_level_2>,
+   /* emmc_d7 */
+   <0 RK_PD3 2 _pull_up_drv_level_2>;
+   };
+   /omit-if-no-ref/
+   emmc_clk: emmc-clk {
+   rockchip,pins =
+   /* emmc_clko */
+   <0 RK_PD7 2 _pull_up_drv_level_2>;
+   };
+   /omit-if-no-ref/
+   emmc_cmd: emmc-cmd {
+   rockchip,pins =
+   /* emmc_cmd */
+   <0 RK_PD5 2 _pull_up_drv_level_2>;
+   };
+   };
+   i2c0 {
+   /omit-if-no-ref/
+   i2c0_xfer: i2c0-xfer {
+   rockchip,pins =
+   /* i2c0_scl */
+   <0 RK_PB4 1 _pull_none_drv_level_0_smt>,
+   /* i2c0_sda */
+   <0 RK_PB5 1 _pull_none_drv_level_0_smt>;
+   };
+   };
+   sdmmc0 {
+   /omit-if-no-ref/
+   sdmmc0_bus4: sdmmc0-bus4 {
+   rockchip,pins =
+   /* sdmmc0_d0 */
+   <1 RK_PA4 1 _pull_up_drv_level_2>,
+   /* sdmmc0_d1 */
+   <1 RK_PA5 1 _pull_up_drv_level_2>,
+   /* sdmmc0_d2 */
+   <1 RK_PA6 1 _pull_up_drv_level_2>,
+   /* sdmmc0_d3 */
+   <1 RK_PA7 1 _pull_up_drv_level_2>;
+   };
+   /omit-if-no-ref/
+   sdmmc0_clk: sdmmc0-clk {
+   rockchip,pins =
+   /* sdmmc0_clk */
+   <1 RK_PB0 1 _pull_up_drv_level_2>;
+   };
+   /omit-if-no-ref/
+   sdmmc0_cmd: sdmmc0-cmd {
+   rockchip,pins =
+   /* sdmmc0_cmd */
+   <1 RK_PB1 1 _pull_up_drv_level_2>;
+   };
+   /omit-if-no-ref/
+   sdmmc0_det: sdmmc0-det {
+   rockchip,pins =
+   <0 RK_PA3 1 _pull_none>;
+   };
+   /omit-if-no-ref/
+   sdmmc0_pwr: sdmmc0-pwr {
+   rockchip,pins =
+   <0 RK_PC0 1 _pull_none>;
+   };
+   };
+   sdmmc1 {
+   /omit-if-no-ref/
+   sdmmc1_bus4: sdmmc1-bus4 {
+   rockchip,pins =
+   /* sdmmc1_d0 */
+   <1 RK_PB4 1 _pull_up_drv_level_2>,
+   /* sdmmc1_d1 */
+   <1 RK_PB5 1 _pull_up_drv_level_2>,
+   /* sdmmc1_d2 */
+   <1 

[PATCH v4 15/25] dt-bindings: power: Add power-domain header for rv1126

[Jagan Teki]

Add power-domain header for RV1126 SoC from description in TRM.

Signed-off-by: Elaine Zhang 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- sync changes from linux
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 .../dt-bindings/power/rockchip,rv1126-power.h | 35 +++
 1 file changed, 35 insertions(+)
 create mode 100644 include/dt-bindings/power/rockchip,rv1126-power.h

diff --git a/include/dt-bindings/power/rockchip,rv1126-power.h 
b/include/dt-bindings/power/rockchip,rv1126-power.h
new file mode 100644
index 00..38a68e000d
--- /dev/null
+++ b/include/dt-bindings/power/rockchip,rv1126-power.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__
+#define __DT_BINDINGS_POWER_RV1126_POWER_H__
+
+/* VD_CORE */
+#define RV1126_PD_CPU_00
+#define RV1126_PD_CPU_11
+#define RV1126_PD_CPU_22
+#define RV1126_PD_CPU_33
+#define RV1126_PD_CORE_ALIVE   4
+
+/* VD_PMU */
+#define RV1126_PD_PMU  5
+#define RV1126_PD_PMU_ALIVE6
+
+/* VD_NPU */
+#define RV1126_PD_NPU  7
+
+/* VD_VEPU */
+#define RV1126_PD_VEPU 8
+
+/* VD_LOGIC */
+#define RV1126_PD_VI   9
+#define RV1126_PD_VO   10
+#define RV1126_PD_ISPP 11
+#define RV1126_PD_VDPU 12
+#define RV1126_PD_CRYPTO   13
+#define RV1126_PD_DDR  14
+#define RV1126_PD_NVM  15
+#define RV1126_PD_SDIO 16
+#define RV1126_PD_USB  17
+#define RV1126_PD_LOGIC_ALIVE  18
+
+#endif
-- 
2.25.1

[PATCH v4 13/25] dt-bindings: clk: Add dt-binding header for RV1126

[Jagan Teki]

Add the dt-bindings header for the Rockchip RV1126, that gets shared
between the clock controller and the clock references in the dts.

Signed-off-by: Finley Xiao 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- sync changes from linux
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 .../dt-bindings/clock/rockchip,rv1126-cru.h   | 632 ++
 1 file changed, 632 insertions(+)
 create mode 100644 include/dt-bindings/clock/rockchip,rv1126-cru.h

diff --git a/include/dt-bindings/clock/rockchip,rv1126-cru.h 
b/include/dt-bindings/clock/rockchip,rv1126-cru.h
new file mode 100644
index 00..e89a3a5a4a
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rv1126-cru.h
@@ -0,0 +1,632 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
+ * Author: Finley Xiao 
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
+
+/* pmucru-clocks indices */
+
+/* pll clocks */
+#define PLL_GPLL   1
+
+/* sclk (special clocks) */
+#define CLK_OSC0_DIV32K2
+#define CLK_RTC32K 3
+#define CLK_WIFI_DIV   4
+#define CLK_WIFI_OSC0  5
+#define CLK_WIFI   6
+#define CLK_PMU7
+#define SCLK_UART1_DIV 8
+#define SCLK_UART1_FRACDIV 9
+#define SCLK_UART1_MUX 10
+#define SCLK_UART1 11
+#define CLK_I2C0   12
+#define CLK_I2C2   13
+#define CLK_CAPTURE_PWM0   14
+#define CLK_PWM0   15
+#define CLK_CAPTURE_PWM1   16
+#define CLK_PWM1   17
+#define CLK_SPI0   18
+#define DBCLK_GPIO019
+#define CLK_PMUPVTM20
+#define CLK_CORE_PMUPVTM   21
+#define CLK_REF12M 22
+#define CLK_USBPHY_OTG_REF 23
+#define CLK_USBPHY_HOST_REF24
+#define CLK_REF24M 25
+#define CLK_MIPIDSIPHY_REF 26
+
+/* pclk */
+#define PCLK_PDPMU 30
+#define PCLK_PMU   31
+#define PCLK_UART1 32
+#define PCLK_I2C0  33
+#define PCLK_I2C2  34
+#define PCLK_PWM0  35
+#define PCLK_PWM1  36
+#define PCLK_SPI0  37
+#define PCLK_GPIO0 38
+#define PCLK_PMUSGRF   39
+#define PCLK_PMUGRF40
+#define PCLK_PMUCRU41
+#define PCLK_CHIPVEROTP42
+#define PCLK_PDPMU_NIU 43
+#define PCLK_PMUPVTM   44
+#define PCLK_SCRKEYGEN 45
+
+#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1)
+
+/* cru-clocks indices */
+
+/* pll clocks */
+#define PLL_APLL   1
+#define PLL_DPLL   2
+#define PLL_CPLL   3
+#define PLL_HPLL   4
+
+/* sclk (special clocks) */
+#define ARMCLK 5
+#define USB480M6
+#define CLK_CORE_CPUPVTM   7
+#define CLK_CPUPVTM8
+#define CLK_SCR1   9
+#define CLK_SCR1_CORE  10
+#define CLK_SCR1_RTC   11
+#define CLK_SCR1_JTAG  12
+#define SCLK_UART0_DIV 13
+#define SCLK_UART0_FRAC14
+#define SCLK_UART0_MUX 15
+#define SCLK_UART0 16
+#define SCLK_UART2_DIV 17
+#define SCLK_UART2_FRAC18
+#define SCLK_UART2_MUX 19
+#define SCLK_UART2 20
+#define SCLK_UART3_DIV 21
+#define SCLK_UART3_FRAC22
+#define SCLK_UART3_MUX 23
+#define SCLK_UART3 24
+#define SCLK_UART4_DIV 25
+#define SCLK_UART4_FRAC26
+#define SCLK_UART4_MUX 27
+#define SCLK_UART4 28
+#define SCLK_UART5_DIV 29
+#define SCLK_UART5_FRAC30
+#define SCLK_UART5_MUX 31
+#define SCLK_UART5 32
+#define CLK_I2C1   33
+#define CLK_I2C3   34
+#define CLK_I2C4   35
+#define CLK_I2C5   36
+#define CLK_SPI1   37
+#define CLK_CAPTURE_PWM2   38
+#define CLK_PWM2   39
+#define DBCLK_GPIO140
+#define DBCLK_GPIO241
+#define DBCLK_GPIO342
+#define DBCLK_GPIO443
+#define CLK_SARADC 44
+#define CLK_TIMER0 45
+#define CLK_TIMER1 46
+#define CLK_TIMER2 47
+#define CLK_TIMER3 48
+#define CLK_TIMER4 49
+#define CLK_TIMER5 50
+#define CLK_CAN51
+#define CLK_NPU_TSADC  52
+#define CLK_NPU_TSADCPHY   53
+#define CLK_CPU_TSADC  54
+#define CLK_CPU_TSADCPHY   55
+#define CLK_CRYPTO_CORE56
+#define CLK_CRYPTO_PKA 57
+#define MCLK_I2S0_TX_DIV   58
+#define MCLK_I2S0_TX_FRACDIV   59
+#define MCLK_I2S0_TX_MUX   60
+#define MCLK_I2S0_TX   61
+#define MCLK_I2S0_RX_DIV   62
+#define MCLK_I2S0_RX_FRACDIV   63
+#define MCLK_I2S0_RX_MUX   64
+#define 

[PATCH v4 11/25] pinctrl: rockchip: Add rv1126 support

[Jagan Teki]

Add pinctrl driver for Rockchip RV1126.

Signed-off-by: Jianqun Xu 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 drivers/pinctrl/rockchip/Makefile |   1 +
 drivers/pinctrl/rockchip/pinctrl-rv1126.c | 416 ++
 2 files changed, 417 insertions(+)
 create mode 100644 drivers/pinctrl/rockchip/pinctrl-rv1126.c

diff --git a/drivers/pinctrl/rockchip/Makefile 
b/drivers/pinctrl/rockchip/Makefile
index 7d03f8101d..9884355473 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
 obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
+obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1126.c 
b/drivers/pinctrl/rockchip/pinctrl-rv1126.c
new file mode 100644
index 00..eefb8b1776
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rv1126.c
@@ -0,0 +1,416 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-rockchip.h"
+
+static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
+   {
+   .num = 0,
+   .pin = 20,
+   .reg = 0x1,
+   .bit = 0,
+   .mask = 0xf
+   },
+   {
+   .num = 0,
+   .pin = 21,
+   .reg = 0x1,
+   .bit = 4,
+   .mask = 0xf
+   },
+   {
+   .num = 0,
+   .pin = 22,
+   .reg = 0x1,
+   .bit = 8,
+   .mask = 0xf
+   },
+   {
+   .num = 0,
+   .pin = 23,
+   .reg = 0x1,
+   .bit = 12,
+   .mask = 0xf
+   },
+};
+
+static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
+   MR_TOPGRF(RK_GPIO3, RK_PD2, 1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* 
I2S0_MCLK_M0 */
+   MR_TOPGRF(RK_GPIO3, RK_PB0, 3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* 
I2S0_MCLK_M1 */
+
+   MR_TOPGRF(RK_GPIO0, RK_PD4, 4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* 
I2S1_MCLK_M0 */
+   MR_TOPGRF(RK_GPIO1, RK_PD5, 2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* 
I2S1_MCLK_M1 */
+   MR_TOPGRF(RK_GPIO2, RK_PC7, 6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* 
I2S1_MCLK_M2 */
+
+   MR_TOPGRF(RK_GPIO1, RK_PD0, 1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* 
I2S2_MCLK_M0 */
+   MR_TOPGRF(RK_GPIO2, RK_PB3, 2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* 
I2S2_MCLK_M1 */
+
+   MR_TOPGRF(RK_GPIO3, RK_PD4, 2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* 
PDM_CLK0_M0 */
+   MR_TOPGRF(RK_GPIO3, RK_PC0, 3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* 
PDM_CLK0_M1 */
+
+   MR_TOPGRF(RK_GPIO3, RK_PC6, 1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* 
CIF_CLKOUT_M0 */
+   MR_TOPGRF(RK_GPIO2, RK_PD1, 3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* 
CIF_CLKOUT_M1 */
+
+   MR_TOPGRF(RK_GPIO3, RK_PA4, 5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* 
I2C3_SCL_M0 */
+   MR_TOPGRF(RK_GPIO2, RK_PD4, 7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* 
I2C3_SCL_M1 */
+   MR_TOPGRF(RK_GPIO1, RK_PD6, 3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* 
I2C3_SCL_M2 */
+
+   MR_TOPGRF(RK_GPIO3, RK_PA0, 7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* 
I2C4_SCL_M0 */
+   MR_TOPGRF(RK_GPIO4, RK_PA0, 4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* 
I2C4_SCL_M1 */
+
+   MR_TOPGRF(RK_GPIO2, RK_PA5, 7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* 
I2C5_SCL_M0 */
+   MR_TOPGRF(RK_GPIO3, RK_PB0, 5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* 
I2C5_SCL_M1 */
+   MR_TOPGRF(RK_GPIO1, RK_PD0, 4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* 
I2C5_SCL_M2 */
+
+   MR_TOPGRF(RK_GPIO3, RK_PC0, 5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* 
SPI1_CLK_M0 */
+   MR_TOPGRF(RK_GPIO1, RK_PC6, 3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* 
SPI1_CLK_M1 */
+   MR_TOPGRF(RK_GPIO2, RK_PD5, 6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* 
SPI1_CLK_M2 */
+
+   MR_TOPGRF(RK_GPIO3, RK_PC0, 2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* 
RGMII_CLK_M0 */
+   MR_TOPGRF(RK_GPIO2, RK_PB7, 2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* 
RGMII_CLK_M1 */
+
+   MR_TOPGRF(RK_GPIO3, RK_PA1, 3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* 
CAN_TXD_M0 */
+   MR_TOPGRF(RK_GPIO3, RK_PA7, 5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* 
CAN_TXD_M1 */
+
+   MR_TOPGRF(RK_GPIO3, RK_PA4, 6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* 
PWM8_M0 */
+   MR_TOPGRF(RK_GPIO2, RK_PD7, 5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* 
PWM8_M1 */
+
+   MR_TOPGRF(RK_GPIO3, RK_PA5, 6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* 
PWM9_M0 */
+   MR_TOPGRF(RK_GPIO2, RK_PD6, 5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* 
PWM9_M1 */
+
+   

[PATCH v4 12/25] arch: rockchip: Add cru header for rv1126

[Jagan Teki]

Add clock and reset unit header include for rv1126.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 .../include/asm/arch-rockchip/cru_rv1126.h| 459 ++
 1 file changed, 459 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rv1126.h

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1126.h 
b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h
new file mode 100644
index 00..49a1f76379
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h
@@ -0,0 +1,459 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
+ * Author: Finley Xiao 
+ */
+
+#ifndef _ASM_ARCH_CRU_RV1126_H
+#define _ASM_ARCH_CRU_RV1126_H
+
+#define MHz100
+#define KHz1000
+#define OSC_HZ (24 * MHz)
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
+#define APLL_HZ(1008 * MHz)
+#else
+#define APLL_HZ(816 * MHz)
+#endif
+#define GPLL_HZ(1188 * MHz)
+#define CPLL_HZ(500 * MHz)
+#define HPLL_HZ(1400 * MHz)
+#define PCLK_PDPMU_HZ  (100 * MHz)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
+#define ACLK_PDBUS_HZ  (396 * MHz)
+#else
+#define ACLK_PDBUS_HZ  (500 * MHz)
+#endif
+#define HCLK_PDBUS_HZ  (200 * MHz)
+#define PCLK_PDBUS_HZ  (100 * MHz)
+#define ACLK_PDPHP_HZ  (300 * MHz)
+#define HCLK_PDPHP_HZ  (200 * MHz)
+#define HCLK_PDCORE_HZ (200 * MHz)
+#define HCLK_PDAUDIO_HZ(150 * MHz)
+#define CLK_OSC0_DIV_HZ(32768)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
+#define ACLK_PDVI_HZ   (297 * MHz)
+#define CLK_ISP_HZ (297 * MHz)
+#define ACLK_PDISPP_HZ (297 * MHz)
+#define CLK_ISPP_HZ(237 * MHz)
+#define ACLK_VOP_HZ(300 * MHz)
+#define DCLK_VOP_HZ(65 * MHz)
+#endif
+
+/* RV1126 pll id */
+enum rv1126_pll_id {
+   APLL,
+   DPLL,
+   CPLL,
+   HPLL,
+   GPLL,
+   PLL_COUNT,
+};
+
+struct rv1126_clk_info {
+   unsigned long id;
+   char *name;
+   bool is_cru;
+};
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rv1126_pmuclk_priv {
+   struct rv1126_pmucru *pmucru;
+   ulong gpll_hz;
+};
+
+struct rv1126_clk_priv {
+   struct rv1126_cru *cru;
+   struct rv1126_grf *grf;
+   ulong gpll_hz;
+   ulong cpll_hz;
+   ulong hpll_hz;
+   ulong armclk_hz;
+   ulong armclk_enter_hz;
+   ulong armclk_init_hz;
+   bool sync_kernel;
+   bool set_armclk_rate;
+};
+
+struct rv1126_pll {
+   unsigned int con0;
+   unsigned int con1;
+   unsigned int con2;
+   unsigned int con3;
+   unsigned int con4;
+   unsigned int con5;
+   unsigned int con6;
+   unsigned int reserved0[1];
+};
+
+struct rv1126_pmucru {
+   unsigned int pmu_mode;
+   unsigned int reserved1[3];
+   struct rv1126_pll pll;
+   unsigned int offsetcal_status;
+   unsigned int reserved2[51];
+   unsigned int pmu_clksel_con[14];
+   unsigned int reserved3[18];
+   unsigned int pmu_clkgate_con[3];
+   unsigned int reserved4[29];
+   unsigned int pmu_softrst_con[2];
+   unsigned int reserved5[14];
+   unsigned int pmu_autocs_con[2];
+};
+
+check_member(rv1126_pmucru, pmu_autocs_con[1], 0x244);
+
+struct rv1126_cru {
+   struct rv1126_pll pll[4];
+   unsigned int offsetcal_status[4];
+   unsigned int mode;
+   unsigned int reserved1[27];
+   unsigned int clksel_con[78];
+   unsigned int reserved2[18];
+   unsigned int clkgate_con[25];
+   unsigned int reserved3[7];
+   unsigned int softrst_con[15];
+   unsigned int reserved4[17];
+   unsigned int ssgtbl[32];
+   unsigned int glb_cnt_th;
+   unsigned int glb_rst_st;
+   unsigned int glb_srst_fst;
+   unsigned int glb_srst_snd;
+   unsigned int glb_rst_con;
+   unsigned int reserved5[11];
+   unsigned int sdmmc_con[2];
+   unsigned int sdio_con[2];
+   unsigned int emmc_con[2];
+   unsigned int reserved6[2];
+   unsigned int gmac_con;
+   unsigned int misc[2];
+   unsigned int reserved7[45];
+   unsigned int autocs_con[26];
+};
+
+check_member(rv1126_cru, autocs_con[25], 0x584);
+
+struct pll_rate_table {
+   unsigned long rate;
+   unsigned int fbdiv;
+   unsigned int postdiv1;
+   unsigned int refdiv;
+   unsigned int postdiv2;
+   unsigned int dsmpd;
+   unsigned int frac;
+};
+
+struct cpu_rate_table {
+   unsigned long rate;
+   unsigned int aclk_div;
+   unsigned int pclk_div;
+};
+
+#define RV1126_PMU_MODE0x0
+#define RV1126_PMU_PLL_CON(x)  ((x) * 0x4 + 0x10)
+#define RV1126_PLL_CON(x)  ((x) * 0x4)
+#define RV1126_MODE_CON0x90
+
+enum {
+   /* 

[PATCH v4 10/25] pinctrl: rockchip: Add pinctrl route types

[Jagan Teki]

Some pins in rockchip are routed via Top GRF and PMU GRF
instead of direct regmap.

Add support to handle all these routing paths so that the
SoC pinctrl drivers will use them accordingly.

Signed-off-by: Jianqun Xu 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 drivers/pinctrl/rockchip/pinctrl-px30.c   | 11 +---
 drivers/pinctrl/rockchip/pinctrl-rk3128.c | 11 +---
 drivers/pinctrl/rockchip/pinctrl-rk322x.c | 11 +---
 drivers/pinctrl/rockchip/pinctrl-rk3288.c | 11 +---
 drivers/pinctrl/rockchip/pinctrl-rk3308.c | 11 +---
 drivers/pinctrl/rockchip/pinctrl-rk3328.c | 11 +---
 drivers/pinctrl/rockchip/pinctrl-rk3399.c | 11 +---
 .../pinctrl/rockchip/pinctrl-rockchip-core.c  | 45 --
 drivers/pinctrl/rockchip/pinctrl-rockchip.h   | 58 ++-
 9 files changed, 102 insertions(+), 78 deletions(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl-px30.c 
b/drivers/pinctrl/rockchip/pinctrl-px30.c
index 9de29c0b8b..2c35491b24 100644
--- a/drivers/pinctrl/rockchip/pinctrl-px30.c
+++ b/drivers/pinctrl/rockchip/pinctrl-px30.c
@@ -80,7 +80,7 @@ static int px30_set_mux(struct rockchip_pin_bank *bank, int 
pin, int mux)
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
-   u32 data, route_reg, route_val;
+   u32 data;
 
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
@@ -90,15 +90,6 @@ static int px30_set_mux(struct rockchip_pin_bank *bank, int 
pin, int mux)
reg = bank->iomux[iomux_num].offset;
reg += rockchip_get_mux_data(mux_type, pin, , );
 
-   if (bank->route_mask & BIT(pin)) {
-   if (rockchip_get_mux_route(bank, pin, mux, _reg,
-  _val)) {
-   ret = regmap_write(regmap, route_reg, route_val);
-   if (ret)
-   return ret;
-   }
-   }
-
data = (mask << (bit + 16));
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c 
b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
index e6dc1af86e..355c45eb7f 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
@@ -106,7 +106,7 @@ static int rk3128_set_mux(struct rockchip_pin_bank *bank, 
int pin, int mux)
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
-   u32 data, route_reg, route_val;
+   u32 data;
 
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
@@ -119,15 +119,6 @@ static int rk3128_set_mux(struct rockchip_pin_bank *bank, 
int pin, int mux)
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, , , );
 
-   if (bank->route_mask & BIT(pin)) {
-   if (rockchip_get_mux_route(bank, pin, mux, _reg,
-  _val)) {
-   ret = regmap_write(regmap, route_reg, route_val);
-   if (ret)
-   return ret;
-   }
-   }
-
data = (mask << (bit + 16));
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c 
b/drivers/pinctrl/rockchip/pinctrl-rk322x.c
index 7c58f40d93..351406da2d 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c
@@ -150,7 +150,7 @@ static int rk3228_set_mux(struct rockchip_pin_bank *bank, 
int pin, int mux)
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
-   u32 data, route_reg, route_val;
+   u32 data;
 
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
@@ -160,15 +160,6 @@ static int rk3228_set_mux(struct rockchip_pin_bank *bank, 
int pin, int mux)
reg = bank->iomux[iomux_num].offset;
reg += rockchip_get_mux_data(mux_type, pin, , );
 
-   if (bank->route_mask & BIT(pin)) {
-   if (rockchip_get_mux_route(bank, pin, mux, _reg,
-  _val)) {
-   ret = regmap_write(regmap, route_reg, route_val);
-   if (ret)
-   return ret;
-   }
-   }
-
data = (mask << (bit + 16));
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c 
b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
index 5894f47f53..a976b7aeeb 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
@@ 

[PATCH v4 09/25] ram: rockchip: Add rv1126 lpddr4 support

[Jagan Teki]

Add LPDDR4 detection timings and support for RV1126.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 .../sdram-rv1126-lpddr4-detect-1056.inc   | 78 +++
 .../sdram-rv1126-lpddr4-detect-328.inc| 78 +++
 .../sdram-rv1126-lpddr4-detect-396.inc| 78 +++
 .../sdram-rv1126-lpddr4-detect-528.inc| 78 +++
 .../sdram-rv1126-lpddr4-detect-664.inc| 78 +++
 .../sdram-rv1126-lpddr4-detect-784.inc| 78 +++
 .../sdram-rv1126-lpddr4-detect-924.inc| 78 +++
 drivers/ram/rockchip/sdram_rv1126.c   | 10 +++
 8 files changed, 556 insertions(+)
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-1056.inc
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-328.inc
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-396.inc
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-528.inc
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-664.inc
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-784.inc
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-924.inc

diff --git a/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-1056.inc 
b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-1056.inc
new file mode 100644
index 00..705cbfb5cb
--- /dev/null
+++ b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-1056.inc
@@ -0,0 +1,78 @@
+{
+   {
+   {
+   .rank = 0x1,
+   .col = 0xB,
+   .bk = 0x3,
+   .bw = 0x1,
+   .dbw = 0x1,
+   .row_3_4 = 0x0,
+   .cs0_row = 0x11,
+   .cs1_row = 0x11,
+   .cs0_high16bit_row = 0x0,
+   .cs1_high16bit_row = 0x0,
+   .ddrconfig = 0
+   },
+   {
+   {0x41241522},
+   {0x15050b07},
+   {0x0602},
+   {0x},
+   {0x0054},
+   {0x},
+   0x00ff
+   }
+   },
+   {
+   .ddr_freq = 1056,   /* clock rate(MHz) */
+   .dramtype = LPDDR4,
+   .num_channels = 1,
+   .stride = 0,
+   .odt = 1
+   },
+   {
+   {
+   {0x, 0x81081020},   /* MSTR */
+   {0x0064, 0x00400094},   /* RFSHTMG */
+   {0x00d0, 0x00030409},   /* INIT0 */
+   {0x00d4, 0x0069},   /* INIT1 */
+   {0x00d8, 0x0206},   /* INIT2 */
+   {0x00dc, 0x0034001b},   /* INIT3 */
+   {0x00e0, 0x0031},   /* INIT4 */
+   {0x00e8, 0x0011},   /* INIT6 */
+   {0x00ec, 0x},   /* INIT7 */
+   {0x00f4, 0x000f033f},   /* RANKCTL */
+   {0x0100, 0x14161217},   /* DRAMTMG0 */
+   {0x0104, 0x00040422},   /* DRAMTMG1 */
+   {0x0108, 0x050a0e0f},   /* DRAMTMG2 */
+   {0x010c, 0x00808000},   /* DRAMTMG3 */
+   {0x0110, 0x0a04060c},   /* DRAMTMG4 */
+   {0x0114, 0x02040808},   /* DRAMTMG5 */
+   {0x0118, 0x01010005},   /* DRAMTMG6 */
+   {0x011c, 0x0401},   /* DRAMTMG7 */
+   {0x0120, 0x0606},   /* DRAMTMG8 */
+   {0x0130, 0x0002},   /* DRAMTMG12 */
+   {0x0134, 0x0a12},   /* DRAMTMG13 */
+   {0x0138, 0x0098},   /* DRAMTMG14 */
+   {0x0180, 0x02100010},   /* ZQCTL0 */
+   {0x0184, 0x01b0},   /* ZQCTL1 */
+   {0x0190, 0x07070001},   /* DFITMG0 */
+   {0x0198, 0x07000101},   /* DFILPCFG0 */
+   {0x01a0, 0xc043},   /* DFIUPD0 */
+   {0x0240, 0x0b050d3c},   /* ODTCFG */
+   {0x0244, 0x0101},   /* ODTMAP */
+   {0x0250, 0x1f00},   /* SCHED */
+   {0x0490, 0x0001},   /* PCTRL_0 */
+   {0x, 0x}
+   }
+   },
+   {
+   {
+   {0x0004, 0x008d},   /* PHYREG01 */
+   

[PATCH v4 08/25] ram: rockchip: rv1126: Control ddr init prints via DEBUG

[Jagan Teki]

Control the ddr init print messages via RAM_ROCKCHIP_DEBUG
instead of printing by default.

This gives an option to configs to enable these prints or
not.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 drivers/ram/rockchip/sdram_rv1126.c | 38 +++--
 1 file changed, 25 insertions(+), 13 deletions(-)

diff --git a/drivers/ram/rockchip/sdram_rv1126.c 
b/drivers/ram/rockchip/sdram_rv1126.c
index d41e043556..34b690668a 100644
--- a/drivers/ram/rockchip/sdram_rv1126.c
+++ b/drivers/ram/rockchip/sdram_rv1126.c
@@ -3358,22 +3358,33 @@ static void ddr_set_rate_for_fsp(struct dram_info *dram,
if (get_wrlvl_val(dram, sdram_params))
printascii("get wrlvl value fail\n");
 
-   printascii("change to: ");
-   printdec(f1);
-   printascii("MHz\n");
+   if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) {
+   printascii("change to: ");
+   printdec(f1);
+   printascii("MHz\n");
+   }
ddr_set_rate(_info, sdram_params, f1,
 sdram_params->base.ddr_freq, 1, 1, 1);
-   printascii("change to: ");
-   printdec(f2);
-   printascii("MHz\n");
+
+   if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) {
+   printascii("change to: ");
+   printdec(f2);
+   printascii("MHz\n");
+   }
ddr_set_rate(_info, sdram_params, f2, f1, 2, 0, 1);
-   printascii("change to: ");
-   printdec(f3);
-   printascii("MHz\n");
+
+   if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) {
+   printascii("change to: ");
+   printdec(f3);
+   printascii("MHz\n");
+   }
ddr_set_rate(_info, sdram_params, f3, f2, 3, 1, 1);
-   printascii("change to: ");
-   printdec(f0);
-   printascii("MHz(final freq)\n");
+
+   if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) {
+   printascii("change to: ");
+   printdec(f0);
+   printascii("MHz(final freq)\n");
+   }
ddr_set_rate(_info, sdram_params, f0, f3, 0, 0, 1);
 }
 
@@ -3465,7 +3476,8 @@ static int rv1126_dmc_init(struct udevice *dev)
save_rw_trn_result_to_ddr(_trn_result);
 #endif
 
-   printascii("out\n");
+   if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG))
+   printascii("out\n");
 
return ret;
 error:
-- 
2.25.1

[PATCH v4 06/25] ram: rockchip: Add rv1126 ddr loader params

[Jagan Teki]

Add DDR loader parameters for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 .../rockchip/sdram-rv1126-loader_params.inc   | 197 ++
 1 file changed, 197 insertions(+)
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-loader_params.inc

diff --git a/drivers/ram/rockchip/sdram-rv1126-loader_params.inc 
b/drivers/ram/rockchip/sdram-rv1126-loader_params.inc
new file mode 100644
index 00..a4c9e7f328
--- /dev/null
+++ b/drivers/ram/rockchip/sdram-rv1126-loader_params.inc
@@ -0,0 +1,197 @@
+0x12345678,
+2,/* version */
+(0 << 0) | (1 << 8) | (9 << 16) | (8 << 24),/* cpu_gen,global index */
+(0 << 0) | (9 << 8) | (17 << 16) | (9 << 24),/* d2,d3 index */
+(26 << 0) | (9 << 8) | (0 << 16) | (0 << 24),/* d4,d5 index */
+(0 << 0) | (9 << 8) | (35 << 16) | (9 << 24),/* lp2,lp3 index */
+(44 << 0) | (13 << 8) | (0 << 16) | (0 << 24),/* lp4,lp5 index */
+(0 << 0) | (0 << 8) | (57 << 16) | (8 << 24),/* skew index, dq_map index */
+(65 << 0) | (13 << 8) | (0 << 16) | (0 << 24), /*lp4x index*/
+/* global info */
+0,
+(93 << 16) | 13,/* sr_idle << 16 | pd_idle */
+0,/* channel info */
+1,/* 2t info */
+0, 0, 0, 0,/* reserved */
+
+/* ddr3 */
+(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT),
+(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT),
+(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT),
+/* drv when odt on */
+(30 << PHY_DQ_DRV_SHIFT) | (41 << PHY_CA_DRV_SHIFT) |
+   (38 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
+/* drv when odt off */
+(30 << PHY_DQ_DRV_SHIFT) | (30 << PHY_CA_DRV_SHIFT) |
+   (38 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
+/* odt info */
+(120 << DRAM_ODT_SHIFT) | (141 << PHY_ODT_SHIFT) |
+   (1 << PHY_ODT_PUUP_EN_SHIFT) |
+   (0 << PHY_ODT_PUDN_EN_SHIFT),
+/* odt enable freq */
+(333 << DRAM_ODT_EN_FREQ_SHIFT) | (333 << PHY_ODT_EN_FREQ_SHIFT),
+/* slew rate when odt enable */
+(0x1f << PHY_DQ_SR_SHIFT) | (0x1f << PHY_CA_SR_SHIFT) |
+   (0x1f << PHY_CLK_SR_SHIFT),
+/* slew  ratee when odt disable */
+(0x1f << PHY_DQ_SR_SHIFT) | (0x1f << PHY_CA_SR_SHIFT) |
+   (0x1f << PHY_CLK_SR_SHIFT),
+
+/* ddr4 */
+(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT),
+(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT),
+(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT),
+/* drv when odt on */
+(37 << PHY_DQ_DRV_SHIFT) | (44 << PHY_CA_DRV_SHIFT) |
+   (37 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
+/* drv when odt off */
+(37 << PHY_DQ_DRV_SHIFT) | (44 << PHY_CA_DRV_SHIFT) |
+   (37 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
+/* odt info */
+(120 << DRAM_ODT_SHIFT) | (148 << PHY_ODT_SHIFT) |
+   (1 << PHY_ODT_PUUP_EN_SHIFT) | (1 << PHY_ODT_PUDN_EN_SHIFT),
+/* odt enable freq */
+(625 << DRAM_ODT_EN_FREQ_SHIFT) | (625 << PHY_ODT_EN_FREQ_SHIFT),
+/* slew rate when odt enable */
+(0xe << PHY_DQ_SR_SHIFT) | (0x3 << PHY_CA_SR_SHIFT) |
+   (0x3 << PHY_CLK_SR_SHIFT),
+/* slew  ratee when odt disable */
+(0xe << PHY_DQ_SR_SHIFT) | (0x3 << PHY_CA_SR_SHIFT) |
+   (0x3 << PHY_CLK_SR_SHIFT),
+
+/* lpddr3 */
+(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT),
+(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT),
+(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT),
+/* drv when odt on */
+(28 << PHY_DQ_DRV_SHIFT) | (37 << PHY_CA_DRV_SHIFT) |
+   (34 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
+/* drv when odt off */
+(28 << PHY_DQ_DRV_SHIFT) | (37 << PHY_CA_DRV_SHIFT) |
+   (34 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
+/* odt info */
+(120 << DRAM_ODT_SHIFT) | (148 << PHY_ODT_SHIFT) |
+   (1 << PHY_ODT_PUUP_EN_SHIFT) | (1 << PHY_ODT_PUDN_EN_SHIFT),
+/* odt enable freq */
+(333 << DRAM_ODT_EN_FREQ_SHIFT) | (333 << PHY_ODT_EN_FREQ_SHIFT),
+
+/* slew rate when odt enable */
+(0xe << PHY_DQ_SR_SHIFT) | (0x0 << PHY_CA_SR_SHIFT) |
+   (0x0 << PHY_CLK_SR_SHIFT),
+/* slew  ratee when odt disable */
+(0xe << PHY_DQ_SR_SHIFT) | (0x0 << PHY_CA_SR_SHIFT) |
+   (0x0 << PHY_CLK_SR_SHIFT),
+
+/* lpddr4 */
+(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT),
+(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT),
+(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT),
+
+/* drv when odt on */
+(38 << PHY_DQ_DRV_SHIFT) | (46 << PHY_CA_DRV_SHIFT) |
+   (38 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT),
+/* drv when odt off */
+(38 << PHY_DQ_DRV_SHIFT) | (46 << PHY_CA_DRV_SHIFT) |
+   (38 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT),
+/* odt info and PU-cal info */
+(240 << DRAM_ODT_SHIFT) | (80 << PHY_ODT_SHIFT) |
+   (0 << LP4_CA_ODT_SHIFT) |
+   (LPDDR4_VDDQ_2_5 << LP4_DRV_PU_CAL_ODTEN_SHIFT) |
+   (LPDDR4_VDDQ_2_5 << LP4_DRV_PU_CAL_ODTOFF_SHIFT) |
+   (0 << PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT) |
+   (0 << PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT),
+/* odt enable freq */
+(333 << 

[PATCH v4 05/25] ram: rockchip: Add rv1126 ddr3 support

[Jagan Teki]

Add DDR3 detection timings for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 .../sdram-rv1126-ddr3-detect-1056.inc | 72 +++
 .../rockchip/sdram-rv1126-ddr3-detect-328.inc | 72 +++
 .../rockchip/sdram-rv1126-ddr3-detect-396.inc | 72 +++
 .../rockchip/sdram-rv1126-ddr3-detect-528.inc | 72 +++
 .../rockchip/sdram-rv1126-ddr3-detect-664.inc | 72 +++
 .../rockchip/sdram-rv1126-ddr3-detect-784.inc | 72 +++
 .../rockchip/sdram-rv1126-ddr3-detect-924.inc | 72 +++
 7 files changed, 504 insertions(+)
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr3-detect-1056.inc
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr3-detect-328.inc
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr3-detect-396.inc
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr3-detect-528.inc
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr3-detect-664.inc
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr3-detect-784.inc
 create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr3-detect-924.inc

diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-1056.inc 
b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-1056.inc
new file mode 100644
index 00..4cde21565b
--- /dev/null
+++ b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-1056.inc
@@ -0,0 +1,72 @@
+{
+   {
+   {
+   .rank = 0x1,
+   .col = 0xC,
+   .bk = 0x3,
+   .bw = 0x0,
+   .dbw = 0x0,
+   .row_3_4 = 0x0,
+   .cs0_row = 0x10,
+   .cs1_row = 0x10,
+   .cs0_high16bit_row = 0x10,
+   .cs1_high16bit_row = 0x10,
+   .ddrconfig = 0
+   },
+   {
+   {0x351b1019},
+   {0x12030903},
+   {0x0002},
+   {0x},
+   {0x000c},
+   {0x},
+   0x00ff
+   }
+   },
+   {
+   .ddr_freq = 1056,   /* clock rate(MHz) */
+   .dramtype = DDR3,
+   .num_channels = 1,
+   .stride = 0,
+   .odt = 1
+   },
+   {
+   {
+   {0x, 0x43042001},   /* MSTR */
+   {0x0064, 0x008000b9},   /* RFSHTMG */
+   {0x00d0, 0x00020103},   /* INIT0 */
+   {0x00d4, 0x0069},   /* INIT1 */
+   {0x00d8, 0x0100},   /* INIT2 */
+   {0x00dc, 0x01240040},   /* INIT3 */
+   {0x00e0, 0x0028},   /* INIT4 */
+   {0x00e4, 0x000c},   /* INIT5 */
+   {0x00f4, 0x000f011f},   /* RANKCTL */
+   {0x0100, 0x0f132414},   /* DRAMTMG0 */
+   {0x0104, 0x000d0419},   /* DRAMTMG1 */
+   {0x0108, 0x0507050b},   /* DRAMTMG2 */
+   {0x010c, 0x00202008},   /* DRAMTMG3 */
+   {0x0110, 0x07020408},   /* DRAMTMG4 */
+   {0x0114, 0x06060404},   /* DRAMTMG5 */
+   {0x0120, 0x0907},   /* DRAMTMG8 */
+   {0x0180, 0x00a9002b},   /* ZQCTL0 */
+   {0x0184, 0x},   /* ZQCTL1 */
+   {0x0190, 0x07050003},   /* DFITMG0 */
+   {0x0198, 0x07000101},   /* DFILPCFG0 */
+   {0x01a0, 0xc043},   /* DFIUPD0 */
+   {0x0240, 0x06000610},   /* ODTCFG */
+   {0x0244, 0x0201},   /* ODTMAP */
+   {0x0250, 0x1f00},   /* SCHED */
+   {0x0490, 0x0001},   /* PCTRL_0 */
+   {0x, 0x}
+   }
+   },
+   {
+   {
+   {0x0004, 0x008a},   /* PHYREG01 */
+   {0x0014, 0x000e},   /* PHYREG05 */
+   {0x0018, 0x},   /* PHYREG06 */
+   {0x001c, 0x000a},   /* PHYREG07 */
+   {0x, 0x}
+   }
+   }
+},
diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-328.inc 
b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-328.inc
new file mode 100644
index 00..eef61ab500
--- /dev/null
+++ 

[PATCH v4 04/25] ram: rockchip: Update ddr pctl regs for px30

[Jagan Teki]

Add full ddr pctl registers and bit masks for px30.

Signed-off-by: YouMin Chen 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 .../asm/arch-rockchip/sdram_pctl_px30.h   | 100 +-
 drivers/ram/rockchip/sdram_pctl_px30.c|   6 +-
 2 files changed, 101 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h 
b/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h
index 3a3657789f..3780dc6ea5 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h
@@ -12,7 +12,7 @@
 #endif
 
 struct ddr_pctl_regs {
-   u32 pctl[30][2];
+   u32 pctl[35][2];
 };
 
 /* ddr pctl registers define */
@@ -25,6 +25,7 @@ struct ddr_pctl_regs {
 #define DDR_PCTL2_MRCTRL2  0x1c
 #define DDR_PCTL2_DERATEEN 0x20
 #define DDR_PCTL2_DERATEINT0x24
+#define DDR_PCTL2_MSTR20x28
 #define DDR_PCTL2_PWRCTL   0x30
 #define DDR_PCTL2_PWRTMG   0x34
 #define DDR_PCTL2_HWLPCTL  0x38
@@ -122,8 +123,103 @@ struct ddr_pctl_regs {
 #define DDR_PCTL2_PCFGW_n  0x408
 #define DDR_PCTL2_PCTRL_n  0x490
 
+#define UMCTL2_REGS_FREQ(n)\
+   ((0x1000 * (n) + (((n) > 0) ? 0x1000 : 0)))
+
+/* PCTL2_MSTR */
+#define PCTL2_FREQUENCY_MODE_MASK  (1)
+#define PCTL2_FREQUENCY_MODE_SHIFT (29)
+#define PCTL2_DLL_OFF_MODE BIT(15)
+/* PCTL2_STAT */
+#define PCTL2_SELFREF_TYPE_MASK(3 << 4)
+#define PCTL2_SELFREF_TYPE_SR_NOT_AUTO (2 << 4)
+#define PCTL2_OPERATING_MODE_MASK  (7)
+#define PCTL2_OPERATING_MODE_INIT  (0)
+#define PCTL2_OPERATING_MODE_NORMAL(1)
+#define PCTL2_OPERATING_MODE_PD(2)
+#define PCTL2_OPERATING_MODE_SR(3)
+/* PCTL2_MRCTRL0 */
+#define PCTL2_MR_WRBIT(31)
+#define PCTL2_MR_ADDR_SHIFT(12)
+#define PCTL2_MR_RANK_SHIFT(4)
+#define PCTL2_MR_TYPE_WR   (0)
+#define PCTL2_MR_TYPE_RD   (1)
+/* PCTL2_MRCTRL1 */
+#define PCTL2_MR_ADDRESS_SHIFT (8)
+#define PCTL2_MR_DATA_MASK (0xff)
 /* PCTL2_MRSTAT */
-#define MR_WR_BUSY BIT(0)
+#define PCTL2_MR_WR_BUSY   BIT(0)
+/* PCTL2_DERATEEN */
+#define PCTL2_DERATE_ENABLE(1)
+/* PCTL2_PWRCTL */
+#define PCTL2_SELFREF_SW   BIT(5)
+#define PCTL2_POWERDOWN_EN BIT(1)
+#define PCTL2_SELFREF_EN   (1)
+/* PCTL2_PWRTMG */
+#define PCTL2_SELFREF_TO_X32_MASK  (0xFF)
+#define PCTL2_SELFREF_TO_X32_SHIFT (16)
+#define PCTL2_POWERDOWN_TO_X32_MASK(0x1F)
+/* PCTL2_INIT3 */
+#define PCTL2_DDR34_MR0_SHIFT  (16)
+#define PCTL2_LPDDR234_MR1_SHIFT   (16)
+#define PCTL2_DDR34_MR1_SHIFT  (0)
+#define PCTL2_LPDDR234_MR2_SHIFT   (0)
+/* PCTL2_INIT4 */
+#define PCTL2_DDR34_MR2_SHIFT  (16)
+#define PCTL2_LPDDR234_MR3_SHIFT   (16)
+#define PCTL2_DDR34_MR3_SHIFT  (0)
+#define PCTL2_LPDDR4_MR13_SHIFT(0)
+
+/* PCTL2_INIT6 */
+#define PCTL2_DDR4_MR4_SHIFT   (16)
+#define PCTL2_LPDDR4_MR11_SHIFT(16)
+#define PCTL2_DDR4_MR5_SHIFT   (0)
+#define PCTL2_LPDDR4_MR12_SHIFT(0)
+
+/* PCTL2_INIT7 */
+#define PCTL2_LPDDR4_MR22_SHIFT(16)
+#define PCTL2_DDR4_MR6_SHIFT   (0)
+#define PCTL2_LPDDR4_MR14_SHIFT(0)
+
+#define PCTL2_MR_MASK  (0x)
+
+/* PCTL2_RFSHCTL3 */
+#define PCTL2_DIS_AUTO_REFRESH (1)
+/* PCTL2_ZQCTL0 */
+#define PCTL2_DIS_AUTO_ZQ  BIT(31)
+#define PCTL2_DIS_SRX_ZQCL BIT(30)
+/* PCTL2_DFILPCFG0 */
+#define PCTL2_DFI_LP_EN_SR BIT(8)
+#define PCTL2_DFI_LP_EN_SR_MASKBIT(8)
+#define PCTL2_DFI_LP_EN_SR_SHIFT   (8)
+/* PCTL2_DFIMISC */
+#define PCTL2_DFI_INIT_COMPLETE_EN (1)
+/* PCTL2_DFISTAT */
+#define PCTL2_DFI_LP_ACK   BIT(1)
+#define PCTL2_DFI_INIT_COMPLETE(1)
+/* PCTL2_DBG1 */
+#define PCTL2_DIS_HIF  BIT(1)
+/* PCTL2_DBGCAM */
+#define PCTL2_DBG_WR_Q_EMPTY   BIT(26)
+#define PCTL2_DBG_RD_Q_EMPTY   BIT(25)
+#define PCTL2_DBG_LPR_Q_DEPTH_MASK (0x << 8)
+#define PCTL2_DBG_LPR_Q_DEPTH_EMPTY(0x0 << 8)
+/* PCTL2_DBGCMD */
+#define PCTL2_RANK1_REFRESHBIT(1)
+#define PCTL2_RANK0_REFRESH(1)
+/* PCTL2_DBGSTAT */
+#define PCTL2_RANK1_REFRESH_BUSY   BIT(1)
+#define PCTL2_RANK0_REFRESH_BUSY   (1)
+/* PCTL2_SWCTL */
+#define PCTL2_SW_DONE  (1)
+#define PCTL2_SW_DONE_CLEAR(0)
+/* PCTL2_SWSTAT */
+#define PCTL2_SW_DONE_ACK  (1)
+/* PCTL2_PSTAT */
+#define PCTL2_WR_PORT_BUSY_0   BIT(16)
+#define PCTL2_RD_PORT_BUSY_0   (1)
+/* PCTL2_PCTRLn */
+#define PCTL2_PORT_EN   

[PATCH v4 03/25] ram: rockchip: Compute ddr capacity based on grf split

[Jagan Teki]

DDR chip capacity is computed based on GRF split in some
Rockchip SoC's like PX30 and RV1126.

Add split argument in ddr print info so-that the respective
ddr driver will pass the grf split.

Signed-off-by: YouMin Chen 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 +-
 drivers/ram/rockchip/sdram_common.c   | 6 --
 drivers/ram/rockchip/sdram_px30.c | 2 +-
 drivers/ram/rockchip/sdram_rk3328.c   | 2 +-
 drivers/ram/rockchip/sdram_rk3399.c   | 2 +-
 5 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h 
b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 5efa6e9445..a14b37cbc5 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -116,7 +116,7 @@ struct sdram_base_params {
 
 void sdram_print_dram_type(unsigned char dramtype);
 void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
- struct sdram_base_params *base);
+ struct sdram_base_params *base, u32 split);
 void sdram_print_stride(unsigned int stride);
 
 void sdram_org_config(struct sdram_cap_info *cap_info,
diff --git a/drivers/ram/rockchip/sdram_common.c 
b/drivers/ram/rockchip/sdram_common.c
index b3e7421d08..1c3236746a 100644
--- a/drivers/ram/rockchip/sdram_common.c
+++ b/drivers/ram/rockchip/sdram_common.c
@@ -36,7 +36,7 @@ void sdram_print_dram_type(unsigned char dramtype)
 }
 
 void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
- struct sdram_base_params *base)
+ struct sdram_base_params *base, u32 split)
 {
u64 cap;
u32 bg;
@@ -83,6 +83,8 @@ void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
cap = sdram_get_cs_cap(cap_info, 3, base->dramtype);
if (cap_info->row_3_4)
cap = cap * 3 / 4;
+   else if (split)
+   cap = cap / 2 + (split << 24) / 2;
 
printascii(" Size=");
printdec(cap >> 20);
@@ -123,7 +125,7 @@ inline void sdram_print_dram_type(unsigned char dramtype)
 }
 
 inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
-struct sdram_base_params *base)
+struct sdram_base_params *base, u32 split)
 {
 }
 
diff --git a/drivers/ram/rockchip/sdram_px30.c 
b/drivers/ram/rockchip/sdram_px30.c
index 357fe2432a..a003893538 100644
--- a/drivers/ram/rockchip/sdram_px30.c
+++ b/drivers/ram/rockchip/sdram_px30.c
@@ -711,7 +711,7 @@ int sdram_init(void)
if (ret)
goto error;
 
-   sdram_print_ddr_info(_params->ch.cap_info, _params->base);
+   sdram_print_ddr_info(_params->ch.cap_info, _params->base, 
0);
 
printascii("out\n");
return ret;
diff --git a/drivers/ram/rockchip/sdram_rk3328.c 
b/drivers/ram/rockchip/sdram_rk3328.c
index 9c6798f816..efe0049ead 100644
--- a/drivers/ram/rockchip/sdram_rk3328.c
+++ b/drivers/ram/rockchip/sdram_rk3328.c
@@ -506,7 +506,7 @@ static int sdram_init_detect(struct dram_info *dram,
writel(sys_reg3, >grf->os_reg[3]);
}
 
-   sdram_print_ddr_info(_params->ch.cap_info, _params->base);
+   sdram_print_ddr_info(_params->ch.cap_info, _params->base, 
0);
 
return 0;
 }
diff --git a/drivers/ram/rockchip/sdram_rk3399.c 
b/drivers/ram/rockchip/sdram_rk3399.c
index ce49a91393..1cb67cf14a 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -2986,7 +2986,7 @@ static int sdram_init(struct dram_info *dram,
continue;
}
 
-   sdram_print_ddr_info(cap_info, >base);
+   sdram_print_ddr_info(cap_info, >base, 0);
set_memory_map(chan, channel, params);
cap_info->ddrconfig =
calculate_ddrconfig(params, channel);
-- 
2.25.1

[PATCH v4 01/25] ram: Mark ram-uclass depend on TPL_DM or SPL_DM

[Jagan Teki]

ram-uclass is building irrespective of whether TPL_DM
or SPL_DM is enabled. So control the ram uclass build
based on TPL/SPL_DM.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 drivers/ram/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 5a39611349..83948e2c43 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -3,7 +3,7 @@
 # Copyright (c) 2015 Google, Inc
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
-obj-$(CONFIG_RAM) += ram-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)DM) += ram-uclass.o
 obj-$(CONFIG_MPC83XX_SDRAM) += mpc83xx_sdram.o
 obj-$(CONFIG_SANDBOX) += sandbox_ram.o
 obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/
-- 
2.25.1

[PATCH v4 02/25] ram: rockchip: Add common ddr type configs

[Jagan Teki]

From: Jagan Teki 

We have common ddr types in rockchip or in general. So use
the common ddr type names instead of per Rockchip SoC to
avoid confusion.

The respective ddr type names will use on the associated
ddr SoC driver as these drivers are built per SoC at a time.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none

 board/engicam/px30_core/Kconfig  |  2 +-
 configs/khadas-edge-captain-rk3399_defconfig |  2 +-
 configs/khadas-edge-rk3399_defconfig |  2 +-
 configs/khadas-edge-v-rk3399_defconfig   |  2 +-
 configs/leez-rk3399_defconfig|  2 +-
 configs/nanopi-r4s-rk3399_defconfig  |  2 +-
 configs/pinebook-pro-rk3399_defconfig|  2 +-
 configs/roc-pc-mezzanine-rk3399_defconfig|  2 +-
 configs/roc-pc-rk3399_defconfig  |  2 +-
 configs/rock-pi-4-rk3399_defconfig   |  2 +-
 configs/rock-pi-4c-rk3399_defconfig  |  2 +-
 configs/rockpro64-rk3399_defconfig   |  2 +-
 drivers/ram/rockchip/Kconfig | 32 +---
 drivers/ram/rockchip/sdram_px30.c|  6 ++--
 drivers/ram/rockchip/sdram_rk3399.c  |  7 ++---
 15 files changed, 33 insertions(+), 36 deletions(-)

diff --git a/board/engicam/px30_core/Kconfig b/board/engicam/px30_core/Kconfig
index a03be78369..924c30f3e1 100644
--- a/board/engicam/px30_core/Kconfig
+++ b/board/engicam/px30_core/Kconfig
@@ -11,6 +11,6 @@ config SYS_CONFIG_NAME
 
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
-   select RAM_PX30_DDR4 
+   select RAM_ROCKCHIP_DDR4
 
 endif
diff --git a/configs/khadas-edge-captain-rk3399_defconfig 
b/configs/khadas-edge-captain-rk3399_defconfig
index dff0522308..4c70909434 100644
--- a/configs/khadas-edge-captain-rk3399_defconfig
+++ b/configs/khadas-edge-captain-rk3399_defconfig
@@ -53,7 +53,7 @@ CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_RAM_ROCKCHIP_LPDDR4=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
diff --git a/configs/khadas-edge-rk3399_defconfig 
b/configs/khadas-edge-rk3399_defconfig
index 5a8b69c0f9..eba93ec6a2 100644
--- a/configs/khadas-edge-rk3399_defconfig
+++ b/configs/khadas-edge-rk3399_defconfig
@@ -52,7 +52,7 @@ CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_RAM_ROCKCHIP_LPDDR4=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
diff --git a/configs/khadas-edge-v-rk3399_defconfig 
b/configs/khadas-edge-v-rk3399_defconfig
index f54a610a27..5e622e166d 100644
--- a/configs/khadas-edge-v-rk3399_defconfig
+++ b/configs/khadas-edge-v-rk3399_defconfig
@@ -53,7 +53,7 @@ CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_RAM_ROCKCHIP_LPDDR4=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig
index a8326f03a2..f996c84a66 100644
--- a/configs/leez-rk3399_defconfig
+++ b/configs/leez-rk3399_defconfig
@@ -48,7 +48,7 @@ CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_RAM_ROCKCHIP_LPDDR4=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
diff --git a/configs/nanopi-r4s-rk3399_defconfig 
b/configs/nanopi-r4s-rk3399_defconfig
index 2185f87d7d..27233c0a18 100644
--- a/configs/nanopi-r4s-rk3399_defconfig
+++ b/configs/nanopi-r4s-rk3399_defconfig
@@ -49,7 +49,7 @@ CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_RAM_ROCKCHIP_LPDDR4=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
diff --git a/configs/pinebook-pro-rk3399_defconfig 
b/configs/pinebook-pro-rk3399_defconfig
index 528b7bb69f..7d4570b3df 100644
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig
@@ -74,7 +74,7 @@ CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_RAM_ROCKCHIP_LPDDR4=y
 CONFIG_DM_RESET=y
 CONFIG_DM_RNG=y
 CONFIG_RNG_ROCKCHIP=y
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig 
b/configs/roc-pc-mezzanine-rk3399_defconfig
index 3cdcc729f8..6fca5f5a3d 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -67,7 +67,7 @@ CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 # CONFIG_RAM_ROCKCHIP_DEBUG is not set
-CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_RAM_ROCKCHIP_LPDDR4=y
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index e03442afa4..f59f36076e 100644
--- 

[PATCH v4 00/25] ARM: Add Rockchip RV1126 support

[Jagan Teki]

RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.

This patch series add basic core support for Rockchip RV1126
and boot from eMMC and SD.

Tested RV1126 in Edgeble Neural Compute Module 2.

Changes for v4:
- rebased linux merged patches
- updated changes based on master

Changes for v3:
- dropped px30 SPL size change patch
- rebased on linux-next
- collect Kever r-b

Any inputs?
Jagan.

Jagan Teki (25):
  ram: Mark ram-uclass depend on TPL_DM or SPL_DM
  ram: rockchip: Add common ddr type configs
  ram: rockchip: Compute ddr capacity based on grf split
  ram: rockchip: Update ddr pctl regs for px30
  ram: rockchip: Add rv1126 ddr3 support
  ram: rockchip: Add rv1126 ddr loader params
  ram: rockchip: Add rv1126 ddr driver support
  ram: rockchip: rv1126: Control ddr init prints via DEBUG
  ram: rockchip: Add rv1126 lpddr4 support
  pinctrl: rockchip: Add pinctrl route types
  pinctrl: rockchip: Add rv1126 support
  arch: rockchip: Add cru header for rv1126
  dt-bindings: clk: Add dt-binding header for RV1126
  clk: rockchip: Add rv1126 clk support
  dt-bindings: power: Add power-domain header for rv1126
  arm: rockchip: Add grf header for rv1126
  ARM: dts: rockchip: Add Rockchip RV1126 pinctrl
  ARM: dts: rockchip: Add Rockchip RV1126 SoC
  arm: rockchip: Add RV1126 arch core support
  arm: rockchip: rv1126: Set dram area unsecure for SPL
  rockchip: mkimage: Add rv1126 support
  ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2)
  ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IO
  ARM: dts: rockchip: Add rv1126-u-boot.dtsi
  board: rockchip: Add Edgeble Neu2 IO Board

 arch/arm/dts/Makefile |3 +
 .../dts/rv1126-edgeble-neu2-io-u-boot.dtsi|   10 +
 arch/arm/dts/rv1126-edgeble-neu2-io.dts   |   42 +
 arch/arm/dts/rv1126-edgeble-neu2.dtsi |  338 ++
 arch/arm/dts/rv1126-pinctrl.dtsi  |  211 +
 arch/arm/dts/rv1126-u-boot.dtsi   |   62 +
 arch/arm/dts/rv1126.dtsi  |  438 ++
 .../include/asm/arch-rockchip/cru_rv1126.h|  459 +++
 .../asm/arch-rockchip/dram_spec_timing.h  |  452 +++
 .../include/asm/arch-rockchip/grf_rv1126.h|  251 ++
 .../include/asm/arch-rockchip/sdram_common.h  |  214 +-
 .../include/asm/arch-rockchip/sdram_msch.h|   12 +
 .../asm/arch-rockchip/sdram_pctl_px30.h   |  100 +-
 .../asm/arch-rockchip/sdram_phy_rv1126.h  |   93 +
 .../include/asm/arch-rockchip/sdram_rv1126.h  |  420 ++
 arch/arm/include/asm/arch-rv1126/boot0.h  |   11 +
 arch/arm/include/asm/arch-rv1126/gpio.h   |   11 +
 arch/arm/mach-rockchip/Kconfig|   46 +
 arch/arm/mach-rockchip/Makefile   |1 +
 arch/arm/mach-rockchip/rv1126/Kconfig |   59 +
 arch/arm/mach-rockchip/rv1126/Makefile|   13 +
 arch/arm/mach-rockchip/rv1126/clk_rv1126.c|   33 +
 arch/arm/mach-rockchip/rv1126/rv1126.c|   75 +
 arch/arm/mach-rockchip/rv1126/syscon_rv1126.c |   47 +
 board/edgeble/neural-compute-module-2/Kconfig |   16 +
 .../neural-compute-module-2/MAINTAINERS   |6 +
 .../edgeble/neural-compute-module-2/Makefile  |7 +
 board/edgeble/neural-compute-module-2/neu2.c  |4 +
 board/engicam/px30_core/Kconfig   |2 +-
 common/spl/Kconfig.tpl|2 +-
 configs/khadas-edge-captain-rk3399_defconfig  |2 +-
 configs/khadas-edge-rk3399_defconfig  |2 +-
 configs/khadas-edge-v-rk3399_defconfig|2 +-
 configs/leez-rk3399_defconfig |2 +-
 configs/nanopi-r4s-rk3399_defconfig   |2 +-
 configs/neu2-io-rv1126_defconfig  |   57 +
 configs/pinebook-pro-rk3399_defconfig |2 +-
 configs/roc-pc-mezzanine-rk3399_defconfig |2 +-
 configs/roc-pc-rk3399_defconfig   |2 +-
 configs/rock-pi-4-rk3399_defconfig|2 +-
 configs/rock-pi-4c-rk3399_defconfig   |2 +-
 configs/rockpro64-rk3399_defconfig|2 +-
 doc/board/rockchip/rockchip.rst   |3 +
 drivers/clk/rockchip/Makefile |1 +
 drivers/clk/rockchip/clk_rv1126.c | 1889 +
 drivers/pinctrl/rockchip/Makefile |1 +
 drivers/pinctrl/rockchip/pinctrl-px30.c   |   11 +-
 drivers/pinctrl/rockchip/pinctrl-rk3128.c |   11 +-
 drivers/pinctrl/rockchip/pinctrl-rk322x.c |   11 +-
 drivers/pinctrl/rockchip/pinctrl-rk3288.c |   11 +-
 drivers/pinctrl/rockchip/pinctrl-rk3308.c |   11 +-
 drivers/pinctrl/rockchip/pinctrl-rk3328.c |   11 +-
 drivers/pinctrl/rockchip/pinctrl-rk3399.c |   11 +-
 .../pinctrl/rockchip/pinctrl-rockchip-core.c  |   45 +-
 drivers/pinctrl/rockchip/pinctrl-rockchip.h   |   58 +-
 drivers/pinctrl/rockchip/pinctrl-rv1126.c |  416 ++
 drivers/ram/Makefile  |2 +-
 drivers/ram/rockchip/Kconfig  |   32 +-
 

Re: [PATCH v2 1/3] spl: Kconfig: Fix SPL_OPTEE_IMAGE dependency

[Jagan Teki]

On Thu, 3 Nov 2022 at 11:50, Jagan Teki  wrote:
>
> fdt_addr will build as part of SPL_LOAD_FIT or SPL_LOAD_FIT_FULL
> which is indeed required to build optee image support in SPL.
>
> common/spl/spl.c: In function ‘jump_to_image_optee’:
> common/spl/spl.c:220:46: error: ‘struct spl_image_info’ has no member named 
> ‘fdt_addr’
>   220 | spl_optee_entry(NULL, NULL, spl_image->fdt_addr,
>
> Fix the dependency support.
>
> Signed-off-by: Jagan Teki 
> ---

Tom, please apply this fix.

Jagan.

Re: [PATCH v2 1/4] ARM: stm32: Fix ECDSA authentication with Dcache enabled

[Marek Vasut]

On 12/12/22 10:40, Patrick DELAUNAY wrote:

Hi,


Hello Patrick

[...]


Hmmm, what does the BootROM use CRYP for then ?



used for SSP = Secure Secret Provisioning

https://wiki.st.com/stm32mpu/wiki/Secure_Secret_Provisioning_(SSP)


Oh, only this part, I see.

It is necessary to have MP15xC/F for the authenticated boot to work, 
but it seems the only difference there is the presence of CRYP. Or is 
there some BootROM fuse too ?



Yes,  the secure boot feature availability is indicated in the security 
field of the chip part number, for STM32MP13 and STM32MP15.


- SSP is not supported

- the associated authentication feature for secure boot is deactivated 
in ROM code



=> the key is burned/locked in OTP on these chips

       and checked by ROM code before to authenticate the FSBL


Thank you for the clarification, this is really useful.

Re: [PATCH v2 2/2] drivers: spi: sh_qspi.c: Use log_warning() instead of printf()

[Jagan Teki]

On Fri, Dec 9, 2022 at 8:34 AM Pengfei Fan
 wrote:
>
> Use log_warning() instead of printf() to print out driver information
>
> Signed-off-by: Pengfei Fan 
> Reviewed-by: Simon Glass 
> ---

Applied both to u-boot-spi/master

Re: [PATCH] spi: Add Socionext F_OSPI SPI flash controller driver

[Jagan Teki]

On Tue, Nov 29, 2022 at 7:47 AM Kunihiko Hayashi
 wrote:
>
> Introduce Socionext F_OSPI controller driver. This controller is used to
> communicate with slave devices such as SPI flash memories. It supports
> 4 slave devices and up to 8-bit wide bus, but supports master mode only.
>
> This driver uses spi-mem framework for SPI flash memory access, and
> can only operate indirect access mode and single data rate mode.
>
> Signed-off-by: Kunihiko Hayashi 
> ---

Applied to u-boot-spi/master

[PATCH 2/2] env: add failing trace in env_erase

[Patrick Delaunay]

Add trace in env save to indicate any errors to end user and avoid
silent output when the command 'env erase' is not executed as it is
done in env_save with commit 8968288cb477 ("env: add failing trace in
env_save")

Signed-off-by: Patrick Delaunay 
Signed-off-by: Patrick Delaunay 
---

 env/env.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/env/env.c b/env/env.c
index 69848fb06080..06078c7f3744 100644
--- a/env/env.c
+++ b/env/env.c
@@ -311,11 +311,15 @@ int env_erase(void)
if (drv) {
int ret;
 
-   if (!drv->erase)
+   if (!drv->erase) {
+   printf("not possible\n");
return -ENODEV;
+   }
 
-   if (!env_has_inited(drv->location))
+   if (!env_has_inited(drv->location)) {
+   printf("not initialized\n");
return -ENODEV;
+   }
 
printf("Erasing Environment on %s... ", drv->name);
ret = drv->erase();
-- 
2.25.1

[PATCH 1/2] env: ubi: add support of command env erase

[Patrick Delaunay]

Add support of opts erase for ubi env backend, this opts is used by
command 'env erase'.

This command only zero-fill the env UBI volume CONFIG_ENV_UBI_VOLUME
and CONFIG_ENV_UBI_VOLUME_REDUND, so the saved environment becomes
invalid.

This patch introduces a local define ENV_UBI_VOLUME_REDUND
only to avoid #if in the code, as CONFIG_ENV_UBI_VOLUME_REDUND
is only defined when CONFIG_SYS_REDUNDAND_ENVIRONMENT is defined.

Signed-off-by: Patrick Delaunay 
---

 env/ubi.c | 40 
 1 file changed, 40 insertions(+)

diff --git a/env/ubi.c b/env/ubi.c
index eb21c4f38b49..445d34fedb89 100644
--- a/env/ubi.c
+++ b/env/ubi.c
@@ -28,6 +28,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define ENV_UBI_VOLUME_REDUND CONFIG_ENV_UBI_VOLUME_REDUND
+#else
+#define ENV_UBI_VOLUME_REDUND "invalid"
+#endif
+
 #ifdef CONFIG_CMD_SAVEENV
 #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
 static int env_ubi_save(void)
@@ -177,9 +183,43 @@ static int env_ubi_load(void)
 }
 #endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */
 
+static int env_ubi_erase(void)
+{
+   ALLOC_CACHE_ALIGN_BUFFER(char, env_buf, CONFIG_ENV_SIZE);
+   int ret = 0;
+
+   if (ubi_part(CONFIG_ENV_UBI_PART, UBI_VID_OFFSET)) {
+   printf("\n** Cannot find mtd partition \"%s\"\n",
+  CONFIG_ENV_UBI_PART);
+   return 1;
+   }
+
+   memset(env_buf, 0x0, CONFIG_ENV_SIZE);
+
+   if (ubi_volume_write(CONFIG_ENV_UBI_VOLUME,
+(void *)env_buf, CONFIG_ENV_SIZE)) {
+   printf("\n** Unable to erase env to %s:%s **\n",
+  CONFIG_ENV_UBI_PART,
+  CONFIG_ENV_UBI_VOLUME);
+   ret = 1;
+   }
+   if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) {
+   if (ubi_volume_write(ENV_UBI_VOLUME_REDUND,
+(void *)env_buf, CONFIG_ENV_SIZE)) {
+   printf("\n** Unable to erase env to %s:%s **\n",
+  CONFIG_ENV_UBI_PART,
+  ENV_UBI_VOLUME_REDUND);
+   ret = 1;
+   }
+   }
+
+   return ret;
+}
+
 U_BOOT_ENV_LOCATION(ubi) = {
.location   = ENVL_UBI,
ENV_NAME("UBI")
.load   = env_ubi_load,
.save   = env_save_ptr(env_ubi_save),
+   .erase  = ENV_ERASE_PTR(env_ubi_erase),
 };
-- 
2.25.1

Re: [PATCH] add xt25f32b, which is soldered down to Rock Pi 4b

[Jagan Teki]

Please submit the patch using git send-email.

Re: [PATCH] mtd: spi-nor-ids: Add identity for GigaDevice GD25LQ128E

[Jagan Teki]

On Thu, Nov 10, 2022 at 4:44 PM Peter Robinson  wrote:
>
> Add the Gigadevice GD25LQ128E identifers so it can be properly
> used.
>
> Datasheet: https://www.gigadevice.com/datasheet/gd25lq128e/
>
> Signed-off-by: Peter Robinson 
> ---
>  drivers/mtd/spi/spi-nor-ids.c | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 4fe8b0d92c4..d9dea7463f0 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -123,6 +123,11 @@ const struct flash_info spi_nor_ids[] = {
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> },
> +   {
> +   INFO("gd25lq128e", 0x257018, 0, 64 * 1024, 256,

Seems like part id is wrong, Page 20 shows 0xc86018.

Jagan.

Re: [PATCH v2] cmd: pxe_utils: Limit fdtcontroladdr usage to non-fitImage

[Marek Vasut]

On 12/14/22 16:23, Quentin Schulz wrote:

Hi Marek,


Hi,


On 12/14/22 07:45, Marek Vasut wrote:

Commit d5ba6188dfb ("cmd: pxe_utils: Check fdtcontroladdr in label_boot")
forces '$fdtcontroladdr' DT address as a third parameter of bootm command
even if the PXE transfer pulls in a fitImage which contains configuration
node with its own DT that is preferrable to be passed to Linux. Limit the
$fdtcontroladdr fallback utilization to non-fitImages, since it is highly
likely a fitImage would come with its own DT, while single-file images do
need a separate DT.



Reviewed-by: Quentin Schulz 
Tested-by: Quentin Schulz 

Tested on top of an almost vanilla v2022.10 on Ringneck PX30, the FDT 
from the selected fitimage configuration (via #conf in kernel field in 
extlinux.conf) is taken into account.


Not sure overriding the DT gotten from the fit image wasn't a use-case 
Peter wanted to support though.


I am hoping to get feedback from Peter, but that kind of behavior would 
be rather odd. If user wants to use fdtcontroladdr DT, then just don't 
add DT fdt property into the configuration node entry in the fitImage.

[PATCH 3/3] ARM: dts: stm32: Add timer interrupts on stm32mp15

[Patrick Delaunay]

The timer units in the stm32mp15x CPUs have interrupts, depending on the
timer flavour either one "global" or four dedicated ones. Add the irqs
to the timer units on stm32mp15x.

Sync the DT Files with linux kernel v6.1 and with commit a9b70102253ce
("ARM: dts: stm32: Add timer interrupts on stm32mp15")

Signed-off-by: Patrick Delaunay 
---

 arch/arm/dts/stm32mp151.dtsi | 34 ++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index f0fb022fc63e..27ea6a3d3d14 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -145,6 +145,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4000 0x400>;
+   interrupts = ;
+   interrupt-names = "global";
clocks = < TIM2_K>;
clock-names = "int";
dmas = < 18 0x400 0x1>,
@@ -178,6 +180,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
+   interrupts = ;
+   interrupt-names = "global";
clocks = < TIM3_K>;
clock-names = "int";
dmas = < 23 0x400 0x1>,
@@ -212,6 +216,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
+   interrupts = ;
+   interrupt-names = "global";
clocks = < TIM4_K>;
clock-names = "int";
dmas = < 29 0x400 0x1>,
@@ -244,6 +250,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40003000 0x400>;
+   interrupts = ;
+   interrupt-names = "global";
clocks = < TIM5_K>;
clock-names = "int";
dmas = < 55 0x400 0x1>,
@@ -278,6 +286,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40004000 0x400>;
+   interrupts = ;
+   interrupt-names = "global";
clocks = < TIM6_K>;
clock-names = "int";
dmas = < 69 0x400 0x1>;
@@ -296,6 +306,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40005000 0x400>;
+   interrupts = ;
+   interrupt-names = "global";
clocks = < TIM7_K>;
clock-names = "int";
dmas = < 70 0x400 0x1>;
@@ -314,6 +326,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40006000 0x400>;
+   interrupts = ;
+   interrupt-names = "global";
clocks = < TIM12_K>;
clock-names = "int";
status = "disabled";
@@ -336,6 +350,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40007000 0x400>;
+   interrupts = ;
+   interrupt-names = "global";
clocks = < TIM13_K>;
clock-names = "int";
status = "disabled";
@@ -358,6 +374,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40008000 0x400>;
+   interrupts = ;
+   interrupt-names = "global";
clocks = < TIM14_K>;
clock-names = "int";
status = "disabled";
@@ -641,6 +659,11 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4400 0x400>;
+   interrupts = ,
+,
+,
+;
+   interrupt-names = "brk", "up", "trg-com", "cc";
clocks = < TIM1_K>;
clock-names = "int";
dmas = < 11 0x400 0x1>,
@@ -677,6 +700,11 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x44001000 0x400>;
+   interrupts = ,
+,
+

[PATCH 2/3] ARM: dts: stm32mp15: fix typo in stm32mp15xx-dkx.dtsi

[Patrick Delaunay]

Remove unnecessary space in device tree stm32mp15xx-dkx.dtsi.

Signed-off-by: Patrick Delaunay 
---

 arch/arm/dts/stm32mp15xx-dkx.dtsi | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi 
b/arch/arm/dts/stm32mp15xx-dkx.dtsi
index 5a045d7156be..34af90195d12 100644
--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
@@ -390,21 +390,21 @@
regulator-always-on;
};
 
-bst_out: boost {
+   bst_out: boost {
regulator-name = "bst_out";
interrupts = ;
-};
+   };
 
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = ;
-};
+   };
 
-vbus_sw: pwr_sw2 {
+   vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = ;
regulator-active-discharge = <1>;
-};
+   };
};
 
onkey {
-- 
2.25.1

[PATCH 1/3] ARM: dts: stm32mp15: remove clksrc include in SCMI dtsi file

[Patrick Delaunay]

The include file stm32mp1-clksrc.h is not necessary for the SCMI STM32MP15
dtsi files as the clock tree is not defined in the U-Boot SCMI device tree;
these SCMI device tree only support TFABOOT with stm32mp15_defconfig,
SPL with the basic boot defconfig is not supported.

Signed-off-by: Patrick Delaunay 
---

 arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi | 1 -
 arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi | 1 -
 2 files changed, 2 deletions(-)

diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi 
b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
index 1209dfe009c9..92fdf0987200 100644
--- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
@@ -3,7 +3,6 @@
  * Copyright : STMicroelectronics 2022
  */
 
-#include 
 #include "stm32mp15-scmi-u-boot.dtsi"
 
 / {
diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi 
b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
index c265745ff107..63948ef4930e 100644
--- a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
@@ -3,7 +3,6 @@
  * Copyright : STMicroelectronics 2022
  */
 
-#include 
 #include "stm32mp15-scmi-u-boot.dtsi"
 
 / {
-- 
2.25.1

Re: [PATCH v2] cmd: pxe_utils: Limit fdtcontroladdr usage to non-fitImage

[Quentin Schulz]

Hi Marek,

On 12/14/22 07:45, Marek Vasut wrote:

Commit d5ba6188dfb ("cmd: pxe_utils: Check fdtcontroladdr in label_boot")
forces '$fdtcontroladdr' DT address as a third parameter of bootm command
even if the PXE transfer pulls in a fitImage which contains configuration
node with its own DT that is preferrable to be passed to Linux. Limit the
$fdtcontroladdr fallback utilization to non-fitImages, since it is highly
likely a fitImage would come with its own DT, while single-file images do
need a separate DT.



Reviewed-by: Quentin Schulz 
Tested-by: Quentin Schulz 

Tested on top of an almost vanilla v2022.10 on Ringneck PX30, the FDT 
from the selected fitimage configuration (via #conf in kernel field in 
extlinux.conf) is taken into account.


Not sure overriding the DT gotten from the fit image wasn't a use-case 
Peter wanted to support though.


Cheers,
Quentin


Fixes: d5ba6188dfb ("cmd: pxe_utils: Check fdtcontroladdr in label_boot")
Signed-off-by: Marek Vasut 
---
Cc: Peter Hoyes 
Cc: Ramon Fried 
Cc: Simon Glass 
---
V1: Map the kernel buffer before testing image type
V2: Update code comment to reflect the change
---
  boot/pxe_utils.c | 9 +
  1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c
index 8133006875f..099aa2f4bc7 100644
--- a/boot/pxe_utils.c
+++ b/boot/pxe_utils.c
@@ -617,7 +617,7 @@ static int label_boot(struct pxe_context *ctx, struct 
pxe_label *label)
 * bootm, and adjust argc appropriately.
 *
 * Scenario 3: If there is an fdtcontroladdr specified, pass it along to
-* bootm, and adjust argc appropriately.
+* bootm, and adjust argc appropriately, unless the image type is 
fitImage.
 *
 * Scenario 4: fdt blob is not available.
 */
@@ -724,7 +724,10 @@ static int label_boot(struct pxe_context *ctx, struct 
pxe_label *label)
if (!bootm_argv[3])
bootm_argv[3] = env_get("fdt_addr");
  
-	if (!bootm_argv[3])

+   kernel_addr_r = genimg_get_kernel_addr(kernel_addr);
+   buf = map_sysmem(kernel_addr_r, 0);
+
+   if (!bootm_argv[3] && genimg_get_format(buf) != IMAGE_FORMAT_FIT)
bootm_argv[3] = env_get("fdtcontroladdr");
  
  	if (bootm_argv[3]) {

@@ -733,8 +736,6 @@ static int label_boot(struct pxe_context *ctx, struct 
pxe_label *label)
bootm_argc = 4;
}
  
-	kernel_addr_r = genimg_get_kernel_addr(kernel_addr);

-   buf = map_sysmem(kernel_addr_r, 0);
/* Try bootm for legacy and FIT format image */
if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID &&
  IS_ENABLED(CONFIG_CMD_BOOTM))

Re: [PATCH v2 1/3] asm/arch-meson: add missing meson_sm_write_efuse signature

[Neil Armstrong]

On 14/12/2022 05:39, Simon Glass wrote:

Hi Alexey,

On Tue, 13 Dec 2022 at 10:32, Alexey Romanov  wrote:


This function can be used by other modules.

Signed-off-by: Alexey Romanov 
---
  arch/arm/include/asm/arch-meson/sm.h | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-meson/sm.h 
b/arch/arm/include/asm/arch-meson/sm.h
index f3ae46a6d6b..b68edf842e4 100644
--- a/arch/arm/include/asm/arch-meson/sm.h
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -8,6 +8,8 @@

  ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);

+ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer, size_t size);
+
  #define SM_SERIAL_SIZE 12

  int meson_sm_get_serial(void *buffer, size_t size);
--
2.25.1



Should add function comments.

Also, you might consider adding a uclass for this. It seems like an
important use case that is not handled right now.


An NVMEM uclass would be a great addition, but for the scope of this
change it can be done later.

Neil



Regards,
Simon


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Re: [PATCH v2 2/3] arm/mach-meson: move smc commands in cmd/meson

[Neil Armstrong]

On 14/12/2022 11:33, Mattijs Korpershoek wrote:

On Tue, Dec 13, 2022 at 21:31, Alexey Romanov  wrote:


It is incorrect to keep commands in the arch/ folder.

Signed-off-by: Alexey Romanov 
---
  MAINTAINERS  |   1 +
  arch/arm/mach-meson/sm.c | 144 
  cmd/Kconfig  |   7 ++
  cmd/Makefile |   3 +
  cmd/meson/Makefile   |   5 ++
  cmd/meson/sm.c   | 154 +++
  6 files changed, 170 insertions(+), 144 deletions(-)
  create mode 100644 cmd/meson/Makefile
  create mode 100644 cmd/meson/sm.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 7f27ff4c20f..7a5460d4922 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -149,6 +149,7 @@ L:  u-boot-amlo...@groups.io
  T:git https://source.denx.de/u-boot/custodians/u-boot-amlogic.git
  F:arch/arm/mach-meson/
  F:arch/arm/include/asm/arch-meson/
+F: cmd/meson/
  F:drivers/clk/meson/
  F:drivers/serial/serial_meson.c
  F:drivers/reset/reset-meson.c
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index d6eb910689f..f2ca7e76932 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -6,8 +6,6 @@
   */
  
  #include 

-#include 
-#include 
  #include 
  #include 
  #include 
@@ -139,145 +137,3 @@ int meson_sm_get_reboot_reason(void)
/* The SMC call is not used, we directly use AO_SEC_SD_CFG15 */
return FIELD_GET(REBOOT_REASON_MASK, reason);
  }
-
-static int do_sm_serial(struct cmd_tbl *cmdtp, int flag, int argc,
-   char *const argv[])
-{
-   ulong address;
-   int ret;
-
-   if (argc < 2)
-   return CMD_RET_USAGE;
-
-   address = simple_strtoul(argv[1], NULL, 0);
-
-   ret = meson_sm_get_serial((void *)address, SM_CHIP_ID_SIZE);
-   if (ret)
-   return CMD_RET_FAILURE;
-
-   return CMD_RET_SUCCESS;
-}
-
-#define MAX_REBOOT_REASONS 14
-
-static const char *reboot_reasons[MAX_REBOOT_REASONS] = {
-   [REBOOT_REASON_COLD] = "cold_boot",
-   [REBOOT_REASON_NORMAL] = "normal",
-   [REBOOT_REASON_RECOVERY] = "recovery",
-   [REBOOT_REASON_UPDATE] = "update",
-   [REBOOT_REASON_FASTBOOT] = "fastboot",
-   [REBOOT_REASON_SUSPEND_OFF] = "suspend_off",
-   [REBOOT_REASON_HIBERNATE] = "hibernate",
-   [REBOOT_REASON_BOOTLOADER] = "bootloader",
-   [REBOOT_REASON_SHUTDOWN_REBOOT] = "shutdown_reboot",
-   [REBOOT_REASON_RPMBP] = "rpmbp",
-   [REBOOT_REASON_CRASH_DUMP] = "crash_dump",
-   [REBOOT_REASON_KERNEL_PANIC] = "kernel_panic",
-   [REBOOT_REASON_WATCHDOG_REBOOT] = "watchdog_reboot",
-};
-
-static int do_sm_reboot_reason(struct cmd_tbl *cmdtp, int flag, int argc,
-  char *const argv[])
-{
-   const char *reason_str;
-   char *destarg = NULL;
-   int reason;
-
-   if (argc > 1)
-   destarg = argv[1];
-
-   reason = meson_sm_get_reboot_reason();
-   if (reason < 0)
-   return CMD_RET_FAILURE;
-
-   if (reason >= MAX_REBOOT_REASONS ||
-   !reboot_reasons[reason])
-   reason_str = "unknown";
-   else
-   reason_str = reboot_reasons[reason];
-
-   if (destarg)
-   env_set(destarg, reason_str);
-   else
-   printf("reboot reason: %s (%x)\n", reason_str, reason);
-
-   return CMD_RET_SUCCESS;
-}
-
-static int do_efuse_read(struct cmd_tbl *cmdtp, int flag, int argc,
-   char *const argv[])
-{
-   ulong address, offset, size;
-   int ret;
-
-   if (argc < 4)
-   return CMD_RET_USAGE;
-
-offset = simple_strtoul(argv[1], NULL, 0);
-size = simple_strtoul(argv[2], NULL, 0);
-
-address = simple_strtoul(argv[3], NULL, 0);
-
-   ret = meson_sm_read_efuse(offset, (void *)address, size);
-   if (ret != size)
-   return CMD_RET_FAILURE;
-
-   return CMD_RET_SUCCESS;
-}
-
-static int do_efuse_write(struct cmd_tbl *cmdtp, int flag, int argc,
-   char *const argv[])
-{
-   ulong address, offset, size;
-   int ret;
-
-   if (argc < 4)
-   return CMD_RET_USAGE;
-
-offset = simple_strtoul(argv[1], NULL, 0);
-size = simple_strtoul(argv[2], NULL, 0);
-
-address = simple_strtoul(argv[3], NULL, 0);
-
-   ret = meson_sm_write_efuse(offset, (void *)address, size);
-   if (ret != size)
-   return CMD_RET_FAILURE;
-
-   return CMD_RET_SUCCESS;
-}
-
-static struct cmd_tbl cmd_sm_sub[] = {
-   U_BOOT_CMD_MKENT(serial, 2, 1, do_sm_serial, "", ""),
-   U_BOOT_CMD_MKENT(reboot_reason, 1, 1, do_sm_reboot_reason, "", ""),
-   U_BOOT_CMD_MKENT(efuseread, 4, 1, do_efuse_read, "", ""),
-   U_BOOT_CMD_MKENT(efusewrite, 4, 0, do_efuse_write, "", ""),
-};
-
-static int do_sm(struct cmd_tbl *cmdtp, int flag, int argc,
-char *const argv[])
-{
-   struct 

Re: [PATCH 0/2] mach-meson: port dwc2_otg usage to CONFIG_DM_USB_GADGET=y

[neil . armstrong]

Hi,

On 14/12/2022 15:45, Mattijs Korpershoek wrote:

Hi Neil,






I'll run some tests on other G12 boards but so far this looks very good, thanks 
!


I got my hands on an odroid-c4 board and I also tested:
=> fastboot usb 0
=> # hit Ctrl-c
# disconnection is ok

And tested "usb start" and could list a usb thumb drive.

Any other tests you would like me to do?


No it's enough, thx for testing on the C4, this test the Device/Host
switch is still working !

Marek, can you take the whole patchset with my Acked-by or should I take it ?

Neil





Neil



---
Mattijs Korpershoek (2):
usb: dwc3-meson-g12a: force mode on child add/removal
ARM: meson: g12a: switch dwc2 otg to DM

   arch/arm/mach-meson/board-g12a.c  | 127 
--
   configs/bananapi-m5_defconfig |   1 +
   configs/beelink-gsking-x_defconfig|   1 +
   configs/beelink-gtking_defconfig  |   1 +
   configs/beelink-gtkingpro_defconfig   |   1 +
   configs/khadas-vim3_android_ab_defconfig  |   1 +
   configs/khadas-vim3_android_defconfig |   1 +
   configs/khadas-vim3_defconfig |   1 +
   configs/khadas-vim3l_android_ab_defconfig |   1 +
   configs/khadas-vim3l_android_defconfig|   1 +
   configs/khadas-vim3l_defconfig|   1 +
   configs/odroid-c4_defconfig   |   1 +
   configs/odroid-hc4_defconfig  |   1 +
   configs/odroid-n2_defconfig   |   1 +
   configs/radxa-zero_defconfig  |   1 +
   configs/sei510_defconfig  |   1 +
   configs/sei610_defconfig  |   1 +
   configs/u200_defconfig|   1 +
   drivers/usb/dwc3/dwc3-meson-g12a.c|  18 +
   19 files changed, 35 insertions(+), 127 deletions(-)
---
base-commit: 7b70f68977578360d9c47bb25d6d1937075153b4
change-id: 20221024-meson-dm-usb-60e413696519

Best regards,

Re: [PATCH 0/2] mach-meson: port dwc2_otg usage to CONFIG_DM_USB_GADGET=y

[Mattijs Korpershoek]

Hi Neil,

On Thu, Nov 24, 2022 at 10:34, Neil Armstrong  wrote:

> Hi Mattijs,
>
> On 23/11/2022 16:42, Mattijs Korpershoek wrote:
>> While working on some USB bugs on the VIM3L board, we stumbled upon the fact
>> that mach-meson still uses legacy board_usb_*() functions instead of using 
>> DM [1]
>> 
>> This series aim to switch the g12a based boards to use CONFIG_DM_USB_GADGET 
>> and
>> removes the board_usb_*() logic.
>> 
>> * The first patch adds mode switching in the dwc3-meson-g12a glue driver 
>> whenever
>>the dwc2 otg driver is probed()/removed().
>> 
>> * The second patch enables the config option and cleans up all board_usb_*().
>> 
>> This has been mainly tested with khadas-vim3l_android_defconfig using 
>> fastboot:
>> 
>> => fastboot usb 0
>> 
>> => # hit Ctrl-c
>> 
>> Other tests:
>> * ums 0 mmc 2 # can list / mount partitions from host
>> * usb start; usb storage # list usb thumb drive
>> * all defconfigs have been build tested
>> 
>> [1] 
>> https://lore.kernel.org/u-boot/938b9439-9014-5ee8-1627-16af508bf...@linaro.org/
>> Signed-off-by: Mattijs Korpershoek 
>
> I'll run some tests on other G12 boards but so far this looks very good, 
> thanks !

I got my hands on an odroid-c4 board and I also tested:
=> fastboot usb 0
=> # hit Ctrl-c
# disconnection is ok

And tested "usb start" and could list a usb thumb drive.

Any other tests you would like me to do?

>
> Neil
>
>> 
>> ---
>> Mattijs Korpershoek (2):
>>usb: dwc3-meson-g12a: force mode on child add/removal
>>ARM: meson: g12a: switch dwc2 otg to DM
>> 
>>   arch/arm/mach-meson/board-g12a.c  | 127 
>> --
>>   configs/bananapi-m5_defconfig |   1 +
>>   configs/beelink-gsking-x_defconfig|   1 +
>>   configs/beelink-gtking_defconfig  |   1 +
>>   configs/beelink-gtkingpro_defconfig   |   1 +
>>   configs/khadas-vim3_android_ab_defconfig  |   1 +
>>   configs/khadas-vim3_android_defconfig |   1 +
>>   configs/khadas-vim3_defconfig |   1 +
>>   configs/khadas-vim3l_android_ab_defconfig |   1 +
>>   configs/khadas-vim3l_android_defconfig|   1 +
>>   configs/khadas-vim3l_defconfig|   1 +
>>   configs/odroid-c4_defconfig   |   1 +
>>   configs/odroid-hc4_defconfig  |   1 +
>>   configs/odroid-n2_defconfig   |   1 +
>>   configs/radxa-zero_defconfig  |   1 +
>>   configs/sei510_defconfig  |   1 +
>>   configs/sei610_defconfig  |   1 +
>>   configs/u200_defconfig|   1 +
>>   drivers/usb/dwc3/dwc3-meson-g12a.c|  18 +
>>   19 files changed, 35 insertions(+), 127 deletions(-)
>> ---
>> base-commit: 7b70f68977578360d9c47bb25d6d1937075153b4
>> change-id: 20221024-meson-dm-usb-60e413696519
>> 
>> Best regards,

Re: [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR

[Andre Przywara]

On Wed, 14 Dec 2022 02:37:12 -0600
Samuel Holland  wrote:

Hi Samuel,

many thanks for having a look!

> On 12/5/22 18:45, Andre Przywara wrote:
> > The CONFIG_SATAPWR Kconfig symbol was used to point to a GPIO that
> > enables the power for a SATA harddisk.
> > In the DT this is described with the target-supply property in the AHCI
> > DT node, pointing to a (GPIO controlled) regulator. Since we need SATA
> > only in U-Boot proper, and use a DM driver for AHCI there, we should use
> > the DT instead of hardcoding this.
> > 
> > Add code to the sunxi AHCI driver to check the DT for that regulator and
> > enable it, at probe time. Then drop the current code from board.c, which
> > was doing that job before.
> > This allows us to remove the SATAPWR Kconfig definition and the
> > respective values from the defconfigs.
> > We also select the generic fixed regulator driver, which handles those
> > GPIO controlled regulators.
> > 
> > Signed-off-by: Andre Przywara 
> > ---
> >  arch/arm/Kconfig |  2 ++
> >  arch/arm/mach-sunxi/Kconfig  |  8 
> >  board/sunxi/board.c  | 14 --
> >  configs/A10-OLinuXino-Lime_defconfig |  1 -
> >  configs/A20-OLinuXino-Lime2-eMMC_defconfig   |  1 -
> >  configs/A20-OLinuXino-Lime2_defconfig|  1 -
> >  configs/A20-OLinuXino-Lime_defconfig |  1 -
> >  configs/A20-OLinuXino_MICRO-eMMC_defconfig   |  1 -
> >  configs/A20-OLinuXino_MICRO_defconfig|  1 -
> >  configs/A20-Olimex-SOM-EVB_defconfig |  1 -
> >  configs/A20-Olimex-SOM204-EVB-eMMC_defconfig |  1 -
> >  configs/A20-Olimex-SOM204-EVB_defconfig  |  1 -
> >  configs/Cubieboard2_defconfig|  1 -
> >  configs/Cubieboard_defconfig |  1 -
> >  configs/Cubietruck_defconfig |  1 -
> >  configs/Itead_Ibox_A20_defconfig |  1 -
> >  configs/Lamobo_R1_defconfig  |  1 -
> >  configs/Linksprite_pcDuino3_Nano_defconfig   |  1 -
> >  configs/Linksprite_pcDuino3_defconfig|  1 -
> >  configs/Sinovoip_BPI_M3_defconfig|  1 -
> >  configs/orangepi_plus_defconfig  |  1 -
> >  drivers/ata/ahci_sunxi.c |  9 +
> >  22 files changed, 11 insertions(+), 40 deletions(-)
> > 
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index f95ed71b246..3623520b353 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1148,6 +1148,8 @@ config ARCH_SUNXI
> > select DM_SPI_FLASH if SPI
> > select DM_KEYBOARD
> > select DM_MMC if MMC
> > +   select DM_REGULATOR
> > +   select DM_REGULATOR_FIXED  
> 
> While not all boards have fixed regulators, so many do that I am happy
> to have this driver enabled by default. However, I recommend "imply"
> over "select" so the regulator uclass can be disabled if
> USB/SATA/Ethernet/whatever are not being used. You also need to
> select/imply POWER, as it is a dependency.

Yes, that's indeed better.

> > select DM_SCSI if SCSI
> > select DM_SERIAL
> > select GPIO_EXTRA_HEADER
> > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> > index dbe6005daab..5f95fe72d08 100644
> > --- a/arch/arm/mach-sunxi/Kconfig
> > +++ b/arch/arm/mach-sunxi/Kconfig
> > @@ -985,14 +985,6 @@ config VIDEO_LCD_TL059WV5C0
> >  
> >  endchoice
> >  
> > -config SATAPWR
> > -   string "SATA power pin"
> > -   default ""
> > -   help
> > - Set the pins used to power the SATA. This takes a string in the
> > - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
> > - port H.
> > -
> >  config GMAC_TX_DELAY
> > int "GMAC Transmit Clock Delay Chain"
> > default 0
> > diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> > index 21a2407e062..ec35a7f06bd 100644
> > --- a/board/sunxi/board.c
> > +++ b/board/sunxi/board.c
> > @@ -229,20 +229,6 @@ int board_init(void)
> > return ret;
> >  
> > /* strcmp() would look better, but doesn't get optimised away. */
> > -   if (CONFIG_SATAPWR[0]) {
> > -   satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
> > -   if (satapwr_pin >= 0) {
> > -   gpio_request(satapwr_pin, "satapwr");
> > -   gpio_direction_output(satapwr_pin, 1);
> > -
> > -   /*
> > -* Give the attached SATA device time to power-up
> > -* to avoid link timeouts
> > -*/
> > -   mdelay(500);
> > -   }
> > -   }
> > -
> > if (CONFIG_MACPWR[0]) {
> > macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
> > if (macpwr_pin >= 0) {
> > diff --git a/configs/A10-OLinuXino-Lime_defconfig 
> > b/configs/A10-OLinuXino-Lime_defconfig
> > index ee92ac45fbc..f5d98607003 100644
> > --- a/configs/A10-OLinuXino-Lime_defconfig
> > +++ b/configs/A10-OLinuXino-Lime_defconfig
> > @@ -8,7 +8,6 @@ CONFIG_DRAM_EMR1=4
> >  

Re: [RFC PATCH 02/17] sunxi: remove CONFIG_MACPWR

[Andre Przywara]

On Wed, 14 Dec 2022 03:09:22 -0600
Samuel Holland  wrote:

Hi Samuel,

> Thanks for this cleanup! With the two issues below addressed, it looks
> good to me.

many thanks for having such a thorough look!

> On 12/5/22 18:45, Andre Przywara wrote:
> > The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables
> > the power for the Ethernet "MAC" (mostly PHY, really).
> > In the DT this is described with the phy-supply property in the MAC DT
> > node, pointing to a (GPIO controlled) regulator. Since we need Ethernet
> > only in U-Boot proper, and use a DM driver there, we should use the DT
> > instead of hardcoding this.
> > 
> > Add code to the sun8i_emac and sunxi_emac drivers to check the DT for
> > that regulator and enable it, at probe time. Then drop the current code
> > from board.c, which was doing that job before.
> > This allows us to remove the MACPWR Kconfig definition and the respective
> > values from the defconfigs.  
> 
> ... and we don't care about sun7i-gmac here because there's no U-Boot
> driver for it, and the Linux driver already uses the devicetree.

If you mean the Gigabit MAC on the A20 (allwinner,sun7i-a20-gmac), that's
implemented in drivers/net/designware.c. And this code already parses
phy-supply. I think I tried it on my BananaPi, but can double check.

> 
> > Signed-off-by: Andre Przywara 
> > ---
> >  arch/arm/mach-sunxi/Kconfig   |  7 ---
> >  board/sunxi/board.c   | 10 --
> >  configs/Bananapi_M2_Ultra_defconfig   |  1 -
> >  configs/Bananapi_defconfig|  1 -
> >  configs/Bananapro_defconfig   |  1 -
> >  configs/Lamobo_R1_defconfig   |  1 -
> >  configs/Mele_A1000_defconfig  |  1 -
> >  configs/Orangepi_defconfig|  1 -
> >  configs/Orangepi_mini_defconfig   |  1 -
> >  configs/bananapi_m1_plus_defconfig|  1 -
> >  configs/bananapi_m2_plus_h3_defconfig |  1 -
> >  configs/bananapi_m2_plus_h5_defconfig |  1 -
> >  configs/i12-tvbox_defconfig   |  1 -
> >  configs/jesurun_q5_defconfig  |  1 -
> >  configs/mixtile_loftq_defconfig   |  1 -
> >  configs/nanopi_m1_plus_defconfig  |  1 -
> >  configs/nanopi_neo_plus2_defconfig|  1 -
> >  configs/nanopi_r1s_h5_defconfig   |  1 -
> >  configs/orangepi_pc2_defconfig|  1 -
> >  configs/orangepi_plus2e_defconfig |  1 -
> >  configs/orangepi_plus_defconfig   |  1 -
> >  configs/orangepi_win_defconfig|  1 -
> >  configs/pine_h64_defconfig|  1 -
> >  configs/zeropi_defconfig  |  1 -
> >  drivers/net/sun8i_emac.c  |  9 +++--
> >  drivers/net/sunxi_emac.c  | 10 --
> >  26 files changed, 15 insertions(+), 43 deletions(-)
> > 
> > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> > index 5f95fe72d08..6220175d612 100644
> > --- a/arch/arm/mach-sunxi/Kconfig
> > +++ b/arch/arm/mach-sunxi/Kconfig
> > @@ -645,13 +645,6 @@ config OLD_SUNXI_KERNEL_COMPAT
> > Set this to enable various workarounds for old kernels, this results in
> > sub-optimal settings for newer kernels, only enable if needed.
> >  
> > -config MACPWR
> > -   string "MAC power pin"
> > -   default ""
> > -   help
> > - Set the pin used to power the MAC. This takes a string in the format
> > - understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
> > -
> >  config MMC0_CD_PIN
> > string "Card detect pin for mmc0"
> > default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
> > diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> > index ec35a7f06bd..3077cc71ebd 100644
> > --- a/board/sunxi/board.c
> > +++ b/board/sunxi/board.c
> > @@ -228,15 +228,6 @@ int board_init(void)
> > if (ret)
> > return ret;
> >  
> > -   /* strcmp() would look better, but doesn't get optimised away. */
> > -   if (CONFIG_MACPWR[0]) {
> > -   macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
> > -   if (macpwr_pin >= 0) {
> > -   gpio_request(macpwr_pin, "macpwr");
> > -   gpio_direction_output(macpwr_pin, 1);
> > -   }
> > -   }
> > -
> >  #if CONFIG_IS_ENABLED(DM_I2C)
> > /*
> >  * Temporary workaround for enabling I2C clocks until proper sunxi DM
> > @@ -244,7 +235,6 @@ int board_init(void)
> >  */
> > i2c_init_board();
> >  #endif
> > -
> > eth_init_board();
> >  
> > return 0;
> > diff --git a/configs/Bananapi_M2_Ultra_defconfig 
> > b/configs/Bananapi_M2_Ultra_defconfig
> > index 0bd163afdd7..1c4b90ab9d2 100644
> > --- a/configs/Bananapi_M2_Ultra_defconfig
> > +++ b/configs/Bananapi_M2_Ultra_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN8I_R40=y
> >  CONFIG_DRAM_CLK=576
> > -CONFIG_MACPWR="PA17"  
> 
> This GPIO is actually the PHY reset line, not its power supply. Since
> that line has a pull up, I don't think this was necessary to begin 

Re: [PATCH 0/3] Add support for USB onboard HUB, used on stm32 boards

[Michal Simek]

On 12/12/22 14:19, Marek Vasut wrote:
CAUTION: This message has originated from an External Source. Please use proper 
judgment and caution when opening attachments, clicking links, or responding to 
this email.



On 12/12/22 11:44, Fabrice Gasnier wrote:

This series adds a driver to support USB onboard HUB, inspired by Linux
onboard hub driver.

Purpose is to manage the power supply regulator on STM32 boards, for
low power use case in Linux. U-boot driver allows to benefit of the
device tree part to supply the HUB when need, instead using an
always-on regulator.

It aligns the relevant DT part from emerging Linux v6.2. It also adds the
relevant default configuration on stm32mp15.


Not sure why v6.2 is relevant. That changes in connection to usb hubs/companion 
hubs/peer hubs have been merged some time ago.


It would be lovely to see also peer hubs part in u-boot too but nothing wrong 
with this part.


Acked-by: Michal Simek 

Thanks,
Michal

Re: [PATCH v2 0/3] arch-meson: introduce efusedump command

[Alexey Romanov]

Hello!

On Tue, Dec 13, 2022 at 08:39:43PM -0800, Simon Glass wrote:
> Hi Alexey,
> 
> On Tue, 13 Dec 2022 at 10:31, Alexey Romanov  wrote:
> >
> > Keeping the commands code in an arch/ is not correct. This patchset
> > moves the meson smc commands from arch/arm/mach-meson to cmd/meson
> > folder and also adds a new 'efusedump' command with which user can
> > print efuse memory.
> >
> > Alexey Romanov (3):
> >   asm/arch-meson: add missing meson_sm_write_efuse signature
> >   arm/mach-meson: move smc commands in cmd/meson
> >   cmd/arm: meson: sm: introduce efusedump command
> >
> >  MAINTAINERS  |   1 +
> >  arch/arm/include/asm/arch-meson/sm.h |   2 +
> >  arch/arm/mach-meson/sm.c | 144 -
> >  cmd/Kconfig  |   7 +
> >  cmd/Makefile |   3 +
> >  cmd/meson/Makefile   |   5 +
> >  cmd/meson/sm.c   | 187 +++
> >  7 files changed, 205 insertions(+), 144 deletions(-)
> >  create mode 100644 cmd/meson/Makefile
> >  create mode 100644 cmd/meson/sm.c
> >
> > --
> > 2.25.1
> >
> 
> It might be a good time to add some documentation in doc/usage/cmd/meson ?
> 
> Regards,
> Simon

Yeah, I'll add docs in v3 patchest.

-- 
Thank you,
Alexey

Re: [PATCH v2 1/3] asm/arch-meson: add missing meson_sm_write_efuse signature

[Alexey Romanov]

Hello!

On Tue, Dec 13, 2022 at 08:39:46PM -0800, Simon Glass wrote:
> Hi Alexey,
> 
> On Tue, 13 Dec 2022 at 10:32, Alexey Romanov  wrote:
> >
> > This function can be used by other modules.
> >
> > Signed-off-by: Alexey Romanov 
> > ---
> >  arch/arm/include/asm/arch-meson/sm.h | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm/include/asm/arch-meson/sm.h 
> > b/arch/arm/include/asm/arch-meson/sm.h
> > index f3ae46a6d6b..b68edf842e4 100644
> > --- a/arch/arm/include/asm/arch-meson/sm.h
> > +++ b/arch/arm/include/asm/arch-meson/sm.h
> > @@ -8,6 +8,8 @@
> >
> >  ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
> >
> > +ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer, size_t size);
> > +
> >  #define SM_SERIAL_SIZE 12
> >
> >  int meson_sm_get_serial(void *buffer, size_t size);
> > --
> > 2.25.1
> >
> 
> Should add function comments.
> 
> Also, you might consider adding a uclass for this. It seems like an
> important use case that is not handled right now.
> 
> Regards,
> Simon

I'm afraid we can't generalize sm API for each arch types. It's very close to 
Secure Monitor 
vendor implementation and can provide various APIs for different purposes.

-- 
Thank you,
Alexey

Re: [PATCH v2 2/3] arm/mach-meson: move smc commands in cmd/meson

[Alexey Romanov]

On Wed, Dec 14, 2022 at 11:33:35AM +0100, Mattijs Korpershoek wrote:
> On Tue, Dec 13, 2022 at 21:31, Alexey Romanov  
> wrote:
> 
> > It is incorrect to keep commands in the arch/ folder.
> >
> > Signed-off-by: Alexey Romanov 
> > ---
> >  MAINTAINERS  |   1 +
> >  arch/arm/mach-meson/sm.c | 144 
> >  cmd/Kconfig  |   7 ++
> >  cmd/Makefile |   3 +
> >  cmd/meson/Makefile   |   5 ++
> >  cmd/meson/sm.c   | 154 +++
> >  6 files changed, 170 insertions(+), 144 deletions(-)
> >  create mode 100644 cmd/meson/Makefile
> >  create mode 100644 cmd/meson/sm.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 7f27ff4c20f..7a5460d4922 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -149,6 +149,7 @@ L:  u-boot-amlo...@groups.io
> >  T: git https://source.denx.de/u-boot/custodians/u-boot-amlogic.git
> >  F: arch/arm/mach-meson/
> >  F: arch/arm/include/asm/arch-meson/
> > +F: cmd/meson/
> >  F: drivers/clk/meson/
> >  F: drivers/serial/serial_meson.c
> >  F: drivers/reset/reset-meson.c
> > diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
> > index d6eb910689f..f2ca7e76932 100644
> > --- a/arch/arm/mach-meson/sm.c
> > +++ b/arch/arm/mach-meson/sm.c
> > @@ -6,8 +6,6 @@
> >   */
> >  
> >  #include 
> > -#include 
> > -#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -139,145 +137,3 @@ int meson_sm_get_reboot_reason(void)
> > /* The SMC call is not used, we directly use AO_SEC_SD_CFG15 */
> > return FIELD_GET(REBOOT_REASON_MASK, reason);
> >  }
> > -
> > -static int do_sm_serial(struct cmd_tbl *cmdtp, int flag, int argc,
> > -   char *const argv[])
> > -{
> > -   ulong address;
> > -   int ret;
> > -
> > -   if (argc < 2)
> > -   return CMD_RET_USAGE;
> > -
> > -   address = simple_strtoul(argv[1], NULL, 0);
> > -
> > -   ret = meson_sm_get_serial((void *)address, SM_CHIP_ID_SIZE);
> > -   if (ret)
> > -   return CMD_RET_FAILURE;
> > -
> > -   return CMD_RET_SUCCESS;
> > -}
> > -
> > -#define MAX_REBOOT_REASONS 14
> > -
> > -static const char *reboot_reasons[MAX_REBOOT_REASONS] = {
> > -   [REBOOT_REASON_COLD] = "cold_boot",
> > -   [REBOOT_REASON_NORMAL] = "normal",
> > -   [REBOOT_REASON_RECOVERY] = "recovery",
> > -   [REBOOT_REASON_UPDATE] = "update",
> > -   [REBOOT_REASON_FASTBOOT] = "fastboot",
> > -   [REBOOT_REASON_SUSPEND_OFF] = "suspend_off",
> > -   [REBOOT_REASON_HIBERNATE] = "hibernate",
> > -   [REBOOT_REASON_BOOTLOADER] = "bootloader",
> > -   [REBOOT_REASON_SHUTDOWN_REBOOT] = "shutdown_reboot",
> > -   [REBOOT_REASON_RPMBP] = "rpmbp",
> > -   [REBOOT_REASON_CRASH_DUMP] = "crash_dump",
> > -   [REBOOT_REASON_KERNEL_PANIC] = "kernel_panic",
> > -   [REBOOT_REASON_WATCHDOG_REBOOT] = "watchdog_reboot",
> > -};
> > -
> > -static int do_sm_reboot_reason(struct cmd_tbl *cmdtp, int flag, int argc,
> > -  char *const argv[])
> > -{
> > -   const char *reason_str;
> > -   char *destarg = NULL;
> > -   int reason;
> > -
> > -   if (argc > 1)
> > -   destarg = argv[1];
> > -
> > -   reason = meson_sm_get_reboot_reason();
> > -   if (reason < 0)
> > -   return CMD_RET_FAILURE;
> > -
> > -   if (reason >= MAX_REBOOT_REASONS ||
> > -   !reboot_reasons[reason])
> > -   reason_str = "unknown";
> > -   else
> > -   reason_str = reboot_reasons[reason];
> > -
> > -   if (destarg)
> > -   env_set(destarg, reason_str);
> > -   else
> > -   printf("reboot reason: %s (%x)\n", reason_str, reason);
> > -
> > -   return CMD_RET_SUCCESS;
> > -}
> > -
> > -static int do_efuse_read(struct cmd_tbl *cmdtp, int flag, int argc,
> > -   char *const argv[])
> > -{
> > -   ulong address, offset, size;
> > -   int ret;
> > -
> > -   if (argc < 4)
> > -   return CMD_RET_USAGE;
> > -
> > -offset = simple_strtoul(argv[1], NULL, 0);
> > -size = simple_strtoul(argv[2], NULL, 0);
> > -
> > -address = simple_strtoul(argv[3], NULL, 0);
> > -
> > -   ret = meson_sm_read_efuse(offset, (void *)address, size);
> > -   if (ret != size)
> > -   return CMD_RET_FAILURE;
> > -
> > -   return CMD_RET_SUCCESS;
> > -}
> > -
> > -static int do_efuse_write(struct cmd_tbl *cmdtp, int flag, int argc,
> > -   char *const argv[])
> > -{
> > -   ulong address, offset, size;
> > -   int ret;
> > -
> > -   if (argc < 4)
> > -   return CMD_RET_USAGE;
> > -
> > -offset = simple_strtoul(argv[1], NULL, 0);
> > -size = simple_strtoul(argv[2], NULL, 0);
> > -
> > -address = simple_strtoul(argv[3], NULL, 0);
> > -
> > -   ret = meson_sm_write_efuse(offset, (void *)address, size);
> > -   if (ret != size)
> > -   return CMD_RET_FAILURE;
> > -
> > -   return CMD_RET_SUCCESS;
> > -}
> > -
> > -static struct cmd_tbl cmd_sm_sub[] = {
> > -   U_BOOT_CMD_MKENT(serial, 2, 1, do_sm_serial, "", 

Re: cmd: exit: Exit functionality broken

[Max van den Biggelaar]

Hi Hector and Marek,

Thanks for your reply. I am glad that there is already a thread open for this 
problem. As reverting the commit seems to be the best way to resolve this 
problem, we will take the same approach in our forked U-Boot mainline source 
code.

I am looking forward to the solution in mainline U-Boot. Thanks for your 
support.

Met vriendelijke groet / Kind regards,

Max van den Biggelaar
Designer

Mobile  +31 62 57 28 396
Phone   +31 40 26 76 200
Address Science Park Eindhoven 5501
5692 EM SON, The Netherlands

www.prodrive-technologies.com

Disclaimer: The content of this e-mail is intended solely for the use of the 
Individual or entity to whom it is addressed. If you have received this 
communication in error, be aware that forwarding it, copying it, or in any way 
disclosing its content to any other person, is strictly prohibited. If you have 
received this communication in error, please notify the author by replying to 
this e-mail immediately.

From: Marek Vasut 
Sent: Tuesday, December 13, 2022 5:06 PM
To: Hector Palacios ; Max van den Biggelaar 
; u-boot@lists.denx.de 

Cc: Martijn de Gouw 
Subject: Re: cmd: exit: Exit functionality broken

On 12/13/22 16:41, Hector Palacios wrote:
> Hi Max,
>
> On 12/13/22 13:24, Max van den Biggelaar wrote:
>> Hi,
>>
>> I have a question regarding the U-Boot exit command. We are currently
>> using mainline U-Boot 2022.04 version to provide our embedded systems
>> with a bootloader image. To start our firmware via U-Boot environment,
>> we use a bootscript to start our firmware. However, when we tried to
>> exit a bootscript with the exit command, the bootscript was never exited.
>>
>> After debugging to investigate the problem, we found this commit
>> (https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fu-boot%2Fu-boot%2Fcommit%2F8c4e3b79bd0bb76eea16869e9666e19047c0d005data=05%7C01%7Cmax.van.den.biggelaar%40prodrive-technologies.com%7Cdc9f555b4f9047280cb508dadd23f512%7C612607c95af74e7f8976faf1ae77be60%7C0%7C0%7C638065443753164173%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=nhHtOiLzPhWV0VXIQhXS5mvefORmuierzfOV%2B69o10A%3Dreserved=0)
>>  in mainline U-Boot:
>> cmd: exit: Fix return value
>>
>>
>> In case exit is called in a script without parameter, the command
>> returns -2 ; in case exit is called with a numerical parameter,
>> the command returns -2 and lower. This leads to the following problem:
>> => setenv foo 'echo bar ; exit 1' ; run foo ; echo $?
>> bar
>> 0
>> => setenv foo 'echo bar ; exit 0' ; run foo ; echo $?
>> bar
>> 0
>> => setenv foo 'echo bar ; exit -2' ; run foo ; echo $?
>> bar
>> 0
>> That is, no matter what the 'exit' command argument is, the return
>> value is always 0 and so it is not possible to use script return
>> value in subsequent tests.
>>
>> Fix this and simplify the exit command such that if exit is called with
>> no argument, the command returns 0, just like 'true' in cmd/test.c. In
>> case the command is called with any argument that is positive integer,
>> the argument is set as return value.
>> => setenv foo 'echo bar ; exit 1' ; run foo ; echo $?
>> bar
>> 1
>> => setenv foo 'echo bar ; exit 0' ; run foo ; echo $?
>> bar
>> 0
>> => setenv foo 'echo bar ; exit -2' ; run foo ; echo $?
>> bar
>> 0
>>
>> Note that this does change ABI established in 2004 , although it is
>> unclear whether that ABI was originally OK or not.
>>
>> Fixes:
>> c26e454
>> Signed-off-by: Marek Vasut 
>> Cc: Pantelis Antoniou 
>> Cc: Tom Rini 
>>
>> This commit does solve the problem of returning the correct value
>> given to the exit command, but this breaks the following source code
>> in common/cli_hush.c:
>> https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fu-boot%2Fu-boot%2Fblob%2Fmaster%2Fcommon%2Fcli_hush.c%23L3207data=05%7C01%7Cmax.van.den.biggelaar%40prodrive-technologies.com%7Cdc9f555b4f9047280cb508dadd23f512%7C612607c95af74e7f8976faf1ae77be60%7C0%7C0%7C638065443753164173%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=iZMaTL7J477g9JKwiI0%2BmLurEmNzcl4rhTEoF0WPlNs%3Dreserved=0
>>
>> In the previous versions of U-Boot, such as 2020.04, the exit command
>> returned -2, which was expected of the exit command API. However,
>> after the patch above to fix the return value, -2 was never returned

Re: [PATCH v2 2/3] arm/mach-meson: move smc commands in cmd/meson

[Mattijs Korpershoek]

On Tue, Dec 13, 2022 at 21:31, Alexey Romanov  wrote:

> It is incorrect to keep commands in the arch/ folder.
>
> Signed-off-by: Alexey Romanov 
> ---
>  MAINTAINERS  |   1 +
>  arch/arm/mach-meson/sm.c | 144 
>  cmd/Kconfig  |   7 ++
>  cmd/Makefile |   3 +
>  cmd/meson/Makefile   |   5 ++
>  cmd/meson/sm.c   | 154 +++
>  6 files changed, 170 insertions(+), 144 deletions(-)
>  create mode 100644 cmd/meson/Makefile
>  create mode 100644 cmd/meson/sm.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7f27ff4c20f..7a5460d4922 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -149,6 +149,7 @@ L:u-boot-amlo...@groups.io
>  T:   git https://source.denx.de/u-boot/custodians/u-boot-amlogic.git
>  F:   arch/arm/mach-meson/
>  F:   arch/arm/include/asm/arch-meson/
> +F:   cmd/meson/
>  F:   drivers/clk/meson/
>  F:   drivers/serial/serial_meson.c
>  F:   drivers/reset/reset-meson.c
> diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
> index d6eb910689f..f2ca7e76932 100644
> --- a/arch/arm/mach-meson/sm.c
> +++ b/arch/arm/mach-meson/sm.c
> @@ -6,8 +6,6 @@
>   */
>  
>  #include 
> -#include 
> -#include 
>  #include 
>  #include 
>  #include 
> @@ -139,145 +137,3 @@ int meson_sm_get_reboot_reason(void)
>   /* The SMC call is not used, we directly use AO_SEC_SD_CFG15 */
>   return FIELD_GET(REBOOT_REASON_MASK, reason);
>  }
> -
> -static int do_sm_serial(struct cmd_tbl *cmdtp, int flag, int argc,
> - char *const argv[])
> -{
> - ulong address;
> - int ret;
> -
> - if (argc < 2)
> - return CMD_RET_USAGE;
> -
> - address = simple_strtoul(argv[1], NULL, 0);
> -
> - ret = meson_sm_get_serial((void *)address, SM_CHIP_ID_SIZE);
> - if (ret)
> - return CMD_RET_FAILURE;
> -
> - return CMD_RET_SUCCESS;
> -}
> -
> -#define MAX_REBOOT_REASONS 14
> -
> -static const char *reboot_reasons[MAX_REBOOT_REASONS] = {
> - [REBOOT_REASON_COLD] = "cold_boot",
> - [REBOOT_REASON_NORMAL] = "normal",
> - [REBOOT_REASON_RECOVERY] = "recovery",
> - [REBOOT_REASON_UPDATE] = "update",
> - [REBOOT_REASON_FASTBOOT] = "fastboot",
> - [REBOOT_REASON_SUSPEND_OFF] = "suspend_off",
> - [REBOOT_REASON_HIBERNATE] = "hibernate",
> - [REBOOT_REASON_BOOTLOADER] = "bootloader",
> - [REBOOT_REASON_SHUTDOWN_REBOOT] = "shutdown_reboot",
> - [REBOOT_REASON_RPMBP] = "rpmbp",
> - [REBOOT_REASON_CRASH_DUMP] = "crash_dump",
> - [REBOOT_REASON_KERNEL_PANIC] = "kernel_panic",
> - [REBOOT_REASON_WATCHDOG_REBOOT] = "watchdog_reboot",
> -};
> -
> -static int do_sm_reboot_reason(struct cmd_tbl *cmdtp, int flag, int argc,
> -char *const argv[])
> -{
> - const char *reason_str;
> - char *destarg = NULL;
> - int reason;
> -
> - if (argc > 1)
> - destarg = argv[1];
> -
> - reason = meson_sm_get_reboot_reason();
> - if (reason < 0)
> - return CMD_RET_FAILURE;
> -
> - if (reason >= MAX_REBOOT_REASONS ||
> - !reboot_reasons[reason])
> - reason_str = "unknown";
> - else
> - reason_str = reboot_reasons[reason];
> -
> - if (destarg)
> - env_set(destarg, reason_str);
> - else
> - printf("reboot reason: %s (%x)\n", reason_str, reason);
> -
> - return CMD_RET_SUCCESS;
> -}
> -
> -static int do_efuse_read(struct cmd_tbl *cmdtp, int flag, int argc,
> - char *const argv[])
> -{
> - ulong address, offset, size;
> - int ret;
> -
> - if (argc < 4)
> - return CMD_RET_USAGE;
> -
> -offset = simple_strtoul(argv[1], NULL, 0);
> -size = simple_strtoul(argv[2], NULL, 0);
> -
> -address = simple_strtoul(argv[3], NULL, 0);
> -
> - ret = meson_sm_read_efuse(offset, (void *)address, size);
> - if (ret != size)
> - return CMD_RET_FAILURE;
> -
> - return CMD_RET_SUCCESS;
> -}
> -
> -static int do_efuse_write(struct cmd_tbl *cmdtp, int flag, int argc,
> - char *const argv[])
> -{
> - ulong address, offset, size;
> - int ret;
> -
> - if (argc < 4)
> - return CMD_RET_USAGE;
> -
> -offset = simple_strtoul(argv[1], NULL, 0);
> -size = simple_strtoul(argv[2], NULL, 0);
> -
> -address = simple_strtoul(argv[3], NULL, 0);
> -
> - ret = meson_sm_write_efuse(offset, (void *)address, size);
> - if (ret != size)
> - return CMD_RET_FAILURE;
> -
> - return CMD_RET_SUCCESS;
> -}
> -
> -static struct cmd_tbl cmd_sm_sub[] = {
> - U_BOOT_CMD_MKENT(serial, 2, 1, do_sm_serial, "", ""),
> - U_BOOT_CMD_MKENT(reboot_reason, 1, 1, do_sm_reboot_reason, "", ""),
> - U_BOOT_CMD_MKENT(efuseread, 4, 1, do_efuse_read, "", ""),
> - U_BOOT_CMD_MKENT(efusewrite, 4, 0, do_efuse_write, "", ""),
> -};
> -
> -static 

[PATCH] board/pg_wcom: rework defconfig

[Holger Brunck]

Switch off SCSI related config options to get rid of the board
removal warning. We don't use this interface. Also disable UBIFS
to decrease the image size, as this is also not used.

Signed-off-by: Holger Brunck 
---
 configs/pg_wcom_expu1_defconfig| 6 --
 configs/pg_wcom_expu1_update_defconfig | 6 --
 configs/pg_wcom_seli8_defconfig| 6 --
 configs/pg_wcom_seli8_update_defconfig | 6 --
 4 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig
index b57e588f4e..d6b62340a3 100644
--- a/configs/pg_wcom_expu1_defconfig
+++ b/configs/pg_wcom_expu1_defconfig
@@ -17,7 +17,6 @@ CONFIG_SYS_CLK_FREQ=
 # CONFIG_HAS_ARMV7_SECURE_BASE is not set
 CONFIG_SYS_LOAD_ADDR=0x8200
 CONFIG_ENV_ADDR=0x6006
-CONFIG_AHCI=y
 # CONFIG_DEEP_SLEEP is not set
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_KM_COMMON_ETH_INIT=y
@@ -62,6 +61,7 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=6000.nor,nand0=6800.flash"
 
CONFIG_MTDPARTS_DEFAULT="mtdparts=6000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);6800.flash:-(ubi1)"
 CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1"
 CONFIG_ENV_OVERWRITE=y
@@ -71,6 +71,7 @@ CONFIG_ENV_ADDR_REDUND=0x6004
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="ethernet@2d9"
 CONFIG_VERSION_VARIABLE=y
+# CONFIG_SCSI_AHCI is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_DDR_CLK_FREQ=5000
@@ -96,8 +97,9 @@ CONFIG_PHY_GIGE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_QE_FW_ADDR=0x6002
-CONFIG_SCSI_AHCI_PLAT=y
+# CONFIG_SCSI is not set
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_POST=y
+CONFIG_LZO=y
diff --git a/configs/pg_wcom_expu1_update_defconfig 
b/configs/pg_wcom_expu1_update_defconfig
index 9029e7babc..933515bb7d 100644
--- a/configs/pg_wcom_expu1_update_defconfig
+++ b/configs/pg_wcom_expu1_update_defconfig
@@ -16,7 +16,6 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0x7020
 # CONFIG_HAS_ARMV7_SECURE_BASE is not set
 CONFIG_SYS_LOAD_ADDR=0x8200
 CONFIG_ENV_ADDR=0x6022
-CONFIG_AHCI=y
 # CONFIG_DEEP_SLEEP is not set
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_KM_COMMON_ETH_INIT=y
@@ -60,6 +59,7 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=6000.nor,nand0=6800.flash"
 
CONFIG_MTDPARTS_DEFAULT="mtdparts=6000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);6800.flash:-(ubi1)"
 CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1"
 CONFIG_ENV_OVERWRITE=y
@@ -69,6 +69,7 @@ CONFIG_ENV_ADDR_REDUND=0x6020
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="ethernet@2d9"
 CONFIG_VERSION_VARIABLE=y
+# CONFIG_SCSI_AHCI is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_DDR_CLK_FREQ=5000
@@ -94,8 +95,9 @@ CONFIG_PHY_GIGE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_QE_FW_ADDR=0x6002
-CONFIG_SCSI_AHCI_PLAT=y
+# CONFIG_SCSI is not set
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_POST=y
+CONFIG_LZO=y
diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig
index aa74e1746a..b58199d783 100644
--- a/configs/pg_wcom_seli8_defconfig
+++ b/configs/pg_wcom_seli8_defconfig
@@ -17,7 +17,6 @@ CONFIG_SYS_CLK_FREQ=
 # CONFIG_HAS_ARMV7_SECURE_BASE is not set
 CONFIG_SYS_LOAD_ADDR=0x8200
 CONFIG_ENV_ADDR=0x6006
-CONFIG_AHCI=y
 # CONFIG_DEEP_SLEEP is not set
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_KM_COMMON_ETH_INIT=y
@@ -62,6 +61,7 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=6000.nor,nand0=6800.flash"
 
CONFIG_MTDPARTS_DEFAULT="mtdparts=6000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);6800.flash:-(ubi1)"
 CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8"
 CONFIG_ENV_OVERWRITE=y
@@ -71,6 +71,7 @@ CONFIG_ENV_ADDR_REDUND=0x6004
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="ethernet@2d9"
 CONFIG_VERSION_VARIABLE=y
+# CONFIG_SCSI_AHCI is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_DDR_CLK_FREQ=5000
@@ -96,8 +97,9 @@ CONFIG_PHY_GIGE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_QE_FW_ADDR=0x6002
-CONFIG_SCSI_AHCI_PLAT=y
+# CONFIG_SCSI is not set
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_POST=y
+CONFIG_LZO=y
diff --git a/configs/pg_wcom_seli8_update_defconfig 
b/configs/pg_wcom_seli8_update_defconfig
index 2b18a88d44..385073336d 100644
--- a/configs/pg_wcom_seli8_update_defconfig
+++ b/configs/pg_wcom_seli8_update_defconfig
@@ -16,7 +16,6 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0x7020
 # CONFIG_HAS_ARMV7_SECURE_BASE is not set
 

Re: [PATCH v5 1/3] efi_loader: Add SPI I/O protocol support

[Paul Barker]

On 14/12/2022 04:39, Simon Glass wrote:
> Hi Paul,
> 
> On Wed, 23 Nov 2022 at 10:50, Paul Barker  wrote:
>>
>> This addition allows UEFI applications running under u-boot to access
>> peripherals on SPI busses. It is based on the UEFI Platform
>> Initialization (PI) Specification, Version 1.7 Errata A (April 2020).
>> Only the core functionality required to discover SPI peripherals and
>> communicate with them is currently implemented. Other functionality such
>> as the legacy SPI controller interface and the ability to update the SPI
>> peripheral object associated with a particular SPI I/O protocol object
>> is currently unimplemented.
>>
>> The following protocols are defined:
>> * EFI_SPI_CONFIGURATION_PROTOCOL
>> * EFI_SPI_IO_PROTOCOL
>> * EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
>>
>> Since there are no open source implementations of these protocols to use
>> as an example, educated guesses/hacks have been made in cases where the
>> UEFI PI specification is unclear and these are documented in comments.
>>
>> This implementation has been tested on the SanCloud BBE Lite and allowed
>> a UEFI test application to successfully communicate with a Micron
>> Authenta flash device connected via the SPI bus.
>>
>> Signed-off-by: Paul Barker 
>> ---
>>  MAINTAINERS   |   6 +
>>  configs/am335x_evm_defconfig  |   1 +
>>  include/efi_api.h |   4 +
>>  include/efi_loader.h  |   4 +
>>  include/efi_spi_protocol.h| 166 +
>>  lib/efi_loader/Kconfig|   8 +
>>  lib/efi_loader/Makefile   |   1 +
>>  lib/efi_loader/efi_setup.c|   6 +
>>  lib/efi_loader/efi_spi_protocol.c | 576 ++
>>  lib/uuid.c|   4 +
>>  10 files changed, 776 insertions(+)
>>  create mode 100644 include/efi_spi_protocol.h
>>  create mode 100644 lib/efi_loader/efi_spi_protocol.c
> 
> This should have a sandbox test as well. See test/dm/spi.c or sf.c for 
> examples.

Hi Simon,

There is a test case in patch 2 of this series, is that what you're
looking for? It was split out as requested in the review of v3 of this
series.

Thanks,

-- 
Paul Barker
Principal Software Engineer
SanCloud Ltd

e: paul.bar...@sancloud.com
w: https://sancloud.com/

Re: [PATCH 1/2] efi_loader: fix get_package_list_handle() status

[AKASHI Takahiro]

On Tue, Dec 13, 2022 at 10:39:09PM +0100, Vincent Stehl?? wrote:
> When the HII protocol function get_package_list_handle() is called with an
> invalid package list handle, it returns EFI_NOT_FOUND but this is not in
> its list of possible status codes as per the EFI specification.
> Return EFI_INVALID_PARAMETER instead to fix conformance.

Thank you for the heads-up.
You're right as far as the EFI specification is concerned.

FYI,
EDK-II also returns EFI_NOT_FOUND if the package list handle is *valid*
and yet we cannot find any matching handle in the HII database.
See
  MdeModulePkg/Universal/HiiDatabaseDxe/Database.c

-Takahiro Akashi

> Signed-off-by: Vincent Stehlé 
> Cc: Heinrich Schuchardt 
> Cc: Ilias Apalodimas 
> ---
>  lib/efi_loader/efi_hii.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/efi_loader/efi_hii.c b/lib/efi_loader/efi_hii.c
> index 75ff58aafa5..27db3be6a17 100644
> --- a/lib/efi_loader/efi_hii.c
> +++ b/lib/efi_loader/efi_hii.c
> @@ -780,7 +780,7 @@ get_package_list_handle(const struct 
> efi_hii_database_protocol *this,
>   }
>   }
>  
> - return EFI_EXIT(EFI_NOT_FOUND);
> + return EFI_EXIT(EFI_INVALID_PARAMETER);
>  }
>  
>  const struct efi_hii_database_protocol efi_hii_database = {
> -- 
> 2.35.1
> 

Re: [RFC PATCH 02/17] sunxi: remove CONFIG_MACPWR

[Samuel Holland]

Hi Andre,

Thanks for this cleanup! With the two issues below addressed, it looks
good to me.

On 12/5/22 18:45, Andre Przywara wrote:
> The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables
> the power for the Ethernet "MAC" (mostly PHY, really).
> In the DT this is described with the phy-supply property in the MAC DT
> node, pointing to a (GPIO controlled) regulator. Since we need Ethernet
> only in U-Boot proper, and use a DM driver there, we should use the DT
> instead of hardcoding this.
> 
> Add code to the sun8i_emac and sunxi_emac drivers to check the DT for
> that regulator and enable it, at probe time. Then drop the current code
> from board.c, which was doing that job before.
> This allows us to remove the MACPWR Kconfig definition and the respective
> values from the defconfigs.

... and we don't care about sun7i-gmac here because there's no U-Boot
driver for it, and the Linux driver already uses the devicetree.

> Signed-off-by: Andre Przywara 
> ---
>  arch/arm/mach-sunxi/Kconfig   |  7 ---
>  board/sunxi/board.c   | 10 --
>  configs/Bananapi_M2_Ultra_defconfig   |  1 -
>  configs/Bananapi_defconfig|  1 -
>  configs/Bananapro_defconfig   |  1 -
>  configs/Lamobo_R1_defconfig   |  1 -
>  configs/Mele_A1000_defconfig  |  1 -
>  configs/Orangepi_defconfig|  1 -
>  configs/Orangepi_mini_defconfig   |  1 -
>  configs/bananapi_m1_plus_defconfig|  1 -
>  configs/bananapi_m2_plus_h3_defconfig |  1 -
>  configs/bananapi_m2_plus_h5_defconfig |  1 -
>  configs/i12-tvbox_defconfig   |  1 -
>  configs/jesurun_q5_defconfig  |  1 -
>  configs/mixtile_loftq_defconfig   |  1 -
>  configs/nanopi_m1_plus_defconfig  |  1 -
>  configs/nanopi_neo_plus2_defconfig|  1 -
>  configs/nanopi_r1s_h5_defconfig   |  1 -
>  configs/orangepi_pc2_defconfig|  1 -
>  configs/orangepi_plus2e_defconfig |  1 -
>  configs/orangepi_plus_defconfig   |  1 -
>  configs/orangepi_win_defconfig|  1 -
>  configs/pine_h64_defconfig|  1 -
>  configs/zeropi_defconfig  |  1 -
>  drivers/net/sun8i_emac.c  |  9 +++--
>  drivers/net/sunxi_emac.c  | 10 --
>  26 files changed, 15 insertions(+), 43 deletions(-)
> 
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 5f95fe72d08..6220175d612 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -645,13 +645,6 @@ config OLD_SUNXI_KERNEL_COMPAT
>   Set this to enable various workarounds for old kernels, this results in
>   sub-optimal settings for newer kernels, only enable if needed.
>  
> -config MACPWR
> - string "MAC power pin"
> - default ""
> - help
> -   Set the pin used to power the MAC. This takes a string in the format
> -   understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
> -
>  config MMC0_CD_PIN
>   string "Card detect pin for mmc0"
>   default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index ec35a7f06bd..3077cc71ebd 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -228,15 +228,6 @@ int board_init(void)
>   if (ret)
>   return ret;
>  
> - /* strcmp() would look better, but doesn't get optimised away. */
> - if (CONFIG_MACPWR[0]) {
> - macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
> - if (macpwr_pin >= 0) {
> - gpio_request(macpwr_pin, "macpwr");
> - gpio_direction_output(macpwr_pin, 1);
> - }
> - }
> -
>  #if CONFIG_IS_ENABLED(DM_I2C)
>   /*
>* Temporary workaround for enabling I2C clocks until proper sunxi DM
> @@ -244,7 +235,6 @@ int board_init(void)
>*/
>   i2c_init_board();
>  #endif
> -
>   eth_init_board();
>  
>   return 0;
> diff --git a/configs/Bananapi_M2_Ultra_defconfig 
> b/configs/Bananapi_M2_Ultra_defconfig
> index 0bd163afdd7..1c4b90ab9d2 100644
> --- a/configs/Bananapi_M2_Ultra_defconfig
> +++ b/configs/Bananapi_M2_Ultra_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN8I_R40=y
>  CONFIG_DRAM_CLK=576
> -CONFIG_MACPWR="PA17"

This GPIO is actually the PHY reset line, not its power supply. Since
that line has a pull up, I don't think this was necessary to begin with.

>  CONFIG_MMC0_CD_PIN="PH13"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  CONFIG_USB1_VBUS_PIN="PH23"
> diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
> index 2814d77c187..2a590e141d9 100644
> --- a/configs/Bananapi_defconfig
> +++ b/configs/Bananapi_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=432
> -CONFIG_MACPWR="PH23"
>  CONFIG_VIDEO_COMPOSITE=y
>  CONFIG_GMAC_TX_DELAY=3
>  

Re: [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR

[Samuel Holland]

Hi Andre,

On 12/5/22 18:45, Andre Przywara wrote:
> The CONFIG_SATAPWR Kconfig symbol was used to point to a GPIO that
> enables the power for a SATA harddisk.
> In the DT this is described with the target-supply property in the AHCI
> DT node, pointing to a (GPIO controlled) regulator. Since we need SATA
> only in U-Boot proper, and use a DM driver for AHCI there, we should use
> the DT instead of hardcoding this.
> 
> Add code to the sunxi AHCI driver to check the DT for that regulator and
> enable it, at probe time. Then drop the current code from board.c, which
> was doing that job before.
> This allows us to remove the SATAPWR Kconfig definition and the
> respective values from the defconfigs.
> We also select the generic fixed regulator driver, which handles those
> GPIO controlled regulators.
> 
> Signed-off-by: Andre Przywara 
> ---
>  arch/arm/Kconfig |  2 ++
>  arch/arm/mach-sunxi/Kconfig  |  8 
>  board/sunxi/board.c  | 14 --
>  configs/A10-OLinuXino-Lime_defconfig |  1 -
>  configs/A20-OLinuXino-Lime2-eMMC_defconfig   |  1 -
>  configs/A20-OLinuXino-Lime2_defconfig|  1 -
>  configs/A20-OLinuXino-Lime_defconfig |  1 -
>  configs/A20-OLinuXino_MICRO-eMMC_defconfig   |  1 -
>  configs/A20-OLinuXino_MICRO_defconfig|  1 -
>  configs/A20-Olimex-SOM-EVB_defconfig |  1 -
>  configs/A20-Olimex-SOM204-EVB-eMMC_defconfig |  1 -
>  configs/A20-Olimex-SOM204-EVB_defconfig  |  1 -
>  configs/Cubieboard2_defconfig|  1 -
>  configs/Cubieboard_defconfig |  1 -
>  configs/Cubietruck_defconfig |  1 -
>  configs/Itead_Ibox_A20_defconfig |  1 -
>  configs/Lamobo_R1_defconfig  |  1 -
>  configs/Linksprite_pcDuino3_Nano_defconfig   |  1 -
>  configs/Linksprite_pcDuino3_defconfig|  1 -
>  configs/Sinovoip_BPI_M3_defconfig|  1 -
>  configs/orangepi_plus_defconfig  |  1 -
>  drivers/ata/ahci_sunxi.c |  9 +
>  22 files changed, 11 insertions(+), 40 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index f95ed71b246..3623520b353 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1148,6 +1148,8 @@ config ARCH_SUNXI
>   select DM_SPI_FLASH if SPI
>   select DM_KEYBOARD
>   select DM_MMC if MMC
> + select DM_REGULATOR
> + select DM_REGULATOR_FIXED

While not all boards have fixed regulators, so many do that I am happy
to have this driver enabled by default. However, I recommend "imply"
over "select" so the regulator uclass can be disabled if
USB/SATA/Ethernet/whatever are not being used. You also need to
select/imply POWER, as it is a dependency.

>   select DM_SCSI if SCSI
>   select DM_SERIAL
>   select GPIO_EXTRA_HEADER
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index dbe6005daab..5f95fe72d08 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -985,14 +985,6 @@ config VIDEO_LCD_TL059WV5C0
>  
>  endchoice
>  
> -config SATAPWR
> - string "SATA power pin"
> - default ""
> - help
> -   Set the pins used to power the SATA. This takes a string in the
> -   format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
> -   port H.
> -
>  config GMAC_TX_DELAY
>   int "GMAC Transmit Clock Delay Chain"
>   default 0
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 21a2407e062..ec35a7f06bd 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -229,20 +229,6 @@ int board_init(void)
>   return ret;
>  
>   /* strcmp() would look better, but doesn't get optimised away. */
> - if (CONFIG_SATAPWR[0]) {
> - satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
> - if (satapwr_pin >= 0) {
> - gpio_request(satapwr_pin, "satapwr");
> - gpio_direction_output(satapwr_pin, 1);
> -
> - /*
> -  * Give the attached SATA device time to power-up
> -  * to avoid link timeouts
> -  */
> - mdelay(500);
> - }
> - }
> -
>   if (CONFIG_MACPWR[0]) {
>   macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
>   if (macpwr_pin >= 0) {
> diff --git a/configs/A10-OLinuXino-Lime_defconfig 
> b/configs/A10-OLinuXino-Lime_defconfig
> index ee92ac45fbc..f5d98607003 100644
> --- a/configs/A10-OLinuXino-Lime_defconfig
> +++ b/configs/A10-OLinuXino-Lime_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DRAM_EMR1=4
>  CONFIG_SYS_CLK_FREQ=91200
>  CONFIG_MMC0_CD_PIN="PH1"
>  CONFIG_I2C1_ENABLE=y
> -CONFIG_SATAPWR="PC3"
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig 
> 

[PATCH 2/2] efi_selftest: add hii database protocol test case

[Vincent Stehlé]

Add a test for the case when the HII database protocol
get_package_list_handle() function is called with an invalid package list
handle.

Signed-off-by: Vincent Stehlé 
Cc: Heinrich Schuchardt 
Cc: Ilias Apalodimas 
---
 lib/efi_selftest/efi_selftest_hii.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/lib/efi_selftest/efi_selftest_hii.c 
b/lib/efi_selftest/efi_selftest_hii.c
index eaf3b0995d4..8a038d9f534 100644
--- a/lib/efi_selftest/efi_selftest_hii.c
+++ b/lib/efi_selftest/efi_selftest_hii.c
@@ -605,6 +605,16 @@ static int test_hii_database_get_package_list_handle(void)
goto out;
}
 
+   /* Invalid package list handle. */
+   driver_handle = NULL;
+   ret = hii_database_protocol->get_package_list_handle(
+   hii_database_protocol, NULL, _handle);
+   if (ret != EFI_INVALID_PARAMETER) {
+   efi_st_error("get_package_list_handle returned %u not 
invalid\n",
+(unsigned int)ret);
+   goto out;
+   }
+
result = EFI_ST_SUCCESS;
 
 out:
-- 
2.35.1

[PATCH 1/2] efi_loader: fix get_package_list_handle() status

[Vincent Stehlé]

When the HII protocol function get_package_list_handle() is called with an
invalid package list handle, it returns EFI_NOT_FOUND but this is not in
its list of possible status codes as per the EFI specification.
Return EFI_INVALID_PARAMETER instead to fix conformance.

Signed-off-by: Vincent Stehlé 
Cc: Heinrich Schuchardt 
Cc: Ilias Apalodimas 
---
 lib/efi_loader/efi_hii.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/efi_loader/efi_hii.c b/lib/efi_loader/efi_hii.c
index 75ff58aafa5..27db3be6a17 100644
--- a/lib/efi_loader/efi_hii.c
+++ b/lib/efi_loader/efi_hii.c
@@ -780,7 +780,7 @@ get_package_list_handle(const struct 
efi_hii_database_protocol *this,
}
}
 
-   return EFI_EXIT(EFI_NOT_FOUND);
+   return EFI_EXIT(EFI_INVALID_PARAMETER);
 }
 
 const struct efi_hii_database_protocol efi_hii_database = {
-- 
2.35.1

[PATCH 0/2] efi: small hii conformance fix

[Vincent Stehlé]

Hi,

The following couple of patches fixes a small UEFI HII conformance issue and
adds a selftest demonstrating the issue.
This is sent in this order to avoid breaking `bootefi selftest' in the middle
but feel free to apply in any order if preferred.

Best regards,
Vincent.


Vincent Stehlé (2):
  efi_loader: fix get_package_list_handle() status
  efi_selftest: add hii database protocol test case

 lib/efi_loader/efi_hii.c|  2 +-
 lib/efi_selftest/efi_selftest_hii.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)

-- 
2.35.1