Re: [PATCH] arm: kirkwood: Enable uart0 dm-pre-reloc for Pogoplug V4 board
Hi Michael, On 2/13/23 09:48, Michael Walle wrote: Am 2023-02-13 09:43, schrieb Stefan Roese: On 2/10/23 22:08, Tony Dinh wrote: When DM_SERIAL is enabled, the device-tree tag u-boot,dm-pre-reloc is required for this board to boot over UART with kwboot. Enable this in kirkwood-pogoplug-series-4-u-boot.dtsi. Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese If I understood it correctly, this is a workaround, right? Maybe we can include a link to the original discussion here for the case when someone stumbles over this commit: Link: https://lore.kernel.org/r/20230201080210.ypz4nrj4y2igwxz3@pali/ Correct, it's not fully understood, why this property is really needed. Some bug still might be hidden in the early DT console code. Still we want to move forward with this board, so this dm-pre-reloc property helps here. I'll add the link to the discussion to the commit text. Good idea. Thanks, Stefan
Re: [PATCH v2 2/2] i2c: i2c-cdns.c: Update driver to read fifo-depth from device tree
Hello Pei, On 13.02.23 09:02, Pei Yue Ho wrote: > Enable driver to fetch the optional parameter (fifo-depth) from device > tree. If the parameter is not found in the device tree, it will use > the default value declared in the driver. > > Signed-off-by: Pei Yue Ho > Reviewed-by: Wei Liang Lim > Reviewed-by: Eng Lee Teh > --- > drivers/i2c/i2c-cdns.c | 30 ++ > 1 file changed, 18 insertions(+), 12 deletions(-) Thanks for fixing the build error! Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v2 1/2] dt-bindings: i2c: i2c-cdns.txt: Add description for an optional parameter, fifo-depth
Hello Pei, On 13.02.23 09:02, Pei Yue Ho wrote: > Add description for fifo-depth parameter that can be used > in the device tree. > > Signed-off-by: Pei Yue Ho > Reviewed-by: Wei Liang Lim > Reviewed-by: Eng Lee Teh > --- > doc/device-tree-bindings/i2c/i2c-cdns.txt | 4 > 1 file changed, 4 insertions(+) Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH] arm: kirkwood: Enable uart0 dm-pre-reloc for Pogoplug V4 board
Am 2023-02-13 09:43, schrieb Stefan Roese: On 2/10/23 22:08, Tony Dinh wrote: When DM_SERIAL is enabled, the device-tree tag u-boot,dm-pre-reloc is required for this board to boot over UART with kwboot. Enable this in kirkwood-pogoplug-series-4-u-boot.dtsi. Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese If I understood it correctly, this is a workaround, right? Maybe we can include a link to the original discussion here for the case when someone stumbles over this commit: Link: https://lore.kernel.org/r/20230201080210.ypz4nrj4y2igwxz3@pali/ -michael
Re: [PATCH v2] riscv: cancel the limitation that NR_CPUS is less than or equal to 32
Hi Xiang, On Sat, Feb 11, 2023 at 10:11:31PM +0800, Xiang W wrote: > 在 2023-02-10星期五的 07:25 +，Leo Liang写道： > > Hi Xiang, > > > > On Fri, Feb 03, 2023 at 03:24:37PM +0100, David Abdurachmanov wrote: > > > On Mon, Jan 3, 2022 at 1:13 PM Leo Liang wrote: > > > > > > > > On Thu, Dec 30, 2021 at 01:55:15AM +0800, Xiang W wrote: > > > > > 在 2021-12-29星期三的 17:23 +0800，Leo Liang写道： > > > > > > Hi Xiang, > > > > > > On Wed, Dec 22, 2021 at 07:32:53AM +0800, Xiang W wrote: > > > > > > > Various specifications of riscv allow the number of hart to be > > > > > > > greater than 32. The limit of 32 is determined by > > > > > > > gd->arch.available_harts. We can eliminate this limitation through > > > > > > > bitmaps. Currently, the number of hart is limited to 4095, and > > > > > > > 4095 > > > > > > > is the limit of the RISC-V Advanced Core Local Interruptor > > > > > > > Specification. > > > > > > > > > > > > > > Test on sifive unmatched. > > > > > > > > > > > > > > Signed-off-by: Xiang W > > > > > > > --- > > > > > > > Changes since v1: > > > > > > > > > > > > > > * When NR_CPUS is very large, the value of GD_AVAILABLE_HARTS will > > > > > > > overflow the immediate range of ld/lw. This patch fixes this > > > > > > > problem > > > > > > > > > > > > > > arch/riscv/Kconfig | 4 ++-- > > > > > > > arch/riscv/cpu/start.S | 21 - > > > > > > > arch/riscv/include/asm/global_data.h | 4 +++- > > > > > > > arch/riscv/lib/smp.c | 2 +- > > > > > > > 4 files changed, 22 insertions(+), 9 deletions(-) > > > > > > > > > > > > > I noticed that this has never landed in U-Boot. Was this forgotten or > > > dropped for some reason (couldn't find anything)? > > > > > > The current limit on the Linux kernel side is 512. The default on > > > 64-bit (riscv64) is 64. > > > > > > david > > > > The patch seems to cause some CI error (timeout on QEMU). > > (https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15076) > > Could you take a look at it if you have time? > > > > Best regards, > > Leo > > sorry! I missing a bug. There is an error in calculating the starting address > of available_harts. The patch for start.S needs to be updated. > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > index 76850ec9be..92f3b78f29 100644 > --- a/arch/riscv/cpu/start.S > +++ b/arch/riscv/cpu/start.S > @@ -166,11 +166,22 @@ wait_for_gd_init: > mv gp, s0 > > /* register available harts in the available_harts mask */ > - li t1, 1 > - sll t1, t1, tp > - LREGt2, GD_AVAILABLE_HARTS(gp) > - or t2, t2, t1 > - SREGt2, GD_AVAILABLE_HARTS(gp) > + li t1, GD_AVAILABLE_HARTS > + add t1, t1, gp > +#if defined(CONFIG_ARCH_RV64I) > + srlit2, tp, 6 > + sllit2, t2, 3 > +#elif defined(CONFIG_ARCH_RV32I) > + srlit2, tp, 5 > + sllit2, t2, 2 > +#endif > + add t1, t1, t2 > + LREGt2, 0(t1) > + li t3, 1 > + sll t3, t3, tp > + or t2, t2, t3 > + SREGt2, 0(t1) > > amoswap.w.rl zero, zero, 0(t0) > > The mailing list cannot receive my mail, please help to update > I have updated the patch. (https://patchwork.ozlabs.org/project/uboot/patch/20230213084313.10419-1-ycli...@andestech.com/) Could you take a look to see if there is any issue? Best regards, Leo
[V3,1/1] riscv: Increase the upper bound of NR_CPUS to 4095
From: Xiang W
The maximum hart number is 32 and is determined by
the type of gd->arch.available_harts. However, various
RISC-V specifications allow the hart number to be greater
than 32. We can eliminate this limitation through bitmaps.
The patch modifies the upper bound of the hart number to 4095,
which is also the maximum hart number RISC-V Advanced Core Local
Interruptor Specification gives.
Some defconfigs, (e.g. qemu-riscv32_smode_defconfig,
qemu-riscv64_smode_defconfig, openpiton_riscv64_defconfig, ...)
do not define CONFIG_NR_CPUS, and may result in compile error,
so define CONFIG_NR_CPUS to be 1 if CONFIG_NR_CPUS is not defined.
Tested on sifive unmatched.
Signed-off-by: Xiang W
Signed-off-by: Leo Yu-Chi Liang
---
Changes v2 -> v3:
- Fix the calculation of the GD_AVAILABLE_HARTS start address
- Fix compilation error for defconfigs that do not define CONFIG_NR_CPUS
---
arch/riscv/Kconfig | 4 ++--
arch/riscv/cpu/start.S | 20 +++-
arch/riscv/include/asm/global_data.h | 8 +++-
arch/riscv/lib/smp.c | 2 +-
4 files changed, 25 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ebc4bef220..063734cbb9 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -232,8 +232,8 @@ config SPL_SMP
all, single processor machines.
config NR_CPUS
- int "Maximum number of CPUs (2-32)"
- range 2 32
+ int "Maximum number of CPUs (2-4095)"
+ range 2 4095
depends on SMP || SPL_SMP
default 8
help
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 4687bca3c9..ae19c2b43d 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -172,11 +172,21 @@ wait_for_gd_init:
bnezt1, 1b
/* register available harts in the available_harts mask */
- li t1, 1
- sll t1, t1, tp
- LREGt2, GD_AVAILABLE_HARTS(gp)
- or t2, t2, t1
- SREGt2, GD_AVAILABLE_HARTS(gp)
+ li t1, GD_AVAILABLE_HARTS
+ add t1, t1, gp
+#if defined(CONFIG_ARCH_RV64I)
+ srlit2, tp, 6
+ sllit2, t2, 3
+#elif defined(CONFIG_ARCH_RV32I)
+ srlit2, tp, 5
+ sllit2, t2, 2
+#endif
+ add t1, t1, t2
+ LREGt2, 0(t1)
+ li t3, 1
+ sll t3, t3, tp
+ or t2, t2, t3
+ SREGt2, 0(t1)
amoswap.w.rl zero, zero, 0(t0)
#endif
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
index 6fdc86dd8b..7e37e90db0 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -10,9 +10,15 @@
#ifndef__ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
+#include
#include
#include
#include
+#include
+
+#ifndef CONFIG_NR_CPUS
+#define CONFIG_NR_CPUS 1
+#endif
/* Architecture-specific global data */
struct arch_global_data {
@@ -29,7 +35,7 @@ struct arch_global_data {
#endif
#if !CONFIG_IS_ENABLED(XIP)
#ifdef CONFIG_AVAILABLE_HARTS
- ulong available_harts;
+ ulong available_harts[BITS_TO_LONGS(CONFIG_NR_CPUS)];
#endif
#endif
};
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index 4f073a016f..511e3ed98d 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -48,7 +48,7 @@ static int send_ipi_many(struct ipi_data *ipi, int wait)
#if !CONFIG_IS_ENABLED(XIP)
#ifdef CONFIG_AVAILABLE_HARTS
/* skip if hart is not available */
- if (!(gd->arch.available_harts & (1 << reg)))
+ if (!test_bit(reg, gd->arch.available_harts))
continue;
#endif
#endif
--
2.38.0.68.ge85701b4af.dirty
Re: [PATCH] arm: kirkwood: Enable uart0 dm-pre-reloc for Pogoplug V4 board
On 2/10/23 22:08, Tony Dinh wrote:
When DM_SERIAL is enabled, the device-tree tag u-boot,dm-pre-reloc is
required for this board to boot over UART with kwboot. Enable this in
kirkwood-pogoplug-series-4-u-boot.dtsi.
Signed-off-by: Tony Dinh
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi | 7 +++
1 file changed, 7 insertions(+)
create mode 100644 arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
diff --git a/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
b/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
new file mode 100644
index 00..f9e127234c
--- /dev/null
+++ b/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Tony Dinh
+ */
+ {
+ u-boot,dm-pre-reloc;
+};
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 2/2] riscv: ae350: Adjust the memory layout of ae350
> From: Leo Yu-Chi Liang(梁育齊) > Sent: Thursday, February 09, 2023 4:34 PM > To: u-boot@lists.denx.de > Cc: Rick Jian-Zhi Chen(陳建志) ; Peter Yu-Chien Lin(林宇謙) > ; Leo Yu-Chi Liang(梁育齊) > Subject: [PATCH 2/2] riscv: ae350: Adjust the memory layout of ae350 > > Signed-off-by: Leo Yu-Chi Liang > --- > configs/ae350_rv32_spl_defconfig | 6 +++--- > configs/ae350_rv32_spl_xip_defconfig | 6 +++--- > configs/ae350_rv64_spl_defconfig | 6 +++--- > configs/ae350_rv64_spl_xip_defconfig | 6 +++--- > 4 files changed, 12 insertions(+), 12 deletions(-) Reviewed-by: Rick Chen
Re: [PATCH 1/2] riscv: Rename Andes cpu and board names
> From: Leo Yu-Chi Liang(梁育齊) > Sent: Thursday, February 09, 2023 4:34 PM > To: u-boot@lists.denx.de > Cc: Rick Jian-Zhi Chen(陳建志) ; Peter Yu-Chien Lin(林宇謙) > ; Leo Yu-Chi Liang(梁育齊) > Subject: [PATCH 1/2] riscv: Rename Andes cpu and board names > > The current ae350-related defconfigs could also support newer Andes CPU IP, > so modify the names of CPU from ax25 to andesv5, and board name from > ax25-ae350 to ae350. > > Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen
[PATCH v2 1/2] Revert "mmc: s5p_sdhci: unset the SDHCI_QUIRK_BROKEN_R1B"
This reverts commit a034ec06ff1d558bbe11d5ee05edbb4de3ee2215.
Commit 4a3ea75de4c5 ("Revert "mmc: sdhci: set to INT_DATA_END when
there are data"") reverted the alternative fix that was added for
Exynos 4 devices, causing an error when trying to boot from an sdcard:
<...>
Loading Environment from MMC... sdhci_send_command: Timeout for status
update!
mmc fail to send stop cmd
<...>
Re-add the quirk to allow booting from sdcards again.
Signed-off-by: Henrik Grimler
---
drivers/mmc/s5p_sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index dee84263c3fd..3b74feae68c7 100644
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -90,7 +90,7 @@ static int s5p_sdhci_core_init(struct sdhci_host *host)
host->name = S5P_NAME;
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
- SDHCI_QUIRK_32BIT_DMA_ADDR |
+ SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
host->max_clk = 5200;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
--
2.30.2
[PATCH v2 2/2] samsung: common: do not reset if cros-ec uclass is missing
Otherwise non-ChromeOS samsung devices, like the odroid boards, are
stuck in a bootloop if CONFIG_CROS_EC is not enabled:
<...>
MMC: SAMSUNG SDHCI: 2, EXYNOS DWMMC: 0
Loading Environment from MMC... *** Warning - bad CRC, using default
environment
cros-ec communications failure -96
Please reset with Power+Refresh
Cannot init cros-ec device
resetting ...
Issue started after commit e44d7e73fe0d ("dm: core: Switch
uclass_*_device_err to use uclass_*_device_check").
Signed-off-by: Henrik Grimler
---
board/samsung/common/board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 16ce5cb89253..663d7ca991bc 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -223,7 +223,7 @@ int board_late_init(void)
char mmcbootdev_str[16];
ret = uclass_first_device_err(UCLASS_CROS_EC, );
- if (ret && ret != -ENODEV) {
+ if (ret && ret != -ENODEV && ret != -EPFNOSUPPORT) {
/* Force console on */
gd->flags &= ~GD_FLG_SILENT;
--
2.30.2
[PATCH v2 0/2] odroid: fix boot issues on u2, xu4 and siblings
Hi,
Patch 1 fixes issue reported in [1], which happens on odroid-u2 and
probably other devices in that family. Re-adding this quirk was
discussed already by Jaehoon and Andy in the patch that
(re-)introduced this issue [2], but I do not think a patch was sent
for it.
Patch 2 fixes issue reported in [3], which happens on odroid-{u2,xu4}
and other devices in that family. An alternative fix was sent
previously by Joost [4], but has not been picked up yet.
Tested on odroid-u2 and odroid-xu4 on top of master branch, I am able
to boot from sdcard on both without issues.
Changes since v1:
Patch 1: none
Patch 2:
* Check return code of uclass_first_device_err instead of guarding it
with IS_ENABLED(CONFIG_CROS_EC), suggested by Simon Glass.
[1] https://lists.denx.de/pipermail/u-boot/2023-January/504116.html
[2] https://lists.denx.de/pipermail/u-boot/2021-March/445243.html
[3] https://lists.denx.de/pipermail/u-boot/2023-January/504115.html
[4] https://lists.denx.de/pipermail/u-boot/2023-January/505551.html
Henrik Grimler (2):
Revert "mmc: s5p_sdhci: unset the SDHCI_QUIRK_BROKEN_R1B"
samsung: common: do not reset if cros-ec uclass is missing
board/samsung/common/board.c | 2 +-
drivers/mmc/s5p_sdhci.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
base-commit: a5e490f14e904fd240ccec5d364509b36a3150f9
--
2.30.2
[PATCH v2 2/2] i2c: i2c-cdns.c: Update driver to read fifo-depth from device tree
Enable driver to fetch the optional parameter (fifo-depth) from device
tree. If the parameter is not found in the device tree, it will use
the default value declared in the driver.
Signed-off-by: Pei Yue Ho
Reviewed-by: Wei Liang Lim
Reviewed-by: Eng Lee Teh
---
drivers/i2c/i2c-cdns.c | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 0da9f6f35a..c1672ca18e 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -78,7 +78,7 @@ struct cdns_i2c_regs {
CDNS_I2C_INTERRUPT_RXUNF | \
CDNS_I2C_INTERRUPT_ARBLOST)
-#define CDNS_I2C_FIFO_DEPTH16
+#define CDNS_I2C_FIFO_DEPTH_DEFAULT16
#define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
@@ -135,6 +135,7 @@ struct i2c_cdns_bus {
int hold_flag;
u32 quirks;
+ u32 fifo_depth;
};
struct cdns_i2c_platform_data {
@@ -277,7 +278,7 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus
*i2c_bus, u32 addr, u8 *data,
writel(addr, >address);
start = 0;
}
- if (len && readl(>transfer_size) == CDNS_I2C_FIFO_DEPTH) {
+ if (len && readl(>transfer_size) == i2c_bus->fifo_depth) {
ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
CDNS_I2C_INTERRUPT_ARBLOST);
if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
@@ -310,9 +311,10 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus
*i2c_bus, u32 addr, u8 *data,
return 0;
}
-static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
+static inline bool cdns_is_hold_quirk(struct i2c_cdns_bus *i2c_bus, int
hold_quirk,
+ int curr_recv_count)
{
- return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
+ return hold_quirk && (curr_recv_count == i2c_bus->fifo_depth + 1);
}
static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
@@ -327,7 +329,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus,
u32 addr, u8 *data,
curr_recv_count = recv_count;
/* Check for the message size against the FIFO depth */
- if (recv_count > CDNS_I2C_FIFO_DEPTH)
+ if (recv_count > i2c_bus->fifo_depth)
setbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
@@ -349,7 +351,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus,
u32 addr, u8 *data,
while (recv_count && !is_arbitration_lost(regs)) {
while (readl(>status) & CDNS_I2C_STATUS_RXDV) {
- if (recv_count < CDNS_I2C_FIFO_DEPTH &&
+ if (recv_count < i2c_bus->fifo_depth &&
!i2c_bus->hold_flag) {
clrbits_le32(>control,
CDNS_I2C_CONTROL_HOLD);
@@ -358,27 +360,27 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus
*i2c_bus, u32 addr, u8 *data,
recv_count--;
curr_recv_count--;
- if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
+ if (cdns_is_hold_quirk(i2c_bus, hold_quirk,
curr_recv_count))
break;
}
- if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
+ if (cdns_is_hold_quirk(i2c_bus, hold_quirk, curr_recv_count)) {
/* wait while fifo is full */
while (readl(>transfer_size) !=
-(curr_recv_count - CDNS_I2C_FIFO_DEPTH))
+(curr_recv_count - i2c_bus->fifo_depth))
;
/*
* Check number of bytes to be received against maximum
* transfer size and update register accordingly.
*/
- if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
+ if ((recv_count - i2c_bus->fifo_depth) >
CDNS_I2C_TRANSFER_SIZE) {
writel(CDNS_I2C_TRANSFER_SIZE,
>transfer_size);
curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
- CDNS_I2C_FIFO_DEPTH;
+ i2c_bus->fifo_depth;
} else {
- writel(recv_count - CDNS_I2C_FIFO_DEPTH,
+ writel(recv_count - i2c_bus->fifo_depth,
[PATCH v2 0/2] i2c: i2c-cdns.c: Update driver to read fifo-depth from device tree
V2: Added 'i2c_bus' parameter to function 'cdns_is_hold_quirk' to fix compilation issue Enable driver to fetch the optional parameter (fifo-depth) from device tree. If the parameter is not found in the device tree, it will use the default value declared in the driver. Pei Yue Ho (2): dt-bindings: i2c: i2c-cdns.txt: Add description for an optional parameter, fifo-depth i2c: i2c-cdns.c: Update driver to read fifo-depth from device tree doc/device-tree-bindings/i2c/i2c-cdns.txt | 4 +++ drivers/i2c/i2c-cdns.c| 30 ++- 2 files changed, 22 insertions(+), 12 deletions(-) -- 2.25.1
[PATCH v2 1/2] dt-bindings: i2c: i2c-cdns.txt: Add description for an optional parameter, fifo-depth
Add description for fifo-depth parameter that can be used
in the device tree.
Signed-off-by: Pei Yue Ho
Reviewed-by: Wei Liang Lim
Reviewed-by: Eng Lee Teh
---
doc/device-tree-bindings/i2c/i2c-cdns.txt | 4
1 file changed, 4 insertions(+)
diff --git a/doc/device-tree-bindings/i2c/i2c-cdns.txt
b/doc/device-tree-bindings/i2c/i2c-cdns.txt
index 202e0b7626..eaff34a555 100644
--- a/doc/device-tree-bindings/i2c/i2c-cdns.txt
+++ b/doc/device-tree-bindings/i2c/i2c-cdns.txt
@@ -9,6 +9,9 @@ Required properties:
- interrupt-parent : Must be core interrupt controller
- clocks : Clock phandles (see clock bindings for details).
+Optional properties:
+- fifo-depth : To specify the FIFO depth of the controller.
+
Example:
i2c0: i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
@@ -16,5 +19,6 @@ Example:
clocks = < 38>;
interrupts = <0 25 4>;
interrupt-parent = <>;
+ fifo-depth = <32>;
status = "disabled";
};
--
2.25.1
