Re: [PATCH] riscv: Add a 64-bit image type
> From: Simon Glass > Sent: Monday, April 03, 2023 4:28 AM > To: U-Boot Mailing List > Cc: Sean Anderson ; Bin Meng ; Rick > Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊) > ; Simon Glass ; Andre Przywara > ; Marc Kleine-Budde ; SESA644425 > ; Samuel Holland ; Steven > Lawrance > Subject: [PATCH] riscv: Add a 64-bit image type > > At present it is not possible to know whether an image can be booted by a 32- > or 64-bit bootloader. This means that U-Boot may attempt to boot the wrong > image. This may cause a crash which might be hard to debug. > > Add a new property to make this explicit. > > The existing 'RISC-V' is now taken to mean 32-bit. > > Signed-off-by: Simon Glass > --- > > boot/image.c| 3 ++- > include/image.h | 3 ++- > 2 files changed, 4 insertions(+), 2 deletions(-) Reviewed-by: Rick Chen
[PATCH] riscv: Support riscv64 image type
Allow U-Boot to load 32 or 64 bits RISC-V Kernel Image distinguishly. It helps to avoid someone maybe make a mistake to run 32-bit U-Boot to load 64-bit kernel. Signed-off-by: Rick Chen --- The patchset is based on Simon's patch: riscv: Add a 64-bit image type --- --- arch/riscv/include/asm/u-boot.h | 4 cmd/booti.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/u-boot.h b/arch/riscv/include/asm/u-boot.h index d5e1d5f323..e3b4a0357c 100644 --- a/arch/riscv/include/asm/u-boot.h +++ b/arch/riscv/include/asm/u-boot.h @@ -23,6 +23,10 @@ #include /* For image.h:image_check_target_arch() */ +#ifdef CONFIG_ARCH_RV64I +#define IH_ARCH_DEFAULT IH_ARCH_RISCV64 +#else #define IH_ARCH_DEFAULT IH_ARCH_RISCV +#endif #endif /* _U_BOOT_H_ */ diff --git a/cmd/booti.c b/cmd/booti.c index 6ac39193db..dc0b0ae41c 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -119,7 +119,7 @@ int do_booti(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) images.os.os = IH_OS_LINUX; #ifdef CONFIG_RISCV_SMODE - images.os.arch = IH_ARCH_RISCV; + images.os.arch = IH_ARCH_DEFAULT; #elif CONFIG_ARM64 images.os.arch = IH_ARCH_ARM64; #endif -- 2.17.1
[PATCH V7 00/14] Add splash screen support at u-boot SPL
To enable splash screen at SPL stage move video driver and splash screen framework at SPL, which will bring up image on display very quickly and thus have early display support in SPL. Changes in V7 - Replace #ifdefs' and #ifs' with if in common/splash and common/bmp. - Add Reviewed-by and Tested-by tag in apprpriate patch. Changes in V6 - Fix commit messages. - Fix compile rules for video related files in patch drivers: video: Makefile: Rule to compile necessary video driver files. Changes in V5 - Drop patch cmd: Makefile: Rule to compile bmp_cmd. - Squash common: splash: Replace CONFIG_CMD_BMP patch into patches common: Enable splash functions at SPL include: Enable video related global data variable and splash at SPL - Fix merge issue for next branch. - Replace cmd/bmp_cmd with cmd/bmp. - Use CONFIG_$(SPL_TPL_) to compile files in drivers: video: Makefile: Rule to compile necessary video driver files. - Add Reviewed-by tag in apprpriate patch. Changes in V4 - Add Reviewed-by tag in apprpriate patch. Changes in V3 - Add separate video configs for SPL splash screen. - Add rule to compile video driver in drivers/Makefile at SPL. - Add rule to compile splash.c and splash_source.c. - Squash drivers: video: video-uclass: Disable u-boot logo at SPL into drivers: video: Use CONFIG_IS_ENABLED and CONFIG_VAL. - Split cmd/bmp.c to separate bmp functions and commands. - Add CONFIG_BMP and CONFIG_SPL_BMP. - Add rule to compile necessary files required for video driver. - Add rule to compile common/bmp.c. Changes in V2 - Removed artifacts from bad patch apply. Nikhil M Jain (14): drivers: video: Kconfig: Add configs for enabling video at SPL drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPL drivers: Makefile: Add rule to compile video driver drivers: video: Makefile: Rule to compile necessary video driver files drivers: video: tidss: Makefile: Add condition to compile TIDSS at SPL common: Makefile: Add rule to compile splash and splash_source at SPL common: Kconfig: Add BMP configs cmd: bmp: Split bmp commands and functions common: Makefile: Rule to compile bmp.c drivers: video: Enable necessary video functions at SPL common: Enable splash functions at SPL include: Enable video related global data variable and splash at SPL board: ti: am62x: evm: OSPI support for splash screen common: Replace #ifdef and #if with if's board/ti/am62x/evm.c | 8 +- cmd/bmp.c | 162 +- common/Kconfig| 12 ++ common/Makefile | 3 + common/bmp.c | 147 common/splash.c | 18 +-- drivers/Makefile | 1 + drivers/video/Kconfig | 223 +- drivers/video/Makefile| 16 +-- drivers/video/console_core.c | 6 +- drivers/video/tidss/Kconfig | 6 + drivers/video/tidss/Makefile | 2 +- drivers/video/vidconsole-uclass.c | 2 +- drivers/video/video-uclass.c | 14 +- drivers/video/video_bmp.c | 8 +- include/asm-generic/global_data.h | 4 +- include/splash.h | 16 +-- include/video.h | 8 ++ 18 files changed, 445 insertions(+), 211 deletions(-) create mode 100644 common/bmp.c -- 2.34.1
[PATCH V7 01/14] drivers: video: Kconfig: Add configs for enabling video at SPL
Add Kconfigs which enable the video driver and splash screen at SPL stage only and not at u-boot proper. The existing Kconfigs from u-boot proper were not used to make SPL splash screen independent to them. Signed-off-by: Nikhil M Jain Reviewed-by: Devarsh Thakkar Reviewed-by: Simon Glass Tested-by: Simon Glass --- V7: - Add Reviewed-by and Tested-by tag. V6: - Replace CMD_BMP with BMP. V5: - Added Reviewed-by tag. V4: - No change. V3: - Add separate SPL video and splash configs. - Reviewed-by tag not added due to additional changes in V3. V2: - No change. drivers/video/Kconfig | 223 +- 1 file changed, 222 insertions(+), 1 deletion(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 60f4a4bf9c..05eaaa767a 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -893,7 +893,7 @@ endif # SPLASH_SCREEN config VIDEO_BMP_GZIP bool "Gzip compressed BMP image support" - depends on CMD_BMP || SPLASH_SCREEN + depends on BMP || SPLASH_SCREEN help If this option is set, additionally to standard BMP images, gzipped BMP images can be displayed via the @@ -930,4 +930,225 @@ config BMP_32BPP endif # VIDEO +config SPL_VIDEO + bool "Enable driver model support for LCD/video" + depends on SPL_DM + help + The video subsystem adds a small amount of overhead to the image. + If this is acceptable and you have a need to use video drivers in + SPL, enable this option. It might provide a cleaner interface to + setting up video within SPL, and allows the same drivers to be + used as U-Boot proper. + +if SPL_VIDEO +source "drivers/video/tidss/Kconfig" + +config SPL_VIDEO_LOGO + bool "Show the U-Boot logo on the display atSPL" + default y if !SPL_SPLASH_SCREEN + select SPL_VIDEO_BMP_RLE8 + help + This enables showing the U-Boot logo on the display when a video + device is probed. It appears at the top right. The logo itself is at + tools/logos/u-boot_logo.bmp and looks best when the display has a + black background. + +config SPL_SPLASH_SCREEN + bool "Show a splash-screen image at SPL" + help + If this option is set, the environment is checked for a variable + "splashimage" at spl stage. + +config SPL_SYS_WHITE_ON_BLACK + bool "Display console as white on a black background at SPL" + help +Normally the display is black on a white background, Enable this +option to invert this, i.e. white on a black background at spl stage. +This can be better in low-light situations or to reduce eye strain in +some cases. + +config SPL_VIDEO_PCI_DEFAULT_FB_SIZE + hex "Default framebuffer size to use if no drivers request it at SPL" + default 0x100 if X86 && PCI + default 0 if !(X86 && PCI) + help + Generally, video drivers request the amount of memory they need for + the frame buffer when they are bound, by setting the size field in + struct video_uc_plat. That memory is then reserved for use after + relocation. But PCI drivers cannot be bound before relocation unless + they are mentioned in the devicetree. + + With this value set appropriately, it is possible for PCI video + devices to have a framebuffer allocated by U-Boot. + + Note: the framebuffer needs to be large enough to store all pixels at + maximum resolution. For example, at 1920 x 1200 with 32 bits per + pixel, 2560 * 1600 * 32 / 8 = 0xfa bytes are needed. + +config SPL_CONSOLE_SCROLL_LINES + int "Number of lines to scroll the console by at SPL" + default 1 + help + When the console need to be scrolled, this is the number of + lines to scroll by. It defaults to 1. Increasing this makes the + console jump but can help speed up operation when scrolling + is slow. + +config SPL_CONSOLE_NORMAL + bool "Support a simple text console at SPL" + default y + help + Support drawing text on the frame buffer console so that it can be + used as a console. Rotation is not supported by this driver (see + CONFIG_CONSOLE_ROTATION for that). A built-in 8x16 font is used + for the display. + +config SPL_BACKLIGHT + bool "Enable panel backlight uclass support at SPL" + default y + help + This provides backlight uclass driver that enables basic panel + backlight support. + +config SPL_PANEL + bool "Enable panel uclass support at SPL" + default y + help + This provides panel uclass driver that enables basic panel support. + +config SPL_SIMPLE_PANEL + bool "Enable simple panel support at SPL" + depends on SPL_PANEL && SPL_BACKLIGHT && SPL_DM_GPIO + default y + help + This turns on a simple panel dr
[PATCH V7 03/14] drivers: Makefile: Add rule to compile video driver
Compile video driver at SPL using CONFIG_SPL_VIDEO. Signed-off-by: Nikhil M Jain Reviewed-by: Devarsh Thakkar Reviewed-by: Simon Glass Tested-by: Simon Glass --- V7: - Add Reviewed-by and Tested-by tag. V6: - Add Reviewed-by tag - Commit message updated. V5: - Add rule to build video at SPL using CONFIG_SPL_VIDEO and retain obj-y +=video for u-boot proper. V4: - No change V3 (patch introduced): - Add rule to compile video driver at SPL. drivers/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/Makefile b/drivers/Makefile index 58be410135..928a8b0e9d 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_SPL_USB_HOST) += usb/host/ obj-$(CONFIG_SPL_SATA) += ata/ scsi/ obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/ obj-$(CONFIG_SPL_THERMAL) += thermal/ +obj-$(CONFIG_SPL_VIDEO) +=video/ endif endif -- 2.34.1
[PATCH V7 02/14] drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPL
To enable tidss display driver only at SPL stage, add necessary config, CONFIG_SPL_VIDEO_TIDSS. Signed-off-by: Nikhil M Jain Reviewed-by: Simon Glass Reviewed-by: Devarsh Thakkar --- V7: - No change V6: - Fix commit message. - Add Reviewed-By tag. V5: - No change V4: - Add Reviewed-By tag V3: - No change V2: - No change drivers/video/tidss/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/video/tidss/Kconfig b/drivers/video/tidss/Kconfig index 2a5e56ea4e..95086f3a5d 100644 --- a/drivers/video/tidss/Kconfig +++ b/drivers/video/tidss/Kconfig @@ -16,3 +16,9 @@ menuconfig VIDEO_TIDSS DPI . This option enables these supports which can be used on devices which have OLDI or HDMI display connected. +config SPL_VIDEO_TIDSS + bool "Enable TIDSS video support in SPL Stage" + depends on SPL_VIDEO + help + This options enables tidss driver in SPL stage. If + you need to use tidss at SPL stage use this config. -- 2.34.1
[PATCH V7 07/14] common: Kconfig: Add BMP configs
Add CONFIG_BMP and CONFIG_SPL_BMP which enable displaying bmp images at u-boot proper and SPL. Signed-off-by: Nikhil M Jain Reviewed-by: Simon Glass Reviewed-by: Devarsh Thakkar --- V7: - No change. V6: - Added Reviewed-by tag. V5: - Added Reviewed-by tag. V4: - No change. common/Kconfig | 12 1 file changed, 12 insertions(+) diff --git a/common/Kconfig b/common/Kconfig index 7ff62552cb..7329dc8253 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1154,3 +1154,15 @@ config FDT_SIMPLEFB config IO_TRACE bool + +config BMP + bool "Enable bmp image display" + default y if CMD_BMP + help + Enable bmp functions to display bmp image and get bmp info. + +config SPL_BMP + bool "Enable bmp image display at SPL" + depends on SPL_VIDEO + help + Enable bmp functions to display bmp image and get bmp info at SPL. -- 2.34.1
[PATCH V7 09/14] common: Makefile: Rule to compile bmp.c
Add rule to compile bmp.c at SPL and u-boot proper when CONFIG_SPL_BMP and CONFIG_BMP are defined. Signed-off-by: Nikhil M Jain Reviewed-by: Devarsh Thakkar Reviewed-by: Simon Glass Tested-by: Simon Glass --- V7: - Add Reviewed-by and Tested-by tag. V6: - Add Reviewed-by tag. V5: - Remove obj-y+= read.o. V4: - No change. V3 (patch introduced): - Rule to compile common/bmp. common/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/common/Makefile b/common/Makefile index 3a6ca337e0..c87bb2e78b 100644 --- a/common/Makefile +++ b/common/Makefile @@ -45,6 +45,7 @@ endif # !CONFIG_SPL_BUILD obj-$(CONFIG_$(SPL_TPL_)BOOTSTAGE) += bootstage.o obj-$(CONFIG_$(SPL_TPL_)BLOBLIST) += bloblist.o +obj-$(CONFIG_$(SPL_)BMP) += bmp.o ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_DFU -- 2.34.1
[PATCH V7 04/14] drivers: video: Makefile: Rule to compile necessary video driver files
To enable video driver at SPL, need to compile video-uclass, vidconsole-uclass, backlight-uclass, panel-uclass, simple-panel, add rules to compile them at SPL and u-boot proper. To support splash_display at SPL, need to compile video-bmp, add rule to compile at SPL and u-boot proper. Signed-off-by: Nikhil M Jain Reviewed-by: Devarsh Thakkar Reviewed-by: Simon Glass Tested-by: Simon Glass --- V7: - Add Reviewed-by and Tested-by tag. V6: - Fix CONFIG_$(SPL_TPL)CONSOLE_NORMAL to CONFIG_$(SPL_TPL_)CONSOLE_NORMAL - Add rule to compile simple_panel at SPL and u-boot proper. V5: - Use $(SPL_TPL_) to check for stage specific configs and compile at specific stages. - Removed ifdef CONFIG_SPL_BUILD V4: - No change V3: - Rule to compile backlight, console and panel files - Not added Reiewed-by tag due to changes V2: - No change drivers/video/Makefile | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/video/Makefile b/drivers/video/Makefile index cb3f373645..ba2fd41865 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -4,12 +4,12 @@ # Wolfgang Denk, DENX Software Engineering, w...@denx.de. ifdef CONFIG_DM -obj-$(CONFIG_BACKLIGHT) += backlight-uclass.o +obj-$(CONFIG_$(SPL_TPL_)BACKLIGHT) += backlight-uclass.o obj-$(CONFIG_BACKLIGHT_GPIO) += backlight_gpio.o obj-$(CONFIG_BACKLIGHT_PWM) += pwm_backlight.o -obj-$(CONFIG_CONSOLE_NORMAL) += console_normal.o +obj-$(CONFIG_$(SPL_TPL_)CONSOLE_NORMAL) += console_normal.o obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o -ifdef CONFIG_CONSOLE_NORMAL +ifdef CONFIG_$(SPL_TPL_)CONSOLE_NORMAL obj-y += console_core.o else ifdef CONFIG_CONSOLE_ROTATION obj-y += console_core.o @@ -18,11 +18,11 @@ obj-$(CONFIG_CONSOLE_ROTATION) += console_core.o obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/ obj-$(CONFIG_DISPLAY) += display-uclass.o obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o -obj-$(CONFIG_VIDEO) += video-uclass.o vidconsole-uclass.o -obj-$(CONFIG_VIDEO) += video_bmp.o -obj-$(CONFIG_PANEL) += panel-uclass.o +obj-$(CONFIG_$(SPL_TPL_)VIDEO) += video-uclass.o vidconsole-uclass.o +obj-$(CONFIG_$(SPL_TPL_)VIDEO) += video_bmp.o +obj-$(CONFIG_$(SPL_TPL_)PANEL) += panel-uclass.o obj-$(CONFIG_PANEL_HX8238D) += hx8238d.o -obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o +obj-$(CONFIG_$(SPL_TPL_)SIMPLE_PANEL) += simple_panel.o obj-$(CONFIG_VIDEO_LOGO) += u_boot_logo.o -- 2.34.1
[PATCH V7 05/14] drivers: video: tidss: Makefile: Add condition to compile TIDSS at SPL
To enable TIDSS driver only at SPL stage add rule to compile the TIDSS
video driver.
CONFIG_$(SPL_)VIDEO_TIDSS will compile tidss_drv, at SPL only if
CONFIG_SPL_VIDEO_TIDSS is defined and at u-boot proper if
CONFIG_VIDEO_TIDSS is defined.
Signed-off-by: Nikhil M Jain
Reviewed-by: Simon Glass
---
V7:
- No change.
V6:
- No change.
V5:
- Use CONFIG_$(SPL_)VIDEO_TIDSS to build TIDSS driver at SPL and u-boot
proper.
V4:
- Added Reviewed-by tag.
V3:
- No change.
V2:
- No change.
drivers/video/Makefile | 2 +-
drivers/video/tidss/Makefile | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index ba2fd41865..c6a84581fc 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -32,7 +32,7 @@ obj-${CONFIG_EXYNOS_FB} += exynos/
obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
obj-${CONFIG_VIDEO_STM32} += stm32/
obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
-obj-${CONFIG_VIDEO_TIDSS} += tidss/
+obj-${CONFIG_$(SPL_)VIDEO_TIDSS} += tidss/
obj-y += ti/
obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
diff --git a/drivers/video/tidss/Makefile b/drivers/video/tidss/Makefile
index f4f8c6c470..a29cee2a41 100644
--- a/drivers/video/tidss/Makefile
+++ b/drivers/video/tidss/Makefile
@@ -9,4 +9,4 @@
# Author: Tomi Valkeinen
-obj-${CONFIG_VIDEO_TIDSS} = tidss_drv.o
+obj-${CONFIG_$(SPL_)VIDEO_TIDSS} = tidss_drv.o
--
2.34.1
[PATCH V7 12/14] include: Enable video related global data variable and splash at SPL
To include video related global data variables and splash functions at
SPL and u-boot proper, use CONFIG_IS_ENABLED.
Replace CONFIG_CMD_BMP with CONFIG_BMP to enable splash_display function
at u-boot proper and SPL.
Signed-off-by: Nikhil M Jain
Reviewed-by: Devarsh Thakkar
Reviewed-by: Simon Glass
---
V7:
- Add Reviewed-by tag.
V6:
- Fix commit message.
- Add Reviewed-by tag.
V5:
- Replace CONFIG_CMD_BMP with CONFIG_BMP.
V4:
- No change
V3 (patch introduced):
- Enable splash functions at SPL
include/asm-generic/global_data.h | 4 ++--
include/splash.h | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/asm-generic/global_data.h
b/include/asm-generic/global_data.h
index 987fb66c17..65bf8df1e5 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -68,7 +68,7 @@ struct global_data {
* @mem_clk: memory clock rate in Hz
*/
unsigned long mem_clk;
-#if defined(CONFIG_VIDEO)
+#if CONFIG_IS_ENABLED(VIDEO)
/**
* @fb_base: base address of frame buffer memory
*/
@@ -359,7 +359,7 @@ struct global_data {
*/
struct membuff console_in;
#endif
-#ifdef CONFIG_VIDEO
+#if CONFIG_IS_ENABLED(VIDEO)
/**
* @video_top: top of video frame buffer area
*/
diff --git a/include/splash.h b/include/splash.h
index 083c978582..aa0c14024e 100644
--- a/include/splash.h
+++ b/include/splash.h
@@ -49,7 +49,7 @@ struct splash_location {
char *ubivol; /* UBI volume-name for ubifsmount */
};
-#ifdef CONFIG_SPLASH_SOURCE
+#if CONFIG_IS_ENABLED(SPLASH_SOURCE)
int splash_source_load(struct splash_location *locations, uint size);
#else
static inline int splash_source_load(struct splash_location *locations,
@@ -61,13 +61,13 @@ static inline int splash_source_load(struct splash_location
*locations,
int splash_screen_prepare(void);
-#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+#if CONFIG_IS_ENABLED(SPLASH_SCREEN_ALIGN)
void splash_get_pos(int *x, int *y);
#else
static inline void splash_get_pos(int *x, int *y) { }
#endif
-#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_CMD_BMP)
+#if CONFIG_IS_ENABLED(SPLASH_SCREEN) && CONFIG_IS_ENABLED(BMP)
int splash_display(void);
#else
static inline int splash_display(void)
--
2.34.1
[PATCH V7 11/14] common: Enable splash functions at SPL
To support splash screen at both u-boot proper and SPL use
CONFIG_IS_ENABLED and CONFIG_VAL to check for video related Kconfigs at
respective stages.
Replace CONFIG_CMD_BMP with CONFIG_BMP to enable splash_display function
at u-boot proper and SPL.
Signed-off-by: Nikhil M Jain
Reviewed-by: Devarsh Thakkar
Reviewed-by: Simon Glass
---
V7:
- Add Reviewed-by tag.
V6:
- Fix commit message.
- Add Reviewed-by tag.
V5:
- Replace CONFIG_CMD_BMP with CONFIG_BMP.
V4:
- No change
V3 (patch introduced):
- Enable splash functions at SPL
common/bmp.c | 12 ++--
common/splash.c | 10 +-
include/splash.h | 2 +-
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/common/bmp.c b/common/bmp.c
index d98ba9d882..51766b3c21 100644
--- a/common/bmp.c
+++ b/common/bmp.c
@@ -33,7 +33,7 @@
* Returns NULL if decompression failed, or if the decompressed data
* didn't contain a valid BMP signature.
*/
-#ifdef CONFIG_VIDEO_BMP_GZIP
+#if CONFIG_IS_ENABLED(VIDEO_BMP_GZIP)
struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
void **alloc_addr)
{
@@ -44,9 +44,9 @@ struct bmp_image *gunzip_bmp(unsigned long addr, unsigned
long *lenp,
/*
* Decompress bmp image
*/
- len = CONFIG_VIDEO_LOGO_MAX_SIZE;
+ len = CONFIG_VAL(VIDEO_LOGO_MAX_SIZE);
/* allocate extra 3 bytes for 32-bit-aligned-address + 2 alignment */
- dst = malloc(CONFIG_VIDEO_LOGO_MAX_SIZE + 3);
+ dst = malloc(CONFIG_VAL(VIDEO_LOGO_MAX_SIZE) + 3);
if (!dst) {
puts("Error: malloc in gunzip failed!\n");
return NULL;
@@ -55,12 +55,12 @@ struct bmp_image *gunzip_bmp(unsigned long addr, unsigned
long *lenp,
/* align to 32-bit-aligned-address + 2 */
bmp = dst + 2;
- if (gunzip(bmp, CONFIG_VIDEO_LOGO_MAX_SIZE, map_sysmem(addr, 0),
+ if (gunzip(bmp, CONFIG_VAL(VIDEO_LOGO_MAX_SIZE), map_sysmem(addr, 0),
&len)) {
free(dst);
return NULL;
}
- if (len == CONFIG_VIDEO_LOGO_MAX_SIZE)
+ if (len == CONFIG_VAL(VIDEO_LOGO_MAX_SIZE))
puts("Image could be truncated (increase
CONFIG_VIDEO_LOGO_MAX_SIZE)!\n");
/*
@@ -115,7 +115,7 @@ int bmp_info(ulong addr)
if (bmp_alloc_addr)
free(bmp_alloc_addr);
- return 0;
+ return(0);
}
int bmp_display(ulong addr, int x, int y)
diff --git a/common/splash.c b/common/splash.c
index 4bc54b1bf9..a4e68b7042 100644
--- a/common/splash.c
+++ b/common/splash.c
@@ -89,14 +89,14 @@ static inline int splash_video_logo_load(void) { return
-ENOSYS; }
__weak int splash_screen_prepare(void)
{
- if (IS_ENABLED(CONFIG_SPLASH_SOURCE))
+ if (CONFIG_IS_ENABLED(SPLASH_SOURCE))
return splash_source_load(default_splash_locations,
ARRAY_SIZE(default_splash_locations));
return splash_video_logo_load();
}
-#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+#if CONFIG_IS_ENABLED(SPLASH_SCREEN_ALIGN)
void splash_get_pos(int *x, int *y)
{
char *s = env_get("splashpos");
@@ -119,7 +119,7 @@ void splash_get_pos(int *x, int *y)
}
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
-#if defined(CONFIG_VIDEO) && !defined(CONFIG_HIDE_LOGO_VERSION)
+#if CONFIG_IS_ENABLED(VIDEO) && !CONFIG_IS_ENABLED(HIDE_LOGO_VERSION)
#ifdef CONFIG_VIDEO_LOGO
#include
@@ -159,7 +159,7 @@ void splash_display_banner(void)
* Common function to show a splash image if env("splashimage") is set.
* For additional details please refer to doc/README.splashprepare.
*/
-#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_CMD_BMP)
+#if CONFIG_IS_ENABLED(SPLASH_SCREEN) && CONFIG_IS_ENABLED(BMP)
int splash_display(void)
{
ulong addr;
@@ -183,7 +183,7 @@ int splash_display(void)
if (x || y)
goto end;
-#if defined(CONFIG_VIDEO) && !defined(CONFIG_HIDE_LOGO_VERSION)
+#if CONFIG_IS_ENABLED(VIDEO) && !CONFIG_IS_ENABLED(HIDE_LOGO_VERSION)
splash_display_banner();
#endif
end:
diff --git a/include/splash.h b/include/splash.h
index 33e45e6941..083c978582 100644
--- a/include/splash.h
+++ b/include/splash.h
@@ -78,4 +78,4 @@ static inline int splash_display(void)
#define BMP_ALIGN_CENTER 0x7FFF
-#endif
+#endif
\ No newline at end of file
--
2.34.1
[PATCH V7 06/14] common: Makefile: Add rule to compile splash and splash_source at SPL
To enable splash screen and loading bmp from boot media, add rules to compile splash.c and splash_source.c at SPL stage only when CONFIG_SPL_SPLASH_SCREEN and CONFIG_SPL_SPLASH_SOURCE are defined. Signed-off-by: Nikhil M Jain Reviewed-by: Devarsh Thakkar Reviewed-by: Simon Glass --- V7: - Add Reviewed-by tag. V6: - Add Reviewed-by tag. V5: - No change V4: - No change common/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/common/Makefile b/common/Makefile index a50302d8b5..3a6ca337e0 100644 --- a/common/Makefile +++ b/common/Makefile @@ -56,6 +56,8 @@ obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o obj-$(CONFIG_SPL_USB_HOST) += usb.o usb_hub.o obj-$(CONFIG_SPL_USB_STORAGE) += usb_storage.o obj-$(CONFIG_SPL_MUSB_NEW) += usb.o +obj-$(CONFIG_SPL_SPLASH_SCREEN) += splash.o +obj-$(CONFIG_SPL_SPLASH_SOURCE) += splash_source.o endif # CONFIG_SPL_BUILD #others -- 2.34.1
[PATCH V7 14/14] common: Replace #ifdef and #if with if's
Remove #ifdef in header file to avoid multiple definitions while
compilation. To improve code readability use if() rather than if's and
'#ifdef's'.
Signed-off-by: Nikhil M Jain
---
V7(patch introduced):
- Replace #ifdef and #if with if's.
common/bmp.c | 12 +++-
common/splash.c | 12 ++--
include/splash.h | 12
3 files changed, 9 insertions(+), 27 deletions(-)
diff --git a/common/bmp.c b/common/bmp.c
index 51766b3c21..62b2d07d23 100644
--- a/common/bmp.c
+++ b/common/bmp.c
@@ -33,7 +33,7 @@
* Returns NULL if decompression failed, or if the decompressed data
* didn't contain a valid BMP signature.
*/
-#if CONFIG_IS_ENABLED(VIDEO_BMP_GZIP)
+
struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
void **alloc_addr)
{
@@ -41,6 +41,8 @@ struct bmp_image *gunzip_bmp(unsigned long addr, unsigned
long *lenp,
unsigned long len;
struct bmp_image *bmp;
+ if (!CONFIG_IS_ENABLED(VIDEO_BMP_GZIP))
+ return NULL;
/*
* Decompress bmp image
*/
@@ -77,14 +79,6 @@ struct bmp_image *gunzip_bmp(unsigned long addr, unsigned
long *lenp,
*alloc_addr = dst;
return bmp;
}
-#else
-struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
-void **alloc_addr)
-{
- return NULL;
-}
-#endif
-
#ifdef CONFIG_NEEDS_MANUAL_RELOC
void bmp_reloc(void) {
diff --git a/common/splash.c b/common/splash.c
index a4e68b7042..4c38a155d0 100644
--- a/common/splash.c
+++ b/common/splash.c
@@ -79,7 +79,7 @@ static int splash_video_logo_load(void)
}
memcpy((void *)bmp_load_addr, bmp_logo_bitmap,
- ARRAY_SIZE(bmp_logo_bitmap));
+ ARRAY_SIZE(bmp_logo_bitmap));
return 0;
}
@@ -96,11 +96,12 @@ __weak int splash_screen_prepare(void)
return splash_video_logo_load();
}
-#if CONFIG_IS_ENABLED(SPLASH_SCREEN_ALIGN)
void splash_get_pos(int *x, int *y)
{
char *s = env_get("splashpos");
+ if (!CONFIG_IS_ENABLED(SPLASH_SCREEN_ALIGN))
+ return;
if (!s)
return;
@@ -117,7 +118,6 @@ void splash_get_pos(int *x, int *y)
*y = simple_strtol(s + 1, NULL, 0);
}
}
-#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
#if CONFIG_IS_ENABLED(VIDEO) && !CONFIG_IS_ENABLED(HIDE_LOGO_VERSION)
@@ -159,13 +159,14 @@ void splash_display_banner(void)
* Common function to show a splash image if env("splashimage") is set.
* For additional details please refer to doc/README.splashprepare.
*/
-#if CONFIG_IS_ENABLED(SPLASH_SCREEN) && CONFIG_IS_ENABLED(BMP)
+
int splash_display(void)
{
ulong addr;
char *s;
int x = 0, y = 0, ret;
-
+ if (!(CONFIG_IS_ENABLED(SPLASH_SCREEN) && CONFIG_IS_ENABLED(BMP)))
+ return -ENOSYS;
s = env_get("splashimage");
if (!s)
return -EINVAL;
@@ -189,4 +190,3 @@ int splash_display(void)
end:
return ret;
}
-#endif
diff --git a/include/splash.h b/include/splash.h
index aa0c14024e..8f15adf9dd 100644
--- a/include/splash.h
+++ b/include/splash.h
@@ -61,21 +61,9 @@ static inline int splash_source_load(struct splash_location
*locations,
int splash_screen_prepare(void);
-#if CONFIG_IS_ENABLED(SPLASH_SCREEN_ALIGN)
void splash_get_pos(int *x, int *y);
-#else
-static inline void splash_get_pos(int *x, int *y) { }
-#endif
-#if CONFIG_IS_ENABLED(SPLASH_SCREEN) && CONFIG_IS_ENABLED(BMP)
int splash_display(void);
-#else
-static inline int splash_display(void)
-{
- return -ENOSYS;
-}
-#endif
-
#define BMP_ALIGN_CENTER 0x7FFF
#endif
\ No newline at end of file
--
2.34.1
[PATCH V7 10/14] drivers: video: Enable necessary video functions at SPL
To support video driver at SPL use CONFIG_IS_ENABLED and CONFIG_VAL,
which checks for stage specific configs and thus enables video support
at respective stage.
Signed-off-by: Nikhil M Jain
Reviewed-by: Devarsh Thakkar
Reviewed-by: Simon Glass
Tested-by: Simon Glass
---
V7:
- Add Reviewed-by and Tested-by tag.
V6:
- No change.
V5:
- Add Reviewed-By tag.
- Use COFIG_IS_ENABLED in console_core in place of console_normal.
V4:
- No change.
V3 (patch introduced):
- Enable necessary video functions at SPL.
drivers/video/console_core.c | 6 +++---
drivers/video/vidconsole-uclass.c | 2 +-
drivers/video/video-uclass.c | 14 +++---
drivers/video/video_bmp.c | 8
4 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/video/console_core.c b/drivers/video/console_core.c
index d4f79c656a..1f93b1b85f 100644
--- a/drivers/video/console_core.c
+++ b/drivers/video/console_core.c
@@ -46,11 +46,11 @@ static int console_set_font(struct udevice *dev, struct
video_fontdata *fontdata
int check_bpix_support(int bpix)
{
- if (bpix == VIDEO_BPP8 && IS_ENABLED(CONFIG_VIDEO_BPP8))
+ if (bpix == VIDEO_BPP8 && CONFIG_IS_ENABLED(VIDEO_BPP8))
return 0;
- else if (bpix == VIDEO_BPP16 && IS_ENABLED(CONFIG_VIDEO_BPP16))
+ else if (bpix == VIDEO_BPP16 && CONFIG_IS_ENABLED(VIDEO_BPP16))
return 0;
- else if (bpix == VIDEO_BPP32 && IS_ENABLED(CONFIG_VIDEO_BPP32))
+ else if (bpix == VIDEO_BPP32 && CONFIG_IS_ENABLED(VIDEO_BPP32))
return 0;
else
return -ENOSYS;
diff --git a/drivers/video/vidconsole-uclass.c
b/drivers/video/vidconsole-uclass.c
index 1225de2333..a21fde0e1d 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -86,7 +86,7 @@ static void vidconsole_newline(struct udevice *dev)
struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
struct udevice *vid_dev = dev->parent;
struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev);
- const int rows = CONFIG_CONSOLE_SCROLL_LINES;
+ const int rows = CONFIG_VAL(CONSOLE_SCROLL_LINES);
int i, ret;
priv->xcur_frac = priv->xstart_frac;
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index da89f43144..8396bdfb11 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -132,7 +132,7 @@ int video_reserve(ulong *addrp)
/* Allocate space for PCI video devices in case there were not bound */
if (*addrp == gd->video_top)
- *addrp -= CONFIG_VIDEO_PCI_DEFAULT_FB_SIZE;
+ *addrp -= CONFIG_VAL(VIDEO_PCI_DEFAULT_FB_SIZE);
gd->video_bottom = *addrp;
gd->fb_base = *addrp;
@@ -149,7 +149,7 @@ int video_fill(struct udevice *dev, u32 colour)
switch (priv->bpix) {
case VIDEO_BPP16:
- if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ if (CONFIG_IS_ENABLED(VIDEO_BPP16)) {
u16 *ppix = priv->fb;
u16 *end = priv->fb + priv->fb_size;
@@ -158,7 +158,7 @@ int video_fill(struct udevice *dev, u32 colour)
break;
}
case VIDEO_BPP32:
- if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ if (CONFIG_IS_ENABLED(VIDEO_BPP32)) {
u32 *ppix = priv->fb;
u32 *end = priv->fb + priv->fb_size;
@@ -212,14 +212,14 @@ u32 video_index_to_colour(struct video_priv *priv,
unsigned int idx)
{
switch (priv->bpix) {
case VIDEO_BPP16:
- if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ if (CONFIG_IS_ENABLED(VIDEO_BPP16)) {
return ((colours[idx].r >> 3) << 11) |
((colours[idx].g >> 2) << 5) |
((colours[idx].b >> 3) << 0);
}
break;
case VIDEO_BPP32:
- if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ if (CONFIG_IS_ENABLED(VIDEO_BPP32)) {
if (priv->format == VIDEO_X2R10G10B10)
return (colours[idx].r << 22) |
(colours[idx].g << 12) |
@@ -513,8 +513,8 @@ static int video_post_probe(struct udevice *dev)
return ret;
}
- if (IS_ENABLED(CONFIG_VIDEO_LOGO) &&
- !IS_ENABLED(CONFIG_SPLASH_SCREEN) && !plat->hide_logo) {
+ if (CONFIG_IS_ENABLED(VIDEO_LOGO) &&
+ !CONFIG_IS_ENABLED(SPLASH_SCREEN) && !plat->hide_logo) {
ret = show_splash(dev);
if (ret) {
log_debug("Cannot show splash screen\n");
diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c
index 6188a13e44..47e52c4f69 100644
--- a/drivers/video/video_bmp.c
+++ b/drivers/video/video_bmp.c
@@ -320,7 +320,7 @@ int video_bmp_display(struct u
[PATCH V7 08/14] cmd: bmp: Split bmp commands and functions
To enable splash screen at SPL, need to compile cmd/bmp.c which also
includes bmp commands, since SPL doesn't use commands split bmp.c into
common/bmp.c which includes all bmp functions and cmd/bmp.c which only
contains bmp commands.
Add function delclaration for bmp_info in video.h.
Signed-off-by: Nikhil M Jain
Reviewed-by: Simon Glass
---
V7:
- No change.
V6:
- Fix commit message.
- Remove unused header files.
V5:
- Rename cmd/bmp_cmd to cmd/bmp.
V4:
- No change.
V3 (patch introduced):
- Split bmp functions and commands.
cmd/bmp.c | 162 +---
common/bmp.c| 153 +
include/video.h | 8 +++
3 files changed, 163 insertions(+), 160 deletions(-)
create mode 100644 common/bmp.c
diff --git a/cmd/bmp.c b/cmd/bmp.c
index 46d0d916e8..8f43a40daf 100644
--- a/cmd/bmp.c
+++ b/cmd/bmp.c
@@ -9,84 +9,12 @@
*/
#include
-#include
#include
-#include
-#include
#include
-#include
-#include
#include
#include
#include
-#include
-
-static int bmp_info (ulong addr);
-
-/*
- * Allocate and decompress a BMP image using gunzip().
- *
- * Returns a pointer to the decompressed image data. This pointer is
- * aligned to 32-bit-aligned-address + 2.
- * See doc/README.displaying-bmps for explanation.
- *
- * The allocation address is passed to 'alloc_addr' and must be freed
- * by the caller after use.
- *
- * Returns NULL if decompression failed, or if the decompressed data
- * didn't contain a valid BMP signature.
- */
-#ifdef CONFIG_VIDEO_BMP_GZIP
-struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
-void **alloc_addr)
-{
- void *dst;
- unsigned long len;
- struct bmp_image *bmp;
-
- /*
-* Decompress bmp image
-*/
- len = CONFIG_VIDEO_LOGO_MAX_SIZE;
- /* allocate extra 3 bytes for 32-bit-aligned-address + 2 alignment */
- dst = malloc(CONFIG_VIDEO_LOGO_MAX_SIZE + 3);
- if (!dst) {
- puts("Error: malloc in gunzip failed!\n");
- return NULL;
- }
-
- /* align to 32-bit-aligned-address + 2 */
- bmp = dst + 2;
-
- if (gunzip(bmp, CONFIG_VIDEO_LOGO_MAX_SIZE, map_sysmem(addr, 0),
- &len)) {
- free(dst);
- return NULL;
- }
- if (len == CONFIG_VIDEO_LOGO_MAX_SIZE)
- puts("Image could be truncated (increase
CONFIG_VIDEO_LOGO_MAX_SIZE)!\n");
-
- /*
-* Check for bmp mark 'BM'
-*/
- if (!((bmp->header.signature[0] == 'B') &&
- (bmp->header.signature[1] == 'M'))) {
- free(dst);
- return NULL;
- }
-
- debug("Gzipped BMP image detected!\n");
-
- *alloc_addr = dst;
- return bmp;
-}
-#else
-struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
-void **alloc_addr)
-{
- return NULL;
-}
-#endif
+#include
static int do_bmp_info(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
@@ -137,7 +65,7 @@ static int do_bmp_display(struct cmd_tbl *cmdtp, int flag,
int argc,
return CMD_RET_USAGE;
}
-return (bmp_display(addr, x, y));
+ return (bmp_display(addr, x, y));
}
static struct cmd_tbl cmd_bmp_sub[] = {
@@ -145,22 +73,6 @@ static struct cmd_tbl cmd_bmp_sub[] = {
U_BOOT_CMD_MKENT(display, 5, 0, do_bmp_display, "", ""),
};
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-void bmp_reloc(void) {
- fixup_cmdtable(cmd_bmp_sub, ARRAY_SIZE(cmd_bmp_sub));
-}
-#endif
-
-/*
- * Subroutine: do_bmp
- *
- * Description: Handler for 'bmp' command..
- *
- * Inputs: argv[1] contains the subcommand
- *
- * Return: None
- *
- */
static int do_bmp(struct cmd_tbl *cmdtp, int flag, int argc, char *const
argv[])
{
struct cmd_tbl *c;
@@ -183,73 +95,3 @@ U_BOOT_CMD(
"info - display image info\n"
"bmp display [x y] - display image at x,y"
);
-
-/*
- * Subroutine: bmp_info
- *
- * Description: Show information about bmp file in memory
- *
- * Inputs: addraddress of the bmp file
- *
- * Return: None
- *
- */
-static int bmp_info(ulong addr)
-{
- struct bmp_image *bmp = (struct bmp_image *)map_sysmem(addr, 0);
- void *bmp_alloc_addr = NULL;
- unsigned long len;
-
- if (!((bmp->header.signature[0]=='B') &&
- (bmp->header.signature[1]=='M')))
- bmp = gunzip_bmp(addr, &len, &bmp_alloc_addr);
-
- if (bmp == NULL) {
- printf("There is no valid bmp file at the given address\n");
- return 1;
- }
-
- printf("Image size: %d x %d\n", le32_to_cpu(bmp->header.width),
- le32_to_cpu(bmp->header.height));
- printf("Bits per pixel: %d\n", le16_to_cpu(bmp->header.bit_count));
- printf("Compression : %d\n", le32_to_cpu(bmp->he
[PATCH V7 13/14] board: ti: am62x: evm: OSPI support for splash screen
Add ospi boot media support to load splash image from OSPI memory,
add offset to read image from ospi and necessary flags defininig type
of storage and storage device.
Use CONFIG_IS_ENBALED to use the splash locations at SPL and u-boot
proper.
Signed-off-by: Nikhil M Jain
Reviewed-by: Simon Glass
Reviewed-by: Devarsh Thakkar
---
V7:
- Add Reviewed-by tag.
V6:
- No change.
V5:
- Replace #ifdef with #if.
- Add Reviewed-by tag.
V4:
- Added Reviewed-by tag.
V3:
- Enable splash location at SPL.
V2:
- No change.
board/ti/am62x/evm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index 584b4ec552..fd58ece29c 100644
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -20,8 +20,14 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SPLASH_SCREEN
+#if CONFIG_IS_ENABLED(SPLASH_SCREEN)
static struct splash_location default_splash_locations[] = {
+ {
+ .name = "sf",
+ .storage = SPLASH_STORAGE_SF,
+ .flags = SPLASH_STORAGE_RAW,
+ .offset = 0x70,
+ },
{
.name = "mmc",
.storage= SPLASH_STORAGE_MMC,
--
2.34.1
[PATCH 0/3] J7 merge HS configs
This series depends on the fixes provided for j721e as that series also includes some base support for running the other HS platforms. Link for dependent series - https://lore.kernel.org/u-boot/20230324-j721e-upstream-hs-v6-0-5aa43a481...@ti.com/ Signed-off-by: Manorit Chawdhry --- Manorit Chawdhry (3): configs: j721s2: Merge the HS and non-HS defconfigs Kconfig: j721s2: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region configs: j7200: Merge the HS and non-HS defconfigs MAINTAINERS | 4 - arch/arm/mach-k3/Kconfig| 2 +- configs/j7200_evm_a72_defconfig | 3 +- configs/j7200_evm_r5_defconfig | 1 + configs/j7200_hs_evm_a72_defconfig | 204 -- configs/j7200_hs_evm_r5_defconfig | 170 - configs/j721s2_evm_a72_defconfig| 3 +- configs/j721s2_evm_r5_defconfig | 1 + configs/j721s2_hs_evm_a72_defconfig | 212 configs/j721s2_hs_evm_r5_defconfig | 175 - 10 files changed, 7 insertions(+), 768 deletions(-) --- base-commit: 4ab3044bb08dbfebcccdf5aa091492a0cd7c6af6 change-id: 20230405-j721s2-hs-evm-upstream-bad9551303cd Best regards, -- Manorit Chawdhry
[PATCH 1/3] configs: j721s2: Merge the HS and non-HS defconfigs
K3 devices have runtime type board detection. Make the default defconfig
include the secure configuration. Then remove the HS specific config.
Non-HS devices will continue to boot due to runtime device type detection.
If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS
devices these can be ignored.
Signed-off-by: Manorit Chawdhry
---
MAINTAINERS | 2 -
configs/j721s2_evm_a72_defconfig| 3 +-
configs/j721s2_evm_r5_defconfig | 1 +
configs/j721s2_hs_evm_a72_defconfig | 212
configs/j721s2_hs_evm_r5_defconfig | 175 -
5 files changed, 3 insertions(+), 390 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 84a21da6302b..c0bde1a0ac4a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1463,8 +1463,6 @@ F:configs/am65x_hs_evm_r5_defconfig
F: configs/am65x_hs_evm_a53_defconfig
F: configs/j7200_hs_evm_a72_defconfig
F: configs/j7200_hs_evm_r5_defconfig
-F: configs/j721s2_hs_evm_a72_defconfig
-F: configs/j721s2_hs_evm_r5_defconfig
TPM DRIVERS
M: Ilias Apalodimas
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index eae4c109e55c..44f22d587438 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x200
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
@@ -30,7 +31,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run
get_overlaystring; run run_fit; else; run get_kern_${boot}; run
get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 343e3c16305f..7416ba2d38d7 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x200
CONFIG_SYS_MALLOC_F_LEN=0x1
CONFIG_SPL_GPIO=y
diff --git a/configs/j721s2_hs_evm_a72_defconfig
b/configs/j721s2_hs_evm_a72_defconfig
deleted file mode 100644
index dff12ab82b81..
--- a/configs/j721s2_hs_evm_a72_defconfig
+++ /dev/null
@@ -1,212 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_LEN=0x200
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_J721S2=y
-CONFIG_TARGET_J721S2_A72_EVM=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048
-CONFIG_ENV_SIZE=0x2
-CONFIG_ENV_OFFSET=0x68
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x8008
-CONFIG_DM_RESET=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x8200
-CONFIG_ENV_OFFSET_REDUND=0x6A
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
-CONFIG_LOGLEVEL=7
-CONFIG_SPL_MAX_SIZE=0xc
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80a0
-CONFIG_SPL_BSS_MAX_SIZE=0x8
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
-CONFIG_SPL_DMA=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
-CONFIG_SPL_THERMAL=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_REMOT
[PATCH 2/3] Kconfig: j721s2: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region
On K3 HS-SE devices all the firewalls are locked by default until sysfw comes up. Rom configures some of the firewall for its usage along with the SRAM for R5 but the PSRAM region is still locked. The K3 MCU Scratchpad for j721s2 was set to a PSRAM region triggering the firewall exception before sysfw came up. The exception started happening after adding multi dtb support that accesses the scratchpad for reading EEPROM contents. Old map: ┌─┐ 0x41c0 │ SPL │ ├─┤ 0x41c61f20 (approx) │STACK│ ├─┤ 0x41c65f20 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─┤ gd->malloc_base = 0x41c66000 │HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x1 │ ├─┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41c76000) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ ├─┤ (0x41c8) │ DM DATA │ ├─┤ (0x41c84130) (approx) │EMPTY│ └─┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX (0x41cffbfc) New map: ┌─┐ 0x41c0 │ SPL │ ├─┤ 0x41c61f20 (approx) │STACK│ ├─┤ 0x41c65f20 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─┤ gd->malloc_base = 0x41c66000 │HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x1 │ ├─┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41c76000) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ ├─┤ (0x41c8) │ DM DATA │ ├─┤ (0x41c84130) (approx) │EMPTY│ ├─┤ SYS_K3_MCU_SCRATCHPAD_BASE │ SCRATCHPAD │ (0x41cff9fc) │ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │ └─┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX (0x41cffbfc) Signed-off-by: Manorit Chawdhry --- arch/arm/mach-k3/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index bae0a827c29f..bf1c3c51a41c 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -52,7 +52,7 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE config SYS_K3_MCU_SCRATCHPAD_BASE hex default 0x4028 if SOC_K3_AM654 - default 0x4028 if SOC_K3_J721S2 + default 0x41cff9fc if SOC_K3_J721S2 default 0x41cff9fc if SOC_K3_J721E help Describes the base address of MCU Scratchpad RAM. -- 2.34.1
[PATCH 3/3] configs: j7200: Merge the HS and non-HS defconfigs
K3 devices have runtime type board detection. Make the default defconfig
include the secure configuration. Then remove the HS specific config.
Non-HS devices will continue to boot due to runtime device type detection.
If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS
devices these can be ignored.
Signed-off-by: Manorit Chawdhry
---
MAINTAINERS| 2 -
configs/j7200_evm_a72_defconfig| 3 +-
configs/j7200_evm_r5_defconfig | 1 +
configs/j7200_hs_evm_a72_defconfig | 204 -
configs/j7200_hs_evm_r5_defconfig | 170 ---
5 files changed, 3 insertions(+), 377 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index c0bde1a0ac4a..d5e07e244ad7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1461,8 +1461,6 @@ F:configs/k2g_hs_evm_defconfig
F: configs/k2l_hs_evm_defconfig
F: configs/am65x_hs_evm_r5_defconfig
F: configs/am65x_hs_evm_a53_defconfig
-F: configs/j7200_hs_evm_a72_defconfig
-F: configs/j7200_hs_evm_r5_defconfig
TPM DRIVERS
M: Ilias Apalodimas
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 74903138e5ed..e33b3f17cbb1 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x200
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
@@ -32,7 +33,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run
get_overlaystring; run run_fit; else; run get_kern_${boot}; run
get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 00ec48b83b78..dd4454943c36 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x200
CONFIG_SYS_MALLOC_F_LEN=0x7
CONFIG_SPL_GPIO=y
diff --git a/configs/j7200_hs_evm_a72_defconfig
b/configs/j7200_hs_evm_a72_defconfig
deleted file mode 100644
index e4f3c462ca5e..
--- a/configs/j7200_hs_evm_a72_defconfig
+++ /dev/null
@@ -1,204 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_LEN=0x200
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_J721E=y
-CONFIG_TARGET_J7200_A72_EVM=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048
-CONFIG_ENV_SIZE=0x2
-CONFIG_ENV_OFFSET=0x68
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x8008
-CONFIG_DM_RESET=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x8200
-CONFIG_ENV_OFFSET_REDUND=0x6A
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
-CONFIG_LOGLEVEL=7
-CONFIG_SPL_MAX_SIZE=0xc
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80a0
-CONFIG_SPL_BSS_MAX_SIZE=0x8
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
-CONFIG_SPL_DMA=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_UFS=y
-CONFIG_CMD_USB=y
-CONFIG
[PATCH 1/4] configs: am62x_evm_a53_defconfig: Changes in memory map to support SPL splash screen
To enable splash at A53 SPL, need to do memory map changes which
involves locate stack above malloc and have enough space to load bmp
image above stack. To load a 1920X1200 image a minimum of 8.8MB space is
needed, to support it move malloc down to 0x80b8 from 0x8048 and
bss to 0x80c8 to have 1MB buffer between malloc and BSS.
Observed SPL size 195KB, CONFIG_SPL_SIZE_LIMIT set to 256KB.
Observed stack size 1904Bytes, CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK set
to 2KB.
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE config sets stack above the malloc
and reports for stack overflow.
Memory map at A53 SPL before splash screen
0x8000+-+
|Empty 512 KB |
| |
0x8008+-+
| Text Base |
| 352 KB|
| |
0x800D8000+-+
| |
| |
|Empty 3.6MB |
| |
| |
0x80477660+-+
|Stack 2 KB |
0x80477e60+-+
| GD 416 Bytes|
0x80478000+-+
|Malloc 352 KB|
| |
0x8048+-+
| |
| |
| |
| |
| Empty 5.5 MB |
| |
| |
| |
| |
0x80a0+-+
| |
| BSS 512 KB |
| |
0x80a8+-+
| |
| |
| |
| |
| Empty 5.5 MB |
| |
| |
| |
| |
0x8100+-+FIT Image load address
New memory map with splash screen at SPL
0x8000+-+
|Empty 512 KB |
| |
0x8008+-+
| Text Base |
| 352 KB|
| |
0x800D8000+-+
|Empty 1.1MB |
| |
0x8020+-+
| |
| |
| |
| BMP Image Load|
| |
| 9.4 MB|
| |
| |
| |
| |
| |
| |
0x80b77660+-+
| Stack 2KB |
0x80b77e60+-+
|GD 416 Bytes |
0x80b78000+-+
| |
|Malloc 352KB |
0x80b8+-+
| |
| Empty 1 MB |
| |
0x80c8+-+
| BSS 512 KB |
| |
0x80d0+-+
| |
| |
|Empty 3.0 MB |
| |
| |
| |
0x8100+-+FIT Image load addressi
Signed-off-by: Nikhil M Jain
---
configs/am62x_evm_a53_defconfig | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index cc9c8eab3e..6490b57a0f 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -8,14 +8,18 @@ CONFIG_SOC_K3_AM625=y
CONFIG_K3_ATF_LOAD_ADDR=0x9e78
CONFIG_TARGET_AM625_A53_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b8
+CONFIG_SF_DEFAULT_SPEED=2500
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk"
CONFIG_SPL_TEXT_BASE=0x8008
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x8200
+CONFIG_SPL_SIZE_LIMIT=0x4
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -27,8 +31,9 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern;
setenv fdtfile ti/${name_fdt}; run distro_bootcmd"
CONFIG_SPL_M
[PATCH 2/4] board: ti: am62x: am62x: Change splashimage and splashsource
Change splashimage which is bmp image loadaddr to 0x8020 since stack
is situated at 0x80477660 as splash framework requires bmp image to be
present above stack.
Change splashsource to sf to support loading bmp image from ospi flash
memory.
Signed-off-by: Nikhil M Jain
---
board/ti/am62x/am62x.env | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env
index e4e64fa637..5ac15fd240 100644
--- a/board/ti/am62x/am62x.env
+++ b/board/ti/am62x/am62x.env
@@ -33,6 +33,6 @@ get_fit_mmc=load mmc ${bootpart} ${addr_fit}
partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}
splashfile=ti.gz
-splashimage=0x8200
+splashimage=0x8020
splashpos=m,m
-splashsource=mmc
+splashsource=sf
--
2.34.1
[PATCH 3/4] board: ti: am62x: evm: Add necessary functions to call splash screen
To enable splash screen on AM62x at a53 SPL setup DRAM, set page table,
enable cache to allow copying of bmp image to frame buffer and display
it using splash_display.
Signed-off-by: Nikhil M Jain
---
board/ti/am62x/evm.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index 20b2a70122..e3c80c5c67 100644
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -9,6 +9,7 @@
#include
#include
+#include
#include
#include
#include
@@ -53,6 +54,44 @@ int dram_init_banksize(void)
}
#if defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_SPL_VIDEO_TIDSS
+static int setup_dram(void)
+{
+ dram_init();
+ dram_init_banksize();
+ gd->ram_base = CFG_SYS_SDRAM_BASE;
+ gd->ram_top = gd->ram_base + gd->ram_size;
+ gd->relocaddr = gd->ram_top;
+ return 0;
+}
+
+static int video_setup(void)
+{
+ ulong addr;
+ int ret;
+ addr = gd->relocaddr;
+
+ ret = video_reserve(&addr);
+ if (ret)
+ return ret;
+ debug("Reserving %luk for video at: %08lx\n",
+ ((unsigned long)gd->relocaddr - addr) >> 10, addr);
+ gd->relocaddr = addr;
+ return 0;
+}
+
+#endif
+void spl_board_init(void)
+{
+#if defined(CONFIG_SPL_VIDEO_TIDSS)
+ setup_dram();
+ arch_reserve_mmu();
+ video_setup();
+ enable_caches();
+ splash_display();
+#endif
+}
+
#if defined(CONFIG_K3_AM64_DDRSS)
static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
{
--
2.34.1
[PATCH 4/4] common: spl: spl: Remove video driver before u-boot proper
Add method to remove video driver before loading u-boot proper. When
bootstage changes from SPL to u-boot proper, noo method is called to
remove video driver, and at u-boot proper if video driver is not
enabled, the video driver starts displaying garbage on the screen,
because there is no reserved space for video and the frame buffer gets
u-boot proper data written.
Signed-off-by: Nikhil M Jain
---
common/spl/spl.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index a630e79866..72078a8ebc 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -35,6 +35,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -889,6 +891,19 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
debug("Failed to stash bootstage: err=%d\n", ret);
#endif
+#if defined(CONFIG_SPL_VIDEO)
+ struct udevice *dev;
+ int rc;
+
+ rc = uclass_find_device(UCLASS_VIDEO, 0, &dev);
+ if (!rc && dev) {
+ rc = device_remove(dev, DM_REMOVE_NORMAL);
+ if (rc)
+ printf("Cannot remove video device '%s' (err=%d)\n",
+ dev->name, rc);
+ }
+#endif
+
spl_board_prepare_for_boot();
jump_to_image_no_args(&spl_image);
}
--
2.34.1
[PATCH v2 00/10] sunxi: Update H616 DRAM driver
Current H616 DRAM driver is completely customized to Orange Pi Zero2 board, which is only one of two H616 boards supported by U-Boot. Needless to say, this is not ideal for adding new boards. With changes in this series, all DDR3 boards are supported and all that is needed is just vendor DRAM values extracted from Android image. New DRAM types should also be easier to support, since a lot of constants used before are not really DRAM type dependent. Changes were verified by decompiling driver and generated values were compared to previous, hard coded ones. This was done without dram_para structures, so compiler was able to heavily optimize code and produce constants. Please take a look. Best regards, Jernej Changes from v1: - added tags - updated dram config macros to have 8 or 4 nibbles - renamed unknown macros to something useful when known - removed unknown macro when not known what it does - added patch 9 and 10 which introduces TPR2 (needed on one h313 board) - update commit subjects Jernej Skrabec (10): sunxi: Fix write to H616 DRAM CR register sunxi: cosmetic: Fix H616 DRAM driver code style sunxi: parameterize H616 DRAM ODT values sunxi: Convert H616 DRAM options to single setting sunxi: Always configure ODT on H616 DRAM sunxi: Make bit delay function in H616 DRAM code void sunxi: Parameterize bit delay code in H616 DRAM driver sunxi: Parameterize "unknown feature" in H616 DRAM driver sunxi: Parameterize some of H616 DDR3 timings sunxi: Add TPR2 parameter for H616 DRAM driver .../include/asm/arch-sunxi/dram_sun50i_h616.h | 17 + arch/arm/mach-sunxi/Kconfig | 83 +-- arch/arm/mach-sunxi/dram_sun50i_h616.c| 530 -- .../mach-sunxi/dram_timings/h616_ddr3_1333.c | 20 +- configs/orangepi_zero2_defconfig | 8 +- configs/x96_mate_defconfig| 7 + 6 files changed, 442 insertions(+), 223 deletions(-) -- 2.40.0
[PATCH v2 01/10] sunxi: Fix write to H616 DRAM CR register
Vendor DRAM code actually writes to whole CR register and not just sets bit 31 in mctl_ctrl_init(). Just to be safe, do that here too. Acked-by: Andre Przywara Signed-off-by: Jernej Skrabec --- arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 454c845a0010..039e76224367 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -873,7 +873,7 @@ static bool mctl_ctrl_init(struct dram_para *para) writel(0x06000400, &mctl_ctl->unk_0x3240); writel(0x06000400, &mctl_ctl->unk_0x4240); - setbits_le32(&mctl_com->cr, BIT(31)); + writel(BIT(31), &mctl_com->cr); mctl_set_addrmap(para); -- 2.40.0
[PATCH v2 02/10] sunxi: cosmetic: Fix H616 DRAM driver code style
Fix code style for pointer declaration. This is just cosmetic change to
avoid checkpatch errors in later commits.
Reviewed-by: Andre Przywara
Signed-off-by: Jernej Skrabec
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 74 +-
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 039e76224367..49983bf7a1b8 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -285,7 +285,7 @@ static bool mctl_phy_write_leveling(struct dram_para *para)
else
val = 3;
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
@@ -314,7 +314,7 @@ static bool mctl_phy_write_leveling(struct dram_para *para)
else
val = 3;
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x188),
val, val);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x188),
val, val);
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
}
@@ -398,26 +398,26 @@ static bool mctl_phy_read_training(struct dram_para *para)
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 6);
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 1);
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3)
result = false;
if (para->bus_full_width) {
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xa40),
0xc, 0xc);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa40),
0xc, 0xc);
if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3)
result = false;
}
- ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x898);
- ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x850);
+ ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x898);
+ ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x850);
for (i = 0; i < 9; i++) {
val1 = readl(&ptr1[i]);
val2 = readl(&ptr2[i]);
if (val1 - val2 <= 6)
result = false;
}
- ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x8bc);
- ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x874);
+ ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8bc);
+ ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x874);
for (i = 0; i < 9; i++) {
val1 = readl(&ptr1[i]);
val2 = readl(&ptr2[i]);
@@ -426,8 +426,8 @@ static bool mctl_phy_read_training(struct dram_para *para)
}
if (para->bus_full_width) {
- ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa98);
- ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa50);
+ ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa98);
+ ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa50);
for (i = 0; i < 9; i++) {
val1 = readl(&ptr1[i]);
val2 = readl(&ptr2[i]);
@@ -435,8 +435,8 @@ static bool mctl_phy_read_training(struct dram_para *para)
result = false;
}
- ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xabc);
- ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa74);
+ ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xabc);
+ ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa74);
for (i = 0; i < 9; i++) {
val1 = readl(&ptr1[i]);
val2 = readl(&ptr2[i]);
@@ -454,12 +454,12 @@ static bool mctl_phy_read_training(struct dram_para *para)
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 6);
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 1);
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x840),
0xc, 0xc);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x840),
0xc, 0xc);
if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3)
result = false;
if (para->bus_full_width) {
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE +
0xa40), 0xc, 0xc);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE +
0xa40), 0xc, 0xc);
if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3)
result = false;
}
@@ -488,26 +488,26 @@ static bool mctl_phy_write_training(struct dram_para
*para)
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x20);
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8e0
[PATCH v2 03/10] sunxi: parameterize H616 DRAM ODT values
While ODT values for same memory type are similar, they are not
necessary the same. Let's parameterize them and make parameter same as
in vendor DRAM settings. That way it will be easy to introduce new board
support.
Reviewed-by: Andre Przywara
Signed-off-by: Jernej Skrabec
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 3 +
arch/arm/mach-sunxi/Kconfig | 15 +
arch/arm/mach-sunxi/dram_sun50i_h616.c| 59 ---
configs/orangepi_zero2_defconfig | 3 +
configs/x96_mate_defconfig| 3 +
5 files changed, 61 insertions(+), 22 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index 134679d55205..c9e1f84bfcdd 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -144,6 +144,9 @@ struct dram_para {
u8 rows;
u8 ranks;
u8 bus_full_width;
+ u32 dx_odt;
+ u32 dx_dri;
+ u32 ca_dri;
};
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 6417aee944bc..14fb9a95905a 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -83,6 +83,21 @@ config DRAM_SUN50I_H616_UNKNOWN_FEATURE
---help---
Select this when DRAM on your H616 board needs this unknown
feature.
+
+config DRAM_SUN50I_H616_DX_ODT
+ hex "H616 DRAM DX ODT parameter"
+ help
+ DX ODT value from vendor DRAM settings.
+
+config DRAM_SUN50I_H616_DX_DRI
+ hex "H616 DRAM DX DRI parameter"
+ help
+ DX DRI value from vendor DRAM settings.
+
+config DRAM_SUN50I_H616_CA_DRI
+ hex "H616 DRAM CA DRI parameter"
+ help
+ CA DRI value from vendor DRAM settings.
endif
config SUN6I_PRCM
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 49983bf7a1b8..06a07dfbf9cc 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -234,37 +234,49 @@ static const u8 phy_init[] = {
0x09, 0x05, 0x18
};
-static void mctl_phy_configure_odt(void)
+static void mctl_phy_configure_odt(struct dram_para *para)
{
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x388);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x38c);
+ unsigned int val;
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x3c8);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x3cc);
+ val = para->dx_dri & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x388);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x38c);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x408);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x40c);
+ val = (para->dx_dri >> 8) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c8);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3cc);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x448);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x44c);
+ val = (para->dx_dri >> 16) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x408);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x40c);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x340);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x344);
+ val = (para->dx_dri >> 24) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x448);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x44c);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x348);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x34c);
+ val = para->ca_dri & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x340);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x344);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x380);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x384);
+ val = (para->ca_dri >> 8) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x348);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x34c);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x3c0);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x3c4);
+ val = para->dx_odt & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x380);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x384);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x400);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x404);
+ val = (para->dx_odt >> 8) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c0);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c4);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x440);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x444);
+ val = (para->dx_odt >> 16) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x400);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x404);
+
+ val = (para->dx_odt >> 24) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_
[PATCH v2 06/10] sunxi: Make bit delay function in H616 DRAM code void
Mentioned function result is always true and result isn't checked
anyway. Let's make it void.
Reviewed-by: Andre Przywara
Signed-off-by: Jernej Skrabec
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 7d2434309b07..3fe45845b78e 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -572,7 +572,7 @@ static bool mctl_phy_write_training(struct dram_para *para)
return result;
}
-static bool mctl_phy_bit_delay_compensation(struct dram_para *para)
+static void mctl_phy_bit_delay_compensation(struct dram_para *para)
{
u32 *ptr;
int i;
@@ -683,8 +683,6 @@ static bool mctl_phy_bit_delay_compensation(struct
dram_para *para)
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80);
}
-
- return true;
}
static bool mctl_phy_init(struct dram_para *para)
--
2.40.0
[PATCH v2 08/10] sunxi: Parameterize "unknown feature" in H616 DRAM driver
Part of the code, previously known as "unknown feature", also doesn't
have constant values. They are derived from TPR0 parameter in vendor
DRAM code.
Let's move that code to separate function and introduce TPR0 parameter
here too, to ease adding new boards.
Signed-off-by: Jernej Skrabec
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 1 +
arch/arm/mach-sunxi/Kconfig | 6 +++
arch/arm/mach-sunxi/dram_sun50i_h616.c| 47 ++-
configs/x96_mate_defconfig| 1 +
4 files changed, 44 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index 034ba98bc243..615532c6eebb 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -156,6 +156,7 @@ struct dram_para {
u32 dx_dri;
u32 ca_dri;
u32 odt_en;
+ u32 tpr0;
u32 tpr10;
u32 tpr11;
u32 tpr12;
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 7b38e83c2d7e..fe34755f88ec 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -73,6 +73,12 @@ config DRAM_SUN50I_H616_ODT_EN
help
ODT EN value from vendor DRAM settings.
+config DRAM_SUN50I_H616_TPR0
+ hex "H616 DRAM TPR0 parameter"
+ default 0x0
+ help
+ TPR0 value from vendor DRAM settings.
+
config DRAM_SUN50I_H616_TPR10
hex "H616 DRAM TPR10 parameter"
help
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index f5d8718fefff..44bb15367beb 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -773,6 +773,39 @@ static void mctl_phy_bit_delay_compensation(struct
dram_para *para)
}
}
+static void mctl_phy_ca_bit_delay_compensation(struct dram_para *para)
+{
+ u32 val, *ptr;
+ int i;
+
+ if (para->tpr0 & BIT(30))
+ val = (para->tpr0 >> 7) & 0x3e;
+ else
+ val = (para->tpr10 >> 3) & 0x1e;
+
+ ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x780);
+ for (i = 0; i < 32; i++)
+ writel(val, &ptr[i]);
+
+ val = (para->tpr10 << 1) & 0x1e;
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7dc);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e0);
+
+ /* following configuration is DDR3 specific */
+ val = (para->tpr10 >> 7) & 0x1e;
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7d4);
+ if (para->ranks == 2) {
+ val = (para->tpr10 >> 11) & 0x1e;
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x79c);
+ }
+ if (para->tpr0 & BIT(31)) {
+ val = (para->tpr0 << 1) & 0x3e;
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x78c);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a4);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
+ }
+}
+
static bool mctl_phy_init(struct dram_para *para)
{
struct sunxi_mctl_com_reg * const mctl_com =
@@ -807,17 +840,8 @@ static bool mctl_phy_init(struct dram_para *para)
for (i = 0; i < ARRAY_SIZE(phy_init); i++)
writel(phy_init[i], &ptr[i]);
- if (para->tpr10 & TPR10_CA_BIT_DELAY) {
- ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x780);
- for (i = 0; i < 32; i++)
- writel(0x16, &ptr[i]);
- writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x78c);
- writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7a4);
- writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7b8);
- writel(0x8, SUNXI_DRAM_PHY0_BASE + 0x7d4);
- writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7dc);
- writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7e0);
- }
+ if (para->tpr10 & TPR10_CA_BIT_DELAY)
+ mctl_phy_ca_bit_delay_compensation(para);
writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc);
writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c);
@@ -1110,6 +1134,7 @@ unsigned long sunxi_dram_init(void)
.dx_dri = CONFIG_DRAM_SUN50I_H616_DX_DRI,
.ca_dri = CONFIG_DRAM_SUN50I_H616_CA_DRI,
.odt_en = CONFIG_DRAM_SUN50I_H616_ODT_EN,
+ .tpr0 = CONFIG_DRAM_SUN50I_H616_TPR0,
.tpr10 = CONFIG_DRAM_SUN50I_H616_TPR10,
.tpr11 = CONFIG_DRAM_SUN50I_H616_TPR11,
.tpr12 = CONFIG_DRAM_SUN50I_H616_TPR12,
diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig
index acc64898da19..aedb3277022a 100644
--- a/configs/x96_mate_defconfig
+++ b/configs/x96_mate_defconfig
@@ -6,6 +6,7 @@ CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
CONFIG_DRAM_SUN50I_H616_CA_DRI=0x1c12
+CONFIG_DRAM_SUN50I_H616_TPR0=0xcc05
CONFIG_DRAM_SUN50I_H616_TPR10=0x2f0007
CONFIG_DRAM_SUN50I_H616_TPR11=0x
CONFIG_DRAM_SUN50I_
[PATCH v2 05/10] sunxi: Always configure ODT on H616 DRAM
Vendor H616 DRAM code always configure part which we call ODT configuration. Let's reflect that here too. Signed-off-by: Jernej Skrabec --- arch/arm/mach-sunxi/Kconfig| 2 +- arch/arm/mach-sunxi/dram_sun50i_h616.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 1b47a49f938c..4300d388e066 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -488,12 +488,12 @@ config DRAM_ZQ config DRAM_ODT_EN bool "sunxi dram odt enable" + depends on !MACH_SUN50I_H616 default y if MACH_SUN8I_A23 default y if MACH_SUNXI_H3_H5 default y if MACH_SUN8I_R40 default y if MACH_SUN50I default y if MACH_SUN50I_H6 - default y if MACH_SUN50I_H616 ---help--- Select this to enable dram odt (on die termination). diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 630c7c3be882..7d2434309b07 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -736,8 +736,7 @@ static bool mctl_phy_init(struct dram_para *para) writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc); writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c); - if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) - mctl_phy_configure_odt(para); + mctl_phy_configure_odt(para); clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 7, 0xa); -- 2.40.0
[PATCH v2 04/10] sunxi: Convert H616 DRAM options to single setting
Vendor DRAM settings use TPR10 parameter to enable various features.
There are many mores features that just those that are currently
mentioned. Since new will be added later and most are not known, let's
reuse value from vendor DRAM driver as-is. This will also help adding
support for new boards.
Signed-off-by: Jernej Skrabec
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 9 +
arch/arm/mach-sunxi/Kconfig | 38 +---
arch/arm/mach-sunxi/dram_sun50i_h616.c| 197 +-
configs/orangepi_zero2_defconfig | 5 +-
configs/x96_mate_defconfig| 1 +
5 files changed, 117 insertions(+), 133 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index c9e1f84bfcdd..dbdc6b694ec1 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -137,6 +137,14 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
#define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24)
#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16)
+#define TPR10_CA_BIT_DELAY BIT(16)
+#define TPR10_DX_BIT_DELAY0BIT(17)
+#define TPR10_DX_BIT_DELAY1BIT(18)
+#define TPR10_WRITE_LEVELING BIT(20)
+#define TPR10_READ_CALIBRATION BIT(21)
+#define TPR10_READ_TRAININGBIT(22)
+#define TPR10_WRITE_TRAINING BIT(23)
+
struct dram_para {
u32 clk;
enum sunxi_dram_type type;
@@ -147,6 +155,7 @@ struct dram_para {
u32 dx_odt;
u32 dx_dri;
u32 ca_dri;
+ u32 tpr10;
};
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 14fb9a95905a..1b47a49f938c 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -52,38 +52,6 @@ config DRAM_SUN50I_H616
like H616.
if DRAM_SUN50I_H616
-config DRAM_SUN50I_H616_WRITE_LEVELING
- bool "H616 DRAM write leveling"
- ---help---
- Select this when DRAM on your H616 board needs write leveling.
-
-config DRAM_SUN50I_H616_READ_CALIBRATION
- bool "H616 DRAM read calibration"
- ---help---
- Select this when DRAM on your H616 board needs read calibration.
-
-config DRAM_SUN50I_H616_READ_TRAINING
- bool "H616 DRAM read training"
- ---help---
- Select this when DRAM on your H616 board needs read training.
-
-config DRAM_SUN50I_H616_WRITE_TRAINING
- bool "H616 DRAM write training"
- ---help---
- Select this when DRAM on your H616 board needs write training.
-
-config DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION
- bool "H616 DRAM bit delay compensation"
- ---help---
- Select this when DRAM on your H616 board needs bit delay
- compensation.
-
-config DRAM_SUN50I_H616_UNKNOWN_FEATURE
- bool "H616 DRAM unknown feature"
- ---help---
- Select this when DRAM on your H616 board needs this unknown
- feature.
-
config DRAM_SUN50I_H616_DX_ODT
hex "H616 DRAM DX ODT parameter"
help
@@ -98,6 +66,12 @@ config DRAM_SUN50I_H616_CA_DRI
hex "H616 DRAM CA DRI parameter"
help
CA DRI value from vendor DRAM settings.
+
+config DRAM_SUN50I_H616_TPR10
+ hex "H616 DRAM TPR10 parameter"
+ help
+ TPR10 value from vendor DRAM settings. It tells which features
+ should be configured, like write leveling, read calibration, etc.
endif
config SUN6I_PRCM
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 06a07dfbf9cc..630c7c3be882 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -577,109 +577,112 @@ static bool mctl_phy_bit_delay_compensation(struct
dram_para *para)
u32 *ptr;
int i;
- clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
- setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
- clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
+ if (para->tpr10 & TPR10_DX_BIT_DELAY1) {
+ clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
+ setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
+ clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
- ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x484);
- for (i = 0; i < 9; i++) {
- writel_relaxed(0x16, ptr);
- writel_relaxed(0x16, ptr + 0x30);
- ptr += 2;
- }
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4d0);
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x590);
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4cc);
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x58c);
+ ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x484);
+ for (i = 0; i < 9; i++) {
+ writel_relaxed(0x16, ptr);
+ writel_relaxed(0x16, ptr + 0x30);
+ ptr += 2;
+ }
+ writel_relaxed(0x
[PATCH v2 09/10] sunxi: Parameterize some of H616 DDR3 timings
Currently twr2rd, trd2wr and twtp are constants, but according to vendor driver they are calculated from other values. Do that here too, in preparation for later introduction of new parameter. While at it, introduce constant for t_wr_lat, which was incorrectly calculated from tcl before. Signed-off-by: Jernej Skrabec --- arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c index 8f508344bc17..f109e920820b 100644 --- a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c @@ -48,10 +48,11 @@ void mctl_set_timing_params(struct dram_para *para) u8 tcl = 7;/* JEDEC: CL / 2 => 6 */ u8 tcwl = 5;/* JEDEC: 8 */ u8 t_rdata_en = 9;/* ? */ + u8 t_wr_lat = 5;/* ? */ - u8 twtp = 14; /* (WL + BL / 2 + tWR) / 2 */ - u8 twr2rd = trtp + 7; /* (WL + BL / 2 + tWTR) / 2 */ - u8 trd2wr = 5;/* (RL + BL / 2 + 2 - WL) / 2 */ + u8 twtp = tcl + 2 + tcwl; /* (WL + BL / 2 + tWR) / 2 */ + u8 twr2rd = trtp + 2 + tcwl; /* (WL + BL / 2 + tWTR) / 2 */ + u8 trd2wr = tcl + 3 - tcwl; /* (RL + BL / 2 + 2 - WL) / 2 */ /* set DRAM timing */ writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, @@ -85,7 +86,7 @@ void mctl_set_timing_params(struct dram_para *para) clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); /* Configure DFI timing */ - writel((tcl - 2) | 0x200 | (t_rdata_en << 16) | 0x808000, + writel(t_wr_lat | 0x200 | (t_rdata_en << 16) | 0x808000, &mctl_ctl->dfitmg0); writel(0x100202, &mctl_ctl->dfitmg1); -- 2.40.0
[PATCH v2 10/10] sunxi: Add TPR2 parameter for H616 DRAM driver
It turns out that some H616 and related SoCs (like H313) need TPR2
parameter for proper working. Add it.
Signed-off-by: Jernej Skrabec
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 1 +
arch/arm/mach-sunxi/Kconfig | 6 ++
arch/arm/mach-sunxi/dram_sun50i_h616.c| 75 +--
.../mach-sunxi/dram_timings/h616_ddr3_1333.c | 17 -
4 files changed, 75 insertions(+), 24 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index 615532c6eebb..6db869c0985b 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -157,6 +157,7 @@ struct dram_para {
u32 ca_dri;
u32 odt_en;
u32 tpr0;
+ u32 tpr2;
u32 tpr10;
u32 tpr11;
u32 tpr12;
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index fe34755f88ec..6be8a4de53fe 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -79,6 +79,12 @@ config DRAM_SUN50I_H616_TPR0
help
TPR0 value from vendor DRAM settings.
+config DRAM_SUN50I_H616_TPR2
+ hex "H616 DRAM TPR2 parameter"
+ default 0x0
+ help
+ TPR2 value from vendor DRAM settings.
+
config DRAM_SUN50I_H616_TPR10
hex "H616 DRAM TPR10 parameter"
help
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 44bb15367beb..1f9416d6eaf5 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -788,21 +788,37 @@ static void mctl_phy_ca_bit_delay_compensation(struct
dram_para *para)
writel(val, &ptr[i]);
val = (para->tpr10 << 1) & 0x1e;
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7d8);
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7dc);
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e0);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7f4);
/* following configuration is DDR3 specific */
val = (para->tpr10 >> 7) & 0x1e;
- writel(val, SUNXI_DRAM_PHY0_BASE + 0x7d4);
- if (para->ranks == 2) {
- val = (para->tpr10 >> 11) & 0x1e;
- writel(val, SUNXI_DRAM_PHY0_BASE + 0x79c);
- }
- if (para->tpr0 & BIT(31)) {
- val = (para->tpr0 << 1) & 0x3e;
- writel(val, SUNXI_DRAM_PHY0_BASE + 0x78c);
- writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a4);
- writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
+ if (para->tpr2 & 1) {
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x794);
+ if (para->ranks == 2) {
+ val = (para->tpr10 >> 11) & 0x1e;
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e4);
+ }
+ if (para->tpr0 & BIT(31)) {
+ val = (para->tpr0 << 1) & 0x3e;
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x790);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7cc);
+ }
+ } else {
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7d4);
+ if (para->ranks == 2) {
+ val = (para->tpr10 >> 11) & 0x1e;
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x79c);
+ }
+ if (para->tpr0 & BIT(31)) {
+ val = (para->tpr0 << 1) & 0x3e;
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x78c);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a4);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
+ }
}
}
@@ -812,7 +828,7 @@ static bool mctl_phy_init(struct dram_para *para)
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- u32 val, *ptr;
+ u32 val, val2, *ptr, mr0, mr2;
int i;
if (para->bus_full_width)
@@ -821,20 +837,28 @@ static bool mctl_phy_init(struct dram_para *para)
val = 3;
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3c, 0xf, val);
- writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x14);
- writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x35c);
- writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x368);
- writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x374);
+ if (para->tpr2 & 0x100) {
+ val = 9;
+ val2 = 7;
+ } else {
+ val = 13;
+ val2 = 9;
+ }
+
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x14);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x35c);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x368);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x374);
writel(0, SUNXI_DRAM_PHY0_BASE + 0x18);
writel(0, SUNXI_DRAM_PHY0_BASE + 0x360);
writel(0, SUNXI_DRAM_
[PATCH v2 07/10] sunxi: Parameterize bit delay code in H616 DRAM driver
These values are highly board specific and thus make sense to add
parameter for them. To ease adding support for new boards, let's make
them same as in vendor DRAM settings.
Signed-off-by: Jernej Skrabec
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 3 +
arch/arm/mach-sunxi/Kconfig | 18 ++
arch/arm/mach-sunxi/dram_sun50i_h616.c| 189 +-
configs/x96_mate_defconfig| 2 +
4 files changed, 163 insertions(+), 49 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index dbdc6b694ec1..034ba98bc243 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -155,7 +155,10 @@ struct dram_para {
u32 dx_odt;
u32 dx_dri;
u32 ca_dri;
+ u32 odt_en;
u32 tpr10;
+ u32 tpr11;
+ u32 tpr12;
};
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 4300d388e066..7b38e83c2d7e 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -67,11 +67,29 @@ config DRAM_SUN50I_H616_CA_DRI
help
CA DRI value from vendor DRAM settings.
+config DRAM_SUN50I_H616_ODT_EN
+ hex "H616 DRAM ODT EN parameter"
+ default 0x1
+ help
+ ODT EN value from vendor DRAM settings.
+
config DRAM_SUN50I_H616_TPR10
hex "H616 DRAM TPR10 parameter"
help
TPR10 value from vendor DRAM settings. It tells which features
should be configured, like write leveling, read calibration, etc.
+
+config DRAM_SUN50I_H616_TPR11
+ hex "H616 DRAM TPR11 parameter"
+ default 0x0
+ help
+ TPR11 value from vendor DRAM settings.
+
+config DRAM_SUN50I_H616_TPR12
+ hex "H616 DRAM TPR12 parameter"
+ default 0x0
+ help
+ TPR12 value from vendor DRAM settings.
endif
config SUN6I_PRCM
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 3fe45845b78e..f5d8718fefff 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -574,7 +574,7 @@ static bool mctl_phy_write_training(struct dram_para *para)
static void mctl_phy_bit_delay_compensation(struct dram_para *para)
{
- u32 *ptr;
+ u32 *ptr, val;
int i;
if (para->tpr10 & TPR10_DX_BIT_DELAY1) {
@@ -582,49 +582,93 @@ static void mctl_phy_bit_delay_compensation(struct
dram_para *para)
setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
+ if (para->tpr10 & BIT(30))
+ val = para->tpr11 & 0x3f;
+ else
+ val = (para->tpr11 & 0xf) << 1;
+
ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x484);
for (i = 0; i < 9; i++) {
- writel_relaxed(0x16, ptr);
- writel_relaxed(0x16, ptr + 0x30);
+ writel_relaxed(val, ptr);
+ writel_relaxed(val, ptr + 0x30);
ptr += 2;
}
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4d0);
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x590);
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4cc);
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x58c);
+
+ if (para->tpr10 & BIT(30))
+ val = (para->odt_en >> 15) & 0x1e;
+ else
+ val = (para->tpr11 >> 15) & 0x1e;
+
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x4d0);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x590);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x4cc);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x58c);
+
+ if (para->tpr10 & BIT(30))
+ val = (para->tpr11 >> 8) & 0x3f;
+ else
+ val = (para->tpr11 >> 3) & 0x1e;
ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d8);
for (i = 0; i < 9; i++) {
- writel_relaxed(0x1a, ptr);
- writel_relaxed(0x1a, ptr + 0x30);
+ writel_relaxed(val, ptr);
+ writel_relaxed(val, ptr + 0x30);
ptr += 2;
}
- writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x524);
- writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e4);
- writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x520);
- writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e0);
+
+ if (para->tpr10 & BIT(30))
+ val = (para->odt_en >> 19) & 0x1e;
+ else
+ val = (para->tpr11 >> 19) & 0x1e;
+
+ writel_relaxed(val,
[PATCH V2 0/4] Enable SPL splash screen on AM62x
This patch series aims at eanbling SPL splash screen on AM62x. Changes in V2: - Correct CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK value. Nikhil M Jain (4): configs: am62x_evm_a53_defconfig: Changes in memory to support SPL splash screen board: ti: am62x: am62x: Change splashimage and splashsource board: ti: am62x: evm: Add necessary functions to call splash screen common: spl: spl: Remove video driver before u-boot proper board/ti/am62x/am62x.env| 4 ++-- board/ti/am62x/evm.c| 39 + common/spl/spl.c| 15 + configs/am62x_evm_a53_defconfig | 11 ++ 4 files changed, 63 insertions(+), 6 deletions(-) -- 2.34.1
[PATCH V2 1/4] configs: am62x_evm_a53_defconfig: Changes in memory to support SPL splash screen
To enable splash at A53 SPL, need to do memory map changes which
involves locate stack above malloc and have enough space to load bmp
image above stack. To load a 1920X1200 image a minimum of 8.8MB space is
needed, to support it move malloc down to 0x80b8 from 0x8048 and
bss to 0x80c8 to have 1MB buffer between malloc and BSS.
Observed SPL size 195KB, CONFIG_SPL_SIZE_LIMIT set to 256KB.
Observed stack size 1904Bytes, CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK set
to 2KB.
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE config sets stack above the malloc
and reports for stack overflow.
Memory map at A53 SPL before splash screen
0x8000+-+
|Empty 512 KB |
| |
0x8008+-+
| Text Base |
| 352 KB|
| |
0x800D8000+-+
| |
| |
|Empty 3.6MB |
| |
| |
0x80477660+-+
|Stack 2 KB |
0x80477e60+-+
| GD 416 Bytes|
0x80478000+-+
|Malloc 352 KB|
| |
0x8048+-+
| |
| |
| |
| |
| Empty 5.5 MB |
| |
| |
| |
| |
0x80a0+-+
| |
| BSS 512 KB |
| |
0x80a8+-+
| |
| |
| |
| |
| Empty 5.5 MB |
| |
| |
| |
| |
0x8100+-+FIT Image load address
New memory map with splash screen at SPL
0x8000+-+
|Empty 512 KB |
| |
0x8008+-+
| Text Base |
| 352 KB|
| |
0x800D8000+-+
|Empty 1.1MB |
| |
0x8020+-+
| |
| |
| |
| BMP Image Load|
| |
| 9.4 MB|
| |
| |
| |
| |
| |
| |
0x80b77660+-+
| Stack 2KB |
0x80b77e60+-+
|GD 416 Bytes |
0x80b78000+-+
| |
|Malloc 352KB |
0x80b8+-+
| |
| Empty 1 MB |
| |
0x80c8+-+
| BSS 512 KB |
| |
0x80d0+-+
| |
| |
|Empty 3.0 MB |
| |
| |
| |
0x8100+-+FIT Image load addressi
Signed-off-by: Nikhil M Jain
---
V2:
- Correct CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK value set it to 2KB.
configs/am62x_evm_a53_defconfig | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index cc9c8eab3e..b9bad6ca6a 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -8,14 +8,18 @@ CONFIG_SOC_K3_AM625=y
CONFIG_K3_ATF_LOAD_ADDR=0x9e78
CONFIG_TARGET_AM625_A53_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b8
+CONFIG_SF_DEFAULT_SPEED=2500
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk"
CONFIG_SPL_TEXT_BASE=0x8008
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x8200
+CONFIG_SPL_SIZE_LIMIT=0x4
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -27,8 +31,9 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_
[PATCH V2 2/4] board: ti: am62x: am62x: Change splashimage and splashsource
Change splashimage which is bmp image loadaddr to 0x8020 since stack
is situated at 0x80477660 as splash framework requires bmp image to be
present above stack.
Change splashsource to sf to support loading bmp image from ospi flash
memory.
Signed-off-by: Nikhil M Jain
---
V2:
- No change.
board/ti/am62x/am62x.env | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env
index e4e64fa637..5ac15fd240 100644
--- a/board/ti/am62x/am62x.env
+++ b/board/ti/am62x/am62x.env
@@ -33,6 +33,6 @@ get_fit_mmc=load mmc ${bootpart} ${addr_fit}
partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}
splashfile=ti.gz
-splashimage=0x8200
+splashimage=0x8020
splashpos=m,m
-splashsource=mmc
+splashsource=sf
--
2.34.1
[PATCH V2 3/4] board: ti: am62x: evm: Add necessary functions to call splash screen
To enable splash screen on AM62x at a53 SPL setup DRAM, set page table,
enable cache to allow copying of bmp image to frame buffer and display
it using splash_display.
Signed-off-by: Nikhil M Jain
---
V2:
- No change.
board/ti/am62x/evm.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index 20b2a70122..e3c80c5c67 100644
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -9,6 +9,7 @@
#include
#include
+#include
#include
#include
#include
@@ -53,6 +54,44 @@ int dram_init_banksize(void)
}
#if defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_SPL_VIDEO_TIDSS
+static int setup_dram(void)
+{
+ dram_init();
+ dram_init_banksize();
+ gd->ram_base = CFG_SYS_SDRAM_BASE;
+ gd->ram_top = gd->ram_base + gd->ram_size;
+ gd->relocaddr = gd->ram_top;
+ return 0;
+}
+
+static int video_setup(void)
+{
+ ulong addr;
+ int ret;
+ addr = gd->relocaddr;
+
+ ret = video_reserve(&addr);
+ if (ret)
+ return ret;
+ debug("Reserving %luk for video at: %08lx\n",
+ ((unsigned long)gd->relocaddr - addr) >> 10, addr);
+ gd->relocaddr = addr;
+ return 0;
+}
+
+#endif
+void spl_board_init(void)
+{
+#if defined(CONFIG_SPL_VIDEO_TIDSS)
+ setup_dram();
+ arch_reserve_mmu();
+ video_setup();
+ enable_caches();
+ splash_display();
+#endif
+}
+
#if defined(CONFIG_K3_AM64_DDRSS)
static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
{
--
2.34.1
[PATCH V2 4/4] common: spl: spl: Remove video driver before u-boot proper
Add method to remove video driver before loading u-boot proper. When
bootstage changes from SPL to u-boot proper, noo method is called to
remove video driver, and at u-boot proper if video driver is not
enabled, the video driver starts displaying garbage on the screen,
because there is no reserved space for video and the frame buffer gets
u-boot proper data written.
Signed-off-by: Nikhil M Jain
---
V2:
- No change.
common/spl/spl.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index a630e79866..72078a8ebc 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -35,6 +35,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -889,6 +891,19 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
debug("Failed to stash bootstage: err=%d\n", ret);
#endif
+#if defined(CONFIG_SPL_VIDEO)
+ struct udevice *dev;
+ int rc;
+
+ rc = uclass_find_device(UCLASS_VIDEO, 0, &dev);
+ if (!rc && dev) {
+ rc = device_remove(dev, DM_REMOVE_NORMAL);
+ if (rc)
+ printf("Cannot remove video device '%s' (err=%d)\n",
+ dev->name, rc);
+ }
+#endif
+
spl_board_prepare_for_boot();
jump_to_image_no_args(&spl_image);
}
--
2.34.1
[PATCH v5 0/4] FMP versioning support
Firmware version management is not implemented in the current FMP implementation. This series aims to add the versioning support in FMP. There is a major design change in v5. Until v4, the fw_version and lowest_supported_version are stored as a EFI variable. If the backing storage is a file we can't trust any of that information since anyone can tamper with the file, although the variables are defined as RO. With that, we store the version information in the device tree in v5. We can trust the information from dtb as long as the former stage boot loader verifies the image containing the dtb. The disadvantage of this design change is that we need to maintain the fw_version in both device tree and FMP Payload Header. It is inevitable since not all the capsule files contain the dtb. EDK II reference implementation utilizes the FMP Payload Header inserted right before the capsule payload. With this series, U-Boot also follows the EDK II implementation. Currently, there is no way to know the current running firmware version through the EFI interface. FMP->GetImageInfo() returns always 0 for the version number. So a user can not know that expected firmware is running after the capsule update. With this series applied, version number can be specified in the capsule file generation with mkeficapsule tool, then user can know the running firmware version through FMP->GetImageInfo() and ESRT. Note that this series does not mandate the FMP Payload Header, compatible with boards that are already using the existing U-Boot FMP implementation. If no FMP Payload Header is found in the capsule file, fw_version, lowest supported version, last attempt version and last attempt status is set to 0 and this is the same behavior as existing FMP implementation. Major Changes in v5: - major design changes, versioning is implemented with device tree instead of EFI variable Major Changes in v4: - add python-based test Major Changes in v3: - exclude CONFIG_FWU_MULTI Masahisa Kojima (4): efi_loader: get version information from device tree efi_loader: check lowest supported version mkeficapsule: add FMP Payload Header test/py: efi_capsule: test for FMP versioning .../firmware/firmware-version.txt | 25 +++ doc/mkeficapsule.1| 10 + lib/efi_loader/efi_firmware.c | 187 +--- test/py/tests/test_efi_capsule/conftest.py| 73 +++ .../test_capsule_firmware_fit.py | 187 .../test_capsule_firmware_raw.py | 201 ++ .../test_capsule_firmware_signed_fit.py | 165 ++ .../test_capsule_firmware_signed_raw.py | 169 +++ test/py/tests/test_efi_capsule/version.dts| 27 +++ tools/eficapsule.h| 30 +++ tools/mkeficapsule.c | 37 +++- 11 files changed, 1082 insertions(+), 29 deletions(-) create mode 100644 doc/device-tree-bindings/firmware/firmware-version.txt create mode 100644 test/py/tests/test_efi_capsule/version.dts -- 2.17.1
[PATCH v5 2/4] efi_loader: check lowest supported version
The FMP Payload Header which EDK II capsule generation scripts
insert has a firmware version.
This commit reads the lowest supported version stored in the
device tree, then check if the firmware version in FMP payload header
of the ongoing capsule is equal or greater than the
lowest supported version. If the firmware version is lower than
lowest supported version, capsule update fails.
Signed-off-by: Masahisa Kojima
---
Changes in v5:
- newly implement the device tree based versioning
Changes in v4:
- use log_err() instead of printf()
Changes in v2:
- add error message when the firmware version is lower than
lowest supported version
lib/efi_loader/efi_firmware.c | 124 --
1 file changed, 103 insertions(+), 21 deletions(-)
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index 1c6ef468bf..c88c1bb364 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -33,7 +33,7 @@ struct fmp_payload_header {
u32 signature;
u32 header_size;
u32 fw_version;
- u32 lowest_supported_version;
+ u32 lowest_supported_version; /* not used */
};
__weak void set_dfu_alt_info(char *interface, char *devstr)
@@ -250,8 +250,6 @@ efi_status_t efi_firmware_capsule_authenticate(const void
**p_image,
{
const void *image = *p_image;
efi_uintn_t image_size = *p_image_size;
- u32 fmp_hdr_signature;
- struct fmp_payload_header *header;
void *capsule_payload;
efi_status_t status;
efi_uintn_t capsule_payload_size;
@@ -264,7 +262,7 @@ efi_status_t efi_firmware_capsule_authenticate(const void
**p_image,
&capsule_payload_size);
if (status == EFI_SECURITY_VIOLATION) {
- printf("Capsule authentication check failed. Aborting
update\n");
+ log_err("Capsule authentication check failed. Aborting
update\n");
return status;
} else if (status != EFI_SUCCESS) {
return status;
@@ -278,21 +276,6 @@ efi_status_t efi_firmware_capsule_authenticate(const void
**p_image,
debug("Updating capsule without authenticating.\n");
}
- fmp_hdr_signature = FMP_PAYLOAD_HDR_SIGNATURE;
- header = (void *)image;
-
- if (!memcmp(&header->signature, &fmp_hdr_signature,
- sizeof(fmp_hdr_signature))) {
- /*
-* When building the capsule with the scripts in
-* edk2, a FMP header is inserted above the capsule
-* payload. Compensate for this header to get the
-* actual payload that is to be updated.
-*/
- image += header->header_size;
- image_size -= header->header_size;
- }
-
*p_image = image;
*p_image_size = image_size;
return EFI_SUCCESS;
@@ -349,6 +332,105 @@ efi_status_t EFIAPI efi_firmware_get_image_info(
return EFI_EXIT(ret);
}
+/**
+ * efi_firmware_get_image_type_id - get image_type_id
+ * @image_index: image index
+ *
+ * Return the image_type_id identified by the image index.
+ *
+ * Return: pointer to the image_type_id, NULL if image_index is
invalid
+ */
+static
+efi_guid_t *efi_firmware_get_image_type_id(u8 image_index)
+{
+ int i;
+ struct efi_fw_image *fw_array;
+
+ fw_array = update_info.images;
+ for (i = 0; i < num_image_type_guids; i++) {
+ if (fw_array[i].image_index == image_index)
+ return &fw_array[i].image_type_id;
+ }
+
+ return NULL;
+}
+
+/**
+ * efi_firmware_check_lowest_supported_version - check the lowest supported
version
+ * @p_image: Pointer to new image
+ * @p_image_size: Pointer to size of new image
+ * @image_index: image_index
+ *
+ * Check the fw_version in FMP payload header is equal to or greather than the
+ * lowest_supported_version stored in the device tree
+ *
+ * Return: status code
+ */
+static
+efi_status_t efi_firmware_check_lowest_supported_version(const void **p_image,
+efi_uintn_t
*p_image_size,
+u8 image_index)
+{
+ const void *image = *p_image;
+ efi_uintn_t image_size = *p_image_size;
+ const struct fmp_payload_header *header;
+ u32 fmp_hdr_signature = FMP_PAYLOAD_HDR_SIGNATURE;
+
+ /* FMP header is inserted above the capsule payload */
+ header = image;
+ if (header->signature == fmp_hdr_signature) {
+ efi_guid_t *image_type_id;
+ u32 version = 0, lsv = 0;
+
+ image_type_id = efi_firmware_get_image_type_id(image_index);
+ if (!image_type_id)
+ return EFI_INVALID_PARAMETER;
+
+ efi_firm
[PATCH v5 1/4] efi_loader: get version information from device tree
Current FMP->GetImageInfo() always return 0 for the firmware
version, user can not identify which firmware version is currently
running through the EFI interface.
This commit gets the version information from device tree,
then fills the firmware version, lowest supported version
in FMP->GetImageInfo().
Now FMP->GetImageInfo() and ESRT have the meaningful version number.
Signed-off-by: Masahisa Kojima
---
Changes in v5:
- newly implement a device tree based versioning
.../firmware/firmware-version.txt | 25
lib/efi_loader/efi_firmware.c | 63 +--
2 files changed, 84 insertions(+), 4 deletions(-)
create mode 100644 doc/device-tree-bindings/firmware/firmware-version.txt
diff --git a/doc/device-tree-bindings/firmware/firmware-version.txt
b/doc/device-tree-bindings/firmware/firmware-version.txt
new file mode 100644
index 00..6112de4a1d
--- /dev/null
+++ b/doc/device-tree-bindings/firmware/firmware-version.txt
@@ -0,0 +1,25 @@
+firmware-version bindings
+---
+
+Required properties:
+- image-type-id: guid for image blob type
+- image-index : image index
+- fw-version : firmware version
+- lowest-supported-version : lowest supported version
+
+Example:
+
+ firmware-version {
+ image1 {
+ image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8";
+ image-index = <1>;
+ fw-version = <5>;
+ lowest-supported-version = <3>;
+ };
+ image2 {
+ image-type-id = "5A7021F5-FEF2-48B4-AABA-832E777418C0";
+ image-index = <2>;
+ fw-version = <10>;
+ lowest-supported-version = <7>;
+ };
+ };
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index 93e2b01c07..1c6ef468bf 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -102,6 +102,56 @@ efi_status_t EFIAPI
efi_firmware_set_package_info_unsupported(
return EFI_EXIT(EFI_UNSUPPORTED);
}
+/**
+ * efi_firmware_get_firmware_version - get firmware version from dtb
+ * @image_index: Image index
+ * @image_type_id: Image type id
+ * @fw_version:Pointer to store the version number
+ * @lsv: Pointer to store the lowest supported version
+ *
+ * Authenticate the capsule if authentication is enabled.
+ * The image pointer and the image size are updated in case of success.
+ */
+void efi_firmware_get_firmware_version(u8 image_index,
+ efi_guid_t *image_type_id,
+ u32 *fw_version, u32 *lsv)
+{
+ const void *fdt = gd->fdt_blob;
+ const fdt32_t *val;
+ const char *guid_str;
+ int len, offset, index;
+ int parent;
+
+ parent = fdt_subnode_offset(fdt, 0, "firmware-version");
+ if (parent < 0)
+ return;
+
+ fdt_for_each_subnode(offset, fdt, parent) {
+ efi_guid_t guid;
+
+ guid_str = fdt_getprop(fdt, offset, "image-type-id", &len);
+ if (!guid_str)
+ continue;
+ uuid_str_to_bin(guid_str, guid.b, UUID_STR_FORMAT_GUID);
+
+ val = fdt_getprop(fdt, offset, "image-index", &len);
+ if (!val)
+ continue;
+ index = fdt32_to_cpu(*val);
+
+ if (!guidcmp(&guid, image_type_id) && index == image_index) {
+ val = fdt_getprop(fdt, offset, "fw-version", &len);
+ if (val)
+ *fw_version = fdt32_to_cpu(*val);
+
+ val = fdt_getprop(fdt, offset,
+ "lowest-supported-version", &len);
+ if (val)
+ *lsv = fdt32_to_cpu(*val);
+ }
+ }
+}
+
/**
* efi_fill_image_desc_array - populate image descriptor array
* @image_info_size: Size of @image_info
@@ -148,13 +198,19 @@ static efi_status_t efi_fill_image_desc_array(
*package_version_name = NULL; /* not supported */
for (i = 0; i < num_image_type_guids; i++) {
+ u32 fw_version = 0;
+ u32 lowest_supported_version = 0;
+
image_info[i].image_index = fw_array[i].image_index;
image_info[i].image_type_id = fw_array[i].image_type_id;
image_info[i].image_id = fw_array[i].image_index;
image_info[i].image_id_name = fw_array[i].fw_name;
-
- image_info[i].version = 0; /* not supported */
+ efi_firmware_get_firmware_version(fw_array[i].image_index,
+ &fw_array[i].image_type_id,
+
[PATCH v5 3/4] mkeficapsule: add FMP Payload Header
Current mkeficapsule tool does not provide firmware
version management. EDK II reference implementation inserts
the FMP Payload Header right before the payload.
It coutains the fw_version and lowest supported version.
This commit adds a new parameters required to generate
the FMP Payload Header for mkeficapsule tool.
'-v' indicates the firmware version.
When mkeficapsule tool is invoked without '-v' option,
FMP Payload Header is not inserted, the behavior is same as
current implementation.
The lowest supported version included in the FMP Payload Header
is not used in the current versioning support, the value stored
in the device tree is used.
Signed-off-by: Masahisa Kojima
---
Changes in v5:
- remove --lsv since we use the lowest_supported_version in the dtb
Changes in v3:
- remove '-f' option
- move some definitions into tools/eficapsule.h
- add dependency check of fw_version and lowest_supported_version
- remove unexpected modification of existing fprintf() call
- add documentation
Newly created in v2
doc/mkeficapsule.1 | 10 ++
tools/eficapsule.h | 30 ++
tools/mkeficapsule.c | 37 +
3 files changed, 73 insertions(+), 4 deletions(-)
diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1
index 1ca245a10f..c4c2057d5c 100644
--- a/doc/mkeficapsule.1
+++ b/doc/mkeficapsule.1
@@ -61,6 +61,16 @@ Specify an image index
.BI "-I\fR,\fB --instance " instance
Specify a hardware instance
+.PP
+FMP Payload Header is inserted right before the payload if
+.BR --fw-version
+is specified
+
+
+.TP
+.BI "-v\fR,\fB --fw-version " firmware-version
+Specify a firmware version, 0 if omitted
+
.PP
For generation of firmware accept empty capsule
.BR --guid
diff --git a/tools/eficapsule.h b/tools/eficapsule.h
index 072a4b5598..753fb73313 100644
--- a/tools/eficapsule.h
+++ b/tools/eficapsule.h
@@ -113,4 +113,34 @@ struct efi_firmware_image_authentication {
struct win_certificate_uefi_guid auth_info;
} __packed;
+/* fmp payload header */
+#define SIGNATURE_16(A, B) ((A) | ((B) << 8))
+#define SIGNATURE_32(A, B, C, D) \
+ (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16))
+
+#define FMP_PAYLOAD_HDR_SIGNATURE SIGNATURE_32('M', 'S', 'S', '1')
+
+/**
+ * struct fmp_payload_header - EDK2 header for the FMP payload
+ *
+ * This structure describes the header which is preprended to the
+ * FMP payload by the edk2 capsule generation scripts.
+ *
+ * @signature: Header signature used to identify the header
+ * @header_size: Size of the structure
+ * @fw_version:Firmware versions used
+ * @lowest_supported_version: Lowest supported version (not used)
+ */
+struct fmp_payload_header {
+ uint32_t signature;
+ uint32_t header_size;
+ uint32_t fw_version;
+ uint32_t lowest_supported_version;
+};
+
+struct fmp_payload_header_params {
+ bool have_header;
+ uint32_t fw_version;
+};
+
#endif /* _EFI_CAPSULE_H */
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index b71537beee..52be1f122e 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -41,6 +41,7 @@ static struct option options[] = {
{"guid", required_argument, NULL, 'g'},
{"index", required_argument, NULL, 'i'},
{"instance", required_argument, NULL, 'I'},
+ {"fw-version", required_argument, NULL, 'v'},
{"private-key", required_argument, NULL, 'p'},
{"certificate", required_argument, NULL, 'c'},
{"monotonic-count", required_argument, NULL, 'm'},
@@ -60,6 +61,7 @@ static void print_usage(void)
"\t-g, --guid guid for image blob type\n"
"\t-i, --index update image index\n"
"\t-I, --instanceupdate hardware instance\n"
+ "\t-v, --fw-version firmware version\n"
"\t-p, --private-key private key file\n"
"\t-c, --certificate signer's certificate
file\n"
"\t-m, --monotonic-count monotonic count\n"
@@ -402,6 +404,7 @@ static void free_sig_data(struct auth_context *ctx)
*/
static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
unsigned long index, unsigned long instance,
+ struct fmp_payload_header_params *fmp_ph_params,
uint64_t mcount, char *privkey_file, char *cert_file,
uint16_t oemflags)
{
@@ -410,10 +413,11 @@ static int create_fwbin(char *path, char *bin, efi_guid_t
*guid,
struct efi_firmware_management_capsule_image_header image;
struct auth_context auth_context;
FILE *f;
- uint8_t *data;
+ uint8_t *data, *new_data, *buf;
off_t bin_size;
uint64_t offset;
int ret;
+ struct fmp_payload_header payload_header;
#ifdef DEBUG
fprintf(stderr, "For output: %s\n", path);
@@ -423,6 +427,7 @@ static int
[PATCH v5 4/4] test/py: efi_capsule: test for FMP versioning
This test covers FMP versioning for both raw and FIT image,
and both signed and non-signed capsule update.
Signed-off-by: Masahisa Kojima
---
Changes in v5:
- get aligned to the device tree based versioning
Newly created in v4
test/py/tests/test_efi_capsule/conftest.py| 73 +++
.../test_capsule_firmware_fit.py | 187
.../test_capsule_firmware_raw.py | 201 ++
.../test_capsule_firmware_signed_fit.py | 165 ++
.../test_capsule_firmware_signed_raw.py | 169 +++
test/py/tests/test_efi_capsule/version.dts| 27 +++
6 files changed, 822 insertions(+)
create mode 100644 test/py/tests/test_efi_capsule/version.dts
diff --git a/test/py/tests/test_efi_capsule/conftest.py
b/test/py/tests/test_efi_capsule/conftest.py
index 4879f2b5c2..9655e5ec1f 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -70,6 +70,23 @@ def efi_capsule_data(request, u_boot_config):
'-out SIGNER2.crt -nodes -days 365'
% data_dir, shell=True)
+# Update dtb adding version information
+check_call('cd %s; '
+ 'cp %s/test/py/tests/test_efi_capsule/version.dts .'
+ % (data_dir, u_boot_config.source_dir), shell=True)
+if capsule_auth_enabled:
+check_call('cd %s; '
+ 'dtc -@ -I dts -O dtb -o version.dtbo version.dts; '
+ 'fdtoverlay -i test_sig.dtb '
+'-o test_ver.dtb version.dtbo'
+ % (data_dir), shell=True)
+else:
+check_call('cd %s; '
+ 'dtc -@ -I dts -O dtb -o version.dtbo version.dts; '
+ 'fdtoverlay -i %s/arch/sandbox/dts/test.dtb '
+'-o test_ver.dtb version.dtbo'
+ % (data_dir, u_boot_config.build_dir), shell=True)
+
# Create capsule files
# two regions: one for u-boot.bin and the other for u-boot.env
check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n
u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old > u-boot.env.old; echo -n
u-boot-env:New > u-boot.env.new' % data_dir,
@@ -95,6 +112,26 @@ def efi_capsule_data(request, u_boot_config):
check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid
058B7D83-50D5-4C47-A195-60D86AD341C4 uboot_bin_env.itb Test05' %
(data_dir, u_boot_config.build_dir),
shell=True)
+check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 5 '
+'--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8
u-boot.bin.new Test101' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
+check_call('cd %s; %s/tools/mkeficapsule --index 2 --fw-version 10 '
+'--guid 5A7021F5-FEF2-48B4-AABA-832E777418C0
u-boot.env.new Test102' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
+check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 2 '
+'--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8
u-boot.bin.new Test103' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
+check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 5 '
+'--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937
uboot_bin_env.itb Test104' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
+check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 2 '
+'--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937
uboot_bin_env.itb Test105' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
if capsule_auth_enabled:
# raw firmware signed with proper key
@@ -131,6 +168,42 @@ def efi_capsule_data(request, u_boot_config):
'uboot_bin_env.itb Test14'
% (data_dir, u_boot_config.build_dir),
shell=True)
+# raw firmware signed with proper key with version information
+check_call('cd %s; '
+ '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
+'--fw-version 5 '
+'--private-key SIGNER.key --certificate SIGNER.crt
'
+'--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 '
+'u-boot.bin.new Test111'
+ % (data_dir, u_boot_config.build_dir),
+ shell=True)
+# raw firmware signed with *mal* key with version information
+check_call('cd %s; '
+ '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
+'-
[GIT PULL] Please pull u-boot-mmc master
Dear Tom, Please pull u-boot-mmc master into u-boot master branch. If there is any problem, let me know, plz. Best Regards, Jaehoon Chung CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/15969 The following changes since commit 7daa8dd59bc8455a43cdd2d0e34206e406e5cdcc: Merge tag 'efi-2023-07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi (2023-04-09 11:08:39 -0400) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-mmc.git master for you to fetch changes up to fbf368f176641029ac30843d4d3dbf26e384df38: cmd: mmc: Return CMD_RET_* from commands (2023-04-10 12:18:45 +0900) Loic Poulain (3): mmc: Check support for TRIM operations mmc: erase: Use TRIM erase when available test: dm: mmc: Check block erasing boundaries Pali Rohár (2): mmc: Use EXT_CSD_EXTRACT_BOOT_PART() macro for extracting boot part cmd: mmc: Return CMD_RET_* from commands Stefan Roese (3): mmc: mv_sdhci: Simplify call to sdhci_mvebu_mbus_config() mmc: mv_sdhci: Remove CONFIG_MMC_SDHCI_IO_ACCESSORS support mmc: mv_sdhci: Depend on DM_MMC board/purism/librem5/librem5.c | 2 +- cmd/mmc.c | 18 ++ cmd/mvebu/bubt.c | 3 +-- common/spl/spl_mmc.c | 2 +- drivers/mmc/Kconfig| 1 + drivers/mmc/mmc.c | 3 +++ drivers/mmc/mmc_write.c| 34 +- drivers/mmc/mv_sdhci.c | 55 +++--- include/mmc.h | 4 +++ test/dm/mmc.c | 14 +-- 10 files changed, 63 insertions(+), 73 deletions(-)
RE: [PATCH 1/3] firmware: psci: enable DM_FLAG_PRE_RELOC
Tom, Simon,
Sorry for ping early, I have other patches pending on this patchset, just
wonder whether you are fine with this patchset.
Thanks,
Peng.
> Subject: [PATCH 1/3] firmware: psci: enable DM_FLAG_PRE_RELOC
>
> From: Peng Fan
>
> It is possible that cpu core may reset before relocation with PSCI reset
>
> Signed-off-by: Peng Fan
> ---
> drivers/firmware/psci.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index
> ef3e9836461..c6b9efab41c 100644
> --- a/drivers/firmware/psci.c
> +++ b/drivers/firmware/psci.c
> @@ -319,4 +319,5 @@ U_BOOT_DRIVER(psci) = { #ifdef
> CONFIG_ARM_SMCCC_FEATURES
> .plat_auto = sizeof(struct psci_plat_data), #endif
> + .flags = DM_FLAG_PRE_RELOC,
> };
> --
> 2.36.0
Re: [PATCH] board: ti: j721s2: Add support to detect daughtercards
On Mon, Apr 10, 2023 at 11:40:15AM +0530, Siddharth Vadapalli wrote: > From: Kishon Vijay Abraham I > > Add support to detect daughtercards (GESI Ethernet card) in-order > to set the MAC address of the main CPSW2G interface. > > Signed-off-by: Kishon Vijay Abraham I > Signed-off-by: Siddharth Vadapalli > --- > board/ti/j721s2/evm.c | 130 ++ > 1 file changed, 130 insertions(+) Do we (a) use this interface in U-Boot? If not (b) can Linux not read the MAC directly? -- Tom signature.asc Description: PGP signature
[PATCH 0/8] Add ESM support for J721E and J7200
Add support for ESM (Error Signalling Module) in J721E and J7200. The ESM error pin output is routed to the PMIC (Power Management IC) which can reset the board. The dts nodes for SoC and PMIC ESM modules are added (if not already) to enable them. Gowtham Tammana (6): arm: dts: k3-j7200: Add Main domain ESM support arm: dts: k3-j7200-r5-common: Add pmic node for esm arm: dts: k3-j7200: Add ESM PMIC support for tps659413 j721e_init: initialize ESM support for J7200 SOM power: pmic: tps65491: Dont fail on master node configs: j7200_evm_r5_defconfig: Enable ESM modules Tero Kristo (2): arm: mach-k3: j721e_init: initialize ESM support arm: dts: k3-k721e: Add Main domain ESM support .../k3-j7200-common-proc-board-u-boot.dtsi| 4 +++ arch/arm/dts/k3-j7200-main.dtsi | 6 + .../k3-j7200-r5-common-proc-board-u-boot.dtsi | 11 .../arm/dts/k3-j7200-r5-common-proc-board.dts | 13 +++--- arch/arm/dts/k3-j7200.dtsi| 1 + arch/arm/dts/k3-j721e.dtsi| 1 + arch/arm/mach-k3/j721e_init.c | 25 ++- configs/j7200_evm_r5_defconfig| 2 ++ drivers/power/pmic/tps65941.c | 1 - 9 files changed, 59 insertions(+), 5 deletions(-) create mode 100644 arch/arm/dts/k3-j7200-r5-common-proc-board-u-boot.dtsi -- 2.34.1
[PATCH 1/8] arm: mach-k3: j721e_init: initialize ESM support
From: Tero Kristo
Initialize both ESM and ESM_PMIC support if available for the board.
If support is not available for either, a warning is printed out.
Signed-off-by: Tero Kristo
Signed-off-by: Gowtham Tammana
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/j721e_init.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 9cae3ac67e..b22530f39d 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include "../../../board/ti/common/board_detect.h"
#ifdef CONFIG_K3_LOAD_SYSFW
struct fwl_data cbass_hc_cfg0_fwls[] = {
@@ -189,7 +190,8 @@ void do_dt_magic(void)
void board_init_f(ulong dummy)
{
-#if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
+#if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW) || \
+ defined(CONFIG_ESM_K3) || defined(CONFIG_ESM_PMIC)
struct udevice *dev;
int ret;
#endif
@@ -277,6 +279,25 @@ void board_init_f(ulong dummy)
printf("AVS init failed: %d\n", ret);
#endif
+#ifdef CONFIG_ESM_K3
+ if (board_ti_k3_is("J721EX-PM2-SOM")) {
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(k3_esm), &dev);
+ if (ret)
+ printf("MISC init failed: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_ESM_PMIC
+ if (board_ti_k3_is("J721EX-PM2-SOM")) {
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(pmic_esm),
+ &dev);
+ if (ret)
+ printf("ESM PMIC init failed: %d\n", ret);
+ }
+#endif
+
#if defined(CONFIG_K3_J721E_DDRSS)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
--
2.34.1
[PATCH 2/8] arm: dts: k3-k721e: Add Main domain ESM support
From: Tero Kristo Main domain ESM support is needed to configure main domain watchdogs to generate ESM pin events by default. On J7 processor board these propagate to the PMIC to generate a reset when watchdog expires. Signed-off-by: Tero Kristo Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-j721e.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/k3-j721e.dtsi b/arch/arm/dts/k3-j721e.dtsi index f0587fde14..d7f73f61db 100644 --- a/arch/arm/dts/k3-j721e.dtsi +++ b/arch/arm/dts/k3-j721e.dtsi @@ -126,6 +126,7 @@ #size-cells = <2>; ranges = <0x00 0x0010 0x00 0x0010 0x00 0x0002>, /* ctrl mmr */ <0x00 0x0060 0x00 0x0060 0x00 0x00031100>, /* GPIO */ +<0x00 0x0070 0x00 0x0070 0x00 0x1000>, /* ESM */ <0x00 0x0090 0x00 0x0090 0x00 0x00012000>, /* serdes */ <0x00 0x00a4 0x00 0x00a4 0x00 0x0800>, /* timesync router */ <0x00 0x0600 0x00 0x0600 0x00 0x0040>, /* USBSS0 */ -- 2.34.1
[PATCH 3/8] arm: dts: k3-j7200: Add Main domain ESM support
From: Gowtham Tammana
Main domain ESM support is needed to configure main domain watchdog
interrupts to generate ESM pin events. On J7200 boards ESM error pin
output is propagated to PMIC to generate reset.
Signed-off-by: Gowtham Tammana
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 4
arch/arm/dts/k3-j7200-main.dtsi | 6 ++
arch/arm/dts/k3-j7200.dtsi | 1 +
3 files changed, 11 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index f57c2306ba..088fdb4072 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -196,3 +196,7 @@
&main_r5fss0 {
ti,cluster-mode = <0>;
};
+
+&main_esm {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index e8a41d09b4..4c8ba123dc 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -774,4 +774,10 @@
ti,loczrama = <1>;
};
};
+
+ main_esm: esm@70 {
+ compatible = "ti,j721e-esm";
+ reg = <0x0 0x70 0x0 0x1000>;
+ ti,esm-pins = <656>, <657>;
+ };
};
diff --git a/arch/arm/dts/k3-j7200.dtsi b/arch/arm/dts/k3-j7200.dtsi
index b7005b8031..9252d97399 100644
--- a/arch/arm/dts/k3-j7200.dtsi
+++ b/arch/arm/dts/k3-j7200.dtsi
@@ -124,6 +124,7 @@
#size-cells = <2>;
ranges = <0x00 0x0010 0x00 0x0010 0x00 0x0002>, /*
ctrl mmr */
<0x00 0x0060 0x00 0x0060 0x00 0x00031100>, /*
GPIO */
+<0x00 0x0070 0x00 0x0070 0x00 0x1000>, /*
ESM */
<0x00 0x00a4 0x00 0x00a4 0x00 0x0800>, /*
timesync router */
<0x00 0x0100 0x00 0x0100 0x00 0x0d00>, /*
Most peripherals */
<0x00 0x3000 0x00 0x3000 0x00 0x0c40>, /*
MAIN NAVSS */
--
2.34.1
[PATCH 4/8] arm: dts: k3-j7200-r5-common: Add pmic node for esm
From: Gowtham Tammana
Add pmic tps659413 node needed for ESM error event handling.
Signed-off-by: Gowtham Tammana
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 55ad6153dd..01e3a507d4 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -248,13 +248,20 @@
&wkup_i2c0 {
bootph-pre-ram;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <40>;
+
+ tps659413: tps659413@48 {
+ compatible = "ti,tps659413";
+ reg = <0x48>;
+ bootph-pre-ram;
+ };
+
lp876441: lp876441@4c {
compatible = "ti,lp876441";
reg = <0x4c>;
bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <40>;
regulators: regulators {
bootph-pre-ram;
--
2.34.1
[PATCH 5/8] arm: dts: k3-j7200: Add ESM PMIC support for tps659413
From: Gowtham Tammana
On J7200 processor board MCU_SAFETY_ERROR signal is routed to PMIC for
ESM error handling. The PMIC resets the board on receipt of the signal.
Enable the support for the board by adding ESM PMIC node.
Signed-off-by: Gowtham Tammana
Signed-off-by: Neha Malcom Francis
---
.../arm/dts/k3-j7200-r5-common-proc-board-u-boot.dtsi | 11 +++
1 file changed, 11 insertions(+)
create mode 100644 arch/arm/dts/k3-j7200-r5-common-proc-board-u-boot.dtsi
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j7200-r5-common-proc-board-u-boot.dtsi
new file mode 100644
index 00..9cd4dd09ca
--- /dev/null
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+&tps659413 {
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ bootph-pre-ram;
+ };
+};
--
2.34.1
[PATCH 7/8] power: pmic: tps65491: Dont fail on master node
From: Gowtham Tammana
TPS65941 can have child only ESM nodes with no regulators, so dont fail
on regulator probe failure.
Signed-off-by: Gowtham Tammana
Signed-off-by: Neha Malcom Francis
---
drivers/power/pmic/tps65941.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/power/pmic/tps65941.c b/drivers/power/pmic/tps65941.c
index 83d0f83c64..06a3c1406c 100644
--- a/drivers/power/pmic/tps65941.c
+++ b/drivers/power/pmic/tps65941.c
@@ -51,7 +51,6 @@ static int tps65941_bind(struct udevice *dev)
if (!ofnode_valid(regulators_node)) {
debug("%s: %s regulators subnode not found!\n", __func__,
dev->name);
- return -ENXIO;
}
debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
--
2.34.1
[PATCH 6/8] j721e_init: initialize ESM support for J7200 SOM
From: Gowtham Tammana
ESM and ESM PMIC support is available for J7200X-PM2-SOM board, as such
enable support for it.
Signed-off-by: Gowtham Tammana
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/j721e_init.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index b22530f39d..294aeb2f88 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -280,7 +280,8 @@ void board_init_f(ulong dummy)
#endif
#ifdef CONFIG_ESM_K3
- if (board_ti_k3_is("J721EX-PM2-SOM")) {
+ if (board_ti_k3_is("J721EX-PM2-SOM") ||
+ board_ti_k3_is("J7200X-PM2-SOM")) {
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(k3_esm), &dev);
if (ret)
@@ -289,7 +290,8 @@ void board_init_f(ulong dummy)
#endif
#ifdef CONFIG_ESM_PMIC
- if (board_ti_k3_is("J721EX-PM2-SOM")) {
+ if (board_ti_k3_is("J721EX-PM2-SOM") ||
+ board_ti_k3_is("J7200X-PM2-SOM")) {
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(pmic_esm),
&dev);
--
2.34.1
[PATCH 8/8] configs: j7200_evm_r5_defconfig: Enable ESM modules
From: Gowtham Tammana Enable ESM modules for both PMIC and SoC for watchdog error intterupt handling on the board. Signed-off-by: Gowtham Tammana Signed-off-by: Neha Malcom Francis --- configs/j7200_evm_r5_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 00ec48b83b..7b3b4766f0 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -168,3 +168,5 @@ CONFIG_FS_EXT4=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_LIB_RATIONAL=y CONFIG_SPL_LIB_RATIONAL=y +CONFIG_ESM_K3=y +CONFIG_ESM_PMIC=y -- 2.34.1
Re: [PATCH 1/3] firmware: psci: enable DM_FLAG_PRE_RELOC
On Mon, Apr 10, 2023 at 12:39:07PM +, Peng Fan wrote:
> Tom, Simon,
>
> Sorry for ping early, I have other patches pending on this patchset, just
> wonder whether you are fine with this patchset.
This is fine I think.
>
> Thanks,
> Peng.
> > Subject: [PATCH 1/3] firmware: psci: enable DM_FLAG_PRE_RELOC
> >
> > From: Peng Fan
> >
> > It is possible that cpu core may reset before relocation with PSCI reset
> >
> > Signed-off-by: Peng Fan
> > ---
> > drivers/firmware/psci.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index
> > ef3e9836461..c6b9efab41c 100644
> > --- a/drivers/firmware/psci.c
> > +++ b/drivers/firmware/psci.c
> > @@ -319,4 +319,5 @@ U_BOOT_DRIVER(psci) = { #ifdef
> > CONFIG_ARM_SMCCC_FEATURES
> > .plat_auto = sizeof(struct psci_plat_data), #endif
> > + .flags = DM_FLAG_PRE_RELOC,
> > };
> > --
> > 2.36.0
>
--
Tom
signature.asc
Description: PGP signature
Re: [GIT PULL] Please pull u-boot-mmc master
On Mon, Apr 10, 2023 at 07:18:55PM +0900, Jaehoon Chung wrote: > Dear Tom, > > Please pull u-boot-mmc master into u-boot master branch. > If there is any problem, let me know, plz. > > Best Regards, > Jaehoon Chung > > CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/15969 > > > The following changes since commit 7daa8dd59bc8455a43cdd2d0e34206e406e5cdcc: > > Merge tag 'efi-2023-07-rc1' of > https://source.denx.de/u-boot/custodians/u-boot-efi (2023-04-09 11:08:39 > -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-mmc.git master > > for you to fetch changes up to fbf368f176641029ac30843d4d3dbf26e384df38: > > cmd: mmc: Return CMD_RET_* from commands (2023-04-10 12:18:45 +0900) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 0/8] Add ESM support for J721E and J7200
Hi Neha! On April 10, 2023 thus sayeth Neha Malcom Francis: > Add support for ESM (Error Signalling Module) in J721E and J7200. The > ESM error pin output is routed to the PMIC (Power Management IC) which > can reset the board. The dts nodes for SoC and PMIC ESM modules are > added (if not already) to enable them. > > Gowtham Tammana (6): > arm: dts: k3-j7200: Add Main domain ESM support > arm: dts: k3-j7200-r5-common: Add pmic node for esm > arm: dts: k3-j7200: Add ESM PMIC support for tps659413 > j721e_init: initialize ESM support for J7200 SOM > power: pmic: tps65491: Dont fail on master node > configs: j7200_evm_r5_defconfig: Enable ESM modules > > Tero Kristo (2): > arm: mach-k3: j721e_init: initialize ESM support > arm: dts: k3-k721e: Add Main domain ESM support > > .../k3-j7200-common-proc-board-u-boot.dtsi| 4 +++ > arch/arm/dts/k3-j7200-main.dtsi | 6 + > .../k3-j7200-r5-common-proc-board-u-boot.dtsi | 11 > .../arm/dts/k3-j7200-r5-common-proc-board.dts | 13 +++--- > arch/arm/dts/k3-j7200.dtsi| 1 + > arch/arm/dts/k3-j721e.dtsi| 1 + > arch/arm/mach-k3/j721e_init.c | 25 ++- > configs/j7200_evm_r5_defconfig| 2 ++ > drivers/power/pmic/tps65941.c | 1 - > 9 files changed, 59 insertions(+), 5 deletions(-) > create mode 100644 arch/arm/dts/k3-j7200-r5-common-proc-board-u-boot.dtsi > I know Praneeth and Andrew have already commented internally, I just wanted to summarize publicly Thank you for sending this out! Unfortunately some of these dt node updates where never sent to the kernel. We'll need to get these merged over there so it will be a simple copy/paste once they make it to a linux tag. Though I guess we can treat the dt updates as a DONOTMERGE ~Bryan
Re: [PATCH v9 3/6] tpm: Support boot measurements
On 4/6/23 04:18, Ilias Apalodimas wrote:
Hi Eddie,
Do you plan on resending this?
If yes, I can spend some time trying to figure out the CI failures and
send you a patch.
Hi,
Yes I do, I have been short on time. I was a bit confused by the CI, it
didn't seem to run with the updated v9? I believed I had fixed at least
some of the failures with patch 2 to update the sandbox driver. I also
haven't figured out how to run the ci suite locally
Thanks,
Eddie
Thanks
/Ilias
On Wed, 8 Mar 2023 at 23:25, Eddie James wrote:
Add TPM2 functions to support boot measurement. This includes
starting up the TPM, initializing/appending the event log, and
measuring the U-Boot version. Much of the code was used in the
EFI subsystem, so remove it there and use the common functions.
Signed-off-by: Eddie James
---
Changes since v8:
- Fix log parsing again - any data corruption seen while replaying the
event log was failing the entire measurement.
- Added an option to ignore the existing log. This should only be used
for systems that know that U-Boot is the first stage bootloader. This
is necessary because the reserved memory region may persist through
resets and so U-Boot attempts to append to the previous boot's log.
Changes since v7:
- Change name of tcg2_init_log and add more documentation
- Add a check, when parsing the event log header, to ensure that the
previous stage bootloader used all the active PCRs.
- Change name of tcg2_log_find_end
- Fix the greater than or equal to check to exit the log parsing
- Make sure log_position is 0 if there is any error discovering the log
- Return errors parsing the log if the data is corrupt so that we don't
end up with half a log
Changes since v6:
- Added Linaro copyright for all the EFI moved code
- Changed tcg2_init_log (and by extension, tcg2_measurement_init) to
copy any discovered event log to the user's log if passed in.
Changes since v5:
- Remove unused platform_get_eventlog in efi_tcg2.c
- First look for tpm_event_log_* properties instead of linux,sml-*
- Fix efi_tcg2.c compilation
- Select SHA* configs
Changes since v4:
- Remove tcg2_measure_event function and check for NULL data in
tcg2_measure_data
- Use tpm_auto_startup
- Fix efi_tcg2.c compilation for removing tcg2_pcr_read function
Changes since v3:
- Reordered headers
- Refactored more of EFI code into common code
Removed digest_info structure and instead used the common alg_to_mask
and alg_to_len
Improved event log parsing in common code to get it equivalent to EFI
Common code now extends PCR if previous bootloader stage couldn't
No need to allocate memory in the common code, so EFI copies the
discovered buffer like it did before
Rename efi measure_event function
Changes since v1:
- Refactor TPM layer functions to allow EFI system to use them, and
remove duplicate EFI functions
include/efi_tcg2.h| 44 --
include/tpm-v2.h | 259 +
lib/Kconfig |4 +
lib/efi_loader/efi_tcg2.c | 1054 +++--
lib/tpm-v2.c | 814
5 files changed, 1154 insertions(+), 1021 deletions(-)
diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h
index b1c3abd097..b21c5cb3dd 100644
--- a/include/efi_tcg2.h
+++ b/include/efi_tcg2.h
@@ -129,50 +129,6 @@ struct efi_tcg2_boot_service_capability {
#define BOOT_SERVICE_CAPABILITY_MIN \
offsetof(struct efi_tcg2_boot_service_capability, number_of_pcr_banks)
-#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03"
-#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2 2
-#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 0
-#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2 2
-
-/**
- * struct TCG_EfiSpecIdEventAlgorithmSize - hashing algorithm information
- *
- * @algorithm_id: algorithm defined in enum tpm2_algorithms
- * @digest_size: size of the algorithm
- */
-struct tcg_efi_spec_id_event_algorithm_size {
- u16 algorithm_id;
- u16 digest_size;
-} __packed;
-
-/**
- * struct TCG_EfiSpecIDEventStruct - content of the event log header
- *
- * @signature: signature, set to Spec ID Event03
- * @platform_class:class defined in TCG ACPI Specification
- * Client Common Header.
- * @spec_version_minor:minor version
- * @spec_version_major:major version
- * @spec_version_errata: major version
- * @uintn_size:size of the efi_uintn_t fields used in
various
- * data structures used in this specification.
- * 0x01 indicates u32 and 0x02 indicates u64
- * @number_of_algorithms: hashing algorithms used in this event log
- * @digest_sizes: array of number_of_algorithms pairs
- *
[PATCH v2 3/4] test/py: IPv6 network discovery test
From: Ehsan Mohandesi
Test the IPv6 network discovery feature if indicated by boardenv file.
Signed-off-by: Ehsan Mohandesi
Conflicts:
configs/sandbox64_defconfig
configs/sandbox_defconfig
configs/sandbox_flattree_defconfig
---
configs/sandbox64_defconfig| 2 ++
configs/sandbox_defconfig | 2 ++
configs/sandbox_flattree_defconfig | 2 ++
test/py/tests/test_net.py | 31 ++-
4 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index af2c56a..be36ede 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -260,3 +260,5 @@ CONFIG_FWU_MULTI_BANK_UPDATE=y
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
+CONFIG_IPV6=y
+CONFIG_IPV6_ROUTER_DISCOVERY=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index ca95b2c..0673c69 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -341,3 +341,5 @@ CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_CMD_2048=y
+CONFIG_IPV6=y
+CONFIG_IPV6_ROUTER_DISCOVERY=y
diff --git a/configs/sandbox_flattree_defconfig
b/configs/sandbox_flattree_defconfig
index e9fcc5b..d6c8dd2 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -229,3 +229,5 @@ CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
+CONFIG_IPV6=y
+CONFIG_IPV6_ROUTER_DISCOVERY=y
diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index 9ca6743..f85071d 100644
--- a/test/py/tests/test_net.py
+++ b/test/py/tests/test_net.py
@@ -9,7 +9,7 @@ import u_boot_utils
"""
Note: This test relies on boardenv_* containing configuration values to define
-which the network environment available for testing. Without this, this test
+which network environment is available for testing. Without this, this test
will be automatically skipped.
For example:
@@ -55,6 +55,11 @@ env__net_nfs_readable_file = {
'size': 5058624,
'crc32': 'c2244b26',
}
+
+# True if a router advertisement service is connected to the network, and
should
+# be tested. If router advertisement testing is not possible or desired, this
+variable may be omitted or set to False.
+env__router_on_net = True
"""
net_set_up = False
@@ -126,6 +131,30 @@ def test_net_ping(u_boot_console):
output = u_boot_console.run_command('ping $serverip')
assert 'is alive' in output
+@pytest.mark.buildconfigspec('IPV6_ROUTER_DISCOVERY')
+def test_net_network_discovery(u_boot_console):
+"""Test the network discovery feature of IPv6.
+
+An IPv6 network command (ping6 in this case) is run to make U-Boot send a
+router solicitation packet, receive a router advertisement message, and
+parse it.
+A router advertisement service needs to be running for this test to
succeed.
+U-Boot receives the RA, processes it, and if successful, assigns the
gateway
+IP and prefix length.
+The configuration is provided by the boardenv_* file; see the comment at
+the beginning of this file.
+"""
+
+router_on_net = u_boot_console.config.env.get('env__router_on_net', False)
+if not router_on_net:
+pytest.skip('No router on network')
+
+fake_host_ip = 'fe80::215:5dff:fef6:2ec6'
+output = u_boot_console.run_command('ping6 ' + fake_host_ip)
+assert 'ROUTER SOLICITATION 1' in output
+assert 'Set gatewayip6:' in output
+assert ':::::::' not in output
+
@pytest.mark.buildconfigspec('cmd_net')
def test_net_tftpboot(u_boot_console):
"""Test the tftpboot command.
--
1.8.3.1
[PATCH v2 0/4] Add IPv6 Network Discovery
From: Ehsan Mohandesi This series adds IPv6 network discovery to U-Boot. When an IPv6 command is run in U-Boot, it sends a router solicitation (RS) message to the network. The router on the network responds with a router advertisement (RA) message. Then U-Boot processes the RA message and sets the gatewayip6 and net_prefix_length environment variables. It is based on RFC 4861, but not everything in the RFC is supported here. https://www.rfc-editor.org/rfc/rfc4861 Changes in v2: - Improved IPv6 network discovery code. - Added IPv6 network discovery feature test (Python test). - Added unit tests (C code). Ehsan Mohandesi (4): Revert "net: ipv6: Add support for default gateway discovery." net: ipv6: Add support for default gateway discovery. test/py: IPv6 network discovery test test: eth: IPv6 network discovery unit test cmd/Kconfig| 6 + configs/sandbox64_defconfig| 2 + configs/sandbox_defconfig | 2 + configs/sandbox_flattree_defconfig | 2 + include/ndisc.h| 35 ++ include/net.h | 5 +- include/net6.h | 40 ++ net/ndisc.c| 243 +++-- net/net.c | 26 +++- net/net6.c | 1 + test/dm/eth.c | 88 ++ test/py/tests/test_net.py | 31 - 12 files changed, 467 insertions(+), 14 deletions(-) -- 1.8.3.1
[PATCH v2 4/4] test: eth: IPv6 network discovery unit test
From: Ehsan Mohandesi
Test router advertisement validation and processing functions.
Signed-off-by: Ehsan Mohandesi
---
test/dm/eth.c | 88 +++
1 file changed, 88 insertions(+)
diff --git a/test/dm/eth.c b/test/dm/eth.c
index ebf01d8..d05d2a9 100644
--- a/test/dm/eth.c
+++ b/test/dm/eth.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#define DM_TEST_ETH_NUM4
@@ -607,3 +608,90 @@ static int dm_test_eth_async_ping_reply(struct
unit_test_state *uts)
}
DM_TEST(dm_test_eth_async_ping_reply, UT_TESTF_SCAN_FDT);
+
+#if IS_ENABLED(CONFIG_IPV6_ROUTER_DISCOVERY)
+
+static u8 ip6_ra_buf[] = {0x60, 0xf, 0xc5, 0x4a, 0x0, 0x38, 0x3a, 0xff, 0xfe,
+ 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0x85, 0xe6,
+ 0x29, 0x77, 0xcb, 0xc8, 0x53, 0xff, 0x2, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x1, 0x86, 0x0, 0xdc, 0x90, 0x40, 0x80, 0x15, 0x18,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x4,
+ 0x40, 0xc0, 0x0, 0x0, 0x37, 0xdc, 0x0, 0x0, 0x37,
+ 0x78, 0x0, 0x0, 0x0, 0x0, 0x20, 0x1, 0xca, 0xfe, 0xca,
+ 0xfe, 0xca, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x1, 0x1, 0x0, 0x15, 0x5d, 0xe2, 0x8a, 0x2};
+
+static int dm_test_validate_ra(struct unit_test_state *uts)
+{
+ struct ip6_hdr *ip6 = (struct ip6_hdr *)ip6_ra_buf;
+ struct icmp6hdr *icmp = (struct icmp6hdr *)(ip6 + 1);
+ __be16 temp = 0;
+
+ ut_assert(validate_ra(ip6) == true);
+
+ temp = ip6->payload_len;
+ ip6->payload_len = 15;
+ ut_assert(validate_ra(ip6) == false);
+ ip6->payload_len = temp;
+
+ temp = ip6->saddr.s6_addr16[0];
+ ip6->saddr.s6_addr16[0] = 0x2001;
+ ut_assert(validate_ra(ip6) == false);
+ ip6->saddr.s6_addr16[0] = temp;
+
+ temp = ip6->hop_limit;
+ ip6->hop_limit = 15;
+ ut_assert(validate_ra(ip6) == false);
+ ip6->hop_limit = temp;
+
+ temp = icmp->icmp6_code;
+ icmp->icmp6_code = 15;
+ ut_assert(validate_ra(ip6) == false);
+ icmp->icmp6_code = temp;
+
+ return 0;
+}
+
+DM_TEST(dm_test_validate_ra, 0);
+
+static int dm_test_process_ra(struct unit_test_state *uts)
+{
+ int len = sizeof(ip6_ra_buf);
+ struct ip6_hdr *ip6 = (struct ip6_hdr *)ip6_ra_buf;
+ struct icmp6hdr *icmp = (struct icmp6hdr *)(ip6 + 1);
+ struct ra_msg *msg = (struct ra_msg *)icmp;
+ unsigned char *option = msg->opt;
+ struct icmp6_ra_prefix_info *prefix =
+ (struct icmp6_ra_prefix_info *)option;
+ __be16 temp = 0;
+ unsigned char option_len = option[1];
+
+ ut_assert(process_ra(ip6, len) == 0);
+
+ temp = icmp->icmp6_rt_lifetime;
+ icmp->icmp6_rt_lifetime = 0;
+ ut_assert(process_ra(ip6, len) != 0);
+ icmp->icmp6_rt_lifetime = temp;
+
+ ut_assert(process_ra(ip6, 0) != 0);
+
+ option[1] = 0;
+ ut_assert(process_ra(ip6, len) != 0);
+ option[1] = option_len;
+
+ prefix->on_link = false;
+ ut_assert(process_ra(ip6, len) != 0);
+ prefix->on_link = true;
+
+ temp = prefix->prefix.s6_addr16[0];
+ prefix->prefix.s6_addr16[0] = 0x80fe;
+ ut_assert(process_ra(ip6, len) != 0);
+ prefix->prefix.s6_addr16[0] = temp;
+
+ return 0;
+}
+
+DM_TEST(dm_test_process_ra, 0);
+
+#endif
--
1.8.3.1
[PATCH v2 1/4] Revert "net: ipv6: Add support for default gateway discovery."
From: Ehsan Mohandesi
This reverts commit 0af1035a55d9c1486b2db43ee70ff0a63affd4f4.
Signed-off-by: Ehsan Mohandesi
Conflicts:
cmd/Kconfig
include/net.h
include/net6.h
net/net.c
---
include/net.h | 4 ++--
net/net.c | 3 +++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/include/net.h b/include/net.h
index 399af5e..8ba50a0 100644
--- a/include/net.h
+++ b/include/net.h
@@ -504,8 +504,8 @@ extern ushort net_native_vlan;/* Our
Native VLAN */
extern int net_restart_wrap; /* Tried all network devices */
enum proto_t {
- BOOTP, RARP, ARP, TFTPGET, DHCP, PING, PING6, DNS, NFS, CDP, NETCONS,
- SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI, WGET
+ BOOTP, RARP, ARP, TFTPGET, DHCP, DHCP6, PING, PING6, DNS, NFS, CDP,
+ NETCONS, SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI,
WGET
};
extern charnet_boot_file_name[1024];/* Boot File name */
diff --git a/net/net.c b/net/net.c
index c9a749f..d69bfb0 100644
--- a/net/net.c
+++ b/net/net.c
@@ -122,6 +122,9 @@
#endif
#include
#include
+#if defined(CONFIG_CMD_DHCP6)
+#include "dhcpv6.h"
+#endif
/** BOOTP EXTENTIONS **/
--
1.8.3.1
[PATCH v2 2/4] net: ipv6: Add support for default gateway discovery.
From: Ehsan Mohandesi
In IPv6, the default gateway and prefix length are determined by receiving
a router advertisement as defined in -
https://www.rfc-editor.org/rfc/rfc4861.
Add support for sending router solicitation (RS) and processing router
advertisements (RA).
If the RA has prefix info option and following conditions are met, then
gatewayip6 and net_prefix_length of ip6addr env variables are initialized.
These are later consumed by IPv6 code for non-local destination IP.
- "Router Lifetime" != 0
- Prefix is NOT link-local prefix (0xfe80::/10)
- L flag is 1
- "Valid Lifetime" != 0
Timing Parameters:
- MAX_RTR_SOLICITATION_DELAY (0-1s)
- RTR_SOLICITATION_INTERVAL (4s) (min retransmit delay)
- MAX_RTR_SOLICITATIONS (3 RS transmissions)
The functionality is enabled by CONFIG_IPV6_ROUTER_DISCOVERY and invoked
automatically from net_init_loop().
Signed-off-by: Ehsan Mohandesi
Conflicts:
cmd/Kconfig
net/net.c
---
Changes in v2:
- A few of cosmetic changes.
- Made some functions not static in order to be able to test them.
cmd/Kconfig | 6 ++
include/ndisc.h | 35
include/net.h | 3 +-
include/net6.h | 40 ++
net/ndisc.c | 243 +---
net/net.c | 23 +-
net/net6.c | 1 +
7 files changed, 339 insertions(+), 12 deletions(-)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index e45b884..6919d31 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1916,6 +1916,12 @@ config CMD_NCSI
Normally this happens automatically before other network
operations.
+config IPV6_ROUTER_DISCOVERY
+ bool "Do IPv6 router discovery"
+ depends on IPV6
+ help
+ Will automatically perform router solicitation on first IPv6
+ network operation
endif
config CMD_ETHSW
diff --git a/include/ndisc.h b/include/ndisc.h
index f6f8eb6..12fa9e7 100644
--- a/include/ndisc.h
+++ b/include/ndisc.h
@@ -19,6 +19,20 @@ struct nd_msg {
__u8opt[0];
};
+/* struct rs_msg - ICMPv6 Router Solicitation message format */
+struct rs_msg {
+ struct icmp6hdr icmph;
+ __u8opt[0];
+};
+
+/* struct ra_msg - ICMPv6 Router Advertisement message format */
+struct ra_msg {
+ struct icmp6hdr icmph;
+ __u32 reachable_time;
+ __u32 retransmission_timer;
+ __u8opt[0];
+};
+
/* struct echo_msg - ICMPv6 echo request/reply message format */
struct echo_msg {
struct icmp6hdr icmph;
@@ -57,6 +71,11 @@ extern int net_nd_try;
*/
void ndisc_init(void);
+/*
+ * ip6_send_rs() - Send IPv6 Router Solicitation Message
+ */
+void ip6_send_rs(void);
+
/**
* ndisc_receive() - Handle ND packet
*
@@ -78,6 +97,8 @@ void ndisc_request(void);
* Return: 0 if no timeout, -1 otherwise
*/
int ndisc_timeout_check(void);
+bool validate_ra(struct ip6_hdr *ip6);
+int process_ra(struct ip6_hdr *ip6, int len);
#else
static inline void ndisc_init(void)
{
@@ -97,6 +118,20 @@ static inline int ndisc_timeout_check(void)
{
return 0;
}
+
+void ip6_send_rs(void)
+{
+}
+
+static inline bool validate_ra(struct ip6_hdr *ip6)
+{
+ return true;
+}
+
+static inline int process_ra(struct ip6_hdr *ip6, int len)
+{
+ return 0;
+}
#endif
#endif /* __NDISC_H__ */
diff --git a/include/net.h b/include/net.h
index 8ba50a0..58774f6 100644
--- a/include/net.h
+++ b/include/net.h
@@ -505,7 +505,8 @@ extern int net_restart_wrap; /* Tried all
network devices */
enum proto_t {
BOOTP, RARP, ARP, TFTPGET, DHCP, DHCP6, PING, PING6, DNS, NFS, CDP,
- NETCONS, SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI,
WGET
+ NETCONS, SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI,
+ WGET, RS
};
extern charnet_boot_file_name[1024];/* Boot File name */
diff --git a/include/net6.h b/include/net6.h
index 2d7c5a0..beafc05 100644
--- a/include/net6.h
+++ b/include/net6.h
@@ -81,8 +81,17 @@ struct udp_hdr {
0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00 } } }
+/*
+ * All-routers multicast address is the link-local scope address to reach all
+ * routers.
+ */
+#define ALL_ROUTERS_MULT_ADDR { { { 0xFF, 0x02, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x02 } } }
#define IPV6_LINK_LOCAL_PREFIX 0xfe80
+#define IPV6_LINK_LOCAL_MASK 0xffb0 /* The first 10-bit of address mask. */
/* hop limit for neighbour discovery packets */
#define IPV6_NDISC_HOPLIMIT 255
@@ -166,6 +175,37 @@ struct icmp6hdr {
#define icmp6_rt_lifetime icmp6_dataun.u_nd_ra.rt_lifetime
} __packed;
+/*
+ * struct icmp6_ra_prefix_info - Prefix Information option of the ICMPv6
message
+ * The Prefix Information option provides hosts with on
Reading file would overwrite reserved memory. Failed to load 'hello_world.bin - imx7d-pico - Uboot 2022.04
https://stackoverflow.com/questions/71073386/reading-file-would-overwrite-reserved-memory-failed-to-load-hello-world-bin Hi, I had this issue last year and I solved it via device tree. However, I used Yocto hardknott and uboot 2021.04 and Ubuntu 20.04. Now I use Yocto kirkstone and uboot 2022.04 and Ubuntu 22.04 I've been trying to resolve this issue for seven days now. I've already made several changes to the uboot and yocto/device tree configurations without success. Every help is welcome Note I tried: https://dantechrb.com/blog/how-to-build-and-debug-freertos-applications-for-cortexm4-on-mx6sx https://whycan.com/t_5474.html
[PATCH v5 0/6] FWU: Add support for mtd backed feature on DeveloperBox
From: Jassi Brar Introduce support for mtd backed storage for FWU feature and enable it on Synquacer platform based DeveloperBox. This revision is rebased onto patchset that trims the FWU api https://lore.kernel.org/u-boot/20230306231747.1888513-1-jassisinghb...@gmail.com/ Changes since v4: * Provide default/weak implementations of fwu_plat_get_alt_num and fwu_plat_get_bootidx * Provide man page for mkfwumdata * Misc typo fixes and cosmetic changes Changes since v3: * Fix and Update documentation to also build optee for FWU FIP image. * Fixed checkpatch warnings * Made local functions static. * Split config changes to a separate patch * Fix authorship of three patches. Jassi Brar (4): dt: fwu: developerbox: enable fwu banks and mdata regions configs: move to new flash layout and boot flow fwu: DeveloperBox: add support for FWU fwu: provide default fwu_plat_get_bootidx Masami Hiramatsu (2): FWU: Add FWU metadata access driver for MTD storage regions tools: Add mkfwumdata tool for FWU metadata image .../synquacer-sc2a11-developerbox-u-boot.dtsi | 49 ++- board/socionext/developerbox/Makefile | 1 + board/socionext/developerbox/developerbox.c | 8 + board/socionext/developerbox/fwu_plat.c | 37 ++ configs/synquacer_developerbox_defconfig | 12 +- doc/board/socionext/developerbox.rst | 155 +++- doc/mkfwumdata.1 | 89 + drivers/fwu-mdata/Kconfig | 15 + drivers/fwu-mdata/Makefile| 1 + drivers/fwu-mdata/raw_mtd.c | 272 ++ include/configs/synquacer.h | 10 + include/fwu.h | 32 ++ lib/fwu_updates/Makefile | 1 + lib/fwu_updates/fwu.c | 18 + lib/fwu_updates/fwu_mtd.c | 185 ++ tools/Kconfig | 9 + tools/Makefile| 4 + tools/mkfwumdata.c| 334 ++ 18 files changed, 1221 insertions(+), 11 deletions(-) create mode 100644 board/socionext/developerbox/fwu_plat.c create mode 100644 doc/mkfwumdata.1 create mode 100644 drivers/fwu-mdata/raw_mtd.c create mode 100644 lib/fwu_updates/fwu_mtd.c create mode 100644 tools/mkfwumdata.c -- 2.34.1
[PATCH v5 1/6] FWU: Add FWU metadata access driver for MTD storage regions
From: Masami Hiramatsu
In the FWU Multi Bank Update feature, the information about the
updatable images is stored as part of the metadata, on a separate
region. Add a driver for reading from and writing to the metadata
when the updatable images and the metadata are stored on a raw
MTD region.
The code is divided into core under drivers/fwu-mdata/ and some helper
functions clubbed together under lib/fwu_updates/
Signed-off-by: Masami Hiramatsu
Signed-off-by: Jassi Brar
---
drivers/fwu-mdata/Kconfig | 15 ++
drivers/fwu-mdata/Makefile | 1 +
drivers/fwu-mdata/raw_mtd.c | 272
include/fwu.h | 32 +
lib/fwu_updates/Makefile| 1 +
lib/fwu_updates/fwu_mtd.c | 185
6 files changed, 506 insertions(+)
create mode 100644 drivers/fwu-mdata/raw_mtd.c
create mode 100644 lib/fwu_updates/fwu_mtd.c
diff --git a/drivers/fwu-mdata/Kconfig b/drivers/fwu-mdata/Kconfig
index 36c4479a59..42736a5e43 100644
--- a/drivers/fwu-mdata/Kconfig
+++ b/drivers/fwu-mdata/Kconfig
@@ -6,6 +6,11 @@ config FWU_MDATA
FWU Metadata partitions reside on the same storage device
which contains the other FWU updatable firmware images.
+choice
+ prompt "Storage Layout Scheme"
+ depends on FWU_MDATA
+ default FWU_MDATA_GPT_BLK
+
config FWU_MDATA_GPT_BLK
bool "FWU Metadata access for GPT partitioned Block devices"
select PARTITION_TYPE_GUID
@@ -14,3 +19,13 @@ config FWU_MDATA_GPT_BLK
help
Enable support for accessing FWU Metadata on GPT partitioned
block devices.
+
+config FWU_MDATA_MTD
+ bool "Raw MTD devices"
+ depends on MTD
+ help
+ Enable support for accessing FWU Metadata on non-partitioned
+ (or non-GPT partitioned, e.g. partition nodes in devicetree)
+ MTD devices.
+
+endchoice
diff --git a/drivers/fwu-mdata/Makefile b/drivers/fwu-mdata/Makefile
index 3fee64c10c..06c49747ba 100644
--- a/drivers/fwu-mdata/Makefile
+++ b/drivers/fwu-mdata/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_FWU_MDATA) += fwu-mdata-uclass.o
obj-$(CONFIG_FWU_MDATA_GPT_BLK) += gpt_blk.o
+obj-$(CONFIG_FWU_MDATA_MTD) += raw_mtd.o
diff --git a/drivers/fwu-mdata/raw_mtd.c b/drivers/fwu-mdata/raw_mtd.c
new file mode 100644
index 00..25c1aa33ec
--- /dev/null
+++ b/drivers/fwu-mdata/raw_mtd.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#define LOG_CATEGORY UCLASS_FWU_MDATA
+
+#include
+#include
+#include
+
+#include
+#include
+
+/* Internal helper structure to move data around */
+struct fwu_mdata_mtd_priv {
+ struct mtd_info *mtd;
+ char pri_label[50];
+ char sec_label[50];
+ u32 pri_offset;
+ u32 sec_offset;
+};
+
+enum fwu_mtd_op {
+ FWU_MTD_READ,
+ FWU_MTD_WRITE,
+};
+
+extern struct fwu_mtd_image_info fwu_mtd_images[];
+
+static bool mtd_is_aligned_with_block_size(struct mtd_info *mtd, u64 size)
+{
+ return !do_div(size, mtd->erasesize);
+}
+
+static int mtd_io_data(struct mtd_info *mtd, u32 offs, u32 size, void *data,
+ enum fwu_mtd_op op)
+{
+ struct mtd_oob_ops io_op = {};
+ u64 lock_offs, lock_len;
+ size_t len;
+ void *buf;
+ int ret;
+
+ if (!mtd_is_aligned_with_block_size(mtd, offs)) {
+ log_err("Offset unaligned with a block (0x%x)\n",
mtd->erasesize);
+ return -EINVAL;
+ }
+
+ lock_offs = offs;
+ /* This will expand erase size to align with the block size */
+ lock_len = round_up(size, mtd->erasesize);
+
+ ret = mtd_unlock(mtd, lock_offs, lock_len);
+ if (ret && ret != -EOPNOTSUPP)
+ return ret;
+
+ if (op == FWU_MTD_WRITE) {
+ struct erase_info erase_op = {};
+
+ erase_op.mtd = mtd;
+ erase_op.addr = lock_offs;
+ erase_op.len = lock_len;
+ erase_op.scrub = 0;
+
+ ret = mtd_erase(mtd, &erase_op);
+ if (ret)
+ goto lock;
+ }
+
+ /* Also, expand the write size to align with the write size */
+ len = round_up(size, mtd->writesize);
+
+ buf = memalign(ARCH_DMA_MINALIGN, len);
+ if (!buf) {
+ ret = -ENOMEM;
+ goto lock;
+ }
+ memset(buf, 0xff, len);
+
+ io_op.mode = MTD_OPS_AUTO_OOB;
+ io_op.len = len;
+ io_op.ooblen = 0;
+ io_op.datbuf = buf;
+ io_op.oobbuf = NULL;
+
+ if (op == FWU_MTD_WRITE) {
+ memcpy(buf, data, size);
+ ret = mtd_write_oob(mtd, offs, &io_op);
+ } else {
+ ret = mtd_read_oob(mtd, offs, &io_op);
+ if (!ret)
+ memcpy(data, buf, size);
+ }
+ free(buf);
+
+lock:
+ mtd_lock(mtd, lock_offs, lock_len);
+
+ return ret;
+}
+
+static int fwu
[PATCH v5 2/6] tools: Add mkfwumdata tool for FWU metadata image
From: Masami Hiramatsu
Add 'mkfwumdata' tool to generate FWU metadata image for the meta-data
partition to be used in A/B Update imeplementation.
Signed-off-by: Sughosh Ganu
Signed-off-by: Jassi Brar
Signed-off-by: Masami Hiramatsu
---
doc/mkfwumdata.1 | 89
tools/Kconfig | 9 ++
tools/Makefile | 4 +
tools/mkfwumdata.c | 334 +
4 files changed, 436 insertions(+)
create mode 100644 doc/mkfwumdata.1
create mode 100644 tools/mkfwumdata.c
diff --git a/doc/mkfwumdata.1 b/doc/mkfwumdata.1
new file mode 100644
index 00..7dd718b26e
--- /dev/null
+++ b/doc/mkfwumdata.1
@@ -0,0 +1,89 @@
+.\" SPDX-License-Identifier: GPL-2.0-or-later
+.\" Copyright (C) 2023 Jassi Brar
+.TH MKFWUMDATA 1 2023-04-10 U-Boot
+.SH NAME
+mkfwumdata \- create FWU metadata image
+.
+.SH SYNOPSIS
+.SY mkfwumdata
+.OP \-a activeidx
+.OP \-p previousidx
+.OP \-g
+.BI \-i\~ imagecount
+.BI \-b\~ bankcount
+.I UUIDs
+.I outputimage
+.YS
+.SY mkfwumdata
+.B \-h
+.YS
+.
+.SH DESCRIPTION
+.B mkfwumdata
+creates metadata info to be used with FWU.
+.
+.SH OPTIONS
+.TP
+.B \-h
+Print usage information and exit.
+.
+.TP
+.B \-a
+Set
+.IR activeidx
+as the currently active Bank. Default is 0.
+.
+.TP
+.B \-p
+Set
+.IR previousidx
+as the previous active Bank. Default is
+.IR activeidx "-1"
+or
+.IR bankcount "-1,"
+whichever is non-negative.
+.
+.TP
+.B \-g
+Convert the
+.IR UUIDs
+as GUIDs before use.
+.
+.TP
+.B \-i
+Specify there are
+.IR imagecount
+images in each bank.
+.
+.TP
+.B \-b
+Specify there are a total of
+.IR bankcount
+banks.
+.
+.TP
+.IR UUIDs
+Comma-separated list of UUIDs required to create the metadata :-
+location_uuid,image_type_uuid,
+.
+.TP
+.IR outputimage
+Specify the name of the metadata image file to be created.
+.
+.SH BUGS
+Please report bugs to the
+.UR https://\:source\:.denx\:.de/\:u-boot/\:u-boot/\:issues
+U-Boot bug tracker
+.UE .
+.SH EXAMPLES
+Create a metadata image with 2 banks and 1 image/bank, BankAct=0, BankPrev=1:
+.PP
+.EX
+.in +4
+$ \c
+.B mkfwumdata \-a 0 \-p 1 \-b 2 \-i 1 \&
+.in +6
+.B 17e86d77-41f9-4fd7-87ec-a55df9842de5,\&
+.B 10c36d7d-ca52-b843-b7b9-f9d6c501d108,\&
+.B 5a66a702-99fd-4fef-a392-c26e261a2828,a8f868a1-6e5c-4757-878d-ce63375ef2c0
\&
+.B fwu-mdata.img
diff --git a/tools/Kconfig b/tools/Kconfig
index 539708f277..6e23f44d55 100644
--- a/tools/Kconfig
+++ b/tools/Kconfig
@@ -157,4 +157,13 @@ config LUT_SEQUENCE
help
Look Up Table Sequence
+config TOOLS_MKFWUMDATA
+ bool "Build mkfwumdata command"
+ default y if FWU_MULTI_BANK_UPDATE
+ help
+ This command allows users to create a raw image of the FWU
+ metadata for initial installation of the FWU multi bank
+ update on the board. The installation method depends on
+ the platform.
+
endmenu
diff --git a/tools/Makefile b/tools/Makefile
index 38699b069d..1e3fce0b1c 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -250,6 +250,10 @@ HOSTLDLIBS_mkeficapsule += \
$(shell pkg-config --libs uuid 2> /dev/null || echo "-luuid")
hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule
+mkfwumdata-objs := mkfwumdata.o lib/crc32.o
+HOSTLDLIBS_mkfwumdata += -luuid
+hostprogs-$(CONFIG_TOOLS_MKFWUMDATA) += mkfwumdata
+
# We build some files with extra pedantic flags to try to minimize things
# that won't build on some weird host compiler -- though there are lots of
# exceptions for files that aren't complaint.
diff --git a/tools/mkfwumdata.c b/tools/mkfwumdata.c
new file mode 100644
index 00..43dabf3b72
--- /dev/null
+++ b/tools/mkfwumdata.c
@@ -0,0 +1,334 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* This will dynamically allocate the fwu_mdata */
+#define CONFIG_FWU_NUM_BANKS 0
+#define CONFIG_FWU_NUM_IMAGES_PER_BANK 0
+
+/* Since we can not include fwu.h, redefine version here. */
+#define FWU_MDATA_VERSION 1
+
+typedef uint8_t u8;
+typedef int16_t s16;
+typedef uint16_t u16;
+typedef uint32_t u32;
+typedef uint64_t u64;
+
+#include
+
+/* TODO: Endianness conversion may be required for some arch. */
+
+static const char *opts_short = "b:i:a:p:gh";
+
+static struct option options[] = {
+ {"banks", required_argument, NULL, 'b'},
+ {"images", required_argument, NULL, 'i'},
+ {"guid", required_argument, NULL, 'g'},
+ {"active-bank", required_argument, NULL, 'a'},
+ {"previous-bank", required_argument, NULL, 'p'},
+ {"help", no_argument, NULL, 'h'},
+ {NULL, 0, NULL, 0},
+};
+
+static void print_usage(void)
+{
+ fprintf(stderr, "Usage: mkfwumdata [options] \n");
+ fprintf(stderr, "Options:\n"
+ "\t-i, --images Number of images\n"
+ "\t-b, --banksNumber of banks\n"
+
[PATCH v5 3/6] dt: fwu: developerbox: enable fwu banks and mdata regions
From: Jassi Brar
Specify Bank-0/1 and fwu metadata mtd regions.
Signed-off-by: Jassi Brar
---
.../synquacer-sc2a11-developerbox-u-boot.dtsi | 49 +--
1 file changed, 46 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
index 9f9837b33b..9957646a46 100644
--- a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
@@ -21,7 +21,7 @@
#size-cells = <0>;
status = "okay";
- flash@0 {
+ flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -74,8 +74,24 @@
};
partition@50 {
- label = "Ex-OPTEE";
- reg = <0x50 0x20>;
+ label = "MDATA-Pri";
+ reg = <0x50 0x1000>;
+ };
+
+ partition@53 {
+ label = "MDATA-Sec";
+ reg = <0x53 0x1000>;
+ };
+
+ /* FWU Multi bank update partitions */
+ partition@60 {
+ label = "FIP-Bank0";
+ reg = <0x60 0x40>;
+ };
+
+ partition@a0 {
+ label = "FIP-Bank1";
+ reg = <0xa0 0x40>;
};
};
};
@@ -102,6 +118,33 @@
optee {
status = "okay";
};
+
+ fwu-mdata {
+ compatible = "u-boot,fwu-mdata-mtd";
+ fwu-mdata-store = <&flash0>;
+ mdata-parts = "MDATA-Pri", "MDATA-Sec";
+
+ fwu-bank0 {
+ id = <0>;
+ label = "FIP-Bank0";
+ fwu-image0 {
+ id = <0>;
+ offset = <0x0>;
+ size = <0x40>;
+ uuid =
"5a66a702-99fd-4fef-a392-c26e261a2828";
+ };
+ };
+ fwu-bank1 {
+ id = <1>;
+ label = "FIP-Bank1";
+ fwu-image0 {
+ id = <0>;
+ offset = <0x0>;
+ size = <0x40>;
+ uuid =
"a8f868a1-6e5c-4757-878d-ce63375ef2c0";
+ };
+ };
+ };
};
};
--
2.34.1
[PATCH v5 4/6] configs: move to new flash layout and boot flow
From: Jassi Brar Towards enabling FWU and supporting new firmware layout in NOR flash, make u-boot PIC and adjust uboot env offset in flash. Signed-off-by: Jassi Brar --- configs/synquacer_developerbox_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index 08f19a90cb..09e12b739b 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -1,12 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_SYNQUACER=y -CONFIG_TEXT_BASE=0x0820 +CONFIG_POSITION_INDEPENDENT=y CONFIG_SYS_MALLOC_LEN=0x100 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xe000 CONFIG_ENV_SIZE=0x3 -CONFIG_ENV_OFFSET=0x30 +CONFIG_ENV_OFFSET=0x58 CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox" -- 2.34.1
[PATCH v5 5/6] fwu: DeveloperBox: add support for FWU
From: Jassi Brar
Add code to support FWU_MULTI_BANK_UPDATE.
The platform does not have gpt-partition storage for
Banks and MetaData, rather it used SPI-NOR backed
mtd regions for the purpose.
Signed-off-by: Jassi Brar
---
board/socionext/developerbox/Makefile | 1 +
board/socionext/developerbox/developerbox.c | 8 +
board/socionext/developerbox/fwu_plat.c | 37 +
configs/synquacer_developerbox_defconfig| 8 +
doc/board/socionext/developerbox.rst| 155 +++-
include/configs/synquacer.h | 10 ++
6 files changed, 213 insertions(+), 6 deletions(-)
create mode 100644 board/socionext/developerbox/fwu_plat.c
diff --git a/board/socionext/developerbox/Makefile
b/board/socionext/developerbox/Makefile
index 4a46de995a..1acd067a7e 100644
--- a/board/socionext/developerbox/Makefile
+++ b/board/socionext/developerbox/Makefile
@@ -7,3 +7,4 @@
#
obj-y := developerbox.o
+obj-$(CONFIG_FWU_MDATA_MTD) += fwu_plat.o
diff --git a/board/socionext/developerbox/developerbox.c
b/board/socionext/developerbox/developerbox.c
index 16e14d4f7f..ce2cccf4f0 100644
--- a/board/socionext/developerbox/developerbox.c
+++ b/board/socionext/developerbox/developerbox.c
@@ -20,6 +20,13 @@
#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
struct efi_fw_image fw_images[] = {
+#if CONFIG_IS_ENABLED(FWU_MULTI_BANK_UPDATE)
+ {
+ .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID,
+ .fw_name = u"DEVELOPERBOX-FIP",
+ .image_index = 1,
+ },
+#else
{
.image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID,
.fw_name = u"DEVELOPERBOX-UBOOT",
@@ -35,6 +42,7 @@ struct efi_fw_image fw_images[] = {
.fw_name = u"DEVELOPERBOX-OPTEE",
.image_index = 3,
},
+#endif
};
struct efi_capsule_update_info update_info = {
diff --git a/board/socionext/developerbox/fwu_plat.c
b/board/socionext/developerbox/fwu_plat.c
new file mode 100644
index 00..e5dae0ff11
--- /dev/null
+++ b/board/socionext/developerbox/fwu_plat.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define DFU_ALT_BUF_LEN 256
+
+/* Generate dfu_alt_info from partitions */
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ int ret;
+ struct mtd_info *mtd;
+
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+ memset(buf, 0, sizeof(buf));
+
+ mtd_probe_devices();
+
+ mtd = get_mtd_device_nm("nor1");
+ if (IS_ERR_OR_NULL(mtd))
+ return;
+
+ ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd);
+ if (ret < 0) {
+ log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret);
+ return;
+ }
+ log_debug("Make dfu_alt_info: '%s'\n", buf);
+
+ env_set("dfu_alt_info", buf);
+}
diff --git a/configs/synquacer_developerbox_defconfig
b/configs/synquacer_developerbox_defconfig
index 09e12b739b..d09684153a 100644
--- a/configs/synquacer_developerbox_defconfig
+++ b/configs/synquacer_developerbox_defconfig
@@ -97,3 +97,11 @@ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_IGNORE_OSINDICATIONS=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+CONFIG_FWU_MULTI_BANK_UPDATE=y
+CONFIG_FWU_MDATA=y
+CONFIG_FWU_MDATA_MTD=y
+CONFIG_FWU_NUM_BANKS=2
+CONFIG_FWU_NUM_IMAGES_PER_BANK=1
+CONFIG_CMD_FWU_METADATA=y
+CONFIG_TOOLS_MKFWUMDATA=y
diff --git a/doc/board/socionext/developerbox.rst
b/doc/board/socionext/developerbox.rst
index 2d943c23be..908d3a7e6f 100644
--- a/doc/board/socionext/developerbox.rst
+++ b/doc/board/socionext/developerbox.rst
@@ -57,14 +57,20 @@ Installation
You can install the SNI_NOR_UBOOT.fd via NOR flash writer.
-Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine
or other mezzanine which can connect to LS-UART0 port.
-Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the
board on again. The flash writer program will be started automatically; don???t
forget to turn the DSW2-7 off again after flashing.
+Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine
+or other mezzanine which can connect to LS-UART0 port.
+Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the
+board on again. The flash writer program will be started automatically;
+don't forget to turn the DSW2-7 off again after flashing.
-*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the
board can be bricked. See below page if you need to recover the bricked board.
See the following page for more detail*
+*!!CAUTION!! If you write the U-Boot image on wrong address, the board can
+be bricked. See below page if you need to recover the bricked board. See
+the following page for more detail*
https://www.96boards.org/docume
[PATCH v5 6/6] fwu: provide default fwu_plat_get_bootidx
From: Jassi Brar
Just like fwu_plat_get_update_index, provide a default/weak
implementation of fwu_plat_get_bootidx. So that most platforms
wouldn't have to re-implement the likely case.
Signed-off-by: Jassi Brar
---
lib/fwu_updates/fwu.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c
index a24ccf567a..c9996f4d6d 100644
--- a/lib/fwu_updates/fwu.c
+++ b/lib/fwu_updates/fwu.c
@@ -545,6 +545,24 @@ __weak int fwu_plat_get_update_index(uint *update_idx)
return ret;
}
+/**
+ * fwu_plat_get_bootidx() - Get the value of the boot index
+ * @boot_idx: Boot index value
+ *
+ * Get the value of the bank(partition) from which the platform
+ * has booted. This value is passed to U-Boot from the earlier
+ * stage bootloader which loads and boots all the relevant
+ * firmware images
+ */
+__weak void fwu_plat_get_bootidx(uint *boot_idx)
+{
+ int ret;
+
+ ret = fwu_get_active_index(boot_idx);
+ if (ret < 0)
+ *boot_idx = 0; /* Dummy value */
+}
+
/**
* fwu_update_checks_pass() - Check if FWU update can be done
*
--
2.34.1
[PATCH] dt/bindings: fwu-mdata-mtd: drop changes outside FWU
From: Jassi Brar
Any requirement of FWU should not require changes to bindings
of other subsystems. For example, for mtd-backed storage we
can do without requiring 'fixed-partitions' children to also
carry 'uuid', a property which is non-standard and not in the
bindings.
There exists no code yet, so we can change the fwu-mtd bindings
to contain all properties within the fwu-mdata node.
Signed-off-by: Jassi Brar
---
Hi Rob, Hi Krzysztof,
I was suggested, and I agree, it would be a good idea to get your blessings
for the location and meta-data (fwu-mdata) bindings for the FWU.
The FWU images can be located in GPT partitions or MTD backed storage.
The basic bindings for fwu-mdata has already been merged in uboot (ideally they
too should have had your review). Now I am trying to fully support MTD backed
storage and hence looking for your review. The proposed bindings are totally
self-contained and don't require changes to any other subsystem.
Thanks.
.../firmware/fwu-mdata-mtd.yaml | 105 +++---
1 file changed, 91 insertions(+), 14 deletions(-)
diff --git a/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
index 4f5404f999..6a22aeea30 100644
--- a/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
+++ b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
@@ -1,13 +1,13 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/firmware/u-boot,fwu-mdata-sf.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
+$id: http://devicetree.org/schemas/firmware/u-boot,fwu-mdata-mtd.yaml#
+$schema: http://devicetree.org/meta-schemas/base.yaml#
title: FWU metadata on MTD device without GPT
maintainers:
- - Masami Hiramatsu
+ - Jassi Brar
properties:
compatible:
@@ -15,24 +15,101 @@ properties:
- const: u-boot,fwu-mdata-mtd
fwu-mdata-store:
-maxItems: 1
-description: Phandle of the MTD device which contains the FWU medatata.
+$ref: /schemas/types.yaml#/definitions/phandle
+description: Phandle of the MTD device which contains the FWU MetaData and
Banks.
- mdata-offsets:
+ mdata-parts:
+$ref: /schemas/types.yaml#/definitions/non-unique-string-array
minItems: 2
-description: Offsets of the primary and secondary FWU metadata in the NOR
flash.
+maxItems: 2
+description: labels of the primary and secondary FWU metadata partitions
in the 'fixed-partitions' subnode of the 'jedec,spi-nor' flash device node.
+
+ patternProperties:
+"fwu-bank[0-9]":
+type: object
+description: List of FWU mtd-backed banks. Typically two banks.
+
+properties:
+ id:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Index of the bank.
+
+ label:
+$ref: /schemas/types.yaml#/definitions/non-unique-string-array
+minItems: 1
+maxItems: 1
+description: label of the partition, in the 'fixed-partitions' subnode
of the 'jedec,spi-nor' flash device node, that holds this bank.
+
+ patternProperties:
+"fwu-image[0-9]":
+type: object
+description: List of images in the FWU mtd-backed bank.
+
+properties:
+ id:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Index of the bank.
+
+ offset:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Offset, from start of the bank, where the image is
located.
+
+ size:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Size reserved for the image.
+
+ uuid:
+$ref: /schemas/types.yaml#/definitions/non-unique-string-array
+minItems: 1
+maxItems: 1
+description: UUID of the image.
+
+required:
+ - id
+ - offset
+ - size
+ - uuid
+additionalProperties: false
+
+required:
+ - id
+ - label
+ - fwu-images
+additionalProperties: false
required:
- compatible
- fwu-mdata-store
- - mdata-offsets
-
+ - mdata-parts
+ - fwu-banks
additionalProperties: false
examples:
- |
-fwu-mdata {
-compatible = "u-boot,fwu-mdata-mtd";
-fwu-mdata-store = <&spi-flash>;
-mdata-offsets = <0x50 0x53>;
-};
+ fwu-mdata {
+ compatible = "u-boot,fwu-mdata-mtd";
+ fwu-mdata-store = <&flash0>;
+ mdata-parts = "MDATA-Pri", "MDATA-Sec";
+
+ fwu-bank0 {
+ id = <0>;
+ label = "FIP-Bank0";
+ fwu-image0 {
+ id = <0>;
+ offset = <0x0>;
+ size = <0x40>;
+ uuid = "5a66a702-99fd-4fef-a392-c26e261a2828";
+ };
+ };
+
Re: [PATCH v2 2/3] net: dhcp6: pxe: Add DHCP/PXE commands for IPv6
On 2023-04-07 11:55 a.m., Simon Glass wrote:
Hi Sean,
On Fri, 7 Apr 2023 at 18:56, wrote:
From: Sean Edmond
Adds commands to support DHCP and PXE with IPv6.
New configs added:
- CMD_DHCP6
- DHCP6_PXE_CLIENTARCH
- DHCP6_PXE_DHCP_OPTION
- DHCP6_ENTERPRISE_ID
New commands added (when IPv6 is enabled):
- dhcp6
- pxe get -ipv6
- pxe boot -ipv6
Signed-off-by: Sean Edmond
---
boot/bootmeth_distro.c | 2 +-
boot/bootmeth_pxe.c| 4 +-
boot/pxe_utils.c | 3 +-
cmd/Kconfig| 26 +
cmd/net.c | 23 +++
cmd/pxe.c | 86 +-
cmd/sysboot.c | 2 +-
include/pxe_utils.h| 10 -
8 files changed, 140 insertions(+), 16 deletions(-)
With nits below:
Reviewed-by: Simon Glass
[..]
+if CMD_DHCP6
+
+config DHCP6_PXE_CLIENTARCH
+ hex
+ default 0x16 if ARM64
+ default 0x15 if ARM
+ default 0xFF
Do we need a separate option or could we use BOOTP_PXE_CLIENTARCH ?
I created a new option because I wanted to change the default to 0xFF
("undefined" Processor Architecture Types according to
https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml).
I wanted to do this without changing BOOTP_PXE_CLIENTARCH , and
potentially disrupting exisiting DHCPv4 implementations.
+
+config DHCP6_PXE_DHCP_OPTION
+ bool "Request & store 'pxe_configfile' from DHCP6 server"
+
+config DHCP6_ENTERPRISE_ID
+ int "Enterprise ID to send in DHCPv6 Vendor Class Option"
+ default 0
+
+endif
+
config CMD_TFTPBOOT
bool "tftpboot"
default y
diff --git a/cmd/net.c b/cmd/net.c
index d5e20843dd..95529a9d12 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -111,6 +111,29 @@ U_BOOT_CMD(
);
#endif
+#if defined(CONFIG_CMD_DHCP6)
+static int do_dhcp6(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int i;
+ int dhcp_argc;
+ char *dhcp_argv[] = {NULL, NULL, NULL, NULL};
+
+ /* Add -ipv6 flag for autoload */
+ for (i = 0; i < argc; i++)
+ dhcp_argv[i] = argv[i];
+ dhcp_argc = argc + 1;
+ dhcp_argv[dhcp_argc - 1] = USE_IP6_CMD_PARAM;
+
+ return netboot_common(DHCP6, cmdtp, dhcp_argc, dhcp_argv);
+}
+
+U_BOOT_CMD(dhcp6, 3, 1, do_dhcp6,
+ "boot image via network using DHCPv6/TFTP protocol. \n"
+ "Use IPv6 hostIPaddr framed with [] brackets",
+ "[loadAddress] [[hostIPaddr:]bootfilename]");
+#endif
+
#if defined(CONFIG_CMD_DHCP)
static int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
diff --git a/cmd/pxe.c b/cmd/pxe.c
index db8e4697f2..71e6fd9633 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include "pxe_utils.h"
@@ -29,12 +30,20 @@ static int do_get_tftp(struct pxe_context *ctx, const char
*file_path,
{
char *tftp_argv[] = {"tftp", NULL, NULL, NULL};
int ret;
+ int num_args;
tftp_argv[1] = file_addr;
tftp_argv[2] = (void *)file_path;
+ if (ctx->use_ipv6) {
+ tftp_argv[3] = USE_IP6_CMD_PARAM;
+ num_args = 4;
+ } else {
+ num_args = 3;
+ }
- if (do_tftpb(ctx->cmdtp, 0, 3, tftp_argv))
+ if (do_tftpb(ctx->cmdtp, 0, num_args, tftp_argv))
return -ENOENT;
+
ret = pxe_get_file_size(sizep);
if (ret)
return log_msg_ret("tftp", ret);
@@ -43,6 +52,23 @@ static int do_get_tftp(struct pxe_context *ctx, const char
*file_path,
return 1;
}
+#if defined(CONFIG_DHCP6_PXE_DHCP_OPTION)
+/*
+ * Looks for a pxe file with specified config file name,
+ * which is received from DHCPv4 option 209 or
+ * DHCPv6 option 60.
+ *
+ * Returns 1 on success or < 0 on error.
+ */
+static inline int pxe_dhcp_option_path(struct pxe_context *ctx, unsigned long
pxefile_addr_r)
Please drop the inline as the compiler can handle that.
+{
+ int ret = get_pxe_file(ctx, pxelinux_configfile, pxefile_addr_r);
+
+ free(pxelinux_configfile);
+
+ return ret;
+}
+#endif
/*
* Looks for a pxe file with a name based on the pxeuuid environment variable.
*
@@ -105,15 +131,25 @@ static int pxe_ipaddr_paths(struct pxe_context *ctx,
unsigned long pxefile_addr_
return -ENOENT;
}
-int pxe_get(ulong pxefile_addr_r, char **bootdirp, ulong *sizep)
+int pxe_get(ulong pxefile_addr_r, char **bootdirp, ulong *sizep, bool use_ipv6)
{
struct cmd_tbl cmdtp[] = {};/* dummy */
struct pxe_context ctx;
int i;
if (pxe_setup_ctx(&ctx, cmdtp, do_get_tftp, NULL, false,
- env_get("bootfile")))
+ env_get("bootfile"), use_ipv6))
return -ENOMEM;
+
+#if defined(CONFIG_DHCP6_PXE_DHCP_OPTION)
It's a bit annoying that pxelinux_configfile causes these #ifdefs.
[PATCH v4 2/3] configs: starfive-jh7110: Add support for PCIe host driver
From: Mason Huo also add the nvme driver and rtl8169 support. Signed-off-by: Mason Huo Signed-off-by: Minda Chen --- configs/starfive_visionfive2_12a_defconfig | 10 ++ configs/starfive_visionfive2_13b_defconfig | 10 ++ 2 files changed, 20 insertions(+) diff --git a/configs/starfive_visionfive2_12a_defconfig b/configs/starfive_visionfive2_12a_defconfig index e0f98292ff..bd5b25f9d4 100644 --- a/configs/starfive_visionfive2_12a_defconfig +++ b/configs/starfive_visionfive2_12a_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x8200 +CONFIG_SYS_PCI_64BIT=y CONFIG_TARGET_STARFIVE_VISIONFIVE2=y CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000 CONFIG_ARCH_RV64I=y @@ -49,9 +50,12 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SYS_BOOTM_LEN=0x400 +CONFIG_CMD_PCI=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_TFTPPUT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_JH7110=y @@ -65,6 +69,12 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_REGION_MULTI_ENTRY=y +CONFIG_PCIE_STARFIVE_JH7110=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y diff --git a/configs/starfive_visionfive2_13b_defconfig b/configs/starfive_visionfive2_13b_defconfig index 550d0ff3ab..7247992796 100644 --- a/configs/starfive_visionfive2_13b_defconfig +++ b/configs/starfive_visionfive2_13b_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x8200 +CONFIG_SYS_PCI_64BIT=y CONFIG_TARGET_STARFIVE_VISIONFIVE2=y CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000 CONFIG_ARCH_RV64I=y @@ -50,8 +51,11 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_MEMINFO=y +CONFIG_CMD_PCI=y CONFIG_CMD_TFTPPUT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_JH7110=y @@ -65,6 +69,12 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_REGION_MULTI_ENTRY=y +CONFIG_PCIE_STARFIVE_JH7110=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y -- 2.17.1
[PATCH v4 0/3] Add StarFive JH7110 PCIe drvier support
This patchset needs to apply after patchset in [1]. These PCIe series patches are based on the JH7110 RISC-V SoC and VisionFive V2 board. [1] https://patchwork.ozlabs.org/project/uboot/cover/20230329034224.26545-1-yanhong.w...@starfivetech.com The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init. The PCIe dts configuation includes all these setting. The PCIe drivers codes has been tested on the VisionFive V2 boards. The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter. previous patch version v1: https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-minda.c...@starfivetech.com/ v2: https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.95730-1-minda.c...@starfivetech.com/ v3: https://patchwork.ozlabs.org/project/uboot/cover/20230329100143.10724-1-minda.c...@starfivetech.com/ changes v4 patch 1 1. Remove the IDS_REVISION_ID macros. 2. Replace sec_busno to first_busno in starfive_pcie 3. Remove starfive_pcie_off_conf function. 4. Replace "imply" to "depends on" in PCIe Kconfig. 5 .Check sec_busno in starfive_pcie_addr_valid. v3 patch 1 1. remove the read vendor ID delay 2. remove starfive_pcie_hide_rc_bar function. do not hide host bridge BAR write. 3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros. 4. Add comments for bus and address limitation reason in function starfive_pcie_addr_valid 5. Change the multiple line comments in Line 373 6. Using gpio_request_by_name to get PCIe reset gpio,and using dm_gpio_set_value set GPIO value. patch 2 1. support PCIeboth 12a and 13b vf2 board. patch 3 1. reset dts change to reset-gpio. v2 1. remove clock commit. The pcie clocks change has been includeded in [1]. 2. Using GENMASK marco1 in patch1. 3. remove the syscon dts node in patch3. The syscon dts dts node has been included in [1]. --- Mason Huo (3): starfive: pci: Add StarFive JH7110 pcie driver configs: starfive-jh7110: Add support for PCIe host driver riscv: dts: starfive: Enable PCIe host controller .../dts/jh7110-starfive-visionfive-2.dtsi | 11 + arch/riscv/dts/jh7110.dtsi| 74 +++ configs/starfive_visionfive2_12a_defconfig| 10 + configs/starfive_visionfive2_13b_defconfig| 10 + drivers/pci/Kconfig | 9 + drivers/pci/Makefile | 1 + drivers/pci/pcie_starfive_jh7110.c| 465 ++ 7 files changed, 580 insertions(+) create mode 100644 drivers/pci/pcie_starfive_jh7110.c base-commit: 41a88ad529b3943b1e465846eb24fe2c29203e35 prerequisite-patch-id: a84452ba131408ff842b65ae19a3a05f64b3ff60 prerequisite-patch-id: 4abb46d56dbaf36017b2866688f31a73c2cacd0d prerequisite-patch-id: ef5e9d61f7392c7d2e5321aa8a10996ca8eae5fc prerequisite-patch-id: 26dfdb401d680ecd9449acf09131cf4790e987b7 prerequisite-patch-id: a0cfa5d8cdb49bbe9d4739afa90991f882950881 prerequisite-patch-id: 61ceecb41cfd9029bfb267f7b7c5330a2d7e5edc prerequisite-patch-id: d834ece14ffb525b8c3e661e78736692f33fca9b prerequisite-patch-id: 88c9f9637335fdc4107d42db67b9110c9b73ead3 prerequisite-patch-id: ebc26ed3f97f7babc0fc805152acb578f5eff922 prerequisite-patch-id: e85a9ca22facac4d5b5562a2708b7332478d6db4 prerequisite-patch-id: ff5bd799e4cb905fef6cf1cd0ce757980e1d34b7 prerequisite-patch-id: a341d4e8a8e25cb711309123939235fcb3c10c1a prerequisite-patch-id: 749e4eafb431857ee2bec4ac8e78a682f6a57588 prerequisite-patch-id: d4a3666ce2e7135402537cea60e9e6f0435230bf prerequisite-patch-id: fa8ad1bfce7d6ab74ad63ff8d31dff3c2ccb5e43 prerequisite-patch-id: cc352634b8dfaf2d4243819362326a579e010c94 prerequisite-patch-id: 8e0fa3d987020ca06e22401bc4c69f834c38c3dc -- 2.17.1
[PATCH v4 3/3] riscv: dts: starfive: Enable PCIe host controller
From: Mason Huo
Enable and add pinctrl configuration for PCIe host controller.
Also add JH7110 stg syscon configuration.
Signed-off-by: Mason Huo
Signed-off-by: Minda Chen
---
.../dts/jh7110-starfive-visionfive-2.dtsi | 11 +++
arch/riscv/dts/jh7110.dtsi| 74 +++
2 files changed, 85 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..12245576ac 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -7,6 +7,7 @@
#include "jh7110.dtsi"
#include
+#include
/ {
aliases {
serial0 = &uart0;
@@ -300,6 +301,16 @@
};
};
+&pcie0 {
+ reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+};
+
+&pcie1 {
+ reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
<&syscrg JH7110_SYSCLK_BUS_ROOT>,
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..eaf8035a61 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -569,5 +569,79 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ pcie0: pcie@2B00 {
+ compatible = "starfive,jh7110-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ reg = <0x0 0x2B00 0x0 0x100>,
+ <0x9 0x4000 0x0 0x1000>;
+ reg-names = "reg", "config";
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x8200 0x0 0x3000 0x0 0x3000
0x0 0x0800>,
+ <0xc300 0x9 0x 0x9 0x 0x0
0x4000>;
+ msi-parent = <&plic>;
+ interrupts = <56>;
+ interrupt-controller;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ <0x0 0x0 0x0 0x2 &plic 0x2>,
+ <0x0 0x0 0x0 0x3 &plic 0x3>,
+ <0x0 0x0 0x0 0x4 &plic 0x4>;
+ resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV>,
+<&stgcrg JH7110_STGRST_PCIE0_BRG>,
+<&stgcrg JH7110_STGRST_PCIE0_CORE>,
+<&stgcrg JH7110_STGRST_PCIE0_APB>;
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_TL>,
+<&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_APB>;
+ clock-names = "noc_bus_stg_axi", "pcie0_tl",
"pcie0_axi", "pcie0_apb";
+ status = "disabled";
+ };
+
+ pcie1: pcie@2C00 {
+ compatible = "starfive,jh7110-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ reg = <0x0 0x2C00 0x0 0x100>,
+ <0x9 0xc000 0x0 0x1000>;
+ reg-names = "reg", "config";
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x8200 0x0 0x3800 0x0 0x3800
0x0 0x0800>,
+ <0xc300 0x9 0x8000 0x9 0x8000 0x0
0x4000>;
+ msi-parent = <&plic>;
+ interrupts = <57>;
+ interrupt-controller;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ <0x0 0x0 0x0 0x2 &plic 0x2>,
+ <0x0 0x0 0x0 0x3 &plic 0x3>,
+ <0x0 0x0 0x0 0x4 &plic 0x4>;
+ resets = <&stgcrg JH7110_STGRST_PCIE1_M
[PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver
From: Mason Huo
Add pcie driver for StarFive JH7110, the driver depends on
starfive gpio, pinctrl, clk and reset driver to do init.
Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.
Signed-off-by: Mason Huo
Signed-off-by: Minda Chen
---
drivers/pci/Kconfig| 9 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_starfive_jh7110.c | 465 +
3 files changed, 475 insertions(+)
create mode 100644 drivers/pci/pcie_starfive_jh7110.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d2652..f37b6baa25 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -374,4 +374,13 @@ config PCIE_UNIPHIER
Say Y here if you want to enable PCIe controller support on
UniPhier SoCs.
+config PCIE_STARFIVE_JH7110
+ bool "Enable Starfive JH7110 PCIe driver"
+ imply STARFIVE_JH7110
+ imply CLK_JH7110
+ imply RESET_JH7110
+ help
+ Say Y here if you want to enable PCIe controller support on
+ StarFive JH7110 SoC.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 49506e7ba5..bbe3323bb5 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_starfive_jh7110.c
b/drivers/pci/pcie_starfive_jh7110.c
new file mode 100644
index 00..130181013e
--- /dev/null
+++ b/drivers/pci/pcie_starfive_jh7110.c
@@ -0,0 +1,465 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive PLDA PCIe host controller driver
+ *
+ * Copyright (c) 2023 Starfive, Inc.
+ * Author: Mason Huo
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GEN_SETTINGS 0x80
+#define PCIE_PCI_IDS 0x9C
+#define PCIE_WINROM0xFC
+#define PMSG_SUPPORT_RX0x3F0
+#define PCI_MISC 0xB4
+
+#define PLDA_EP_ENABLE 0
+#define PLDA_RP_ENABLE 1
+
+#define IDS_CLASS_CODE_SHIFT 8
+
+#define PREF_MEM_WIN_64_SUPPORTBIT(3)
+#define PMSG_LTR_SUPPORT BIT(2)
+#define PLDA_FUNCTION_DIS BIT(15)
+#define PLDA_FUNC_NUM 4
+#define PLDA_PHY_FUNC_SHIFT9
+
+#define XR3PCI_ATR_AXI4_SLV0 0x800
+#define XR3PCI_ATR_SRC_ADDR_LOW0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
+#define XR3PCI_ATR_TRSL_PARAM 0x10
+#define XR3PCI_ATR_TABLE_OFFSET0x20
+#define XR3PCI_ATR_MAX_TABLE_NUM 8
+
+#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
+#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
+#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
+#define XR3_PCI_ECAM_SIZE 28
+#define XR3PCI_ATR_TRSL_DIRBIT(22)
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
+#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
+
+/* system control */
+#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
+#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
+#define STG_SYSCON_CLKREQ_MASK BIT(22)
+#define STG_SYSCON_CKREF_SRC_SHIFT 18
+#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
+
+struct starfive_pcie {
+ struct udevice *dev;
+
+ void __iomem *reg_base;
+ void __iomem *cfg_base;
+
+ struct regmap *regmap;
+ u32 stg_arfun;
+ u32 stg_awfun;
+ u32 stg_rp_nep;
+
+ struct clk_bulk clks;
+ struct reset_ctl_bulk rsts;
+ struct gpio_descreset_gpio;
+
+ int atr_table_num;
+ int sec_busno;
+};
+
+static bool starfive_pcie_addr_valid(pci_dev_t bdf, struct starfive_pcie *priv)
+{
+ /*
+* Single device limitation.
+* For JH7110 SoC limitation, one bus can only connnect one device.
+* And PCIe controller contain HW issue that secondary bus of
+* host bridge emumerate duplicate devices.
+* Only can access device 0 in secondary bus.
+*/
+ if (PCI_BUS(bdf) == priv->sec_busno && PCI_DEV(bdf) > 0)
+ return false;
+
+ return true;
+}
+
+static int starfive_pcie_conf_address(const struct udevice *udev, pci_dev_t
bdf,
+ uint offset, void **paddr)
+{
+ struct starfive_pcie *priv = dev_get_priv(u
Re: [PATCH 7/8] riscv: spl: Remove relocation sections
> From: Bin Meng
> Sent: Thursday, March 30, 2023 12:20 PM
> To: u-boot@lists.denx.de
> Cc: Andrew Scull ; Leo Yu-Chi Liang(梁育齊)
> ; Rick Jian-Zhi Chen(陳建志) ; Simon
> Glass
> Subject: [PATCH 7/8] riscv: spl: Remove relocation sections
>
> U-Boot SPL is not relocable. Drop these relocation sections.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/cpu/u-boot-spl.lds | 25 -
> 1 file changed, 25 deletions(-)
>
> diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
> index 993536302a..c3b4907905 100644
> --- a/arch/riscv/cpu/u-boot-spl.lds
> +++ b/arch/riscv/cpu/u-boot-spl.lds
> @@ -32,14 +32,6 @@ SECTIONS
> } > .spl_mem
> . = ALIGN(4);
>
> - .got : {
> - __got_start = .;
> - *(.got.plt) *(.got)
> - __got_end = .;
> - } > .spl_mem
> -
> - . = ALIGN(4);
> -
> __u_boot_list : {
> KEEP(*(SORT(__u_boot_list*)));
> } > .spl_mem
> @@ -54,23 +46,6 @@ SECTIONS
>
> . = ALIGN(4);
>
> - /DISCARD/ : { *(.rela.plt*) }
> - .rela.dyn : {
> - __rel_dyn_start = .;
> - *(.rela*)
> - __rel_dyn_end = .;
> - } > .spl_mem
This patch will cause u-boot-spl build fail:
...
LD spl/u-boot-spl
riscv64-linux-ld.bfd: arch/riscv/cpu/start.o: in function `fix_rela_dyn':
/home/u-boot-riscv/arch/riscv/cpu/start.S:299: undefined reference to
`__rel_dyn_start'
riscv64-linux-ld.bfd: arch/riscv/cpu/start.o: in function `.L0 ':
Thanks,
Rick
> -
> - . = ALIGN(4);
> -
> - .dynsym : {
> - __dyn_sym_start = .;
> - *(.dynsym)
> - __dyn_sym_end = .;
> - } > .spl_mem
> -
> - . = ALIGN(4);
> -
> _end = .;
> _image_binary_end = .;
>
> --
> 2.34.1
Re: [PATCH] configs: rk3588: rename defconfig for rock-5b
Hi,
On 4/10/23 12:12, Kever Yang wrote:
Hi,
On 2023/4/8 17:33, FUKAUMI Naoki wrote:
it should be rock-5b-rk3588_defconfig.
Why it should be rock-5b?
Its seems rock pi has many boards and with different name, I thinks
rock5b is a reasonable config name
because there is no name rule for rock pi boards till now.
configs/rockpro64-rk3399_defconfig
> configs/rock64-rk3328_defconfig
> configs/rock960-rk3399_defconfig
above 3 are not made by Radxa. please ignore for now.
configs/rock_defconfig
> configs/rock2_defconfig
above 2 are made by Radxa. but very old, no name rule.
configs/rock-pi-s-rk3308_defconfig
configs/rock-pi-e-rk3328_defconfig
configs/rock5b-rk3588_defconfig
configs/rock-pi-4-rk3399_defconfig
configs/rock-pi-4c-rk3399_defconfig
configs/rock-pi-n10-rk3399pro_defconfig
configs/rock-3a-rk3568_defconfig
configs/rock-pi-n8-rk3288_defconfig
$ grep -h CONFIG_DEFAULT_DEVICE_TREE configs/*rock*
CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960"
CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c"
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4b"
CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e"
CONFIG_DEFAULT_DEVICE_TREE="rk3399pro-rock-pi-n10"
CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock-pi-n8"
CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s"
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
I think "rock-5b" is better than "rock5b".
--
FUKAUMI Naoki
Thanks,
- Kever
Signed-off-by: FUKAUMI Naoki
---
configs/{rock5b-rk3588_defconfig => rock-5b-rk3588_defconfig} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename configs/{rock5b-rk3588_defconfig => rock-5b-rk3588_defconfig}
(100%)
diff --git a/configs/rock5b-rk3588_defconfig
b/configs/rock-5b-rk3588_defconfig
similarity index 100%
rename from configs/rock5b-rk3588_defconfig
rename to configs/rock-5b-rk3588_defconfig
[PATCH] board: ti: j721s2: Add support to detect daughtercards
From: Kishon Vijay Abraham I
Add support to detect daughtercards (GESI Ethernet card) in-order
to set the MAC address of the main CPSW2G interface.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Siddharth Vadapalli
---
board/ti/j721s2/evm.c | 130 ++
1 file changed, 130 insertions(+)
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index c86715fa21..b920c441a9 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -171,6 +171,135 @@ static void setup_serial(void)
snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
env_set("serial#", serial_string);
}
+
+/*
+ * Declaration of daughtercards to probe. Note that when adding more
+ * cards they should be grouped by the 'i2c_addr' field to allow for a
+ * more efficient probing process.
+ */
+static const struct {
+ u8 i2c_addr;/* I2C address of card EEPROM */
+ char *card_name;/* EEPROM-programmed card name */
+ char *dtbo_name;/* Device tree overlay to apply */
+ u8 eth_offset; /* ethXaddr MAC address index offset */
+} ext_cards[] = {
+ {
+ 0x52,
+ "J7X-GESI-EXP",
+ "k3-j721s2-gesi-exp-board.dtbo",
+ 1, /* Start populating from eth1addr */
+ },
+};
+
+#define DAUGHTER_CARD_NO_OF_MAC_ADDR 5
+static bool daughter_card_detect_flags[ARRAY_SIZE(ext_cards)];
+
+static int probe_daughtercards(void)
+{
+ char mac_addr[DAUGHTER_CARD_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+ bool eeprom_read_success;
+ struct ti_am6_eeprom ep;
+ u8 previous_i2c_addr;
+ u8 mac_addr_cnt;
+ int i;
+ int ret;
+
+ /* Mark previous I2C address variable as not populated */
+ previous_i2c_addr = 0xff;
+
+ /* No EEPROM data was read yet */
+ eeprom_read_success = false;
+
+ /* Iterate through list of daughtercards */
+ for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+ /* Obtain card-specific I2C address */
+ u8 i2c_addr = ext_cards[i].i2c_addr;
+
+ /* Read card EEPROM if not already read previously */
+ if (i2c_addr != previous_i2c_addr) {
+ /* Store I2C address so we can avoid reading twice */
+ previous_i2c_addr = i2c_addr;
+
+ /* Get and parse the daughter card EEPROM record */
+ ret = ti_i2c_eeprom_am6_get(CONFIG_EEPROM_BUS_ADDRESS,
+ i2c_addr,
+ &ep,
+ (char **)mac_addr,
+
DAUGHTER_CARD_NO_OF_MAC_ADDR,
+ &mac_addr_cnt);
+ if (ret) {
+ debug("%s: No daughtercard EEPROM at 0x%02x
found %d\n",
+ __func__, i2c_addr, ret);
+ eeprom_read_success = false;
+ /* Skip to the next daughtercard to probe */
+ continue;
+ }
+
+ /* EEPROM read successful, okay to further process. */
+ eeprom_read_success = true;
+ }
+
+ /* Only continue processing if EEPROM data was read */
+ if (!eeprom_read_success)
+ continue;
+
+ /* Only process the parsed data if we found a match */
+ if (strncmp(ep.name, ext_cards[i].card_name, sizeof(ep.name)))
+ continue;
+
+ printf("Detected: %s rev %s\n", ep.name, ep.version);
+ daughter_card_detect_flags[i] = true;
+
+ if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ int j;
+ /*
+* Populate any MAC addresses from daughtercard into
the U-Boot
+* environment, starting with a card-specific offset so
we can
+* have multiple ext_cards contribute to the MAC pool
in a well-
+* defined manner.
+*/
+ for (j = 0; j < mac_addr_cnt; j++) {
+ if (!is_valid_ethaddr((u8 *)mac_addr[j]))
+ continue;
+
+ eth_env_set_enetaddr_by_index("eth",
ext_cards[i].eth_offset + j,
+ (uchar
*)mac_addr[j]);
+ }
+ }
+ }
+
+ if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ char name_overlays[1024] = { 0 };
+
+ for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+ if (!daughter_card_detect_fl
Re: [PATCH v5 0/4] FMP versioning support
Hi Kojima-san, On Mon, Apr 10, 2023 at 06:07:28PM +0900, Masahisa Kojima wrote: > Firmware version management is not implemented in the current > FMP implementation. This series aims to add the versioning support > in FMP. > > There is a major design change in v5. > Until v4, the fw_version and lowest_supported_version are stored > as a EFI variable. If the backing storage is a file we can't trust > any of that information since anyone can tamper with the file, > although the variables are defined as RO. > With that, we store the version information in the device tree > in v5. We can trust the information from dtb as long as the former > stage boot loader verifies the image containing the dtb. I have a basic question here. You said that the former-stage boot loader is responsible for maintaining the dtb with the correct firmware version to be passed to U-Boot. But how can it obtain the new version number of firmware which is only contained in a capsule file (and its header)? Looking into you pytest, you simply always *reboot* the sandbox with an already-modified dtb (test_ver.dtb). (Please note that, at the reboot time, a capsule has not been applied yet.) I believe that your current approach is rather incomplete as a workable solution. -Takahiro Akashi > The disadvantage of this design change is that we need to maintain > the fw_version in both device tree and FMP Payload Header. > It is inevitable since not all the capsule files contain the dtb. > > EDK II reference implementation utilizes the FMP Payload Header > inserted right before the capsule payload. With this series, > U-Boot also follows the EDK II implementation. > > Currently, there is no way to know the current running firmware > version through the EFI interface. FMP->GetImageInfo() returns > always 0 for the version number. So a user can not know that > expected firmware is running after the capsule update. > > With this series applied, version number can be specified > in the capsule file generation with mkeficapsule tool, then > user can know the running firmware version through > FMP->GetImageInfo() and ESRT. > > Note that this series does not mandate the FMP Payload Header, > compatible with boards that are already using the existing > U-Boot FMP implementation. > If no FMP Payload Header is found in the capsule file, fw_version, > lowest supported version, last attempt version and last attempt > status is set to 0 and this is the same behavior as existing FMP > implementation. > > Major Changes in v5: > - major design changes, versioning is implemented with > device tree instead of EFI variable > > Major Changes in v4: > - add python-based test > > Major Changes in v3: > - exclude CONFIG_FWU_MULTI > > Masahisa Kojima (4): > efi_loader: get version information from device tree > efi_loader: check lowest supported version > mkeficapsule: add FMP Payload Header > test/py: efi_capsule: test for FMP versioning > > .../firmware/firmware-version.txt | 25 +++ > doc/mkeficapsule.1| 10 + > lib/efi_loader/efi_firmware.c | 187 +--- > test/py/tests/test_efi_capsule/conftest.py| 73 +++ > .../test_capsule_firmware_fit.py | 187 > .../test_capsule_firmware_raw.py | 201 ++ > .../test_capsule_firmware_signed_fit.py | 165 ++ > .../test_capsule_firmware_signed_raw.py | 169 +++ > test/py/tests/test_efi_capsule/version.dts| 27 +++ > tools/eficapsule.h| 30 +++ > tools/mkeficapsule.c | 37 +++- > 11 files changed, 1082 insertions(+), 29 deletions(-) > create mode 100644 doc/device-tree-bindings/firmware/firmware-version.txt > create mode 100644 test/py/tests/test_efi_capsule/version.dts > > -- > 2.17.1 >
Re: [PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On Tue, Apr 11, 2023 at 9:03 AM Minda Chen wrote:
>
> From: Mason Huo
>
> Add pcie driver for StarFive JH7110, the driver depends on
> starfive gpio, pinctrl, clk and reset driver to do init.
>
> Several devices are tested:
> a) M.2 NVMe SSD
> b) Realtek 8169 Ethernet adapter.
>
> Signed-off-by: Mason Huo
> Signed-off-by: Minda Chen
> ---
> drivers/pci/Kconfig| 9 +
> drivers/pci/Makefile | 1 +
> drivers/pci/pcie_starfive_jh7110.c | 465 +
> 3 files changed, 475 insertions(+)
> create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index ef328d2652..f37b6baa25 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -374,4 +374,13 @@ config PCIE_UNIPHIER
> Say Y here if you want to enable PCIe controller support on
> UniPhier SoCs.
>
> +config PCIE_STARFIVE_JH7110
> + bool "Enable Starfive JH7110 PCIe driver"
> + imply STARFIVE_JH7110
> + imply CLK_JH7110
> + imply RESET_JH7110
> + help
> + Say Y here if you want to enable PCIe controller support on
> + StarFive JH7110 SoC.
> +
> endif
> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> index 49506e7ba5..bbe3323bb5 100644
> --- a/drivers/pci/Makefile
> +++ b/drivers/pci/Makefile
> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
> diff --git a/drivers/pci/pcie_starfive_jh7110.c
> b/drivers/pci/pcie_starfive_jh7110.c
> new file mode 100644
> index 00..130181013e
> --- /dev/null
> +++ b/drivers/pci/pcie_starfive_jh7110.c
> @@ -0,0 +1,465 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * StarFive PLDA PCIe host controller driver
> + *
> + * Copyright (c) 2023 Starfive, Inc.
> + * Author: Mason Huo
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define GEN_SETTINGS 0x80
> +#define PCIE_PCI_IDS 0x9C
> +#define PCIE_WINROM0xFC
> +#define PMSG_SUPPORT_RX0x3F0
> +#define PCI_MISC 0xB4
> +
> +#define PLDA_EP_ENABLE 0
> +#define PLDA_RP_ENABLE 1
> +
> +#define IDS_CLASS_CODE_SHIFT 8
> +
> +#define PREF_MEM_WIN_64_SUPPORTBIT(3)
> +#define PMSG_LTR_SUPPORT BIT(2)
> +#define PLDA_FUNCTION_DIS BIT(15)
> +#define PLDA_FUNC_NUM 4
> +#define PLDA_PHY_FUNC_SHIFT9
> +
> +#define XR3PCI_ATR_AXI4_SLV0 0x800
> +#define XR3PCI_ATR_SRC_ADDR_LOW0x0
> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
> +#define XR3PCI_ATR_TRSL_PARAM 0x10
> +#define XR3PCI_ATR_TABLE_OFFSET0x20
> +#define XR3PCI_ATR_MAX_TABLE_NUM 8
> +
> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
> +#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
> +#define XR3_PCI_ECAM_SIZE 28
> +#define XR3PCI_ATR_TRSL_DIRBIT(22)
> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
> +
> +/* system control */
> +#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
> +#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
> +#define STG_SYSCON_CLKREQ_MASK BIT(22)
> +#define STG_SYSCON_CKREF_SRC_SHIFT 18
> +#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
> +
> +struct starfive_pcie {
> + struct udevice *dev;
> +
> + void __iomem *reg_base;
> + void __iomem *cfg_base;
> +
> + struct regmap *regmap;
> + u32 stg_arfun;
> + u32 stg_awfun;
> + u32 stg_rp_nep;
> +
> + struct clk_bulk clks;
> + struct reset_ctl_bulk rsts;
> + struct gpio_descreset_gpio;
> +
> + int atr_table_num;
> + int sec_busno;
> +};
> +
> +static bool starfive_pcie_addr_valid(pci_dev_t bdf, struct starfive_pcie
> *priv)
> +{
> + /*
> +* Single device limitation.
> +* For JH7110 SoC limitation, one bus can only connnect one device.
> +* And PCIe controller contain HW issue that secondary bus of
> +* host bridge emumerate duplicate devices.
> +* Only can access device 0
Re: [PATCH v5 0/4] FMP versioning support
Hi Akashi-san, On Tue, 11 Apr 2023 at 10:48, Takahiro Akashi wrote: > > Hi Kojima-san, > > On Mon, Apr 10, 2023 at 06:07:28PM +0900, Masahisa Kojima wrote: > > Firmware version management is not implemented in the current > > FMP implementation. This series aims to add the versioning support > > in FMP. > > > > There is a major design change in v5. > > Until v4, the fw_version and lowest_supported_version are stored > > as a EFI variable. If the backing storage is a file we can't trust > > any of that information since anyone can tamper with the file, > > although the variables are defined as RO. > > With that, we store the version information in the device tree > > in v5. We can trust the information from dtb as long as the former > > stage boot loader verifies the image containing the dtb. > > I have a basic question here. > You said that the former-stage boot loader is responsible for maintaining > the dtb with the correct firmware version to be passed to U-Boot. > But how can it obtain the new version number of firmware which is only > contained in a capsule file (and its header)? Yes, there is a problem that we need to maintain the fw_version in both FMP Payload Header and dtb, it is not an ideal situation and prone to errors. On second thought, I need to change my approach again. fw_version: specified in FMP Payload Header and stored in EFI variable lowest_supported_version: stored in dtb When the capsule update is performed, U-Boot gets the fw_version from FMP Payload Header of the ongoing capsule, then checks if the version is equal to or greater than lowest_supported_version read from dtb. One disadvantage is that fw_version in the EFI variable can be tampered if the backing storage is file, but it is not the critical issue. Thanks, Masahisa Kojima > > Looking into you pytest, you simply always *reboot* the sandbox with > an already-modified dtb (test_ver.dtb). > (Please note that, at the reboot time, a capsule has not been > applied yet.) > > I believe that your current approach is rather incomplete > as a workable solution. > > -Takahiro Akashi > > > The disadvantage of this design change is that we need to maintain > > the fw_version in both device tree and FMP Payload Header. > > It is inevitable since not all the capsule files contain the dtb. > > > > EDK II reference implementation utilizes the FMP Payload Header > > inserted right before the capsule payload. With this series, > > U-Boot also follows the EDK II implementation. > > > > Currently, there is no way to know the current running firmware > > version through the EFI interface. FMP->GetImageInfo() returns > > always 0 for the version number. So a user can not know that > > expected firmware is running after the capsule update. > > > > With this series applied, version number can be specified > > in the capsule file generation with mkeficapsule tool, then > > user can know the running firmware version through > > FMP->GetImageInfo() and ESRT. > > > > Note that this series does not mandate the FMP Payload Header, > > compatible with boards that are already using the existing > > U-Boot FMP implementation. > > If no FMP Payload Header is found in the capsule file, fw_version, > > lowest supported version, last attempt version and last attempt > > status is set to 0 and this is the same behavior as existing FMP > > implementation. > > > > Major Changes in v5: > > - major design changes, versioning is implemented with > > device tree instead of EFI variable > > > > Major Changes in v4: > > - add python-based test > > > > Major Changes in v3: > > - exclude CONFIG_FWU_MULTI > > > > Masahisa Kojima (4): > > efi_loader: get version information from device tree > > efi_loader: check lowest supported version > > mkeficapsule: add FMP Payload Header > > test/py: efi_capsule: test for FMP versioning > > > > .../firmware/firmware-version.txt | 25 +++ > > doc/mkeficapsule.1| 10 + > > lib/efi_loader/efi_firmware.c | 187 +--- > > test/py/tests/test_efi_capsule/conftest.py| 73 +++ > > .../test_capsule_firmware_fit.py | 187 > > .../test_capsule_firmware_raw.py | 201 ++ > > .../test_capsule_firmware_signed_fit.py | 165 ++ > > .../test_capsule_firmware_signed_raw.py | 169 +++ > > test/py/tests/test_efi_capsule/version.dts| 27 +++ > > tools/eficapsule.h| 30 +++ > > tools/mkeficapsule.c | 37 +++- > > 11 files changed, 1082 insertions(+), 29 deletions(-) > > create mode 100644 doc/device-tree-bindings/firmware/firmware-version.txt > > create mode 100644 test/py/tests/test_efi_capsule/version.dts > > > > -- > > 2.17.1 > >
Re: [PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On 2023/4/11 10:55, Bin Meng wrote:
> On Tue, Apr 11, 2023 at 9:03 AM Minda Chen
> wrote:
>>
>> From: Mason Huo
>>
>> Add pcie driver for StarFive JH7110, the driver depends on
>> starfive gpio, pinctrl, clk and reset driver to do init.
>>
>> Several devices are tested:
>> a) M.2 NVMe SSD
>> b) Realtek 8169 Ethernet adapter.
>>
>> Signed-off-by: Mason Huo
>> Signed-off-by: Minda Chen
>> ---
>> drivers/pci/Kconfig| 9 +
>> drivers/pci/Makefile | 1 +
>> drivers/pci/pcie_starfive_jh7110.c | 465 +
>> 3 files changed, 475 insertions(+)
>> create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>>
>> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
>> index ef328d2652..f37b6baa25 100644
>> --- a/drivers/pci/Kconfig
>> +++ b/drivers/pci/Kconfig
>> @@ -374,4 +374,13 @@ config PCIE_UNIPHIER
>> Say Y here if you want to enable PCIe controller support on
>> UniPhier SoCs.
>>
>> +config PCIE_STARFIVE_JH7110
>> + bool "Enable Starfive JH7110 PCIe driver"
>> + imply STARFIVE_JH7110
>> + imply CLK_JH7110
>> + imply RESET_JH7110
>> + help
>> + Say Y here if you want to enable PCIe controller support on
>> + StarFive JH7110 SoC.
>> +
>> endif
>> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
>> index 49506e7ba5..bbe3323bb5 100644
>> --- a/drivers/pci/Makefile
>> +++ b/drivers/pci/Makefile
>> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
>> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
>> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
>> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
>> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
>> diff --git a/drivers/pci/pcie_starfive_jh7110.c
>> b/drivers/pci/pcie_starfive_jh7110.c
>> new file mode 100644
>> index 00..130181013e
>> --- /dev/null
>> +++ b/drivers/pci/pcie_starfive_jh7110.c
>> @@ -0,0 +1,465 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * StarFive PLDA PCIe host controller driver
>> + *
>> + * Copyright (c) 2023 Starfive, Inc.
>> + * Author: Mason Huo
>> + *
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define GEN_SETTINGS 0x80
>> +#define PCIE_PCI_IDS 0x9C
>> +#define PCIE_WINROM0xFC
>> +#define PMSG_SUPPORT_RX0x3F0
>> +#define PCI_MISC 0xB4
>> +
>> +#define PLDA_EP_ENABLE 0
>> +#define PLDA_RP_ENABLE 1
>> +
>> +#define IDS_CLASS_CODE_SHIFT 8
>> +
>> +#define PREF_MEM_WIN_64_SUPPORTBIT(3)
>> +#define PMSG_LTR_SUPPORT BIT(2)
>> +#define PLDA_FUNCTION_DIS BIT(15)
>> +#define PLDA_FUNC_NUM 4
>> +#define PLDA_PHY_FUNC_SHIFT9
>> +
>> +#define XR3PCI_ATR_AXI4_SLV0 0x800
>> +#define XR3PCI_ATR_SRC_ADDR_LOW0x0
>> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
>> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
>> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
>> +#define XR3PCI_ATR_TRSL_PARAM 0x10
>> +#define XR3PCI_ATR_TABLE_OFFSET0x20
>> +#define XR3PCI_ATR_MAX_TABLE_NUM 8
>> +
>> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
>> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
>> +#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
>> +#define XR3_PCI_ECAM_SIZE 28
>> +#define XR3PCI_ATR_TRSL_DIRBIT(22)
>> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
>> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
>> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
>> +
>> +/* system control */
>> +#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
>> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
>> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
>> +#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
>> +#define STG_SYSCON_CLKREQ_MASK BIT(22)
>> +#define STG_SYSCON_CKREF_SRC_SHIFT 18
>> +#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
>> +
>> +struct starfive_pcie {
>> + struct udevice *dev;
>> +
>> + void __iomem *reg_base;
>> + void __iomem *cfg_base;
>> +
>> + struct regmap *regmap;
>> + u32 stg_arfun;
>> + u32 stg_awfun;
>> + u32 stg_rp_nep;
>> +
>> + struct clk_bulk clks;
>> + struct reset_ctl_bulk rsts;
>> + struct gpio_descreset_gpio;
>> +
>> + int atr_table_num;
>> + int sec_busno;
>> +};
>> +
>> +static bool starfive_pcie_addr_valid(pci_dev_t bdf, struct starfive_pcie
>> *priv)
>> +{
>> + /*
>> +* Single device limitation.
>> +* For JH7110 SoC limitation, one b
Re: [PATCH 6/6] m68k: upgrading all boards to dm i2c
Hello Angelo, On 05.04.23 00:59, Angelo Dureghello wrote: > Upgrading all board configs where i2c is involved to DM i2c. > > Signed-off-by: Angelo Dureghello > --- > configs/M5208EVBE_defconfig | 5 + > configs/M5235EVB_Flash32_defconfig| 1 + > configs/M5235EVB_defconfig| 1 + > configs/M5253DEMO_defconfig | 5 + > configs/M5275EVB_defconfig| 5 + > configs/M53017EVB_defconfig | 6 ++ > configs/M5329AFEE_defconfig | 6 ++ > configs/M5329BFEE_defconfig | 6 ++ > configs/M5373EVB_defconfig| 3 ++- > configs/astro_mcf5373l_defconfig | 6 ++ > configs/eb_cpu5282_defconfig | 5 ++--- > configs/eb_cpu5282_internal_defconfig | 5 ++--- > configs/stmark2_defconfig | 4 > 13 files changed, 23 insertions(+), 35 deletions(-) Thanks for this series, I did not find a cover letter Email, so I have here a common question: You rename in patch 1/6 CONFIG_SYS_I2C_0 -> CFG_SYS_I2C_0 but only add in patch 2/6 for the stmark2 this renamed define, and add DTS nodes for other boards in patch 5/6 and here the defconfig changes... may I oversee something obvious, but do the other boards not also need some CFG_SYS_I2C_0 define? Thanks! bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On Tue, Apr 11, 2023 at 11:53 AM Minda Chen wrote:
>
>
>
> On 2023/4/11 10:55, Bin Meng wrote:
> > On Tue, Apr 11, 2023 at 9:03 AM Minda Chen
> > wrote:
> >>
> >> From: Mason Huo
> >>
> >> Add pcie driver for StarFive JH7110, the driver depends on
> >> starfive gpio, pinctrl, clk and reset driver to do init.
> >>
> >> Several devices are tested:
> >> a) M.2 NVMe SSD
> >> b) Realtek 8169 Ethernet adapter.
> >>
> >> Signed-off-by: Mason Huo
> >> Signed-off-by: Minda Chen
> >> ---
> >> drivers/pci/Kconfig| 9 +
> >> drivers/pci/Makefile | 1 +
> >> drivers/pci/pcie_starfive_jh7110.c | 465 +
> >> 3 files changed, 475 insertions(+)
> >> create mode 100644 drivers/pci/pcie_starfive_jh7110.c
> >>
> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> >> index ef328d2652..f37b6baa25 100644
> >> --- a/drivers/pci/Kconfig
> >> +++ b/drivers/pci/Kconfig
> >> @@ -374,4 +374,13 @@ config PCIE_UNIPHIER
> >> Say Y here if you want to enable PCIe controller support on
> >> UniPhier SoCs.
> >>
> >> +config PCIE_STARFIVE_JH7110
> >> + bool "Enable Starfive JH7110 PCIe driver"
> >> + imply STARFIVE_JH7110
> >> + imply CLK_JH7110
> >> + imply RESET_JH7110
> >> + help
> >> + Say Y here if you want to enable PCIe controller support on
> >> + StarFive JH7110 SoC.
> >> +
> >> endif
> >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> >> index 49506e7ba5..bbe3323bb5 100644
> >> --- a/drivers/pci/Makefile
> >> +++ b/drivers/pci/Makefile
> >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
> >> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
> >> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
> >> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
> >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
> >> diff --git a/drivers/pci/pcie_starfive_jh7110.c
> >> b/drivers/pci/pcie_starfive_jh7110.c
> >> new file mode 100644
> >> index 00..130181013e
> >> --- /dev/null
> >> +++ b/drivers/pci/pcie_starfive_jh7110.c
> >> @@ -0,0 +1,465 @@
> >> +// SPDX-License-Identifier: GPL-2.0+
> >> +/*
> >> + * StarFive PLDA PCIe host controller driver
> >> + *
> >> + * Copyright (c) 2023 Starfive, Inc.
> >> + * Author: Mason Huo
> >> + *
> >> + */
> >> +
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +
> >> +DECLARE_GLOBAL_DATA_PTR;
> >> +
> >> +#define GEN_SETTINGS 0x80
> >> +#define PCIE_PCI_IDS 0x9C
> >> +#define PCIE_WINROM0xFC
> >> +#define PMSG_SUPPORT_RX0x3F0
> >> +#define PCI_MISC 0xB4
> >> +
> >> +#define PLDA_EP_ENABLE 0
> >> +#define PLDA_RP_ENABLE 1
> >> +
> >> +#define IDS_CLASS_CODE_SHIFT 8
> >> +
> >> +#define PREF_MEM_WIN_64_SUPPORTBIT(3)
> >> +#define PMSG_LTR_SUPPORT BIT(2)
> >> +#define PLDA_FUNCTION_DIS BIT(15)
> >> +#define PLDA_FUNC_NUM 4
> >> +#define PLDA_PHY_FUNC_SHIFT9
> >> +
> >> +#define XR3PCI_ATR_AXI4_SLV0 0x800
> >> +#define XR3PCI_ATR_SRC_ADDR_LOW0x0
> >> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
> >> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
> >> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
> >> +#define XR3PCI_ATR_TRSL_PARAM 0x10
> >> +#define XR3PCI_ATR_TABLE_OFFSET0x20
> >> +#define XR3PCI_ATR_MAX_TABLE_NUM 8
> >> +
> >> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
> >> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
> >> +#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
> >> +#define XR3_PCI_ECAM_SIZE 28
> >> +#define XR3PCI_ATR_TRSL_DIRBIT(22)
> >> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
> >> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
> >> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
> >> +
> >> +/* system control */
> >> +#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
> >> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
> >> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
> >> +#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
> >> +#define STG_SYSCON_CLKREQ_MASK BIT(22)
> >> +#define STG_SYSCON_CKREF_SRC_SHIFT 18
> >> +#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
> >> +
> >> +struct starfive_pcie {
> >> + struct udevice *dev;
> >> +
> >> + void __iomem *reg_base;
> >> + void __iomem *cfg_base;
> >> +
> >> + struct regmap *regmap;
> >> + u32 stg_arfun;
> >> + u32 stg_awfun;
> >> + u32 stg_rp_nep;
> >> +
> >> + struct clk_bulk clks;
> >> + str
Re: [PATCH] configs: stm32mp15: increase malloc size for pre-reloc
Hi Patrick On 4/7/23 11:37, Patrick Delaunay wrote: > The early malloc usage increased so the associated defined > CONFIG_SYS_MALLOC_F_LEN need to be increased. > > For example, for stm32mp15_defconfig and > stm32mp157c-dk2-scmi.dtsi, we have: > > Early malloc usage: 280b8 / 8 > > Signed-off-by: Patrick Delaunay > --- > > configs/stm32mp15_defconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig > index 0005e4266441..2676ff381d85 100644 > --- a/configs/stm32mp15_defconfig > +++ b/configs/stm32mp15_defconfig > @@ -1,7 +1,7 @@ > CONFIG_ARM=y > CONFIG_ARCH_STM32MP=y > CONFIG_TFABOOT=y > -CONFIG_SYS_MALLOC_F_LEN=0x2 > +CONFIG_SYS_MALLOC_F_LEN=0x8 > CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc010 > CONFIG_ENV_OFFSET=0x48 > CONFIG_ENV_SECT_SIZE=0x4 Reviewed-by: Patrice Chotard Thanks Patrice
Re: [PATCH] mtd: rawnand: stm32_fmc2: remove unsupported EDO mode
Hi Christophe On 3/30/23 11:16, Christophe Kerello wrote: > Remove the EDO mode support from as the FMC2 controller does not > support the feature. > > Signed-off-by: Christophe Kerello > --- > > drivers/mtd/nand/raw/stm32_fmc2_nand.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c > b/drivers/mtd/nand/raw/stm32_fmc2_nand.c > index fb3279b405e..69dbb629e93 100644 > --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c > +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c > @@ -735,6 +735,9 @@ static int stm32_fmc2_nfc_setup_interface(struct mtd_info > *mtd, int chipnr, > if (IS_ERR(sdrt)) > return PTR_ERR(sdrt); > > + if (sdrt->tRC_min < 3) > + return -EOPNOTSUPP; > + > if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) > return 0; > Reviewed-by: Patrice Chotard Thanks Patrice
Re: [PATCH] ARM: dts: stm32: add FMC support on STM32MP13x SoC family
Hi Christophe
On 3/30/23 11:26, Christophe Kerello wrote:
> Add FMC support on STM32MP13x SoC family.
>
> Signed-off-by: Christophe Kerello
> ---
>
> arch/arm/dts/stm32mp131.dtsi | 33 +
> 1 file changed, 33 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
> index 3cf51f09bcb..cf1171bc9bb 100644
> --- a/arch/arm/dts/stm32mp131.dtsi
> +++ b/arch/arm/dts/stm32mp131.dtsi
> @@ -191,6 +191,39 @@
> dma-requests = <48>;
> };
>
> + fmc: memory-controller@58002000 {
> + compatible = "st,stm32mp1-fmc2-ebi";
> + reg = <0x58002000 0x1000>;
> + ranges = <0 0 0x6000 0x0400>, /* EBI CS 1 */
> + <1 0 0x6400 0x0400>, /* EBI CS 2 */
> + <2 0 0x6800 0x0400>, /* EBI CS 3 */
> + <3 0 0x6c00 0x0400>, /* EBI CS 4 */
> + <4 0 0x8000 0x1000>; /* NAND */
> + #address-cells = <2>;
> + #size-cells = <1>;
> + clocks = <&rcc FMC_K>;
> + resets = <&rcc FMC_R>;
> + status = "disabled";
> +
> + nand-controller@4,0 {
> + compatible = "st,stm32mp1-fmc2-nfc";
> + reg = <4 0x 0x1000>,
> + <4 0x0801 0x1000>,
> + <4 0x0802 0x1000>,
> + <4 0x0100 0x1000>,
> + <4 0x0901 0x1000>,
> + <4 0x0902 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = ;
> + dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
> +<&mdma 24 0x2 0x12000a08 0x0 0x0>,
> +<&mdma 25 0x2 0x12000a0a 0x0 0x0>;
> + dma-names = "tx", "rx", "ecc";
> + status = "disabled";
> + };
> + };
> +
> sdmmc1: mmc@58005000 {
> compatible = "st,stm32-sdmmc2", "arm,pl18x",
> "arm,primecell";
> arm,primecell-periphid = <0x20253180>;
Reviewed-by: Patrice Chotard
Thanks
Patrice
