Re: [PATCH v4 2/6] arm: mach-k3: j721e_init: Move clk_k3 probe before loading TIFS
Hi Neha,
On 18:39-20230927, Neha Malcom Francis wrote:
> When setting boot media to load the TIFS binary in legacy boot flow
> (followed by J721E), get_timer() is called which eventually calls
> dm_timer_init() to grab the tick-timer, which is mcu_timer0. Since we
> need to set up the clocks before using the timer, move clk_k3 driver
> probe before k3_sysfw_loader to ensure we have all necessary clocks set
> up before.
>
> Signed-off-by: Neha Malcom Francis
> Reviewed-by: Nishanth Menon
> ---
> arch/arm/mach-k3/j721e_init.c | 24
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> index b6164575b7..b1f7e25ed0 100644
> --- a/arch/arm/mach-k3/j721e_init.c
> +++ b/arch/arm/mach-k3/j721e_init.c
> @@ -228,6 +228,18 @@ void board_init_f(ulong dummy)
> if (!ret)
> pinctrl_select_state(dev, "default");
>
> + /*
> + * Force probe of clk_k3 driver here to ensure basic default clock
> + * configuration is always done.
> + */
> + if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
> + ret = uclass_get_device_by_driver(UCLASS_CLK,
> + DM_DRIVER_GET(ti_clk),
> + );
> + if (ret)
> + panic("Failed to initialize clk-k3!\n");
> + }
> +
> /*
>* Load, start up, and configure system controller firmware. Provide
>* the U-Boot console init function to the SYSFW post-PM configuration
> @@ -241,18 +253,6 @@ void board_init_f(ulong dummy)
> do_dt_magic();
> #endif
>
> - /*
> - * Force probe of clk_k3 driver here to ensure basic default clock
> - * configuration is always done.
> - */
> - if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
> - ret = uclass_get_device_by_driver(UCLASS_CLK,
> - DM_DRIVER_GET(ti_clk),
> - );
> - if (ret)
> - panic("Failed to initialize clk-k3!\n");
> - }
> -
> /* Prepare console output */
> preloader_console_init();
>
Reviewed-by: Manorit Chawdhry
Regards,
Manorit
> diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
> --
> 2.34.1
>
[PATCH 3/3] arm64: versal_net: Disable the lock option for mini ospi and qspi
As mini configs are required only for flashing the images, so disabling the lock config which will save nearly 6KB of memory. Signed-off-by: Venkatesh Yadav Abbarapu --- configs/xilinx_versal_net_mini_ospi_defconfig | 3 ++- configs/xilinx_versal_net_mini_qspi_defconfig | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig index d11e180780..db3e7c80b2 100644 --- a/configs/xilinx_versal_net_mini_ospi_defconfig +++ b/configs/xilinx_versal_net_mini_ospi_defconfig @@ -12,7 +12,6 @@ CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_ENV_SIZE=0x80 # CONFIG_DM_GPIO is not set CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-ospi-single" -CONFIG_SYS_PROMPT="Versal NET> " CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0xBBF8 @@ -26,6 +25,7 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="Versal NET> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set @@ -56,6 +56,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +# CONFIG_SPI_FLASH_LOCK is not set CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig index a7ebc38cda..c0ff42aa91 100644 --- a/configs/xilinx_versal_net_mini_qspi_defconfig +++ b/configs/xilinx_versal_net_mini_qspi_defconfig @@ -10,7 +10,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF2 CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-qspi-single" -CONFIG_SYS_PROMPT="Versal NET> " CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0xBBF8 @@ -26,6 +25,7 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="Versal NET> " # CONFIG_SYS_XTRACE is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set @@ -60,6 +60,7 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_SMART_HWCAPS is not set +# CONFIG_SPI_FLASH_LOCK is not set # CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y -- 2.17.1
[PATCH 2/3] arm64: versal: Disable the lock option for mini ospi and qspi
As mini configs are required only for flashing the images, so disabling the lock config which will save nearly 6KB of memory. Signed-off-by: Venkatesh Yadav Abbarapu --- configs/xilinx_versal_mini_ospi_defconfig | 3 ++- configs/xilinx_versal_mini_qspi_defconfig | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index 27b59f899a..539ce2d3c0 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -12,7 +12,6 @@ CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_ENV_SIZE=0x80 # CONFIG_DM_GPIO is not set CONFIG_DEFAULT_DEVICE_TREE="versal-mini-ospi-single" -CONFIG_SYS_PROMPT="Versal> " CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_VERSAL_NO_DDR=y # CONFIG_PSCI_RESET is not set @@ -27,6 +26,7 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="Versal> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set @@ -57,6 +57,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +# CONFIG_SPI_FLASH_LOCK is not set CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index 4b0793411c..93365e7d30 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -10,7 +10,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-qspi-single" -CONFIG_SYS_PROMPT="Versal> " CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_VERSAL_NO_DDR=y # CONFIG_PSCI_RESET is not set @@ -27,6 +26,7 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="Versal> " # CONFIG_SYS_XTRACE is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set @@ -61,6 +61,7 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_SMART_HWCAPS is not set +# CONFIG_SPI_FLASH_LOCK is not set # CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y -- 2.17.1
[PATCH 1/3] mtd: spi-nor: Add spi flash lock config option
Provide an explicit configuration option to disable default "lock"
of any flash chip which supports locking.
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/Kconfig| 7 +++
drivers/mtd/spi/spi-nor-core.c | 8 +++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index a9617c6c58..476d848321 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -134,6 +134,13 @@ config SPI_FLASH_BAR
Bank/Extended address registers are used to access the flash
which has size > 16MiB in 3-byte addressing.
+config SPI_FLASH_LOCK
+ bool "Enable the Locking feature"
+ default y
+ help
+Enable the SPI flash lock support. By default this is set to y.
+If you intend not to use the lock support you should say n here.
+
config SPI_FLASH_UNLOCK_ALL
bool "Unlock the entire SPI flash on u-boot startup"
default y
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 6093277f17..9c51f2b1b0 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1099,6 +1099,7 @@ static int spansion_erase_non_uniform(struct spi_nor
*nor, u32 addr,
}
#endif
+#if defined(CONFIG_SPI_FLASH_LOCK)
#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
/* Write status register and ensure bits in mask match written values */
static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
@@ -1386,6 +1387,7 @@ static int stm_is_unlocked(struct spi_nor *nor, loff_t
ofs, uint64_t len)
return stm_is_unlocked_sr(nor, ofs, len, status);
}
#endif /* CONFIG_SPI_FLASH_STMICRO */
+#endif
static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
{
@@ -1461,6 +1463,7 @@ read_err:
return ret;
}
+#if defined(CONFIG_SPI_FLASH_LOCK)
#ifdef CONFIG_SPI_FLASH_SST
/*
* sst26 flash series has its own block protection implementation:
@@ -1729,6 +1732,8 @@ sst_write_err:
return ret;
}
#endif
+#endif
+
/*
* Write an address range to the nor chip. Data must be written in
* FLASH_PAGESIZE chunks. The address range may be any size provided
@@ -4103,6 +4108,7 @@ int spi_nor_scan(struct spi_nor *nor)
mtd->_read = spi_nor_read;
mtd->_write = spi_nor_write;
+#if defined(CONFIG_SPI_FLASH_LOCK)
#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
/* NOR protection support for STmicro/Micron chips and similar */
if (JEDEC_MFR(info) == SNOR_MFR_ST ||
@@ -4126,7 +4132,7 @@ int spi_nor_scan(struct spi_nor *nor)
nor->flash_is_unlocked = sst26_is_unlocked;
}
#endif
-
+#endif
if (info->flags & USE_FSR)
nor->flags |= SNOR_F_USE_FSR;
if (info->flags & SPI_NOR_HAS_TB)
--
2.17.1
[PATCH 0/3] Add spi flash lock option
Disabling the flash lock option for versal and versal-net mini ospi and qspi defconfigs. Venkatesh Yadav Abbarapu (3): mtd: spi-nor: Add spi flash lock config option arm64: versal: Disable the lock option for mini ospi and qspi arm64: versal_net: Disable the lock option for mini ospi and qspi configs/xilinx_versal_mini_ospi_defconfig | 3 ++- configs/xilinx_versal_mini_qspi_defconfig | 3 ++- configs/xilinx_versal_net_mini_ospi_defconfig | 3 ++- configs/xilinx_versal_net_mini_qspi_defconfig | 3 ++- drivers/mtd/spi/Kconfig | 7 +++ drivers/mtd/spi/spi-nor-core.c| 8 +++- 6 files changed, 22 insertions(+), 5 deletions(-) -- 2.17.1
Re: [PATCH v1 3/3] rockchip: cmd: add rockmtd command
Hi Johan,
On 2023/8/24 21:29, Johan Jonker wrote:
Rockmtd creates a virtual block device to transfer Rockchip
boot block data to and from NAND with block orientated tools
like "ums" and "rockusb".
It uses the Rockchip MTD driver to scan for boot blocks and copies
data from the first block in a GPT formated virtual disk.
Data must be written in U-boot "idbloader.img" format and start at
partition "loader1" offset 64. The data header is parsed
for length and offset. When the last sector is received
it erases up to 5 erase blocks on NAND and writes bootblocks
in a pattern depending on the NAND ID. Data is then verified.
When a block turns out bad the block header is discarded.
Signed-off-by: Johan Jonker
---
cmd/Kconfig |7 +
cmd/Makefile |1 +
cmd/rockmtd.c | 1429 +
3 files changed, 1437 insertions(+)
create mode 100644 cmd/rockmtd.c
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 2d6e5f993f04..87f862076355 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1553,6 +1553,13 @@ config CMD_USB_SDP
Enables the command "sdp" which is used to have U-Boot emulating the
Serial Download Protocol (SDP) via USB.
+config CMD_ROCKMTD
+ bool "rockmtd"
For most of modules for rockchip platform, it's naming with rockchip_ or
short with prefix rk**,
so I think it's better to use rkmtd for this command.
rockusb is the only one I know with prefix "rock", which is used with
very long history before
linux/u-boot driver available.
Thanks,
- Kever
+ help
+ Rockmtd creates a virtual block device to transfer Rockchip
+ boot block data to and from NAND with block orientated tools
+ like "ums" and "rockusb".
+
config CMD_ROCKUSB
bool "rockusb"
depends on USB_FUNCTION_ROCKUSB
diff --git a/cmd/Makefile b/cmd/Makefile
index 9f8c0b058bea..19b609ace782 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -150,6 +150,7 @@ obj-$(CONFIG_CMD_REISER) += reiser.o
obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o
obj-$(CONFIG_CMD_RNG) += rng.o
obj-$(CONFIG_CMD_KASLRSEED) += kaslrseed.o
+obj-$(CONFIG_CMD_ROCKMTD) += rockmtd.o
obj-$(CONFIG_CMD_ROCKUSB) += rockusb.o
obj-$(CONFIG_CMD_RTC) += rtc.o
obj-$(CONFIG_SANDBOX) += host.o
diff --git a/cmd/rockmtd.c b/cmd/rockmtd.c
new file mode 100644
index ..cf5259ecb4d7
--- /dev/null
+++ b/cmd/rockmtd.c
@@ -0,0 +1,1429 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) 2023 Johan Jonker
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define LBA64 + 512 + 33
+
+#define RK_TAG 0xFCDC8C3B
+#define NFC_SYS_DATA_SIZE 4
+
+struct nand_para_info {
+ u8 id_bytes;
+ u8 nand_id[6];
+ u8 vendor;
+ u8 die_per_chip;
+ u8 sec_per_page;
+ u16 page_per_blk;
+ u8 cell;
+ u8 plane_per_die;
+ u16 blk_per_plane;
+ u16 operation_opt;
+ u8 lsb_mode;
+ u8 read_retry_mode;
+ u8 ecc_bits;
+ u8 access_freq;
+ u8 opt_mode;
+ u8 die_gap;
+ u8 bad_block_mode;
+ u8 multi_plane_mode;
+ u8 slc_mode;
+ u8 reserved[5];
+};
+
+struct bootblk {
+ int blk;
+ int boot_size;
+ int offset;
+};
+
+struct rockmtd_dev {
+ struct blk_desc *desc;
+ char *label;
+ legacy_mbr *mbr;
+ gpt_header *gpt_h;
+ gpt_header *gpt_h2;
+ gpt_entry *gpt_e;
+ char *check;
+ char *idb;
+ char *str;
+ char uuid_part_str[UUID_STR_LEN + 1];
+ char uuid_disk_str[UUID_STR_LEN + 1];
+ char *datbuf;
+ char *oobbuf;
+ struct mtd_info *mtd;
+ struct nand_para_info *info;
+ u16 page_table[512];
+ u32 idb_need_write_back;
+ struct bootblk idblock[5];
+ u32 blk_counter;
+ u32 boot_blks;
+ u32 offset;
+ u32 boot_size;
+};
+
+struct sector0 {
+ u32 magic;
+ u8 reserved[4];
+ u32 rc4_flag;
+ u16 boot_code1_offset;
+ u16 boot_code2_offset;
+ u8 reserved1[490];
+ u16 flash_data_size;
+ u16 flash_boot_size;
+ u8 reserved2[2];
+} __packed;
+
+struct rk_nfc_nand_chip {
+ struct nand_chip chip;
+
+ u16 boot_blks;
+ u16 metadata_size;
+ u32 boot_ecc;
+ u32 timing;
+
+ u8 nsels;
+ u8 sels[0];
+ /* Nothing after this field. */
+};
+
+struct nand_para_info nand_para_tbl[] = {
+ {6, {0x2c, 0x64, 0x44, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 2048,
0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0x44, 0x44, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 1064,
0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0x68, 0x04, 0x4a, 0xa9, 0x00}, 4, 1, 8, 256, 2, 2, 2048,
0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0,
Re: [PATCH v1 2/3] dm: prepare rkmtd UCLASS
On 2023/8/24 21:29, Johan Jonker wrote:
Prepare a rkmtd UCLASS in use for writing Rockchip boot blocks
in combination with existing userspace tools and rockusb command.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Thanks,
- Kever
---
disk/part.c| 4
drivers/block/blk-uclass.c | 1 +
include/dm/uclass-id.h | 1 +
3 files changed, 6 insertions(+)
diff --git a/disk/part.c b/disk/part.c
index 186ee965006e..a65f9df5dd29 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -170,6 +170,7 @@ void dev_print(struct blk_desc *dev_desc)
case UCLASS_PVBLOCK:
case UCLASS_HOST:
case UCLASS_BLKMAP:
+ case UCLASS_RKMTD:
printf ("Vendor: %s Rev: %s Prod: %s\n",
dev_desc->vendor,
dev_desc->revision,
@@ -303,6 +304,9 @@ static void print_part_header(const char *type, struct
blk_desc *dev_desc)
case UCLASS_PVBLOCK:
puts("PV BLOCK");
break;
+ case UCLASS_RKMTD:
+ puts("RKMTD");
+ break;
case UCLASS_VIRTIO:
puts("VirtIO");
break;
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index 614b975e25c2..6bad2719e729 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -34,6 +34,7 @@ static struct {
{ UCLASS_VIRTIO, "virtio" },
{ UCLASS_PVBLOCK, "pvblock" },
{ UCLASS_BLKMAP, "blkmap" },
+ { UCLASS_RKMTD, "rkmtd" },
};
static enum uclass_id uclass_name_to_iftype(const char *uclass_idname)
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 307ad6931ca7..99a411429a2f 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -113,6 +113,7 @@ enum uclass_id {
UCLASS_REGULATOR, /* Regulator device */
UCLASS_REMOTEPROC, /* Remote Processor device */
UCLASS_RESET, /* Reset controller device */
+ UCLASS_RKMTD, /* Rockchip MTD device */
UCLASS_RNG, /* Random Number Generator */
UCLASS_RTC, /* Real time clock device */
UCLASS_SCMI_AGENT, /* Interface with an SCMI server */
--
2.30.2
Re: [PATCH v1 1/3] mtd: nand: raw: rockchip_nfc: add NAND_SKIP_BBTSCAN option
On 2023/8/24 21:28, Johan Jonker wrote: On Rockchip SoCs the first boot stages are written on NAND with help of manufacturer software that uses a different format then the MTD framework. Skip the automatic BBT scan with the NAND_SKIP_BBTSCAN option to be able to pass the driver probe function and to let the original data unchanged. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang Thanks, - Kever --- drivers/mtd/nand/raw/Kconfig| 9 + drivers/mtd/nand/raw/rockchip_nfc.c | 3 +++ 2 files changed, 12 insertions(+) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index d624589a892b..72547f00fbec 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -611,6 +611,15 @@ config ROCKCHIP_NAND NFC v800: RK3308, RV1108 NFC v900: PX30, RK3326 +config ROCKCHIP_NAND_SKIP_BBTSCAN + bool "Skip the automatic BBT scan with Rockchip NAND controllers" + depends on ROCKCHIP_NAND + default n + help + Skip the automatic BBT scan with the NAND_SKIP_BBTSCAN + option when data content is not in MTD format or + must remain unchanged. + config TEGRA_NAND bool "Support for NAND controller on Tegra SoCs" depends on ARCH_TEGRA diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c index 6ad51df4acff..df6742c2f9bb 100644 --- a/drivers/mtd/nand/raw/rockchip_nfc.c +++ b/drivers/mtd/nand/raw/rockchip_nfc.c @@ -981,6 +981,9 @@ static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc *nfc, int devnum) chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER; + if (IS_ENABLED(CONFIG_ROCKCHIP_NAND_SKIP_BBTSCAN)) + chip->options |= NAND_SKIP_BBTSCAN; + rk_nfc_hw_init(nfc); ret = nand_scan_ident(mtd, nsels, NULL); if (ret) -- 2.30.2
SSE instructions
Hi Bin, U-Boot 64-bit on x86 disables sse, but when enabling Truetype I get a compiler error: drivers/video/console_truetype.c: In function 'frac': drivers/video/console_truetype.c:30:15: error: SSE register return with SSE disabled 30 | static double frac(double val) Do you know how to enable SSE for 64-bit? Regards, Simon
Re: [PATCH v1] wdt: nuvoton: fix reset/expire function error and add dts
Hi Stefan
Thanks for your quick review.
i will followed your suggestions to update V2
Best regards,
Jim
On Tue, Sep 26, 2023 at 5:30 PM Stefan Roese wrote:
>
> Hi Jim,
>
> On 9/26/23 11:04, Jim Liu wrote:
> > Signed-off-by: Jim Liu
>
> Please provide a short commit summary, explaining what this patch
> does. Starting with a reasoning for this change and a short dscription
> of what was changed.
>
> More comments below...
>
> > ---
> > arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 24
> > drivers/watchdog/npcm_wdt.c | 12
> > 2 files changed, 32 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
> > b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
> > index fabe5925b7..87c77dcb2c 100644
> > --- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
> > +++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
> > @@ -154,6 +154,30 @@
> > clock-names = "refclk";
> > };
> >
> > + watchdog0: watchdog@801c {
> > + compatible = "nuvoton,npcm750-wdt";
> > + reg = <0x801c 0x4>;
> > + clocks = < NPCM8XX_CLK_REFCLK>;
> > + interrupts = ;
> > + status = "disabled";
> > + };
> > +
> > + watchdog1: watchdog@901c {
> > + compatible = "nuvoton,npcm750-wdt";
> > + reg = <0x901c 0x4>;
> > + clocks = < NPCM8XX_CLK_REFCLK>;
> > + interrupts = ;
> > + status = "disabled";
> > + };
> > +
> > + watchdog2: watchdog@a01c {
> > + compatible = "nuvoton,npcm750-wdt";
> > + reg = <0xa01c 0x4>;
> > + clocks = < NPCM8XX_CLK_REFCLK>;
> > + interrupts = ;
> > + status = "disabled";
> > + };
> > +
> > serial0: serial@0 {
> > compatible = "nuvoton,npcm845-uart",
> > "nuvoton,npcm750-uart";
> > reg = <0x0 0x1000>;
> > diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c
> > index e56aa0ebe1..d6792bab35 100644
> > --- a/drivers/watchdog/npcm_wdt.c
> > +++ b/drivers/watchdog/npcm_wdt.c
> > @@ -69,17 +69,21 @@ static int npcm_wdt_stop(struct udevice *dev)
> > static int npcm_wdt_reset(struct udevice *dev)
> > {
> > struct npcm_wdt_priv *priv = dev_get_priv(dev);
> > + u32 val;
> >
> > - writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs);
> > + val = readl(priv->regs);
> > + writel(val | NPCM_WTR, priv->regs);
> >
> > return 0;
> > }
> > -
> > static int npcm_wdt_expire_now(struct udevice *dev, ulong flags)
> > {
> > - return npcm_wdt_reset(dev);
> > -}
> > + struct npcm_wdt_priv *priv = dev_get_priv(dev);
> >
> > + writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs);
> > +
> > + return 0;
> > +}
> > static int npcm_wdt_of_to_plat(struct udevice *dev)
>
> Hmmm. This will result in npcm_wdt_of_to_plat() not having an empty line
> before its declaration. Please fix.
>
> Thanks,
> Stefan
Re: [PATCH v1 3/3] arm: npcm8xx: support dcache off
Hi Tom Thanks for the quick review. if we set the CONFIG_SYS_DCACHE_OFF the armv8 will build error. So we added a workaround for our bmc uboot. the error message as below: CONFIG_SYS_DCACHE_OFF can't be enabled on armv8, or the following build error would happen. arch/arm/cpu/armv8/cpu.o: in function `cleanup_before_linux': arch/arm/cpu/armv8/cpu.c:60: undefined reference to `icache_disable' arch/arm/cpu/armv8/cpu.c:68: undefined reference to `dcache_disable' arch/arm/cpu/armv8/cpu.c:69: undefined reference to `invalidate_dcache_all' Best regards, Jim On Tue, Sep 26, 2023 at 9:48 PM Tom Rini wrote: > > On Tue, Sep 26, 2023 at 04:56:50PM +0800, Jim Liu wrote: > > > do not enable dcache by setting CONFIG_SYS_NPCM_DCACHE_OFF=y > > > > Signed-off-by: Jim Liu > > --- > > arch/arm/mach-npcm/npcm8xx/Kconfig | 4 > > arch/arm/mach-npcm/npcm8xx/cpu.c | 12 +++- > > 2 files changed, 15 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm/mach-npcm/npcm8xx/Kconfig > > b/arch/arm/mach-npcm/npcm8xx/Kconfig > > index 5f4a0506dc..163e7e7d48 100644 > > --- a/arch/arm/mach-npcm/npcm8xx/Kconfig > > +++ b/arch/arm/mach-npcm/npcm8xx/Kconfig > > @@ -6,6 +6,10 @@ config SYS_CPU > > config SYS_SOC > > default "npcm8xx" > > > > +config SYS_NPCM_DCACHE_OFF > > + bool "Do not enable dcache" > > + default n > > + > > config TARGET_ARBEL_EVB > > bool "Arbel Evaluation Board" > > help > > Why do we need a new Kconfig option here on top of the existing generic > ones to control cache? > > -- > Tom
Re: [PATCH v2 4/5] sunxi: psci: implement PSCI on R528
On Wed, 27 Sep 2023 18:01:40 -0600
Sam Edwards wrote:
Hi Sam,
> On 9/27/23 10:31, Andre Przywara wrote:
> > On Wed, 16 Aug 2023 10:34:19 -0700
> > Sam Edwards wrote:
> >
> > Hi Sam,
>
> Hi Andre,
>
> >> @@ -103,10 +116,13 @@ static void __secure clamp_set(u32 *clamp)
> >>
> >> static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void
> >> *entry)
> >> {
> >> - /* secondary core entry address is programmed differently on R40 */
> >> + /* secondary core entry address is programmed differently on R40/528 */
> >>
> >
> > I think that's somewhat obvious now from the code, so you can remove this
> > comment.
>
> Done, change will be included in v3.
Thanks!
> >>if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {
> >>writel((u32)entry,
> >> SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
> >> + } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
> >> + writel((u32)entry,
> >> + SUNXI_R_CPUCFG_BASE + SUN8I_R528_SOFT_ENTRY);
> >>} else {
> >>writel((u32)entry, SUNXI_CPUCFG_BASE + SUNXI_PRIV0);
> >>}
> >> @@ -124,6 +140,9 @@ static void __secure sunxi_cpu_set_power(int cpu, bool
> >> on)
> >>} else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {
> >>clamp = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWR_CLAMP(cpu);
> >>pwroff = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWROFF;
> >> + } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
> >> + /* R528 leaves both cores powered up, manages them via reset */
> >> + return;
> >>} else {
> >>if (IS_ENABLED(CONFIG_MACH_SUN6I) ||
> >>IS_ENABLED(CONFIG_MACH_SUN8I_H3))
> >> @@ -151,11 +170,27 @@ static void __secure sunxi_cpu_set_power(int cpu,
> >> bool on)
> >>
> >> static void __secure sunxi_cpu_set_reset(int cpu, bool reset)
> >> {
> >> + if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
> >> + if (reset) {
> >
> > I think you can lose the brackets here, since it's a single statement
> > branch, even if it spans multiple lines. The indentation should make this
> > clear.
>
> FWIW a lot of reviewers insist on braces surrounding *any* multiline
> blocks, even if said block is only a single statement. This is to
> prevent mishaps where another developer comes along later to add another
> statement to the same block (at the same indentation level), but doesn't
> think to look for missing brackets because the block is already bigger
> than one line.
>
> I could go either way on it, but would like to be sure that your
> feedback stands in light of that counterpoint.
Yeah, I hear you, but my reflex is to look for that other statement if
I see curly braces. Seeing something without braces matches a pattern
of "just a single statement being different" for me.
And modern compilers actually warn about those indentation issues in
connection with if-statements or for-loops without braces.
But I leave this up to you, checkpatch doesn't seem to care here, so I
am fine either way.
>
> >> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> >> index 0a3454a51a..d46fd8c0bc 100644
> >> --- a/arch/arm/mach-sunxi/Kconfig
> >> +++ b/arch/arm/mach-sunxi/Kconfig
> >> @@ -355,6 +355,8 @@ config MACH_SUN8I_R40
> >> config MACH_SUN8I_R528
> >>bool "sun8i (Allwinner R528)"
> >>select CPU_V7A
> >> + select CPU_V7_HAS_NONSEC
> >> + select ARCH_SUPPORT_PSCI
> >
> > Please add
> > select CPU_V7_HAS_VIRT
> > here, as the cores are perfectly capable of virtualisation. Granted,
> > support for KVM is long gone from Linux, but at least Xen still supports
> > it.
>
> Good catch; will be done in v3.
>
> > And I believe you also need:
> > select SPL_ARMV7_SET_CORTEX_SMPEN
> > At least this is what the other cores do. The PSCI code sets this bit for
> > the secondaries, but for the primary core we need to set it as early as
> > possible. Probably not a biggie on an A7, in reality, but good to have,
> > and be it for correctness and consistency's sake.
>
> That's already enabled down below:
> # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
> config MACH_SUN8I
> bool
> select SPL_ARMV7_SET_CORTEX_SMPEN if !ARM64
Ah, that's the big confusion about that Allwinner naming change:
https://linux-sunxi.org/Allwinner_SoC_Family#2013_naming_scheme_change
So if you look closely, this MACH_SUN8I is more related to that old SoC
generation, not to "anything with an Cortex-A7 in it". And consequently
the R528 support series does NOT enable this symbol, but uses the new
NCAT2 family symbol.
I was checking the generated .config, and didn't find it in there,
hence it needs to be set separately.
> >> diff --git a/include/configs/sunxi-common.h
> >> b/include/configs/sunxi-common.h
> >> index b8ca77d031..67eb0d25db 100644
> >> --- a/include/configs/sunxi-common.h
> >> +++ b/include/configs/sunxi-common.h
> >> @@ -33,6 +33,14 @@
> >>
Re: [PATCH v2 5/5] HACK: sunxi: psci: be compatible with v1 of R528 patchset
On Wed, 27 Sep 2023 17:28:51 -0600 Sam Edwards wrote: > On 9/27/23 10:32, Andre Przywara wrote: > > On Wed, 16 Aug 2023 10:34:20 -0700 > > Sam Edwards wrote: > > > > Hi Sam, > > Hi Andre, > > > Mmh, I didn't find a better solution than keeping this in. > > I'll keep it if your R528 v2 doesn't find some other way to address it. > > >> +#endif > >> +#if defined(SUNXI_CPUX_BASE) && defined(SUNXI_CPUCFG_BASE) > >> +#undef SUNXI_CPUCFG_BASE > >> +#define SUNXI_CPUCFG_BASE SUNXI_CPUX_BASE > > > > So what's the story with this? Do we name this differently > > (SUNXI_CPUX_BASE) because the IP block is different from the other SoCs? > > Or is there another SUNXI_CPUCFG IP block on the R528/T113s SoCs? > > > > If not, I think we should use the SUNXI_CPUCFG_BASE name directly in > > cpu_sunxi_ncat2.h, as we never claimed that same names for some MMIO > > address blocks means they are compatible. > > > > Please let me know if I miss something. > > That's just for compatibility with R528 series v1. It's expected that > you'll rename it to SUNXI_CPUCFG_BASE for v2. The preprocessor trickery > looks for *both* being defined and applies the update. The rest of the > code proceeds using SUNXI_CPUCFG_BASE. (Keep in mind this is particular > patch is a hack patch, it's not considered for inclusion.) Yes, I got this, but surely the expectation is that those fixes should not be needed anymore after a v2 of the R528 support series, right? Which I am preparing as we speak, so I am supposed to fix them there, and just wanted to double check whether my solution is in line with what you had in mind. After all you seem to be deeper into this CPUCFG stuff than I am. Cheers, Andre
Re: [PATCH v2 4/5] sunxi: psci: implement PSCI on R528
On 9/27/23 10:31, Andre Przywara wrote:
On Wed, 16 Aug 2023 10:34:19 -0700
Sam Edwards wrote:
Hi Sam,
Hi Andre,
@@ -103,10 +116,13 @@ static void __secure clamp_set(u32 *clamp)
static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void *entry)
{
- /* secondary core entry address is programmed differently on R40 */
+ /* secondary core entry address is programmed differently on R40/528 */
I think that's somewhat obvious now from the code, so you can remove this
comment.
Done, change will be included in v3.
if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {
writel((u32)entry,
SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
+ } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
+ writel((u32)entry,
+ SUNXI_R_CPUCFG_BASE + SUN8I_R528_SOFT_ENTRY);
} else {
writel((u32)entry, SUNXI_CPUCFG_BASE + SUNXI_PRIV0);
}
@@ -124,6 +140,9 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)
} else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {
clamp = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWR_CLAMP(cpu);
pwroff = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWROFF;
+ } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
+ /* R528 leaves both cores powered up, manages them via reset */
+ return;
} else {
if (IS_ENABLED(CONFIG_MACH_SUN6I) ||
IS_ENABLED(CONFIG_MACH_SUN8I_H3))
@@ -151,11 +170,27 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)
static void __secure sunxi_cpu_set_reset(int cpu, bool reset)
{
+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
+ if (reset) {
I think you can lose the brackets here, since it's a single statement
branch, even if it spans multiple lines. The indentation should make this
clear.
FWIW a lot of reviewers insist on braces surrounding *any* multiline
blocks, even if said block is only a single statement. This is to
prevent mishaps where another developer comes along later to add another
statement to the same block (at the same indentation level), but doesn't
think to look for missing brackets because the block is already bigger
than one line.
I could go either way on it, but would like to be sure that your
feedback stands in light of that counterpoint.
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 0a3454a51a..d46fd8c0bc 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -355,6 +355,8 @@ config MACH_SUN8I_R40
config MACH_SUN8I_R528
bool "sun8i (Allwinner R528)"
select CPU_V7A
+ select CPU_V7_HAS_NONSEC
+ select ARCH_SUPPORT_PSCI
Please add
select CPU_V7_HAS_VIRT
here, as the cores are perfectly capable of virtualisation. Granted,
support for KVM is long gone from Linux, but at least Xen still supports it.
Good catch; will be done in v3.
And I believe you also need:
select SPL_ARMV7_SET_CORTEX_SMPEN
At least this is what the other cores do. The PSCI code sets this bit for
the secondaries, but for the primary core we need to set it as early as
possible. Probably not a biggie on an A7, in reality, but good to have,
and be it for correctness and consistency's sake.
That's already enabled down below:
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
select SPL_ARMV7_SET_CORTEX_SMPEN if !ARM64
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b8ca77d031..67eb0d25db 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -33,6 +33,14 @@
/* CPU */
+/*
+ * Newer ARM SoCs have moved the GIC, but have not updated their ARM cores to
+ * reflect the correct address in CBAR/PERIPHBASE.
+ */
+#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
+#define CFG_ARM_GIC_BASE_ADDRESS 0x0302
+#endif
I feel this should go into Kconfig. I can make a patch, unless you want to
beat me to it.
Note that you had previously [1] suggested placing this here, though
even then speculated that it belonged in Kconfig. I'm probably holding
off on sending a PSCI v3 until you send your R528 v2, so that might be a
good place to patch it. I'll remove this hunk if it's unnecessary by then.
[1]:
https://lore.kernel.org/u-boot/20230531161937.20d37...@donnerap.cambridge.arm.com/
Cheers,
Andre
Likewise,
Sam
Re: [PATCH v2 1/5] sunxi: psci: clean away preprocessor macros
On 9/27/23 10:34, Andre Przywara wrote:
In the majority of cases, there are no changes to the text section
introduced by this patch. In the R40 case, there's a small change where
the compiler adds a NULL check onto the result of the `(void *)cpucfg +
SUN8I_R40_PWR_CLAMP(cpu)` computation, which we can ignore as it won't
affect anything in practice. In the sun7i case, the only changes are
because I am NOT hardcoding the CPU to 0, which does look like I broke
it (since that means it will use cpu=1). So I'm going to need to fix
that in v3.
^^^
Do you have an update on this? I will try to test it on an R40 ASAP.
In my (not yet submitted) v3, I have the following change done:
if (IS_ENABLED(CONFIG_MACH_SUN7I)) {
clamp = >cpu1_pwr_clamp;
pwroff = >cpu1_pwroff;
+ cpu = 0;
} else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {
That does negate any binary change in the SUN7I case. R40 is the only
one that needs testing still. If you feel like testing on any SUN7Is
just for good measure, you'll want to add in that missing line.
Cheers,
Andre
Likewise,
Sam
Re: [PATCH v2 5/5] HACK: sunxi: psci: be compatible with v1 of R528 patchset
On 9/27/23 10:32, Andre Przywara wrote: On Wed, 16 Aug 2023 10:34:20 -0700 Sam Edwards wrote: Hi Sam, Hi Andre, Mmh, I didn't find a better solution than keeping this in. I'll keep it if your R528 v2 doesn't find some other way to address it. +#endif +#if defined(SUNXI_CPUX_BASE) && defined(SUNXI_CPUCFG_BASE) +#undef SUNXI_CPUCFG_BASE +#define SUNXI_CPUCFG_BASE SUNXI_CPUX_BASE So what's the story with this? Do we name this differently (SUNXI_CPUX_BASE) because the IP block is different from the other SoCs? Or is there another SUNXI_CPUCFG IP block on the R528/T113s SoCs? If not, I think we should use the SUNXI_CPUCFG_BASE name directly in cpu_sunxi_ncat2.h, as we never claimed that same names for some MMIO address blocks means they are compatible. Please let me know if I miss something. That's just for compatibility with R528 series v1. It's expected that you'll rename it to SUNXI_CPUCFG_BASE for v2. The preprocessor trickery looks for *both* being defined and applies the update. The rest of the code proceeds using SUNXI_CPUCFG_BASE. (Keep in mind this is particular patch is a hack patch, it's not considered for inclusion.) Warm regards, Sam
Re: [PATCH] riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode
On 9/27/23 02:25, Yu Chien Peter Lin wrote: > The Andes PLMT driver directly accesses the mtime MMIO region, > indicating its intended use in the M-mode boot stage. However, > since U-Boot proper (S-mode) also uses the PLMT driver, we need > to specifically mark the region as readable through PMPCFGx (or > S/U-mode read-only shared data region for Smepmp) in OpenSBI. > > Granting permission for this case doesn't make sense. Instead, > we should use the generic RISC-V timer driver to read the mtime > through the TIME CSR. Therefore, we add SPL_ANDES_PLMT_TIMER > config, the PLMT driver will be compiled only against M-mode > U-Boot or U-Boot SPL. > > Signed-off-by: Yu Chien Peter Lin > --- > arch/riscv/cpu/andesv5/Kconfig | 3 ++- > drivers/timer/Kconfig | 9 - > drivers/timer/Makefile | 2 +- > 3 files changed, 11 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig > index 82bb5a2a53..eba576af2f 100644 > --- a/arch/riscv/cpu/andesv5/Kconfig > +++ b/arch/riscv/cpu/andesv5/Kconfig > @@ -4,8 +4,9 @@ config RISCV_NDS > imply CPU > imply CPU_RISCV > imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) > + imply ANDES_PLMT_TIMER if RISCV_MMODE > + imply SPL_ANDES_PLMT_TIMER if SPL_RISCV_MMODE You don't need the "if RISCV_MMODE" condition since the imply statement will be ignored if the dependency is not met. Either way: Reviewed-by: Samuel Holland > imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) > - imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE) > imply V5L2_CACHE > imply SPL_CPU > imply SPL_OPENSBI > diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig > index 915b2af160..157298a941 100644 > --- a/drivers/timer/Kconfig > +++ b/drivers/timer/Kconfig > @@ -59,7 +59,14 @@ config ALTERA_TIMER > > config ANDES_PLMT_TIMER > bool > - depends on RISCV_MMODE || SPL_RISCV_MMODE > + depends on RISCV_MMODE > + help > + The Andes PLMT block holds memory-mapped mtime register > + associated with timer tick. > + > +config SPL_ANDES_PLMT_TIMER > + bool > + depends on SPL_RISCV_MMODE > help > The Andes PLMT block holds memory-mapped mtime register > associated with timer tick. > diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile > index 1ca74805fd..1f5c16fdf3 100644 > --- a/drivers/timer/Makefile > +++ b/drivers/timer/Makefile > @@ -4,7 +4,7 @@ > > obj-y += timer-uclass.o > obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o > -obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o > +obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o > obj-$(CONFIG_ARC_TIMER) += arc_timer.o > obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o > obj-$(CONFIG_AST_TIMER) += ast_timer.o
Re: [PATCH 2/2] board: Add support for Conclusive KSTR-SAMA5D27
On 9/25/23 22:31, Artur Rojek wrote:
Hey Eugen,
thanks for the review.
Hello,
Thank you for your patch,
On 9/21/23 18:37, Artur Rojek wrote:
Introduce support for Conclusive KSTR-SAMA5D27 Single Board Computer.
Co-developed-by: Jakub Klama
Signed-off-by: Jakub Klama
Co-developed-by: Marcin Jabrzyk
Signed-off-by: Marcin Jabrzyk
Signed-off-by: Artur Rojek
---
arch/arm/dts/Makefile | 3 +
arch/arm/dts/at91-kstr-sama5d27.dts | 310 ++
arch/arm/mach-at91/Kconfig| 13 +
board/conclusive/kstr-sama5d27/Kconfig| 15 +
board/conclusive/kstr-sama5d27/MAINTAINERS| 8 +
board/conclusive/kstr-sama5d27/Makefile | 5 +
.../conclusive/kstr-sama5d27/kstr-sama5d27.c | 235 +
configs/kstr_sama5d27_defconfig | 79 +
include/configs/kstr-sama5d27.h | 15 +
9 files changed, 683 insertions(+)
create mode 100644 arch/arm/dts/at91-kstr-sama5d27.dts
create mode 100644 board/conclusive/kstr-sama5d27/Kconfig
create mode 100644 board/conclusive/kstr-sama5d27/MAINTAINERS
create mode 100644 board/conclusive/kstr-sama5d27/Makefile
create mode 100644 board/conclusive/kstr-sama5d27/kstr-sama5d27.c
create mode 100644 configs/kstr_sama5d27_defconfig
create mode 100644 include/configs/kstr-sama5d27.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 85fd5b1157b1..8e4d33c01912 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1198,6 +1198,9 @@ dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \
dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \
at91-sama5d27_wlsom1_ek.dtb
+dtb-$(CONFIG_TARGET_KSTR_SAMA5D27) += \
+ at91-kstr-sama5d27.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D2_ICP) += \
at91-sama5d2_icp.dtb
diff --git a/arch/arm/dts/at91-kstr-sama5d27.dts b/arch/arm/dts/at91-kstr-sama5d27.dts
new file mode 100644
index ..6de918a3c964
--- /dev/null
+++ b/arch/arm/dts/at91-kstr-sama5d27.dts
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * at91-kstr-sama5d27.dts - Device Tree file for Conclusive KSTR-SAMA5D27 board
+ *
+ * Copyright (C) 2019-2023 Conclusive Engineering Sp. z o. o.
SPDX tag is enough, no need to replicate the license text below
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+#include
+#include
+
+/ {
+ model = "Conclusive KSTR-SAMA5D27";
+ compatible = "conclusive,kstr-sama5d27", "atmel,sama5d2", "atmel,sama5";
+
+ chosen {
+ bootph-all;
+ stdout-path =
+ };
+
+ clocks {
+ main_xtal: main_xtal {
+ clock-frequency = <1200>;
+ };
+ };
+
+ ahb {
+ usb0: gadget@0030 {
I feel this line is not properly aligned
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible =
[PATCH 3/3] dt-bindings: mtd: binman-partitions: Add alignment properties
Add three properties for controlling alignment of partitions, aka
'entries' in binman.
For now there is no explicit mention of hierarchy, so a 'section' is
just the 'fixed-partitions' node.
These new properties are inputs to the packaging process, but are also
needed if the firmware is repacked, to ensure that alignment
constraints are not violated. Therefore they a provided as part of the
schema.
Signed-off-by: Simon Glass
---
.../mtd/partitions/binman-partition.yaml | 39 +++
1 file changed, 39 insertions(+)
diff --git
a/Documentation/devicetree/bindings/mtd/partitions/binman-partition.yaml
b/Documentation/devicetree/bindings/mtd/partitions/binman-partition.yaml
index 6ee832cb4c4c..9cd424447e76 100644
--- a/Documentation/devicetree/bindings/mtd/partitions/binman-partition.yaml
+++ b/Documentation/devicetree/bindings/mtd/partitions/binman-partition.yaml
@@ -27,6 +27,42 @@ properties:
- u-boot # u-boot.bin from U-Boot projec6t
- atf-bl31 # bl31.bin or bl31.elf from TF-A project
+ align:
+$ref: /schemas/types.yaml#/definitions/uint32
+description:
+ This sets the alignment of the entry. The entry offset is adjusted
+ so that the entry starts on an aligned boundary within the containing
+ section or image. For example ‘align = <16>’ means that the entry will
+ start on a 16-byte boundary. This may mean that padding is added before
+ the entry. The padding is part of the containing section but is not
+ included in the entry, meaning that an empty space may be created before
+ the entry starts. Alignment should be a power of 2. If ‘align’ is not
+ provided, no alignment is performed.
+
+ align-size:
+$ref: /schemas/types.yaml#/definitions/uint32
+description:
+ This sets the alignment of the entry size. For example, to ensure
+ that the size of an entry is a multiple of 64 bytes, set this to 64.
+ While this does not affect the contents of the entry within binman
+ itself (the padding is performed only when its parent section is
+ assembled), the end result is that the entry ends with the padding
+ bytes, so may grow. If ‘align-size’ is not provided, no alignment is
+ performed.
+
+ align-end:
+$ref: /schemas/types.yaml#/definitions/uint32
+description:
+ This sets the alignment of the end of an entry with respect to the
+ containing section. Some entries require that they end on an alignment
+ boundary, regardless of where they start. This does not move the start
+ of the entry, so the contents of the entry will still start at the
+ beginning. But there may be padding at the end. While this does not
+ affect the contents of the entry within binman itself (the padding is
+ performed only when its parent section is assembled), the end result is
+ that the entry ends with the padding bytes, so may grow. If ‘align-end’
+ is not provided, no alignment is performed.
+
additionalProperties: false
examples:
@@ -39,10 +75,13 @@ examples:
partition-u-boot@10 {
label = "u-boot";
reg = <0x10 0xf0>;
+align-size = <0x1000>;
+align-end = <0x1>;
};
partition-atf-bl31t@20 {
label = "atf-bl31";
reg = <0x20 0x10>;
+align = <0x4000>;
};
};
--
2.42.0.515.g380fc7ccd1-goog
[PATCH 2/3] dt-bindings: mtd: binman-partition: Add binman labels
Add two labels for binman entries, as a starting point for the schema.
Signed-off-by: Simon Glass
---
.../mtd/partitions/binman-partition.yaml | 48 +++
1 file changed, 48 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/partitions/binman-partition.yaml
diff --git
a/Documentation/devicetree/bindings/mtd/partitions/binman-partition.yaml
b/Documentation/devicetree/bindings/mtd/partitions/binman-partition.yaml
new file mode 100644
index ..6ee832cb4c4c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/partitions/binman-partition.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2023 Google LLC
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/partitions/binman-partition.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Binman partition
+
+maintainers:
+ - Simon Glass
+
+select: false
+
+description: |
+ This corresponds to a binman 'entry'. It is a single partition which holds
+ data of a defined type.
+
+allOf:
+ - $ref: /schemas/mtd/partitions/partition.yaml#
+
+properties:
+ label:
+items:
+ enum:
+- u-boot # u-boot.bin from U-Boot projec6t
+- atf-bl31 # bl31.bin or bl31.elf from TF-A project
+
+additionalProperties: false
+
+examples:
+ - |
+partitions {
+compatible = "binman", "fixed-partitions";
+#address-cells = <1>;
+#size-cells = <1>;
+
+partition-u-boot@10 {
+label = "u-boot";
+reg = <0x10 0xf0>;
+};
+
+partition-atf-bl31t@20 {
+label = "atf-bl31";
+reg = <0x20 0x10>;
+};
+};
--
2.42.0.515.g380fc7ccd1-goog
[PATCH 1/3] dt-bindings: mtd: fixed-partitions: Add binman compatible
Add a compatible string for binman, so we can extend fixed-partitions
in various ways.
Signed-off-by: Simon Glass
---
.../bindings/mtd/partitions/binman.yaml | 49 +++
.../mtd/partitions/fixed-partitions.yaml | 6 +++
.../bindings/mtd/partitions/partitions.yaml | 1 +
MAINTAINERS | 5 ++
4 files changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/partitions/binman.yaml
diff --git a/Documentation/devicetree/bindings/mtd/partitions/binman.yaml
b/Documentation/devicetree/bindings/mtd/partitions/binman.yaml
new file mode 100644
index ..34fd10c1a318
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/partitions/binman.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2023 Google LLC
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/partitions/binman.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Binman firmware layout
+
+maintainers:
+ - Simon Glass
+
+select: false
+
+description: |
+ The binman node provides a layout for firmware, used when packaging firmware
+ from multiple projects. It is based on fixed-partitions, with some
+ extensions.
+
+ Documentation for Binman is available at:
+
+ https://u-boot.readthedocs.io/en/latest/develop/package/binman.html
+
+ with the current image-description format at:
+
+
https://u-boot.readthedocs.io/en/latest/develop/package/binman.html#image-description-format
+
+allOf:
+ - $ref: /schemas/mtd/partitions/fixed-partitions.yaml#
+
+properties:
+ compatible:
+const: binman
+
+additionalProperties: false
+
+examples:
+ - |
+partitions {
+compatible = "binman", "fixed-partitions";
+#address-cells = <1>;
+#size-cells = <1>;
+
+partition-u-boot@10 {
+label = "u-boot";
+reg = <0x10 0xf0>;
+};
+};
diff --git
a/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml
b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml
index 331e564f29dc..1c04bc2b95af 100644
--- a/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml
+++ b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml
@@ -14,6 +14,9 @@ description: |
The partition table should be a node named "partitions". Partitions are then
defined as subnodes.
+ The Binman tool provides some enhanced features, so provides a compatible
+ string to indicate that these are permitted.
+
maintainers:
- Rafał Miłecki
@@ -24,6 +27,9 @@ properties:
- items:
- const: sercomm,sc-partitions
- const: fixed-partitions
+ - items:
+ - const: binman
+ - const: fixed-partitions
"#address-cells": true
diff --git a/Documentation/devicetree/bindings/mtd/partitions/partitions.yaml
b/Documentation/devicetree/bindings/mtd/partitions/partitions.yaml
index 1dda2c80747b..849fd15d085c 100644
--- a/Documentation/devicetree/bindings/mtd/partitions/partitions.yaml
+++ b/Documentation/devicetree/bindings/mtd/partitions/partitions.yaml
@@ -15,6 +15,7 @@ maintainers:
oneOf:
- $ref: arm,arm-firmware-suite.yaml
+ - $ref: binman.yaml
- $ref: brcm,bcm4908-partitions.yaml
- $ref: brcm,bcm947xx-cfe-partitions.yaml
- $ref: fixed-partitions.yaml
diff --git a/MAINTAINERS b/MAINTAINERS
index 5f18c6ba3c3c..367c843ec348 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3517,6 +3517,11 @@ F: Documentation/filesystems/bfs.rst
F: fs/bfs/
F: include/uapi/linux/bfs_fs.h
+BINMAN
+M: Simon Glass
+S: Supported
+F: Documentation/devicetree/bindings/mtd/partitions/binman*
+
BITMAP API
M: Yury Norov
R: Andy Shevchenko
--
2.42.0.515.g380fc7ccd1-goog
Re: [PATCH 1/4] mkimage: also honour -B even without external data
On 9/19/23 07:37, Rasmus Villemoes wrote:
In some cases, using the "external data" feature is impossible or
undesirable, but one may still want (or need) the FIT image to have a
certain alignment. Also, given the current 'mkimage -h' output,
-B => align size in hex for FIT structure and header
it is quite unexpected for -B to be effectively ignored without -E.
FWIW, this behavior is documented in doc/mkimage.1 (which should also be
updated if this behavior is implemented):
| The alignment, in hexadecimal, that external data will be aligned to.
| This option only has an effect when -E is specified.
And, for additional context, the documentation for -E is
| After processing, move the image data outside the FIT and store a data
| offset in the FIT. Images will be placed one after the other
| immediately after the FIT, with each one aligned to a 4-byte boundary.
| The existing ‘data’ property in each image will be replaced with
| ‘data-offset’ and ‘data-size’ properties. A ‘data-offset’ of 0
| indicates that it starts in the first (4-byte-aligned) byte after the
| FIT.
Based on this documentation and my understanding of the code as-is, -B
controls the alignment of the images themselves, not the size multiple
of the FIT. However, from what I can tell, this patch does not actually
affect the alignment of the images, but rather adjusts the size of the
overall FIT to a certain alignment. I find this rather unexpected.
--Sean
Signed-off-by: Rasmus Villemoes
---
tools/fit_image.c | 40
1 file changed, 40 insertions(+)
diff --git a/tools/fit_image.c b/tools/fit_image.c
index 9fe69ea0d9..2f5b25098a 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -712,6 +712,42 @@ err:
return ret;
}
+/**
+ * fit_align() - Ensure FIT image has certain alignment
+ *
+ * This takes a normal FIT file (with embedded data) and increases its
+ * size so that it is a multiple of params->bl_len.
+ */
+static int fit_align(struct image_tool_params *params, const char *fname)
+{
+ int fit_size, new_size;
+ int fd;
+ struct stat sbuf;
+ void *fdt;
+ int ret = 0;
+ int align_size;
+
+ align_size = params->bl_len;
+ fd = mmap_fdt(params->cmdname, fname, 0, , , false, false);
+ if (fd < 0)
+ return -EIO;
+
+ fit_size = fdt_totalsize(fdt);
+ new_size = ALIGN(fit_size, align_size);
+ fdt_set_totalsize(fdt, new_size);
+ debug("Size extended from from %x to %x\n", fit_size, new_size);
+ munmap(fdt, sbuf.st_size);
+
+ if (ftruncate(fd, new_size)) {
+ debug("%s: Failed to truncate file: %s\n", __func__,
+ strerror(errno));
+ ret = -EIO;
+ }
+
+ close(fd);
+ return ret;
+}
+
/**
* fit_handle_file - main FIT file processing function
*
@@ -817,6 +853,10 @@ static int fit_handle_file(struct image_tool_params
*params)
ret = fit_extract_data(params, tmpfile);
if (ret)
goto err_system;
+ } else if (params->bl_len) {
+ ret = fit_align(params, tmpfile);
+ if (ret)
+ goto err_system;
}
if (rename (tmpfile, params->imagefile) == -1) {
Re: [PATCH v4 1/1] CI: add test/usage_of_is_enabled_check.sh
On Wed, Sep 27, 2023 at 11:14 AM Troy Kisky wrote: > > > On Mon, Jun 19, 2023 at 4:07 PM Troy Kisky > wrote: > >> Add script usage_of_is_enabled_check to print any configs that >> use CONFIG_IS_ENABLED instead of IS_ENABLED and vice versa. >> >> Add usage_of_is_enabled_commit.sh to generate commits to fix the above >> issues. >> >> You can remove entries from test/usage_of_is_enabled_todo.txt >> or the entire file and then run >> test/usage_of_is_enabled_commit.sh >> to convert to suggested usage of CONFIG_IS_ENABLED/IS_ENABLED >> >> or run test/usage_of_is_enabled_check.sh to >> see which configs are still todo. >> >> Reviewed-by: Simon Glass >> Signed-off-by: Troy Kisky >> --- >> >> (no changes since v1) >> >> .azure-pipelines.yml| 11 ++ >> .gitlab-ci.yml | 5 + >> test/usage_of_is_enabled_check.sh | 19 +++ >> test/usage_of_is_enabled_commit.sh | 12 ++ >> test/usage_of_is_enabled_correct.sh | 50 +++ >> test/usage_of_is_enabled_exempt.txt | 9 ++ >> test/usage_of_is_enabled_list.sh| 86 +++ >> test/usage_of_is_enabled_splcfg.txt | 21 +++ >> test/usage_of_is_enabled_todo.txt | 213 >> 9 files changed, 426 insertions(+) >> create mode 100755 test/usage_of_is_enabled_check.sh >> create mode 100755 test/usage_of_is_enabled_commit.sh >> create mode 100755 test/usage_of_is_enabled_correct.sh >> create mode 100644 test/usage_of_is_enabled_exempt.txt >> create mode 100755 test/usage_of_is_enabled_list.sh >> create mode 100644 test/usage_of_is_enabled_splcfg.txt >> create mode 100644 test/usage_of_is_enabled_todo.txt >> >> > If this patch is still desirable, it can be updated by > > rm test/usage_of_is_enabled_todo.txt > test/usage_of_is_enabled_check.sh >test/usage_of_is_enabled_todo.txt > > And delete the last 2 lines sed -i '$d' test/usage_of_is_enabled_todo.txt sed -i '$d' test/usage_of_is_enabled_todo.txt > BR > Troy > >
Re: [PATCH v4 1/1] CI: add test/usage_of_is_enabled_check.sh
On Mon, Jun 19, 2023 at 4:07 PM Troy Kisky wrote: > Add script usage_of_is_enabled_check to print any configs that > use CONFIG_IS_ENABLED instead of IS_ENABLED and vice versa. > > Add usage_of_is_enabled_commit.sh to generate commits to fix the above > issues. > > You can remove entries from test/usage_of_is_enabled_todo.txt > or the entire file and then run > test/usage_of_is_enabled_commit.sh > to convert to suggested usage of CONFIG_IS_ENABLED/IS_ENABLED > > or run test/usage_of_is_enabled_check.sh to > see which configs are still todo. > > Reviewed-by: Simon Glass > Signed-off-by: Troy Kisky > --- > > (no changes since v1) > > .azure-pipelines.yml| 11 ++ > .gitlab-ci.yml | 5 + > test/usage_of_is_enabled_check.sh | 19 +++ > test/usage_of_is_enabled_commit.sh | 12 ++ > test/usage_of_is_enabled_correct.sh | 50 +++ > test/usage_of_is_enabled_exempt.txt | 9 ++ > test/usage_of_is_enabled_list.sh| 86 +++ > test/usage_of_is_enabled_splcfg.txt | 21 +++ > test/usage_of_is_enabled_todo.txt | 213 > 9 files changed, 426 insertions(+) > create mode 100755 test/usage_of_is_enabled_check.sh > create mode 100755 test/usage_of_is_enabled_commit.sh > create mode 100755 test/usage_of_is_enabled_correct.sh > create mode 100644 test/usage_of_is_enabled_exempt.txt > create mode 100755 test/usage_of_is_enabled_list.sh > create mode 100644 test/usage_of_is_enabled_splcfg.txt > create mode 100644 test/usage_of_is_enabled_todo.txt > > If this patch is still desirable, it can be updated by rm test/usage_of_is_enabled_todo.txt test/usage_of_is_enabled_check.sh >test/usage_of_is_enabled_todo.txt BR Troy
[PATCH v4] dt-bindings: mtd: fixed-partitions: Add compression property
Sometimes the contents of a partition are compressed. Add a property to
express this and define the algorithm used.
Signed-off-by: Simon Glass
---
Changes in v4:
- Add an example
Changes in v3:
- Just add a compression property for now
Changes in v2:
- Use "binman" for compatible instead of "u-boot,binman"
- Significantly rework the patch
- Use make dt_binding_check DT_SCHEMA_FILES=Documentation/../partitions
.../mtd/partitions/fixed-partitions.yaml | 19 +++
1 file changed, 19 insertions(+)
diff --git
a/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml
b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml
index 331e564f29dc..058253d6d889 100644
--- a/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml
+++ b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml
@@ -29,6 +29,24 @@ properties:
"#size-cells": true
+ compression:
+$ref: /schemas/types.yaml#/definitions/string
+description: |
+ Compression algorithm used to store the data in this partition, chosen
+ from a list of well-known algorithms.
+
+ The contents are compressed using this algorithm.
+
+enum:
+ - none
+ - bzip2
+ - gzip
+ - lzop
+ - lz4
+ - lzma
+ - xz
+ - zstd
+
patternProperties:
"@[0-9a-f]+$":
$ref: partition.yaml#
@@ -64,6 +82,7 @@ examples:
uimage@10 {
reg = <0x010 0x20>;
+compress = "lzma";
};
};
--
2.42.0.515.g380fc7ccd1-goog
[PATCH] configs: iot2050: Disable CONFIG_CONSOLE_MUX
From: Jan Kiszka We only have serial as console option, and leaving this on turns on SYS_CONSOLE_IS_IN_ENV which is also not true for these devices, leaving an ugly In:No input devices available! Out: No output devices available! Err: No error devices available! behind. Signed-off-by: Jan Kiszka --- Fix for 2023.10. configs/iot2050_defconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig index bc9ca16fac3..3f05f8c38d7 100644 --- a/configs/iot2050_defconfig +++ b/configs/iot2050_defconfig @@ -18,7 +18,6 @@ CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic" CONFIG_SPL_TEXT_BASE=0x8008 -CONFIG_SYS_PROMPT="IOT2050> " CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_SERIAL=y @@ -41,7 +40,6 @@ CONFIG_AUTOBOOT_FLUSH_STDIN=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE to stop autoboot in %d seconds...\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOOTCOMMAND="run start_watchdog; run distro_bootcmd" -CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -62,6 +60,7 @@ CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x38 +CONFIG_SYS_PROMPT="IOT2050> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_ASKENV=y -- 2.35.3
[PATCH v3] dt-bindings: mtd: fixed-partitions: Add compression property
Sometimes the contents of a partition are compressed. Add a property to express this and define the algorithm used. Signed-off-by: Simon Glass --- Changes in v3: - Just add a compression property for now Changes in v2: - Use "binman" for compatible instead of "u-boot,binman" - Significantly rework the patch - Use make dt_binding_check DT_SCHEMA_FILES=Documentation/../partitions .../mtd/partitions/fixed-partitions.yaml | 18 ++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml index 331e564f29dc..13ff313cabda 100644 --- a/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml +++ b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml @@ -29,6 +29,24 @@ properties: "#size-cells": true + compression: +$ref: /schemas/types.yaml#/definitions/string +description: | + Compression algorithm used to store the data in this partition, chosen + from a list of well-known algorithms. + + The contents are compressed using this algorithm. + +enum: + - none + - bzip2 + - gzip + - lzop + - lz4 + - lzma + - xz + - zstd + patternProperties: "@[0-9a-f]+$": $ref: partition.yaml# -- 2.42.0.515.g380fc7ccd1-goog
Re: [PATCH] dt-bindings: mtd: Add a schema for binman
Hi Rob, On Tue, 26 Sept 2023 at 11:29, Rob Herring wrote: > > On Tue, Sep 26, 2023 at 2:48 AM Miquel Raynal > wrote: > > > > Hello, > > > > > > > > > These are firmware bindings, as indicated, but I > > > > > > > took them out of the /firmware node since that is for a different > > > > > > > purpose. Rob suggested that partitions was a good place. We have > > > > > > > fwupd > > > > > > > using DT to hold the firmware-update information, so I expect it > > > > > > > will > > > > > > > move to use these bindings too. > > > > > > > > > > > > I would definitely use fixed partitions as that's what you need > > > > > > then: > > > > > > registering where everything starts and ends. If you have "in-band" > > > > > > meta data you might require a compatible, but I don't think you > > > > > > do, in this case you should probably carry the content through a > > > > > > label > > > > > > (which will become the partition name) and we can discuss additional > > > > > > properties if needed. > > > > > > > > > > I believe I am going to need a compatible string at the 'partitions' > > > > > level to indicate that this is the binman scheme. But we can leave > > > > > that until later. > > > > > > > > Perhaps: > > > > > > > > compatible = "binman", "fixed-partitions"; > > > > > > > > Though I don't understand why binman couldn't just understand what > > > > "fixed-partitions" means rather than "binman". > > > > > > Well so long as we don't add any binman things in here, you are right. > > > > > > But the eventual goal is parity with current Binman functionality, > > > which writes the entire (augmented) description to the DT, allowing > > > tools to rebuild / repack / replace pieces later, maintaining the same > > > alignment constraints, etc. I am assuming that properties like 'align > > > = <16>' would not fit with fixed-partitions. > > > > I am personally not bothered by this kind of properties. But if we plan > > on adding too much properties, I will advise to indeed use another name > > than fixed-partitions (or add the "binman" secondary compatible) > > otherwise it's gonna be hard to support in the code while still > > restraining as much as we can the other partition schema. > > Agreed. It's a trade off. I think we need enough to understand the > problem (not just presented with a solution), agree on the general > solution/direction, and then discuss specific additions. > > > > But if we don't preserve > > > these properties then Binman cannot do repacking reliably. Perhaps for > > > now I could put the augmented DT in its own section somewhere, but I > > > am just not sure if that will work in a real system. E.g. with VBE the > > > goal is to use the DT to figure out how to access the firmware, update > > > it, etc. > > VBE? > > > > Is it not possible to have my own node with whatever things Binman > > > needs in it (subject to review of course)? i.e. could we discuss how > > > to encode it, but argue less about whether things are needed? I > > > kind-of feel I know what is needed, since I wrote the tool. > > What we don't need is the same information in 2 places for the DTB > used at runtime. If the binman node is removed, do whatever you want. > If you want to keep it at runtime, then it's got to extend what we > already have. > > I don't think anyone is disagreeing about whether specific information > is needed or not. > > > > > > So you are suggesting 'label' for the contents. Rob suggested > > > > > 'compatible' [1], so what should I do? > > > > > > > > "label" is for consumption by humans, not tools/software. Compatible > > > > values are documented, label values are not. Though the partition > > > > stuff started out using label long ago and it's evolved to preferring > > > > compatible. > > > > > > OK so we are agreed that we are going with 'compatible'. > > > > Still strongly disagree here. > > Miquel is right. I was confused here. "label" is still pretty much > used for what the image is. Though we do have "u-boot,env" for both it > seems. > > My position on "label" stands. To the extent we have images for common > components, I think we should standardize the names. Certainly if > tools rely on the names, then they should be documented. OK thanks for clearing that up. But at present 'label' is free-form text. If I change it to an enum, won't that break things? If not, how do I actually do it? There is a u-boot.yaml but it doesn't actually have a "u-boot" label in the schema. In fact it seems that the label is not validated at all? > > > > My understanding is that a compatible carries how the content is > > organized, and how this maybe specific (like you have in-band meta data > > data that needs to be parsed in a specific way or in your case > > additional specific properties in the DT which give more context about > > how the data is stored). But the real content of the partition, ie. if > > it contains a firmware, the kernel or some user data does not belong to > > the compatible. > > >
Re: [PATCH v2 1/5] sunxi: psci: clean away preprocessor macros
On Fri, 18 Aug 2023 14:17:07 -0700 Sam Edwards wrote: > On 8/18/23 10:40, Sam Edwards wrote: > > On 8/18/23 07:11, Andre Przywara wrote: > > > > Hi Andre, > > > >> The resulting object file is different (8 byte larger, > >> even), so it's hard to prove > > > > I'm no stranger to reading object code. Since the output should be > > identical in principle, I'll spend a little bit of time today seeing if > > I can identify what's changing. If it's easy enough, I'd like to adjust > > my patch so that the optimizer does produce the same output. (Keep in > > mind I'm on Clang, though. If Clang already gives the same output for > > both, I'll just report back to use that when comparing.) > > I built only psci.o from every ARM32 sunxi for which we have a defconfig > (and for which PSCI is supported), for 81 targets total (though there > are only 4 variations: R40, sun7i, H3/sun6i, and "everything else"). I > am working with Clang version 16.0.6. > > I compared only the secure text section. The command to extract this > looks like: > llvm-objcopy -O binary --only-section=._secure.text psci.o text.bin > This is important because there are debug sections that will change when > the source file line numbers change, so we must ignore those when comparing. > > In the majority of cases, there are no changes to the text section > introduced by this patch. In the R40 case, there's a small change where > the compiler adds a NULL check onto the result of the `(void *)cpucfg + > SUN8I_R40_PWR_CLAMP(cpu)` computation, which we can ignore as it won't > affect anything in practice. In the sun7i case, the only changes are > because I am NOT hardcoding the CPU to 0, which does look like I broke > it (since that means it will use cpu=1). So I'm going to need to fix > that in v3. ^^^ Do you have an update on this? I will try to test it on an R40 ASAP. Cheers, Andre > For good measure, I also applied the same methodology to patch 2 in this > series, and that introduces no text section changes whatsoever in any of > the tested cases. So patch 2 (theoretically, anyway) needs no bugfixes > or hardware testing. > > Patch 3 does cause a text section change for all targets. I will have to > investigate why, in case I messed up any of the offsets when migrating > off of structs. > > Regards, > Sam
Re: [PATCH v2 5/5] HACK: sunxi: psci: be compatible with v1 of R528 patchset
On Wed, 16 Aug 2023 10:34:20 -0700
Sam Edwards wrote:
Hi Sam,
> This is a hack for reviewer QoL. It is not being submitted for mainline
> inclusion.
> ---
> arch/arm/cpu/armv7/sunxi/psci.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
> index b4ce4f6def..27bac291d5 100644
> --- a/arch/arm/cpu/armv7/sunxi/psci.c
> +++ b/arch/arm/cpu/armv7/sunxi/psci.c
> @@ -60,6 +60,18 @@
>
> #define SUN8I_R528_C0_STATUS_STANDBYWFI (16)
>
> +/* 3 hacks for compatibility across v1/v2 of Andre's R528 support series */
> +#ifndef SUNXI_R_CPUCFG_BASE
> +#define SUNXI_R_CPUCFG_BASE 0
> +#endif
Mmh, I didn't find a better solution than keeping this in.
> +#ifndef SUNXI_PRCM_BASE
> +#define SUNXI_PRCM_BASE 0
So this is now handled. As Samuel pointed out, the R329 (another member of
the "NCAT2" family), actually documents a PRCM block, and arguably the
T113s/D1 have that as well, it's just not very useful (at least for
U-Boot), so we didn't need it so far. I just put the address documented in
the R329 manual into cpu_sunxi_ncat2.h, so the symbol expands properly.
> +#endif
> +#if defined(SUNXI_CPUX_BASE) && defined(SUNXI_CPUCFG_BASE)
> +#undef SUNXI_CPUCFG_BASE
> +#define SUNXI_CPUCFG_BASE SUNXI_CPUX_BASE
So what's the story with this? Do we name this differently
(SUNXI_CPUX_BASE) because the IP block is different from the other SoCs?
Or is there another SUNXI_CPUCFG IP block on the R528/T113s SoCs?
If not, I think we should use the SUNXI_CPUCFG_BASE name directly in
cpu_sunxi_ncat2.h, as we never claimed that same names for some MMIO
address blocks means they are compatible.
Please let me know if I miss something.
Cheers,
Andre
> +#endif
> +
> static void __secure cp15_write_cntp_tval(u32 tval)
> {
> asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
Re: [PATCH v2 4/5] sunxi: psci: implement PSCI on R528
On Wed, 16 Aug 2023 10:34:19 -0700
Sam Edwards wrote:
Hi Sam,
> This patch adds the necessary code to make nonsec booting and PSCI
> secondary core management functional on the R528/T113.
>
> Signed-off-by: Sam Edwards
> Tested-by: Maksim Kiselev
> ---
> arch/arm/cpu/armv7/sunxi/psci.c | 48 -
> arch/arm/mach-sunxi/Kconfig | 2 ++
> include/configs/sunxi-common.h | 8 ++
> 3 files changed, 57 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
> index 6ecdd05250..b4ce4f6def 100644
> --- a/arch/arm/cpu/armv7/sunxi/psci.c
> +++ b/arch/arm/cpu/armv7/sunxi/psci.c
> @@ -47,6 +47,19 @@
> #define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
> #define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
>
> +/*
> + * R528 is also different, as it has both cores powered up (but held in reset
> + * state) after the SoC is reset. Like the R40, it uses a "soft" entry point
> + * address register, but unlike the R40, it uses a newer "CPUX" block to
> manage
> + * CPU state, rather than the older CPUCFG system.
> + */
> +#define SUN8I_R528_SOFT_ENTRY(0x1c8)
> +#define SUN8I_R528_C0_RST_CTRL (0x)
> +#define SUN8I_R528_C0_CTRL_REG0 (0x0010)
> +#define SUN8I_R528_C0_CPU_STATUS (0x0080)
> +
> +#define SUN8I_R528_C0_STATUS_STANDBYWFI (16)
> +
> static void __secure cp15_write_cntp_tval(u32 tval)
> {
> asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
> @@ -103,10 +116,13 @@ static void __secure clamp_set(u32 *clamp)
>
> static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void
> *entry)
> {
> - /* secondary core entry address is programmed differently on R40 */
> + /* secondary core entry address is programmed differently on R40/528 */
I think that's somewhat obvious now from the code, so you can remove this
comment.
> if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {
> writel((u32)entry,
> SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
> + } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
> + writel((u32)entry,
> +SUNXI_R_CPUCFG_BASE + SUN8I_R528_SOFT_ENTRY);
> } else {
> writel((u32)entry, SUNXI_CPUCFG_BASE + SUNXI_PRIV0);
> }
> @@ -124,6 +140,9 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)
> } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {
> clamp = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWR_CLAMP(cpu);
> pwroff = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWROFF;
> + } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
> + /* R528 leaves both cores powered up, manages them via reset */
> + return;
> } else {
> if (IS_ENABLED(CONFIG_MACH_SUN6I) ||
> IS_ENABLED(CONFIG_MACH_SUN8I_H3))
> @@ -151,11 +170,27 @@ static void __secure sunxi_cpu_set_power(int cpu, bool
> on)
>
> static void __secure sunxi_cpu_set_reset(int cpu, bool reset)
> {
> + if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
> + if (reset) {
I think you can lose the brackets here, since it's a single statement
branch, even if it spans multiple lines. The indentation should make this
clear.
> + clrbits_le32(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_RST_CTRL,
> + BIT(cpu));
> + } else {
> + setbits_le32(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_RST_CTRL,
> + BIT(cpu));
> + }
> + return;
> + }
> +
> writel(reset ? 0b00 : 0b11, SUNXI_CPUCFG_BASE + SUNXI_CPU_RST(cpu));
> }
>
> static void __secure sunxi_cpu_set_locking(int cpu, bool lock)
> {
> + if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
> + /* Not required on R528 */
> + return;
> + }
> +
> if (lock)
> clrbits_le32(SUNXI_CPUCFG_BASE + SUNXI_DBG_CTRL1, BIT(cpu));
> else
> @@ -164,11 +199,22 @@ static void __secure sunxi_cpu_set_locking(int cpu,
> bool lock)
>
> static bool __secure sunxi_cpu_poll_wfi(int cpu)
> {
> + if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
> + return !!(readl(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_CPU_STATUS) &
> + BIT(SUN8I_R528_C0_STATUS_STANDBYWFI + cpu));
> + }
> +
> return !!(readl(SUNXI_CPUCFG_BASE + SUNXI_CPU_STATUS(cpu)) & BIT(2));
> }
>
> static void __secure sunxi_cpu_invalidate_cache(int cpu)
> {
> + if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
> + clrbits_le32(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_CTRL_REG0,
> + BIT(cpu));
> + return;
> + }
> +
> clrbits_le32(SUNXI_CPUCFG_BASE + SUNXI_GEN_CTRL, BIT(cpu));
> }
>
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index
[PATCH] tools: iot2050-sign-fw.sh: Make localization of tools dir more robust
From: Jan Kiszka
When building in-tree, there is no source link.
Signed-off-by: Jan Kiszka
---
tools/iot2050-sign-fw.sh | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/tools/iot2050-sign-fw.sh b/tools/iot2050-sign-fw.sh
index 6b426c854c2..75ffd560823 100755
--- a/tools/iot2050-sign-fw.sh
+++ b/tools/iot2050-sign-fw.sh
@@ -5,6 +5,8 @@ if [ -z "$1" ]; then
exit 1
fi
+TOOLS_DIR=$(dirname $0)
+
TEMP_X509=$(mktemp .temp)
REVISION=${2:-0}
@@ -39,10 +41,10 @@ CERT_X509=$(mktemp .crt)
openssl req -new -x509 -key $1 -nodes -outform DER -out $CERT_X509 -config
$TEMP_X509 -sha512
cat $CERT_X509 tispl.bin > tispl.bin_signed
-source/tools/binman/binman replace -i flash-pg1.bin -f tispl.bin_signed
fit@18
-source/tools/binman/binman replace -i flash-pg2.bin -f tispl.bin_signed
fit@18
+$TOOLS_DIR/binman/binman replace -i flash-pg1.bin -f tispl.bin_signed
fit@18
+$TOOLS_DIR/binman/binman replace -i flash-pg2.bin -f tispl.bin_signed
fit@18
rm $TEMP_X509 $CERT_X509
-source/tools/binman/binman sign -i flash-pg1.bin -k $1 -a sha256,rsa4096
fit@38
-source/tools/binman/binman sign -i flash-pg2.bin -k $1 -a sha256,rsa4096
fit@38
+$TOOLS_DIR/binman/binman sign -i flash-pg1.bin -k $1 -a sha256,rsa4096
fit@38
+$TOOLS_DIR/binman/binman sign -i flash-pg2.bin -k $1 -a sha256,rsa4096
fit@38
--
2.35.3
[PATCH v2 4/4] board: freescale: ls1088a: declare MC reserved regions
Populate the device tree with the MC reserved memory regions. Signed-off-by: Laurentiu Tudor --- board/freescale/ls1088a/ls1088a.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 65593f10a3f5..7674e31a268a 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -983,6 +983,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); + fdt_reserve_mc_mem(blob, 0x300); #endif fdt_fixup_icid(blob); -- 2.17.1
[PATCH v2 3/4] board: freescale: ls2080a: declare MC reserved regions
Populate the device tree with the MC reserved memory regions. Signed-off-by: Laurentiu Tudor --- board/freescale/ls2080aqds/ls2080aqds.c | 1 + board/freescale/ls2080ardb/ls2080ardb.c | 1 + 2 files changed, 2 insertions(+) diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index ba25e9b0b8fc..5c94c83121b5 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -325,6 +325,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) fdt_fixup_board_enet(blob); + fdt_reserve_mc_mem(blob, 0x300); #endif fdt_fixup_icid(blob); diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 8d340f17a256..5c30de83d841 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -522,6 +522,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); + fdt_reserve_mc_mem(blob, 0x300); #endif fdt_fixup_icid(blob); -- 2.17.1
[PATCH v2 2/4] drivers: net: fsl-mc: add support for MC reserved memory
Add support for declaring in device tree the reserved memory ranges
required for MC. Since the MC firmware acts as any DMA master present
in the SoC, the reserved memory ranges need also be identity mapped
in the SMMU, so create the required 'iommu-addresses' property in
the reserved memory nodes.
For now this support is used only on LX2160A SoCs.
Signed-off-by: Laurentiu Tudor
---
board/freescale/lx2160a/lx2160a.c | 1 +
drivers/net/fsl-mc/mc.c | 110 ++
include/fsl-mc/fsl_mc.h | 1 +
3 files changed, 112 insertions(+)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index d631a11ff667..688d81f04f64 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -834,6 +834,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_FSL_MC_ENET
fdt_fsl_mc_fixup_iommu_map_entry(blob);
fdt_fixup_board_enet(blob);
+ fdt_reserve_mc_mem(blob, 0x4000);
#endif
fdt_fixup_icid(blob);
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 984616fb65c0..f5c5057bec10 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -30,6 +30,8 @@
#include
#include
#include
+#include
+#include
#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK(~(MC_RAM_BASE_ADDR_ALIGNMENT -
1))
@@ -929,6 +931,114 @@ unsigned long mc_get_dram_block_size(void)
return dram_block_size;
}
+/**
+ * Populate the device tree with MC reserved memory ranges.
+ */
+void fdt_reserve_mc_mem(void *blob, u32 mc_icid)
+{
+ u32 phandle, mc_ph;
+ int noff, ret, i;
+ char mem_name[16];
+ struct fdt_memory mc_mem_ranges[] = {
+ {
+ .start = 0,
+ .end = 0
+ },
+ {
+ .start = CFG_SYS_FSL_MC_BASE,
+ .end = CFG_SYS_FSL_MC_BASE + CFG_SYS_FSL_MC_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_NI_BASE,
+ .end = CFG_SYS_FSL_NI_BASE + CFG_SYS_FSL_NI_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_QBMAN_BASE,
+ .end = CFG_SYS_FSL_QBMAN_BASE +
+ CFG_SYS_FSL_QBMAN_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_PEBUF_BASE,
+ .end = CFG_SYS_FSL_PEBUF_BASE +
+ CFG_SYS_FSL_PEBUF_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_CCSR_BASE,
+ .end = CFG_SYS_FSL_CCSR_BASE + CFG_SYS_FSL_CCSR_SIZE - 1
+ }
+ };
+
+ mc_mem_ranges[0].start = gd->arch.resv_ram;
+ mc_mem_ranges[0].end = mc_mem_ranges[0].start +
+ mc_get_dram_block_size() - 1;
+
+ for (i = 0; i < ARRAY_SIZE(mc_mem_ranges); i++) {
+ noff = fdt_node_offset_by_compatible(blob, -1, "fsl,qoriq-mc");
+ if (noff < 0) {
+ printf("WARN: failed to get MC node: %d\n", noff);
+ return;
+ }
+ mc_ph = fdt_get_phandle(blob, noff);
+ if (!mc_ph) {
+ mc_ph = fdt_create_phandle(blob, noff);
+ if (!mc_ph) {
+ printf("WARN: failed to get MC node phandle\n");
+ return;
+ }
+ }
+
+ sprintf(mem_name, "mc-mem%d", i);
+ ret = fdtdec_add_reserved_memory(blob, mem_name,
+_mem_ranges[i], NULL, 0,
+, 0);
+ if (ret < 0) {
+ printf("ERROR: failed to reserve MC memory: %d\n", ret);
+ return;
+ }
+
+ noff = fdt_node_offset_by_phandle(blob, phandle);
+ if (noff < 0) {
+ printf("ERROR: failed get resvmem node offset: %d\n",
+ noff);
+ return;
+ }
+ ret = fdt_setprop_u32(blob, noff, "iommu-addresses", mc_ph);
+ if (ret < 0) {
+ printf("ERROR: failed to set 'iommu-addresses': %d\n",
+ ret);
+ return;
+ }
+ ret = fdt_appendprop_u64(blob, noff, "iommu-addresses",
+mc_mem_ranges[i].start);
+ if (ret < 0) {
+ printf("ERROR: failed to set 'iommu-addresses': %d\n",
+ ret);
+ return;
+ }
+ ret = fdt_appendprop_u64(blob,
[PATCH v2 1/4] armv8: fsl-layerscape: make some functions static
Some functions are not used outside this file, so make them static.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index ad20d71717b3..c22e73253c3c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -23,8 +23,8 @@ static void set_icid(struct icid_id_table *tbl, int size)
out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
}
-#ifdef CONFIG_SYS_DPAA_FMAN
-void set_fman_icids(struct fman_icid_id_table *tbl, int size)
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
+static void set_fman_icids(struct fman_icid_id_table *tbl, int size)
{
int i;
ccsr_fman_t *fm = (void *)CFG_SYS_FSL_FM1_ADDR;
@@ -71,7 +71,7 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32
*ids, int num_ids)
return 0;
}
-int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
+static int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
struct icid_id_table *tbl, int size)
{
int i, err, off;
@@ -98,7 +98,7 @@ int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
}
#ifdef CONFIG_SYS_DPAA_FMAN
-int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
+static int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
const int size)
{
int i;
@@ -111,7 +111,7 @@ int get_fman_port_icid(int port_id, struct
fman_icid_id_table *tbl,
return -1;
}
-void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
+static void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
const char *compat)
{
int noff, len, icid;
@@ -140,7 +140,7 @@ void fdt_fixup_fman_port_icid_by_compat(void *blob, int
smmu_ph,
}
}
-void fdt_fixup_fman_icids(void *blob, int smmu_ph)
+static void fdt_fixup_fman_icids(void *blob, int smmu_ph)
{
static const char * const compats[] = {
"fsl,fman-v3-port-oh",
--
2.17.1
[PATCH v2 0/4] armv8: fsl-layerscape: add support for MC reserved memory
Add support for declaring in device tree the reserved memory ranges required for MC. Since the MC firmware acts as any DMA master present in the SoC, the reserved memory ranges need also be identity mapped in the SMMU, so create the required 'iommu-addresses' property in the reserved memory nodes. Changes in v2: - added a cover letter - dropped patch creating useless bypass mapping in SMMU Laurentiu Tudor (4): armv8: fsl-layerscape: make some functions static drivers: net: fsl-mc: add support for MC reserved memory board: freescale: ls2080a: declare MC reserved regions board: freescale: ls1088a: declare MC reserved regions arch/arm/cpu/armv8/fsl-layerscape/icid.c | 12 +-- board/freescale/ls1088a/ls1088a.c| 1 + board/freescale/ls2080aqds/ls2080aqds.c | 1 + board/freescale/ls2080ardb/ls2080ardb.c | 1 + board/freescale/lx2160a/lx2160a.c| 1 + drivers/net/fsl-mc/mc.c | 110 +++ include/fsl-mc/fsl_mc.h | 1 + 7 files changed, 121 insertions(+), 6 deletions(-) -- 2.17.1
[PATCH v5 39/43] command: Include a required header in command.h
This uses ARRAY_SIZE() but does not include the header file which declares it. Fix this, so that command.h can be included without common.h Signed-off-by: Simon Glass --- Changes in v5: - Adjust so this builds on azure boot/bootm.c | 2 +- include/command.h | 4 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/boot/bootm.c b/boot/bootm.c index b1c3afe0a3a..8f96a80d425 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -29,7 +30,6 @@ #include "mkimage.h" #endif -#include #include #include diff --git a/include/command.h b/include/command.h index ae7bb4a30b0..34ea989b39b 100644 --- a/include/command.h +++ b/include/command.h @@ -25,6 +25,10 @@ #endif #ifndef__ASSEMBLY__ + +/* For ARRAY_SIZE() */ +#include + /* * Monitor Command Table */ -- 2.42.0.515.g380fc7ccd1-goog
Re: [PATCH v3 04/38] spl: mx6: powerpc: Drop the condition on timer_init()
Hi Christophe,
On Tue, 26 Sept 2023 at 00:46, Christophe Leroy
wrote:
>
>
>
> Le 24/09/2023 à 21:24, Simon Glass a écrit :
> > It doesn't make sense to have some boards do this differently. Drop the
> > condition in the hope that the maintainers can figure out any run-time
> > problems.
>
> This was added by commit ea8256f072 ("SPL: Port SPL framework to
> powerpc"), and the commit log explains why.
>
> Then commit 70e2aaf380 ("board_f: powerpc: Use timer_init() instead of
> init_timebase()") brought timer_init() to powerpc.
>
> All timer_init() does it reset the timebase register to 0 instead of
> leaving a potentially random value. That should just be fine.
>
> Therefore this change should be ok for powerpc.
>
> Acked-by: Christophe Leroy
OK thank you.
>
> >
> > This has been tested on qemu-ppce500
> >
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v3:
> > - Mention testing on qemu-ppce500
> >
> > Changes in v2:
> > - Explicitly copy two maintainers as it seems only Mario was auto-cc'd
> >
> > common/spl/spl.c | 6 --
> > 1 file changed, 6 deletions(-)
> >
> > diff --git a/common/spl/spl.c b/common/spl/spl.c
> > index 5cc86288145b..4233390d7de2 100644
> > --- a/common/spl/spl.c
> > +++ b/common/spl/spl.c
> > @@ -762,13 +762,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
> > if (spl_init())
> > hang();
> > }
> > -#if !defined(CONFIG_PPC) && !defined(CONFIG_ARCH_MX6)
> > - /*
> > - * timer_init() does not exist on PPC systems. The timer is
> > initialized
> > - * and enabled (decrementer) in interrupt_init() here.
> > - */
> > timer_init();
> > -#endif
> > if (CONFIG_IS_ENABLED(BLOBLIST)) {
> > ret = bloblist_init();
> > if (ret) {
Regards,
Simon
Re: [PATCH 4/4] binman: update documentation for fit,align property
Hi Rasmus, On Tue, 26 Sept 2023 at 00:25, Rasmus Villemoes wrote: > > On 25/09/2023 17.14, Jonas Karlman wrote: > > >> fit,align > >> -Indicates what alignment to use for the FIT and its external data, > >> -and provides the alignment to use. This is passed to mkimage via > >> -the -B flag. > >> +Indicates what alignment to use for the FIT and, if applicable, > >> +its external data. This is passed to mkimage via the -B flag. > > > > This only updates entries.rst, please update tools/binman/etype/fit.py > > and re-generate entries.rst from output of running binman entry-docs. > > Ah, I didn't know the .rst was generated. > > Simon, want me to resend (this one or the whole series?), or can you > fold in this when applying: I can fold it in, so long as I remember. > > diff --git a/tools/binman/etype/fit.py b/tools/binman/etype/fit.py > index 2c14b15b03..97d3cedaf5 100644 > --- a/tools/binman/etype/fit.py > +++ b/tools/binman/etype/fit.py > @@ -71,9 +71,8 @@ class Entry_fit(Entry_section): > external offset. This is passed to mkimage via the -E and > -p flags. > > fit,align > -Indicates what alignment to use for the FIT and its > external data, > -and provides the alignment to use. This is passed to > mkimage via > -the -B flag. > +Indicates what alignment to use for the FIT and, if applicable, > +its external data. This is passed to mkimage via the -B flag. > > fit,fdt-list > Indicates the entry argument which provides the list of > device tree > > Rasmus > Regards, Simon
Re: [PATCH v2 01/17] dm: usb: udc: Factor out plain udevice handler functions
Hi Marek, miquel.ray...@bootlin.com wrote on Fri, 22 Sep 2023 12:00:12 +0200: > Hi Marek, > > I'm answering here as there is no cover letter. Just to let you know > I'm still concerned by the series and want to test it but did not had > the time to do so recently. Hopefully next week. The series looks good to me and works as well on a Beagle Bone Black with no visible functional changes regarding the use of the UDC. The whole series is: Tested-by: Miquel Raynal By the way, following your initial series there have been three followup patches trying to improve a little bit the doc, one got merged and two others were delegated to you: https://patchwork.ozlabs.org/project/uboot/list/?series=367635 They are almost 2 months old now, would you mind acking or merging them so both your initial USB gadget rework and the additional (related) doc can be in the same release please? Thanks, Miquèl
[PATCH] arm: mach-k3: common: fix compile warnings with PHYS_64BIT on 32bit
Use uintptr_t instead of phys_addr_t where appropriate, so passing the
addresses to writel() doesn't result in compile warnings when PHYS_64BIT
is set for 32bit builds (which is actually a useful configuration, as
the K3 SoC family boots from an R5 SPL, which may pass bank information
based on gd->bd->bi_dram to fdt_fixup_memory_banks() etc., so PHYS_64BIT
is needed for fixing up the upper bank).
Signed-off-by: Matthias Schiffer
---
arch/arm/mach-k3/common.c | 4 ++--
arch/arm/mach-k3/common.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index a35110429b2..9b90b2fa11c 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -83,10 +83,10 @@ void k3_sysfw_print_ver(void)
ti_sci->version.firmware_revision, fw_desc);
}
-void mmr_unlock(phys_addr_t base, u32 partition)
+void mmr_unlock(uintptr_t base, u32 partition)
{
/* Translate the base address */
- phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
+ uintptr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
/* Unlock the requested partition if locked using two-step sequence */
writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 9bd9ad6d1a0..eabb44f6204 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -38,7 +38,7 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t
fwl_data_size);
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
void k3_sysfw_print_ver(void);
void spl_enable_dcache(void);
-void mmr_unlock(phys_addr_t base, u32 partition);
+void mmr_unlock(uintptr_t base, u32 partition);
bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
enum k3_device_type get_device_type(void);
void ti_secure_image_post_process(void **p_image, size_t *p_size);
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/
[PATCH 4/5] pinctrl: single: fix compile warnings with PHYS_64BIT on 32bit
pinctrl-single uses fdt_addr_t and phys_addr_t inconsistently, but both
are wrong to be passed to readb() etc., which expect a pointer or
pointer-sized integer. Change the driver to use
dev_read_addr_size_index_ptr(), so we consistently deal with void*
(except for the sandbox case and single_get_pin_muxing()).
Signed-off-by: Matthias Schiffer
---
Tested on x86 sandbox and TI AM62x. No new unit test failures in
sandbox.
drivers/pinctrl/pinctrl-single.c | 33 +---
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index d80281fd3dd..fb34f681740 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -24,7 +24,7 @@
* @bits_per_mux: true if one register controls more than one pin
*/
struct single_pdata {
- fdt_addr_t base;
+ void *base;
int offset;
u32 mask;
u32 width;
@@ -97,7 +97,7 @@ struct single_fdt_bits_cfg {
#if (!IS_ENABLED(CONFIG_SANDBOX))
-static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
+static unsigned int single_read(struct udevice *dev, void *reg)
{
struct single_pdata *pdata = dev_get_plat(dev);
@@ -113,7 +113,7 @@ static unsigned int single_read(struct udevice *dev,
fdt_addr_t reg)
return readb(reg);
}
-static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
+static void single_write(struct udevice *dev, unsigned int val, void *reg)
{
struct single_pdata *pdata = dev_get_plat(dev);
@@ -131,18 +131,18 @@ static void single_write(struct udevice *dev, unsigned
int val, fdt_addr_t reg)
#else /* CONFIG_SANDBOX */
-static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
+static unsigned int single_read(struct udevice *dev, void *reg)
{
struct single_priv *priv = dev_get_priv(dev);
- return priv->sandbox_regs[reg];
+ return priv->sandbox_regs[map_to_sysmem(reg)];
}
-static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
+static void single_write(struct udevice *dev, unsigned int val, void *reg)
{
struct single_priv *priv = dev_get_priv(dev);
- priv->sandbox_regs[reg] = val;
+ priv->sandbox_regs[map_to_sysmem(reg)] = val;
}
#endif /* CONFIG_SANDBOX */
@@ -214,7 +214,8 @@ static int single_get_pin_muxing(struct udevice *dev,
unsigned int pin,
{
struct single_pdata *pdata = dev_get_plat(dev);
struct single_priv *priv = dev_get_priv(dev);
- fdt_addr_t reg;
+ phys_addr_t phys_reg;
+ void *reg;
const char *fname;
unsigned int val;
int offset, pin_shift = 0;
@@ -226,13 +227,15 @@ static int single_get_pin_muxing(struct udevice *dev,
unsigned int pin,
reg = pdata->base + offset;
val = single_read(dev, reg);
+ phys_reg = map_to_sysmem(reg);
+
if (pdata->bits_per_mux)
pin_shift = pin % (pdata->width / priv->bits_per_pin) *
priv->bits_per_pin;
val &= (pdata->mask << pin_shift);
fname = single_get_pin_function(dev, pin);
- snprintf(buf, size, "%pa 0x%08x %s", , val,
+ snprintf(buf, size, "%pa 0x%08x %s", _reg, val,
fname ? fname : "UNCLAIMED");
return 0;
}
@@ -243,7 +246,7 @@ static int single_request(struct udevice *dev, int pin, int
flags)
struct single_pdata *pdata = dev_get_plat(dev);
struct single_gpiofunc_range *frange = NULL;
struct list_head *pos, *tmp;
- phys_addr_t reg;
+ void *reg;
int mux_bytes = 0;
u32 data;
@@ -321,7 +324,7 @@ static int single_configure_pins(struct udevice *dev,
int stride = pdata->args_count + 1;
int n, pin, count = size / sizeof(u32);
struct single_func *func;
- phys_addr_t reg;
+ void *reg;
u32 offset, val, mux;
/* If function mask is null, needn't enable it. */
@@ -379,7 +382,7 @@ static int single_configure_bits(struct udevice *dev,
int n, pin, count = size / sizeof(struct single_fdt_bits_cfg);
int npins_in_reg, pin_num_from_lsb;
struct single_func *func;
- phys_addr_t reg;
+ void *reg;
u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask;
/* If function mask is null, needn't enable it. */
@@ -570,7 +573,7 @@ static int single_probe(struct udevice *dev)
static int single_of_to_plat(struct udevice *dev)
{
- fdt_addr_t addr;
+ void *addr;
fdt_size_t size;
struct single_pdata *pdata = dev_get_plat(dev);
int ret;
@@ -591,8 +594,8 @@ static int single_of_to_plat(struct udevice *dev)
return -EINVAL;
}
- addr = dev_read_addr_size_index(dev, 0, );
- if (addr == FDT_ADDR_T_NONE) {
+ addr = dev_read_addr_size_index_ptr(dev, 0, );
+ if (!addr) {
dev_err(dev, "failed to
[PATCH 5/5] treewide: use dev_read_addr_*_ptr() where appropriate
A follow-up to commit 842fb5de424e
("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer")
and commit 320a1938b6f7
("drivers: use devfdt_get_addr_index_ptr when cast to pointer").
In addition to using the *_ptr variants of these functions where the
address is cast to a pointer, this also changes devfdt_get_addr_*() to
dev_read_addr_*() in a few places. Some variable and field types are
changed from fdt_addr_t or phys_addr_t to void* where the cast was
happening later.
This patch fixes a number of compile warnings when building a 32bit
U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error
handling where the return value of dev_read_addr() etc. was checked for
NULL instead of FDT_ADDR_T_NONE.
Signed-off-by: Matthias Schiffer
---
This seems to work correctly (tested on x86 sandbox and TI AM62x; I have
not tested the Tegra, Sun4i and BCM drivers), but I have two questions:
It is not entirely clear to me what the difference between
dev_read_addr_ptr*() and dev_remap_addr*() etc. is, but some drivers mix
both. Should dev_remap_addr*() be used for __iomem? Is __iomem used
consistently in U-Boot at all?
Furthermore, can devfdt_get_*() be replaced with dev_read_*()
unconditionally? Is there any reason why devfdt_get_*() hasn't been
dropped entirely in a treewide search-and-replace?
The k3-sec-proxy change goes on top of my other patch "mailbox:
k3-sec-proxy: fix error handling for missing scfg in FDT" I submitted
yesterday.
arch/arm/mach-k3/sysfw-loader.c | 16
drivers/dma/ti/k3-udma.c | 5 ++---
drivers/gpio/tegra186_gpio.c | 4 ++--
drivers/mailbox/k3-sec-proxy.c| 18 +-
drivers/phy/allwinner/phy-sun4i-usb.c | 12 ++--
drivers/phy/phy-bcm-sr-pcie.c | 4 ++--
drivers/ram/k3-am654-ddrss.c | 20 ++--
drivers/ram/k3-ddrss/k3-ddrss.c | 23 ++-
drivers/soc/ti/k3-navss-ringacc.c | 12 ++--
9 files changed, 55 insertions(+), 59 deletions(-)
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 9be2d9eaea2..ef245fef9c4 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -321,7 +321,7 @@ exit:
static void *k3_sysfw_get_spi_addr(void)
{
struct udevice *dev;
- fdt_addr_t addr;
+ void *addr;
int ret;
unsigned int sf_bus = spl_spi_boot_bus();
@@ -329,11 +329,11 @@ static void *k3_sysfw_get_spi_addr(void)
if (ret)
return NULL;
- addr = dev_read_addr_index(dev, 1);
- if (addr == FDT_ADDR_T_NONE)
+ addr = dev_read_addr_index_ptr(dev, 1);
+ if (!addr)
return NULL;
- return (void *)(addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS);
+ return addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS;
}
static void k3_sysfw_spi_copy(u32 *dst, u32 *src, size_t len)
@@ -349,18 +349,18 @@ static void k3_sysfw_spi_copy(u32 *dst, u32 *src, size_t
len)
static void *get_sysfw_hf_addr(void)
{
struct udevice *dev;
- fdt_addr_t addr;
+ void *addr;
int ret;
ret = uclass_find_first_device(UCLASS_MTD, );
if (ret)
return NULL;
- addr = dev_read_addr_index(dev, 1);
- if (addr == FDT_ADDR_T_NONE)
+ addr = dev_read_addr_index_ptr(dev, 1);
+ if (!addr)
return NULL;
- return (void *)(addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS);
+ return addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS;
}
#endif
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 05c3a4311ce..1847c8889aa 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -1286,7 +1286,7 @@ static int udma_get_mmrs(struct udevice *dev)
u32 cap2, cap3, cap4;
int i;
- ud->mmrs[MMR_GCFG] = (uint32_t *)devfdt_get_addr_name(dev,
mmr_names[MMR_GCFG]);
+ ud->mmrs[MMR_GCFG] = dev_read_addr_name_ptr(dev, mmr_names[MMR_GCFG]);
if (!ud->mmrs[MMR_GCFG])
return -EINVAL;
@@ -1324,8 +1324,7 @@ static int udma_get_mmrs(struct udevice *dev)
if (i == MMR_RCHANRT && ud->rchan_cnt == 0)
continue;
- ud->mmrs[i] = (uint32_t *)devfdt_get_addr_name(dev,
- mmr_names[i]);
+ ud->mmrs[i] = dev_read_addr_name_ptr(dev, mmr_names[i]);
if (!ud->mmrs[i])
return -EINVAL;
}
diff --git a/drivers/gpio/tegra186_gpio.c b/drivers/gpio/tegra186_gpio.c
index 82dcaf96312..94a20d143e1 100644
--- a/drivers/gpio/tegra186_gpio.c
+++ b/drivers/gpio/tegra186_gpio.c
@@ -176,8 +176,8 @@ static int tegra186_gpio_bind(struct udevice *parent)
if (parent_plat)
return 0;
- regs = (uint32_t *)devfdt_get_addr_name(parent, "gpio");
- if (regs == (uint32_t *)FDT_ADDR_T_NONE)
+ regs = dev_read_addr_name_ptr(parent, "gpio");
+
[PATCH 3/5] core: introduce dev_read_addr_name[_size]_ptr() functions
Same as dev_read_addr_name[_size](), but returns a pointer, cast
through map_sysmem().
Signed-off-by: Matthias Schiffer
---
drivers/core/fdtaddr.c | 21 +
drivers/core/read.c| 21 +
include/dm/fdtaddr.h | 31 +++
include/dm/read.h | 41 +
4 files changed, 114 insertions(+)
diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index 426bb762754..560b0b634a2 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -153,6 +153,16 @@ fdt_addr_t devfdt_get_addr_name(const struct udevice *dev,
const char *name)
#endif
}
+void *devfdt_get_addr_name_ptr(const struct udevice *dev, const char *name)
+{
+ fdt_addr_t addr = devfdt_get_addr_name(dev, name);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_sysmem(addr, 0);
+}
+
fdt_addr_t devfdt_get_addr_size_name(const struct udevice *dev,
const char *name, fdt_size_t *size)
{
@@ -170,6 +180,17 @@ fdt_addr_t devfdt_get_addr_size_name(const struct udevice
*dev,
#endif
}
+void *devfdt_get_addr_size_name_ptr(const struct udevice *dev,
+ const char *name, fdt_size_t *size)
+{
+ fdt_addr_t addr = devfdt_get_addr_size_name(dev, name, size);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_sysmem(addr, 0);
+}
+
fdt_addr_t devfdt_get_addr(const struct udevice *dev)
{
return devfdt_get_addr_index(dev, 0);
diff --git a/drivers/core/read.c b/drivers/core/read.c
index 49066b59cda..0908321c846 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -181,6 +181,16 @@ fdt_addr_t dev_read_addr_name(const struct udevice *dev,
const char *name)
return dev_read_addr_index(dev, index);
}
+void *dev_read_addr_name_ptr(const struct udevice *dev, const char *name)
+{
+ fdt_addr_t addr = dev_read_addr_name(dev, name);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_sysmem(addr, 0);
+}
+
fdt_addr_t dev_read_addr_size_name(const struct udevice *dev, const char *name,
fdt_size_t *size)
{
@@ -192,6 +202,17 @@ fdt_addr_t dev_read_addr_size_name(const struct udevice
*dev, const char *name,
return dev_read_addr_size_index(dev, index, size);
}
+void *dev_read_addr_size_name_ptr(const struct udevice *dev, const char *name,
+ fdt_size_t *size)
+{
+ fdt_addr_t addr = dev_read_addr_size_name(dev, name, size);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_sysmem(addr, 0);
+}
+
void *dev_remap_addr_name(const struct udevice *dev, const char *name)
{
fdt_addr_t addr = dev_read_addr_name(dev, name);
diff --git a/include/dm/fdtaddr.h b/include/dm/fdtaddr.h
index d3ad77faebf..750ca0076ed 100644
--- a/include/dm/fdtaddr.h
+++ b/include/dm/fdtaddr.h
@@ -146,6 +146,19 @@ void *devfdt_get_addr_size_index_ptr(const struct udevice
*dev, int index,
*/
fdt_addr_t devfdt_get_addr_name(const struct udevice *dev, const char *name);
+/**
+ * devfdt_get_addr_name_ptr() - Get the reg property of a device as a pointer,
+ * indexed by name
+ *
+ * @dev: Pointer to a device
+ * @name: the 'reg' property can hold a list of pairs, with the
+ * 'reg-names' property providing named-based identification. @name
+ * indicates the value to search for in 'reg-names'.
+ *
+ * Return: Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_get_addr_name_ptr(const struct udevice *dev, const char *name);
+
/**
* devfdt_get_addr_size_name() - Get the reg property and its size for a
device,
* indexed by name
@@ -164,6 +177,24 @@ fdt_addr_t devfdt_get_addr_name(const struct udevice *dev,
const char *name);
fdt_addr_t devfdt_get_addr_size_name(const struct udevice *dev,
const char *name, fdt_size_t *size);
+/**
+ * devfdt_get_addr_size_name_ptr() - Get the reg property for a device as a
+ * pointer, indexed by name
+ *
+ * Returns the address and size specified in the 'reg' property of a device.
+ *
+ * @dev: Pointer to a device
+ * @name: the 'reg' property can hold a list of pairs, with the
+ * 'reg-names' property providing named-based identification. @name
+ * indicates the value to search for in 'reg-names'.
+ * @size: Pointer to size variable - this function returns the size
+ *specified in the 'reg' property here
+ *
+ * Return: Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_get_addr_size_name_ptr(const struct udevice *dev,
+ const char *name, fdt_size_t *size);
+
/**
* devfdt_get_addr_pci() - Read an address and handle PCI address translation
[PATCH 2/5] core: return FDT_ADDR_T_NONE from devfdt_get_addr_[size_]name() on errors
Checking for the error cast to fdt_addr_t is rather awkward - IS_ERR() can be used, but it's not really made to be used on fdt_addr_t, which may not even be the same size as a native pointer. Most places in U-Boot only check for FDT_ADDR_T_NONE; let's adjust the error return to match the expectation. Signed-off-by: Matthias Schiffer --- drivers/core/fdtaddr.c | 4 ++-- include/dm/fdtaddr.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c index 546db675aaf..426bb762754 100644 --- a/drivers/core/fdtaddr.c +++ b/drivers/core/fdtaddr.c @@ -145,7 +145,7 @@ fdt_addr_t devfdt_get_addr_name(const struct udevice *dev, const char *name) index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev), "reg-names", name); if (index < 0) - return index; + return FDT_ADDR_T_NONE; return devfdt_get_addr_index(dev, index); #else @@ -162,7 +162,7 @@ fdt_addr_t devfdt_get_addr_size_name(const struct udevice *dev, index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev), "reg-names", name); if (index < 0) - return index; + return FDT_ADDR_T_NONE; return devfdt_get_addr_size_index(dev, index, size); #else diff --git a/include/dm/fdtaddr.h b/include/dm/fdtaddr.h index ca788dccb39..d3ad77faebf 100644 --- a/include/dm/fdtaddr.h +++ b/include/dm/fdtaddr.h @@ -142,7 +142,7 @@ void *devfdt_get_addr_size_index_ptr(const struct udevice *dev, int index, * 'reg-names' property providing named-based identification. @name * indicates the value to search for in 'reg-names'. * - * Return: addr + * Return: Address, or FDT_ADDR_T_NONE if there is no such property */ fdt_addr_t devfdt_get_addr_name(const struct udevice *dev, const char *name); @@ -159,7 +159,7 @@ fdt_addr_t devfdt_get_addr_name(const struct udevice *dev, const char *name); * @size: Pointer to size variable - this function returns the size *specified in the 'reg' property here * - * Return: addr + * Return: Address, or FDT_ADDR_T_NONE if there is no such property */ fdt_addr_t devfdt_get_addr_size_name(const struct udevice *dev, const char *name, fdt_size_t *size); -- TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht München, HRB 105018 Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider https://www.tq-group.com/
[PATCH 1/5] core: fix doc comments of dev_read_addr*() and related functions
- The dev_read_addr_name*() family of functions has no "index" argument, doc comments should refer to "name" - Specify the error return for several devfdt_get_addr*() functions Signed-off-by: Matthias Schiffer --- include/dm/fdtaddr.h | 12 ++-- include/dm/read.h| 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/dm/fdtaddr.h b/include/dm/fdtaddr.h index dcdc19137cc..ca788dccb39 100644 --- a/include/dm/fdtaddr.h +++ b/include/dm/fdtaddr.h @@ -19,7 +19,7 @@ struct udevice; * * @dev: Pointer to a device * - * Return: addr + * Return: Address, or FDT_ADDR_T_NONE if there is no such property */ fdt_addr_t devfdt_get_addr(const struct udevice *dev); @@ -59,7 +59,7 @@ void *devfdt_remap_addr_index(const struct udevice *dev, int index); * devfdt_remap_addr_name() - Get the reg property of a device, indexed by *name, as a memory-mapped I/O pointer * @name: the 'reg' property can hold a list of pairs, with the - * 'reg-names' property providing named-based identification. @index + * 'reg-names' property providing named-based identification. @name * indicates the value to search for in 'reg-names'. * * @dev: Pointer to a device @@ -87,7 +87,7 @@ void *devfdt_map_physmem(const struct udevice *dev, unsigned long size); * @index: the 'reg' property can hold a list of pairs *and @index is used to select which one is required * - * Return: addr + * Return: Address, or FDT_ADDR_T_NONE if there is no such property */ fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index); @@ -114,7 +114,7 @@ void *devfdt_get_addr_index_ptr(const struct udevice *dev, int index); * @size: Pointer to size variable - this function returns the size *specified in the 'reg' property here * - * Return: addr + * Return: Address, or FDT_ADDR_T_NONE if there is no such property */ fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index, fdt_size_t *size); @@ -139,7 +139,7 @@ void *devfdt_get_addr_size_index_ptr(const struct udevice *dev, int index, * * @dev: Pointer to a device * @name: the 'reg' property can hold a list of pairs, with the - * 'reg-names' property providing named-based identification. @index + * 'reg-names' property providing named-based identification. @name * indicates the value to search for in 'reg-names'. * * Return: addr @@ -154,7 +154,7 @@ fdt_addr_t devfdt_get_addr_name(const struct udevice *dev, const char *name); * * @dev: Pointer to a device * @name: the 'reg' property can hold a list of pairs, with the - * 'reg-names' property providing named-based identification. @index + * 'reg-names' property providing named-based identification. @name * indicates the value to search for in 'reg-names'. * @size: Pointer to size variable - this function returns the size *specified in the 'reg' property here diff --git a/include/dm/read.h b/include/dm/read.h index c2615f72f40..da7732a170f 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -277,7 +277,7 @@ void *dev_remap_addr_index(const struct udevice *dev, int index); * * @dev: Device to read from * @name: the 'reg' property can hold a list of pairs, with the - * 'reg-names' property providing named-based identification. @index + * 'reg-names' property providing named-based identification. @name * indicates the value to search for in 'reg-names'. * * Return: address or FDT_ADDR_T_NONE if not found @@ -289,7 +289,7 @@ fdt_addr_t dev_read_addr_name(const struct udevice *dev, const char *name); * * @dev: Device to read from * @name: the 'reg' property can hold a list of pairs, with the - * 'reg-names' property providing named-based identification. @index + * 'reg-names' property providing named-based identification. @name * indicates the value to search for in 'reg-names'. * @size: place to put size value (on success) * @@ -304,7 +304,7 @@ fdt_addr_t dev_read_addr_size_name(const struct udevice *dev, const char *name, * * @dev: Device to read from * @name: the 'reg' property can hold a list of pairs, with the - * 'reg-names' property providing named-based identification. @index + * 'reg-names' property providing named-based identification. @name * indicates the value to search for in 'reg-names'. * * Return: pointer or NULL if not found -- TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht München, HRB 105018 Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider https://www.tq-group.com/
[PATCH v4 5/6] arm: dts: k3-j721e-r5: Clean up inclusion hierarchy
Get rid of k3-j721e-r5-*-u-boot.dtsi as it is not
necessary. Change the inclusion hierarchy to be as follows:
k3-j721e-.dts---
-
-->k3-j721e-r5-.dts
-
k3-j721e--u-boot.dtsi---
Reason for explicitly mentioning the inclusion of -u-boot.dtsi in code
although it could've been automatically done by U-Boot is to resolve
some of the dependencies that R5 file requires.
Also remove duplicate phandles while making this shift as well as remove
firmware-loader as it serves no purpose without "phandlepart" property.
Signed-off-by: Neha Malcom Francis
---
.../k3-j721e-r5-common-proc-board-u-boot.dtsi | 29
.../arm/dts/k3-j721e-r5-common-proc-board.dts | 38 +++
arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi | 31
arch/arm/dts/k3-j721e-r5-sk.dts | 47 ---
4 files changed, 16 insertions(+), 129 deletions(-)
delete mode 100644 arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
delete mode 100644 arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
deleted file mode 100644
index f9746d33ec..00
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include "k3-j721e-common-proc-board-u-boot.dtsi"
-
-/ {
- chosen {
- firmware-loader = _loader0;
- };
-
- aliases {
- remoteproc0 =
- remoteproc1 = _0;
- };
-
- fs_loader0: fs_loader@0 {
- bootph-all;
- compatible = "u-boot,fs-loader";
- };
-};
-
- {
- esm: esm {
- compatible = "ti,tps659413-esm";
- bootph-pre-ram;
- };
-};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 32f71e9b6a..7bb5ce775c 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -5,10 +5,10 @@
/dts-v1/;
-#include "k3-j721e-som-p0.dtsi"
+#include "k3-j721e-common-proc-board.dts"
#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
#include "k3-j721e-ddr.dtsi"
-#include "k3-j721e-binman.dtsi"
+#include "k3-j721e-common-proc-board-u-boot.dtsi"
#include
/ {
@@ -198,27 +198,6 @@
>;
};
- main_usbss0_pins_default: main_usbss0_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS
*/
- J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3)
MCAN1_RX.GPIO1_3 */
- >;
- };
-
- main_mmc1_pins_default: main_mmc1_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
- J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
- J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
- J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
- J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
- J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
- J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
- J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
- J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
- >;
- };
-
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5)
I2C0_SCL */
@@ -300,6 +279,11 @@
bootph-pre-ram;
};
};
+
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ bootph-pre-ram;
+ };
};
};
@@ -424,14 +408,6 @@
assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>, <
CDNS_SIERRA_PLL_CMNLC1>;
assigned-clock-parents = <_pll1_refclk>, <_pll1_refclk>;
- serdes0_pcie_link: link@0 {
- reg = <0>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = ;
- resets = <_wiz0 1>;
- };
-
serdes0_qsgmii_link: phy@1 {
reg = <1>;
cdns,num-lanes = <1>;
diff --git a/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
b/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
deleted file mode 100644
index 733d69cd00..00
--- a/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2021 Texas Instruments Incorporated -
[PATCH v4 4/6] configs: j721e: Remove HBMC_AM654 config
Kernel commit d93036b47f35 ("arm64: dts: ti: k3-j721e-mcu_wakeup: Add
HyperBus node") was merged to kernel without its dependent patch [1].
Similar fix is needed in U-Boot, and hbmc currently breaks boot. Till
this gets fixed in U-Boot, disable the config by default so that the
hbmc probe that happens in board/ti/j721e/evm.c will not take place
and lead to boot failure.
[1] https://lore.kernel.org/all/20230424184810.29453-1-...@ti.com/
Signed-off-by: Neha Malcom Francis
---
configs/j721e_evm_a72_defconfig | 1 -
configs/j721e_evm_r5_defconfig | 1 -
2 files changed, 2 deletions(-)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 214fa8b2f3..beea948c4e 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -140,7 +140,6 @@ CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index cf7bc872b5..d974be275f 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -127,7 +127,6 @@ CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_STMICRO=y
--
2.34.1
[PATCH v4 3/6] drivers: firmware: ti_sci: Get SCI revision only if TIFS/SYSFW is up
When setting up boot media to load the TIFS binary in legacy boot flow
(followed by J721E), get_timer() is called which calls dm_timer_init()
which then gets the tick-timer: mcu_timer0. mcu_timer0 uses k3_clks
(clock controller) and k3_pds (power controller) from the dmsc node that
forces probe of the ti_sci driver of TIFS that hasn't been loaded yet!
Running ti_sci_cmd_get_revision from the probe leads to panic since no
TIFS and board config binaries have been loaded yet. Resolve this by
moving ti_sci_cmd_get_revision to ti_sci_get_handle_from_sysfw as a
common point of invocation for both legacy and combined boot flows.
Before doing this, it is important to go through whether any sync points
exist where revision is needed before ti_sci_get_handle_from_sysfw is
invoked. Going through the code along with boot tests on both flows
ensures that there are none.
Signed-off-by: Neha Malcom Francis
---
Boot logs for affected boot flows (AM65x, AM64x, J721E, J7200, J721S2,
AM62x):
https://gist.github.com/nehamalcom/dcaa32bb9f7f28bf1bb449d153e7b566
drivers/firmware/ti_sci.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 72f572d824..166bd78ca5 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -2690,6 +2690,8 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
const
struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *sci_dev)
{
+ int ret;
+
if (!sci_dev)
return ERR_PTR(-EINVAL);
@@ -2703,6 +2705,11 @@ struct ti_sci_handle
*ti_sci_get_handle_from_sysfw(struct udevice *sci_dev)
if (!handle)
return ERR_PTR(-EINVAL);
+ ret = ti_sci_cmd_get_revision(handle);
+
+ if (ret)
+ return ERR_PTR(-EINVAL);
+
return handle;
}
@@ -2825,11 +2832,9 @@ static int ti_sci_probe(struct udevice *dev)
list_add_tail(>list, _sci_list);
ti_sci_setup_ops(info);
- ret = ti_sci_cmd_get_revision(>handle);
-
INIT_LIST_HEAD(>dev_list);
- return ret;
+ return 0;
}
/**
--
2.34.1
[PATCH v4 2/6] arm: mach-k3: j721e_init: Move clk_k3 probe before loading TIFS
When setting boot media to load the TIFS binary in legacy boot flow
(followed by J721E), get_timer() is called which eventually calls
dm_timer_init() to grab the tick-timer, which is mcu_timer0. Since we
need to set up the clocks before using the timer, move clk_k3 driver
probe before k3_sysfw_loader to ensure we have all necessary clocks set
up before.
Signed-off-by: Neha Malcom Francis
Reviewed-by: Nishanth Menon
---
arch/arm/mach-k3/j721e_init.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index b6164575b7..b1f7e25ed0 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -228,6 +228,18 @@ void board_init_f(ulong dummy)
if (!ret)
pinctrl_select_state(dev, "default");
+ /*
+* Force probe of clk_k3 driver here to ensure basic default clock
+* configuration is always done.
+*/
+ if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(ti_clk),
+ );
+ if (ret)
+ panic("Failed to initialize clk-k3!\n");
+ }
+
/*
* Load, start up, and configure system controller firmware. Provide
* the U-Boot console init function to the SYSFW post-PM configuration
@@ -241,18 +253,6 @@ void board_init_f(ulong dummy)
do_dt_magic();
#endif
- /*
-* Force probe of clk_k3 driver here to ensure basic default clock
-* configuration is always done.
-*/
- if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
- ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_DRIVER_GET(ti_clk),
- );
- if (ret)
- panic("Failed to initialize clk-k3!\n");
- }
-
/* Prepare console output */
preloader_console_init();
--
2.34.1
[PATCH v4 1/6] arm: mach-k3: j721e: dev-data: Add mcu_timer0 ID
U-Boot uses mcu_timer0 as the tick-timer, so add it to device list.
Signed-off-by: Neha Malcom Francis
Reviewed-by: Manorit Chawdhry
Reviewed-by: Nishanth Menon
---
arch/arm/mach-k3/j721e/dev-data.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-k3/j721e/dev-data.c
b/arch/arm/mach-k3/j721e/dev-data.c
index 97f017f8af..b0adb1857b 100644
--- a/arch/arm/mach-k3/j721e/dev-data.c
+++ b/arch/arm/mach-k3/j721e/dev-data.c
@@ -56,6 +56,7 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(4, _lpsc_list[8]),
PSC_DEV(202, _lpsc_list[9]),
PSC_DEV(203, _lpsc_list[10]),
+ PSC_DEV(35, _lpsc_list[11]),
PSC_DEV(102, _lpsc_list[11]),
PSC_DEV(103, _lpsc_list[11]),
PSC_DEV(104, _lpsc_list[11]),
--
2.34.1
[PATCH v4 0/6] J721E DTS Sync with Kernel v6.6-rc1
This series aims to sync kernel.org v6.6-rc1 DTS with that of U-Boot. It also includes cleanups where necessary along with certain changes to ensure boot is unaffected. Same as with other board series that have taken up this effort, cleanup of mcu_ringacc and mcu_udmap are dependent on MCU DMA [1] fixes. Also adding TPS6594 PMIC support is still under review [2] in the Kernel. These will be taken up after their merge to Linux. [1] https://lore.kernel.org/all/20230810174356.3322583-1-vigne...@ti.com/ [2] https://lore.kernel.org/all/20230810-tps6594-v6-0-2b2e2399e...@ti.com/ Boot logs: https://gist.github.com/nehamalcom/ca67dd714027a76cc711f41c25d33dfe Changes in v4: - return PTR_ERR instead of int in ti_sci_get_handle_sysfw for error handling - Nishanth: - Modify commit message to include summary of changes - Move wkup_uart0_pins_default and mcu_uart0_pins_default to R5 DTS - Remove hbmc node completely - Remove ti,cluster-mode override - Remove clock-frequency properties that are already accounted for by clk-data - Document reason for retaining tps node in commit message - Move mcu_ringacc and mcu_udmap before peripherals - add bootlogs for patch (3/7) for different boot flows Changes in v3: - Nishanth: - synced to v6.6-rc1 from v6.5-rc1 - reworded commit messages - removed patch adding k3_avs compatible since it has been merged to -next separately - removed unnecessary #includes - added extra comments for OSPI reg overrides - removed hbmc node from R5 DTS - changed ti_sci_get_cmd_revision to be at a common point for all boot flows - Manorit: - added Reviewed-by tag for mcu_timer0 ID patch (2/7) - removed all aliases - removed unnecessary properties Changes in v2: - Nishanth: - synced k3-j721e-som-0.dtsi 6.5-rc1 - delete tick-timer from -u-boot.dtsi - remove unnecessary aliases - remove SERDES overrides in U-Boot - formatting changes - drop repeated nodes and properties in U-Boot dts - drop nodes and properties not related to U-Boot from U-Boot dts - drop all /delete Neha Malcom Francis (6): arm: mach-k3: j721e: dev-data: Add mcu_timer0 ID arm: mach-k3: j721e_init: Move clk_k3 probe before loading TIFS drivers: firmware: ti_sci: Get SCI revision only if TIFS/SYSFW is up configs: j721e: Remove HBMC_AM654 config arm: dts: k3-j721e-r5: Clean up inclusion hierarchy arm: dts: k3-j721e: Sync with v6.6-rc1 .../k3-j721e-common-proc-board-u-boot.dtsi| 159 +-- arch/arm/dts/k3-j721e-common-proc-board.dts | 513 ++--- arch/arm/dts/k3-j721e-main.dtsi | 1018 +++-- arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 305 - .../k3-j721e-r5-common-proc-board-u-boot.dtsi | 29 - .../arm/dts/k3-j721e-r5-common-proc-board.dts | 384 +-- arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi | 31 - arch/arm/dts/k3-j721e-r5-sk.dts | 587 +- arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 180 +-- arch/arm/dts/k3-j721e-sk.dts | 673 +++ arch/arm/dts/k3-j721e-som-p0.dtsi | 217 ++-- arch/arm/dts/k3-j721e-thermal.dtsi| 75 ++ arch/arm/dts/k3-j721e.dtsi| 32 +- arch/arm/mach-k3/j721e/dev-data.c |1 + arch/arm/mach-k3/j721e_init.c | 24 +- configs/j721e_evm_a72_defconfig |1 - configs/j721e_evm_r5_defconfig|1 - drivers/firmware/ti_sci.c | 11 +- 18 files changed, 2407 insertions(+), 1834 deletions(-) delete mode 100644 arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi delete mode 100644 arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-j721e-thermal.dtsi -- 2.34.1
Re: image-host: small improvements and fixes.
On 27/09/2023 12:59, Hugo Cornelis wrote: > Yocto build can involve very long filenames. These two patches protect > the Yocto build from failing without a sensible error message and > increase the path length for the cipher key for the kernel from 128 to > 256 characters. > > For both patches: see the documentation on sending patches [1], particularly the section on commit message conventions. Your patches are missing 'Signed-off-by' lines at least. [1]: https://u-boot.readthedocs.io/en/latest/develop/sending_patches.html Thanks, Paul OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature Description: OpenPGP digital signature
[PATCH 2/2] board: dh_stm32mp1: Only print board code with CONFIG_SPL_DISPLAY_PRINT
Ensure that the SoM and board code information is only printed when
CONFIG_SPL_DISPLAY_PRINT is set.
Signed-off-by: Harald Seiler
---
board/dhelectronics/dh_stm32mp1/board.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/board/dhelectronics/dh_stm32mp1/board.c
b/board/dhelectronics/dh_stm32mp1/board.c
index f9cfabe2420..b933761d0de 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -229,8 +229,9 @@ static void board_get_coding_straps(void)
gpio_free_list_nodev(gpio, ret);
- printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
- somcode, ddr3code, brdcode);
+ if (CONFIG_IS_ENABLED(DISPLAY_PRINT))
+ printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
+ somcode, ddr3code, brdcode);
}
int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
--
2.41.0
[PATCH 1/2] ram: stm32mp1: Only print RAM config with CONFIG_SPL_DISPLAY_PRINT
Ensure that the RAM configuration line is only printed when
CONFIG_SPL_DISPLAY_PRINT is set.
Signed-off-by: Harald Seiler
---
drivers/ram/stm32mp1/stm32mp1_ram.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c
b/drivers/ram/stm32mp1/stm32mp1_ram.c
index a6c19af9722..2808d07c3ae 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ram.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -126,7 +126,8 @@ static int stm32mp1_ddr_setup(struct udevice *dev)
dev_dbg(dev, "no st,mem-name\n");
return -EINVAL;
}
- printf("RAM: %s\n", config.info.name);
+ if (CONFIG_IS_ENABLED(DISPLAY_PRINT))
+ printf("RAM: %s\n", config.info.name);
for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
ret = ofnode_read_u32_array(node, param[idx].name,
--
2.41.0
[PATCH 2/2] image-host: increase path length when setting up the cipher.
---
tools/image-host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/image-host.c b/tools/image-host.c
index 0c92a2ddeb..9afcc02192 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -361,7 +361,7 @@ static int fit_image_setup_cipher(struct image_cipher_info
*info,
int noffset)
{
char *algo_name;
- char filename[128];
+ char filename[256];
int ret = -1;
int snprintf_return;
--
2.34.1
[PATCH 1/2] image-host: add a check of the return value of snprintf.
---
tools/image-host.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/tools/image-host.c b/tools/image-host.c
index a6b0a94420..0c92a2ddeb 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -363,6 +363,7 @@ static int fit_image_setup_cipher(struct image_cipher_info
*info,
char *algo_name;
char filename[128];
int ret = -1;
+ int snprintf_return;
if (fit_image_cipher_get_algo(fit, noffset, _name)) {
printf("Can't get algo name for cipher in image '%s'\n",
@@ -399,8 +400,20 @@ static int fit_image_setup_cipher(struct image_cipher_info
*info,
}
/* Read the key in the file */
- snprintf(filename, sizeof(filename), "%s/%s%s",
+ snprintf_return = snprintf(filename, sizeof(filename), "%s/%s%s",
info->keydir, info->keyname, ".bin");
+ if (snprintf_return >= sizeof(filename))
+ {
+ printf("Can't format the key filename when setting up the
cipher: insufficient buffer space\n");
+ ret = -1;
+ goto out;
+ }
+ if (snprintf_return < 0)
+ {
+ printf("Can't format the key filename when setting up the
cipher: snprintf error\n");
+ ret = -1;
+ goto out;
+ }
info->key = malloc(info->cipher->key_len);
if (!info->key) {
printf("Can't allocate memory for key\n");
@@ -423,6 +436,18 @@ static int fit_image_setup_cipher(struct image_cipher_info
*info,
/* Read the IV in the file */
snprintf(filename, sizeof(filename), "%s/%s%s",
info->keydir, info->ivname, ".bin");
+ if (snprintf_return >= sizeof(filename))
+ {
+ printf("Can't format the IV filename when setting up
the cipher: insufficient buffer space\n");
+ ret = -1;
+ goto out;
+ }
+ if (snprintf_return < 0)
+ {
+ printf("Can't format the IV filename when setting up
the cipher: snprintf error\n");
+ ret = -1;
+ goto out;
+ }
ret = fit_image_read_data(filename, (unsigned char *)info->iv,
info->cipher->iv_len);
} else {
--
2.34.1
image-host: small improvements and fixes.
Yocto build can involve very long filenames. These two patches protect the Yocto build from failing without a sensible error message and increase the path length for the cipher key for the kernel from 128 to 256 characters.
[PATCH v2] test/py: sleep: Add a test for the time command
Execute "time ", and validate that it gives the approximately
the correct amount of command execution time.
Signed-off-by: Love Kumar
---
Changes in v2:
- Used @pytest.mark.buildconfigspec('')
---
test/py/tests/test_sleep.py | 18 ++
1 file changed, 18 insertions(+)
diff --git a/test/py/tests/test_sleep.py b/test/py/tests/test_sleep.py
index 392af29db224..66a57434bff7 100644
--- a/test/py/tests/test_sleep.py
+++ b/test/py/tests/test_sleep.py
@@ -41,3 +41,21 @@ def test_sleep(u_boot_console):
if not u_boot_console.config.gdbserver:
# margin is hopefully enough to account for any system overhead.
assert elapsed < (sleep_time + sleep_margin)
+
+@pytest.mark.buildconfigspec("cmd_misc")
+def test_time(u_boot_console):
+"""Test the time command, and validate that it gives approximately the
+correct amount of command execution time."""
+
+sleep_skip = u_boot_console.config.env.get("env__sleep_accurate", True)
+if not sleep_skip:
+pytest.skip("sleep is not accurate")
+
+sleep_time = u_boot_console.config.env.get("env__sleep_time", 10)
+sleep_margin = u_boot_console.config.env.get("env__sleep_margin", 0.25)
+output = u_boot_console.run_command("time sleep %d" % sleep_time)
+execute_time = float(output.split()[1])
+assert sleep_time >= (execute_time - 0.01)
+if not u_boot_console.config.gdbserver:
+# margin is hopefully enough to account for any system overhead.
+assert sleep_time < (execute_time + sleep_margin)
--
2.25.1
Re: [PATCH 0/2] arm: dts: k3-am64: Sync dts from Linux v6.6-rc1
On 15:01-20230927, Roger Quadros wrote: > Hi, > > This series aligns the dts files for AM64 platform from Linux v6.6-rc1. > > cheers, > -roger > > Roger Quadros (2): > Revert "ARM: dts: k3-am642-sk-u-boot: add PMIC node" > arm: dts: k3-am64: Bump dts from Linux v6.6-rc1 > > arch/arm/dts/k3-am64-main.dtsi| 209 ++ > arch/arm/dts/k3-am64-mcu.dtsi | 53 ++- > arch/arm/dts/k3-am64-thermal.dtsi | 33 > arch/arm/dts/k3-am64.dtsi | 22 +-- > arch/arm/dts/k3-am642-evm-u-boot.dtsi | 70 + > arch/arm/dts/k3-am642-evm.dts | 177 +- > arch/arm/dts/k3-am642-r5-evm.dts | 194 ++-- > arch/arm/dts/k3-am642-r5-sk.dts | 194 +--- > arch/arm/dts/k3-am642-sk-u-boot.dtsi | 122 --- > arch/arm/dts/k3-am642-sk.dts | 174 +++-- > arch/arm/dts/k3-am642.dtsi| 1 + > arch/arm/dts/k3-serdes.h | 204 + > 12 files changed, 815 insertions(+), 638 deletions(-) > create mode 100644 arch/arm/dts/k3-am64-thermal.dtsi > create mode 100644 arch/arm/dts/k3-serdes.h > > > base-commit: 4cb31a9f3560b293670de95e76c1f3cf2f9e1ca8 > -- > 2.34.1 > https://lore.kernel.org/u-boot/20230911144401.1011354-1...@ti.com/ https://github.com/u-boot/u-boot/commits/next?after=90c81f407dd4a7747385b10f9b8f732202c45cde+104=next_name=refs%2Fheads%2Fnext Can you send delta patches based off u-boot next? -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
[PATCH 2/2] arm: dts: k3-am64: Bump dts from Linux v6.6-rc1
Update the am64 and am642 device-trees from linux v6.6-rc1.
This needed the following tweaks to the u-boot specific dtsi as well:
- Switch tick-timer to the main_timer as it's now defined in the main dtsi
- Secure proxies are defined in SoC dtsi
- Drop duplicate nodes - u-boot.dtsi is included in r5-*.dts, no need for
either the definitions from main.dtsi OR duplication from u-boot.dtsi
- deal with both am642-evm and am642-sk
Signed-off-by: Roger Quadros
---
arch/arm/dts/k3-am64-main.dtsi| 209 ++
arch/arm/dts/k3-am64-mcu.dtsi | 53 ++-
arch/arm/dts/k3-am64-thermal.dtsi | 33
arch/arm/dts/k3-am64.dtsi | 22 +--
arch/arm/dts/k3-am642-evm-u-boot.dtsi | 70 +
arch/arm/dts/k3-am642-evm.dts | 177 +-
arch/arm/dts/k3-am642-r5-evm.dts | 194 ++--
arch/arm/dts/k3-am642-r5-sk.dts | 194 +---
arch/arm/dts/k3-am642-sk-u-boot.dtsi | 61
arch/arm/dts/k3-am642-sk.dts | 174 +++--
arch/arm/dts/k3-am642.dtsi| 1 +
arch/arm/dts/k3-serdes.h | 204 +
12 files changed, 815 insertions(+), 577 deletions(-)
create mode 100644 arch/arm/dts/k3-am64-thermal.dtsi
create mode 100644 arch/arm/dts/k3-serdes.h
diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
index 5e8036f32d..0df54a7418 100644
--- a/arch/arm/dts/k3-am64-main.dtsi
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -44,11 +44,28 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x4300 0x2>;
+ chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x0014 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
};
+
+ phy_gmii_sel: phy@4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
+
+ epwm_tbclk: clock-controller@4140 {
+ compatible = "ti,am64-epwm-tbclk";
+ reg = <0x4130 0x4>;
+ #clock-cells = <1>;
+ };
};
gic500: interrupt-controller@180 {
@@ -203,29 +220,154 @@
pinctrl-single,function-mask = <0x>;
};
- main_conf: syscon@4300 {
- compatible = "syscon", "simple-mfd";
- reg = <0x00 0x4300 0x00 0x2>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00 0x00 0x4300 0x2>;
+ main_timer0: timer@240 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x240 0x00 0x400>;
+ interrupts = ;
+ clocks = <_clks 36 1>;
+ clock-names = "fck";
+ assigned-clocks = <_clks 36 1>;
+ assigned-clock-parents = <_clks 36 2>;
+ power-domains = <_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
- chipid@14 {
- compatible = "ti,am654-chipid";
- reg = <0x0014 0x4>;
- };
+ main_timer1: timer@241 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x241 0x00 0x400>;
+ interrupts = ;
+ clocks = <_clks 37 1>;
+ clock-names = "fck";
+ assigned-clocks = <_clks 37 1>;
+ assigned-clock-parents = <_clks 37 2>;
+ power-domains = <_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
- phy_gmii_sel: phy@4044 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x4044 0x8>;
- #phy-cells = <1>;
- };
+ main_timer2: timer@242 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x242 0x00 0x400>;
+ interrupts = ;
+ clocks = <_clks 38 1>;
+ clock-names = "fck";
+ assigned-clocks = <_clks 38 1>;
+ assigned-clock-parents = <_clks 38 2>;
+ power-domains = <_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
- epwm_tbclk: clock@4140 {
- compatible = "ti,am64-epwm-tbclk", "syscon";
- reg = <0x4130 0x4>;
- #clock-cells = <1>;
- };
+ main_timer3: timer@243 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x243 0x00 0x400>;
+
[PATCH 1/2] Revert "ARM: dts: k3-am642-sk-u-boot: add PMIC node"
This reverts commit 28a4c3113445d4400639f357fae0def007a41093.
The PMIC should come from the k3-am642-sk.dts file.
There are 2 variants of the AM642-SK board and each has a different PMIC.
i.e. SK-AM64 [1] has TPS6521855 and SK-AM64B [2] has TPS6522053.
[1] - https://www.ti.com/tool/SK-AM64
[2] - https://www.ti.com/tool/SK-AM64B
Signed-off-by: Roger Quadros
---
arch/arm/dts/k3-am642-sk-u-boot.dtsi | 61
1 file changed, 61 deletions(-)
diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi
b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
index 3d6be025bd..4431750dc6 100644
--- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
@@ -54,67 +54,6 @@
pinctrl-names = "default";
pinctrl-0 = <_i2c0_pins_default>;
clock-frequency = <40>;
-
- tps65219: pmic@30 {
- compatible = "ti,tps65219";
- reg = <0x30>;
-
- regulators {
- buck1_reg: buck1 {
- regulator-name = "VDD_CORE";
- regulator-min-microvolt = <75>;
- regulator-max-microvolt = <75>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck2_reg: buck2 {
- regulator-name = "VCC1V8";
- regulator-min-microvolt = <180>;
- regulator-max-microvolt = <180>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck3_reg: buck3 {
- regulator-name = "VDD_LPDDR4";
- regulator-min-microvolt = <110>;
- regulator-max-microvolt = <110>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- regulator-name = "VDDSHV_SD_IO_PMIC";
- regulator-min-microvolt = <3300>;
- regulator-max-microvolt = <3300>;
- };
-
- ldo2_reg: ldo2 {
- regulator-name = "VDDAR_CORE";
- regulator-min-microvolt = <85>;
- regulator-max-microvolt = <85>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3_reg: ldo3 {
- regulator-name = "VDDA_1V8";
- regulator-min-microvolt = <1800>;
- regulator-max-microvolt = <1800>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4_reg: ldo4 {
- regulator-name = "VDD_PHY_2V5";
- regulator-min-microvolt = <2500>;
- regulator-max-microvolt = <2500>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
};
_uart0 {
--
2.34.1
[PATCH 0/2] arm: dts: k3-am64: Sync dts from Linux v6.6-rc1
Hi, This series aligns the dts files for AM64 platform from Linux v6.6-rc1. cheers, -roger Roger Quadros (2): Revert "ARM: dts: k3-am642-sk-u-boot: add PMIC node" arm: dts: k3-am64: Bump dts from Linux v6.6-rc1 arch/arm/dts/k3-am64-main.dtsi| 209 ++ arch/arm/dts/k3-am64-mcu.dtsi | 53 ++- arch/arm/dts/k3-am64-thermal.dtsi | 33 arch/arm/dts/k3-am64.dtsi | 22 +-- arch/arm/dts/k3-am642-evm-u-boot.dtsi | 70 + arch/arm/dts/k3-am642-evm.dts | 177 +- arch/arm/dts/k3-am642-r5-evm.dts | 194 ++-- arch/arm/dts/k3-am642-r5-sk.dts | 194 +--- arch/arm/dts/k3-am642-sk-u-boot.dtsi | 122 --- arch/arm/dts/k3-am642-sk.dts | 174 +++-- arch/arm/dts/k3-am642.dtsi| 1 + arch/arm/dts/k3-serdes.h | 204 + 12 files changed, 815 insertions(+), 638 deletions(-) create mode 100644 arch/arm/dts/k3-am64-thermal.dtsi create mode 100644 arch/arm/dts/k3-serdes.h base-commit: 4cb31a9f3560b293670de95e76c1f3cf2f9e1ca8 -- 2.34.1
Re: [PATCH 0/4] Add AM62x LP SK support
On 13:51-20230927, Nitin Yadav wrote: > This series adds support of AM62x LP SK. The AM62x LP SK board > is similar to AM62x SK but has some significant changes that > requires different set of device tree at each stage of bootloader. > Also refactors to have common nodes at k3-am62x-r5-sk-common.dtsi > and k3-am62x-sk-common-u-boot.dtsi for all am62x SoC varients. > > Nitin Yadav (4): > arm: dts: Refactor common dtsi file for R5 and A53 SPL > arm: dts: Add support for AM62x LP SK > arm: dts: k3-am62-lp-sk-binman: Add binman support > board: ti: am62x: add am62x_lpsk_* defconfigs and env files > > arch/arm/dts/Makefile |2 + > arch/arm/dts/k3-am62-lp-sk-binman.dtsi| 29 + > arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi|9 + > arch/arm/dts/k3-am62-lp-sk.dts| 231 ++ > arch/arm/dts/k3-am62-r5-lp-sk.dts | 21 + > arch/arm/dts/k3-am625-r5-sk.dts | 94 +- > arch/arm/dts/k3-am625-sk-u-boot.dtsi | 110 +- > arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi | 2190 + > arch/arm/dts/k3-am62x-r5-sk-common.dtsi | 96 + > arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi | 109 + > board/ti/am62x/am62x_lpsk_a53.config |5 + > board/ti/am62x/am62x_lpsk_r5.config |5 + > board/ti/am62x/am62xlpsk.env | 21 + > 13 files changed, 2724 insertions(+), 198 deletions(-) > create mode 100644 arch/arm/dts/k3-am62-lp-sk-binman.dtsi > create mode 100644 arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi > create mode 100644 arch/arm/dts/k3-am62-lp-sk.dts > create mode 100644 arch/arm/dts/k3-am62-r5-lp-sk.dts > create mode 100644 arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi > create mode 100644 arch/arm/dts/k3-am62x-r5-sk-common.dtsi > create mode 100644 arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi > create mode 100644 board/ti/am62x/am62x_lpsk_a53.config > create mode 100644 board/ti/am62x/am62x_lpsk_r5.config > create mode 100644 board/ti/am62x/am62xlpsk.env > Board documentation missing! -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Re: [PATCH 1/4] arm: dts: Refactor common dtsi file for R5 and A53 SPL
On 13:51-20230927, Nitin Yadav wrote: > Add k3-am62x-r5-sk-common to include nodes common for R5 > SPL from k3-am625-r5-sk for AM62x SoC based boards. Add > k3-am62x-sk-common-u-boot to move common nodes of A53 SPL > stage from k3-am625-sk-u-boot. > > Signed-off-by: Nitin Yadav > --- [...] > +#include "k3-am625-sk-binman.dtsi" Might be a good time to refactor and squash sk-binman.dtsi to u-boot.dtsi ? [...] -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Re: [PATCH 4/4] board: ti: am62x: add am62x_lpsk_* defconfigs and env files
On 13:51-20230927, Nitin Yadav wrote:
> Add defconfig fragments for AM62x LP SK and corresponding
> customized environment file for AM62x LP SK.
>
> Signed-off-by: Nitin Yadav
> ---
> board/ti/am62x/am62x_lpsk_a53.config | 5 +
> board/ti/am62x/am62x_lpsk_r5.config | 5 +
> board/ti/am62x/am62xlpsk.env | 21 +
> 3 files changed, 31 insertions(+)
> create mode 100644 board/ti/am62x/am62x_lpsk_a53.config
> create mode 100644 board/ti/am62x/am62x_lpsk_r5.config
> create mode 100644 board/ti/am62x/am62xlpsk.env
>
> diff --git a/board/ti/am62x/am62x_lpsk_a53.config
> b/board/ti/am62x/am62x_lpsk_a53.config
> new file mode 100644
> index 00..a568324997
> --- /dev/null
> +++ b/board/ti/am62x/am62x_lpsk_a53.config
> @@ -0,0 +1,5 @@
> +# Defconfig fragment to apply on top of am62x_evm_a53_defconfig
> +
> +CONFIG_DEFAULT_DEVICE_TREE="k3-am62-lp-sk"
> +CONFIG_SPL_OF_LIST="k3-am62-lp-sk"
> +CONFIG_OF_LIST="k3-am62-lp-sk"
> diff --git a/board/ti/am62x/am62x_lpsk_r5.config
> b/board/ti/am62x/am62x_lpsk_r5.config
> new file mode 100644
> index 00..1532f4e336
> --- /dev/null
> +++ b/board/ti/am62x/am62x_lpsk_r5.config
> @@ -0,0 +1,5 @@
> +# Defconfig fragment to apply on top of am62x_evm_r5_defconfig
> +
> +CONFIG_DEFAULT_DEVICE_TREE="k3-am62-r5-lp-sk"
> +CONFIG_SPL_OF_LIST="k3-am62-r5-lp-sk"
> +CONFIG_OF_LIST="k3-am62-r5-lp-sk"
> diff --git a/board/ti/am62x/am62xlpsk.env b/board/ti/am62x/am62xlpsk.env
> new file mode 100644
> index 00..3b79ae1b3f
> --- /dev/null
> +++ b/board/ti/am62x/am62xlpsk.env
> @@ -0,0 +1,21 @@
> +#include
> +#include
> +#include
> +
> +name_kern=Image
> +console=ttyS2,115200n8
> +args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x0280
> + ${mtdparts}
> +run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
> +
> +boot_targets=ti_mmc mmc0 mmc1 usb pxe dhcp
> +boot=mmc
> +mmcdev=1
> +bootpart=1:2
> +bootdir=/boot
> +rd_spec=-
> +
> +splashfile=ti.gz
> +splashimage=0x8020
> +splashpos=m,m
> +splashsource=sf
Why dont we use the am62.env ? What is here to customize?
> --
> 2.25.1
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5
849D 1736 249D
Re: [PATCH 3/4] arm: dts: k3-am62-lp-sk-binman: Add binman support
On 13:51-20230927, Nitin Yadav wrote:
> Switch to binman for building bootloader images. Reuse
> k3-am625-sk-binman and override the dtb names to that
> of AM62 LP SK board.
>
> Signed-off-by: Nitin Yadav
> ---
> arch/arm/dts/k3-am62-lp-sk-binman.dtsi | 29 ++
> 1 file changed, 29 insertions(+)
> create mode 100644 arch/arm/dts/k3-am62-lp-sk-binman.dtsi
>
> diff --git a/arch/arm/dts/k3-am62-lp-sk-binman.dtsi
> b/arch/arm/dts/k3-am62-lp-sk-binman.dtsi
> new file mode 100644
> index 00..6841bea118
> --- /dev/null
> +++ b/arch/arm/dts/k3-am62-lp-sk-binman.dtsi
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#include "k3-am625-sk-binman.dtsi"
> +
> +#ifdef CONFIG_TARGET_AM625_A53_EVM
> +
> +#define SPL_AM62_LP_SK_DTB "spl/dts/k3-am62-lp-sk.dtb"
> +#define AM62_LP_SK_DTB "u-boot.dtb"
> +
> +_am625_sk_dtb_unsigned {
> + filename = SPL_AM62_LP_SK_DTB;
> +};
> +
> +_sk_dtb_unsigned {
> + filename = AM62_LP_SK_DTB;
> +};
> +
> +_am625_sk_dtb {
> + filename = SPL_AM62_LP_SK_DTB;
> +};
> +
> +_sk_dtb {
> + filename = AM62_LP_SK_DTB;
> +};
> +
> +#endif
> --
> 2.25.1
>
Squash this to the u-boot.dtsi ?
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5
849D 1736 249D
Re: [PATCH 2/4] arm: dts: Add support for AM62x LP SK
On 13:51-20230927, Nitin Yadav wrote:
> The AM62x LP SK board is similar to the AM62x SK board,
> but has some significant changes that requires different
> device tree.
>
> The differences are mainly:
> - AM62x SoC in the AMC package that meets AECQ100 automotive standard.
> - LPDDR4 versus DDR4 on the AM62x SK.
> - TPS65219 PMIC instead of discrete regulators.
> - IO expander pin names are wired differently.
> - Second ethernet port is currently disabled as the boards do not have
> the part physically installed.
> - OSPI NAND vs OSPI NOR.
> - No WLAN chip instead a SDIO M.2 connector.
>
> Signed-off-by: Nitin Yadav
> ---
> arch/arm/dts/Makefile |2 +
> arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi|9 +
> arch/arm/dts/k3-am62-lp-sk.dts| 231 ++
> arch/arm/dts/k3-am62-r5-lp-sk.dts | 21 +
> arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi | 2190 +
> 5 files changed, 2453 insertions(+)
> create mode 100644 arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
> create mode 100644 arch/arm/dts/k3-am62-lp-sk.dts
> create mode 100644 arch/arm/dts/k3-am62-r5-lp-sk.dts
> create mode 100644 arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index bde2176ec7..72ea57885f 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1337,6 +1337,8 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
>
> dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
> k3-am625-r5-sk.dtb \
> + k3-am62-lp-sk.dtb \
> + k3-am62-r5-lp-sk.dtb \
> k3-am625-beagleplay.dtb \
> k3-am625-r5-beagleplay.dtb \
> k3-am625-verdin-wifi-dev.dtb \
> diff --git a/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
> b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
> new file mode 100644
> index 00..7da94fe4b6
> --- /dev/null
> +++ b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
> @@ -0,0 +1,9 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * AM62x LP SK dts file for SPLs
> + * Copyright (C) 2021-2023 Texas Instruments Incorporated -
> https://www.ti.com/
> + */
> +
> +#include "k3-am62x-sk-common-u-boot.dtsi"
> +
> +#include "k3-am62-lp-sk-binman.dtsi"
Are you sure you don't need the dt phase properties for regulators for
mmc to work?
> diff --git a/arch/arm/dts/k3-am62-lp-sk.dts b/arch/arm/dts/k3-am62-lp-sk.dts
Is this coming in from v6.6-rc1 if so document that in commit message.
[...]
> diff --git a/arch/arm/dts/k3-am62-r5-lp-sk.dts
> b/arch/arm/dts/k3-am62-r5-lp-sk.dts
> new file mode 100644
> index 00..ed2c028bad
> --- /dev/null
> +++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * AM62x LP SK dts file for R5 SPL
> + * Copyright (C) 2021-2023 Texas Instruments Incorporated -
> https://www.ti.com/
> + */
> +
> +#include "k3-am62-lp-sk.dts"
> +#include "k3-am62x-ddr-lp4-50-800-800.dtsi"
> +#include "k3-am62-ddr.dtsi"
> +
> +#include "k3-am62-lp-sk-u-boot.dtsi"
> +#include "k3-am62x-r5-sk-common.dtsi"
> +
> +/ {
> + memory@8000 {
> + device_type = "memory";
> + /* 2G RAM */
> + reg = <0x 0x8000 0x 0x8000>;
> + bootph-pre-ram;
> + };
> +};
NAK. should come from board.dts.
> diff --git a/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi
> b/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi
> new file mode 100644
> index 00..74693d12e1
> --- /dev/null
> +++ b/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi
> @@ -0,0 +1,2190 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * This file was generated with the
> + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.61
> + * Tue Mar 22 2022 17:03:08 GMT-0500 (Central Daylight Time)
Are you sure this does'nt need a sync up to latest?
> + * DDR Type: LPDDR4
Would be good to document the exact DDR part.
> + * F0 = 50MHzF1 = 800MHzF2 = 800MHz
> + * Density (per channel): 16Gb
> + * Number of Ranks: 1
> + */
> +
[...]
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5
849D 1736 249D
Re: [PATCH 2/5] iot2050: rename overlay sources to .dtso
On 25.09.23 10:09, Rasmus Villemoes wrote:
> Distinguish more clearly between source files meant for producing .dtb
> from those meant for producing .dtbo. No functional change, as we
> currently have rules for producing a foo.dtbo from either foo.dts or
> foo.dtso.
>
> Note that in the linux tree, all device tree overlay sources have been
> renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit
> 81d362732bac). So this is also a step towards staying closer to linux
> with respect to both Kbuild and device tree sources.
>
> Signed-off-by: Rasmus Villemoes
> ---
> ... => k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso} | 0
> ...y.dts => k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso} | 0
> 2 files changed, 0 insertions(+), 0 deletions(-)
> rename
> arch/arm/dts/{k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts =>
> k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso} (100%)
> rename arch/arm/dts/{k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts =>
> k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso} (100%)
>
> diff --git
> a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts
> b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso
> similarity index 100%
> rename from
> arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts
> rename to
> arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso
> diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts
> b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso
> similarity index 100%
> rename from arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts
> rename to arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso
Reviewed-by: Jan Kiszka
Jan
--
Siemens AG, Technology
Linux Expert Center
Re: Enable thumb on AT91?
On 9/27/23 01:15, Sean Anderson wrote: Hi Eugen, I noticed that several AT91 boards are quite close to their SPL size limit. For example, sama5d27_wlsom1_ek_mmc is just 173 bytes short of its limit and doesn't even git with older GCCs. I looked at the datasheet for that processor, and noticed that it has thumb support. Have you considered enabling SYS_THUMB_BUILD? This shrinks SPL by around 30%. I don't have a board to test with, so I don't know if there are any technical reasons blocking this. --Sean Hello Sean, Thumb should be fine for the AT91 architecture. + Nicolas and Aubin in CC. The change would require testing. Eugen
Re: [RESEND PATCH v2] rockchip: include: asm: fix entering download mode rk3066
Hi Johan,
On 2023/9/19 23:28, Johan Jonker wrote:
Keep track of the re-entries with help of the lr register.
This binary can be re-used and called from various BROM functions.
Only when it's called from the part that handles SPI, NAND or EMMC
hardware it needs to early return to BROM ones.
In download mode when it handles data on USB OTG and UART0
this section must be skipped.
Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in
support to enter download mode on return to BROM. This binary must check
the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set.
It then returns to BROM to the end of the function that reads boot blocks.
>From there the BROM code goes into a download mode and waits for data
on USB OTG and UART0.
Signed-off-by: Johan Jonker
---
Note:
Normal boot flow is OK.
In download mode this binary hangs after return to BROM for unknown reasons.
Basically do not touch the stack area of Bootrom and no more other
requirement.
The bootrom download mode is usually used for boards without any
available firmware.
If there is available firmware, it'd be better to enable download
feature in U-Boot.
Thanks,
- Kever
Replace CODE471_OPTION with 30_LPDDR2_300MHz_DD.bin for now.
Could Rockchip disclose what further conditions must be met
in rk3066 download mode?
Changed V2:
Move file to rk3066 specific location
Replace retry_counter by LR check
Add DNL mode return address
Restyle
Reword
---
arch/arm/include/asm/arch-rk3066/boot0.h | 77 +++-
arch/arm/mach-rockchip/Kconfig | 17 +-
arch/arm/mach-rockchip/rk3066/Kconfig| 6 ++
3 files changed, 98 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h
b/arch/arm/include/asm/arch-rk3066/boot0.h
index 28c0fb9a4c6b..1af4b9c1d7ba 100644
--- a/arch/arm/include/asm/arch-rk3066/boot0.h
+++ b/arch/arm/include/asm/arch-rk3066/boot0.h
@@ -3,6 +3,81 @@
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
-#include
+#include
+/*
+ * Execution starts on the instruction following this 4-byte header
+ * (containing the magic 'RK30'). This magic constant will be written into
+ * the final image by the rkimage tool, but we need to reserve space for it
here.
+ */
+#ifdef CONFIG_SPL_BUILD
+ b 1f /* if overwritten, entry-address is at the next word */
+1:
+#endif
+
+#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
+/*
+ * Keep track of the re-entries with help of the lr register.
+ * This binary can be re-used and called from various BROM functions.
+ * Only when it's called from the part that handles SPI, NAND or EMMC
+ * hardware it needs to early return to BROM ones.
+ * In download mode when it handles data on USB OTG and UART0
+ * this section must be skipped.
+ */
+ ldr r3, =CONFIG_ROCKCHIP_BOOT_LR_REG
+ cmp lr, r3 /* if (LR != CONFIG_ROCKCHIP_BOOT_LR_REG)
*/
+ bne reset /* goto reset;
*/
+/*
+ * Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in
+ * support to enter download mode on return to BROM. This binary must check
+ * the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's
set.
+ * It then returns to BROM to the end of the function that reads boot blocks.
+ * From there the BROM code goes into a download mode and waits for data
+ * on USB OTG and UART0.
+ */
+ ldr r2, =BOOT_BROM_DOWNLOAD
+ ldr r3, =CONFIG_ROCKCHIP_BOOT_MODE_REG
+ ldr r0, [r3]/* if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) !=
*/
+ cmp r0, r2 /* BOOT_BROM_DOWNLOAD) {
*/
+ bne early_return/* goto early_return;
*/
+ /* } else {
*/
+ mov r0, #0
+ str r0, [r3]/* writel(0,
CONFIG_ROCKCHIP_BOOT_MODE_REG); */
+
+ ldr r3, =CONFIG_ROCKCHIP_BOOT_RETURN_REG
+ bx r3 /* return to
CONFIG_ROCKCHIP_BOOT_RETURN_REG;*/
+
+early_return:
+ bx lr /* return to LR in BROM
*/
+
+SAVE_SP_ADDR:
+ .word 0
+
+ .globl save_boot_params
+save_boot_params:
+ push{r1-r12, lr}
+ ldr r0, =SAVE_SP_ADDR
+ str sp, [r0]
+ b save_boot_params_ret
+
+ .globl back_to_bootrom
+back_to_bootrom:
+ ldr r0, =SAVE_SP_ADDR
+ ldr sp, [r0]
+ mov r0, #0
+ pop {r1-r12, pc}
+#endif
+
+#if (defined(CONFIG_SPL_BUILD))
+/* U-Boot proper of armv7 does not need this */
+ b reset
+#endif
+
+/*
+ * For armv7, the addr '_start' will be used as vector start address
+ * and is written to the VBAR register, which needs to aligned to 0x20.
+ */
+ .align(5), 0x0
+_start:
+ ARM_VECTORS
#endif
diff --git
[PATCH] arm64: xilinx: Do not use '_' in si5335 DT node names
Character '_' not recommended in node name. Use '-' instead.
Pretty much run sed below for node names.
s/si5335_/si5335-/
Signed-off-by: Michal Simek
---
Till now I didn't heard back that different style should be used that's why
also sending this patch and separately from other similar change recently
sent.
---
arch/arm/dts/zynqmp-zcu100-revC.dts | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts
b/arch/arm/dts/zynqmp-zcu100-revC.dts
index a84cd86694e2..44d1b24677d1 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU100 revC
*
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek
* Nathalie Chan King Choy
@@ -131,13 +132,13 @@
io-channels = < 0>, < 1>, < 2>, < 3>;
};
- si5335_0: si5335_0 { /* clk0_usb - u23 */
+ si5335_0: si5335-0 { /* clk0_usb - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2600>;
};
- si5335_1: si5335_1 { /* clk1_dp - u23 */
+ si5335_1: si5335-1 { /* clk1_dp - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2700>;
--
2.36.1
[PATCH] Revert "clk: versal: Enable clock driver for Versal NET"
This partially reverts commit ff33227819f579ffb963e0dac6bc6a6566b89563.
Versal NET clock node should use "xlnx,versal-net-clk", "xlnx,versal-clk"
compatible string that's why it is not necessary to define Versal NET
specific compatible string if there is no any other change needed. It can
be get back if there is a need to differentiate clock support between
Versal and Versal NET.
Signed-off-by: Michal Simek
---
drivers/clk/clk_versal.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index 2e004beca2f9..c473643603a4 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -773,7 +773,6 @@ static struct clk_ops versal_clk_ops = {
static const struct udevice_id versal_clk_ids[] = {
{ .compatible = "xlnx,versal-clk" },
- { .compatible = "xlnx,versal-net-clk" },
{ }
};
--
2.36.1
Re: sunxi: introduce NCAT2 generation model
On Wed, 27 Sep 2023 12:42:52 +0300 Okhunjon Sobirjonov wrote: Hi, > When NCAT2 generation model's introduced for t113, > the modification in drivers/mmc/sunxi_mmc.c > > + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) && (sdc_no == 2)) > in struct mmc *sunxi_mmc_init(int sdc_no) seems to have > some negative side effects, meaning enabling 8-bit mode for MMC2. "Some negative side effects" sounds cute, but it actually breaks it ;-) > Paticularly, IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) > should not be used for D1/T113 > since there is not support for 8-bit mode for MMC2 yet. > Therefore, the solution would be to drop this particular > change entirely. So yeah, that line is just plain wrong, it seems like all the NCAT SoCs we have seen (D1/T113/R329) do no support 8-bit eMMC. So thanks for the heads up, I will remove that line from v2. > Signed-off-by: Okhunjon Sobirjonov S-o-b:'s are only needed for actual patch submissions, not for comments on the list. Cheers, Andre
[PATCH] arm64: zynqmp: Do not use '_' in DT node names
Using '_' is not recommended for node names. Use '-' instead.
Pretty much run seds below for node names.
s/heartbeat_led/heartbeat-led/
s/gtr_sel/gtr-sel/
s/zynqmp_ipi/zynqmp-ipi/
s/nvmem_firmware/nvmem-firmware/
s/soc_revision/soc-revision/
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 8
arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 8
arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 8
arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 8
arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +-
arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +-
arch/arm/dts/zynqmp.dtsi| 6 +++---
7 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index cfd5ba1aac63..25ef646c8466 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -363,25 +363,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3",
"sw4_4",
"", "", "", "";
- gtr_sel0 {
+ gtr-sel0 {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr_sel1 {
+ gtr-sel1 {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr_sel2 {
+ gtr-sel2 {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr_sel3 {
+ gtr-sel3 {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index 18e14389f85f..ece9e6914541 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -365,25 +365,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3",
"sw4_4",
"", "", "", "";
- gtr_sel0 {
+ gtr-sel0 {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr_sel1 {
+ gtr-sel1 {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr_sel2 {
+ gtr-sel2 {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr_sel3 {
+ gtr-sel3 {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index cd7654a9f7ed..7372968e5734 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -359,25 +359,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3",
"sw4_4",
"", "", "", "";
- gtr_sel0 {
+ gtr-sel0 {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
[PATCH] arm: dts: xilinx: Remove undocumented is-dual property
Xilinx was using in past is-dual property for QSPIs to reflect their
configurations. But handling for them never reached upstream code that's
why better to remove them.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynq-cc108.dts | 1 -
arch/arm/dts/zynq-dlc20-rev1.0.dts| 1 -
arch/arm/dts/zynq-minized.dts | 1 -
arch/arm/dts/zynq-topic-miami.dts | 1 -
arch/arm/dts/zynq-topic-miamilite.dts | 1 -
arch/arm/dts/zynq-topic-miamiplus.dts | 1 -
arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 1 -
arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 1 -
arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 1 -
arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts | 2 --
arch/arm/dts/zynqmp-zcu102-revA.dts | 1 -
arch/arm/dts/zynqmp-zcu106-revA.dts | 1 -
arch/arm/dts/zynqmp-zcu111-revA.dts | 1 -
arch/arm/dts/zynqmp-zcu208-revA.dts | 1 -
arch/arm/dts/zynqmp-zcu216-revA.dts | 1 -
15 files changed, 16 deletions(-)
diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts
index dc942b0f595e..593ca4a49cf5 100644
--- a/arch/arm/dts/zynq-cc108.dts
+++ b/arch/arm/dts/zynq-cc108.dts
@@ -55,7 +55,6 @@
{
status = "okay";
- is-dual = <0>;
num-cs = <1>;
flash@0 { /* 16 MB */
compatible = "n25q128a11", "jedec,spi-nor";
diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts
b/arch/arm/dts/zynq-dlc20-rev1.0.dts
index d06838c5eeb3..8d0073780336 100644
--- a/arch/arm/dts/zynq-dlc20-rev1.0.dts
+++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts
@@ -66,7 +66,6 @@
{
bootph-all;
status = "okay";
- is-dual = <0>;
num-cs = <1>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts
index 3214ee49e283..96d2937de8bf 100644
--- a/arch/arm/dts/zynq-minized.dts
+++ b/arch/arm/dts/zynq-minized.dts
@@ -39,7 +39,6 @@
{
status = "okay";
- is-dual = <0>;
num-cs = <1>;
flash@0 {
compatible = "micron,m25p128";
diff --git a/arch/arm/dts/zynq-topic-miami.dts
b/arch/arm/dts/zynq-topic-miami.dts
index 57cb86aafd29..8307a2ef9dd3 100644
--- a/arch/arm/dts/zynq-topic-miami.dts
+++ b/arch/arm/dts/zynq-topic-miami.dts
@@ -33,7 +33,6 @@
{
bootph-all;
status = "okay";
- is-dual = <0>;
num-cs = <1>;
flash@0 {
compatible = "st,m25p80", "n25q256a", "jedec,spi-nor";
diff --git a/arch/arm/dts/zynq-topic-miamilite.dts
b/arch/arm/dts/zynq-topic-miamilite.dts
index 366fd5bbb100..af0bc7ecf700 100644
--- a/arch/arm/dts/zynq-topic-miamilite.dts
+++ b/arch/arm/dts/zynq-topic-miamilite.dts
@@ -12,5 +12,4 @@
};
{
- is-dual = <1>;
};
diff --git a/arch/arm/dts/zynq-topic-miamiplus.dts
b/arch/arm/dts/zynq-topic-miamiplus.dts
index df538865296d..36a7db355e5b 100644
--- a/arch/arm/dts/zynq-topic-miamiplus.dts
+++ b/arch/arm/dts/zynq-topic-miamiplus.dts
@@ -21,5 +21,4 @@
};
{
- is-dual = <1>;
};
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index 2c3e30ba8916..cfd5ba1aac63 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -71,7 +71,6 @@
{
status = "okay";
- is-dual = <1>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index ad724a135872..18e14389f85f 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -67,7 +67,6 @@
{
status = "okay";
- is-dual = <1>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index 296af0426ee2..cd7654a9f7ed 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -67,7 +67,6 @@
{
status = "okay";
- is-dual = <1>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
index 3750bb38b585..0d96c6f9f041 100644
--- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
+++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
@@ -56,7 +56,6 @@
{
status = "okay";
- is-dual = <1>;
flash@0 {
compatible = "st,m25p80", "n25q256a", "jedec,spi-nor";
m25p,fast-read;
@@ -66,7 +65,6 @@
[PATCH 11/11] arm64: zynqmp: Add support for zcu670-revB
RevB has different SD level shifter compare to revA. There are couple of
changes between revisions but none of them requires SW alignment.
Signed-off-by: Michal Simek
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-zcu670-revB.dts | 672
2 files changed, 673 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-zcu670-revB.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4c31a923aebc..fa65821ff475 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -448,6 +448,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu208-revA.dtb \
zynqmp-zcu216-revA.dtb \
zynqmp-zcu670-revA.dtb \
+ zynqmp-zcu670-revB.dtb \
zynqmp-zc1232-revA.dtb \
zynqmp-zc1254-revA.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts
b/arch/arm/dts/zynqmp-zcu670-revB.dts
new file mode 100644
index ..97599c5658fb
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu670-revB.dts
@@ -0,0 +1,672 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP ZCU670 (67DR) revB
+ *
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include
+#include
+#include
+#include
+
+/ {
+ model = "ZynqMP ZCU670 RevB";
+ compatible = "xlnx,zynqmp-zcu670-revB", "xlnx,zynqmp-zcu670",
+"xlnx,zynqmp";
+
+ aliases {
+ ethernet0 =
+ i2c0 =
+ i2c1 =
+ mmc0 =
+ nvmem0 =
+ rtc0 =
+ serial0 =
+ serial1 =
+ spi0 =
+ usb0 =
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0 0x8000>, <0x8 0x0 0x0 0x8000>;
+ /* Another 4GB connected to PL */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ sw1 {
+ label = "sw1";
+ gpios = < 22 GPIO_ACTIVE_HIGH>;
+ linux,code = ;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat-led {
+ label = "heartbeat"; /* DS1 */
+ gpios = < 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ ina226-vccint {
+ compatible = "iio-hwmon";
+ io-channels = < 0>, < 1>, < 2>, <
3>;
+ };
+ ina226-vccint-io-bram-ps {
+ compatible = "iio-hwmon";
+ io-channels = <_io_bram_ps 0>, <_io_bram_ps 1>,
<_io_bram_ps 2>, <_io_bram_ps 3>;
+ };
+ ina226-vcc1v8 {
+ compatible = "iio-hwmon";
+ io-channels = < 0>, < 1>, < 2>, <
3>;
+ };
+ ina226-vcc1v2 {
+ compatible = "iio-hwmon";
+ io-channels = < 0>, < 1>, < 2>, <
3>;
+ };
+ ina226-vadj-fmc {
+ compatible = "iio-hwmon";
+ io-channels = <_fmc 0>, <_fmc 1>, <_fmc 2>,
<_fmc 3>;
+ };
+ ina226-mgtavcc {
+ compatible = "iio-hwmon";
+ io-channels = < 0>, < 1>, < 2>,
< 3>;
+ };
+ ina226-mgt1v2 {
+ compatible = "iio-hwmon";
+ io-channels = < 0>, < 1>, < 2>, <
3>;
+ };
+ ina226-mgt1v8 {
+ compatible = "iio-hwmon";
+ io-channels = < 0>, < 1>, < 2>, <
3>;
+ };
+ ina226-vccint-ams {
+ compatible = "iio-hwmon";
+ io-channels = <_ams 0>, <_ams 1>, <_ams
2>, <_ams 3>;
+ };
+ ina226-dac-avtt {
+ compatible = "iio-hwmon";
+ io-channels = <_avtt 0>, <_avtt 1>, <_avtt 2>,
<_avtt 3>;
+ };
+ ina226-dac-avccaux {
+ compatible = "iio-hwmon";
+ io-channels = <_avccaux 0>, <_avccaux 1>, <_avccaux
2>, <_avccaux 3>;
+ };
+ ina226-adc-avcc {
+ compatible = "iio-hwmon";
+ io-channels = <_avcc 0>, <_avcc 1>, <_avcc 2>,
<_avcc 3>;
+ };
+ ina226-adc-avccaux {
+ compatible = "iio-hwmon";
+ io-channels = <_avccaux 0>, <_avccaux 1>, <_avccaux
2>, <_avccaux 3>;
+ };
+ ina226-dac-avcc {
+ compatible = "iio-hwmon";
+ io-channels = <_avcc 0>, <_avcc 1>, <_avcc 2>,
<_avcc 3>;
+ };
+
+ /* 48MHz
[PATCH 10/11] arm64: zynqmp: Add support for zcu670-revA
The board is sharing a lot of components with zcu208 but it contains
differet silicon and also several components are done differently.
The board has 4GB memory connected to PS and additional 4GB connected to
PL. Compare to zcu208 sata support has been dropped and only USB3.0 is
using GTR (lane2). Others GTRs are routed to connectors.
MIO configuration is also shared with zcu111.
The board is using si5381 chip compare to si5341 which is normally used.
And as of now there is no Linux driver for this chip. PS reference clock is
generated out of si570 chip which is also new approach compare to zcu208.
Signed-off-by: Michal Simek
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-zcu670-revA.dts | 669
2 files changed, 670 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-zcu670-revA.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 42def7a1178b..4c31a923aebc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -447,6 +447,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu1285-revA.dtb \
zynqmp-zcu208-revA.dtb \
zynqmp-zcu216-revA.dtb \
+ zynqmp-zcu670-revA.dtb \
zynqmp-zc1232-revA.dtb \
zynqmp-zc1254-revA.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts
b/arch/arm/dts/zynqmp-zcu670-revA.dts
new file mode 100644
index ..edbbf0b30e7b
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu670-revA.dts
@@ -0,0 +1,669 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP ZCU670 (67DR)
+ *
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include
+#include
+#include
+#include
+
+/ {
+ model = "ZynqMP ZCU670 RevA";
+ compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670",
+"xlnx,zynqmp";
+
+ aliases {
+ ethernet0 =
+ i2c0 =
+ i2c1 =
+ mmc0 =
+ nvmem0 =
+ rtc0 =
+ serial0 =
+ serial1 =
+ spi0 =
+ usb0 =
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0 0x8000>, <0x8 0x0 0x0 0x8000>;
+ /* Another 4GB connected to PL */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ sw1 {
+ label = "sw1";
+ gpios = < 22 GPIO_ACTIVE_HIGH>;
+ linux,code = ;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat-led {
+ label = "heartbeat"; /* DS1 */
+ gpios = < 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ ina226-vccint {
+ compatible = "iio-hwmon";
+ io-channels = < 0>, < 1>, < 2>, <
3>;
+ };
+ ina226-vccint-io-bram-ps {
+ compatible = "iio-hwmon";
+ io-channels = <_io_bram_ps 0>, <_io_bram_ps 1>,
<_io_bram_ps 2>, <_io_bram_ps 3>;
+ };
+ ina226-vcc1v8 {
+ compatible = "iio-hwmon";
+ io-channels = < 0>, < 1>, < 2>, <
3>;
+ };
+ ina226-vcc1v2 {
+ compatible = "iio-hwmon";
+ io-channels = < 0>, < 1>, < 2>, <
3>;
+ };
+ ina226-vadj-fmc {
+ compatible = "iio-hwmon";
+ io-channels = <_fmc 0>, <_fmc 1>, <_fmc 2>,
<_fmc 3>;
+ };
+ ina226-mgtavcc {
+ compatible = "iio-hwmon";
+ io-channels = < 0>, < 1>, < 2>,
< 3>;
+ };
+ ina226-mgt1v2 {
+ compatible = "iio-hwmon";
+ io-channels = < 0>, < 1>, < 2>, <
3>;
+ };
+ ina226-mgt1v8 {
+ compatible = "iio-hwmon";
+ io-channels = < 0>, < 1>, < 2>, <
3>;
+ };
+ ina226-vccint-ams {
+ compatible = "iio-hwmon";
+ io-channels = <_ams 0>, <_ams 1>, <_ams
2>, <_ams 3>;
+ };
+ ina226-dac-avtt {
+ compatible = "iio-hwmon";
+ io-channels = <_avtt 0>, <_avtt 1>, <_avtt 2>,
<_avtt 3>;
+ };
+ ina226-dac-avccaux {
+ compatible = "iio-hwmon";
+ io-channels = <_avccaux 0>, <_avccaux 1>, <_avccaux
2>, <_avccaux 3>;
+ };
+ ina226-adc-avcc {
+
[PATCH 08/11] arm64: zynqmp: Describe i2c structures for SCs
Generic system controller (SC) covers connection defined by specification
but different boards have different i2c devices. That's why describe i2c
devices available on multiple boards.
Signed-off-by: Michal Simek
---
arch/arm/dts/Makefile | 7 +
arch/arm/dts/zynqmp-sc-vek280-revA.dtso | 230 +
arch/arm/dts/zynqmp-sc-vek280-revB.dtso | 15 +
arch/arm/dts/zynqmp-sc-vhk158-revA.dtso | 321
.../arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso | 460 ++
arch/arm/dts/zynqmp-sc-vpk120-revB.dtso | 326 +
arch/arm/dts/zynqmp-sc-vpk180-revA.dtso | 371 ++
arch/arm/dts/zynqmp-sc-vpk180-revB.dtso | 337 +
8 files changed, 2067 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-sc-vek280-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-sc-vek280-revB.dtso
create mode 100644 arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
create mode 100644 arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3cde86d9eb38..a15ecd4bc70b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -413,6 +413,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-qspi.dtb\
zynqmp-sc-revB.dtb \
zynqmp-sc-revC.dtb \
+ zynqmp-sc-vek280-revA.dtbo \
+ zynqmp-sc-vek280-revB.dtbo \
+ zynqmp-sc-vhk158-revA.dtbo \
+ zynqmp-sc-vpk120-revB.dtbo \
+ zynqmp-sc-vpk180-revA.dtbo \
+ zynqmp-sc-vpk180-revB.dtbo \
+ zynqmp-sc-vn-p-b2197-00-revA.dtbo \
zynqmp-sm-k24-revA.dtb \
zynqmp-smk-k24-revA.dtb \
zynqmp-sm-k26-revA.dtb \
diff --git a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
new file mode 100644
index ..3320bbc11fcd
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VEK280 revA
+ *
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
+ *
+ * Michal Simek
+ */
+
+#include
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA",
+"xlnx,zynqmp-vek280", "xlnx,zynqmp";
+
+ vc7_xin: vc7-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5000>;
+ };
+};
+
+ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "", "", "SFP_MOD_ABS", "SFP_TX_DISABLE", /* 0
- 3 */
+ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "",
"FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B",
"PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = < SYSCTLR_IIC_MUX0_RESET_B
GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir35215_46: pmic@46 { /* IR35215 - u152 */
+ compatible = "infineon,ir35215";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ irps5401_48: pmic@48 { /* IRPS5401 - u279 */
+ compatible = "infineon,irps5401";
+ reg = <0x48>; /* i2c addr 0x18 */
+ };
+ ir38064_49: regulator@49 { /* IR38064 - u295 */
+ compatible = "infineon,ir38064";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible =
[PATCH 09/11] arm64: zynqmp: Add support for VPXA2785
VPXA2785(vp-x-a2785-00) is evaluation board which contains two PCIe-Edge
fingers, one for PCIe-B(gen5x8) and one for CPM(dual gen5x8, gen5x16).
Each of the ports can operate in endpoint or root port mode. This allows
the single card to be used for both root port, endpoint, and switch modes.
The board is designed in the similar manner as others Versal boards. It
means board also have ZynqMP Zu4 System Controller which is described in a
separate file.
Signed-off-by: Michal Simek
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts | 438 +
2 files changed, 439 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a15ecd4bc70b..42def7a1178b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -431,6 +431,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-sck-kv-g-revB.dtbo \
zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb\
zynqmp-vpk120-revA.dtb \
+ zynqmp-vp-x-a2785-00-revA.dtb \
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
new file mode 100644
index ..2f88aa4a0d28
--- /dev/null
+++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include
+#include
+#include
+#include
+
+/ {
+ model = "ZynqMP System Controller on vp-x-a2785-00 board RevA";
+ compatible = "xlnx,zynqmp-vp-x-a2785-00-revA",
+"xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 =
+ i2c0 =
+ i2c1 =
+ mmc0 =
+ serial0 =
+ serial1 =
+ spi0 =
+ usb0 =
+ usb1 =
+ nvmem0 =
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0 0x8000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ j383 {
+ label = "j383";
+ gpios = < 10 GPIO_ACTIVE_HIGH>;
+ linux,code = ;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat-led { /* ds52 */
+ label = "heartbeat";
+ gpios = < 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ si5332_0: si5332_0 { /* ps_ref_clk - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <>;
+ };
+
+ si5332_1: si5332_1 { /* clk0_sgmii - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <>; /* FIXME */
+ };
+
+ si5332_2: si5332_2 { /* clk1_usb - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2700>;
+ };
+};
+
+ { /* MIO 0-5 */
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* u285 -
mt25qu512abb8e12 512Mib */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-tx-bus-width = <4>; /* maybe 4 here */
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <10800>;
+ partition@0 { /* for testing purpose */
+ label = "qspi";
+ reg = <0 0x400>;
+ };
+ };
+};
+
+ { /* sd MIO 45-51 */
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio-bank = <1>;
+};
+
+ { /* uart0 MIO38-39 */
+ status = "okay";
+ bootph-all;
+};
+
+ {
+ status = "okay";
+ phy-handle = <>;
+ phy-mode = "sgmii"; /* DTG generates this properly 1512 */
+ is-internal-pcspma;
+ /* phys = < 0 PHY_TYPE_SGMII 0 0>; */
+ /* phy-reset-gpios = < 142 GPIO_ACTIVE_LOW>; */
+ phy0: ethernet-phy@0 { /* u131 - M88e1512 */
+ reg = <0>;
+ };
+};
+
+ {
+ status = "okay";
+
[PATCH 07/11] arm64: zynqmp: Add support for SC revC
System controller revC is using ADI ethernet phy instead of TI because of
supply chain issues.
Describe reset assert and de-assert times to 10us and 5ms respectively
according to the datasheet. Also setup RGMII RX and TX delay values to
2400ps as per board bring up observations.
Signed-off-by: Michal Simek
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-sc-revC.dts | 37 +
2 files changed, 38 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-sc-revC.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 29c40d1c3b66..3cde86d9eb38 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -412,6 +412,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-nand.dtb\
zynqmp-mini-qspi.dtb\
zynqmp-sc-revB.dtb \
+ zynqmp-sc-revC.dtb \
zynqmp-sm-k24-revA.dtb \
zynqmp-smk-k24-revA.dtb \
zynqmp-sm-k26-revA.dtb \
diff --git a/arch/arm/dts/zynqmp-sc-revC.dts b/arch/arm/dts/zynqmp-sc-revC.dts
new file mode 100644
index ..530a4a5f080f
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-revC.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP Generic System Controller
+ *
+ * Copyright (C) 2021 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek
+ */
+
+#include "zynqmp-sc-revB.dts"
+
+/ {
+ model = "ZynqMP Generic System Controller";
+ compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp";
+};
+
+ { /* gem1 MIO38-49, MDIO MIO50/51 */
+ /delete-node/ mdio;
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@1 { /* ADI1300 */
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id0283.bc30";
+ reg = <1>;
+ adi,rx-internal-delay-ps = <2400>;
+ adi,tx-internal-delay-ps = <2400>;
+ adi,fifo-depth-bits = <8>;
+ reset-gpios = < 77 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <5000>;
+ };
+ };
+};
--
2.36.1
[PATCH 06/11] arm64: zynqmp: Create description for generic SC (vpk120-revB)
System controllers are pretty much the same on the all boards that's why
use autodetection based on i2c eeprom. This should end up with having only
one BSP for all SCs with only DT overlays to cover different i2c
structures.
All MIOs are fixed by the spec that's why not a problem to description
pinctrl setting.
Apart from eth phy reset, it also set proper phy delays.
The TI DP83867 PHY datasheet says:
T1: Post RESET stabilization time == 195us
T3: Hardware configuration pins transition to output drivers == 64us
T4: RESET pulse width == 1us
So with a little overhead set 'reset-assert-us' to 100us (T4) and
'reset-deassert-us' to 280us (T1+T3).
NOTE: The tuning of TI DP83867 phy reset delay is derived from linux
upstream commit: 5dbadc848259(arm64: dts: fsl: add support for Kontron
pitx-imx8m board).
i2c structure on Xilinx Versal evaluation platforms contain a lot of
devices but also connection to connectors like SFP. Because of this
complicated structure with also all level shifters, i2c muxes, etc. not all
devices are able to reliably work on 400kHz even if they are compatible
with this speed. That's why set i2c frequency to 100KHz to increase
reliability of the i2c bus.
Signed-off-by: Michal Simek
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-sc-revB.dts | 430
2 files changed, 431 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-sc-revB.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fbce328acafe..29c40d1c3b66 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -411,6 +411,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb\
zynqmp-mini-qspi.dtb\
+ zynqmp-sc-revB.dtb \
zynqmp-sm-k24-revA.dtb \
zynqmp-smk-k24-revA.dtb \
zynqmp-sm-k26-revA.dtb \
diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts
new file mode 100644
index ..e0b554c9c545
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-revB.dts
@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP Generic System Controller
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ model = "ZynqMP Generic System Controller";
+ compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp";
+
+ aliases {
+ i2c0 =
+ i2c1 =
+ mmc0 =
+ mmc1 =
+ nvmem0 =
+ rtc0 =
+ serial0 =
+ serial1 =
+ serial2 =
+ spi0 =
+ spi1 =
+ spi2 =
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x8000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ fwuen {
+ label = "sw16";
+ gpios = < 12 GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ ds40-led {
+ label = "heartbeat";
+ gpios = < 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ ds44-led {
+ label = "status";
+ gpios = < 8 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ si5332_2: si5332_2 { /* u42 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ };
+
+ pwm-fan {
+ compatible = "pwm-fan";
+ status = "okay";
+ pwms = < 2 4 1>;
+ };
+};
+
+ {
+ status = "okay";
+ gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3",
"QSPI_DQ0", /* 0 - 4 */
+ "QSPI_CS_B", "", "LED1", "LED2", "", /* 5 - 9 */
+ "", "ZU4_TRIGGER", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 -
14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5",
"EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "I2C1_SCL",
/* 20 - 24 */
+ "I2C1_SDA", "UART0_RXD", "UART0_TXD", "", "", /* 25 - 29 */
+ "", "", "", "", "I2C0_SCL", /* 30 - 34 */
+ "I2C0_SDA", "UART1_TXD",
[PATCH 05/11] arm64: zynqmp: Add support for vpk120-revA
Board contains two systems. The primary is Versal VP1202 ACAP device and
the secondary is ZynqMP zu4 which acts as system controller. The patch is
describing only ZynqMP system controller part.
Signed-off-by: Michal Simek
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-vpk120-revA.dts | 574
2 files changed, 575 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-vpk120-revA.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d1b28a6d02ed..fbce328acafe 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -421,6 +421,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-sck-kv-g-revA.dtbo \
zynqmp-sck-kv-g-revB.dtbo \
zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb\
+ zynqmp-vpk120-revA.dtb \
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts
b/arch/arm/dts/zynqmp-vpk120-revA.dts
new file mode 100644
index ..66919f578e02
--- /dev/null
+++ b/arch/arm/dts/zynqmp-vpk120-revA.dts
@@ -0,0 +1,574 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VPK120 RevA System Controller
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include
+#include
+#include
+#include
+
+/ {
+ model = "ZynqMP System Controller on VPK120 board RevA";
+ compatible = "xlnx,zynqmp-vpk120-revA",
+"xlnx,zynqmp-vpk120", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 =
+ i2c0 =
+ i2c1 =
+ mmc0 =
+ serial0 =
+ serial1 =
+ spi0 =
+ usb0 =
+ usb1 =
+ nvmem0 =
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x8000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ sw16 {
+ label = "sw16";
+ gpios = < 10 GPIO_ACTIVE_HIGH>;
+ linux,code = ;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat-led { /* ds40 */
+ label = "heartbeat";
+ gpios = < 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ si5332_0: si5332_0 { /* ps_ref_clk */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <>;
+ };
+
+ si5332_1: si5332_1 { /* clk0_sgmii */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <>; /* FIXME */
+ };
+
+ si5332_2: si5332_2 { /* clk1_usb */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2700>;
+ };
+};
+
+ { /* MIO 0-5 */
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12
512Mib */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <10800>;
+ partition@0 { /* for testing purpose */
+ label = "qspi";
+ reg = <0 0x400>;
+ };
+ };
+};
+
+ { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio-bank = <0>;
+};
+
+ { /* uart0 MIO38-39 */
+ status = "okay";
+ bootph-all;
+};
+
+ {
+ status = "okay";
+ phy-handle = <>;
+ phy-mode = "sgmii"; /* DTG generates this properly 1512 */
+ is-internal-pcspma;
+ /* phys = < 0 PHY_TYPE_SGMII 0 0>; */
+ /* phy-reset-gpios = < 142 GPIO_ACTIVE_LOW>; */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+ {
+ status = "okay";
+ gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3",
"QSPI_DQ0", /* 0 - 4 */
+ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9
*/
+ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0",
"EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3",
[PATCH 04/11] arm64: zynqmp: Add x-prc-01/02/03/04/05 revA support from SC
Add i2c accessible devices with description.
There is versal specific eeprom and i2c-gpio controller.
SE3 has also clock chip present.
Also remove x-prc description from SC dts.
Signed-off-by: Michal Simek
---
arch/arm/dts/Makefile | 5 ++
.../zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso | 76
.../zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso | 76
.../zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso | 80 +
.../zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso | 86 +++
.../zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso | 86 +++
6 files changed, 409 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e060081cdea5..d1b28a6d02ed 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -401,6 +401,11 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-m-a2197-02-revA.dtb \
zynqmp-m-a2197-03-revA.dtb \
zynqmp-p-a2197-00-revA.dtb \
+ zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo \
+ zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo \
+ zynqmp-p-a2197-00-revA-x-prc-03-revA.dtbo \
+ zynqmp-p-a2197-00-revA-x-prc-04-revA.dtbo \
+ zynqmp-p-a2197-00-revA-x-prc-05-revA.dtbo \
zynqmp-mini.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
new file mode 100644
index ..197dc2523531
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-01 revA (SE1)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01";
+
+ fragment@0 {
+ target = <_i2c>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ x_prc_eeprom: eeprom@52 { /* u120 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u121 tca9534 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3",
"sw4_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <>; /* Must be enabled via J242 */
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom_versal: eeprom@51 { /* u116 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
[PATCH 03/11] arm64: zynqmp: Add support for vck190 revB system controller
There are some changes between revA and revB boards. u39 8T49N240 was
removed and also three ina226 at 42/43/44 addresses (u178/u180/u182).
Signed-off-by: Michal Simek
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-e-a2197-00-revB.dts | 34 +
configs/xilinx_zynqmp_virt_defconfig| 2 +-
3 files changed, 36 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/zynqmp-e-a2197-00-revB.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e42261233758..e060081cdea5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -395,6 +395,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-a2197-revA.dtb \
zynqmp-dlc21-revA.dtb \
zynqmp-e-a2197-00-revA.dtb \
+ zynqmp-e-a2197-00-revB.dtb \
zynqmp-g-a2197-00-revA.dtb \
zynqmp-m-a2197-01-revA.dtb \
zynqmp-m-a2197-02-revA.dtb \
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revB.dts
b/arch/arm/dts/zynqmp-e-a2197-00-revB.dts
new file mode 100644
index ..8310df9ed369
--- /dev/null
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revB.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevB System Controller
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek
+ */
+
+#include "zynqmp-e-a2197-00-revA.dts"
+
+/ {
+ model = "Versal System Controller on a2197 Eval board RevB"; /*
VCK190/VMK180 */
+ compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB",
+"xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+ /delete-node/ ina226-vcco-500;
+ /delete-node/ ina226-vcco-501;
+ /delete-node/ ina226-vcco-502;
+};
+
+ {
+ i2c-mux@74 { /* u33 */
+ i2c@2 { /* PCIE_CLK */
+ /delete-node/ clock-generator@6c;
+ };
+ i2c@3 { /* PMBUS2_INA226 */
+ /delete-node/ ina226@42;
+ /delete-node/ ina226@43;
+ /delete-node/ ina226@44;
+ };
+ };
+};
diff --git a/configs/xilinx_zynqmp_virt_defconfig
b/configs/xilinx_zynqmp_virt_defconfig
index 30e420951dad..d72fac40a516 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -103,7 +103,7 @@ CONFIG_CMD_UBI=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_BOARD=y
-CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA
zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA
zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA
zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2
zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5
zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA
zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA
zynqmp-zcu106-rev1.0 zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB
zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA
zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA
zynqmp-dlc21-revA"
+CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA
zynqmp-e-a2197-00-revB zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA
zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA
zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1
zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4
zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1
zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA
zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu106-rev1.0 zynqmp-zcu111-revA
zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA
zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA
zynqmp-smk-k26-revA zynqmp-dlc21-revA"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent
interrupts iommus power-domains"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_FAT=y
--
2.36.1
[PATCH 02/11] arm64: zynqmp: Remove xlnx,fclk nodes
xlnx,fclk nodes are not described in dtschema that's why remove them.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 18 --
1 file changed, 18 deletions(-)
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 4044b62d27a2..5f1b0b23c124 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -16,24 +16,6 @@
clocks = <_clk PL0_REF>;
};
- fclk1: fclk1 {
- status = "okay";
- compatible = "xlnx,fclk";
- clocks = <_clk PL1_REF>;
- };
-
- fclk2: fclk2 {
- status = "okay";
- compatible = "xlnx,fclk";
- clocks = <_clk PL2_REF>;
- };
-
- fclk3: fclk3 {
- status = "okay";
- compatible = "xlnx,fclk";
- clocks = <_clk PL3_REF>;
- };
-
pss_ref_clk: pss_ref_clk {
bootph-all;
compatible = "fixed-clock";
--
2.36.1
[PATCH 01/11] arm64: zynqmp: Add support for KD240 Kria SOM CC
Add support for KD240 Kria SOM CC. It is pretty much subset of KR260 board
from PS perspective.
Signed-off-by: Michal Simek
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 353 +
2 files changed, 354 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bde2176ec7f6..e42261233758 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -409,6 +409,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-smk-k24-revA.dtb \
zynqmp-sm-k26-revA.dtb \
zynqmp-smk-k26-revA.dtb \
+ zynqmp-sck-kd-g-revA.dtbo \
zynqmp-sck-kr-g-revA.dtbo \
zynqmp-sck-kr-g-revB.dtbo \
zynqmp-sck-kv-g-revA.dtbo \
diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
new file mode 100644
index ..5a5c1efd6b96
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for KD240 revA Carrier Card
+ *
+ * Copyright (C) 2021 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek
+ */
+
+#include
+#include
+#include
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "xlnx,zynqmp-sk-kd240-rev1",
+"xlnx,zynqmp-sk-kd240-revB",
+"xlnx,zynqmp-sk-kd240-revA",
+"xlnx,zynqmp-sk-kd240", "xlnx,zynqmp";
+ model = "ZynqMP KD240 revA/B/1";
+
+ ina260-u3 {
+ compatible = "iio-hwmon";
+ io-channels = < 0>, < 1>, < 2>;
+ };
+
+ clk_26: clock2 { /* u17 - USB */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ };
+};
+
+ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_can0_default>;
+};
+
+ { /* I2C_SCK C26/C27 - MIO from SOM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <_i2c1_default>;
+ pinctrl-1 = <_i2c1_gpio>;
+ scl-gpios = < 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = < 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ u3: ina260@40 { /* u3 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
+ };
+
+ slg7xl45106: gpio@11 { /* u13 - reset logic */
+ compatible = "dlg,slg7xl45106";
+ reg = <0x11>;
+ label = "resetchip";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "USB0_PHY_RESET_B", "",
+ "SD_RESET_B", "USB0_HUB_RESET_B",
+ "", "PS_GEM0_RESET_B",
+ "", "";
+ };
+
+ /* usb5744@2d */
+};
+
+/* USB 3.0 */
+ {
+ status = "okay";
+ /* usb */
+ clocks = <_26>;
+ clock-names = "ref2";
+};
+
+ { /* mio52 - mio63 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = < 2 PHY_TYPE_USB3 0 2>;
+ reset-gpios = < 0 GPIO_ACTIVE_LOW>;
+ assigned-clock-rates = <25000>, <2000>;
+
+ usbhub0: usb-hub { /* u36 */
+ i2c-bus = <>;
+ compatible = "microchip,usb5744";
+ reset-gpios = < 3 GPIO_ACTIVE_LOW>;
+ };
+
+ usb2244: usb-sd { /* u41 */
+ compatible = "microchip,usb2244";
+ reset-gpios = < 2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
+};
+
+ { /* mdio mio50/51 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_gem1_default>;
+ assigned-clock-rates = <25000>;
+
+ phy-handle = <>;
+ phy-mode = "rgmii-id";
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@8 { /* Adin u31 */
+ reg = <8>;
+ adi,rx-internal-delay-ps = <2000>;
+ adi,tx-internal-delay-ps = <2000>;
+ adi,fifo-depth-bits = <8>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <5000>;
+ reset-gpios = < 77 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+/* 2 more ethernet phys u32@2 and u34@3 */
+
+ { /* required by spec */
+ status = "okay";
+
+ pinctrl_can0_default: can0-default {
+ mux {
+ function = "can0";
+
[PATCH 00/11] xilinx: add missing boards/SC descriptions
Hi, I am sending series of zynqmp boards mostly related to system controller. System controller is small ZynqMP board sitting on Versal/Versal NET board doing board management. There is a internal spec about connection outside but pretty much DT description describe all connected IPs. The only thing what it is not covered in generic SC are i2c buses because they contain different devices. That's why they are described by DT overlays. The first version was created for vpk120-revA, next was generic SC revB and because of supply chain issue ethernet phy was replaced which ends up in revC version. The series also contain some cleanups and also adding new platforms like KD240. Thanks, Michal Michal Simek (11): arm64: zynqmp: Add support for KD240 Kria SOM CC arm64: zynqmp: Remove xlnx,fclk nodes arm64: zynqmp: Add support for vck190 revB system controller arm64: zynqmp: Add x-prc-01/02/03/04/05 revA support from SC arm64: zynqmp: Add support for vpk120-revA arm64: zynqmp: Create description for generic SC (vpk120-revB) arm64: zynqmp: Add support for SC revC arm64: zynqmp: Describe i2c structures for SCs arm64: zynqmp: Add support for VPXA2785 arm64: zynqmp: Add support for zcu670-revA arm64: zynqmp: Add support for zcu670-revB arch/arm/dts/Makefile | 20 + arch/arm/dts/zynqmp-clk-ccf.dtsi | 18 - arch/arm/dts/zynqmp-e-a2197-00-revB.dts | 34 + .../zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso | 76 ++ .../zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso | 76 ++ .../zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso | 80 +++ .../zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso | 86 +++ .../zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso | 86 +++ arch/arm/dts/zynqmp-sc-revB.dts | 430 +++ arch/arm/dts/zynqmp-sc-revC.dts | 37 + arch/arm/dts/zynqmp-sc-vek280-revA.dtso | 230 ++ arch/arm/dts/zynqmp-sc-vek280-revB.dtso | 15 + arch/arm/dts/zynqmp-sc-vhk158-revA.dtso | 321 + .../arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso | 460 arch/arm/dts/zynqmp-sc-vpk120-revB.dtso | 326 + arch/arm/dts/zynqmp-sc-vpk180-revA.dtso | 371 ++ arch/arm/dts/zynqmp-sc-vpk180-revB.dtso | 337 + arch/arm/dts/zynqmp-sck-kd-g-revA.dtso| 353 + arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts| 438 arch/arm/dts/zynqmp-vpk120-revA.dts | 574 +++ arch/arm/dts/zynqmp-zcu670-revA.dts | 669 + arch/arm/dts/zynqmp-zcu670-revB.dts | 672 ++ configs/xilinx_zynqmp_virt_defconfig | 2 +- 23 files changed, 5692 insertions(+), 19 deletions(-) create mode 100644 arch/arm/dts/zynqmp-e-a2197-00-revB.dts create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso create mode 100644 arch/arm/dts/zynqmp-sc-revB.dts create mode 100644 arch/arm/dts/zynqmp-sc-revC.dts create mode 100644 arch/arm/dts/zynqmp-sc-vek280-revA.dtso create mode 100644 arch/arm/dts/zynqmp-sc-vek280-revB.dtso create mode 100644 arch/arm/dts/zynqmp-sc-vhk158-revA.dtso create mode 100644 arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso create mode 100644 arch/arm/dts/zynqmp-sc-vpk120-revB.dtso create mode 100644 arch/arm/dts/zynqmp-sc-vpk180-revA.dtso create mode 100644 arch/arm/dts/zynqmp-sc-vpk180-revB.dtso create mode 100644 arch/arm/dts/zynqmp-sck-kd-g-revA.dtso create mode 100644 arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts create mode 100644 arch/arm/dts/zynqmp-vpk120-revA.dts create mode 100644 arch/arm/dts/zynqmp-zcu670-revA.dts create mode 100644 arch/arm/dts/zynqmp-zcu670-revB.dts -- 2.36.1
sunxi: introduce NCAT2 generation model
When NCAT2 generation model's introduced for t113, the modification in drivers/mmc/sunxi_mmc.c > + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) && (sdc_no == 2)) in struct mmc *sunxi_mmc_init(int sdc_no) seems to have some negative side effects, meaning enabling 8-bit mode for MMC2. Paticularly, IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) should not be used for D1/T113 since there is not support for 8-bit mode for MMC2 yet. Therefore, the solution would be to drop this particular change entirely. Signed-off-by: Okhunjon Sobirjonov
[PATCH v5 7/7] efi_loader: create BlockIo device boot option
Current efibootmgr automatically creates the boot options
of all the disks and partitions installing
SIMPLE_FILE_SYSTEM_PROTOCOL. These boot options are created
to load and start the default file(e.g. EFI/BOOT/BOOTAA64.EFI).
Now efibootmgr can scan the BlockIo device and try to boot
with the default file on the fly, this commit creates the
boot options only for the BlockIo devices exluding the logical
partition.
Signed-off-by: Masahisa Kojima
---
include/efi_loader.h | 1 +
lib/efi_loader/efi_bootmgr.c | 50 ++--
lib/efi_loader/efi_device_path.c | 20 +
3 files changed, 55 insertions(+), 16 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index c4207edc91..cc292f0553 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -932,6 +932,7 @@ struct efi_device_path *efi_dp_from_lo(struct
efi_load_option *lo,
struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1,
const struct efi_device_path *dp2);
struct efi_device_path *search_gpt_dp_node(struct efi_device_path
*device_path);
+struct efi_device_path *efi_search_file_path_dp_node(struct efi_device_path
*device_path);
efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8 *data,
efi_uintn_t *size);
unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data);
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index a5030d50c0..2da80428b4 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -387,7 +387,6 @@ static efi_status_t try_load_entry(u16 n, efi_handle_t
*handle,
}
if (lo.attributes & LOAD_OPTION_ACTIVE) {
- struct efi_device_path *file_path;
u32 attributes;
log_debug("trying to load \"%ls\" from %pD\n", lo.label,
@@ -407,11 +406,17 @@ static efi_status_t try_load_entry(u16 n, efi_handle_t
*handle,
} else {
ret = EFI_LOAD_ERROR;
}
- } else {
- file_path = expand_media_path(lo.file_path);
- ret = EFI_CALL(efi_load_image(true, efi_root, file_path,
+ } else if (efi_search_file_path_dp_node(lo.file_path)) {
+ ret = EFI_CALL(efi_load_image(true, efi_root,
lo.file_path,
NULL, 0, handle));
- efi_free_pool(file_path);
+ } else {
+ efi_handle_t h;
+
+ h = efi_dp_find_obj(lo.file_path, _block_io_guid,
NULL);
+ if (h)
+ ret = load_default_file_from_blk_dev(h->dev,
handle);
+ else
+ ret = EFI_LOAD_ERROR;
}
if (ret != EFI_SUCCESS) {
log_warning("Loading %ls '%ls' failed\n",
@@ -551,13 +556,13 @@ error:
*/
static efi_status_t efi_bootmgr_enumerate_boot_option(struct
eficonfig_media_boot_option *opt,
efi_handle_t
*volume_handles,
- efi_status_t count)
+ efi_uintn_t *count)
{
- u32 i;
+ u32 i, num = 0;
struct efi_handler *handler;
efi_status_t ret = EFI_SUCCESS;
- for (i = 0; i < count; i++) {
+ for (i = 0; i < *count; i++) {
u16 *p;
u16 dev_name[BOOTMENU_DEVICE_NAME_MAX];
char *optional_data;
@@ -565,6 +570,16 @@ static efi_status_t
efi_bootmgr_enumerate_boot_option(struct eficonfig_media_boo
char buf[BOOTMENU_DEVICE_NAME_MAX];
struct efi_device_path *device_path;
struct efi_device_path *short_dp;
+ struct efi_block_io *blkio;
+
+ ret = efi_search_protocol(volume_handles[i],
_block_io_guid, );
+ blkio = handler->protocol_interface;
+ /*
+* The logical partition is excluded since the bootmgr tries to
+* boot with the default file by scanning the default file on
the fly.
+*/
+ if (blkio->media->logical_partition)
+ continue;
ret = efi_search_protocol(volume_handles[i],
_guid_device_path, );
if (ret != EFI_SUCCESS)
@@ -598,16 +613,18 @@ static efi_status_t
efi_bootmgr_enumerate_boot_option(struct eficonfig_media_boo
* to store guid, instead of realloc the load_option.
*/
lo.optional_data = "1234567";
- opt[i].size = efi_serialize_load_option(, (u8 **)[i].lo);
- if (!opt[i].size) {
+ opt[num].size =
[PATCH v5 6/7] doc: uefi: add HTTP Boot support
This adds the description about HTTP Boot. Signed-off-by: Masahisa Kojima Reviewed-by: Ilias Apalodimas --- doc/develop/uefi/uefi.rst | 30 ++ 1 file changed, 30 insertions(+) diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index a7a41f2fac..23b3da0f95 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -594,6 +594,36 @@ UEFI variables. Booting according to these variables is possible via:: As of U-Boot v2020.10 UEFI variables cannot be set at runtime. The U-Boot command 'efidebug' can be used to set the variables. +UEFI HTTP Boot +~~ + +HTTP Boot provides the capability for system deployment and configuration +over the network. HTTP Boot can be activated by specifying:: + +CONFIG_CMD_DNS +CONFIG_CMD_WGET +CONFIG_BLKMAP + +Set up the load option specifying the target URI:: + +efidebug boot add -u 1 netinst http://foo/bar + +When this load option is selected as boot selection, resolve the +host ip address by dns, then download the file with wget. +If the downloaded file extension is .iso or .img file, efibootmgr tries to +mount the image and boot with the default file(e.g. EFI/BOOT/BOOTAA64.EFI). +If the downloaded file is PE-COFF image, load the downloaded file and +start it. + +The current implementation tries to resolve the IP address as a host name. +If the uri is like "http://192.168.1.1/foobar;, +the dns process tries to resolve the host "192.168.1.1" and it will +end up with "host not found". + +We need to preset the "httpserverip" environment variable to proceed the wget:: + +setenv httpserverip 192.168.1.1 + Executing the built in hello world application ~~ -- 2.34.1
[PATCH v5 5/7] cmd: efidebug: add uri device path
This adds the URI device path option for 'boot add' subcommand.
User can add the URI load option for downloading ISO image file
or EFI application through network. Currently HTTP is only supported.
Signed-off-by: Masahisa Kojima
---
cmd/efidebug.c | 50 +++
include/net.h | 8 ++
net/wget.c | 72 ++
3 files changed, 130 insertions(+)
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 0be3af3e76..f2fd6ba71d 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -829,6 +830,52 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag,
argc -= 1;
argv += 1;
break;
+#if (IS_ENABLED(CONFIG_BLKMAP) && IS_ENABLED(CONFIG_CMD_WGET) &&
IS_ENABLED(CONFIG_CMD_DNS))
+ case 'u':
+ {
+ char *pos;
+ int uridp_len;
+ struct efi_device_path_uri *uridp;
+
+ if (argc < 3 || lo.label) {
+ r = CMD_RET_USAGE;
+ goto out;
+ }
+ id = (int)hextoul(argv[1], );
+ if (*endp != '\0' || id > 0x)
+ return CMD_RET_USAGE;
+
+ efi_create_indexed_name(var_name16, sizeof(var_name16),
+ "Boot", id);
+
+ label = efi_convert_string(argv[2]);
+ if (!label)
+ return CMD_RET_FAILURE;
+ lo.label = label;
+
+ uridp_len = sizeof(struct efi_device_path) +
strlen(argv[3]) + 1;
+ fp_free = efi_alloc(uridp_len + sizeof(END));
+ uridp = (struct efi_device_path_uri *)fp_free;
+ uridp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ uridp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_URI;
+ uridp->dp.length = uridp_len;
+ if (!wget_validate_uri(argv[3])) {
+ printf("ERROR: invalid URI\n");
+ r = CMD_RET_FAILURE;
+ goto out;
+ }
+
+ strcpy(uridp->uri, argv[3]);
+ pos = (char *)uridp + uridp_len;
+ memcpy(pos, , sizeof(END));
+ fp_size += uridp_len + sizeof(END);
+ file_path = (struct efi_device_path *)uridp;
+ argc -= 3;
+ argv += 3;
+ break;
+ }
+#endif
+
default:
r = CMD_RET_USAGE;
goto out;
@@ -1492,6 +1539,9 @@ static char efidebug_help_text[] =
" -b|-B[:] \n"
" -i|-I [:] \n"
" (-b, -i for short form device path)\n"
+#if (IS_ENABLED(CONFIG_BLKMAP) && IS_ENABLED(CONFIG_CMD_WGET) &&
IS_ENABLED(CONFIG_CMD_DNS))
+ " -u \n"
+#endif
" -s ''\n"
"efidebug boot rm [ [ [...]]]\n"
" - delete UEFI Boot variables\n"
diff --git a/include/net.h b/include/net.h
index 57889d8b7a..c748974573 100644
--- a/include/net.h
+++ b/include/net.h
@@ -935,4 +935,12 @@ static inline void eth_set_enable_bootdevs(bool enable) {}
*/
int wget_with_dns(ulong dst_addr, char *uri);
+/**
+ * wget_validate_uri() - varidate the uri
+ *
+ * @uri: uri string of target file of wget
+ * Return: true if uri is valid, false if uri is invalid
+ */
+bool wget_validate_uri(char *uri);
+
#endif /* __NET_H__ */
diff --git a/net/wget.c b/net/wget.c
index 4801e28eb9..6a4d22be32 100644
--- a/net/wget.c
+++ b/net/wget.c
@@ -558,3 +558,75 @@ out:
return ret;
}
#endif
+
+/**
+ * wget_validate_uri() - validate the uri for wget
+ *
+ * @uri: uri string
+ * Return: true on success, false on failure
+ */
+bool wget_validate_uri(char *uri)
+{
+ char c;
+ bool ret = true;
+ char *str_copy, *s, *authority;
+
+ /* TODO: strict uri conformance check */
+
+ /*
+* Uri is expected to be correctly percent encoded.
+* This is the minimum check, control codes(0x1-0x19, 0x7F, except '\0')
+* and space character(0x20) are not allowed.
+*/
+ for (c = 0x1; c < 0x21; c++) {
+ if (strchr(uri, c)) {
+ printf("invalid character is used\n");
+ return false;
+ }
+ }
+ if (strchr(uri, 0x7f)) {
+ printf("invalid character is used\n");
+ return false;
+ }
+
+ /*
+* This follows the current U-Boot wget implementation.
+* scheme: only
[PATCH v5 4/7] efi_loader: support boot from URI device path
This supports to boot from the URI device path.
When user selects the URI device path, bootmgr downloads
the file using wget into the address specified by loadaddr
env variable.
If the file is .iso or .img file, mount the image with blkmap
then try to boot with the default file(e.g. EFI/BOOT/BOOTAA64.EFI).
If the file is PE-COFF file, load and start the downloaded file.
The buffer used to download the ISO image file must be
reserved to avoid the unintended access to the image.
For PE-COFF file case, this memory reservation is done
in LoadImage Boot Service.
Signed-off-by: Masahisa Kojima
---
include/efi_loader.h | 2 +
lib/efi_loader/efi_bootmgr.c | 198 +-
lib/efi_loader/efi_dt_fixup.c | 2 +-
3 files changed, 200 insertions(+), 2 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 4a29ddaef4..c4207edc91 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -554,6 +554,8 @@ void efi_runtime_detach(void);
/* efi_convert_pointer() - convert pointer to virtual address */
efi_status_t EFIAPI efi_convert_pointer(efi_uintn_t debug_disposition,
void **address);
+/* add reserved memory to memory map */
+void efi_reserve_memory(u64 addr, u64 size, bool nomap);
/* Carve out DT reserved memory ranges */
void efi_carve_out_dt_rsv(void *fdt);
/* Purge unused kaslr-seed */
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index a40762c74c..a5030d50c0 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -7,10 +7,14 @@
#define LOG_CATEGORY LOGC_EFI
+#include
+#include
#include
#include
+#include
#include
#include
+#include
#include
#include
#include
@@ -168,6 +172,187 @@ out:
return ret;
}
+/**
+ * mount_image() - mount the image with blkmap
+ *
+ * @lo_label u16 label string of load option
+ * @image_addr:image address
+ * @image_size image size
+ * Return: pointer to the UCLASS_BLK udevice, NULL if failed
+ */
+static struct udevice *mount_image(u16 *lo_label, ulong image_addr, int
image_size)
+{
+ int err;
+ struct blkmap *bm;
+ struct udevice *bm_dev;
+ char *label = NULL, *p;
+
+ label = efi_alloc(utf16_utf8_strlen(lo_label) + 1);
+ if (!label)
+ return NULL;
+
+ p = label;
+ utf16_utf8_strcpy(, lo_label);
+ err = blkmap_create_ramdisk(label, image_addr, image_size, _dev);
+ if (err) {
+ efi_free_pool(label);
+ return NULL;
+ }
+ bm = dev_get_plat(bm_dev);
+
+ efi_free_pool(label);
+
+ return bm->blk;
+}
+
+/**
+ * try_load_default_file() - try to load the default file
+ *
+ * Search the device having EFI_SIMPLE_FILE_SYSTEM_PROTOCOL,
+ * then try to load with the default boot file(e.g. EFI/BOOT/BOOTAA64.EFI).
+ *
+ * @devpointer to the UCLASS_BLK or UCLASS_PARTITION
udevice
+ * @image_handle: pointer to handle for newly installed image
+ * Return: status code
+ */
+static efi_status_t try_load_default_file(struct udevice *dev,
+ efi_handle_t *image_handle)
+{
+ efi_status_t ret;
+ efi_handle_t handle;
+ struct efi_handler *handler;
+ struct efi_device_path *file_path;
+ struct efi_device_path *device_path;
+
+ if (dev_tag_get_ptr(dev, DM_TAG_EFI, (void **))) {
+ log_warning("DM_TAG_EFI not found\n");
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ret = efi_search_protocol(handle,
+ _simple_file_system_protocol_guid,
);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ ret = EFI_CALL(bs->open_protocol(handle, _guid_device_path,
+(void **)_path, efi_root, NULL,
+EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ file_path = expand_media_path(device_path);
+ ret = EFI_CALL(efi_load_image(true, efi_root, file_path, NULL, 0,
+ image_handle));
+
+ efi_free_pool(file_path);
+
+ return ret;
+}
+
+/**
+ * load_default_file_from_blk_dev() - load the default file
+ *
+ * @blkpointer to the UCLASS_BLK udevice
+ * @handle:pointer to handle for newly installed image
+ * Return: status code
+ */
+static efi_status_t load_default_file_from_blk_dev(struct udevice *blk,
+ efi_handle_t *handle)
+{
+ efi_status_t ret;
+ struct udevice *partition;
+
+ /* image that has no partition table but a file system */
+ ret = try_load_default_file(blk, handle);
+ if (ret == EFI_SUCCESS)
+ return ret;
+
+ /* try the partitions */
+ device_foreach_child(partition, blk) {
+
[PATCH v5 3/7] blk: blkmap: add ramdisk creation utility function
User needs to call several functions to create the ramdisk
with blkmap.
This adds the utility function to create blkmap device and
mount the ramdisk.
Signed-off-by: Masahisa Kojima
Reviewed-by: Simon Glass
Reviewed-by: Ilias Apalodimas
---
drivers/block/Makefile| 1 +
drivers/block/blkmap.c| 15 --
drivers/block/blkmap_helper.c | 53 +++
include/blkmap.h | 29 +++
4 files changed, 83 insertions(+), 15 deletions(-)
create mode 100644 drivers/block/blkmap_helper.c
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index a161d145fd..c3ccfc03e5 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -15,6 +15,7 @@ endif
obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o
obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o
obj-$(CONFIG_BLKMAP) += blkmap.o
+obj-$(CONFIG_BLKMAP) += blkmap_helper.o
obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o
obj-$(CONFIG_EFI_MEDIA_SANDBOX) += sb_efi_media.o
diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c
index 2bb0acc20f..4e95997f61 100644
--- a/drivers/block/blkmap.c
+++ b/drivers/block/blkmap.c
@@ -66,21 +66,6 @@ struct blkmap_slice {
void (*destroy)(struct blkmap *bm, struct blkmap_slice *bms);
};
-/**
- * struct blkmap - Block map
- *
- * Data associated with a blkmap.
- *
- * @label: Human readable name of this blkmap
- * @blk: Underlying block device
- * @slices: List of slices associated with this blkmap
- */
-struct blkmap {
- char *label;
- struct udevice *blk;
- struct list_head slices;
-};
-
static bool blkmap_slice_contains(struct blkmap_slice *bms, lbaint_t blknr)
{
return (blknr >= bms->blknr) && (blknr < (bms->blknr + bms->blkcnt));
diff --git a/drivers/block/blkmap_helper.c b/drivers/block/blkmap_helper.c
new file mode 100644
index 00..0f80035f57
--- /dev/null
+++ b/drivers/block/blkmap_helper.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * blkmap helper function
+ *
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include
+#include
+#include
+#include
+
+int blkmap_create_ramdisk(const char *label, ulong image_addr, int image_size,
+ struct udevice **devp)
+{
+ int ret;
+ lbaint_t blknum;
+ struct blkmap *bm;
+ struct blk_desc *desc;
+ struct udevice *bm_dev;
+
+ ret = blkmap_create(label, _dev);
+ if (ret) {
+ log_err("failed to create blkmap\n");
+ return ret;
+ }
+
+ bm = dev_get_plat(bm_dev);
+ desc = dev_get_uclass_plat(bm->blk);
+ blknum = image_size >> desc->log2blksz;
+ ret = blkmap_map_pmem(bm_dev, 0, blknum, image_addr);
+ if (ret) {
+ log_err("Unable to map %#llx at block %d : %d\n",
+ (unsigned long long)image_addr, 0, ret);
+ goto err;
+ }
+ log_info("Block %d+0x" LBAF " mapped to %#llx\n", 0, blknum,
+(unsigned long long)image_addr);
+
+ ret = device_probe(bm->blk);
+ if (ret)
+ goto err;
+
+ if (devp)
+ *devp = bm_dev;
+
+ return 0;
+
+err:
+ blkmap_destroy(bm_dev);
+
+ return ret;
+}
diff --git a/include/blkmap.h b/include/blkmap.h
index af54583c7d..0d87e6db6b 100644
--- a/include/blkmap.h
+++ b/include/blkmap.h
@@ -7,6 +7,23 @@
#ifndef _BLKMAP_H
#define _BLKMAP_H
+#include
+
+/**
+ * struct blkmap - Block map
+ *
+ * Data associated with a blkmap.
+ *
+ * @label: Human readable name of this blkmap
+ * @blk: Underlying block device
+ * @slices: List of slices associated with this blkmap
+ */
+struct blkmap {
+ char *label;
+ struct udevice *blk;
+ struct list_head slices;
+};
+
/**
* blkmap_map_linear() - Map region of other block device
*
@@ -74,4 +91,16 @@ int blkmap_create(const char *label, struct udevice **devp);
*/
int blkmap_destroy(struct udevice *dev);
+/**
+ * blkmap_create_ramdisk() - Create new ramdisk with blkmap
+ *
+ * @label: Label of the new blkmap
+ * @image_addr: Target memory start address of this mapping
+ * @image_size: Target memory size of this mapping
+ * @devp: Updated with the address of the created blkmap device
+ * Returns: 0 on success, negative error code on failure
+ */
+int blkmap_create_ramdisk(const char *label, ulong image_addr, int image_size,
+ struct udevice **devp);
+
#endif /* _BLKMAP_H */
--
2.34.1
[PATCH v5 2/7] net: wget: add wget with dns utility function
Current wget takes the target uri in this format:
":" e.g.) 192.168.1.1:/bar
The http server ip address must be resolved before
calling wget.
This commit adds the utility function runs wget with dhs.
User can call wget with the uri like "http://foo/bar;.
Signed-off-by: Masahisa Kojima
Reviewed-by: Ilias Apalodimas
---
include/net.h | 9 +
net/wget.c| 54 +++
2 files changed, 63 insertions(+)
diff --git a/include/net.h b/include/net.h
index e254df7d7f..57889d8b7a 100644
--- a/include/net.h
+++ b/include/net.h
@@ -926,4 +926,13 @@ void eth_set_enable_bootdevs(bool enable);
static inline void eth_set_enable_bootdevs(bool enable) {}
#endif
+/**
+ * wget_with_dns() - runs dns host IP address resulution before wget
+ *
+ * @dst_addr: destination address to download the file
+ * @uri: uri string of target file of wget
+ * Return: downloaded file size, negative if failed
+ */
+int wget_with_dns(ulong dst_addr, char *uri);
+
#endif /* __NET_H__ */
diff --git a/net/wget.c b/net/wget.c
index a48a8cb624..4801e28eb9 100644
--- a/net/wget.c
+++ b/net/wget.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -504,3 +505,56 @@ void wget_start(void)
wget_send(TCP_SYN, 0, 0, 0);
}
+
+#if (IS_ENABLED(CONFIG_CMD_DNS))
+int wget_with_dns(ulong dst_addr, char *uri)
+{
+ int ret;
+ char *s, *host_name, *file_name, *str_copy;
+
+ /*
+* Download file using wget.
+*
+* U-Boot wget takes the target uri in this format.
+* ":" e.g.) 192.168.1.1:/sample/test.iso
+* Need to resolve the http server ip address before starting wget.
+*/
+ str_copy = strdup(uri);
+ if (!str_copy)
+ return -ENOMEM;
+
+ s = str_copy + strlen("http://;);
+ host_name = strsep(, "/");
+ if (!s) {
+ log_err("Error: invalied uri, no file path\n");
+ ret = -EINVAL;
+ goto out;
+ }
+ file_name = s;
+
+ /* TODO: If the given uri has ip address for the http server, skip dns
*/
+ net_dns_resolve = host_name;
+ net_dns_env_var = "httpserverip";
+ if (net_loop(DNS) < 0) {
+ log_err("Error: dns lookup of %s failed, check setup\n",
net_dns_resolve);
+ ret = -EINVAL;
+ goto out;
+ }
+ s = env_get("httpserverip");
+ if (!s) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ strlcpy(net_boot_file_name, s, sizeof(net_boot_file_name));
+ strlcat(net_boot_file_name, ":/", sizeof(net_boot_file_name)); /*
append '/' which is removed by strsep() */
+ strlcat(net_boot_file_name, file_name, sizeof(net_boot_file_name));
+ image_load_addr = dst_addr;
+ ret = net_loop(WGET);
+
+out:
+ free(str_copy);
+
+ return ret;
+}
+#endif
--
2.34.1
[PATCH v5 1/7] net: wget: prevent overwriting reserved memory
This introduces the valid range check to store the received
blocks using lmb. The same logic is implemented in tftp.
Signed-off-by: Masahisa Kojima
Acked-by: Ilias Apalodimas
Reviewed-by: Simon Glass
---
net/wget.c | 80 +-
1 file changed, 73 insertions(+), 7 deletions(-)
diff --git a/net/wget.c b/net/wget.c
index 2dbfeb1a1d..a48a8cb624 100644
--- a/net/wget.c
+++ b/net/wget.c
@@ -4,16 +4,20 @@
* Copyright Duncan Hare 2017
*/
+#include
#include
#include
#include
#include
#include
+#include
#include
#include
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
static const char bootfile1[] = "GET ";
static const char bootfile3[] = " HTTP/1.0\r\n\r\n";
static const char http_eom[] = "\r\n\r\n";
@@ -55,6 +59,29 @@ static unsigned int retry_tcp_ack_num; /* TCP retry
acknowledge number*/
static unsigned int retry_tcp_seq_num; /* TCP retry sequence number */
static int retry_len; /* TCP retry length */
+static ulong wget_load_size;
+
+/**
+ * wget_init_max_size() - initialize maximum load size
+ *
+ * Return: 0 if success, -1 if fails
+ */
+static int wget_init_load_size(void)
+{
+ struct lmb lmb;
+ phys_size_t max_size;
+
+ lmb_init_and_reserve(, gd->bd, (void *)gd->fdt_blob);
+
+ max_size = lmb_get_free_size(, image_load_addr);
+ if (!max_size)
+ return -1;
+
+ wget_load_size = max_size;
+
+ return 0;
+}
+
/**
* store_block() - store block in memory
* @src: source of data
@@ -63,10 +90,25 @@ static int retry_len; /* TCP retry
length */
*/
static inline int store_block(uchar *src, unsigned int offset, unsigned int
len)
{
+ ulong store_addr = image_load_addr + offset;
ulong newsize = offset + len;
uchar *ptr;
- ptr = map_sysmem(image_load_addr + offset, len);
+ if (IS_ENABLED(CONFIG_LMB)) {
+ ulong end_addr = image_load_addr + wget_load_size;
+
+ if (!end_addr)
+ end_addr = ULONG_MAX;
+
+ if (store_addr < image_load_addr ||
+ store_addr + len > end_addr) {
+ printf("\nwget error: ");
+ printf("trying to overwrite reserved memory...\n");
+ return -1;
+ }
+ }
+
+ ptr = map_sysmem(store_addr, len);
memcpy(ptr, src, len);
unmap_sysmem(ptr);
@@ -240,25 +282,39 @@ static void wget_connected(uchar *pkt, unsigned int
tcp_seq_num,
net_boot_file_size = 0;
- if (len > hlen)
- store_block(pkt + hlen, 0, len - hlen);
+ if (len > hlen) {
+ if (store_block(pkt + hlen, 0, len - hlen) !=
0) {
+ wget_loop_state = NETLOOP_FAIL;
+ wget_fail("wget: store error\n",
tcp_seq_num, tcp_ack_num, action);
+ net_set_state(NETLOOP_FAIL);
+ return;
+ }
+ }
debug_cond(DEBUG_WGET,
"wget: Connected Pkt %p hlen %x\n",
pkt, hlen);
for (i = 0; i < pkt_q_idx; i++) {
+ int err;
+
ptr1 = map_sysmem(
(phys_addr_t)(pkt_q[i].pkt),
pkt_q[i].len);
- store_block(ptr1,
- pkt_q[i].tcp_seq_num -
- initial_data_seq_num,
- pkt_q[i].len);
+ err = store_block(ptr1,
+ pkt_q[i].tcp_seq_num -
+ initial_data_seq_num,
+ pkt_q[i].len);
unmap_sysmem(ptr1);
debug_cond(DEBUG_WGET,
"wget: Connctd pkt Q %p len %x\n",
pkt_q[i].pkt, pkt_q[i].len);
+ if (err) {
+ wget_loop_state = NETLOOP_FAIL;
+ wget_fail("wget: store error\n",
tcp_seq_num, tcp_ack_num, action);
+ net_set_state(NETLOOP_FAIL);
+ return;
+ }
}
}
}
@@ -330,6 +386,7 @@ static void wget_handler(uchar *pkt, u16 dport,
len) != 0) {
[PATCH v5 0/7] Add EFI HTTP boot support
This series adds the EFI HTTP boot support. User can add the URI device path with "efidebug boot add" command. efibootmgr handles the URI device path, download the specified file using wget, mount the downloaded image with blkmap, then boot with the default file(e.g. EFI/BOOT/BOOTAA64.EFI). This version still does not include the test. To enable EFI HTTP boot, we need to enable the following Kconfig options. CONFIG_CMD_DNS CONFIG_CMD_WGET CONFIG_BLKMAP On the Socionext Developerbox, enter the following commands then debian installer is downloaded into "loadaddr" and installer automatically starts. => dhcp => setenv serverip 192.168.1.1 => efidebug boot add -u 3 debian-netinst http://ftp.riken.jp/Linux/debian/debian-cd/12.1.0/arm64/iso-cd/debian-12.1.0-arm64-netinst.iso => efidebug boot order 3 => bootefi bootmgr Note that this debian installer can not proceed the installation bacause RAM disk of installer image is not recogniged by the kernel. I'm still investigating this issue, but drivers/nvdimm/of_pmem.c in linux will be one of the solution to recognize RAM disk from kernel. (In EDK2, the equivalent solution is called ACPI NFIT.) On QEMU, I can not make DNS work from the QEMU guest. The following commands work on qemu_arm64(manually set the http server ip in URI). => dhcp => setenv gatewayip 10.0.2.2 => setenv httpserverip 134.160.38.1 => efidebug boot add -u 3 debian-netinst http://134.160.38.1/Linux/debian/debian-cd/12.1.0/arm64/iso-cd/debian-12.1.0-arm64-netinst.iso => efidebug boot order 3 => bootefi bootmgr [TODO] - add test - stricter wget uri check - omit the dns process if the given uri has ip address -> this will be supported when the lwip migration completes - uri device path support in eficonfig [change log] v4 -> v5 - add missing else statement - add NULL check of efi_dp_find_obj() call - update document to remove "limitation" v3 -> v4 - patch#8 is added to simplify the bootmgr default boot process - add function comments v2 -> v3 - Patch#6 is added, reserve the whole ramdisk memory region - remove .efi file extension check for PE-COFF image - use "if IS_ENABLED(..)" as much as possible - 1024 should be sizeof(net_boot_file_name) - call net_set_state(NETLOOP_FAIL) when wget encounters error - describe DNS ip address host name limitation in document v1 -> v2 - carve out the network handling(wget and dns code) under net/wget.c - carve out ramdisk creation code under drivers/block/blkmap_helper.c - wget supports the valid range check to store the received blocks using lmb - support when the downloaded image have no partiton table but a file system - not start the .efi file in try_load_entry() - call efi_check_pe() for .efi file to check the file is PE-COFF image - add documentation for EFI HTTP Boot Masahisa Kojima (7): net: wget: prevent overwriting reserved memory net: wget: add wget with dns utility function blk: blkmap: add ramdisk creation utility function efi_loader: support boot from URI device path cmd: efidebug: add uri device path doc: uefi: add HTTP Boot support efi_loader: create BlockIo device boot option cmd/efidebug.c | 50 +++ doc/develop/uefi/uefi.rst| 30 drivers/block/Makefile | 1 + drivers/block/blkmap.c | 15 -- drivers/block/blkmap_helper.c| 53 +++ include/blkmap.h | 29 include/efi_loader.h | 3 + include/net.h| 17 +++ lib/efi_loader/efi_bootmgr.c | 248 --- lib/efi_loader/efi_device_path.c | 20 +++ lib/efi_loader/efi_dt_fixup.c| 2 +- net/wget.c | 206 - 12 files changed, 634 insertions(+), 40 deletions(-) create mode 100644 drivers/block/blkmap_helper.c -- 2.34.1
[PATCH 4/4] board: ti: am62x: add am62x_lpsk_* defconfigs and env files
Add defconfig fragments for AM62x LP SK and corresponding
customized environment file for AM62x LP SK.
Signed-off-by: Nitin Yadav
---
board/ti/am62x/am62x_lpsk_a53.config | 5 +
board/ti/am62x/am62x_lpsk_r5.config | 5 +
board/ti/am62x/am62xlpsk.env | 21 +
3 files changed, 31 insertions(+)
create mode 100644 board/ti/am62x/am62x_lpsk_a53.config
create mode 100644 board/ti/am62x/am62x_lpsk_r5.config
create mode 100644 board/ti/am62x/am62xlpsk.env
diff --git a/board/ti/am62x/am62x_lpsk_a53.config
b/board/ti/am62x/am62x_lpsk_a53.config
new file mode 100644
index 00..a568324997
--- /dev/null
+++ b/board/ti/am62x/am62x_lpsk_a53.config
@@ -0,0 +1,5 @@
+# Defconfig fragment to apply on top of am62x_evm_a53_defconfig
+
+CONFIG_DEFAULT_DEVICE_TREE="k3-am62-lp-sk"
+CONFIG_SPL_OF_LIST="k3-am62-lp-sk"
+CONFIG_OF_LIST="k3-am62-lp-sk"
diff --git a/board/ti/am62x/am62x_lpsk_r5.config
b/board/ti/am62x/am62x_lpsk_r5.config
new file mode 100644
index 00..1532f4e336
--- /dev/null
+++ b/board/ti/am62x/am62x_lpsk_r5.config
@@ -0,0 +1,5 @@
+# Defconfig fragment to apply on top of am62x_evm_r5_defconfig
+
+CONFIG_DEFAULT_DEVICE_TREE="k3-am62-r5-lp-sk"
+CONFIG_SPL_OF_LIST="k3-am62-r5-lp-sk"
+CONFIG_OF_LIST="k3-am62-r5-lp-sk"
diff --git a/board/ti/am62x/am62xlpsk.env b/board/ti/am62x/am62xlpsk.env
new file mode 100644
index 00..3b79ae1b3f
--- /dev/null
+++ b/board/ti/am62x/am62xlpsk.env
@@ -0,0 +1,21 @@
+#include
+#include
+#include
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x0280
+ ${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+boot_targets=ti_mmc mmc0 mmc1 usb pxe dhcp
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
+
+splashfile=ti.gz
+splashimage=0x8020
+splashpos=m,m
+splashsource=sf
--
2.25.1
[PATCH 2/4] arm: dts: Add support for AM62x LP SK
The AM62x LP SK board is similar to the AM62x SK board,
but has some significant changes that requires different
device tree.
The differences are mainly:
- AM62x SoC in the AMC package that meets AECQ100 automotive standard.
- LPDDR4 versus DDR4 on the AM62x SK.
- TPS65219 PMIC instead of discrete regulators.
- IO expander pin names are wired differently.
- Second ethernet port is currently disabled as the boards do not have
the part physically installed.
- OSPI NAND vs OSPI NOR.
- No WLAN chip instead a SDIO M.2 connector.
Signed-off-by: Nitin Yadav
---
arch/arm/dts/Makefile |2 +
arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi|9 +
arch/arm/dts/k3-am62-lp-sk.dts| 231 ++
arch/arm/dts/k3-am62-r5-lp-sk.dts | 21 +
arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi | 2190 +
5 files changed, 2453 insertions(+)
create mode 100644 arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
create mode 100644 arch/arm/dts/k3-am62-lp-sk.dts
create mode 100644 arch/arm/dts/k3-am62-r5-lp-sk.dts
create mode 100644 arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bde2176ec7..72ea57885f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1337,6 +1337,8 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
k3-am625-r5-sk.dtb \
+ k3-am62-lp-sk.dtb \
+ k3-am62-r5-lp-sk.dtb \
k3-am625-beagleplay.dtb \
k3-am625-r5-beagleplay.dtb \
k3-am625-verdin-wifi-dev.dtb \
diff --git a/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
new file mode 100644
index 00..7da94fe4b6
--- /dev/null
+++ b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM62x LP SK dts file for SPLs
+ * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-am62x-sk-common-u-boot.dtsi"
+
+#include "k3-am62-lp-sk-binman.dtsi"
diff --git a/arch/arm/dts/k3-am62-lp-sk.dts b/arch/arm/dts/k3-am62-lp-sk.dts
new file mode 100644
index 00..5e6feb8cd1
--- /dev/null
+++ b/arch/arm/dts/k3-am62-lp-sk.dts
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM62x LP SK: https://www.ti.com/tool/SK-AM62-LP
+ *
+ * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am62x-sk-common.dtsi"
+
+/ {
+ compatible = "ti,am62-lp-sk", "ti,am625";
+ model = "Texas Instruments AM62x LP SK";
+
+ vmain_pd: regulator-0 {
+ /* TPS65988 PD CONTROLLER OUTPUT */
+ compatible = "regulator-fixed";
+ regulator-name = "vmain_pd";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_5v0: regulator-1 {
+ /* Output of TPS630702RNMR */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_5v0";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_pd>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_3v3_sys: regulator-2 {
+ /* output of LM61460-Q1 */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_sys";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_pd>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: regulator-3 {
+ /* TPS22918DBVR */
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <_3v3_sys>;
+ gpio = < 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ vddshv_sdio: regulator-4 {
+ compatible = "regulator-gpio";
+ regulator-name = "vddshv_sdio";
+ pinctrl-names = "default";
+ pinctrl-0 = <_sdio_pins_default>;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ vin-supply = <_reg>;
+ gpios = <_gpio0 31 GPIO_ACTIVE_HIGH>;
+ states = <180 0x0>,
+<330 0x1>;
+ };
+};
+
+_pmx0 {
+ vddshv_sdio_pins_default: vddshv-sdio-default-pins {
+ pinctrl-single,pins =
