Re: [PATCH v2 2/2] lmb: Fix adjacent region merge in lmb_add_region_flags()
Hello Patrice,
On 4/13/2024 1:54 PM, Patrice CHOTARD wrote:
On 4/12/24 17:53, Patrice Chotard wrote:
In case a new region is adjacent to a previous region with
similar flag, this region is merged with its predecessor, but no
check are done if this new added region is overlapping another region
present in lmb (see reserved[3] which overlaps reserved[4]).
[..]
phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align)
{
return lmb_alloc_base(lmb, size, align, LMB_ALLOC_ANYWHERE);
I think this series (v2) is not correct even if now the CI tests are OK.
After re-reading carefully the lib_test_lmb_overlapping_reserve() test
it appears to me there is a contradiction.
It's indicating that "check that calling lmb_reserve with overlapping regions
fails"
but the very last test of lib_test_lmb_overlapping_reserve() has this comment :
/* allocate 3rd region, coalesce with first and overlap with second */
and this test allows this overlap case.
It's not clear if LMB region can overlap each other or not ?
I would say partial overlap and coalescing with before one
May be Below can help
/* allocate 2nd region , This should coalesced all region into one
you will get one region as
Address --- Size
0x4001 --- 0x3
Next after this /* allocate 2nd region, which should be added as first
region */
we will have two region like
Address --- Size
(0x4000 -- 0x8000)
(0x4001 --- 0x3)
Now third request comes in
/* allocate 3rd region, coalesce with first and overlap with second */
which is address of 0x40008000 and size of 0x1, Now this region to
be added
is coalescing with first (0x4000 -- 0x8000) and part of this overlap
with (0x4001 --- 0x3).
So, what this patch does , merge all these into one region
as (0x4000 -- 0x4)
Udit, your patch edb5824be17f ("lmb: remove overlapping region with next range")
is authorizing LMB overlapping right ?
As said before this is checking overlap and coalescing and acting
accordingly.
Patrice
Re: [PATCH v6 5/5] imx93: convert to OF_UPSTREAM
Hello, I was able to test this series on the imx93-phyboard-segin. Up to that specific commit no issue to report. That specific commit however, using an updated dts subtree at 2639a0e2fd, fails to boot. There is no more garbage on the UART, but the boot stops after BL31 is started: U-Boot SPL 2024.04-rc5-00388-gf81e4e85fd6-dirty (Apr 14 2024 - 12:15:51 +0200) SOC: 0xa0009300 LC: 0x40040 M33 prepare ok Normal Boot WDT: Started wdog@4249 with servicing every 1000ms (40s timeout) Trying to boot from BOOTROM Boot Stage: Primary boot image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x45c00 by ROM_API NOTICE: BL31: v2.8(release):lf-6.1.36-2.1.0-0-g1a3beeab6-dirty NOTICE: BL31: Built : 11:39:38, Aug 7 2023 Not sure where that could come from. Mathieu
[PATCH] net: wget: Support retransmission a dropped packet
The server sends multiple packets without waiting for an ACK
by window control and if some packets are dropped,
wget will return an ACK including the dropped packets.
Following log indicates this issue.
wget_handler() wget: Transferring, seq=97bbdd4a, ack=30,len=580
wget_handler() wget: Transferring, seq=97bbedca, ack=30,len=580
First packet of TCP sequence number is 0x97bbdd4a.
Second packet of TCP sequence number should be 0x97bbe2ca,
however it is 0x97bbedca and returns its ACK, so the server
suppose that 0x97bbe2ca and 0x97bbedca are received appropriately.
In this case, 0x97bbe2ca was lost and the data of wget was broken.
In this patch, next_data_seq_num holds the next expected
TCP sequence number.
If the TCP sequence number different from next_data_seq_num,
trying to retransmit the packet.
Signed-off-by: Yasuharu Shibata
---
net/wget.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/net/wget.c b/net/wget.c
index 817c5ebd5d..71bac92d84 100644
--- a/net/wget.c
+++ b/net/wget.c
@@ -50,6 +50,7 @@ static unsigned long content_length;
static unsigned int packets;
static unsigned int initial_data_seq_num;
+static unsigned int next_data_seq_num;
static enum wget_state current_wget_state;
@@ -272,17 +273,18 @@ static void wget_connected(uchar *pkt, unsigned int
tcp_seq_num,
current_wget_state = WGET_TRANSFERRING;
+ initial_data_seq_num = tcp_seq_num + hlen;
+ next_data_seq_num= tcp_seq_num + len;
+
if (strstr((char *)pkt, http_ok) == 0) {
debug_cond(DEBUG_WGET,
"wget: Connected Bad Xfer\n");
- initial_data_seq_num = tcp_seq_num + hlen;
wget_loop_state = NETLOOP_FAIL;
wget_send(action, tcp_seq_num, tcp_ack_num, len);
} else {
debug_cond(DEBUG_WGET,
"wget: Connctd pkt %p hlen %x\n",
pkt, hlen);
- initial_data_seq_num = tcp_seq_num + hlen;
pos = strstr((char *)pkt, content_len);
if (!pos) {
@@ -396,6 +398,12 @@ static void wget_handler(uchar *pkt, u16 dport,
"wget: Transferring, seq=%x, ack=%x,len=%x\n",
tcp_seq_num, tcp_ack_num, len);
+ if (next_data_seq_num != tcp_seq_num) {
+ debug_cond(DEBUG_WGET, "wget: seq=%x packet was
lost\n", next_data_seq_num);
+ return;
+ }
+ next_data_seq_num = tcp_seq_num + len;
+
if (tcp_seq_num >= initial_data_seq_num &&
store_block(pkt, tcp_seq_num - initial_data_seq_num,
len) != 0) {
--
2.25.1
RE: [PATCH v6 5/5] imx93: convert to OF_UPSTREAM
> Subject: Re: [PATCH v6 5/5] imx93: convert to OF_UPSTREAM > > > Hello, > > I was able to test this series on the imx93-phyboard-segin. Up to that > specific > commit no issue to report. > > That specific commit however, using an updated dts subtree at 2639a0e2fd, > fails to boot. > > There is no more garbage on the UART, but the boot stops after BL31 is > started: > > U-Boot SPL 2024.04-rc5-00388-gf81e4e85fd6-dirty (Apr 14 2024 - 12:15:51 > +0200) > SOC: 0xa0009300 > LC: 0x40040 > M33 prepare ok > Normal Boot > WDT: Started wdog@4249 with servicing every 1000ms (40s timeout) > Trying to boot from BOOTROM > Boot Stage: Primary boot > image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x45c00 > by ROM_API > NOTICE: BL31: v2.8(release):lf-6.1.36-2.1.0-0-g1a3beeab6-dirty > NOTICE: BL31: Built : 11:39:38, Aug 7 2023 > > Not sure where that could come from. Which dts upstream tag are u using? Do you have time to debug the issue? I not have the board, so not sure what happens here. Regards, Peng. > > Mathieu
Re: [PATCH v2 0/6] mtd: nand: raw: Collected improvements
Hi Alexander, On Wed, Mar 20, 2024 at 10:02 AM Alexander Dahl wrote: > > Hello everyone, > > while working on NAND flash support for a custom board based on the at91 > SAM9X60 SoC I stumbled over some issues in the raw nand subsystem. > > Four of six patches are minor fixes. > > Patch 4 introduces a new subcommand for the new atmel nand controller > driver. Patch 6 introduces a new subcommand for the nand command to > override ONFI timing mode. Both are are for debugging purposes only and > thus optional, and need to be enabled through menu. Both helped me a > lot when investigating issues. > > Series is based on upstream next branch, but should also apply to master > cleanly. > > Greets > Alex > > v1: > > Link: > https://lore.kernel.org/u-boot/20240307091014.39796-1-...@thorsis.com/T/#t > > v2: > > - rebased on recent next > - collected tags > - improved patch 4 after feedback from Mihai > - added new patch 5 with another help text fix > - added new patch 6 with a new debug command > - reworded cover letter > > See per patch changes in patches for more detailed changes. > > Alexander Dahl (6): > mtd: nand: raw: Use macro nand_to_mtd() where appropriate > mtd: nand: raw: Port another option flag from Linux > mtd: nand: raw: Fix (most) Kconfig indentation > mtd: nand: raw: atmel: Introduce optional debug commands > mtd: nand: raw: atmel: Fix comment in timings preparation > cmd: nand: Add new optional sub-command 'onfi' > > cmd/Kconfig | 10 + > cmd/nand.c | 61 > drivers/mtd/nand/raw/Kconfig | 115 +++ > drivers/mtd/nand/raw/atmel/nand-controller.c | 299 ++- > drivers/mtd/nand/raw/nand_base.c | 8 +- > include/linux/mtd/rawnand.h | 8 + > 6 files changed, 441 insertions(+), 60 deletions(-) > > > base-commit: f048104999db28d49362201eaebfc91adb14f47c > -- > 2.39.2 > Applied to nand-next the first 4 patches. For the others, we will conduct further testing before applying them. Thanks and regards, Dario -- Dario Binacchi Senior Embedded Linux Developer dario.binac...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH] cmd: sf: Fix sf probe crash
Hi Weizhao,
On Fri, Mar 15, 2024 at 7:07 PM Jonas Karlman wrote:
>
> Hi,
>
> On 2024-01-04 12:46, Weizhao Ouyang wrote:
> > Handle the return value of spi_flash_probe_bus_cs() to avoid sf probe
> > crashes.
> >
> > Signed-off-by: Weizhao Ouyang
>
> This fixes a null pointer dereference when running "sf probe" and there
> are no spi devices enabled in the device tree for my boards, so:
>
> Fixes: 3feea0ba196a ("spi: spi_flash_probe_bus_cs() rely on DT for spi speed
> and mode")
>
> Reviewed-by: Jonas Karlman
>
> Regards,
> Jonas
>
> > ---
> > cmd/sf.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/cmd/sf.c b/cmd/sf.c
> > index 730996c02b..e3866899f6 100644
> > --- a/cmd/sf.c
> > +++ b/cmd/sf.c
> > @@ -135,8 +135,9 @@ static int do_spi_flash_probe(int argc, char *const
> > argv[])
> > }
> > flash = NULL;
> > if (use_dt) {
> > - spi_flash_probe_bus_cs(bus, cs, &new);
> > - flash = dev_get_uclass_priv(new);
> > + ret = spi_flash_probe_bus_cs(bus, cs, &new);
> > + if (!ret)
> > + flash = dev_get_uclass_priv(new);
> > } else {
> > flash = spi_flash_probe(bus, cs, speed, mode);
> > }
>
Applied to nand-next
Thanks and regards
Dario
--
Dario Binacchi
Senior Embedded Linux Developer
dario.binac...@amarulasolutions.com
__
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH v5] cmd: mtd: OTP access support
Hi Arseniy,
On Tue, Mar 26, 2024 at 11:49 PM Arseniy Krasnov
wrote:
>
> Add access to OTP region. It supports info, dump, write and lock
> operations. Usage example:
>
> 'mtd otpread nand0 u 0 1024' - dump 1024 bytes of user area starting
> from offset 0 of device 'nand0'.
>
> 'mtd otpwrite nand0 10 11223344' - write binary data 0x11, 0x22, 0x33,
> 0x44 to offset 10 to user area of device 'nand0'.
>
> 'mtd otplock nand0 0 1024' - lock 1024 bytes of user area starting
> from offset 0 of device 'nand0'.
>
> 'mtd otpinfo nand0 f' - show info about factory area of device 'nand0'.
>
> Signed-off-by: Arseniy Krasnov
> ---
> Changelog:
> v1 -> v2:
> * Remove warning that OTP can't be erased after write.
> v2 -> v3:
> * Commit message updated by adding usage.
> * R-b added.
> v3 -> v4:
> * Fix build failure due to invalid format strings for 'printf()'.
> * Rebase over latest version of cmd/mtd.c.
> v4 -> v5:
> * Implement commands from this patch as config option due to too big
> final size of the uboot image.
> * R-b removed because of patch update.
>
> cmd/Kconfig | 7 ++
> cmd/mtd.c | 234
> 2 files changed, 241 insertions(+)
>
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index 7292a150f5..832098e66e 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -1366,6 +1366,13 @@ config CMD_MTD
> help
> MTD commands support.
>
> +config CMD_MTD_OTP
> + bool "mtd otp"
> + depends on CMD_MTD
> + select HEXDUMP
> + help
> + MTD commands for OTP access.
> +
> config CMD_MUX
> bool "mux"
> depends on MULTIPLEXER
> diff --git a/cmd/mtd.c b/cmd/mtd.c
> index e63c011e79..c66105e373 100644
> --- a/cmd/mtd.c
> +++ b/cmd/mtd.c
> @@ -11,6 +11,9 @@
> #include
> #include
> #include
> +#if CONFIG_IS_ENABLED(CMD_MTD_OTP)
> +#include
> +#endif
> #include
> #include
> #include
> @@ -202,6 +205,221 @@ static bool mtd_oob_write_is_empty(struct mtd_oob_ops
> *op)
> return true;
> }
>
> +#if CONFIG_IS_ENABLED(CMD_MTD_OTP)
> +static int do_mtd_otp_read(struct cmd_tbl *cmdtp, int flag, int argc,
> + char *const argv[])
> +{
> + struct mtd_info *mtd;
> + size_t retlen;
> + off_t from;
> + size_t len;
> + bool user;
> + int ret;
> + u8 *buf;
> +
> + if (argc != 5)
> + return CMD_RET_USAGE;
> +
> + if (!strcmp(argv[2], "u"))
> + user = true;
> + else if (!strcmp(argv[2], "f"))
> + user = false;
> + else
> + return CMD_RET_USAGE;
> +
> + mtd = get_mtd_by_name(argv[1]);
> + if (IS_ERR_OR_NULL(mtd))
> + return CMD_RET_FAILURE;
> +
> + from = simple_strtoul(argv[3], NULL, 0);
> + len = simple_strtoul(argv[4], NULL, 0);
> +
> + ret = CMD_RET_FAILURE;
> +
> + buf = malloc(len);
> + if (!buf)
> + goto put_mtd;
> +
> + printf("Reading %s OTP from 0x%lx, %zu bytes\n",
> + user ? "user" : "factory", from, len);
> +
> + if (user)
> + ret = mtd_read_user_prot_reg(mtd, from, len, &retlen, buf);
> + else
> + ret = mtd_read_fact_prot_reg(mtd, from, len, &retlen, buf);
> + if (ret) {
> + free(buf);
> + pr_err("OTP read failed: %d\n", ret);
> + ret = CMD_RET_FAILURE;
> + goto put_mtd;
> + }
> +
> + if (retlen != len)
> + pr_err("OTP read returns %zu, but %zu expected\n",
> + retlen, len);
> +
> + print_hex_dump("", 0, 16, 1, buf, retlen, true);
> +
> + free(buf);
> +
> + ret = CMD_RET_SUCCESS;
> +
> +put_mtd:
> + put_mtd_device(mtd);
> +
> + return ret;
> +}
> +
> +static int do_mtd_otp_lock(struct cmd_tbl *cmdtp, int flag, int argc,
> + char *const argv[])
> +{
> + struct mtd_info *mtd;
> + off_t from;
> + size_t len;
> + int ret;
> +
> + if (argc != 4)
> + return CMD_RET_USAGE;
> +
> + mtd = get_mtd_by_name(argv[1]);
> + if (IS_ERR_OR_NULL(mtd))
> + return CMD_RET_FAILURE;
> +
> + from = simple_strtoul(argv[2], NULL, 0);
> + len = simple_strtoul(argv[3], NULL, 0);
> +
> + ret = mtd_lock_user_prot_reg(mtd, from, len);
> + if (ret) {
> + pr_err("OTP lock failed: %d\n", ret);
> + ret = CMD_RET_FAILURE;
> + goto put_mtd;
> + }
> +
> + ret = CMD_RET_SUCCESS;
> +
> +put_mtd:
> + put_mtd_device(mtd);
> +
> + return ret;
> +}
> +
> +static int do_mtd_otp_write(struct cmd_tbl *cmdtp, int flag, int argc,
> + char *const argv[])
> +{
> + struct mtd_info *mtd;
> + size_t retlen;
> + size_t binlen;
> + u8 *binbuf;
> + off_t from;
> + int ret;
> +
> +
Re: [PATCH v3] mtd: rawnand: Meson NAND controller support
Hi Arseniy, On Mon, Feb 12, 2024 at 11:19 AM Michael Nazzareno Trimarchi wrote: > > Hi > > On Sat, Feb 10, 2024 at 11:48 PM Arseniy Krasnov > wrote: > > > > Basic support for Amlogic Meson NAND controller on AXG. This version > > works at only first EDO mode. > > > > Based on Linux version 6.7.0-rc4. > > > > Signed-off-by: Arseniy Krasnov > > --- > > Changelog: > > v1 -> v2: > > * Update commit message with 'Based on Linux ...'. > > * Add Linux driver author to .c file header. > > * Add comment for defines 'NFC_DEFAULT_BUS_CYCLE' and > > 'NFC_DEFAULT_BUS_TIMING'. > > * Use 'dev_read_addr_index_ptr()' instead of 'dev_read_addr()'. > > v2 -> v3: > > * Update commit message about EDO mode limitation. > > * Fix scrambling bit value in CMDRWGEN macro. > > * Add scrambling support for reading. > > > > drivers/mtd/nand/raw/Kconfig |9 + > > drivers/mtd/nand/raw/Makefile |1 + > > drivers/mtd/nand/raw/meson_nand.c | 1248 + > > 3 files changed, 1258 insertions(+) > > create mode 100644 drivers/mtd/nand/raw/meson_nand.c > > > > diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig > > index 46a1460746..e946305ccc 100644 > > --- a/drivers/mtd/nand/raw/Kconfig > > +++ b/drivers/mtd/nand/raw/Kconfig > > @@ -479,6 +479,15 @@ config NAND_ARASAN > > controller. This uses the hardware ECC for read and > > write operations. > > > > +config NAND_MESON > > + bool "Meson NAND support" > > + select SYS_NAND_SELF_INIT > > + depends on DM_MTD && ARCH_MESON > > + imply CMD_NAND > > + help > > + This enables Nand driver support for Meson raw NAND flash > > + controller. > > + > > config NAND_MXC > > bool "MXC NAND support" > > depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 > > diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile > > index add2b4cf65..5b4efd52c9 100644 > > --- a/drivers/mtd/nand/raw/Makefile > > +++ b/drivers/mtd/nand/raw/Makefile > > @@ -61,6 +61,7 @@ obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o > > obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o > > obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o > > obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o > > +obj-$(CONFIG_NAND_MESON) += meson_nand.o > > obj-$(CONFIG_NAND_MXC) += mxc_nand.o > > obj-$(CONFIG_NAND_MXS) += mxs_nand.o > > obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o > > diff --git a/drivers/mtd/nand/raw/meson_nand.c > > b/drivers/mtd/nand/raw/meson_nand.c > > new file mode 100644 > > index 00..5d411c4594 > > --- /dev/null > > +++ b/drivers/mtd/nand/raw/meson_nand.c > > @@ -0,0 +1,1248 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * Amlogic Meson Nand Flash Controller Driver > > + * > > + * Copyright (c) 2018 Amlogic, inc. > > + * Author: Liang Yang > > + * > > + * Copyright (c) 2023 SaluteDevices, Inc. > > + * Author: Arseniy Krasnov > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define NFC_CMD_IDLE (0xc << 14) > > +#define NFC_CMD_CLE(0x5 << 14) > > +#define NFC_CMD_ALE(0x6 << 14) > > +#define NFC_CMD_DWR(0x4 << 14) > > +#define NFC_CMD_DRD(0x8 << 14) > > +#define NFC_CMD_ADL((0 << 16) | (3 << 20)) > > +#define NFC_CMD_ADH((1 << 16) | (3 << 20)) > > +#define NFC_CMD_AIL((2 << 16) | (3 << 20)) > > +#define NFC_CMD_AIH((3 << 16) | (3 << 20)) > > +#define NFC_CMD_SEED ((8 << 16) | (3 << 20)) > > +#define NFC_CMD_M2N((0 << 17) | (2 << 20)) > > +#define NFC_CMD_N2M((1 << 17) | (2 << 20)) > > +#define NFC_CMD_RB BIT(20) > > +#define NFC_CMD_SCRAMBLER_ENABLE BIT(19) > > +#define NFC_CMD_SCRAMBLER_DISABLE 0 > > +#define NFC_CMD_SHORTMODE_DISABLE 0 > > +#define NFC_CMD_RB_INT BIT(14) > > +#define NFC_CMD_RB_INT_NO_PIN ((0xb << 10) | BIT(18) | BIT(16)) > > + > > +#define NFC_CMD_GET_SIZE(x)(((x) >> 22) & GENMASK(4, 0)) > > + > > +#define NFC_REG_CMD0x00 > > +#define NFC_REG_CFG0x04 > > +#define NFC_REG_DADR 0x08 > > +#define NFC_REG_IADR 0x0c > > +#define NFC_REG_BUF0x10 > > +#define NFC_REG_INFO 0x14 > > +#define NFC_REG_DC 0x18 > > +#define NFC_REG_ADR0x1c > > +#define NFC_REG_DL 0x20 > > +#define NFC_REG_DH 0x24 > > +#define NFC_REG_CADR 0x28 > > +#define NFC_REG_SADR 0x2c > > +#define NFC_REG_PINS 0x30 > > +#define NFC_REG_VER0x38 > > + > > +#define CMDRWGEN(cmd_dir, ran, bch, sh
Re: [PATCH V4] mtd: spinand: Add support for XTX SPINAND
Hi Bruce,
On Tue, Mar 12, 2024 at 2:43 AM Bruce Suen wrote:
>
> Add support for XTX XT26G0xA and XT26xxxD. The driver is ported from
> linux-6.7.1. This driver is tested on Banana BPI-R3 with XT26G01A and
> XT26G12D.
>
> Signed-off-by: Bruce Suen
> Reviewed-by: Frieder Schrempf
> ---
> V3->V4:
> - modify commit message minor flaws
> ---
> drivers/mtd/nand/spi/Makefile | 2 +-
> drivers/mtd/nand/spi/core.c | 1 +
> drivers/mtd/nand/spi/xtx.c| 266 ++
> include/linux/mtd/spinand.h | 1 +
> 4 files changed, 269 insertions(+), 1 deletion(-)
> create mode 100644 drivers/mtd/nand/spi/xtx.c
>
> diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile
> index f172f4787f..65b836b34c 100644
> --- a/drivers/mtd/nand/spi/Makefile
> +++ b/drivers/mtd/nand/spi/Makefile
> @@ -1,5 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
>
> spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o
> -spinand-objs += toshiba.o winbond.o
> +spinand-objs += toshiba.o winbond.o xtx.o
> obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
> diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
> index 8ca33459f9..62c28aa422 100644
> --- a/drivers/mtd/nand/spi/core.c
> +++ b/drivers/mtd/nand/spi/core.c
> @@ -829,6 +829,7 @@ static const struct spinand_manufacturer
> *spinand_manufacturers[] = {
> &toshiba_spinand_manufacturer,
> &winbond_spinand_manufacturer,
> &esmt_c8_spinand_manufacturer,
> + &xtx_spinand_manufacturer,
> };
>
> static int spinand_manufacturer_match(struct spinand_device *spinand,
> diff --git a/drivers/mtd/nand/spi/xtx.c b/drivers/mtd/nand/spi/xtx.c
> new file mode 100644
> index 00..aee1849a71
> --- /dev/null
> +++ b/drivers/mtd/nand/spi/xtx.c
> @@ -0,0 +1,266 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Author:
> + * Felix Matouschek
> + */
> +
> +#include
> +#ifndef __UBOOT__
> +#include
> +#include
> +#endif
> +#include
> +
> +#define SPINAND_MFR_XTX0x0B
> +
> +#define XT26G0XA_STATUS_ECC_MASK GENMASK(5, 2)
> +#define XT26G0XA_STATUS_ECC_NO_DETECTED(0 << 2)
> +#define XT26G0XA_STATUS_ECC_8_CORRECTED(3 << 4)
> +#define XT26G0XA_STATUS_ECC_UNCOR_ERROR(2 << 4)
> +
> +#define XT26XXXD_STATUS_ECC3_ECC2_MASK GENMASK(7, 6)
> +#define XT26XXXD_STATUS_ECC_NO_DETECTED (0)
> +#define XT26XXXD_STATUS_ECC_1_7_CORRECTED (1)
> +#define XT26XXXD_STATUS_ECC_8_CORRECTED (3)
> +#define XT26XXXD_STATUS_ECC_UNCOR_ERROR (2)
> +
> +static SPINAND_OP_VARIANTS(read_cache_variants,
> + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
> + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
> + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
> + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
> + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
> +
> +static SPINAND_OP_VARIANTS(write_cache_variants,
> + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
> + SPINAND_PROG_LOAD(true, 0, NULL, 0));
> +
> +static SPINAND_OP_VARIANTS(update_cache_variants,
> + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
> + SPINAND_PROG_LOAD(false, 0, NULL, 0));
> +
> +static int xt26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section,
> + struct mtd_oob_region *region)
> +{
> + if (section)
> + return -ERANGE;
> +
> + region->offset = 48;
> + region->length = 16;
> +
> + return 0;
> +}
> +
> +static int xt26g0xa_ooblayout_free(struct mtd_info *mtd, int section,
> + struct mtd_oob_region *region)
> +{
> + if (section)
> + return -ERANGE;
> +
> + region->offset = 1;
> + region->length = 47;
> +
> + return 0;
> +}
> +
> +static const struct mtd_ooblayout_ops xt26g0xa_ooblayout = {
> + .ecc = xt26g0xa_ooblayout_ecc,
> + .rfree = xt26g0xa_ooblayout_free,
> +};
> +
> +static int xt26g0xa_ecc_get_status(struct spinand_device *spinand,
> + u8 status)
> +{
> + status = status & XT26G0XA_STATUS_ECC_MASK;
> +
> + switch (status) {
> + case XT26G0XA_STATUS_ECC_NO_DETECTED:
> + return 0;
> + case XT26G0XA_STATUS_ECC_8_CORRECTED:
> + return 8;
> + case XT26G0XA_STATUS_ECC_UNCOR_ERROR:
> + return -EBADMSG;
> + default:
> + break;
> + }
> +
> + /* At this point values greater than (2 << 4) are invalid */
> + if (status > XT26G0XA_STATUS_ECC_UNCOR_ERROR)
> + return -EINVAL;
> +
> + /* (1 << 2) through (7 << 2) are 1-7 corrected errors */
> + return status >> 2;
> +}
> +
> +static int xt26xxxd_ooblayout_ecc(struct mtd_info *mtd, int section,
> +
[PATCH] fs/erofs: add DEFLATE algorithm support
This patch adds DEFLATE compression algorithm support. It's a good choice
to trade off between compression ratios and performance compared to LZ4.
Alternatively, DEFLATE could be used for some specific files since EROFS
supports multiple compression algorithms in one image.
Signed-off-by: Jianan Huang
---
fs/erofs/Kconfig | 15
fs/erofs/decompress.c | 83 +++
fs/erofs/erofs_fs.h | 1 +
3 files changed, 99 insertions(+)
diff --git a/fs/erofs/Kconfig b/fs/erofs/Kconfig
index ee4e777c5c..c8463357ca 100644
--- a/fs/erofs/Kconfig
+++ b/fs/erofs/Kconfig
@@ -19,3 +19,18 @@ config FS_EROFS_ZIP
help
Enable fixed-sized output compression for EROFS.
If you don't want to enable compression feature, say N.
+
+config FS_EROFS_ZIP_DEFLATE
+ bool "EROFS DEFLATE compressed data support"
+ depends on FS_EROFS_ZIP
+ select ZLIB
+ help
+ Saying Y here includes support for reading EROFS file systems
+ containing DEFLATE compressed data. It gives better compression
+ ratios than the default LZ4 format, while it costs more CPU
+ overhead.
+
+ DEFLATE support is an experimental feature for now and so most
+ file systems will be readable without selecting this option.
+
+ If unsure, say N.
diff --git a/fs/erofs/decompress.c b/fs/erofs/decompress.c
index e04e5c34a8..ec74816534 100644
--- a/fs/erofs/decompress.c
+++ b/fs/erofs/decompress.c
@@ -1,6 +1,85 @@
// SPDX-License-Identifier: GPL-2.0+
#include "decompress.h"
+#if IS_ENABLED(CONFIG_ZLIB)
+#include
+
+/* report a zlib or i/o error */
+static int zerr(int ret)
+{
+ switch (ret) {
+ case Z_STREAM_ERROR:
+ return -EINVAL;
+ case Z_DATA_ERROR:
+ return -EIO;
+ case Z_MEM_ERROR:
+ return -ENOMEM;
+ case Z_ERRNO:
+ default:
+ return -EFAULT;
+ }
+}
+
+static int z_erofs_decompress_deflate(struct z_erofs_decompress_req *rq)
+{
+ u8 *dest = (u8 *)rq->out;
+ u8 *src = (u8 *)rq->in;
+ u8 *buff = NULL;
+ unsigned int inputmargin = 0;
+ z_stream strm;
+ int ret;
+
+ while (!src[inputmargin & (erofs_blksiz() - 1)])
+ if (!(++inputmargin & (erofs_blksiz() - 1)))
+ break;
+
+ if (inputmargin >= rq->inputsize)
+ return -EFSCORRUPTED;
+
+ if (rq->decodedskip) {
+ buff = malloc(rq->decodedlength);
+ if (!buff)
+ return -ENOMEM;
+ dest = buff;
+ }
+
+ /* allocate inflate state */
+ strm.zalloc = Z_NULL;
+ strm.zfree = Z_NULL;
+ strm.opaque = Z_NULL;
+ strm.avail_in = 0;
+ strm.next_in = Z_NULL;
+ ret = inflateInit2(&strm, -15);
+ if (ret != Z_OK) {
+ free(buff);
+ return zerr(ret);
+ }
+
+ strm.next_in = src + inputmargin;
+ strm.avail_in = rq->inputsize - inputmargin;
+ strm.next_out = dest;
+ strm.avail_out = rq->decodedlength;
+
+ ret = inflate(&strm, rq->partial_decoding ? Z_SYNC_FLUSH : Z_FINISH);
+ if (ret != Z_STREAM_END || strm.total_out != rq->decodedlength) {
+ if (ret != Z_OK || !rq->partial_decoding) {
+ ret = zerr(ret);
+ goto out_inflate_end;
+ }
+ }
+
+ if (rq->decodedskip)
+ memcpy(rq->out, dest + rq->decodedskip,
+ rq->decodedlength - rq->decodedskip);
+
+out_inflate_end:
+ inflateEnd(&strm);
+ if (buff)
+ free(buff);
+ return ret;
+}
+#endif
+
#if IS_ENABLED(CONFIG_LZ4)
#include
static int z_erofs_decompress_lz4(struct z_erofs_decompress_req *rq)
@@ -93,6 +172,10 @@ int z_erofs_decompress(struct z_erofs_decompress_req *rq)
#if IS_ENABLED(CONFIG_LZ4)
if (rq->alg == Z_EROFS_COMPRESSION_LZ4)
return z_erofs_decompress_lz4(rq);
+#endif
+#if IS_ENABLED(CONFIG_ZLIB)
+ if (rq->alg == Z_EROFS_COMPRESSION_DEFLATE)
+ return z_erofs_decompress_deflate(rq);
#endif
return -EOPNOTSUPP;
}
diff --git a/fs/erofs/erofs_fs.h b/fs/erofs/erofs_fs.h
index 158e2c68a1..5bac4fe1a1 100644
--- a/fs/erofs/erofs_fs.h
+++ b/fs/erofs/erofs_fs.h
@@ -304,6 +304,7 @@ enum {
enum {
Z_EROFS_COMPRESSION_LZ4 = 0,
Z_EROFS_COMPRESSION_LZMA= 1,
+ Z_EROFS_COMPRESSION_DEFLATE = 2,
Z_EROFS_COMPRESSION_MAX
};
--
2.34.1
Re: [PATCH v6 5/5] imx93: convert to OF_UPSTREAM
Hello, > Which dts upstream tag are u using? You will find it in my previous email. The command I use is: ./dts/update-dts-subtree.sh pull 2639a0e2fdbdb7f2dd351d06afe54c895adf9d9d > Do you have time to debug the issue? I not have the board, so not sure what > happens here. Not at the moment sorry. Mathieu
Re: [PATCH v2 00/16] pxe: Allow extlinux booting without CMDLINE enabled
Hi Tom and Simon, On 2024-04-11 03:45, Tom Rini wrote: > On Thu, 14 Dec 2023 21:18:58 -0700, Simon Glass wrote: > >> This series is the culmanation of the current line of refactoring >> series. It adjusts pxe to call the booting functionality directly >> rather than going through the command-line interface. >> >> With this is is possible to boot using the extlinux bootmeth without >> the command line enabled. >> >> [...] > > Applied to u-boot/master, thanks! > This series is causing boot issues using extlinux in bootm_run_states(): ERROR: booting os 'Invalid OS' (0) is not supported Following extlinux.conf was used: label linux kernel /Image.gz initrd /initramfs.cpio.gz Before this series booting works, bootm_run_states() is first called with states=0x1 (BOOTM_STATE_START): Scanning bootdev 'mmc@fe2b.bootdev': 1 extlinux ready mmc 1 m...@fe2b.bootdev.part /extlinux/extlinux.conf ** Booting bootflow 'mmc@fe2b.bootdev.part_1' with extlinux 1: linux Retrieving file: /Image.gz Retrieving file: /initramfs.cpio.gz bootm_run_states(): images->state: 0, states: 1 bootm_run_states(): images->os.os: 0 bootm_run_states(): images->os.arch: 0 bootm_run_states(): boot_fn: , need_boot_fn: 0 Uncompressing Kernel Image to 0 ## Flattened Device Tree blob at edef8410 Booting using the fdt blob at 0xedef8410 Working FDT set to edef8410 bootm_run_states(): images->state: 1, states: 1710 Loading Ramdisk to ecdfd000, end eceb274d ... OK bootm_run_states(): images->os.os: 5 bootm_run_states(): images->os.arch: 16 boot_fn: eff2b83c, need_boot_fn: 0 Loading Device Tree to ecde8000, end ecdfc97f ... OK Working FDT set to ecde8000 After this series booting fails, bootm_run_states() is first called with states=0x1710. Scanning bootdev 'mmc@fe2b.bootdev': 1 extlinux ready mmc 1 m...@fe2b.bootdev.part /extlinux/extlinux.conf ** Booting bootflow 'mmc@fe2b.bootdev.part_1' with extlinux 1: linux Retrieving file: /Image.gz Retrieving file: /initramfs.cpio.gz bootm_run_states(): images->state: 0, states: 1710 bootm_run_states(): images->os.os: 0 bootm_run_states(): images->os.arch: 0 bootm_run_states(): boot_fn: , need_boot_fn: 0 ERROR: booting os 'Invalid OS' (0) is not supported Boot failed (err=-14) Looks like booti_start() -> bootm_run_states(bmi, BOOTM_STATE_START) is no longer called due to changes in this series. Regards, Jonas
[PULL] Pull request for u-boot-nand-20240414
Hello Tom, The following changes since commit 266603d8c39cf4d194e2cfe8d86d870590e150e0: Merge tag 'efi-2024-07-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi (2024-04-13 10:18:38 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git tags/u-boot-nand-20240414 for you to fetch changes up to 248fc16055858c2028a381bb59e12354c4ae19ea: cmd: mtd: OTP access support (2024-04-14 08:49:40 +0200) Gitlab CI showed no issues: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/20333 Pull request for u-boot-nand-20240414 The first patch is by Weizhao Ouyang and avoids sf probe crashes. The second patch is by Arseniy Krasnov and adds basic support for Amlogic Meson NAND controller on AXG. The following four patches are by Alexander Dahl and apply some fixes to drivers/mtd/nand/raw/ and port some changes applied in Linux. The following patch is by Bruce Suen and adds support for XTX SPINAND. Finally, the last patch is again by Arseniy Krasnov and adds access to OTP region, supporting info, dump, write and lock operations. Alexander Dahl (4): mtd: nand: raw: Use macro nand_to_mtd() where appropriate mtd: nand: raw: Port another option flag from Linux mtd: nand: raw: Fix (most) Kconfig indentation mtd: nand: raw: atmel: Fix comment in timings preparation Arseniy Krasnov (2): mtd: rawnand: Meson NAND controller support cmd: mtd: OTP access support Bruce Suen (1): mtd: spinand: Add support for XTX SPINAND Weizhao Ouyang (1): cmd: sf: Fix sf probe crash cmd/Kconfig |7 + cmd/mtd.c| 234 +++ cmd/sf.c |5 +- drivers/mtd/nand/raw/Kconfig | 115 +- drivers/mtd/nand/raw/Makefile|1 + drivers/mtd/nand/raw/atmel/nand-controller.c |4 +- drivers/mtd/nand/raw/meson_nand.c| 1248 +++ drivers/mtd/nand/raw/nand_base.c |6 +- drivers/mtd/nand/spi/Makefile|2 +- drivers/mtd/nand/spi/core.c |1 + drivers/mtd/nand/spi/xtx.c | 266 + include/linux/mtd/rawnand.h |7 + include/linux/mtd/spinand.h |1 + 13 files changed, 1835 insertions(+), 62 deletions(-) create mode 100644 drivers/mtd/nand/raw/meson_nand.c create mode 100644 drivers/mtd/nand/spi/xtx.c -- Dario Binacchi Senior Embedded Linux Developer dario.binac...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
[PATCH] boot: fdt: Turn all addresses and sizes into u64
In case of systems where DRAM bank ends at the edge of 32bit boundary,
start + size calculations would overflow. This happens on STM32MP15xx
with 1 DRAM bank starting at 0xc000 and 1 GiB of DRAM. This is a
usual 32bit system DRAM size overflow, fix it by doing all DRAM size
and offset calculations using u64 types. This also covers a case where
a 32bit PAE system might be able to address up to 36bits of DRAM.
Fixes: a4df06e41fa2 ("boot: fdt: Change type of env_get_bootm_low() to
phys_addr_t")
Signed-off-by: Marek Vasut
---
Cc: Laurent Pinchart
Cc: Matthias Schiffer
Cc: Simon Glass
Cc: Tom Rini
---
boot/image-fdt.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/boot/image-fdt.c b/boot/image-fdt.c
index 2b92bdaff16..f09716cba30 100644
--- a/boot/image-fdt.c
+++ b/boot/image-fdt.c
@@ -158,13 +158,10 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void
*fdt_blob)
*/
int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size)
{
+ u64 start, size, usable, addr, low, mapsize;
void*fdt_blob = *of_flat_tree;
void*of_start = NULL;
- phys_addr_t start, size, usable;
char*fdt_high;
- phys_addr_t addr;
- phys_addr_t low;
- phys_size_t mapsize;
ulong of_len = 0;
int bank;
int err;
--
2.43.0
[PATCH] ARM: stm32: Drop superfluous Makefile entry for ecdsa_romapi.o
The source file is in arch/arm/mach-stm32mp/ecdsa_romapi.c and not in arch/arm/mach-stm32mp/stm32mp1/ecdsa_romapi.c . There are two Makefile entries in each subdirectory. Drop the bogus one and keep only the correct one, the one in arch/arm/mach-stm32mp/Makefile . Signed-off-by: Marek Vasut --- Cc: Igor Opaniuk Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Tom Rini Cc: u-b...@dh-electronics.com Cc: uboot-st...@st-md-mailman.stormreply.com --- arch/arm/mach-stm32mp/stm32mp1/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile index 857148747ef..ebae50f66c9 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -8,7 +8,6 @@ obj-y += cpu.o obj-$(CONFIG_STM32MP13X) += stm32mp13x.o obj-$(CONFIG_STM32MP15X) += stm32mp15x.o -obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-y += tzc400.o -- 2.43.0
[PATCH] ARM: stm32: Report OTP-CLOSED instead of rev.? on closed STM32MP15xx
SoC revision is only accessible via DBUMCU IDC register,
which requires BSEC.DENABLE DBGSWENABLE bit to be set to
make the register accessible, otherwise an access to the
register triggers bus fault. As BSEC.DBGSWENABLE is zero
in case of an OTP-CLOSED system, do NOT set DBGSWENABLE
bit as this might open a brief window for timing attacks.
Instead, report that this system is OTP-CLOSED and do not
report any SoC revision to avoid confusing users. Use an
SEC/C abbreviation to avoid growing SOC_NAME_SIZE .
Signed-off-by: Marek Vasut
---
Cc: Igor Opaniuk
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Simon Glass
Cc: Tom Rini
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
index afc56b02eea..dd99150fbc2 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
@@ -322,8 +322,23 @@ void get_soc_name(char name[SOC_NAME_SIZE])
get_cpu_string_offsets(&type, &pkg, &rev);
- snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
-soc_type[type], soc_pkg[pkg], soc_rev[rev]);
+ if (bsec_dbgswenable()) {
+ snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
+soc_type[type], soc_pkg[pkg], soc_rev[rev]);
+ } else {
+ /*
+* SoC revision is only accessible via DBUMCU IDC register,
+* which requires BSEC.DENABLE DBGSWENABLE bit to be set to
+* make the register accessible, otherwise an access to the
+* register triggers bus fault. As BSEC.DBGSWENABLE is zero
+* in case of an OTP-CLOSED system, do NOT set DBGSWENABLE
+* bit as this might open a brief window for timing attacks.
+* Instead, report that this system is OTP-CLOSED and do not
+* report any SoC revision to avoid confusing users.
+*/
+ snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s SEC/C",
+soc_type[type], soc_pkg[pkg]);
+ }
}
static void setup_soc_type_pkg_rev(void)
--
2.43.0
[PATCH] ARM: stm32: Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx
In case of an OTP-CLOSED STM32MP15xx system, the CPU core 1 cannot be released from endless loop in BootROM only by populating TAMP BKPxR 4 and 5 with magic and branch address and sending SGI0 interrupt from core 0 to core 1 twice. TAMP_SMCR BKP..PROT fields must be initialized as well to release the core 1 from endless loop during the second SGI0 handling on core 1. Initialize TAMP_SMCR to protect the first 16 backup registers, the ones which contain the core 1 magic, branch address and boot information. This requirement seems to be undocumented, therefore it was necessary to trace and analyze the STM32MP15xx BootROM using OpenOCD and objdump. Ultimately, it turns out that a certain BootROM function reads out the TAMP_SMCR register and tests whether the BKP..PROT fields are non-zero. If they are zero, the BootROM code again waits for SGI0 using WFI, else the execution moves forward until it reaches handoff to the TAMP BKPxR 5 branch address. This fixes CPU core 1 release using U-Boot PSCI implementation on an OTP-CLOSED system, i.e. system with fuse 0 bit 6 set. Signed-off-by: Marek Vasut --- Cc: Igor Opaniuk Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Tom Rini Cc: u-b...@dh-electronics.com Cc: uboot-st...@st-md-mailman.stormreply.com --- arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index dd99150fbc2..138a6d6b614 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -14,6 +14,7 @@ #include #include #include +#include /* RCC register */ #define RCC_TZCR (STM32_RCC_BASE + 0x00) @@ -41,6 +42,9 @@ #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) +#define TAMP_SMCR (STM32_TAMP_BASE + 0x20) +#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0) +#define TAMP_SMCR_BKPWDPROTGENMASK(23, 16) #define PWR_CR1(STM32_PWR_BASE + 0x00) #define PWR_MCUCR (STM32_PWR_BASE + 0x14) @@ -136,6 +140,18 @@ static void security_init(void) */ writel(0x0, TAMP_CR1); + /* +* TAMP: Configure non-zero secure protection settings. This is +* checked by BootROM function 35ac on OTP-CLOSED device during +* CPU core 1 release from endless loop. If secure protection +* fields are zero, the core 1 is not released from endless +* loop on second SGI0. +*/ + clrsetbits_le32(TAMP_SMCR, + TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPRWDPROT, + FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x10) | + FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x10)); + /* GPIOZ: deactivate the security */ writel(BIT(0), RCC_MP_AHB5ENSETR); writel(0x0, GPIOZ_SECCFGR); -- 2.43.0
[PULL] u-boot-usb/master
The following changes since commit cdfcc37428e06f4730ab9a17cc084eeb7676ea1a: Merge tag 'u-boot-dfu-next-20240402' of https://source.denx.de/u-boot/custodians/u-boot-dfu (2024-04-02 22:37:23 -0400) are available in the Git repository at: git://source.denx.de/u-boot-usb.git master for you to fetch changes up to 63f6a449bffe46beca89580d3efa48e5d041025c: usb: kbd: Add probe quirk for Apple and Keychron keyboards (2024-04-12 14:53:13 +0200) Janne Grunau (6): usb: xhci: refactor xhci_set_configuration usb: xhci: Set up endpoints for the first 2 interfaces usb: xhci: Abort transfers with unallocated rings usb: Add environment based device ignorelist usb: kbd: support Apple Magic Keyboards (2021) usb: kbd: Add probe quirk for Apple and Keychron keyboards common/usb.c | 70 common/usb_kbd.c | 59 ++-- doc/usage/environment.rst| 13 + drivers/usb/host/xhci-ring.c | 5 ++ drivers/usb/host/xhci.c | 126 +++ include/env_default.h| 11 include/usb.h| 6 +++ 7 files changed, 241 insertions(+), 49 deletions(-)
Re: [PATCH] net: wget: Support retransmission a dropped packet
Hi Yasuharu, On Sun, Apr 14, 2024 at 9:46 AM Yasuharu Shibata wrote: > > The server sends multiple packets without waiting for an ACK > by window control and if some packets are dropped, > wget will return an ACK including the dropped packets. > > Following log indicates this issue. > > wget_handler() wget: Transferring, seq=97bbdd4a, ack=30,len=580 > wget_handler() wget: Transferring, seq=97bbedca, ack=30,len=580 > > First packet of TCP sequence number is 0x97bbdd4a. > Second packet of TCP sequence number should be 0x97bbe2ca, > however it is 0x97bbedca and returns its ACK, so the server > suppose that 0x97bbe2ca and 0x97bbedca are received appropriately. > In this case, 0x97bbe2ca was lost and the data of wget was broken. > > In this patch, next_data_seq_num holds the next expected > TCP sequence number. > If the TCP sequence number different from next_data_seq_num, > trying to retransmit the packet. Thanks for your patch. I tested it in the hope that it would fix the following issue: https://lore.kernel.org/u-boot/caj+vnu2u9w2nrt6hf1caeq_56sdqviuezudd1iyopdf1cna...@mail.gmail.com/ but I still get wget corruption when loading large files multiple times in a row. Would you happen to have any suggestions? Thanks
Re: [PATCH] boot: fdt: Turn all addresses and sizes into u64
Hi Marek,
Thank you for the patch.
On Sun, Apr 14, 2024 at 08:37:20PM +0200, Marek Vasut wrote:
> In case of systems where DRAM bank ends at the edge of 32bit boundary,
> start + size calculations would overflow. This happens on STM32MP15xx
> with 1 DRAM bank starting at 0xc000 and 1 GiB of DRAM. This is a
> usual 32bit system DRAM size overflow, fix it by doing all DRAM size
> and offset calculations using u64 types.
I'm not sure I like this much, as it removes a useful indication
regarding what the variables store. Wouldn't it be better if the code's
logic could be modified to avoid those overflows ?
> This also covers a case where
> a 32bit PAE system might be able to address up to 36bits of DRAM.
Shouldn't phys_addr_t be a 64-bit type on PAE systems ?
> Fixes: a4df06e41fa2 ("boot: fdt: Change type of env_get_bootm_low() to
> phys_addr_t")
> Signed-off-by: Marek Vasut
> ---
> Cc: Laurent Pinchart
> Cc: Matthias Schiffer
> Cc: Simon Glass
> Cc: Tom Rini
> ---
> boot/image-fdt.c | 5 +
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/boot/image-fdt.c b/boot/image-fdt.c
> index 2b92bdaff16..f09716cba30 100644
> --- a/boot/image-fdt.c
> +++ b/boot/image-fdt.c
> @@ -158,13 +158,10 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void
> *fdt_blob)
> */
> int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size)
> {
> + u64 start, size, usable, addr, low, mapsize;
> void*fdt_blob = *of_flat_tree;
> void*of_start = NULL;
> - phys_addr_t start, size, usable;
> char*fdt_high;
> - phys_addr_t addr;
> - phys_addr_t low;
> - phys_size_t mapsize;
> ulong of_len = 0;
> int bank;
> int err;
--
Regards,
Laurent Pinchart
Re: [PATCH] boot: fdt: Turn all addresses and sizes into u64
On 4/14/24 9:29 PM, Laurent Pinchart wrote: Hi Marek, Thank you for the patch. On Sun, Apr 14, 2024 at 08:37:20PM +0200, Marek Vasut wrote: In case of systems where DRAM bank ends at the edge of 32bit boundary, start + size calculations would overflow. This happens on STM32MP15xx with 1 DRAM bank starting at 0xc000 and 1 GiB of DRAM. This is a usual 32bit system DRAM size overflow, fix it by doing all DRAM size and offset calculations using u64 types. I'm not sure I like this much, as it removes a useful indication regarding what the variables store. That's what the variable name is for, not variable type. Wouldn't it be better if the code's logic could be modified to avoid those overflows ? I'd prefer to keep the code simple and blanket avoid the overflows for a very long time, rather than play whack-a-mole with various odd corner cases here. Note that this is a fix for a previous series which changed from u64/ulong to phys_addr/size_t , which clearly was incorrect . This also covers a case where a 32bit PAE system might be able to address up to 36bits of DRAM. Shouldn't phys_addr_t be a 64-bit type on PAE systems ? That depends on CONFIG_PHYS_64BIT , on am57xx this is not set for example, so there phys_addr_t is 32bit .
Re: [PATCH] boot: fdt: Turn all addresses and sizes into u64
On Sun, Apr 14, 2024 at 11:25:06PM +0200, Marek Vasut wrote: > On 4/14/24 9:29 PM, Laurent Pinchart wrote: > > Hi Marek, > > > > Thank you for the patch. > > > > On Sun, Apr 14, 2024 at 08:37:20PM +0200, Marek Vasut wrote: > >> In case of systems where DRAM bank ends at the edge of 32bit boundary, > >> start + size calculations would overflow. This happens on STM32MP15xx > >> with 1 DRAM bank starting at 0xc000 and 1 GiB of DRAM. This is a > >> usual 32bit system DRAM size overflow, fix it by doing all DRAM size > >> and offset calculations using u64 types. > > > > I'm not sure I like this much, as it removes a useful indication > > regarding what the variables store. > > That's what the variable name is for, not variable type. > > > Wouldn't it be better if the code's > > logic could be modified to avoid those overflows ? > > I'd prefer to keep the code simple and blanket avoid the overflows for a > very long time, rather than play whack-a-mole with various odd corner > cases here. Up to you. > Note that this is a fix for a previous series which changed from > u64/ulong to phys_addr/size_t , which clearly was incorrect . > > >> This also covers a case where > >> a 32bit PAE system might be able to address up to 36bits of DRAM. > > > > Shouldn't phys_addr_t be a 64-bit type on PAE systems ? > > That depends on CONFIG_PHYS_64BIT , on am57xx this is not set for > example, so there phys_addr_t is 32bit . The system won't be able to address more than 32 bits of memory in that case, would it ? -- Regards, Laurent Pinchart
Re: [PATCH] boot: fdt: Turn all addresses and sizes into u64
On 4/14/24 11:28 PM, Laurent Pinchart wrote: On Sun, Apr 14, 2024 at 11:25:06PM +0200, Marek Vasut wrote: On 4/14/24 9:29 PM, Laurent Pinchart wrote: Hi Marek, Thank you for the patch. On Sun, Apr 14, 2024 at 08:37:20PM +0200, Marek Vasut wrote: In case of systems where DRAM bank ends at the edge of 32bit boundary, start + size calculations would overflow. This happens on STM32MP15xx with 1 DRAM bank starting at 0xc000 and 1 GiB of DRAM. This is a usual 32bit system DRAM size overflow, fix it by doing all DRAM size and offset calculations using u64 types. I'm not sure I like this much, as it removes a useful indication regarding what the variables store. That's what the variable name is for, not variable type. Wouldn't it be better if the code's logic could be modified to avoid those overflows ? I'd prefer to keep the code simple and blanket avoid the overflows for a very long time, rather than play whack-a-mole with various odd corner cases here. Up to you. Note that this is a fix for a previous series which changed from u64/ulong to phys_addr/size_t , which clearly was incorrect . This also covers a case where a 32bit PAE system might be able to address up to 36bits of DRAM. Shouldn't phys_addr_t be a 64-bit type on PAE systems ? That depends on CONFIG_PHYS_64BIT , on am57xx this is not set for example, so there phys_addr_t is 32bit . The system won't be able to address more than 32 bits of memory in that case, would it ? It might do so through some memory window, like PCIe, but I never used the am57xx so I cannot tell what it really does.
Re: [PULL] Pull request for u-boot-nand-20240414
On Sun, Apr 14, 2024 at 08:16:13PM +0200, Dario Binacchi wrote: > Hello Tom, > > The following changes since commit 266603d8c39cf4d194e2cfe8d86d870590e150e0: > > Merge tag 'efi-2024-07-rc1-2' of > https://source.denx.de/u-boot/custodians/u-boot-efi (2024-04-13 > 10:18:38 -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git > tags/u-boot-nand-20240414 > > for you to fetch changes up to 248fc16055858c2028a381bb59e12354c4ae19ea: > > cmd: mtd: OTP access support (2024-04-14 08:49:40 +0200) > > Gitlab CI showed no issues: > https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/20333 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] DRAM_SUN50I_H616_TRIM_SIZE
On Sat, 13 Apr 2024 21:43:52 +0800
da...@189.cn wrote:
Hi,
thanks for sending a patch!
> From: lalakii
>
> Add "DRAM_SUN50I_H616_TRIM_SIZE" option for 1.5gb board.
>
> Signed-off-by: lalakii
> ---
> arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h | 1 +
> arch/arm/mach-sunxi/Kconfig| 7 +++
> arch/arm/mach-sunxi/dram_sun50i_h616.c | 11 ++-
> 3 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> index a8fdda124a..2d2526fead 100644
> --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> @@ -166,6 +166,7 @@ struct dram_config {
> u8 rows;
> u8 ranks;
> u8 bus_full_width;
> + bool trim_size;
> };
>
> static inline int ns_to_t(int nanoseconds)
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index fe89aec6b9..255a498557 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -108,6 +108,13 @@ config DRAM_SUN50I_H616_TPR12
> default 0x0
> help
> TPR12 value from vendor DRAM settings.
> +
> +config DRAM_SUN50I_H616_TRIM_SIZE
> +bool "H616 DRAM trim size"
> +help
> + Due to unknown issue, some H616 based boards may need to trim
Well, it's not really an unknown issue, is it? The problem seems to be
that the auto detection code cannot deal with the topology of the 1.5GB
DRAM chips.
The general problem with this approach is that it would need to be
enabled at build time, which means the generated image will always trim
the DRAM size, and would not be universal for each board anymore.
So we need something to auto-detect this situation. Can you describe
the failure mode, without this patch? Does the DRAM init code hang or
give up already, or does this all pass, and then later on the board
hangs or crashes when we try access the missing DRAM area?
Maybe a small test access beyond 1.5GB would be able to check for this
particular case?
Cheers,
Andre
> + size a bit.
> +
> endif
>
> config SUN6I_PRCM
> diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
> b/arch/arm/mach-sunxi/dram_sun50i_h616.c
> index 37c139e0ee..4598d60a57 100644
> --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
> +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
> @@ -1349,8 +1349,15 @@ static unsigned long mctl_calc_size(const struct
> dram_config *config)
> {
> u8 width = config->bus_full_width ? 4 : 2;
>
> + unsigned long size;
> +
> + size = (1ULL << (config->cols + config->rows + 3)) * width *
> config->ranks;
> +
> + if (config->trim_size)
> + size = (size * 3) / (width == 4 ? 4 : 8);
> +
> /* 8 banks */
> - return (1ULL << (config->cols + config->rows + 3)) * width *
> config->ranks;
> + return size;
> }
>
> static const struct dram_para para = {
> @@ -1379,6 +1386,8 @@ unsigned long sunxi_dram_init(void)
> struct sunxi_prcm_reg *const prcm =
> (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
> struct dram_config config;
> + if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_TRIM_SIZE))
> + config.trim_size = true;
> unsigned long size;
>
> setbits_le32(&prcm->res_cal_ctrl, BIT(8));
Re: [PULL] u-boot-usb/master
On Sun, Apr 14, 2024 at 08:45:17PM +0200, Marek Vasut wrote: > The following changes since commit cdfcc37428e06f4730ab9a17cc084eeb7676ea1a: > > Merge tag 'u-boot-dfu-next-20240402' of > https://source.denx.de/u-boot/custodians/u-boot-dfu (2024-04-02 22:37:23 > -0400) > > are available in the Git repository at: > > git://source.denx.de/u-boot-usb.git master > > for you to fetch changes up to 63f6a449bffe46beca89580d3efa48e5d041025c: > > usb: kbd: Add probe quirk for Apple and Keychron keyboards (2024-04-12 > 14:53:13 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH 0/4] mtd: Make sure UBIFS does not do multi-pass page programming on flashes that don't support it
From: Takahiro Kuwano This series is equivalent to the one for Linux MTD submitted by Pratyush Yadav. https://patchwork.ozlabs.org/project/linux-mtd/list/?series=217759&state=* Takahiro Kuwano (4): mtd: ubi: Do not zero out EC and VID on ECC-ed NOR flashes mtd: spi-nor: Allow flashes to specify MTD writesize mtd: spi-nor-core: Rework default_init() to take flash_parameter mtd: spi-nor: Set ECC unit size to MTD writesize in Infineon SEMPER flashes drivers/mtd/spi/spi-nor-core.c | 45 +- drivers/mtd/ubi/build.c| 4 +-- drivers/mtd/ubi/io.c | 9 ++- include/linux/mtd/spi-nor.h| 1 + 4 files changed, 44 insertions(+), 15 deletions(-) -- 2.34.1
[PATCH 1/4] mtd: ubi: Do not zero out EC and VID on ECC-ed NOR flashes
From: Takahiro Kuwano
For NOR flashes EC and VID are zeroed out before an erase is issued to
make sure UBI does not mistakenly treat the PEB as used and associate it
with an LEB.
But on some flashes, like the Infineon Semper NOR flash family,
multi-pass page programming is not allowed on the default ECC scheme.
This means zeroing out these magic numbers will result in the flash
throwing a page programming error.
Do not zero out EC and VID for such flashes. A writesize > 1 is an
indication of an ECC-ed flash.
Signed-off-by: Takahiro Kuwano
---
drivers/mtd/ubi/build.c | 4 +---
drivers/mtd/ubi/io.c| 9 -
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index a1941b8eb8..81c1b7bdbc 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -679,10 +679,8 @@ static int io_init(struct ubi_device *ubi, int
max_beb_per1024)
ubi->bad_peb_limit = get_bad_peb_limit(ubi, max_beb_per1024);
}
- if (ubi->mtd->type == MTD_NORFLASH) {
- ubi_assert(ubi->mtd->writesize == 1);
+ if (ubi->mtd->type == MTD_NORFLASH)
ubi->nor_flash = 1;
- }
ubi->min_io_size = ubi->mtd->writesize;
ubi->hdrs_min_io_size = ubi->mtd->writesize >> ubi->mtd->subpage_sft;
diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c
index 14be95b74b..45699b4a47 100644
--- a/drivers/mtd/ubi/io.c
+++ b/drivers/mtd/ubi/io.c
@@ -563,7 +563,14 @@ int ubi_io_sync_erase(struct ubi_device *ubi, int pnum,
int torture)
return -EROFS;
}
- if (ubi->nor_flash) {
+ /*
+* If the flash is ECC-ed then we have to erase the ECC block before we
+* can write to it. But the write is in preparation to an erase in the
+* first place. This means we cannot zero out EC and VID before the
+* erase and we just have to hope the flash starts erasing from the
+* start of the page.
+*/
+ if (ubi->nor_flash && ubi->mtd->writesize == 1) {
err = nor_erase_prepare(ubi, pnum);
if (err)
return err;
--
2.34.1
[PATCH 2/4] mtd: spi-nor: Allow flashes to specify MTD writesize
From: Takahiro Kuwano
Some flashes like the Infineon SEMPER NOR flash family use ECC. Under
this ECC scheme, multi-pass writes to an ECC block is not allowed.
In other words, once data is programmed to an ECC block, it can't be
programmed again without erasing it first.
Upper layers like file systems need to be given this information so they
do not cause error conditions on the flash by attempting multi-pass
programming. This can be done by setting 'writesize' in 'struct
mtd_info'.
Set the default to 1 but allow flashes to modify it in fixup hooks. If
more flashes show up with this constraint in the future it might be
worth it to add it to 'struct flash_info', but for now increasing its
size is not worth it.
Signed-off-by: Takahiro Kuwano
---
drivers/mtd/spi/spi-nor-core.c | 3 ++-
include/linux/mtd/spi-nor.h| 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index f86003ca8c..1bfef6797f 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -2789,6 +2789,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
memset(params, 0, sizeof(*params));
/* Set SPI NOR sizes. */
+ params->writesize = 1;
params->size = info->sector_size * info->n_sectors;
params->page_size = info->page_size;
@@ -4078,7 +4079,7 @@ int spi_nor_scan(struct spi_nor *nor)
mtd->dev = nor->dev;
mtd->priv = nor;
mtd->type = MTD_NORFLASH;
- mtd->writesize = 1;
+ mtd->writesize = params.writesize;
mtd->flags = MTD_CAP_NORFLASH;
mtd->size = params.size;
mtd->_erase = spi_nor_erase;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index d1dbf3eadb..0d37a806c4 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -436,6 +436,7 @@ enum spi_nor_pp_command_index {
struct spi_nor_flash_parameter {
u64 size;
+ u32 writesize;
u32 page_size;
u8 rdsr_dummy;
u8 rdsr_addr_nbytes;
--
2.34.1
[PATCH 3/4] mtd: spi-nor-core: Rework default_init() to take flash_parameter
From: Takahiro Kuwano
default_init() fixup hook should be used to initialize flash parameters
when its information is not provided in SFDP. To support that case, it
needs to take flash_parameter structure like as other hooks.
Signed-off-by: Takahiro Kuwano
---
drivers/mtd/spi/spi-nor-core.c | 28 ++--
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 1bfef6797f..8f371a5213 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -203,7 +203,8 @@ struct sfdp_bfpt {
* table is broken or not available.
*/
struct spi_nor_fixups {
- void (*default_init)(struct spi_nor *nor);
+ void (*default_init)(struct spi_nor *nor,
+struct spi_nor_flash_parameter *params);
int (*post_bfpt)(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt,
@@ -2775,10 +2776,11 @@ static void spi_nor_post_sfdp_fixups(struct spi_nor
*nor,
nor->fixups->post_sfdp(nor, params);
}
-static void spi_nor_default_init_fixups(struct spi_nor *nor)
+static void spi_nor_default_init_fixups(struct spi_nor *nor,
+ struct spi_nor_flash_parameter *params)
{
if (nor->fixups && nor->fixups->default_init)
- nor->fixups->default_init(nor);
+ nor->fixups->default_init(nor, params);
}
static int spi_nor_init_params(struct spi_nor *nor,
@@ -2885,7 +2887,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
}
}
- spi_nor_default_init_fixups(nor);
+ spi_nor_default_init_fixups(nor, params);
/* Override the parameters with data read from SFDP tables. */
nor->addr_width = 0;
@@ -3328,7 +3330,8 @@ static int s25fs_s_setup(struct spi_nor *nor, const
struct flash_info *info,
return spi_nor_default_setup(nor, info, params);
}
-static void s25fs_s_default_init(struct spi_nor *nor)
+static void s25fs_s_default_init(struct spi_nor *nor,
+struct spi_nor_flash_parameter *params)
{
nor->setup = s25fs_s_setup;
}
@@ -3452,7 +3455,8 @@ static int s25_s28_setup(struct spi_nor *nor, const
struct flash_info *info,
return spi_nor_default_setup(nor, info, params);
}
-static void s25_default_init(struct spi_nor *nor)
+static void s25_default_init(struct spi_nor *nor,
+struct spi_nor_flash_parameter *params)
{
nor->setup = s25_s28_setup;
}
@@ -3544,7 +3548,8 @@ static int s25fl256l_setup(struct spi_nor *nor, const
struct flash_info *info,
return -ENOTSUPP; /* Bank Address Register is not supported */
}
-static void s25fl256l_default_init(struct spi_nor *nor)
+static void s25fl256l_default_init(struct spi_nor *nor,
+ struct spi_nor_flash_parameter *params)
{
nor->setup = s25fl256l_setup;
}
@@ -3613,7 +3618,8 @@ static int spi_nor_cypress_octal_dtr_enable(struct
spi_nor *nor)
return 0;
}
-static void s28hx_t_default_init(struct spi_nor *nor)
+static void s28hx_t_default_init(struct spi_nor *nor,
+struct spi_nor_flash_parameter *params)
{
nor->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
nor->setup = s25_s28_setup;
@@ -3705,7 +3711,8 @@ static int spi_nor_micron_octal_dtr_enable(struct spi_nor
*nor)
return 0;
}
-static void mt35xu512aba_default_init(struct spi_nor *nor)
+static void mt35xu512aba_default_init(struct spi_nor *nor,
+ struct spi_nor_flash_parameter *params)
{
nor->octal_dtr_enable = spi_nor_micron_octal_dtr_enable;
}
@@ -3795,7 +3802,8 @@ static int spi_nor_macronix_octal_dtr_enable(struct
spi_nor *nor)
return 0;
}
-static void macronix_octal_default_init(struct spi_nor *nor)
+static void macronix_octal_default_init(struct spi_nor *nor,
+ struct spi_nor_flash_parameter *params)
{
nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
}
--
2.34.1
[PATCH 4/4] mtd: spi-nor: Set ECC unit size to MTD writesize in Infineon SEMPER flashes
From: Takahiro Kuwano
The Infineon SEMPER NOR flash family uses 2-bit ECC by default with each
ECC block being 16 bytes. Under this scheme multi-pass programming to an
ECC block is not allowed. Set the writesize to make sure multi-pass
programming is not attempted on the flash.
Signed-off-by: Takahiro Kuwano
---
drivers/mtd/spi/spi-nor-core.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 8f371a5213..773afd4040 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3459,6 +3459,13 @@ static void s25_default_init(struct spi_nor *nor,
struct spi_nor_flash_parameter *params)
{
nor->setup = s25_s28_setup;
+
+ /*
+* Programming is supported only in 16-byte ECC data unit granularity.
+* Byte-programming, bit-walking, or multiple program operations to the
+* same ECC data unit without an erase are not allowed.
+*/
+ params->writesize = 16;
}
static int s25_s28_post_bfpt_fixup(struct spi_nor *nor,
@@ -3623,6 +3630,13 @@ static void s28hx_t_default_init(struct spi_nor *nor,
{
nor->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
nor->setup = s25_s28_setup;
+
+ /*
+* Programming is supported only in 16-byte ECC data unit granularity.
+* Byte-programming, bit-walking, or multiple program operations to the
+* same ECC data unit without an erase are not allowed.
+*/
+ params->writesize = 16;
}
static void s28hx_t_post_sfdp_fixup(struct spi_nor *nor,
--
2.34.1
Re: [PATCH] ubi: Depend on MTD
Hello John, On 11.04.24 07:05, John Watts wrote: UBI required MTD to build correctly, add it as a Kconfig dependency. Signed-off-by: John Watts --- While working with UBI on my SPI NAND patch series I found it was possible to enable it without enabling the MTD subsystem. Add a Kconfig option to solve this. --- drivers/mtd/ubi/Kconfig | 1 + 1 file changed, 1 insertion(+) Reviewed-by: Heiko Schocher Thanks! bye, Heiko -- -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
[PATCH v2 00/17] Misc changes for CSSI boards
This series contains misc fixes and changes for CSSI boards. Main changes are: - Fix and optimise mpc8xx SPI driver - Add support for LM74 temperature sensor - Add support for loading FPGA on MCR3000 I will send a pull request later before close of the merge window. Changes since v1: - Added temperature and FPGA support and SPI driver optimisation Christophe Leroy (13): board: cssi: Fix SPI nodes in DTS spi: mpc8xx: Add GPIO dependency spi: mpc8xx: Fix transfert when input or output buffer is NULL thermal: Add support for TI LM74 board: cssi: Add support for SPI bus on MCR3000 board board: cssi: add support for reading temperature powerpc: 8xx: Set SDMA configuration register correcly spi: mpc8xx: Allow transfer of more than MAX_BUFFER len spi: mpc8xx: Use 16 bit mode for large transfers with even size spi: mpc8xx: Set up speed as requested board: cssi: Use HAVE_VENDOR_COMMON_LIB logic board: cssi: Load FPGA on MCR3000 board board: cssi: Read and display MCR board address Hugo Dubois (2): board: cssi: Initialise port F on MIAE board: cssi: Properly initialise MAC address for fibre on CMPC885 board Jean-Michel CASAUBON (2): board: cssi: Fix MCR3000 board environment board: cssi: Allow use without HUSH shell arch/powerpc/cpu/mpc8xx/cpu_init.c | 6 ++ arch/powerpc/dts/cmpc885.dts | 18 - arch/powerpc/dts/cmpcpro.dts | 16 +++- arch/powerpc/dts/mcr3000.dts | 41 +++ board/cssi/cmpc885/Makefile| 2 +- board/cssi/cmpc885/cmpc885.c | 4 +- board/cssi/cmpc885/cmpc885.env | 4 +- board/cssi/cmpcpro/Makefile| 2 +- board/cssi/cmpcpro/cmpcpro.env | 4 +- board/cssi/common/Makefile | 8 ++ board/cssi/common/common.c | 42 ++- board/cssi/mcr3000/Makefile| 1 + board/cssi/mcr3000/fpga_code.h | 10 +++ board/cssi/mcr3000/mcr3000.c | 58 +++ board/cssi/mcr3000/mcr3000.env | 2 +- board/cssi/mcr3000/mcr3000_gpio.c | 109 configs/CMPC885_defconfig | 3 + configs/CMPCPRO_defconfig | 3 + configs/MCR3000_defconfig | 8 ++ drivers/spi/Kconfig| 2 +- drivers/spi/mpc8xx_spi.c | 113 - drivers/thermal/Kconfig| 6 ++ drivers/thermal/Makefile | 1 + drivers/thermal/ti-lm74.c | 52 + 24 files changed, 476 insertions(+), 39 deletions(-) create mode 100644 board/cssi/common/Makefile create mode 100644 board/cssi/mcr3000/fpga_code.h create mode 100644 board/cssi/mcr3000/mcr3000_gpio.c create mode 100644 drivers/thermal/ti-lm74.c -- 2.43.0
[PATCH v2 01/17] board: cssi: Fix MCR3000 board environment
From: Jean-Michel CASAUBON
Remove a stray semicolon in MCR3000 board environment.
Signed-off-by: Jean-Michel CASAUBON
Reviewed-by: DUBOIS Hugo
Signed-off-by: Christophe Leroy
---
board/cssi/mcr3000/mcr3000.env | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/cssi/mcr3000/mcr3000.env b/board/cssi/mcr3000/mcr3000.env
index 372ab09094..380c10c4ce 100644
--- a/board/cssi/mcr3000/mcr3000.env
+++ b/board/cssi/mcr3000/mcr3000.env
@@ -8,7 +8,7 @@ dhcp_ip=ip=:eth0:dhcp
console_args=console=ttyCPM0,115200N8
loadkernel=ubi part nand0;ubifsmount ubi0;ubifsload ${loadaddr}
/boot/${filename};ubifsumount; ubi detach
bootcmd=run flashboot
-flashboot=setenv bootargs ${console_args}
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off;${ofl_args};
run loadkernel; bootm ${loadaddr}
+flashboot=setenv bootargs ${console_args}
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off ${ofl_args};
run loadkernel; bootm ${loadaddr}
tftpboot=setenv bootargs ${console_args}
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off ${ofl_args};
tftp ${loadaddr} ${filename}; bootm ${loadaddr}
dhcpboot=dhcp ${loadaddr} ${filename};setenv bootargs ${console_args}
${dhcp_ip} ${ofl_args}; bootm ${loadaddr}
update=echo 'Updating ubi image'; if tftp 0x2000 $ubifile; then nand
erase.chip; nand write 0x2000 0x00 $filesize; fi
--
2.43.0
[PATCH v2 02/17] board: cssi: Fix SPI nodes in DTS
When adding additional SPI peripherals, the reg property needs to
be added, and this leads to the following error:
arch/powerpc/dts/cmpc885.dtb: Warning (reg_format):
/immr@ff00/spi@aa0/temp@1:reg: property has invalid length (4 bytes)
(#address-cells == 1, #size-cells == 1)
arch/powerpc/dts/cmpc885.dtb: Warning (reg_format):
/immr@ff00/spi@aa0/temp@2:reg: property has invalid length (4 bytes)
(#address-cells == 1, #size-cells == 1)
Fix it by removing cell-index and cell-size which is unused and add
reg property. Also fix node name to be in line with reg value.
Also add missing compatible for eeprom node.
Signed-off-by: Christophe Leroy
---
arch/powerpc/dts/cmpc885.dts | 6 +++---
arch/powerpc/dts/cmpcpro.dts | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/dts/cmpc885.dts b/arch/powerpc/dts/cmpc885.dts
index 7b9566a0fa..9a33e7e77c 100644
--- a/arch/powerpc/dts/cmpc885.dts
+++ b/arch/powerpc/dts/cmpc885.dts
@@ -83,13 +83,13 @@
spi: spi@aa0 {
status = "okay";
#address-cells = <1>;
- #size-cells = <1>;
- cell-index = <0>;
+ #size-cells = <0>;
compatible = "fsl,mpc8xx-spi";
gpios = <&CPM1_PIO_B 21 1>; /* /EEPROM_CS ACTIVE_LOW */
eeprom@0 {
- cell-index = <1>;
+ reg = <0>;
+ compatible = "atmel,at25", "cs,eeprom";
};
};
};
diff --git a/arch/powerpc/dts/cmpcpro.dts b/arch/powerpc/dts/cmpcpro.dts
index c27d9dba33..78f8a9f4d3 100644
--- a/arch/powerpc/dts/cmpcpro.dts
+++ b/arch/powerpc/dts/cmpcpro.dts
@@ -142,9 +142,9 @@
mode = "cpu";
gpios = <&qe_pio_d 3 1>;
clock-frequency = <0>;
- eeprom@3 {
+ eeprom@0 {
+ reg = <0>;
compatible = "atmel,at25", "cs,eeprom";
- cell-index = <1>;
};
};
eth0: ucc@3000 {
--
2.43.0
[PATCH v2 03/17] board: cssi: Allow use without HUSH shell
From: Jean-Michel CASAUBON
HUSH shell is not always wanted/desirable.
Add missing braces in environment in order to allow use without
HUSH shell.
Signed-off-by: Jean-Michel CASAUBON
Cc: DUBOIS Hugo
Signed-off-by: Christophe Leroy
---
board/cssi/cmpc885/cmpc885.env | 4 ++--
board/cssi/cmpcpro/cmpcpro.env | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/cssi/cmpc885/cmpc885.env b/board/cssi/cmpc885/cmpc885.env
index 51ab5ce2cf..570117cd36 100644
--- a/board/cssi/cmpc885/cmpc885.env
+++ b/board/cssi/cmpc885/cmpc885.env
@@ -2,6 +2,6 @@ loadaddr=0x1a0
filename=cmpc885.itb
console_args=console=ttyCPM0,115200N8
loadkernel=ubi part nand0;ubifsmount ubi0;ubifsload ${loadaddr}
/boot/${filename};ubifsumount; ubi detach
-flashboot=setenv bootargs ${console_args}
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off
${ofl_args}; run loadkernel; bootm $loadaddr#$config
-tftpboot=setenv bootargs ${console_args}
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off
${ofl_args}; tftp ${loadaddr} ${filename};bootm $loadaddr#$config
+flashboot=setenv bootargs ${console_args}
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off
${ofl_args}; run loadkernel; bootm ${loadaddr}#${config}
+tftpboot=setenv bootargs ${console_args}
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off
${ofl_args}; tftp ${loadaddr} ${filename};bootm ${loadaddr}#${config}
update=echo 'Updating ubi image'; if tftp $loadaddr $ubifile; then nand
erase.chip; nand write $loadaddr 0x00 $filesize; fi;
diff --git a/board/cssi/cmpcpro/cmpcpro.env b/board/cssi/cmpcpro/cmpcpro.env
index 7394b8386e..47b436ff6b 100644
--- a/board/cssi/cmpcpro/cmpcpro.env
+++ b/board/cssi/cmpcpro/cmpcpro.env
@@ -3,6 +3,6 @@ filename=cmpcpro.itb
netdev=eth0
console_args=console=ttyS0,115200N8
loadkernel=ubi part nand0;ubifsmount ubi0; ubifsload ${loadaddr}
/boot/${filename}; ubifsumount; ubi detach
-flashboot=mw.w 9040 0x000E 1; setenv bootargs ${console_args}
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off
${ofl_args}; run loadkernel; bootm $loadaddr#$config
-tftpboot=mw.w 9040 0x000E 1; setenv bootargs ${console_args}
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off
${ofl_args}; tftp ${loadaddr} ${filename}; bootm $loadaddr#$config
+flashboot=mw.w 9040 0x000E 1; setenv bootargs ${console_args}
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off
${ofl_args}; run loadkernel; bootm ${loadaddr}#${config}
+tftpboot=mw.w 9040 0x000E 1; setenv bootargs ${console_args}
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off
${ofl_args}; tftp ${loadaddr} ${filename}; bootm ${loadaddr}#${config}
update=echo 'Updating ubi image'; mw.w 9040 0x000E 1; if tftp $loadaddr
$ubifile; then nand erase.chip; nand write $loadaddr 0x00 $filesize; fi;
--
2.43.0
[PATCH v2 04/17] board: cssi: Initialise port F on MIAE
From: Hugo Dubois
When equipped with the SRSA audio board, MIAE equipment
has an additional port called port F.
Initialise that port just like other ports of the board, so
that it is already configured when starting Linux kernel.
Signed-off-by: Hugo Dubois
Reviewed-by: CASAUBON Jean Michel
Signed-off-by: Christophe Leroy
---
board/cssi/common/common.c | 36 ++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/board/cssi/common/common.c b/board/cssi/common/common.c
index 7ecf772620..6848efd43b 100644
--- a/board/cssi/common/common.c
+++ b/board/cssi/common/common.c
@@ -208,12 +208,44 @@ void misc_init_r_common(void)
}
}
+static void iop_setup_fpgam_common(void)
+{
+ u8 far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
+
+ if (far_id == FAR_CASRSA) {
+ /*
+* PFDIR[15] = 0 [0x01]
+* PFDIR[14] = 1 [0x02]
+* PFDIR[13] = 1 [0x04]
+*/
+ clrsetbits_8(ADDR_FPGA_R_BASE + 0x37, 0x01, 0x06);
+ /*
+* PFODR[15] = 1 [0x01]
+* PFODR[14] = 0 [0x02]
+* PFODR[13] = 0 [0x04]
+*/
+ clrsetbits_8(ADDR_FPGA_R_BASE + 0x39, 0x06, 0x01);
+ /*
+* PFDAT[15] = 0 [0x01]
+* PFDAT[14] = 1 [0x02]
+* PFDAT[13] = 1 [0x04]
+* PFDAT[12] = 1 [0x08]
+*/
+ clrsetbits_8(ADDR_FPGA_R_BASE + 0x3B, 0x01, 0x0E);
+
+ /* Setup TOR_OUT */
+ out_8(ADDR_FPGA_R_BASE + 0x32, 0x2A);
+ }
+}
+
void iop_setup_common(void)
{
u8 type = in_8(ADDR_FPGA_R_BASE);
- if (type == TYPE_MCR)
+ if (type == TYPE_MCR) {
iop_setup_mcr();
- else if (type == TYPE_MIAE)
+ } else if (type == TYPE_MIAE) {
iop_setup_miae();
+ iop_setup_fpgam_common();
+ }
}
--
2.43.0
[PATCH v2 05/17] board: cssi: Properly initialise MAC address for fibre on CMPC885 board
From: Hugo Dubois
CMPC885 board can be pluged on a mother board with fibre interface, so
fibre interface MAC address must be initialised for that case.
Signed-off-by: Hugo Dubois
Reviewed-by: CASAUBON Jean Michel
Signed-off-by: Christophe Leroy
---
board/cssi/cmpc885/cmpc885.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/board/cssi/cmpc885/cmpc885.c b/board/cssi/cmpc885/cmpc885.c
index e11cfafaa5..49c13056ed 100644
--- a/board/cssi/cmpc885/cmpc885.c
+++ b/board/cssi/cmpc885/cmpc885.c
@@ -114,8 +114,10 @@ static int setup_mac(void)
if (memcmp(din + EE_OFF_MAC1, &ident, sizeof(ident)) == 0)
eth_env_set_enetaddr("ethaddr", din + EE_OFF_MAC1);
- if (memcmp(din + EE_OFF_MAC2, &ident, sizeof(ident)) == 0)
+ if (memcmp(din + EE_OFF_MAC2, &ident, sizeof(ident)) == 0) {
eth_env_set_enetaddr("eth1addr", din + EE_OFF_MAC2);
+ eth_env_set_enetaddr("eth2addr", din + EE_OFF_MAC2);
+ }
return 0;
}
--
2.43.0
[PATCH v2 06/17] spi: mpc8xx: Add GPIO dependency
Since commit 773ad4ebb1d6 ("spi, mpc8xx: Add support for chipselect via
GPIO and fixups"), DM_GPIO is required for 8xx SPI.
Add the missing dependency to avoid build failures.
Fixes: 773ad4ebb1d6 ("spi, mpc8xx: Add support for chipselect via GPIO and
fixups")
Signed-off-by: Christophe Leroy
---
drivers/spi/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 69b184b0d9..612434633b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -262,7 +262,7 @@ config MESON_SPIFC_A1
config MPC8XX_SPI
bool "MPC8XX SPI Driver"
- depends on MPC8xx
+ depends on MPC8xx && DM_GPIO
help
Enable support for SPI on MPC8XX
--
2.43.0
[PATCH v2 07/17] spi: mpc8xx: Fix transfert when input or output buffer is NULL
xfer ops can be passed a NULL input or output buffer. At the
time being the driver ignores it and overwrites memory at 0.
Define a dummy buffer and use it when either input or output
buffer is NULL. Bail out when both are NULL as it shouldn't.
Also increase MAX_BUFFER len to 32k as the current is pretty
low.
Signed-off-by: Christophe Leroy
---
drivers/spi/mpc8xx_spi.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c
index 5c8d760935..2aa9c7d5df 100644
--- a/drivers/spi/mpc8xx_spi.c
+++ b/drivers/spi/mpc8xx_spi.c
@@ -29,7 +29,7 @@
#define CPM_SPI_BASE_RXCPM_SPI_BASE
#define CPM_SPI_BASE_TX(CPM_SPI_BASE + sizeof(cbd_t))
-#define MAX_BUFFER 0x104
+#define MAX_BUFFER 0x8000 /* Max possible is 0x. We want power of 2 */
struct mpc8xx_priv {
spi_t __iomem *spi;
@@ -37,6 +37,8 @@ struct mpc8xx_priv {
int max_cs;
};
+static char dummy_buffer[MAX_BUFFER];
+
static int mpc8xx_spi_set_mode(struct udevice *dev, uint mod)
{
return 0;
@@ -154,6 +156,8 @@ static int mpc8xx_spi_xfer(struct udevice *dev, unsigned
int bitlen,
int tm;
size_t count = (bitlen + 7) / 8;
+ if (!din && !dout)
+ return -EINVAL;
if (count > MAX_BUFFER)
return -EINVAL;
@@ -165,12 +169,12 @@ static int mpc8xx_spi_xfer(struct udevice *dev, unsigned
int bitlen,
mpc8xx_spi_cs_activate(dev);
/* Setting tx bd status and data length */
- out_be32(&tbdf->cbd_bufaddr, (ulong)dout);
+ out_be32(&tbdf->cbd_bufaddr, dout ? (ulong)dout : (ulong)dummy_buffer);
out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
out_be16(&tbdf->cbd_datlen, count);
/* Setting rx bd status and data length */
- out_be32(&rbdf->cbd_bufaddr, (ulong)din);
+ out_be32(&rbdf->cbd_bufaddr, din ? (ulong)din : (ulong)dummy_buffer);
out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
--
2.43.0
[PATCH v2 08/17] thermal: Add support for TI LM74
LM74 is a SPI temperature sensor.
Implement a driver to read temperature from it.
Signed-off-by: Christophe Leroy
---
drivers/thermal/Kconfig | 6 +
drivers/thermal/Makefile | 1 +
drivers/thermal/ti-lm74.c | 52 +++
3 files changed, 59 insertions(+)
create mode 100644 drivers/thermal/ti-lm74.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 681b621760..440eb64a56 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -41,4 +41,10 @@ config TI_DRA7_THERMAL
Enable thermal support for for the Texas Instruments DRA752 SoC family.
The driver supports reading CPU temperature.
+config TI_LM74_THERMAL
+bool "Temperature sensor driver for TI LM74 chip"
+help
+Enable thermal support for the Texas Instruments LM74 chip.
+The driver supports reading CPU temperature.
+
endif # if DM_THERMAL
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 8acc7d20cb..b5ab0fc221 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
obj-$(CONFIG_IMX_SCU_THERMAL) += imx_scu_thermal.o
obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o
obj-$(CONFIG_IMX_TMU) += imx_tmu.o
+obj-$(CONFIG_TI_LM74_THERMAL) += ti-lm74.o
diff --git a/drivers/thermal/ti-lm74.c b/drivers/thermal/ti-lm74.c
new file mode 100644
index 00..7d56f75df0
--- /dev/null
+++ b/drivers/thermal/ti-lm74.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI LM74 temperature sensor driver
+ *
+ * Copyright (C) 2024 CS GROUP France
+ *
+ */
+
+#include
+#include
+#include
+
+static int ti_lm74_get_temp(struct udevice *dev, int *temp)
+{
+ char buf[2];
+ s16 raw;
+ int ret;
+
+ ret = dm_spi_claim_bus(dev);
+ if (ret)
+ return ret;
+
+ ret = dm_spi_xfer(dev, 16, NULL, buf, SPI_XFER_BEGIN | SPI_XFER_END);
+
+ dm_spi_release_bus(dev);
+ if (ret)
+ return ret;
+
+ raw = ((buf[0] << 8) + buf[1]) >> 3;
+
+ *temp = (((int)raw * 125) + 1000) / 2000;
+
+ return 0;
+}
+
+static struct dm_thermal_ops ti_lm74_ops = {
+ .get_temp = ti_lm74_get_temp,
+};
+
+static const struct udevice_id of_ti_lm74_match[] = {
+ {
+ .compatible = "ti,lm74",
+ },
+ {},
+};
+
+U_BOOT_DRIVER(ti_bandgap_thermal) = {
+ .name = "ti_lm74_thermal",
+ .id = UCLASS_THERMAL,
+ .ops= &ti_lm74_ops,
+ .of_match = of_ti_lm74_match,
+};
--
2.43.0
[PATCH v2 09/17] board: cssi: Add support for SPI bus on MCR3000 board
MCR3000 board has some components tied to the SPI bus, like the Texas
Instruments LM74 temperature sensor.
Add support for SPI bus. The SPI chipselects are a bit special in the
way that they are driven by 3 bits in a register of the board's CPLD
where the value writen in those bits exclusively activates one of the
7 possible chipselects and value 0 sets all chipselets to inactive.
So add a special GPIO driver that simulates GPIOs for those chipselect.
Signed-off-by: Christophe Leroy
---
arch/powerpc/dts/mcr3000.dts | 31 +
board/cssi/mcr3000/Makefile | 1 +
board/cssi/mcr3000/mcr3000.c | 5 ++
board/cssi/mcr3000/mcr3000_gpio.c | 109 ++
configs/MCR3000_defconfig | 5 ++
5 files changed, 151 insertions(+)
create mode 100644 board/cssi/mcr3000/mcr3000_gpio.c
diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts
index c4d7737bc6..edcd8358d0 100644
--- a/arch/powerpc/dts/mcr3000.dts
+++ b/arch/powerpc/dts/mcr3000.dts
@@ -26,6 +26,37 @@
timeout-sec = <2>;
hw_margin_ms = <1000>;
};
+
+ spi: spi@aa0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl,mpc8xx-spi";
+ };
+ };
+
+ localbus@ff000100 {
+ compatible = "s3k,mcr3000-localbus", "fsl,pq1-localbus",
"simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0xff000100 0x40>;// ORx and BRx register
+
+ ranges = <0 0 0x0400 0x0400 // BOOT
+ 1 0 0x 0x0400 // SDRAM
+ 2 0 0x0800 0x0400 // RAMDP
+ 3 0 0x0C00 0x0400 // NAND
+ 4 0 0x1000 0x0400 // Periphs
+ 5 0 0x1400 0x0400 // FPGA
+ 6 0 0x1800 0x0400 // mezzanine
+ 7 0 0x1c00 0x0400>; // DSP
+
+ csspi: gpio-controller@2 {
+ #gpio-cells = <2>;
+ compatible = "s3k,mcr3000-cpld-csspi";
+ reg = <4 0x802 2>;
+ gpio-controller;
+ };
};
SERIAL: smc@0 {
diff --git a/board/cssi/mcr3000/Makefile b/board/cssi/mcr3000/Makefile
index 7803016af3..846fd680e9 100644
--- a/board/cssi/mcr3000/Makefile
+++ b/board/cssi/mcr3000/Makefile
@@ -6,3 +6,4 @@
obj-y += mcr3000.o
obj-$(CONFIG_CMD_NAND) += nand.o
+obj-$(CONFIG_MPC8XX_SPI) += mcr3000_gpio.o
diff --git a/board/cssi/mcr3000/mcr3000.c b/board/cssi/mcr3000/mcr3000.c
index 8857c9e42c..537d7fa124 100644
--- a/board/cssi/mcr3000/mcr3000.c
+++ b/board/cssi/mcr3000/mcr3000.c
@@ -116,6 +116,11 @@ int misc_init_r(void)
clrbits_be16(&iop->iop_pcpar, 0x4);
clrbits_be16(&iop->iop_pcdir, 0x4);
+ /* Activate SPI */
+ clrsetbits_be32(&immr->im_cpm.cp_pbpar, 0x1, 0xe);
+ setbits_be32(&immr->im_cpm.cp_pbdir, 0xf);
+ clrbits_be32(&immr->im_cpm.cp_pbdat, 0x1);
+
/* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
env_set("bootdelay", "60");
diff --git a/board/cssi/mcr3000/mcr3000_gpio.c
b/board/cssi/mcr3000/mcr3000_gpio.c
new file mode 100644
index 00..2bba14e6e5
--- /dev/null
+++ b/board/cssi/mcr3000/mcr3000_gpio.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024 CS GROUP France
+ * Christophe Leroy
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "../common/common.h"
+
+struct mcr3000_spi_gpio_plat {
+ ulong addr;
+};
+
+struct mcr3000_spi_gpio_data {
+ void __iomem *base;
+};
+
+static int mcr3000_spi_gpio_set_value(struct udevice *dev, uint gpio, int
value)
+{
+ struct mcr3000_spi_gpio_data *data = dev_get_priv(dev);
+
+ if (value)
+ clrsetbits_be16(data->base, 7 << 5, (gpio & 7) << 5);
+ else
+ clrbits_be16(data->base, 7 << 5);
+
+ return 0;
+}
+
+static int mcr3000_spi_gpio_get_value(struct udevice *dev, uint gpio)
+{
+ struct mcr3000_spi_gpio_data *data = dev_get_priv(dev);
+
+ return gpio == ((in_be16(data->base) >> 5) & 7);
+}
+
+static int mcr3000_spi_gpio_direction_input(struct udevice *dev, uint gpio)
+{
+ return 0;
+}
+
+static int mcr3000_spi_gpio_get_function(struct udevice *dev, uint gpio)
+{
+ return GPIOF_OUTPUT;
+}
+
+static int mcr3000_spi_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+ struct mcr3000_spi_gpio_plat *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
+ u32 reg[2];
+
+ dev_read_u32_array(dev, "reg", reg, 2);
+ addr = dev_translat
[PATCH v2 10/17] board: cssi: add support for reading temperature
All CSSI boards have an LM74 chip as temperature sensor.
Enable it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/dts/cmpc885.dts | 12 +++-
arch/powerpc/dts/cmpcpro.dts | 12 +++-
arch/powerpc/dts/mcr3000.dts | 6 ++
configs/CMPC885_defconfig| 3 +++
configs/CMPCPRO_defconfig| 3 +++
configs/MCR3000_defconfig| 3 +++
6 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/dts/cmpc885.dts b/arch/powerpc/dts/cmpc885.dts
index 9a33e7e77c..454ceb91ca 100644
--- a/arch/powerpc/dts/cmpc885.dts
+++ b/arch/powerpc/dts/cmpc885.dts
@@ -85,12 +85,22 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc8xx-spi";
- gpios = <&CPM1_PIO_B 21 1>; /* /EEPROM_CS ACTIVE_LOW */
+ gpios = <&CPM1_PIO_B 21 1 /* /EEPROM_CS
ACTIVE_LOW */
+&CPM1_PIO_B 23 1 /* Temperature mother
board */
+&CPM1_PIO_B 14 1>; /* Temperature CPU
board */
eeprom@0 {
reg = <0>;
compatible = "atmel,at25", "cs,eeprom";
};
+ temp@1 {
+ reg = <1>;
+ compatible = "ti,lm74";
+ };
+ temp@2 {
+ reg = <2>;
+ compatible = "ti,lm74";
+ };
};
};
};
diff --git a/arch/powerpc/dts/cmpcpro.dts b/arch/powerpc/dts/cmpcpro.dts
index 78f8a9f4d3..1dfa864ebb 100644
--- a/arch/powerpc/dts/cmpcpro.dts
+++ b/arch/powerpc/dts/cmpcpro.dts
@@ -140,12 +140,22 @@
compatible = "fsl,mpc832x-spi";
reg = <0x4c0 0x40>;
mode = "cpu";
- gpios = <&qe_pio_d 3 1>;
+ gpios = <&qe_pio_d 3 1
+&qe_pio_c 5 1 /* TEMP mother board */
+&qe_pio_c 3 1>;/* TEMP CPU board */
clock-frequency = <0>;
eeprom@0 {
reg = <0>;
compatible = "atmel,at25", "cs,eeprom";
};
+ temp@1 {
+ reg = <1>;
+ compatible = "ti,lm74";
+ };
+ temp@2 {
+ reg = <2>;
+ compatible = "ti,lm74";
+ };
};
eth0: ucc@3000 {
device_type = "network";
diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts
index edcd8358d0..f678951e22 100644
--- a/arch/powerpc/dts/mcr3000.dts
+++ b/arch/powerpc/dts/mcr3000.dts
@@ -33,6 +33,12 @@
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl,mpc8xx-spi";
+ gpios = <&csspi 2 0>;
+
+ temp@0 {
+ reg = <0>;
+ compatible = "ti,lm74";
+ };
};
};
diff --git a/configs/CMPC885_defconfig b/configs/CMPC885_defconfig
index bbe8d5be7e..11c24f72a8 100644
--- a/configs/CMPC885_defconfig
+++ b/configs/CMPC885_defconfig
@@ -50,6 +50,7 @@ CONFIG_CMD_ASKENV=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_TEMPERATURE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_MII_INIT=y
@@ -107,6 +108,8 @@ CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MPC8XX_SPI=y
+CONFIG_DM_THERMAL=y
+CONFIG_TI_LM74_THERMAL=y
CONFIG_WDT=y
CONFIG_WDT_MPC8xxx_BME=y
# CONFIG_REGEX is not set
diff --git a/configs/CMPCPRO_defconfig b/configs/CMPCPRO_defconfig
index cefed63f24..f8f5c9fd86 100644
--- a/configs/CMPCPRO_defconfig
+++ b/configs/CMPCPRO_defconfig
@@ -134,6 +134,7 @@ CONFIG_CMD_ASKENV=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_TEMPERATURE=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y
@@ -197,6 +198,8 @@ CONFIG_DM_SPI=y
CONFIG_MPC8XXX_SPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_MPC83XX=y
+CONFIG_DM_THERMAL=y
+CONFIG_TI_LM74_THERMAL=y
CONFIG_WDT=y
CONFIG_WDT_MPC8xxx=y
# CONFIG_REGEX is not set
diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig
index ce34c2aa88..f2eac2c544 100644
--- a/configs/MCR3000_defconfig
+++ b/configs/MCR3000_defconfig
@@ -47,6 +47,7 @@ CONFIG_CMD_ASKENV=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_TEMPERATURE=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
@@ -107,6 +108,8 @@ CONFIG_D
[PATCH v2 11/17] powerpc: 8xx: Set SDMA configuration register correcly
SDMA configuration register needs to be set up only once and doesn't belong to drivers. Also, the value to be used is different on mpc885. So do the init in cpu_init_f() with 0x40 for mpc885 and 0x1 for others. Signed-off-by: Christophe Leroy --- arch/powerpc/cpu/mpc8xx/cpu_init.c | 6 ++ drivers/spi/mpc8xx_spi.c | 4 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index aac4203a6e..d1abe8f00b 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -92,6 +92,12 @@ void cpu_init_f(immap_t __iomem *immr) CONFIG_SYS_PLPRCR); #endif + /* Set SDMA configuration register */ + if (IS_ENABLED(CONFIG_MPC885)) + out_be32(&immr->im_siu_conf.sc_sdcr, 0x0040); + else + out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001); + /* * Memory Controller: */ diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c index 2aa9c7d5df..0d142f12e9 100644 --- a/drivers/spi/mpc8xx_spi.c +++ b/drivers/spi/mpc8xx_spi.c @@ -103,10 +103,6 @@ static int mpc8xx_spi_probe(struct udevice *dev) while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) ; -/* 5 */ - /* Set SDMA configuration register */ - out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001); - /* 6 */ /* Set to big endian. */ out_8(&spi->spi_tfcr, SMC_EB); -- 2.43.0
[PATCH v2 12/17] spi: mpc8xx: Allow transfer of more than MAX_BUFFER len
Perform multiple transfer of size MAX_BUFFER when the data to be
transferred is longer than MAX_BUFFER.
Signed-off-by: Christophe Leroy
---
drivers/spi/mpc8xx_spi.c | 48
1 file changed, 34 insertions(+), 14 deletions(-)
diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c
index 0d142f12e9..a193ac711b 100644
--- a/drivers/spi/mpc8xx_spi.c
+++ b/drivers/spi/mpc8xx_spi.c
@@ -143,27 +143,17 @@ static void mpc8xx_spi_cs_deactivate(struct udevice *dev)
dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
}
-static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+static int mpc8xx_spi_xfer_one(struct udevice *dev, size_t count,
+ const void *dout, void *din)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &immr->im_cpm;
cbd_t __iomem *tbdf, *rbdf;
int tm;
- size_t count = (bitlen + 7) / 8;
-
- if (!din && !dout)
- return -EINVAL;
- if (count > MAX_BUFFER)
- return -EINVAL;
tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
- /* Set CS for device */
- if (flags & SPI_XFER_BEGIN)
- mpc8xx_spi_cs_activate(dev);
-
/* Setting tx bd status and data length */
out_be32(&tbdf->cbd_bufaddr, dout ? (ulong)dout : (ulong)dummy_buffer);
out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
@@ -196,13 +186,43 @@ static int mpc8xx_spi_xfer(struct udevice *dev, unsigned
int bitlen,
}
if (tm >= 1000)
- printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
+ return -ETIMEDOUT;
+
+ return 0;
+}
+static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ size_t count = (bitlen + 7) / 8;
+ size_t offset = 0;
+ int ret = 0;
+
+ if (!din && !dout)
+ return -EINVAL;
+
+ /* Set CS for device */
+ if (flags & SPI_XFER_BEGIN)
+ mpc8xx_spi_cs_activate(dev);
+
+ while (count > 0 && !ret) {
+ size_t chunk = min(count, (size_t)MAX_BUFFER);
+ const void *out = dout ? dout + offset : NULL;
+ void *in = din ? din + offset : NULL;
+
+ ret = mpc8xx_spi_xfer_one(dev, chunk, out, in);
+
+ offset += chunk;
+ count -= chunk;
+ }
/* Clear CS for device */
if (flags & SPI_XFER_END)
mpc8xx_spi_cs_deactivate(dev);
- return 0;
+ if (ret)
+ printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
+
+ return ret;
}
static int mpc8xx_spi_ofdata_to_platdata(struct udevice *dev)
--
2.43.0
[PATCH v2 13/17] spi: mpc8xx: Use 16 bit mode for large transfers with even size
On CPM, the RISC core is a lot more efficiant when doing transfers
in 16-bits chunks than in 8-bits chunks, but unfortunately the
words need to be byte swapped.
So, for large tranfers with an even size, allocate a temporary
buffer and byte-swap data before and after transfer.
This change allows setting higher speed for transfer. For instance
on an MPC 8xx (CPM1 comms RISC processor), the documentation tells
that transfer in byte mode at 1 kbit/s uses 0.200% of CPM load
at 25 MHz while a word transfer at the same speed uses 0.032%
of CPM load. This means the speed can be 6 times higher in
word mode for the same CPM load.
For small transfers, the load reduction is not worth the CPU load
required to allocate the temporary buffer, so do it only when data
size is over 64 bytes.
Signed-off-by: Christophe Leroy
---
drivers/spi/mpc8xx_spi.c | 44 +---
1 file changed, 41 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c
index a193ac711b..b1abfbf4fc 100644
--- a/drivers/spi/mpc8xx_spi.c
+++ b/drivers/spi/mpc8xx_spi.c
@@ -18,6 +18,7 @@
#include
#include
+#include
#include
#include
#include
@@ -30,6 +31,7 @@
#define CPM_SPI_BASE_TX(CPM_SPI_BASE + sizeof(cbd_t))
#define MAX_BUFFER 0x8000 /* Max possible is 0x. We want power of 2 */
+#define MIN_HWORD_XFER 64 /* Minimum size for 16 bits transfer */
struct mpc8xx_priv {
spi_t __iomem *spi;
@@ -149,23 +151,46 @@ static int mpc8xx_spi_xfer_one(struct udevice *dev,
size_t count,
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &immr->im_cpm;
cbd_t __iomem *tbdf, *rbdf;
+ void *bufout, *bufin;
+ u16 spmode_len;
int tm;
tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
+ if (!(count & 1) && count >= MIN_HWORD_XFER) {
+ spmode_len = SPMODE_LEN(16);
+ if (dout) {
+ int i;
+
+ bufout = malloc(count);
+ for (i = 0; i < count; i += 2)
+ *(u16 *)(bufout + i) = swab16(*(u16 *)(dout +
i));
+ } else {
+ bufout = NULL;
+ }
+ if (din)
+ bufin = malloc(count);
+ else
+ bufin = NULL;
+ } else {
+ spmode_len = SPMODE_LEN(8);
+ bufout = (void *)dout;
+ bufin = din;
+ }
+
/* Setting tx bd status and data length */
- out_be32(&tbdf->cbd_bufaddr, dout ? (ulong)dout : (ulong)dummy_buffer);
+ out_be32(&tbdf->cbd_bufaddr, bufout ? (ulong)bufout :
(ulong)dummy_buffer);
out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
out_be16(&tbdf->cbd_datlen, count);
/* Setting rx bd status and data length */
- out_be32(&rbdf->cbd_bufaddr, din ? (ulong)din : (ulong)dummy_buffer);
+ out_be32(&rbdf->cbd_bufaddr, bufin ? (ulong)bufin :
(ulong)dummy_buffer);
out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
- SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8));
+ SPMODE_EN | spmode_len | SPMODE_PM(0x8));
out_8(&cp->cp_spim, 0); /* Mask all SPI events */
out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
@@ -188,6 +213,19 @@ static int mpc8xx_spi_xfer_one(struct udevice *dev, size_t
count,
if (tm >= 1000)
return -ETIMEDOUT;
+ if (!(count & 1) && count > MIN_HWORD_XFER) {
+ if (dout)
+ free(bufout);
+ if (din) {
+ int i;
+
+ bufout = malloc(count);
+ for (i = 0; i < count; i += 2)
+ *(u16 *)(din + i) = swab16(*(u16 *)(bufin + i));
+ free(bufin);
+ }
+ }
+
return 0;
}
--
2.43.0
[PATCH v2 14/17] spi: mpc8xx: Set up speed as requested
Set the speed requested through mpc8xx_spi_set_speed() instead
of hardcoding a fixed speed.
Signed-off-by: Christophe Leroy
---
drivers/spi/mpc8xx_spi.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c
index b1abfbf4fc..e1448cc619 100644
--- a/drivers/spi/mpc8xx_spi.c
+++ b/drivers/spi/mpc8xx_spi.c
@@ -48,6 +48,21 @@ static int mpc8xx_spi_set_mode(struct udevice *dev, uint mod)
static int mpc8xx_spi_set_speed(struct udevice *dev, uint speed)
{
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cp = &immr->im_cpm;
+ u8 pm = (gd->arch.brg_clk - 1) / (speed * 16);
+
+ if (pm > 16) {
+ setbits_be16(&cp->cp_spmode, SPMODE_DIV16);
+ pm /= 16;
+ if (pm > 16)
+ pm = 16;
+ } else {
+ clrbits_be16(&cp->cp_spmode, SPMODE_DIV16);
+ }
+
+ clrsetbits_be16(&cp->cp_spmode, SPMODE_PM(0xf), SPMODE_PM(pm));
+
return 0;
}
@@ -189,8 +204,8 @@ static int mpc8xx_spi_xfer_one(struct udevice *dev, size_t
count,
out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
- clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
- SPMODE_EN | spmode_len | SPMODE_PM(0x8));
+ clrsetbits_be16(&cp->cp_spmode, ~(SPMODE_LOOP | SPMODE_PM(0xf) |
SPMODE_DIV16),
+ SPMODE_REV | SPMODE_MSTR | SPMODE_EN | spmode_len);
out_8(&cp->cp_spim, 0); /* Mask all SPI events */
out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
--
2.43.0
[PATCH v2 15/17] board: cssi: Use HAVE_VENDOR_COMMON_LIB logic
Instead of cross using cross-directory makefile directives, add a Makefile in board/cssi/common/ directory in order to benefit from HAVE_VENDOR_COMMON_LIB logic. Signed-off-by: Christophe Leroy --- board/cssi/cmpc885/Makefile | 2 +- board/cssi/cmpcpro/Makefile | 2 +- board/cssi/common/Makefile | 8 3 files changed, 10 insertions(+), 2 deletions(-) create mode 100644 board/cssi/common/Makefile diff --git a/board/cssi/cmpc885/Makefile b/board/cssi/cmpc885/Makefile index baf9e5ab4f..6c055097cd 100644 --- a/board/cssi/cmpc885/Makefile +++ b/board/cssi/cmpc885/Makefile @@ -5,6 +5,6 @@ # Christophe Leroy # -obj-y += cmpc885.o ../common/common.o +obj-y += cmpc885.o obj-y += sdram.o obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/board/cssi/cmpcpro/Makefile b/board/cssi/cmpcpro/Makefile index 73ff451ea1..30837781af 100644 --- a/board/cssi/cmpcpro/Makefile +++ b/board/cssi/cmpcpro/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cmpcpro.o nand.o ../common/common.o +obj-y += cmpcpro.o nand.o diff --git a/board/cssi/common/Makefile b/board/cssi/common/Makefile new file mode 100644 index 00..973582639e --- /dev/null +++ b/board/cssi/common/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 CS GROUP France +# Christophe Leroy +# + +obj-$(CONFIG_TARGET_CMPC885) += common.o +obj-$(CONFIG_TARGET_CMPCPRO) += common.o -- 2.43.0
[PATCH v2 16/17] board: cssi: Load FPGA on MCR3000 board
Unlike CMPC885 and CMPCPRO boards, the FPGA of MCR3000 board doesn't
load code automatically but needs to be loaded by software through SPI.
Until now it was loaded later by Linux, but we'd like U-boot to have
access to some information that require the FPGA, like board address
in racks.
So, implemented the load of FPGA in U-boot.
Signed-off-by: Christophe Leroy
---
To avoid spamming your email boxes, the code isn't included in
the emailed patch but will be present in the PULL request
---
arch/powerpc/dts/mcr3000.dts | 6 -
board/cssi/mcr3000/fpga_code.h | 10 +++
board/cssi/mcr3000/mcr3000.c | 48 ++
3 files changed, 63 insertions(+), 1 deletion(-)
create mode 100644 board/cssi/mcr3000/fpga_code.h
diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts
index f678951e22..aa46007b8d 100644
--- a/arch/powerpc/dts/mcr3000.dts
+++ b/arch/powerpc/dts/mcr3000.dts
@@ -33,12 +33,16 @@
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl,mpc8xx-spi";
- gpios = <&csspi 2 0>;
+ gpios = <&csspi 2 0
+&csspi 0 0>;
temp@0 {
reg = <0>;
compatible = "ti,lm74";
};
+ fpga@1 {
+ reg = <1>;
+ };
};
};
diff --git a/board/cssi/mcr3000/fpga_code.h b/board/cssi/mcr3000/fpga_code.h
new file mode 100644
index 00..0d710ba41f
--- /dev/null
+++ b/board/cssi/mcr3000/fpga_code.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010 CS Systemes d'Information
+ *
+ * uCORE FPGA code for MCR3000 board
+ */
+
+u32 fpga_code[] = {
+ 0xdeadbeef,
+};
diff --git a/board/cssi/mcr3000/mcr3000.c b/board/cssi/mcr3000/mcr3000.c
index 537d7fa124..15a2d0d946 100644
--- a/board/cssi/mcr3000/mcr3000.c
+++ b/board/cssi/mcr3000/mcr3000.c
@@ -13,12 +13,15 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include
+#include "fpga_code.h"
+
DECLARE_GLOBAL_DATA_PTR;
#define SDRAM_MAX_SIZE (32 * 1024 * 1024)
@@ -107,6 +110,49 @@ int dram_init(void)
return 0;
}
+static int load_fpga(void)
+{
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ struct udevice *master;
+ struct spi_slave *slave;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_SPI, 0, &master);
+ if (ret)
+ return ret;
+
+ ret = _spi_get_bus_and_cs(0, 1, 1000, 0, "spi_generic_drv",
+ "generic_0:0", &master, &slave);
+ if (ret)
+ return ret;
+
+ ret = spi_claim_bus(slave);
+
+ printf("FPGA Init ... ");
+
+ clrbits_be32(&immr->im_cpm.cp_pbdat, 0x2);
+ while ((in_be32(&immr->im_cpm.cp_pbdat) & 0x8000))
+ ;
+ setbits_be32(&immr->im_cpm.cp_pbdat, 0x2);
+ while (!(in_be32(&immr->im_cpm.cp_pbdat) & 0x8000))
+ ;
+
+ printf("Loading ... ");
+
+ ret = spi_xfer(slave, sizeof(fpga_code) * BITS_PER_BYTE, fpga_code,
NULL, 0);
+
+ spi_release_bus(slave);
+
+ if ((in_be32(&immr->im_cpm.cp_pbdat) & 0x4000)) {
+ printf("Done\n");
+ } else {
+ printf("FAILED\n");
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
int misc_init_r(void)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -121,6 +167,8 @@ int misc_init_r(void)
setbits_be32(&immr->im_cpm.cp_pbdir, 0xf);
clrbits_be32(&immr->im_cpm.cp_pbdat, 0x1);
+ load_fpga();
+
/* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
env_set("bootdelay", "60");
--
2.43.0
[PATCH v2 17/17] board: cssi: Read and display MCR board address
MCR boards are plugged in racks. The position in the rack can be read
in a register.
For MCR3000, that's provided by the FPGA so check it is loaded before
reading the address.
For the other boards, the FPGA is loaded by hardware so it can be
read inconditionnaly.
Signed-off-by: Christophe Leroy
---
board/cssi/common/common.c | 6 +-
board/cssi/mcr3000/mcr3000.c | 7 ++-
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/board/cssi/common/common.c b/board/cssi/common/common.c
index 6848efd43b..0292a9016e 100644
--- a/board/cssi/common/common.c
+++ b/board/cssi/common/common.c
@@ -164,7 +164,7 @@ int checkboard_common(void)
void misc_init_r_common(void)
{
- u8 tmp, far_id;
+ u8 tmp, far_id, addr;
int count = 3;
switch (in_8(ADDR_FPGA_R_BASE)) {
@@ -173,6 +173,10 @@ void misc_init_r_common(void)
if ((in_8(ADDR_FPGA_R_BASE + 0x31) & FPGA_R_ACQ_AL_FAV) == 0)
env_set("bootdelay", "60");
+ addr = in_8(ADDR_FPGA_R_BASE + 0x43);
+ printf("Board address: 0x%2.2x (System %d Rack %d Slot %d)\n",
+ addr, addr >> 7, (addr >> 4) & 7, addr & 15);
+
env_set("config", CFG_BOARD_MCR3000_2G);
env_set("hostname", CFG_BOARD_MCR3000_2G);
break;
diff --git a/board/cssi/mcr3000/mcr3000.c b/board/cssi/mcr3000/mcr3000.c
index 15a2d0d946..48e82a902d 100644
--- a/board/cssi/mcr3000/mcr3000.c
+++ b/board/cssi/mcr3000/mcr3000.c
@@ -167,7 +167,12 @@ int misc_init_r(void)
setbits_be32(&immr->im_cpm.cp_pbdir, 0xf);
clrbits_be32(&immr->im_cpm.cp_pbdat, 0x1);
- load_fpga();
+ if (!load_fpga()) {
+ u8 addr = in_be16((void *)0x149c);
+
+ printf("Board address: 0x%2.2x (System %d Rack %d Slot %d)\n",
+ addr, addr >> 7, (addr >> 4) & 7, addr & 15);
+ }
/* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
--
2.43.0
Re: [PATCH v2 0/6] mtd: nand: raw: Collected improvements
Hello Dario, Am Sun, Apr 14, 2024 at 03:41:38PM +0200 schrieb Dario Binacchi: > Hi Alexander, > > On Wed, Mar 20, 2024 at 10:02 AM Alexander Dahl wrote: > > > > Hello everyone, > > > > while working on NAND flash support for a custom board based on the at91 > > SAM9X60 SoC I stumbled over some issues in the raw nand subsystem. > > > > Four of six patches are minor fixes. > > > > Patch 4 introduces a new subcommand for the new atmel nand controller > > driver. Patch 6 introduces a new subcommand for the nand command to > > override ONFI timing mode. Both are are for debugging purposes only and > > thus optional, and need to be enabled through menu. Both helped me a > > lot when investigating issues. > > > > Series is based on upstream next branch, but should also apply to master > > cleanly. > > > > Greets > > Alex > > > > v1: > > > > Link: > > https://lore.kernel.org/u-boot/20240307091014.39796-1-...@thorsis.com/T/#t > > > > v2: > > > > - rebased on recent next > > - collected tags > > - improved patch 4 after feedback from Mihai > > - added new patch 5 with another help text fix > > - added new patch 6 with a new debug command > > - reworded cover letter > > > > See per patch changes in patches for more detailed changes. > > > > Alexander Dahl (6): > > mtd: nand: raw: Use macro nand_to_mtd() where appropriate > > mtd: nand: raw: Port another option flag from Linux > > mtd: nand: raw: Fix (most) Kconfig indentation > > mtd: nand: raw: atmel: Introduce optional debug commands > > mtd: nand: raw: atmel: Fix comment in timings preparation > > cmd: nand: Add new optional sub-command 'onfi' > > > > cmd/Kconfig | 10 + > > cmd/nand.c | 61 > > drivers/mtd/nand/raw/Kconfig | 115 +++ > > drivers/mtd/nand/raw/atmel/nand-controller.c | 299 ++- > > drivers/mtd/nand/raw/nand_base.c | 8 +- > > include/linux/mtd/rawnand.h | 8 + > > 6 files changed, 441 insertions(+), 60 deletions(-) > > > > > > base-commit: f048104999db28d49362201eaebfc91adb14f47c > > -- > > 2.39.2 > > > Applied to nand-next the first 4 patches. > For the others, we will conduct further testing before applying them. Thanks so far. :-) I have another fix for the atmel raw nand driver, which I forgot to send with this series. I could add it to v3. Or should I send it separately? Greets Alex
Re: [PATCH v2 03/23] rockchip: rk35xx: Drop USB_GADGET_PRODUCT_NUM Kconfig option
On 2024-04-13 20:13, Jonas Karlman wrote:
The commit 8c19275fdb13 ("rockchip: Update the default USB Product ID
value") added default product id for all supported Rockchip SoCs.
Remove USB_GADGET_PRODUCT_NUM options that match default value from
RK35xx boards.
Signed-off-by: Jonas Karlman
Looking good to me.
Reviewed-by: Dragan Simic
---
v2: No change
---
configs/pinetab2-rk3566_defconfig | 1 -
configs/rock5b-rk3588_defconfig | 1 -
configs/turing-rk1-rk3588_defconfig | 1 -
3 files changed, 3 deletions(-)
diff --git a/configs/pinetab2-rk3566_defconfig
b/configs/pinetab2-rk3566_defconfig
index bc7a77aa52fd..edeb1d89b993 100644
--- a/configs/pinetab2-rk3566_defconfig
+++ b/configs/pinetab2-rk3566_defconfig
@@ -99,7 +99,6 @@ CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
diff --git a/configs/rock5b-rk3588_defconfig
b/configs/rock5b-rk3588_defconfig
index 58c7c44fb4f7..ac4f1ebb4c13 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -102,7 +102,6 @@ CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_PRODUCT_NUM=0x350b
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
diff --git a/configs/turing-rk1-rk3588_defconfig
b/configs/turing-rk1-rk3588_defconfig
index 07f7b848529e..e18ced721789 100644
--- a/configs/turing-rk1-rk3588_defconfig
+++ b/configs/turing-rk1-rk3588_defconfig
@@ -109,7 +109,6 @@ CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_PRODUCT_NUM=0x350b
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
Re: [PATCH v2 04/23] rockchip: rk3588: Drop REGULATOR_PWM Kconfig option
On 2024-04-13 20:13, Jonas Karlman wrote: RK3588 boards do not have any pwm-regulator compatible nodes in DT, drop the superfluous REGULATOR_PWM Kconfig options. Signed-off-by: Jonas Karlman Looking good to me. Reviewed-by: Dragan Simic --- v2: No change --- configs/evb-rk3588_defconfig | 1 - configs/neu6a-io-rk3588_defconfig| 1 - configs/neu6b-io-rk3588_defconfig| 1 - configs/quartzpro64-rk3588_defconfig | 1 - configs/rock5b-rk3588_defconfig | 1 - configs/toybrick-rk3588_defconfig| 1 - configs/turing-rk1-rk3588_defconfig | 1 - 7 files changed, 7 deletions(-) diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig index c8db04c076ef..68ecbc54b807 100644 --- a/configs/evb-rk3588_defconfig +++ b/configs/evb-rk3588_defconfig @@ -52,7 +52,6 @@ CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_PHY_ROCKCHIP_USBDP=y -CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=150 diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig index 307a540f4249..bc2d70421ee9 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -40,7 +40,6 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=150 diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig index 9ef2bb21fffa..8bc75a5f0dd9 100644 --- a/configs/neu6b-io-rk3588_defconfig +++ b/configs/neu6b-io-rk3588_defconfig @@ -40,7 +40,6 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=150 diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig index b2a66d3f2db0..ee2521f87ae5 100644 --- a/configs/quartzpro64-rk3588_defconfig +++ b/configs/quartzpro64-rk3588_defconfig @@ -64,7 +64,6 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y -CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_SCSI=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index ac4f1ebb4c13..8af56baf04d7 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -75,7 +75,6 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y -CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_SCSI=y diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig index 6ee92e943138..38fc7906eef2 100644 --- a/configs/toybrick-rk3588_defconfig +++ b/configs/toybrick-rk3588_defconfig @@ -53,7 +53,6 @@ CONFIG_PHY_REALTEK=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=150 diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig index e18ced721789..77aacbc64b6c 100644 --- a/configs/turing-rk1-rk3588_defconfig +++ b/configs/turing-rk1-rk3588_defconfig @@ -81,7 +81,6 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y -CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_SCSI=y
Re: [PATCH v2 06/23] rockchip: rk35xx: Sort imply statements alphabetically
On 2024-04-13 20:13, Jonas Karlman wrote: Sort imply statements under ROCKCHIP_RK3568 and ROCKCHIP_RK3588 alphabetically. Signed-off-by: Jonas Karlman Looking good to me. Reviewed-by: Dragan Simic --- v2: No change --- arch/arm/mach-rockchip/Kconfig | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index fee463e6d92f..649c22618f36 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -305,12 +305,12 @@ config ROCKCHIP_RK3568 select BOARD_LATE_INIT select DM_REGULATOR_FIXED select DM_RESET - imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - imply ROCKCHIP_COMMON_BOARD - imply OF_LIBFDT_OVERLAY - imply ROCKCHIP_OTP imply MISC_INIT_R imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP + imply OF_LIBFDT_OVERLAY + imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_OTP + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT help The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55, @@ -332,16 +332,16 @@ config ROCKCHIP_RK3588 select BOARD_LATE_INIT select DM_REGULATOR_FIXED select DM_RESET - imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - imply ROCKCHIP_COMMON_BOARD - imply OF_LIBFDT_OVERLAY - imply ROCKCHIP_OTP - imply MISC_INIT_R - imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP - imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT + imply BOOTSTD_FULL imply CLK_SCMI + imply MISC_INIT_R + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP + imply OF_LIBFDT_OVERLAY + imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_OTP imply SCMI_FIRMWARE - imply BOOTSTD_FULL + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT help The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
Re: [PATCH v2 0/6] mtd: nand: raw: Collected improvements
Hello Alexander, On Mon, Apr 15, 2024 at 8:13 AM Alexander Dahl wrote: > > Hello Dario, > > Am Sun, Apr 14, 2024 at 03:41:38PM +0200 schrieb Dario Binacchi: > > Hi Alexander, > > > > On Wed, Mar 20, 2024 at 10:02 AM Alexander Dahl wrote: > > > > > > Hello everyone, > > > > > > while working on NAND flash support for a custom board based on the at91 > > > SAM9X60 SoC I stumbled over some issues in the raw nand subsystem. > > > > > > Four of six patches are minor fixes. > > > > > > Patch 4 introduces a new subcommand for the new atmel nand controller > > > driver. Patch 6 introduces a new subcommand for the nand command to > > > override ONFI timing mode. Both are are for debugging purposes only and > > > thus optional, and need to be enabled through menu. Both helped me a > > > lot when investigating issues. > > > > > > Series is based on upstream next branch, but should also apply to master > > > cleanly. > > > > > > Greets > > > Alex > > > > > > v1: > > > > > > Link: > > > https://lore.kernel.org/u-boot/20240307091014.39796-1-...@thorsis.com/T/#t > > > > > > v2: > > > > > > - rebased on recent next > > > - collected tags > > > - improved patch 4 after feedback from Mihai > > > - added new patch 5 with another help text fix > > > - added new patch 6 with a new debug command > > > - reworded cover letter > > > > > > See per patch changes in patches for more detailed changes. > > > > > > Alexander Dahl (6): > > > mtd: nand: raw: Use macro nand_to_mtd() where appropriate > > > mtd: nand: raw: Port another option flag from Linux > > > mtd: nand: raw: Fix (most) Kconfig indentation > > > mtd: nand: raw: atmel: Introduce optional debug commands > > > mtd: nand: raw: atmel: Fix comment in timings preparation > > > cmd: nand: Add new optional sub-command 'onfi' > > > > > > cmd/Kconfig | 10 + > > > cmd/nand.c | 61 > > > drivers/mtd/nand/raw/Kconfig | 115 +++ > > > drivers/mtd/nand/raw/atmel/nand-controller.c | 299 ++- > > > drivers/mtd/nand/raw/nand_base.c | 8 +- > > > include/linux/mtd/rawnand.h | 8 + > > > 6 files changed, 441 insertions(+), 60 deletions(-) > > > > > > > > > base-commit: f048104999db28d49362201eaebfc91adb14f47c > > > -- > > > 2.39.2 > > > > > Applied to nand-next the first 4 patches. > > For the others, we will conduct further testing before applying them. > > Thanks so far. :-) > > I have another fix for the atmel raw nand driver, which I forgot to > send with this series. I could add it to v3. Of course, feel free to add it to version 3. Thanks and regards, Dario > Or should I send it > separately? > > Greets > Alex -- Dario Binacchi Senior Embedded Linux Developer dario.binac...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH v2 07/23] rockchip: rk35xx: Enable random generator
Hello Jonas,
Please see a couple of comments below.
On 2024-04-13 20:13, Jonas Karlman wrote:
The RK35xx SoCs contain a crypto engine block that can generate random
numbers.
Enable rng node in soc u-boot.dtsi and enable Kconfig options to take
advantage of the random generator.
Signed-off-by: Jonas Karlman
---
v2: No change
---
arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 6 --
arch/arm/dts/rk356x-u-boot.dtsi| 5 +
arch/arm/dts/rk3588s-u-boot.dtsi | 1 -
arch/arm/mach-rockchip/Kconfig | 4
configs/anbernic-rgxx3-rk3566_defconfig| 2 --
5 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
index 791f16b206f2..793ed4ae8ae0 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
@@ -6,12 +6,6 @@
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc1, &sdmmc0;
};
-
- rng: rng@fe388000 {
- compatible = "rockchip,cryptov2-rng";
- reg = <0x0 0xfe388000 0x0 0x2000>;
- status = "okay";
- };
};
&dsi_dphy0 {
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi
b/arch/arm/dts/rk356x-u-boot.dtsi
index d347080577d9..05367216e118 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -21,6 +21,11 @@
bootph-all;
};
+ rng: rng@fe388000 {
+ compatible = "rockchip,cryptov2-rng";
+ reg = <0x0 0xfe388000 0x0 0x2000>;
Shouldn't
+ status = "okay";
also be specified here?
+ };
+
otp: nvmem@fe38c000 {
compatible = "rockchip,rk3568-otp";
reg = <0x0 0xfe38c000 0x0 0x4000>;
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi
b/arch/arm/dts/rk3588s-u-boot.dtsi
index ac67c777adea..233eb79d9ba2 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -91,7 +91,6 @@
rng: rng@fe378000 {
compatible = "rockchip,trngv1";
reg = <0x0 0xfe378000 0x0 0x200>;
- status = "disabled";
Shouldn't it be enabled instead?
};
usbdp_phy0: phy@fed8 {
diff --git a/arch/arm/mach-rockchip/Kconfig
b/arch/arm/mach-rockchip/Kconfig
index 649c22618f36..247b9a3146c2 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -305,9 +305,11 @@ config ROCKCHIP_RK3568
select BOARD_LATE_INIT
select DM_REGULATOR_FIXED
select DM_RESET
+ imply DM_RNG
imply MISC_INIT_R
imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
imply OF_LIBFDT_OVERLAY
+ imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_OTP
imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
@@ -334,9 +336,11 @@ config ROCKCHIP_RK3588
select DM_RESET
imply BOOTSTD_FULL
imply CLK_SCMI
+ imply DM_RNG
imply MISC_INIT_R
imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
imply OF_LIBFDT_OVERLAY
+ imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_OTP
imply SCMI_FIRMWARE
diff --git a/configs/anbernic-rgxx3-rk3566_defconfig
b/configs/anbernic-rgxx3-rk3566_defconfig
index 24b050c59b53..110237e798f9 100644
--- a/configs/anbernic-rgxx3-rk3566_defconfig
+++ b/configs/anbernic-rgxx3-rk3566_defconfig
@@ -68,8 +68,6 @@ CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
# CONFIG_RNG_SMCCC_TRNG is not set
CONFIG_BAUDRATE=150
CONFIG_DEBUG_UART_SHIFT=2
Re: [PATCH v2 08/23] rockchip: rk35xx: Imply support for GbE PHY
On 2024-04-13 20:13, Jonas Karlman wrote: Imply support for GbE PHY status parsing and configuration when support for onboard ethernet is enabled. s/ethernet/Ethernet/ -- only if there will be v3 Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Looking good to me. Reviewed-by: Dragan Simic --- v2: Collect r-b tag --- arch/arm/mach-rockchip/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 247b9a3146c2..88bab9c7b3bf 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -309,6 +309,7 @@ config ROCKCHIP_RK3568 imply MISC_INIT_R imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP imply OF_LIBFDT_OVERLAY + imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_OTP @@ -340,6 +341,7 @@ config ROCKCHIP_RK3588 imply MISC_INIT_R imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP imply OF_LIBFDT_OVERLAY + imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_OTP
Re: [PATCH v2 09/23] rockchip: rk356x: Imply enhanced features for standard boot
On 2024-04-13 20:13, Jonas Karlman wrote: Imply BOOTSTD_FULL for all RK356x boards to more closely follow RK3588. Signed-off-by: Jonas Karlman Looking good to me. Reviewed-by: Dragan Simic --- v2: No change --- arch/arm/mach-rockchip/Kconfig | 1 + configs/bpi-r2-pro-rk3568_defconfig | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 88bab9c7b3bf..22eccaaf5cb1 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -305,6 +305,7 @@ config ROCKCHIP_RK3568 select BOARD_LATE_INIT select DM_REGULATOR_FIXED select DM_RESET + imply BOOTSTD_FULL imply DM_RNG imply MISC_INIT_R imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig index 5cc95241ba43..70837574462b 100644 --- a/configs/bpi-r2-pro-rk3568_defconfig +++ b/configs/bpi-r2-pro-rk3568_defconfig @@ -15,7 +15,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_BOOTSTD_FULL=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb" # CONFIG_DISPLAY_CPUINFO is not set
Re: [PATCH v2 14/23] rockchip: rk3588-coolpi: Add boards to documentation
On 2024-04-13 20:13, Jonas Karlman wrote:
Add the CoolPi 4 Model B and CoolPi CM5 EVB board to the documentation.
Also fix .dtb-file entries in Makefile.
Perhaps the patch subject could be improved a bit to also mention
fixing of the Makefile, but only if there will be v3.
Fixes: 3e15dee38d45 ("board: rockchip: Add support for rk3588 based
Cool Pi CM5 EVB")
Signed-off-by: Jonas Karlman
Looking good to me.
Reviewed-by: Dragan Simic
---
v2: No change
---
arch/arm/dts/Makefile | 4 ++--
doc/board/rockchip/rockchip.rst | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 08dfbdd557b7..38d259a7035c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -167,8 +167,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
- rk3588s-coolpi-4b.dts \
- rk3588-coolpi-cm5-evb.dts \
+ rk3588s-coolpi-4b.dtb \
+ rk3588-coolpi-cm5-evb.dtb \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
diff --git a/doc/board/rockchip/rockchip.rst
b/doc/board/rockchip/rockchip.rst
index 5dd5ea7f1e29..9a726e9cde63 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -131,6 +131,8 @@ List of mainline supported Rockchip boards:
- Turing Machines RK1 (turing-rk1-rk3588)
- Xunlong Orange Pi 5 (orangepi-5-rk3588s)
- Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588)
+ - Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s)
+ - Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588)
* rv1108
- Rockchip Evb-rv1108 (evb-rv1108)
RE: [PATCH v2 1/3] mmc: hi6220-dwmmc: handle clocks and resets if CONFIG_CLK and CONFIG_DM_RESET enabled
Hi,
> -Original Message-
> From: Yang Xiwen
> Sent: Wednesday, April 3, 2024 10:16 AM
> To: Jaehoon Chung ; Peng Fan
> Cc: u-boot@lists.denx.de
> Subject: Re: [PATCH v2 1/3] mmc: hi6220-dwmmc: handle clocks and resets if
> CONFIG_CLK and
> CONFIG_DM_RESET enabled
>
> On 4/3/2024 8:39 AM, Jaehoon Chung wrote:
> > Hi,
> >
> > On 2/1/24 23:05, Yang Xiwen via B4 Relay wrote:
> >> From: Yang Xiwen
> >>
> >> This can avoid hardcoding a clock rate in driver. Also can enable the
> >> clocks and deassert the resets if the pre-bootloader does not do this
> >> for us.
> >>
> >> Currently only enabled for Hi3798MV200.
> >>
> >> Signed-off-by: Yang Xiwen
Reviewed-by: Jaehoon Chung
> >> ---
> >> drivers/mmc/hi6220_dw_mmc.c | 61
> >> -
> >> 1 file changed, 60 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
> >> index 71962cd47e..a4b8072976 100644
> >> --- a/drivers/mmc/hi6220_dw_mmc.c
> >> +++ b/drivers/mmc/hi6220_dw_mmc.c
> >> @@ -5,15 +5,24 @@
> >>*/
> >>
> >> #include
> >> +#include
> >> #include
> >> #include
> >> #include
> >> #include
> >> #include
> >> +#include
> >> #include
> >> +#include
> >>
> >> DECLARE_GLOBAL_DATA_PTR;
> >>
> >> +enum hi6220_dwmmc_clk_type {
> >> + HI6220_DWMMC_CLK_BIU,
> >> + HI6220_DWMMC_CLK_CIU,
> >> + HI6220_DWMMC_CLK_CNT,
> >> +};
> >> +
> >> struct hi6220_dwmmc_plat {
> >>struct mmc_config cfg;
> >>struct mmc mmc;
> >> @@ -21,6 +30,8 @@ struct hi6220_dwmmc_plat {
> >>
> >> struct hi6220_dwmmc_priv_data {
> >>struct dwmci_host host;
> >> + struct clk *clks[HI6220_DWMMC_CLK_CNT];
> >> + struct reset_ctl_bulk rsts;
> >> };
> >>
> >> struct hisi_mmc_data {
> >> @@ -32,7 +43,29 @@ static int hi6220_dwmmc_of_to_plat(struct udevice *dev)
> >> {
> >>struct hi6220_dwmmc_priv_data *priv = dev_get_priv(dev);
> >>struct dwmci_host *host = &priv->host;
> >> + int ret;
> > If CONFIG_CLK and DM_RESET aren't enabled, this value is a dead code.
> > It also needs to initialize.
>
>
> I think a alternative solution is replacing the if stmt below with some
> `#ifdef`s just like some unittests code. So we can mask variable `ret'
> out if it's not used However, this seems not favored by checkpatch.pl.
It's not a critical thing. If possible to change more generic, I will change
them.
Thanks!
Best Regards,
Jaehoon Chung
>
>
> >
> >>
> >> + if (CONFIG_IS_ENABLED(CLK) && CONFIG_IS_ENABLED(DM_RESET)) {
> >> + priv->clks[HI6220_DWMMC_CLK_BIU] = devm_clk_get(dev, "biu");
> >> + if (IS_ERR(priv->clks[HI6220_DWMMC_CLK_BIU])) {
> >> + ret = PTR_ERR(priv->clks[HI6220_DWMMC_CLK_BIU]);
> >> + dev_err(dev, "Failed to get BIU clock(ret = %d).\n",
> >> ret);
> >> + return log_msg_ret("clk", ret);
> >> + }
> >> +
> >> + priv->clks[HI6220_DWMMC_CLK_CIU] = devm_clk_get(dev, "ciu");
> >> + if (IS_ERR(priv->clks[HI6220_DWMMC_CLK_CIU])) {
> >> + ret = PTR_ERR(priv->clks[HI6220_DWMMC_CLK_CIU]);
> >> + dev_err(dev, "Failed to get CIU clock(ret = %d).\n",
> >> ret);
> >> + return log_msg_ret("clk", ret);
> >> + }
> >> +
> >> + ret = reset_get_bulk(dev, &priv->rsts);
> >> + if (ret) {
> >> + dev_err(dev, "Failed to get resets(ret = %d)", ret);
> >> + return log_msg_ret("rst", ret);
> >> + }
> >> + }
> >>host->name = dev->name;
> >>host->ioaddr = dev_read_addr_ptr(dev);
> >>host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
> >> @@ -56,11 +89,37 @@ static int hi6220_dwmmc_probe(struct udevice *dev)
> >>struct hi6220_dwmmc_priv_data *priv = dev_get_priv(dev);
> >>struct dwmci_host *host = &priv->host;
> >>struct hisi_mmc_data *mmc_data;
> >> + int ret;
> > Ditto.
> >
> >
> > Best Regards,
> > Jaehoon Chung
> >
> >>
> >>mmc_data = (struct hisi_mmc_data *)dev_get_driver_data(dev);
> >>
> >> - /* Use default bus speed due to absence of clk driver */
> >>host->bus_hz = mmc_data->clock;
> >> + if (CONFIG_IS_ENABLED(CLK) && CONFIG_IS_ENABLED(DM_RESET)) {
> >> + ret = clk_prepare_enable(priv->clks[HI6220_DWMMC_CLK_BIU]);
> >> + if (ret) {
> >> + dev_err(dev, "Failed to enable biu clock(ret = %d).\n",
> >> ret);
> >> + return log_msg_ret("clk", ret);
> >> + }
> >> +
> >> + ret = clk_prepare_enable(priv->clks[HI6220_DWMMC_CLK_CIU]);
> >> + if (ret) {
> >> + dev_err(dev, "Failed to enable ciu clock(ret = %d).\n",
> >> ret);
> >> + return log_msg_ret("clk", ret);
> >> + }
> >> +
> >> + ret = reset_deassert_bulk(&priv->rsts);
> >> + if (ret) {
> >> + dev_err(dev, "Failed to deassert resets(ret = %d).\n",
> >> ret);
> >> +
RE: [PATCH v2 2/3] mmc: dw_mmc: Don't return error if data busy timeout
Hi,
> -Original Message-
> From: Yang Xiwen
> Sent: Wednesday, April 3, 2024 10:20 AM
> To: Jaehoon Chung ; Peng Fan
> Cc: u-boot@lists.denx.de
> Subject: Re: [PATCH v2 2/3] mmc: dw_mmc: Don't return error if data busy
> timeout
>
> On 4/3/2024 8:41 AM, Jaehoon Chung wrote:
> > Hi,
> >
> > On 2/1/24 23:05, Yang Xiwen via B4 Relay wrote:
> >> From: Yang Xiwen
> >>
> >> As described in [1], some poor hardware or cards would fail to release
> >> the bus and keep driving data lines low. Ignore it and send the next cmd
> >> directly seems okay for most cases.
> > This patch seems to be same with previous patch, right?
>
>
> From my observation, this patch does fix some weird problems and is
> mostly okay for other dwmmc users. I can't say it is very well tested
> because of I can't come up of other tests i can do except some `mmc
> read` and `mmc write`.
>
>
> >
> > Best Regards,
> > Jaehoon Chung
> >
> >> [1]:
> >> https://patchwork.kernel.org/project/linux-mmc/patch/1424458179-5456-1-git-send-email-
> diand...@chromium.org/
> >>
> >> Signed-off-by: Yang Xiwen
Tested-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> >> ---
> >> drivers/mmc/dw_mmc.c | 4 ++--
> >> 1 file changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
> >> index 400066fa99..e103664145 100644
> >> --- a/drivers/mmc/dw_mmc.c
> >> +++ b/drivers/mmc/dw_mmc.c
> >> @@ -262,8 +262,8 @@ static int dwmci_send_cmd(struct mmc *mmc, struct
> >> mmc_cmd *cmd,
> >>
> >>while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
> >>if (get_timer(start) > timeout) {
> >> - debug("%s: Timeout on data busy\n", __func__);
> >> - return -ETIMEDOUT;
> >> + debug("%s: Timeout on data busy, continue anyway\n",
> >> __func__);
> >> + break;
> >>}
> >>}
> >>
>
>
> --
> Regards,
> Yang Xiwen
