from:"Andy Yan"

[PATCH v3 2/2] board: rockchip: Add support for rk3588 based Cool Pi CM5 EVB

2024-02-17 Thread Andy Yan

Cool Pi CM5 EVB works as a mother board connect with CM5.

CM5 Specification:
- Rockchip RK3588
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet x 1 with PHY YT8531
- Gigabit ethernet x 1 drived by PCIE with YT6801S

CM5 EVB Specification:
- HDMI Type A out x 2
- HDMI Type D in x 1
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- PCIE M.2 E Key for Wireless connection
- PCIE M.2 M Key for NVME connection
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang 

[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/

---

Changes in v3:
- remove spl-boot-order as it is already in rk3588s-u-boot.dtsi
- Enable MMC_HS400 and MMC_HS400_ES as suggestted by Quentin

Changes in v2:
- sync dts from linux-rockchip which will be in linux-6.8 rc6[0]

 arch/arm/dts/Makefile |   1 +
 .../arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi |  29 +
 arch/arm/dts/rk3588-coolpi-cm5-evb.dts| 216 ++
 arch/arm/dts/rk3588-coolpi-cm5.dtsi   | 649 ++
 board/rockchip/evb_rk3588/MAINTAINERS |   8 +
 configs/coolpi-cm5-evb-rk3588_defconfig   | 113 +++
 6 files changed, 1016 insertions(+)
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb.dts
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5.dtsi
 create mode 100644 configs/coolpi-cm5-evb-rk3588_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ae7c088ceb..aafc41c466 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -191,6 +191,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
 
 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588s-coolpi-4b.dts \
+   rk3588-coolpi-cm5-evb.dts \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi 
b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
new file mode 100644
index 00..ed15b14ea0
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-u-boot.dtsi"
+
+_pins {
+   bootph-all;
+};
+
+ {
+   cap-mmc-highspeed;
+   mmc-hs200-1_8v;
+};
+
+ {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb.dts 
b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
new file mode 100644
index 00..a4946cdc3b
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include 
+#include "rk3588-coolpi-cm5.dtsi"
+
+/ {
+   model = "RK3588 CoolPi CM5 EVB";
+   compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588";
+
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   enable-gpios = < RK_PA3 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_en>;
+   power-supply = <_dcin>;
+   pwms = < 0 25000 0>;
+   };
+
+   leds: leds {
+   compatible = "gpio-leds";
+
+   green_led: led-0 {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = < RK_PB7 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+
+   vcc12v_dcin: vcc12v-dcin-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc12v_dcin";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;
+   };
+
+   vcc5v0_sys: vcc5v0-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   vin-supply = <_dcin>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys-regulator {
+   compatible = "regulator-fix

[PATCH v3 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B

2024-02-17 Thread Andy Yan

CoolPi 4B is a rk3588s based SBC.

Specification:
- Rockchip RK3588S
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet drived by PCIE with RTL8111HS
- HDMI Type D out
- Mini DP out
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- WIFI/BT module AIC8800
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang 
[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/

---

Changes in v3:
- remove spl-boot-order as it is already in rk3588s-u-boot.dtsi
- Enable MMC_HS400 and MMC_HS400_ES as suggestted by Quentin

Changes in v2:
- sync dts from linux-rockchip which will be in linux-6.8 rc6[0]

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi |  29 +
 arch/arm/dts/rk3588s-coolpi-4b.dts | 812 +
 board/rockchip/evb_rk3588/MAINTAINERS  |   7 +
 configs/coolpi-4b-rk3588s_defconfig| 113 +++
 5 files changed, 962 insertions(+)
 create mode 100644 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588s-coolpi-4b.dts
 create mode 100644 configs/coolpi-4b-rk3588s_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce10d3dbb0..ae7c088ceb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -190,6 +190,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-rock-3a.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
+   rk3588s-coolpi-4b.dts \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi 
b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
new file mode 100644
index 00..6e4b97028d
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+_pins {
+   bootph-all;
+};
+
+ {
+   cap-mmc-highspeed;
+   mmc-hs200-1_8v;
+};
+
+ {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts 
b/arch/arm/dts/rk3588s-coolpi-4b.dts
new file mode 100644
index 00..e037bf9db7
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b.dts
@@ -0,0 +1,812 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
+ *
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+#include 
+#include "rk3588s.dtsi"
+
+/ {
+   model = "RK3588S CoolPi 4 Model B";
+   compatible = "coolpi,pi-4b", "rockchip,rk3588s";
+
+   aliases {
+   mmc0 = 
+   mmc1 = 
+   mmc2 = 
+   };
+
+   analog-sound {
+   compatible = "audio-graph-card";
+   dais = <_8ch_p0>;
+   label = "rk3588-es8316";
+   routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+   widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+   };
+
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   leds: leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <_leds>;
+
+   led0: led-green {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = < RK_PD0 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+
+   led1: led-red {
+   color = ;
+   default-state = "off";
+   function = LED_FUNCTION_WLAN;
+   gpios = < RK_PC4 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "phy0tx";
+   };
+   };
+
+   sdio_pwrseq: sdio-pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   clocks = <>;
+   clock-names = "ext_clock";
+   pinctrl-names = "default";
+   pinctrl-0 = <_enable_h>;
+   /*
+* On the m

Re:Re: [PATCH v2 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B

2024-02-16 Thread Andy Yan


Hi Quentin：


在 2024-02-15 20:42:56，"Quentin Schulz"  
写道：
>Hi Andy,
>
>On 2/15/24 12:55, Andy Yan wrote:
>> [You don't often get email from andys...@163.com. Learn why this is 
>> important at https://aka.ms/LearnAboutSenderIdentification ]
>> 
>> Hi Quentin：
>> At 2024-02-15 18:40:25, "Quentin Schulz" 
>>  wrote:
>>> Hi Andy,
>>>
>>> On 2/15/24 11:35, Andy Yan wrote:
>>> [...]
>>>>>> diff --git a/configs/coolpi-4b-rk3588s_defconfig 
>>>>>> b/configs/coolpi-4b-rk3588s_defconfig
>>>>>> new file mode 100644
>>>>>> index 00..3e3e5abc86
>>>>>> --- /dev/null
>>>>>> +++ b/configs/coolpi-4b-rk3588s_defconfig
>>>>>> @@ -0,0 +1,105 @@
>>>>>> +CONFIG_ARM=y
>>>>>> +CONFIG_SKIP_LOWLEVEL_INIT=y
>>>>>> +CONFIG_COUNTER_FREQUENCY=2400
>>>>>> +CONFIG_ARCH_ROCKCHIP=y
>>>>>> +CONFIG_TEXT_BASE=0x00a0
>>>>>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>>>>>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>>>>>> +CONFIG_NR_DRAM_BANKS=2
>>>>>> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>>>>>> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
>>>>>> +CONFIG_SF_DEFAULT_SPEED=2400
>>>>>> +CONFIG_SF_DEFAULT_MODE=0x2000
>>>>>> +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b"
>>>>>> +CONFIG_ROCKCHIP_RK3588=y
>>>>>> +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
>>>>>> +CONFIG_ROCKCHIP_SPI_IMAGE=y
>>>>>> +CONFIG_SPL_SERIAL=y
>>>>>> +CONFIG_SPL_STACK_R_ADDR=0x60
>>>>>> +CONFIG_TARGET_EVB_RK3588=y
>>>>>> +CONFIG_SPL_STACK=0x40
>>>>>> +CONFIG_DEBUG_UART_BASE=0xFEB5
>>>>>> +CONFIG_DEBUG_UART_CLOCK=2400
>>>>>> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
>>>>>> +CONFIG_SPL_SPI=y
>>>>>> +CONFIG_SYS_LOAD_ADDR=0xc00800
>>>>>> +CONFIG_PCI=y
>>>>>> +CONFIG_DEBUG_UART=y
>>>>>> +CONFIG_AHCI=y
>>>>>> +CONFIG_FIT=y
>>>>>> +CONFIG_FIT_VERBOSE=y
>>>>>> +CONFIG_SPL_FIT_SIGNATURE=y
>>>>>> +CONFIG_SPL_LOAD_FIT=y
>>>>>> +CONFIG_LEGACY_IMAGE_FORMAT=y
>>>>>> +CONFIG_OF_BOARD_SETUP=y
>>>>>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
>>>>>> +# CONFIG_DISPLAY_CPUINFO is not set
>>>>>> +CONFIG_DISPLAY_BOARDINFO_LATE=y
>>>>>> +CONFIG_SPL_MAX_SIZE=0x4
>>>>>> +CONFIG_SPL_PAD_TO=0x7f8000
>>>>>> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
>>>>>> +CONFIG_SPL_BSS_START_ADDR=0x400
>>>>>> +CONFIG_SPL_BSS_MAX_SIZE=0x4000
>>>>>> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>>>>>> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
>>>>>> +CONFIG_SPL_STACK_R=y
>>>>>> +CONFIG_SPL_SPI_LOAD=y
>>>>>> +CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
>>>>>> +CONFIG_SPL_ATF=y
>>>>>> +CONFIG_CMD_GPIO=y
>>>>>> +CONFIG_CMD_GPT=y
>>>>>> +CONFIG_CMD_I2C=y
>>>>>> +CONFIG_CMD_MMC=y
>>>>>> +CONFIG_CMD_PCI=y
>>>>>> +CONFIG_CMD_USB=y
>>>>>> +# CONFIG_CMD_SETEXPR is not set
>>>>>> +CONFIG_CMD_REGULATOR=y
>>>>>> +# CONFIG_SPL_DOS_PARTITION is not set
>>>>>> +CONFIG_SPL_OF_CONTROL=y
>>>>>> +CONFIG_OF_LIVE=y
>>>>>> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent 
>>>>>> assigned-clocks assigned-clock-rates assigned-clock-parents"
>>>>>> +CONFIG_SPL_DM_SEQ_ALIAS=y
>>>>>> +CONFIG_SPL_REGMAP=y
>>>>>> +CONFIG_SPL_SYSCON=y
>>>>>> +CONFIG_AHCI_PCI=y
>>>>>> +CONFIG_DWC_AHCI=y
>>>>>> +CONFIG_SPL_CLK=y
>>>>>> +CONFIG_ROCKCHIP_GPIO=y
>>>>>> +CONFIG_SYS_I2C_ROCKCHIP=y
>>>>>> +CONFIG_MISC=y
>>>>>> +CONFIG_SUPPORT_EMMC_RPMB=y
>>>>>> +CONFIG_MMC_DW=y
>>>>>> +CONFIG_MMC_DW_ROCKCHIP=y
>>>>>> +CONFIG_MMC_SDHCI=y
>>>>>> +CONFIG_MMC_SDHCI_SDMA=y
>>>>>> +CONFIG_MMC_SDHCI_ROCKCHIP=y
>>>>>> +CONFIG_SF_DEFAULT_BUS=5
&g

Re:Re: [PATCH v2 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B

2024-02-15 Thread Andy Yan



Hi Quentin：
At 2024-02-15 18:40:25, "Quentin Schulz"  
wrote:
>Hi Andy,
>
>On 2/15/24 11:35, Andy Yan wrote:
>[...]
>>>> diff --git a/configs/coolpi-4b-rk3588s_defconfig 
>>>> b/configs/coolpi-4b-rk3588s_defconfig
>>>> new file mode 100644
>>>> index 00..3e3e5abc86
>>>> --- /dev/null
>>>> +++ b/configs/coolpi-4b-rk3588s_defconfig
>>>> @@ -0,0 +1,105 @@
>>>> +CONFIG_ARM=y
>>>> +CONFIG_SKIP_LOWLEVEL_INIT=y
>>>> +CONFIG_COUNTER_FREQUENCY=2400
>>>> +CONFIG_ARCH_ROCKCHIP=y
>>>> +CONFIG_TEXT_BASE=0x00a0
>>>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>>>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>>>> +CONFIG_NR_DRAM_BANKS=2
>>>> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>>>> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
>>>> +CONFIG_SF_DEFAULT_SPEED=2400
>>>> +CONFIG_SF_DEFAULT_MODE=0x2000
>>>> +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b"
>>>> +CONFIG_ROCKCHIP_RK3588=y
>>>> +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
>>>> +CONFIG_ROCKCHIP_SPI_IMAGE=y
>>>> +CONFIG_SPL_SERIAL=y
>>>> +CONFIG_SPL_STACK_R_ADDR=0x60
>>>> +CONFIG_TARGET_EVB_RK3588=y
>>>> +CONFIG_SPL_STACK=0x40
>>>> +CONFIG_DEBUG_UART_BASE=0xFEB5
>>>> +CONFIG_DEBUG_UART_CLOCK=2400
>>>> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
>>>> +CONFIG_SPL_SPI=y
>>>> +CONFIG_SYS_LOAD_ADDR=0xc00800
>>>> +CONFIG_PCI=y
>>>> +CONFIG_DEBUG_UART=y
>>>> +CONFIG_AHCI=y
>>>> +CONFIG_FIT=y
>>>> +CONFIG_FIT_VERBOSE=y
>>>> +CONFIG_SPL_FIT_SIGNATURE=y
>>>> +CONFIG_SPL_LOAD_FIT=y
>>>> +CONFIG_LEGACY_IMAGE_FORMAT=y
>>>> +CONFIG_OF_BOARD_SETUP=y
>>>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
>>>> +# CONFIG_DISPLAY_CPUINFO is not set
>>>> +CONFIG_DISPLAY_BOARDINFO_LATE=y
>>>> +CONFIG_SPL_MAX_SIZE=0x4
>>>> +CONFIG_SPL_PAD_TO=0x7f8000
>>>> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
>>>> +CONFIG_SPL_BSS_START_ADDR=0x400
>>>> +CONFIG_SPL_BSS_MAX_SIZE=0x4000
>>>> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>>>> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
>>>> +CONFIG_SPL_STACK_R=y
>>>> +CONFIG_SPL_SPI_LOAD=y
>>>> +CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
>>>> +CONFIG_SPL_ATF=y
>>>> +CONFIG_CMD_GPIO=y
>>>> +CONFIG_CMD_GPT=y
>>>> +CONFIG_CMD_I2C=y
>>>> +CONFIG_CMD_MMC=y
>>>> +CONFIG_CMD_PCI=y
>>>> +CONFIG_CMD_USB=y
>>>> +# CONFIG_CMD_SETEXPR is not set
>>>> +CONFIG_CMD_REGULATOR=y
>>>> +# CONFIG_SPL_DOS_PARTITION is not set
>>>> +CONFIG_SPL_OF_CONTROL=y
>>>> +CONFIG_OF_LIVE=y
>>>> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
>>>> assigned-clock-rates assigned-clock-parents"
>>>> +CONFIG_SPL_DM_SEQ_ALIAS=y
>>>> +CONFIG_SPL_REGMAP=y
>>>> +CONFIG_SPL_SYSCON=y
>>>> +CONFIG_AHCI_PCI=y
>>>> +CONFIG_DWC_AHCI=y
>>>> +CONFIG_SPL_CLK=y
>>>> +CONFIG_ROCKCHIP_GPIO=y
>>>> +CONFIG_SYS_I2C_ROCKCHIP=y
>>>> +CONFIG_MISC=y
>>>> +CONFIG_SUPPORT_EMMC_RPMB=y
>>>> +CONFIG_MMC_DW=y
>>>> +CONFIG_MMC_DW_ROCKCHIP=y
>>>> +CONFIG_MMC_SDHCI=y
>>>> +CONFIG_MMC_SDHCI_SDMA=y
>>>> +CONFIG_MMC_SDHCI_ROCKCHIP=y
>>>> +CONFIG_SF_DEFAULT_BUS=5
>>>> +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
>>>> +CONFIG_SPI_FLASH_XMC=y
>>>> +CONFIG_SPI_FLASH_XTX=y
>>>> +CONFIG_PHY_MOTORCOMM=y
>>>> +CONFIG_DWC_ETH_QOS=y
>>>> +CONFIG_DWC_ETH_QOS_ROCKCHIP=y
>>>> +CONFIG_NVME_PCI=y
>>>> +CONFIG_PCIE_DW_ROCKCHIP=y
>>>> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
>>>> +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
>>>> +CONFIG_PHY_ROCKCHIP_USBDP=y
>>>> +CONFIG_SPL_PINCTRL=y
>>>> +CONFIG_PWM_ROCKCHIP=y
>>>> +CONFIG_SPL_RAM=y
>>>> +CONFIG_SCSI=y
>>>> +CONFIG_BAUDRATE=150
>>>> +CONFIG_DEBUG_UART_SHIFT=2
>>>> +CONFIG_SYS_NS16550_MEM32=y
>>>> +CONFIG_ROCKCHIP_SFC=y
>>>> +CONFIG_SYSRESET=y
>>>> +CONFIG_USB=y
>>>> +CONFIG_USB_XHCI_HCD=y
>>>> +CONFIG_USB_EHCI_HCD=y
>>>> +CONFIG_USB_EHCI_GENERIC=y
>>>> +CONFIG_USB_OHCI_HCD=y
>>>> +CONFIG_USB_OHCI_GENERIC=y
>>>> +CONFIG_USB_DWC3=y
>>>> +CONFIG_USB_DWC3_GENERIC=y
>>>> +CONFIG_ERRNO_STR=y
>>>
>>> Is there any reason for NOT enabling MMC_HS400_ES?
>> 
>> No, I just follow the config of other rk3588/s based boards.
>
>Fortunately enough, a patch was recently merged to have at least HS200 
>on RK3588, which is the first mode that actually works, anything below 
>that is broken right now.
>
>> It seems that there are no rk3588/s based boards enable MMC_HS400_ES in the 
>> current u-boot mainline ?
>> 
>
>Jaguar is hopefully coming soon-ish, maybe not in this release but the 
>next one (patches are sent already), and we make us of it in U-Boot 
>proper and the SPL. Up to you, can always be enabled later on.

With a quick search， I fond jonas'S patch for enabling HS200 has been merged, 
but
your patch will bring HS400_ES, does that mean all the rk3588/s based boars 
will switch to
HS400 ES if they support it?

Thanks.
>
>FWIW, both comments on this patch also apply to the second patch in this 
>series :)
>
>Cheers,
>Quentin

Re:Re: [PATCH v2 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B

2024-02-15 Thread Andy Yan



At 2024-02-14 22:13:08, "Quentin Schulz"  
wrote:
>Hi Andy,
>
>On 2/14/24 10:31, Andy Yan wrote:
>> [You don't often get email from andys...@163.com. Learn why this is 
>> important at https://aka.ms/LearnAboutSenderIdentification ]
>> 
>> CoolPi 4B is a rk3588s based SBC.
>> 
>> Specification:
>> - Rockchip RK3588S
>> - LPDDR4 2/4/8/16 GB
>> - TF scard slot
>> - eMMC 8/32/64/128 GB module
>> - SPI Nor 8MB
>> - Gigabit ethernet drived by PCIE with RTL8111HS
>> - HDMI Type D out
>> - Mini DP out
>> - USB 2.0 Host x 2
>> - USB 3.0 OTG x 1
>> - USB 3.0 Host x 1
>> - WIFI/BT module AIC8800
>> - 40 pin header
>> 
>> The dts is from linux-6.8 rc1.
>> 
>> Signed-off-by: Andy Yan 
>> Reviewed-by: Kever Yang 
>> 
>> ---
>> 
>> Changes in v2:
>> - sync dts from linux-rockchip which will be in linux-6.8 rc6[0]
>> 
>> [0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/
>>   arch/arm/dts/Makefile  |   1 +
>>   arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi |  30 +
>>   arch/arm/dts/rk3588s-coolpi-4b.dts | 812 +
>>   board/rockchip/evb_rk3588/MAINTAINERS  |   7 +
>>   configs/coolpi-4b-rk3588s_defconfig| 105 +++
>>   5 files changed, 955 insertions(+)
>>   create mode 100644 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
>>   create mode 100644 arch/arm/dts/rk3588s-coolpi-4b.dts
>>   create mode 100644 configs/coolpi-4b-rk3588s_defconfig
>> 
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index ce10d3dbb0..ae7c088ceb 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -190,6 +190,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
>>  rk3568-rock-3a.dtb
>> 
>>   dtb-$(CONFIG_ROCKCHIP_RK3588) += \
>> +   rk3588s-coolpi-4b.dts \
>>  rk3588-edgeble-neu6a-io.dtb \
>>  rk3588-edgeble-neu6b-io.dtb \
>>  rk3588-evb1-v10.dtb \
>> diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi 
>> b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
>> new file mode 100644
>> index 00..6b69ff424f
>> --- /dev/null
>> +++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
>> @@ -0,0 +1,30 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +
>> +#include "rk3588s-u-boot.dtsi"
>> +
>> +/ {
>> +   chosen {
>> +   u-boot,spl-boot-order = "same-as-spl", , 
>> +   };
>
>This is already in rk3588s-u-boot.dtsi

Okay, will be dropped in the next version. Thanks for catching that.

>
>> +};
>> +
>> +_pins {
>> +   bootph-all;
>> +};
>> +
>> + {
>> +   bootph-pre-ram;
>> +   u-boot,spl-sfc-no-dma;
>> +   pinctrl-names = "default";
>> +   pinctrl-0 = <_pins>;
>> +   status = "okay";
>> +
>> +   flash@0 {
>> +   bootph-pre-ram;
>> +   compatible = "jedec,spi-nor";
>> +   reg = <0>;
>> +   spi-max-frequency = <2400>;
>> +   spi-rx-bus-width = <4>;
>> +   spi-tx-bus-width = <1>;
>> +   };
>> +};
>> diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts 
>> b/arch/arm/dts/rk3588s-coolpi-4b.dts
>> new file mode 100644
>> index 00..e037bf9db7
>> --- /dev/null
>> +++ b/arch/arm/dts/rk3588s-coolpi-4b.dts
>> @@ -0,0 +1,812 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
>> + *
>> + * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
>> + *
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include "rk3588s.dtsi"
>> +
>> +/ {
>> +   model = "RK3588S CoolPi 4 Model B";
>> +   compatible = "coolpi,pi-4b", "rockchip,rk3588s";
>> +
>> +   aliases {
>> +   mmc0 = 
>> +   mmc1 = 
>> +   mmc2 = 
>> +   };
>> +
>> +   analog-sound {
>> +   compatible = "audio-graph-card";
>> +   dais = <_8ch_p0>;
>> +   label = "rk3588-es8316";
>> +   routing = "MIC2", "Mic Jack",
>> + "Headphones&quo

[PATCH v2 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B

2024-02-14 Thread Andy Yan

CoolPi 4B is a rk3588s based SBC.

Specification:
- Rockchip RK3588S
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet drived by PCIE with RTL8111HS
- HDMI Type D out
- Mini DP out
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- WIFI/BT module AIC8800
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang 

---

Changes in v2:
- sync dts from linux-rockchip which will be in linux-6.8 rc6[0]

[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi |  30 +
 arch/arm/dts/rk3588s-coolpi-4b.dts | 812 +
 board/rockchip/evb_rk3588/MAINTAINERS  |   7 +
 configs/coolpi-4b-rk3588s_defconfig| 105 +++
 5 files changed, 955 insertions(+)
 create mode 100644 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588s-coolpi-4b.dts
 create mode 100644 configs/coolpi-4b-rk3588s_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce10d3dbb0..ae7c088ceb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -190,6 +190,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-rock-3a.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
+   rk3588s-coolpi-4b.dts \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi 
b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
new file mode 100644
index 00..6b69ff424f
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", , 
+   };
+};
+
+_pins {
+   bootph-all;
+};
+
+ {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts 
b/arch/arm/dts/rk3588s-coolpi-4b.dts
new file mode 100644
index 00..e037bf9db7
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b.dts
@@ -0,0 +1,812 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
+ *
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+#include 
+#include "rk3588s.dtsi"
+
+/ {
+   model = "RK3588S CoolPi 4 Model B";
+   compatible = "coolpi,pi-4b", "rockchip,rk3588s";
+
+   aliases {
+   mmc0 = 
+   mmc1 = 
+   mmc2 = 
+   };
+
+   analog-sound {
+   compatible = "audio-graph-card";
+   dais = <_8ch_p0>;
+   label = "rk3588-es8316";
+   routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+   widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+   };
+
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   leds: leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <_leds>;
+
+   led0: led-green {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = < RK_PD0 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+
+   led1: led-red {
+   color = ;
+   default-state = "off";
+   function = LED_FUNCTION_WLAN;
+   gpios = < RK_PC4 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "phy0tx";
+   };
+   };
+
+   sdio_pwrseq: sdio-pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   clocks = <>;
+   clock-names = "ext_clock";
+   pinctrl-names = "default";
+   pinctrl-0 = <_enable_h>;
+   /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+

[PATCH v2 2/2] board: rockchip: Add support for rk3588 based Cool Pi CM5 EVB

2024-02-14 Thread Andy Yan

Cool Pi CM5 EVB works as a mother board connect with CM5.

CM5 Specification:
- Rockchip RK3588
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet x 1 with PHY YT8531
- Gigabit ethernet x 1 drived by PCIE with YT6801S

CM5 EVB Specification:
- HDMI Type A out x 2
- HDMI Type D in x 1
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- PCIE M.2 E Key for Wireless connection
- PCIE M.2 M Key for NVME connection
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang 


---

Changes in v2:
- sync dts from linux-rockchip which will be in linux-6.8 rc6[0]

[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/

 .../arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi |  30 +
 arch/arm/dts/rk3588-coolpi-cm5-evb.dts| 216 ++
 arch/arm/dts/rk3588-coolpi-cm5.dtsi   | 649 ++
 board/rockchip/evb_rk3588/MAINTAINERS |   8 +
 configs/coolpi-cm5-evb-rk3588_defconfig   | 105 +++
 5 files changed, 1008 insertions(+)
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb.dts
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5.dtsi
 create mode 100644 configs/coolpi-cm5-evb-rk3588_defconfig

diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi 
b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
new file mode 100644
index 00..6b69ff424f
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", , 
+   };
+};
+
+_pins {
+   bootph-all;
+};
+
+ {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb.dts 
b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
new file mode 100644
index 00..a4946cdc3b
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include 
+#include "rk3588-coolpi-cm5.dtsi"
+
+/ {
+   model = "RK3588 CoolPi CM5 EVB";
+   compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588";
+
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   enable-gpios = < RK_PA3 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_en>;
+   power-supply = <_dcin>;
+   pwms = < 0 25000 0>;
+   };
+
+   leds: leds {
+   compatible = "gpio-leds";
+
+   green_led: led-0 {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = < RK_PB7 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+
+   vcc12v_dcin: vcc12v-dcin-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc12v_dcin";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;
+   };
+
+   vcc5v0_sys: vcc5v0-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   vin-supply = <_dcin>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   vin-supply = <_dcin>;
+   };
+
+   vcc3v3_lcd: vcc3v3-lcd-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_lcd";
+   enable-active-high;
+   gpio = < RK_PC4 GPIO_ACTIVE_HI

[PATCH] rockchip: rk3588-evb: Enable USB support

2024-02-03 Thread Andy Yan

From: Andy Yan 

Enable USB releated config to support
boot from usb.

Signed-off-by: Andy Yan 
---
 configs/evb-rk3588_defconfig | 12 
 1 file changed, 12 insertions(+)

diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index 0b7b4f2f627..8a6aa91cb29 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -40,6 +40,7 @@ CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
@@ -61,6 +62,9 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_PHY_REALTEK=y
 CONFIG_DWC_ETH_QOS=y
 CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
@@ -68,4 +72,12 @@ CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_ERRNO_STR=y
-- 
2.34.1

[PATCH 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B

2024-01-20 Thread Andy Yan

CoolPi 4B is a rk3588s based SBC.

Specification:
- Rockchip RK3588S
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet drived by PCIE with RTL8111HS
- HDMI Type D out
- Mini DP out
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- WIFI/BT module AIC8800
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan 
---

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi |  30 +
 arch/arm/dts/rk3588s-coolpi-4b.dts | 813 +
 board/rockchip/evb_rk3588/MAINTAINERS  |   7 +
 configs/coolpi-4b-rk3588s_defconfig| 105 +++
 5 files changed, 956 insertions(+)
 create mode 100644 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588s-coolpi-4b.dts
 create mode 100644 configs/coolpi-4b-rk3588s_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b5c588c3363..a3d0cad3471 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -189,6 +189,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-rock-3a.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
+   rk3588s-coolpi-4b.dts \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi 
b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
new file mode 100644
index 000..6b69ff424fa
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", , 
+   };
+};
+
+_pins {
+   bootph-all;
+};
+
+ {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts 
b/arch/arm/dts/rk3588s-coolpi-4b.dts
new file mode 100644
index 000..a15c8e8fa6d
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b.dts
@@ -0,0 +1,813 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
+ *
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+#include 
+#include "rk3588s.dtsi"
+
+/ {
+   model = "RK3588S CoolPi 4 Model B";
+   compatible = "coolpi,pi-4b", "rockchip,rk3588s";
+
+   aliases {
+   mmc0 = 
+   mmc1 = 
+   mmc2 = 
+   serial2 = 
+   };
+
+   analog-sound {
+   compatible = "audio-graph-card";
+   dais = <_8ch_p0>;
+   label = "rk3588-es8316";
+   routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+   widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+   };
+
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   leds: leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <_leds>;
+
+   led0: led-green {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = < RK_PD0 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+
+   led1: led-red {
+   color = ;
+   default-state = "off";
+   function = LED_FUNCTION_WLAN;
+   gpios = < RK_PC4 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "phy0tx";
+   };
+   };
+
+   sdio_pwrseq: sdio-pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   clocks = <>;
+   clock-names = "ext_clock";
+   pinctrl-names = "default";
+   pinctrl-0 = <_enable_h>;
+   /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+* - SDIO_RESET_L_WL_REG_ON
+* - PDN (power down when low)
+*/
+   post-power-on-delay-ms = <200

[PATCH 2/2] board: rockchip: Add support for rk3588 based Cool Pi CM5 EVB

2024-01-20 Thread Andy Yan

Cool Pi CM5 EVB works as a mother board connect with CM5.

CM5 Specification:
- Rockchip RK3588
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet x 1 with PHY YT8531
- Gigabit ethernet x 1 drived by PCIE with YT6801S

CM5 EVB Specification:
- HDMI Type A out x 2
- HDMI Type D in x 1
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- PCIE M.2 E Key for Wireless connection
- PCIE M.2 M Key for NVME connection
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan 
---

 .../arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi |  30 +
 arch/arm/dts/rk3588-coolpi-cm5-evb.dts| 214 ++
 arch/arm/dts/rk3588-coolpi-cm5.dtsi   | 650 ++
 board/rockchip/evb_rk3588/MAINTAINERS |   8 +
 configs/coolpi-cm5-evb-rk3588_defconfig   | 105 +++
 5 files changed, 1007 insertions(+)
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb.dts
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5.dtsi
 create mode 100644 configs/coolpi-cm5-evb-rk3588_defconfig

diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi 
b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
new file mode 100644
index 000..6b69ff424fa
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", , 
+   };
+};
+
+_pins {
+   bootph-all;
+};
+
+ {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb.dts 
b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
new file mode 100644
index 000..d4c70835e0f
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include 
+#include "rk3588-coolpi-cm5.dtsi"
+
+/ {
+   model = "RK3588 CoolPi CM5 EVB";
+   compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588";
+
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   enable-gpios = < RK_PA3 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_en>;
+   power-supply = <_dcin>;
+   pwms = < 0 25000 0>;
+   };
+
+   leds: leds {
+   compatible = "gpio-leds";
+
+   green_led: led-0 {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = < RK_PB7 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+
+   vcc12v_dcin: vcc12v-dcin-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc12v_dcin";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;
+   };
+
+   vcc5v0_sys: vcc5v0-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   vin-supply = <_dcin>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   vin-supply = <_dcin>;
+   };
+
+   vcc3v3_lcd: vcc3v3-lcd-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_lcd";
+   enable-active-high;
+   gpio = < RK_PC4 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_en>;
+   vin-supply = <_sys>;
+   };
+
+   vcc5v0_usb30_host: vcc5v0-usb30-ho

Re:Re: [PATCH v2 13/17] video: rockchip: Add rk3328 vop support

2023-12-19 Thread Andy Yan



Hi Jaqan，
在 2023-12-19 15:42:26，"Jagan Teki"  写道：
>Hi Andy,
>
>On Tue, Dec 19, 2023 at 6:50 AM Andy Yan  wrote:
>>
>>
>> Hi Jaqan：
>>
>> At 2023-12-19 03:11:10, "Jagan Teki"  wrote:
>> >From: Jagan Teki 
>> >
>> >Add support for Rockchip RK3328 VOP.
>> >
>> >Require VOP cleanup before handoff to Linux by writing reset values to
>> >WIN registers. Without this Linux VOP trigger page fault as below
>> >[0.752016] Loading compiled-in X.509 certificates
>> >[0.787796] inno_hdmi_phy_rk3328_clk_recalc_rate: parent 2400
>> >[0.788391] inno-hdmi-phy ff43.phy: 
>> >inno_hdmi_phy_rk3328_clk_recalc_rate rate 14850 vco 14850
>> >[0.798353] rockchip-drm display-subsystem: bound ff37.vop (ops 
>> >vop_component_ops)
>> >[0.799403] dwhdmi-rockchip ff3c.hdmi: supply avdd-0v9 not found, 
>> >using dummy regulator
>> >[0.800288] rk_iommu ff373f00.iommu: Enable stall request timed out, 
>> >status: 0x4b
>> >[0.801131] dwhdmi-rockchip ff3c.hdmi: supply avdd-1v8 not found, 
>> >using dummy regulator
>> >[0.802056] rk_iommu ff373f00.iommu: Disable paging request timed out, 
>> >status: 0x4b
>> >[0.803233] dwhdmi-rockchip ff3c.hdmi: Detected HDMI TX controller 
>> >v2.11a with HDCP (inno_dw_hdmi_phy2)
>> >[0.805355] dwhdmi-rockchip ff3c.hdmi: registered DesignWare HDMI 
>> >I2C bus driver
>> >[0.808769] rockchip-drm display-subsystem: bound ff3c.hdmi (ops 
>> >dw_hdmi_rockchip_ops)
>> >[0.810869] [drm] Initialized rockchip 1.0.0 20140818 for 
>> >display-subsystem on minor 0
>> >
>> >Signed-off-by: Jagan Teki 
>> >---
>> >Changes for v2:
>> >- Add VOP cleanup
>> >- Update commit
>> >
>> > drivers/video/rockchip/Makefile |  1 +
>> > drivers/video/rockchip/rk3328_vop.c | 83 +
>> > 2 files changed, 84 insertions(+)
>> > create mode 100644 drivers/video/rockchip/rk3328_vop.c
>> >
>> >diff --git a/drivers/video/rockchip/Makefile 
>> >b/drivers/video/rockchip/Makefile
>> >index 4991303c73..f55beceebf 100644
>> >--- a/drivers/video/rockchip/Makefile
>> >+++ b/drivers/video/rockchip/Makefile
>> >@@ -6,6 +6,7 @@
>> > ifdef CONFIG_VIDEO_ROCKCHIP
>> > obj-y += rk_vop.o
>> > obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o
>> >+obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o
>> > obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o
>> > obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
>> > obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
>> >diff --git a/drivers/video/rockchip/rk3328_vop.c 
>> >b/drivers/video/rockchip/rk3328_vop.c
>> >new file mode 100644
>> >index 00..a4da3a91e8
>> >--- /dev/null
>> >+++ b/drivers/video/rockchip/rk3328_vop.c
>> >@@ -0,0 +1,83 @@
>> >+// SPDX-License-Identifier: GPL-2.0+
>> >+/*
>> >+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
>> >+ */
>> >+
>> >+#include 
>> >+#include 
>> >+#include 
>> >+#include "rk_vop.h"
>> >+
>> >+DECLARE_GLOBAL_DATA_PTR;
>> >+
>> >+static void rk3328_set_pin_polarity(struct udevice *dev,
>> >+  enum vop_modes mode, u32 polarity)
>> >+{
>> >+  struct rk_vop_priv *priv = dev_get_priv(dev);
>> >+  struct rk3288_vop *regs = priv->regs;
>> >+
>> >+  switch (mode) {
>> >+  case VOP_MODE_HDMI:
>> >+  clrsetbits_le32(>dsp_ctrl1,
>> >+  M_RK3399_DSP_HDMI_POL,
>> >+  V_RK3399_DSP_HDMI_POL(polarity));
>> >+  break;
>> >+  default:
>> >+  debug("%s: unsupported output mode %x\n", __func__, mode);
>> >+  }
>> >+}
>> >+
>> >+static int rk3328_vop_probe(struct udevice *dev)
>> >+{
>> >+  /* Before relocation we don't need to do anything */
>> >+  if (!(gd->flags & GD_FLG_RELOC))
>> >+  return 0;
>> >+
>> >+  return rk_vop_probe(dev);
>> >+}
>> >+
>> >+static int rk3328_vop_remove(struct udevice *dev)
>> >+{
>> >+  struct rk_vop_priv *priv = dev_get_priv(dev);
>> >+  struct rk3288_vop *regs =

Re:[PATCH v2 13/17] video: rockchip: Add rk3328 vop support

2023-12-18 Thread Andy Yan


Hi Jaqan：

At 2023-12-19 03:11:10, "Jagan Teki"  wrote:
>From: Jagan Teki 
>
>Add support for Rockchip RK3328 VOP.
>
>Require VOP cleanup before handoff to Linux by writing reset values to
>WIN registers. Without this Linux VOP trigger page fault as below
>[0.752016] Loading compiled-in X.509 certificates
>[0.787796] inno_hdmi_phy_rk3328_clk_recalc_rate: parent 2400
>[0.788391] inno-hdmi-phy ff43.phy: 
>inno_hdmi_phy_rk3328_clk_recalc_rate rate 14850 vco 14850
>[0.798353] rockchip-drm display-subsystem: bound ff37.vop (ops 
>vop_component_ops)
>[0.799403] dwhdmi-rockchip ff3c.hdmi: supply avdd-0v9 not found, using 
>dummy regulator
>[0.800288] rk_iommu ff373f00.iommu: Enable stall request timed out, 
>status: 0x4b
>[0.801131] dwhdmi-rockchip ff3c.hdmi: supply avdd-1v8 not found, using 
>dummy regulator
>[0.802056] rk_iommu ff373f00.iommu: Disable paging request timed out, 
>status: 0x4b
>[0.803233] dwhdmi-rockchip ff3c.hdmi: Detected HDMI TX controller 
>v2.11a with HDCP (inno_dw_hdmi_phy2)
>[0.805355] dwhdmi-rockchip ff3c.hdmi: registered DesignWare HDMI I2C 
>bus driver
>[0.808769] rockchip-drm display-subsystem: bound ff3c.hdmi (ops 
>dw_hdmi_rockchip_ops)
>[0.810869] [drm] Initialized rockchip 1.0.0 20140818 for display-subsystem 
>on minor 0
>
>Signed-off-by: Jagan Teki 
>---
>Changes for v2:
>- Add VOP cleanup
>- Update commit
>
> drivers/video/rockchip/Makefile |  1 +
> drivers/video/rockchip/rk3328_vop.c | 83 +
> 2 files changed, 84 insertions(+)
> create mode 100644 drivers/video/rockchip/rk3328_vop.c
>
>diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
>index 4991303c73..f55beceebf 100644
>--- a/drivers/video/rockchip/Makefile
>+++ b/drivers/video/rockchip/Makefile
>@@ -6,6 +6,7 @@
> ifdef CONFIG_VIDEO_ROCKCHIP
> obj-y += rk_vop.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o
>+obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o
> obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
> obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
>diff --git a/drivers/video/rockchip/rk3328_vop.c 
>b/drivers/video/rockchip/rk3328_vop.c
>new file mode 100644
>index 00..a4da3a91e8
>--- /dev/null
>+++ b/drivers/video/rockchip/rk3328_vop.c
>@@ -0,0 +1,83 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
>+ */
>+
>+#include 
>+#include 
>+#include 
>+#include "rk_vop.h"
>+
>+DECLARE_GLOBAL_DATA_PTR;
>+
>+static void rk3328_set_pin_polarity(struct udevice *dev,
>+  enum vop_modes mode, u32 polarity)
>+{
>+  struct rk_vop_priv *priv = dev_get_priv(dev);
>+  struct rk3288_vop *regs = priv->regs;
>+
>+  switch (mode) {
>+  case VOP_MODE_HDMI:
>+  clrsetbits_le32(>dsp_ctrl1,
>+  M_RK3399_DSP_HDMI_POL,
>+  V_RK3399_DSP_HDMI_POL(polarity));
>+  break;
>+  default:
>+  debug("%s: unsupported output mode %x\n", __func__, mode);
>+  }
>+}
>+
>+static int rk3328_vop_probe(struct udevice *dev)
>+{
>+  /* Before relocation we don't need to do anything */
>+  if (!(gd->flags & GD_FLG_RELOC))
>+  return 0;
>+
>+  return rk_vop_probe(dev);
>+}
>+
>+static int rk3328_vop_remove(struct udevice *dev)
>+{
>+  struct rk_vop_priv *priv = dev_get_priv(dev);
>+  struct rk3288_vop *regs = priv->regs;
>+  struct rk3288_vop *win_regs = priv->regs + priv->win_offset;
>+
>+  /* write reset values */
>+  writel(0xef013f, _regs->win0_act_info);
>+  writel(0xef013f, _regs->win0_dsp_info);
>+  writel(0xa000a, _regs->win0_dsp_st);
>+  writel(0x0, _regs->win0_yrgb_mst);
>+  writel(0x01, >reg_cfg_done);
>+
>+  return 0;
>+}

I think this just workaround Linux iommu page fault by luck。
The reset value（what you called it is）your write just let win0 read a
320x240 rectangular from address 0 and display it at next frame（maybe 16ms 
later if your
current display is run at 60HZ）。

1. we don't know what content is at address 0, so you will see something 
strange on your monitor.
2. there is no guarantee that address 0 is really readable（maybe a security 
memory space， or maybe
it is not a valid address）， this may cause another issue that not easy to 
detect。

>+
>+struct rkvop_driverdata rk3328_driverdata = {
>+  .dsp_offset = 0x490,
>+  .win_offset = 0xd0,
>+  .features = VOP_FEATURE_OUTPUT_10BIT,
>+  .set_pin_polarity = rk3328_set_pin_polarity,
>+};
>+
>+static const struct udevice_id rk3328_vop_ids[] = {
>+  {
>+  .compatible = "rockchip,rk3328-vop",
>+  .data = (ulong)_driverdata
>+  },
>+  { /* sentile */ }
>+};
>+
>+static const struct video_ops rk3328_vop_ops = {
>+};
>+
>+U_BOOT_DRIVER(rk3328_vop) = {
>+  .name   = "rk3328_vop",

[PATCH v4] rockchip: rk3568: Add EmbedFire Lubancat 2 support

2023-08-05 Thread Andy Yan

LubanCat2 is a rk3568 based SBC from EmbedFire.

Specification:
- Rockchip rk3568
- LPDDR4/4X 1/2/4/8 GB
- TF scard slot
- eMMC 8/32/64/128 GB
- Gigabit ethernet x 2
- HDMI out
- USB 2.0 Host x 1
- USB 2.0 Type-C OTG x 1
- USB 3.0 Host x 1
- Mini PCIE interface for WIFI/BT module
- M.2 key for 2280 NVME
- 40 pin header

The dts file is sync from linux mainline.

Signed-off-by: Andy Yan 

---

Changes in v4:
- Add entry for this board to evb_rk3568/MAINTAINERS
- document this board at doc/board/rockchip/rockchip.rst
- restore the  copyright header of dts from linux kernel
- remove ETH_DESIGNWARE from defconfig
- remove mmc-hs200-1_8v from u-boot.dsti

Changes in v3:
- some alphabetical order update
- disable all SPI flash related options.
- remove bootph-all for pinctrl
- add emmc_datastrobe pinconfig for hs200/hs400 in u-boot.dtsi
- use USB_DWC3_GENERIC driver as Jonas suggested.
- add CONFIG_SPL_DM_SEQ_ALIAS

Changes in v2:
- enable SPL_FIT_SIGNATURE

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi |  27 +
 arch/arm/dts/rk3568-lubancat-2.dts | 733 +
 board/rockchip/evb_rk3568/MAINTAINERS  |   7 +
 configs/lubancat-2-rk3568_defconfig|  85 +++
 doc/board/rockchip/rockchip.rst|   1 +
 6 files changed, 854 insertions(+)
 create mode 100644 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3568-lubancat-2.dts
 create mode 100644 configs/lubancat-2-rk3568_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bd518064f3..64c885dcf9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -178,6 +178,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-soquartz-cm4.dtb \
rk3566-soquartz-model-a.dtb \
rk3568-evb.dtb \
+   rk3568-lubancat-2.dtb \
rk3568-nanopi-r5c.dtb \
rk3568-nanopi-r5s.dtb \
rk3568-odroid-m1.dtb \
diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi 
b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
new file mode 100644
index 00..27c6277523
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2023 Andy Yan 
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
+
+ {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+   mmc-hs400-1_8v;
+   mmc-hs400-enhanced-strobe;
+   pinctrl-0 = <_bus8 _clk _cmd _datastrobe>;
+};
+
+ {
+   bootph-all;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-lubancat-2.dts 
b/arch/arm/dts/rk3568-lubancat-2.dts
new file mode 100644
index 00..e653b067aa
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2.dts
@@ -0,0 +1,733 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 EmbedFire 
+ */
+
+/dts-v1/;
+#include 
+#include 
+#include 
+#include 
+#include "rk3568.dtsi"
+
+/ {
+   model = "EmbedFire LubanCat 2";
+   compatible = "embedfire,lubancat-2", "rockchip,rk3568";
+
+   aliases {
+   ethernet0 = 
+   ethernet1 = 
+   mmc0 = 
+   mmc1 = 
+   };
+
+   chosen: chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   user_led: user-led {
+   label = "user_led";
+   linux,default-trigger = "heartbeat";
+   default-state = "on";
+   gpios = < RK_PC7 GPIO_ACTIVE_LOW>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_led_pin>;
+   };
+   };
+
+   hdmi-con {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <_out_con>;
+   };
+   };
+   };
+
+   dc_5v: dc-5v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "dc_5v";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <330>;
+

Re:Re: [PATCH v3] rockchip: rk3568: Add EmbedFire Lubancat 2 support

2023-07-30 Thread Andy Yan




Hi Jonas：
  Thanks for you kindly review。












At 2023-07-30 21:22:36, "Jonas Karlman"  wrote:
>Hi Andy,
>
>On 2023-07-29 13:58, Andy Yan wrote:
>> LubanCat2 is a rk3568 based SBC from EmbedFire.
>> 
>> Specification:
>> - Rockchip rk3568
>> - LPDDR4/4X 1/2/4/8 GB
>> - TF scard slot
>> - eMMC 8/32/64/128 GB
>> - Gigabit ethernet x 2
>> - HDMI out
>> - USB 2.0 Host x 1
>> - USB 2.0 Type-C OTG x 1
>> - USB 3.0 Host x 1
>> - Mini PCIE interface for WIFI/BT module
>> - M.2 key for 2280 NVME
>> - 40 pin header
>> 
>> The dts file is sync from linux mainline.
>> 
>> There are some dts bootph-all and USB3 update according to Jonas 
>> suggestion[0],
>> so this patch based on Jonas patch [1] [2].
>> 
>> Signed-off-by: Andy Yan 
>> [0]:http://patchwork.ozlabs.org/project/uboot/patch/20230708102556.25472-1-andys...@163.com/
>> [1]:http://patchwork.ozlabs.org/project/uboot/cover/20230728115302.1735429-1-jo...@kwiboo.se/
>> [2]:http://patchwork.ozlabs.org/project/uboot/cover/20230728124011.1747408-1-jo...@kwiboo.se/
>> 
>> ---
>> 
>> Changes in v3:
>> - some alphabetical order update
>> - disable all SPI flash related options.
>> - remove bootph-all for pinctrl
>> - add emmc_datastrobe pinconfig for hs200/hs400 in u-boot.dtsi
>> - use USB_DWC3_GENERIC driver as Jonas suggested.
>> - add CONFIG_SPL_DM_SEQ_ALIAS
>> 
>> Changes in v2:
>> - enable SPL_FIT_SIGNATURE
>> 
>>  arch/arm/dts/Makefile  |   1 +
>>  arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi |  28 +
>>  arch/arm/dts/rk3568-lubancat-2.dts | 734 +
>>  configs/lubancat-2-rk3568_defconfig|  87 +++
>>  4 files changed, 850 insertions(+)
>>  create mode 100644 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
>>  create mode 100644 arch/arm/dts/rk3568-lubancat-2.dts
>>  create mode 100644 configs/lubancat-2-rk3568_defconfig
>
>You should add an entry for this board to evb_rk3568/MAINTAINERS and
>also to the documentation at doc/board/rockchip/rockchip.rst
>
>[...]
>
>> diff --git a/arch/arm/dts/rk3568-lubancat-2.dts 
>> b/arch/arm/dts/rk3568-lubancat-2.dts
>> new file mode 100644
>> index 00..da257b0591
>> --- /dev/null
>> +++ b/arch/arm/dts/rk3568-lubancat-2.dts
>> @@ -0,0 +1,734 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +
>> +/*
>> + * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
>> + * Copyright (c) 2023 EmbedFire 
>> + * Copyright (c) 2023 Andy Yan 
>
>You are changing copyright header on a file otherwise copied 1:1 from
>the linux kernel.
>
>> + */
>> +
>
>[...]
>
>> diff --git a/configs/lubancat-2-rk3568_defconfig 
>> b/configs/lubancat-2-rk3568_defconfig
>> new file mode 100644
>> index 00..278ee8dc70
>> --- /dev/null
>> +++ b/configs/lubancat-2-rk3568_defconfig
>> @@ -0,0 +1,87 @@
>> +CONFIG_ARM=y
>> +CONFIG_SKIP_LOWLEVEL_INIT=y
>> +CONFIG_COUNTER_FREQUENCY=2400
>> +CONFIG_ARCH_ROCKCHIP=y
>> +CONFIG_TEXT_BASE=0x00a0
>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>> +CONFIG_NR_DRAM_BANKS=2
>> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
>> +CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2"
>> +CONFIG_ROCKCHIP_RK3568=y
>> +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
>> +CONFIG_SPL_SERIAL=y
>> +CONFIG_SPL_STACK_R_ADDR=0x60
>> +CONFIG_SPL_STACK=0x40
>> +CONFIG_DEBUG_UART_BASE=0xFE66
>> +CONFIG_DEBUG_UART_CLOCK=2400
>> +CONFIG_SYS_LOAD_ADDR=0xc00800
>> +CONFIG_DEBUG_UART=y
>> +CONFIG_FIT=y
>> +CONFIG_FIT_VERBOSE=y
>> +CONFIG_SPL_FIT_SIGNATURE=y
>> +CONFIG_SPL_LOAD_FIT=y
>> +CONFIG_LEGACY_IMAGE_FORMAT=y
>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb"
>> +# CONFIG_DISPLAY_CPUINFO is not set
>> +CONFIG_DISPLAY_BOARDINFO_LATE=y
>> +CONFIG_SPL_MAX_SIZE=0x4
>> +CONFIG_SPL_PAD_TO=0x7f8000
>> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
>> +CONFIG_SPL_BSS_START_ADDR=0x400
>> +CONFIG_SPL_BSS_MAX_SIZE=0x4000
>> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
>> +CONFIG_SPL_STACK_R=y
>> +CONFIG_SPL_ATF=y
>> +CONFIG_CMD_GPIO=y
>> +CONFIG_CMD_GPT=y
>> +CONFIG_CMD_I2C=y
>> +CONFIG_CMD_MMC=y
>> +CONFIG_CMD_USB=y
>> +# CONFIG_CMD_SETEXPR is not set
>> +CONFIG_CMD_PMIC=y
>> +CONFIG_CMD_REGULATOR=

[PATCH v3] rockchip: rk3568: Add EmbedFire Lubancat 2 support

2023-07-29 Thread Andy Yan

LubanCat2 is a rk3568 based SBC from EmbedFire.

Specification:
- Rockchip rk3568
- LPDDR4/4X 1/2/4/8 GB
- TF scard slot
- eMMC 8/32/64/128 GB
- Gigabit ethernet x 2
- HDMI out
- USB 2.0 Host x 1
- USB 2.0 Type-C OTG x 1
- USB 3.0 Host x 1
- Mini PCIE interface for WIFI/BT module
- M.2 key for 2280 NVME
- 40 pin header

The dts file is sync from linux mainline.

There are some dts bootph-all and USB3 update according to Jonas suggestion[0],
so this patch based on Jonas patch [1] [2].

Signed-off-by: Andy Yan 
[0]:http://patchwork.ozlabs.org/project/uboot/patch/20230708102556.25472-1-andys...@163.com/
[1]:http://patchwork.ozlabs.org/project/uboot/cover/20230728115302.1735429-1-jo...@kwiboo.se/
[2]:http://patchwork.ozlabs.org/project/uboot/cover/20230728124011.1747408-1-jo...@kwiboo.se/

---

Changes in v3:
- some alphabetical order update
- disable all SPI flash related options.
- remove bootph-all for pinctrl
- add emmc_datastrobe pinconfig for hs200/hs400 in u-boot.dtsi
- use USB_DWC3_GENERIC driver as Jonas suggested.
- add CONFIG_SPL_DM_SEQ_ALIAS

Changes in v2:
- enable SPL_FIT_SIGNATURE

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi |  28 +
 arch/arm/dts/rk3568-lubancat-2.dts | 734 +
 configs/lubancat-2-rk3568_defconfig|  87 +++
 4 files changed, 850 insertions(+)
 create mode 100644 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3568-lubancat-2.dts
 create mode 100644 configs/lubancat-2-rk3568_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bd5887bf75..fb139a14fe 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -172,6 +172,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
+   rk3568-lubancat-2.dtb \
rk3568-nanopi-r5c.dtb \
rk3568-nanopi-r5s.dtb \
rk3568-odroid-m1.dtb \
diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi 
b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
new file mode 100644
index 00..52bd757bd0
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2023 Andy Yan 
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
+
+ {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+   mmc-hs200-1_8v;
+   mmc-hs400-1_8v;
+   mmc-hs400-enhanced-strobe;
+   pinctrl-0 = <_bus8 _clk _cmd _datastrobe>;
+};
+
+ {
+   bootph-all;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-lubancat-2.dts 
b/arch/arm/dts/rk3568-lubancat-2.dts
new file mode 100644
index 00..da257b0591
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2.dts
@@ -0,0 +1,734 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 EmbedFire 
+ * Copyright (c) 2023 Andy Yan 
+ */
+
+/dts-v1/;
+#include 
+#include 
+#include 
+#include 
+#include "rk3568.dtsi"
+
+/ {
+   model = "EmbedFire LubanCat 2";
+   compatible = "embedfire,lubancat-2", "rockchip,rk3568";
+
+   aliases {
+   ethernet0 = 
+   ethernet1 = 
+   mmc0 = 
+   mmc1 = 
+   };
+
+   chosen: chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   user_led: user-led {
+   label = "user_led";
+   linux,default-trigger = "heartbeat";
+   default-state = "on";
+   gpios = < RK_PC7 GPIO_ACTIVE_LOW>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_led_pin>;
+   };
+   };
+
+   hdmi-con {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <_out_con>;
+   };
+   };
+   };
+
+   dc_5v: dc-5v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "dc_5v";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-always-on;
+

[PATCH v2] rockchip: rk3568: Add support for Lubancat2 board from EmbedFire

2023-07-08 Thread Andy Yan

LubanCat2 is a rk3568 based SBC from EmbedFire.

Specification:
- Rockchip rk3568
- LPDDR4/4X 1/2/4/8 GB
- TF scard slot
- eMMC 8/32/64/128 GB
- Gigabit ethernet x 2
- HDMI out
- USB 2.0 Host x 1
- USB 2.0 Type-C OTG x 1
- USB 3.0 Host x 1
- Mini PCIE interface for WIFI/BT module
- M.2 key for 2280 NVME
- 40 pin header

The dts file is sync from linux mainline.

Signed-off-by: Andy Yan 

---

Changes in v2:
- enable SPL_FIT_SIGNATURE

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi |  87 +++
 arch/arm/dts/rk3568-lubancat-2.dts | 734 +
 configs/lubancat-2-rk3568_defconfig|  94 +++
 4 files changed, 917 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3568-lubancat-2.dts
 create mode 100644 configs/lubancat-2-rk3568_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 480269fa60..b177c0c4f9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -169,7 +169,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
-   rk3568-rock-3a.dtb
+   rk3568-rock-3a.dtb \
+   rk3568-lubancat-2.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-edgeble-neu6a-io.dtb \
diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi 
b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
new file mode 100644
index 00..42072dd0bd
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2023 Andy Yan 
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
+
+_bus8 {
+   bootph-all;
+};
+
+_clk {
+   bootph-all;
+};
+
+_cmd {
+   bootph-all;
+};
+
+_datastrobe {
+   bootph-all;
+};
+
+ {
+   bootph-all;
+};
+
+_pull_none {
+   bootph-all;
+};
+
+_pull_up_drv_level_2 {
+   bootph-all;
+};
+
+_pull_up {
+   bootph-all;
+};
+
+_bus4 {
+   bootph-all;
+};
+
+_clk {
+   bootph-all;
+};
+
+_cmd {
+   bootph-all;
+};
+
+_det {
+   bootph-all;
+};
+
+ {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+   mmc-hs200-1_8v;
+   mmc-hs400-1_8v;
+   mmc-hs400-enhanced-strobe;
+};
+
+ {
+   status = "disabled";
+};
+
+ {
+   status = "disabled";
+};
+
+_xfer {
+   bootph-all;
+};
+
+ {
+   clock-frequency = <2400>;
+   bootph-all;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-lubancat-2.dts 
b/arch/arm/dts/rk3568-lubancat-2.dts
new file mode 100644
index 00..da257b0591
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2.dts
@@ -0,0 +1,734 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 EmbedFire 
+ * Copyright (c) 2023 Andy Yan 
+ */
+
+/dts-v1/;
+#include 
+#include 
+#include 
+#include 
+#include "rk3568.dtsi"
+
+/ {
+   model = "EmbedFire LubanCat 2";
+   compatible = "embedfire,lubancat-2", "rockchip,rk3568";
+
+   aliases {
+   ethernet0 = 
+   ethernet1 = 
+   mmc0 = 
+   mmc1 = 
+   };
+
+   chosen: chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   user_led: user-led {
+   label = "user_led";
+   linux,default-trigger = "heartbeat";
+   default-state = "on";
+   gpios = < RK_PC7 GPIO_ACTIVE_LOW>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_led_pin>;
+   };
+   };
+
+   hdmi-con {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <_out_con>;
+   };
+   };
+   };
+
+   dc_5v: dc-5v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "dc_5v";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <330>;
+   regulato

Re:Re: [PATCH] rockchip: Restore support for boot scripts in legacy image format

2023-06-29 Thread Andy Yan







Hi: 











在 2023-06-29 22:07:05，"Jonas Karlman"  写道：
>Hi Kever,
>
>On 2023-06-29 12:51, Kever Yang wrote:
>> Hi Jonas,
>> 
>>  What is the legacy image format, does these boards really use than?
>> 
>> I think most of the board using linux distro image.
>
>The legacy image format it the normal boot script format,
>in the documentation it is called Legacy U-Boot image, see [1].
>
>i.e. boot scripts compiled with:
>
>  mkimage -T script -n 'Test script' -d boot.txt boot.scr
>
>Such boot scripts are used by some linux distro, e.g. Armbian.
>
>[1] 
>https://u-boot.readthedocs.io/en/latest/usage/cmd/source.html#legacy-u-boot-image

>


Yes, this is a common use case, I also run into this case a few weeks ago on 
armbian[2]:


The code handle this logic in u-boot  is image_locate_script.


[2 
]https://github.com/armbian/build/blob/main/config/bootscripts/boot-rockchip.cmd


>Regards,
>Jonas
>
>> 
>> 
>> Thanks,
>> 
>> - Kever
>> 
>> On 2023/6/27 03:43, Jonas Karlman wrote:
>>> Use of CONFIG_SPL_FIT_SIGNATURE=y cause CONFIG_LEGACY_IMAGE_FORMAT=n as
>>> default, this prevent boot scripts in legacy image format from working
>>> and was an unintended change in the listed fixes commits:
>>>
>>>Wrong image format for "source" command
>>>
>>> Add CONFIG_LEGACY_IMAGE_FORMAT=y to defconfig for affected boards to
>>> restore support for boot scripts in legacy image format.
>>>
>>> Fixes: 3bf8e4080763 ("board: rockchip: add Radxa ROCK5B Rk3588 board")
>>> Fixes: cf777572ca31 ("rockchip: rockpro64: Use SDMA to boost eMMC 
>>> performance")
>>> Fixes: 6e2b8344d60c ("rockchip: rock-pi-4: Use SDMA to boost eMMC 
>>> performance")
>>> Fixes: 1bf49d5a4a7c ("rockchip: rk3566-radxa-cm3-io: Update defconfig")
>>> Fixes: 703c170b40f2 ("rockchip: rk3568-evb: Update defconfig")
>>> Fixes: 68000f750acd ("rockchip: rk3568-rock-3a: Update defconfig")
>>> Fixes: 6fb02589a608 ("rockchip: rk3588-evb: Update defconfig")
>>> Signed-off-by: Jonas Karlman 
>>> ---
>>>   configs/evb-rk3568_defconfig  | 1 +
>>>   configs/evb-rk3588_defconfig  | 1 +
>>>   configs/radxa-cm3-io-rk3566_defconfig | 1 +
>>>   configs/rock-3a-rk3568_defconfig  | 1 +
>>>   configs/rock-pi-4-rk3399_defconfig| 1 +
>>>   configs/rock5b-rk3588_defconfig   | 1 +
>>>   configs/rockpro64-rk3399_defconfig| 1 +
>>>   7 files changed, 7 insertions(+)
>>>
>>> diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
>>> index 07819d105441..5f3fab7304c2 100644
>>> --- a/configs/evb-rk3568_defconfig
>>> +++ b/configs/evb-rk3568_defconfig
>>> @@ -22,6 +22,7 @@ CONFIG_FIT=y
>>>   CONFIG_FIT_VERBOSE=y
>>>   CONFIG_SPL_FIT_SIGNATURE=y
>>>   CONFIG_SPL_LOAD_FIT=y
>>> +CONFIG_LEGACY_IMAGE_FORMAT=y
>>>   CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
>>>   # CONFIG_DISPLAY_CPUINFO is not set
>>>   CONFIG_DISPLAY_BOARDINFO_LATE=y
>>> diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
>>> index d5f1c4b9ebc7..f49c2ca686a8 100644
>>> --- a/configs/evb-rk3588_defconfig
>>> +++ b/configs/evb-rk3588_defconfig
>>> @@ -23,6 +23,7 @@ CONFIG_FIT=y
>>>   CONFIG_FIT_VERBOSE=y
>>>   CONFIG_SPL_FIT_SIGNATURE=y
>>>   CONFIG_SPL_LOAD_FIT=y
>>> +CONFIG_LEGACY_IMAGE_FORMAT=y
>>>   CONFIG_OF_BOARD_SETUP=y
>>>   CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
>>>   # CONFIG_DISPLAY_CPUINFO is not set
>>> diff --git a/configs/radxa-cm3-io-rk3566_defconfig 
>>> b/configs/radxa-cm3-io-rk3566_defconfig
>>> index 56802d85cc25..488723dfaa30 100644
>>> --- a/configs/radxa-cm3-io-rk3566_defconfig
>>> +++ b/configs/radxa-cm3-io-rk3566_defconfig
>>> @@ -22,6 +22,7 @@ CONFIG_FIT=y
>>>   CONFIG_FIT_VERBOSE=y
>>>   CONFIG_SPL_FIT_SIGNATURE=y
>>>   CONFIG_SPL_LOAD_FIT=y
>>> +CONFIG_LEGACY_IMAGE_FORMAT=y
>>>   CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb"
>>>   # CONFIG_DISPLAY_CPUINFO is not set
>>>   CONFIG_DISPLAY_BOARDINFO_LATE=y
>>> diff --git a/configs/rock-3a-rk3568_defconfig 
>>> b/configs/rock-3a-rk3568_defconfig
>>> index 616499f2f82b..753d03914d90 100644
>>> --- a/configs/rock-3a-rk3568_defconfig
>>> +++ b/configs/rock-3a-rk3568_defconfig
>>> @@ -27,6 +27,7 @@ CONFIG_FIT=y
>>>   CONFIG_FIT_VERBOSE=y
>>>   CONFIG_SPL_FIT_SIGNATURE=y
>>>   CONFIG_SPL_LOAD_FIT=y
>>> +CONFIG_LEGACY_IMAGE_FORMAT=y
>>>   CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
>>>   # CONFIG_DISPLAY_CPUINFO is not set
>>>   CONFIG_DISPLAY_BOARDINFO_LATE=y
>>> diff --git a/configs/rock-pi-4-rk3399_defconfig 
>>> b/configs/rock-pi-4-rk3399_defconfig
>>> index 4b984adc6ef8..466868d80b03 100644
>>> --- a/configs/rock-pi-4-rk3399_defconfig
>>> +++ b/configs/rock-pi-4-rk3399_defconfig
>>> @@ -20,6 +20,7 @@ CONFIG_PCI=y
>>>   CONFIG_DEBUG_UART=y
>>>   # CONFIG_ANDROID_BOOT_IMAGE is not set
>>>   CONFIG_SPL_FIT_SIGNATURE=y
>>> +CONFIG_LEGACY_IMAGE_FORMAT=y
>>>   CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
>>>   CONFIG_DISPLAY_BOARDINFO_LATE=y
>>>   CONFIG_MISC_INIT_R=y
>>> diff --git a/configs/rock5b-rk3588_defconfig 
>>>

[PATCH] rockchip: rk3568: Add support for Lubancat2 board from EmbedFire

2023-06-22 Thread Andy Yan

LubanCat 2 is a rk3568 based SBC from EmbedFire.

Specification:
- Rockchip rk3568
- LPDDR4/4X 1/2/4/8 GB
- TF scard slot
- eMMC 8/32/64/128 GB
- Gigabit ethernet x 2
- HDMI out
- USB 2.0 Host x 1
- USB 2.0 Type-C OTG x 1
- USB 3.0 Host x 1
- Mini PCIE interface for WIFI/BT module
- M.2 key for 2280 NVME
- 40 pin header

The dts file is sync from linux mainline.

Signed-off-by: Andy Yan 
---

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi |  87 +++
 arch/arm/dts/rk3568-lubancat-2.dts | 734 +
 configs/lubancat-2-rk3568_defconfig|  96 +++
 4 files changed, 919 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3568-lubancat-2.dts
 create mode 100644 configs/lubancat-2-rk3568_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 480269fa60..b177c0c4f9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -169,7 +169,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
-   rk3568-rock-3a.dtb
+   rk3568-rock-3a.dtb \
+   rk3568-lubancat-2.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-edgeble-neu6a-io.dtb \
diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi 
b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
new file mode 100644
index 00..42072dd0bd
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2023 Andy Yan 
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
+
+_bus8 {
+   bootph-all;
+};
+
+_clk {
+   bootph-all;
+};
+
+_cmd {
+   bootph-all;
+};
+
+_datastrobe {
+   bootph-all;
+};
+
+ {
+   bootph-all;
+};
+
+_pull_none {
+   bootph-all;
+};
+
+_pull_up_drv_level_2 {
+   bootph-all;
+};
+
+_pull_up {
+   bootph-all;
+};
+
+_bus4 {
+   bootph-all;
+};
+
+_clk {
+   bootph-all;
+};
+
+_cmd {
+   bootph-all;
+};
+
+_det {
+   bootph-all;
+};
+
+ {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+   mmc-hs200-1_8v;
+   mmc-hs400-1_8v;
+   mmc-hs400-enhanced-strobe;
+};
+
+ {
+   status = "disabled";
+};
+
+ {
+   status = "disabled";
+};
+
+_xfer {
+   bootph-all;
+};
+
+ {
+   clock-frequency = <2400>;
+   bootph-all;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-lubancat-2.dts 
b/arch/arm/dts/rk3568-lubancat-2.dts
new file mode 100644
index 00..da257b0591
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2.dts
@@ -0,0 +1,734 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 EmbedFire 
+ * Copyright (c) 2023 Andy Yan 
+ */
+
+/dts-v1/;
+#include 
+#include 
+#include 
+#include 
+#include "rk3568.dtsi"
+
+/ {
+   model = "EmbedFire LubanCat 2";
+   compatible = "embedfire,lubancat-2", "rockchip,rk3568";
+
+   aliases {
+   ethernet0 = 
+   ethernet1 = 
+   mmc0 = 
+   mmc1 = 
+   };
+
+   chosen: chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   user_led: user-led {
+   label = "user_led";
+   linux,default-trigger = "heartbeat";
+   default-state = "on";
+   gpios = < RK_PC7 GPIO_ACTIVE_LOW>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_led_pin>;
+   };
+   };
+
+   hdmi-con {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <_out_con>;
+   };
+   };
+   };
+
+   dc_5v: dc-5v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "dc_5v";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+

Re: rockchip: correctly set vop0 or vop1

2020-06-27 Thread Andy Yan


Hi :

On 6/27/20 8:56 PM, Kever Yang wrote:

+Andy Yan for this topic,

Hi Patrick and Arnaud,

    I would like to leave this patch until the code fits for all the 
socs,


Thanks,

- Kever

On 2020/6/8 下午8:39, Patrick Wildt wrote:

On Mon, Jun 08, 2020 at 02:24:32PM +0200, Arnaud Patard wrote:

Patrick Wildt  writes:


On Mon, Jun 08, 2020 at 10:18:19AM +0200, Arnaud Patard wrote:

Patrick Wildt  writes:

Hi,


The EDP_LCDC_SEL bit has to be set correctly to select vop0 or
vop1, but so far we have set it in both conditions, which is not
correct.

Can someone verify this is the correct way round?  vop1 -> set,
vop0 -> clear?

Signed-off-by: Patrick Wildt 

diff --git a/drivers/video/rockchip/rk_edp.c 
b/drivers/video/rockchip/rk_edp.c

index 92188be9275..000bd481408 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -1062,7 +1062,8 @@ static int rk_edp_probe(struct udevice *dev)
  rk_setreg(>grf->soc_con12, 1 << 4);
    /* select epd signal from vop0 or vop1 */
-    rk_setreg(>grf->soc_con6, (vop_id == 1) ? (1 << 5) : 
(1 << 5));

+    rk_clrsetreg(>grf->soc_con6, (1 << 5),
+    (vop_id == 1) ? (1 << 5) : (0 << 5));
While working on PBP EDP support, found this too but I'm not sure 
it's

fine or not. For rk3399, my (not yet published) patch is doing:

+   if (vop_id == 0)
+   rk_clrreg(>grf->soc_con20, (1 << 5));
+   else
+   rk_setreg(>grf->soc_con20, (1 << 5));

I believe that the rk3288 may need similar treatment but I've yet to
look at the rk3288 manual.

Arnaud

Yes, it does.  If you look at the linux code, they have:

static const struct rockchip_dp_chip_data rk3399_edp = {
 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, 
RK3399_EDP_LCDC_SEL),

 .chip_type = RK3399_EDP,
};

static const struct rockchip_dp_chip_data rk3288_dp = {
 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, 
RK3288_EDP_LCDC_SEL),

 .chip_type = RK3288_DP,
};



It's true that different soc have different grf register for selecting 
lcdc/vop, and so it is for other modules such as rockchip_gmac/pinctrl. 
The above code in linux kernel is a example for how  we handle this case.




which indicates that for rk3399 *and* rk3288 the bit has to be set to
select "lit".  Now your diff looks equivalent to mine, apart from 
using

a different operation to achieve the same goal.

The linux code does

 ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, 
encoder);

 if (ret < 0)
 return;

 if (ret)
 val = dp->data->lcdsel_lit;
 else
 val = dp->data->lcdsel_big;

Assuming that endpoint_id essentiall returns vop id 0 or vop id 1, 
this

would mean that vop1 -> lit -> set bit and vop0 -> big -> clr bit.

That said, my diff seems to be fine, and your RK3399 code as well.  Do
you agree?
According to the code you've shown, it should be fine for rk3288 I 
guess
but not for rk3399. Please note that it's grf soc_con6 register for 
rk3288

but grf soc_con20 for rk3399.

Arnaud

Exactly, which is why you had that if defined() in your diff, to compile
one part of the code for RK3288, and the other for RK3399. :) The bit
though happens to be the same.

[PATCH 1/2] rockchip: rk3308: allow loading larger kernel Image

2019-12-25 Thread Andy Yan

When compile the curren mainline linux kernel(Linux 5.5-rc3)
with defconfig, the final Image is 29M, it's much
larger than Linux 5.4.

On the current u-boot side on rk3308, the gap between
kernel and fdt is 25M, the fdt will overwrite kernel
Image, so move ftd to a higher memory to give 34M
gab for them.

Signed-off-by: Andy Yan 
---

 include/configs/rk3308_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index a67d3d7d1b..bd9ac826f3 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -42,7 +42,7 @@
 #define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x0050\0" \
"pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x01f0\0" \
+   "fdt_addr_r=0x0280\0" \
"kernel_addr_r=0x0068\0" \
"ramdisk_addr_r=0x0400\0"
 
-- 
2.17.1

[PATCH 2/2] doc: rockchip: Fix reference the wrong defconfig name of ROC-CC-RK3308

2019-12-25 Thread Andy Yan

The defconfig file for ROC-CC-RK3308 is roc-cc-rk3308_defconfig.

Fixes: 7f08bfb74f04 ("doc: rockchip: Add documentation for rk3308 based
boards")

Signed-off-by: Andy Yan 
---

 doc/README.rockchip | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/doc/README.rockchip b/doc/README.rockchip
index dae4ebc8e4..ffab8ff417 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -50,7 +50,7 @@ Two RK3036 boards are supported:
 Two RK3308 boards are supported:
 
- EVB RK3308 - use evb-rk3308 configuration
-   - ROC-CC-RK3308 - use roc-rk3308-cc configuration
+   - ROC-CC-RK3308 - use roc-cc-rk3308 configuration
 
 Two RK3328 board are supported:
 
@@ -106,7 +106,7 @@ For example:
- Compile U-Boot
  => cd /path/to/u-boot
  => export BL31=/path/to/rkbin/bin/rk33/rk3308_bl31_v2.22.elf
- => make roc-rk3308-cc_defconfig
+ => make roc-cc-rk3308_defconfig
  => make CROSS_COMPILE=aarch64-linux-gnu- all
  => ./tools/mkimage -n rk3308 -T rksd -d 
/path/to/rkbin/bin/rk33/rk3308_ddr_589MHz_uart2_m0_v1.26.bin idbloader.img
  => cat spl/u-boot-spl.bin  >> idbloader.img
-- 
2.17.1

[U-Boot] [PATCH 2/4] rockchip: rk3308: enable spl-fifo-mode for emmc

2019-11-26 Thread Andy Yan

We need load some parts of ATF to sram, but rockchip
dwmmc controllers can't do dma to non-ddr addresses
space, so set the mmc controller into fifo mode in spl.

And show my best respect to Heiko's work for this solution.

Signed-off-by: Andy Yan 
---

 arch/arm/dts/rk3308-u-boot.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi
index 1a68decef3..f5a595337e 100644
--- a/arch/arm/dts/rk3308-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-u-boot.dtsi
@@ -12,6 +12,8 @@
 };
 
  {
+   /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+   u-boot,spl-fifo-mode;
u-boot,dm-pre-reloc;
 };
 
-- 
2.17.1



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[U-Boot] [PATCH 4/4] rockchip: evb-px5: disable NET

2019-11-26 Thread Andy Yan

PX5 evb has no ETH port, so disable it.

Signed-off-by: Andy Yan 
---

 configs/evb-px5_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index f9b17be10e..2d18da6cc8 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -45,7 +45,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names 
interrupt-parent"
 CONFIG_TPL_OF_PLATDATA=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_NET is not set
 CONFIG_TPL_DM=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
-- 
2.17.1



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[U-Boot] [PATCH 1/4] doc: rockchip: Update build instruction for rk3308

2019-11-26 Thread Andy Yan

After commit d8765e2422cd ("Enable building of u-boot.itb
on Rockchip platform"), u-boot.itb will automatically
generated by "make all" command, manually command
"make u-boot.itb" is no longer needed.

Signed-off-by: Andy Yan 
---

 doc/README.rockchip | 1 -
 1 file changed, 1 deletion(-)

diff --git a/doc/README.rockchip b/doc/README.rockchip
index 67c14006a3..dae4ebc8e4 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -108,7 +108,6 @@ For example:
  => export BL31=/path/to/rkbin/bin/rk33/rk3308_bl31_v2.22.elf
  => make roc-rk3308-cc_defconfig
  => make CROSS_COMPILE=aarch64-linux-gnu- all
- => make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb
  => ./tools/mkimage -n rk3308 -T rksd -d 
/path/to/rkbin/bin/rk33/rk3308_ddr_589MHz_uart2_m0_v1.26.bin idbloader.img
  => cat spl/u-boot-spl.bin  >> idbloader.img
 
-- 
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[U-Boot] [PATCH 3/4] rockchip: px5: enable spl-fifo-mode for emmc for px5-evb

2019-11-26 Thread Andy Yan

We need load some parts of ATF to sram, but rockchip
dwmmc controllers can't do dma to non-ddr addresses
space, so set the mmc controller into fifo mode in spl.

Signed-off-by: Andy Yan 
---

 arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi 
b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
index 002767a033..936ce55727 100644
--- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
@@ -58,6 +58,8 @@
 };
 
  {
+   /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+   u-boot,spl-fifo-mode;
u-boot,dm-pre-reloc;
 };
 
-- 
2.17.1



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[U-Boot] [PATCH v3 9/9] doc: rockchip: Add documentation for rk3308 based boards

2019-11-13 Thread Andy Yan

Add build documentation for rk3308 based boards.

Signed-off-by: Andy Yan 

---

Changes in v3:
- Doc update with more detail message.

 doc/README.rockchip | 92 -
 1 file changed, 91 insertions(+), 1 deletion(-)

diff --git a/doc/README.rockchip b/doc/README.rockchip
index d17afeabdd..67c14006a3 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -47,6 +47,11 @@ Two RK3036 boards are supported:
- EVB RK3036 - use evb-rk3036 configuration
- Kylin - use kylin_rk3036 configuration
 
+Two RK3308 boards are supported:
+
+   - EVB RK3308 - use evb-rk3308 configuration
+   - ROC-CC-RK3308 - use roc-rk3308-cc configuration
+
 Two RK3328 board are supported:
 
- EVB RK3328 - use evb-rk3328_defconfig
@@ -94,7 +99,20 @@ For example:
 
 (or you can use another cross compiler if you prefer)
 
-2. To build RK3399 board:
+2. To build RK3308 board:
+   - Get the rkbin
+ => git clone https://github.com/rockchip-linux/rkbin.git
+
+   - Compile U-Boot
+ => cd /path/to/u-boot
+ => export BL31=/path/to/rkbin/bin/rk33/rk3308_bl31_v2.22.elf
+ => make roc-rk3308-cc_defconfig
+ => make CROSS_COMPILE=aarch64-linux-gnu- all
+ => make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb
+ => ./tools/mkimage -n rk3308 -T rksd -d 
/path/to/rkbin/bin/rk33/rk3308_ddr_589MHz_uart2_m0_v1.26.bin idbloader.img
+ => cat spl/u-boot-spl.bin  >> idbloader.img
+
+3. To build RK3399 board:
 
Option 1: Package the image with Rockchip miniloader:
 
@@ -203,6 +221,78 @@ as several other platforms do. However it does not seem to 
be possible to
 use the existing boot ROM code from SPL.
 
 
+Writing to the eMMC with USB on ROC-RK3308-CC
+=
+For USB to work you must get your board into Bootrom mode,
+either by erasing the eMMC or short circuit the GND and D0
+on core board.
+
+Connect the board to your computer via tyepc.
+=> rkdeveloptool db rk3308_loader_v1.26.117.bin
+=> rkdeveloptool wl 0x40 idbloader.img
+=> rkdeveloptool wl 0x4000 u-boot.itb
+=> rkdeveloptool rd
+
+Then you will see the boot log from Debug UART at baud rate 150:
+DDR Version V1.26
+REGFB: 0x0032, 0x0032
+In
+589MHz
+DDR3
+ Col=10 Bank=8 Row=14 Size=256MB
+msch:1
+Returning to boot ROM...
+
+U-Boot SPL 2020.01-rc1-00225-g34b681327f (Nov 14 2019 - 10:58:04 +0800)
+Trying to boot from MMC1
+INFO:Preloader serial: 2
+NOTICE:  BL31: v1.3(release):30f1405
+NOTICE:  BL31: Built : 17:08:28, Sep 23 2019
+INFO:Lastlog: last=0x10, realtime=0x102000, size=0x2000
+INFO:ARM GICv2 driver initialized
+INFO:Using opteed sec cpu_context!
+INFO:boot cpu mask: 1
+INFO:plat_rockchip_pmu_init: pd status 0xe b
+INFO:BL31: Initializing runtime services
+WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE 
initialization. SMC`s destined for OPTEE will rK
+ERROR:   Error initializing runtime service opteed_fast
+INFO:BL31: Preparing for EL3 exit to normal world
+INFO:Entry point address = 0x60
+INFO:SPSR = 0x3c9
+
+
+U-Boot 2020.01-rc1-00225-g34b681327f (Nov 14 2019 - 10:58:47 +0800)
+
+Model: Firefly ROC-RK3308-CC board
+DRAM:  254 MiB
+MMC:   dwmmc@ff48: 0, dwmmc@ff49: 1
+rockchip_dnl_key_pressed read adc key val failed
+Net:   No ethernet found.
+Hit any key to stop autoboot:  0
+Card did not respond to voltage select!
+switch to partitions #0, OK
+mmc1(part 0) is current device
+Scanning mmc 1:4...
+Found /extlinux/extlinux.conf
+Retrieving file: /extlinux/extlinux.conf
+151 bytes read in 3 ms (48.8 KiB/s)
+1:  kernel-mainline
+Retrieving file: /Image
+14737920 bytes read in 377 ms (37.3 MiB/s)
+append: earlycon=uart8250,mmio32,0xff0c console=ttyS2,150n8
+Retrieving file: /rk3308-roc-cc.dtb
+28954 bytes read in 4 ms (6.9 MiB/s)
+Flattened Device Tree blob at 01f0
+Booting using the fdt blob at 0x1f0
+## Loading Device Tree to 0df3a000, end 0df44119 ... OK
+
+Starting kernel ...
+[0.00] Booting Linux on physical CPU 0x00 [0x410fd042]
+[0.00] Linux version 5.4.0-rc1-00040-g4dc2d508fa47-dirty (andy@B150) 
(gcc version 6.3.1 20170404 (Linaro GCC 6.3-209
+[0.00] Machine model: Firefly ROC-RK3308-CC board
+[0.00] earlycon: uart8250 at MMIO32 0xff0c (options '')
+[0.00] printk: bootconsole [uart8250] enabled
+
 Booting from an SD card
 ===
 
-- 
2.17.1



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[U-Boot] [PATCH v3 8/9] rockchip: rk3308: Add support for ROC-RK3308-CC board

2019-11-13 Thread Andy Yan

ROC-RK3308-CC is a rk3308 based board designed by
Firelfy, with eMMC and 256MB DDR3 and RTL8188 Wifi
on board.

Signed-off-by: Andy Yan 

---

Changes in v3:
- rename config to roc-cc-rk3308_defconfig

 arch/arm/mach-rockchip/rk3308/Kconfig|  5 ++
 board/firefly/firefly-rk3308/Kconfig | 15 
 board/firefly/firefly-rk3308/MAINTAINERS |  5 ++
 board/firefly/firefly-rk3308/Makefile|  7 ++
 board/firefly/firefly-rk3308/roc_cc_rk3308.c | 82 
 configs/roc-cc-rk3308_defconfig  | 77 ++
 include/configs/firefly_rk3308.h | 20 +
 7 files changed, 211 insertions(+)
 create mode 100644 board/firefly/firefly-rk3308/Kconfig
 create mode 100644 board/firefly/firefly-rk3308/MAINTAINERS
 create mode 100644 board/firefly/firefly-rk3308/Makefile
 create mode 100644 board/firefly/firefly-rk3308/roc_cc_rk3308.c
 create mode 100644 configs/roc-cc-rk3308_defconfig
 create mode 100644 include/configs/firefly_rk3308.h

diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig 
b/arch/arm/mach-rockchip/rk3308/Kconfig
index c74d1fc7f1..b9fdfe2e95 100644
--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -4,6 +4,10 @@ config TARGET_EVB_RK3308
bool "EVB_RK3308"
select BOARD_LATE_INIT
 
+config TARGET_ROC_RK3308_CC
+   bool "Firefly roc-rk3308-cc"
+   select BOARD_LATE_INIT
+
 config SYS_SOC
default "rk3308"
 
@@ -18,5 +22,6 @@ config ROCKCHIP_BOOT_MODE_REG
 
 
 source "board/rockchip/evb_rk3308/Kconfig"
+source "board/firefly/firefly-rk3308/Kconfig"
 
 endif
diff --git a/board/firefly/firefly-rk3308/Kconfig 
b/board/firefly/firefly-rk3308/Kconfig
new file mode 100644
index 00..80b1ad85a2
--- /dev/null
+++ b/board/firefly/firefly-rk3308/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROC_RK3308_CC
+
+config SYS_BOARD
+   default "firefly-rk3308"
+
+config SYS_VENDOR
+   default "firefly"
+
+config SYS_CONFIG_NAME
+   default "firefly_rk3308"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+
+endif
diff --git a/board/firefly/firefly-rk3308/MAINTAINERS 
b/board/firefly/firefly-rk3308/MAINTAINERS
new file mode 100644
index 00..8670d8c6a8
--- /dev/null
+++ b/board/firefly/firefly-rk3308/MAINTAINERS
@@ -0,0 +1,5 @@
+ROC-RK3308-CC
+M:  Andy Yan 
+S:  Maintained
+F:  board/firefly/firefly-rk3308/roc_rk3308_cc.c
+F:  configs/roc-rk3308-cc_defconfig
diff --git a/board/firefly/firefly-rk3308/Makefile 
b/board/firefly/firefly-rk3308/Makefile
new file mode 100644
index 00..4c50b26ea9
--- /dev/null
+++ b/board/firefly/firefly-rk3308/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += roc_cc_rk3308.o
diff --git a/board/firefly/firefly-rk3308/roc_cc_rk3308.c 
b/board/firefly/firefly-rk3308/roc_cc_rk3308.c
new file mode 100644
index 00..1deaa39516
--- /dev/null
+++ b/board/firefly/firefly-rk3308/roc_cc_rk3308.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#if defined(CONFIG_DEBUG_UART)
+#define GRF_BASE   0xff00
+
+enum {
+   GPIO1C7_SHIFT   = 8,
+   GPIO1C7_MASK= GENMASK(11, 8),
+   GPIO1C7_GPIO= 0,
+   GPIO1C7_UART1_RTSN,
+   GPIO1C7_UART2_TX_M0,
+   GPIO1C7_SPI2_MOSI,
+   GPIO1C7_JTAG_TMS,
+
+   GPIO1C6_SHIFT   = 4,
+   GPIO1C6_MASK= GENMASK(7, 4),
+   GPIO1C6_GPIO= 0,
+   GPIO1C6_UART1_CTSN,
+   GPIO1C6_UART2_RX_M0,
+   GPIO1C6_SPI2_MISO,
+   GPIO1C6_JTAG_TCLK,
+
+   GPIO4D3_SHIFT   = 6,
+   GPIO4D3_MASK= GENMASK(7, 6),
+   GPIO4D3_GPIO= 0,
+   GPIO4D3_SDMMC_D3,
+   GPIO4D3_UART2_TX_M1,
+
+   GPIO4D2_SHIFT   = 4,
+   GPIO4D2_MASK= GENMASK(5, 4),
+   GPIO4D2_GPIO= 0,
+   GPIO4D2_SDMMC_D2,
+   GPIO4D2_UART2_RX_M1,
+
+   UART2_IO_SEL_SHIFT  = 2,
+   UART2_IO_SEL_MASK   = GENMASK(3, 2),
+   UART2_IO_SEL_M0 = 0,
+   UART2_IO_SEL_M1,
+   UART2_IO_SEL_USB,
+};
+
+void board_debug_uart_init(void)
+{
+   static struct rk3308_grf * const grf = (void *)GRF_BASE;
+
+   /* Enable early UART2 channel m0 on the rk3308 */
+   rk_clrsetreg(>soc_con5, UART2_IO_SEL_MASK,
+UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
+   rk_clrsetreg(>gpio1ch_iomux,
+GPIO1C6_MASK | GPIO1C7_MASK,
+GPIO1C6_UART2_RX_M0 << GPIO1C6_SHIFT |
+GPIO1C7_UART2_TX_M0 << GPIO1C7_SHIFT);
+}
+#endif
+
+#define KEY_DOWN_MIN_VAL0
+#define KEY_DOWN_MAX_VAL30
+
+int rockchi

[U-Boot] [PATCH v3 7/9] rockchip: rk3308: Add dts for ROC-RK3308-CC

2019-11-13 Thread Andy Yan

Add dts file for ROC-RK3308-CC from firefly.

Sync form linux rockchip for v5.5-armsoc/dts64:
"arm64: dts: rockchip: Add devicetree for board roc-rk3308-cc"
(sha1: 4403e1237be3af0977aa23ef399e3496316317a0)

Signed-off-by: Andy Yan 

---

Changes in v3:
- Add commit message.

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi |  17 +++
 arch/arm/dts/rk3308-roc-cc.dts | 190 +
 3 files changed, 209 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-roc-cc.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f2ea546831..be5c8d0ff6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -94,7 +94,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-vyasa.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3308) += \
-   rk3308-evb.dtb
+   rk3308-evb.dtb \
+   rk3308-roc-cc.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
diff --git a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi 
b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
new file mode 100644
index 00..ffbe742053
--- /dev/null
+++ b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+#include "rk3308-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", 
+   };
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts
new file mode 100644
index 00..e10aa638a3
--- /dev/null
+++ b/arch/arm/dts/rk3308-roc-cc.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3308.dtsi"
+
+/ {
+   model = "Firefly ROC-RK3308-CC board";
+   compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308";
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   ir_rx {
+   compatible = "gpio-ir-receiver";
+   gpios = < RK_PC0 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_recv_pin>;
+   };
+
+   ir_tx {
+   compatible = "pwm-ir-tx";
+   pwms = < 0 25000 0>;
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   power {
+   label = "firefly:red:power";
+   linux,default-trigger = "ir-power-click";
+   default-state = "on";
+   gpios = < RK_PA6 GPIO_ACTIVE_HIGH>;
+   };
+
+   user {
+   label = "firefly:blue:user";
+   linux,default-trigger = "ir-user-click";
+   default-state = "off";
+   gpios = < RK_PB2 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   typec_vcc5v: typec-vcc5v {
+   compatible = "regulator-fixed";
+   regulator-name = "typec_vcc5v";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vcc5v0_sys: vcc5v0-sys {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_sys";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   vin-supply = <_vcc5v>;
+   };
+
+   vdd_core: vdd-core {
+   compatible = "pwm-regulator";
+   pwms = < 0 5000 1>;
+   regulator-name = "vdd_core";
+   regulator-min-microvolt = <827000>;
+   regulator-max-microvolt = <134>;
+   regulator-init-microvolt = <1015000>;
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-settling-time-up-us = <250>;
+   pwm-supply = <_sys>;
+   };
+
+   vdd_log: vdd-log {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_log";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <105>;
+   regulator-max-microvolt = <105>;
+   vin-supply = <_sys>;
+   };
+
+   vcc_io: vcc-io {
+

[U-Boot] [PATCH v3 5/9] rockchip: rk3308: Add sdram driver

2019-11-13 Thread Andy Yan

A dm based dram driver for rk3308 u-boot
to get capacity.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang
---

Changes in v3: None

 drivers/ram/rockchip/Makefile   |  1 +
 drivers/ram/rockchip/sdram_rk3308.c | 55 +
 2 files changed, 56 insertions(+)
 create mode 100644 drivers/ram/rockchip/sdram_rk3308.c

diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index feb1f82d00..1adca32dcb 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -9,5 +9,6 @@ obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o
 obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o
diff --git a/drivers/ram/rockchip/sdram_rk3308.c 
b/drivers/ram/rockchip/sdram_rk3308.c
new file mode 100644
index 00..43d44cce62
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3308.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct dram_info {
+   struct ram_info info;
+   struct rk3308_grf *grf;
+};
+
+static int rk3308_dmc_probe(struct udevice *dev)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   priv->info.base = CONFIG_SYS_SDRAM_BASE;
+   priv->info.size = rockchip_sdram_size((phys_addr_t)>grf->os_reg2);
+
+   return 0;
+}
+
+static int rk3308_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   *info = priv->info;
+
+   return 0;
+}
+
+static struct ram_ops rk3308_dmc_ops = {
+   .get_info = rk3308_dmc_get_info,
+};
+
+static const struct udevice_id rk3308_dmc_ids[] = {
+   { .compatible = "rockchip,rk3308-dmc" },
+   { }
+};
+
+U_BOOT_DRIVER(dmc_rk3308) = {
+   .name = "rockchip_rk3308_dmc",
+   .id = UCLASS_RAM,
+   .of_match = rk3308_dmc_ids,
+   .ops = _dmc_ops,
+   .probe = rk3308_dmc_probe,
+   .priv_auto_alloc_size = sizeof(struct dram_info),
+};
-- 
2.17.1



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[U-Boot] [PATCH v3 6/9] rockchip: mkimage: add support for RK3308

2019-11-13 Thread Andy Yan

Usage:

 (1) tools/mkimage -n rk3308 -T rksd -d tpl/u-boot-tpl.bin idbloader.img
 (2) cat spl/u-boot-spl.bin >> idbloader.img
 (3) upgrade_tool wl 0x40 idbloader.img

Note:
  When use a ddr binary from rkbin as tpl, use it replace u-boot-tpl.bin in (1)

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang
---

Changes in v3: None

 tools/rkcommon.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 831c2ad820..a16f83c1ef 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -72,6 +72,7 @@ static struct spl_info spl_infos[] = {
{ "rk3188", "RK31", 0x8000 - 0x800, true },
{ "rk322x", "RK32", 0x8000 - 0x1000, false },
{ "rk3288", "RK32", 0x8000, false },
+   { "rk3308", "RK33", 0x4 - 0x1000, false},
{ "rk3328", "RK32", 0x8000 - 0x1000, false },
{ "rk3368", "RK33", 0x8000 - 0x1000, false },
{ "rk3399", "RK33", 0x3 - 0x2000, false },
-- 
2.17.1



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[U-Boot] [PATCH v3 2/9] rockchip: clk: Add clk driver for rk3308

2019-11-13 Thread Andy Yan

From: Finley Xiao 

Add clk controller driver for RK3308 SOC.

This patch depends on Elaine's pll patch[0].

[0]http://patchwork.ozlabs.org/patch/1183718/

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang
---

Changes in v3: None

 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk_rk3308.c  | 1078 
 include/dt-bindings/clock/rk3308-cru.h |  387 +
 3 files changed, 1466 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk_rk3308.c
 create mode 100644 include/dt-bindings/clock/rk3308-cru.h

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 03a9fa77ba..f2068a8e94 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
diff --git a/drivers/clk/rockchip/clk_rk3308.c 
b/drivers/clk/rockchip/clk_rk3308.c
new file mode 100644
index 00..e5653bbad7
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -0,0 +1,1078 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+   VCO_MAX_HZ  = 3200U * 100,
+   VCO_MIN_HZ  = 800 * 100,
+   OUTPUT_MAX_HZ   = 3200U * 100,
+   OUTPUT_MIN_HZ   = 24 * 100,
+};
+
+#define DIV_TO_RATE(input_rate, div)((input_rate) / ((div) + 1))
+
+#define RK3308_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \
+{   \
+   .rate   = _rate##U, \
+   .aclk_div = _aclk_div,  \
+   .pclk_div = _pclk_div,  \
+}
+
+static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE(13, 6, 325, 1, 1, 1, 0),
+   RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
+   RK3036_PLL_RATE(81600, 1, 68, 2, 1, 1, 0),
+   RK3036_PLL_RATE(74800, 2, 187, 3, 1, 1, 0),
+};
+
+static struct rockchip_cpu_rate_table rk3308_cpu_rates[] = {
+   RK3308_CPUCLK_RATE(12, 1, 5),
+   RK3308_CPUCLK_RATE(100800, 1, 5),
+   RK3308_CPUCLK_RATE(81600, 1, 3),
+   RK3308_CPUCLK_RATE(6, 1, 3),
+   RK3308_CPUCLK_RATE(40800, 1, 1),
+};
+
+static struct rockchip_pll_clock rk3308_pll_clks[] = {
+   [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
+RK3308_MODE_CON, 0, 10, 0, rk3308_pll_rates),
+   [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
+RK3308_MODE_CON, 2, 10, 0, NULL),
+   [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
+ RK3308_MODE_CON, 4, 10, 0, NULL),
+   [VPLL1] = PLL(pll_rk3328, PLL_VPLL1, RK3308_PLL_CON(24),
+ RK3308_MODE_CON, 6, 10, 0, NULL),
+};
+
+static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz)
+{
+   struct rk3308_cru *cru = priv->cru;
+   const struct rockchip_cpu_rate_table *rate;
+   ulong old_rate;
+
+   rate = rockchip_get_cpu_settings(rk3308_cpu_rates, hz);
+   if (!rate) {
+   printf("%s unsupport rate\n", __func__);
+   return -EINVAL;
+   }
+
+   /*
+* select apll as cpu/core clock pll source and
+* set up dependent divisors for PERI and ACLK clocks.
+* core hz : apll = 1:1
+*/
+   old_rate = rockchip_pll_get_rate(_pll_clks[APLL],
+priv->cru, APLL);
+   if (old_rate > hz) {
+   if (rockchip_pll_set_rate(_pll_clks[APLL],
+ priv->cru, APLL, hz))
+   return -EINVAL;
+   rk_clrsetreg(>clksel_con[0],
+CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
+CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
+rate->aclk_div << CORE_ACLK_DIV_SHIFT |
+rate->pclk_div << CORE_DBG_DIV_SHIFT |
+CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
+0 << CORE_DIV_CON_SHIFT);
+   } else if (old_rate < hz) {
+   rk_clrsetreg(>clksel_con[0],
+CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
+

[U-Boot] [PATCH v3 3/9] arm: dts: rockchip: Add dts for rk3308 evb

2019-11-13 Thread Andy Yan

Add dts for rk3308 evb, sync from the linux kernel
upstream list [0].

[0]https://patchwork.kernel.org/patch/11201555/

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang
---

Changes in v3: None

 arch/arm/dts/Makefile   |3 +
 arch/arm/dts/rk3308-evb-u-boot.dtsi |   17 +
 arch/arm/dts/rk3308-evb.dts |  230 
 arch/arm/dts/rk3308-u-boot.dtsi |   25 +
 arch/arm/dts/rk3308.dtsi| 1829 +++
 5 files changed, 2104 insertions(+)
 create mode 100644 arch/arm/dts/rk3308-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-evb.dts
 create mode 100644 arch/arm/dts/rk3308-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 85ef00a2bd..f2ea546831 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -93,6 +93,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb
 
+dtb-$(CONFIG_ROCKCHIP_RK3308) += \
+   rk3308-evb.dtb
+
 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-rock64.dtb
diff --git a/arch/arm/dts/rk3308-evb-u-boot.dtsi 
b/arch/arm/dts/rk3308-evb-u-boot.dtsi
new file mode 100644
index 00..c6ea746de0
--- /dev/null
+++ b/arch/arm/dts/rk3308-evb-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+#include "rk3308-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", 
+   };
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3308-evb.dts b/arch/arm/dts/rk3308-evb.dts
new file mode 100644
index 00..124a240866
--- /dev/null
+++ b/arch/arm/dts/rk3308-evb.dts
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ */
+
+/dts-v1/;
+#include 
+#include "rk3308.dtsi"
+
+/ {
+   model = "Rockchip RK3308 EVB";
+   compatible = "rockchip,rk3308-evb", "rockchip,rk3308";
+
+   chosen {
+   stdout-path = "serial4:150n8";
+   };
+
+   adc-keys0 {
+   compatible = "adc-keys";
+   io-channels = < 0>;
+   io-channel-names = "buttons";
+   poll-interval = <100>;
+   keyup-threshold-microvolt = <180>;
+
+   func-key {
+   linux,code = ;
+   label = "function";
+   press-threshold-microvolt = <18000>;
+   };
+   };
+
+   adc-keys1 {
+   compatible = "adc-keys";
+   io-channels = < 1>;
+   io-channel-names = "buttons";
+   poll-interval = <100>;
+   keyup-threshold-microvolt = <180>;
+
+   esc-key {
+   linux,code = ;
+   label = "micmute";
+   press-threshold-microvolt = <113>;
+   };
+
+   home-key {
+   linux,code = ;
+   label = "mode";
+   press-threshold-microvolt = <901000>;
+   };
+
+   menu-key {
+   linux,code = ;
+   label = "play";
+   press-threshold-microvolt = <624000>;
+   };
+
+   vol-down-key {
+   linux,code = ;
+   label = "volume down";
+   press-threshold-microvolt = <30>;
+   };
+
+   vol-up-key {
+   linux,code = ;
+   label = "volume up";
+   press-threshold-microvolt = <18000>;
+   };
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   autorepeat;
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_key>;
+
+   power {
+   gpios = < RK_PA6 GPIO_ACTIVE_LOW>;
+   linux,code = ;
+   label = "GPIO Key Power";
+   wakeup-source;
+   debounce-interval = <100>;
+   };
+   };
+
+   vcc12v_dcin: vcc12v-dcin {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc12v_dcin";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;
+   };
+
+

[U-Boot] [PATCH v3 4/9] board: rockchip: Add rk3308 evb support

2019-11-13 Thread Andy Yan

Add support for rk3308 evaluation board.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang
---

Changes in v3: None

 arch/arm/mach-rockchip/rk3308/Kconfig  |  8 +++
 board/rockchip/evb_rk3308/Kconfig  | 15 +
 board/rockchip/evb_rk3308/MAINTAINERS  |  6 ++
 board/rockchip/evb_rk3308/Makefile |  7 +++
 board/rockchip/evb_rk3308/evb_rk3308.c | 44 +++
 configs/evb-rk3308_defconfig   | 77 ++
 include/configs/evb_rk3308.h   | 20 +++
 7 files changed, 177 insertions(+)
 create mode 100644 board/rockchip/evb_rk3308/Kconfig
 create mode 100644 board/rockchip/evb_rk3308/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3308/Makefile
 create mode 100644 board/rockchip/evb_rk3308/evb_rk3308.c
 create mode 100644 configs/evb-rk3308_defconfig
 create mode 100644 include/configs/evb_rk3308.h

diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig 
b/arch/arm/mach-rockchip/rk3308/Kconfig
index 9c09661595..c74d1fc7f1 100644
--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -1,5 +1,9 @@
 if ROCKCHIP_RK3308
 
+config TARGET_EVB_RK3308
+   bool "EVB_RK3308"
+   select BOARD_LATE_INIT
+
 config SYS_SOC
default "rk3308"
 
@@ -11,4 +15,8 @@ config SPL_SERIAL_SUPPORT
 
 config ROCKCHIP_BOOT_MODE_REG
default 0xff000500
+
+
+source "board/rockchip/evb_rk3308/Kconfig"
+
 endif
diff --git a/board/rockchip/evb_rk3308/Kconfig 
b/board/rockchip/evb_rk3308/Kconfig
new file mode 100644
index 00..0074429cb6
--- /dev/null
+++ b/board/rockchip/evb_rk3308/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3308
+
+config SYS_BOARD
+   default "evb_rk3308"
+
+config SYS_VENDOR
+   default "rockchip"
+
+config SYS_CONFIG_NAME
+   default "evb_rk3308"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3308/MAINTAINERS 
b/board/rockchip/evb_rk3308/MAINTAINERS
new file mode 100644
index 00..0af119ae0a
--- /dev/null
+++ b/board/rockchip/evb_rk3308/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3308
+M:  Andy Yan 
+S:  Maintained
+F:  board/rockchip/evb_rk3308
+F:  include/configs/evb_rk3308.h
+F:  configs/evb-rk3308_defconfig
diff --git a/board/rockchip/evb_rk3308/Makefile 
b/board/rockchip/evb_rk3308/Makefile
new file mode 100644
index 00..05de5560f1
--- /dev/null
+++ b/board/rockchip/evb_rk3308/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += evb_rk3308.o
diff --git a/board/rockchip/evb_rk3308/evb_rk3308.c 
b/board/rockchip/evb_rk3308/evb_rk3308.c
new file mode 100644
index 00..180f1fe4f0
--- /dev/null
+++ b/board/rockchip/evb_rk3308/evb_rk3308.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define KEY_DOWN_MIN_VAL0
+#define KEY_DOWN_MAX_VAL30
+
+/*
+ * Two board variants whith adc channel 3 is for board id
+ * v10: 1024, v11: 512
+ * v10: adc channel 0 for dnl key
+ * v11: adc channel 1 for dnl key
+ */
+int rockchip_dnl_key_pressed(void)
+{
+   unsigned int key_val, id_val;
+   int key_ch;
+
+   if (adc_channel_single_shot("saradc", 3, _val)) {
+   printf("%s read board id failed\n", __func__);
+   return false;
+   }
+
+   if (abs(id_val - 1024) <= 30)
+   key_ch = 0;
+   else
+   key_ch = 1;
+
+   if (adc_channel_single_shot("saradc", key_ch, _val)) {
+   printf("%s read adc key val failed\n", __func__);
+   return false;
+   }
+
+   if (key_val >= KEY_DOWN_MIN_VAL && key_val <= KEY_DOWN_MAX_VAL)
+   return true;
+   else
+   return false;
+}
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
new file mode 100644
index 00..36d30dfa80
--- /dev/null
+++ b/configs/evb-rk3308_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0060
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3308=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_EVB_RK3308=y
+CONFIG_SPL_STACK_R_ADDR=0xc0
+CONFIG_DEBUG_UART_BASE=0xFF0C
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_DEBUG_UART=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set

[U-Boot] [PATCH v3 0/9] Add support for RK3308 SOC

2019-11-13 Thread Andy Yan


RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

This path set add basic support for it, test on a emmc
based evb and roc-rk3308-cc.


Changes in v3:
- Add commit message.
- rename config to roc-cc-rk3308_defconfig
- Doc update with more detail message.

Andy Yan (8):
  arm: rockchip: Add RK3308 SOC support
  arm: dts: rockchip: Add dts for rk3308 evb
  board: rockchip: Add rk3308 evb support
  rockchip: rk3308: Add sdram driver
  rockchip: mkimage: add support for RK3308
  rockchip: rk3308: Add dts for ROC-RK3308-CC
  rockchip: rk3308: Add support for ROC-RK3308-CC board
  doc: rockchip: Add documentation for rk3308 based boards

Finley Xiao (1):
  rockchip: clk: Add clk driver for rk3308

 arch/arm/dts/Makefile |4 +
 arch/arm/dts/rk3308-evb-u-boot.dtsi   |   17 +
 arch/arm/dts/rk3308-evb.dts   |  230 +++
 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi|   17 +
 arch/arm/dts/rk3308-roc-cc.dts|  190 ++
 arch/arm/dts/rk3308-u-boot.dtsi   |   25 +
 arch/arm/dts/rk3308.dtsi  | 1829 +
 arch/arm/include/asm/arch-rk3308/boot0.h  |   11 +
 arch/arm/include/asm/arch-rk3308/cru_rk3308.h |  290 +++
 arch/arm/include/asm/arch-rk3308/gpio.h   |   11 +
 arch/arm/include/asm/arch-rk3308/grf_rk3308.h |  197 ++
 arch/arm/mach-rockchip/Kconfig|   24 +
 arch/arm/mach-rockchip/Makefile   |1 +
 arch/arm/mach-rockchip/rk3308/Kconfig |   27 +
 arch/arm/mach-rockchip/rk3308/Makefile|9 +
 arch/arm/mach-rockchip/rk3308/clk_rk3308.c|   31 +
 arch/arm/mach-rockchip/rk3308/rk3308.c|  175 ++
 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c |   20 +
 board/firefly/firefly-rk3308/Kconfig  |   15 +
 board/firefly/firefly-rk3308/MAINTAINERS  |5 +
 board/firefly/firefly-rk3308/Makefile |7 +
 board/firefly/firefly-rk3308/roc_cc_rk3308.c  |   82 +
 board/rockchip/evb_rk3308/Kconfig |   15 +
 board/rockchip/evb_rk3308/MAINTAINERS |6 +
 board/rockchip/evb_rk3308/Makefile|7 +
 board/rockchip/evb_rk3308/evb_rk3308.c|   44 +
 configs/evb-rk3308_defconfig  |   77 +
 configs/roc-cc-rk3308_defconfig   |   77 +
 doc/README.rockchip   |   92 +-
 drivers/clk/rockchip/Makefile |1 +
 drivers/clk/rockchip/clk_rk3308.c | 1078 ++
 drivers/ram/rockchip/Makefile |1 +
 drivers/ram/rockchip/sdram_rk3308.c   |   55 +
 include/configs/evb_rk3308.h  |   20 +
 include/configs/firefly_rk3308.h  |   20 +
 include/configs/rk3308_common.h   |   58 +
 include/dt-bindings/clock/rk3308-cru.h|  387 
 tools/rkcommon.c  |1 +
 38 files changed, 5155 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3308-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-evb.dts
 create mode 100644 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-roc-cc.dts
 create mode 100644 arch/arm/dts/rk3308-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308.dtsi
 create mode 100644 arch/arm/include/asm/arch-rk3308/boot0.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/cru_rk3308.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/gpio.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/grf_rk3308.h
 create mode 100644 arch/arm/mach-rockchip/rk3308/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3308/clk_rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
 create mode 100644 board/firefly/firefly-rk3308/Kconfig
 create mode 100644 board/firefly/firefly-rk3308/MAINTAINERS
 create mode 100644 board/firefly/firefly-rk3308/Makefile
 create mode 100644 board/firefly/firefly-rk3308/roc_cc_rk3308.c
 create mode 100644 board/rockchip/evb_rk3308/Kconfig
 create mode 100644 board/rockchip/evb_rk3308/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3308/Makefile
 create mode 100644 board/rockchip/evb_rk3308/evb_rk3308.c
 create mode 100644 configs/evb-rk3308_defconfig
 create mode 100644 configs/roc-cc-rk3308_defconfig
 create mode 100644 drivers/clk/rockchip/clk_rk3308.c
 create mode 100644 drivers/ram/rockchip/sdram_rk3308.c
 create mode 100644 include/configs/evb_rk3308.h
 create mode 100644 include/configs/firefly_rk3308.h
 create mode 100644 include/configs/rk3308_common.h
 create mode 100644 include/dt-bindings/clock/rk3308-cru.h

-- 
2.17.1



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[U-Boot] [PATCH v3 1/9] arm: rockchip: Add RK3308 SOC support

2019-11-13 Thread Andy Yan

RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang

---

Changes in v3: None

 arch/arm/include/asm/arch-rk3308/boot0.h  |  11 +
 arch/arm/include/asm/arch-rk3308/cru_rk3308.h | 290 ++
 arch/arm/include/asm/arch-rk3308/gpio.h   |  11 +
 arch/arm/include/asm/arch-rk3308/grf_rk3308.h | 197 
 arch/arm/mach-rockchip/Kconfig|  24 ++
 arch/arm/mach-rockchip/Makefile   |   1 +
 arch/arm/mach-rockchip/rk3308/Kconfig |  14 +
 arch/arm/mach-rockchip/rk3308/Makefile|   9 +
 arch/arm/mach-rockchip/rk3308/clk_rk3308.c|  31 ++
 arch/arm/mach-rockchip/rk3308/rk3308.c| 175 +++
 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c |  20 ++
 include/configs/rk3308_common.h   |  58 
 12 files changed, 841 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rk3308/boot0.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/cru_rk3308.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/gpio.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/grf_rk3308.h
 create mode 100644 arch/arm/mach-rockchip/rk3308/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3308/clk_rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
 create mode 100644 include/configs/rk3308_common.h

diff --git a/arch/arm/include/asm/arch-rk3308/boot0.h 
b/arch/arm/include/asm/arch-rk3308/boot0.h
new file mode 100644
index 00..2e78b074ad
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3308/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include 
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h 
b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
new file mode 100644
index 00..a14b64cdb3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+ */
+#ifndef _ASM_ARCH_CRU_RK3308_H
+#define _ASM_ARCH_CRU_RK3308_H
+
+#include 
+
+#define MHz100
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ(816 * MHz)
+
+#define CORE_ACLK_HZ   40800
+#define CORE_DBG_HZ20400
+
+#define BUS_ACLK_HZ2
+#define BUS_HCLK_HZ1
+#define BUS_PCLK_HZ1
+
+#define PERI_ACLK_HZ   2
+#define PERI_HCLK_HZ   1
+#define PERI_PCLK_HZ   1
+
+#define AUDIO_HCLK_HZ  1
+#define AUDIO_PCLK_HZ  1
+
+#define RK3308_PLL_CON(x)  ((x) * 0x4)
+#define RK3308_MODE_CON0xa0
+
+/* RK3308 pll id */
+enum rk3308_pll_id {
+   APLL,
+   DPLL,
+   VPLL0,
+   VPLL1,
+   PLL_COUNT,
+};
+
+struct rk3308_clk_info {
+   unsigned long id;
+   char *name;
+};
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3308_clk_priv {
+   struct rk3308_cru *cru;
+   ulong armclk_hz;
+   ulong dpll_hz;
+   ulong vpll0_hz;
+   ulong vpll1_hz;
+};
+
+struct rk3308_cru {
+   struct rk3308_pll {
+   unsigned int con0;
+   unsigned int con1;
+   unsigned int con2;
+   unsigned int con3;
+   unsigned int con4;
+   unsigned int reserved0[3];
+   } pll[4];
+   unsigned int reserved1[8];
+   unsigned int mode;
+   unsigned int misc;
+   unsigned int reserved2[2];
+   unsigned int glb_cnt_th;
+   unsigned int glb_rst_st;
+   unsigned int glb_srst_fst;
+   unsigned int glb_srst_snd;
+   unsigned int glb_rst_con;
+   unsigned int pll_lock;
+   unsigned int reserved3[6];
+   unsigned int hwffc_con0;
+   unsigned int reserved4;
+   unsigned int hwffc_th;
+   unsigned int hwffc_intst;
+   unsigned int apll_con0_s;
+   unsigned int apll_con1_s;
+   unsigned int clksel_con0_s;
+   unsigned int reserved5;
+   unsigned int clksel_con[74];
+   unsigned int reserved6[54];
+   unsigned int clkgate_con[15];
+   unsigned int reserved7[(0x380 - 0x338) / 4 - 1];
+   unsigned int ssgtbl[32];
+   unsigned int softrst_con[10];
+   unsigned int reserved8[(0x480 - 0x424) / 4 - 1];
+   unsigned int sdmmc_con[2];
+   unsigned int sdio_con[2];
+   unsigned int emmc_con[2];
+};
+
+enum {
+   /* PLLCON0*/
+   PLL_BP_SHIFT= 15,
+   PLL_POSTDIV1_SHIFT  = 12,
+   PLL_POSTDIV1_MASK   = 7 << PLL_POSTDIV1_SHIFT,
+   PLL_FBDIV_SHIFT = 0,
+   PLL_FBDIV_MASK  =

[U-Boot] [PATCH v2 7/9] rockchip: rk3308: Add dts for ROC-RK3308-CC

2019-10-30 Thread Andy Yan

Signed-off-by: Andy Yan 
---

Changes in v2: None

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi |  17 +++
 arch/arm/dts/rk3308-roc-cc.dts | 190 +
 3 files changed, 209 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-roc-cc.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 95538b117e..1cb10b5613 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -94,7 +94,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-vyasa.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3308) += \
-   rk3308-evb.dtb
+   rk3308-evb.dtb \
+   rk3308-roc-cc.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
diff --git a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi 
b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
new file mode 100644
index 00..ffbe742053
--- /dev/null
+++ b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+#include "rk3308-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", 
+   };
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts
new file mode 100644
index 00..e10aa638a3
--- /dev/null
+++ b/arch/arm/dts/rk3308-roc-cc.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3308.dtsi"
+
+/ {
+   model = "Firefly ROC-RK3308-CC board";
+   compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308";
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   ir_rx {
+   compatible = "gpio-ir-receiver";
+   gpios = < RK_PC0 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_recv_pin>;
+   };
+
+   ir_tx {
+   compatible = "pwm-ir-tx";
+   pwms = < 0 25000 0>;
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   power {
+   label = "firefly:red:power";
+   linux,default-trigger = "ir-power-click";
+   default-state = "on";
+   gpios = < RK_PA6 GPIO_ACTIVE_HIGH>;
+   };
+
+   user {
+   label = "firefly:blue:user";
+   linux,default-trigger = "ir-user-click";
+   default-state = "off";
+   gpios = < RK_PB2 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   typec_vcc5v: typec-vcc5v {
+   compatible = "regulator-fixed";
+   regulator-name = "typec_vcc5v";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vcc5v0_sys: vcc5v0-sys {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_sys";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   vin-supply = <_vcc5v>;
+   };
+
+   vdd_core: vdd-core {
+   compatible = "pwm-regulator";
+   pwms = < 0 5000 1>;
+   regulator-name = "vdd_core";
+   regulator-min-microvolt = <827000>;
+   regulator-max-microvolt = <134>;
+   regulator-init-microvolt = <1015000>;
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-settling-time-up-us = <250>;
+   pwm-supply = <_sys>;
+   };
+
+   vdd_log: vdd-log {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_log";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <105>;
+   regulator-max-microvolt = <105>;
+   vin-supply = <_sys>;
+   };
+
+   vcc_io: vcc-io {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc_io";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator

[U-Boot] [PATCH v2 9/9] doc: rockchip: Add documentation for rk3308 based boards

2019-10-30 Thread Andy Yan

Add build documentation for rk3308 based boards.

Signed-off-by: Andy Yan 

---

Changes in v2:
- Update doc/README.rockchip

 doc/README.rockchip | 20 +++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/doc/README.rockchip b/doc/README.rockchip
index d17afeabdd..f9f5ca8ac8 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -47,6 +47,11 @@ Two RK3036 boards are supported:
- EVB RK3036 - use evb-rk3036 configuration
- Kylin - use kylin_rk3036 configuration
 
+Two RK3308 boards are supported:
+
+   - EVB RK3308 - use evb-rk3308 configuration
+   - roc-RK3308-CC - use roc-rk3308-cc configuration
+
 Two RK3328 board are supported:
 
- EVB RK3328 - use evb-rk3328_defconfig
@@ -94,7 +99,20 @@ For example:
 
 (or you can use another cross compiler if you prefer)
 
-2. To build RK3399 board:
+2. To build RK3308 board:
+   - Get the rkbin
+ => git clone https://github.com/rockchip-linux/rkbin.git
+
+   - Compile U-Boot
+ => cd /path/to/u-boot
+ => export BL31=/path/to/rkbin/bin/rk33/rk3308_bl31_v2.22.elf
+ => make roc-rk3308-cc_defconfig
+ => make CROSS_COMPILE=aarch64-linux-gnu- all
+ => make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb
+ => ./tools/mkimage -n rk3308 -T rksd -d 
/path/to/rkbin/bin/rk33/rk3308_ddr_589MHz_uart2_m0_v1.26.bin idbloader.img
+ => cat spl/u-boot-spl.bin  >> idbloader.img
+
+3. To build RK3399 board:
 
Option 1: Package the image with Rockchip miniloader:
 
-- 
2.17.1



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[U-Boot] [PATCH v2 6/9] rockchip: mkimage: add support for RK3308

2019-10-30 Thread Andy Yan

Usage:

 (1) tools/mkimage -n rk3308 -T rksd -d tpl/u-boot-tpl.bin idbloader.img
 (2) cat spl/u-boot-spl.bin >> idbloader.img
 (3) upgrade_tool wl 0x40 idbloader.img

Note:
  When use a ddr binary from rkbin as tpl, use it replace u-boot-tpl.bin in (1)

Signed-off-by: Andy Yan 
---

Changes in v2: None

 tools/rkcommon.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 831c2ad820..a16f83c1ef 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -72,6 +72,7 @@ static struct spl_info spl_infos[] = {
{ "rk3188", "RK31", 0x8000 - 0x800, true },
{ "rk322x", "RK32", 0x8000 - 0x1000, false },
{ "rk3288", "RK32", 0x8000, false },
+   { "rk3308", "RK33", 0x4 - 0x1000, false},
{ "rk3328", "RK32", 0x8000 - 0x1000, false },
{ "rk3368", "RK33", 0x8000 - 0x1000, false },
{ "rk3399", "RK33", 0x3 - 0x2000, false },
-- 
2.17.1



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[U-Boot] [PATCH v2 5/9] rockchip: rk3308: Add sdram driver

2019-10-30 Thread Andy Yan

A dm based dram driver for rk3308 u-boot
to get capacity.

Signed-off-by: Andy Yan 
---

Changes in v2: None

 drivers/ram/rockchip/Makefile   |  1 +
 drivers/ram/rockchip/sdram_rk3308.c | 55 +
 2 files changed, 56 insertions(+)
 create mode 100644 drivers/ram/rockchip/sdram_rk3308.c

diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index feb1f82d00..1adca32dcb 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -9,5 +9,6 @@ obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o
 obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o
diff --git a/drivers/ram/rockchip/sdram_rk3308.c 
b/drivers/ram/rockchip/sdram_rk3308.c
new file mode 100644
index 00..43d44cce62
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3308.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct dram_info {
+   struct ram_info info;
+   struct rk3308_grf *grf;
+};
+
+static int rk3308_dmc_probe(struct udevice *dev)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   priv->info.base = CONFIG_SYS_SDRAM_BASE;
+   priv->info.size = rockchip_sdram_size((phys_addr_t)>grf->os_reg2);
+
+   return 0;
+}
+
+static int rk3308_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   *info = priv->info;
+
+   return 0;
+}
+
+static struct ram_ops rk3308_dmc_ops = {
+   .get_info = rk3308_dmc_get_info,
+};
+
+static const struct udevice_id rk3308_dmc_ids[] = {
+   { .compatible = "rockchip,rk3308-dmc" },
+   { }
+};
+
+U_BOOT_DRIVER(dmc_rk3308) = {
+   .name = "rockchip_rk3308_dmc",
+   .id = UCLASS_RAM,
+   .of_match = rk3308_dmc_ids,
+   .ops = _dmc_ops,
+   .probe = rk3308_dmc_probe,
+   .priv_auto_alloc_size = sizeof(struct dram_info),
+};
-- 
2.17.1



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[U-Boot] [PATCH v2 8/9] rockchip: rk3308: Add support for ROC-RK3308-CC board

2019-10-30 Thread Andy Yan

Signed-off-by: Andy Yan 

---

Changes in v2:
- Add board ROC-rk3308-CC

 arch/arm/mach-rockchip/rk3308/Kconfig|  5 ++
 board/firefly/firefly-rk3308/Kconfig | 15 
 board/firefly/firefly-rk3308/MAINTAINERS |  5 ++
 board/firefly/firefly-rk3308/Makefile|  7 ++
 board/firefly/firefly-rk3308/roc_rk3308_cc.c | 82 
 configs/roc-rk3308-cc_defconfig  | 77 ++
 6 files changed, 191 insertions(+)
 create mode 100644 board/firefly/firefly-rk3308/Kconfig
 create mode 100644 board/firefly/firefly-rk3308/MAINTAINERS
 create mode 100644 board/firefly/firefly-rk3308/Makefile
 create mode 100644 board/firefly/firefly-rk3308/roc_rk3308_cc.c
 create mode 100644 configs/roc-rk3308-cc_defconfig

diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig 
b/arch/arm/mach-rockchip/rk3308/Kconfig
index c74d1fc7f1..b9fdfe2e95 100644
--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -4,6 +4,10 @@ config TARGET_EVB_RK3308
bool "EVB_RK3308"
select BOARD_LATE_INIT
 
+config TARGET_ROC_RK3308_CC
+   bool "Firefly roc-rk3308-cc"
+   select BOARD_LATE_INIT
+
 config SYS_SOC
default "rk3308"
 
@@ -18,5 +22,6 @@ config ROCKCHIP_BOOT_MODE_REG
 
 
 source "board/rockchip/evb_rk3308/Kconfig"
+source "board/firefly/firefly-rk3308/Kconfig"
 
 endif
diff --git a/board/firefly/firefly-rk3308/Kconfig 
b/board/firefly/firefly-rk3308/Kconfig
new file mode 100644
index 00..7d4d189e54
--- /dev/null
+++ b/board/firefly/firefly-rk3308/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROC_RK3308_CC
+
+config SYS_BOARD
+   default "firefly-rk3308"
+
+config SYS_VENDOR
+   default "firefly"
+
+config SYS_CONFIG_NAME
+   default "evb_rk3308"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+
+endif
diff --git a/board/firefly/firefly-rk3308/MAINTAINERS 
b/board/firefly/firefly-rk3308/MAINTAINERS
new file mode 100644
index 00..8670d8c6a8
--- /dev/null
+++ b/board/firefly/firefly-rk3308/MAINTAINERS
@@ -0,0 +1,5 @@
+ROC-RK3308-CC
+M:  Andy Yan 
+S:  Maintained
+F:  board/firefly/firefly-rk3308/roc_rk3308_cc.c
+F:  configs/roc-rk3308-cc_defconfig
diff --git a/board/firefly/firefly-rk3308/Makefile 
b/board/firefly/firefly-rk3308/Makefile
new file mode 100644
index 00..587d2e6f44
--- /dev/null
+++ b/board/firefly/firefly-rk3308/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += roc_rk3308_cc.o
diff --git a/board/firefly/firefly-rk3308/roc_rk3308_cc.c 
b/board/firefly/firefly-rk3308/roc_rk3308_cc.c
new file mode 100644
index 00..1deaa39516
--- /dev/null
+++ b/board/firefly/firefly-rk3308/roc_rk3308_cc.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#if defined(CONFIG_DEBUG_UART)
+#define GRF_BASE   0xff00
+
+enum {
+   GPIO1C7_SHIFT   = 8,
+   GPIO1C7_MASK= GENMASK(11, 8),
+   GPIO1C7_GPIO= 0,
+   GPIO1C7_UART1_RTSN,
+   GPIO1C7_UART2_TX_M0,
+   GPIO1C7_SPI2_MOSI,
+   GPIO1C7_JTAG_TMS,
+
+   GPIO1C6_SHIFT   = 4,
+   GPIO1C6_MASK= GENMASK(7, 4),
+   GPIO1C6_GPIO= 0,
+   GPIO1C6_UART1_CTSN,
+   GPIO1C6_UART2_RX_M0,
+   GPIO1C6_SPI2_MISO,
+   GPIO1C6_JTAG_TCLK,
+
+   GPIO4D3_SHIFT   = 6,
+   GPIO4D3_MASK= GENMASK(7, 6),
+   GPIO4D3_GPIO= 0,
+   GPIO4D3_SDMMC_D3,
+   GPIO4D3_UART2_TX_M1,
+
+   GPIO4D2_SHIFT   = 4,
+   GPIO4D2_MASK= GENMASK(5, 4),
+   GPIO4D2_GPIO= 0,
+   GPIO4D2_SDMMC_D2,
+   GPIO4D2_UART2_RX_M1,
+
+   UART2_IO_SEL_SHIFT  = 2,
+   UART2_IO_SEL_MASK   = GENMASK(3, 2),
+   UART2_IO_SEL_M0 = 0,
+   UART2_IO_SEL_M1,
+   UART2_IO_SEL_USB,
+};
+
+void board_debug_uart_init(void)
+{
+   static struct rk3308_grf * const grf = (void *)GRF_BASE;
+
+   /* Enable early UART2 channel m0 on the rk3308 */
+   rk_clrsetreg(>soc_con5, UART2_IO_SEL_MASK,
+UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
+   rk_clrsetreg(>gpio1ch_iomux,
+GPIO1C6_MASK | GPIO1C7_MASK,
+GPIO1C6_UART2_RX_M0 << GPIO1C6_SHIFT |
+GPIO1C7_UART2_TX_M0 << GPIO1C7_SHIFT);
+}
+#endif
+
+#define KEY_DOWN_MIN_VAL0
+#define KEY_DOWN_MAX_VAL30
+
+int rockchip_dnl_key_pressed(void)
+{
+   unsigned int val;
+
+
+   if (adc_channel_single_shot("saradc", 1, )) {
+   printf("%s read adc key val failed\n", __func__);
+   return false;
+   }
+
+   if (val >= KEY

[U-Boot] [PATCH v2 1/9] arm: rockchip: Add RK3308 SOC support

2019-10-30 Thread Andy Yan

RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

Signed-off-by: Andy Yan 

---

Changes in v2: None

 arch/arm/include/asm/arch-rk3308/boot0.h  |  11 +
 arch/arm/include/asm/arch-rk3308/cru_rk3308.h | 290 ++
 arch/arm/include/asm/arch-rk3308/gpio.h   |  11 +
 arch/arm/include/asm/arch-rk3308/grf_rk3308.h | 197 
 arch/arm/mach-rockchip/Kconfig|  24 ++
 arch/arm/mach-rockchip/Makefile   |   1 +
 arch/arm/mach-rockchip/rk3308/Kconfig |  14 +
 arch/arm/mach-rockchip/rk3308/Makefile|   9 +
 arch/arm/mach-rockchip/rk3308/clk_rk3308.c|  31 ++
 arch/arm/mach-rockchip/rk3308/rk3308.c| 175 +++
 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c |  20 ++
 include/configs/rk3308_common.h   |  58 
 12 files changed, 841 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rk3308/boot0.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/cru_rk3308.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/gpio.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/grf_rk3308.h
 create mode 100644 arch/arm/mach-rockchip/rk3308/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3308/clk_rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
 create mode 100644 include/configs/rk3308_common.h

diff --git a/arch/arm/include/asm/arch-rk3308/boot0.h 
b/arch/arm/include/asm/arch-rk3308/boot0.h
new file mode 100644
index 00..2e78b074ad
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3308/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include 
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h 
b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
new file mode 100644
index 00..a14b64cdb3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+ */
+#ifndef _ASM_ARCH_CRU_RK3308_H
+#define _ASM_ARCH_CRU_RK3308_H
+
+#include 
+
+#define MHz100
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ(816 * MHz)
+
+#define CORE_ACLK_HZ   40800
+#define CORE_DBG_HZ20400
+
+#define BUS_ACLK_HZ2
+#define BUS_HCLK_HZ1
+#define BUS_PCLK_HZ1
+
+#define PERI_ACLK_HZ   2
+#define PERI_HCLK_HZ   1
+#define PERI_PCLK_HZ   1
+
+#define AUDIO_HCLK_HZ  1
+#define AUDIO_PCLK_HZ  1
+
+#define RK3308_PLL_CON(x)  ((x) * 0x4)
+#define RK3308_MODE_CON0xa0
+
+/* RK3308 pll id */
+enum rk3308_pll_id {
+   APLL,
+   DPLL,
+   VPLL0,
+   VPLL1,
+   PLL_COUNT,
+};
+
+struct rk3308_clk_info {
+   unsigned long id;
+   char *name;
+};
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3308_clk_priv {
+   struct rk3308_cru *cru;
+   ulong armclk_hz;
+   ulong dpll_hz;
+   ulong vpll0_hz;
+   ulong vpll1_hz;
+};
+
+struct rk3308_cru {
+   struct rk3308_pll {
+   unsigned int con0;
+   unsigned int con1;
+   unsigned int con2;
+   unsigned int con3;
+   unsigned int con4;
+   unsigned int reserved0[3];
+   } pll[4];
+   unsigned int reserved1[8];
+   unsigned int mode;
+   unsigned int misc;
+   unsigned int reserved2[2];
+   unsigned int glb_cnt_th;
+   unsigned int glb_rst_st;
+   unsigned int glb_srst_fst;
+   unsigned int glb_srst_snd;
+   unsigned int glb_rst_con;
+   unsigned int pll_lock;
+   unsigned int reserved3[6];
+   unsigned int hwffc_con0;
+   unsigned int reserved4;
+   unsigned int hwffc_th;
+   unsigned int hwffc_intst;
+   unsigned int apll_con0_s;
+   unsigned int apll_con1_s;
+   unsigned int clksel_con0_s;
+   unsigned int reserved5;
+   unsigned int clksel_con[74];
+   unsigned int reserved6[54];
+   unsigned int clkgate_con[15];
+   unsigned int reserved7[(0x380 - 0x338) / 4 - 1];
+   unsigned int ssgtbl[32];
+   unsigned int softrst_con[10];
+   unsigned int reserved8[(0x480 - 0x424) / 4 - 1];
+   unsigned int sdmmc_con[2];
+   unsigned int sdio_con[2];
+   unsigned int emmc_con[2];
+};
+
+enum {
+   /* PLLCON0*/
+   PLL_BP_SHIFT= 15,
+   PLL_POSTDIV1_SHIFT  = 12,
+   PLL_POSTDIV1_MASK   = 7 << PLL_POSTDIV1_SHIFT,
+   PLL_FBDIV_SHIFT = 0,
+   PLL_FBDIV_MASK  = 0xfff,
+
+   /* P

[U-Boot] [PATCH v2 2/9] rockchip: clk: Add clk driver for rk3308

2019-10-30 Thread Andy Yan

From: Finley Xiao 

Add clk controller driver for RK3308 SOC.

Signed-off-by: Andy Yan 
---

Changes in v2: None

 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk_rk3308.c  | 1078 
 include/dt-bindings/clock/rk3308-cru.h |  387 +
 3 files changed, 1466 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk_rk3308.c
 create mode 100644 include/dt-bindings/clock/rk3308-cru.h

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 03a9fa77ba..f2068a8e94 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
diff --git a/drivers/clk/rockchip/clk_rk3308.c 
b/drivers/clk/rockchip/clk_rk3308.c
new file mode 100644
index 00..e4e213d463
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -0,0 +1,1078 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+   VCO_MAX_HZ  = 3200U * 100,
+   VCO_MIN_HZ  = 800 * 100,
+   OUTPUT_MAX_HZ   = 3200U * 100,
+   OUTPUT_MIN_HZ   = 24 * 100,
+};
+
+#define DIV_TO_RATE(input_rate, div)((input_rate) / ((div) + 1))
+
+#define RK3308_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \
+{   \
+   .rate   = _rate##U, \
+   .aclk_div = _aclk_div,  \
+   .pclk_div = _pclk_div,  \
+}
+
+static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE(13, 6, 325, 1, 1, 1, 0),
+   RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
+   RK3036_PLL_RATE(81600, 1, 68, 2, 1, 1, 0),
+   RK3036_PLL_RATE(74800, 2, 187, 3, 1, 1, 0),
+};
+
+static struct rockchip_cpu_rate_table rk3308_cpu_rates[] = {
+   RK3308_CPUCLK_RATE(12, 1, 5),
+   RK3308_CPUCLK_RATE(100800, 1, 5),
+   RK3308_CPUCLK_RATE(81600, 1, 3),
+   RK3308_CPUCLK_RATE(6, 1, 3),
+   RK3308_CPUCLK_RATE(40800, 1, 1),
+};
+
+static struct rockchip_pll_clock rk3308_pll_clks[] = {
+   [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
+RK3308_MODE_CON, 0, 10, 0, rk3308_pll_rates),
+   [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
+RK3308_MODE_CON, 2, 10, 0, NULL),
+   [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
+ RK3308_MODE_CON, 4, 10, 0, NULL),
+   [VPLL1] = PLL(pll_rk3328, PLL_VPLL1, RK3308_PLL_CON(24),
+ RK3308_MODE_CON, 6, 10, 0, NULL),
+};
+
+static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz)
+{
+   struct rk3308_cru *cru = priv->cru;
+   const struct rockchip_cpu_rate_table *rate;
+   ulong old_rate;
+
+   rate = rockchip_get_cpu_settings(rk3308_cpu_rates, hz);
+   if (!rate) {
+   printf("%s unsupport rate\n", __func__);
+   return -EINVAL;
+   }
+
+   /*
+* select apll as cpu/core clock pll source and
+* set up dependent divisors for PERI and ACLK clocks.
+* core hz : apll = 1:1
+*/
+   old_rate = rockchip_pll_get_rate(_pll_clks[APLL],
+priv->cru, APLL);
+   if (old_rate > hz) {
+   if (rockchip_pll_set_rate(_pll_clks[APLL],
+ priv->cru, APLL, hz))
+   return -EINVAL;
+   rk_clrsetreg(>clksel_con[0],
+CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
+CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
+rate->aclk_div << CORE_ACLK_DIV_SHIFT |
+rate->pclk_div << CORE_DBG_DIV_SHIFT |
+CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
+0 << CORE_DIV_CON_SHIFT);
+   } else if (old_rate < hz) {
+   rk_clrsetreg(>clksel_con[0],
+CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
+CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
+rate->aclk_div << CORE_ACLK_DIV_SHI

[U-Boot] [PATCH v2 3/9] arm: dts: rockchip: Add dts for rk3308 evb

2019-10-30 Thread Andy Yan

Add dts for rk3308 evb, sync from the linux kernel
upstream list [0].

[0]https://patchwork.kernel.org/patch/11201555/

Signed-off-by: Andy Yan 
---

Changes in v2: None

 arch/arm/dts/Makefile   |3 +
 arch/arm/dts/rk3308-evb-u-boot.dtsi |   17 +
 arch/arm/dts/rk3308-evb.dts |  230 
 arch/arm/dts/rk3308-u-boot.dtsi |   25 +
 arch/arm/dts/rk3308.dtsi| 1829 +++
 5 files changed, 2104 insertions(+)
 create mode 100644 arch/arm/dts/rk3308-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-evb.dts
 create mode 100644 arch/arm/dts/rk3308-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 11feb0c533..95538b117e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -93,6 +93,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb
 
+dtb-$(CONFIG_ROCKCHIP_RK3308) += \
+   rk3308-evb.dtb
+
 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-rock64.dtb
diff --git a/arch/arm/dts/rk3308-evb-u-boot.dtsi 
b/arch/arm/dts/rk3308-evb-u-boot.dtsi
new file mode 100644
index 00..c6ea746de0
--- /dev/null
+++ b/arch/arm/dts/rk3308-evb-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+#include "rk3308-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", 
+   };
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3308-evb.dts b/arch/arm/dts/rk3308-evb.dts
new file mode 100644
index 00..124a240866
--- /dev/null
+++ b/arch/arm/dts/rk3308-evb.dts
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ */
+
+/dts-v1/;
+#include 
+#include "rk3308.dtsi"
+
+/ {
+   model = "Rockchip RK3308 EVB";
+   compatible = "rockchip,rk3308-evb", "rockchip,rk3308";
+
+   chosen {
+   stdout-path = "serial4:150n8";
+   };
+
+   adc-keys0 {
+   compatible = "adc-keys";
+   io-channels = < 0>;
+   io-channel-names = "buttons";
+   poll-interval = <100>;
+   keyup-threshold-microvolt = <180>;
+
+   func-key {
+   linux,code = ;
+   label = "function";
+   press-threshold-microvolt = <18000>;
+   };
+   };
+
+   adc-keys1 {
+   compatible = "adc-keys";
+   io-channels = < 1>;
+   io-channel-names = "buttons";
+   poll-interval = <100>;
+   keyup-threshold-microvolt = <180>;
+
+   esc-key {
+   linux,code = ;
+   label = "micmute";
+   press-threshold-microvolt = <113>;
+   };
+
+   home-key {
+   linux,code = ;
+   label = "mode";
+   press-threshold-microvolt = <901000>;
+   };
+
+   menu-key {
+   linux,code = ;
+   label = "play";
+   press-threshold-microvolt = <624000>;
+   };
+
+   vol-down-key {
+   linux,code = ;
+   label = "volume down";
+   press-threshold-microvolt = <30>;
+   };
+
+   vol-up-key {
+   linux,code = ;
+   label = "volume up";
+   press-threshold-microvolt = <18000>;
+   };
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   autorepeat;
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_key>;
+
+   power {
+   gpios = < RK_PA6 GPIO_ACTIVE_LOW>;
+   linux,code = ;
+   label = "GPIO Key Power";
+   wakeup-source;
+   debounce-interval = <100>;
+   };
+   };
+
+   vcc12v_dcin: vcc12v-dcin {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc12v_dcin";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;
+   };
+
+   vcc5v0_sys: vcc5v0-sys {
+

[U-Boot] [PATCH v2 4/9] board: rockchip: Add rk3308 evb support

2019-10-30 Thread Andy Yan

Add support for rk3308 evaluation board.

Signed-off-by: Andy Yan 
---

Changes in v2: None

 arch/arm/mach-rockchip/rk3308/Kconfig  |  8 +++
 board/rockchip/evb_rk3308/Kconfig  | 15 +
 board/rockchip/evb_rk3308/MAINTAINERS  |  6 ++
 board/rockchip/evb_rk3308/Makefile |  7 +++
 board/rockchip/evb_rk3308/evb_rk3308.c | 44 +++
 configs/evb-rk3308_defconfig   | 77 ++
 include/configs/evb_rk3308.h   | 20 +++
 7 files changed, 177 insertions(+)
 create mode 100644 board/rockchip/evb_rk3308/Kconfig
 create mode 100644 board/rockchip/evb_rk3308/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3308/Makefile
 create mode 100644 board/rockchip/evb_rk3308/evb_rk3308.c
 create mode 100644 configs/evb-rk3308_defconfig
 create mode 100644 include/configs/evb_rk3308.h

diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig 
b/arch/arm/mach-rockchip/rk3308/Kconfig
index 9c09661595..c74d1fc7f1 100644
--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -1,5 +1,9 @@
 if ROCKCHIP_RK3308
 
+config TARGET_EVB_RK3308
+   bool "EVB_RK3308"
+   select BOARD_LATE_INIT
+
 config SYS_SOC
default "rk3308"
 
@@ -11,4 +15,8 @@ config SPL_SERIAL_SUPPORT
 
 config ROCKCHIP_BOOT_MODE_REG
default 0xff000500
+
+
+source "board/rockchip/evb_rk3308/Kconfig"
+
 endif
diff --git a/board/rockchip/evb_rk3308/Kconfig 
b/board/rockchip/evb_rk3308/Kconfig
new file mode 100644
index 00..0074429cb6
--- /dev/null
+++ b/board/rockchip/evb_rk3308/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3308
+
+config SYS_BOARD
+   default "evb_rk3308"
+
+config SYS_VENDOR
+   default "rockchip"
+
+config SYS_CONFIG_NAME
+   default "evb_rk3308"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3308/MAINTAINERS 
b/board/rockchip/evb_rk3308/MAINTAINERS
new file mode 100644
index 00..0af119ae0a
--- /dev/null
+++ b/board/rockchip/evb_rk3308/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3308
+M:  Andy Yan 
+S:  Maintained
+F:  board/rockchip/evb_rk3308
+F:  include/configs/evb_rk3308.h
+F:  configs/evb-rk3308_defconfig
diff --git a/board/rockchip/evb_rk3308/Makefile 
b/board/rockchip/evb_rk3308/Makefile
new file mode 100644
index 00..05de5560f1
--- /dev/null
+++ b/board/rockchip/evb_rk3308/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += evb_rk3308.o
diff --git a/board/rockchip/evb_rk3308/evb_rk3308.c 
b/board/rockchip/evb_rk3308/evb_rk3308.c
new file mode 100644
index 00..180f1fe4f0
--- /dev/null
+++ b/board/rockchip/evb_rk3308/evb_rk3308.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define KEY_DOWN_MIN_VAL0
+#define KEY_DOWN_MAX_VAL30
+
+/*
+ * Two board variants whith adc channel 3 is for board id
+ * v10: 1024, v11: 512
+ * v10: adc channel 0 for dnl key
+ * v11: adc channel 1 for dnl key
+ */
+int rockchip_dnl_key_pressed(void)
+{
+   unsigned int key_val, id_val;
+   int key_ch;
+
+   if (adc_channel_single_shot("saradc", 3, _val)) {
+   printf("%s read board id failed\n", __func__);
+   return false;
+   }
+
+   if (abs(id_val - 1024) <= 30)
+   key_ch = 0;
+   else
+   key_ch = 1;
+
+   if (adc_channel_single_shot("saradc", key_ch, _val)) {
+   printf("%s read adc key val failed\n", __func__);
+   return false;
+   }
+
+   if (key_val >= KEY_DOWN_MIN_VAL && key_val <= KEY_DOWN_MAX_VAL)
+   return true;
+   else
+   return false;
+}
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
new file mode 100644
index 00..36d30dfa80
--- /dev/null
+++ b/configs/evb-rk3308_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0060
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3308=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_EVB_RK3308=y
+CONFIG_SPL_STACK_R_ADDR=0xc0
+CONFIG_DEBUG_UART_BASE=0xFF0C
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_DEBUG_UART=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_C

[U-Boot] [PATCH v2 0/9] Add support for RK3308 SOC

2019-10-30 Thread Andy Yan


RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

This path set add basic support for it, test with a
emmc board.

More boards support such as Firefly ROC-RK3308-CC will coming soon.

Changes in v2:
- Add board ROC-rk3308-CC
- Update doc/README.rockchip

Andy Yan (8):
  arm: rockchip: Add RK3308 SOC support
  arm: dts: rockchip: Add dts for rk3308 evb
  board: rockchip: Add rk3308 evb support
  rockchip: rk3308: Add sdram driver
  rockchip: mkimage: add support for RK3308
  rockchip: rk3308: Add dts for ROC-RK3308-CC
  rockchip: rk3308: Add support for ROC-RK3308-CC board
  doc: rockchip: Add documentation for rk3308 based boards

Finley Xiao (1):
  rockchip: clk: Add clk driver for rk3308

 arch/arm/dts/Makefile |4 +
 arch/arm/dts/rk3308-evb-u-boot.dtsi   |   17 +
 arch/arm/dts/rk3308-evb.dts   |  230 +++
 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi|   17 +
 arch/arm/dts/rk3308-roc-cc.dts|  190 ++
 arch/arm/dts/rk3308-u-boot.dtsi   |   25 +
 arch/arm/dts/rk3308.dtsi  | 1829 +
 arch/arm/include/asm/arch-rk3308/boot0.h  |   11 +
 arch/arm/include/asm/arch-rk3308/cru_rk3308.h |  290 +++
 arch/arm/include/asm/arch-rk3308/gpio.h   |   11 +
 arch/arm/include/asm/arch-rk3308/grf_rk3308.h |  197 ++
 arch/arm/mach-rockchip/Kconfig|   24 +
 arch/arm/mach-rockchip/Makefile   |1 +
 arch/arm/mach-rockchip/rk3308/Kconfig |   27 +
 arch/arm/mach-rockchip/rk3308/Makefile|9 +
 arch/arm/mach-rockchip/rk3308/clk_rk3308.c|   31 +
 arch/arm/mach-rockchip/rk3308/rk3308.c|  175 ++
 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c |   20 +
 board/firefly/firefly-rk3308/Kconfig  |   15 +
 board/firefly/firefly-rk3308/MAINTAINERS  |5 +
 board/firefly/firefly-rk3308/Makefile |7 +
 board/firefly/firefly-rk3308/roc_rk3308_cc.c  |   82 +
 board/rockchip/evb_rk3308/Kconfig |   15 +
 board/rockchip/evb_rk3308/MAINTAINERS |6 +
 board/rockchip/evb_rk3308/Makefile|7 +
 board/rockchip/evb_rk3308/evb_rk3308.c|   44 +
 configs/evb-rk3308_defconfig  |   77 +
 configs/roc-rk3308-cc_defconfig   |   77 +
 doc/README.rockchip   |   20 +-
 drivers/clk/rockchip/Makefile |1 +
 drivers/clk/rockchip/clk_rk3308.c | 1078 ++
 drivers/ram/rockchip/Makefile |1 +
 drivers/ram/rockchip/sdram_rk3308.c   |   55 +
 include/configs/evb_rk3308.h  |   20 +
 include/configs/rk3308_common.h   |   58 +
 include/dt-bindings/clock/rk3308-cru.h|  387 
 tools/rkcommon.c  |1 +
 37 files changed, 5063 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3308-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-evb.dts
 create mode 100644 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-roc-cc.dts
 create mode 100644 arch/arm/dts/rk3308-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308.dtsi
 create mode 100644 arch/arm/include/asm/arch-rk3308/boot0.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/cru_rk3308.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/gpio.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/grf_rk3308.h
 create mode 100644 arch/arm/mach-rockchip/rk3308/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3308/clk_rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
 create mode 100644 board/firefly/firefly-rk3308/Kconfig
 create mode 100644 board/firefly/firefly-rk3308/MAINTAINERS
 create mode 100644 board/firefly/firefly-rk3308/Makefile
 create mode 100644 board/firefly/firefly-rk3308/roc_rk3308_cc.c
 create mode 100644 board/rockchip/evb_rk3308/Kconfig
 create mode 100644 board/rockchip/evb_rk3308/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3308/Makefile
 create mode 100644 board/rockchip/evb_rk3308/evb_rk3308.c
 create mode 100644 configs/evb-rk3308_defconfig
 create mode 100644 configs/roc-rk3308-cc_defconfig
 create mode 100644 drivers/clk/rockchip/clk_rk3308.c
 create mode 100644 drivers/ram/rockchip/sdram_rk3308.c
 create mode 100644 include/configs/evb_rk3308.h
 create mode 100644 include/configs/rk3308_common.h
 create mode 100644 include/dt-bindings/clock/rk3308-cru.h

-- 
2.17.1



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[U-Boot] [PATCH 6/6] rockchip: mkimage: add support for RK3308

2019-10-25 Thread Andy Yan

Usage:

 (1) tools/mkimage -n rk3308 -T rksd -d tpl/u-boot-tpl.bin idbloader.img
 (2) cat spl/u-boot-spl.bin >> idbloader.img
 (3) upgrade_tool wl 0x40 idbloader.img

Note:
  When use a ddr binary from rkbin as tpl, use it replace u-boot-tpl.bin in (1)

Signed-off-by: Andy Yan 
---

 tools/rkcommon.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 831c2ad820..a16f83c1ef 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -72,6 +72,7 @@ static struct spl_info spl_infos[] = {
{ "rk3188", "RK31", 0x8000 - 0x800, true },
{ "rk322x", "RK32", 0x8000 - 0x1000, false },
{ "rk3288", "RK32", 0x8000, false },
+   { "rk3308", "RK33", 0x4 - 0x1000, false},
{ "rk3328", "RK32", 0x8000 - 0x1000, false },
{ "rk3368", "RK33", 0x8000 - 0x1000, false },
{ "rk3399", "RK33", 0x3 - 0x2000, false },
-- 
2.17.1



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[U-Boot] [PATCH 5/6] rockchip: rk3308: Add sdram driver

2019-10-25 Thread Andy Yan

A dm based dram driver for rk3308 u-boot
to get capacity.

Signed-off-by: Andy Yan 
---

 drivers/ram/rockchip/Makefile   |  1 +
 drivers/ram/rockchip/sdram_rk3308.c | 55 +
 2 files changed, 56 insertions(+)
 create mode 100644 drivers/ram/rockchip/sdram_rk3308.c

diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index feb1f82d00..1adca32dcb 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -9,5 +9,6 @@ obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o
 obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o
diff --git a/drivers/ram/rockchip/sdram_rk3308.c 
b/drivers/ram/rockchip/sdram_rk3308.c
new file mode 100644
index 00..43d44cce62
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3308.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct dram_info {
+   struct ram_info info;
+   struct rk3308_grf *grf;
+};
+
+static int rk3308_dmc_probe(struct udevice *dev)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   priv->info.base = CONFIG_SYS_SDRAM_BASE;
+   priv->info.size = rockchip_sdram_size((phys_addr_t)>grf->os_reg2);
+
+   return 0;
+}
+
+static int rk3308_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   *info = priv->info;
+
+   return 0;
+}
+
+static struct ram_ops rk3308_dmc_ops = {
+   .get_info = rk3308_dmc_get_info,
+};
+
+static const struct udevice_id rk3308_dmc_ids[] = {
+   { .compatible = "rockchip,rk3308-dmc" },
+   { }
+};
+
+U_BOOT_DRIVER(dmc_rk3308) = {
+   .name = "rockchip_rk3308_dmc",
+   .id = UCLASS_RAM,
+   .of_match = rk3308_dmc_ids,
+   .ops = _dmc_ops,
+   .probe = rk3308_dmc_probe,
+   .priv_auto_alloc_size = sizeof(struct dram_info),
+};
-- 
2.17.1



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[U-Boot] [PATCH 4/6] board: rockchip: Add rk3308 evb support

2019-10-25 Thread Andy Yan

Add support for rk3308 evaluation board.

Signed-off-by: Andy Yan 
---

 arch/arm/mach-rockchip/rk3308/Kconfig  |  8 +++
 board/rockchip/evb_rk3308/Kconfig  | 15 +
 board/rockchip/evb_rk3308/MAINTAINERS  |  6 ++
 board/rockchip/evb_rk3308/Makefile |  7 +++
 board/rockchip/evb_rk3308/evb_rk3308.c | 44 +++
 configs/evb-rk3308_defconfig   | 77 ++
 include/configs/evb_rk3308.h   | 20 +++
 7 files changed, 177 insertions(+)
 create mode 100644 board/rockchip/evb_rk3308/Kconfig
 create mode 100644 board/rockchip/evb_rk3308/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3308/Makefile
 create mode 100644 board/rockchip/evb_rk3308/evb_rk3308.c
 create mode 100644 configs/evb-rk3308_defconfig
 create mode 100644 include/configs/evb_rk3308.h

diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig 
b/arch/arm/mach-rockchip/rk3308/Kconfig
index 9c09661595..c74d1fc7f1 100644
--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -1,5 +1,9 @@
 if ROCKCHIP_RK3308
 
+config TARGET_EVB_RK3308
+   bool "EVB_RK3308"
+   select BOARD_LATE_INIT
+
 config SYS_SOC
default "rk3308"
 
@@ -11,4 +15,8 @@ config SPL_SERIAL_SUPPORT
 
 config ROCKCHIP_BOOT_MODE_REG
default 0xff000500
+
+
+source "board/rockchip/evb_rk3308/Kconfig"
+
 endif
diff --git a/board/rockchip/evb_rk3308/Kconfig 
b/board/rockchip/evb_rk3308/Kconfig
new file mode 100644
index 00..0074429cb6
--- /dev/null
+++ b/board/rockchip/evb_rk3308/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3308
+
+config SYS_BOARD
+   default "evb_rk3308"
+
+config SYS_VENDOR
+   default "rockchip"
+
+config SYS_CONFIG_NAME
+   default "evb_rk3308"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3308/MAINTAINERS 
b/board/rockchip/evb_rk3308/MAINTAINERS
new file mode 100644
index 00..0af119ae0a
--- /dev/null
+++ b/board/rockchip/evb_rk3308/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3308
+M:  Andy Yan 
+S:  Maintained
+F:  board/rockchip/evb_rk3308
+F:  include/configs/evb_rk3308.h
+F:  configs/evb-rk3308_defconfig
diff --git a/board/rockchip/evb_rk3308/Makefile 
b/board/rockchip/evb_rk3308/Makefile
new file mode 100644
index 00..05de5560f1
--- /dev/null
+++ b/board/rockchip/evb_rk3308/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += evb_rk3308.o
diff --git a/board/rockchip/evb_rk3308/evb_rk3308.c 
b/board/rockchip/evb_rk3308/evb_rk3308.c
new file mode 100644
index 00..180f1fe4f0
--- /dev/null
+++ b/board/rockchip/evb_rk3308/evb_rk3308.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define KEY_DOWN_MIN_VAL0
+#define KEY_DOWN_MAX_VAL30
+
+/*
+ * Two board variants whith adc channel 3 is for board id
+ * v10: 1024, v11: 512
+ * v10: adc channel 0 for dnl key
+ * v11: adc channel 1 for dnl key
+ */
+int rockchip_dnl_key_pressed(void)
+{
+   unsigned int key_val, id_val;
+   int key_ch;
+
+   if (adc_channel_single_shot("saradc", 3, _val)) {
+   printf("%s read board id failed\n", __func__);
+   return false;
+   }
+
+   if (abs(id_val - 1024) <= 30)
+   key_ch = 0;
+   else
+   key_ch = 1;
+
+   if (adc_channel_single_shot("saradc", key_ch, _val)) {
+   printf("%s read adc key val failed\n", __func__);
+   return false;
+   }
+
+   if (key_val >= KEY_DOWN_MIN_VAL && key_val <= KEY_DOWN_MAX_VAL)
+   return true;
+   else
+   return false;
+}
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
new file mode 100644
index 00..36d30dfa80
--- /dev/null
+++ b/configs/evb-rk3308_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0060
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3308=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_EVB_RK3308=y
+CONFIG_SPL_STACK_R_ADDR=0xc0
+CONFIG_DEBUG_UART_BASE=0xFF0C
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_DEBUG_UART=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_M

[U-Boot] [PATCH 2/6] rockchip: clk: Add clk driver for rk3308

2019-10-25 Thread Andy Yan

From: Finley Xiao 

Add clk controller driver for RK3308 SOC.

Signed-off-by: Andy Yan 
---

 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk_rk3308.c  | 1078 
 include/dt-bindings/clock/rk3308-cru.h |  387 +
 3 files changed, 1466 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk_rk3308.c
 create mode 100644 include/dt-bindings/clock/rk3308-cru.h

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 03a9fa77ba..f2068a8e94 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
diff --git a/drivers/clk/rockchip/clk_rk3308.c 
b/drivers/clk/rockchip/clk_rk3308.c
new file mode 100644
index 00..e4e213d463
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -0,0 +1,1078 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+   VCO_MAX_HZ  = 3200U * 100,
+   VCO_MIN_HZ  = 800 * 100,
+   OUTPUT_MAX_HZ   = 3200U * 100,
+   OUTPUT_MIN_HZ   = 24 * 100,
+};
+
+#define DIV_TO_RATE(input_rate, div)((input_rate) / ((div) + 1))
+
+#define RK3308_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \
+{   \
+   .rate   = _rate##U, \
+   .aclk_div = _aclk_div,  \
+   .pclk_div = _pclk_div,  \
+}
+
+static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE(13, 6, 325, 1, 1, 1, 0),
+   RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
+   RK3036_PLL_RATE(81600, 1, 68, 2, 1, 1, 0),
+   RK3036_PLL_RATE(74800, 2, 187, 3, 1, 1, 0),
+};
+
+static struct rockchip_cpu_rate_table rk3308_cpu_rates[] = {
+   RK3308_CPUCLK_RATE(12, 1, 5),
+   RK3308_CPUCLK_RATE(100800, 1, 5),
+   RK3308_CPUCLK_RATE(81600, 1, 3),
+   RK3308_CPUCLK_RATE(6, 1, 3),
+   RK3308_CPUCLK_RATE(40800, 1, 1),
+};
+
+static struct rockchip_pll_clock rk3308_pll_clks[] = {
+   [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
+RK3308_MODE_CON, 0, 10, 0, rk3308_pll_rates),
+   [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
+RK3308_MODE_CON, 2, 10, 0, NULL),
+   [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
+ RK3308_MODE_CON, 4, 10, 0, NULL),
+   [VPLL1] = PLL(pll_rk3328, PLL_VPLL1, RK3308_PLL_CON(24),
+ RK3308_MODE_CON, 6, 10, 0, NULL),
+};
+
+static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz)
+{
+   struct rk3308_cru *cru = priv->cru;
+   const struct rockchip_cpu_rate_table *rate;
+   ulong old_rate;
+
+   rate = rockchip_get_cpu_settings(rk3308_cpu_rates, hz);
+   if (!rate) {
+   printf("%s unsupport rate\n", __func__);
+   return -EINVAL;
+   }
+
+   /*
+* select apll as cpu/core clock pll source and
+* set up dependent divisors for PERI and ACLK clocks.
+* core hz : apll = 1:1
+*/
+   old_rate = rockchip_pll_get_rate(_pll_clks[APLL],
+priv->cru, APLL);
+   if (old_rate > hz) {
+   if (rockchip_pll_set_rate(_pll_clks[APLL],
+ priv->cru, APLL, hz))
+   return -EINVAL;
+   rk_clrsetreg(>clksel_con[0],
+CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
+CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
+rate->aclk_div << CORE_ACLK_DIV_SHIFT |
+rate->pclk_div << CORE_DBG_DIV_SHIFT |
+CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
+0 << CORE_DIV_CON_SHIFT);
+   } else if (old_rate < hz) {
+   rk_clrsetreg(>clksel_con[0],
+CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
+CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
+rate->aclk_div << CORE_ACLK_DIV_SHI

[U-Boot] [PATCH 0/6] Add support for RK3308 SOC

2019-10-25 Thread Andy Yan


RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

This path set add basic support for it, test with a
emmc board.

More boards support such as Firefly ROC-RK3308-CC will coming soon.


Andy Yan (5):
  arm: rockchip: Add RK3308 SOC support
  arm: dts: rockchip: Add dts for rk3308 evb
  board: rockchip: Add rk3308 evb support
  rockchip: rk3308: Add sdram driver
  rockchip: mkimage: add support for RK3308

Finley Xiao (1):
  rockchip: clk: Add clk driver for rk3308

 arch/arm/dts/Makefile |3 +
 arch/arm/dts/rk3308-evb-u-boot.dtsi   |   17 +
 arch/arm/dts/rk3308-evb.dts   |  230 +++
 arch/arm/dts/rk3308-u-boot.dtsi   |   25 +
 arch/arm/dts/rk3308.dtsi  | 1832 +
 arch/arm/include/asm/arch-rk3308/boot0.h  |   11 +
 arch/arm/include/asm/arch-rk3308/cru_rk3308.h |  290 +++
 arch/arm/include/asm/arch-rk3308/gpio.h   |   11 +
 arch/arm/include/asm/arch-rk3308/grf_rk3308.h |  197 ++
 arch/arm/mach-rockchip/Kconfig|   24 +
 arch/arm/mach-rockchip/Makefile   |1 +
 arch/arm/mach-rockchip/rk3308/Kconfig |   22 +
 arch/arm/mach-rockchip/rk3308/Makefile|9 +
 arch/arm/mach-rockchip/rk3308/clk_rk3308.c|   31 +
 arch/arm/mach-rockchip/rk3308/rk3308.c|  175 ++
 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c |   20 +
 board/rockchip/evb_rk3308/Kconfig |   15 +
 board/rockchip/evb_rk3308/MAINTAINERS |6 +
 board/rockchip/evb_rk3308/Makefile|7 +
 board/rockchip/evb_rk3308/evb_rk3308.c|   44 +
 configs/evb-rk3308_defconfig  |   77 +
 drivers/clk/rockchip/Makefile |1 +
 drivers/clk/rockchip/clk_rk3308.c | 1078 ++
 drivers/ram/rockchip/Makefile |1 +
 drivers/ram/rockchip/sdram_rk3308.c   |   55 +
 include/configs/evb_rk3308.h  |   20 +
 include/configs/rk3308_common.h   |   58 +
 include/dt-bindings/clock/rk3308-cru.h|  387 
 tools/rkcommon.c  |1 +
 29 files changed, 4648 insertions(+)
 create mode 100644 arch/arm/dts/rk3308-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-evb.dts
 create mode 100644 arch/arm/dts/rk3308-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308.dtsi
 create mode 100644 arch/arm/include/asm/arch-rk3308/boot0.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/cru_rk3308.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/gpio.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/grf_rk3308.h
 create mode 100644 arch/arm/mach-rockchip/rk3308/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3308/clk_rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
 create mode 100644 board/rockchip/evb_rk3308/Kconfig
 create mode 100644 board/rockchip/evb_rk3308/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3308/Makefile
 create mode 100644 board/rockchip/evb_rk3308/evb_rk3308.c
 create mode 100644 configs/evb-rk3308_defconfig
 create mode 100644 drivers/clk/rockchip/clk_rk3308.c
 create mode 100644 drivers/ram/rockchip/sdram_rk3308.c
 create mode 100644 include/configs/evb_rk3308.h
 create mode 100644 include/configs/rk3308_common.h
 create mode 100644 include/dt-bindings/clock/rk3308-cru.h

-- 
2.17.1



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[U-Boot] [PATCH 3/6] arm: dts: rockchip: Add dts for rk3308 evb

2019-10-25 Thread Andy Yan

Add dts for rk3308 evb, sync from the linux kernel
upstream list [0].

[0]https://patchwork.kernel.org/patch/11201555/

Signed-off-by: Andy Yan 
---

 arch/arm/dts/Makefile   |3 +
 arch/arm/dts/rk3308-evb-u-boot.dtsi |   17 +
 arch/arm/dts/rk3308-evb.dts |  230 
 arch/arm/dts/rk3308-u-boot.dtsi |   25 +
 arch/arm/dts/rk3308.dtsi| 1832 +++
 5 files changed, 2107 insertions(+)
 create mode 100644 arch/arm/dts/rk3308-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-evb.dts
 create mode 100644 arch/arm/dts/rk3308-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 11feb0c533..95538b117e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -93,6 +93,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb
 
+dtb-$(CONFIG_ROCKCHIP_RK3308) += \
+   rk3308-evb.dtb
+
 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-rock64.dtb
diff --git a/arch/arm/dts/rk3308-evb-u-boot.dtsi 
b/arch/arm/dts/rk3308-evb-u-boot.dtsi
new file mode 100644
index 00..c6ea746de0
--- /dev/null
+++ b/arch/arm/dts/rk3308-evb-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+#include "rk3308-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", 
+   };
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3308-evb.dts b/arch/arm/dts/rk3308-evb.dts
new file mode 100644
index 00..124a240866
--- /dev/null
+++ b/arch/arm/dts/rk3308-evb.dts
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ */
+
+/dts-v1/;
+#include 
+#include "rk3308.dtsi"
+
+/ {
+   model = "Rockchip RK3308 EVB";
+   compatible = "rockchip,rk3308-evb", "rockchip,rk3308";
+
+   chosen {
+   stdout-path = "serial4:150n8";
+   };
+
+   adc-keys0 {
+   compatible = "adc-keys";
+   io-channels = < 0>;
+   io-channel-names = "buttons";
+   poll-interval = <100>;
+   keyup-threshold-microvolt = <180>;
+
+   func-key {
+   linux,code = ;
+   label = "function";
+   press-threshold-microvolt = <18000>;
+   };
+   };
+
+   adc-keys1 {
+   compatible = "adc-keys";
+   io-channels = < 1>;
+   io-channel-names = "buttons";
+   poll-interval = <100>;
+   keyup-threshold-microvolt = <180>;
+
+   esc-key {
+   linux,code = ;
+   label = "micmute";
+   press-threshold-microvolt = <113>;
+   };
+
+   home-key {
+   linux,code = ;
+   label = "mode";
+   press-threshold-microvolt = <901000>;
+   };
+
+   menu-key {
+   linux,code = ;
+   label = "play";
+   press-threshold-microvolt = <624000>;
+   };
+
+   vol-down-key {
+   linux,code = ;
+   label = "volume down";
+   press-threshold-microvolt = <30>;
+   };
+
+   vol-up-key {
+   linux,code = ;
+   label = "volume up";
+   press-threshold-microvolt = <18000>;
+   };
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   autorepeat;
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_key>;
+
+   power {
+   gpios = < RK_PA6 GPIO_ACTIVE_LOW>;
+   linux,code = ;
+   label = "GPIO Key Power";
+   wakeup-source;
+   debounce-interval = <100>;
+   };
+   };
+
+   vcc12v_dcin: vcc12v-dcin {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc12v_dcin";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;
+   };
+
+   vcc5v0_sys: vcc5v0-sys {
+

[U-Boot] [PATCH 1/6] arm: rockchip: Add RK3308 SOC support

2019-10-25 Thread Andy Yan

RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

Signed-off-by: Andy Yan 

---

 arch/arm/include/asm/arch-rk3308/boot0.h  |  11 +
 arch/arm/include/asm/arch-rk3308/cru_rk3308.h | 290 ++
 arch/arm/include/asm/arch-rk3308/gpio.h   |  11 +
 arch/arm/include/asm/arch-rk3308/grf_rk3308.h | 197 
 arch/arm/mach-rockchip/Kconfig|  24 ++
 arch/arm/mach-rockchip/Makefile   |   1 +
 arch/arm/mach-rockchip/rk3308/Kconfig |  14 +
 arch/arm/mach-rockchip/rk3308/Makefile|   9 +
 arch/arm/mach-rockchip/rk3308/clk_rk3308.c|  31 ++
 arch/arm/mach-rockchip/rk3308/rk3308.c| 175 +++
 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c |  20 ++
 include/configs/rk3308_common.h   |  58 
 12 files changed, 841 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rk3308/boot0.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/cru_rk3308.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/gpio.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/grf_rk3308.h
 create mode 100644 arch/arm/mach-rockchip/rk3308/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3308/clk_rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
 create mode 100644 include/configs/rk3308_common.h

diff --git a/arch/arm/include/asm/arch-rk3308/boot0.h 
b/arch/arm/include/asm/arch-rk3308/boot0.h
new file mode 100644
index 00..2e78b074ad
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3308/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include 
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h 
b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
new file mode 100644
index 00..a14b64cdb3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+ */
+#ifndef _ASM_ARCH_CRU_RK3308_H
+#define _ASM_ARCH_CRU_RK3308_H
+
+#include 
+
+#define MHz100
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ(816 * MHz)
+
+#define CORE_ACLK_HZ   40800
+#define CORE_DBG_HZ20400
+
+#define BUS_ACLK_HZ2
+#define BUS_HCLK_HZ1
+#define BUS_PCLK_HZ1
+
+#define PERI_ACLK_HZ   2
+#define PERI_HCLK_HZ   1
+#define PERI_PCLK_HZ   1
+
+#define AUDIO_HCLK_HZ  1
+#define AUDIO_PCLK_HZ  1
+
+#define RK3308_PLL_CON(x)  ((x) * 0x4)
+#define RK3308_MODE_CON0xa0
+
+/* RK3308 pll id */
+enum rk3308_pll_id {
+   APLL,
+   DPLL,
+   VPLL0,
+   VPLL1,
+   PLL_COUNT,
+};
+
+struct rk3308_clk_info {
+   unsigned long id;
+   char *name;
+};
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3308_clk_priv {
+   struct rk3308_cru *cru;
+   ulong armclk_hz;
+   ulong dpll_hz;
+   ulong vpll0_hz;
+   ulong vpll1_hz;
+};
+
+struct rk3308_cru {
+   struct rk3308_pll {
+   unsigned int con0;
+   unsigned int con1;
+   unsigned int con2;
+   unsigned int con3;
+   unsigned int con4;
+   unsigned int reserved0[3];
+   } pll[4];
+   unsigned int reserved1[8];
+   unsigned int mode;
+   unsigned int misc;
+   unsigned int reserved2[2];
+   unsigned int glb_cnt_th;
+   unsigned int glb_rst_st;
+   unsigned int glb_srst_fst;
+   unsigned int glb_srst_snd;
+   unsigned int glb_rst_con;
+   unsigned int pll_lock;
+   unsigned int reserved3[6];
+   unsigned int hwffc_con0;
+   unsigned int reserved4;
+   unsigned int hwffc_th;
+   unsigned int hwffc_intst;
+   unsigned int apll_con0_s;
+   unsigned int apll_con1_s;
+   unsigned int clksel_con0_s;
+   unsigned int reserved5;
+   unsigned int clksel_con[74];
+   unsigned int reserved6[54];
+   unsigned int clkgate_con[15];
+   unsigned int reserved7[(0x380 - 0x338) / 4 - 1];
+   unsigned int ssgtbl[32];
+   unsigned int softrst_con[10];
+   unsigned int reserved8[(0x480 - 0x424) / 4 - 1];
+   unsigned int sdmmc_con[2];
+   unsigned int sdio_con[2];
+   unsigned int emmc_con[2];
+};
+
+enum {
+   /* PLLCON0*/
+   PLL_BP_SHIFT= 15,
+   PLL_POSTDIV1_SHIFT  = 12,
+   PLL_POSTDIV1_MASK   = 7 << PLL_POSTDIV1_SHIFT,
+   PLL_FBDIV_SHIFT = 0,
+   PLL_FBDIV_MASK  = 0xfff,
+
+   /* P

[U-Boot] [PATCH] rockchip: rk3399: Add Leez P710 support

2019-09-21 Thread Andy Yan

From: Andy Yan 

Specification
- Rockchip RK3399
- LPDDR4
- TF sd scard slot
- eMMC
- M.2 B-Key for 4G LTE
- AP6256 for WiFi + BT
- Gigabit ethernet
- HDMI out
- 40 pin header
- USB 2.0 x 2
- USB 3.0 x 1
- USB 3.0 Type-C x 1
- TYPE-C Power supply

Signed-off-by: Andy Yan 
Signed-off-by: Andy Yan 
---

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3399-leez-p710-u-boot.dtsi |  13 +
 arch/arm/dts/rk3399-leez-p710.dts | 645 ++
 configs/leez-rk3399_defconfig |  58 ++
 4 files changed, 717 insertions(+)
 create mode 100644 arch/arm/dts/rk3399-leez-p710-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3399-leez-p710.dts
 create mode 100644 configs/leez-rk3399_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 62da168ef8..dbb062edda 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -111,6 +111,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-khadas-edge.dtb \
rk3399-khadas-edge-captain.dtb \
rk3399-khadas-edge-v.dtb \
+   rk3399-leez-p710.dtb \
rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
rk3399-nanopi-neo4.dtb \
diff --git a/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi 
b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi
new file mode 100644
index 00..f8b2a1d56e
--- /dev/null
+++ b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Andy Yan 
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", , 
+   };
+};
diff --git a/arch/arm/dts/rk3399-leez-p710.dts 
b/arch/arm/dts/rk3399-leez-p710.dts
new file mode 100644
index 00..32baa57b94
--- /dev/null
+++ b/arch/arm/dts/rk3399-leez-p710.dts
@@ -0,0 +1,645 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Andy Yan 
+ */
+
+/dts-v1/;
+#include 
+#include 
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+   model = "Leez RK3399 P710";
+   compatible = "leez,p710", "rockchip,rk3399";
+
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   clkin_gmac: external-gmac-clock {
+   compatible = "fixed-clock";
+   clock-frequency = <12500>;
+   clock-output-names = "clkin_gmac";
+   #clock-cells = <0>;
+   };
+
+   sdio_pwrseq: sdio-pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   clocks = < 1>;
+   clock-names = "ext_clock";
+   pinctrl-names = "default";
+   pinctrl-0 = <_reg_on_h>;
+   reset-gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
+   };
+
+   dc5v_adp: dc5v-adp {
+   compatible = "regulator-fixed";
+   regulator-name = "dc5v_adapter";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vcc5v0_sys: vcc5v0-sys {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   vin-supply = <_adp>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   vin-supply = <_sys>;
+   };
+
+   vcc5v0_host0: vcc5v0_host1: vcc5v0-host {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_host";
+   regulator-boot-on;
+   regulator-always-on;
+   regulator-min-microvolt = <550>;
+   regulator-max-microvolt = <550>;
+   vin-supply = <_sys>;
+   };
+
+   vcc5v0_host3: vcc5v0-host3 {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_host3";
+   enable-active-high;
+   gpio = < RK_PA2 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_host3_en>;
+   regulator-always-on;
+   vin-supply = <_sys>;
+   };
+
+   vcc3v3_lan: vcc3v3-lan {
+   compatible =

Re: [U-Boot] [PATCH v3 1/2] rockchip: make_fit_atf.py: Eliminate pyelftools dependency

2019-07-16 Thread Andy Yan


Hi Chris:

On 7/17/19 3:52 AM, Chris Webb wrote:

make_fit_aft.py depends on the non-standard library pyelftools to pull
out PT_LOAD segments from ELF files. However, this is as easy to do
manually, without imposing the extra dependency on users.

Structures in the ELF file are unpacked into variables named to exactly
match the ELF spec to ensure the destructuring code is reasonably
self-documenting.

Signed-off-by: Chris Webb 



Reviewed-by: Andy Yan 


---
  arch/arm/mach-rockchip/make_fit_atf.py | 75 +++---
  1 file changed, 32 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mach-rockchip/make_fit_atf.py 
b/arch/arm/mach-rockchip/make_fit_atf.py
index db0ae96ca8..b9a1988298 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -13,16 +13,7 @@ import os
  import sys
  import getopt
  import logging
-
-# pip install pyelftools
-from elftools.elf.elffile import ELFFile
-
-ELF_SEG_P_TYPE = 'p_type'
-ELF_SEG_P_PADDR = 'p_paddr'
-ELF_SEG_P_VADDR = 'p_vaddr'
-ELF_SEG_P_OFFSET = 'p_offset'
-ELF_SEG_P_FILESZ = 'p_filesz'
-ELF_SEG_P_MEMSZ = 'p_memsz'
+import struct
  
  DT_HEADER = """

  /*
@@ -118,33 +109,19 @@ def append_conf_node(file, dtbs, segments):
  file.write('\n')
  
  def generate_atf_fit_dts_uboot(fit_file, uboot_file_name):

-num_load_seg = 0
-p_paddr = 0x
-with open(uboot_file_name, 'rb') as uboot_file:
-uboot = ELFFile(uboot_file)
-for i in range(uboot.num_segments()):
-seg = uboot.get_segment(i)
-if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-p_paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-num_load_seg = num_load_seg + 1
-
-assert (p_paddr != 0x and num_load_seg == 1)
-
+segments = unpack_elf(uboot_file_name)
+if len(segments) != 1:
+raise ValueError("Invalid u-boot ELF image '%s'" % uboot_file_name)
+index, entry, p_paddr, data = segments[0]
  fit_file.write(DT_UBOOT % p_paddr)
  
  def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, dtbs_file_name):

-with open(bl31_file_name, 'rb') as bl31_file:
-bl31 = ELFFile(bl31_file)
-elf_entry = bl31.header['e_entry']
-segments = bl31.num_segments()
-for i in range(segments):
-seg = bl31.get_segment(i)
-if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-append_bl31_node(fit_file, i + 1, paddr, elf_entry)
+segments = unpack_elf(bl31_file_name)
+for index, entry, paddr, data in segments:
+append_bl31_node(fit_file, index + 1, paddr, entry)
  append_fdt_node(fit_file, dtbs_file_name)
  fit_file.write(DT_IMAGES_NODE_END)
-append_conf_node(fit_file, dtbs_file_name, segments)
+append_conf_node(fit_file, dtbs_file_name, len(segments))
  
  def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name):

  # Generate FIT script for ATF image.
@@ -162,17 +139,29 @@ def generate_atf_fit_dts(fit_file_name, bl31_file_name, 
uboot_file_name, dtbs_fi
  fit_file.close()
  
  def generate_atf_binary(bl31_file_name):

-with open(bl31_file_name, 'rb') as bl31_file:
-bl31 = ELFFile(bl31_file)
-
-num = bl31.num_segments()
-for i in range(num):
-seg = bl31.get_segment(i)
-if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-file_name = 'bl31_0x%08x.bin' % paddr
-with open(file_name, "wb") as atf:
-atf.write(seg.data())
+for index, entry, paddr, data in unpack_elf(bl31_file_name):
+file_name = 'bl31_0x%08x.bin' % paddr
+with open(file_name, "wb") as atf:
+atf.write(data)
+
+def unpack_elf(filename):
+with open(filename, 'rb') as file:
+elf = file.read()
+if elf[0:7] != b'\x7fELF\x02\x01\x01' or elf[18:20] != b'\xb7\x00':
+raise ValueError("Invalid arm64 ELF file '%s'" % filename)
+
+e_entry, e_phoff = struct.unpack_from('<2Q', elf, 0x18)
+e_phentsize, e_phnum = struct.unpack_from('<2H', elf, 0x36)
+segments = []
+
+for index in range(e_phnum):
+offset = e_phoff + e_phentsize * index
+p_type, p_flags, p_offset = struct.unpack_from('  
  def main():

  uboot_elf = "./u-boot"





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Re: [U-Boot] [PATCH v2 1/2] rockchip: make_fit_atf.py: Eliminate pyelftools dependency

2019-07-16 Thread Andy Yan


Hi Chris:

On 7/14/19 4:46 PM, Chris Webb wrote:

make_fit_aft.py depends on the non-standard library pyelftools to pull
out PT_LOAD segments from ELF files. However, this is as easy to do
manually, without imposing the extra dependency on users.

Structures in the ELF file are unpacked into variables named to exactly
match the ELF spec to ensure the destructuring code is reasonably
self-documenting.

Signed-off-by: Chris Webb 
---
  arch/arm/mach-rockchip/make_fit_atf.py | 75 +++---
  1 file changed, 32 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mach-rockchip/make_fit_atf.py 
b/arch/arm/mach-rockchip/make_fit_atf.py
index db0ae96ca8..9acc1edfc6 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -13,16 +13,7 @@ import os
  import sys
  import getopt
  import logging
-
-# pip install pyelftools
-from elftools.elf.elffile import ELFFile
-
-ELF_SEG_P_TYPE = 'p_type'
-ELF_SEG_P_PADDR = 'p_paddr'
-ELF_SEG_P_VADDR = 'p_vaddr'
-ELF_SEG_P_OFFSET = 'p_offset'
-ELF_SEG_P_FILESZ = 'p_filesz'
-ELF_SEG_P_MEMSZ = 'p_memsz'
+import struct
  
  DT_HEADER = """

  /*
@@ -118,33 +109,19 @@ def append_conf_node(file, dtbs, segments):
  file.write('\n')
  
  def generate_atf_fit_dts_uboot(fit_file, uboot_file_name):

-num_load_seg = 0
-p_paddr = 0x
-with open(uboot_file_name, 'rb') as uboot_file:
-uboot = ELFFile(uboot_file)
-for i in range(uboot.num_segments()):
-seg = uboot.get_segment(i)
-if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-p_paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-num_load_seg = num_load_seg + 1
-
-assert (p_paddr != 0x and num_load_seg == 1)
-
+segments = unpack_elf(uboot_file_name)
+if len(segments) != 1:
+raise ValueError("Invalid u-boot ELF image '%s'" % uboot_file_name)
+index, entry, p_paddr, data = segments[0]
  fit_file.write(DT_UBOOT % p_paddr)
  
  def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, dtbs_file_name):

-with open(bl31_file_name, 'rb') as bl31_file:
-bl31 = ELFFile(bl31_file)
-elf_entry = bl31.header['e_entry']
-segments = bl31.num_segments()
-for i in range(segments):
-seg = bl31.get_segment(i)
-if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-append_bl31_node(fit_file, i + 1, paddr, elf_entry)
+segments = unpack_elf(bl31_file_name)
+for index, entry, paddr, data in segments:
+append_bl31_node(fit_file, index + 1, paddr, entry)
  append_fdt_node(fit_file, dtbs_file_name)
  fit_file.write(DT_IMAGES_NODE_END)
-append_conf_node(fit_file, dtbs_file_name, segments)
+append_conf_node(fit_file, dtbs_file_name, len(segments))
  
  def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name):

  # Generate FIT script for ATF image.
@@ -162,17 +139,29 @@ def generate_atf_fit_dts(fit_file_name, bl31_file_name, 
uboot_file_name, dtbs_fi
  fit_file.close()
  
  def generate_atf_binary(bl31_file_name):

-with open(bl31_file_name, 'rb') as bl31_file:
-bl31 = ELFFile(bl31_file)
-
-num = bl31.num_segments()
-for i in range(num):
-seg = bl31.get_segment(i)
-if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-file_name = 'bl31_0x%08x.bin' % paddr
-with open(file_name, "wb") as atf:
-atf.write(seg.data())
+for index, entry, paddr, data in unpack_elf(bl31_file_name):
+file_name = 'bl31_0x%08x.bin' % paddr
+with open(file_name, "wb") as atf:
+atf.write(data)
+
+def unpack_elf(filename):
+with open(filename, 'rb') as file:
+elf = file.read()
+if elf[0:7] != b'\x7fELF\x02\x01\x01' or elf[18:20] != b'\xb7\x00':
+raise ValueError("Invalid arm64 ELF file '%s'" % filename)
+
+e_entry, e_phoff = struct.unpack_from('<2Q', elf, 0x18)
+e_phentsize, e_phnum = struct.unpack_from('<2H', elf, 0x36)
+segments = []
+
+for index in range(e_phnum):
+offset = e_phoff + e_phentsize*index



One small coding style issue:

offset = e_phoff + e_phentsize * index



+p_type, p_flags, p_offset = struct.unpack_from('  
  def main():

  uboot_elf = "./u-boot"





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[U-Boot] [PATCH] rockchip: dts: rk3399: Add 'same-as-spl' for Rock PI 4

2019-07-16 Thread Andy Yan

Let the board continue boot from the storage device where
it bootup.

Signed-off-by: Andy Yan 
---

 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
index 30f2b5f479..f8d8e33383 100644
--- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -6,6 +6,6 @@
 #include "rk3399-u-boot.dtsi"
 / {
chosen {
-   u-boot,spl-boot-order = , 
+   u-boot,spl-boot-order = "same-as-spl", , 
};
 };
-- 
2.17.1



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Re: [U-Boot] [PATCH] rockchip: dts: rk3399: Add spl-boot-order for Rock PI 4

2019-07-07 Thread Andy Yan

Hi Mark:

Mark Kettenis  于2019年7月4日周四 下午3:16写道：

> > From: Andy Yan 
> > Date: Thu,  4 Jul 2019 14:52:47 +0800
> >
> > RK3399 use sdhci for eMMC and DW MMC for SD Card, and
> > spl will only try to boot from SDMMC if we don't specify
> > other boot device for spl-boot-order. So add sdhci and sdmmc
> > for spl-boot-order here.
>
> Do you really not want "same-as-spl" in there as well?
>
>
same-as-spl can be added as a feather with another patch.
But this patch should be applied first as a fix, or the board can't bootup
when there is no sdcard  on board.


> > Signed-off-by: Andy Yan 
> > ---
> >
> >  arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 5 +
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
> b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
> > index 7bddc3acdb..30f2b5f479 100644
> > --- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
> > +++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
> > @@ -4,3 +4,8 @@
> >   */
> >
> >  #include "rk3399-u-boot.dtsi"
> > +/ {
> > + chosen {
> > + u-boot,spl-boot-order = , 
> > + };
> > +};
> > --
> > 2.17.1
> >
> >
> >
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Re: [U-Boot] [PATCH] rockchip: make_fit_atf.py: fix loadables property set error【请注意，邮件由mark.kette...@sibelius.xs4all.nl代发】

2019-07-07 Thread Andy Yan


Hi Christoph:

On 2019/7/7 上午1:32, Christoph Müllner wrote:

On 7/6/19 5:02 PM, Kever Yang wrote:

Hi Mark,


On 07/05/2019 08:03 PM, Mark Kettenis wrote:

From: Kever Yang
Date: Fri, 5 Jul 2019 19:38:42 +0800

Hi Christoph,


On 07/05/2019 05:15 PM, Christoph Müllner wrote:

On 04.07.19 11:44, Andy Yan wrote:

Commit b238e4b00ced ("rockchip: Cleanup of make_fit_atf.py.") set
firmware = "atf_1";
loadables = "uboot","atf_1","atf_2";

Actually it should be:
firmware = "atf_1";
loadables = "uboot","atf_2","atf_3";

Does "atf_1" not need to be among loadables as well?

The "atf_1" not need to be among loadables, or else it will be loaded twice.
The loadables suppose to be those firmware not have a entry but need to
load by SPL.

My version of the script produces:

loadables = "uboot","atf_1","atf_2","atf_3";

And with that I was able to boot mainline ATF.

The mainline ATF now have 4 segments instead of 3, I don't know why
there is a stand alone 'GNU_STACK' section, so it's able to boot there is
one extra segment help, it loads all atf_1, atf_2 and atf_3. Rockchip elf
and older mainline ATF do not have the extra 'GNU_STACK' section, and
the last atf_3 is not loaded, which lead to the ATF not able to run.
Program Headers:
   Type   Offset VirtAddr   PhysAddr
  FileSiz    MemSiz  Flags Align
   LOAD   0x 0x 0x
  0x00014058 0x00044000  RWE 1
   LOAD   0x0002 0xff3b 0xff3b
  0x1f58 0x1f58  RWE 1
   LOAD   0x0003 0xff8c 0xff8c
  0x2000 0x3000  RWE 1
   GNU_STACK  0x 0x 0x
  0x 0x  RW 10

I will apply this patch as a fix.

That GNU_STACK segment is produced by your toolchain.  It doesn't
really make sense to have it for standalone binaries like ATF, and
there is no reason to load it.  Not all toolchains produce a GNU_STACK
section.

But the make_fit_atf.py script already checks that the segment type is
PT_LOAD, so I don't understand what you're trying to fix here.  For me
things seem to work fine with mainline u-boot and ATF 2.1 on both the
rock64e and rockpro64.

Looks work fine does not means every thing is correct.

The ATF2.1 works find because of the extra GNU_STACK, but the logical
is not correct.
For mainline ATF 2.1, there are for segments, and SPL loads:
- atf_1 as firmware;
- atf_1, atf_2, atf_3 as loadables;
atf_1 load twice loads twice which is not correct.

For other ATF which not have extra GNU_STACK, eg, rockchip vendor atf at
[0],
the SPL loads:
- atf_1 as firmware;
- atf_1 and atf_2 as loadables;
atf_1 load twice and atf_3 is missing which the ATF is not able to boot.

So with this patch applied, we require the GNU_STACK section to be
present in the mainline ATF ELF?

In other words:
If I use a toolchain, which does not create the GNU_STACK section,
or if I have this information stripped away, then the Python script
does not work correctly anymore?

Is this summary correct?



No. This is the situation with your patch(b238e4b00ced): After your 
patch applied, the script won't work correctly when there is no extra 
GNU_STACK segment.


When my fix applied, the script can work well with or without the extra 
GNU_STACK segment again.



Thanks,
Christoph


This patch fix this logic.

Thanks,
- Kever
  
[0]https://github.com/rockchip-linux/rkbin/blob/master/bin/rk33/rk3399_bl31_v1.28.elf



Signed-off-by: Andy Yan
---

  arch/arm/mach-rockchip/make_fit_atf.py | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/make_fit_atf.py 
b/arch/arm/mach-rockchip/make_fit_atf.py
index 45ec105887..db0ae96ca8 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -94,7 +94,7 @@ def append_conf_section(file, cnt, dtname, segments):
  if segments != 0:
  file.write(',')
  for i in range(1, segments):
-file.write('"atf_%d"' % (i))
+file.write('"atf_%d"' % (i + 1))
  if i != (segments - 1):
  file.write(',')
  else:


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Re: [U-Boot] [PATCH v2 2/3] spl: add relocation support【请注意，邮件由s...@google.com代发】

2019-07-06 Thread Andy Yan

Hi Simon：

Simon Glass  于2019年7月7日周日 上午1:16写道：

> Hi Andy,
>
> On Mon, 24 Jun 2019 at 04:37, Andy Yan  wrote:
> >
> > Hi Simon:
> >
> > Glad to see you online again.
> >
> > On 2019/6/23 上午3:10, Simon Glass wrote:
> > > Hi Andy,
> > >
> > > On Tue, 28 May 2019 at 09:34, Andy Yan 
> wrote:
> > >> Hi Simon:
> > >>
> > >> On 2019/5/23 上午3:39, Simon Glass wrote:
> > >>
> > >> Hi Andy,
> > >>
> > >> On Tue, 21 May 2019 at 19:56, Andy Yan  wrote:
> > >>
> > >> Hi Simon:
> > >>
> > >> Simon Glass  于2019年5月22日周三 上午8:28写道：
> > >>
> > >> Hi Andy,
> > >>
> > >> On Tue, 21 May 2019 at 00:51, Andy Yan 
> wrote:
> > >>
> > >> Hi Simon:
> > >>
> > >> On 2019/5/20 下午11:35, Simon Glass wrote:
> > >>
> > >> Hi Andy,
> > >>
> > >> On Mon, 20 May 2019 at 00:34, Andy Yan 
> wrote:
> > >>
> > >> Hi Simon:
> > >>
> > >> On 2019/5/19 上午12:26, Simon Glass wrote:
> > >>
> > >> Hi Andy,
> > >>
> > >> Instead of this could you:
> > >>
> > >> - move ATF?
> > >>
> > >> All rockchip based arm64 ATF run from the start 64KB of dram as this
> > >> will give convenient for kernel manage the memory.
> > >>
> > >> On the other hand, change the ATF load address will break the
> > >> compatibility of the exiting firmware.
> > >>
> > >> - change the SPL load address so it is not in the way (since TPL can
> > >> load to any address)
> > >>
> > >> The SPL is loaded by bootrom after TPL back to bootrom, so the load
> > >> address if fixed by bootrom code.
> > >>
> > >> I think you are creating a nightmare here. If you have to do things
> > >> like this for older and smaller SoCs, OK. But it should not be used
> > >> for newer ones that can do things properly.
> > >>
> > >> Most rockchip based SOC sram is small,  even in the future soc
> roadmap,
> > >> this situation  will still exist, larger sram means more cost.
> > >>
> > >> I believe the RK3399 has 192KB. What is the minimum size in new chips?
> > >>
> > >> The sram size of RK3328 is 32KB, and now the u-boot-tpl.bin of rk3328
> without storage drive is 28KB.
> > >> The available sram size for TPL on RK3326 is 10KB,  our another A35
> based IOT SOC has the same limitation.
> > >>
> > >> OK, I see.
> > >>
> > >>
> > >> As for the current spl for rockchip soc in mainline, we use a
> workaround
> > >> by reserve large space at the head of spl(see
> > >> CONFIG_ROCKCHIP_SPL_RESERVE_IRAM ), this generate a very large spl
> binary.
> > >>
> > >> Yes.
> > >>
> > >> As for my patch, the spl relocation is disabled default, we only
> enable
> > >> it on necessary platform, so it won't hurt others .
> > >>
> > >> Well it adds more code and complexity. Perhaps it makes sense to add
> > >> this, but I want to understand the need.
> > >>
> > >> The bootrom has so many limitations that it just creates pain.
> > >>
> > >> I know we can build mmc or other storage driver into TPL so we can use
> > >> tpl load spl on some platform that sram is big enough, but there are
> > >> also many rockchip soc has very small sram, so we tend to only do dram
> > >> initialization in tpl, and let bootrom load next stage .
> > >>
> > >> See above
> > >>
> > >> For the consideration of software development, we also want to keep
> TPL
> > >> clean,  only do dram initialization(as it current status), this make
> our
> > >> internal dram team work more simple, they don't need to care about
> other
> > >> modules like mmc.
> > >>
> > >> Yes I understand this, but the boot ROM should be provided as a
> > >> library to call into:
> > >>
> > >> int mmc_read(void *addr, int start_block, int end_block)
> > >> int spi_read(void *addr, int start_block, int end_block)
> > >>
> > >> Then SPL or TPL can use it without all the strange limitations we
> have now.
> > >>
> > >> Since you probably already h

Re: [U-Boot] [PATCH] rockchip: make_fit_atf.py: fix loadables property set error

2019-07-05 Thread Andy Yan


Hi  Christoph:

On 2019/7/5 下午5:15, Christoph Müllner wrote:


On 04.07.19 11:44, Andy Yan wrote:

Commit b238e4b00ced ("rockchip: Cleanup of make_fit_atf.py.") set
firmware = "atf_1";
loadables = "uboot","atf_1","atf_2";

Actually it should be:
firmware = "atf_1";
loadables = "uboot","atf_2","atf_3";

Does "atf_1" not need to be among loadables as well?
My version of the script produces:

loadables = "uboot","atf_1","atf_2","atf_3";


Will you please provide your ble31.elf ?

The current u-boot mainline(your version) produces :

loadables = "uboot","atf_1","atf_2";

from [0]
[0]https://github.com/rockchip-linux/rkbin/blob/master/bin/rk33/rk3399_bl31_v1.28.elf



And with that I was able to boot mainline ATF.


Signed-off-by: Andy Yan 
---

  arch/arm/mach-rockchip/make_fit_atf.py | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/make_fit_atf.py 
b/arch/arm/mach-rockchip/make_fit_atf.py
index 45ec105887..db0ae96ca8 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -94,7 +94,7 @@ def append_conf_section(file, cnt, dtname, segments):
  if segments != 0:
  file.write(',')
  for i in range(1, segments):
-file.write('"atf_%d"' % (i))
+file.write('"atf_%d"' % (i + 1))
  if i != (segments - 1):
  file.write(',')
  else:







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[U-Boot] [PATCH] rockchip: make_fit_atf.py: fix loadables property set error

2019-07-04 Thread Andy Yan

Commit b238e4b00ced ("rockchip: Cleanup of make_fit_atf.py.") set
firmware = "atf_1";
loadables = "uboot","atf_1","atf_2";

Actually it should be:
firmware = "atf_1";
loadables = "uboot","atf_2","atf_3";

Signed-off-by: Andy Yan 
---

 arch/arm/mach-rockchip/make_fit_atf.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/make_fit_atf.py 
b/arch/arm/mach-rockchip/make_fit_atf.py
index 45ec105887..db0ae96ca8 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -94,7 +94,7 @@ def append_conf_section(file, cnt, dtname, segments):
 if segments != 0:
 file.write(',')
 for i in range(1, segments):
-file.write('"atf_%d"' % (i))
+file.write('"atf_%d"' % (i + 1))
 if i != (segments - 1):
 file.write(',')
 else:
-- 
2.17.1



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[U-Boot] [PATCH] rockchip: dts: rk3399: Add spl-boot-order for Rock PI 4

2019-07-04 Thread Andy Yan

RK3399 use sdhci for eMMC and DW MMC for SD Card, and
spl will only try to boot from SDMMC if we don't specify
other boot device for spl-boot-order. So add sdhci and sdmmc
for spl-boot-order here.

Signed-off-by: Andy Yan 
---

 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
index 7bddc3acdb..30f2b5f479 100644
--- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -4,3 +4,8 @@
  */
 
 #include "rk3399-u-boot.dtsi"
+/ {
+   chosen {
+   u-boot,spl-boot-order = , 
+   };
+};
-- 
2.17.1



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Re: [U-Boot] [PATCH v2 2/3] spl: add relocation support【请注意，邮件由s...@google.com代发】

2019-06-24 Thread Andy Yan


Hi Simon:

Glad to see you online again.

On 2019/6/23 上午3:10, Simon Glass wrote:

Hi Andy,

On Tue, 28 May 2019 at 09:34, Andy Yan  wrote:

Hi Simon:

On 2019/5/23 上午3:39, Simon Glass wrote:

Hi Andy,

On Tue, 21 May 2019 at 19:56, Andy Yan  wrote:

Hi Simon:

Simon Glass  于2019年5月22日周三 上午8:28写道：

Hi Andy,

On Tue, 21 May 2019 at 00:51, Andy Yan  wrote:

Hi Simon:

On 2019/5/20 下午11:35, Simon Glass wrote:

Hi Andy,

On Mon, 20 May 2019 at 00:34, Andy Yan  wrote:

Hi Simon:

On 2019/5/19 上午12:26, Simon Glass wrote:

Hi Andy,

Instead of this could you:

- move ATF?

All rockchip based arm64 ATF run from the start 64KB of dram as this
will give convenient for kernel manage the memory.

On the other hand, change the ATF load address will break the
compatibility of the exiting firmware.

- change the SPL load address so it is not in the way (since TPL can
load to any address)

The SPL is loaded by bootrom after TPL back to bootrom, so the load
address if fixed by bootrom code.

I think you are creating a nightmare here. If you have to do things
like this for older and smaller SoCs, OK. But it should not be used
for newer ones that can do things properly.

Most rockchip based SOC sram is small,  even in the future soc roadmap,
this situation  will still exist, larger sram means more cost.

I believe the RK3399 has 192KB. What is the minimum size in new chips?

The sram size of RK3328 is 32KB, and now the u-boot-tpl.bin of rk3328 without 
storage drive is 28KB.
The available sram size for TPL on RK3326 is 10KB,  our another A35 based IOT 
SOC has the same limitation.

OK, I see.


As for the current spl for rockchip soc in mainline, we use a workaround
by reserve large space at the head of spl(see
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM ), this generate a very large spl binary.

Yes.

As for my patch, the spl relocation is disabled default, we only enable
it on necessary platform, so it won't hurt others .

Well it adds more code and complexity. Perhaps it makes sense to add
this, but I want to understand the need.

The bootrom has so many limitations that it just creates pain.

I know we can build mmc or other storage driver into TPL so we can use
tpl load spl on some platform that sram is big enough, but there are
also many rockchip soc has very small sram, so we tend to only do dram
initialization in tpl, and let bootrom load next stage .

See above

For the consideration of software development, we also want to keep TPL
clean,  only do dram initialization(as it current status), this make our
internal dram team work more simple, they don't need to care about other
modules like mmc.

Yes I understand this, but the boot ROM should be provided as a
library to call into:

int mmc_read(void *addr, int start_block, int end_block)
int spi_read(void *addr, int start_block, int end_block)

Then SPL or TPL can use it without all the strange limitations we have now.

Since you probably already have these functions somewhere in the boot
ROM, you could implement this using a function table somewhere in the
ROM with a magic number before it, so that SPL can find it.

The Bootrom do much more work than directly load the spl binary. It will do 
somthing like checksum, look for the backup when the current image is invalid, 
also including security check when secure boot is enabled. This is why we did 
much work to add back_too_bootrom   mechanism in mainline in 2017.

Yes I understand that, but it is also quite inflexible, and creates
enormous problems with bootloaders.

I am not suggesting that you remove functionality. I am suggesting
that you allow bootloaders to call into some of it, to reduce the
problems caused by the inflexible bootrom.


I checked with people who write bootrom code these days,  as different chip 
written by different people from different team,  it took a bit long time to 
figure out this.

Yes , bootrom have storage access api like 
mmc_read/read_sfc_nand/read_sfc_nor/nandc_read, but bootrom does  not provide a 
fixed table for these api, and the address for these api are different on 
different chip, this means we have to list the api address chip by chip in SPL 
code. There is another thing, as the bootrom code are written by different 
person, the api interface don't keep constant: sfc_nor_read on one chip is 
sfc_nor_read(void *addr, int start, int len), but on another chip is 
sfc_nor_read(int start, void *addr, int len), this make things complicated.

Also as what I mentioned  before, the Bootrom do much more work than directly 
load the spl binary, especially in secure boot mode, but the bootrom don't want 
to export secure related api for security concern .

So this seems not a good choice to reuse bootrom api in spl.

While I understand what you are saying, I don't think it would be hard
to add a little interface layer for each SoC which supports reading
from each type of device, and knows the SoC ROM address to call, and
deals with changing args, etc.

Really, it should be a very small amount

[U-Boot] [PATCH] dm: mmc: remove unused U_BOOT_DRIVER(mmc)

2019-05-31 Thread Andy Yan

From: Andy Yan 

When look through the code, I found this bare metal
drives is not used, so remove it.

Signed-off-by: Andy Yan 
---

 drivers/mmc/mmc-uclass.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index a9c8f335c1..7e641ed5a6 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -404,10 +404,6 @@ U_BOOT_DRIVER(mmc_blk) = {
 };
 #endif /* CONFIG_BLK */
 
-U_BOOT_DRIVER(mmc) = {
-   .name   = "mmc",
-   .id = UCLASS_MMC,
-};
 
 UCLASS_DRIVER(mmc) = {
.id = UCLASS_MMC,
-- 
2.17.1



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Re: [U-Boot] [PATCH v2 2/3] spl: add relocation support【请注意，邮件由s...@google.com代发】

2019-05-28 Thread Andy Yan


Hi Simon:

On 2019/5/23 上午3:39, Simon Glass wrote:

Hi Andy,

On Tue, 21 May 2019 at 19:43, Andy Yan  wrote:

Hi Andre:

Andre Przywara  于2019年5月20日周一 下午11:59写道：


On Mon, 20 May 2019 14:34:01 +0800
Andy Yan  wrote:

Hi,


On 2019/5/19 上午12:26, Simon Glass wrote:

Hi Andy,

Instead of this could you:

- move ATF?

All rockchip based arm64 ATF run from the start 64KB of dram as this
will give convenient for kernel manage the memory.

This is just BL31 of ATF, right?
ATF recently gained PIE support for BL31 [1], so by just enabling this in
platform.mk you will get a relocatable BL31 image, with a very minimal
runtime linker. Worked out of the box on Allwinner for me, but YMMV.
So you could load newer ATF builds everywhere.



This is not the root case, actually we want put ATF as close as possible to
the start of dram, this give linux kernel convenient to manage the memory.

But instead of 64KB you could put it at 32KB or 128KB. It's still in
the first 1MB. Linux won't care, right?





Does that help you?


On the other hand, change the ATF load address will break the
compatibility of the exiting firmware.

I am not sure what you mean with "compatibility of existing firmware"?
Surely you combine all the firmware components (SPL/TPL/ATF/U-Boot proper)
into one image? And there would be no real mix and match, with older
pre-compiled builds? So by changing the ATF base address and the load
address in TPL at the same time you won't have issues?


I mean older pre-compiled builds published by rockchip rkbin [1], many
projects and popular boards directly use this , for example Armbian. How to
change the base address of the pre-build binary?
  [1] https://github.com/rockchip-linux/rkbin

Perhaps I am misunderstanding your intent here, but mainline U-Boot
should not be bound to the design decisions of old closed-source
binaries.


Indeed rockchip have submit the ATF support for rockchip platforms to 
ATF mainline. But the situation is: we see many people like  directly 
use the pre-build binary from rkbin, they are used on many popular 
boards and projects. Armbian is one of the example for this[0] , it use 
mainline u-boot, but use atf from rkbin for  some boards.


So we are really care about the compatibility.

[0]https://github.com/armbian/build/blob/master/config/sources/rockchip64.conf 
<https://github.com/armbian/build/blob/master/config/sources/rockchip64.conf>



[...]

Regards,
Simon




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Re: [U-Boot] [PATCH v2 2/3] spl: add relocation support【请注意，邮件由s...@google.com代发】

2019-05-28 Thread Andy Yan


Hi Simon:

On 2019/5/23 上午3:39, Simon Glass wrote:

Hi Andy,

On Tue, 21 May 2019 at 19:56, Andy Yan  wrote:

Hi Simon:

Simon Glass  于2019年5月22日周三 上午8:28写道：

Hi Andy,

On Tue, 21 May 2019 at 00:51, Andy Yan  wrote:

Hi Simon:

On 2019/5/20 下午11:35, Simon Glass wrote:

Hi Andy,

On Mon, 20 May 2019 at 00:34, Andy Yan  wrote:

Hi Simon:

On 2019/5/19 上午12:26, Simon Glass wrote:

Hi Andy,

Instead of this could you:

- move ATF?

All rockchip based arm64 ATF run from the start 64KB of dram as this
will give convenient for kernel manage the memory.

On the other hand, change the ATF load address will break the
compatibility of the exiting firmware.


- change the SPL load address so it is not in the way (since TPL can
load to any address)

The SPL is loaded by bootrom after TPL back to bootrom, so the load
address if fixed by bootrom code.

I think you are creating a nightmare here. If you have to do things
like this for older and smaller SoCs, OK. But it should not be used
for newer ones that can do things properly.


Most rockchip based SOC sram is small,  even in the future soc roadmap,
this situation  will still exist, larger sram means more cost.

I believe the RK3399 has 192KB. What is the minimum size in new chips?


The sram size of RK3328 is 32KB, and now the u-boot-tpl.bin of rk3328 without 
storage drive is 28KB.
The available sram size for TPL on RK3326 is 10KB,  our another A35 based IOT 
SOC has the same limitation.

OK, I see.




As for the current spl for rockchip soc in mainline, we use a workaround
by reserve large space at the head of spl(see
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM ), this generate a very large spl binary.

Yes.


As for my patch, the spl relocation is disabled default, we only enable
it on necessary platform, so it won't hurt others .

Well it adds more code and complexity. Perhaps it makes sense to add
this, but I want to understand the need.


The bootrom has so many limitations that it just creates pain.


I know we can build mmc or other storage driver into TPL so we can use
tpl load spl on some platform that sram is big enough, but there are
also many rockchip soc has very small sram, so we tend to only do dram
initialization in tpl, and let bootrom load next stage .

See above


For the consideration of software development, we also want to keep TPL
clean,  only do dram initialization(as it current status), this make our
internal dram team work more simple, they don't need to care about other
modules like mmc.

Yes I understand this, but the boot ROM should be provided as a
library to call into:

int mmc_read(void *addr, int start_block, int end_block)
int spi_read(void *addr, int start_block, int end_block)

Then SPL or TPL can use it without all the strange limitations we have now.

Since you probably already have these functions somewhere in the boot
ROM, you could implement this using a function table somewhere in the
ROM with a magic number before it, so that SPL can find it.


The Bootrom do much more work than directly load the spl binary. It will do 
somthing like checksum, look for the backup when the current image is invalid, 
also including security check when secure boot is enabled. This is why we did 
much work to add back_too_bootrom   mechanism in mainline in 2017.

Yes I understand that, but it is also quite inflexible, and creates
enormous problems with bootloaders.

I am not suggesting that you remove functionality. I am suggesting
that you allow bootloaders to call into some of it, to reduce the
problems caused by the inflexible bootrom.



I checked with people who write bootrom code these days,  as different 
chip written by different people from different team, it took a bit long 
time to figure out this.


Yes , bootrom have storage access api like 
mmc_read/read_sfc_nand/read_sfc_nor/nandc_read, but bootrom does not 
provide a fixed table for these api, and the address for these api are 
different on different chip, this means we have to list the api address 
chip by chip in SPL code. There is another thing, as the bootrom code 
are written by different person, the api interface don't keep constant: 
sfc_nor_read on one chip is sfc_nor_read(void *addr, int start, int 
len), but on another chip is sfc_nor_read(int start, void *addr, int 
len), this make things complicated.


Also as what I mentioned before, the Bootrom do much more work than 
directly load the spl binary, especially in secure boot mode, but the 
bootrom don't want to export secure related api for security concern .


So this seems not a good choice to reuse bootrom api in spl.


Regards,
Simon







- (in extremis) create a function which does a memmove() and a jump,
copy it somewhere and run it (I think x86 does this)

?

I am not very understand about this, just a memmove may not work, we
need to link the code by pie, and fix the rela.dyn sections after copy.
see arm/relocate_64.S

Well if you don't access absolute addresses (which you generally don't
in ARM) your memmove

Re: [U-Boot] [PATCH v2 2/3] spl: add relocation support【请注意，邮件由s...@google.com代发】

2019-05-21 Thread Andy Yan

Hi Simon:

Simon Glass  于2019年5月22日周三 上午8:28写道：

> Hi Andy,
>
> On Tue, 21 May 2019 at 00:51, Andy Yan  wrote:
> >
> > Hi Simon:
> >
> > On 2019/5/20 下午11:35, Simon Glass wrote:
> > > Hi Andy,
> > >
> > > On Mon, 20 May 2019 at 00:34, Andy Yan 
> wrote:
> > >> Hi Simon:
> > >>
> > >> On 2019/5/19 上午12:26, Simon Glass wrote:
> > >>> Hi Andy,
> > >>>
> > >>> Instead of this could you:
> > >>>
> > >>> - move ATF?
> > >> All rockchip based arm64 ATF run from the start 64KB of dram as this
> > >> will give convenient for kernel manage the memory.
> > >>
> > >> On the other hand, change the ATF load address will break the
> > >> compatibility of the exiting firmware.
> > >>
> > >>> - change the SPL load address so it is not in the way (since TPL can
> > >>> load to any address)
> > >> The SPL is loaded by bootrom after TPL back to bootrom, so the load
> > >> address if fixed by bootrom code.
> > > I think you are creating a nightmare here. If you have to do things
> > > like this for older and smaller SoCs, OK. But it should not be used
> > > for newer ones that can do things properly.
> >
> >
> > Most rockchip based SOC sram is small,  even in the future soc roadmap,
> > this situation  will still exist, larger sram means more cost.
>
> I believe the RK3399 has 192KB. What is the minimum size in new chips?
>

The sram size of RK3328 is 32KB, and now the u-boot-tpl.bin of rk3328
without storage drive is 28KB.
The available sram size for TPL on RK3326 is 10KB,  our another A35 based
IOT SOC has the same limitation.


>
> >
> > As for the current spl for rockchip soc in mainline, we use a workaround
> > by reserve large space at the head of spl(see
> > CONFIG_ROCKCHIP_SPL_RESERVE_IRAM ), this generate a very large spl
> binary.
>
> Yes.
>
> >
> > As for my patch, the spl relocation is disabled default, we only enable
> > it on necessary platform, so it won't hurt others .
>
> Well it adds more code and complexity. Perhaps it makes sense to add
> this, but I want to understand the need.
>
> >
> > > The bootrom has so many limitations that it just creates pain.
> > >
> > >> I know we can build mmc or other storage driver into TPL so we can use
> > >> tpl load spl on some platform that sram is big enough, but there are
> > >> also many rockchip soc has very small sram, so we tend to only do dram
> > >> initialization in tpl, and let bootrom load next stage .
> > > See above
> > >
> > For the consideration of software development, we also want to keep TPL
> > clean,  only do dram initialization(as it current status), this make our
> > internal dram team work more simple, they don't need to care about other
> > modules like mmc.
>
> Yes I understand this, but the boot ROM should be provided as a
> library to call into:
>
> int mmc_read(void *addr, int start_block, int end_block)
> int spi_read(void *addr, int start_block, int end_block)
>
> Then SPL or TPL can use it without all the strange limitations we have now.
>
> Since you probably already have these functions somewhere in the boot
> ROM, you could implement this using a function table somewhere in the
> ROM with a magic number before it, so that SPL can find it.
>

The Bootrom do much more work than directly load the spl binary. It will do
somthing like checksum, look for the backup when the current image is
invalid, also including security check when secure boot is enabled. This is
why we did much work to add back_too_bootrom   mechanism in mainline in
2017.

>
> >
> >
> > >>> - (in extremis) create a function which does a memmove() and a jump,
> > >>> copy it somewhere and run it (I think x86 does this)
> > > ?
> > I am not very understand about this, just a memmove may not work, we
> > need to link the code by pie, and fix the rela.dyn sections after copy.
> > see arm/relocate_64.S
>
> Well if you don't access absolute addresses (which you generally don't
> in ARM) your memmove() and jump code should be relocatable.
>
> Also I wonder what you think of Andre's solution?
>
>
 See my reply .

> [..]
>
> Regards
> Simon
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Re: [U-Boot] [PATCH v2 2/3] spl: add relocation support【请注意，邮件由s...@google.com代发】

2019-05-21 Thread Andy Yan

Hi Andre:

Andre Przywara  于2019年5月20日周一 下午11:59写道：

> On Mon, 20 May 2019 14:34:01 +0800
> Andy Yan  wrote:
>
> Hi,
>
> > On 2019/5/19 上午12:26, Simon Glass wrote:
> > > Hi Andy,
> > >
> > > Instead of this could you:
> > >
> > > - move ATF?
> >
> > All rockchip based arm64 ATF run from the start 64KB of dram as this
> > will give convenient for kernel manage the memory.
>
> This is just BL31 of ATF, right?
> ATF recently gained PIE support for BL31 [1], so by just enabling this in
> platform.mk you will get a relocatable BL31 image, with a very minimal
> runtime linker. Worked out of the box on Allwinner for me, but YMMV.
> So you could load newer ATF builds everywhere.
>
>
This is not the root case, actually we want put ATF as close as possible to
the start of dram, this give linux kernel convenient to manage the memory.



> Does that help you?
>
> > On the other hand, change the ATF load address will break the
> > compatibility of the exiting firmware.
>
> I am not sure what you mean with "compatibility of existing firmware"?
> Surely you combine all the firmware components (SPL/TPL/ATF/U-Boot proper)
> into one image? And there would be no real mix and match, with older
> pre-compiled builds? So by changing the ATF base address and the load
> address in TPL at the same time you won't have issues?
>

I mean older pre-compiled builds published by rockchip rkbin [1], many
projects and popular boards directly use this , for example Armbian. How to
change the base address of the pre-build binary?
 [1] https://github.com/rockchip-linux/rkbin


> Cheers,
> Andre.
>
> [1]
> https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=fc922ca87cc6af8277dc0eb710fc63a2957f0194
>
> > > - change the SPL load address so it is not in the way (since TPL can
> > > load to any address)
> >
> > The SPL is loaded by bootrom after TPL back to bootrom, so the load
> > address if fixed by bootrom code.
> >
> > I know we can build mmc or other storage driver into TPL so we can use
> > tpl load spl on some platform that sram is big enough, but there are
> > also many rockchip soc has very small sram, so we tend to only do dram
> > initialization in tpl, and let bootrom load next stage .
> >
> > > - (in extremis) create a function which does a memmove() and a jump,
> > > copy it somewhere and run it (I think x86 does this)
> > >
> > > Regards,
> > > Simon
> > >
> > > On Thu, 16 May 2019 at 06:22, Andy Yan 
> wrote:
> > >> Some times we want to relocate spl code to dram after dram
> > >> initialization or relocate spl code to a high memory to avoid
> > >> code overid.
> > >>
> > >> For example on Rockchip armv8 platform, we run with boot flow
> > >> TPL->SPL->ATF->U-Boot.
> > >> TPL run in sram and is responsible for dram initialization.
> > >> SPL run from the start address of dram and is responsible for
> > >> loading ATF and U-Boot.
> > >>
> > >> The case here is that the ATF load address is from 64KB of dram,
> > >> which overlaps with spl code itself.
> > >>
> > >> So we want to relocate spl itself to high memory to aovid this.
> > >>
> > >> Signed-off-by: Andy Yan 
> > >> ---
> > >>
> > >> Changes in v2:
> > >> - Move Kconfig modification to PATCH 1/3
> > >>
> > >>   common/spl/spl.c | 55
> 
> > >>   1 file changed, 55 insertions(+)
> > >>
> > >> diff --git a/common/spl/spl.c b/common/spl/spl.c
> > >> index 88d4b8a9bf..affb65ccbd 100644
> > >> --- a/common/spl/spl.c
> > >> +++ b/common/spl/spl.c
> > >> @@ -12,6 +12,7 @@
> > >>   #include 
> > >>   #include 
> > >>   #include 
> > >> +#include 
> > >>   #include 
> > >>   #include 
> > >>   #include 
> > >> @@ -439,6 +440,28 @@ static int spl_common_init(bool setup_malloc)
> > >>  return 0;
> > >>   }
> > >>
> > >> +#if !defined(CONFIG_SPL_SKIP_RELOCATE) && !defined(CONFIG_TPL_BUILD)
> > >> +static void spl_setup_relocate(void)
> > >> +{
> > >> +   gd->relocaddr = CONFIG_SPL_RELOC_TEXT_BASE;
> > >> +   gd->new_gd = (gd_t *)gd;
> > >> +   gd->start_addr_sp = gd->relocaddr;
> > >> +   gd->fdt_size

Re: [U-Boot] [PATCH v2 2/3] spl: add relocation support【请注意，邮件由s...@google.com代发】

2019-05-21 Thread Andy Yan


Hi Simon:

On 2019/5/20 下午11:35, Simon Glass wrote:

Hi Andy,

On Mon, 20 May 2019 at 00:34, Andy Yan  wrote:

Hi Simon:

On 2019/5/19 上午12:26, Simon Glass wrote:

Hi Andy,

Instead of this could you:

- move ATF?

All rockchip based arm64 ATF run from the start 64KB of dram as this
will give convenient for kernel manage the memory.

On the other hand, change the ATF load address will break the
compatibility of the exiting firmware.


- change the SPL load address so it is not in the way (since TPL can
load to any address)

The SPL is loaded by bootrom after TPL back to bootrom, so the load
address if fixed by bootrom code.

I think you are creating a nightmare here. If you have to do things
like this for older and smaller SoCs, OK. But it should not be used
for newer ones that can do things properly.



Most rockchip based SOC sram is small,  even in the future soc roadmap, 
this situation  will still exist, larger sram means more cost.


As for the current spl for rockchip soc in mainline, we use a workaround 
by reserve large space at the head of spl(see 
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM ), this generate a very large spl binary.


As for my patch, the spl relocation is disabled default, we only enable 
it on necessary platform, so it won't hurt others .



The bootrom has so many limitations that it just creates pain.


I know we can build mmc or other storage driver into TPL so we can use
tpl load spl on some platform that sram is big enough, but there are
also many rockchip soc has very small sram, so we tend to only do dram
initialization in tpl, and let bootrom load next stage .

See above

For the consideration of software development, we also want to keep TPL 
clean,  only do dram initialization(as it current status), this make our 
internal dram team work more simple, they don't need to care about other 
modules like mmc.




- (in extremis) create a function which does a memmove() and a jump,
copy it somewhere and run it (I think x86 does this)

?
I am not very understand about this, just a memmove may not work, we 
need to link the code by pie, and fix the rela.dyn sections after copy. 
see arm/relocate_64.S


- Simon


Regards,
Simon

On Thu, 16 May 2019 at 06:22, Andy Yan  wrote:

Some times we want to relocate spl code to dram after dram
initialization or relocate spl code to a high memory to avoid
code overid.

For example on Rockchip armv8 platform, we run with boot flow
TPL->SPL->ATF->U-Boot.
TPL run in sram and is responsible for dram initialization.
SPL run from the start address of dram and is responsible for
loading ATF and U-Boot.

The case here is that the ATF load address is from 64KB of dram,
which overlaps with spl code itself.

So we want to relocate spl itself to high memory to aovid this.

Signed-off-by: Andy Yan 
---

Changes in v2:
- Move Kconfig modification to PATCH 1/3

   common/spl/spl.c | 55 
   1 file changed, 55 insertions(+)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 88d4b8a9bf..affb65ccbd 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -12,6 +12,7 @@
   #include 
   #include 
   #include 
+#include 
   #include 
   #include 
   #include 
@@ -439,6 +440,28 @@ static int spl_common_init(bool setup_malloc)
  return 0;
   }

+#if !defined(CONFIG_SPL_SKIP_RELOCATE) && !defined(CONFIG_TPL_BUILD)
+static void spl_setup_relocate(void)
+{
+   gd->relocaddr = CONFIG_SPL_RELOC_TEXT_BASE;
+   gd->new_gd = (gd_t *)gd;
+   gd->start_addr_sp = gd->relocaddr;
+   gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
+
+   gd->start_addr_sp -= gd->fdt_size;
+   gd->new_fdt = (void *)gd->start_addr_sp;
+   memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
+   gd->fdt_blob = gd->new_fdt;
+
+   gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
+}
+#else
+static void spl_setup_relocate(void)
+{
+
+}
+#endif
+
   void spl_set_bd(void)
   {
  /*
@@ -460,6 +483,8 @@ int spl_early_init(void)
  return ret;
  gd->flags |= GD_FLG_SPL_EARLY_INIT;

+   spl_setup_relocate();
+
  return 0;
   }

@@ -563,6 +588,34 @@ static int boot_from_devices(struct spl_image_info 
*spl_image,
  return -ENODEV;
   }

+#if defined(CONFIG_DM) && !defined(CONFIG_SPL_SKIP_RELOCATE) && 
!defined(CONFIG_TPL_BUILD)
+static int spl_initr_dm(void)
+{
+   int ret;
+
+   /* Save the pre-reloc driver model and start a new one */
+   gd->dm_root_f = gd->dm_root;
+   gd->dm_root = NULL;
+   bootstage_start(BOOTSTATE_ID_ACCUM_DM_R, "dm_r");
+   ret = dm_init_and_scan(false);
+   bootstage_accum(BOOTSTATE_ID_ACCUM_DM_R);
+   if (ret)
+   return ret;
+
+#if defined(CONFIG_TIMER)
+   gd->timer = NULL;
+#endif
+   serial_init();
+
+   return 0;
+}
+#else
+static int spl_initr_d

Re: [U-Boot] [PATCH v2 2/3] spl: add relocation support【请注意，邮件由s...@google.com代发】

2019-05-20 Thread Andy Yan


Hi Simon:

On 2019/5/19 上午12:26, Simon Glass wrote:

Hi Andy,

Instead of this could you:

- move ATF?


All rockchip based arm64 ATF run from the start 64KB of dram as this 
will give convenient for kernel manage the memory.


On the other hand, change the ATF load address will break the 
compatibility of the exiting firmware.



- change the SPL load address so it is not in the way (since TPL can
load to any address)


The SPL is loaded by bootrom after TPL back to bootrom, so the load 
address if fixed by bootrom code.


I know we can build mmc or other storage driver into TPL so we can use 
tpl load spl on some platform that sram is big enough, but there are 
also many rockchip soc has very small sram, so we tend to only do dram  
initialization in tpl, and let bootrom load next stage .



- (in extremis) create a function which does a memmove() and a jump,
copy it somewhere and run it (I think x86 does this)

Regards,
Simon

On Thu, 16 May 2019 at 06:22, Andy Yan  wrote:

Some times we want to relocate spl code to dram after dram
initialization or relocate spl code to a high memory to avoid
code overid.

For example on Rockchip armv8 platform, we run with boot flow
TPL->SPL->ATF->U-Boot.
TPL run in sram and is responsible for dram initialization.
SPL run from the start address of dram and is responsible for
loading ATF and U-Boot.

The case here is that the ATF load address is from 64KB of dram,
which overlaps with spl code itself.

So we want to relocate spl itself to high memory to aovid this.

Signed-off-by: Andy Yan 
---

Changes in v2:
- Move Kconfig modification to PATCH 1/3

  common/spl/spl.c | 55 
  1 file changed, 55 insertions(+)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 88d4b8a9bf..affb65ccbd 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -12,6 +12,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -439,6 +440,28 @@ static int spl_common_init(bool setup_malloc)
 return 0;
  }

+#if !defined(CONFIG_SPL_SKIP_RELOCATE) && !defined(CONFIG_TPL_BUILD)
+static void spl_setup_relocate(void)
+{
+   gd->relocaddr = CONFIG_SPL_RELOC_TEXT_BASE;
+   gd->new_gd = (gd_t *)gd;
+   gd->start_addr_sp = gd->relocaddr;
+   gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
+
+   gd->start_addr_sp -= gd->fdt_size;
+   gd->new_fdt = (void *)gd->start_addr_sp;
+   memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
+   gd->fdt_blob = gd->new_fdt;
+
+   gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
+}
+#else
+static void spl_setup_relocate(void)
+{
+
+}
+#endif
+
  void spl_set_bd(void)
  {
 /*
@@ -460,6 +483,8 @@ int spl_early_init(void)
 return ret;
 gd->flags |= GD_FLG_SPL_EARLY_INIT;

+   spl_setup_relocate();
+
 return 0;
  }

@@ -563,6 +588,34 @@ static int boot_from_devices(struct spl_image_info 
*spl_image,
 return -ENODEV;
  }

+#if defined(CONFIG_DM) && !defined(CONFIG_SPL_SKIP_RELOCATE) && 
!defined(CONFIG_TPL_BUILD)
+static int spl_initr_dm(void)
+{
+   int ret;
+
+   /* Save the pre-reloc driver model and start a new one */
+   gd->dm_root_f = gd->dm_root;
+   gd->dm_root = NULL;
+   bootstage_start(BOOTSTATE_ID_ACCUM_DM_R, "dm_r");
+   ret = dm_init_and_scan(false);
+   bootstage_accum(BOOTSTATE_ID_ACCUM_DM_R);
+   if (ret)
+   return ret;
+
+#if defined(CONFIG_TIMER)
+   gd->timer = NULL;
+#endif
+   serial_init();
+
+   return 0;
+}
+#else
+static int spl_initr_dm(void)
+{
+   return 0;
+}
+#endif
+
  void board_init_r(gd_t *dummy1, ulong dummy2)
  {
 u32 spl_boot_list[] = {
@@ -577,6 +630,8 @@ void board_init_r(gd_t *dummy1, ulong dummy2)

 debug(">>" SPL_TPL_PROMPT "board_init_r()\n");

+   spl_initr_dm();
+
 spl_set_bd();

  #if defined(CONFIG_SYS_SPL_MALLOC_START)
--
2.17.1









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Re: [U-Boot] [PATCH v2 2/3] spl: add relocation support

2019-05-17 Thread Andy Yan


Hi Lukasz:

On 2019/5/17 下午4:34, Lukasz Majewski wrote:

On Thu, 16 May 2019 20:21:50 +0800
Andy Yan  wrote:


Some times we want to relocate spl code to dram after dram
initialization or relocate spl code to a high memory to avoid
code overid.

For example on Rockchip armv8 platform, we run with boot flow
TPL->SPL->ATF->U-Boot.
TPL run in sram and is responsible for dram initialization.
SPL run from the start address of dram and is responsible for
loading ATF and U-Boot.

The case here is that the ATF load address is from 64KB of dram,
which overlaps with spl code itself.

So we want to relocate spl itself to high memory to aovid this.

Signed-off-by: Andy Yan 
---

Changes in v2:
- Move Kconfig modification to PATCH 1/3

  common/spl/spl.c | 55
 1 file changed, 55
insertions(+)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 88d4b8a9bf..affb65ccbd 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -12,6 +12,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -439,6 +440,28 @@ static int spl_common_init(bool setup_malloc)
return 0;
  }
  
+#if !defined(CONFIG_SPL_SKIP_RELOCATE) && !defined(CONFIG_TPL_BUILD)

+static void spl_setup_relocate(void)
+{
+   gd->relocaddr = CONFIG_SPL_RELOC_TEXT_BASE;
+   gd->new_gd = (gd_t *)gd;
+   gd->start_addr_sp = gd->relocaddr;
+   gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000,
32); +

What is the purpose of 0x1000 magic number? Could it be described in
some way (in-code comment, #define, etc) ?


This code is copied from board_f.c,  I think is to aligned to 4KB here.



+   gd->start_addr_sp -= gd->fdt_size;
+   gd->new_fdt = (void *)gd->start_addr_sp;
+   memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
+   gd->fdt_blob = gd->new_fdt;
+
+   gd->reloc_off = gd->relocaddr - (unsigned
long)__image_copy_start; +}
+#else
+static void spl_setup_relocate(void)
+{
+
+}
+#endif
+
  void spl_set_bd(void)
  {
/*
@@ -460,6 +483,8 @@ int spl_early_init(void)
return ret;
gd->flags |= GD_FLG_SPL_EARLY_INIT;
  
+	spl_setup_relocate();

+
return 0;
  }
  
@@ -563,6 +588,34 @@ static int boot_from_devices(struct

spl_image_info *spl_image, return -ENODEV;
  }
  
+#if defined(CONFIG_DM) && !defined(CONFIG_SPL_SKIP_RELOCATE)

&& !defined(CONFIG_TPL_BUILD) +static int spl_initr_dm(void)
+{
+   int ret;
+
+   /* Save the pre-reloc driver model and start a new one */
+   gd->dm_root_f = gd->dm_root;
+   gd->dm_root = NULL;
+   bootstage_start(BOOTSTATE_ID_ACCUM_DM_R, "dm_r");
+   ret = dm_init_and_scan(false);
+   bootstage_accum(BOOTSTATE_ID_ACCUM_DM_R);
+   if (ret)
+   return ret;
+
+#if defined(CONFIG_TIMER)
+   gd->timer = NULL;
+#endif
+   serial_init();
+
+   return 0;
+}
+#else
+static int spl_initr_dm(void)
+{
+   return 0;
+}
+#endif
+
  void board_init_r(gd_t *dummy1, ulong dummy2)
  {
u32 spl_boot_list[] = {
@@ -577,6 +630,8 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
  
  	debug(">>" SPL_TPL_PROMPT "board_init_r()\n");
  
+	spl_initr_dm();

+
spl_set_bd();
  
  #if defined(CONFIG_SYS_SPL_MALLOC_START)




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de



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[U-Boot] [PATCH v2 3/3] arm: add spl relocation support for arm

2019-05-16 Thread Andy Yan

Some times we want to relocate spl code to dram after dram
initialization or relocate spl code to a high memory to avoid
code overid.

For example on Rockchip armv8 platform, we run with boot flow
TPL->SPL->ATF->U-Boot.
TPL run in sram and is responsible for dram initialization.
SPL run from the start address of dram and is responsible for
loading ATF and U-Boot.

The case here is that the ATF load address is from 64KB of dram,
which overlaps with spl code itself.

So we want to relocate spl itself to high memory to aovid this.

Signed-off-by: Andy Yan 
---

Changes in v2:
- Add more detial commit message

 arch/arm/config.mk|  6 ++
 arch/arm/cpu/armv8/start.S|  4 
 arch/arm/cpu/armv8/u-boot-spl.lds | 17 +
 arch/arm/lib/Makefile |  2 +-
 arch/arm/lib/crt0_64.S|  3 ++-
 5 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index f25603109e..7f6ad89601 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -102,6 +102,12 @@ endif
 # needed for relocation
 LDFLAGS_u-boot += -pie
 
+ifndef CONFIG_SPL_SKIP_RELOCATE
+LDFLAGS_u-boot-spl = -pie
+else
+SPL_LDFLAGS_u-boot-spl =
+endif
+
 #
 # FIXME: binutils versions < 2.22 have a bug in the assembler where
 # branches to weak symbols can be incorrectly optimized in thumb mode
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index fe52166e28..a7dad3cd69 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -35,7 +35,11 @@ _start:
 
 .globl _TEXT_BASE
 _TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD)
+   .quad   CONFIG_SPL_TEXT_BASE
+#else
.quad   CONFIG_SYS_TEXT_BASE
+#endif
 
 /*
  * These are defined in the linker script.
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds 
b/arch/arm/cpu/armv8/u-boot-spl.lds
index ccbf359bd1..64102afc8b 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -53,6 +53,23 @@ SECTIONS
*(.__end)
} >.sram
 
+#ifndef CONFIG_SPL_SKIP_RELOCATE
+   . = ALIGN(8);
+
+   .rel_dyn_start :
+   {
+   *(.__rel_dyn_start)
+   } >.sram
+
+   .rela.dyn : {
+   *(.rela*)
+   } >.sram
+
+   .rel_dyn_end :
+   {
+   *(.__rel_dyn_end)
+   } >.sram
+#endif
_image_binary_end = .;
 
.bss_start (NOLOAD) : {
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 48ee6c3c60..f27b3fb79f 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -21,7 +21,7 @@ else
 obj-y   += setjmp.o
 endif
 
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_ARM64
 obj-y  += relocate_64.o
 else
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index d6b632aa87..e5605fe325 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -89,7 +89,8 @@ ENTRY(_main)
mov x0, #0
bl  board_init_f
 
-#if !defined(CONFIG_SPL_BUILD)
+#if (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) && 
!defined(CONFIG_SPL_SKIP_RELOCATE)) || \
+   !defined(CONFIG_SPL_BUILD)
 /*
  * Set up intermediate environment (new sp and gd) and call
  * relocate_code(addr_moni). Trick here is that we'll return
-- 
2.17.1



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[U-Boot] [PATCH v2 2/3] spl: add relocation support

2019-05-16 Thread Andy Yan

Some times we want to relocate spl code to dram after dram
initialization or relocate spl code to a high memory to avoid
code overid.

For example on Rockchip armv8 platform, we run with boot flow
TPL->SPL->ATF->U-Boot.
TPL run in sram and is responsible for dram initialization.
SPL run from the start address of dram and is responsible for
loading ATF and U-Boot.

The case here is that the ATF load address is from 64KB of dram,
which overlaps with spl code itself.

So we want to relocate spl itself to high memory to aovid this.

Signed-off-by: Andy Yan 
---

Changes in v2:
- Move Kconfig modification to PATCH 1/3

 common/spl/spl.c | 55 
 1 file changed, 55 insertions(+)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 88d4b8a9bf..affb65ccbd 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -439,6 +440,28 @@ static int spl_common_init(bool setup_malloc)
return 0;
 }
 
+#if !defined(CONFIG_SPL_SKIP_RELOCATE) && !defined(CONFIG_TPL_BUILD)
+static void spl_setup_relocate(void)
+{
+   gd->relocaddr = CONFIG_SPL_RELOC_TEXT_BASE;
+   gd->new_gd = (gd_t *)gd;
+   gd->start_addr_sp = gd->relocaddr;
+   gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
+
+   gd->start_addr_sp -= gd->fdt_size;
+   gd->new_fdt = (void *)gd->start_addr_sp;
+   memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
+   gd->fdt_blob = gd->new_fdt;
+
+   gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
+}
+#else
+static void spl_setup_relocate(void)
+{
+
+}
+#endif
+
 void spl_set_bd(void)
 {
/*
@@ -460,6 +483,8 @@ int spl_early_init(void)
return ret;
gd->flags |= GD_FLG_SPL_EARLY_INIT;
 
+   spl_setup_relocate();
+
return 0;
 }
 
@@ -563,6 +588,34 @@ static int boot_from_devices(struct spl_image_info 
*spl_image,
return -ENODEV;
 }
 
+#if defined(CONFIG_DM) && !defined(CONFIG_SPL_SKIP_RELOCATE) && 
!defined(CONFIG_TPL_BUILD)
+static int spl_initr_dm(void)
+{
+   int ret;
+
+   /* Save the pre-reloc driver model and start a new one */
+   gd->dm_root_f = gd->dm_root;
+   gd->dm_root = NULL;
+   bootstage_start(BOOTSTATE_ID_ACCUM_DM_R, "dm_r");
+   ret = dm_init_and_scan(false);
+   bootstage_accum(BOOTSTATE_ID_ACCUM_DM_R);
+   if (ret)
+   return ret;
+
+#if defined(CONFIG_TIMER)
+   gd->timer = NULL;
+#endif
+   serial_init();
+
+   return 0;
+}
+#else
+static int spl_initr_dm(void)
+{
+   return 0;
+}
+#endif
+
 void board_init_r(gd_t *dummy1, ulong dummy2)
 {
u32 spl_boot_list[] = {
@@ -577,6 +630,8 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 
debug(">>" SPL_TPL_PROMPT "board_init_r()\n");
 
+   spl_initr_dm();
+
spl_set_bd();
 
 #if defined(CONFIG_SYS_SPL_MALLOC_START)
-- 
2.17.1



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[U-Boot] [PATCH v2 1/3] powerpc: Convert CONFIG_SPL_RELOC_TEXT_BASE to Kconfig

2019-05-16 Thread Andy Yan

Move CONFIG_SPL_RELOC_TEXT_BASE and CONFIG_SPL_SKIP_RELOCATE
to Kconfig, so we can reuse it for cross other platform.

Signed-off-by: Andy Yan 
---

Changes in v2: None

 common/spl/Kconfig   | 13 +
 configs/BSC9131RDB_NAND_SYSCLK100_defconfig  |  2 ++
 configs/BSC9131RDB_NAND_defconfig|  2 ++
 configs/BSC9132QDS_NAND_DDRCLK100_defconfig  |  2 ++
 configs/BSC9132QDS_NAND_DDRCLK133_defconfig  |  2 ++
 configs/C29XPCIE_NAND_defconfig  |  2 ++
 configs/P1010RDB-PA_36BIT_NAND_defconfig |  2 ++
 configs/P1010RDB-PA_36BIT_SDCARD_defconfig   |  2 ++
 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig |  2 ++
 configs/P1010RDB-PA_NAND_defconfig   |  2 ++
 configs/P1010RDB-PA_SDCARD_defconfig |  2 ++
 configs/P1010RDB-PA_SPIFLASH_defconfig   |  2 ++
 configs/P1010RDB-PB_36BIT_NAND_defconfig |  2 ++
 configs/P1010RDB-PB_36BIT_SDCARD_defconfig   |  2 ++
 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig |  2 ++
 configs/P1010RDB-PB_NAND_defconfig   |  2 ++
 configs/P1010RDB-PB_SDCARD_defconfig |  2 ++
 configs/P1010RDB-PB_SPIFLASH_defconfig   |  2 ++
 configs/P1020MBG-PC_36BIT_SDCARD_defconfig   |  2 ++
 configs/P1020MBG-PC_SDCARD_defconfig |  2 ++
 configs/P1020RDB-PC_36BIT_NAND_defconfig |  2 ++
 configs/P1020RDB-PC_36BIT_SDCARD_defconfig   |  2 ++
 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig |  2 ++
 configs/P1020RDB-PC_NAND_defconfig   |  2 ++
 configs/P1020RDB-PC_SDCARD_defconfig |  2 ++
 configs/P1020RDB-PC_SPIFLASH_defconfig   |  2 ++
 configs/P1020RDB-PD_NAND_defconfig   |  2 ++
 configs/P1020RDB-PD_SDCARD_defconfig |  2 ++
 configs/P1020RDB-PD_SPIFLASH_defconfig   |  2 ++
 configs/P1020UTM-PC_36BIT_SDCARD_defconfig   |  2 ++
 configs/P1020UTM-PC_SDCARD_defconfig |  2 ++
 configs/P1021RDB-PC_36BIT_NAND_defconfig |  2 ++
 configs/P1021RDB-PC_36BIT_SDCARD_defconfig   |  2 ++
 configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig |  2 ++
 configs/P1021RDB-PC_NAND_defconfig   |  2 ++
 configs/P1021RDB-PC_SDCARD_defconfig |  2 ++
 configs/P1021RDB-PC_SPIFLASH_defconfig   |  2 ++
 configs/P1022DS_36BIT_NAND_defconfig |  2 ++
 configs/P1022DS_36BIT_SDCARD_defconfig   |  2 ++
 configs/P1022DS_36BIT_SPIFLASH_defconfig |  2 ++
 configs/P1022DS_NAND_defconfig   |  2 ++
 configs/P1022DS_SDCARD_defconfig |  2 ++
 configs/P1022DS_SPIFLASH_defconfig   |  2 ++
 configs/P1024RDB_NAND_defconfig  |  2 ++
 configs/P1024RDB_SDCARD_defconfig|  2 ++
 configs/P1024RDB_SPIFLASH_defconfig  |  2 ++
 configs/P1025RDB_NAND_defconfig  |  2 ++
 configs/P1025RDB_SDCARD_defconfig|  2 ++
 configs/P1025RDB_SPIFLASH_defconfig  |  2 ++
 configs/P2020RDB-PC_36BIT_NAND_defconfig |  2 ++
 configs/P2020RDB-PC_36BIT_SDCARD_defconfig   |  2 ++
 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig |  2 ++
 configs/P2020RDB-PC_NAND_defconfig   |  2 ++
 configs/P2020RDB-PC_SDCARD_defconfig |  2 ++
 configs/P2020RDB-PC_SPIFLASH_defconfig   |  2 ++
 include/configs/BSC9131RDB.h |  1 -
 include/configs/BSC9132QDS.h |  1 -
 include/configs/C29XPCIE.h   |  3 ---
 include/configs/P1010RDB.h   |  4 
 include/configs/P1022DS.h|  3 ---
 include/configs/p1_p2_rdb_pc.h   |  3 ---
 61 files changed, 121 insertions(+), 15 deletions(-)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 206c24076d..52669ce1f8 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -189,6 +189,19 @@ config SPL_DISPLAY_PRINT
  banner ("U-Boot SPL ..."). This function should be provided by
  the board.
 
+config SPL_SKIP_RELOCATE
+   bool "Skip code relocation in SPL"
+   default y
+   help
+ The SPL code will be relocated to a high memory if you say no here.
+ Only ARM64 and PowerPC SPL support relocate now.
+
+config SPL_RELOC_TEXT_BASE
+   hex "Address the SPL relocate to"
+   depends on !SPL_SKIP_RELOCATE
+   help
+ The address on the ram where the SPL relocate to.
+
 config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
bool "MMC raw mode: by sector"
default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \
diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig 
b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
index 55906fa0ff..81aaff4585 100644
--- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
@@ -13,6 +13,8 @@ CONFIG_BOOTDELAY=10
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 # CONFIG_MISC_INIT_R is not set
 # CONFIG_SPL_FRAMEWORK is not set
+# CONFIG_SPL_SKIP_RELOCATE is not set
+CONFIG_SPL_RELOC_TEXT_BASE=0x10
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_FLASH is not set
diff --git a/conf

[U-Boot] [PATCH v2 0/3] Enable spl relocation on arm

2019-05-16 Thread Andy Yan

Some times we want to relocate spl code to dram after dram
initialization or relocate spl code to a high memory to avoid
code overid.

For example on Rockchip armv8 platform, we run with boot flow
TPL->SPL->ATF->U-Boot.
TPL run in sram and is responsible for dram initialization.
SPL run from the start address of dram and is responsible for
loading ATF and U-Boot.

The case here is that the ATF load address is from 64KB of dram,
which overlaps with spl code itself.

So we want to relocate spl itself to high memory to aovid this.

When look the code, I found powerpc use the spl relocation. So
I dicide share the config with powerpc.

Changes in v2:
- Move Kconfig modification to PATCH 1/3
- Add more detial commit message

Andy Yan (3):
  powerpc: Convert CONFIG_SPL_RELOC_TEXT_BASE to Kconfig
  spl: add relocation support
  arm: add spl relocation support for arm

 arch/arm/config.mk   |  6 +++
 arch/arm/cpu/armv8/start.S   |  4 ++
 arch/arm/cpu/armv8/u-boot-spl.lds| 17 ++
 arch/arm/lib/Makefile|  2 +-
 arch/arm/lib/crt0_64.S   |  3 +-
 common/spl/Kconfig   | 13 +
 common/spl/spl.c | 55 
 configs/BSC9131RDB_NAND_SYSCLK100_defconfig  |  2 +
 configs/BSC9131RDB_NAND_defconfig|  2 +
 configs/BSC9132QDS_NAND_DDRCLK100_defconfig  |  2 +
 configs/BSC9132QDS_NAND_DDRCLK133_defconfig  |  2 +
 configs/C29XPCIE_NAND_defconfig  |  2 +
 configs/P1010RDB-PA_36BIT_NAND_defconfig |  2 +
 configs/P1010RDB-PA_36BIT_SDCARD_defconfig   |  2 +
 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig |  2 +
 configs/P1010RDB-PA_NAND_defconfig   |  2 +
 configs/P1010RDB-PA_SDCARD_defconfig |  2 +
 configs/P1010RDB-PA_SPIFLASH_defconfig   |  2 +
 configs/P1010RDB-PB_36BIT_NAND_defconfig |  2 +
 configs/P1010RDB-PB_36BIT_SDCARD_defconfig   |  2 +
 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig |  2 +
 configs/P1010RDB-PB_NAND_defconfig   |  2 +
 configs/P1010RDB-PB_SDCARD_defconfig |  2 +
 configs/P1010RDB-PB_SPIFLASH_defconfig   |  2 +
 configs/P1020MBG-PC_36BIT_SDCARD_defconfig   |  2 +
 configs/P1020MBG-PC_SDCARD_defconfig |  2 +
 configs/P1020RDB-PC_36BIT_NAND_defconfig |  2 +
 configs/P1020RDB-PC_36BIT_SDCARD_defconfig   |  2 +
 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig |  2 +
 configs/P1020RDB-PC_NAND_defconfig   |  2 +
 configs/P1020RDB-PC_SDCARD_defconfig |  2 +
 configs/P1020RDB-PC_SPIFLASH_defconfig   |  2 +
 configs/P1020RDB-PD_NAND_defconfig   |  2 +
 configs/P1020RDB-PD_SDCARD_defconfig |  2 +
 configs/P1020RDB-PD_SPIFLASH_defconfig   |  2 +
 configs/P1020UTM-PC_36BIT_SDCARD_defconfig   |  2 +
 configs/P1020UTM-PC_SDCARD_defconfig |  2 +
 configs/P1021RDB-PC_36BIT_NAND_defconfig |  2 +
 configs/P1021RDB-PC_36BIT_SDCARD_defconfig   |  2 +
 configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig |  2 +
 configs/P1021RDB-PC_NAND_defconfig   |  2 +
 configs/P1021RDB-PC_SDCARD_defconfig |  2 +
 configs/P1021RDB-PC_SPIFLASH_defconfig   |  2 +
 configs/P1022DS_36BIT_NAND_defconfig |  2 +
 configs/P1022DS_36BIT_SDCARD_defconfig   |  2 +
 configs/P1022DS_36BIT_SPIFLASH_defconfig |  2 +
 configs/P1022DS_NAND_defconfig   |  2 +
 configs/P1022DS_SDCARD_defconfig |  2 +
 configs/P1022DS_SPIFLASH_defconfig   |  2 +
 configs/P1024RDB_NAND_defconfig  |  2 +
 configs/P1024RDB_SDCARD_defconfig|  2 +
 configs/P1024RDB_SPIFLASH_defconfig  |  2 +
 configs/P1025RDB_NAND_defconfig  |  2 +
 configs/P1025RDB_SDCARD_defconfig|  2 +
 configs/P1025RDB_SPIFLASH_defconfig  |  2 +
 configs/P2020RDB-PC_36BIT_NAND_defconfig |  2 +
 configs/P2020RDB-PC_36BIT_SDCARD_defconfig   |  2 +
 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig |  2 +
 configs/P2020RDB-PC_NAND_defconfig   |  2 +
 configs/P2020RDB-PC_SDCARD_defconfig |  2 +
 configs/P2020RDB-PC_SPIFLASH_defconfig   |  2 +
 include/configs/BSC9131RDB.h |  1 -
 include/configs/BSC9132QDS.h |  1 -
 include/configs/C29XPCIE.h   |  3 --
 include/configs/P1010RDB.h   |  4 --
 include/configs/P1022DS.h|  3 --
 include/configs/p1_p2_rdb_pc.h   |  3 --
 67 files changed, 206 insertions(+), 17 deletions(-)

-- 
2.17.1



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Re: [U-Boot] [PATCH 2/2] arm: add spl relocation support for armv8

2019-04-29 Thread Andy Yan


Hi Marek, Fabio:

On 2019/4/29 下午7:46, Marek Vasut wrote:

On 4/29/19 1:38 PM, Andy Yan wrote:

Hi Fabio:

On 2019/4/29 下午7:08, Fabio Estevam wrote:

Hi Andy,

On Mon, Apr 29, 2019 at 6:06 AM Andy Yan  wrote:

Relocate spl itself to a high memory.

Please improve the commit message and explain the reason for doing this.



The detail reason I described in [PATCH 1/2],  you are in the list.

Once this is committed to git, there will be no PATCH 1/2 in the git log
, so the commit message should explain what this patch does.



I will add the detail in next version.



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Re: [U-Boot] [PATCH 2/2] arm: add spl relocation support for armv8

2019-04-29 Thread Andy Yan


Hi Fabio:

On 2019/4/29 下午7:08, Fabio Estevam wrote:

Hi Andy,

On Mon, Apr 29, 2019 at 6:06 AM Andy Yan  wrote:

Relocate spl itself to a high memory.

Please improve the commit message and explain the reason for doing this.




The detail reason I described in [PATCH 1/2],  you are in the list.



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Re: [U-Boot] [PATCH 3/3] rockchip: rk3399: update defconfig for TPL

2019-04-29 Thread Andy Yan

Kever Yang  于2019年4月1日周一 下午5:26写道：

> The SPL is now running at SDRAM, and 0x1 is used by BL31,
> and the ARM SPL do not support relocate now, we need reserved
> 0x5 so that it won't overwrite the code when we load the
> bl31 to target space.
> We should remove this after we enable the relocate feature.
>
> The SPL need malloc 0x9000 for MMC as buffer used for transfer
> data to IRAM(The EMMC DMA can not transfer data to IRAM directly).
>
> Signed-off-by: Kever Yang 
> ---
>
>  configs/evb-rk3399_defconfig | 6 --
>  configs/firefly-rk3399_defconfig | 6 --
>  2 files changed, 8 insertions(+), 4 deletions(-)
>
> Tested-by: Andy Yan 


> diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
> index 3a0ed1808b..b5a6019343 100644
> --- a/configs/evb-rk3399_defconfig
> +++ b/configs/evb-rk3399_defconfig
> @@ -5,7 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
>  CONFIG_SPL_LIBGENERIC_SUPPORT=y
>  CONFIG_SYS_MALLOC_F_LEN=0x4000
>  CONFIG_ROCKCHIP_RK3399=y
> -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
> +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x5
>  CONFIG_DEBUG_UART_BASE=0xFF1A
>  CONFIG_DEBUG_UART_CLOCK=2400
>  CONFIG_SPL_STACK_R_ADDR=0x8
> @@ -18,9 +18,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
>  # CONFIG_DISPLAY_CPUINFO is not set
>  CONFIG_DISPLAY_BOARDINFO_LATE=y
>  CONFIG_SPL_STACK_R=y
> -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
> +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
>  CONFIG_SPL_ATF=y
>  CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
> +CONFIG_TPL=y
>  CONFIG_CMD_BOOTZ=y
>  CONFIG_CMD_GPT=y
>  CONFIG_CMD_MMC=y
> @@ -77,4 +78,5 @@ CONFIG_VIDEO_ROCKCHIP=y
>  CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
>  CONFIG_DISPLAY_ROCKCHIP_MIPI=y
>  CONFIG_USE_TINY_PRINTF=y
> +CONFIG_SPL_TINY_MEMSET=y
>  CONFIG_ERRNO_STR=y
> diff --git a/configs/firefly-rk3399_defconfig
> b/configs/firefly-rk3399_defconfig
> index 3b3be2218f..444af07f9a 100644
> --- a/configs/firefly-rk3399_defconfig
> +++ b/configs/firefly-rk3399_defconfig
> @@ -5,7 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
>  CONFIG_SPL_LIBGENERIC_SUPPORT=y
>  CONFIG_SYS_MALLOC_F_LEN=0x4000
>  CONFIG_ROCKCHIP_RK3399=y
> -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
> +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x5
>  CONFIG_DEBUG_UART_BASE=0xFF1A
>  CONFIG_DEBUG_UART_CLOCK=2400
>  CONFIG_SPL_STACK_R_ADDR=0x8
> @@ -18,9 +18,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
>  # CONFIG_DISPLAY_CPUINFO is not set
>  CONFIG_DISPLAY_BOARDINFO_LATE=y
>  CONFIG_SPL_STACK_R=y
> -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
> +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
>  CONFIG_SPL_ATF=y
>  CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
> +CONFIG_TPL=y
>  CONFIG_CMD_BOOTZ=y
>  CONFIG_CMD_GPT=y
>  CONFIG_CMD_MMC=y
> @@ -72,4 +73,5 @@ CONFIG_USB_ETHER_MCS7830=y
>  CONFIG_USB_ETHER_RTL8152=y
>  CONFIG_USB_ETHER_SMSC95XX=y
>  CONFIG_USE_TINY_PRINTF=y
> +CONFIG_SPL_TINY_MEMSET=y
>  CONFIG_ERRNO_STR=y
> --
> 2.20.1
>
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Re: [U-Boot] [PATCH v2 09/10] rockchip: rk3399: use grf structure to access reg

2019-04-29 Thread Andy Yan

Kever Yang  于2019年3月29日周五 上午9:13写道：

> Prefer to use structure to access register if we could.
>
> Signed-off-by: Kever Yang 
> ---
>
>  arch/arm/mach-rockchip/rk3399/rk3399.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
>

Tested-by: Andy Yan 


> diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c
> b/arch/arm/mach-rockchip/rk3399/rk3399.c
> index 7567a4f584..b76ba4ed32 100644
> --- a/arch/arm/mach-rockchip/rk3399/rk3399.c
> +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
> @@ -6,11 +6,13 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>
>  DECLARE_GLOBAL_DATA_PTR;
>
>  #define GRF_EMMCCORE_CON11 0xff77f02c
> +#define GRF_BASE   0xff77
>
>  static struct mm_region rk3399_mem_map[] = {
> {
> @@ -48,9 +50,10 @@ int dram_init_banksize(void)
>  int arch_cpu_init(void)
>  {
> /* We do some SoC one time setting here. */
> +   struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
>
> /* Emmc clock generator: disable the clock multipilier */
> -   rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
> +   rk_clrreg(>emmccore_con[11], 0x0ff);
>
> return 0;
>  }
> --
> 2.20.1
>
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Re: [U-Boot] [PATCH 3/8] rockchip: px5: update SPL size for spl/tpl

2019-04-29 Thread Andy Yan

Kever Yang  于2019年3月29日周五 下午10:55写道：

> Signed-off-by: Kever Yang 
> ---
>
>  include/configs/evb_px5.h   | 1 +
>  include/configs/rk3368_common.h | 3 ++-
>  2 files changed, 3 insertions(+), 1 deletion(-)
>
>
Tested-by: Andy Yan 


> diff --git a/include/configs/evb_px5.h b/include/configs/evb_px5.h
> index e67bee1721..e9304206bb 100644
> --- a/include/configs/evb_px5.h
> +++ b/include/configs/evb_px5.h
> @@ -9,5 +9,6 @@
>  #include 
>
>  #define CONFIG_CONSOLE_SCROLL_LINES10
> +#define CONFIG_SYS_MMC_ENV_DEV 0
>
>  #endif
> diff --git a/include/configs/rk3368_common.h
> b/include/configs/rk3368_common.h
> index 5aa598287a..bb5490c3c2 100644
> --- a/include/configs/rk3368_common.h
> +++ b/include/configs/rk3368_common.h
> @@ -28,9 +28,10 @@
>  #define CONFIG_SYS_LOAD_ADDR   0x0028
>
>  #define CONFIG_SPL_TEXT_BASE0x
> -#define CONFIG_SPL_MAX_SIZE 0x4
> +#define CONFIG_SPL_MAX_SIZE 0x6
>  #define CONFIG_SPL_BSS_START_ADDR   0x40
>  #define CONFIG_SPL_BSS_MAX_SIZE 0x2
> +#define CONFIG_SPL_STACK   0x00188000
>
>  #ifndef CONFIG_SPL_BUILD
>  #define ENV_MEM_LAYOUT_SETTINGS \
> --
> 2.20.1
>
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Re: [U-Boot] [PATCH 8/8] rockchip: px5: add timer0 dts node as tick timer

2019-04-29 Thread Andy Yan

Kever Yang  于2019年3月29日周五 下午10:54写道：

> Let's use rockchip timer before stimer patches can be merged.
>
> Signed-off-by: Kever Yang 
> ---
>
>  arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 7 +++
>  1 file changed, 7 insertions(+)
>
> Tested-by: Andy Yan 


> diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> index 18b841864c..f5406d4c7e 100644
> --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> @@ -5,6 +5,7 @@
>  / {
> chosen {
> u-boot,spl-boot-order = 
> +   tick-timer = "/timer@ff81";
> };
>  };
>
> @@ -60,3 +61,9 @@
>   {
> u-boot,dm-pre-reloc;
>  };
> +
> + {
> +   u-boot,dm-pre-reloc;
> +   clock-frequency = <2400>;
> +   status = "okay";
> +};
> --
> 2.20.1
>
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Re: [U-Boot] [PATCH 2/3] rockchip: ram: rk3399: update for TPL

2019-04-29 Thread Andy Yan

Kever Yang  于2019年4月1日周一 下午5:25写道：

> Init the ddr sdram in TPL instead of SPL, update the code.
>
> Signed-off-by: Kever Yang 
> ---
>
>  drivers/ram/rockchip/sdram_rk3399.c | 15 ++-
>  1 file changed, 10 insertions(+), 5 deletions(-)
>
>
Tested-by: Andy Yan 


> diff --git a/drivers/ram/rockchip/sdram_rk3399.c
> b/drivers/ram/rockchip/sdram_rk3399.c
> index 05ec5fc28d..52518656c4 100644
> --- a/drivers/ram/rockchip/sdram_rk3399.c
> +++ b/drivers/ram/rockchip/sdram_rk3399.c
> @@ -30,7 +30,8 @@ struct chan_info {
>  };
>
>  struct dram_info {
> -#ifdef CONFIG_SPL_BUILD
> +#if defined(CONFIG_TPL_BUILD) || \
> +   (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
> struct chan_info chan[2];
> struct clk ddr_clk;
> struct rk3399_cru *cru;
> @@ -55,7 +56,8 @@ struct dram_info {
>  #define PHY_DRV_ODT_40 0xe
>  #define PHY_DRV_ODT_34_3   0xf
>
> -#ifdef CONFIG_SPL_BUILD
> +#if defined(CONFIG_TPL_BUILD) || \
> +   (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
>
>  struct rockchip_dmc_plat {
>  #if CONFIG_IS_ENABLED(OF_PLATDATA)
> @@ -1187,7 +1189,8 @@ static int rk3399_dmc_init(struct udevice *dev)
>
>  static int rk3399_dmc_probe(struct udevice *dev)
>  {
> -#ifdef CONFIG_SPL_BUILD
> +#if defined(CONFIG_TPL_BUILD) || \
> +   (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
> if (rk3399_dmc_init(dev))
> return 0;
>  #else
> @@ -1226,12 +1229,14 @@ U_BOOT_DRIVER(dmc_rk3399) = {
> .id = UCLASS_RAM,
> .of_match = rk3399_dmc_ids,
> .ops = _dmc_ops,
> -#ifdef CONFIG_SPL_BUILD
> +#if defined(CONFIG_TPL_BUILD) || \
> +   (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
> .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
>  #endif
> .probe = rk3399_dmc_probe,
> .priv_auto_alloc_size = sizeof(struct dram_info),
> -#ifdef CONFIG_SPL_BUILD
> +#if defined(CONFIG_TPL_BUILD) || \
> +   (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
> .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
>  #endif
>  };
> --
> 2.20.1
>
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Re: [U-Boot] [PATCH 7/8] rockchip: rk3368: remove uart iomux init in SPL

2019-04-29 Thread Andy Yan

Hi Kever:

Kever Yang  于2019年3月29日周五 下午10:55写道：

> The iomux should have been set in board_debug_uart_init(),
> do not set in board_init_f(), remove it.
>
> Signed-off-by: Kever Yang 
> ---
>
>  arch/arm/mach-rockchip/rk3368-board-spl.c | 13 -
>  1 file changed, 13 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c
> b/arch/arm/mach-rockchip/rk3368-board-spl.c
> index b055ed4aee..9cb5eab8ae 100644
> --- a/arch/arm/mach-rockchip/rk3368-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c
> @@ -24,19 +24,6 @@ void board_init_f(ulong dummy)
> hang();
> }
>
> -   /* Set up our preloader console */
> -   ret = uclass_get_device(UCLASS_PINCTRL, 0, );
>


the struct udevice* pinctrl definition should also be removed.



> -   if (ret) {
> -   pr_err("%s: pinctrl init failed: %d\n", __func__, ret);
> -   hang();
> -   }
> -
> -   ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0);
> -   if (ret) {
> -   pr_err("%s: failed to set up console UART\n", __func__);
> -   hang();
> -   }
> -
> preloader_console_init();
>
> ret = uclass_get_device(UCLASS_RAM, 0, );
> --
> 2.20.1
>
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Re: [U-Boot] [PATCH 1/8] rockchip: rk3368: support UART2/4 in board_debug_uart_init()

2019-04-29 Thread Andy Yan

Kever Yang  于2019年3月29日周五 下午10:54写道：

> evb-rk3368 is using UART2 and PX5 evb is using UART4
>
> Signed-off-by: Kever Yang 
> ---
>
>  arch/arm/mach-rockchip/rk3368/rk3368.c | 40 ++
>  1 file changed, 40 insertions(+)
>
>
Tested-by: Andy Yan 


> diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c
> b/arch/arm/mach-rockchip/rk3368/rk3368.c
> index 1ed06c5352..f06d27717d 100644
> --- a/arch/arm/mach-rockchip/rk3368/rk3368.c
> +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
> @@ -124,6 +124,46 @@ void board_debug_uart_init(void)
>  GPIO2D0_MASK, GPIO2D0_UART0_SIN);
> rk_clrsetreg(>gpio2d_iomux,
>  GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
> +#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE ==
> 0xff1c)
> +   struct rk3368_pmu_grf * const pmugrf __maybe_unused =
> +   (struct rk3368_pmu_grf * const)0xff738000;
> +
> +   enum {
> +   /* UART4 */
> +   GPIO0D2_MASK= GENMASK(5, 4),
> +   GPIO0D2_GPIO= 0,
> +   GPIO0D2_UART4_SOUT  = (3 << 4),
> +
> +   GPIO0D3_MASK= GENMASK(7, 6),
> +   GPIO0D3_GPIO= 0,
> +   GPIO0D3_UART4_SIN   = (3 << 6),
> +   };
> +
> +   /* Enable early UART4 on the PX5 */
> +   rk_clrsetreg(>gpio0d_iomux,
> +GPIO0D2_MASK | GPIO0D3_MASK,
> +GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
> +#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE ==
> 0xff69)
> +   struct rk3368_grf * const grf =
> +   (struct rk3368_grf * const)0xff77;
> +
> +   enum {
> +   GPIO2A6_SHIFT   = 12,
> +   GPIO2A6_MASK= GENMASK(13, 12),
> +   GPIO2A6_GPIO= 0,
> +   GPIO2A6_UART2_SIN   = (2 << GPIO2A6_SHIFT),
> +
> +   GPIO2A5_SHIFT   = 10,
> +   GPIO2A5_MASK= GENMASK(11, 10),
> +   GPIO2A5_GPIO= 0,
> +   GPIO2A5_UART2_SOUT  = (2 << GPIO2A5_SHIFT),
> +   };
> +
> +   /* Enable early UART2 on the RK3368 */
> +   rk_clrsetreg(>gpio2a_iomux,
> +GPIO2A6_MASK, GPIO2A6_UART2_SIN);
> +   rk_clrsetreg(>gpio2a_iomux,
> +GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
>  #endif
>  }
>  #endif
> --
> 2.20.1
>
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Re: [U-Boot] [PATCH 4/8] rockchip: px5: update defconfig for TPL/SPL

2019-04-29 Thread Andy Yan

Kever Yang  于2019年3月29日周五 下午10:54写道：

> Signed-off-by: Kever Yang 
> ---
>
>  configs/evb-px5_defconfig | 56 +--
>  1 file changed, 54 insertions(+), 2 deletions(-)
>
>
Tested-by: Andy Yan 


> diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
> index 1d428e7ac8..f99943de08 100644
> --- a/configs/evb-px5_defconfig
> +++ b/configs/evb-px5_defconfig
> @@ -1,30 +1,82 @@
>  CONFIG_ARM=y
>  CONFIG_ARCH_ROCKCHIP=y
>  CONFIG_SYS_TEXT_BASE=0x0020
> -CONFIG_SYS_MALLOC_F_LEN=0x1000
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
>  CONFIG_ROCKCHIP_RK3368=y
> +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4
> +CONFIG_TPL_LIBCOMMON_SUPPORT=y
> +CONFIG_TPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
>  CONFIG_TARGET_EVB_PX5=y
> +CONFIG_SPL=y
>  CONFIG_DEBUG_UART_BASE=0xFF1c
>  CONFIG_DEBUG_UART_CLOCK=2400
> +CONFIG_SPL_STACK_R_ADDR=0x60
> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
> +CONFIG_SPL_SPI_SUPPORT=y
>  CONFIG_DEBUG_UART=y
>  CONFIG_NR_DRAM_BANKS=1
>  CONFIG_ANDROID_BOOT_IMAGE=y
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
> +CONFIG_BOOTSTAGE=y
> +CONFIG_SPL_BOOTSTAGE=y
> +CONFIG_BOOTSTAGE_REPORT=y
> +CONFIG_BOOTSTAGE_FDT=y
>  CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb"
>  # CONFIG_DISPLAY_CPUINFO is not set
>  CONFIG_DISPLAY_BOARDINFO_LATE=y
>  CONFIG_ARCH_EARLY_INIT_R=y
> +CONFIG_SPL_BOOTROM_SUPPORT=y
> +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
> +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
> +CONFIG_SPL_STACK_R=y
> +CONFIG_SPL_ATF=y
> +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
> +CONFIG_TPL=y
> +CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
> +CONFIG_TPL_BOOTROM_SUPPORT=y
>  CONFIG_CMD_MMC=y
>  CONFIG_CMD_CACHE=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_TPL_OF_CONTROL=y
> +CONFIG_OF_LIVE=y
>  CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb"
> +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
> +CONFIG_TPL_OF_PLATDATA=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_TPL_DM=y
>  CONFIG_REGMAP=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_TPL_REGMAP=y
>  CONFIG_SYSCON=y
> +CONFIG_SPL_SYSCON=y
> +CONFIG_TPL_SYSCON=y
>  CONFIG_CLK=y
> +CONFIG_SPL_CLK=y
> +CONFIG_TPL_CLK=y
>  CONFIG_MMC_DW=y
>  CONFIG_MMC_DW_ROCKCHIP=y
>  CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
>  CONFIG_RAM=y
> +CONFIG_SPL_RAM=y
> +CONFIG_TPL_RAM=y
> +CONFIG_DM_RESET=y
>  CONFIG_DEBUG_UART_SHIFT=2
> -CONFIG_DEBUG_UART_ANNOUNCE=y
>  CONFIG_DEBUG_UART_SKIP_INIT=y
>  CONFIG_SYSRESET=y
> +CONFIG_TIMER=y
> +CONFIG_SPL_TIMER=y
> +CONFIG_TPL_TIMER=y
> +CONFIG_ROCKCHIP_TIMER=y
> +CONFIG_USE_TINY_PRINTF=y
> +CONFIG_PANIC_HANG=y
> +CONFIG_SPL_TINY_MEMSET=y
> +CONFIG_TPL_TINY_MEMSET=y
>  CONFIG_ERRNO_STR=y
> --
> 2.20.1
>
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Re: [U-Boot] [PATCH 6/8] rockchip: dmc: rk3368: update rank number for evb-px5

2019-04-29 Thread Andy Yan

Kever Yang  于2019年3月29日周五 下午10:53写道：

> evb-px5 has only 1 CS, update for it.
>
> Signed-off-by: Kever Yang 
> ---
>
>  drivers/ram/rockchip/dmc-rk3368.c | 4 
>  1 file changed, 4 insertions(+)
>
>
Tested-by: Andy Yan 


> diff --git a/drivers/ram/rockchip/dmc-rk3368.c
> b/drivers/ram/rockchip/dmc-rk3368.c
> index 92f584fadc..e52fc3baad 100644
> --- a/drivers/ram/rockchip/dmc-rk3368.c
> +++ b/drivers/ram/rockchip/dmc-rk3368.c
> @@ -842,7 +842,11 @@ static int setup_sdram(struct udevice *dev)
> move_to_access_state(pctl);
>
> /* TODO(prt): could detect rank in training... */
> +#ifdef CONFIG_TARGET_EVB_PX5
> +   params->chan.rank = 1;
> +#else
> params->chan.rank = 2;
> +#endif
> /* TODO(prt): bus width is not auto-detected (yet)... */
> params->chan.bw = 2;  /* 32bit wide bus */
> params->chan.dbw = params->chan.dbw;  /* 32bit wide bus */
> --
> 2.20.1
>
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Re: [U-Boot] [PATCH 2/8] rockchip: px5 update dts for spl/tpl

2019-04-29 Thread Andy Yan

Kever Yang  于2019年3月29日周五 下午10:52写道：

> TPL need dmc to init ddr sdram, and emmc, boot-order.
>
> Signed-off-by: Kever Yang 
> ---
>
>  arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 29 +
>  1 file changed, 29 insertions(+)
>
>
Tested-by: Andy Yan 


> diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> index 7495781454..18b841864c 100644
> --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> @@ -2,6 +2,27 @@
>  /*
>   * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>   */
> +/ {
> +   chosen {
> +   u-boot,spl-boot-order = 
> +   };
> +};
> +
> + {
> +   u-boot,dm-pre-reloc;
> +
> +   /*
> +* PX5-evb(2GB) need to use CBRD mode, or else the dram is not
> correct
> +* See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
> +* details on the 'rockchip,memory-schedule' property and how it
> +* affects the physical-address to device-address mapping.
> +*/
> +   rockchip,memory-schedule = ;
> +   rockchip,ddr-frequency = <8>;
> +   rockchip,ddr-speed-bin = ;
> +
> +   status = "okay";
> +};
>
>   {
> u-boot,dm-pre-reloc;
> @@ -20,6 +41,10 @@
> u-boot,dm-pre-reloc;
>  };
>
> + {
> +   u-boot,dm-pre-reloc;
> +};
> +
>   {
> u-boot,dm-pre-reloc;
>  };
> @@ -31,3 +56,7 @@
>   {
> u-boot,dm-pre-reloc;
>  };
> +
> + {
> +   u-boot,dm-pre-reloc;
> +};
> --
> 2.20.1
>
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Re: [U-Boot] [PATCH v2 08/10] rockchip: rk3368: move board_debug_uart_init() to rk3368.c

2019-04-29 Thread Andy Yan

Kever Yang  于2019年3月29日周五 上午9:12写道：

> Move the function to soc file so
> that we can find all the soc/board setting in soc file and
> use a common board file later for all rockchip SoCs.
>
> Signed-off-by: Kever Yang 
> ---
>
>  arch/arm/mach-rockchip/rk3368-board-spl.c |  8 --
>  arch/arm/mach-rockchip/rk3368-board-tpl.c | 33 +--
>  arch/arm/mach-rockchip/rk3368/rk3368.c| 31 +
>  3 files changed, 32 insertions(+), 40 deletions(-)
>
>
Tested-by: Andy Yan 


> diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c
> b/arch/arm/mach-rockchip/rk3368-board-spl.c
> index 9dea4ed994..b055ed4aee 100644
> --- a/arch/arm/mach-rockchip/rk3368-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c
> @@ -9,17 +9,9 @@
>  #include 
>  #include 
>  #include 
> -#include 
> -#include 
> -#include 
>  #include 
> -#include 
>  #include 
>
> -void board_debug_uart_init(void)
> -{
> -}
> -
>  void board_init_f(ulong dummy)
>  {
> struct udevice *pinctrl;
> diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c
> b/arch/arm/mach-rockchip/rk3368-board-tpl.c
> index 373f009414..dc65a021c8 100644
> --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c
> +++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c
> @@ -13,7 +13,6 @@
>  #include 
>  #include 
>  #include 
> -#include 
>  #include 
>  #include 
>
> @@ -79,42 +78,12 @@ static void sgrf_init(void)
> rk_clrreg(>softrst_con[4], DMA2_SRST_REQ);
>  }
>
> -void board_debug_uart_init(void)
> -{
> -   /*
> -* N.B.: This is called before the device-model has been
> -*   initialised. For this reason, we can not access
> -*   the GRF address range using the syscon API.
> -*/
> -   struct rk3368_grf * const grf =
> -   (struct rk3368_grf * const)0xff77;
> -
> -   enum {
> -   GPIO2D1_MASK= GENMASK(3, 2),
> -   GPIO2D1_GPIO= 0,
> -   GPIO2D1_UART0_SOUT  = (1 << 2),
> -
> -   GPIO2D0_MASK= GENMASK(1, 0),
> -   GPIO2D0_GPIO= 0,
> -   GPIO2D0_UART0_SIN   = (1 << 0),
> -   };
> -
> -#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE ==
> 0xff18)
> -   /* Enable early UART0 on the RK3368 */
> -   rk_clrsetreg(>gpio2d_iomux,
> -GPIO2D0_MASK, GPIO2D0_UART0_SIN);
> -   rk_clrsetreg(>gpio2d_iomux,
> -GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
> -#endif
> -}
> -
>  void board_init_f(ulong dummy)
>  {
> struct udevice *dev;
> int ret;
>
> -#define EARLY_UART
> -#ifdef EARLY_UART
> +#ifdef CONFIG_DEBUG_UART
> /*
>  * Debug UART can be used from here if required:
>  *
> diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c
> b/arch/arm/mach-rockchip/rk3368/rk3368.c
> index 197f0c485a..1ed06c5352 100644
> --- a/arch/arm/mach-rockchip/rk3368/rk3368.c
> +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
> @@ -96,3 +96,34 @@ int arch_early_init_r(void)
> return mcu_init();
>  }
>  #endif
> +
> +#ifdef CONFIG_DEBUG_UART_BOARD_INIT
> +void board_debug_uart_init(void)
> +{
> +   /*
> +* N.B.: This is called before the device-model has been
> +*   initialised. For this reason, we can not access
> +*   the GRF address range using the syscon API.
> +*/
> +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE ==
> 0xff18)
> +   struct rk3368_grf * const grf =
> +   (struct rk3368_grf * const)0xff77;
> +
> +   enum {
> +   GPIO2D1_MASK= GENMASK(3, 2),
> +   GPIO2D1_GPIO= 0,
> +   GPIO2D1_UART0_SOUT  = (1 << 2),
> +
> +   GPIO2D0_MASK= GENMASK(1, 0),
> +   GPIO2D0_GPIO= 0,
> +   GPIO2D0_UART0_SIN   = (1 << 0),
> +   };
> +
> +   /* Enable early UART0 on the RK3368 */
> +   rk_clrsetreg(>gpio2d_iomux,
> +GPIO2D0_MASK, GPIO2D0_UART0_SIN);
> +   rk_clrsetreg(>gpio2d_iomux,
> +GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
> +#endif
> +}
> +#endif
> --
> 2.20.1
>
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[U-Boot] [PATCH 2/2] arm: add spl relocation support for armv8

2019-04-29 Thread Andy Yan

Relocate spl itself to a high memory.

Signed-off-by: Andy Yan 
---

 arch/arm/config.mk|  6 ++
 arch/arm/cpu/armv8/start.S|  4 
 arch/arm/cpu/armv8/u-boot-spl.lds | 17 +
 arch/arm/lib/Makefile |  2 +-
 arch/arm/lib/crt0_64.S|  3 ++-
 5 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index f25603109e..7f6ad89601 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -102,6 +102,12 @@ endif
 # needed for relocation
 LDFLAGS_u-boot += -pie
 
+ifndef CONFIG_SPL_SKIP_RELOCATE
+LDFLAGS_u-boot-spl = -pie
+else
+SPL_LDFLAGS_u-boot-spl =
+endif
+
 #
 # FIXME: binutils versions < 2.22 have a bug in the assembler where
 # branches to weak symbols can be incorrectly optimized in thumb mode
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index fe52166e28..a7dad3cd69 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -35,7 +35,11 @@ _start:
 
 .globl _TEXT_BASE
 _TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD)
+   .quad   CONFIG_SPL_TEXT_BASE
+#else
.quad   CONFIG_SYS_TEXT_BASE
+#endif
 
 /*
  * These are defined in the linker script.
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds 
b/arch/arm/cpu/armv8/u-boot-spl.lds
index ccbf359bd1..64102afc8b 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -53,6 +53,23 @@ SECTIONS
*(.__end)
} >.sram
 
+#ifndef CONFIG_SPL_SKIP_RELOCATE
+   . = ALIGN(8);
+
+   .rel_dyn_start :
+   {
+   *(.__rel_dyn_start)
+   } >.sram
+
+   .rela.dyn : {
+   *(.rela*)
+   } >.sram
+
+   .rel_dyn_end :
+   {
+   *(.__rel_dyn_end)
+   } >.sram
+#endif
_image_binary_end = .;
 
.bss_start (NOLOAD) : {
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 48ee6c3c60..f27b3fb79f 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -21,7 +21,7 @@ else
 obj-y   += setjmp.o
 endif
 
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_ARM64
 obj-y  += relocate_64.o
 else
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index d6b632aa87..e5605fe325 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -89,7 +89,8 @@ ENTRY(_main)
mov x0, #0
bl  board_init_f
 
-#if !defined(CONFIG_SPL_BUILD)
+#if (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) && 
!defined(CONFIG_SPL_SKIP_RELOCATE)) || \
+   !defined(CONFIG_SPL_BUILD)
 /*
  * Set up intermediate environment (new sp and gd) and call
  * relocate_code(addr_moni). Trick here is that we'll return
-- 
2.17.1



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[U-Boot] [PATCH 1/2] spl: add relocation support

2019-04-29 Thread Andy Yan

Some times we want to relocate spl code to dram after dram
initialization or relocate spl code to a high memory to avoid
code overide.

For example on Rockchip armv8 platform, we run with boot flow
TPL->SPL->ATF->U-Boot.

TPL run in sram and is responsible for dram initialization.
SPL run from the start address of dram and is responsible for
loading ATF and U-Boot.

The case here is that the ATF load address is from 64KB of dram,
which overlaps with spl code itself.

So we want to relocate spl itself to high memory to aovid this.

Signed-off-by: Andy Yan 
---

 common/spl/Kconfig | 13 +++
 common/spl/spl.c   | 55 ++
 2 files changed, 68 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 206c24076d..52669ce1f8 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -189,6 +189,19 @@ config SPL_DISPLAY_PRINT
  banner ("U-Boot SPL ..."). This function should be provided by
  the board.
 
+config SPL_SKIP_RELOCATE
+   bool "Skip code relocation in SPL"
+   default y
+   help
+ The SPL code will be relocated to a high memory if you say no here.
+ Only ARM64 and PowerPC SPL support relocate now.
+
+config SPL_RELOC_TEXT_BASE
+   hex "Address the SPL relocate to"
+   depends on !SPL_SKIP_RELOCATE
+   help
+ The address on the ram where the SPL relocate to.
+
 config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
bool "MMC raw mode: by sector"
default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 88d4b8a9bf..affb65ccbd 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -439,6 +440,28 @@ static int spl_common_init(bool setup_malloc)
return 0;
 }
 
+#if !defined(CONFIG_SPL_SKIP_RELOCATE) && !defined(CONFIG_TPL_BUILD)
+static void spl_setup_relocate(void)
+{
+   gd->relocaddr = CONFIG_SPL_RELOC_TEXT_BASE;
+   gd->new_gd = (gd_t *)gd;
+   gd->start_addr_sp = gd->relocaddr;
+   gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
+
+   gd->start_addr_sp -= gd->fdt_size;
+   gd->new_fdt = (void *)gd->start_addr_sp;
+   memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
+   gd->fdt_blob = gd->new_fdt;
+
+   gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
+}
+#else
+static void spl_setup_relocate(void)
+{
+
+}
+#endif
+
 void spl_set_bd(void)
 {
/*
@@ -460,6 +483,8 @@ int spl_early_init(void)
return ret;
gd->flags |= GD_FLG_SPL_EARLY_INIT;
 
+   spl_setup_relocate();
+
return 0;
 }
 
@@ -563,6 +588,34 @@ static int boot_from_devices(struct spl_image_info 
*spl_image,
return -ENODEV;
 }
 
+#if defined(CONFIG_DM) && !defined(CONFIG_SPL_SKIP_RELOCATE) && 
!defined(CONFIG_TPL_BUILD)
+static int spl_initr_dm(void)
+{
+   int ret;
+
+   /* Save the pre-reloc driver model and start a new one */
+   gd->dm_root_f = gd->dm_root;
+   gd->dm_root = NULL;
+   bootstage_start(BOOTSTATE_ID_ACCUM_DM_R, "dm_r");
+   ret = dm_init_and_scan(false);
+   bootstage_accum(BOOTSTATE_ID_ACCUM_DM_R);
+   if (ret)
+   return ret;
+
+#if defined(CONFIG_TIMER)
+   gd->timer = NULL;
+#endif
+   serial_init();
+
+   return 0;
+}
+#else
+static int spl_initr_dm(void)
+{
+   return 0;
+}
+#endif
+
 void board_init_r(gd_t *dummy1, ulong dummy2)
 {
u32 spl_boot_list[] = {
@@ -577,6 +630,8 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 
debug(">>" SPL_TPL_PROMPT "board_init_r()\n");
 
+   spl_initr_dm();
+
spl_set_bd();
 
 #if defined(CONFIG_SYS_SPL_MALLOC_START)
-- 
2.17.1



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Re: [U-Boot] [U-Boot, 2/2] rockchip: Drop call to rockchip_dnl_mode_check() for now【请注意，邮件由u-boot-boun...@lists.denx.de代发】【请注意，邮件由s...@google.com代发】

2019-03-12 Thread Andy Yan


Hi Simon:

On 2019/3/11 上午10:30, Simon Glass wrote:

Hi Andy,

On Wed, 6 Mar 2019 at 03:52, Andy Yan  wrote:

Hi Simon:

On 2019/2/12 下午11:31, Simon Glass wrote:

HI Andy,

On Tue, 12 Feb 2019 at 04:05, Andy Yan  wrote:

Hi Philipp:

   Sorry for the late reply, we just come back from the Chinese Spring
Festival.

On 2019/2/1 下午6:26, Philipp Tomsich wrote:

Kever,

Independent of whether we revert this for the current cycle (and also
independent of
if I ever find the other patch you had been referring to — I couldn’t
find it in my local
mailing list archive) and then deprecate it for the next release
(unless converted to
DM), we still have a number of architectural issues that need to be
addressed:

I still doubt  is this a right  work-flow for patch apply. Before we
apply  a patch  which will break many other boards , should we  make
sure there is a solution patch applied for these boars first?



1.This really should be a driver under DTS control.
2.We need to not get away from configuring SOM-specific addresses via
Kconfig

Both these issues are technical debt that we’ve accumulated over the
last 18 months
and need to address for the sake of future maintainability.
E.g. ‘setting an address to 0x0 via Kconfig to disable a
driver/feature’ really isn’t in line
with the architectural direction of U-Boot.


For technical side, I think CONFIG_ROCKCHIP_BOOT_MODE_REG is necessary
here, we will read this register from save_boot_params when we get out
from bootrom,  the dtb is not available at this point.

Yes this is happening very early, but I wonder why this is necessary?
Can it be moved to later?

The call to check_back_to_brom_dnl_flag() happens much later so there
should be no problem to convert that.


On the other hand, almost rockchip based products use a recovery key to
enter download(upgrade)mode, this is a muti-funtion key, most of them
reuse with vol+- key,  we would like the u-boot share

dtb with linux kernel. To keep the linux kernel dts as clean as possible
,we don't want to add another dts property to describe this key either.
This is why I implement function rockchip_dnl_key_pressed as __weak.


OK, but given that it is called later, it seems to me that it could
use a driver.



We can't let it called later. See the discuss here :
http://patchwork.ozlabs.org/patch/812228/

Yes I read that, and took a look myself, and certainly it does not
look very easy and I take your point about potential bugs being
introduced.

It seems like you have tried quite hard, so I'm not going to object if
you can't find a way. My main objection was that it broke other
boards.



I took the code many times,  what this code done is : call 
adc_channel_single_shot to check if a download key is pressed, so it is 
very strange it broke the display on minnie. Would you please show the 
boot log when the display broke.




Is there any way the check could be delayed enough to actually be able
to read the device tree? It could call spl_early_init() quite early
and then do that.


Actually,  the interrupt overwrite happens in start.s,  so this don't do 
help.




Regards,
Simon






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Re: [U-Boot] [U-Boot, 2/2] rockchip: Drop call to rockchip_dnl_mode_check() for now【请注意，邮件由u-boot-boun...@lists.denx.de代发】【请注意，邮件由s...@google.com代发】

2019-03-06 Thread Andy Yan


Hi Simon:

On 2019/2/12 下午11:31, Simon Glass wrote:

HI Andy,

On Tue, 12 Feb 2019 at 04:05, Andy Yan  wrote:

Hi Philipp:

  Sorry for the late reply, we just come back from the Chinese Spring
Festival.

On 2019/2/1 下午6:26, Philipp Tomsich wrote:

Kever,

Independent of whether we revert this for the current cycle (and also
independent of
if I ever find the other patch you had been referring to — I couldn’t
find it in my local
mailing list archive) and then deprecate it for the next release
(unless converted to
DM), we still have a number of architectural issues that need to be
addressed:

I still doubt  is this a right  work-flow for patch apply. Before we
apply  a patch  which will break many other boards , should we  make
sure there is a solution patch applied for these boars first?



1.This really should be a driver under DTS control.
2.We need to not get away from configuring SOM-specific addresses via
Kconfig

Both these issues are technical debt that we’ve accumulated over the
last 18 months
and need to address for the sake of future maintainability.
E.g. ‘setting an address to 0x0 via Kconfig to disable a
driver/feature’ really isn’t in line
with the architectural direction of U-Boot.


For technical side, I think CONFIG_ROCKCHIP_BOOT_MODE_REG is necessary
here, we will read this register from save_boot_params when we get out
from bootrom,  the dtb is not available at this point.

Yes this is happening very early, but I wonder why this is necessary?
Can it be moved to later?

The call to check_back_to_brom_dnl_flag() happens much later so there
should be no problem to convert that.


On the other hand, almost rockchip based products use a recovery key to
enter download(upgrade)mode, this is a muti-funtion key, most of them
reuse with vol+- key,  we would like the u-boot share

dtb with linux kernel. To keep the linux kernel dts as clean as possible
,we don't want to add another dts property to describe this key either.
This is why I implement function rockchip_dnl_key_pressed as __weak.


OK, but given that it is called later, it seems to me that it could
use a driver.




We can't let it called later. See the discuss here : 
http://patchwork.ozlabs.org/patch/812228/




Regards,
Simon



I don’t have my own house completely in order (I’ve been talking for a
year now about
finally wrapping the RGMII/GMII selection into an ioctl-call to a
driver) yet, but that doesn’t
mean that we we should delay this clean-up more than absolutely necessary.

Thanks,
Philipp.


On 01.02.2019, at 10:34, Philipp Tomsich
mailto:philipp.toms...@theobroma-systems.com>> wrote:




On 01.02.2019, at 10:32, Kever Yang mailto:kever.y...@rock-chips.com>> wrote:

Hi Philipp,

This is not right,  this patch should not merged like this!!!

I have give my review comment in previous mail, and this will break
many boards.

My another patch do not break anything, but you insist NAK it
without acceptable reason;

What other patch?
I don’t remember seeing that one...


This patch definitely break other board and I have comment it, but
you just ignore other people's review and merge it, good job!

Thanks,
- Kever
On 02/01/2019 05:12 AM, Philipp Tomsich wrote:

This function causes a 5-second delay and stops the display working on
minnie. This code should be in a driver and should only be enabled by
a device-tree property, so that it does not affect devices which
do not
have this feature.

Signed-off-by: Simon Glass mailto:s...@chromium.org>>
Reviewed-by: Philipp Tomsich
mailto:philipp.toms...@theobroma-systems.com>>
---

arch/arm/mach-rockchip/boot_mode.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)


Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [U-Boot, 2/2] rockchip: Drop call to rockchip_dnl_mode_check() for now【请注意，邮件由u-boot-boun...@lists.denx.de代发】

2019-02-11 Thread Andy Yan

Hi Philipp:

    Sorry for the late reply, we just come back from the Chinese Spring 
Festival.

On 2019/2/1 下午6:26, Philipp Tomsich wrote:

Kever,

Independent of whether we revert this for the current cycle (and also 
independent of
if I ever find the other patch you had been referring to — I couldn’t 
find it in my local
mailing list archive) and then deprecate it for the next release 
(unless converted to
DM), we still have a number of architectural issues that need to be 
addressed:

I still doubt  is this a right  work-flow for patch apply. Before we  
apply  a patch  which will break many other boards , should we  make 
sure there is a solution patch applied for these boars first?

1.This really should be a driver under DTS control.
2.We need to not get away from configuring SOM-specific addresses via 
Kconfig

Both these issues are technical debt that we’ve accumulated over the 
last 18 months

and need to address for the sake of future maintainability.
E.g. ‘setting an address to 0x0 via Kconfig to disable a 
driver/feature’ really isn’t in line

with the architectural direction of U-Boot.

For technical side, I think CONFIG_ROCKCHIP_BOOT_MODE_REG is necessary 
here, we will read this register from save_boot_params when we get out 
from bootrom,  the dtb is not available at this point.

On the other hand, almost rockchip based products use a recovery key to 
enter download(upgrade)mode, this is a muti-funtion key, most of them 
reuse with vol+- key,  we would like the u-boot share

dtb with linux kernel. To keep the linux kernel dts as clean as possible 
,we don't want to add another dts property to describe this key either. 
This is why I implement function rockchip_dnl_key_pressed as __weak.

I don’t have my own house completely in order (I’ve been talking for a 
year now about
finally wrapping the RGMII/GMII selection into an ioctl-call to a 
driver) yet, but that doesn’t

mean that we we should delay this clean-up more than absolutely necessary.

Thanks,
Philipp.

On 01.02.2019, at 10:34, Philipp Tomsich 
> wrote:

On 01.02.2019, at 10:32, Kever Yang > wrote:

Hi Philipp,

   This is not right,  this patch should not merged like this!!!

   I have give my review comment in previous mail, and this will break
many boards.

   My another patch do not break anything, but you insist NAK it
without acceptable reason;

What other patch?
I don’t remember seeing that one...

   This patch definitely break other board and I have comment it, but
you just ignore other people's review and merge it, good job!

Thanks,
- Kever
On 02/01/2019 05:12 AM, Philipp Tomsich wrote:

This function causes a 5-second delay and stops the display working on
minnie. This code should be in a driver and should only be enabled by
a device-tree property, so that it does not affect devices which 
do not

have this feature.

Signed-off-by: Simon Glass >
Reviewed-by: Philipp Tomsich 
>

---

arch/arm/mach-rockchip/boot_mode.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH 05/18] rockchip: Add mention of other boards

2019-01-20 Thread Andy Yan

Hi Simon:

Simon Glass  于2019年1月10日周四 下午12:30写道：

> At present some Rockchip SoCs and boards are not mentioned in the README.
> So that people can see which SoCs are supported, expand the list to
> include everything.
>
> Signed-off-by: Simon Glass 
> ---
>
>  doc/README.rockchip | 43 +--
>  1 file changed, 41 insertions(+), 2 deletions(-)
>
> diff --git a/doc/README.rockchip b/doc/README.rockchip
> index 51b00a9d85..2b24ce8c06 100644
> --- a/doc/README.rockchip
> +++ b/doc/README.rockchip
> @@ -34,23 +34,62 @@ You will need:
>  Building
>  
>
> -At present nine RK3288 boards are supported:
> +At present 12 RK3288 boards are supported:
>
> - EVB RK3288 - use evb-rk3288 configuration
> - Fennec RK3288 - use fennec-rk3288 configuration
> - Firefly RK3288 - use firefly-rk3288 configuration
> - Hisense Chromebook - use chromebook_jerry configuration
> +   - Asus C100P Chromebook - use chromebook_minnie configuration
> +   - Asus Chromebit - use chromebook_mickey configuration
> - MiQi RK3288 - use miqi-rk3288 configuration
> - phyCORE-RK3288 RDK - use phycore-rk3288 configuration
> - PopMetal RK3288 - use popmetal-rk3288 configuration
> - Radxa Rock 2 - use rock2 configuration
> - Tinker RK3288 - use tinker-rk3288 configuration
> +   - Vyasa RK3288 - use vyasa-rk3288 configuration
>
> -Two RK3036 board are supported:
> +Two RK3036 boards are supported:
>
> - EVB RK3036 - use evb-rk3036 configuration
> - Kylin - use kylin_rk3036 configuration
>
> +One RK3328 board is supported:
> +
> +   - EVB RK3328
> +
> +Five RK3399 boards are supported (aarch64):
> +
> +   - EBV RK3399 - use evb_rk3399 configuration
> +   - Firefly RK3399 - use the same evb_rk3399 configuration
> +   - Puma - use puma_rk3399 configuration
> +   - Ficus - use ficus-rk3399 configuration
> +   - Rock960 (Vamrs) - use rock960-rk3399 configuration
> +
> +Four RK3368 boards are supported:
> +
> +   - Sheep - use sheep-rk3368 configuration
> +   - Lion - use lion-rk3368 configuration
> +   - Geekbox - use geekbox configuration
> +   - EVB PX5 - use evb-px5  configuration
> +
> +One RK3128 board is supported:
> +
> +   - EVB RK3128 - use evb-rk3128 configuration
> +
> +One RK3229 board is supported:
> +
> +   - EVB RK3229 - use evb-rk3229 configuration
> +
> +One RV1108 board is supported:
> +
> +   - Elgin R1 - use elgin-rv1108 configuration
>

We also  have an EVB for RV1108, see  board/rockchip/evb_rv1108/README

> +
> +One RV3188 baord is supported:
> +
> +   - Raxda Rock - use rock configuration
> +
> +
>  For example:
>
> CROSS_COMPILE=arm-linux-gnueabi- make O=firefly
> firefly-rk3288_defconfig all
> --
> 2.20.1.97.g81188d93c3-goog
>
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Re: [U-Boot] [PATCH v3 0/9] Stop AXP from crashing when enabling LDO3

2018-11-28 Thread Andy Yan

Hi :
Priit Laes  于2018年11月28日周三 下午10:23写道：

> On Wed, Nov 28, 2018 at 08:23:37PM +0800, Andy Yan wrote:
> > Hi :
> > Andy Yan  于2018年11月28日周三 下午7:10写道：
> >
> > > Hi:
> > > Priit Laes  于2018年11月22日周四 上午2:06写道：
> > >
> > >> This is a resend/v2 of a "Stop AXP from crashing when enabling LDO3"
> > >> series,
> > >> posted by Olliver Schinagl in March 2017. Unfortunately it never got
> past
> > >> initial discussion [1], but most Olimex Lime2 boards are still running
> > >> into this bug.
> > >>
> > >> When powering up an AXP209, the default value for LDO3 output is
> enabled.
> > >> This
> > >> works fine. However if for whatever reason, LDO3 is disabled, for
> example
> > >> by OS
> > >> during reboot and u-boot enables LDO3 again, the PMIC shuts down
> (without
> > >> setting an interrupt) causing the board to hang. This behavior has
> been
> > >> seen
> > >> from Linux as well, u-boot disables LDO3 as a default value, the
> kernel
> > >> enables
> > >> it per its DTS, the kernel hangs as the PMIC gets shut down.
> > >>
> > >> The root cause is that some boards have too high capacitance on the
> LDO3
> > >> output
> > >> port causing inrush currents exceeding the maximum of the AXP209.
> > >>
> > >> The fix is to turn on the LDO3 at the lowest possible voltage and then
> > >> set the
> > >> final voltage.
> > >>
> > >> If the capacitance is really big (due to a connected device for
> example)
> > >> the
> > >> AXP209 also features VRC, or Voltage Rate Control, allowing voltage to
> > >> ramp up
> > >> even slower.
> > >>
> > >> Similar changes need to be also implemented in the operating system
> driver
> > >> side when driver needs to toggle power for the ALDO3 regulator.
> > >>
> > >> This patch series implements the above with a few tiny cleanups.
> > >>
> > >> The initial discussion with some scope screenshots can be found in the
> > >> linux-sunxi mailing list [0].
> > >>
> > >> And the initial series were posted to u-boot mailing list [1].
> > >>
> > >> Signed-off-by: Olliver Schinagl 
> > >> Signed-off-by: Priit Laes 
> > >>
> > >> [0] https://groups.google.com/forum/m/#!topic/linux-sunxi/EDvEsbHHqQI
> > >> [1] https://lists.denx.de/pipermail/u-boot/2017-March/282789.html
> > >>
> > >> --
> > >> Changes since v2:
> > >> - Collected Acked-by tags, patches 1,3-5 are now ripe for picking.
> > >> - Olliver fixed wrong code in patch 2, thanks for Maxime for spotting
> > >> - Fixed checkpatch error in patch 5
> > >> - Expanded commit message for patch 6
> > >>
> > >> Changes from initial submission:
> > >> - Rebased on top of latest master and fixed conflicts
> > >> - Added comments about datasheet errors for patch 6
> > >> - Fixed some typos and checkpatch errors
> > >> - Added patch to Olimex Lime2 eMMC board
> > >>
> > >> Olliver Schinagl (8):
> > >>   sunxi: board: Print error after power initialization fails
> > >>   sunxi: pmic_bus: Decrease boot time by not writing duplicate data
> > >>   power: axp209: Use BIT() macro
> > >>   power: axp209: Define the chip version mask
> > >>   power: axp209: Reduce magic values by adding defines for LDO[234]
> > >>   power: axp209: Add support for voltage rate control on LDO3
> > >>   power: axp209: Limit inrush current for broken boards
> > >>   arm: sunxi: Reduce inrush current on Olimex OLinuXino-A20-Lime2
> > >>
> > >> Priit Laes (1):
> > >>   arm: sunxi: Reduce inrush current on Olimex OLinuXino-A20-Lime2-eMMC
> > >>
> > >>  arch/arm/mach-sunxi/pmic_bus.c |  6 ++-
> > >>  board/sunxi/board.c| 18 +++---
> > >>  configs/A20-OLinuXino-Lime2-eMMC_defconfig |  2 +-
> > >>  configs/A20-OLinuXino-Lime2_defconfig  |  2 +-
> > >>  drivers/power/Kconfig  | 43 ++-
> > >>  drivers/power/axp209.c | 66
> ++
> > >>  include/axp209.h   | 70
> +--
> > >>  7 files changed, 172 ins

Re: [U-Boot] [PATCH v3 0/9] Stop AXP from crashing when enabling LDO3

2018-11-28 Thread Andy Yan

Hi :
Andy Yan  于2018年11月28日周三 下午7:10写道：

> Hi:
> Priit Laes  于2018年11月22日周四 上午2:06写道：
>
>> This is a resend/v2 of a "Stop AXP from crashing when enabling LDO3"
>> series,
>> posted by Olliver Schinagl in March 2017. Unfortunately it never got past
>> initial discussion [1], but most Olimex Lime2 boards are still running
>> into this bug.
>>
>> When powering up an AXP209, the default value for LDO3 output is enabled.
>> This
>> works fine. However if for whatever reason, LDO3 is disabled, for example
>> by OS
>> during reboot and u-boot enables LDO3 again, the PMIC shuts down (without
>> setting an interrupt) causing the board to hang. This behavior has been
>> seen
>> from Linux as well, u-boot disables LDO3 as a default value, the kernel
>> enables
>> it per its DTS, the kernel hangs as the PMIC gets shut down.
>>
>> The root cause is that some boards have too high capacitance on the LDO3
>> output
>> port causing inrush currents exceeding the maximum of the AXP209.
>>
>> The fix is to turn on the LDO3 at the lowest possible voltage and then
>> set the
>> final voltage.
>>
>> If the capacitance is really big (due to a connected device for example)
>> the
>> AXP209 also features VRC, or Voltage Rate Control, allowing voltage to
>> ramp up
>> even slower.
>>
>> Similar changes need to be also implemented in the operating system driver
>> side when driver needs to toggle power for the ALDO3 regulator.
>>
>> This patch series implements the above with a few tiny cleanups.
>>
>> The initial discussion with some scope screenshots can be found in the
>> linux-sunxi mailing list [0].
>>
>> And the initial series were posted to u-boot mailing list [1].
>>
>> Signed-off-by: Olliver Schinagl 
>> Signed-off-by: Priit Laes 
>>
>> [0] https://groups.google.com/forum/m/#!topic/linux-sunxi/EDvEsbHHqQI
>> [1] https://lists.denx.de/pipermail/u-boot/2017-March/282789.html
>>
>> --
>> Changes since v2:
>> - Collected Acked-by tags, patches 1,3-5 are now ripe for picking.
>> - Olliver fixed wrong code in patch 2, thanks for Maxime for spotting
>> - Fixed checkpatch error in patch 5
>> - Expanded commit message for patch 6
>>
>> Changes from initial submission:
>> - Rebased on top of latest master and fixed conflicts
>> - Added comments about datasheet errors for patch 6
>> - Fixed some typos and checkpatch errors
>> - Added patch to Olimex Lime2 eMMC board
>>
>> Olliver Schinagl (8):
>>   sunxi: board: Print error after power initialization fails
>>   sunxi: pmic_bus: Decrease boot time by not writing duplicate data
>>   power: axp209: Use BIT() macro
>>   power: axp209: Define the chip version mask
>>   power: axp209: Reduce magic values by adding defines for LDO[234]
>>   power: axp209: Add support for voltage rate control on LDO3
>>   power: axp209: Limit inrush current for broken boards
>>   arm: sunxi: Reduce inrush current on Olimex OLinuXino-A20-Lime2
>>
>> Priit Laes (1):
>>   arm: sunxi: Reduce inrush current on Olimex OLinuXino-A20-Lime2-eMMC
>>
>>  arch/arm/mach-sunxi/pmic_bus.c |  6 ++-
>>  board/sunxi/board.c| 18 +++---
>>  configs/A20-OLinuXino-Lime2-eMMC_defconfig |  2 +-
>>  configs/A20-OLinuXino-Lime2_defconfig  |  2 +-
>>  drivers/power/Kconfig  | 43 ++-
>>  drivers/power/axp209.c | 66 ++
>>  include/axp209.h   | 70 +--
>>  7 files changed, 172 insertions(+), 35 deletions(-)
>>
>> base-commit: a3e1653ddeb02f39481eba572275016171e9670c
>>
>
>
> I also play with a Lime2-eMMC board(rev K) these days,  but I found this
> board could do reboot whatevery in u-boot or kernel when it boot from
> emmc.  But it reboot well when it boot from sdcard.
>
>
Sorry I mean this board couldn't do reboot from kernel or u-boot here .


>  root@lime2:~#
> root@lime2:~#
> root@lime2:~#
> root@lime2:~# reboot
> [ 2089.632091] reboot: Restarting system
>
> Can't see any further reboot log. unless i replug the power jack.
>
>
>
>
>
> When I do reset from u-boot , it failed too:
>
> Boot SPL 2018.05-armbian (Nov 28 2018 - 14:39:04 +0800)
> DRAM: 3/2/2
> Trying to boot from MMC2
>
>
> U-ready
> DRAM:  1 GiB
> MMC:   SUNXI MMC: 1
> Loading Environment from EXT4... MMC: no card present
> ** Bad device mmc 0 **
> In:serial
> Out:   serial
> Err:   serial

Re: [U-Boot] [PATCH v3 0/9] Stop AXP from crashing when enabling LDO3

2018-11-28 Thread Andy Yan

Hi:
Priit Laes  于2018年11月22日周四 上午2:06写道：

> This is a resend/v2 of a "Stop AXP from crashing when enabling LDO3"
> series,
> posted by Olliver Schinagl in March 2017. Unfortunately it never got past
> initial discussion [1], but most Olimex Lime2 boards are still running
> into this bug.
>
> When powering up an AXP209, the default value for LDO3 output is enabled.
> This
> works fine. However if for whatever reason, LDO3 is disabled, for example
> by OS
> during reboot and u-boot enables LDO3 again, the PMIC shuts down (without
> setting an interrupt) causing the board to hang. This behavior has been
> seen
> from Linux as well, u-boot disables LDO3 as a default value, the kernel
> enables
> it per its DTS, the kernel hangs as the PMIC gets shut down.
>
> The root cause is that some boards have too high capacitance on the LDO3
> output
> port causing inrush currents exceeding the maximum of the AXP209.
>
> The fix is to turn on the LDO3 at the lowest possible voltage and then set
> the
> final voltage.
>
> If the capacitance is really big (due to a connected device for example)
> the
> AXP209 also features VRC, or Voltage Rate Control, allowing voltage to
> ramp up
> even slower.
>
> Similar changes need to be also implemented in the operating system driver
> side when driver needs to toggle power for the ALDO3 regulator.
>
> This patch series implements the above with a few tiny cleanups.
>
> The initial discussion with some scope screenshots can be found in the
> linux-sunxi mailing list [0].
>
> And the initial series were posted to u-boot mailing list [1].
>
> Signed-off-by: Olliver Schinagl 
> Signed-off-by: Priit Laes 
>
> [0] https://groups.google.com/forum/m/#!topic/linux-sunxi/EDvEsbHHqQI
> [1] https://lists.denx.de/pipermail/u-boot/2017-March/282789.html
>
> --
> Changes since v2:
> - Collected Acked-by tags, patches 1,3-5 are now ripe for picking.
> - Olliver fixed wrong code in patch 2, thanks for Maxime for spotting
> - Fixed checkpatch error in patch 5
> - Expanded commit message for patch 6
>
> Changes from initial submission:
> - Rebased on top of latest master and fixed conflicts
> - Added comments about datasheet errors for patch 6
> - Fixed some typos and checkpatch errors
> - Added patch to Olimex Lime2 eMMC board
>
> Olliver Schinagl (8):
>   sunxi: board: Print error after power initialization fails
>   sunxi: pmic_bus: Decrease boot time by not writing duplicate data
>   power: axp209: Use BIT() macro
>   power: axp209: Define the chip version mask
>   power: axp209: Reduce magic values by adding defines for LDO[234]
>   power: axp209: Add support for voltage rate control on LDO3
>   power: axp209: Limit inrush current for broken boards
>   arm: sunxi: Reduce inrush current on Olimex OLinuXino-A20-Lime2
>
> Priit Laes (1):
>   arm: sunxi: Reduce inrush current on Olimex OLinuXino-A20-Lime2-eMMC
>
>  arch/arm/mach-sunxi/pmic_bus.c |  6 ++-
>  board/sunxi/board.c| 18 +++---
>  configs/A20-OLinuXino-Lime2-eMMC_defconfig |  2 +-
>  configs/A20-OLinuXino-Lime2_defconfig  |  2 +-
>  drivers/power/Kconfig  | 43 ++-
>  drivers/power/axp209.c | 66 ++
>  include/axp209.h   | 70 +--
>  7 files changed, 172 insertions(+), 35 deletions(-)
>
> base-commit: a3e1653ddeb02f39481eba572275016171e9670c
>


I also play with a Lime2-eMMC board(rev K) these days,  but I found this
board could do reboot whatevery in u-boot or kernel when it boot from
emmc.  But it reboot well when it boot from sdcard.

 root@lime2:~#
root@lime2:~#
root@lime2:~#
root@lime2:~# reboot
[ 2089.632091] reboot: Restarting system

Can't see any further reboot log. unless i replug the power jack.





When I do reset from u-boot , it failed too:

Boot SPL 2018.05-armbian (Nov 28 2018 - 14:39:04 +0800)
DRAM: 3/2/2
Trying to boot from MMC2


U-ready
DRAM:  1 GiB
MMC:   SUNXI MMC: 1
Loading Environment from EXT4... MMC: no card present
** Bad device mmc 0 **
In:serial
Out:   serial
Err:   serial
Allwinner mUSB OTG (Peripheral)
SCSI:  SATA link 0 timeout.
A: ethernet@01c5
Warning: usb_ether using MAC address from ROM
, eth1: usb_ether
MMC: no card present
** Bad device mmc 0 **
us 0 for devices... 1 USB Device(s) found
scan1 USB Device(s) found
   scaswitch to partitions #0, OK
mmc1(part MMC: no card present
=> 
=>
=> reset
resetting ...

I post these here hope to know if anyone meet the same situtation.


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Re: [U-Boot] [PATCH v2 3/5] rv1108: Enable eMMC support

2018-11-26 Thread Andy Yan


Hi:

On 2018/11/27 上午12:18, Otavio Salvador wrote:

On Tue, Nov 20, 2018 at 4:56 PM Otavio Salvador  wrote:

This adds the pinctrl handles to enable the use of eMMC on custom
boards (as minievk) and makes it easier for later addition.

Signed-off-by: Otavio Salvador 

Andy, did you review it? Is there someone which would be more
appropriate for me to send the patches?



Thte whole series will to through Dr. Philipp Tomsich





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Re: [U-Boot] [PATCH v2 5/5] rv1108: Add support for default distro_bootcmd

2018-11-26 Thread Andy Yan


Hi:

On 2018/11/21 上午2:55, Otavio Salvador wrote:

This allow easier integration of RV1108 based boards on generic
distributions and build systems.

Signed-off-by: Otavio Salvador 
---

Changes in v2: None

  include/configs/rv1108_common.h | 15 +++
  1 file changed, 15 insertions(+)

diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index cc0384e2f4..16d4e2e355 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -28,3 +28,18 @@
  #define CONFIG_USB_OHCI_NEW
  #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS1
  #endif
+
+#ifndef CONFIG_SPL_BUILD
+#define ENV_MEM_LAYOUT_SETTINGS \
+   "scriptaddr=0x6000\0" \
+   "fdt_addr_r=0x61f0\0" \
+   "kernel_addr_r=0x6200\0" \
+   "ramdisk_addr_r=0x6400\0"
+
+#include 
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   ENV_MEM_LAYOUT_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "partitions=" PARTS_DEFAULT \
+   BOOTENV
+#endif



Reviewed-by: Andy Yan 


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Re: [U-Boot] [PATCH v2 4/5] rv1108: Make USB OTG functional

2018-11-26 Thread Andy Yan


Hi:

On 2018/11/21 上午2:55, Otavio Salvador wrote:

Like it is done for other Rockchip SoCs, introduce a board_usb_init()
function so that USB OTG can be functional on rv1108 too.

Signed-off-by: Otavio Salvador 
---

Changes in v2: None

  arch/arm/dts/rv1108.dtsi  | 45 ++-
  arch/arm/mach-rockchip/Makefile   |  1 +
  arch/arm/mach-rockchip/rv1108-board.c | 81 +++
  3 files changed, 124 insertions(+), 3 deletions(-)
  create mode 100644 arch/arm/mach-rockchip/rv1108-board.c



It's better to split dtsi and .c file



diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi
index 23a44bfaca..215d885225 100644
--- a/arch/arm/dts/rv1108.dtsi
+++ b/arch/arm/dts/rv1108.dtsi
@@ -121,8 +121,35 @@
};
  
  	grf: syscon@1030 {

-   compatible = "rockchip,rv1108-grf", "syscon";
+   compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
reg = <0x1030 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   u2phy: usb2-phy@100 {
+   compatible = "rockchip,rv1108-usb2phy";
+   reg = <0x100 0x0c>;
+   clocks = < SCLK_USBPHY>;
+   clock-names = "phyclk";
+   #clock-cells = <0>;
+   clock-output-names = "usbphy";
+   rockchip,usbgrf = <>;
+   status = "disabled";
+
+   u2phy_otg: otg-port {
+   interrupts = ;
+   interrupt-names = "otg-mux";
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+
+   u2phy_host: host-port {
+   interrupts = ;
+   interrupt-names = "linestate";
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+   };
};
  
  	saradc: saradc@1038c000 {

@@ -141,6 +168,11 @@
reg = <0x2006 0x1000>;
};
  
+	usbgrf: syscon@202a {

+   compatible = "rockchip,rv1108-usbgrf", "syscon";
+   reg = <0x202a 0x1000>;
+   };
+
cru: clock-controller@2020 {
compatible = "rockchip,rv1108-cru";
reg = <0x2020 0x1000>;
@@ -200,12 +232,19 @@
};
  
  	usb20_otg: usb@3018 {

-   compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb",
+   compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
 "snps,dwc2";
reg = <0x3018 0x4>;
interrupts = ;
-   hnp-srp-disable;
+   clocks = < HCLK_OTG>;
+   clock-names = "otg";
dr_mode = "otg";
+   g-np-tx-fifo-size = <16>;
+   g-rx-fifo-size = <280>;
+   g-tx-fifo-size = <256 128 128 64 32 16>;
+   g-use-dma;
+   phys = <_otg>;
+   phy-names = "usb2-phy";
status = "disabled";
};
  
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile

index 05706c472a..368302e1da 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
  obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
  obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
  obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o
+obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108-board.o
  endif
  
  obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o

diff --git a/arch/arm/mach-rockchip/rv1108-board.c 
b/arch/arm/mach-rockchip/rv1108-board.c
new file mode 100644
index 00..3412f2c063
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1108-board.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include 
+#include 
+
+static struct dwc2_plat_otg_data rv1108_otg_data = {
+   .rx_fifo_sz = 512,
+   .np_tx_fifo_sz  = 16,
+   .tx_fifo_sz = 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+   const void *blob = gd->fdt_blob;
+   bool matched = false;
+   int node, phy_node;
+   u32 grf_phy_offset;
+   const char *mode;
+
+   /* find the usb_otg node */
+   node = fdt_node_offset_by_compatible(blob, -1, "rockchip,rk3066-usb");
+   while (node > 0) {
+   mode = fdt_getprop(blob, node, "dr_mode", NULL);
+   if (mode && strcmp(mode, "otg") == 0) {
+   matched = true;
+   break;
+   }
+
+   node = fdt_node_offset_by_compatible(blob, node,
+

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