from:"Bao Xiaowei"

[U-Boot] [PATCH] Powerpc: T208xQDS: Modify the comment of the CONFIG_FSL_PCIE_RESET macro

2017-12-18 Thread Bao Xiaowei

Remove duplicate macro CONFIG_FSL_PCIE_RESET and update its comment.
It enables PCIe reset to fix link width 2x - 4x.

Signed-off-by: Bao Xiaowei <xiaowei@nxp.com>
---
 include/configs/T208xQDS.h |3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index e792ec5..06a824e 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -540,7 +540,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PCIE2   /* PCIE controller 2 */
 #define CONFIG_PCIE3   /* PCIE controller 3 */
 #define CONFIG_PCIE4   /* PCIE controller 4 */
-#define CONFIG_FSL_PCIE_RESET
+#define CONFIG_FSL_PCIE_RESET   /* pcie reset fix link width 2x-4x*/
 #define CONFIG_FSL_PCI_INIT/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
 /* controller 1, direct to uli, tgtid 3, Base address 2 */
@@ -584,7 +584,6 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
 #endif
 
-- 
1.7.1

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[U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state judgement more specific

2017-10-20 Thread Bao Xiaowei

For some special reset times for longer pcie devices, the pcie device
may on polling compliance state, the RC considers the pcie device is
link up, but the pcie device is not link up, only the L0 state is link
up state.

Signed-off-by: Bao Xiaowei <xiaowei@nxp.com>
---
 arch/powerpc/include/asm/fsl_pci.h |  2 ++
 drivers/pci/fsl_pci_init.c | 10 ++
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_pci.h 
b/arch/powerpc/include/asm/fsl_pci.h
index 70a5461..323b182 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -25,6 +25,8 @@
 #define PCI_LTSSM  0x404   /* PCIe Link Training, Status State Machine */
 #define PCI_LTSSM_L0   0x16/* L0 state */
 #define PCI_LTSSM_L0_PEX_REV3  0x11/* L0 state for pex rev3*/
+#define LTSSM_PCIE_DETECT_QUIET0x00/* Detect state */
+#define LTSSM_PCIE_DETECT_ACTIVE   0x01/* Detect state */
 
 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
 int fsl_is_pci_agent(struct pci_controller *hose);
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index be57e53..9b5f386 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -335,15 +335,17 @@ static int fsl_pci_link_up(struct pci_controller *hose,
pci_ltssm_l0 = PCI_LTSSM_L0;
 
ltssm = fsl_get_ltssm(hose, pci_info);
-
-   if (ltssm == pci_ltssm_l0) {
+   if (ltssm == LTSSM_PCIE_DETECT_QUIET ||
+   ltssm == LTSSM_PCIE_DETECT_ACTIVE) {
+   enabled = 0;
+   } else if (ltssm == pci_ltssm_l0) {
enabled = 1;
} else {
-   for (i = 0; i < 100 && ltssm < pci_ltssm_l0; i++) {
+   for (i = 0; i < 100 && ltssm != pci_ltssm_l0; i++) {
ltssm = fsl_get_ltssm(hose, pci_info);
udelay(1000);
}
-   enabled = ltssm >= pci_ltssm_l0;
+   enabled = (ltssm == pci_ltssm_l0) ? 1 : 0;
}
 
return enabled;
-- 
2.7.4

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[U-Boot] [PATCH 2/3] Powerpc: pcie: optmize the code of pci init function

2017-10-20 Thread Bao Xiaowei

Adjust the code structure, detail the function module function,
remove the redundancy code.

Signed-off-by: Bao Xiaowei <xiaowei@nxp.com>
---
 arch/powerpc/include/asm/fsl_pci.h |   1 +
 drivers/pci/fsl_pci_init.c | 150 -
 2 files changed, 83 insertions(+), 68 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_pci.h 
b/arch/powerpc/include/asm/fsl_pci.h
index 970f3a48d5..70a5461709 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -24,6 +24,7 @@
 
 #define PCI_LTSSM  0x404   /* PCIe Link Training, Status State Machine */
 #define PCI_LTSSM_L0   0x16/* L0 state */
+#define PCI_LTSSM_L0_PEX_REV3  0x11/* L0 state for pex rev3*/
 
 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
 int fsl_is_pci_agent(struct pci_controller *hose);
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index af20cf0f3e..be57e53811 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
 #endif
+#define PEX_CSR0_LTSSM_MASK0xFC
+#define PEX_CSR0_LTSSM_SHIFT   2
 
 /* Setup one inbound ATMU window.
  *
@@ -290,6 +292,80 @@ static void fsl_pcie_boot_master_release_slave(int port)
 }
 #endif
 
+static int fsl_is_pex_rev_3(struct fsl_pci_info *pci_info)
+{
+   u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
+   ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
+   u32 block_rev;
+
+   block_rev = in_be32(>block_rev1);
+   if (block_rev >= PEX_IP_BLK_REV_3_0)
+   return 1;
+
+   return 0;
+}
+
+static int fsl_get_ltssm(struct pci_controller *hose,
+struct fsl_pci_info *pci_info)
+{
+   u16 ltssm = 0;
+   pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
+   u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
+   ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
+
+   if (fsl_is_pex_rev_3(pci_info))
+   ltssm = (in_be32(>pex_csr0)
+   & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
+   else
+   pci_hose_read_config_word(hose, dev, PCI_LTSSM, );
+
+   return ltssm;
+}
+
+static int fsl_pci_link_up(struct pci_controller *hose,
+   struct fsl_pci_info *pci_info)
+{
+   int enabled = 0;
+   u16 ltssm;
+   int i, pci_ltssm_l0;
+
+   if (fsl_is_pex_rev_3(pci_info))
+   pci_ltssm_l0 = PCI_LTSSM_L0_PEX_REV3;
+   else
+   pci_ltssm_l0 = PCI_LTSSM_L0;
+
+   ltssm = fsl_get_ltssm(hose, pci_info);
+
+   if (ltssm == pci_ltssm_l0) {
+   enabled = 1;
+   } else {
+   for (i = 0; i < 100 && ltssm < pci_ltssm_l0; i++) {
+   ltssm = fsl_get_ltssm(hose, pci_info);
+   udelay(1000);
+   }
+   enabled = ltssm >= pci_ltssm_l0;
+   }
+
+   return enabled;
+}
+
+#if defined(CONFIG_FSL_PCIE_RESET) || \
+   defined(CONFIG_SYS_P4080_ERRATUM_PCIE_A003)
+static void fsl_do_pcie_reset(struct fsl_pci_info *pci_info)
+{
+   u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
+   ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
+
+   /* assert PCIe reset */
+   setbits_be32(>pdb_stat, 0x0800);
+   (void) in_be32(>pdb_stat);
+   udelay(1000);
+   /* clear PCIe reset */
+   clrbits_be32(>pdb_stat, 0x0800);
+   asm("sync;isync");
+}
+#endif
+
 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 {
u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
@@ -298,7 +374,6 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
u32 temp32;
u32 block_rev;
int enabled, r, inbound = 0;
-   u16 ltssm;
u8 temp8, pcie_cap;
int pcie_cap_pos;
int pci_dcr;
@@ -438,63 +513,12 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
udelay(1);
 #endif
if (pcie_cap == PCI_CAP_ID_EXP) {
-   if (block_rev >= PEX_IP_BLK_REV_3_0) {
-#define PEX_CSR0_LTSSM_MASK0xFC
-#define PEX_CSR0_LTSSM_SHIFT   2
-   ltssm = (in_be32(>pex_csr0)
-   & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
-   enabled = (ltssm == 0x11) ? 1 : 0;
 #ifdef CONFIG_FSL_PCIE_RESET
-   int i;
-   /* assert PCIe reset */
-   setbits_be32(>pdb_stat, 0x0800);
-   (void) in_be32(>pdb_stat);
-   udelay(1000);
-

[U-Boot] [PATCH 1/3] fsl/pci: fix leading whitespace of PCI_LTSSM_L0

2017-10-20 Thread Bao Xiaowei

Fix the whitespace of PCI_LTSSM_L0 in fsl_pci.h

Signed-off-by: Bao Xiaowei <xiaowei@nxp.com>
---
 arch/powerpc/include/asm/fsl_pci.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/fsl_pci.h 
b/arch/powerpc/include/asm/fsl_pci.h
index cad341e72c..970f3a48d5 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -23,7 +23,7 @@
 #define FSL_PROG_IF_AGENT  0x1
 
 #define PCI_LTSSM  0x404   /* PCIe Link Training, Status State Machine */
-#define  PCI_LTSSM_L0  0x16/* L0 state */
+#define PCI_LTSSM_L0   0x16/* L0 state */
 
 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
 int fsl_is_pci_agent(struct pci_controller *hose);
-- 
2.14.1

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[U-Boot] [PATCH] Powerpc: Make pcie link state judge more specific

2017-09-24 Thread Bao Xiaowei

For some special reset times for longer pcie devices, in this case, the
pcie device may on polling compliance state, the RC considers the pcie
device is link up, but the pcie device is not link up, only the L0 state
is link up state. So add the link up status judgement mechanisms.

Signed-off-by: Bao Xiaowei <xiaowei@nxp.com>
---
v2:
 - Detailed function module
 - Adjust the code structure

 arch/powerpc/include/asm/fsl_pci.h |   3 +
 drivers/pci/fsl_pci_init.c | 151 -
 2 files changed, 86 insertions(+), 68 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_pci.h 
b/arch/powerpc/include/asm/fsl_pci.h
index cad341e..9dfbf19 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -24,6 +24,9 @@
 
 #define PCI_LTSSM  0x404   /* PCIe Link Training, Status State Machine */
 #define  PCI_LTSSM_L0  0x16/* L0 state */
+#define PCIE_GEN3_LTSSM_L0 0x11/* L0 state */
+#define LTSSM_PCIE_DETECT_QUIET0x00 /* Detect state */
+#define LTSSM_PCIE_DETECT_ACTIVE   0x01 /* Detect state */
 
 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
 int fsl_is_pci_agent(struct pci_controller *hose);
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index af20cf0..5d697bc 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
 #endif
+#define PEX_CSR0_LTSSM_MASK0xFC
+#define PEX_CSR0_LTSSM_SHIFT   2
 
 /* Setup one inbound ATMU window.
  *
@@ -290,6 +292,81 @@ static void fsl_pcie_boot_master_release_slave(int port)
 }
 #endif
 
+static int is_pcie_gen3(struct fsl_pci_info *pci_info)
+{
+   u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
+   volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
+   u32 block_rev;
+
+   block_rev = in_be32(>block_rev1);
+   if (block_rev >= PEX_IP_BLK_REV_3_0)
+   return 1;
+   else
+   return 0;
+}
+
+static int get_ltssm_val(struct pci_controller *hose,
+struct fsl_pci_info *pci_info)
+{
+   u16 ltssm = 0;
+   pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
+   u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
+   volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
+
+   if (is_pcie_gen3(pci_info))
+   ltssm = (in_be32(>pex_csr0)
+   & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
+   else
+   pci_hose_read_config_word(hose, dev, PCI_LTSSM, );
+
+   return ltssm;
+}
+
+static int pci_link_up(struct pci_controller *hose,
+   struct fsl_pci_info *pci_info)
+{
+   int enabled = 0;
+   u16 ltssm;
+   int i, pcie_ltssm_l0;
+
+   if (is_pcie_gen3(pci_info))
+   pcie_ltssm_l0 = PCIE_GEN3_LTSSM_L0;
+   else
+   pcie_ltssm_l0 = PCI_LTSSM_L0;
+
+   ltssm = get_ltssm_val(hose, pci_info);
+   if (ltssm == LTSSM_PCIE_DETECT_QUIET ||
+   ltssm == LTSSM_PCIE_DETECT_ACTIVE)
+   enabled = 0;
+   else if (ltssm == PCIE_GEN3_LTSSM_L0)
+   enabled = 1;
+   else {
+   for (i = 0; i < 100 && ltssm != pcie_ltssm_l0; i++) {
+   ltssm = get_ltssm_val(hose, pci_info);
+   udelay(1000);
+   }
+   enabled = (ltssm == pcie_ltssm_l0) ? 1 : 0;
+   }
+   return enabled;
+}
+
+#if defined(CONFIG_FSL_PCIE_RESET) || \
+   defined(CONFIG_SYS_P4080_ERRATUM_PCIE_A003)
+static void do_pcie_reset(struct fsl_pci_info *pci_info)
+{
+   u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
+   volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
+
+   /* assert PCIe reset */
+   setbits_be32(>pdb_stat, 0x0800);
+   (void) in_be32(>pdb_stat);
+   udelay(1000);
+   /* clear PCIe reset */
+   clrbits_be32(>pdb_stat, 0x0800);
+   asm("sync;isync");
+}
+#endif
+
 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 {
u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
@@ -298,7 +375,6 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
u32 temp32;
u32 block_rev;
int enabled, r, inbound = 0;
-   u16 ltssm;
u8 temp8, pcie_cap;
int pcie_cap_pos;
int pci_dcr;
@@ -438,63 +514,12 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
udelay(1);
 #endif
if (pcie_cap == PCI_CAP_ID_EXP) {
-   if (block_rev >= PEX_IP_BLK_REV_3_0) {
-#define PEX

[U-Boot] [PATCH] PCI: layerscape: Make the pcie link up status judgement more specific

2017-08-15 Thread Bao Xiaowei

For some special reset times for longer pcie devices, in this case, the
pcie device may on polling compliance state, the RC considers the pcie
device is link up, but the pcie device is not link up, only the L0 state
is link up state. So add the link up status judgement mechanisms.

Signed-off-by: Bao Xiaowei <xiaowei@nxp.com>
---
 drivers/pci/pcie_layerscape.c | 25 +
 drivers/pci/pcie_layerscape.h |  3 +++
 2 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 78cde21..4db95c5 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -69,13 +69,30 @@ static int ls_pcie_ltssm(struct ls_pcie *pcie)
 
 static int ls_pcie_link_up(struct ls_pcie *pcie)
 {
-   int ltssm;
+   int ltssm, i;
 
ltssm = ls_pcie_ltssm(pcie);
-   if (ltssm < LTSSM_PCIE_L0)
-   return 0;
 
-   return 1;
+   /*
+* For some special reset times for longer pcie devices,
+* the pcie device may on polling compliance state,
+* on this state, if the device can restored to the L0 state
+* within 100ms considers the pcie device is link up
+*/
+   if (ltssm == LTSSM_PCIE_DETECT_QUIET ||
+   ltssm == LTSSM_PCIE_DETECT_ACTIVE) {
+   return 0;
+   } else if (ltssm == LTSSM_PCIE_L0) {
+   return 1;
+   } else {
+   for (i = 0; i < 100; i++) {
+   udelay(1000);
+   ltssm = ls_pcie_ltssm(pcie);
+   if (ltssm == LTSSM_PCIE_L0)
+   return 1;
+   }
+   return 0;
+   }
 }
 
 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 782e3ab..4313e85 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -70,6 +70,9 @@
 
 #define LTSSM_STATE_MASK   0x3f
 #define LTSSM_PCIE_L0  0x11 /* L0 state */
+#define LTSSM_PCIE_DETECT_QUIET0x00 /* L0 state */
+#define LTSSM_PCIE_DETECT_ACTIVE   0x01 /* L0 state */
+#define LTSSM_PCIE_L0  0x11 /* L0 state */
 
 #define PCIE_DBI_SIZE  0x10 /* 1M */
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: layerscape platform pcie link up state judgment strongly

2017-08-02 Thread Bao Xiaowei

modifiy the ls_pcie_link_up function, add the following three judging
mechanisms:

detect state: return link down status;
L0 state: return link up status;
other state: delay about 100ms retrieve Status Returns the corresponding link
status;

Signed-off-by: Bao Xiaowei <xiaowei@nxp.com>
---
 drivers/pci/pcie_layerscape.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 7565e2f..4446ac9 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -65,13 +65,22 @@ static int ls_pcie_ltssm(struct ls_pcie *pcie)
 
 static int ls_pcie_link_up(struct ls_pcie *pcie)
 {
-   int ltssm;
+   int ltssm, i;
 
ltssm = ls_pcie_ltssm(pcie);
-   if (ltssm < LTSSM_PCIE_L0)
+   if ((ltssm == 0) || (ltssm == 1))
return 0;
-
-   return 1;
+   else if (ltssm == LTSSM_PCIE_L0)
+   return 1;
+   else {
+   for (i = 0; i < 100; i++) {
+   udelay(1000);
+   ltssm = ls_pcie_ltssm(pcie);
+   if (ltssm == LTSSM_PCIE_L0)
+   return 1;
+   }
+   return 0;
+   }
 }
 
 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] ls1046aqds: update the defaule mtdparts

2017-07-12 Thread Bao Xiaowei

modify the include/configs/ls1046aqds.h file, according to the latest
partion rules, norflash nandflash dspiflash detailed partion as follows:

mtd0: 0010 0002 "nor_bank0_rcw"
mtd1: 0020 0002 "nor_bank0_uboot"
mtd2: 0010 0002 "nor_bank0_uboot_env"
mtd3: 0020 0002 "nor_bank0_ppa"
mtd4: 0030 0002 "nor_bank0_secure_boot"
mtd5: 0060 0002 "nor_bank0_dppa_qe"
mtd6: 0010 0002 "nor_bank0_dtb"
mtd7: 0100 0002 "nor_bank0_kernel"
mtd8: 0200 0002 "nor_bank0_rootfs"
mtd9: 0010 0002 "nor_bank4_rcw"
mtd10: 0020 0002 "nor_bank4_uboot"
mtd11: 0020 0002 "nor_bank4_uboot_env"
mtd12: 0010 0002 "nor_bank4_ppa"
mtd13: 0030 0002 "nor_bank4_secure_boot"
mtd14: 0060 0002 "nor_bank4_dppa_qe"
mtd15: 0010 0002 "nor_bank4_dtb"
mtd16: 0100 0002 "nor_bank4_kernel"
mtd17: 0200 0002 "nor_bank4_rootfs"
mtd18: 0010 0004 "nand_rcw"
mtd19: 0020 0004 "nand_uboot"
mtd20: 0010 0004 "nand_uboot_env"
mtd21: 0020 0004 "nand_ppa"
mtd22: 0030 0004 "nand_secure_boot"
mtd23: 0060 0004 "nand_dppa_qe"
mtd24: 0010 0004 "nand_dtb"
mtd25: 0100 0004 "nand_kernel"
mtd26: 0200 0004 "nand_rootfs"
mtd27: 1c00 0004 "nand_free"
mtd28: 0100 0001 "spi0_free"
mtd29: 0008 1000 "spi1_free"
mtd30: 0080 1000 "spi2_free"

Signed-off-by: Bao Xiaowei <xiaowei@nxp.com>
---
 include/configs/ls1046aqds.h | 28 +---
 1 file changed, 17 insertions(+), 11 deletions(-)

diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 5d2e819..57aed04 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -479,17 +479,23 @@ unsigned long get_board_ddr_clk(void);
 #define MTDPARTS_DEFAULT "mtdparts=155.quadspi:2m(uboot)," \
"14m(free)"
 #else
-#define MTDPARTS_DEFAULT "mtdparts=6000.nor:" \
-   "2m@0x10(nor_bank0_uboot),"\
-   "40m@0x110(nor_bank0_fit)," \
-   "7m(nor_bank0_user)," \
-   "2m@0x410(nor_bank4_uboot)," \
-   "40m@0x510(nor_bank4_fit),"\
-   "-(nor_bank4_user);" \
-   "7e80.flash:" \
-   "4m(nand_uboot),36m(nand_kernel)," \
-   "472m(nand_free);spi0.0:2m(uboot)," \
-   "14m(free)"
+#define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \
+   "2m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
+   "2m(nor_bank0_ppa),3m(nor_bank0_secure_boot)," \
+   "6m(nor_bank0_dppa_qe),1m(nor_bank0_dtb)," \
+   "16m(nor_bank0_kernel),32m(nor_bank0_rootfs)," \
+   "1m(nor_bank4_rcw),2m(nor_bank4_uboot)," \
+   "2m(nor_bank4_uboot_env),1m(nor_bank4_ppa)," \
+   "3m(nor_bank4_secure_boot),6m(nor_bank4_dppa_qe)," \
+   "1m(nor_bank4_dtb),16m(nor_bank4_kernel)," \
+   "32m(nor_bank4_rootfs);7e80.flash:" \
+   "1m(nand_rcw),2m(nand_uboot)," \
+   "1m(nand_uboot_env),2m(nand_ppa)," \
+   "3m(nand_secure_boot),6m(nand_dppa_qe)," \
+   "1m(nand_dtb),16m(nand_kernel)," \
+   "32m(nand_rootfs),448m(nand_free);" \
+   "spi0.0:16m(spi0_free);" \
+   "spi0.1:512k(spi1_free);spi0.2:8m(spi2_free)"
 #endif
 
 #include 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] Powerpc: T208xQDS: Modify the comment of the CONFIG_FSL_PCIE_RESET macro

[U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state judgement more specific

[U-Boot] [PATCH 2/3] Powerpc: pcie: optmize the code of pci init function

[U-Boot] [PATCH 1/3] fsl/pci: fix leading whitespace of PCI_LTSSM_L0

[U-Boot] [PATCH] Powerpc: Make pcie link state judge more specific

[U-Boot] [PATCH] PCI: layerscape: Make the pcie link up status judgement more specific

[U-Boot] [PATCH] armv8: layerscape platform pcie link up state judgment strongly

[U-Boot] [PATCH] ls1046aqds: update the defaule mtdparts

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