Re: [PATCH v2] config: imx: Define CFG_SYS_UBOOT_BASE for Phytec's imx8mm SoM QSPI boot

[Benjamin Hahn]

Hi Lukasz,

On 28.08.24 09:55, Lukasz Majewski wrote:
> Hi Fabio,
>
>> Hi Lukasz,
>>
>> On Tue, Aug 20, 2024 at 12:00 PM Lukasz Majewski 
>> wrote:
>>> The image offset when booting from SPI-NOR (QSPI, FSPI driver) is
>>> different than one for SD card / eMMC as extra space (0x1000) is
>>> consumed by FSPI configuration header (CONFIG_FSPI_CONF_HEADER).
>>>
>>> Signed-off-by: Lukasz Majewski 
>>> ---
>>> Changes for v2:
>>> - Avoid line breaks with defines
>>  From the other thread, my understanding is that QSPI boot is still not
>> working with this patch applied.
>>
> But this is an orthogonal problem - the problem is with binman image
> generation.
>
> This patch follows the code already present in e.g. imx8mm_beacon*
> boards.
>
>> Please resend this patch when the QSPI boot problem is resolved.
>>
> As I've written above - problem is solely with binman code generation -
> after reverting 3 last commits from imx8mm-u-boot.dtsi the image is
> correctly generated.

I can also see this. When I apply all your patches and revert those 3 
commits, SDP boot via uuu and flashing SPI NOR flash with the qspi Image 
works. And then also SPI boot works.
When I don't revert the 3 commit, it does not work. (SDP boot via uuu 
does not work and the Image does not boot when flashed into SPI NOR flash).

I haven't investigated what the problem is or how it can be fixed 
though. So I guess further investigation is needed here.

Benjamin

>
>> Thanks
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH,  Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de

[PATCH 0/2] phycore-imx8mp: Add support for SPI NOR flash

[Benjamin Hahn]

Add support for flashing and booting from spi nor flash.

Signed-off-by: Benjamin Hahn 
---
Benjamin Hahn (2):
  configs: phycore-imx8mp_defconfig: Enable SPI NOR flash support
  board: phytec: phycore_imx8mp: Add mtd spi partitions

 board/phytec/phycore_imx8mp/phycore-imx8mp.c   | 34 ++
 board/phytec/phycore_imx8mp/phycore_imx8mp.env |  4 +++
 configs/phycore-imx8mp_defconfig   | 24 ++
 3 files changed, 62 insertions(+)
---
base-commit: ee2af844ba1b27b2e959c4e649e4b769fbeb4074
change-id: 20240826-wip-bhahn-add_qspi_support-61200b09e4eb

Best regards,
-- 
Benjamin Hahn 

[PATCH 2/2] board: phytec: phycore_imx8mp: Add mtd spi partitions

[Benjamin Hahn]

Depending on if a SPI-NOR flash is populated add the mtd partition
table to the device tree. For this we have to also probe the
flash before booting.

Signed-off-by: Benjamin Hahn 
---
 board/phytec/phycore_imx8mp/phycore-imx8mp.c   | 34 ++
 board/phytec/phycore_imx8mp/phycore_imx8mp.env |  4 +++
 2 files changed, 38 insertions(+)

diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c 
b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
index ef9513618449..bf2d5ce01fa5 100644
--- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
+++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
@@ -10,10 +10,34 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
+#include 
+
+#include "../common/imx8m_som_detection.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define EEPROM_ADDR0x51
+#define EEPROM_ADDR_FALLBACK   0x59
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+   u8 spi = phytec_get_imx8m_spi(NULL);
+   /* Do nothing if no SPI is populated */
+   if (!spi)
+   return 0;
+
+   static const struct node_info nodes[] = {
+   { "jedec,spi-nor", MTD_DEV_TYPE_NOR, },
+   };
+
+   fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+   return 0;
+}
+
 static int setup_fec(void)
 {
struct iomuxc_gpr_base_regs *gpr =
@@ -27,6 +51,11 @@ static int setup_fec(void)
 
 int board_init(void)
 {
+   int ret = phytec_eeprom_data_setup_fallback(NULL, 0,
+   EEPROM_ADDR, EEPROM_ADDR_FALLBACK);
+   if (ret)
+   printf("%s: EEPROM data init failed\n", __func__);
+
setup_fec();
 
return 0;
@@ -39,6 +68,11 @@ int board_mmc_get_env_dev(int devno)
 
 int board_late_init(void)
 {
+   u8 spi = phytec_get_imx8m_spi(NULL);
+
+   if (spi != 0 && spi != PHYTEC_EEPROM_INVAL)
+   env_set("spiprobe", "sf probe");
+
switch (get_boot_device()) {
case SD2_BOOT:
env_set_ulong("mmcdev", 1);
diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env 
b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
index f8f878e8f3a6..e5b49756132a 100644
--- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env
+++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
@@ -7,6 +7,7 @@ bootcmd=
fi;
mmc dev ${mmcdev};
if mmc rescan; then
+   run spiprobe;
if test ${doraucboot} = 1; then
run raucinit;
fi;
@@ -27,6 +28,9 @@ fdt_addr_r=0x4800
 fdtfile=CONFIG_DEFAULT_FDT_FILE
 image=Image
 ip_dyn=yes
+mtdparts=30bb.spi:3840k(u-boot),128k(env),128k(env_redund),-(none)
+mtdids=nor0=30bb.spi
+spiprobe=true
 loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
 loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
 mmcargs=

-- 
2.34.1

[PATCH 1/2] configs: phycore-imx8mp_defconfig: Enable SPI NOR flash support

[Benjamin Hahn]

Enable SPI NOR flash support in U-Boot.

Signed-off-by: Benjamin Hahn 
---
 configs/phycore-imx8mp_defconfig | 24 
 1 file changed, 24 insertions(+)

diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 63f8a80ba994..7f6e6c67bfd2 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -6,8 +6,10 @@ CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_PHYTEC_SOM_DETECTION=y
+CONFIG_SF_DEFAULT_SPEED=8000
 CONFIG_ENV_SIZE=0x1
 CONFIG_ENV_OFFSET=0x3C
+CONFIG_ENV_SECT_SIZE=0x1
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk"
@@ -29,7 +31,9 @@ CONFIG_SYS_LOAD_ADDR=0x4048
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
 CONFIG_DEFAULT_FDT_FILE="oftree"
 CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
@@ -48,7 +52,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
 # CONFIG_SPL_CRYPTO is not set
 CONFIG_SPL_I2C=y
+CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_FLASH_MTD=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="u-boot=> "
@@ -64,6 +70,8 @@ CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
@@ -77,10 +85,12 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=2
@@ -113,6 +123,17 @@ CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_ES_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_TI_DP83867=y
 CONFIG_DM_ETH_PHY=y
@@ -134,6 +155,9 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_POWER_I2C=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y

-- 
2.34.1

Re: [PATCH] config: imx: Add support for Phytec's phycore imx8mm running SDP gadget

[Benjamin Hahn]

Hi Lukasz,

On 21.08.24 12:10, Lukasz Majewski wrote:
> Hi Benjamin,
>
>> On 19.08.24 16:36, Lukasz Majewski wrote:
>>> Hi Benjamin,
>>>   
 Hi Lukasz,
 did you test this? It does not work for me. When I try it, the
 U-Boot hangs in SPL. Here is what I got:
From Host:

 bhahn@llp-hahn:~/git-repos/u-boot$ sudo uuu -b spl
 build/mini/flash.bin uuu (Universal Update Utility) for nxp imx
 chips -- lib1.4.193

 Success 0    Failure 0


 7:3  1/ 1 [=100%=] SDP: boot -f
 build/mini/flash.bin
   
>>> Please test this branch:
>>> https://github.com/lmajewski/u-boot/commits/phycore-imx8mm-qspi-nvme
>>>
>>> On HOST:
>>> uuu -v -b qspi ~/work/DENX/u-boot/flash.bin
>>>
>>> Stop on u-boot prompt.
>>>
>>> u-boot=> fastboot 0
>>>
>>> QSPI is flashed via USB - however - I've noticed that there are some
>>> flipped bits on USB transmission when I do compare it with tftp
>>> transfer.
>>>
>>> This needs to be investigated, however seems to be an orthogonal
>>> problem from QSPI boot support.
>> I tested your branch. Your commands seem to work. Here is the log:
>>
>>
>> U-Boot SPL 2024.10-rc2-g718c0f57cacb (Aug 21 2024 - 10:12:26 +0200)
>> WDT:   Started watchdog@3028 with servicing every 1000ms (60s
>> timeout) Trying to boot from USB SDP
>> SDP: initialize...
>> SDP: handle requests...
>> Downloading file of size 984992 to 0x4040... done
>> Jumping to header at 0x4040
>> Header Tag is not an IMX image
>> Found header at 0x40424a00
>> NOTICE:  BL31: v2.6(release):lf-5.15.71-2.2.1-0-gf4540f956
>> NOTICE:  BL31: Built : 06:10:48, Apr 13 2023
>>
>>
>> U-Boot 2024.10-rc2-g718c0f57cacb (Aug 21 2024 - 10:12:26 +0200)
>>
>> CPU:   Freescale i.MX8MMQ rev1.0 1600 MHz (running at 1200 MHz)
>> CPU:   Industrial temperature grade (-40C to 105C) at 42C
>> Reset cause: POR
>> Model: PHYTEC phyBOARD-Polis-i.MX8MM RDK
>> DRAM:  2 GiB
>> Core:  114 devices, 28 uclasses, devicetree: separate
>> WDT:   Started watchdog@3028 with servicing every 1000ms (60s
>> timeout) MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
>> Loading Environment from MMC... *** Warning - bad CRC, using default
>> environment
>>
>> Reading from MMC(2)... In:    serial@3088
>> Out:   serial@3088
>> Err:   serial@3088
>> Net:   eth0: ethernet@30be
>> Hit any key to stop autoboot:  0
>> u-boot=> fastboot 0
>> Starting download of 1194400 bytes
>> .
>> downloading of 1194400 bytes finished
>> Unknown command 'qspihdr' - try 'help'
>> SF: Detected n25q256ax1 with page size 256 Bytes, erase size 64 KiB,
>> total 32 MiB
>> SF: 1245184 bytes @ 0x0 Erased: OK
>> device 0 offset 0x0, size 0x1239a0
>> SF: 1194400 bytes @ 0x0 Written: OK
>>
> Ok.
>
>> I noticed this message in the log though:
>>
>> Unknown command 'qspihdr' - try 'help'
>>
> The same "Unknown command" was also present on my site.
>
>> Booting over qspi does not work. Probably because it is not a
>> dedicated qspi flash image (does not get flashed with the correct
>> offset).
> Are you using imx8mm or imx8mn ?
I use imx8mm (phyboard-polis-imx8mm-5 machine).
>
> Please check if you have:
> https://github.com/lmajewski/u-boot/commit/d33a67756c7a29618ececcfd9a9d2def3b1f9af0
>
> on your board added.

I used the branch you sent me to build the flash.bin binary. And yes 
this commit is included in your branch.

>
> If possible - you can use tftp to download the flash.bin to your board?
>
> setenv serverip 10.0.0.81;dhcp flash-fspi.bin; sf probe; sf
> erase 0x0 0x20; sf write 0x4048 0x0 0x20
> sf erase 0x40 0x10
Yes, tested it with these commands. I get the same result as when I load 
it from the sdcard (identical image is read back from the qspi flash 
after flashing).
>
>> About some bits getting flipped:
>> For me it is not just some bits getting flipped. I read back the
>> image from /dev/mtd0 with the dd command and compare the hexdump
>> ouput to the original image. Theoretically it should identical, but
>> that is not the case. There are not just some flipped bits, but the
>> Image flashed via uuu looks like a completely different image.
> Ok - strange...
>
> Then uuu (and USB) needs to be debugged.
>
>> I also
>> tested flashing with dd in linux and in U-Boot with loading the image
>> via fatload from the sdcard and flashing it with "sf update
>> ${loadaddr} 0 ${filesize}". With those two flashing methods I get an
>> Image that is identical to the original Image when I read it back, as
>> I would expect.
> Ok.
>
> Just to be 100% sure - are you able to boot from QSPI with the
> flash.bin build from
> https://github.com/lmajewski/u-boot/commits/phycore-imx8mm-qspi-nvme

No. Does not work for me. When I reset after flashing and set the boot 
switches to qspi flash boot, nothing comes up. The Image boots fine from 
sdcard though when flashed with the correct offset (33k).

To me it looks like there is no offset in the image and I see that we 
flash the image 

Re: [PATCH] config: imx: Add support for Phytec's phycore imx8mm running SDP gadget

[Benjamin Hahn]

On 19.08.24 16:36, Lukasz Majewski wrote:
> Hi Benjamin,
>
>> Hi Lukasz,
>> did you test this? It does not work for me. When I try it, the U-Boot
>> hangs in SPL. Here is what I got:
>>   From Host:
>>
>> bhahn@llp-hahn:~/git-repos/u-boot$ sudo uuu -b spl
>> build/mini/flash.bin uuu (Universal Update Utility) for nxp imx chips
>> -- lib1.4.193
>>
>> Success 0    Failure 0
>>
>>
>> 7:3  1/ 1 [=100%=] SDP: boot -f
>> build/mini/flash.bin
>>
> Please test this branch:
> https://github.com/lmajewski/u-boot/commits/phycore-imx8mm-qspi-nvme
>
> On HOST:
> uuu -v -b qspi ~/work/DENX/u-boot/flash.bin
>
> Stop on u-boot prompt.
>
> u-boot=> fastboot 0
>
> QSPI is flashed via USB - however - I've noticed that there are some
> flipped bits on USB transmission when I do compare it with tftp
> transfer.
>
> This needs to be investigated, however seems to be an orthogonal
> problem from QSPI boot support.

I tested your branch. Your commands seem to work. Here is the log:


U-Boot SPL 2024.10-rc2-g718c0f57cacb (Aug 21 2024 - 10:12:26 +0200)
WDT:   Started watchdog@3028 with servicing every 1000ms (60s timeout)
Trying to boot from USB SDP
SDP: initialize...
SDP: handle requests...
Downloading file of size 984992 to 0x4040... done
Jumping to header at 0x4040
Header Tag is not an IMX image
Found header at 0x40424a00
NOTICE:  BL31: v2.6(release):lf-5.15.71-2.2.1-0-gf4540f956
NOTICE:  BL31: Built : 06:10:48, Apr 13 2023


U-Boot 2024.10-rc2-g718c0f57cacb (Aug 21 2024 - 10:12:26 +0200)

CPU:   Freescale i.MX8MMQ rev1.0 1600 MHz (running at 1200 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 42C
Reset cause: POR
Model: PHYTEC phyBOARD-Polis-i.MX8MM RDK
DRAM:  2 GiB
Core:  114 devices, 28 uclasses, devicetree: separate
WDT:   Started watchdog@3028 with servicing every 1000ms (60s timeout)
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... *** Warning - bad CRC, using default 
environment

Reading from MMC(2)... In:    serial@3088
Out:   serial@3088
Err:   serial@3088
Net:   eth0: ethernet@30be
Hit any key to stop autoboot:  0
u-boot=> fastboot 0
Starting download of 1194400 bytes
.
downloading of 1194400 bytes finished
Unknown command 'qspihdr' - try 'help'
SF: Detected n25q256ax1 with page size 256 Bytes, erase size 64 KiB, 
total 32 MiB
SF: 1245184 bytes @ 0x0 Erased: OK
device 0 offset 0x0, size 0x1239a0
SF: 1194400 bytes @ 0x0 Written: OK


I noticed this message in the log though:

Unknown command 'qspihdr' - try 'help'


Booting over qspi does not work. Probably because it is not a dedicated 
qspi flash image (does not get flashed with the correct offset).

About some bits getting flipped:
For me it is not just some bits getting flipped. I read back the image 
from /dev/mtd0 with the dd command and compare the hexdump ouput to the 
original image. Theoretically it should identical, but that is not the 
case. There are not just some flipped bits, but the Image flashed via 
uuu looks like a completely different image. I also tested flashing with 
dd in linux and in U-Boot with loading the image via fatload from the 
sdcard and flashing it with "sf update ${loadaddr} 0 ${filesize}". With 
those two flashing methods I get an Image that is identical to the 
original Image when I read it back, as I would expect.

Benjamin

>
>> Log on target:
>>
>> U-Boot SPL 2024.10-rc2-00131-g0303f2240376 (Aug 19 2024 - 15:18:36
>> +0200) WDT:   Started watchdog@3028 with servicing every 1000ms
>> (60s timeout) Trying to boot from USB SDP
>>
>> U-Boot SPL 2024.10-rc2-00131-g0303f2240376 (Aug 19 2024 - 15:18:36
>> +0200) WDT:   Started watchdog@3028 with servicing every 1000ms
>> (60s timeout) Trying to boot from USB SDP
>>
>> To me it looks like there are some changes missing to get this
>> feature to work.
>> You can take a look at my commits where I added this feature for
>> imx8mp. 199229e28b2b2da57c52ee46452f930785cf6002 ("phycore-imx8mp:
>> add USB mass storage support")
>> 8dcf1df48dff339b172d1bce2a38a965ee4aafca ("phycore-imx8mp: add
>> support for booting and flashing emmc via UUU")
>>
>>
>> Here are the changes I needed to do on top of your patch to get this
>> feature to work for mini:
>>
>> diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
>> b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
>> index 516e52e1f5de..cdaff2f8da9b 100644
>> --- a/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
>> +++ b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
>> @@ -69,3 +69,8 @@
>>    &wdog1 {
>>       bootph-pre-ram;
>>    };
>> +
>> +&usbotg1 {
>> +   dr_mode = "peripheral";
>> +   u-boot,dm-spl;
>> +};
>> diff --git a/board/phytec/phycore_imx8mm/phycore-imx8mm.c
>> b/board/phytec/phycore_imx8mm/phycore-imx8mm.c
>> index 06cffbca3a69..00fdd4edbe36 100644
>> --- a/board/phytec/phycore_imx8mm/phycore-imx8mm.c
>> +++ b/board/phytec/phycore_imx8mm/phycore-imx8mm.c
>> @@ -45,6 +45,10 @@ int bo

Re: [PATCH] config: imx: Add support for Phytec's phycore imx8mm running SDP gadget

[Benjamin Hahn]

Hi Lukasz,
did you test this? It does not work for me. When I try it, the U-Boot 
hangs in SPL. Here is what I got:
 From Host:

bhahn@llp-hahn:~/git-repos/u-boot$ sudo uuu -b spl build/mini/flash.bin
uuu (Universal Update Utility) for nxp imx chips -- lib1.4.193

Success 0    Failure 0


7:3  1/ 1 [=100%=] SDP: boot -f 
build/mini/flash.bin


Log on target:

U-Boot SPL 2024.10-rc2-00131-g0303f2240376 (Aug 19 2024 - 15:18:36 +0200)
WDT:   Started watchdog@3028 with servicing every 1000ms (60s timeout)
Trying to boot from USB SDP

U-Boot SPL 2024.10-rc2-00131-g0303f2240376 (Aug 19 2024 - 15:18:36 +0200)
WDT:   Started watchdog@3028 with servicing every 1000ms (60s timeout)
Trying to boot from USB SDP

To me it looks like there are some changes missing to get this feature 
to work.
You can take a look at my commits where I added this feature for imx8mp.
199229e28b2b2da57c52ee46452f930785cf6002 ("phycore-imx8mp: add USB mass 
storage support")
8dcf1df48dff339b172d1bce2a38a965ee4aafca ("phycore-imx8mp: add support 
for booting and flashing emmc via UUU")


Here are the changes I needed to do on top of your patch to get this 
feature to work for mini:

diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi 
b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
index 516e52e1f5de..cdaff2f8da9b 100644
--- a/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
@@ -69,3 +69,8 @@
  &wdog1 {
     bootph-pre-ram;
  };
+
+&usbotg1 {
+   dr_mode = "peripheral";
+   u-boot,dm-spl;
+};
diff --git a/board/phytec/phycore_imx8mm/phycore-imx8mm.c 
b/board/phytec/phycore_imx8mm/phycore-imx8mm.c
index 06cffbca3a69..00fdd4edbe36 100644
--- a/board/phytec/phycore_imx8mm/phycore-imx8mm.c
+++ b/board/phytec/phycore_imx8mm/phycore-imx8mm.c
@@ -45,6 +45,10 @@ int board_late_init(void)
     case MMC3_BOOT:
     env_set_ulong("mmcdev", 2);
     break;
+   case USB_BOOT:
+   printf("Detect USB boot. Will enter fastboot mode!\n");
+   env_set_ulong("dofastboot", 1);
+   break;
     default:
     break;
     }
diff --git a/configs/phycore-imx8mm_defconfig 
b/configs/phycore-imx8mm_defconfig
index beb2f1e9f031..e8d3ffe8c05d 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -31,7 +31,7 @@ CONFIG_FIT_EXTERNAL_OFFSET=0x3000
  CONFIG_SPL_LOAD_FIT=y
  CONFIG_OF_SYSTEM_SETUP=y
  CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run 
loadimage; then run mmcboot; else run netboot; fi; fi;"
+CONFIG_BOOTCOMMAND="if test ${dofastboot} = 1; then fastboot 0; fi; mmc 
dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; 
else run netboot; fi; fi;"
  CONFIG_DEFAULT_FDT_FILE="oftree"
  CONFIG_SYS_CBSIZE=2048
  CONFIG_SYS_PBSIZE=2074
@@ -153,3 +153,11 @@ CONFIG_CI_UDC=y
  CONFIG_SDP_LOADADDR=0x4040
  CONFIG_SPL_USB_SDP_SUPPORT=y
  CONFIG_IMX_WATCHDOG=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc2boot0"
+CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc2boot1"
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_NAME="mmc2"
diff --git a/include/configs/phycore_imx8mm.h 
b/include/configs/phycore_imx8mm.h
index dd7cfdba52d2..f3a750089dd5 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h
@@ -26,6 +26,11 @@
     "fdt_addr=0x4800\0" \
     "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
     "ip_dyn=yes\0" \
+   "dofastboot=0\0" \
+   "fastboot_raw_partition_bootloader=66 8128\0" \
+   "fastboot_raw_partition_all=0 4194304\0" \
+   "emmc_dev=2\0" \
+   "sd_dev=1\0" \
     "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
     "mmcpart=1\0" \
     "mmcroot=2\0" \


With these changes booting via SDP with uuu and flashing emmc with uuu 
should work. Sadly I did not find a way to be able to flash eMMC and 
SD-Card over uuu with the same bootloader because it was necessary for 
me to specify the device to flash in CONFIG_FASTBOOT_FLASH_MMC_DEV.

with kind regards,
Benjamin

On 15.08.24 10:45, Lukasz Majewski wrote:
> After this change it would be possible to boot SDP gadget when Phytec's
> Phycore imx8mm module has USB ROM boot selected.
>
> With this change it shall be possible to flash eMMC/SD card content with
> uuu program.
>
> Signed-off-by: Lukasz Majewski 
> ---
>   configs/phycore-imx8mm_defconfig | 18 +-
>   1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/configs/phycore-imx8mm_defconfig 
> b/configs/phycore-imx8mm_defconfig
> index 6748e6fafb..beb2f1e9f0 100644
> --- a/configs/phycore-imx8mm_defconfig
> +++ b/configs/phycore-imx8mm_defconfig
> @@ -25,6 +25,7 @@ CONFIG_SPL=y
>   CONFIG_ENV_OFFSET_REDUND=0x3E
>   CONFIG_SYS_LOAD_ADDR=0x4048

Re: [PATCH v4] config: Add 'update_bootimg' command to update flash.bin on Phytec's imx8mm

[Benjamin Hahn]

On 09.08.24 18:53, Lukasz Majewski wrote:
> This command allows easy update on SD card or eMMC of the flash.bin
> generated (with binman) during u-boot build.
>
> Signed-off-by: Lukasz Majewski 
Reviewed-by: Benjamin Hahn 
> ---
> Changes for v2:
> - Remove 'update_mmc_part' variable
> - Change path for hostname
> - Use full version of dhcp command (${loadaddr} added)
>
> Changes for v3:
> - Remove +1 when calculating the size of binary to be written
>
> Changes for v4:
> - Replace ${hostname} with ${update_filepath}
> ---
>   include/configs/phycore_imx8mm.h | 8 
>   1 file changed, 8 insertions(+)
>
> diff --git a/include/configs/phycore_imx8mm.h 
> b/include/configs/phycore_imx8mm.h
> index dd7cfdba52..0910ae2d87 100644
> --- a/include/configs/phycore_imx8mm.h
> +++ b/include/configs/phycore_imx8mm.h
> @@ -29,6 +29,14 @@
>   "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
>   "mmcpart=1\0" \
>   "mmcroot=2\0" \
> + "update_offset=0x42\0" \
> + "update_filename=flash.bin\0" \
> + "update_bootimg="   \
> + "mmc dev ${mmcdev} ; "  \
> + "if dhcp ${loadaddr} ${update_filepath}/${update_filename} ; 
> then " \
> + "setexpr fw_sz ${filesize} / 0x200 ; "  /* SD block size */ \
> + "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; "\
> + "fi\0" \
>   "mmcautodetect=yes\0" \
>   "mmcargs=setenv bootargs console=${console} " \
>   "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \

Re: [PATCH v3] config: Add 'update_bootimg' command to update flash.bin on Phytec's imx8mm

[Benjamin Hahn]

Hi Lukasz,

On 06.08.24 10:11, Lukasz Majewski wrote:
> This command allows easy update on SD card or eMMC of the flash.bin
> generated (with binman) during u-boot build.
>
> Signed-off-by: Lukasz Majewski 
> ---
> Changes for v2:
> - Remove 'update_mmc_part' variable
> - Change path for hostname
> - Use full version of dhcp command (${loadaddr} added)
>
> Changes for v3:
> - Remove +1 when calculating the size of binary to be written
> ---
>   include/configs/phycore_imx8mm.h | 10 ++
>   1 file changed, 10 insertions(+)
>
> diff --git a/include/configs/phycore_imx8mm.h 
> b/include/configs/phycore_imx8mm.h
> index ce6dc87c69..361e665676 100644
> --- a/include/configs/phycore_imx8mm.h
> +++ b/include/configs/phycore_imx8mm.h
> @@ -29,6 +29,16 @@
>   "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
>   "mmcpart=1\0" \
>   "mmcroot=2\0" \
> + "update_offset=0x42\0" \
> + "update_filename=flash.bin\0" \
> + "hostname=/srv/tftp/\0" \
> + "update_bootimg="   \
> + "mmc dev ${mmcdev} ; "  \
> + "if dhcp ${loadaddr} ${hostname}/${update_filename} ; then "
> \

The dhcp and tftp command should take the filepath from the tftp 
directory and get the tftp directory automatically not the absolute path.
So this will try to get the file from 
/path_to_tftp_folder/srv/tftp/flash.bin and will fail because it can't 
find it. So you can drop the ${hostname}.
Also drop the initialization of ${hostname} above since it is no longer 
needed.

Should be like this:

dhcp ${loadaddr} ${update_filename}

> + "setexpr fw_sz ${filesize} / 0x200 ; "  /* SD block size */ \
> + "setexpr fw_sz ${fw_sz} ; "
I think you can drop this line since it does not do anything.

Benjamin
>   \
> + "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; "\
> + "fi\0" \
>   "mmcautodetect=yes\0" \
>   "mmcargs=setenv bootargs console=${console} " \
>   "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \

Re: [PATCH 1/2] config: Add 'update_bootimg' command to update flash.bin on Phytec's imx8mm

[Benjamin Hahn]

Hi Lukasz,

On 01.08.24 14:54, Lukasz Majewski wrote:
> This command allows easy update on SD card (hence the update_mmc_part=1)
> of the flash.bin generated during u-boot build.
>
> Signed-off-by: Lukasz Majewski 
> ---
>   include/configs/phycore_imx8mm.h | 11 +++
>   1 file changed, 11 insertions(+)
>
> diff --git a/include/configs/phycore_imx8mm.h 
> b/include/configs/phycore_imx8mm.h
> index ce6dc87c69..fdeb11933f 100644
> --- a/include/configs/phycore_imx8mm.h
> +++ b/include/configs/phycore_imx8mm.h
> @@ -29,6 +29,17 @@
>   "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
>   "mmcpart=1\0" \
>   "mmcroot=2\0" \
> + "update_mmc_part=1\0" \

You define the update_mmc_part variable here, but do not use it 
anywhere. You use the mmcdev variable later which is good, because the 
function then works not only for SD-Card, but also for eMMC.

In the commit description you say it is for updating SD-Card, which 
would be mmc dev 1, but the name of the variable would indicate that is 
is for a partition.
As I understand it you want to update just the U-Boot, which is not 
inside any partition, so you would not need this variable.

> + "update_offset=0x42\0" \
> + "update_filename=flash.bin\0" \
> + "hostname=/tftpboot/lukma/\0" \
We adivse to use /srv/tftp  as tftp dir in our BSP documentation. But I 
don't think you need that variable at all, because the dhcp command 
should find the tftp dir automatically.
> + "update_bootimg="   \
> + "mmc dev ${mmcdev} ; "  \
> + "if dhcp ${hostname}/${update_filename} ; then "\

Does this work? For me it does not. As far as I know the syntax of this command 
is "dhcp  ".
So I would expect this to be:
dhcp ${loadaddr} ${update_filename}

> + "setexpr fw_sz ${filesize} / 0x200 ; "  /* SD block size */ \
> + "setexpr fw_sz ${fw_sz} + 1 ; " \
Why do you add one here? Is this important for something? For me it 
works also without the one.
It is also described in our BSP documentation without adding one. See:
https://phytec.github.io/doc-bsp-yocto/bsp/imx8/imx8mp/mainline-head.html#flash-emmc-u-boot-image-via-network-from-running-u-boot
 

(This is for our imx8mp mainline release but is the same for imx8mm with 
another offset).

Benjamin
> + "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; "\
> + "fi\0" \
>   "mmcautodetect=yes\0" \
>   "mmcargs=setenv bootargs console=${console} " \
>   "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \

Re: [PATCH] configs: phycore-imx8mp: Disable CONFIG_ANDROID_BOOT_IMAGE

[Benjamin Hahn]

Hello,
Please do not apply. We will leave this feature enabled for now.

Benjamin
On 03.07.24 15:42, Benjamin Hahn wrote:
> CONFIG_ANDROID_BOOT_IMAGE gets enabled implicitly by FASTBOOT, but we
> don't need that feature.
>
> Signed-off-by: Benjamin Hahn 
> ---
>   configs/phycore-imx8mp_defconfig | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/configs/phycore-imx8mp_defconfig 
> b/configs/phycore-imx8mp_defconfig
> index 57e320af6030..280ebc9237ee 100644
> --- a/configs/phycore-imx8mp_defconfig
> +++ b/configs/phycore-imx8mp_defconfig
> @@ -25,6 +25,7 @@ CONFIG_SPL=y
>   CONFIG_ENV_OFFSET_REDUND=0x3e
>   CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800
>   CONFIG_SYS_LOAD_ADDR=0x4048
> +# CONFIG_ANDROID_BOOT_IMAGE is not set
>   CONFIG_FIT=y
>   CONFIG_FIT_EXTERNAL_OFFSET=0x3000
>   CONFIG_SPL_LOAD_FIT=y
>
> ---
> base-commit: 65fbdab27224ee3943a89496b21862db83c34da2
> change-id: 20240703-wip-bhahn-disable_config_android_boot_image-326ea0921a03
>
> Best regards,

[PATCH] configs: phycore-imx8mp: Disable CONFIG_ANDROID_BOOT_IMAGE

[Benjamin Hahn]

CONFIG_ANDROID_BOOT_IMAGE gets enabled implicitly by FASTBOOT, but we
don't need that feature.

Signed-off-by: Benjamin Hahn 
---
 configs/phycore-imx8mp_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 57e320af6030..280ebc9237ee 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -25,6 +25,7 @@ CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0x3e
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800
 CONFIG_SYS_LOAD_ADDR=0x4048
+# CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y

---
base-commit: 65fbdab27224ee3943a89496b21862db83c34da2
change-id: 20240703-wip-bhahn-disable_config_android_boot_image-326ea0921a03

Best regards,
-- 
Benjamin Hahn 

Re: [PATCH] configs: Make USB_GADGET_MANUFACTURER consistent over all PHYTEC boards

[Benjamin Hahn]

Hi Fabio,

On 03.05.24 14:44, Fabio Estevam wrote:
> Hi Benjamin,
>
> On Fri, May 3, 2024 at 4:01 AM Benjamin Hahn  wrote:
>
>> -CONFIG_USB_GADGET_MANUFACTURER="FSL"
>> +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
>>   CONFIG_USB_GADGET_VENDOR_NUM=0x0525
>>   CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> ...
>> -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
>> +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
>>   CONFIG_USB_GADGET_VENDOR_NUM=0x0451
>>   CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
> What about making VENDOR_NUM/PRODUCT_NUM consistent as well?

We are not registered at USB-IF and therefore don't have a valid 
VENDOR_NUM and PRODUCT_NUM, so we rely on the VENDOR_NUM and PRODUCT_NUM 
of the SoC Vendor, so the correct features get enabled by the driver.

With kind regards,

Benjamin Hahn

[PATCH] configs: Make USB_GADGET_MANUFACTURER consistent over all PHYTEC boards

[Benjamin Hahn]

Set CONFIG_USB_GADGET_MANUFACTURER to PHYTEC for all PHYTEC boards.

Signed-off-by: Benjamin Hahn 
---
 configs/phycore-imx8mp_defconfig | 2 +-
 configs/phycore_am64x_a53_defconfig  | 2 +-
 configs/phycore_am64x_r5_defconfig   | 2 +-
 configs/phycore_pcl063_defconfig | 2 +-
 configs/phycore_pcl063_ull_defconfig | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index e9a287cb441f..9f42edd72324 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -147,7 +147,7 @@ CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_IMX_WATCHDOG=y
diff --git a/configs/phycore_am64x_a53_defconfig 
b/configs/phycore_am64x_a53_defconfig
index 1a9359773b45..9b52f8ad0644 100644
--- a/configs/phycore_am64x_a53_defconfig
+++ b/configs/phycore_am64x_a53_defconfig
@@ -159,7 +159,7 @@ CONFIG_USB_CDNS3=y
 CONFIG_USB_CDNS3_GADGET=y
 CONFIG_USB_CDNS3_HOST=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/phycore_am64x_r5_defconfig 
b/configs/phycore_am64x_r5_defconfig
index 61d784fa17f6..15a7e7089e73 100644
--- a/configs/phycore_am64x_r5_defconfig
+++ b/configs/phycore_am64x_r5_defconfig
@@ -171,7 +171,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_SPL_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_SPL_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index 017054a8e12b..2f6b158a6772 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -62,7 +62,7 @@ CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
 CONFIG_SPL_USB_HOST=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Phytec"
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
 CONFIG_CI_UDC=y
diff --git a/configs/phycore_pcl063_ull_defconfig 
b/configs/phycore_pcl063_ull_defconfig
index b3da43a5bf1e..b42a410da69c 100644
--- a/configs/phycore_pcl063_ull_defconfig
+++ b/configs/phycore_pcl063_ull_defconfig
@@ -53,7 +53,7 @@ CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
 CONFIG_SPL_USB_HOST=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Phytec"
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
 CONFIG_CI_UDC=y

---
base-commit: 6fdb021f148f598a67eb3cac5e3eb4a569cdaacd
change-id: 20240503-wip-bhahn-bspimx8m-3196-c1ebd0bab6ac

Best regards,
-- 
Benjamin Hahn 

[PATCH] board: phytec: define get_som_type also when SoM detection is disabled

[Benjamin Hahn]

define the phytec_get_som_type function also when the SoM detection is
disabled.

Fixes:
commit 110d321a56c3 ("board: phytec: common: phytec_som_detection: Add 
phytec_get_som_type")

Signed-off-by: Benjamin Hahn 
---
 board/phytec/common/phytec_som_detection.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/board/phytec/common/phytec_som_detection.c 
b/board/phytec/common/phytec_som_detection.c
index f9607b018dea..a56e0f60d628 100644
--- a/board/phytec/common/phytec_som_detection.c
+++ b/board/phytec/common/phytec_som_detection.c
@@ -248,4 +248,9 @@ u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data 
*data)
return PHYTEC_EEPROM_INVAL;
 }
 
+u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data)
+{
+   return PHYTEC_EEPROM_INVAL;
+}
+
 #endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */

---
base-commit: f3c979dd0053c082d2df170446923e7ce5edbc2d
change-id: 20240312-pcl-070-fix-b7bd8bd74d5b

Best regards,
-- 
Benjamin Hahn 

Re: [PATCH v3 0/2] board: phytec_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1

[Benjamin Hahn]

Hi Fabio,

On 07.03.24 21:26, Fabio Estevam wrote:
> Hi Benjamin,
>
> On Wed, Mar 6, 2024 at 1:18 PM Benjamin Hahn  wrote:
>> PCL-070 supports 2GHz RAM-timings from pcb_rev 1 and newer. PCM-070
>> supports 2GHz RAM-timings only from pcb_rev 3 and newer.
>>
>> Signed-off-by: Benjamin Hahn 
> v3 looks good.
>
> Is this material for U-Boot 2024.04 or 2024.07?

If it can be merged into 2024.04 this would be preferred. Otherwise 
2024.07 would also be okay.

Benjamin

[PATCH v3 2/2] board: phycore_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1

[Benjamin Hahn]

We need to differ between PCL-070 and PCM-070. PCL-070 supports 2GHz RAM
timings from pcb rev 1 or newer. PCM-070 supports 2GHz RAM timings from
pcb rev 3 or newer.

Signed-off-by: Benjamin Hahn 
---
 board/phytec/phycore_imx8mp/spl.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/board/phytec/phycore_imx8mp/spl.c 
b/board/phytec/phycore_imx8mp/spl.c
index d38f6368fe36..df158024654e 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -46,8 +46,10 @@ void spl_dram_init(void)
if (!ret)
phytec_print_som_info(NULL);
 
-   ret = phytec_get_rev(NULL);
-   if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) {
+   u8 rev = phytec_get_rev(NULL);
+   u8 somtype = phytec_get_som_type(NULL);
+
+   if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL 
&& rev >= 1))) {
dram_timing.ddrc_cfg[3].val = 0x1323;
dram_timing.ddrc_cfg[4].val = 0x1e84800;
dram_timing.ddrc_cfg[5].val = 0x7a0118;

-- 
2.34.1

[PATCH v3 0/2] board: phytec_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1

[Benjamin Hahn]

PCL-070 supports 2GHz RAM-timings from pcb_rev 1 and newer. PCM-070
supports 2GHz RAM-timings only from pcb_rev 3 and newer.

Signed-off-by: Benjamin Hahn 
---
Changes in v3:
- change variable name from somtyp to somtype
- change enum names from PCL to SOM_TYPE_PCL
- Link to v2: 
https://lore.kernel.org/r/20240304-pcl-070-patches-v2-0-c534960c4...@phytec.de

Changes in v2:
- Fix mistakes that prevented building
- Link to v1: 
https://lore.kernel.org/r/20240304-pcl-070-patches-v1-0-6aa6c89e3...@phytec.de

---
Benjamin Hahn (2):
  board: phytec: common: phytec_som_detection: Add phytec_get_som_type
  board: phycore_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1

 board/phytec/common/phytec_som_detection.c | 10 ++
 board/phytec/common/phytec_som_detection.h |  8 
 board/phytec/phycore_imx8mp/spl.c  |  6 --
 3 files changed, 22 insertions(+), 2 deletions(-)
---
base-commit: eac52e4be4e234d563d6911737ee7ccdc0ada1f1
change-id: 20240304-pcl-070-patches-d31b989cf5b3

Best regards,
-- 
Benjamin Hahn 

[PATCH v3 1/2] board: phytec: common: phytec_som_detection: Add phytec_get_som_type

[Benjamin Hahn]

Add a function that gets the som_type from the EEPROM.
Add an enum for the som_type.

Signed-off-by: Benjamin Hahn 
---
 board/phytec/common/phytec_som_detection.c | 10 ++
 board/phytec/common/phytec_som_detection.h |  8 
 2 files changed, 18 insertions(+)

diff --git a/board/phytec/common/phytec_som_detection.c 
b/board/phytec/common/phytec_som_detection.c
index c73bf9721b2f..f9607b018dea 100644
--- a/board/phytec/common/phytec_som_detection.c
+++ b/board/phytec/common/phytec_som_detection.c
@@ -203,6 +203,16 @@ u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data 
*data)
return api2->pcb_rev;
 }
 
+u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data)
+{
+   if (!data)
+   data = &eeprom_data;
+   if (data->api_rev < PHYTEC_API_REV2)
+   return PHYTEC_EEPROM_INVAL;
+
+   return data->data.data_api2.som_type;
+}
+
 #else
 
 inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data,
diff --git a/board/phytec/common/phytec_som_detection.h 
b/board/phytec/common/phytec_som_detection.h
index 11009240875c..7edbfa3ca5c6 100644
--- a/board/phytec/common/phytec_som_detection.h
+++ b/board/phytec/common/phytec_som_detection.h
@@ -19,6 +19,13 @@ enum {
PHYTEC_API_REV2,
 };
 
+enum phytec_som_type_str {
+   SOM_TYPE_PCM = 0,
+   SOM_TYPE_PCL,
+   SOM_TYPE_KSM,
+   SOM_TYPE_KSP,
+};
+
 static const char * const phytec_som_type_str[] = {
"PCM",
"PCL",
@@ -67,5 +74,6 @@ void __maybe_unused phytec_print_som_info(struct 
phytec_eeprom_data *data);
 
 char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data);
 u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data);
 
 #endif /* _PHYTEC_SOM_DETECTION_H */

-- 
2.34.1

Re: [PATCH 1/2] board: phytec: common: phytec_som_detection: Add phytec_get_som_type

[Benjamin Hahn]

On 04.03.24 15:42, Fabio Estevam wrote:
> On Mon, Mar 4, 2024 at 9:31 AM Benjamin Hahn  wrote:
>> Add a function that gets the som_type from the EEPROM.
>> Add an enum for the som_type.
>>
>> Signed-off-by: Benjamin Hahn 
> Your series does not even build:
>
> board/phytec/common/phytec_som_detection.c: In function ‘phytec_get_som_type’:
> board/phytec/common/phytec_som_detection.c:210:18: error: ‘struct
> phytec_eeprom_data’ has no member named ‘valid’
>210 | if (!data->valid || data->data.api_rev < PHYTEC_API_REV2)
>|  ^~
> board/phytec/common/phytec_som_detection.c:210:39: error: ‘union
> ’ has no member named ‘api_rev’
>210 | if (!data->valid || data->data.api_rev < PHYTEC_API_REV2)
>|   ^
> board/phytec/common/phytec_som_detection.c:213:26: error: ‘union
> ’ has no member named ‘data’
>213 | return data->data.data.data_api2.som_type;
>|  ^
> board/phytec/common/phytec_som_detection.c:214:1: warning: control
> reaches end of non-void function [-Wreturn-type]
>214 | }
>| ^

Oh, I'm very sorry about that. Seems like I made some mistakes when 
porting the patches to upstream.

I sent a v2, where I fixed them.

Benjamin

[PATCH v2 2/2] board: phycore_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1

[Benjamin Hahn]

We need to differ between PCL-070 and PCM-070. PCL-070 supports 2GHz RAM
timings from pcb rev 1 or newer. PCM-070 supports 2GHz RAM timings from
pcb rev 3 or newer.

Signed-off-by: Benjamin Hahn 
---
 board/phytec/phycore_imx8mp/spl.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/board/phytec/phycore_imx8mp/spl.c 
b/board/phytec/phycore_imx8mp/spl.c
index d38f6368fe36..15a8c75e9982 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -46,8 +46,10 @@ void spl_dram_init(void)
if (!ret)
phytec_print_som_info(NULL);
 
-   ret = phytec_get_rev(NULL);
-   if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) {
+   u8 rev = phytec_get_rev(NULL);
+   u8 somtyp = phytec_get_som_type(NULL);
+
+   if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtyp == PCL && rev >= 
1))) {
dram_timing.ddrc_cfg[3].val = 0x1323;
dram_timing.ddrc_cfg[4].val = 0x1e84800;
dram_timing.ddrc_cfg[5].val = 0x7a0118;

-- 
2.34.1

[PATCH v2 0/2] board: phytec_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1

[Benjamin Hahn]

PCL-070 supports 2GHz RAM-timings from pcb_rev 1 and newer. PCM-070
supports 2GHz RAM-timings only from pcb_rev 3 and newer.

Signed-off-by: Benjamin Hahn 
---
Changes in v2:
- Fix mistakes that prevented building
- Link to v1: 
https://lore.kernel.org/r/20240304-pcl-070-patches-v1-0-6aa6c89e3...@phytec.de

---
Benjamin Hahn (2):
  board: phytec: common: phytec_som_detection: Add phytec_get_som_type
  board: phycore_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1

 board/phytec/common/phytec_som_detection.c | 10 ++
 board/phytec/common/phytec_som_detection.h |  8 
 board/phytec/phycore_imx8mp/spl.c  |  6 --
 3 files changed, 22 insertions(+), 2 deletions(-)
---
base-commit: eac52e4be4e234d563d6911737ee7ccdc0ada1f1
change-id: 20240304-pcl-070-patches-d31b989cf5b3

Best regards,
-- 
Benjamin Hahn 

[PATCH v2 1/2] board: phytec: common: phytec_som_detection: Add phytec_get_som_type

[Benjamin Hahn]

Add a function that gets the som_type from the EEPROM.
Add an enum for the som_type.

Signed-off-by: Benjamin Hahn 
---
 board/phytec/common/phytec_som_detection.c | 10 ++
 board/phytec/common/phytec_som_detection.h |  8 
 2 files changed, 18 insertions(+)

diff --git a/board/phytec/common/phytec_som_detection.c 
b/board/phytec/common/phytec_som_detection.c
index c73bf9721b2f..f9607b018dea 100644
--- a/board/phytec/common/phytec_som_detection.c
+++ b/board/phytec/common/phytec_som_detection.c
@@ -203,6 +203,16 @@ u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data 
*data)
return api2->pcb_rev;
 }
 
+u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data)
+{
+   if (!data)
+   data = &eeprom_data;
+   if (data->api_rev < PHYTEC_API_REV2)
+   return PHYTEC_EEPROM_INVAL;
+
+   return data->data.data_api2.som_type;
+}
+
 #else
 
 inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data,
diff --git a/board/phytec/common/phytec_som_detection.h 
b/board/phytec/common/phytec_som_detection.h
index 11009240875c..c0f0c57a6123 100644
--- a/board/phytec/common/phytec_som_detection.h
+++ b/board/phytec/common/phytec_som_detection.h
@@ -19,6 +19,13 @@ enum {
PHYTEC_API_REV2,
 };
 
+enum phytec_som_type_str {
+   PCM = 0,
+   PCL,
+   KSM,
+   KSP,
+};
+
 static const char * const phytec_som_type_str[] = {
"PCM",
"PCL",
@@ -67,5 +74,6 @@ void __maybe_unused phytec_print_som_info(struct 
phytec_eeprom_data *data);
 
 char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data);
 u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data);
 
 #endif /* _PHYTEC_SOM_DETECTION_H */

-- 
2.34.1

[PATCH 2/2] board: phycore_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1

[Benjamin Hahn]

We need to differ between PCL-070 and PCM-070. PCL-070 supports 2GHz RAM
timings from pcb rev 1 or newer. PCM-070 supports 2GHz RAM timings from
pcb rev 3 or newer.

Signed-off-by: Benjamin Hahn 
---
 board/phytec/phycore_imx8mp/spl.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/board/phytec/phycore_imx8mp/spl.c 
b/board/phytec/phycore_imx8mp/spl.c
index d38f6368fe36..15a8c75e9982 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -46,8 +46,10 @@ void spl_dram_init(void)
if (!ret)
phytec_print_som_info(NULL);
 
-   ret = phytec_get_rev(NULL);
-   if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) {
+   u8 rev = phytec_get_rev(NULL);
+   u8 somtyp = phytec_get_som_type(NULL);
+
+   if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtyp == PCL && rev >= 
1))) {
dram_timing.ddrc_cfg[3].val = 0x1323;
dram_timing.ddrc_cfg[4].val = 0x1e84800;
dram_timing.ddrc_cfg[5].val = 0x7a0118;

-- 
2.34.1

[PATCH 1/2] board: phytec: common: phytec_som_detection: Add phytec_get_som_type

[Benjamin Hahn]

Add a function that gets the som_type from the EEPROM.
Add an enum for the som_type.

Signed-off-by: Benjamin Hahn 
---
 board/phytec/common/phytec_som_detection.c | 10 ++
 board/phytec/common/phytec_som_detection.h |  8 
 2 files changed, 18 insertions(+)

diff --git a/board/phytec/common/phytec_som_detection.c 
b/board/phytec/common/phytec_som_detection.c
index c73bf9721b2f..eaf7659c051d 100644
--- a/board/phytec/common/phytec_som_detection.c
+++ b/board/phytec/common/phytec_som_detection.c
@@ -203,6 +203,16 @@ u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data 
*data)
return api2->pcb_rev;
 }
 
+u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data)
+{
+   if (!data)
+   data = &eeprom_data;
+   if (!data->valid || data->data.api_rev < PHYTEC_API_REV2)
+   return PHYTEC_EEPROM_INVAL;
+
+   return data->data.data.data_api2.som_type;
+}
+
 #else
 
 inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data,
diff --git a/board/phytec/common/phytec_som_detection.h 
b/board/phytec/common/phytec_som_detection.h
index 11009240875c..c0f0c57a6123 100644
--- a/board/phytec/common/phytec_som_detection.h
+++ b/board/phytec/common/phytec_som_detection.h
@@ -19,6 +19,13 @@ enum {
PHYTEC_API_REV2,
 };
 
+enum phytec_som_type_str {
+   PCM = 0,
+   PCL,
+   KSM,
+   KSP,
+};
+
 static const char * const phytec_som_type_str[] = {
"PCM",
"PCL",
@@ -67,5 +74,6 @@ void __maybe_unused phytec_print_som_info(struct 
phytec_eeprom_data *data);
 
 char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data);
 u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data);
 
 #endif /* _PHYTEC_SOM_DETECTION_H */

-- 
2.34.1

[PATCH 0/2] board: phytec_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1

[Benjamin Hahn]

PCL-070 supports 2GHz RAM-timings from pcb_rev 1 and newer. PCM-070
supports 2GHz RAM-timings only from pcb_rev 3 and newer.

Signed-off-by: Benjamin Hahn 
---
Benjamin Hahn (2):
  board: phytec: common: phytec_som_detection: Add phytec_get_som_type
  board: phycore_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1

 board/phytec/common/phytec_som_detection.c | 10 ++
 board/phytec/common/phytec_som_detection.h |  8 
 board/phytec/phycore_imx8mp/spl.c  |  6 --
 3 files changed, 22 insertions(+), 2 deletions(-)
---
base-commit: eac52e4be4e234d563d6911737ee7ccdc0ada1f1
change-id: 20240304-pcl-070-patches-d31b989cf5b3

Best regards,
-- 
Benjamin Hahn 

[PATCH] drivers: imx_tmu: Select polling-rate from cpu-thermal devicetree node

[Benjamin Hahn]

The polling rate is already specified in some devicetrees, like
imx8mp.dtsi for example, but was not selected so far. For the
trippoints, the cpu-thermal node is used. Also get the polling rate from
this node. Use the default of 5000ms if the polling rate should not be
specified in the devicetree.

NOTE: The polling rate from the devicetree will be used after this
patch. In imx8*.dtsi devicetrees the polling delay is set to 2000ms for
example.

Signed-off-by: Benjamin Hahn 
---
 drivers/thermal/imx_tmu.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index 4721cfbc0218..c7fe0f07a607 100644
--- a/drivers/thermal/imx_tmu.c
+++ b/drivers/thermal/imx_tmu.c
@@ -570,12 +570,14 @@ static int imx_tmu_parse_fdt(struct udevice *dev)
 {
struct imx_tmu_plat *pdata = dev_get_plat(dev), *p_parent_data;
struct ofnode_phandle_args args;
-   ofnode trips_np;
+   ofnode trips_np, cpu_thermal_np;
int ret;
 
dev_dbg(dev, "%s\n", __func__);
 
-   pdata->polling_delay = IMX_TMU_POLLING_DELAY_MS;
+   cpu_thermal_np = ofnode_path("/thermal-zones/cpu-thermal");
+   pdata->polling_delay = ofnode_read_u32_default(cpu_thermal_np, 
"polling-delay",
+  
IMX_TMU_POLLING_DELAY_MS);
 
if (pdata->zone_node) {
pdata->regs = (union tmu_regs *)dev_read_addr_ptr(dev);

---
base-commit: eac52e4be4e234d563d6911737ee7ccdc0ada1f1
change-id: 20240304-fix-thermal-driver-issue-34004526aa4f

Best regards,
-- 
Benjamin Hahn 

[PATCH 0/3] Enable IMX_TMU driver for PHYTEC boards

[Benjamin Hahn]

Enable IMX_TMU driver to prevent the system from booting when it is too
hot.

Signed-off-by: Benjamin Hahn 
---
Benjamin Hahn (3):
  phycore-imx8mp_defconfig: Enable CONFIG_IMX_TMU
  phycore-imx8mm_defconfig: Enable CONFIG_IMX_TMU
  imx8mm-phygate-tauri-l_defconfig: Enable CONFIG_IMX_TMU

 configs/imx8mm-phygate-tauri-l_defconfig | 1 +
 configs/phycore-imx8mm_defconfig | 1 +
 configs/phycore-imx8mp_defconfig | 1 +
 3 files changed, 3 insertions(+)
---
base-commit: 3e6f2a94bfc25f1782ce2d45db27f47ec781feb1
change-id: 20240220-thermal-support-3e4f6f09ff5c

Best regards,
-- 
Benjamin Hahn 

[PATCH 1/3] phycore-imx8mp_defconfig: Enable CONFIG_IMX_TMU

[Benjamin Hahn]

Enable the imx thermal driver to prevent booting when the system is too
hot.

Signed-off-by: Benjamin Hahn 
---
 configs/phycore-imx8mp_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 0f37286d5d99..c95554283903 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -138,6 +138,7 @@ CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y

-- 
2.34.1

[PATCH 2/3] phycore-imx8mm_defconfig: Enable CONFIG_IMX_TMU

[Benjamin Hahn]

Enable the imx thermal driver to prevent booting when the system is too
hot.

Signed-off-by: Benjamin Hahn 
---
 configs/phycore-imx8mm_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index bcc38d51a7b9..3a81ea7bd23d 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -128,4 +128,5 @@ CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
 CONFIG_IMX_WATCHDOG=y

-- 
2.34.1

[PATCH 3/3] imx8mm-phygate-tauri-l_defconfig: Enable CONFIG_IMX_TMU

[Benjamin Hahn]

Enable the imx thermal driver to prevent booting when the system is too
hot.

Signed-off-by: Benjamin Hahn 
---
 configs/imx8mm-phygate-tauri-l_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/imx8mm-phygate-tauri-l_defconfig 
b/configs/imx8mm-phygate-tauri-l_defconfig
index 0db3ff890cdd..a416ebc2e04a 100644
--- a/configs/imx8mm-phygate-tauri-l_defconfig
+++ b/configs/imx8mm-phygate-tauri-l_defconfig
@@ -112,4 +112,5 @@ CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
 CONFIG_IMX_WATCHDOG=y

-- 
2.34.1

[PATCH v3 4/4] phycore-imx8mp: add support for booting and flashing emmc via UUU

[Benjamin Hahn]

add support for Serial Downloader Boot via UUU as well as flashing emmc
via UUU on USB0 Port of phyBOARD Pollux.

Reviewed-by: Fabio Estevam 
Signed-off-by: Benjamin Hahn 
---
 board/phytec/phycore_imx8mp/phycore-imx8mp.c |  4 
 configs/phycore-imx8mp_defconfig | 18 --
 include/configs/phycore_imx8mp.h |  5 +
 3 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c 
b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
index a8f0821437..dbdd6bb793 100644
--- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
+++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
@@ -46,6 +46,10 @@ int board_late_init(void)
case MMC3_BOOT:
env_set_ulong("mmcdev", 2);
break;
+   case USB_BOOT:
+   printf("Detect USB boot. Will enter fastboot mode!\n");
+   env_set_ulong("dofastboot", 1);
+   break;
default:
break;
}
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index e3fe4ed94e..0f37286d5d 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -27,7 +27,7 @@ CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; 
then run mmcboot; else run netboot; fi; fi;"
+CONFIG_BOOTCOMMAND="if test ${dofastboot} = 1; then fastboot 0; fi; mmc dev 
${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run 
netboot; fi; fi;"
 CONFIG_DEFAULT_FDT_FILE="oftree"
 CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
@@ -66,6 +66,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
@@ -87,6 +88,17 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_IMX8MP=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x4280
+CONFIG_FASTBOOT_BUF_SIZE=0x1300
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc2boot0"
+CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc2boot1"
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_NAME="mmc2"
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
 # CONFIG_SPL_DM_I2C is not set
@@ -111,6 +123,9 @@ CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
 CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
 CONFIG_POWER_PCA9450=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
@@ -136,5 +151,4 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_IMX_WATCHDOG=y
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index d79d364c8e..11a17be7fe 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -19,6 +19,11 @@
"fdt_addr=0x4800\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"ip_dyn=yes\0" \
+   "dofastboot=0\0" \
+   "fastboot_raw_partition_bootloader=64 8128\0" \
+   "fastboot_raw_partition_all=0 4194304\0" \
+   "emmc_dev=2\0" \
+   "sd_dev=1\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=2\0" \

-- 
2.34.1

[PATCH v3 3/4] phycore-imx8mp: add USB mass storage support

[Benjamin Hahn]

add support for USB mass storage to USB0 port of phyBOARD Pollux.

tested with "ums 0 mmc 2"

Signed-off-by: Benjamin Hahn 
---
 arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 4 
 configs/phycore-imx8mp_defconfig| 7 +++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi 
b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
index 1c7b250549..b4efff27a7 100644
--- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
@@ -70,6 +70,10 @@
bootph-pre-ram;
 };
 
+&usb_dwc3_0 {
+   dr_mode = "peripheral";
+};
+
 &usdhc2 {
bootph-pre-ram;
 };
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 74450b957b..e3fe4ed94e 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -66,6 +66,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -123,6 +124,7 @@ CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
@@ -130,4 +132,9 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_IMX_WATCHDOG=y

-- 
2.34.1

[PATCH v3 1/4] imx8mp-phyboard-pollux-rdk: sync with kernel devicetree from v6.8-rc2

[Benjamin Hahn]

sync devicetree with kernel v6.8-rc2.

New commits on kernel v6.8-rc2:
4a58fcdb1818 arm64: dts: imx8mp-phyboard-pollux: Add support for RS232/RS485
3bd7fdcc359e arm64: dts: imx8mp-phyboard-pollux: Add gpio-line-names
f5faa633daf8 arm64: dts: imx8mp-phyboard-pollux: Enable USB support
27c0dc128d04 arm64: dts: imx8mp-phyboard-pollux: Add flexcan support
fa2a1ec50456 arm64: dts: imx8mp-phyboard-pollux: Add missing usdhc clocks 
assignment
055e38c76388 arm64: dts: imx8mp-phyboard-pollux-rdk: Fix led sub-node names

Signed-off-by: Benjamin Hahn 
---
 arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 162 +++-
 1 file changed, 159 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts 
b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
index 6aa720bafe..c8640cac3e 100644
--- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
@@ -19,6 +19,36 @@
stdout-path = &uart1;
};
 
+   reg_can1_stby: regulator-can1-stby {
+   compatible = "regulator-fixed";
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_flexcan1_reg>;
+   gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
+   regulator-max-microvolt = <330>;
+   regulator-min-microvolt = <330>;
+   regulator-name = "can1-stby";
+   };
+
+   reg_can2_stby: regulator-can2-stby {
+   compatible = "regulator-fixed";
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_flexcan2_reg>;
+   gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
+   regulator-max-microvolt = <330>;
+   regulator-min-microvolt = <330>;
+   regulator-name = "can2-stby";
+   };
+
+   reg_usb1_vbus: regulator-usb1-vbus {
+   compatible = "regulator-fixed";
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_usb1_vbus>;
+   gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
+   regulator-max-microvolt = <500>;
+   regulator-min-microvolt = <500>;
+   regulator-name = "usb1_host_vbus";
+   };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -57,6 +87,21 @@
};
 };
 
+/* CAN FD */
+&flexcan1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_flexcan1>;
+   xceiver-supply = <®_can1_stby>;
+   status = "okay";
+};
+
+&flexcan2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_flexcan2>;
+   xceiver-supply = <®_can2_stby>;
+   status = "okay";
+};
+
 &i2c2 {
clock-frequency = <40>;
pinctrl-names = "default", "gpio";
@@ -76,15 +121,15 @@
compatible = "nxp,pca9533";
reg = <0x62>;
 
-   led1 {
+   led-1 {
type = ;
};
 
-   led2 {
+   led-2 {
type = ;
};
 
-   led3 {
+   led-3 {
type = ;
};
};
@@ -101,8 +146,51 @@
status = "okay";
 };
 
+/* USB1 Host mode Type-A */
+&usb3_phy0 {
+   vbus-supply = <®_usb1_vbus>;
+   status = "okay";
+};
+
+&usb3_0 {
+   status = "okay";
+};
+
+&usb_dwc3_0 {
+   dr_mode = "host";
+   status = "okay";
+};
+
+/* USB2 4-port USB3.0 HUB */
+&usb3_phy1 {
+   status = "okay";
+};
+
+&usb3_1 {
+   fsl,permanently-attached;
+   fsl,disable-port-power-control;
+   status = "okay";
+};
+
+&usb_dwc3_1 {
+   dr_mode = "host";
+   status = "okay";
+};
+
+/* RS232/RS485 */
+&uart2 {
+   assigned-clocks = <&clk IMX8MP_CLK_UART2>;
+   assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart2>;
+   uart-has-rtscts;
+   status = "okay";
+};
+
 /* SD-Card */
 &usdhc2 {
+   assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+   assigned-clock-rates = <2>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
@@ -113,6 +201,33 @@
status = "oka

[PATCH v3 2/4] phycore-imx8mp: add USB host support

[Benjamin Hahn]

The phyBOARD Pollux has two USB ports. Add support for USB host and USB
storage for the USB1 port.

Signed-off-by: Benjamin Hahn 
---
 configs/phycore-imx8mp_defconfig | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 519e0cfb3d..74450b957b 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -65,6 +65,7 @@ CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -104,6 +105,7 @@ CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
 CONFIG_RGMII=y
 CONFIG_MII=y
+CONFIG_PHY_IMX8MQ_USB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
@@ -120,4 +122,12 @@ CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
 CONFIG_IMX_WATCHDOG=y

-- 
2.34.1

[PATCH v3 0/4] phycore-imx8mp: Add USB support

[Benjamin Hahn]

add support for various USB features like USB storage, USB mass storage
as well as booting and flashing emmc via UUU.

Signed-off-by: Benjamin Hahn 
---
Changes in v3:
- add patch description for the sync with kernel devicetree commit
- Link to v2: 
https://lore.kernel.org/r/20240131-usb_support-v2-0-7521c554b...@phytec.de

Changes in v2:
- sync kernel devicetree before making changes
- Link to v1: 
https://lore.kernel.org/r/20240129-usb_support-v1-0-8bd2fe840...@phytec.de

---
Benjamin Hahn (4):
  imx8mp-phyboard-pollux-rdk: sync with kernel devicetree from v6.8-rc2
  phycore-imx8mp: add USB host support
  phycore-imx8mp: add USB mass storage support
  phycore-imx8mp: add support for booting and flashing emmc via UUU

 .../arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi |   4 +
 arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts| 162 -
 board/phytec/phycore_imx8mp/phycore-imx8mp.c   |   4 +
 configs/phycore-imx8mp_defconfig   |  33 -
 include/configs/phycore_imx8mp.h   |   5 +
 5 files changed, 204 insertions(+), 4 deletions(-)
---
base-commit: 0101a2ffe125911ebf89172b495f5ff14f2fd058
change-id: 20240126-usb_support-403f47d71ac1

Best regards,
-- 
Benjamin Hahn 

[PATCH v2 4/4] phycore-imx8mp: add support for booting and flashing emmc via UUU

[Benjamin Hahn]

add support for Serial Downloader Boot via UUU as well as flashing emmc
via UUU on USB0 Port of phyBOARD Pollux.

Reviewed-by: Fabio Estevam 
Signed-off-by: Benjamin Hahn 
---
 board/phytec/phycore_imx8mp/phycore-imx8mp.c |  4 
 configs/phycore-imx8mp_defconfig | 18 --
 include/configs/phycore_imx8mp.h |  5 +
 3 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c 
b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
index a8f0821437..dbdd6bb793 100644
--- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
+++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
@@ -46,6 +46,10 @@ int board_late_init(void)
case MMC3_BOOT:
env_set_ulong("mmcdev", 2);
break;
+   case USB_BOOT:
+   printf("Detect USB boot. Will enter fastboot mode!\n");
+   env_set_ulong("dofastboot", 1);
+   break;
default:
break;
}
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index e3fe4ed94e..0f37286d5d 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -27,7 +27,7 @@ CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; 
then run mmcboot; else run netboot; fi; fi;"
+CONFIG_BOOTCOMMAND="if test ${dofastboot} = 1; then fastboot 0; fi; mmc dev 
${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run 
netboot; fi; fi;"
 CONFIG_DEFAULT_FDT_FILE="oftree"
 CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
@@ -66,6 +66,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
@@ -87,6 +88,17 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_IMX8MP=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x4280
+CONFIG_FASTBOOT_BUF_SIZE=0x1300
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc2boot0"
+CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc2boot1"
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_NAME="mmc2"
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
 # CONFIG_SPL_DM_I2C is not set
@@ -111,6 +123,9 @@ CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
 CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
 CONFIG_POWER_PCA9450=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
@@ -136,5 +151,4 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_IMX_WATCHDOG=y
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index d79d364c8e..11a17be7fe 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -19,6 +19,11 @@
"fdt_addr=0x4800\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"ip_dyn=yes\0" \
+   "dofastboot=0\0" \
+   "fastboot_raw_partition_bootloader=64 8128\0" \
+   "fastboot_raw_partition_all=0 4194304\0" \
+   "emmc_dev=2\0" \
+   "sd_dev=1\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=2\0" \

-- 
2.34.1

[PATCH v2 3/4] phycore-imx8mp: add USB mass storage support

[Benjamin Hahn]

add support for USB mass storage to USB0 port of phyBOARD Pollux.

tested with "ums 0 mmc 2"

Signed-off-by: Benjamin Hahn 
---
 arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 4 
 configs/phycore-imx8mp_defconfig| 7 +++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi 
b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
index 1c7b250549..b4efff27a7 100644
--- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
@@ -70,6 +70,10 @@
bootph-pre-ram;
 };
 
+&usb_dwc3_0 {
+   dr_mode = "peripheral";
+};
+
 &usdhc2 {
bootph-pre-ram;
 };
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 74450b957b..e3fe4ed94e 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -66,6 +66,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -123,6 +124,7 @@ CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
@@ -130,4 +132,9 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_IMX_WATCHDOG=y

-- 
2.34.1

[PATCH v2 2/4] phycore-imx8mp: add USB host support

[Benjamin Hahn]

The phyBOARD Pollux has two USB ports. Add support for USB host and USB
storage for the USB1 port.

Signed-off-by: Benjamin Hahn 
---
 configs/phycore-imx8mp_defconfig | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 519e0cfb3d..74450b957b 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -65,6 +65,7 @@ CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -104,6 +105,7 @@ CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
 CONFIG_RGMII=y
 CONFIG_MII=y
+CONFIG_PHY_IMX8MQ_USB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
@@ -120,4 +122,12 @@ CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
 CONFIG_IMX_WATCHDOG=y

-- 
2.34.1

[PATCH v2 0/4] phycore-imx8mp: Add USB support

[Benjamin Hahn]

add support for various USB features like USB storage, USB mass storage
as well as booting and flashing emmc via UUU.

Signed-off-by: Benjamin Hahn 
---
Changes in v2:
- sync kernel devicetree before making changes
- Link to v1: 
https://lore.kernel.org/r/20240129-usb_support-v1-0-8bd2fe840...@phytec.de

---
Benjamin Hahn (4):
  imx8mp-phyboard-pollux-rdk: sync with kernel devicetree from v6.8-rc2
  phycore-imx8mp: add USB host support
  phycore-imx8mp: add USB mass storage support
  phycore-imx8mp: add support for booting and flashing emmc via UUU

 .../arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi |   4 +
 arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts| 162 -
 board/phytec/phycore_imx8mp/phycore-imx8mp.c   |   4 +
 configs/phycore-imx8mp_defconfig   |  33 -
 include/configs/phycore_imx8mp.h   |   5 +
 5 files changed, 204 insertions(+), 4 deletions(-)
---
base-commit: e7f9e5eb584dd0b5d1b1ff82fe607d6da9940cc6
change-id: 20240126-usb_support-403f47d71ac1

Best regards,
-- 
Benjamin Hahn 

[PATCH v2 1/4] imx8mp-phyboard-pollux-rdk: sync with kernel devicetree from v6.8-rc2

[Benjamin Hahn]

Signed-off-by: Benjamin Hahn 
---
 arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 162 +++-
 1 file changed, 159 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts 
b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
index 6aa720bafe..c8640cac3e 100644
--- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
@@ -19,6 +19,36 @@
stdout-path = &uart1;
};
 
+   reg_can1_stby: regulator-can1-stby {
+   compatible = "regulator-fixed";
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_flexcan1_reg>;
+   gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
+   regulator-max-microvolt = <330>;
+   regulator-min-microvolt = <330>;
+   regulator-name = "can1-stby";
+   };
+
+   reg_can2_stby: regulator-can2-stby {
+   compatible = "regulator-fixed";
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_flexcan2_reg>;
+   gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
+   regulator-max-microvolt = <330>;
+   regulator-min-microvolt = <330>;
+   regulator-name = "can2-stby";
+   };
+
+   reg_usb1_vbus: regulator-usb1-vbus {
+   compatible = "regulator-fixed";
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_usb1_vbus>;
+   gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
+   regulator-max-microvolt = <500>;
+   regulator-min-microvolt = <500>;
+   regulator-name = "usb1_host_vbus";
+   };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -57,6 +87,21 @@
};
 };
 
+/* CAN FD */
+&flexcan1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_flexcan1>;
+   xceiver-supply = <®_can1_stby>;
+   status = "okay";
+};
+
+&flexcan2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_flexcan2>;
+   xceiver-supply = <®_can2_stby>;
+   status = "okay";
+};
+
 &i2c2 {
clock-frequency = <40>;
pinctrl-names = "default", "gpio";
@@ -76,15 +121,15 @@
compatible = "nxp,pca9533";
reg = <0x62>;
 
-   led1 {
+   led-1 {
type = ;
};
 
-   led2 {
+   led-2 {
type = ;
};
 
-   led3 {
+   led-3 {
type = ;
};
};
@@ -101,8 +146,51 @@
status = "okay";
 };
 
+/* USB1 Host mode Type-A */
+&usb3_phy0 {
+   vbus-supply = <®_usb1_vbus>;
+   status = "okay";
+};
+
+&usb3_0 {
+   status = "okay";
+};
+
+&usb_dwc3_0 {
+   dr_mode = "host";
+   status = "okay";
+};
+
+/* USB2 4-port USB3.0 HUB */
+&usb3_phy1 {
+   status = "okay";
+};
+
+&usb3_1 {
+   fsl,permanently-attached;
+   fsl,disable-port-power-control;
+   status = "okay";
+};
+
+&usb_dwc3_1 {
+   dr_mode = "host";
+   status = "okay";
+};
+
+/* RS232/RS485 */
+&uart2 {
+   assigned-clocks = <&clk IMX8MP_CLK_UART2>;
+   assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart2>;
+   uart-has-rtscts;
+   status = "okay";
+};
+
 /* SD-Card */
 &usdhc2 {
+   assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+   assigned-clock-rates = <2>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
@@ -113,6 +201,33 @@
status = "okay";
 };
 
+&gpio1 {
+   gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
+   "PMIC_SD_VSEL", "", "", "", "", "",
+   "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
+};
+
+&gpio2 {
+   gpio-line-names = "", "", "", "",
+   "", "", "

[PATCH 3/3] phycore-imx8mp: add support for booting and flashing emmc via UUU

[Benjamin Hahn]

add support for Serial Downloader Boot via UUU as well as flashing emmc
via UUU on USB0 Port of phyBOARD Pollux.

Signed-off-by: Benjamin Hahn 
---
 board/phytec/phycore_imx8mp/phycore-imx8mp.c |  4 
 configs/phycore-imx8mp_defconfig | 18 --
 include/configs/phycore_imx8mp.h |  5 +
 3 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c 
b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
index a8f0821437..dbdd6bb793 100644
--- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
+++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
@@ -46,6 +46,10 @@ int board_late_init(void)
case MMC3_BOOT:
env_set_ulong("mmcdev", 2);
break;
+   case USB_BOOT:
+   printf("Detect USB boot. Will enter fastboot mode!\n");
+   env_set_ulong("dofastboot", 1);
+   break;
default:
break;
}
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index e3fe4ed94e..0f37286d5d 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -27,7 +27,7 @@ CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; 
then run mmcboot; else run netboot; fi; fi;"
+CONFIG_BOOTCOMMAND="if test ${dofastboot} = 1; then fastboot 0; fi; mmc dev 
${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run 
netboot; fi; fi;"
 CONFIG_DEFAULT_FDT_FILE="oftree"
 CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
@@ -66,6 +66,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
@@ -87,6 +88,17 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_IMX8MP=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x4280
+CONFIG_FASTBOOT_BUF_SIZE=0x1300
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc2boot0"
+CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc2boot1"
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_NAME="mmc2"
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
 # CONFIG_SPL_DM_I2C is not set
@@ -111,6 +123,9 @@ CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
 CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
 CONFIG_POWER_PCA9450=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
@@ -136,5 +151,4 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_IMX_WATCHDOG=y
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index d79d364c8e..11a17be7fe 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -19,6 +19,11 @@
"fdt_addr=0x4800\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"ip_dyn=yes\0" \
+   "dofastboot=0\0" \
+   "fastboot_raw_partition_bootloader=64 8128\0" \
+   "fastboot_raw_partition_all=0 4194304\0" \
+   "emmc_dev=2\0" \
+   "sd_dev=1\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=2\0" \

-- 
2.34.1

[PATCH 2/3] phycore-imx8mp: add USB mass storage support

[Benjamin Hahn]

add support for USB mass storage to USB0 port of phyBOARD Pollux.

tested with "ums 0 mmc 2"

Signed-off-by: Benjamin Hahn 
---
 arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 13 +
 configs/phycore-imx8mp_defconfig|  7 +++
 2 files changed, 20 insertions(+)

diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi 
b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
index 5d6974f8fa..dcef4d4c2a 100644
--- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
@@ -70,15 +70,28 @@
bootph-pre-ram;
 };
 
+&usb3_0 {
+   status = "okay";
+   dr_mode = "peripheral";
+};
+
 &usb3_1 {
status = "okay";
dr_mode = "host";
 };
 
+&usb_dwc3_0 {
+   status = "okay";
+};
+
 &usb_dwc3_1 {
status = "okay";
 };
 
+&usb3_phy0 {
+   status = "okay";
+};
+
 &usb3_phy1 {
status = "okay";
 };
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 74450b957b..e3fe4ed94e 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -66,6 +66,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -123,6 +124,7 @@ CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
@@ -130,4 +132,9 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_IMX_WATCHDOG=y

-- 
2.34.1

[PATCH 1/3] phycore-imx8mp: add USB host support

[Benjamin Hahn]

The phyBOARD Pollux has two USB ports. Add support for USB host and USB
storage for the USB1 port.

Signed-off-by: Benjamin Hahn 
---
 arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 13 +
 configs/phycore-imx8mp_defconfig| 10 ++
 2 files changed, 23 insertions(+)

diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi 
b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
index 1c7b250549..5d6974f8fa 100644
--- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
@@ -70,6 +70,19 @@
bootph-pre-ram;
 };
 
+&usb3_1 {
+   status = "okay";
+   dr_mode = "host";
+};
+
+&usb_dwc3_1 {
+   status = "okay";
+};
+
+&usb3_phy1 {
+   status = "okay";
+};
+
 &usdhc2 {
bootph-pre-ram;
 };
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 519e0cfb3d..74450b957b 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -65,6 +65,7 @@ CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -104,6 +105,7 @@ CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
 CONFIG_RGMII=y
 CONFIG_MII=y
+CONFIG_PHY_IMX8MQ_USB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
@@ -120,4 +122,12 @@ CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
 CONFIG_IMX_WATCHDOG=y

-- 
2.34.1

[PATCH 0/3] phycore-imx8mp: Add USB support

[Benjamin Hahn]

add support for various USB features like USB storage, USB mass storage
as well as booting and flashing emmc via UUU.

Signed-off-by: Benjamin Hahn 
---
Benjamin Hahn (3):
  phycore-imx8mp: add USB host support
  phycore-imx8mp: add USB mass storage support
  phycore-imx8mp: add support for booting and flashing emmc via UUU

 .../arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 26 +
 board/phytec/phycore_imx8mp/phycore-imx8mp.c   |  4 +++
 configs/phycore-imx8mp_defconfig   | 33 +-
 include/configs/phycore_imx8mp.h   |  5 
 4 files changed, 67 insertions(+), 1 deletion(-)
---
base-commit: e7f9e5eb584dd0b5d1b1ff82fe607d6da9940cc6
change-id: 20240126-usb_support-403f47d71ac1

Best regards,
-- 
Benjamin Hahn